1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999-2017 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com) and
5 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 3, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
24 ;; See constraints.md for a description of constraints specific to s390.
27 ;; Special formats used for outputting 390 instructions.
29 ;; %C: print opcode suffix for branch condition.
30 ;; %D: print opcode suffix for inverse branch condition.
31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
32 ;; %G: print the size of the operand in bytes.
33 ;; %O: print only the displacement of a memory reference.
34 ;; %R: print only the base register of a memory reference.
35 ;; %S: print S-type memory reference (base+displacement).
36 ;; %N: print the second word of a DImode operand.
37 ;; %M: print the second word of a TImode operand.
38 ;; %Y: print shift count operand.
40 ;; %b: print integer X as if it's an unsigned byte.
41 ;; %c: print integer X as if it's an signed byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
59 (define_c_enum "unspec" [
65 ; Convert CC into a str comparison result and copy it into an
67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1)
68 UNSPEC_STRCMPCC_TO_INT
70 ; Copy CC as is into the lower 2 bits of an integer register
73 ; The right hand side of an setmem
76 ; GOT/PLT and lt-relative accesses
97 ; TLS relocation specifiers
113 ; Stack Smashing Protector
117 ; Split stack support
120 ; Test Data Class (TDC)
132 UNSPEC_FPINT_NEARBYINT
141 UNSPEC_VEC_SMULT_EVEN
142 UNSPEC_VEC_UMULT_EVEN
156 UNSPEC_VEC_INSERT_AND_ZERO
157 UNSPEC_VEC_LOAD_BNDRY
159 UNSPEC_VEC_LOAD_LEN_R
163 UNSPEC_VEC_PACK_SATURATE
164 UNSPEC_VEC_PACK_SATURATE_CC
165 UNSPEC_VEC_PACK_SATURATE_GENCC
166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE
167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
168 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
173 UNSPEC_VEC_STORE_LEN_R
181 UNSPEC_VEC_ADDEC_U128
186 UNSPEC_VEC_GFMSUM_128
187 UNSPEC_VEC_GFMSUM_ACCUM
188 UNSPEC_VEC_GFMSUM_ACCUM_128
205 UNSPEC_VEC_SUBEC_U128
231 UNSPEC_VEC_VFLL ; vector fp load lengthened
232 UNSPEC_VEC_VFLR ; vector fp load rounded
244 ;; UNSPEC_VOLATILE usage
247 (define_c_enum "unspecv" [
269 ; Hotpatching (unremovable NOPs)
274 ; Transactional Execution support
284 ; Set and get floating point control register
288 ; Split stack support
289 UNSPECV_SPLIT_STACK_CALL
290 UNSPECV_SPLIT_STACK_DATA
299 ; Registers with special meaning
303 ; Sibling call register.
305 ; Literal pool base register.
307 ; Return address register.
309 ; Stack pointer register.
311 ; Condition code register.
313 ; Thread local storage pointer register.
317 ; Hardware register names
321 ; General purpose registers
326 ; Floating point registers.
350 ; Rounding modes for binary floating point numbers
353 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
354 (BFP_RND_PREP_FOR_SHORT_PREC 3)
355 (BFP_RND_NEAREST_TIE_TO_EVEN 4)
357 (BFP_RND_TOWARD_INF 6)
358 (BFP_RND_TOWARD_MINF 7)])
360 ; Rounding modes for decimal floating point numbers
361 ; 1-7 were introduced with the floating point extension facility
362 ; available with z196
363 ; With these rounding modes (1-7) a quantum exception might occur
364 ; which is suppressed for the other modes.
367 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
368 (DFP_RND_CURRENT_QUANTEXC 2)
369 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
370 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
371 (DFP_RND_TOWARD_0_QUANTEXC 5)
372 (DFP_RND_TOWARD_INF_QUANTEXC 6)
373 (DFP_RND_TOWARD_MINF_QUANTEXC 7)
374 (DFP_RND_NEAREST_TIE_TO_EVEN 8)
376 (DFP_RND_TOWARD_INF 10)
377 (DFP_RND_TOWARD_MINF 11)
378 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
379 (DFP_RND_NEAREST_TIE_TO_0 13)
380 (DFP_RND_AWAY_FROM_0 14)
381 (DFP_RND_PREP_FOR_SHORT_PREC 15)])
384 ;; PFPO GPR0 argument format
389 ; PFPO operation type
390 (PFPO_CONVERT 0x1000000)
392 (PFPO_OP_TYPE_SF 0x5)
393 (PFPO_OP_TYPE_DF 0x6)
394 (PFPO_OP_TYPE_TF 0x7)
395 (PFPO_OP_TYPE_SD 0x8)
396 (PFPO_OP_TYPE_DD 0x9)
397 (PFPO_OP_TYPE_TD 0xa)
398 ; Bitposition of operand types
399 (PFPO_OP0_TYPE_SHIFT 16)
400 (PFPO_OP1_TYPE_SHIFT 8)
403 ; Immediate operands for tbegin and tbeginc
404 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
405 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
407 ;; Instruction operand type as used in the Principles of Operation.
408 ;; Used to determine defaults for length and other attribute values.
410 (define_attr "op_type"
411 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI"
414 ;; Instruction type attribute used for scheduling.
416 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
417 cs,vs,store,sem,idiv,
418 imulhi,imulsi,imuldi,
419 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex,
420 floadtf,floaddf,floadsf,fstoredf,fstoresf,
421 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
422 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
424 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
425 itoftf, itofdf, itofsf, itofdd, itoftd,
426 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
427 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
429 (cond [(eq_attr "op_type" "NN") (const_string "other")
430 (eq_attr "op_type" "SS") (const_string "cs")]
431 (const_string "integer")))
433 ;; Another attribute used for scheduling purposes:
434 ;; agen: Instruction uses the address generation unit
435 ;; reg: Instruction does not use the agen unit
437 (define_attr "atype" "agen,reg"
438 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
440 (const_string "agen")))
442 ;; Properties concerning Z10 execution grouping and value forwarding.
443 ;; z10_super: instruction is superscalar.
444 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
445 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
446 ;; target register. It can forward this value to a second instruction that reads
447 ;; the same register if that second instruction is issued in the same group.
448 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
449 ;; instruction in the S pipe writes to the register, then the T instruction
450 ;; can immediately read the new value.
451 ;; z10_fr: union of Z10_fwd and z10_rec.
452 ;; z10_c: second operand of instruction is a register and read with complemented bits.
454 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
457 (define_attr "z10prop" "none,
458 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
459 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
461 z10_fr, z10_fr_A3, z10_fr_E1,
463 (const_string "none"))
465 ;; Properties concerning Z196 decoding
466 ;; z196_alone: must group alone
467 ;; z196_end: ends a group
468 ;; z196_cracked: instruction is cracked or expanded
469 (define_attr "z196prop" "none,
470 z196_alone, z196_ends,
472 (const_string "none"))
474 (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
478 (define_attr "length" ""
479 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
480 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
484 ;; Processor type. This attribute must exactly match the processor_type
485 ;; enumeration in s390.h. The current machine description does not
486 ;; distinguish between g5 and g6, but there are differences between the two
487 ;; CPUs could in theory be modeled.
489 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12"
490 (const (symbol_ref "s390_tune_attr")))
492 (define_attr "cpu_facility"
493 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe"
494 (const_string "standard"))
496 (define_attr "enabled" ""
497 (cond [(eq_attr "cpu_facility" "standard")
500 (and (eq_attr "cpu_facility" "ieee")
501 (match_test "TARGET_CPU_IEEE_FLOAT"))
504 (and (eq_attr "cpu_facility" "zarch")
505 (match_test "TARGET_ZARCH"))
508 (and (eq_attr "cpu_facility" "longdisp")
509 (match_test "TARGET_LONG_DISPLACEMENT"))
512 (and (eq_attr "cpu_facility" "extimm")
513 (match_test "TARGET_EXTIMM"))
516 (and (eq_attr "cpu_facility" "dfp")
517 (match_test "TARGET_DFP"))
520 (and (eq_attr "cpu_facility" "cpu_zarch")
521 (match_test "TARGET_CPU_ZARCH"))
524 (and (eq_attr "cpu_facility" "z10")
525 (match_test "TARGET_Z10"))
528 (and (eq_attr "cpu_facility" "z196")
529 (match_test "TARGET_Z196"))
532 (and (eq_attr "cpu_facility" "zEC12")
533 (match_test "TARGET_ZEC12"))
536 (and (eq_attr "cpu_facility" "vx")
537 (match_test "TARGET_VX"))
540 (and (eq_attr "cpu_facility" "z13")
541 (match_test "TARGET_Z13"))
544 (and (eq_attr "cpu_facility" "arch12")
545 (match_test "TARGET_ARCH12"))
548 (and (eq_attr "cpu_facility" "vxe")
549 (match_test "TARGET_VXE"))
554 ;; Pipeline description for z900. For lack of anything better,
555 ;; this description is also used for the g5 and g6.
558 ;; Pipeline description for z990, z9-109 and z9-ec.
561 ;; Pipeline description for z10
564 ;; Pipeline description for z196
567 ;; Pipeline description for zEC12
570 ;; Pipeline description for z13
574 (include "predicates.md")
576 ;; Constraint definitions
577 (include "constraints.md")
584 (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
586 ;; These mode iterators allow floating point patterns to be generated from the
588 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
589 (SD "TARGET_HARD_DFP")])
590 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
591 (define_mode_iterator BFP [TF DF SF])
592 (define_mode_iterator DFP [TD DD])
593 (define_mode_iterator DFP_ALL [TD DD SD])
594 (define_mode_iterator DSF [DF SF])
595 (define_mode_iterator SD_SF [SF SD])
596 (define_mode_iterator DD_DF [DF DD])
597 (define_mode_iterator TD_TF [TF TD])
599 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
600 ;; from the same template.
601 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
602 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI])
603 (define_mode_iterator DSI [DI SI])
604 (define_mode_iterator TDI [TI DI])
606 ;; These mode iterators allow :P to be used for patterns that operate on
607 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
608 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
610 ;; These macros refer to the actual word_mode of the configuration.
611 ;; This is equal to Pmode except on 31-bit machines in zarch mode.
612 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
613 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
615 ;; Used by the umul pattern to express modes having half the size.
616 (define_mode_attr DWH [(TI "DI") (DI "SI")])
617 (define_mode_attr dwh [(TI "di") (DI "si")])
619 ;; This mode iterator allows the QI and HI patterns to be defined from
620 ;; the same template.
621 (define_mode_iterator HQI [HI QI])
623 ;; This mode iterator allows the integer patterns to be defined from the
625 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
626 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
627 (define_mode_iterator SINT [SI HI QI])
629 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
630 ;; the same template.
631 (define_code_iterator SHIFT [ashift lshiftrt])
633 ;; This iterator allows r[ox]sbg to be defined with the same template
634 (define_code_iterator IXOR [ior xor])
636 ;; This iterator is used to expand the patterns for the nearest
637 ;; integer functions.
638 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
639 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL
640 UNSPEC_FPINT_NEARBYINT])
641 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor")
642 (UNSPEC_FPINT_BTRUNC "btrunc")
643 (UNSPEC_FPINT_ROUND "round")
644 (UNSPEC_FPINT_CEIL "ceil")
645 (UNSPEC_FPINT_NEARBYINT "nearbyint")])
646 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7")
647 (UNSPEC_FPINT_BTRUNC "5")
648 (UNSPEC_FPINT_ROUND "1")
649 (UNSPEC_FPINT_CEIL "6")
650 (UNSPEC_FPINT_NEARBYINT "0")])
652 ;; This iterator and attribute allow to combine most atomic operations.
653 (define_code_iterator ATOMIC [and ior xor plus minus mult])
654 (define_code_iterator ATOMIC_Z196 [and ior xor plus])
655 (define_code_attr atomic [(and "and") (ior "or") (xor "xor")
656 (plus "add") (minus "sub") (mult "nand")])
657 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
659 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
660 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
661 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
663 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
664 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
666 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
668 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
669 ;; Likewise for "<RXe>".
670 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
671 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
673 ;; The decimal floating point variants of add, sub, div and mul support 3
674 ;; fp register operands. The following attributes allow to merge the bfp and
675 ;; dfp variants in a single insn definition.
677 ;; These mode attributes are supposed to be used in the `enabled' insn
678 ;; attribute to disable certain alternatives for certain modes.
679 (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
680 (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
681 (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
682 (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
683 (TD "0") (DD "0") (DD "0")
684 (TI "0") (DI "*") (SI "0")])
685 (define_mode_attr DF [(TF "0") (DF "*") (SF "0")
686 (TD "0") (DD "0") (DD "0")
687 (TI "0") (DI "0") (SI "0")])
688 (define_mode_attr SF [(TF "0") (DF "0") (SF "*")
689 (TD "0") (DD "0") (DD "0")
690 (TI "0") (DI "0") (SI "0")])
692 ;; This attribute is used in the operand constraint list
693 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
694 ;; TFmode values are represented by a fp register pair. Since the
695 ;; sign bit instructions only handle single source and target fp registers
696 ;; these instructions can only be used for TFmode values if the source and
697 ;; target operand uses the same fp register.
698 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
700 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
701 ;; within instruction mnemonics.
702 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
704 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
705 ;; modes and to an empty string for bfp modes.
706 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
708 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
709 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
710 ;; version only operates on one register.
711 (define_mode_attr d0 [(DI "d") (SI "0")])
713 ;; In combination with d0 this allows to combine instructions of which the 31bit
714 ;; version only operates on one register. The DImode version needs an additional
715 ;; register for the assembler output.
716 (define_mode_attr 1 [(DI "%1,") (SI "")])
718 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
719 ;; 'ashift' and "srdl" in 'lshiftrt'.
720 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
722 ;; In SHIFT templates, this attribute holds the correct standard name for the
723 ;; pattern itself and the corresponding function calls.
724 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
726 ;; This attribute handles differences in the instruction 'type' and will result
727 ;; in "RRE" for DImode and "RR" for SImode.
728 (define_mode_attr E [(DI "E") (SI "")])
730 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
731 ;; to result in "RXY" for DImode and "RX" for SImode.
732 (define_mode_attr Y [(DI "Y") (SI "")])
734 ;; This attribute handles differences in the instruction 'type' and will result
735 ;; in "RSE" for TImode and "RS" for DImode.
736 (define_mode_attr TE [(TI "E") (DI "")])
738 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
739 ;; and "lcr" in SImode.
740 (define_mode_attr g [(DI "g") (SI "")])
742 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
743 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
744 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
745 ;; variant for long displacements.
746 (define_mode_attr y [(DI "g") (SI "y")])
748 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
749 ;; and "cds" in DImode.
750 (define_mode_attr tg [(TI "g") (DI "")])
752 ;; In TDI templates, a string like "c<d>sg".
753 (define_mode_attr td [(TI "d") (DI "")])
755 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
756 ;; and "cfdbr" in SImode.
757 (define_mode_attr gf [(DI "g") (SI "f")])
759 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
760 ;; and sllk for SI. This way it is possible to merge the new z196 SI
761 ;; 3 operands shift instructions into the existing patterns.
762 (define_mode_attr gk [(DI "g") (SI "k")])
764 ;; ICM mask required to load MODE value into the lowest subreg
765 ;; of a SImode register.
766 (define_mode_attr icm_lo [(HI "3") (QI "1")])
768 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
769 ;; HImode and "llgc" in QImode.
770 (define_mode_attr hc [(HI "h") (QI "c")])
772 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
774 (define_mode_attr DBL [(DI "TI") (SI "DI")])
776 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
777 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
778 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
780 ;; Maximum unsigned integer that fits in MODE.
781 (define_mode_attr max_uint [(HI "65535") (QI "255")])
783 ;; Start and end field computations for RISBG et al.
784 (define_mode_attr bfstart [(DI "s") (SI "t")])
785 (define_mode_attr bfend [(DI "e") (SI "f")])
787 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
788 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
790 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
791 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
793 ;; In place of GET_MODE_SIZE (<MODE>mode)
794 (define_mode_attr modesize [(DI "8") (SI "4")])
796 ;; Allow return and simple_return to be defined from a single template.
797 (define_code_iterator ANY_RETURN [return simple_return])
801 ; Condition code modes generated by vector fp comparisons. These will
802 ; be used also in single element mode.
803 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
804 ; Used with VFCMP to expand part of the mnemonic
805 ; For fp we have a mismatch: eq in the insn name - e in asm
806 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
807 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
809 ;; Subst pattern definitions
812 (include "vector.md")
815 ;;- Compare instructions.
818 ; Test-under-Mask instructions
820 (define_insn "*tmqi_mem"
821 [(set (reg CC_REGNUM)
822 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
823 (match_operand:QI 1 "immediate_operand" "n,n"))
824 (match_operand:QI 2 "immediate_operand" "n,n")))]
825 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
829 [(set_attr "op_type" "SI,SIY")
830 (set_attr "cpu_facility" "*,longdisp")
831 (set_attr "z10prop" "z10_super,z10_super")])
833 (define_insn "*tmdi_reg"
834 [(set (reg CC_REGNUM)
835 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
836 (match_operand:DI 1 "immediate_operand"
837 "N0HD0,N1HD0,N2HD0,N3HD0"))
838 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
840 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
841 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
847 [(set_attr "op_type" "RI")
848 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
850 (define_insn "*tmsi_reg"
851 [(set (reg CC_REGNUM)
852 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
853 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
854 (match_operand:SI 2 "immediate_operand" "n,n")))]
855 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
856 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
860 [(set_attr "op_type" "RI")
861 (set_attr "z10prop" "z10_super,z10_super")])
863 (define_insn "*tm<mode>_full"
864 [(set (reg CC_REGNUM)
865 (compare (match_operand:HQI 0 "register_operand" "d")
866 (match_operand:HQI 1 "immediate_operand" "n")))]
867 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
869 [(set_attr "op_type" "RI")
870 (set_attr "z10prop" "z10_super")])
874 ; Load-and-Test instructions
877 ; tst(di|si) instruction pattern(s).
879 (define_insn "*tstdi_sign"
880 [(set (reg CC_REGNUM)
884 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
885 (const_int 32)) (const_int 32))
886 (match_operand:DI 1 "const0_operand" "")))
887 (set (match_operand:DI 2 "register_operand" "=d,d")
888 (sign_extend:DI (match_dup 0)))]
889 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
892 [(set_attr "op_type" "RRE,RXY")
893 (set_attr "cpu_facility" "*,z10")
894 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
897 (define_insn "*tst<mode>_extimm"
898 [(set (reg CC_REGNUM)
899 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
900 (match_operand:GPR 1 "const0_operand" "")))
901 (set (match_operand:GPR 2 "register_operand" "=d,d")
903 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
907 [(set_attr "op_type" "RR<E>,RXY")
908 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
910 ; Peephole to combine a load-and-test from volatile memory which combine does
913 [(set (match_operand:GPR 0 "register_operand")
914 (match_operand:GPR 2 "memory_operand"))
916 (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))]
917 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM
918 && GENERAL_REG_P (operands[0])
919 && satisfies_constraint_T (operands[2])"
921 [(set (reg:CCS CC_REGNUM)
922 (compare:CCS (match_dup 2) (match_dup 1)))
923 (set (match_dup 0) (match_dup 2))])])
926 (define_insn "*tst<mode>_cconly_extimm"
927 [(set (reg CC_REGNUM)
928 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
929 (match_operand:GPR 1 "const0_operand" "")))
930 (clobber (match_scratch:GPR 2 "=X,d"))]
931 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
935 [(set_attr "op_type" "RR<E>,RXY")
936 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
938 (define_insn "*tstdi"
939 [(set (reg CC_REGNUM)
940 (compare (match_operand:DI 0 "register_operand" "d")
941 (match_operand:DI 1 "const0_operand" "")))
942 (set (match_operand:DI 2 "register_operand" "=d")
944 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
946 [(set_attr "op_type" "RRE")
947 (set_attr "z10prop" "z10_fr_E1")])
949 (define_insn "*tstsi"
950 [(set (reg CC_REGNUM)
951 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
952 (match_operand:SI 1 "const0_operand" "")))
953 (set (match_operand:SI 2 "register_operand" "=d,d,d")
955 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
960 [(set_attr "op_type" "RR,RS,RSY")
961 (set_attr "cpu_facility" "*,*,longdisp")
962 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
964 (define_insn "*tstsi_cconly"
965 [(set (reg CC_REGNUM)
966 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
967 (match_operand:SI 1 "const0_operand" "")))
968 (clobber (match_scratch:SI 2 "=X,d,d"))]
969 "s390_match_ccmode(insn, CCSmode)"
974 [(set_attr "op_type" "RR,RS,RSY")
975 (set_attr "cpu_facility" "*,*,longdisp")
976 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
978 (define_insn "*tstdi_cconly_31"
979 [(set (reg CC_REGNUM)
980 (compare (match_operand:DI 0 "register_operand" "d")
981 (match_operand:DI 1 "const0_operand" "")))]
982 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
984 [(set_attr "op_type" "RS")
985 (set_attr "atype" "reg")])
988 (define_insn "*tst<mode>_cconly2"
989 [(set (reg CC_REGNUM)
990 (compare (match_operand:GPR 0 "register_operand" "d")
991 (match_operand:GPR 1 "const0_operand" "")))]
992 "s390_match_ccmode(insn, CCSmode)"
994 [(set_attr "op_type" "RR<E>")
995 (set_attr "z10prop" "z10_fr_E1")])
997 ; tst(hi|qi) instruction pattern(s).
999 (define_insn "*tst<mode>CCT"
1000 [(set (reg CC_REGNUM)
1001 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
1002 (match_operand:HQI 1 "const0_operand" "")))
1003 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
1005 "s390_match_ccmode(insn, CCTmode)"
1007 icm\t%2,<icm_lo>,%S0
1008 icmy\t%2,<icm_lo>,%S0
1010 [(set_attr "op_type" "RS,RSY,RI")
1011 (set_attr "cpu_facility" "*,longdisp,*")
1012 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
1014 (define_insn "*tsthiCCT_cconly"
1015 [(set (reg CC_REGNUM)
1016 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
1017 (match_operand:HI 1 "const0_operand" "")))
1018 (clobber (match_scratch:HI 2 "=d,d,X"))]
1019 "s390_match_ccmode(insn, CCTmode)"
1024 [(set_attr "op_type" "RS,RSY,RI")
1025 (set_attr "cpu_facility" "*,longdisp,*")
1026 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
1028 (define_insn "*tstqiCCT_cconly"
1029 [(set (reg CC_REGNUM)
1030 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
1031 (match_operand:QI 1 "const0_operand" "")))]
1032 "s390_match_ccmode(insn, CCTmode)"
1037 [(set_attr "op_type" "SI,SIY,RI")
1038 (set_attr "cpu_facility" "*,longdisp,*")
1039 (set_attr "z10prop" "z10_super,z10_super,z10_super")])
1041 (define_insn "*tst<mode>"
1042 [(set (reg CC_REGNUM)
1043 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1044 (match_operand:HQI 1 "const0_operand" "")))
1045 (set (match_operand:HQI 2 "register_operand" "=d,d")
1047 "s390_match_ccmode(insn, CCSmode)"
1049 icm\t%2,<icm_lo>,%S0
1050 icmy\t%2,<icm_lo>,%S0"
1051 [(set_attr "op_type" "RS,RSY")
1052 (set_attr "cpu_facility" "*,longdisp")
1053 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1055 (define_insn "*tst<mode>_cconly"
1056 [(set (reg CC_REGNUM)
1057 (compare (match_operand:HQI 0 "s_operand" "Q,S")
1058 (match_operand:HQI 1 "const0_operand" "")))
1059 (clobber (match_scratch:HQI 2 "=d,d"))]
1060 "s390_match_ccmode(insn, CCSmode)"
1062 icm\t%2,<icm_lo>,%S0
1063 icmy\t%2,<icm_lo>,%S0"
1064 [(set_attr "op_type" "RS,RSY")
1065 (set_attr "cpu_facility" "*,longdisp")
1066 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1069 ; Compare (equality) instructions
1071 (define_insn "*cmpdi_cct"
1072 [(set (reg CC_REGNUM)
1073 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
1074 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
1075 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
1082 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
1083 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
1085 (define_insn "*cmpsi_cct"
1086 [(set (reg CC_REGNUM)
1087 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
1088 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
1089 "s390_match_ccmode (insn, CCTmode)"
1097 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
1098 (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
1099 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
1101 ; Compare (signed) instructions
1103 (define_insn "*cmpdi_ccs_sign"
1104 [(set (reg CC_REGNUM)
1105 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1107 (match_operand:DI 0 "register_operand" "d, d,d")))]
1108 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
1113 [(set_attr "op_type" "RRE,RXY,RIL")
1114 (set_attr "z10prop" "z10_c,*,*")
1115 (set_attr "type" "*,*,larl")])
1119 (define_insn "*cmpsi_ccs_sign"
1120 [(set (reg CC_REGNUM)
1121 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
1122 (match_operand:SI 0 "register_operand" "d,d,d")))]
1123 "s390_match_ccmode(insn, CCSRmode)"
1128 [(set_attr "op_type" "RX,RXY,RIL")
1129 (set_attr "cpu_facility" "*,longdisp,z10")
1130 (set_attr "type" "*,*,larl")
1131 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
1133 (define_insn "*cmphi_ccs_z10"
1134 [(set (reg CC_REGNUM)
1135 (compare (match_operand:HI 0 "s_operand" "Q")
1136 (match_operand:HI 1 "immediate_operand" "K")))]
1137 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
1139 [(set_attr "op_type" "SIL")
1140 (set_attr "z196prop" "z196_cracked")])
1142 (define_insn "*cmpdi_ccs_signhi_rl"
1143 [(set (reg CC_REGNUM)
1144 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
1145 (match_operand:GPR 0 "register_operand" "d,d")))]
1146 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
1150 [(set_attr "op_type" "RXY,RIL")
1151 (set_attr "type" "*,larl")])
1153 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
1154 (define_insn "*cmp<mode>_ccs"
1155 [(set (reg CC_REGNUM)
1156 (compare (match_operand:GPR 0 "nonimmediate_operand"
1158 (match_operand:GPR 1 "general_operand"
1159 "d,K,K,Os,R,T,b")))]
1160 "s390_match_ccmode(insn, CCSmode)"
1169 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
1170 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
1171 (set_attr "type" "*,*,*,*,*,*,larl")
1172 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
1175 ; Compare (unsigned) instructions
1177 (define_insn "*cmpsi_ccu_zerohi_rlsi"
1178 [(set (reg CC_REGNUM)
1179 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
1180 "larl_operand" "X")))
1181 (match_operand:SI 0 "register_operand" "d")))]
1182 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1184 [(set_attr "op_type" "RIL")
1185 (set_attr "type" "larl")
1186 (set_attr "z10prop" "z10_super")])
1189 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
1190 [(set (reg CC_REGNUM)
1191 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
1192 "larl_operand" "X")))
1193 (match_operand:GPR 0 "register_operand" "d")))]
1194 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
1196 [(set_attr "op_type" "RIL")
1197 (set_attr "type" "larl")
1198 (set_attr "z10prop" "z10_super")])
1200 (define_insn "*cmpdi_ccu_zero"
1201 [(set (reg CC_REGNUM)
1202 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
1204 (match_operand:DI 0 "register_operand" "d,d,d")))]
1205 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
1210 [(set_attr "op_type" "RRE,RXY,RIL")
1211 (set_attr "cpu_facility" "*,*,z10")
1212 (set_attr "type" "*,*,larl")
1213 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
1215 (define_insn "*cmpdi_ccu"
1216 [(set (reg CC_REGNUM)
1217 (compare (match_operand:DI 0 "nonimmediate_operand"
1219 (match_operand:DI 1 "general_operand"
1220 "d,Op,b,D,T,BQ,Q")))]
1221 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
1230 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
1231 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
1232 (set_attr "type" "*,*,larl,*,*,*,*")
1233 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
1235 (define_insn "*cmpsi_ccu"
1236 [(set (reg CC_REGNUM)
1237 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
1238 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
1239 "s390_match_ccmode (insn, CCUmode)"
1249 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
1250 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
1251 (set_attr "type" "*,*,larl,*,*,*,*,*")
1252 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
1254 (define_insn "*cmphi_ccu"
1255 [(set (reg CC_REGNUM)
1256 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
1257 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
1258 "s390_match_ccmode (insn, CCUmode)
1259 && !register_operand (operands[1], HImode)"
1266 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
1267 (set_attr "cpu_facility" "*,longdisp,z10,*,*")
1268 (set_attr "z10prop" "*,*,z10_super,*,*")])
1270 (define_insn "*cmpqi_ccu"
1271 [(set (reg CC_REGNUM)
1272 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
1273 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
1274 "s390_match_ccmode (insn, CCUmode)
1275 && !register_operand (operands[1], QImode)"
1283 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
1284 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
1285 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
1288 ; Block compare (CLC) instruction patterns.
1291 [(set (reg CC_REGNUM)
1292 (compare (match_operand:BLK 0 "memory_operand" "Q")
1293 (match_operand:BLK 1 "memory_operand" "Q")))
1294 (use (match_operand 2 "const_int_operand" "n"))]
1295 "s390_match_ccmode (insn, CCUmode)
1296 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1297 "clc\t%O0(%2,%R0),%S1"
1298 [(set_attr "op_type" "SS")])
1301 [(set (reg CC_REGNUM)
1302 (compare (match_operand 0 "memory_operand" "")
1303 (match_operand 1 "memory_operand" "")))]
1305 && s390_match_ccmode (insn, CCUmode)
1306 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1307 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1309 [(set (match_dup 0) (match_dup 1))
1310 (use (match_dup 2))])]
1312 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1313 operands[0] = adjust_address (operands[0], BLKmode, 0);
1314 operands[1] = adjust_address (operands[1], BLKmode, 0);
1316 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
1317 operands[0], operands[1]);
1318 operands[0] = SET_DEST (PATTERN (curr_insn));
1322 ; (TF|DF|SF|TD|DD|SD) instructions
1325 ; load and test instructions turn SNaN into QNaN what is not
1326 ; acceptable if the target will be used afterwards. On the other hand
1327 ; they are quite convenient for implementing comparisons with 0.0. So
1328 ; try to enable them via splitter if the value isn't needed anymore.
1330 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
1331 (define_insn "*cmp<mode>_ccs_0"
1332 [(set (reg CC_REGNUM)
1333 (compare (match_operand:FP 0 "register_operand" "f")
1334 (match_operand:FP 1 "const0_operand" "")))
1335 (clobber (match_operand:FP 2 "register_operand" "=0"))]
1336 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1337 "lt<xde><bt>r\t%0,%0"
1338 [(set_attr "op_type" "RRE")
1339 (set_attr "type" "fsimp<mode>")])
1342 [(set (match_operand 0 "cc_reg_operand")
1343 (compare (match_operand:FP 1 "register_operand")
1344 (match_operand:FP 2 "const0_operand")))]
1345 "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])"
1347 [(set (match_dup 0) (match_dup 3))
1348 (clobber (match_dup 1))])]
1350 /* s390_match_ccmode requires the compare to have the same CC mode
1351 as the CC destination register. */
1352 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]),
1353 operands[1], operands[2]);
1357 ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb
1358 ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb
1359 (define_insn "*cmp<mode>_ccs"
1360 [(set (reg CC_REGNUM)
1361 (compare (match_operand:FP 0 "register_operand" "f,f,v,v")
1362 (match_operand:FP 1 "general_operand" "f,R,v,v")))]
1363 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1369 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
1370 (set_attr "cpu_facility" "*,*,vx,vxe")
1371 (set_attr "enabled" "*,<DSF>,<DF>,<SF>")])
1373 ; Compare and Branch instructions
1375 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1376 ; The following instructions do a complementary access of their second
1377 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1378 (define_insn "*cmp_and_br_signed_<mode>"
1380 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1381 [(match_operand:GPR 1 "register_operand" "d,d")
1382 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1383 (label_ref (match_operand 3 "" ""))
1385 (clobber (reg:CC CC_REGNUM))]
1386 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1388 if (get_attr_length (insn) == 6)
1389 return which_alternative ?
1390 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1392 return which_alternative ?
1393 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1395 [(set_attr "op_type" "RIE")
1396 (set_attr "type" "branch")
1397 (set_attr "z10prop" "z10_super_c,z10_super")
1398 (set (attr "length")
1399 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1400 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1401 ; 10 byte for cgr/jg
1403 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1404 ; The following instructions do a complementary access of their second
1405 ; operand (z10 only): clrj, clgrj, clr, clgr
1406 (define_insn "*cmp_and_br_unsigned_<mode>"
1408 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1409 [(match_operand:GPR 1 "register_operand" "d,d")
1410 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1411 (label_ref (match_operand 3 "" ""))
1413 (clobber (reg:CC CC_REGNUM))]
1414 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1416 if (get_attr_length (insn) == 6)
1417 return which_alternative ?
1418 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1420 return which_alternative ?
1421 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1423 [(set_attr "op_type" "RIE")
1424 (set_attr "type" "branch")
1425 (set_attr "z10prop" "z10_super_c,z10_super")
1426 (set (attr "length")
1427 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1428 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1429 ; 10 byte for clgr/jg
1431 ; And now the same two patterns as above but with a negated CC mask.
1433 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1434 ; The following instructions do a complementary access of their second
1435 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1436 (define_insn "*icmp_and_br_signed_<mode>"
1438 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1439 [(match_operand:GPR 1 "register_operand" "d,d")
1440 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1442 (label_ref (match_operand 3 "" ""))))
1443 (clobber (reg:CC CC_REGNUM))]
1444 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1446 if (get_attr_length (insn) == 6)
1447 return which_alternative ?
1448 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
1450 return which_alternative ?
1451 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
1453 [(set_attr "op_type" "RIE")
1454 (set_attr "type" "branch")
1455 (set_attr "z10prop" "z10_super_c,z10_super")
1456 (set (attr "length")
1457 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1458 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1459 ; 10 byte for cgr/jg
1461 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1462 ; The following instructions do a complementary access of their second
1463 ; operand (z10 only): clrj, clgrj, clr, clgr
1464 (define_insn "*icmp_and_br_unsigned_<mode>"
1466 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1467 [(match_operand:GPR 1 "register_operand" "d,d")
1468 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1470 (label_ref (match_operand 3 "" ""))))
1471 (clobber (reg:CC CC_REGNUM))]
1472 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
1474 if (get_attr_length (insn) == 6)
1475 return which_alternative ?
1476 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
1478 return which_alternative ?
1479 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
1481 [(set_attr "op_type" "RIE")
1482 (set_attr "type" "branch")
1483 (set_attr "z10prop" "z10_super_c,z10_super")
1484 (set (attr "length")
1485 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1486 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1487 ; 10 byte for clgr/jg
1490 ;;- Move instructions.
1494 ; movti instruction pattern(s).
1498 ; Separate out the register pair alternative since constraints (P) are
1499 ; not able to deal with const_wide_int's. But predicates do.
1500 (define_insn "*movti_bigconst"
1501 [(set (match_operand:TI 0 "register_operand" "=d")
1502 (match_operand:TI 1 "reload_const_wide_int_operand" ""))]
1506 ; FIXME: More constants are possible by enabling jxx, jyy constraints
1507 ; for TImode (use double-int for the calculations)
1508 (define_insn "movti"
1509 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
1510 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dT,d"))]
1524 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
1525 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
1526 (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")])
1529 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1530 (match_operand:TI 1 "general_operand" ""))]
1531 "TARGET_ZARCH && reload_completed
1532 && !s_operand (operands[0], TImode)
1533 && !s_operand (operands[1], TImode)
1534 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1535 [(set (match_dup 2) (match_dup 4))
1536 (set (match_dup 3) (match_dup 5))]
1538 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1539 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1540 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1541 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1545 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1546 (match_operand:TI 1 "general_operand" ""))]
1547 "TARGET_ZARCH && reload_completed
1548 && !s_operand (operands[0], TImode)
1549 && !s_operand (operands[1], TImode)
1550 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1551 [(set (match_dup 2) (match_dup 4))
1552 (set (match_dup 3) (match_dup 5))]
1554 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1555 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1556 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1557 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1560 ; Use part of the TImode target reg to perform the address
1561 ; calculation. If the TImode value is supposed to be copied into a VR
1562 ; this splitter is not necessary.
1564 [(set (match_operand:TI 0 "register_operand" "")
1565 (match_operand:TI 1 "memory_operand" ""))]
1566 "TARGET_ZARCH && reload_completed
1567 && !VECTOR_REG_P (operands[0])
1568 && !s_operand (operands[1], VOIDmode)"
1569 [(set (match_dup 0) (match_dup 1))]
1571 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1572 addr = gen_lowpart (Pmode, addr);
1573 s390_load_address (addr, XEXP (operands[1], 0));
1574 operands[1] = replace_equiv_address (operands[1], addr);
1578 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
1579 ; For the higher order bits we do simply a DImode move while the
1580 ; second part is done via vec extract. Both will end up as vlgvg.
1582 [(set (match_operand:TI 0 "register_operand" "")
1583 (match_operand:TI 1 "register_operand" ""))]
1584 "TARGET_VX && reload_completed
1585 && GENERAL_REG_P (operands[0])
1586 && VECTOR_REG_P (operands[1])"
1587 [(set (match_dup 2) (match_dup 4))
1588 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
1589 UNSPEC_VEC_EXTRACT))]
1591 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1592 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1593 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
1594 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
1598 ; Patterns used for secondary reloads
1601 ; z10 provides move instructions accepting larl memory operands.
1602 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1603 ; These patterns are also used for unaligned SI and DI accesses.
1605 (define_expand "reload<ALL:mode><P:mode>_tomem_z10"
1606 [(parallel [(match_operand:ALL 0 "memory_operand" "")
1607 (match_operand:ALL 1 "register_operand" "=d")
1608 (match_operand:P 2 "register_operand" "=&a")])]
1611 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1615 (define_expand "reload<ALL:mode><P:mode>_toreg_z10"
1616 [(parallel [(match_operand:ALL 0 "register_operand" "=d")
1617 (match_operand:ALL 1 "memory_operand" "")
1618 (match_operand:P 2 "register_operand" "=a")])]
1621 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1625 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1626 [(parallel [(match_operand:P 0 "register_operand" "=d")
1627 (match_operand:P 1 "larl_operand" "")
1628 (match_operand:P 2 "register_operand" "=a")])]
1631 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1635 ; Handles loading a PLUS (load address) expression
1637 (define_expand "reload<mode>_plus"
1638 [(parallel [(match_operand:P 0 "register_operand" "=a")
1639 (match_operand:P 1 "s390_plus_operand" "")
1640 (match_operand:P 2 "register_operand" "=&a")])]
1643 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1647 ; Not all the indirect memory access instructions support the full
1648 ; format (long disp + index + base). So whenever a move from/to such
1649 ; an address is required and the instruction cannot deal with it we do
1650 ; a load address into a scratch register first and use this as the new
1652 ; This in particular is used for:
1653 ; - non-offsetable memory accesses for multiword moves
1654 ; - full vector reg moves with long displacements
1656 (define_expand "reload<mode>_la_in"
1657 [(parallel [(match_operand 0 "register_operand" "")
1658 (match_operand 1 "" "")
1659 (match_operand:P 2 "register_operand" "=&a")])]
1662 gcc_assert (MEM_P (operands[1]));
1663 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1664 operands[1] = replace_equiv_address (operands[1], operands[2]);
1665 emit_move_insn (operands[0], operands[1]);
1669 (define_expand "reload<mode>_la_out"
1670 [(parallel [(match_operand 0 "" "")
1671 (match_operand 1 "register_operand" "")
1672 (match_operand:P 2 "register_operand" "=&a")])]
1675 gcc_assert (MEM_P (operands[0]));
1676 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1677 operands[0] = replace_equiv_address (operands[0], operands[2]);
1678 emit_move_insn (operands[0], operands[1]);
1682 (define_expand "reload<mode>_PIC_addr"
1683 [(parallel [(match_operand 0 "register_operand" "=d")
1684 (match_operand 1 "larl_operand" "")
1685 (match_operand:P 2 "register_operand" "=a")])]
1688 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1689 emit_move_insn (operands[0], new_rtx);
1693 ; movdi instruction pattern(s).
1696 (define_expand "movdi"
1697 [(set (match_operand:DI 0 "general_operand" "")
1698 (match_operand:DI 1 "general_operand" ""))]
1701 /* Handle symbolic constants. */
1703 && (SYMBOLIC_CONST (operands[1])
1704 || (GET_CODE (operands[1]) == PLUS
1705 && XEXP (operands[1], 0) == pic_offset_table_rtx
1706 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1707 emit_symbolic_move (operands);
1710 (define_insn "*movdi_larl"
1711 [(set (match_operand:DI 0 "register_operand" "=d")
1712 (match_operand:DI 1 "larl_operand" "X"))]
1714 && !FP_REG_P (operands[0])"
1716 [(set_attr "op_type" "RIL")
1717 (set_attr "type" "larl")
1718 (set_attr "z10prop" "z10_super_A1")])
1720 (define_insn "*movdi_64"
1721 [(set (match_operand:DI 0 "nonimmediate_operand"
1722 "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
1723 (match_operand:DI 1 "general_operand"
1724 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
1759 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1760 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
1761 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1762 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
1764 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1765 z10,*,*,*,*,*,longdisp,*,longdisp,
1766 z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx")
1767 (set_attr "z10prop" "z10_fwd_A1,
1796 [(set (match_operand:DI 0 "register_operand" "")
1797 (match_operand:DI 1 "register_operand" ""))]
1798 "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
1799 [(set (match_dup 2) (match_dup 3))
1800 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1801 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1802 "operands[2] = gen_lowpart (SImode, operands[0]);
1803 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1806 [(set (match_operand:DI 0 "register_operand" "")
1807 (match_operand:DI 1 "register_operand" ""))]
1808 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1809 && dead_or_set_p (insn, operands[1])"
1810 [(set (match_dup 3) (match_dup 2))
1811 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1812 (set (match_dup 4) (match_dup 2))]
1813 "operands[2] = gen_lowpart (SImode, operands[1]);
1814 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1817 [(set (match_operand:DI 0 "register_operand" "")
1818 (match_operand:DI 1 "register_operand" ""))]
1819 "TARGET_ZARCH && ACCESS_REG_P (operands[0])
1820 && !dead_or_set_p (insn, operands[1])"
1821 [(set (match_dup 3) (match_dup 2))
1822 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1823 (set (match_dup 4) (match_dup 2))
1824 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1825 "operands[2] = gen_lowpart (SImode, operands[1]);
1826 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1828 (define_insn "*movdi_31"
1829 [(set (match_operand:DI 0 "nonimmediate_operand"
1830 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1831 (match_operand:DI 1 "general_operand"
1832 " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
1847 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1848 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1849 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
1851 ; For a load from a symbol ref we can use one of the target registers
1852 ; together with larl to load the address.
1854 [(set (match_operand:DI 0 "register_operand" "")
1855 (match_operand:DI 1 "memory_operand" ""))]
1856 "!TARGET_ZARCH && reload_completed && TARGET_Z10
1857 && larl_operand (XEXP (operands[1], 0), SImode)"
1858 [(set (match_dup 2) (match_dup 3))
1859 (set (match_dup 0) (match_dup 1))]
1861 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1862 operands[3] = XEXP (operands[1], 0);
1863 operands[1] = replace_equiv_address (operands[1], operands[2]);
1867 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1868 (match_operand:DI 1 "general_operand" ""))]
1869 "!TARGET_ZARCH && reload_completed
1870 && !s_operand (operands[0], DImode)
1871 && !s_operand (operands[1], DImode)
1872 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1873 [(set (match_dup 2) (match_dup 4))
1874 (set (match_dup 3) (match_dup 5))]
1876 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1877 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1878 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1879 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1883 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1884 (match_operand:DI 1 "general_operand" ""))]
1885 "!TARGET_ZARCH && reload_completed
1886 && !s_operand (operands[0], DImode)
1887 && !s_operand (operands[1], DImode)
1888 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1889 [(set (match_dup 2) (match_dup 4))
1890 (set (match_dup 3) (match_dup 5))]
1892 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1893 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1894 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1895 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1899 [(set (match_operand:DI 0 "register_operand" "")
1900 (match_operand:DI 1 "memory_operand" ""))]
1901 "!TARGET_ZARCH && reload_completed
1902 && !FP_REG_P (operands[0])
1903 && !s_operand (operands[1], VOIDmode)"
1904 [(set (match_dup 0) (match_dup 1))]
1906 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1907 s390_load_address (addr, XEXP (operands[1], 0));
1908 operands[1] = replace_equiv_address (operands[1], addr);
1912 [(set (match_operand:DI 0 "register_operand" "")
1913 (mem:DI (match_operand 1 "address_operand" "")))]
1915 && !FP_REG_P (operands[0])
1916 && GET_CODE (operands[1]) == SYMBOL_REF
1917 && CONSTANT_POOL_ADDRESS_P (operands[1])
1918 && get_pool_mode (operands[1]) == DImode
1919 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1920 [(set (match_dup 0) (match_dup 2))]
1921 "operands[2] = get_pool_constant (operands[1]);")
1923 (define_insn "*la_64"
1924 [(set (match_operand:DI 0 "register_operand" "=d,d")
1925 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
1930 [(set_attr "op_type" "RX,RXY")
1931 (set_attr "type" "la")
1932 (set_attr "cpu_facility" "*,longdisp")
1933 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1937 [(set (match_operand:DI 0 "register_operand" "")
1938 (match_operand:QI 1 "address_operand" ""))
1939 (clobber (reg:CC CC_REGNUM))])]
1941 && preferred_la_operand_p (operands[1], const0_rtx)"
1942 [(set (match_dup 0) (match_dup 1))]
1946 [(set (match_operand:DI 0 "register_operand" "")
1947 (match_operand:DI 1 "register_operand" ""))
1950 (plus:DI (match_dup 0)
1951 (match_operand:DI 2 "nonmemory_operand" "")))
1952 (clobber (reg:CC CC_REGNUM))])]
1954 && !reg_overlap_mentioned_p (operands[0], operands[2])
1955 && preferred_la_operand_p (operands[1], operands[2])"
1956 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1960 ; movsi instruction pattern(s).
1963 (define_expand "movsi"
1964 [(set (match_operand:SI 0 "general_operand" "")
1965 (match_operand:SI 1 "general_operand" ""))]
1968 /* Handle symbolic constants. */
1970 && (SYMBOLIC_CONST (operands[1])
1971 || (GET_CODE (operands[1]) == PLUS
1972 && XEXP (operands[1], 0) == pic_offset_table_rtx
1973 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1974 emit_symbolic_move (operands);
1977 (define_insn "*movsi_larl"
1978 [(set (match_operand:SI 0 "register_operand" "=d")
1979 (match_operand:SI 1 "larl_operand" "X"))]
1980 "!TARGET_64BIT && TARGET_CPU_ZARCH
1981 && !FP_REG_P (operands[0])"
1983 [(set_attr "op_type" "RIL")
1984 (set_attr "type" "larl")
1985 (set_attr "z10prop" "z10_fwd_A1")])
1987 (define_insn "*movsi_zarch"
1988 [(set (match_operand:SI 0 "nonimmediate_operand"
1989 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
1990 (match_operand:SI 1 "general_operand"
1991 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
2024 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
2025 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
2026 (set_attr "type" "*,
2050 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
2051 vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
2052 (set_attr "z10prop" "z10_fwd_A1,
2077 (define_insn "*movsi_esa"
2078 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
2079 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
2095 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
2096 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
2097 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
2099 (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
2103 [(set (match_operand:SI 0 "register_operand" "")
2104 (mem:SI (match_operand 1 "address_operand" "")))]
2105 "!FP_REG_P (operands[0])
2106 && GET_CODE (operands[1]) == SYMBOL_REF
2107 && CONSTANT_POOL_ADDRESS_P (operands[1])
2108 && get_pool_mode (operands[1]) == SImode
2109 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
2110 [(set (match_dup 0) (match_dup 2))]
2111 "operands[2] = get_pool_constant (operands[1]);")
2113 (define_insn "*la_31"
2114 [(set (match_operand:SI 0 "register_operand" "=d,d")
2115 (match_operand:QI 1 "address_operand" "ZR,ZT"))]
2116 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
2120 [(set_attr "op_type" "RX,RXY")
2121 (set_attr "type" "la")
2122 (set_attr "cpu_facility" "*,longdisp")
2123 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2127 [(set (match_operand:SI 0 "register_operand" "")
2128 (match_operand:QI 1 "address_operand" ""))
2129 (clobber (reg:CC CC_REGNUM))])]
2131 && preferred_la_operand_p (operands[1], const0_rtx)"
2132 [(set (match_dup 0) (match_dup 1))]
2136 [(set (match_operand:SI 0 "register_operand" "")
2137 (match_operand:SI 1 "register_operand" ""))
2140 (plus:SI (match_dup 0)
2141 (match_operand:SI 2 "nonmemory_operand" "")))
2142 (clobber (reg:CC CC_REGNUM))])]
2144 && !reg_overlap_mentioned_p (operands[0], operands[2])
2145 && preferred_la_operand_p (operands[1], operands[2])"
2146 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2149 (define_insn "*la_31_and"
2150 [(set (match_operand:SI 0 "register_operand" "=d,d")
2151 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
2152 (const_int 2147483647)))]
2157 [(set_attr "op_type" "RX,RXY")
2158 (set_attr "type" "la")
2159 (set_attr "cpu_facility" "*,longdisp")
2160 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2162 (define_insn_and_split "*la_31_and_cc"
2163 [(set (match_operand:SI 0 "register_operand" "=d")
2164 (and:SI (match_operand:QI 1 "address_operand" "p")
2165 (const_int 2147483647)))
2166 (clobber (reg:CC CC_REGNUM))]
2169 "&& reload_completed"
2171 (and:SI (match_dup 1) (const_int 2147483647)))]
2173 [(set_attr "op_type" "RX")
2174 (set_attr "type" "la")])
2176 (define_insn "force_la_31"
2177 [(set (match_operand:SI 0 "register_operand" "=d,d")
2178 (match_operand:QI 1 "address_operand" "ZR,ZT"))
2179 (use (const_int 0))]
2184 [(set_attr "op_type" "RX")
2185 (set_attr "type" "la")
2186 (set_attr "cpu_facility" "*,longdisp")
2187 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
2190 ; movhi instruction pattern(s).
2193 (define_expand "movhi"
2194 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2195 (match_operand:HI 1 "general_operand" ""))]
2198 /* Make it explicit that loading a register from memory
2199 always sign-extends (at least) to SImode. */
2200 if (optimize && can_create_pseudo_p ()
2201 && register_operand (operands[0], VOIDmode)
2202 && GET_CODE (operands[1]) == MEM)
2204 rtx tmp = gen_reg_rtx (SImode);
2205 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
2206 emit_insn (gen_rtx_SET (tmp, ext));
2207 operands[1] = gen_lowpart (HImode, tmp);
2211 (define_insn "*movhi"
2212 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
2213 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
2231 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
2232 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
2233 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
2234 (set_attr "z10prop" "z10_fr_E1,
2242 z10_super,*,*,*,*,*,*")])
2245 [(set (match_operand:HI 0 "register_operand" "")
2246 (mem:HI (match_operand 1 "address_operand" "")))]
2247 "GET_CODE (operands[1]) == SYMBOL_REF
2248 && CONSTANT_POOL_ADDRESS_P (operands[1])
2249 && get_pool_mode (operands[1]) == HImode
2250 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2251 [(set (match_dup 0) (match_dup 2))]
2252 "operands[2] = get_pool_constant (operands[1]);")
2255 ; movqi instruction pattern(s).
2258 (define_expand "movqi"
2259 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2260 (match_operand:QI 1 "general_operand" ""))]
2263 /* On z/Architecture, zero-extending from memory to register
2264 is just as fast as a QImode load. */
2265 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
2266 && register_operand (operands[0], VOIDmode)
2267 && GET_CODE (operands[1]) == MEM)
2269 rtx tmp = gen_reg_rtx (DImode);
2270 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
2271 emit_insn (gen_rtx_SET (tmp, ext));
2272 operands[1] = gen_lowpart (QImode, tmp);
2276 (define_insn "*movqi"
2277 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
2278 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
2296 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
2297 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
2298 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
2299 (set_attr "z10prop" "z10_fr_E1,
2310 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2311 (mem:QI (match_operand 1 "address_operand" "")))]
2312 "GET_CODE (operands[1]) == SYMBOL_REF
2313 && CONSTANT_POOL_ADDRESS_P (operands[1])
2314 && get_pool_mode (operands[1]) == QImode
2315 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
2316 [(set (match_dup 0) (match_dup 2))]
2317 "operands[2] = get_pool_constant (operands[1]);")
2320 ; movstrictqi instruction pattern(s).
2323 (define_insn "*movstrictqi"
2324 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
2325 (match_operand:QI 1 "memory_operand" "R,T"))]
2330 [(set_attr "op_type" "RX,RXY")
2331 (set_attr "cpu_facility" "*,longdisp")
2332 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2335 ; movstricthi instruction pattern(s).
2338 (define_insn "*movstricthi"
2339 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
2340 (match_operand:HI 1 "memory_operand" "Q,S"))
2341 (clobber (reg:CC CC_REGNUM))]
2346 [(set_attr "op_type" "RS,RSY")
2347 (set_attr "cpu_facility" "*,longdisp")
2348 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
2351 ; movstrictsi instruction pattern(s).
2354 (define_insn "movstrictsi"
2355 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
2356 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
2363 [(set_attr "op_type" "RR,RX,RXY,RRE")
2364 (set_attr "type" "lr,load,load,*")
2365 (set_attr "cpu_facility" "*,*,longdisp,*")
2366 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
2369 ; mov(tf|td) instruction pattern(s).
2372 (define_expand "mov<mode>"
2373 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2374 (match_operand:TD_TF 1 "general_operand" ""))]
2378 (define_insn "*mov<mode>_64"
2379 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
2380 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
2391 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
2392 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
2393 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
2395 (define_insn "*mov<mode>_31"
2396 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
2397 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
2404 [(set_attr "op_type" "RRE,RRE,*,*")
2405 (set_attr "type" "fsimptf,fsimptf,*,*")
2406 (set_attr "cpu_facility" "z196,*,*,*")])
2408 ; TFmode in GPRs splitters
2411 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2412 (match_operand:TD_TF 1 "general_operand" ""))]
2413 "TARGET_ZARCH && reload_completed
2414 && !s_operand (operands[0], <MODE>mode)
2415 && !s_operand (operands[1], <MODE>mode)
2416 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2417 [(set (match_dup 2) (match_dup 4))
2418 (set (match_dup 3) (match_dup 5))]
2420 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2421 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2422 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2423 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2427 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
2428 (match_operand:TD_TF 1 "general_operand" ""))]
2429 "TARGET_ZARCH && reload_completed
2430 && !s_operand (operands[0], <MODE>mode)
2431 && !s_operand (operands[1], <MODE>mode)
2432 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2433 [(set (match_dup 2) (match_dup 4))
2434 (set (match_dup 3) (match_dup 5))]
2436 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2437 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2438 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2439 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2443 [(set (match_operand:TD_TF 0 "register_operand" "")
2444 (match_operand:TD_TF 1 "memory_operand" ""))]
2445 "TARGET_ZARCH && reload_completed
2446 && GENERAL_REG_P (operands[0])
2447 && !s_operand (operands[1], VOIDmode)"
2448 [(set (match_dup 0) (match_dup 1))]
2450 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2451 addr = gen_lowpart (Pmode, addr);
2452 s390_load_address (addr, XEXP (operands[1], 0));
2453 operands[1] = replace_equiv_address (operands[1], addr);
2456 ; TFmode in BFPs splitters
2459 [(set (match_operand:TD_TF 0 "register_operand" "")
2460 (match_operand:TD_TF 1 "memory_operand" ""))]
2461 "reload_completed && offsettable_memref_p (operands[1])
2462 && FP_REG_P (operands[0])"
2463 [(set (match_dup 2) (match_dup 4))
2464 (set (match_dup 3) (match_dup 5))]
2466 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2468 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
2470 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
2471 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
2475 [(set (match_operand:TD_TF 0 "memory_operand" "")
2476 (match_operand:TD_TF 1 "register_operand" ""))]
2477 "reload_completed && offsettable_memref_p (operands[0])
2478 && FP_REG_P (operands[1])"
2479 [(set (match_dup 2) (match_dup 4))
2480 (set (match_dup 3) (match_dup 5))]
2482 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
2483 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
2484 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2486 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2491 ; mov(df|dd) instruction pattern(s).
2494 (define_expand "mov<mode>"
2495 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2496 (match_operand:DD_DF 1 "general_operand" ""))]
2500 (define_insn "*mov<mode>_64dfp"
2501 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2502 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R")
2503 (match_operand:DD_DF 1 "general_operand"
2504 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))]
2527 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2528 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2529 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
2530 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
2531 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")])
2533 (define_insn "*mov<mode>_64"
2534 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
2535 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))]
2550 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY")
2551 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2552 fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
2553 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2554 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")])
2556 (define_insn "*mov<mode>_31"
2557 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2558 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2559 (match_operand:DD_DF 1 "general_operand"
2560 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
2575 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2576 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
2577 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
2578 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
2581 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2582 (match_operand:DD_DF 1 "general_operand" ""))]
2583 "!TARGET_ZARCH && reload_completed
2584 && !s_operand (operands[0], <MODE>mode)
2585 && !s_operand (operands[1], <MODE>mode)
2586 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2587 [(set (match_dup 2) (match_dup 4))
2588 (set (match_dup 3) (match_dup 5))]
2590 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2591 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2592 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2593 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2597 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2598 (match_operand:DD_DF 1 "general_operand" ""))]
2599 "!TARGET_ZARCH && reload_completed
2600 && !s_operand (operands[0], <MODE>mode)
2601 && !s_operand (operands[1], <MODE>mode)
2602 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2603 [(set (match_dup 2) (match_dup 4))
2604 (set (match_dup 3) (match_dup 5))]
2606 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2607 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2608 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2609 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2613 [(set (match_operand:DD_DF 0 "register_operand" "")
2614 (match_operand:DD_DF 1 "memory_operand" ""))]
2615 "!TARGET_ZARCH && reload_completed
2616 && !FP_REG_P (operands[0])
2617 && !s_operand (operands[1], VOIDmode)"
2618 [(set (match_dup 0) (match_dup 1))]
2620 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2621 s390_load_address (addr, XEXP (operands[1], 0));
2622 operands[1] = replace_equiv_address (operands[1], addr);
2626 ; mov(sf|sd) instruction pattern(s).
2629 (define_insn "mov<mode>"
2630 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2631 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
2632 (match_operand:SD_SF 1 "general_operand"
2633 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
2658 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
2659 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
2660 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
2661 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
2662 (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
2665 ; movcc instruction pattern
2668 (define_insn "movcc"
2669 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2670 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))]
2680 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2681 (set_attr "type" "lr,*,*,load,load,store,store")
2682 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
2683 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
2684 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
2687 ; Block move (MVC) patterns.
2691 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2692 (match_operand:BLK 1 "memory_operand" "Q"))
2693 (use (match_operand 2 "const_int_operand" "n"))]
2694 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2695 "mvc\t%O0(%2,%R0),%S1"
2696 [(set_attr "op_type" "SS")])
2698 ; This splitter converts a QI to QI mode copy into a BLK mode copy in
2699 ; order to have it implemented with mvc.
2702 [(set (match_operand:QI 0 "memory_operand" "")
2703 (match_operand:QI 1 "memory_operand" ""))]
2706 [(set (match_dup 0) (match_dup 1))
2707 (use (const_int 1))])]
2709 operands[0] = adjust_address (operands[0], BLKmode, 0);
2710 operands[1] = adjust_address (operands[1], BLKmode, 0);
2716 [(set (match_operand:BLK 0 "memory_operand" "")
2717 (match_operand:BLK 1 "memory_operand" ""))
2718 (use (match_operand 2 "const_int_operand" ""))])
2720 [(set (match_operand:BLK 3 "memory_operand" "")
2721 (match_operand:BLK 4 "memory_operand" ""))
2722 (use (match_operand 5 "const_int_operand" ""))])]
2723 "s390_offset_p (operands[0], operands[3], operands[2])
2724 && s390_offset_p (operands[1], operands[4], operands[2])
2725 && !s390_overlap_p (operands[0], operands[1],
2726 INTVAL (operands[2]) + INTVAL (operands[5]))
2727 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2729 [(set (match_dup 6) (match_dup 7))
2730 (use (match_dup 8))])]
2731 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2732 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2733 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2737 ; load_multiple pattern(s).
2739 ; ??? Due to reload problems with replacing registers inside match_parallel
2740 ; we currently support load_multiple/store_multiple only after reload.
2743 (define_expand "load_multiple"
2744 [(match_par_dup 3 [(set (match_operand 0 "" "")
2745 (match_operand 1 "" ""))
2746 (use (match_operand 2 "" ""))])]
2755 /* Support only loading a constant number of fixed-point registers from
2756 memory and only bother with this if more than two */
2757 if (GET_CODE (operands[2]) != CONST_INT
2758 || INTVAL (operands[2]) < 2
2759 || INTVAL (operands[2]) > 16
2760 || GET_CODE (operands[1]) != MEM
2761 || GET_CODE (operands[0]) != REG
2762 || REGNO (operands[0]) >= 16)
2765 count = INTVAL (operands[2]);
2766 regno = REGNO (operands[0]);
2767 mode = GET_MODE (operands[0]);
2768 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2771 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2772 if (!can_create_pseudo_p ())
2774 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2776 from = XEXP (operands[1], 0);
2779 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2780 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2781 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2783 from = XEXP (XEXP (operands[1], 0), 0);
2784 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2791 from = force_reg (Pmode, XEXP (operands[1], 0));
2795 for (i = 0; i < count; i++)
2796 XVECEXP (operands[3], 0, i)
2797 = gen_rtx_SET (gen_rtx_REG (mode, regno + i),
2798 change_address (operands[1], mode,
2799 plus_constant (Pmode, from,
2800 off + i * GET_MODE_SIZE (mode))));
2803 (define_insn "*load_multiple_di"
2804 [(match_parallel 0 "load_multiple_operation"
2805 [(set (match_operand:DI 1 "register_operand" "=r")
2806 (match_operand:DI 2 "s_operand" "S"))])]
2807 "reload_completed && TARGET_ZARCH"
2809 int words = XVECLEN (operands[0], 0);
2810 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2811 return "lmg\t%1,%0,%S2";
2813 [(set_attr "op_type" "RSY")
2814 (set_attr "type" "lm")])
2816 (define_insn "*load_multiple_si"
2817 [(match_parallel 0 "load_multiple_operation"
2818 [(set (match_operand:SI 1 "register_operand" "=r,r")
2819 (match_operand:SI 2 "s_operand" "Q,S"))])]
2822 int words = XVECLEN (operands[0], 0);
2823 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2824 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2826 [(set_attr "op_type" "RS,RSY")
2827 (set_attr "cpu_facility" "*,longdisp")
2828 (set_attr "type" "lm")])
2831 ; store multiple pattern(s).
2834 (define_expand "store_multiple"
2835 [(match_par_dup 3 [(set (match_operand 0 "" "")
2836 (match_operand 1 "" ""))
2837 (use (match_operand 2 "" ""))])]
2846 /* Support only storing a constant number of fixed-point registers to
2847 memory and only bother with this if more than two. */
2848 if (GET_CODE (operands[2]) != CONST_INT
2849 || INTVAL (operands[2]) < 2
2850 || INTVAL (operands[2]) > 16
2851 || GET_CODE (operands[0]) != MEM
2852 || GET_CODE (operands[1]) != REG
2853 || REGNO (operands[1]) >= 16)
2856 count = INTVAL (operands[2]);
2857 regno = REGNO (operands[1]);
2858 mode = GET_MODE (operands[1]);
2859 if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
2862 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2864 if (!can_create_pseudo_p ())
2866 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2868 to = XEXP (operands[0], 0);
2871 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2872 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2873 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2875 to = XEXP (XEXP (operands[0], 0), 0);
2876 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2883 to = force_reg (Pmode, XEXP (operands[0], 0));
2887 for (i = 0; i < count; i++)
2888 XVECEXP (operands[3], 0, i)
2889 = gen_rtx_SET (change_address (operands[0], mode,
2890 plus_constant (Pmode, to,
2891 off + i * GET_MODE_SIZE (mode))),
2892 gen_rtx_REG (mode, regno + i));
2895 (define_insn "*store_multiple_di"
2896 [(match_parallel 0 "store_multiple_operation"
2897 [(set (match_operand:DI 1 "s_operand" "=S")
2898 (match_operand:DI 2 "register_operand" "r"))])]
2899 "reload_completed && TARGET_ZARCH"
2901 int words = XVECLEN (operands[0], 0);
2902 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2903 return "stmg\t%2,%0,%S1";
2905 [(set_attr "op_type" "RSY")
2906 (set_attr "type" "stm")])
2909 (define_insn "*store_multiple_si"
2910 [(match_parallel 0 "store_multiple_operation"
2911 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2912 (match_operand:SI 2 "register_operand" "r,r"))])]
2915 int words = XVECLEN (operands[0], 0);
2916 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2917 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2919 [(set_attr "op_type" "RS,RSY")
2920 (set_attr "cpu_facility" "*,longdisp")
2921 (set_attr "type" "stm")])
2924 ;; String instructions.
2927 (define_insn "*execute_rl"
2928 [(match_parallel 0 "execute_operation"
2929 [(unspec [(match_operand 1 "register_operand" "a")
2930 (match_operand 2 "" "")
2931 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2932 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2933 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2935 [(set_attr "op_type" "RIL")
2936 (set_attr "type" "cs")])
2938 (define_insn "*execute"
2939 [(match_parallel 0 "execute_operation"
2940 [(unspec [(match_operand 1 "register_operand" "a")
2941 (match_operand:BLK 2 "memory_operand" "R")
2942 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2943 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2944 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2946 [(set_attr "op_type" "RX")
2947 (set_attr "type" "cs")])
2951 ; strlenM instruction pattern(s).
2954 (define_expand "strlen<mode>"
2955 [(match_operand:P 0 "register_operand" "") ; result
2956 (match_operand:BLK 1 "memory_operand" "") ; input string
2957 (match_operand:SI 2 "immediate_operand" "") ; search character
2958 (match_operand:SI 3 "immediate_operand" "")] ; known alignment
2961 if (!TARGET_VX || operands[2] != const0_rtx)
2962 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
2963 operands[2], operands[3]));
2965 s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
2970 (define_expand "strlen_srst<mode>"
2971 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2974 (unspec:P [(const_int 0)
2975 (match_operand:BLK 1 "memory_operand" "")
2977 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2978 (clobber (scratch:P))
2979 (clobber (reg:CC CC_REGNUM))])
2981 [(set (match_operand:P 0 "register_operand" "")
2982 (minus:P (match_dup 4) (match_dup 5)))
2983 (clobber (reg:CC CC_REGNUM))])]
2986 operands[4] = gen_reg_rtx (Pmode);
2987 operands[5] = gen_reg_rtx (Pmode);
2988 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2989 operands[1] = replace_equiv_address (operands[1], operands[5]);
2992 (define_insn "*strlen<mode>"
2993 [(set (match_operand:P 0 "register_operand" "=a")
2994 (unspec:P [(match_operand:P 2 "general_operand" "0")
2995 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2997 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2998 (clobber (match_scratch:P 1 "=a"))
2999 (clobber (reg:CC CC_REGNUM))]
3001 "srst\t%0,%1\;jo\t.-4"
3002 [(set_attr "length" "8")
3003 (set_attr "type" "vs")])
3006 ; cmpstrM instruction pattern(s).
3009 (define_expand "cmpstrsi"
3010 [(set (reg:SI 0) (const_int 0))
3012 [(clobber (match_operand 3 "" ""))
3013 (clobber (match_dup 4))
3014 (set (reg:CCU CC_REGNUM)
3015 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
3016 (match_operand:BLK 2 "memory_operand" "")))
3019 [(set (match_operand:SI 0 "register_operand" "=d")
3020 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT))
3021 (clobber (reg:CC CC_REGNUM))])]
3024 /* As the result of CMPINT is inverted compared to what we need,
3025 we have to swap the operands. */
3026 rtx op1 = operands[2];
3027 rtx op2 = operands[1];
3028 rtx addr1 = gen_reg_rtx (Pmode);
3029 rtx addr2 = gen_reg_rtx (Pmode);
3031 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3032 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
3033 operands[1] = replace_equiv_address_nv (op1, addr1);
3034 operands[2] = replace_equiv_address_nv (op2, addr2);
3035 operands[3] = addr1;
3036 operands[4] = addr2;
3039 (define_insn "*cmpstr<mode>"
3040 [(clobber (match_operand:P 0 "register_operand" "=d"))
3041 (clobber (match_operand:P 1 "register_operand" "=d"))
3042 (set (reg:CCU CC_REGNUM)
3043 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
3044 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
3047 "clst\t%0,%1\;jo\t.-4"
3048 [(set_attr "length" "8")
3049 (set_attr "type" "vs")])
3052 ; movstr instruction pattern.
3055 (define_expand "movstr"
3056 [(match_operand 0 "register_operand" "")
3057 (match_operand 1 "memory_operand" "")
3058 (match_operand 2 "memory_operand" "")]
3062 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
3064 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
3068 (define_expand "movstr<P:mode>"
3069 [(set (reg:SI 0) (const_int 0))
3071 [(clobber (match_dup 3))
3072 (set (match_operand:BLK 1 "memory_operand" "")
3073 (match_operand:BLK 2 "memory_operand" ""))
3074 (set (match_operand:P 0 "register_operand" "")
3075 (unspec:P [(match_dup 1)
3077 (reg:SI 0)] UNSPEC_MVST))
3078 (clobber (reg:CC CC_REGNUM))])]
3083 if (TARGET_VX && optimize_function_for_speed_p (cfun))
3085 s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
3089 addr1 = gen_reg_rtx (Pmode);
3090 addr2 = gen_reg_rtx (Pmode);
3092 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3093 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
3094 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3095 operands[2] = replace_equiv_address_nv (operands[2], addr2);
3096 operands[3] = addr2;
3099 (define_insn "*movstr"
3100 [(clobber (match_operand:P 2 "register_operand" "=d"))
3101 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
3102 (mem:BLK (match_operand:P 3 "register_operand" "2")))
3103 (set (match_operand:P 0 "register_operand" "=d")
3104 (unspec:P [(mem:BLK (match_dup 1))
3105 (mem:BLK (match_dup 3))
3106 (reg:SI 0)] UNSPEC_MVST))
3107 (clobber (reg:CC CC_REGNUM))]
3109 "mvst\t%1,%2\;jo\t.-4"
3110 [(set_attr "length" "8")
3111 (set_attr "type" "vs")])
3115 ; movmemM instruction pattern(s).
3118 (define_expand "movmem<mode>"
3119 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
3120 (match_operand:BLK 1 "memory_operand" "")) ; source
3121 (use (match_operand:GPR 2 "general_operand" "")) ; count
3122 (match_operand 3 "" "")]
3125 if (s390_expand_movmem (operands[0], operands[1], operands[2]))
3131 ; Move a block that is up to 256 bytes in length.
3132 ; The block length is taken as (operands[2] % 256) + 1.
3134 (define_expand "movmem_short"
3136 [(set (match_operand:BLK 0 "memory_operand" "")
3137 (match_operand:BLK 1 "memory_operand" ""))
3138 (use (match_operand 2 "nonmemory_operand" ""))
3139 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3140 (clobber (match_dup 3))])]
3142 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3144 (define_insn "*movmem_short"
3145 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3146 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
3147 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3148 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3149 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3150 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3152 [(set_attr "type" "cs")
3153 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3156 [(set (match_operand:BLK 0 "memory_operand" "")
3157 (match_operand:BLK 1 "memory_operand" ""))
3158 (use (match_operand 2 "const_int_operand" ""))
3159 (use (match_operand 3 "immediate_operand" ""))
3160 (clobber (scratch))]
3163 [(set (match_dup 0) (match_dup 1))
3164 (use (match_dup 2))])]
3165 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3168 [(set (match_operand:BLK 0 "memory_operand" "")
3169 (match_operand:BLK 1 "memory_operand" ""))
3170 (use (match_operand 2 "register_operand" ""))
3171 (use (match_operand 3 "memory_operand" ""))
3172 (clobber (scratch))]
3175 [(unspec [(match_dup 2) (match_dup 3)
3176 (const_int 0)] UNSPEC_EXECUTE)
3177 (set (match_dup 0) (match_dup 1))
3178 (use (const_int 1))])]
3182 [(set (match_operand:BLK 0 "memory_operand" "")
3183 (match_operand:BLK 1 "memory_operand" ""))
3184 (use (match_operand 2 "register_operand" ""))
3185 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3186 (clobber (scratch))]
3187 "TARGET_Z10 && reload_completed"
3189 [(unspec [(match_dup 2) (const_int 0)
3190 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3191 (set (match_dup 0) (match_dup 1))
3192 (use (const_int 1))])]
3193 "operands[3] = gen_label_rtx ();")
3196 [(set (match_operand:BLK 0 "memory_operand" "")
3197 (match_operand:BLK 1 "memory_operand" ""))
3198 (use (match_operand 2 "register_operand" ""))
3199 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3200 (clobber (match_operand 3 "register_operand" ""))]
3201 "reload_completed && TARGET_CPU_ZARCH"
3202 [(set (match_dup 3) (label_ref (match_dup 4)))
3204 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3205 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3206 (set (match_dup 0) (match_dup 1))
3207 (use (const_int 1))])]
3208 "operands[4] = gen_label_rtx ();")
3210 ; Move a block of arbitrary length.
3212 (define_expand "movmem_long"
3214 [(clobber (match_dup 2))
3215 (clobber (match_dup 3))
3216 (set (match_operand:BLK 0 "memory_operand" "")
3217 (match_operand:BLK 1 "memory_operand" ""))
3218 (use (match_operand 2 "general_operand" ""))
3220 (clobber (reg:CC CC_REGNUM))])]
3223 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3224 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3225 rtx reg0 = gen_reg_rtx (dreg_mode);
3226 rtx reg1 = gen_reg_rtx (dreg_mode);
3227 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3228 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3229 rtx len0 = gen_lowpart (Pmode, reg0);
3230 rtx len1 = gen_lowpart (Pmode, reg1);
3232 emit_clobber (reg0);
3233 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3234 emit_move_insn (len0, operands[2]);
3236 emit_clobber (reg1);
3237 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3238 emit_move_insn (len1, operands[2]);
3240 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3241 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3246 (define_insn "*movmem_long"
3247 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3248 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3249 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3250 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
3253 (clobber (reg:CC CC_REGNUM))]
3254 "TARGET_64BIT || !TARGET_ZARCH"
3255 "mvcle\t%0,%1,0\;jo\t.-4"
3256 [(set_attr "length" "8")
3257 (set_attr "type" "vs")])
3259 (define_insn "*movmem_long_31z"
3260 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3261 (clobber (match_operand:TI 1 "register_operand" "=d"))
3262 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3263 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
3266 (clobber (reg:CC CC_REGNUM))]
3267 "!TARGET_64BIT && TARGET_ZARCH"
3268 "mvcle\t%0,%1,0\;jo\t.-4"
3269 [(set_attr "length" "8")
3270 (set_attr "type" "vs")])
3277 (define_expand "signbit<mode>2"
3278 [(set (reg:CCZ CC_REGNUM)
3279 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3282 (set (match_operand:SI 0 "register_operand" "=d")
3283 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3286 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
3289 (define_expand "isinf<mode>2"
3290 [(set (reg:CCZ CC_REGNUM)
3291 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
3294 (set (match_operand:SI 0 "register_operand" "=d")
3295 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))]
3298 operands[2] = GEN_INT (S390_TDC_INFINITY);
3301 ; This extracts CC into a GPR properly shifted. The actual IPM
3302 ; instruction will be issued by reload. The constraint of operand 1
3303 ; forces reload to use a GPR. So reload will issue a movcc insn for
3304 ; copying CC into a GPR first.
3305 (define_insn_and_split "*cc_to_int"
3306 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3307 (unspec:SI [(match_operand 1 "register_operand" "0")]
3312 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
3314 ; This insn is used to generate all variants of the Test Data Class
3315 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
3316 ; is the register to be tested and the second one is the bit mask
3317 ; specifying the required test(s).
3319 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet
3320 (define_insn "*TDC_insn_<mode>"
3321 [(set (reg:CCZ CC_REGNUM)
3322 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
3323 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
3325 "t<_d>c<xde><bt>\t%0,%1"
3326 [(set_attr "op_type" "RXE")
3327 (set_attr "type" "fsimp<mode>")])
3332 ; setmemM instruction pattern(s).
3335 (define_expand "setmem<mode>"
3336 [(set (match_operand:BLK 0 "memory_operand" "")
3337 (match_operand:QI 2 "general_operand" ""))
3338 (use (match_operand:GPR 1 "general_operand" ""))
3339 (match_operand 3 "" "")]
3341 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
3343 ; Clear a block that is up to 256 bytes in length.
3344 ; The block length is taken as (operands[1] % 256) + 1.
3346 (define_expand "clrmem_short"
3348 [(set (match_operand:BLK 0 "memory_operand" "")
3350 (use (match_operand 1 "nonmemory_operand" ""))
3351 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3352 (clobber (match_dup 2))
3353 (clobber (reg:CC CC_REGNUM))])]
3355 "operands[2] = gen_rtx_SCRATCH (Pmode);")
3357 (define_insn "*clrmem_short"
3358 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
3360 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
3361 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
3362 (clobber (match_scratch:P 3 "=X,X,X,&a"))
3363 (clobber (reg:CC CC_REGNUM))]
3364 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)"
3366 [(set_attr "type" "cs")
3367 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3370 [(set (match_operand:BLK 0 "memory_operand" "")
3372 (use (match_operand 1 "const_int_operand" ""))
3373 (use (match_operand 2 "immediate_operand" ""))
3375 (clobber (reg:CC CC_REGNUM))]
3378 [(set (match_dup 0) (const_int 0))
3380 (clobber (reg:CC CC_REGNUM))])]
3381 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
3384 [(set (match_operand:BLK 0 "memory_operand" "")
3386 (use (match_operand 1 "register_operand" ""))
3387 (use (match_operand 2 "memory_operand" ""))
3389 (clobber (reg:CC CC_REGNUM))]
3392 [(unspec [(match_dup 1) (match_dup 2)
3393 (const_int 0)] UNSPEC_EXECUTE)
3394 (set (match_dup 0) (const_int 0))
3396 (clobber (reg:CC CC_REGNUM))])]
3400 [(set (match_operand:BLK 0 "memory_operand" "")
3402 (use (match_operand 1 "register_operand" ""))
3403 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3405 (clobber (reg:CC CC_REGNUM))]
3406 "TARGET_Z10 && reload_completed"
3408 [(unspec [(match_dup 1) (const_int 0)
3409 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3410 (set (match_dup 0) (const_int 0))
3412 (clobber (reg:CC CC_REGNUM))])]
3413 "operands[3] = gen_label_rtx ();")
3416 [(set (match_operand:BLK 0 "memory_operand" "")
3418 (use (match_operand 1 "register_operand" ""))
3419 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3420 (clobber (match_operand 2 "register_operand" ""))
3421 (clobber (reg:CC CC_REGNUM))]
3422 "reload_completed && TARGET_CPU_ZARCH"
3423 [(set (match_dup 2) (label_ref (match_dup 3)))
3425 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
3426 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
3427 (set (match_dup 0) (const_int 0))
3429 (clobber (reg:CC CC_REGNUM))])]
3430 "operands[3] = gen_label_rtx ();")
3432 ; Initialize a block of arbitrary length with (operands[2] % 256).
3434 (define_expand "setmem_long_<P:mode>"
3436 [(clobber (match_dup 1))
3437 (set (match_operand:BLK 0 "memory_operand" "")
3438 (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
3439 (match_dup 4)] UNSPEC_REPLICATE_BYTE))
3441 (clobber (reg:CC CC_REGNUM))])]
3444 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3445 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3446 rtx reg0 = gen_reg_rtx (dreg_mode);
3447 rtx reg1 = gen_reg_rtx (dreg_mode);
3448 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3449 rtx len0 = gen_lowpart (Pmode, reg0);
3451 emit_clobber (reg0);
3452 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3453 emit_move_insn (len0, operands[1]);
3455 emit_move_insn (reg1, const0_rtx);
3457 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3460 operands[4] = gen_lowpart (Pmode, operands[1]);
3463 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
3465 (define_insn "*setmem_long"
3466 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3467 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3468 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
3469 (subreg:P (match_dup 3) <modesize>)]
3470 UNSPEC_REPLICATE_BYTE))
3471 (use (match_operand:<DBL> 1 "register_operand" "d"))
3472 (clobber (reg:CC CC_REGNUM))]
3473 "TARGET_64BIT || !TARGET_ZARCH"
3474 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3475 [(set_attr "length" "8")
3476 (set_attr "type" "vs")])
3478 (define_insn "*setmem_long_and"
3479 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3480 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
3481 (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
3482 (subreg:P (match_dup 3) <modesize>)]
3483 UNSPEC_REPLICATE_BYTE))
3484 (use (match_operand:<DBL> 1 "register_operand" "d"))
3485 (clobber (reg:CC CC_REGNUM))]
3486 "(TARGET_64BIT || !TARGET_ZARCH)"
3487 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3488 [(set_attr "length" "8")
3489 (set_attr "type" "vs")])
3491 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
3492 ; of the SImode subregs.
3494 (define_insn "*setmem_long_31z"
3495 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3496 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3497 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
3498 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3499 (use (match_operand:TI 1 "register_operand" "d"))
3500 (clobber (reg:CC CC_REGNUM))]
3501 "!TARGET_64BIT && TARGET_ZARCH"
3502 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3503 [(set_attr "length" "8")
3504 (set_attr "type" "vs")])
3506 (define_insn "*setmem_long_and_31z"
3507 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3508 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
3509 (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
3510 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
3511 (use (match_operand:TI 1 "register_operand" "d"))
3512 (clobber (reg:CC CC_REGNUM))]
3513 "(!TARGET_64BIT && TARGET_ZARCH)"
3514 "mvcle\t%0,%1,%Y2\;jo\t.-4"
3515 [(set_attr "length" "8")
3516 (set_attr "type" "vs")])
3519 ; cmpmemM instruction pattern(s).
3522 (define_expand "cmpmemsi"
3523 [(set (match_operand:SI 0 "register_operand" "")
3524 (compare:SI (match_operand:BLK 1 "memory_operand" "")
3525 (match_operand:BLK 2 "memory_operand" "") ) )
3526 (use (match_operand:SI 3 "general_operand" ""))
3527 (use (match_operand:SI 4 "" ""))]
3530 if (s390_expand_cmpmem (operands[0], operands[1],
3531 operands[2], operands[3]))
3537 ; Compare a block that is up to 256 bytes in length.
3538 ; The block length is taken as (operands[2] % 256) + 1.
3540 (define_expand "cmpmem_short"
3542 [(set (reg:CCU CC_REGNUM)
3543 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3544 (match_operand:BLK 1 "memory_operand" "")))
3545 (use (match_operand 2 "nonmemory_operand" ""))
3546 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3547 (clobber (match_dup 3))])]
3549 "operands[3] = gen_rtx_SCRATCH (Pmode);")
3551 (define_insn "*cmpmem_short"
3552 [(set (reg:CCU CC_REGNUM)
3553 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
3554 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
3555 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
3556 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
3557 (clobber (match_scratch:P 4 "=X,X,X,&a"))]
3558 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)"
3560 [(set_attr "type" "cs")
3561 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")])
3564 [(set (reg:CCU CC_REGNUM)
3565 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3566 (match_operand:BLK 1 "memory_operand" "")))
3567 (use (match_operand 2 "const_int_operand" ""))
3568 (use (match_operand 3 "immediate_operand" ""))
3569 (clobber (scratch))]
3572 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3573 (use (match_dup 2))])]
3574 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
3577 [(set (reg:CCU CC_REGNUM)
3578 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3579 (match_operand:BLK 1 "memory_operand" "")))
3580 (use (match_operand 2 "register_operand" ""))
3581 (use (match_operand 3 "memory_operand" ""))
3582 (clobber (scratch))]
3585 [(unspec [(match_dup 2) (match_dup 3)
3586 (const_int 0)] UNSPEC_EXECUTE)
3587 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3588 (use (const_int 1))])]
3592 [(set (reg:CCU CC_REGNUM)
3593 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3594 (match_operand:BLK 1 "memory_operand" "")))
3595 (use (match_operand 2 "register_operand" ""))
3596 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3597 (clobber (scratch))]
3598 "TARGET_Z10 && reload_completed"
3600 [(unspec [(match_dup 2) (const_int 0)
3601 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3602 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3603 (use (const_int 1))])]
3604 "operands[4] = gen_label_rtx ();")
3607 [(set (reg:CCU CC_REGNUM)
3608 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3609 (match_operand:BLK 1 "memory_operand" "")))
3610 (use (match_operand 2 "register_operand" ""))
3611 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3612 (clobber (match_operand 3 "register_operand" ""))]
3613 "reload_completed && TARGET_CPU_ZARCH"
3614 [(set (match_dup 3) (label_ref (match_dup 4)))
3616 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3617 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3618 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3619 (use (const_int 1))])]
3620 "operands[4] = gen_label_rtx ();")
3622 ; Compare a block of arbitrary length.
3624 (define_expand "cmpmem_long"
3626 [(clobber (match_dup 2))
3627 (clobber (match_dup 3))
3628 (set (reg:CCU CC_REGNUM)
3629 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3630 (match_operand:BLK 1 "memory_operand" "")))
3631 (use (match_operand 2 "general_operand" ""))
3632 (use (match_dup 3))])]
3635 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
3636 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
3637 rtx reg0 = gen_reg_rtx (dreg_mode);
3638 rtx reg1 = gen_reg_rtx (dreg_mode);
3639 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
3640 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
3641 rtx len0 = gen_lowpart (Pmode, reg0);
3642 rtx len1 = gen_lowpart (Pmode, reg1);
3644 emit_clobber (reg0);
3645 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3646 emit_move_insn (len0, operands[2]);
3648 emit_clobber (reg1);
3649 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3650 emit_move_insn (len1, operands[2]);
3652 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3653 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3658 (define_insn "*cmpmem_long"
3659 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3660 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3661 (set (reg:CCU CC_REGNUM)
3662 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3663 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3665 (use (match_dup 3))]
3666 "TARGET_64BIT || !TARGET_ZARCH"
3667 "clcle\t%0,%1,0\;jo\t.-4"
3668 [(set_attr "length" "8")
3669 (set_attr "type" "vs")])
3671 (define_insn "*cmpmem_long_31z"
3672 [(clobber (match_operand:TI 0 "register_operand" "=d"))
3673 (clobber (match_operand:TI 1 "register_operand" "=d"))
3674 (set (reg:CCU CC_REGNUM)
3675 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
3676 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
3678 (use (match_dup 3))]
3679 "!TARGET_64BIT && TARGET_ZARCH"
3680 "clcle\t%0,%1,0\;jo\t.-4"
3681 [(set_attr "op_type" "NN")
3682 (set_attr "type" "vs")
3683 (set_attr "length" "8")])
3685 ; Convert CCUmode condition code to integer.
3686 ; Result is zero if EQ, positive if LTU, negative if GTU.
3688 (define_insn_and_split "cmpint"
3689 [(set (match_operand:SI 0 "register_operand" "=d")
3690 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3691 UNSPEC_STRCMPCC_TO_INT))
3692 (clobber (reg:CC CC_REGNUM))]
3696 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3698 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3699 (clobber (reg:CC CC_REGNUM))])])
3701 (define_insn_and_split "*cmpint_cc"
3702 [(set (reg CC_REGNUM)
3703 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3704 UNSPEC_STRCMPCC_TO_INT)
3706 (set (match_operand:SI 0 "register_operand" "=d")
3707 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))]
3708 "s390_match_ccmode (insn, CCSmode)"
3710 "&& reload_completed"
3711 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3713 [(set (match_dup 2) (match_dup 3))
3714 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3716 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3717 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3718 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3721 (define_insn_and_split "*cmpint_sign"
3722 [(set (match_operand:DI 0 "register_operand" "=d")
3723 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3724 UNSPEC_STRCMPCC_TO_INT)))
3725 (clobber (reg:CC CC_REGNUM))]
3728 "&& reload_completed"
3729 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3731 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3732 (clobber (reg:CC CC_REGNUM))])])
3734 (define_insn_and_split "*cmpint_sign_cc"
3735 [(set (reg CC_REGNUM)
3736 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3737 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3738 UNSPEC_STRCMPCC_TO_INT) 0)
3739 (const_int 32)) (const_int 32))
3741 (set (match_operand:DI 0 "register_operand" "=d")
3742 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))]
3743 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
3745 "&& reload_completed"
3746 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3748 [(set (match_dup 2) (match_dup 3))
3749 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3751 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3752 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3753 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3758 ;;- Conversion instructions.
3761 (define_insn "*sethighpartsi"
3762 [(set (match_operand:SI 0 "register_operand" "=d,d")
3763 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3764 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3765 (clobber (reg:CC CC_REGNUM))]
3770 [(set_attr "op_type" "RS,RSY")
3771 (set_attr "cpu_facility" "*,longdisp")
3772 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3774 (define_insn "*sethighpartdi_64"
3775 [(set (match_operand:DI 0 "register_operand" "=d")
3776 (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
3777 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3778 (clobber (reg:CC CC_REGNUM))]
3781 [(set_attr "op_type" "RSY")
3782 (set_attr "z10prop" "z10_super")])
3784 (define_insn "*sethighpartdi_31"
3785 [(set (match_operand:DI 0 "register_operand" "=d,d")
3786 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3787 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3788 (clobber (reg:CC CC_REGNUM))]
3793 [(set_attr "op_type" "RS,RSY")
3794 (set_attr "cpu_facility" "*,longdisp")
3795 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3798 ; extv instruction patterns
3801 ; FIXME: This expander needs to be converted from DI to GPR as well
3802 ; after resolving some issues with it.
3804 (define_expand "extzv"
3806 [(set (match_operand:DI 0 "register_operand" "=d")
3808 (match_operand:DI 1 "register_operand" "d")
3809 (match_operand 2 "const_int_operand" "") ; size
3810 (match_operand 3 "const_int_operand" ""))) ; start
3811 (clobber (reg:CC CC_REGNUM))])]
3814 if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
3816 /* Starting with zEC12 there is risbgn not clobbering CC. */
3819 emit_move_insn (operands[0],
3820 gen_rtx_ZERO_EXTRACT (DImode,
3828 (define_insn "*extzv<mode><clobbercc_or_nocc>"
3829 [(set (match_operand:GPR 0 "register_operand" "=d")
3831 (match_operand:GPR 1 "register_operand" "d")
3832 (match_operand 2 "const_int_operand" "") ; size
3833 (match_operand 3 "const_int_operand" ""))) ; start
3835 "<z10_or_zEC12_cond>
3836 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
3837 GET_MODE_BITSIZE (<MODE>mode))"
3838 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
3839 [(set_attr "op_type" "RIE")
3840 (set_attr "z10prop" "z10_super_E1")])
3842 ; 64 bit: (a & -16) | ((b >> 8) & 15)
3843 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
3844 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
3845 (match_operand 1 "const_int_operand" "") ; size
3846 (match_operand 2 "const_int_operand" "")) ; start
3847 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
3848 (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
3849 "<z10_or_zEC12_cond>
3850 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
3851 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
3852 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
3853 [(set_attr "op_type" "RIE")
3854 (set_attr "z10prop" "z10_super_E1")])
3856 ; 32 bit: (a & -16) | ((b >> 8) & 15)
3857 (define_insn "*<risbg_n>_ior_and_sr_ze"
3858 [(set (match_operand:SI 0 "register_operand" "=d")
3860 (match_operand:SI 1 "register_operand" "0")
3861 (match_operand:SI 2 "const_int_operand" ""))
3864 (match_operand:DI 3 "register_operand" "d")
3865 (match_operand 4 "const_int_operand" "") ; size
3866 (match_operand 5 "const_int_operand" "")) ; start
3868 "<z10_or_zEC12_cond>
3869 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
3870 && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
3871 "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
3872 [(set_attr "op_type" "RIE")
3873 (set_attr "z10prop" "z10_super_E1")])
3875 ; ((int)foo >> 10) & 1;
3876 (define_insn "*extract1bitdi<clobbercc_or_nocc>"
3877 [(set (match_operand:DI 0 "register_operand" "=d")
3878 (ne:DI (zero_extract:DI
3879 (match_operand:DI 1 "register_operand" "d")
3880 (const_int 1) ; size
3881 (match_operand 2 "const_int_operand" "")) ; start
3883 "<z10_or_zEC12_cond>
3884 && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
3885 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
3886 [(set_attr "op_type" "RIE")
3887 (set_attr "z10prop" "z10_super_E1")])
3889 (define_insn "*<risbg_n>_and_subregdi_rotr"
3890 [(set (match_operand:DI 0 "register_operand" "=d")
3892 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3893 (match_operand:SINT 2 "const_int_operand" "")) 0)
3894 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3895 "<z10_or_zEC12_cond>
3896 && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
3897 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
3898 [(set_attr "op_type" "RIE")
3899 (set_attr "z10prop" "z10_super_E1")])
3901 (define_insn "*<risbg_n>_and_subregdi_rotl"
3902 [(set (match_operand:DI 0 "register_operand" "=d")
3904 (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
3905 (match_operand:SINT 2 "const_int_operand" "")) 0)
3906 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3907 "<z10_or_zEC12_cond>
3908 && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
3909 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3910 [(set_attr "op_type" "RIE")
3911 (set_attr "z10prop" "z10_super_E1")])
3913 (define_insn "*<risbg_n>_di_and_rot"
3914 [(set (match_operand:DI 0 "register_operand" "=d")
3915 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
3916 (match_operand:DI 2 "const_int_operand" ""))
3917 (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
3918 "<z10_or_zEC12_cond>"
3919 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
3920 [(set_attr "op_type" "RIE")
3921 (set_attr "z10prop" "z10_super_E1")])
3923 (define_insn_and_split "*pre_z10_extzv<mode>"
3924 [(set (match_operand:GPR 0 "register_operand" "=d")
3925 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
3926 (match_operand 2 "nonzero_shift_count_operand" "")
3928 (clobber (reg:CC CC_REGNUM))]
3931 "&& reload_completed"
3933 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3934 (clobber (reg:CC CC_REGNUM))])
3935 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3937 int bitsize = INTVAL (operands[2]);
3938 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3939 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3941 operands[1] = adjust_address (operands[1], BLKmode, 0);
3942 set_mem_size (operands[1], size);
3943 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3944 operands[3] = GEN_INT (mask);
3947 (define_insn_and_split "*pre_z10_extv<mode>"
3948 [(set (match_operand:GPR 0 "register_operand" "=d")
3949 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
3950 (match_operand 2 "nonzero_shift_count_operand" "")
3952 (clobber (reg:CC CC_REGNUM))]
3955 "&& reload_completed"
3957 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3958 (clobber (reg:CC CC_REGNUM))])
3960 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3961 (clobber (reg:CC CC_REGNUM))])]
3963 int bitsize = INTVAL (operands[2]);
3964 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3965 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3967 operands[1] = adjust_address (operands[1], BLKmode, 0);
3968 set_mem_size (operands[1], size);
3969 operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
3970 operands[3] = GEN_INT (mask);
3974 ; insv instruction patterns
3977 (define_expand "insv"
3978 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3979 (match_operand 1 "const_int_operand" "")
3980 (match_operand 2 "const_int_operand" ""))
3981 (match_operand 3 "general_operand" ""))]
3984 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3990 ; The normal RTL expansion will never generate a zero_extract where
3991 ; the location operand isn't word mode. However, we do this in the
3992 ; back-end when generating atomic operations. See s390_two_part_insv.
3993 (define_insn "*insv<mode><clobbercc_or_nocc>"
3994 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3995 (match_operand 1 "const_int_operand" "I") ; size
3996 (match_operand 2 "const_int_operand" "I")) ; pos
3997 (match_operand:GPR 3 "nonimmediate_operand" "d"))]
3998 "<z10_or_zEC12_cond>
3999 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
4000 GET_MODE_BITSIZE (<MODE>mode))
4001 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
4002 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
4003 [(set_attr "op_type" "RIE")
4004 (set_attr "z10prop" "z10_super_E1")])
4006 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
4007 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
4008 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
4009 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
4010 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
4011 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4012 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
4013 (match_operand:GPR 4 "const_int_operand" ""))))]
4014 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4016 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
4017 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
4018 [(set_attr "op_type" "RIE")
4019 (set_attr "z10prop" "z10_super_E1")])
4021 (define_insn "*insv_z10_noshift_cc"
4022 [(set (reg CC_REGNUM)
4025 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
4026 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4027 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
4028 (match_operand:DI 4 "const_int_operand" "")))
4030 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
4031 (ior:DI (and:DI (match_dup 1) (match_dup 2))
4032 (and:DI (match_dup 3) (match_dup 4))))]
4033 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4034 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4036 risbg\t%0,%1,%s2,%e2,0
4037 risbg\t%0,%3,%s4,%e4,0"
4038 [(set_attr "op_type" "RIE")
4039 (set_attr "z10prop" "z10_super_E1")])
4041 (define_insn "*insv_z10_noshift_cconly"
4046 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
4047 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4048 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
4049 (match_operand:DI 4 "const_int_operand" "")))
4051 (clobber (match_scratch:DI 0 "=d,d"))]
4052 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
4053 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
4055 risbg\t%0,%1,%s2,%e2,0
4056 risbg\t%0,%3,%s4,%e4,0"
4057 [(set_attr "op_type" "RIE")
4058 (set_attr "z10prop" "z10_super_E1")])
4060 ; Implement appending Y on the left of S bits of X
4061 ; x = (y << s) | (x & ((1 << s) - 1))
4062 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
4063 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4064 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
4065 (match_operand:GPR 2 "immediate_operand" ""))
4066 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
4067 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4068 "<z10_or_zEC12_cond>
4069 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
4070 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
4071 [(set_attr "op_type" "RIE")
4072 (set_attr "z10prop" "z10_super_E1")])
4074 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
4075 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
4076 [(set (match_operand:GPR 0 "register_operand" "=d")
4078 (match_operand:GPR 1 "register_operand" "0")
4079 (match_operand:GPR 2 "const_int_operand" ""))
4081 (match_operand:GPR 3 "register_operand" "d")
4082 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4083 "<z10_or_zEC12_cond> && UINTVAL (operands[2])
4084 == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
4085 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
4086 [(set_attr "op_type" "RIE")
4087 (set_attr "z10prop" "z10_super_E1")])
4089 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
4090 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
4091 [(set (match_operand:SI 0 "register_operand" "=d")
4093 (match_operand:SI 1 "register_operand" "0")
4094 (match_operand:SI 2 "const_int_operand" ""))
4097 (match_operand:DI 3 "register_operand" "d")
4098 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
4099 "<z10_or_zEC12_cond>
4100 && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
4101 "<risbg_n>\t%0,%3,%4,63,64-%4"
4102 [(set_attr "op_type" "RIE")
4103 (set_attr "z10prop" "z10_super_E1")])
4105 ; (ui32)(((ui64)x) >> 12) & -4
4106 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
4107 [(set (match_operand:SI 0 "register_operand" "=d")
4109 (subreg:SI (lshiftrt:DI
4110 (match_operand:DI 1 "register_operand" "d")
4111 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
4112 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
4113 "<z10_or_zEC12_cond>"
4114 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
4115 [(set_attr "op_type" "RIE")
4116 (set_attr "z10prop" "z10_super_E1")])
4118 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
4119 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
4120 ; -> z = y >> d; z = risbg;
4123 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4124 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4125 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4126 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4127 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
4128 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4130 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4132 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4133 (ashift:GPR (match_dup 3) (match_dup 4))))]
4135 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4136 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4138 if (!can_create_pseudo_p ())
4140 operands[6] = gen_reg_rtx (<MODE>mode);
4143 operands[6] = operands[0];
4148 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
4149 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
4150 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4151 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
4152 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
4153 (clobber (reg:CC CC_REGNUM))])]
4154 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
4156 (lshiftrt:GPR (match_dup 1) (match_dup 2)))
4159 (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
4160 (ashift:GPR (match_dup 3) (match_dup 4))))
4161 (clobber (reg:CC CC_REGNUM))])]
4163 operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
4164 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4166 if (!can_create_pseudo_p ())
4168 operands[6] = gen_reg_rtx (<MODE>mode);
4171 operands[6] = operands[0];
4175 (define_insn "*r<noxa>sbg_<mode>_noshift"
4176 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4178 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
4179 (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
4180 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4181 (clobber (reg:CC CC_REGNUM))]
4183 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
4184 [(set_attr "op_type" "RIE")])
4187 (define_insn "*r<noxa>sbg_di_rotl"
4188 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4192 (match_operand:DI 1 "nonimmediate_operand" "d")
4193 (match_operand:DI 3 "const_int_operand" ""))
4194 (match_operand:DI 2 "contiguous_bitmask_operand" ""))
4195 (match_operand:DI 4 "nonimmediate_operand" "0")))
4196 (clobber (reg:CC CC_REGNUM))]
4198 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
4199 [(set_attr "op_type" "RIE")])
4202 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
4203 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4207 (match_operand:GPR 1 "nonimmediate_operand" "d")
4208 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4209 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4210 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4211 (clobber (reg:CC CC_REGNUM))]
4213 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
4214 INTVAL (operands[2]))"
4215 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
4216 [(set_attr "op_type" "RIE")])
4219 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
4220 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4224 (match_operand:GPR 1 "nonimmediate_operand" "d")
4225 (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
4226 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
4227 (match_operand:GPR 4 "nonimmediate_operand" "0")))
4228 (clobber (reg:CC CC_REGNUM))]
4230 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
4231 INTVAL (operands[2]))"
4232 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
4233 [(set_attr "op_type" "RIE")])
4235 ;; unsigned {int,long} a, b
4236 ;; a = a | (b << const_int)
4237 ;; a = a ^ (b << const_int)
4239 (define_insn "*r<noxa>sbg_<mode>_sll"
4240 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4243 (match_operand:GPR 1 "nonimmediate_operand" "d")
4244 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4245 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4246 (clobber (reg:CC CC_REGNUM))]
4248 "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
4249 [(set_attr "op_type" "RIE")])
4251 ;; unsigned {int,long} a, b
4252 ;; a = a | (b >> const_int)
4253 ;; a = a ^ (b >> const_int)
4255 (define_insn "*r<noxa>sbg_<mode>_srl"
4256 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
4259 (match_operand:GPR 1 "nonimmediate_operand" "d")
4260 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
4261 (match_operand:GPR 3 "nonimmediate_operand" "0")))
4262 (clobber (reg:CC CC_REGNUM))]
4264 "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
4265 [(set_attr "op_type" "RIE")])
4267 ;; These two are generated by combine for s.bf &= val.
4268 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
4269 ;; shifts and ands, which results in some truly awful patterns
4270 ;; including subregs of operations. Rather unnecessisarily, IMO.
4273 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4274 ;; (const_int 24 [0x18])
4275 ;; (const_int 0 [0]))
4276 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
4277 ;; (const_int 40 [0x28])) 4)
4278 ;; (reg:SI 4 %r4 [ y+4 ])) 0))
4280 ;; we should instead generate
4282 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
4283 ;; (const_int 24 [0x18])
4284 ;; (const_int 0 [0]))
4285 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
4286 ;; (const_int 40 [0x28]))
4287 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
4289 ;; by noticing that we can push down the outer paradoxical subreg
4290 ;; into the operation.
4292 (define_insn "*insv_rnsbg_noshift"
4293 [(set (zero_extract:DI
4294 (match_operand:DI 0 "nonimmediate_operand" "+d")
4295 (match_operand 1 "const_int_operand" "")
4296 (match_operand 2 "const_int_operand" ""))
4299 (match_operand:DI 3 "nonimmediate_operand" "d")))
4300 (clobber (reg:CC CC_REGNUM))]
4302 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4303 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
4304 "rnsbg\t%0,%3,%2,63,0"
4305 [(set_attr "op_type" "RIE")])
4307 (define_insn "*insv_rnsbg_srl"
4308 [(set (zero_extract:DI
4309 (match_operand:DI 0 "nonimmediate_operand" "+d")
4310 (match_operand 1 "const_int_operand" "")
4311 (match_operand 2 "const_int_operand" ""))
4315 (match_operand 3 "const_int_operand" ""))
4316 (match_operand:DI 4 "nonimmediate_operand" "d")))
4317 (clobber (reg:CC CC_REGNUM))]
4319 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
4320 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
4321 "rnsbg\t%0,%4,%2,%2+%1-1,%3"
4322 [(set_attr "op_type" "RIE")])
4324 (define_insn "*insv<mode>_mem_reg"
4325 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
4326 (match_operand 1 "const_int_operand" "n,n")
4328 (match_operand:W 2 "register_operand" "d,d"))]
4329 "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4330 && INTVAL (operands[1]) > 0
4331 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4332 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4334 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4336 operands[1] = GEN_INT ((1ul << size) - 1);
4337 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
4338 : "stcmy\t%2,%1,%S0";
4340 [(set_attr "op_type" "RS,RSY")
4341 (set_attr "cpu_facility" "*,longdisp")
4342 (set_attr "z10prop" "z10_super,z10_super")])
4344 (define_insn "*insvdi_mem_reghigh"
4345 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
4346 (match_operand 1 "const_int_operand" "n")
4348 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
4351 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
4352 && INTVAL (operands[1]) > 0
4353 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
4354 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
4356 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
4358 operands[1] = GEN_INT ((1ul << size) - 1);
4359 return "stcmh\t%2,%1,%S0";
4361 [(set_attr "op_type" "RSY")
4362 (set_attr "z10prop" "z10_super")])
4364 (define_insn "*insvdi_reg_imm"
4365 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4367 (match_operand 1 "const_int_operand" "n"))
4368 (match_operand:DI 2 "const_int_operand" "n"))]
4370 && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
4371 && INTVAL (operands[1]) >= 0
4372 && INTVAL (operands[1]) < BITS_PER_WORD
4373 && INTVAL (operands[1]) % 16 == 0"
4375 switch (BITS_PER_WORD - INTVAL (operands[1]))
4377 case 64: return "iihh\t%0,%x2"; break;
4378 case 48: return "iihl\t%0,%x2"; break;
4379 case 32: return "iilh\t%0,%x2"; break;
4380 case 16: return "iill\t%0,%x2"; break;
4381 default: gcc_unreachable();
4384 [(set_attr "op_type" "RI")
4385 (set_attr "z10prop" "z10_super_E1")])
4387 ; Update the left-most 32 bit of a DI.
4388 (define_insn "*insv_h_di_reg_extimm"
4389 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4392 (match_operand:DI 1 "const_int_operand" "n"))]
4395 [(set_attr "op_type" "RIL")
4396 (set_attr "z10prop" "z10_fwd_E1")])
4398 ; Update the right-most 32 bit of a DI.
4399 (define_insn "*insv_l_di_reg_extimm"
4400 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
4403 (match_operand:DI 1 "const_int_operand" "n"))]
4406 [(set_attr "op_type" "RIL")
4407 (set_attr "z10prop" "z10_fwd_A1")])
4410 ; extendsidi2 instruction pattern(s).
4413 (define_expand "extendsidi2"
4414 [(set (match_operand:DI 0 "register_operand" "")
4415 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4420 emit_clobber (operands[0]);
4421 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
4422 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
4423 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
4428 (define_insn "*extendsidi2"
4429 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4430 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4436 [(set_attr "op_type" "RRE,RXY,RIL")
4437 (set_attr "type" "*,*,larl")
4438 (set_attr "cpu_facility" "*,*,z10")
4439 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4442 ; extend(hi|qi)(si|di)2 instruction pattern(s).
4445 (define_expand "extend<HQI:mode><DSI:mode>2"
4446 [(set (match_operand:DSI 0 "register_operand" "")
4447 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4450 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
4452 rtx tmp = gen_reg_rtx (SImode);
4453 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
4454 emit_insn (gen_extendsidi2 (operands[0], tmp));
4457 else if (!TARGET_EXTIMM)
4459 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
4461 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
4462 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
4463 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
4469 ; extendhidi2 instruction pattern(s).
4472 (define_insn "*extendhidi2_extimm"
4473 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4474 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
4475 "TARGET_ZARCH && TARGET_EXTIMM"
4480 [(set_attr "op_type" "RRE,RXY,RIL")
4481 (set_attr "type" "*,*,larl")
4482 (set_attr "cpu_facility" "extimm,extimm,z10")
4483 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4485 (define_insn "*extendhidi2"
4486 [(set (match_operand:DI 0 "register_operand" "=d")
4487 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
4490 [(set_attr "op_type" "RXY")
4491 (set_attr "z10prop" "z10_super_E1")])
4494 ; extendhisi2 instruction pattern(s).
4497 (define_insn "*extendhisi2_extimm"
4498 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4499 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
4506 [(set_attr "op_type" "RRE,RX,RXY,RIL")
4507 (set_attr "type" "*,*,*,larl")
4508 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
4509 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
4511 (define_insn "*extendhisi2"
4512 [(set (match_operand:SI 0 "register_operand" "=d,d")
4513 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
4518 [(set_attr "op_type" "RX,RXY")
4519 (set_attr "cpu_facility" "*,longdisp")
4520 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4523 ; extendqi(si|di)2 instruction pattern(s).
4526 ; lbr, lgbr, lb, lgb
4527 (define_insn "*extendqi<mode>2_extimm"
4528 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4529 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
4534 [(set_attr "op_type" "RRE,RXY")
4535 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4538 (define_insn "*extendqi<mode>2"
4539 [(set (match_operand:GPR 0 "register_operand" "=d")
4540 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
4541 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
4543 [(set_attr "op_type" "RXY")
4544 (set_attr "z10prop" "z10_super_E1")])
4546 (define_insn_and_split "*extendqi<mode>2_short_displ"
4547 [(set (match_operand:GPR 0 "register_operand" "=d")
4548 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
4549 (clobber (reg:CC CC_REGNUM))]
4550 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
4552 "&& reload_completed"
4554 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
4555 (clobber (reg:CC CC_REGNUM))])
4557 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
4558 (clobber (reg:CC CC_REGNUM))])]
4560 operands[1] = adjust_address (operands[1], BLKmode, 0);
4561 set_mem_size (operands[1], GET_MODE_SIZE (QImode));
4562 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
4566 ; zero_extendsidi2 instruction pattern(s).
4569 (define_expand "zero_extendsidi2"
4570 [(set (match_operand:DI 0 "register_operand" "")
4571 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
4576 emit_clobber (operands[0]);
4577 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
4578 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
4583 (define_insn "*zero_extendsidi2"
4584 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4585 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
4591 [(set_attr "op_type" "RRE,RXY,RIL")
4592 (set_attr "type" "*,*,larl")
4593 (set_attr "cpu_facility" "*,*,z10")
4594 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
4597 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
4600 (define_insn "*llgt_sidi"
4601 [(set (match_operand:DI 0 "register_operand" "=d")
4602 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4603 (const_int 2147483647)))]
4606 [(set_attr "op_type" "RXE")
4607 (set_attr "z10prop" "z10_super_E1")])
4609 (define_insn_and_split "*llgt_sidi_split"
4610 [(set (match_operand:DI 0 "register_operand" "=d")
4611 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
4612 (const_int 2147483647)))
4613 (clobber (reg:CC CC_REGNUM))]
4616 "&& reload_completed"
4618 (and:DI (subreg:DI (match_dup 1) 0)
4619 (const_int 2147483647)))]
4622 (define_insn "*llgt_sisi"
4623 [(set (match_operand:SI 0 "register_operand" "=d,d")
4624 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
4625 (const_int 2147483647)))]
4630 [(set_attr "op_type" "RRE,RXE")
4631 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4633 (define_insn "*llgt_didi"
4634 [(set (match_operand:DI 0 "register_operand" "=d,d")
4635 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
4636 (const_int 2147483647)))]
4641 [(set_attr "op_type" "RRE,RXE")
4642 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4645 [(set (match_operand:DSI 0 "register_operand" "")
4646 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
4647 (const_int 2147483647)))
4648 (clobber (reg:CC CC_REGNUM))]
4649 "TARGET_ZARCH && reload_completed"
4651 (and:DSI (match_dup 1)
4652 (const_int 2147483647)))]
4656 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
4659 (define_expand "zero_extend<mode>di2"
4660 [(set (match_operand:DI 0 "register_operand" "")
4661 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4666 rtx tmp = gen_reg_rtx (SImode);
4667 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
4668 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
4671 else if (!TARGET_EXTIMM)
4673 rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
4674 operands[1] = gen_lowpart (DImode, operands[1]);
4675 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
4676 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
4681 (define_expand "zero_extend<mode>si2"
4682 [(set (match_operand:SI 0 "register_operand" "")
4683 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
4688 operands[1] = gen_lowpart (SImode, operands[1]);
4689 emit_insn (gen_andsi3 (operands[0], operands[1],
4690 GEN_INT ((1 << <HQI:bitsize>) - 1)));
4696 (define_insn "*zero_extendhi<mode>2_z10"
4697 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4698 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
4704 [(set_attr "op_type" "RXY,RRE,RIL")
4705 (set_attr "type" "*,*,larl")
4706 (set_attr "cpu_facility" "*,*,z10")
4707 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
4709 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
4710 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
4711 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4712 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
4717 [(set_attr "op_type" "RRE,RXY")
4718 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
4721 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
4722 [(set (match_operand:GPR 0 "register_operand" "=d")
4723 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
4724 "TARGET_ZARCH && !TARGET_EXTIMM"
4726 [(set_attr "op_type" "RXY")
4727 (set_attr "z10prop" "z10_fwd_A3")])
4729 (define_insn_and_split "*zero_extendhisi2_31"
4730 [(set (match_operand:SI 0 "register_operand" "=&d")
4731 (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
4732 (clobber (reg:CC CC_REGNUM))]
4735 "&& reload_completed"
4736 [(set (match_dup 0) (const_int 0))
4738 [(set (strict_low_part (match_dup 2)) (match_dup 1))
4739 (clobber (reg:CC CC_REGNUM))])]
4740 "operands[2] = gen_lowpart (HImode, operands[0]);")
4742 (define_insn_and_split "*zero_extendqisi2_31"
4743 [(set (match_operand:SI 0 "register_operand" "=&d")
4744 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
4747 "&& reload_completed"
4748 [(set (match_dup 0) (const_int 0))
4749 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4750 "operands[2] = gen_lowpart (QImode, operands[0]);")
4753 ; zero_extendqihi2 instruction pattern(s).
4756 (define_expand "zero_extendqihi2"
4757 [(set (match_operand:HI 0 "register_operand" "")
4758 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
4759 "TARGET_ZARCH && !TARGET_EXTIMM"
4761 operands[1] = gen_lowpart (HImode, operands[1]);
4762 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
4766 (define_insn "*zero_extendqihi2_64"
4767 [(set (match_operand:HI 0 "register_operand" "=d")
4768 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4769 "TARGET_ZARCH && !TARGET_EXTIMM"
4771 [(set_attr "op_type" "RXY")
4772 (set_attr "z10prop" "z10_fwd_A3")])
4774 (define_insn_and_split "*zero_extendqihi2_31"
4775 [(set (match_operand:HI 0 "register_operand" "=&d")
4776 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
4779 "&& reload_completed"
4780 [(set (match_dup 0) (const_int 0))
4781 (set (strict_low_part (match_dup 2)) (match_dup 1))]
4782 "operands[2] = gen_lowpart (QImode, operands[0]);")
4785 ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander
4788 ; This is the only entry point for fixuns_trunc. It multiplexes the
4789 ; expansion to either the *_emu expanders below for pre z196 machines
4790 ; or emits the default pattern otherwise.
4791 (define_expand "fixuns_trunc<FP:mode><GPR:mode>2"
4793 [(set (match_operand:GPR 0 "register_operand" "")
4794 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "")))
4795 (unspec:GPR [(match_dup 2)] UNSPEC_ROUND)
4796 (clobber (reg:CC CC_REGNUM))])]
4801 /* We don't provide emulation for TD|DD->SI. */
4802 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT
4803 && <GPR:MODE>mode == SImode)
4805 emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0],
4810 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT)
4811 operands[2] = GEN_INT (DFP_RND_TOWARD_0);
4813 operands[2] = GEN_INT (BFP_RND_TOWARD_0);
4816 ; (sf|df|tf)->unsigned (si|di)
4818 ; Emulate the unsigned conversion with the signed version for pre z196
4820 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu"
4822 [(set (match_operand:GPR 0 "register_operand" "")
4823 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
4824 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
4825 (clobber (reg:CC CC_REGNUM))])]
4826 "!TARGET_Z196 && TARGET_HARD_FLOAT"
4828 rtx_code_label *label1 = gen_label_rtx ();
4829 rtx_code_label *label2 = gen_label_rtx ();
4830 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
4831 REAL_VALUE_TYPE cmp, sub;
4833 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
4834 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
4835 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
4837 emit_cmp_and_jump_insns (operands[1],
4838 const_double_from_real_value (cmp, <BFP:MODE>mode),
4839 LT, NULL_RTX, VOIDmode, 0, label1);
4840 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
4841 const_double_from_real_value (sub, <BFP:MODE>mode)));
4842 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
4843 GEN_INT (BFP_RND_TOWARD_MINF)));
4846 emit_label (label1);
4847 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
4849 GEN_INT (BFP_RND_TOWARD_0)));
4850 emit_label (label2);
4856 ; Emulate the unsigned conversion with the signed version for pre z196
4858 (define_expand "fixuns_truncdddi2_emu"
4860 [(set (match_operand:DI 0 "register_operand" "")
4861 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
4862 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4863 (clobber (reg:CC CC_REGNUM))])]
4865 "!TARGET_Z196 && TARGET_HARD_DFP"
4867 rtx_code_label *label1 = gen_label_rtx ();
4868 rtx_code_label *label2 = gen_label_rtx ();
4869 rtx temp = gen_reg_rtx (TDmode);
4870 REAL_VALUE_TYPE cmp, sub;
4872 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4873 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4875 /* 2^63 can't be represented as 64bit DFP number with full precision. The
4876 solution is doing the check and the subtraction in TD mode and using a
4877 TD -> DI convert afterwards. */
4878 emit_insn (gen_extendddtd2 (temp, operands[1]));
4879 temp = force_reg (TDmode, temp);
4880 emit_cmp_and_jump_insns (temp,
4881 const_double_from_real_value (cmp, TDmode),
4882 LT, NULL_RTX, VOIDmode, 0, label1);
4883 emit_insn (gen_subtd3 (temp, temp,
4884 const_double_from_real_value (sub, TDmode)));
4885 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4886 GEN_INT (DFP_RND_TOWARD_MINF)));
4889 emit_label (label1);
4890 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
4891 GEN_INT (DFP_RND_TOWARD_0)));
4892 emit_label (label2);
4898 ; Emulate the unsigned conversion with the signed version for pre z196
4900 (define_expand "fixuns_trunctddi2_emu"
4902 [(set (match_operand:DI 0 "register_operand" "")
4903 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
4904 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4905 (clobber (reg:CC CC_REGNUM))])]
4907 "!TARGET_Z196 && TARGET_HARD_DFP"
4909 rtx_code_label *label1 = gen_label_rtx ();
4910 rtx_code_label *label2 = gen_label_rtx ();
4911 rtx temp = gen_reg_rtx (TDmode);
4912 REAL_VALUE_TYPE cmp, sub;
4914 operands[1] = force_reg (TDmode, operands[1]);
4915 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
4916 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
4918 emit_cmp_and_jump_insns (operands[1],
4919 const_double_from_real_value (cmp, TDmode),
4920 LT, NULL_RTX, VOIDmode, 0, label1);
4921 emit_insn (gen_subtd3 (temp, operands[1],
4922 const_double_from_real_value (sub, TDmode)));
4923 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
4924 GEN_INT (DFP_RND_TOWARD_MINF)));
4927 emit_label (label1);
4928 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
4929 GEN_INT (DFP_RND_TOWARD_0)));
4930 emit_label (label2);
4934 ; Just a dummy to make the code in the first expander a bit easier.
4935 (define_expand "fixuns_trunc<mode>si2_emu"
4937 [(set (match_operand:SI 0 "register_operand" "")
4938 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
4939 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
4940 (clobber (reg:CC CC_REGNUM))])]
4942 "!TARGET_Z196 && TARGET_HARD_DFP"
4948 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
4951 (define_insn "*fixuns_truncdfdi2_vx"
4952 [(set (match_operand:DI 0 "register_operand" "=d,v")
4953 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4954 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4955 (clobber (reg:CC CC_REGNUM))]
4956 "TARGET_VX && TARGET_HARD_FLOAT"
4959 wclgdb\t%v0,%v1,0,%h2"
4960 [(set_attr "op_type" "RRF,VRR")
4961 (set_attr "type" "ftoi")])
4963 ; (dd|td|sf|df|tf)->unsigned (di|si)
4964 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
4965 ; clfdtr, clfxtr, clgdtr, clgxtr
4966 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
4967 [(set (match_operand:GPR 0 "register_operand" "=d")
4968 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
4969 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
4970 (clobber (reg:CC CC_REGNUM))]
4971 "TARGET_Z196 && TARGET_HARD_FLOAT
4972 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
4973 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
4974 [(set_attr "op_type" "RRF")
4975 (set_attr "type" "ftoi")])
4977 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
4978 [(set (match_operand:GPR 0 "register_operand" "")
4979 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
4982 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
4983 GEN_INT (BFP_RND_TOWARD_0)));
4987 (define_insn "*fix_truncdfdi2_bfp_z13"
4988 [(set (match_operand:DI 0 "register_operand" "=d,v")
4989 (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
4990 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
4991 (clobber (reg:CC CC_REGNUM))]
4992 "TARGET_VX && TARGET_HARD_FLOAT"
4995 wcgdb\t%v0,%v1,0,%h2"
4996 [(set_attr "op_type" "RRE,VRR")
4997 (set_attr "type" "ftoi")])
4999 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
5000 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
5001 [(set (match_operand:GPR 0 "register_operand" "=d")
5002 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
5003 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
5004 (clobber (reg:CC CC_REGNUM))]
5006 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
5007 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
5008 [(set_attr "op_type" "RRE")
5009 (set_attr "type" "ftoi")])
5011 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
5013 [(set (match_operand:GPR 0 "register_operand" "=d")
5014 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
5015 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
5016 (clobber (reg:CC CC_REGNUM))])]
5017 "TARGET_HARD_FLOAT")
5019 ; fix_trunc(td|dd)di2 instruction pattern(s).
5022 (define_expand "fix_trunc<mode>di2"
5023 [(set (match_operand:DI 0 "register_operand" "")
5024 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
5025 "TARGET_ZARCH && TARGET_HARD_DFP"
5027 operands[1] = force_reg (<MODE>mode, operands[1]);
5028 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
5029 GEN_INT (DFP_RND_TOWARD_0)));
5034 (define_insn "fix_trunc<DFP:mode>di2_dfp"
5035 [(set (match_operand:DI 0 "register_operand" "=d")
5036 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
5037 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
5038 (clobber (reg:CC CC_REGNUM))]
5039 "TARGET_ZARCH && TARGET_HARD_DFP"
5040 "cg<DFP:xde>tr\t%0,%h2,%1"
5041 [(set_attr "op_type" "RRF")
5042 (set_attr "type" "ftoidfp")])
5046 ; fix_trunctf(si|di)2 instruction pattern(s).
5049 (define_expand "fix_trunctf<mode>2"
5050 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
5051 (fix:GPR (match_operand:TF 1 "register_operand" "")))
5052 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
5053 (clobber (reg:CC CC_REGNUM))])]
5059 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5062 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
5063 (define_insn "floatdi<mode>2"
5064 [(set (match_operand:FP 0 "register_operand" "=f,v")
5065 (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
5066 "TARGET_ZARCH && TARGET_HARD_FLOAT"
5070 [(set_attr "op_type" "RRE,VRR")
5071 (set_attr "type" "itof<mode>" )
5072 (set_attr "cpu_facility" "*,vx")
5073 (set_attr "enabled" "*,<DFDI>")])
5075 ; cxfbr, cdfbr, cefbr
5076 (define_insn "floatsi<mode>2"
5077 [(set (match_operand:BFP 0 "register_operand" "=f")
5078 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
5081 [(set_attr "op_type" "RRE")
5082 (set_attr "type" "itof<mode>" )])
5085 (define_insn "floatsi<mode>2"
5086 [(set (match_operand:DFP 0 "register_operand" "=f")
5087 (float:DFP (match_operand:SI 1 "register_operand" "d")))]
5088 "TARGET_Z196 && TARGET_HARD_FLOAT"
5089 "c<xde>ftr\t%0,0,%1,0"
5090 [(set_attr "op_type" "RRE")
5091 (set_attr "type" "itof<mode>" )])
5094 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
5097 (define_insn "*floatunsdidf2_z13"
5098 [(set (match_operand:DF 0 "register_operand" "=f,v")
5099 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
5100 "TARGET_VX && TARGET_HARD_FLOAT"
5103 wcdlgb\t%v0,%v1,0,0"
5104 [(set_attr "op_type" "RRE,VRR")
5105 (set_attr "type" "itofdf")])
5107 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
5108 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
5109 (define_insn "*floatuns<GPR:mode><FP:mode>2"
5110 [(set (match_operand:FP 0 "register_operand" "=f")
5111 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
5112 "TARGET_Z196 && TARGET_HARD_FLOAT
5113 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
5114 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
5115 [(set_attr "op_type" "RRE")
5116 (set_attr "type" "itof<FP:mode>")])
5118 (define_expand "floatuns<GPR:mode><FP:mode>2"
5119 [(set (match_operand:FP 0 "register_operand" "")
5120 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
5121 "TARGET_Z196 && TARGET_HARD_FLOAT")
5124 ; truncdfsf2 instruction pattern(s).
5127 (define_insn "truncdfsf2"
5128 [(set (match_operand:SF 0 "register_operand" "=f,v")
5129 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
5133 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
5134 ; According to BFP rounding mode
5135 [(set_attr "op_type" "RRE,VRR")
5136 (set_attr "type" "ftruncdf")
5137 (set_attr "cpu_facility" "*,vx")])
5140 ; trunctf(df|sf)2 instruction pattern(s).
5144 (define_insn "trunctf<mode>2"
5145 [(set (match_operand:DSF 0 "register_operand" "=f")
5146 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
5147 (clobber (match_scratch:TF 2 "=f"))]
5149 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
5150 [(set_attr "length" "6")
5151 (set_attr "type" "ftrunctf")])
5154 ; trunctddd2 and truncddsd2 instruction pattern(s).
5158 (define_expand "trunctddd2"
5160 [(set (match_operand:DD 0 "register_operand" "")
5161 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5162 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
5163 (clobber (scratch:TD))])]
5166 (define_insn "*trunctddd2"
5167 [(set (match_operand:DD 0 "register_operand" "=f")
5168 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
5169 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
5170 (clobber (match_scratch:TD 3 "=f"))]
5172 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
5173 [(set_attr "length" "6")
5174 (set_attr "type" "ftruncdd")])
5176 (define_insn "truncddsd2"
5177 [(set (match_operand:SD 0 "register_operand" "=f")
5178 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
5181 [(set_attr "op_type" "RRF")
5182 (set_attr "type" "ftruncsd")])
5184 (define_expand "trunctdsd2"
5187 (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
5188 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
5189 (clobber (match_scratch:TD 3 ""))])
5190 (set (match_operand:SD 0 "register_operand" "")
5191 (float_truncate:SD (match_dup 2)))]
5194 operands[2] = gen_reg_rtx (DDmode);
5198 ; extend(sf|df)(df|tf)2 instruction pattern(s).
5202 (define_insn "*extendsfdf2_z13"
5203 [(set (match_operand:DF 0 "register_operand" "=f,f,v")
5204 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
5205 "TARGET_VX && TARGET_HARD_FLOAT"
5210 [(set_attr "op_type" "RRE,RXE,VRR")
5211 (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
5213 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
5214 (define_insn "*extend<DSF:mode><BFP:mode>2"
5215 [(set (match_operand:BFP 0 "register_operand" "=f,f")
5216 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
5218 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
5219 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
5221 l<BFP:xde><DSF:xde>br\t%0,%1
5222 l<BFP:xde><DSF:xde>b\t%0,%1"
5223 [(set_attr "op_type" "RRE,RXE")
5224 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
5226 (define_expand "extend<DSF:mode><BFP:mode>2"
5227 [(set (match_operand:BFP 0 "register_operand" "")
5228 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
5230 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
5233 ; extendddtd2 and extendsddd2 instruction pattern(s).
5236 (define_insn "extendddtd2"
5237 [(set (match_operand:TD 0 "register_operand" "=f")
5238 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
5241 [(set_attr "op_type" "RRF")
5242 (set_attr "type" "fsimptf")])
5244 (define_insn "extendsddd2"
5245 [(set (match_operand:DD 0 "register_operand" "=f")
5246 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
5249 [(set_attr "op_type" "RRF")
5250 (set_attr "type" "fsimptf")])
5252 (define_expand "extendsdtd2"
5254 (float_extend:DD (match_operand:SD 1 "register_operand" "")))
5255 (set (match_operand:TD 0 "register_operand" "")
5256 (float_extend:TD (match_dup 2)))]
5259 operands[2] = gen_reg_rtx (DDmode);
5262 ; Binary Floating Point - load fp integer
5264 ; Expanders for: floor, btrunc, round, ceil, and nearbyint
5265 ; For all of them the inexact exceptions are suppressed.
5267 ; fiebra, fidbra, fixbra
5268 (define_insn "<FPINT:fpint_name><BFP:mode>2"
5269 [(set (match_operand:BFP 0 "register_operand" "=f")
5270 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5273 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4"
5274 [(set_attr "op_type" "RRF")
5275 (set_attr "type" "fsimp<BFP:mode>")])
5277 ; rint is supposed to raise an inexact exception so we can use the
5278 ; older instructions.
5280 ; fiebr, fidbr, fixbr
5281 (define_insn "rint<BFP:mode>2"
5282 [(set (match_operand:BFP 0 "register_operand" "=f")
5283 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")]
5284 UNSPEC_FPINT_RINT))]
5286 "fi<BFP:xde>br\t%0,0,%1"
5287 [(set_attr "op_type" "RRF")
5288 (set_attr "type" "fsimp<BFP:mode>")])
5291 ; Decimal Floating Point - load fp integer
5294 (define_insn "<FPINT:fpint_name><DFP:mode>2"
5295 [(set (match_operand:DFP 0 "register_operand" "=f")
5296 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5299 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4"
5300 [(set_attr "op_type" "RRF")
5301 (set_attr "type" "fsimp<DFP:mode>")])
5304 (define_insn "rint<DFP:mode>2"
5305 [(set (match_operand:DFP 0 "register_operand" "=f")
5306 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")]
5307 UNSPEC_FPINT_RINT))]
5309 "fi<DFP:xde>tr\t%0,0,%1,0"
5310 [(set_attr "op_type" "RRF")
5311 (set_attr "type" "fsimp<DFP:mode>")])
5314 ; Binary <-> Decimal floating point trunc patterns
5317 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
5318 [(set (reg:DFP_ALL FPR0_REGNUM)
5319 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5320 (use (reg:SI GPR0_REGNUM))
5321 (clobber (reg:CC CC_REGNUM))
5322 (clobber (reg:SI GPR1_REGNUM))]
5326 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
5327 [(set (reg:BFP FPR0_REGNUM)
5328 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5329 (use (reg:SI GPR0_REGNUM))
5330 (clobber (reg:CC CC_REGNUM))
5331 (clobber (reg:SI GPR1_REGNUM))]
5335 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
5336 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5337 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5339 [(set (reg:DFP_ALL FPR0_REGNUM)
5340 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
5341 (use (reg:SI GPR0_REGNUM))
5342 (clobber (reg:CC CC_REGNUM))
5343 (clobber (reg:SI GPR1_REGNUM))])
5344 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5345 (reg:DFP_ALL FPR0_REGNUM))]
5347 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5349 HOST_WIDE_INT flags;
5351 flags = (PFPO_CONVERT |
5352 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5353 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5355 operands[2] = GEN_INT (flags);
5358 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
5359 [(set (reg:DFP_ALL FPR4_REGNUM)
5360 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5361 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5363 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
5364 (use (reg:SI GPR0_REGNUM))
5365 (clobber (reg:CC CC_REGNUM))
5366 (clobber (reg:SI GPR1_REGNUM))])
5367 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5369 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
5371 HOST_WIDE_INT flags;
5373 flags = (PFPO_CONVERT |
5374 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5375 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5377 operands[2] = GEN_INT (flags);
5381 ; Binary <-> Decimal floating point extend patterns
5384 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
5385 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5386 (use (reg:SI GPR0_REGNUM))
5387 (clobber (reg:CC CC_REGNUM))
5388 (clobber (reg:SI GPR1_REGNUM))]
5392 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
5393 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5394 (use (reg:SI GPR0_REGNUM))
5395 (clobber (reg:CC CC_REGNUM))
5396 (clobber (reg:SI GPR1_REGNUM))]
5400 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
5401 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
5402 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5404 [(set (reg:DFP_ALL FPR0_REGNUM)
5405 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
5406 (use (reg:SI GPR0_REGNUM))
5407 (clobber (reg:CC CC_REGNUM))
5408 (clobber (reg:SI GPR1_REGNUM))])
5409 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
5410 (reg:DFP_ALL FPR0_REGNUM))]
5412 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
5414 HOST_WIDE_INT flags;
5416 flags = (PFPO_CONVERT |
5417 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
5418 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
5420 operands[2] = GEN_INT (flags);
5423 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
5424 [(set (reg:DFP_ALL FPR4_REGNUM)
5425 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
5426 (set (reg:SI GPR0_REGNUM) (match_dup 2))
5428 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
5429 (use (reg:SI GPR0_REGNUM))
5430 (clobber (reg:CC CC_REGNUM))
5431 (clobber (reg:SI GPR1_REGNUM))])
5432 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
5434 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
5436 HOST_WIDE_INT flags;
5438 flags = (PFPO_CONVERT |
5439 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
5440 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
5442 operands[2] = GEN_INT (flags);
5447 ;; ARITHMETIC OPERATIONS
5449 ; arithmetic operations set the ConditionCode,
5450 ; because of unpredictable Bits in Register for Halfword and Byte
5451 ; the ConditionCode can be set wrong in operations for Halfword and Byte
5454 ;;- Add instructions.
5458 ; addti3 instruction pattern(s).
5461 (define_expand "addti3"
5463 [(set (match_operand:TI 0 "register_operand" "")
5464 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5465 (match_operand:TI 2 "general_operand" "") ) )
5466 (clobber (reg:CC CC_REGNUM))])]
5469 /* For z13 we have vaq which doesn't set CC. */
5472 emit_insn (gen_rtx_SET (operands[0],
5473 gen_rtx_PLUS (TImode,
5474 copy_to_mode_reg (TImode, operands[1]),
5475 copy_to_mode_reg (TImode, operands[2]))));
5480 (define_insn_and_split "*addti3"
5481 [(set (match_operand:TI 0 "register_operand" "=&d")
5482 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
5483 (match_operand:TI 2 "general_operand" "do") ) )
5484 (clobber (reg:CC CC_REGNUM))]
5487 "&& reload_completed"
5489 [(set (reg:CCL1 CC_REGNUM)
5490 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
5492 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
5494 [(set (match_dup 3) (plus:DI
5495 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
5496 (match_dup 4)) (match_dup 5)))
5497 (clobber (reg:CC CC_REGNUM))])]
5498 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
5499 operands[4] = operand_subword (operands[1], 0, 0, TImode);
5500 operands[5] = operand_subword (operands[2], 0, 0, TImode);
5501 operands[6] = operand_subword (operands[0], 1, 0, TImode);
5502 operands[7] = operand_subword (operands[1], 1, 0, TImode);
5503 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
5504 [(set_attr "op_type" "*")
5505 (set_attr "cpu_facility" "*")])
5508 ; adddi3 instruction pattern(s).
5511 (define_expand "adddi3"
5513 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5514 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5515 (match_operand:DI 2 "general_operand" "")))
5516 (clobber (reg:CC CC_REGNUM))])]
5520 (define_insn "*adddi3_sign"
5521 [(set (match_operand:DI 0 "register_operand" "=d,d")
5522 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5523 (match_operand:DI 1 "register_operand" "0,0")))
5524 (clobber (reg:CC CC_REGNUM))]
5529 [(set_attr "op_type" "RRE,RXY")
5530 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5532 (define_insn "*adddi3_zero_cc"
5533 [(set (reg CC_REGNUM)
5534 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5535 (match_operand:DI 1 "register_operand" "0,0"))
5537 (set (match_operand:DI 0 "register_operand" "=d,d")
5538 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
5539 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5543 [(set_attr "op_type" "RRE,RXY")
5544 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5546 (define_insn "*adddi3_zero_cconly"
5547 [(set (reg CC_REGNUM)
5548 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5549 (match_operand:DI 1 "register_operand" "0,0"))
5551 (clobber (match_scratch:DI 0 "=d,d"))]
5552 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
5556 [(set_attr "op_type" "RRE,RXY")
5557 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5559 (define_insn "*adddi3_zero"
5560 [(set (match_operand:DI 0 "register_operand" "=d,d")
5561 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
5562 (match_operand:DI 1 "register_operand" "0,0")))
5563 (clobber (reg:CC CC_REGNUM))]
5568 [(set_attr "op_type" "RRE,RXY")
5569 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5571 (define_insn_and_split "*adddi3_31z"
5572 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5573 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5574 (match_operand:DI 2 "general_operand" "do") ) )
5575 (clobber (reg:CC CC_REGNUM))]
5576 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
5578 "&& reload_completed"
5580 [(set (reg:CCL1 CC_REGNUM)
5581 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5583 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5585 [(set (match_dup 3) (plus:SI
5586 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
5587 (match_dup 4)) (match_dup 5)))
5588 (clobber (reg:CC CC_REGNUM))])]
5589 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5590 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5591 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5592 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5593 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5594 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
5596 (define_insn_and_split "*adddi3_31"
5597 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
5598 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5599 (match_operand:DI 2 "general_operand" "do") ) )
5600 (clobber (reg:CC CC_REGNUM))]
5603 "&& reload_completed"
5605 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
5606 (clobber (reg:CC CC_REGNUM))])
5608 [(set (reg:CCL1 CC_REGNUM)
5609 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
5611 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
5613 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
5615 (label_ref (match_dup 9))))
5617 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
5618 (clobber (reg:CC CC_REGNUM))])
5620 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
5621 operands[4] = operand_subword (operands[1], 0, 0, DImode);
5622 operands[5] = operand_subword (operands[2], 0, 0, DImode);
5623 operands[6] = operand_subword (operands[0], 1, 0, DImode);
5624 operands[7] = operand_subword (operands[1], 1, 0, DImode);
5625 operands[8] = operand_subword (operands[2], 1, 0, DImode);
5626 operands[9] = gen_label_rtx ();")
5629 ; addsi3 instruction pattern(s).
5632 (define_expand "addsi3"
5634 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5635 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5636 (match_operand:SI 2 "general_operand" "")))
5637 (clobber (reg:CC CC_REGNUM))])]
5641 (define_insn "*addsi3_sign"
5642 [(set (match_operand:SI 0 "register_operand" "=d,d")
5643 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5644 (match_operand:SI 1 "register_operand" "0,0")))
5645 (clobber (reg:CC CC_REGNUM))]
5650 [(set_attr "op_type" "RX,RXY")
5651 (set_attr "cpu_facility" "*,longdisp")
5652 (set_attr "z196prop" "z196_cracked,z196_cracked")])
5655 ; add(di|si)3 instruction pattern(s).
5658 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
5659 (define_insn "*add<mode>3"
5660 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
5661 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
5662 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
5663 (clobber (reg:CC CC_REGNUM))]
5675 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
5676 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
5677 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
5678 z10_super_E1,z10_super_E1,z10_super_E1")])
5680 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
5681 (define_insn "*add<mode>3_carry1_cc"
5682 [(set (reg CC_REGNUM)
5683 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5684 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5686 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
5687 (plus:GPR (match_dup 1) (match_dup 2)))]
5688 "s390_match_ccmode (insn, CCL1mode)"
5694 al<g>hsik\t%0,%1,%h2
5698 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5699 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5700 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5701 z10_super_E1,z10_super_E1,z10_super_E1")])
5703 ; alr, al, aly, algr, alg, alrk, algrk
5704 (define_insn "*add<mode>3_carry1_cconly"
5705 [(set (reg CC_REGNUM)
5706 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5707 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5709 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5710 "s390_match_ccmode (insn, CCL1mode)"
5716 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5717 (set_attr "cpu_facility" "*,z196,*,longdisp")
5718 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5720 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5721 (define_insn "*add<mode>3_carry2_cc"
5722 [(set (reg CC_REGNUM)
5723 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5724 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5726 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5727 (plus:GPR (match_dup 1) (match_dup 2)))]
5728 "s390_match_ccmode (insn, CCL1mode)"
5734 al<g>hsik\t%0,%1,%h2
5738 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5739 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5740 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
5741 z10_super_E1,z10_super_E1,z10_super_E1")])
5743 ; alr, al, aly, algr, alg, alrk, algrk
5744 (define_insn "*add<mode>3_carry2_cconly"
5745 [(set (reg CC_REGNUM)
5746 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5747 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5749 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5750 "s390_match_ccmode (insn, CCL1mode)"
5756 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5757 (set_attr "cpu_facility" "*,z196,*,longdisp")
5758 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5760 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
5761 (define_insn "*add<mode>3_cc"
5762 [(set (reg CC_REGNUM)
5763 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
5764 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
5766 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
5767 (plus:GPR (match_dup 1) (match_dup 2)))]
5768 "s390_match_ccmode (insn, CCLmode)"
5774 al<g>hsik\t%0,%1,%h2
5778 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
5779 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
5780 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
5781 *,z10_super_E1,z10_super_E1,z10_super_E1")])
5783 ; alr, al, aly, algr, alg, alrk, algrk
5784 (define_insn "*add<mode>3_cconly"
5785 [(set (reg CC_REGNUM)
5786 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5787 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
5789 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5790 "s390_match_ccmode (insn, CCLmode)"
5796 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5797 (set_attr "cpu_facility" "*,z196,*,longdisp")
5798 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5800 ; alr, al, aly, algr, alg, alrk, algrk
5801 (define_insn "*add<mode>3_cconly2"
5802 [(set (reg CC_REGNUM)
5803 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
5804 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
5805 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
5806 "s390_match_ccmode(insn, CCLmode)"
5812 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
5813 (set_attr "cpu_facility" "*,z196,*,longdisp")
5814 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5816 ; ahi, afi, aghi, agfi, asi, agsi
5817 (define_insn "*add<mode>3_imm_cc"
5818 [(set (reg CC_REGNUM)
5819 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
5820 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
5822 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
5823 (plus:GPR (match_dup 1) (match_dup 2)))]
5824 "s390_match_ccmode (insn, CCAmode)
5825 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
5826 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
5827 /* Avoid INT32_MIN on 32 bit. */
5828 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
5834 [(set_attr "op_type" "RI,RIE,RIL,SIY")
5835 (set_attr "cpu_facility" "*,z196,extimm,z10")
5836 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
5838 (define_insn "*adddi3_sign"
5839 [(set (match_operand:DI 0 "register_operand" "=d")
5840 (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
5841 (match_operand:DI 1 "register_operand" "0")))
5842 (clobber (reg:CC CC_REGNUM))]
5845 [(set_attr "op_type" "RXY")])
5848 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
5851 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5852 ; FIXME: wfadb does not clobber cc
5853 (define_insn "add<mode>3"
5854 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
5855 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
5856 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
5857 (clobber (reg:CC CC_REGNUM))]
5865 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
5866 (set_attr "type" "fsimp<mode>")
5867 (set_attr "cpu_facility" "*,*,*,vx,vxe")
5868 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
5870 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5871 (define_insn "*add<mode>3_cc"
5872 [(set (reg CC_REGNUM)
5873 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5874 (match_operand:FP 2 "general_operand" "f,f,R"))
5875 (match_operand:FP 3 "const0_operand" "")))
5876 (set (match_operand:FP 0 "register_operand" "=f,f,f")
5877 (plus:FP (match_dup 1) (match_dup 2)))]
5878 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5883 [(set_attr "op_type" "RRF,RRE,RXE")
5884 (set_attr "type" "fsimp<mode>")
5885 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5887 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
5888 (define_insn "*add<mode>3_cconly"
5889 [(set (reg CC_REGNUM)
5890 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
5891 (match_operand:FP 2 "general_operand" "f,f,R"))
5892 (match_operand:FP 3 "const0_operand" "")))
5893 (clobber (match_scratch:FP 0 "=f,f,f"))]
5894 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
5899 [(set_attr "op_type" "RRF,RRE,RXE")
5900 (set_attr "type" "fsimp<mode>")
5901 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
5904 ; Pointer add instruction patterns
5907 ; This will match "*la_64"
5908 (define_expand "addptrdi3"
5909 [(set (match_operand:DI 0 "register_operand" "")
5910 (plus:DI (match_operand:DI 1 "register_operand" "")
5911 (match_operand:DI 2 "nonmemory_operand" "")))]
5914 if (GET_CODE (operands[2]) == CONST_INT)
5916 HOST_WIDE_INT c = INTVAL (operands[2]);
5918 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5919 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5921 operands[2] = force_const_mem (DImode, operands[2]);
5922 operands[2] = force_reg (DImode, operands[2]);
5924 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5925 operands[2] = force_reg (DImode, operands[2]);
5929 ; For 31 bit we have to prevent the generated pattern from matching
5930 ; normal ADDs since la only does a 31 bit add. This is supposed to
5931 ; match "force_la_31".
5932 (define_expand "addptrsi3"
5934 [(set (match_operand:SI 0 "register_operand" "")
5935 (plus:SI (match_operand:SI 1 "register_operand" "")
5936 (match_operand:SI 2 "nonmemory_operand" "")))
5937 (use (const_int 0))])]
5940 if (GET_CODE (operands[2]) == CONST_INT)
5942 HOST_WIDE_INT c = INTVAL (operands[2]);
5944 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K")
5945 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os"))
5947 operands[2] = force_const_mem (SImode, operands[2]);
5948 operands[2] = force_reg (SImode, operands[2]);
5950 else if (!DISP_IN_RANGE (INTVAL (operands[2])))
5951 operands[2] = force_reg (SImode, operands[2]);
5956 ;;- Subtract instructions.
5960 ; subti3 instruction pattern(s).
5963 (define_expand "subti3"
5965 [(set (match_operand:TI 0 "register_operand" "")
5966 (minus:TI (match_operand:TI 1 "register_operand" "")
5967 (match_operand:TI 2 "general_operand" "") ) )
5968 (clobber (reg:CC CC_REGNUM))])]
5971 /* For z13 we have vsq which doesn't set CC. */
5974 emit_insn (gen_rtx_SET (operands[0],
5975 gen_rtx_MINUS (TImode,
5977 copy_to_mode_reg (TImode, operands[2]))));
5982 (define_insn_and_split "*subti3"
5983 [(set (match_operand:TI 0 "register_operand" "=&d")
5984 (minus:TI (match_operand:TI 1 "register_operand" "0")
5985 (match_operand:TI 2 "general_operand" "do") ) )
5986 (clobber (reg:CC CC_REGNUM))]
5989 "&& reload_completed"
5991 [(set (reg:CCL2 CC_REGNUM)
5992 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
5994 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
5996 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
5997 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
5998 (clobber (reg:CC CC_REGNUM))])]
5999 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
6000 operands[4] = operand_subword (operands[1], 0, 0, TImode);
6001 operands[5] = operand_subword (operands[2], 0, 0, TImode);
6002 operands[6] = operand_subword (operands[0], 1, 0, TImode);
6003 operands[7] = operand_subword (operands[1], 1, 0, TImode);
6004 operands[8] = operand_subword (operands[2], 1, 0, TImode);"
6005 [(set_attr "op_type" "*")
6006 (set_attr "cpu_facility" "*")])
6009 ; subdi3 instruction pattern(s).
6012 (define_expand "subdi3"
6014 [(set (match_operand:DI 0 "register_operand" "")
6015 (minus:DI (match_operand:DI 1 "register_operand" "")
6016 (match_operand:DI 2 "general_operand" "")))
6017 (clobber (reg:CC CC_REGNUM))])]
6021 (define_insn "*subdi3_sign"
6022 [(set (match_operand:DI 0 "register_operand" "=d,d")
6023 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6024 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
6025 (clobber (reg:CC CC_REGNUM))]
6030 [(set_attr "op_type" "RRE,RXY")
6031 (set_attr "z10prop" "z10_c,*")
6032 (set_attr "z196prop" "z196_cracked")])
6034 (define_insn "*subdi3_zero_cc"
6035 [(set (reg CC_REGNUM)
6036 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6037 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
6039 (set (match_operand:DI 0 "register_operand" "=d,d")
6040 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
6041 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
6045 [(set_attr "op_type" "RRE,RXY")
6046 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6048 (define_insn "*subdi3_zero_cconly"
6049 [(set (reg CC_REGNUM)
6050 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6051 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
6053 (clobber (match_scratch:DI 0 "=d,d"))]
6054 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
6058 [(set_attr "op_type" "RRE,RXY")
6059 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6061 (define_insn "*subdi3_zero"
6062 [(set (match_operand:DI 0 "register_operand" "=d,d")
6063 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
6064 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
6065 (clobber (reg:CC CC_REGNUM))]
6070 [(set_attr "op_type" "RRE,RXY")
6071 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
6073 (define_insn_and_split "*subdi3_31z"
6074 [(set (match_operand:DI 0 "register_operand" "=&d")
6075 (minus:DI (match_operand:DI 1 "register_operand" "0")
6076 (match_operand:DI 2 "general_operand" "do") ) )
6077 (clobber (reg:CC CC_REGNUM))]
6078 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
6080 "&& reload_completed"
6082 [(set (reg:CCL2 CC_REGNUM)
6083 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6085 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6087 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
6088 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
6089 (clobber (reg:CC CC_REGNUM))])]
6090 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6091 operands[4] = operand_subword (operands[1], 0, 0, DImode);
6092 operands[5] = operand_subword (operands[2], 0, 0, DImode);
6093 operands[6] = operand_subword (operands[0], 1, 0, DImode);
6094 operands[7] = operand_subword (operands[1], 1, 0, DImode);
6095 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
6097 (define_insn_and_split "*subdi3_31"
6098 [(set (match_operand:DI 0 "register_operand" "=&d")
6099 (minus:DI (match_operand:DI 1 "register_operand" "0")
6100 (match_operand:DI 2 "general_operand" "do") ) )
6101 (clobber (reg:CC CC_REGNUM))]
6104 "&& reload_completed"
6106 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
6107 (clobber (reg:CC CC_REGNUM))])
6109 [(set (reg:CCL2 CC_REGNUM)
6110 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
6112 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
6114 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
6116 (label_ref (match_dup 9))))
6118 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
6119 (clobber (reg:CC CC_REGNUM))])
6121 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
6122 operands[4] = operand_subword (operands[1], 0, 0, DImode);
6123 operands[5] = operand_subword (operands[2], 0, 0, DImode);
6124 operands[6] = operand_subword (operands[0], 1, 0, DImode);
6125 operands[7] = operand_subword (operands[1], 1, 0, DImode);
6126 operands[8] = operand_subword (operands[2], 1, 0, DImode);
6127 operands[9] = gen_label_rtx ();")
6130 ; subsi3 instruction pattern(s).
6133 (define_expand "subsi3"
6135 [(set (match_operand:SI 0 "register_operand" "")
6136 (minus:SI (match_operand:SI 1 "register_operand" "")
6137 (match_operand:SI 2 "general_operand" "")))
6138 (clobber (reg:CC CC_REGNUM))])]
6142 (define_insn "*subsi3_sign"
6143 [(set (match_operand:SI 0 "register_operand" "=d,d")
6144 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6145 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
6146 (clobber (reg:CC CC_REGNUM))]
6151 [(set_attr "op_type" "RX,RXY")
6152 (set_attr "cpu_facility" "*,longdisp")
6153 (set_attr "z196prop" "z196_cracked,z196_cracked")])
6156 ; sub(di|si)3 instruction pattern(s).
6159 ; sr, s, sy, sgr, sg, srk, sgrk
6160 (define_insn "*sub<mode>3"
6161 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6162 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6163 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
6164 (clobber (reg:CC CC_REGNUM))]
6171 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6172 (set_attr "cpu_facility" "*,z196,*,longdisp")
6173 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6175 ; slr, sl, sly, slgr, slg, slrk, slgrk
6176 (define_insn "*sub<mode>3_borrow_cc"
6177 [(set (reg CC_REGNUM)
6178 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6179 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6181 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6182 (minus:GPR (match_dup 1) (match_dup 2)))]
6183 "s390_match_ccmode (insn, CCL2mode)"
6189 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6190 (set_attr "cpu_facility" "*,z196,*,longdisp")
6191 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6193 ; slr, sl, sly, slgr, slg, slrk, slgrk
6194 (define_insn "*sub<mode>3_borrow_cconly"
6195 [(set (reg CC_REGNUM)
6196 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6197 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6199 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6200 "s390_match_ccmode (insn, CCL2mode)"
6206 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6207 (set_attr "cpu_facility" "*,z196,*,longdisp")
6208 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6210 ; slr, sl, sly, slgr, slg, slrk, slgrk
6211 (define_insn "*sub<mode>3_cc"
6212 [(set (reg CC_REGNUM)
6213 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6214 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6216 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6217 (minus:GPR (match_dup 1) (match_dup 2)))]
6218 "s390_match_ccmode (insn, CCLmode)"
6224 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6225 (set_attr "cpu_facility" "*,z196,*,longdisp")
6226 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6228 ; slr, sl, sly, slgr, slg, slrk, slgrk
6229 (define_insn "*sub<mode>3_cc2"
6230 [(set (reg CC_REGNUM)
6231 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6232 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6233 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
6234 (minus:GPR (match_dup 1) (match_dup 2)))]
6235 "s390_match_ccmode (insn, CCL3mode)"
6241 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6242 (set_attr "cpu_facility" "*,z196,*,longdisp")
6243 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6245 ; slr, sl, sly, slgr, slg, slrk, slgrk
6246 (define_insn "*sub<mode>3_cconly"
6247 [(set (reg CC_REGNUM)
6248 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
6249 (match_operand:GPR 2 "general_operand" "d,d,R,T"))
6251 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6252 "s390_match_ccmode (insn, CCLmode)"
6258 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6259 (set_attr "cpu_facility" "*,z196,*,longdisp")
6260 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6263 ; slr, sl, sly, slgr, slg, slrk, slgrk
6264 (define_insn "*sub<mode>3_cconly2"
6265 [(set (reg CC_REGNUM)
6266 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
6267 (match_operand:GPR 2 "general_operand" "d,d,R,T")))
6268 (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
6269 "s390_match_ccmode (insn, CCL3mode)"
6275 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
6276 (set_attr "cpu_facility" "*,z196,*,longdisp")
6277 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
6279 (define_insn "*subdi3_sign"
6280 [(set (match_operand:DI 0 "register_operand" "=d")
6281 (minus:DI (match_operand:DI 1 "register_operand" "0")
6282 (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))))
6283 (clobber (reg:CC CC_REGNUM))]
6286 [(set_attr "op_type" "RXY")])
6290 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
6293 ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why?
6294 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6295 (define_insn "sub<mode>3"
6296 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
6297 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
6298 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
6299 (clobber (reg:CC CC_REGNUM))]
6307 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
6308 (set_attr "type" "fsimp<mode>")
6309 (set_attr "cpu_facility" "*,*,*,vx,vxe")
6310 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
6312 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6313 (define_insn "*sub<mode>3_cc"
6314 [(set (reg CC_REGNUM)
6315 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6316 (match_operand:FP 2 "general_operand" "f,f,R"))
6317 (match_operand:FP 3 "const0_operand" "")))
6318 (set (match_operand:FP 0 "register_operand" "=f,f,f")
6319 (minus:FP (match_dup 1) (match_dup 2)))]
6320 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6325 [(set_attr "op_type" "RRF,RRE,RXE")
6326 (set_attr "type" "fsimp<mode>")
6327 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6329 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
6330 (define_insn "*sub<mode>3_cconly"
6331 [(set (reg CC_REGNUM)
6332 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
6333 (match_operand:FP 2 "general_operand" "f,f,R"))
6334 (match_operand:FP 3 "const0_operand" "")))
6335 (clobber (match_scratch:FP 0 "=f,f,f"))]
6336 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6341 [(set_attr "op_type" "RRF,RRE,RXE")
6342 (set_attr "type" "fsimp<mode>")
6343 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
6347 ;;- Conditional add/subtract instructions.
6351 ; add(di|si)cc instruction pattern(s).
6354 ; the following 4 patterns are used when the result of an add with
6355 ; carry is checked for an overflow condition
6357 ; op1 + op2 + c < op1
6359 ; alcr, alc, alcgr, alcg
6360 (define_insn "*add<mode>3_alc_carry1_cc"
6361 [(set (reg CC_REGNUM)
6363 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6364 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6365 (match_operand:GPR 2 "general_operand" "d,T"))
6367 (set (match_operand:GPR 0 "register_operand" "=d,d")
6368 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6369 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6373 [(set_attr "op_type" "RRE,RXY")
6374 (set_attr "z196prop" "z196_alone,z196_alone")])
6376 ; alcr, alc, alcgr, alcg
6377 (define_insn "*add<mode>3_alc_carry1_cconly"
6378 [(set (reg CC_REGNUM)
6380 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6381 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6382 (match_operand:GPR 2 "general_operand" "d,T"))
6384 (clobber (match_scratch:GPR 0 "=d,d"))]
6385 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6389 [(set_attr "op_type" "RRE,RXY")
6390 (set_attr "z196prop" "z196_alone,z196_alone")])
6392 ; op1 + op2 + c < op2
6394 ; alcr, alc, alcgr, alcg
6395 (define_insn "*add<mode>3_alc_carry2_cc"
6396 [(set (reg CC_REGNUM)
6398 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6399 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6400 (match_operand:GPR 2 "general_operand" "d,T"))
6402 (set (match_operand:GPR 0 "register_operand" "=d,d")
6403 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6404 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6408 [(set_attr "op_type" "RRE,RXY")])
6410 ; alcr, alc, alcgr, alcg
6411 (define_insn "*add<mode>3_alc_carry2_cconly"
6412 [(set (reg CC_REGNUM)
6414 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6415 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6416 (match_operand:GPR 2 "general_operand" "d,T"))
6418 (clobber (match_scratch:GPR 0 "=d,d"))]
6419 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
6423 [(set_attr "op_type" "RRE,RXY")])
6425 ; alcr, alc, alcgr, alcg
6426 (define_insn "*add<mode>3_alc_cc"
6427 [(set (reg CC_REGNUM)
6429 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6430 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6431 (match_operand:GPR 2 "general_operand" "d,T"))
6433 (set (match_operand:GPR 0 "register_operand" "=d,d")
6434 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
6435 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6439 [(set_attr "op_type" "RRE,RXY")])
6441 ; alcr, alc, alcgr, alcg
6442 (define_insn "*add<mode>3_alc"
6443 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6444 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
6445 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
6446 (match_operand:GPR 2 "general_operand" "d,T")))
6447 (clobber (reg:CC CC_REGNUM))]
6452 [(set_attr "op_type" "RRE,RXY")])
6454 ; slbr, slb, slbgr, slbg
6455 (define_insn "*sub<mode>3_slb_cc"
6456 [(set (reg CC_REGNUM)
6458 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6459 (match_operand:GPR 2 "general_operand" "d,T"))
6460 (match_operand:GPR 3 "s390_slb_comparison" ""))
6462 (set (match_operand:GPR 0 "register_operand" "=d,d")
6463 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
6464 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
6468 [(set_attr "op_type" "RRE,RXY")
6469 (set_attr "z10prop" "z10_c,*")])
6471 ; slbr, slb, slbgr, slbg
6472 (define_insn "*sub<mode>3_slb"
6473 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6474 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
6475 (match_operand:GPR 2 "general_operand" "d,T"))
6476 (match_operand:GPR 3 "s390_slb_comparison" "")))
6477 (clobber (reg:CC CC_REGNUM))]
6482 [(set_attr "op_type" "RRE,RXY")
6483 (set_attr "z10prop" "z10_c,*")])
6485 (define_expand "add<mode>cc"
6486 [(match_operand:GPR 0 "register_operand" "")
6487 (match_operand 1 "comparison_operator" "")
6488 (match_operand:GPR 2 "register_operand" "")
6489 (match_operand:GPR 3 "const_int_operand" "")]
6491 "if (!s390_expand_addcc (GET_CODE (operands[1]),
6492 XEXP (operands[1], 0), XEXP (operands[1], 1),
6493 operands[0], operands[2],
6494 operands[3])) FAIL; DONE;")
6497 ; scond instruction pattern(s).
6500 (define_insn_and_split "*scond<mode>"
6501 [(set (match_operand:GPR 0 "register_operand" "=&d")
6502 (match_operand:GPR 1 "s390_alc_comparison" ""))
6503 (clobber (reg:CC CC_REGNUM))]
6506 "&& reload_completed"
6507 [(set (match_dup 0) (const_int 0))
6509 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
6511 (clobber (reg:CC CC_REGNUM))])]
6514 (define_insn_and_split "*scond<mode>_neg"
6515 [(set (match_operand:GPR 0 "register_operand" "=&d")
6516 (match_operand:GPR 1 "s390_slb_comparison" ""))
6517 (clobber (reg:CC CC_REGNUM))]
6520 "&& reload_completed"
6521 [(set (match_dup 0) (const_int 0))
6523 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
6525 (clobber (reg:CC CC_REGNUM))])
6527 [(set (match_dup 0) (neg:GPR (match_dup 0)))
6528 (clobber (reg:CC CC_REGNUM))])]
6532 (define_expand "cstore<mode>4"
6533 [(set (match_operand:SI 0 "register_operand" "")
6534 (match_operator:SI 1 "s390_scond_operator"
6535 [(match_operand:GPR 2 "register_operand" "")
6536 (match_operand:GPR 3 "general_operand" "")]))]
6538 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
6539 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
6541 (define_expand "cstorecc4"
6543 [(set (match_operand:SI 0 "register_operand" "")
6544 (match_operator:SI 1 "s390_eqne_operator"
6545 [(match_operand 2 "cc_reg_operand")
6546 (match_operand 3 "const0_operand")]))
6547 (clobber (reg:CC CC_REGNUM))])]
6549 "machine_mode mode = GET_MODE (operands[2]);
6554 if (GET_CODE (operands[1]) == NE)
6555 cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx);
6557 cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx);
6558 ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx);
6559 emit_insn (gen_rtx_SET (operands[0], ite));
6563 if (mode != CCZ1mode)
6565 emit_insn (gen_sne (operands[0], operands[2]));
6566 if (GET_CODE (operands[1]) == EQ)
6567 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
6571 (define_insn_and_split "sne"
6572 [(set (match_operand:SI 0 "register_operand" "=d")
6573 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
6575 (clobber (reg:CC CC_REGNUM))]
6580 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
6581 (clobber (reg:CC CC_REGNUM))])])
6585 ;; - Conditional move instructions (introduced with z196)
6588 (define_expand "mov<mode>cc"
6589 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
6590 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6591 (match_operand:GPR 2 "nonimmediate_operand" "")
6592 (match_operand:GPR 3 "nonimmediate_operand" "")))]
6595 /* Emit the comparison insn in case we do not already have a comparison result. */
6596 if (!s390_comparison (operands[1], VOIDmode))
6597 operands[1] = s390_emit_compare (GET_CODE (operands[1]),
6598 XEXP (operands[1], 0),
6599 XEXP (operands[1], 1));
6602 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
6603 (define_insn "*mov<mode>cc"
6604 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S")
6606 (match_operator 1 "s390_comparison"
6607 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c")
6608 (match_operand 5 "const_int_operand" "")])
6609 (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0")
6610 (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))]
6621 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
6622 (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")])
6625 ;;- Multiply instructions.
6629 ; muldi3 instruction pattern(s).
6632 (define_expand "muldi3"
6634 [(set (match_operand:DI 0 "register_operand")
6635 (mult:DI (match_operand:DI 1 "nonimmediate_operand")
6636 (match_operand:DI 2 "general_operand")))
6637 (clobber (reg:CC CC_REGNUM))])]
6640 (define_insn "*muldi3_sign"
6641 [(set (match_operand:DI 0 "register_operand" "=d,d")
6642 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
6643 (match_operand:DI 1 "register_operand" "0,0")))]
6648 [(set_attr "op_type" "RRE,RXY")
6649 (set_attr "type" "imuldi")])
6651 (define_insn "*muldi3"
6652 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
6653 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0")
6654 (match_operand:DI 2 "general_operand" "d,d,K,T,Os")))
6655 (clobber (match_scratch:CC 3 "=X,c,X,X,X"))]
6663 [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL")
6664 (set_attr "type" "imuldi")
6665 (set_attr "cpu_facility" "*,arch12,*,*,z10")])
6667 (define_insn "mulditi3"
6668 [(set (match_operand:TI 0 "register_operand" "=d,d")
6669 (mult:TI (sign_extend:TI
6670 (match_operand:DI 1 "register_operand" "%d,0"))
6672 (match_operand:DI 2 "nonimmediate_operand" " d,T"))))]
6677 [(set_attr "op_type" "RRF,RXY")])
6679 ; Combine likes op1 and op2 to be swapped sometimes.
6680 (define_insn "mulditi3_2"
6681 [(set (match_operand:TI 0 "register_operand" "=d,d")
6682 (mult:TI (sign_extend:TI
6683 (match_operand:DI 1 "nonimmediate_operand" "%d,T"))
6685 (match_operand:DI 2 "register_operand" " d,0"))))]
6690 [(set_attr "op_type" "RRF,RXY")])
6692 (define_insn "*muldi3_sign"
6693 [(set (match_operand:DI 0 "register_operand" "=d")
6694 (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
6695 (match_operand:DI 1 "register_operand" "0")))]
6698 [(set_attr "op_type" "RXY")])
6702 ; mulsi3 instruction pattern(s).
6705 (define_expand "mulsi3"
6707 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
6708 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6709 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
6710 (clobber (reg:CC CC_REGNUM))])]
6713 (define_insn "*mulsi3_sign"
6714 [(set (match_operand:SI 0 "register_operand" "=d,d")
6715 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
6716 (match_operand:SI 1 "register_operand" "0,0")))]
6721 [(set_attr "op_type" "RX,RXY")
6722 (set_attr "type" "imulhi")
6723 (set_attr "cpu_facility" "*,z10")])
6725 (define_insn "*mulsi3"
6726 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
6727 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
6728 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
6729 (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))]
6738 [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL")
6739 (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi")
6740 (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")])
6743 ; mulsidi3 instruction pattern(s).
6746 (define_insn "mulsidi3"
6747 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
6748 (mult:DI (sign_extend:DI
6749 (match_operand:SI 1 "register_operand" "%0,0,0"))
6751 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
6757 [(set_attr "op_type" "RR,RX,RXY")
6758 (set_attr "type" "imulsi")
6759 (set_attr "cpu_facility" "*,*,z10")])
6762 ; umul instruction pattern(s).
6765 ; mlr, ml, mlgr, mlg
6766 (define_insn "umul<dwh><mode>3"
6767 [(set (match_operand:DW 0 "register_operand" "=d,d")
6768 (mult:DW (zero_extend:DW
6769 (match_operand:<DWH> 1 "register_operand" "%0,0"))
6771 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
6776 [(set_attr "op_type" "RRE,RXY")
6777 (set_attr "type" "imul<dwh>")])
6780 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
6783 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
6784 (define_insn "mul<mode>3"
6785 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
6786 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
6787 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
6795 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
6796 (set_attr "type" "fmul<mode>")
6797 (set_attr "cpu_facility" "*,*,*,vx,vxe")
6798 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
6800 ; madbr, maebr, maxb, madb, maeb
6801 (define_insn "fma<mode>4"
6802 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
6803 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
6804 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
6805 (match_operand:DSF 3 "register_operand" "0,0,v,v")))]
6810 wfmadb\t%v0,%v1,%v2,%v3
6811 wfmasb\t%v0,%v1,%v2,%v3"
6812 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
6813 (set_attr "type" "fmadd<mode>")
6814 (set_attr "cpu_facility" "*,*,vx,vxe")
6815 (set_attr "enabled" "*,*,<DF>,<SF>")])
6817 ; msxbr, msdbr, msebr, msxb, msdb, mseb
6818 (define_insn "fms<mode>4"
6819 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
6820 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
6821 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
6822 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))]
6827 wfmsdb\t%v0,%v1,%v2,%v3
6828 wfmssb\t%v0,%v1,%v2,%v3"
6829 [(set_attr "op_type" "RRE,RXE,VRR,VRR")
6830 (set_attr "type" "fmadd<mode>")
6831 (set_attr "cpu_facility" "*,*,vx,vxe")
6832 (set_attr "enabled" "*,*,<DF>,<SF>")])
6835 ;;- Divide and modulo instructions.
6839 ; divmoddi4 instruction pattern(s).
6842 (define_expand "divmoddi4"
6843 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6844 (div:DI (match_operand:DI 1 "register_operand" "")
6845 (match_operand:DI 2 "general_operand" "")))
6846 (set (match_operand:DI 3 "general_operand" "")
6847 (mod:DI (match_dup 1) (match_dup 2)))])
6848 (clobber (match_dup 4))]
6851 rtx div_equal, mod_equal;
6854 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
6855 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
6857 operands[4] = gen_reg_rtx(TImode);
6858 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
6860 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6861 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6863 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6864 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6869 (define_insn "divmodtidi3"
6870 [(set (match_operand:TI 0 "register_operand" "=d,d")
6874 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6875 (match_operand:DI 2 "general_operand" "d,T")))
6877 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
6882 [(set_attr "op_type" "RRE,RXY")
6883 (set_attr "type" "idiv")])
6885 (define_insn "divmodtisi3"
6886 [(set (match_operand:TI 0 "register_operand" "=d,d")
6890 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
6892 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
6895 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
6900 [(set_attr "op_type" "RRE,RXY")
6901 (set_attr "type" "idiv")])
6904 ; udivmoddi4 instruction pattern(s).
6907 (define_expand "udivmoddi4"
6908 [(parallel [(set (match_operand:DI 0 "general_operand" "")
6909 (udiv:DI (match_operand:DI 1 "general_operand" "")
6910 (match_operand:DI 2 "nonimmediate_operand" "")))
6911 (set (match_operand:DI 3 "general_operand" "")
6912 (umod:DI (match_dup 1) (match_dup 2)))])
6913 (clobber (match_dup 4))]
6916 rtx div_equal, mod_equal, equal;
6919 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
6920 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
6921 equal = gen_rtx_IOR (TImode,
6922 gen_rtx_ASHIFT (TImode,
6923 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
6925 gen_rtx_ZERO_EXTEND (TImode, div_equal));
6927 operands[4] = gen_reg_rtx(TImode);
6928 emit_clobber (operands[4]);
6929 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
6930 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
6932 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
6933 set_unique_reg_note (insn, REG_EQUAL, equal);
6935 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
6936 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6938 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
6939 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
6944 (define_insn "udivmodtidi3"
6945 [(set (match_operand:TI 0 "register_operand" "=d,d")
6950 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
6952 (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
6956 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
6961 [(set_attr "op_type" "RRE,RXY")
6962 (set_attr "type" "idiv")])
6965 ; divmodsi4 instruction pattern(s).
6968 (define_expand "divmodsi4"
6969 [(parallel [(set (match_operand:SI 0 "general_operand" "")
6970 (div:SI (match_operand:SI 1 "general_operand" "")
6971 (match_operand:SI 2 "nonimmediate_operand" "")))
6972 (set (match_operand:SI 3 "general_operand" "")
6973 (mod:SI (match_dup 1) (match_dup 2)))])
6974 (clobber (match_dup 4))]
6977 rtx div_equal, mod_equal, equal;
6980 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
6981 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
6982 equal = gen_rtx_IOR (DImode,
6983 gen_rtx_ASHIFT (DImode,
6984 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
6986 gen_rtx_ZERO_EXTEND (DImode, div_equal));
6988 operands[4] = gen_reg_rtx(DImode);
6989 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
6991 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
6992 set_unique_reg_note (insn, REG_EQUAL, equal);
6994 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
6995 set_unique_reg_note (insn, REG_EQUAL, div_equal);
6997 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
6998 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
7003 (define_insn "divmoddisi3"
7004 [(set (match_operand:DI 0 "register_operand" "=d,d")
7009 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
7011 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
7015 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
7020 [(set_attr "op_type" "RR,RX")
7021 (set_attr "type" "idiv")])
7024 ; udivsi3 and umodsi3 instruction pattern(s).
7027 (define_expand "udivmodsi4"
7028 [(parallel [(set (match_operand:SI 0 "general_operand" "")
7029 (udiv:SI (match_operand:SI 1 "general_operand" "")
7030 (match_operand:SI 2 "nonimmediate_operand" "")))
7031 (set (match_operand:SI 3 "general_operand" "")
7032 (umod:SI (match_dup 1) (match_dup 2)))])
7033 (clobber (match_dup 4))]
7034 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7036 rtx div_equal, mod_equal, equal;
7039 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7040 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7041 equal = gen_rtx_IOR (DImode,
7042 gen_rtx_ASHIFT (DImode,
7043 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
7045 gen_rtx_ZERO_EXTEND (DImode, div_equal));
7047 operands[4] = gen_reg_rtx(DImode);
7048 emit_clobber (operands[4]);
7049 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
7050 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
7052 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
7053 set_unique_reg_note (insn, REG_EQUAL, equal);
7055 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
7056 set_unique_reg_note (insn, REG_EQUAL, div_equal);
7058 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
7059 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
7064 (define_insn "udivmoddisi3"
7065 [(set (match_operand:DI 0 "register_operand" "=d,d")
7070 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
7072 (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
7076 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
7077 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
7081 [(set_attr "op_type" "RRE,RXY")
7082 (set_attr "type" "idiv")])
7084 (define_expand "udivsi3"
7085 [(set (match_operand:SI 0 "register_operand" "=d")
7086 (udiv:SI (match_operand:SI 1 "general_operand" "")
7087 (match_operand:SI 2 "general_operand" "")))
7088 (clobber (match_dup 3))]
7089 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
7091 rtx udiv_equal, umod_equal, equal;
7094 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7095 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7096 equal = gen_rtx_IOR (DImode,
7097 gen_rtx_ASHIFT (DImode,
7098 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
7100 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
7102 operands[3] = gen_reg_rtx (DImode);
7104 if (CONSTANT_P (operands[2]))
7106 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
7108 rtx_code_label *label1 = gen_label_rtx ();
7110 operands[1] = make_safe_from (operands[1], operands[0]);
7111 emit_move_insn (operands[0], const0_rtx);
7112 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
7114 emit_move_insn (operands[0], const1_rtx);
7115 emit_label (label1);
7119 operands[2] = force_reg (SImode, operands[2]);
7120 operands[2] = make_safe_from (operands[2], operands[0]);
7122 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7123 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7125 set_unique_reg_note (insn, REG_EQUAL, equal);
7127 insn = emit_move_insn (operands[0],
7128 gen_lowpart (SImode, operands[3]));
7129 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
7134 rtx_code_label *label1 = gen_label_rtx ();
7135 rtx_code_label *label2 = gen_label_rtx ();
7136 rtx_code_label *label3 = gen_label_rtx ();
7138 operands[1] = force_reg (SImode, operands[1]);
7139 operands[1] = make_safe_from (operands[1], operands[0]);
7140 operands[2] = force_reg (SImode, operands[2]);
7141 operands[2] = make_safe_from (operands[2], operands[0]);
7143 emit_move_insn (operands[0], const0_rtx);
7144 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7146 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7148 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7150 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7151 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7153 set_unique_reg_note (insn, REG_EQUAL, equal);
7155 insn = emit_move_insn (operands[0],
7156 gen_lowpart (SImode, operands[3]));
7157 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
7160 emit_label (label1);
7161 emit_move_insn (operands[0], operands[1]);
7163 emit_label (label2);
7164 emit_move_insn (operands[0], const1_rtx);
7165 emit_label (label3);
7167 emit_move_insn (operands[0], operands[0]);
7171 (define_expand "umodsi3"
7172 [(set (match_operand:SI 0 "register_operand" "=d")
7173 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
7174 (match_operand:SI 2 "nonimmediate_operand" "")))
7175 (clobber (match_dup 3))]
7176 "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
7178 rtx udiv_equal, umod_equal, equal;
7181 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
7182 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
7183 equal = gen_rtx_IOR (DImode,
7184 gen_rtx_ASHIFT (DImode,
7185 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
7187 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
7189 operands[3] = gen_reg_rtx (DImode);
7191 if (CONSTANT_P (operands[2]))
7193 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
7195 rtx_code_label *label1 = gen_label_rtx ();
7197 operands[1] = make_safe_from (operands[1], operands[0]);
7198 emit_move_insn (operands[0], operands[1]);
7199 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
7201 emit_insn (gen_abssi2 (operands[0], operands[2]));
7202 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
7203 emit_label (label1);
7207 operands[2] = force_reg (SImode, operands[2]);
7208 operands[2] = make_safe_from (operands[2], operands[0]);
7210 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7211 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7213 set_unique_reg_note (insn, REG_EQUAL, equal);
7215 insn = emit_move_insn (operands[0],
7216 gen_highpart (SImode, operands[3]));
7217 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7222 rtx_code_label *label1 = gen_label_rtx ();
7223 rtx_code_label *label2 = gen_label_rtx ();
7224 rtx_code_label *label3 = gen_label_rtx ();
7226 operands[1] = force_reg (SImode, operands[1]);
7227 operands[1] = make_safe_from (operands[1], operands[0]);
7228 operands[2] = force_reg (SImode, operands[2]);
7229 operands[2] = make_safe_from (operands[2], operands[0]);
7231 emit_move_insn(operands[0], operands[1]);
7232 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
7234 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
7236 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
7238 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
7239 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
7241 set_unique_reg_note (insn, REG_EQUAL, equal);
7243 insn = emit_move_insn (operands[0],
7244 gen_highpart (SImode, operands[3]));
7245 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
7248 emit_label (label1);
7249 emit_move_insn (operands[0], const0_rtx);
7251 emit_label (label2);
7252 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
7253 emit_label (label3);
7259 ; div(df|sf)3 instruction pattern(s).
7262 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
7263 (define_insn "div<mode>3"
7264 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
7265 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
7266 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
7274 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
7275 (set_attr "type" "fdiv<mode>")
7276 (set_attr "cpu_facility" "*,*,*,vx,vxe")
7277 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
7281 ;;- And instructions.
7284 (define_expand "and<mode>3"
7285 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7286 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
7287 (match_operand:INT 2 "general_operand" "")))
7288 (clobber (reg:CC CC_REGNUM))]
7290 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
7293 ; anddi3 instruction pattern(s).
7296 (define_insn "*anddi3_cc"
7297 [(set (reg CC_REGNUM)
7299 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7300 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7302 (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
7303 (and:DI (match_dup 1) (match_dup 2)))]
7304 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
7309 risbg\t%0,%1,%s2,128+%e2,0"
7310 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7311 (set_attr "cpu_facility" "*,z196,*,z10")
7312 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7314 (define_insn "*anddi3_cconly"
7315 [(set (reg CC_REGNUM)
7317 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
7318 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
7320 (clobber (match_scratch:DI 0 "=d,d,d, d"))]
7322 && s390_match_ccmode(insn, CCTmode)
7323 /* Do not steal TM patterns. */
7324 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
7329 risbg\t%0,%1,%s2,128+%e2,0"
7330 [(set_attr "op_type" "RRE,RRF,RXY,RIE")
7331 (set_attr "cpu_facility" "*,z196,*,z10")
7332 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
7334 (define_insn "*anddi3"
7335 [(set (match_operand:DI 0 "nonimmediate_operand"
7336 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
7338 (match_operand:DI 1 "nonimmediate_operand"
7339 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
7340 (match_operand:DI 2 "general_operand"
7341 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
7342 (clobber (reg:CC CC_REGNUM))]
7343 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7356 risbg\t%0,%1,%s2,128+%e2,0
7359 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
7360 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
7361 (set_attr "z10prop" "*,
7377 [(set (match_operand:DI 0 "s_operand" "")
7378 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7379 (clobber (reg:CC CC_REGNUM))]
7382 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7383 (clobber (reg:CC CC_REGNUM))])]
7384 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7386 ;; These two are what combine generates for (ashift (zero_extract)).
7387 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
7388 [(set (match_operand:GPR 0 "register_operand" "=d")
7389 (and:GPR (lshiftrt:GPR
7390 (match_operand:GPR 1 "register_operand" "d")
7391 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7392 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7393 "<z10_or_zEC12_cond>
7394 /* Note that even for the SImode pattern, the rotate is always DImode. */
7395 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
7396 INTVAL (operands[3]))"
7397 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
7398 [(set_attr "op_type" "RIE")
7399 (set_attr "z10prop" "z10_super_E1")])
7401 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
7402 [(set (match_operand:GPR 0 "register_operand" "=d")
7403 (and:GPR (ashift:GPR
7404 (match_operand:GPR 1 "register_operand" "d")
7405 (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
7406 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
7407 "<z10_or_zEC12_cond>
7408 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
7409 INTVAL (operands[3]))"
7410 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
7411 [(set_attr "op_type" "RIE")
7412 (set_attr "z10prop" "z10_super_E1")])
7416 ; andsi3 instruction pattern(s).
7419 (define_insn "*andsi3_cc"
7420 [(set (reg CC_REGNUM)
7423 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7424 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7426 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
7427 (and:SI (match_dup 1) (match_dup 2)))]
7428 "s390_match_ccmode(insn, CCTmode)"
7435 risbg\t%0,%1,%t2,128+%f2,0"
7436 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7437 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7438 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7439 z10_super_E1,z10_super_E1,z10_super_E1")])
7441 (define_insn "*andsi3_cconly"
7442 [(set (reg CC_REGNUM)
7445 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
7446 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
7448 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
7449 "s390_match_ccmode(insn, CCTmode)
7450 /* Do not steal TM patterns. */
7451 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
7458 risbg\t%0,%1,%t2,128+%f2,0"
7459 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
7460 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
7461 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
7462 z10_super_E1,z10_super_E1,z10_super_E1")])
7464 (define_insn "*andsi3_zarch"
7465 [(set (match_operand:SI 0 "nonimmediate_operand"
7466 "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
7467 (and:SI (match_operand:SI 1 "nonimmediate_operand"
7468 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
7469 (match_operand:SI 2 "general_operand"
7470 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
7471 (clobber (reg:CC CC_REGNUM))]
7472 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7483 risbg\t%0,%1,%t2,128+%f2,0
7486 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
7487 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
7488 (set_attr "z10prop" "*,
7501 (define_insn "*andsi3_esa"
7502 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
7503 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
7504 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
7505 (clobber (reg:CC CC_REGNUM))]
7506 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7512 [(set_attr "op_type" "RR,RX,SI,SS")
7513 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7517 [(set (match_operand:SI 0 "s_operand" "")
7518 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7519 (clobber (reg:CC CC_REGNUM))]
7522 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7523 (clobber (reg:CC CC_REGNUM))])]
7524 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7527 ; andhi3 instruction pattern(s).
7530 (define_insn "*andhi3_zarch"
7531 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7532 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7533 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
7534 (clobber (reg:CC CC_REGNUM))]
7535 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7542 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7543 (set_attr "cpu_facility" "*,z196,*,*,*")
7544 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
7547 (define_insn "*andhi3_esa"
7548 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7549 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7550 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
7551 (clobber (reg:CC CC_REGNUM))]
7552 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7557 [(set_attr "op_type" "RR,SI,SS")
7558 (set_attr "z10prop" "z10_super_E1,*,*")
7562 [(set (match_operand:HI 0 "s_operand" "")
7563 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7564 (clobber (reg:CC CC_REGNUM))]
7567 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7568 (clobber (reg:CC CC_REGNUM))])]
7569 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
7572 ; andqi3 instruction pattern(s).
7575 (define_insn "*andqi3_zarch"
7576 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7577 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7578 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7579 (clobber (reg:CC CC_REGNUM))]
7580 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7588 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7589 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7590 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
7592 (define_insn "*andqi3_esa"
7593 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7594 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7595 (match_operand:QI 2 "general_operand" "d,n,Q")))
7596 (clobber (reg:CC CC_REGNUM))]
7597 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7602 [(set_attr "op_type" "RR,SI,SS")
7603 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7606 ; And with complement
7608 ; c = ~b & a = (b & a) ^ a
7610 (define_insn_and_split "*andc_split_<mode>"
7611 [(set (match_operand:GPR 0 "nonimmediate_operand" "")
7612 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
7613 (match_operand:GPR 2 "general_operand" "")))
7614 (clobber (reg:CC CC_REGNUM))]
7616 && (GET_CODE (operands[0]) != MEM
7617 /* Ensure that s390_logical_operator_ok_p will succeed even
7618 on the split xor if (b & a) is stored into a pseudo. */
7619 || rtx_equal_p (operands[0], operands[2]))"
7624 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
7625 (clobber (reg:CC CC_REGNUM))])
7627 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
7628 (clobber (reg:CC CC_REGNUM))])]
7630 if (reg_overlap_mentioned_p (operands[0], operands[2]))
7631 operands[3] = gen_reg_rtx (<MODE>mode);
7633 operands[3] = operands[0];
7637 ; Block and (NC) patterns.
7641 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7642 (and:BLK (match_dup 0)
7643 (match_operand:BLK 1 "memory_operand" "Q")))
7644 (use (match_operand 2 "const_int_operand" "n"))
7645 (clobber (reg:CC CC_REGNUM))]
7646 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7647 "nc\t%O0(%2,%R0),%S1"
7648 [(set_attr "op_type" "SS")
7649 (set_attr "z196prop" "z196_cracked")])
7652 [(set (match_operand 0 "memory_operand" "")
7654 (match_operand 1 "memory_operand" "")))
7655 (clobber (reg:CC CC_REGNUM))]
7657 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7658 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7660 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
7662 (clobber (reg:CC CC_REGNUM))])]
7664 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7665 operands[0] = adjust_address (operands[0], BLKmode, 0);
7666 operands[1] = adjust_address (operands[1], BLKmode, 0);
7671 [(set (match_operand:BLK 0 "memory_operand" "")
7672 (and:BLK (match_dup 0)
7673 (match_operand:BLK 1 "memory_operand" "")))
7674 (use (match_operand 2 "const_int_operand" ""))
7675 (clobber (reg:CC CC_REGNUM))])
7677 [(set (match_operand:BLK 3 "memory_operand" "")
7678 (and:BLK (match_dup 3)
7679 (match_operand:BLK 4 "memory_operand" "")))
7680 (use (match_operand 5 "const_int_operand" ""))
7681 (clobber (reg:CC CC_REGNUM))])]
7682 "s390_offset_p (operands[0], operands[3], operands[2])
7683 && s390_offset_p (operands[1], operands[4], operands[2])
7684 && !s390_overlap_p (operands[0], operands[1],
7685 INTVAL (operands[2]) + INTVAL (operands[5]))
7686 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
7688 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
7690 (clobber (reg:CC CC_REGNUM))])]
7691 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
7692 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
7693 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
7697 ;;- Bit set (inclusive or) instructions.
7700 (define_expand "ior<mode>3"
7701 [(set (match_operand:INT 0 "nonimmediate_operand" "")
7702 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
7703 (match_operand:INT 2 "general_operand" "")))
7704 (clobber (reg:CC CC_REGNUM))]
7706 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
7709 ; iordi3 instruction pattern(s).
7712 (define_insn "*iordi3_cc"
7713 [(set (reg CC_REGNUM)
7714 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7715 (match_operand:DI 2 "general_operand" " d,d,T"))
7717 (set (match_operand:DI 0 "register_operand" "=d,d,d")
7718 (ior:DI (match_dup 1) (match_dup 2)))]
7719 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7724 [(set_attr "op_type" "RRE,RRF,RXY")
7725 (set_attr "cpu_facility" "*,z196,*")
7726 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7728 (define_insn "*iordi3_cconly"
7729 [(set (reg CC_REGNUM)
7730 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
7731 (match_operand:DI 2 "general_operand" " d,d,T"))
7733 (clobber (match_scratch:DI 0 "=d,d,d"))]
7734 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
7739 [(set_attr "op_type" "RRE,RRF,RXY")
7740 (set_attr "cpu_facility" "*,z196,*")
7741 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
7743 (define_insn "*iordi3"
7744 [(set (match_operand:DI 0 "nonimmediate_operand"
7745 "=d, d, d, d, d, d,d,d,d, AQ,Q")
7746 (ior:DI (match_operand:DI 1 "nonimmediate_operand"
7747 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
7748 (match_operand:DI 2 "general_operand"
7749 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
7750 (clobber (reg:CC CC_REGNUM))]
7751 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7764 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
7765 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
7766 (set_attr "z10prop" "z10_super_E1,
7779 [(set (match_operand:DI 0 "s_operand" "")
7780 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
7781 (clobber (reg:CC CC_REGNUM))]
7784 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7785 (clobber (reg:CC CC_REGNUM))])]
7786 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7789 ; iorsi3 instruction pattern(s).
7792 (define_insn "*iorsi3_cc"
7793 [(set (reg CC_REGNUM)
7794 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7795 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7797 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
7798 (ior:SI (match_dup 1) (match_dup 2)))]
7799 "s390_match_ccmode(insn, CCTmode)"
7806 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7807 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7808 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7810 (define_insn "*iorsi3_cconly"
7811 [(set (reg CC_REGNUM)
7812 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
7813 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
7815 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
7816 "s390_match_ccmode(insn, CCTmode)"
7823 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
7824 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
7825 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
7827 (define_insn "*iorsi3_zarch"
7828 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
7829 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
7830 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
7831 (clobber (reg:CC CC_REGNUM))]
7832 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7843 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
7844 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
7845 (set_attr "z10prop" "z10_super_E1,
7855 (define_insn "*iorsi3_esa"
7856 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
7857 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
7858 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
7859 (clobber (reg:CC CC_REGNUM))]
7860 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7866 [(set_attr "op_type" "RR,RX,SI,SS")
7867 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
7870 [(set (match_operand:SI 0 "s_operand" "")
7871 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
7872 (clobber (reg:CC CC_REGNUM))]
7875 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7876 (clobber (reg:CC CC_REGNUM))])]
7877 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7880 ; iorhi3 instruction pattern(s).
7883 (define_insn "*iorhi3_zarch"
7884 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
7885 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
7886 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
7887 (clobber (reg:CC CC_REGNUM))]
7888 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7895 [(set_attr "op_type" "RR,RRF,RI,SI,SS")
7896 (set_attr "cpu_facility" "*,z196,*,*,*")
7897 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
7899 (define_insn "*iorhi3_esa"
7900 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
7901 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
7902 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
7903 (clobber (reg:CC CC_REGNUM))]
7904 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7909 [(set_attr "op_type" "RR,SI,SS")
7910 (set_attr "z10prop" "z10_super_E1,*,*")])
7913 [(set (match_operand:HI 0 "s_operand" "")
7914 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
7915 (clobber (reg:CC CC_REGNUM))]
7918 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
7919 (clobber (reg:CC CC_REGNUM))])]
7920 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
7923 ; iorqi3 instruction pattern(s).
7926 (define_insn "*iorqi3_zarch"
7927 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
7928 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
7929 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
7930 (clobber (reg:CC CC_REGNUM))]
7931 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7939 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
7940 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
7941 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
7942 z10_super,z10_super,*")])
7944 (define_insn "*iorqi3_esa"
7945 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
7946 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
7947 (match_operand:QI 2 "general_operand" "d,n,Q")))
7948 (clobber (reg:CC CC_REGNUM))]
7949 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
7954 [(set_attr "op_type" "RR,SI,SS")
7955 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
7958 ; Block inclusive or (OC) patterns.
7962 [(set (match_operand:BLK 0 "memory_operand" "=Q")
7963 (ior:BLK (match_dup 0)
7964 (match_operand:BLK 1 "memory_operand" "Q")))
7965 (use (match_operand 2 "const_int_operand" "n"))
7966 (clobber (reg:CC CC_REGNUM))]
7967 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
7968 "oc\t%O0(%2,%R0),%S1"
7969 [(set_attr "op_type" "SS")
7970 (set_attr "z196prop" "z196_cracked")])
7973 [(set (match_operand 0 "memory_operand" "")
7975 (match_operand 1 "memory_operand" "")))
7976 (clobber (reg:CC CC_REGNUM))]
7978 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7979 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
7981 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
7983 (clobber (reg:CC CC_REGNUM))])]
7985 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
7986 operands[0] = adjust_address (operands[0], BLKmode, 0);
7987 operands[1] = adjust_address (operands[1], BLKmode, 0);
7992 [(set (match_operand:BLK 0 "memory_operand" "")
7993 (ior:BLK (match_dup 0)
7994 (match_operand:BLK 1 "memory_operand" "")))
7995 (use (match_operand 2 "const_int_operand" ""))
7996 (clobber (reg:CC CC_REGNUM))])
7998 [(set (match_operand:BLK 3 "memory_operand" "")
7999 (ior:BLK (match_dup 3)
8000 (match_operand:BLK 4 "memory_operand" "")))
8001 (use (match_operand 5 "const_int_operand" ""))
8002 (clobber (reg:CC CC_REGNUM))])]
8003 "s390_offset_p (operands[0], operands[3], operands[2])
8004 && s390_offset_p (operands[1], operands[4], operands[2])
8005 && !s390_overlap_p (operands[0], operands[1],
8006 INTVAL (operands[2]) + INTVAL (operands[5]))
8007 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8009 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
8011 (clobber (reg:CC CC_REGNUM))])]
8012 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8013 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8014 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8018 ;;- Xor instructions.
8021 (define_expand "xor<mode>3"
8022 [(set (match_operand:INT 0 "nonimmediate_operand" "")
8023 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
8024 (match_operand:INT 2 "general_operand" "")))
8025 (clobber (reg:CC CC_REGNUM))]
8027 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
8029 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing
8030 ; simplifications. So its better to have something matching.
8032 [(set (match_operand:INT 0 "nonimmediate_operand" "")
8033 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))]
8036 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2)))
8037 (clobber (reg:CC CC_REGNUM))])]
8039 operands[2] = constm1_rtx;
8040 if (!s390_logical_operator_ok_p (operands))
8045 ; xordi3 instruction pattern(s).
8048 (define_insn "*xordi3_cc"
8049 [(set (reg CC_REGNUM)
8050 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
8051 (match_operand:DI 2 "general_operand" " d,d,T"))
8053 (set (match_operand:DI 0 "register_operand" "=d,d,d")
8054 (xor:DI (match_dup 1) (match_dup 2)))]
8055 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
8060 [(set_attr "op_type" "RRE,RRF,RXY")
8061 (set_attr "cpu_facility" "*,z196,*")
8062 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
8064 (define_insn "*xordi3_cconly"
8065 [(set (reg CC_REGNUM)
8066 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
8067 (match_operand:DI 2 "general_operand" " d,d,T"))
8069 (clobber (match_scratch:DI 0 "=d,d,d"))]
8070 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
8075 [(set_attr "op_type" "RRE,RRF,RXY")
8076 (set_attr "cpu_facility" "*,z196,*")
8077 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
8079 (define_insn "*xordi3"
8080 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
8081 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
8082 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
8083 (clobber (reg:CC CC_REGNUM))]
8084 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
8093 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
8094 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
8095 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
8096 *,z10_super_E1,*,*")])
8099 [(set (match_operand:DI 0 "s_operand" "")
8100 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
8101 (clobber (reg:CC CC_REGNUM))]
8104 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8105 (clobber (reg:CC CC_REGNUM))])]
8106 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8109 ; xorsi3 instruction pattern(s).
8112 (define_insn "*xorsi3_cc"
8113 [(set (reg CC_REGNUM)
8114 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
8115 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
8117 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
8118 (xor:SI (match_dup 1) (match_dup 2)))]
8119 "s390_match_ccmode(insn, CCTmode)"
8126 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
8127 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
8128 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8129 z10_super_E1,z10_super_E1")])
8131 (define_insn "*xorsi3_cconly"
8132 [(set (reg CC_REGNUM)
8133 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
8134 (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
8136 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
8137 "s390_match_ccmode(insn, CCTmode)"
8144 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
8145 (set_attr "cpu_facility" "*,*,z196,*,longdisp")
8146 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8147 z10_super_E1,z10_super_E1")])
8149 (define_insn "*xorsi3"
8150 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
8151 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
8152 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
8153 (clobber (reg:CC CC_REGNUM))]
8154 "s390_logical_operator_ok_p (operands)"
8163 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
8164 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
8165 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
8166 z10_super_E1,z10_super_E1,*,*")])
8169 [(set (match_operand:SI 0 "s_operand" "")
8170 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
8171 (clobber (reg:CC CC_REGNUM))]
8174 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8175 (clobber (reg:CC CC_REGNUM))])]
8176 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8179 ; xorhi3 instruction pattern(s).
8182 (define_insn "*xorhi3"
8183 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
8184 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
8185 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
8186 (clobber (reg:CC CC_REGNUM))]
8187 "s390_logical_operator_ok_p (operands)"
8194 [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
8195 (set_attr "cpu_facility" "*,*,z196,*,*")
8196 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
8199 [(set (match_operand:HI 0 "s_operand" "")
8200 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
8201 (clobber (reg:CC CC_REGNUM))]
8204 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
8205 (clobber (reg:CC CC_REGNUM))])]
8206 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
8209 ; xorqi3 instruction pattern(s).
8212 (define_insn "*xorqi3"
8213 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
8214 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
8215 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
8216 (clobber (reg:CC CC_REGNUM))]
8217 "s390_logical_operator_ok_p (operands)"
8225 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
8226 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
8227 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
8231 ; Block exclusive or (XC) patterns.
8235 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8236 (xor:BLK (match_dup 0)
8237 (match_operand:BLK 1 "memory_operand" "Q")))
8238 (use (match_operand 2 "const_int_operand" "n"))
8239 (clobber (reg:CC CC_REGNUM))]
8240 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
8241 "xc\t%O0(%2,%R0),%S1"
8242 [(set_attr "op_type" "SS")])
8245 [(set (match_operand 0 "memory_operand" "")
8247 (match_operand 1 "memory_operand" "")))
8248 (clobber (reg:CC CC_REGNUM))]
8250 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8251 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
8253 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
8255 (clobber (reg:CC CC_REGNUM))])]
8257 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
8258 operands[0] = adjust_address (operands[0], BLKmode, 0);
8259 operands[1] = adjust_address (operands[1], BLKmode, 0);
8264 [(set (match_operand:BLK 0 "memory_operand" "")
8265 (xor:BLK (match_dup 0)
8266 (match_operand:BLK 1 "memory_operand" "")))
8267 (use (match_operand 2 "const_int_operand" ""))
8268 (clobber (reg:CC CC_REGNUM))])
8270 [(set (match_operand:BLK 3 "memory_operand" "")
8271 (xor:BLK (match_dup 3)
8272 (match_operand:BLK 4 "memory_operand" "")))
8273 (use (match_operand 5 "const_int_operand" ""))
8274 (clobber (reg:CC CC_REGNUM))])]
8275 "s390_offset_p (operands[0], operands[3], operands[2])
8276 && s390_offset_p (operands[1], operands[4], operands[2])
8277 && !s390_overlap_p (operands[0], operands[1],
8278 INTVAL (operands[2]) + INTVAL (operands[5]))
8279 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
8281 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
8283 (clobber (reg:CC CC_REGNUM))])]
8284 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8285 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
8286 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
8289 ; Block xor (XC) patterns with src == dest.
8292 (define_insn "*xc_zero"
8293 [(set (match_operand:BLK 0 "memory_operand" "=Q")
8295 (use (match_operand 1 "const_int_operand" "n"))
8296 (clobber (reg:CC CC_REGNUM))]
8297 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
8298 "xc\t%O0(%1,%R0),%S0"
8299 [(set_attr "op_type" "SS")
8300 (set_attr "z196prop" "z196_cracked")])
8304 [(set (match_operand:BLK 0 "memory_operand" "")
8306 (use (match_operand 1 "const_int_operand" ""))
8307 (clobber (reg:CC CC_REGNUM))])
8309 [(set (match_operand:BLK 2 "memory_operand" "")
8311 (use (match_operand 3 "const_int_operand" ""))
8312 (clobber (reg:CC CC_REGNUM))])]
8313 "s390_offset_p (operands[0], operands[2], operands[1])
8314 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
8316 [(set (match_dup 4) (const_int 0))
8318 (clobber (reg:CC CC_REGNUM))])]
8319 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
8320 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
8324 ;;- Negate instructions.
8328 ; neg(di|si)2 instruction pattern(s).
8331 (define_expand "neg<mode>2"
8333 [(set (match_operand:DSI 0 "register_operand" "=d")
8334 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
8335 (clobber (reg:CC CC_REGNUM))])]
8339 (define_insn "*negdi2_sign_cc"
8340 [(set (reg CC_REGNUM)
8341 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
8342 (match_operand:SI 1 "register_operand" "d") 0)
8343 (const_int 32)) (const_int 32)))
8345 (set (match_operand:DI 0 "register_operand" "=d")
8346 (neg:DI (sign_extend:DI (match_dup 1))))]
8347 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8349 [(set_attr "op_type" "RRE")
8350 (set_attr "z10prop" "z10_c")])
8352 (define_insn "*negdi2_sign"
8353 [(set (match_operand:DI 0 "register_operand" "=d")
8354 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8355 (clobber (reg:CC CC_REGNUM))]
8358 [(set_attr "op_type" "RRE")
8359 (set_attr "z10prop" "z10_c")])
8362 (define_insn "*neg<mode>2_cc"
8363 [(set (reg CC_REGNUM)
8364 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8366 (set (match_operand:GPR 0 "register_operand" "=d")
8367 (neg:GPR (match_dup 1)))]
8368 "s390_match_ccmode (insn, CCAmode)"
8370 [(set_attr "op_type" "RR<E>")
8371 (set_attr "z10prop" "z10_super_c_E1")])
8374 (define_insn "*neg<mode>2_cconly"
8375 [(set (reg CC_REGNUM)
8376 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
8378 (clobber (match_scratch:GPR 0 "=d"))]
8379 "s390_match_ccmode (insn, CCAmode)"
8381 [(set_attr "op_type" "RR<E>")
8382 (set_attr "z10prop" "z10_super_c_E1")])
8385 (define_insn "*neg<mode>2"
8386 [(set (match_operand:GPR 0 "register_operand" "=d")
8387 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
8388 (clobber (reg:CC CC_REGNUM))]
8391 [(set_attr "op_type" "RR<E>")
8392 (set_attr "z10prop" "z10_super_c_E1")])
8394 (define_insn "*negdi2_31"
8395 [(set (match_operand:DI 0 "register_operand" "=d")
8396 (neg:DI (match_operand:DI 1 "register_operand" "d")))
8397 (clobber (reg:CC CC_REGNUM))]
8401 ; Split a DImode NEG on 31bit into 2 SImode NEGs
8403 ; Doing the twos complement separately on the SImode parts does an
8404 ; unwanted +1 on the high part which needs to be subtracted afterwards
8405 ; ... unless the +1 on the low part created an overflow.
8408 [(set (match_operand:DI 0 "register_operand" "")
8409 (neg:DI (match_operand:DI 1 "register_operand" "")))
8410 (clobber (reg:CC CC_REGNUM))]
8412 && (REGNO (operands[0]) == REGNO (operands[1])
8413 || s390_split_ok_p (operands[0], operands[1], DImode, 0))
8414 && reload_completed"
8416 [(set (match_dup 2) (neg:SI (match_dup 3)))
8417 (clobber (reg:CC CC_REGNUM))])
8419 [(set (reg:CCAP CC_REGNUM)
8420 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
8421 (set (match_dup 4) (neg:SI (match_dup 5)))])
8423 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8425 (label_ref (match_dup 6))))
8427 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8428 (clobber (reg:CC CC_REGNUM))])
8430 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8431 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8432 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8433 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8434 operands[6] = gen_label_rtx ();")
8436 ; Like above but first make a copy of the low part of the src operand
8437 ; since it might overlap with the high part of the destination.
8440 [(set (match_operand:DI 0 "register_operand" "")
8441 (neg:DI (match_operand:DI 1 "register_operand" "")))
8442 (clobber (reg:CC CC_REGNUM))]
8444 && s390_split_ok_p (operands[0], operands[1], DImode, 1)
8445 && reload_completed"
8446 [; Make a backup of op5 first
8447 (set (match_dup 4) (match_dup 5))
8448 ; Setting op2 here might clobber op5
8450 [(set (match_dup 2) (neg:SI (match_dup 3)))
8451 (clobber (reg:CC CC_REGNUM))])
8453 [(set (reg:CCAP CC_REGNUM)
8454 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0)))
8455 (set (match_dup 4) (neg:SI (match_dup 4)))])
8457 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
8459 (label_ref (match_dup 6))))
8461 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
8462 (clobber (reg:CC CC_REGNUM))])
8464 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
8465 operands[3] = operand_subword (operands[1], 0, 0, DImode);
8466 operands[4] = operand_subword (operands[0], 1, 0, DImode);
8467 operands[5] = operand_subword (operands[1], 1, 0, DImode);
8468 operands[6] = gen_label_rtx ();")
8471 ; neg(df|sf)2 instruction pattern(s).
8474 (define_expand "neg<mode>2"
8476 [(set (match_operand:BFP 0 "register_operand")
8477 (neg:BFP (match_operand:BFP 1 "register_operand")))
8478 (clobber (reg:CC CC_REGNUM))])]
8479 "TARGET_HARD_FLOAT")
8481 ; lcxbr, lcdbr, lcebr
8482 (define_insn "*neg<mode>2_cc"
8483 [(set (reg CC_REGNUM)
8484 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8485 (match_operand:BFP 2 "const0_operand" "")))
8486 (set (match_operand:BFP 0 "register_operand" "=f")
8487 (neg:BFP (match_dup 1)))]
8488 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8490 [(set_attr "op_type" "RRE")
8491 (set_attr "type" "fsimp<mode>")])
8493 ; lcxbr, lcdbr, lcebr
8494 (define_insn "*neg<mode>2_cconly"
8495 [(set (reg CC_REGNUM)
8496 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
8497 (match_operand:BFP 2 "const0_operand" "")))
8498 (clobber (match_scratch:BFP 0 "=f"))]
8499 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8501 [(set_attr "op_type" "RRE")
8502 (set_attr "type" "fsimp<mode>")])
8505 (define_insn "*neg<mode>2_nocc"
8506 [(set (match_operand:FP 0 "register_operand" "=f")
8507 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8510 [(set_attr "op_type" "RRE")
8511 (set_attr "type" "fsimp<mode>")])
8513 ; lcxbr, lcdbr, lcebr
8514 ; FIXME: wflcdb does not clobber cc
8515 ; FIXME: Does wflcdb ever match here?
8516 (define_insn "*neg<mode>2"
8517 [(set (match_operand:BFP 0 "register_operand" "=f,v,v")
8518 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v")))
8519 (clobber (reg:CC CC_REGNUM))]
8525 [(set_attr "op_type" "RRE,VRR,VRR")
8526 (set_attr "cpu_facility" "*,vx,vxe")
8527 (set_attr "type" "fsimp<mode>,*,*")
8528 (set_attr "enabled" "*,<DF>,<SF>")])
8532 ;;- Absolute value instructions.
8536 ; abs(di|si)2 instruction pattern(s).
8539 (define_insn "*absdi2_sign_cc"
8540 [(set (reg CC_REGNUM)
8541 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8542 (match_operand:SI 1 "register_operand" "d") 0)
8543 (const_int 32)) (const_int 32)))
8545 (set (match_operand:DI 0 "register_operand" "=d")
8546 (abs:DI (sign_extend:DI (match_dup 1))))]
8547 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8549 [(set_attr "op_type" "RRE")
8550 (set_attr "z10prop" "z10_c")])
8552 (define_insn "*absdi2_sign"
8553 [(set (match_operand:DI 0 "register_operand" "=d")
8554 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
8555 (clobber (reg:CC CC_REGNUM))]
8558 [(set_attr "op_type" "RRE")
8559 (set_attr "z10prop" "z10_c")])
8562 (define_insn "*abs<mode>2_cc"
8563 [(set (reg CC_REGNUM)
8564 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
8566 (set (match_operand:GPR 0 "register_operand" "=d")
8567 (abs:GPR (match_dup 1)))]
8568 "s390_match_ccmode (insn, CCAmode)"
8570 [(set_attr "op_type" "RR<E>")
8571 (set_attr "z10prop" "z10_c")])
8574 (define_insn "*abs<mode>2_cconly"
8575 [(set (reg CC_REGNUM)
8576 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
8578 (clobber (match_scratch:GPR 0 "=d"))]
8579 "s390_match_ccmode (insn, CCAmode)"
8581 [(set_attr "op_type" "RR<E>")
8582 (set_attr "z10prop" "z10_c")])
8585 (define_insn "abs<mode>2"
8586 [(set (match_operand:GPR 0 "register_operand" "=d")
8587 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8588 (clobber (reg:CC CC_REGNUM))]
8591 [(set_attr "op_type" "RR<E>")
8592 (set_attr "z10prop" "z10_c")])
8595 ; abs(df|sf)2 instruction pattern(s).
8598 (define_expand "abs<mode>2"
8600 [(set (match_operand:BFP 0 "register_operand" "=f")
8601 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8602 (clobber (reg:CC CC_REGNUM))])]
8606 ; lpxbr, lpdbr, lpebr
8607 (define_insn "*abs<mode>2_cc"
8608 [(set (reg CC_REGNUM)
8609 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8610 (match_operand:BFP 2 "const0_operand" "")))
8611 (set (match_operand:BFP 0 "register_operand" "=f")
8612 (abs:BFP (match_dup 1)))]
8613 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8615 [(set_attr "op_type" "RRE")
8616 (set_attr "type" "fsimp<mode>")])
8618 ; lpxbr, lpdbr, lpebr
8619 (define_insn "*abs<mode>2_cconly"
8620 [(set (reg CC_REGNUM)
8621 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
8622 (match_operand:BFP 2 "const0_operand" "")))
8623 (clobber (match_scratch:BFP 0 "=f"))]
8624 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8626 [(set_attr "op_type" "RRE")
8627 (set_attr "type" "fsimp<mode>")])
8630 (define_insn "*abs<mode>2_nocc"
8631 [(set (match_operand:FP 0 "register_operand" "=f")
8632 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
8635 [(set_attr "op_type" "RRE")
8636 (set_attr "type" "fsimp<mode>")])
8638 ; lpxbr, lpdbr, lpebr
8639 ; FIXME: wflpdb does not clobber cc
8640 (define_insn "*abs<mode>2"
8641 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8642 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
8643 (clobber (reg:CC CC_REGNUM))]
8648 [(set_attr "op_type" "RRE,VRR")
8649 (set_attr "cpu_facility" "*,vx")
8650 (set_attr "type" "fsimp<mode>,*")
8651 (set_attr "enabled" "*,<DFDI>")])
8655 ;;- Negated absolute value instructions
8662 (define_insn "*negabsdi2_sign_cc"
8663 [(set (reg CC_REGNUM)
8664 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
8665 (match_operand:SI 1 "register_operand" "d") 0)
8666 (const_int 32)) (const_int 32))))
8668 (set (match_operand:DI 0 "register_operand" "=d")
8669 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
8670 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
8672 [(set_attr "op_type" "RRE")
8673 (set_attr "z10prop" "z10_c")])
8675 (define_insn "*negabsdi2_sign"
8676 [(set (match_operand:DI 0 "register_operand" "=d")
8677 (neg:DI (abs:DI (sign_extend:DI
8678 (match_operand:SI 1 "register_operand" "d")))))
8679 (clobber (reg:CC CC_REGNUM))]
8682 [(set_attr "op_type" "RRE")
8683 (set_attr "z10prop" "z10_c")])
8686 (define_insn "*negabs<mode>2_cc"
8687 [(set (reg CC_REGNUM)
8688 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8690 (set (match_operand:GPR 0 "register_operand" "=d")
8691 (neg:GPR (abs:GPR (match_dup 1))))]
8692 "s390_match_ccmode (insn, CCAmode)"
8694 [(set_attr "op_type" "RR<E>")
8695 (set_attr "z10prop" "z10_c")])
8698 (define_insn "*negabs<mode>2_cconly"
8699 [(set (reg CC_REGNUM)
8700 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
8702 (clobber (match_scratch:GPR 0 "=d"))]
8703 "s390_match_ccmode (insn, CCAmode)"
8705 [(set_attr "op_type" "RR<E>")
8706 (set_attr "z10prop" "z10_c")])
8709 (define_insn "*negabs<mode>2"
8710 [(set (match_operand:GPR 0 "register_operand" "=d")
8711 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
8712 (clobber (reg:CC CC_REGNUM))]
8715 [(set_attr "op_type" "RR<E>")
8716 (set_attr "z10prop" "z10_c")])
8722 ; lnxbr, lndbr, lnebr
8723 (define_insn "*negabs<mode>2_cc"
8724 [(set (reg CC_REGNUM)
8725 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8726 (match_operand:BFP 2 "const0_operand" "")))
8727 (set (match_operand:BFP 0 "register_operand" "=f")
8728 (neg:BFP (abs:BFP (match_dup 1))))]
8729 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8731 [(set_attr "op_type" "RRE")
8732 (set_attr "type" "fsimp<mode>")])
8734 ; lnxbr, lndbr, lnebr
8735 (define_insn "*negabs<mode>2_cconly"
8736 [(set (reg CC_REGNUM)
8737 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
8738 (match_operand:BFP 2 "const0_operand" "")))
8739 (clobber (match_scratch:BFP 0 "=f"))]
8740 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
8742 [(set_attr "op_type" "RRE")
8743 (set_attr "type" "fsimp<mode>")])
8746 (define_insn "*negabs<mode>2_nocc"
8747 [(set (match_operand:FP 0 "register_operand" "=f")
8748 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
8751 [(set_attr "op_type" "RRE")
8752 (set_attr "type" "fsimp<mode>")])
8754 ; lnxbr, lndbr, lnebr
8755 ; FIXME: wflndb does not clobber cc
8756 (define_insn "*negabs<mode>2"
8757 [(set (match_operand:BFP 0 "register_operand" "=f,v")
8758 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
8759 (clobber (reg:CC CC_REGNUM))]
8764 [(set_attr "op_type" "RRE,VRR")
8765 (set_attr "cpu_facility" "*,vx")
8766 (set_attr "type" "fsimp<mode>,*")
8767 (set_attr "enabled" "*,<DFDI>")])
8770 ;;- Square root instructions.
8774 ; sqrt(df|sf)2 instruction pattern(s).
8777 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
8778 (define_insn "sqrt<mode>2"
8779 [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
8780 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
8786 [(set_attr "op_type" "RRE,RXE,VRR")
8787 (set_attr "type" "fsqrt<mode>")
8788 (set_attr "cpu_facility" "*,*,vx")
8789 (set_attr "enabled" "*,<DSF>,<DFDI>")])
8793 ;;- One complement instructions.
8797 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
8800 (define_expand "one_cmpl<mode>2"
8802 [(set (match_operand:INT 0 "register_operand" "")
8803 (xor:INT (match_operand:INT 1 "register_operand" "")
8805 (clobber (reg:CC CC_REGNUM))])]
8811 ;; Find leftmost bit instructions.
8814 (define_expand "clzdi2"
8815 [(set (match_operand:DI 0 "register_operand" "=d")
8816 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
8817 "TARGET_EXTIMM && TARGET_ZARCH"
8821 rtx wide_reg = gen_reg_rtx (TImode);
8822 rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
8824 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
8826 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
8828 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
8829 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
8834 (define_insn "clztidi2"
8835 [(set (match_operand:TI 0 "register_operand" "=d")
8839 (xor:DI (match_operand:DI 1 "register_operand" "d")
8840 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
8841 (subreg:SI (clz:DI (match_dup 1)) 4))))
8844 (zero_extend:TI (clz:DI (match_dup 1)))))
8845 (clobber (reg:CC CC_REGNUM))]
8846 "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
8847 && TARGET_EXTIMM && TARGET_ZARCH"
8849 [(set_attr "op_type" "RRE")])
8853 ;;- Rotate instructions.
8857 ; rotl(di|si)3 instruction pattern(s).
8860 (define_expand "rotl<mode>3"
8861 [(set (match_operand:GPR 0 "register_operand" "")
8862 (rotate:GPR (match_operand:GPR 1 "register_operand" "")
8863 (match_operand:SI 2 "nonmemory_operand" "")))]
8868 (define_insn "*rotl<mode>3<addr_style_op><masked_op>"
8869 [(set (match_operand:GPR 0 "register_operand" "=d")
8870 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
8871 (match_operand:SI 2 "nonmemory_operand" "an")))]
8873 "rll<g>\t%0,%1,<addr_style_op_ops>"
8874 [(set_attr "op_type" "RSE")
8875 (set_attr "atype" "reg")
8876 (set_attr "z10prop" "z10_super_E1")])
8880 ;;- Shift instructions.
8884 ; (ashl|lshr)(di|si)3 instruction pattern(s).
8885 ; Left shifts and logical right shifts
8887 (define_expand "<shift><mode>3"
8888 [(set (match_operand:DSI 0 "register_operand" "")
8889 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
8890 (match_operand:SI 2 "nonmemory_operand" "")))]
8894 ; ESA 64 bit register pair shift with reg or imm shift count
8896 (define_insn "*<shift>di3_31<addr_style_op><masked_op>"
8897 [(set (match_operand:DI 0 "register_operand" "=d")
8898 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
8899 (match_operand:SI 2 "nonmemory_operand" "an")))]
8901 "s<lr>dl\t%0,<addr_style_op_ops>"
8902 [(set_attr "op_type" "RS")
8903 (set_attr "atype" "reg")
8904 (set_attr "z196prop" "z196_cracked")])
8907 ; 64 bit register shift with reg or imm shift count
8908 ; sll, srl, sllg, srlg, sllk, srlk
8909 (define_insn "*<shift><mode>3<addr_style_op><masked_op>"
8910 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8911 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8912 (match_operand:SI 2 "nonmemory_operand" "an,an")))]
8915 s<lr>l<g>\t%0,<1><addr_style_op_ops>
8916 s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
8917 [(set_attr "op_type" "RS<E>,RSY")
8918 (set_attr "atype" "reg,reg")
8919 (set_attr "cpu_facility" "*,z196")
8920 (set_attr "z10prop" "z10_super_E1,*")])
8923 ; ashr(di|si)3 instruction pattern(s).
8924 ; Arithmetic right shifts
8926 (define_expand "ashr<mode>3"
8928 [(set (match_operand:DSI 0 "register_operand" "")
8929 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
8930 (match_operand:SI 2 "nonmemory_operand" "")))
8931 (clobber (reg:CC CC_REGNUM))])]
8935 ; FIXME: The number of alternatives is doubled here to match the fix
8936 ; number of 2 in the subst pattern for the (clobber (match_scratch...
8937 ; The right fix should be to support match_scratch in the output
8938 ; pattern of a define_subst.
8939 (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8940 [(set (match_operand:DI 0 "register_operand" "=d, d")
8941 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
8942 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8943 (clobber (reg:CC CC_REGNUM))]
8946 srda\t%0,<addr_style_op_cc_ops>
8947 srda\t%0,<addr_style_op_cc_ops>"
8948 [(set_attr "op_type" "RS")
8949 (set_attr "atype" "reg")])
8953 (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
8954 [(set (match_operand:GPR 0 "register_operand" "=d, d")
8955 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
8956 (match_operand:SI 2 "nonmemory_operand" "an,an")))
8957 (clobber (reg:CC CC_REGNUM))]
8960 sra<g>\t%0,<1><addr_style_op_cc_ops>
8961 sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
8962 [(set_attr "op_type" "RS<E>,RSY")
8963 (set_attr "atype" "reg")
8964 (set_attr "cpu_facility" "*,z196")
8965 (set_attr "z10prop" "z10_super_E1,*")])
8969 ;; Branch instruction patterns.
8972 (define_expand "cbranch<mode>4"
8974 (if_then_else (match_operator 0 "comparison_operator"
8975 [(match_operand:GPR 1 "register_operand" "")
8976 (match_operand:GPR 2 "general_operand" "")])
8977 (label_ref (match_operand 3 "" ""))
8980 "s390_emit_jump (operands[3],
8981 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8984 (define_expand "cbranch<mode>4"
8986 (if_then_else (match_operator 0 "comparison_operator"
8987 [(match_operand:FP 1 "register_operand" "")
8988 (match_operand:FP 2 "general_operand" "")])
8989 (label_ref (match_operand 3 "" ""))
8992 "s390_emit_jump (operands[3],
8993 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2]));
8996 (define_expand "cbranchcc4"
8998 (if_then_else (match_operator 0 "s390_comparison"
8999 [(match_operand 1 "cc_reg_operand" "")
9000 (match_operand 2 "const_int_operand" "")])
9001 (label_ref (match_operand 3 "" ""))
9008 ;;- Conditional jump instructions.
9011 (define_insn "*cjump_64"
9014 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
9015 (match_operand 2 "const_int_operand" "")])
9016 (label_ref (match_operand 0 "" ""))
9020 if (get_attr_length (insn) == 4)
9023 return "jg%C1\t%l0";
9025 [(set_attr "op_type" "RI")
9026 (set_attr "type" "branch")
9027 (set (attr "length")
9028 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9029 (const_int 4) (const_int 6)))])
9031 (define_insn "*cjump_31"
9034 (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
9035 (match_operand 2 "const_int_operand" "")])
9036 (label_ref (match_operand 0 "" ""))
9040 gcc_assert (get_attr_length (insn) == 4);
9043 [(set_attr "op_type" "RI")
9044 (set_attr "type" "branch")
9045 (set (attr "length")
9046 (if_then_else (not (match_test "flag_pic"))
9047 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9048 (const_int 4) (const_int 6))
9049 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9050 (const_int 4) (const_int 8))))])
9052 (define_insn "*cjump_long"
9055 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9056 (match_operand 0 "address_operand" "ZQZR")
9060 if (get_attr_op_type (insn) == OP_TYPE_RR)
9065 [(set (attr "op_type")
9066 (if_then_else (match_operand 0 "register_operand" "")
9067 (const_string "RR") (const_string "RX")))
9068 (set_attr "type" "branch")
9069 (set_attr "atype" "agen")])
9071 ;; A conditional return instruction.
9072 (define_insn "*c<code>"
9075 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9078 "s390_can_use_<code>_insn ()"
9080 [(set_attr "op_type" "RR")
9081 (set_attr "type" "jsr")
9082 (set_attr "atype" "agen")])
9085 ;;- Negated conditional jump instructions.
9088 (define_insn "*icjump_64"
9091 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9093 (label_ref (match_operand 0 "" ""))))]
9096 if (get_attr_length (insn) == 4)
9099 return "jg%D1\t%l0";
9101 [(set_attr "op_type" "RI")
9102 (set_attr "type" "branch")
9103 (set (attr "length")
9104 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9105 (const_int 4) (const_int 6)))])
9107 (define_insn "*icjump_31"
9110 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9112 (label_ref (match_operand 0 "" ""))))]
9115 gcc_assert (get_attr_length (insn) == 4);
9118 [(set_attr "op_type" "RI")
9119 (set_attr "type" "branch")
9120 (set (attr "length")
9121 (if_then_else (not (match_test "flag_pic"))
9122 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9123 (const_int 4) (const_int 6))
9124 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9125 (const_int 4) (const_int 8))))])
9127 (define_insn "*icjump_long"
9130 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
9132 (match_operand 0 "address_operand" "ZQZR")))]
9135 if (get_attr_op_type (insn) == OP_TYPE_RR)
9140 [(set (attr "op_type")
9141 (if_then_else (match_operand 0 "register_operand" "")
9142 (const_string "RR") (const_string "RX")))
9143 (set_attr "type" "branch")
9144 (set_attr "atype" "agen")])
9147 ;;- Trap instructions.
9151 [(trap_if (const_int 1) (const_int 0))]
9154 [(set_attr "op_type" "RI")
9155 (set_attr "type" "branch")])
9157 (define_expand "ctrap<mode>4"
9158 [(trap_if (match_operator 0 "comparison_operator"
9159 [(match_operand:GPR 1 "register_operand" "")
9160 (match_operand:GPR 2 "general_operand" "")])
9161 (match_operand 3 "const0_operand" ""))]
9164 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
9165 operands[1], operands[2]);
9166 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9170 (define_expand "ctrap<mode>4"
9171 [(trap_if (match_operator 0 "comparison_operator"
9172 [(match_operand:FP 1 "register_operand" "")
9173 (match_operand:FP 2 "general_operand" "")])
9174 (match_operand 3 "const0_operand" ""))]
9177 rtx cond = s390_emit_compare (GET_CODE (operands[0]),
9178 operands[1], operands[2]);
9179 emit_insn (gen_condtrap (cond, XEXP (cond, 0)));
9183 (define_insn "condtrap"
9184 [(trap_if (match_operator 0 "s390_comparison"
9185 [(match_operand 1 "cc_reg_operand" "c")
9190 [(set_attr "op_type" "RI")
9191 (set_attr "type" "branch")])
9193 ; crt, cgrt, cit, cgit
9194 (define_insn "*cmp_and_trap_signed_int<mode>"
9195 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
9196 [(match_operand:GPR 1 "register_operand" "d,d")
9197 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
9203 [(set_attr "op_type" "RRF,RIE")
9204 (set_attr "type" "branch")
9205 (set_attr "z10prop" "z10_super_c,z10_super")])
9207 ; clrt, clgrt, clfit, clgit, clt, clgt
9208 (define_insn "*cmp_and_trap_unsigned_int<mode>"
9209 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
9210 [(match_operand:GPR 1 "register_operand" "d,d,d")
9211 (match_operand:GPR 2 "general_operand" "d,D,T")])
9218 [(set_attr "op_type" "RRF,RIE,RSY")
9219 (set_attr "type" "branch")
9220 (set_attr "z10prop" "z10_super_c,z10_super,*")
9221 (set_attr "cpu_facility" "z10,z10,zEC12")])
9224 (define_insn "*load_and_trap<mode>"
9225 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
9228 (set (match_operand:GPR 1 "register_operand" "=d")
9232 [(set_attr "op_type" "RXY")])
9236 ;;- Loop instructions.
9238 ;; This is all complicated by the fact that since this is a jump insn
9239 ;; we must handle our own output reloads.
9243 ; This splitter will be matched by combine and has to add the 2 moves
9244 ; necessary to load the compare and the increment values into a
9245 ; register pair as needed by brxle.
9247 (define_insn_and_split "*brx_stage1_<GPR:mode>"
9250 (match_operator 6 "s390_brx_operator"
9251 [(plus:GPR (match_operand:GPR 1 "register_operand" "")
9252 (match_operand:GPR 2 "general_operand" ""))
9253 (match_operand:GPR 3 "register_operand" "")])
9254 (label_ref (match_operand 0 "" ""))
9256 (set (match_operand:GPR 4 "nonimmediate_operand" "")
9257 (plus:GPR (match_dup 1) (match_dup 2)))
9258 (clobber (match_scratch:GPR 5 ""))]
9261 "!reload_completed && !reload_in_progress"
9262 [(set (match_dup 7) (match_dup 2)) ; the increment
9263 (set (match_dup 8) (match_dup 3)) ; the comparison value
9264 (parallel [(set (pc)
9267 [(plus:GPR (match_dup 1) (match_dup 7))
9269 (label_ref (match_dup 0))
9272 (plus:GPR (match_dup 1) (match_dup 7)))
9273 (clobber (match_dup 5))
9274 (clobber (reg:CC CC_REGNUM))])]
9276 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode);
9277 operands[7] = gen_lowpart (<GPR:MODE>mode,
9278 gen_highpart (word_mode, dreg));
9279 operands[8] = gen_lowpart (<GPR:MODE>mode,
9280 gen_lowpart (word_mode, dreg));
9285 (define_insn_and_split "*brxg_64bit"
9288 (match_operator 5 "s390_brx_operator"
9289 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d")
9290 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0))
9291 (subreg:DI (match_dup 2) 8)])
9292 (label_ref (match_operand 0 "" ""))
9294 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X")
9295 (plus:DI (match_dup 1)
9296 (subreg:DI (match_dup 2) 0)))
9297 (clobber (match_scratch:DI 4 "=X,&1,&?d"))
9298 (clobber (reg:CC CC_REGNUM))]
9301 if (which_alternative != 0)
9303 else if (get_attr_length (insn) == 6)
9304 return "brx%E5g\t%1,%2,%l0";
9306 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0";
9308 "&& reload_completed
9309 && (!REG_P (operands[3])
9310 || !rtx_equal_p (operands[1], operands[3]))"
9311 [(set (match_dup 4) (match_dup 1))
9312 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0)))
9313 (clobber (reg:CC CC_REGNUM))])
9314 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8)))
9315 (set (match_dup 3) (match_dup 4))
9316 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9317 (label_ref (match_dup 0))
9320 [(set_attr "op_type" "RIE")
9321 (set_attr "type" "branch")
9322 (set (attr "length")
9323 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9324 (const_int 6) (const_int 16)))])
9328 (define_insn_and_split "*brx_64bit"
9331 (match_operator 5 "s390_brx_operator"
9332 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9333 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4))
9334 (subreg:SI (match_dup 2) 12)])
9335 (label_ref (match_operand 0 "" ""))
9337 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9338 (plus:SI (match_dup 1)
9339 (subreg:SI (match_dup 2) 4)))
9340 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9341 (clobber (reg:CC CC_REGNUM))]
9344 if (which_alternative != 0)
9346 else if (get_attr_length (insn) == 6)
9347 return "brx%C5\t%1,%2,%l0";
9349 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9351 "&& reload_completed
9352 && (!REG_P (operands[3])
9353 || !rtx_equal_p (operands[1], operands[3]))"
9354 [(set (match_dup 4) (match_dup 1))
9355 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4)))
9356 (clobber (reg:CC CC_REGNUM))])
9357 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12)))
9358 (set (match_dup 3) (match_dup 4))
9359 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9360 (label_ref (match_dup 0))
9363 [(set_attr "op_type" "RSI")
9364 (set_attr "type" "branch")
9365 (set (attr "length")
9366 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9367 (const_int 6) (const_int 14)))])
9371 (define_insn_and_split "*brx_31bit"
9374 (match_operator 5 "s390_brx_operator"
9375 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d")
9376 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0))
9377 (subreg:SI (match_dup 2) 4)])
9378 (label_ref (match_operand 0 "" ""))
9380 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X")
9381 (plus:SI (match_dup 1)
9382 (subreg:SI (match_dup 2) 0)))
9383 (clobber (match_scratch:SI 4 "=X,&1,&?d"))
9384 (clobber (reg:CC CC_REGNUM))]
9385 "!TARGET_ZARCH && TARGET_CPU_ZARCH"
9387 if (which_alternative != 0)
9389 else if (get_attr_length (insn) == 6)
9390 return "brx%C5\t%1,%2,%l0";
9392 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0";
9394 "&& reload_completed
9395 && (!REG_P (operands[3])
9396 || !rtx_equal_p (operands[1], operands[3]))"
9397 [(set (match_dup 4) (match_dup 1))
9398 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0)))
9399 (clobber (reg:CC CC_REGNUM))])
9400 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4)))
9401 (set (match_dup 3) (match_dup 4))
9402 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)])
9403 (label_ref (match_dup 0))
9406 [(set_attr "op_type" "RSI")
9407 (set_attr "type" "branch")
9408 (set (attr "length")
9409 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9410 (const_int 6) (const_int 14)))])
9415 (define_expand "doloop_end"
9416 [(use (match_operand 0 "" "")) ; loop pseudo
9417 (use (match_operand 1 "" ""))] ; label
9420 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
9421 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
9422 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
9423 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
9424 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
9425 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
9432 (define_insn_and_split "doloop_si64"
9435 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9437 (label_ref (match_operand 0 "" ""))
9439 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9440 (plus:SI (match_dup 1) (const_int -1)))
9441 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9442 (clobber (reg:CC CC_REGNUM))]
9445 if (which_alternative != 0)
9447 else if (get_attr_length (insn) == 4)
9448 return "brct\t%1,%l0";
9450 return "ahi\t%1,-1\;jgne\t%l0";
9452 "&& reload_completed
9453 && (! REG_P (operands[2])
9454 || ! rtx_equal_p (operands[1], operands[2]))"
9455 [(set (match_dup 3) (match_dup 1))
9456 (parallel [(set (reg:CCAN CC_REGNUM)
9457 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9459 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9460 (set (match_dup 2) (match_dup 3))
9461 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9462 (label_ref (match_dup 0))
9465 [(set_attr "op_type" "RI")
9466 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9467 ; hurt us in the (rare) case of ahi.
9468 (set_attr "z10prop" "z10_super_E1")
9469 (set_attr "type" "branch")
9470 (set (attr "length")
9471 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9472 (const_int 4) (const_int 10)))])
9474 (define_insn_and_split "doloop_si31"
9477 (ne (match_operand:SI 1 "register_operand" "d,d,d")
9479 (label_ref (match_operand 0 "" ""))
9481 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
9482 (plus:SI (match_dup 1) (const_int -1)))
9483 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
9484 (clobber (reg:CC CC_REGNUM))]
9487 if (which_alternative != 0)
9489 else if (get_attr_length (insn) == 4)
9490 return "brct\t%1,%l0";
9494 "&& reload_completed
9495 && (! REG_P (operands[2])
9496 || ! rtx_equal_p (operands[1], operands[2]))"
9497 [(set (match_dup 3) (match_dup 1))
9498 (parallel [(set (reg:CCAN CC_REGNUM)
9499 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
9501 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9502 (set (match_dup 2) (match_dup 3))
9503 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9504 (label_ref (match_dup 0))
9507 [(set_attr "op_type" "RI")
9508 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9509 ; hurt us in the (rare) case of ahi.
9510 (set_attr "z10prop" "z10_super_E1")
9511 (set_attr "type" "branch")
9512 (set (attr "length")
9513 (if_then_else (not (match_test "flag_pic"))
9514 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9515 (const_int 4) (const_int 6))
9516 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9517 (const_int 4) (const_int 8))))])
9519 (define_insn "*doloop_si_long"
9522 (ne (match_operand:SI 1 "register_operand" "d")
9524 (match_operand 0 "address_operand" "ZR")
9526 (set (match_operand:SI 2 "register_operand" "=1")
9527 (plus:SI (match_dup 1) (const_int -1)))
9528 (clobber (match_scratch:SI 3 "=X"))
9529 (clobber (reg:CC CC_REGNUM))]
9532 if (get_attr_op_type (insn) == OP_TYPE_RR)
9533 return "bctr\t%1,%0";
9535 return "bct\t%1,%a0";
9537 [(set (attr "op_type")
9538 (if_then_else (match_operand 0 "register_operand" "")
9539 (const_string "RR") (const_string "RX")))
9540 (set_attr "type" "branch")
9541 (set_attr "atype" "agen")
9542 (set_attr "z10prop" "z10_c")
9543 (set_attr "z196prop" "z196_cracked")])
9545 (define_insn_and_split "doloop_di"
9548 (ne (match_operand:DI 1 "register_operand" "d,d,d")
9550 (label_ref (match_operand 0 "" ""))
9552 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
9553 (plus:DI (match_dup 1) (const_int -1)))
9554 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
9555 (clobber (reg:CC CC_REGNUM))]
9558 if (which_alternative != 0)
9560 else if (get_attr_length (insn) == 4)
9561 return "brctg\t%1,%l0";
9563 return "aghi\t%1,-1\;jgne\t%l0";
9565 "&& reload_completed
9566 && (! REG_P (operands[2])
9567 || ! rtx_equal_p (operands[1], operands[2]))"
9568 [(set (match_dup 3) (match_dup 1))
9569 (parallel [(set (reg:CCAN CC_REGNUM)
9570 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
9572 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
9573 (set (match_dup 2) (match_dup 3))
9574 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
9575 (label_ref (match_dup 0))
9578 [(set_attr "op_type" "RI")
9579 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
9580 ; hurt us in the (rare) case of ahi.
9581 (set_attr "z10prop" "z10_super_E1")
9582 (set_attr "type" "branch")
9583 (set (attr "length")
9584 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9585 (const_int 4) (const_int 10)))])
9588 ;;- Unconditional jump instructions.
9592 ; jump instruction pattern(s).
9595 (define_expand "jump"
9596 [(match_operand 0 "" "")]
9598 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
9600 (define_insn "*jump64"
9601 [(set (pc) (label_ref (match_operand 0 "" "")))]
9604 if (get_attr_length (insn) == 4)
9609 [(set_attr "op_type" "RI")
9610 (set_attr "type" "branch")
9611 (set (attr "length")
9612 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9613 (const_int 4) (const_int 6)))])
9615 (define_insn "*jump31"
9616 [(set (pc) (label_ref (match_operand 0 "" "")))]
9619 gcc_assert (get_attr_length (insn) == 4);
9622 [(set_attr "op_type" "RI")
9623 (set_attr "type" "branch")
9624 (set (attr "length")
9625 (if_then_else (not (match_test "flag_pic"))
9626 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9627 (const_int 4) (const_int 6))
9628 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
9629 (const_int 4) (const_int 8))))])
9632 ; indirect-jump instruction pattern(s).
9635 (define_expand "indirect_jump"
9636 [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
9639 if (address_operand (operands[0], GET_MODE (operands[0])))
9641 else if (TARGET_ARCH12
9642 && GET_MODE (operands[0]) == Pmode
9643 && memory_operand (operands[0], Pmode))
9646 operands[0] = force_reg (Pmode, operands[0]);
9649 ; The first constraint must be an "extra address constraint" in order
9650 ; to trigger address reloading in LRA/reload
9651 (define_insn "*indirect_jump"
9653 (match_operand 0 "address_operand" "ZR,a"))]
9658 [(set_attr "op_type" "RX,RR")
9659 (set_attr "type" "branch")
9660 (set_attr "atype" "agen")
9661 (set_attr "cpu_facility" "*")])
9663 ; FIXME: LRA does not appear to be able to deal with MEMs being
9664 ; checked against address constraints like ZR above. So make this a
9665 ; separate pattern for now.
9666 (define_insn "*indirect2_jump"
9668 (match_operand 0 "nonimmediate_operand" "a,T"))]
9673 [(set_attr "op_type" "RR,RXY")
9674 (set_attr "type" "branch")
9675 (set_attr "atype" "agen")
9676 (set_attr "cpu_facility" "*,arch12")])
9679 ; casesi instruction pattern(s).
9682 (define_insn "casesi_jump"
9683 [(set (pc) (match_operand 0 "address_operand" "ZR"))
9684 (use (label_ref (match_operand 1 "" "")))]
9687 if (get_attr_op_type (insn) == OP_TYPE_RR)
9692 [(set (attr "op_type")
9693 (if_then_else (match_operand 0 "register_operand" "")
9694 (const_string "RR") (const_string "RX")))
9695 (set_attr "type" "branch")
9696 (set_attr "atype" "agen")])
9698 (define_expand "casesi"
9699 [(match_operand:SI 0 "general_operand" "")
9700 (match_operand:SI 1 "general_operand" "")
9701 (match_operand:SI 2 "general_operand" "")
9702 (label_ref (match_operand 3 "" ""))
9703 (label_ref (match_operand 4 "" ""))]
9706 rtx index = gen_reg_rtx (SImode);
9707 rtx base = gen_reg_rtx (Pmode);
9708 rtx target = gen_reg_rtx (Pmode);
9710 emit_move_insn (index, operands[0]);
9711 emit_insn (gen_subsi3 (index, index, operands[1]));
9712 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
9715 if (Pmode != SImode)
9716 index = convert_to_mode (Pmode, index, 1);
9717 if (GET_CODE (index) != REG)
9718 index = copy_to_mode_reg (Pmode, index);
9721 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
9723 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
9725 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
9727 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
9728 emit_move_insn (target, index);
9731 target = gen_rtx_PLUS (Pmode, base, target);
9732 emit_jump_insn (gen_casesi_jump (target, operands[3]));
9739 ;;- Jump to subroutine.
9744 ; untyped call instruction pattern(s).
9747 ;; Call subroutine returning any type.
9748 (define_expand "untyped_call"
9749 [(parallel [(call (match_operand 0 "" "")
9751 (match_operand 1 "" "")
9752 (match_operand 2 "" "")])]
9757 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
9759 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9761 rtx set = XVECEXP (operands[2], 0, i);
9762 emit_move_insn (SET_DEST (set), SET_SRC (set));
9765 /* The optimizer does not know that the call sets the function value
9766 registers we stored in the result block. We avoid problems by
9767 claiming that all hard registers are used and clobbered at this
9769 emit_insn (gen_blockage ());
9774 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9775 ;; all of memory. This blocks insns from being moved across this point.
9777 (define_insn "blockage"
9778 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
9781 [(set_attr "type" "none")
9782 (set_attr "length" "0")])
9788 (define_expand "sibcall"
9789 [(call (match_operand 0 "" "")
9790 (match_operand 1 "" ""))]
9793 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
9797 (define_insn "*sibcall_br"
9798 [(call (mem:QI (reg SIBCALL_REGNUM))
9799 (match_operand 0 "const_int_operand" "n"))]
9800 "SIBLING_CALL_P (insn)
9801 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
9803 [(set_attr "op_type" "RR")
9804 (set_attr "type" "branch")
9805 (set_attr "atype" "agen")])
9807 (define_insn "*sibcall_brc"
9808 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9809 (match_operand 1 "const_int_operand" "n"))]
9810 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9812 [(set_attr "op_type" "RI")
9813 (set_attr "type" "branch")])
9815 (define_insn "*sibcall_brcl"
9816 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9817 (match_operand 1 "const_int_operand" "n"))]
9818 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9820 [(set_attr "op_type" "RIL")
9821 (set_attr "type" "branch")])
9824 ; sibcall_value patterns
9827 (define_expand "sibcall_value"
9828 [(set (match_operand 0 "" "")
9829 (call (match_operand 1 "" "")
9830 (match_operand 2 "" "")))]
9833 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
9837 (define_insn "*sibcall_value_br"
9838 [(set (match_operand 0 "" "")
9839 (call (mem:QI (reg SIBCALL_REGNUM))
9840 (match_operand 1 "const_int_operand" "n")))]
9841 "SIBLING_CALL_P (insn)
9842 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
9844 [(set_attr "op_type" "RR")
9845 (set_attr "type" "branch")
9846 (set_attr "atype" "agen")])
9848 (define_insn "*sibcall_value_brc"
9849 [(set (match_operand 0 "" "")
9850 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9851 (match_operand 2 "const_int_operand" "n")))]
9852 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
9854 [(set_attr "op_type" "RI")
9855 (set_attr "type" "branch")])
9857 (define_insn "*sibcall_value_brcl"
9858 [(set (match_operand 0 "" "")
9859 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9860 (match_operand 2 "const_int_operand" "n")))]
9861 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
9863 [(set_attr "op_type" "RIL")
9864 (set_attr "type" "branch")])
9868 ; call instruction pattern(s).
9871 (define_expand "call"
9872 [(call (match_operand 0 "" "")
9873 (match_operand 1 "" ""))
9874 (use (match_operand 2 "" ""))]
9877 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
9878 gen_rtx_REG (Pmode, RETURN_REGNUM));
9882 (define_insn "*bras"
9883 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9884 (match_operand 1 "const_int_operand" "n"))
9885 (clobber (match_operand 2 "register_operand" "=r"))]
9886 "!SIBLING_CALL_P (insn)
9887 && TARGET_SMALL_EXEC
9888 && GET_MODE (operands[2]) == Pmode"
9890 [(set_attr "op_type" "RI")
9891 (set_attr "type" "jsr")
9892 (set_attr "z196prop" "z196_cracked")])
9894 (define_insn "*brasl"
9895 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
9896 (match_operand 1 "const_int_operand" "n"))
9897 (clobber (match_operand 2 "register_operand" "=r"))]
9898 "!SIBLING_CALL_P (insn)
9900 && GET_MODE (operands[2]) == Pmode"
9902 [(set_attr "op_type" "RIL")
9903 (set_attr "type" "jsr")
9904 (set_attr "z196prop" "z196_cracked")])
9906 (define_insn "*basr"
9907 [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
9908 (match_operand 1 "const_int_operand" "n"))
9909 (clobber (match_operand 2 "register_operand" "=r"))]
9910 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
9912 if (get_attr_op_type (insn) == OP_TYPE_RR)
9913 return "basr\t%2,%0";
9915 return "bas\t%2,%a0";
9917 [(set (attr "op_type")
9918 (if_then_else (match_operand 0 "register_operand" "")
9919 (const_string "RR") (const_string "RX")))
9920 (set_attr "type" "jsr")
9921 (set_attr "atype" "agen")
9922 (set_attr "z196prop" "z196_cracked")])
9925 ; call_value instruction pattern(s).
9928 (define_expand "call_value"
9929 [(set (match_operand 0 "" "")
9930 (call (match_operand 1 "" "")
9931 (match_operand 2 "" "")))
9932 (use (match_operand 3 "" ""))]
9935 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
9936 gen_rtx_REG (Pmode, RETURN_REGNUM));
9940 (define_insn "*bras_r"
9941 [(set (match_operand 0 "" "")
9942 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9943 (match_operand:SI 2 "const_int_operand" "n")))
9944 (clobber (match_operand 3 "register_operand" "=r"))]
9945 "!SIBLING_CALL_P (insn)
9946 && TARGET_SMALL_EXEC
9947 && GET_MODE (operands[3]) == Pmode"
9949 [(set_attr "op_type" "RI")
9950 (set_attr "type" "jsr")
9951 (set_attr "z196prop" "z196_cracked")])
9953 (define_insn "*brasl_r"
9954 [(set (match_operand 0 "" "")
9955 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
9956 (match_operand 2 "const_int_operand" "n")))
9957 (clobber (match_operand 3 "register_operand" "=r"))]
9958 "!SIBLING_CALL_P (insn)
9960 && GET_MODE (operands[3]) == Pmode"
9962 [(set_attr "op_type" "RIL")
9963 (set_attr "type" "jsr")
9964 (set_attr "z196prop" "z196_cracked")])
9966 (define_insn "*basr_r"
9967 [(set (match_operand 0 "" "")
9968 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
9969 (match_operand 2 "const_int_operand" "n")))
9970 (clobber (match_operand 3 "register_operand" "=r"))]
9971 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
9973 if (get_attr_op_type (insn) == OP_TYPE_RR)
9974 return "basr\t%3,%1";
9976 return "bas\t%3,%a1";
9978 [(set (attr "op_type")
9979 (if_then_else (match_operand 1 "register_operand" "")
9980 (const_string "RR") (const_string "RX")))
9981 (set_attr "type" "jsr")
9982 (set_attr "atype" "agen")
9983 (set_attr "z196prop" "z196_cracked")])
9986 ;;- Thread-local storage support.
9989 (define_expand "get_thread_pointer<mode>"
9990 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))]
9994 (define_expand "set_thread_pointer<mode>"
9995 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" ""))
9996 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))]
10000 (define_insn "*set_tp"
10001 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
10004 [(set_attr "type" "none")
10005 (set_attr "length" "0")])
10007 (define_insn "*tls_load_64"
10008 [(set (match_operand:DI 0 "register_operand" "=d")
10009 (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
10010 (match_operand:DI 2 "" "")]
10014 [(set_attr "op_type" "RXE")
10015 (set_attr "z10prop" "z10_fwd_A3")])
10017 (define_insn "*tls_load_31"
10018 [(set (match_operand:SI 0 "register_operand" "=d,d")
10019 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
10020 (match_operand:SI 2 "" "")]
10026 [(set_attr "op_type" "RX,RXY")
10027 (set_attr "type" "load")
10028 (set_attr "cpu_facility" "*,longdisp")
10029 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
10031 (define_insn "*bras_tls"
10032 [(set (match_operand 0 "" "")
10033 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10034 (match_operand 2 "const_int_operand" "n")))
10035 (clobber (match_operand 3 "register_operand" "=r"))
10036 (use (match_operand 4 "" ""))]
10037 "!SIBLING_CALL_P (insn)
10038 && TARGET_SMALL_EXEC
10039 && GET_MODE (operands[3]) == Pmode"
10041 [(set_attr "op_type" "RI")
10042 (set_attr "type" "jsr")
10043 (set_attr "z196prop" "z196_cracked")])
10045 (define_insn "*brasl_tls"
10046 [(set (match_operand 0 "" "")
10047 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
10048 (match_operand 2 "const_int_operand" "n")))
10049 (clobber (match_operand 3 "register_operand" "=r"))
10050 (use (match_operand 4 "" ""))]
10051 "!SIBLING_CALL_P (insn)
10052 && TARGET_CPU_ZARCH
10053 && GET_MODE (operands[3]) == Pmode"
10055 [(set_attr "op_type" "RIL")
10056 (set_attr "type" "jsr")
10057 (set_attr "z196prop" "z196_cracked")])
10059 (define_insn "*basr_tls"
10060 [(set (match_operand 0 "" "")
10061 (call (mem:QI (match_operand 1 "address_operand" "ZR"))
10062 (match_operand 2 "const_int_operand" "n")))
10063 (clobber (match_operand 3 "register_operand" "=r"))
10064 (use (match_operand 4 "" ""))]
10065 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
10067 if (get_attr_op_type (insn) == OP_TYPE_RR)
10068 return "basr\t%3,%1%J4";
10070 return "bas\t%3,%a1%J4";
10072 [(set (attr "op_type")
10073 (if_then_else (match_operand 1 "register_operand" "")
10074 (const_string "RR") (const_string "RX")))
10075 (set_attr "type" "jsr")
10076 (set_attr "atype" "agen")
10077 (set_attr "z196prop" "z196_cracked")])
10080 ;;- Atomic operations
10084 ; memory barrier patterns.
10087 (define_expand "mem_thread_fence"
10088 [(match_operand:SI 0 "const_int_operand")] ;; model
10091 /* Unless this is a SEQ_CST fence, the s390 memory model is strong
10092 enough not to require barriers of any kind. */
10093 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
10095 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
10096 MEM_VOLATILE_P (mem) = 1;
10097 emit_insn (gen_mem_thread_fence_1 (mem));
10102 ; Although bcr is superscalar on Z10, this variant will never
10103 ; become part of an execution group.
10104 ; With z196 we can make use of the fast-BCR-serialization facility.
10105 ; This allows for a slightly faster sync which is sufficient for our
10107 (define_insn "mem_thread_fence_1"
10108 [(set (match_operand:BLK 0 "" "")
10109 (unspec:BLK [(match_dup 0)] UNSPEC_MB))]
10113 return "bcr\t14,0";
10115 return "bcr\t15,0";
10117 [(set_attr "op_type" "RR")
10118 (set_attr "mnemonic" "bcr_flush")
10119 (set_attr "z196prop" "z196_alone")])
10122 ; atomic load/store operations
10125 ; Atomic loads need not examine the memory model at all.
10126 (define_expand "atomic_load<mode>"
10127 [(match_operand:DINT 0 "register_operand") ;; output
10128 (match_operand:DINT 1 "memory_operand") ;; memory
10129 (match_operand:SI 2 "const_int_operand")] ;; model
10132 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10135 if (<MODE>mode == TImode)
10136 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1]));
10137 else if (<MODE>mode == DImode && !TARGET_ZARCH)
10138 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
10140 emit_move_insn (operands[0], operands[1]);
10144 ; Different from movdi_31 in that we want no splitters.
10145 (define_insn "atomic_loaddi_1"
10146 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f")
10147 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")]
10155 [(set_attr "op_type" "RS,RSY,RS,RSY")
10156 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10157 (set_attr "type" "lm,lm,floaddf,floaddf")])
10159 (define_insn "atomic_loadti_1"
10160 [(set (match_operand:TI 0 "register_operand" "=r")
10161 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
10165 [(set_attr "op_type" "RXY")
10166 (set_attr "type" "other")])
10168 ; Atomic stores must(?) enforce sequential consistency.
10169 (define_expand "atomic_store<mode>"
10170 [(match_operand:DINT 0 "memory_operand") ;; memory
10171 (match_operand:DINT 1 "register_operand") ;; input
10172 (match_operand:SI 2 "const_int_operand")] ;; model
10175 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
10177 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0])))
10180 if (<MODE>mode == TImode)
10181 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1]));
10182 else if (<MODE>mode == DImode && !TARGET_ZARCH)
10183 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
10185 emit_move_insn (operands[0], operands[1]);
10186 if (is_mm_seq_cst (model))
10187 emit_insn (gen_mem_thread_fence (operands[2]));
10191 ; Different from movdi_31 in that we want no splitters.
10192 (define_insn "atomic_storedi_1"
10193 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T")
10194 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")]
10202 [(set_attr "op_type" "RS,RSY,RS,RSY")
10203 (set_attr "cpu_facility" "*,longdisp,*,longdisp")
10204 (set_attr "type" "stm,stm,fstoredf,fstoredf")])
10206 (define_insn "atomic_storeti_1"
10207 [(set (match_operand:TI 0 "memory_operand" "=T")
10208 (unspec:TI [(match_operand:TI 1 "register_operand" "r")]
10212 [(set_attr "op_type" "RXY")
10213 (set_attr "type" "other")])
10216 ; compare and swap patterns.
10219 (define_expand "atomic_compare_and_swap<mode>"
10220 [(match_operand:SI 0 "register_operand") ;; bool success output
10221 (match_operand:DINT 1 "nonimmediate_operand");; oldval output
10222 (match_operand:DINT 2 "s_operand") ;; memory
10223 (match_operand:DINT 3 "general_operand") ;; expected intput
10224 (match_operand:DINT 4 "general_operand") ;; newval intput
10225 (match_operand:SI 5 "const_int_operand") ;; is_weak
10226 (match_operand:SI 6 "const_int_operand") ;; success model
10227 (match_operand:SI 7 "const_int_operand")] ;; failure model
10230 if (GET_MODE_BITSIZE (<MODE>mode) >= 16
10231 && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2]))
10234 s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2],
10235 operands[3], operands[4], INTVAL (operands[5]));
10238 (define_expand "atomic_compare_and_swap<mode>_internal"
10240 [(set (match_operand:DGPR 0 "register_operand")
10241 (match_operand:DGPR 1 "s_operand"))
10243 (unspec_volatile:DGPR
10245 (match_operand:DGPR 2 "register_operand")
10246 (match_operand:DGPR 3 "register_operand")]
10248 (set (match_operand 4 "cc_reg_operand")
10250 "GET_MODE (operands[4]) == CCZmode
10251 || GET_MODE (operands[4]) == CCZ1mode"
10254 = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]);
10258 (define_insn "*atomic_compare_and_swap<mode>_1"
10259 [(set (match_operand:TDI 0 "register_operand" "=r")
10260 (match_operand:TDI 1 "memory_operand" "+S"))
10262 (unspec_volatile:TDI
10264 (match_operand:TDI 2 "register_operand" "0")
10265 (match_operand:TDI 3 "register_operand" "r")]
10267 (set (reg CC_REGNUM)
10268 (compare (match_dup 1) (match_dup 2)))]
10270 && s390_match_ccmode (insn, CCZ1mode)"
10271 "c<td>sg\t%0,%3,%S1"
10272 [(set_attr "op_type" "RSY")
10273 (set_attr "type" "sem")])
10276 (define_insn "*atomic_compare_and_swapdi_2"
10277 [(set (match_operand:DI 0 "register_operand" "=r,r")
10278 (match_operand:DI 1 "memory_operand" "+Q,S"))
10280 (unspec_volatile:DI
10282 (match_operand:DI 2 "register_operand" "0,0")
10283 (match_operand:DI 3 "register_operand" "r,r")]
10285 (set (reg CC_REGNUM)
10286 (compare (match_dup 1) (match_dup 2)))]
10288 && s390_match_ccmode (insn, CCZ1mode)"
10292 [(set_attr "op_type" "RS,RSY")
10293 (set_attr "cpu_facility" "*,longdisp")
10294 (set_attr "type" "sem")])
10297 (define_insn "*atomic_compare_and_swapsi_3"
10298 [(set (match_operand:SI 0 "register_operand" "=r,r")
10299 (match_operand:SI 1 "memory_operand" "+Q,S"))
10301 (unspec_volatile:SI
10303 (match_operand:SI 2 "register_operand" "0,0")
10304 (match_operand:SI 3 "register_operand" "r,r")]
10306 (set (reg CC_REGNUM)
10307 (compare (match_dup 1) (match_dup 2)))]
10308 "s390_match_ccmode (insn, CCZ1mode)"
10312 [(set_attr "op_type" "RS,RSY")
10313 (set_attr "cpu_facility" "*,longdisp")
10314 (set_attr "type" "sem")])
10317 ; Other atomic instruction patterns.
10320 ; z196 load and add, xor, or and and instructions
10322 (define_expand "atomic_fetch_<atomic><mode>"
10323 [(match_operand:GPR 0 "register_operand") ;; val out
10325 (match_operand:GPR 1 "memory_operand") ;; memory
10326 (match_operand:GPR 2 "register_operand")) ;; val in
10327 (match_operand:SI 3 "const_int_operand")] ;; model
10330 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1])))
10333 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf
10334 (operands[0], operands[1], operands[2]));
10338 ; lan, lang, lao, laog, lax, laxg, laa, laag
10339 (define_insn "atomic_fetch_<atomic><mode>_iaf"
10340 [(set (match_operand:GPR 0 "register_operand" "=d")
10341 (match_operand:GPR 1 "memory_operand" "+S"))
10343 (unspec_volatile:GPR
10344 [(ATOMIC_Z196:GPR (match_dup 1)
10345 (match_operand:GPR 2 "general_operand" "d"))]
10346 UNSPECV_ATOMIC_OP))
10347 (clobber (reg:CC CC_REGNUM))]
10349 "la<noxa><g>\t%0,%2,%1"
10350 [(set_attr "op_type" "RSY")
10351 (set_attr "type" "sem")])
10353 ;; For SImode and larger, the optabs.c code will do just fine in
10354 ;; expanding a compare-and-swap loop. For QI/HImode, we can do
10355 ;; better by expanding our own loop.
10357 (define_expand "atomic_<atomic><mode>"
10359 (match_operand:HQI 0 "memory_operand") ;; memory
10360 (match_operand:HQI 1 "general_operand")) ;; val in
10361 (match_operand:SI 2 "const_int_operand")] ;; model
10364 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
10365 operands[1], false);
10369 (define_expand "atomic_fetch_<atomic><mode>"
10370 [(match_operand:HQI 0 "register_operand") ;; val out
10372 (match_operand:HQI 1 "memory_operand") ;; memory
10373 (match_operand:HQI 2 "general_operand")) ;; val in
10374 (match_operand:SI 3 "const_int_operand")] ;; model
10377 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10378 operands[2], false);
10382 (define_expand "atomic_<atomic>_fetch<mode>"
10383 [(match_operand:HQI 0 "register_operand") ;; val out
10385 (match_operand:HQI 1 "memory_operand") ;; memory
10386 (match_operand:HQI 2 "general_operand")) ;; val in
10387 (match_operand:SI 3 "const_int_operand")] ;; model
10390 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
10391 operands[2], true);
10395 ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code
10396 ;; generated by the middleend is not good.
10397 (define_expand "atomic_exchange<mode>"
10398 [(match_operand:DINT 0 "register_operand") ;; val out
10399 (match_operand:DINT 1 "s_operand") ;; memory
10400 (match_operand:DINT 2 "general_operand") ;; val in
10401 (match_operand:SI 3 "const_int_operand")] ;; model
10404 if (<MODE>mode != QImode
10405 && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode))
10407 if (<MODE>mode == HImode || <MODE>mode == QImode)
10408 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2],
10410 else if (<MODE>mode == SImode || TARGET_ZARCH)
10411 s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]);
10418 ;;- Miscellaneous instructions.
10422 ; allocate stack instruction pattern(s).
10425 (define_expand "allocate_stack"
10426 [(match_operand 0 "general_operand" "")
10427 (match_operand 1 "general_operand" "")]
10430 rtx temp = gen_reg_rtx (Pmode);
10432 emit_move_insn (temp, s390_back_chain_rtx ());
10433 anti_adjust_stack (operands[1]);
10434 emit_move_insn (s390_back_chain_rtx (), temp);
10436 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10442 ; setjmp instruction pattern.
10445 (define_expand "builtin_setjmp_receiver"
10446 [(match_operand 0 "" "")]
10449 emit_insn (s390_load_got ());
10450 emit_use (pic_offset_table_rtx);
10454 ;; These patterns say how to save and restore the stack pointer. We need not
10455 ;; save the stack pointer at function level since we are careful to
10456 ;; preserve the backchain. At block level, we have to restore the backchain
10457 ;; when we restore the stack pointer.
10459 ;; For nonlocal gotos, we must save both the stack pointer and its
10460 ;; backchain and restore both. Note that in the nonlocal case, the
10461 ;; save area is a memory location.
10463 (define_expand "save_stack_function"
10464 [(match_operand 0 "general_operand" "")
10465 (match_operand 1 "general_operand" "")]
10469 (define_expand "restore_stack_function"
10470 [(match_operand 0 "general_operand" "")
10471 (match_operand 1 "general_operand" "")]
10475 (define_expand "restore_stack_block"
10476 [(match_operand 0 "register_operand" "")
10477 (match_operand 1 "register_operand" "")]
10480 rtx temp = gen_reg_rtx (Pmode);
10482 emit_move_insn (temp, s390_back_chain_rtx ());
10483 emit_move_insn (operands[0], operands[1]);
10484 emit_move_insn (s390_back_chain_rtx (), temp);
10489 (define_expand "save_stack_nonlocal"
10490 [(match_operand 0 "memory_operand" "")
10491 (match_operand 1 "register_operand" "")]
10494 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10496 /* Copy the backchain to the first word, sp to the second and the
10497 literal pool base to the third. */
10499 rtx save_bc = adjust_address (operands[0], Pmode, 0);
10500 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
10501 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
10503 if (TARGET_BACKCHAIN)
10504 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
10506 emit_move_insn (save_sp, operands[1]);
10507 emit_move_insn (save_bp, base);
10512 (define_expand "restore_stack_nonlocal"
10513 [(match_operand 0 "register_operand" "")
10514 (match_operand 1 "memory_operand" "")]
10517 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
10518 rtx temp = NULL_RTX;
10520 /* Restore the backchain from the first word, sp from the second and the
10521 literal pool base from the third. */
10523 rtx save_bc = adjust_address (operands[1], Pmode, 0);
10524 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
10525 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
10527 if (TARGET_BACKCHAIN)
10528 temp = force_reg (Pmode, save_bc);
10530 emit_move_insn (base, save_bp);
10531 emit_move_insn (operands[0], save_sp);
10534 emit_move_insn (s390_back_chain_rtx (), temp);
10540 (define_expand "exception_receiver"
10544 s390_set_has_landing_pad_p (true);
10549 ; nop instruction pattern(s).
10556 [(set_attr "op_type" "RR")
10557 (set_attr "z10prop" "z10_fr_E1")])
10559 (define_insn "nop1"
10563 [(set_attr "op_type" "RR")])
10565 ;;- Undeletable nops (used for hotpatching)
10567 (define_insn "nop_2_byte"
10568 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
10571 [(set_attr "op_type" "RR")])
10573 (define_insn "nop_4_byte"
10574 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)]
10577 [(set_attr "op_type" "RX")])
10579 (define_insn "nop_6_byte"
10580 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
10583 [(set_attr "op_type" "RIL")])
10587 ; Special literal pool access instruction pattern(s).
10590 (define_insn "*pool_entry"
10591 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
10592 UNSPECV_POOL_ENTRY)]
10595 machine_mode mode = GET_MODE (PATTERN (insn));
10596 unsigned int align = GET_MODE_BITSIZE (mode);
10597 s390_output_pool_entry (operands[0], mode, align);
10600 [(set (attr "length")
10601 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
10603 (define_insn "pool_align"
10604 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
10605 UNSPECV_POOL_ALIGN)]
10608 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10610 (define_insn "pool_section_start"
10611 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
10614 switch_to_section (targetm.asm_out.function_rodata_section
10615 (current_function_decl));
10618 [(set_attr "length" "0")])
10620 (define_insn "pool_section_end"
10621 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
10624 switch_to_section (current_function_section ());
10627 [(set_attr "length" "0")])
10629 (define_insn "main_base_31_small"
10630 [(set (match_operand 0 "register_operand" "=a")
10631 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10632 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10634 [(set_attr "op_type" "RR")
10635 (set_attr "type" "la")
10636 (set_attr "z196prop" "z196_cracked")])
10638 (define_insn "main_base_31_large"
10639 [(set (match_operand 0 "register_operand" "=a")
10640 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
10641 (set (pc) (label_ref (match_operand 2 "" "")))]
10642 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10644 [(set_attr "op_type" "RI")
10645 (set_attr "z196prop" "z196_cracked")])
10647 (define_insn "main_base_64"
10648 [(set (match_operand 0 "register_operand" "=a")
10649 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
10650 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10652 [(set_attr "op_type" "RIL")
10653 (set_attr "type" "larl")
10654 (set_attr "z10prop" "z10_fwd_A1")])
10656 (define_insn "main_pool"
10657 [(set (match_operand 0 "register_operand" "=a")
10658 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
10659 "GET_MODE (operands[0]) == Pmode"
10661 gcc_unreachable ();
10663 [(set (attr "type")
10664 (if_then_else (match_test "TARGET_CPU_ZARCH")
10665 (const_string "larl") (const_string "la")))])
10667 (define_insn "reload_base_31"
10668 [(set (match_operand 0 "register_operand" "=a")
10669 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10670 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10671 "basr\t%0,0\;la\t%0,%1-.(%0)"
10672 [(set_attr "length" "6")
10673 (set_attr "type" "la")
10674 (set_attr "z196prop" "z196_cracked")])
10676 (define_insn "reload_base_64"
10677 [(set (match_operand 0 "register_operand" "=a")
10678 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
10679 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
10681 [(set_attr "op_type" "RIL")
10682 (set_attr "type" "larl")
10683 (set_attr "z10prop" "z10_fwd_A1")])
10685 (define_insn "pool"
10686 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
10689 gcc_unreachable ();
10691 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
10694 ;; Insns related to generating the function prologue and epilogue.
10698 (define_expand "prologue"
10699 [(use (const_int 0))]
10701 "s390_emit_prologue (); DONE;")
10703 (define_expand "epilogue"
10704 [(use (const_int 1))]
10706 "s390_emit_epilogue (false); DONE;")
10708 (define_expand "sibcall_epilogue"
10709 [(use (const_int 0))]
10711 "s390_emit_epilogue (true); DONE;")
10713 ;; A direct return instruction, without using an epilogue.
10714 (define_insn "<code>"
10716 "s390_can_use_<code>_insn ()"
10718 [(set_attr "op_type" "RR")
10719 (set_attr "type" "jsr")
10720 (set_attr "atype" "agen")])
10722 (define_insn "*return"
10724 (use (match_operand 0 "register_operand" "a"))]
10725 "GET_MODE (operands[0]) == Pmode"
10727 [(set_attr "op_type" "RR")
10728 (set_attr "type" "jsr")
10729 (set_attr "atype" "agen")])
10732 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
10733 ;; pointer. This is used for compatibility.
10735 (define_expand "ptr_extend"
10736 [(set (match_operand:DI 0 "register_operand" "=r")
10737 (match_operand:SI 1 "register_operand" "r"))]
10740 emit_insn (gen_anddi3 (operands[0],
10741 gen_lowpart (DImode, operands[1]),
10742 GEN_INT (0x7fffffff)));
10746 ;; Instruction definition to expand eh_return macro to support
10747 ;; swapping in special linkage return addresses.
10749 (define_expand "eh_return"
10750 [(use (match_operand 0 "register_operand" ""))]
10753 s390_emit_tpf_eh_return (operands[0]);
10758 ; Stack Protector Patterns
10761 (define_expand "stack_protect_set"
10762 [(set (match_operand 0 "memory_operand" "")
10763 (match_operand 1 "memory_operand" ""))]
10766 #ifdef TARGET_THREAD_SSP_OFFSET
10768 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10769 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10772 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
10774 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
10779 (define_insn "stack_protect_set<mode>"
10780 [(set (match_operand:DSI 0 "memory_operand" "=Q")
10781 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
10783 "mvc\t%O0(%G0,%R0),%S1"
10784 [(set_attr "op_type" "SS")])
10786 (define_expand "stack_protect_test"
10787 [(set (reg:CC CC_REGNUM)
10788 (compare (match_operand 0 "memory_operand" "")
10789 (match_operand 1 "memory_operand" "")))
10790 (match_operand 2 "" "")]
10794 #ifdef TARGET_THREAD_SSP_OFFSET
10796 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
10797 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
10800 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
10802 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
10804 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM);
10805 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx);
10806 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2]));
10810 (define_insn "stack_protect_test<mode>"
10811 [(set (reg:CCZ CC_REGNUM)
10812 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
10813 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
10815 "clc\t%O0(%G0,%R0),%S1"
10816 [(set_attr "op_type" "SS")])
10818 ; This is used in s390_emit_prologue in order to prevent insns
10819 ; adjusting the stack pointer to be moved over insns writing stack
10820 ; slots using a copy of the stack pointer in a different register.
10821 (define_insn "stack_tie"
10822 [(set (match_operand:BLK 0 "memory_operand" "+m")
10823 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
10826 [(set_attr "length" "0")])
10829 (define_insn "stack_restore_from_fpr"
10830 [(set (reg:DI STACK_REGNUM)
10831 (match_operand:DI 0 "register_operand" "f"))
10832 (clobber (mem:BLK (scratch)))]
10835 [(set_attr "op_type" "RRE")])
10838 ; Data prefetch patterns
10841 (define_insn "prefetch"
10842 [(prefetch (match_operand 0 "address_operand" "ZT,X")
10843 (match_operand:SI 1 "const_int_operand" " n,n")
10844 (match_operand:SI 2 "const_int_operand" " n,n"))]
10847 switch (which_alternative)
10850 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
10852 if (larl_operand (operands[0], Pmode))
10853 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
10857 /* This might be reached for symbolic operands with an odd
10858 addend. We simply omit the prefetch for such rare cases. */
10863 [(set_attr "type" "load,larl")
10864 (set_attr "op_type" "RXY,RIL")
10865 (set_attr "z10prop" "z10_super")
10866 (set_attr "z196prop" "z196_alone")])
10870 ; Byte swap instructions
10873 ; FIXME: There is also mvcin but we cannot use it since src and target
10875 ; lrvr, lrv, strv, lrvgr, lrvg, strvg
10876 (define_insn "bswap<mode>2"
10877 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
10878 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
10884 [(set_attr "type" "*,load,store")
10885 (set_attr "op_type" "RRE,RXY,RXY")
10886 (set_attr "z10prop" "z10_super")])
10888 (define_insn "bswaphi2"
10889 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
10890 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
10896 [(set_attr "type" "*,load,store")
10897 (set_attr "op_type" "RRE,RXY,RXY")
10898 (set_attr "z10prop" "z10_super")])
10901 [(set (match_operand:HI 0 "register_operand" "")
10902 (bswap:HI (match_operand:HI 1 "register_operand" "")))]
10904 [(set (match_dup 2) (bswap:SI (match_dup 3)))
10905 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
10907 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
10908 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
10913 ; Population count instruction
10916 ; The S/390 popcount instruction counts the bits of op1 in 8 byte
10917 ; portions and stores the result in the corresponding bytes in op0.
10918 (define_insn "*popcount<mode>"
10919 [(set (match_operand:INT 0 "register_operand" "=d")
10920 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
10921 (clobber (reg:CC CC_REGNUM))]
10924 [(set_attr "op_type" "RRE")])
10926 (define_expand "popcountdi2"
10928 (parallel [(set (match_operand:DI 0 "register_operand" "")
10929 (unspec:DI [(match_operand:DI 1 "register_operand")]
10931 (clobber (reg:CC CC_REGNUM))])
10932 ; sllg op2, op0, 32
10933 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
10935 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10936 (clobber (reg:CC CC_REGNUM))])
10937 ; sllg op2, op0, 16
10939 (ashift:DI (match_dup 0) (const_int 16)))
10941 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10942 (clobber (reg:CC CC_REGNUM))])
10944 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
10946 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
10947 (clobber (reg:CC CC_REGNUM))])
10948 ; srlg op0, op0, 56
10949 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
10950 "TARGET_Z196 && TARGET_64BIT"
10951 "operands[2] = gen_reg_rtx (DImode);")
10953 (define_expand "popcountsi2"
10955 (parallel [(set (match_operand:SI 0 "register_operand" "")
10956 (unspec:SI [(match_operand:SI 1 "register_operand")]
10958 (clobber (reg:CC CC_REGNUM))])
10959 ; sllk op2, op0, 16
10961 (ashift:SI (match_dup 0) (const_int 16)))
10963 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10964 (clobber (reg:CC CC_REGNUM))])
10966 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
10968 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10969 (clobber (reg:CC CC_REGNUM))])
10971 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
10973 "operands[2] = gen_reg_rtx (SImode);")
10975 (define_expand "popcounthi2"
10977 (parallel [(set (match_operand:HI 0 "register_operand" "")
10978 (unspec:HI [(match_operand:HI 1 "register_operand")]
10980 (clobber (reg:CC CC_REGNUM))])
10983 (ashift:SI (match_dup 0) (const_int 8)))
10985 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
10986 (clobber (reg:CC CC_REGNUM))])
10988 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
10990 "operands[2] = gen_reg_rtx (SImode);")
10992 (define_expand "popcountqi2"
10994 (parallel [(set (match_operand:QI 0 "register_operand" "")
10995 (unspec:QI [(match_operand:QI 1 "register_operand")]
10997 (clobber (reg:CC CC_REGNUM))])]
11002 ;;- Copy sign instructions
11005 (define_insn "copysign<mode>3"
11006 [(set (match_operand:FP 0 "register_operand" "=f")
11007 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
11008 (match_operand:FP 2 "register_operand" "f")]
11012 [(set_attr "op_type" "RRF")
11013 (set_attr "type" "fsimp<mode>")])
11017 ;;- Transactional execution instructions
11020 ; This splitter helps combine to make use of CC directly when
11021 ; comparing the integer result of a tbegin builtin with a constant.
11022 ; The unspec is already removed by canonicalize_comparison. So this
11023 ; splitters only job is to turn the PARALLEL into separate insns
11024 ; again. Unfortunately this only works with the very first cc/int
11025 ; compare since combine is not able to deal with data flow across
11026 ; basic block boundaries.
11028 ; It needs to be an insn pattern as well since combine does not apply
11029 ; the splitter directly. Combine would only use it if it actually
11030 ; would reduce the number of instructions.
11031 (define_insn_and_split "*ccraw_to_int"
11034 (match_operator 0 "s390_eqne_operator"
11035 [(reg:CCRAW CC_REGNUM)
11036 (match_operand 1 "const_int_operand" "")])
11037 (label_ref (match_operand 2 "" ""))
11039 (set (match_operand:SI 3 "register_operand" "=d")
11040 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11044 [(set (match_dup 3)
11045 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))
11047 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)])
11048 (label_ref (match_dup 2))
11052 ; Non-constrained transaction begin
11054 (define_expand "tbegin"
11055 [(match_operand:SI 0 "register_operand" "")
11056 (match_operand:BLK 1 "memory_operand" "")]
11059 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true);
11063 (define_expand "tbegin_nofloat"
11064 [(match_operand:SI 0 "register_operand" "")
11065 (match_operand:BLK 1 "memory_operand" "")]
11068 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false);
11072 (define_expand "tbegin_retry"
11073 [(match_operand:SI 0 "register_operand" "")
11074 (match_operand:BLK 1 "memory_operand" "")
11075 (match_operand:SI 2 "general_operand" "")]
11078 s390_expand_tbegin (operands[0], operands[1], operands[2], true);
11082 (define_expand "tbegin_retry_nofloat"
11083 [(match_operand:SI 0 "register_operand" "")
11084 (match_operand:BLK 1 "memory_operand" "")
11085 (match_operand:SI 2 "general_operand" "")]
11088 s390_expand_tbegin (operands[0], operands[1], operands[2], false);
11092 ; Clobber VRs since they don't get restored
11093 (define_insn "tbegin_1_z13"
11094 [(set (reg:CCRAW CC_REGNUM)
11095 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11097 (set (match_operand:BLK 1 "memory_operand" "=Q")
11098 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
11099 (clobber (reg:TI 16)) (clobber (reg:TI 38))
11100 (clobber (reg:TI 17)) (clobber (reg:TI 39))
11101 (clobber (reg:TI 18)) (clobber (reg:TI 40))
11102 (clobber (reg:TI 19)) (clobber (reg:TI 41))
11103 (clobber (reg:TI 20)) (clobber (reg:TI 42))
11104 (clobber (reg:TI 21)) (clobber (reg:TI 43))
11105 (clobber (reg:TI 22)) (clobber (reg:TI 44))
11106 (clobber (reg:TI 23)) (clobber (reg:TI 45))
11107 (clobber (reg:TI 24)) (clobber (reg:TI 46))
11108 (clobber (reg:TI 25)) (clobber (reg:TI 47))
11109 (clobber (reg:TI 26)) (clobber (reg:TI 48))
11110 (clobber (reg:TI 27)) (clobber (reg:TI 49))
11111 (clobber (reg:TI 28)) (clobber (reg:TI 50))
11112 (clobber (reg:TI 29)) (clobber (reg:TI 51))
11113 (clobber (reg:TI 30)) (clobber (reg:TI 52))
11114 (clobber (reg:TI 31)) (clobber (reg:TI 53))]
11115 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
11116 ; not supposed to be used for immediates (see genpreds.c).
11117 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11119 [(set_attr "op_type" "SIL")])
11121 (define_insn "tbegin_1"
11122 [(set (reg:CCRAW CC_REGNUM)
11123 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11125 (set (match_operand:BLK 1 "memory_operand" "=Q")
11126 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
11127 (clobber (reg:DF 16))
11128 (clobber (reg:DF 17))
11129 (clobber (reg:DF 18))
11130 (clobber (reg:DF 19))
11131 (clobber (reg:DF 20))
11132 (clobber (reg:DF 21))
11133 (clobber (reg:DF 22))
11134 (clobber (reg:DF 23))
11135 (clobber (reg:DF 24))
11136 (clobber (reg:DF 25))
11137 (clobber (reg:DF 26))
11138 (clobber (reg:DF 27))
11139 (clobber (reg:DF 28))
11140 (clobber (reg:DF 29))
11141 (clobber (reg:DF 30))
11142 (clobber (reg:DF 31))]
11143 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
11144 ; not supposed to be used for immediates (see genpreds.c).
11145 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11147 [(set_attr "op_type" "SIL")])
11149 ; Same as above but without the FPR clobbers
11150 (define_insn "tbegin_nofloat_1"
11151 [(set (reg:CCRAW CC_REGNUM)
11152 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
11154 (set (match_operand:BLK 1 "memory_operand" "=Q")
11155 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))]
11156 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11158 [(set_attr "op_type" "SIL")])
11161 ; Constrained transaction begin
11163 (define_expand "tbeginc"
11164 [(set (reg:CCRAW CC_REGNUM)
11165 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)]
11170 (define_insn "*tbeginc_1"
11171 [(set (reg:CCRAW CC_REGNUM)
11172 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")]
11174 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
11176 [(set_attr "op_type" "SIL")])
11180 (define_expand "tend"
11181 [(set (reg:CCRAW CC_REGNUM)
11182 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))
11183 (set (match_operand:SI 0 "register_operand" "")
11184 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
11188 (define_insn "*tend_1"
11189 [(set (reg:CCRAW CC_REGNUM)
11190 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))]
11193 [(set_attr "op_type" "S")])
11195 ; Transaction abort
11197 (define_expand "tabort"
11198 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
11200 "TARGET_HTM && operands != NULL"
11202 if (CONST_INT_P (operands[0])
11203 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
11205 error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
11206 ". Values in range 0 through 255 are reserved.",
11207 INTVAL (operands[0]));
11212 (define_insn "*tabort_1"
11213 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
11215 "TARGET_HTM && operands != NULL"
11217 [(set_attr "op_type" "S")])
11219 (define_insn "*tabort_1_plus"
11220 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
11221 (match_operand:SI 1 "const_int_operand" "J"))]
11223 "TARGET_HTM && operands != NULL
11224 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
11226 [(set_attr "op_type" "S")])
11228 ; Transaction extract nesting depth
11230 (define_insn "etnd"
11231 [(set (match_operand:SI 0 "register_operand" "=d")
11232 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))]
11235 [(set_attr "op_type" "RRE")])
11237 ; Non-transactional store
11239 (define_insn "ntstg"
11240 [(set (match_operand:DI 0 "memory_operand" "=T")
11241 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
11245 [(set_attr "op_type" "RXY")])
11247 ; Transaction perform processor assist
11249 (define_expand "tx_assist"
11250 [(unspec_volatile [(match_operand:SI 0 "register_operand" "")
11251 (reg:SI GPR0_REGNUM)
11257 (define_insn "*ppa"
11258 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")
11259 (match_operand:SI 1 "register_operand" "d")
11260 (match_operand 2 "const_int_operand" "I")]
11262 "TARGET_HTM && INTVAL (operands[2]) < 16"
11264 [(set_attr "op_type" "RRF")])
11267 ; Set and get floating point control register
11269 (define_insn "sfpc"
11270 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
11272 "TARGET_HARD_FLOAT"
11275 (define_insn "efpc"
11276 [(set (match_operand:SI 0 "register_operand" "=d")
11277 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
11278 "TARGET_HARD_FLOAT"
11282 ; Load count to block boundary
11284 (define_insn "lcbb"
11285 [(set (match_operand:SI 0 "register_operand" "=d")
11286 (unspec:SI [(match_operand 1 "address_operand" "ZR")
11287 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
11288 (clobber (reg:CC CC_REGNUM))]
11291 [(set_attr "op_type" "VRX")])
11293 ; Handle -fsplit-stack.
11295 (define_expand "split_stack_prologue"
11299 s390_expand_split_stack_prologue ();
11303 ;; If there are operand 0 bytes available on the stack, jump to
11306 (define_expand "split_stack_space_check"
11307 [(set (pc) (if_then_else
11308 (ltu (minus (reg 15)
11309 (match_operand 0 "register_operand"))
11310 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
11311 (label_ref (match_operand 1))
11315 /* Offset from thread pointer to __private_ss. */
11316 int psso = TARGET_64BIT ? 0x38 : 0x20;
11317 rtx tp = s390_get_thread_pointer ();
11318 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
11319 rtx reg = gen_reg_rtx (Pmode);
11322 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
11324 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
11325 cc = s390_emit_compare (GT, reg, guard);
11326 s390_emit_jump (operands[1], cc);
11331 ;; __morestack parameter block for split stack prologue. Parameters are:
11332 ;; parameter block label, label to be called by __morestack, frame size,
11333 ;; stack parameter size.
11335 (define_insn "split_stack_data"
11336 [(unspec_volatile [(match_operand 0 "" "X")
11337 (match_operand 1 "" "X")
11338 (match_operand 2 "const_int_operand" "X")
11339 (match_operand 3 "const_int_operand" "X")]
11340 UNSPECV_SPLIT_STACK_DATA)]
11343 switch_to_section (targetm.asm_out.function_rodata_section
11344 (current_function_decl));
11347 output_asm_insn (".align\t8", operands);
11349 output_asm_insn (".align\t4", operands);
11350 (*targetm.asm_out.internal_label) (asm_out_file, "L",
11351 CODE_LABEL_NUMBER (operands[0]));
11354 output_asm_insn (".quad\t%2", operands);
11355 output_asm_insn (".quad\t%3", operands);
11356 output_asm_insn (".quad\t%1-%0", operands);
11360 output_asm_insn (".long\t%2", operands);
11361 output_asm_insn (".long\t%3", operands);
11362 output_asm_insn (".long\t%1-%0", operands);
11365 switch_to_section (current_function_section ());
11368 [(set_attr "length" "0")])
11371 ;; A jg with minimal fuss for use in split stack prologue.
11373 (define_expand "split_stack_call"
11374 [(match_operand 0 "bras_sym_operand" "X")
11375 (match_operand 1 "" "")]
11379 emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
11381 emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
11385 (define_insn "split_stack_call_<mode>"
11386 [(set (pc) (label_ref (match_operand 1 "" "")))
11387 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11389 UNSPECV_SPLIT_STACK_CALL))]
11392 [(set_attr "op_type" "RIL")
11393 (set_attr "type" "branch")])
11395 ;; Also a conditional one.
11397 (define_expand "split_stack_cond_call"
11398 [(match_operand 0 "bras_sym_operand" "X")
11399 (match_operand 1 "" "")
11400 (match_operand 2 "" "")]
11404 emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
11406 emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
11410 (define_insn "split_stack_cond_call_<mode>"
11413 (match_operand 1 "" "")
11414 (label_ref (match_operand 2 "" ""))
11416 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
11418 UNSPECV_SPLIT_STACK_CALL))]
11421 [(set_attr "op_type" "RIL")
11422 (set_attr "type" "branch")])
11424 (define_insn "osc_break"
11425 [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
11428 [(set_attr "op_type" "RR")])