gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
 143    BITS_PER_WORD would invoke undefined behavior.  Work around it.  */
 144
 145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
 146   (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
 147
 148 /* Maximum register number, which is the size of the tables below.  */
 149
 150 static unsigned int combine_max_regno;
 151
 152 struct reg_stat {
 153   /* Record last point of death of (hard or pseudo) register n.  */
 154   rtx                           last_death;
 155
 156   /* Record last point of modification of (hard or pseudo) register n.  */
 157   rtx                           last_set;
 158
 159   /* The next group of fields allows the recording of the last value assigned
 160      to (hard or pseudo) register n.  We use this information to see if an
 161      operation being processed is redundant given a prior operation performed
 162      on the register.  For example, an `and' with a constant is redundant if
 163      all the zero bits are already known to be turned off.
 164
 165      We use an approach similar to that used by cse, but change it in the
 166      following ways:
 167
 168      (1) We do not want to reinitialize at each label.
 169      (2) It is useful, but not critical, to know the actual value assigned
 170          to a register.  Often just its form is helpful.
 171
 172      Therefore, we maintain the following fields:
 173
 174      last_set_value             the last value assigned
 175      last_set_label             records the value of label_tick when the
 176                                 register was assigned
 177      last_set_table_tick        records the value of label_tick when a
 178                                 value using the register is assigned
 179      last_set_invalid           set to nonzero when it is not valid
 180                                 to use the value of this register in some
 181                                 register's value
 182
 183      To understand the usage of these tables, it is important to understand
 184      the distinction between the value in last_set_value being valid and
 185      the register being validly contained in some other expression in the
 186      table.
 187
 188      (The next two parameters are out of date).
 189
 190      reg_stat[i].last_set_value is valid if it is nonzero, and either
 191      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 192
 193      Register I may validly appear in any expression returned for the value
 194      of another register if reg_n_sets[i] is 1.  It may also appear in the
 195      value for register J if reg_stat[j].last_set_invalid is zero, or
 196      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 197
 198      If an expression is found in the table containing a register which may
 199      not validly appear in an expression, the register is replaced by
 200      something that won't match, (clobber (const_int 0)).  */
 201
 202   /* Record last value assigned to (hard or pseudo) register n.  */
 203
 204   rtx                           last_set_value;
 205
 206   /* Record the value of label_tick when an expression involving register n
 207      is placed in last_set_value.  */
 208
 209   int                           last_set_table_tick;
 210
 211   /* Record the value of label_tick when the value for register n is placed in
 212      last_set_value.  */
 213
 214   int                           last_set_label;
 215
 216   /* These fields are maintained in parallel with last_set_value and are
 217      used to store the mode in which the register was last set, the bits
 218      that were known to be zero when it was last set, and the number of
 219      sign bits copies it was known to have when it was last set.  */
 220
 221   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 222   char                          last_set_sign_bit_copies;
 223   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 224
 225   /* Set nonzero if references to register n in expressions should not be
 226      used.  last_set_invalid is set nonzero when this register is being
 227      assigned to and last_set_table_tick == label_tick.  */
 228
 229   char                          last_set_invalid;
 230
 231   /* Some registers that are set more than once and used in more than one
 232      basic block are nevertheless always set in similar ways.  For example,
 233      a QImode register may be loaded from memory in two places on a machine
 234      where byte loads zero extend.
 235
 236      We record in the following fields if a register has some leading bits
 237      that are always equal to the sign bit, and what we know about the
 238      nonzero bits of a register, specifically which bits are known to be
 239      zero.
 240
 241      If an entry is zero, it means that we don't know anything special.  */
 242
 243   unsigned char                 sign_bit_copies;
 244
 245   unsigned HOST_WIDE_INT        nonzero_bits;
 246
 247   /* Record the value of the label_tick when the last truncation
 248      happened.  The field truncated_to_mode is only valid if
 249      truncation_label == label_tick.  */
 250
 251   int                           truncation_label;
 252
 253   /* Record the last truncation seen for this register.  If truncation
 254      is not a nop to this mode we might be able to save an explicit
 255      truncation if we know that value already contains a truncated
 256      value.  */
 257
 258   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 259 };
 260
 261 static struct reg_stat *reg_stat;
 262
 263 /* Record the cuid of the last insn that invalidated memory
 264    (anything that writes memory, and subroutine calls, but not pushes).  */
 265
 266 static int mem_last_set;
 267
 268 /* Record the cuid of the last CALL_INSN
 269    so we can tell whether a potential combination crosses any calls.  */
 270
 271 static int last_call_cuid;
 272
 273 /* When `subst' is called, this is the insn that is being modified
 274    (by combining in a previous insn).  The PATTERN of this insn
 275    is still the old pattern partially modified and it should not be
 276    looked at, but this may be used to examine the successors of the insn
 277    to judge whether a simplification is valid.  */
 278
 279 static rtx subst_insn;
 280
 281 /* This is the lowest CUID that `subst' is currently dealing with.
 282    get_last_value will not return a value if the register was set at or
 283    after this CUID.  If not for this mechanism, we could get confused if
 284    I2 or I1 in try_combine were an insn that used the old value of a register
 285    to obtain a new value.  In that case, we might erroneously get the
 286    new value of the register when we wanted the old one.  */
 287
 288 static int subst_low_cuid;
 289
 290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 291    must consider all these registers to be always live.  */
 292
 293 static HARD_REG_SET newpat_used_regs;
 294
 295 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 296    insn is the earlier than I2 or I3, combine should rescan starting at
 297    that location.  */
 298
 299 static rtx added_links_insn;
 300
 301 /* Basic block in which we are performing combines.  */
 302 static basic_block this_basic_block;
 303
 304 /* A bitmap indicating which blocks had registers go dead at entry.
 305    After combine, we'll need to re-do global life analysis with
 306    those blocks as starting points.  */
 307 static sbitmap refresh_blocks;
 308 \f
 309 /* The following array records the insn_rtx_cost for every insn
 310    in the instruction stream.  */
 311
 312 static int *uid_insn_cost;
 313
 314 /* Length of the currently allocated uid_insn_cost array.  */
 315
 316 static int last_insn_cost;
 317
 318 /* Incremented for each label.  */
 319
 320 static int label_tick;
 321
 322 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 323    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 324
 325 static enum machine_mode nonzero_bits_mode;
 326
 327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 328    be safely used.  It is zero while computing them and after combine has
 329    completed.  This former test prevents propagating values based on
 330    previously set values, which can be incorrect if a variable is modified
 331    in a loop.  */
 332
 333 static int nonzero_sign_valid;
 334
 335 \f
 336 /* Record one modification to rtl structure
 337    to be undone by storing old_contents into *where.  */
 338
 339 struct undo
 340 {
 341   struct undo *next;
 342   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 343   union { rtx r; int i; enum machine_mode m; } old_contents;
 344   union { rtx *r; int *i; } where;
 345 };
 346
 347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 348    num_undo says how many are currently recorded.
 349
 350    other_insn is nonzero if we have modified some other insn in the process
 351    of working on subst_insn.  It must be verified too.  */
 352
 353 struct undobuf
 354 {
 355   struct undo *undos;
 356   struct undo *frees;
 357   rtx other_insn;
 358 };
 359
 360 static struct undobuf undobuf;
 361
 362 /* Number of times the pseudo being substituted for
 363    was found and replaced.  */
 364
 365 static int n_occurrences;
 366
 367 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 368                                          enum machine_mode,
 369                                          unsigned HOST_WIDE_INT,
 370                                          unsigned HOST_WIDE_INT *);
 371 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 372                                                 enum machine_mode,
 373                                                 unsigned int, unsigned int *);
 374 static void do_SUBST (rtx *, rtx);
 375 static void do_SUBST_INT (int *, int);
 376 static void init_reg_last (void);
 377 static void setup_incoming_promotions (void);
 378 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 379 static int cant_combine_insn_p (rtx);
 380 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 381 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 382 static int contains_muldiv (rtx);
 383 static rtx try_combine (rtx, rtx, rtx, int *);
 384 static void undo_all (void);
 385 static void undo_commit (void);
 386 static rtx *find_split_point (rtx *, rtx);
 387 static rtx subst (rtx, rtx, rtx, int, int);
 388 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 389 static rtx simplify_if_then_else (rtx);
 390 static rtx simplify_set (rtx);
 391 static rtx simplify_logical (rtx);
 392 static rtx expand_compound_operation (rtx);
 393 static rtx expand_field_assignment (rtx);
 394 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 395                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 396 static rtx extract_left_shift (rtx, int);
 397 static rtx make_compound_operation (rtx, enum rtx_code);
 398 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 399                               unsigned HOST_WIDE_INT *);
 400 static rtx canon_reg_for_combine (rtx, rtx);
 401 static rtx force_to_mode (rtx, enum machine_mode,
 402                           unsigned HOST_WIDE_INT, int);
 403 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 404 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 405 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 406 static rtx make_field_assignment (rtx);
 407 static rtx apply_distributive_law (rtx);
 408 static rtx distribute_and_simplify_rtx (rtx, int);
 409 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 410                                      unsigned HOST_WIDE_INT);
 411 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 412                                    unsigned HOST_WIDE_INT);
 413 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 414                             HOST_WIDE_INT, enum machine_mode, int *);
 415 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 417                                  int);
 418 static int recog_for_combine (rtx *, rtx, rtx *);
 419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 421 static void update_table_tick (rtx);
 422 static void record_value_for_reg (rtx, rtx, rtx);
 423 static void check_conversions (rtx, rtx);
 424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 425 static void record_dead_and_set_regs (rtx);
 426 static int get_last_value_validate (rtx *, rtx, int, int);
 427 static rtx get_last_value (rtx);
 428 static int use_crosses_set_p (rtx, int);
 429 static void reg_dead_at_p_1 (rtx, rtx, void *);
 430 static int reg_dead_at_p (rtx, rtx);
 431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 432 static int reg_bitfield_target_p (rtx, rtx);
 433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 434 static void distribute_links (rtx);
 435 static void mark_used_regs_combine (rtx);
 436 static int insn_cuid (rtx);
 437 static void record_promoted_value (rtx, rtx);
 438 static int unmentioned_reg_p_1 (rtx *, void *);
 439 static bool unmentioned_reg_p (rtx, rtx);
 440 static void record_truncated_value (rtx);
 441 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 442 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 443 \f
 444
 445 /* It is not safe to use ordinary gen_lowpart in combine.
 446    See comments in gen_lowpart_for_combine.  */
 447 #undef RTL_HOOKS_GEN_LOWPART
 448 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 449
 450 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 453
 454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 455 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 456
 457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 459
 460 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 461
 462 \f
 463 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 464    insn.  The substitution can be undone by undo_all.  If INTO is already
 465    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 466    also call SUBST, we have to compute it before we put anything into
 467    the undo table.  */
 468
 469 static void
 470 do_SUBST (rtx *into, rtx newval)
 471 {
 472   struct undo *buf;
 473   rtx oldval = *into;
 474
 475   if (oldval == newval)
 476     return;
 477
 478   /* We'd like to catch as many invalid transformations here as
 479      possible.  Unfortunately, there are way too many mode changes
 480      that are perfectly valid, so we'd waste too much effort for
 481      little gain doing the checks here.  Focus on catching invalid
 482      transformations involving integer constants.  */
 483   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 484       && GET_CODE (newval) == CONST_INT)
 485     {
 486       /* Sanity check that we're replacing oldval with a CONST_INT
 487          that is a valid sign-extension for the original mode.  */
 488       gcc_assert (INTVAL (newval)
 489                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 490
 491       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 492          CONST_INT is not valid, because after the replacement, the
 493          original mode would be gone.  Unfortunately, we can't tell
 494          when do_SUBST is called to replace the operand thereof, so we
 495          perform this test on oldval instead, checking whether an
 496          invalid replacement took place before we got here.  */
 497       gcc_assert (!(GET_CODE (oldval) == SUBREG
 498                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 499       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 500                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 501     }
 502
 503   if (undobuf.frees)
 504     buf = undobuf.frees, undobuf.frees = buf->next;
 505   else
 506     buf = XNEW (struct undo);
 507
 508   buf->kind = UNDO_RTX;
 509   buf->where.r = into;
 510   buf->old_contents.r = oldval;
 511   *into = newval;
 512
 513   buf->next = undobuf.undos, undobuf.undos = buf;
 514 }
 515
 516 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 517
 518 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 519    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 520    not safe.  */
 521
 522 static void
 523 do_SUBST_INT (int *into, int newval)
 524 {
 525   struct undo *buf;
 526   int oldval = *into;
 527
 528   if (oldval == newval)
 529     return;
 530
 531   if (undobuf.frees)
 532     buf = undobuf.frees, undobuf.frees = buf->next;
 533   else
 534     buf = XNEW (struct undo);
 535
 536   buf->kind = UNDO_INT;
 537   buf->where.i = into;
 538   buf->old_contents.i = oldval;
 539   *into = newval;
 540
 541   buf->next = undobuf.undos, undobuf.undos = buf;
 542 }
 543
 544 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 545
 546 /* Similar to SUBST, but just substitute the mode.  This is used when
 547    changing the mode of a pseudo-register, so that any other
 548    references to the entry in the regno_reg_rtx array will change as
 549    well.  */
 550
 551 static void
 552 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 553 {
 554   struct undo *buf;
 555   enum machine_mode oldval = GET_MODE (*into);
 556
 557   if (oldval == newval)
 558     return;
 559
 560   if (undobuf.frees)
 561     buf = undobuf.frees, undobuf.frees = buf->next;
 562   else
 563     buf = XNEW (struct undo);
 564
 565   buf->kind = UNDO_MODE;
 566   buf->where.r = into;
 567   buf->old_contents.m = oldval;
 568   PUT_MODE (*into, newval);
 569
 570   buf->next = undobuf.undos, undobuf.undos = buf;
 571 }
 572
 573 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 574 \f
 575 /* Subroutine of try_combine.  Determine whether the combine replacement
 576    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 577    that the original instruction sequence I1, I2 and I3.  Note that I1
 578    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 579    costs of all instructions can be estimated, and the replacements are
 580    more expensive than the original sequence.  */
 581
 582 static bool
 583 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 584 {
 585   int i1_cost, i2_cost, i3_cost;
 586   int new_i2_cost, new_i3_cost;
 587   int old_cost, new_cost;
 588
 589   /* Lookup the original insn_rtx_costs.  */
 590   i2_cost = INSN_UID (i2) <= last_insn_cost
 591             ? uid_insn_cost[INSN_UID (i2)] : 0;
 592   i3_cost = INSN_UID (i3) <= last_insn_cost
 593             ? uid_insn_cost[INSN_UID (i3)] : 0;
 594
 595   if (i1)
 596     {
 597       i1_cost = INSN_UID (i1) <= last_insn_cost
 598                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 599       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 600                  ? i1_cost + i2_cost + i3_cost : 0;
 601     }
 602   else
 603     {
 604       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 605       i1_cost = 0;
 606     }
 607
 608   /* Calculate the replacement insn_rtx_costs.  */
 609   new_i3_cost = insn_rtx_cost (newpat);
 610   if (newi2pat)
 611     {
 612       new_i2_cost = insn_rtx_cost (newi2pat);
 613       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 614                  ? new_i2_cost + new_i3_cost : 0;
 615     }
 616   else
 617     {
 618       new_cost = new_i3_cost;
 619       new_i2_cost = 0;
 620     }
 621
 622   if (undobuf.other_insn)
 623     {
 624       int old_other_cost, new_other_cost;
 625
 626       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 627                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 628       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 629       if (old_other_cost > 0 && new_other_cost > 0)
 630         {
 631           old_cost += old_other_cost;
 632           new_cost += new_other_cost;
 633         }
 634       else
 635         old_cost = 0;
 636     }
 637
 638   /* Disallow this recombination if both new_cost and old_cost are
 639      greater than zero, and new_cost is greater than old cost.  */
 640   if (old_cost > 0
 641       && new_cost > old_cost)
 642     {
 643       if (dump_file)
 644         {
 645           if (i1)
 646             {
 647               fprintf (dump_file,
 648                        "rejecting combination of insns %d, %d and %d\n",
 649                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 650               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 651                        i1_cost, i2_cost, i3_cost, old_cost);
 652             }
 653           else
 654             {
 655               fprintf (dump_file,
 656                        "rejecting combination of insns %d and %d\n",
 657                        INSN_UID (i2), INSN_UID (i3));
 658               fprintf (dump_file, "original costs %d + %d = %d\n",
 659                        i2_cost, i3_cost, old_cost);
 660             }
 661
 662           if (newi2pat)
 663             {
 664               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 665                        new_i2_cost, new_i3_cost, new_cost);
 666             }
 667           else
 668             fprintf (dump_file, "replacement cost %d\n", new_cost);
 669         }
 670
 671       return false;
 672     }
 673
 674   /* Update the uid_insn_cost array with the replacement costs.  */
 675   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 676   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 677   if (i1)
 678     uid_insn_cost[INSN_UID (i1)] = 0;
 679
 680   return true;
 681 }
 682 \f
 683 /* Main entry point for combiner.  F is the first insn of the function.
 684    NREGS is the first unused pseudo-reg number.
 685
 686    Return nonzero if the combiner has turned an indirect jump
 687    instruction into a direct jump.  */
 688 static int
 689 combine_instructions (rtx f, unsigned int nregs)
 690 {
 691   rtx insn, next;
 692 #ifdef HAVE_cc0
 693   rtx prev;
 694 #endif
 695   int i;
 696   unsigned int j = 0;
 697   rtx links, nextlinks;
 698   sbitmap_iterator sbi;
 699
 700   int new_direct_jump_p = 0;
 701
 702   combine_attempts = 0;
 703   combine_merges = 0;
 704   combine_extras = 0;
 705   combine_successes = 0;
 706
 707   combine_max_regno = nregs;
 708
 709   rtl_hooks = combine_rtl_hooks;
 710
 711   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 712
 713   init_recog_no_volatile ();
 714
 715   /* Compute maximum uid value so uid_cuid can be allocated.  */
 716
 717   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 718     if (INSN_UID (insn) > i)
 719       i = INSN_UID (insn);
 720
 721   uid_cuid = XNEWVEC (int, i + 1);
 722   max_uid_cuid = i;
 723
 724   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 725
 726   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 727      problems when, for example, we have j <<= 1 in a loop.  */
 728
 729   nonzero_sign_valid = 0;
 730
 731   /* Compute the mapping from uids to cuids.
 732      Cuids are numbers assigned to insns, like uids,
 733      except that cuids increase monotonically through the code.
 734
 735      Scan all SETs and see if we can deduce anything about what
 736      bits are known to be zero for some registers and how many copies
 737      of the sign bit are known to exist for those registers.
 738
 739      Also set any known values so that we can use it while searching
 740      for what bits are known to be set.  */
 741
 742   label_tick = 1;
 743
 744   setup_incoming_promotions ();
 745
 746   refresh_blocks = sbitmap_alloc (last_basic_block);
 747   sbitmap_zero (refresh_blocks);
 748
 749   /* Allocate array of current insn_rtx_costs.  */
 750   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 751   last_insn_cost = max_uid_cuid;
 752
 753   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 754     {
 755       uid_cuid[INSN_UID (insn)] = ++i;
 756       subst_low_cuid = i;
 757       subst_insn = insn;
 758
 759       if (INSN_P (insn))
 760         {
 761           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 762                        NULL);
 763           record_dead_and_set_regs (insn);
 764
 765 #ifdef AUTO_INC_DEC
 766           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 767             if (REG_NOTE_KIND (links) == REG_INC)
 768               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 769                                                 NULL);
 770 #endif
 771
 772           /* Record the current insn_rtx_cost of this instruction.  */
 773           if (NONJUMP_INSN_P (insn))
 774             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 775           if (dump_file)
 776             fprintf(dump_file, "insn_cost %d: %d\n",
 777                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 778         }
 779
 780       if (LABEL_P (insn))
 781         label_tick++;
 782     }
 783
 784   nonzero_sign_valid = 1;
 785
 786   /* Now scan all the insns in forward order.  */
 787
 788   label_tick = 1;
 789   last_call_cuid = 0;
 790   mem_last_set = 0;
 791   init_reg_last ();
 792   setup_incoming_promotions ();
 793
 794   FOR_EACH_BB (this_basic_block)
 795     {
 796       for (insn = BB_HEAD (this_basic_block);
 797            insn != NEXT_INSN (BB_END (this_basic_block));
 798            insn = next ? next : NEXT_INSN (insn))
 799         {
 800           next = 0;
 801
 802           if (LABEL_P (insn))
 803             label_tick++;
 804
 805           else if (INSN_P (insn))
 806             {
 807               /* See if we know about function return values before this
 808                  insn based upon SUBREG flags.  */
 809               check_conversions (insn, PATTERN (insn));
 810
 811               /* Try this insn with each insn it links back to.  */
 812
 813               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 814                 if ((next = try_combine (insn, XEXP (links, 0),
 815                                          NULL_RTX, &new_direct_jump_p)) != 0)
 816                   goto retry;
 817
 818               /* Try each sequence of three linked insns ending with this one.  */
 819
 820               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 821                 {
 822                   rtx link = XEXP (links, 0);
 823
 824                   /* If the linked insn has been replaced by a note, then there
 825                      is no point in pursuing this chain any further.  */
 826                   if (NOTE_P (link))
 827                     continue;
 828
 829                   for (nextlinks = LOG_LINKS (link);
 830                        nextlinks;
 831                        nextlinks = XEXP (nextlinks, 1))
 832                     if ((next = try_combine (insn, link,
 833                                              XEXP (nextlinks, 0),
 834                                              &new_direct_jump_p)) != 0)
 835                       goto retry;
 836                 }
 837
 838 #ifdef HAVE_cc0
 839               /* Try to combine a jump insn that uses CC0
 840                  with a preceding insn that sets CC0, and maybe with its
 841                  logical predecessor as well.
 842                  This is how we make decrement-and-branch insns.
 843                  We need this special code because data flow connections
 844                  via CC0 do not get entered in LOG_LINKS.  */
 845
 846               if (JUMP_P (insn)
 847                   && (prev = prev_nonnote_insn (insn)) != 0
 848                   && NONJUMP_INSN_P (prev)
 849                   && sets_cc0_p (PATTERN (prev)))
 850                 {
 851                   if ((next = try_combine (insn, prev,
 852                                            NULL_RTX, &new_direct_jump_p)) != 0)
 853                     goto retry;
 854
 855                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 856                        nextlinks = XEXP (nextlinks, 1))
 857                     if ((next = try_combine (insn, prev,
 858                                              XEXP (nextlinks, 0),
 859                                              &new_direct_jump_p)) != 0)
 860                       goto retry;
 861                 }
 862
 863               /* Do the same for an insn that explicitly references CC0.  */
 864               if (NONJUMP_INSN_P (insn)
 865                   && (prev = prev_nonnote_insn (insn)) != 0
 866                   && NONJUMP_INSN_P (prev)
 867                   && sets_cc0_p (PATTERN (prev))
 868                   && GET_CODE (PATTERN (insn)) == SET
 869                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 870                 {
 871                   if ((next = try_combine (insn, prev,
 872                                            NULL_RTX, &new_direct_jump_p)) != 0)
 873                     goto retry;
 874
 875                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 876                        nextlinks = XEXP (nextlinks, 1))
 877                     if ((next = try_combine (insn, prev,
 878                                              XEXP (nextlinks, 0),
 879                                              &new_direct_jump_p)) != 0)
 880                       goto retry;
 881                 }
 882
 883               /* Finally, see if any of the insns that this insn links to
 884                  explicitly references CC0.  If so, try this insn, that insn,
 885                  and its predecessor if it sets CC0.  */
 886               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 887                 if (NONJUMP_INSN_P (XEXP (links, 0))
 888                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 889                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 890                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 891                     && NONJUMP_INSN_P (prev)
 892                     && sets_cc0_p (PATTERN (prev))
 893                     && (next = try_combine (insn, XEXP (links, 0),
 894                                             prev, &new_direct_jump_p)) != 0)
 895                   goto retry;
 896 #endif
 897
 898               /* Try combining an insn with two different insns whose results it
 899                  uses.  */
 900               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 901                 for (nextlinks = XEXP (links, 1); nextlinks;
 902                      nextlinks = XEXP (nextlinks, 1))
 903                   if ((next = try_combine (insn, XEXP (links, 0),
 904                                            XEXP (nextlinks, 0),
 905                                            &new_direct_jump_p)) != 0)
 906                     goto retry;
 907
 908               /* Try this insn with each REG_EQUAL note it links back to.  */
 909               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 910                 {
 911                   rtx set, note;
 912                   rtx temp = XEXP (links, 0);
 913                   if ((set = single_set (temp)) != 0
 914                       && (note = find_reg_equal_equiv_note (temp)) != 0
 915                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 916                       /* Avoid using a register that may already been marked
 917                          dead by an earlier instruction.  */
 918                       && ! unmentioned_reg_p (note, SET_SRC (set))
 919                       && (GET_MODE (note) == VOIDmode
 920                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 921                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 922                     {
 923                       /* Temporarily replace the set's source with the
 924                          contents of the REG_EQUAL note.  The insn will
 925                          be deleted or recognized by try_combine.  */
 926                       rtx orig = SET_SRC (set);
 927                       SET_SRC (set) = note;
 928                       next = try_combine (insn, temp, NULL_RTX,
 929                                           &new_direct_jump_p);
 930                       if (next)
 931                         goto retry;
 932                       SET_SRC (set) = orig;
 933                     }
 934                 }
 935
 936               if (!NOTE_P (insn))
 937                 record_dead_and_set_regs (insn);
 938
 939             retry:
 940               ;
 941             }
 942         }
 943     }
 944   clear_bb_flags ();
 945
 946   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 947     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 948   new_direct_jump_p |= purge_all_dead_edges ();
 949   delete_noop_moves ();
 950
 951   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 952                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 953                                     | PROP_KILL_DEAD_CODE);
 954
 955   /* Clean up.  */
 956   sbitmap_free (refresh_blocks);
 957   free (uid_insn_cost);
 958   free (reg_stat);
 959   free (uid_cuid);
 960
 961   {
 962     struct undo *undo, *next;
 963     for (undo = undobuf.frees; undo; undo = next)
 964       {
 965         next = undo->next;
 966         free (undo);
 967       }
 968     undobuf.frees = 0;
 969   }
 970
 971   total_attempts += combine_attempts;
 972   total_merges += combine_merges;
 973   total_extras += combine_extras;
 974   total_successes += combine_successes;
 975
 976   nonzero_sign_valid = 0;
 977   rtl_hooks = general_rtl_hooks;
 978
 979   /* Make recognizer allow volatile MEMs again.  */
 980   init_recog ();
 981
 982   return new_direct_jump_p;
 983 }
 984
 985 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 986
 987 static void
 988 init_reg_last (void)
 989 {
 990   unsigned int i;
 991   for (i = 0; i < combine_max_regno; i++)
 992     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 993 }
 994 \f
 995 /* Set up any promoted values for incoming argument registers.  */
 996
 997 static void
 998 setup_incoming_promotions (void)
 999 {
1000   unsigned int regno;
1001   rtx reg;
1002   enum machine_mode mode;
1003   int unsignedp;
1004   rtx first = get_insns ();
1005
1006   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1007     {
1008       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1009         /* Check whether this register can hold an incoming pointer
1010            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1011            numbers, so translate if necessary due to register windows.  */
1012         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1013             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1014           {
1015             record_value_for_reg
1016               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1017                                            : SIGN_EXTEND),
1018                                           GET_MODE (reg),
1019                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1020           }
1021     }
1022 }
1023 \f
1024 /* Called via note_stores.  If X is a pseudo that is narrower than
1025    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1026
1027    If we are setting only a portion of X and we can't figure out what
1028    portion, assume all bits will be used since we don't know what will
1029    be happening.
1030
1031    Similarly, set how many bits of X are known to be copies of the sign bit
1032    at all locations in the function.  This is the smallest number implied
1033    by any set of X.  */
1034
1035 static void
1036 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1037                                   void *data ATTRIBUTE_UNUSED)
1038 {
1039   unsigned int num;
1040
1041   if (REG_P (x)
1042       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1043       /* If this register is undefined at the start of the file, we can't
1044          say what its contents were.  */
1045       && ! REGNO_REG_SET_P
1046          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1047       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1048     {
1049       if (set == 0 || GET_CODE (set) == CLOBBER)
1050         {
1051           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1052           reg_stat[REGNO (x)].sign_bit_copies = 1;
1053           return;
1054         }
1055
1056       /* If this is a complex assignment, see if we can convert it into a
1057          simple assignment.  */
1058       set = expand_field_assignment (set);
1059
1060       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1061          set what we know about X.  */
1062
1063       if (SET_DEST (set) == x
1064           || (GET_CODE (SET_DEST (set)) == SUBREG
1065               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1066                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1067               && SUBREG_REG (SET_DEST (set)) == x))
1068         {
1069           rtx src = SET_SRC (set);
1070
1071 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1072           /* If X is narrower than a word and SRC is a non-negative
1073              constant that would appear negative in the mode of X,
1074              sign-extend it for use in reg_stat[].nonzero_bits because some
1075              machines (maybe most) will actually do the sign-extension
1076              and this is the conservative approach.
1077
1078              ??? For 2.5, try to tighten up the MD files in this regard
1079              instead of this kludge.  */
1080
1081           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1082               && GET_CODE (src) == CONST_INT
1083               && INTVAL (src) > 0
1084               && 0 != (INTVAL (src)
1085                        & ((HOST_WIDE_INT) 1
1086                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1087             src = GEN_INT (INTVAL (src)
1088                            | ((HOST_WIDE_INT) (-1)
1089                               << GET_MODE_BITSIZE (GET_MODE (x))));
1090 #endif
1091
1092           /* Don't call nonzero_bits if it cannot change anything.  */
1093           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1094             reg_stat[REGNO (x)].nonzero_bits
1095               |= nonzero_bits (src, nonzero_bits_mode);
1096           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1097           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1098               || reg_stat[REGNO (x)].sign_bit_copies > num)
1099             reg_stat[REGNO (x)].sign_bit_copies = num;
1100         }
1101       else
1102         {
1103           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1104           reg_stat[REGNO (x)].sign_bit_copies = 1;
1105         }
1106     }
1107 }
1108 \f
1109 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1110    insns that were previously combined into I3 or that will be combined
1111    into the merger of INSN and I3.
1112
1113    Return 0 if the combination is not allowed for any reason.
1114
1115    If the combination is allowed, *PDEST will be set to the single
1116    destination of INSN and *PSRC to the single source, and this function
1117    will return 1.  */
1118
1119 static int
1120 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1121                rtx *pdest, rtx *psrc)
1122 {
1123   int i;
1124   rtx set = 0, src, dest;
1125   rtx p;
1126 #ifdef AUTO_INC_DEC
1127   rtx link;
1128 #endif
1129   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1130                               && next_active_insn (succ) == i3)
1131                       : next_active_insn (insn) == i3);
1132
1133   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1134      or a PARALLEL consisting of such a SET and CLOBBERs.
1135
1136      If INSN has CLOBBER parallel parts, ignore them for our processing.
1137      By definition, these happen during the execution of the insn.  When it
1138      is merged with another insn, all bets are off.  If they are, in fact,
1139      needed and aren't also supplied in I3, they may be added by
1140      recog_for_combine.  Otherwise, it won't match.
1141
1142      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1143      note.
1144
1145      Get the source and destination of INSN.  If more than one, can't
1146      combine.  */
1147
1148   if (GET_CODE (PATTERN (insn)) == SET)
1149     set = PATTERN (insn);
1150   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1151            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1152     {
1153       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1154         {
1155           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1156           rtx note;
1157
1158           switch (GET_CODE (elt))
1159             {
1160             /* This is important to combine floating point insns
1161                for the SH4 port.  */
1162             case USE:
1163               /* Combining an isolated USE doesn't make sense.
1164                  We depend here on combinable_i3pat to reject them.  */
1165               /* The code below this loop only verifies that the inputs of
1166                  the SET in INSN do not change.  We call reg_set_between_p
1167                  to verify that the REG in the USE does not change between
1168                  I3 and INSN.
1169                  If the USE in INSN was for a pseudo register, the matching
1170                  insn pattern will likely match any register; combining this
1171                  with any other USE would only be safe if we knew that the
1172                  used registers have identical values, or if there was
1173                  something to tell them apart, e.g. different modes.  For
1174                  now, we forgo such complicated tests and simply disallow
1175                  combining of USES of pseudo registers with any other USE.  */
1176               if (REG_P (XEXP (elt, 0))
1177                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1178                 {
1179                   rtx i3pat = PATTERN (i3);
1180                   int i = XVECLEN (i3pat, 0) - 1;
1181                   unsigned int regno = REGNO (XEXP (elt, 0));
1182
1183                   do
1184                     {
1185                       rtx i3elt = XVECEXP (i3pat, 0, i);
1186
1187                       if (GET_CODE (i3elt) == USE
1188                           && REG_P (XEXP (i3elt, 0))
1189                           && (REGNO (XEXP (i3elt, 0)) == regno
1190                               ? reg_set_between_p (XEXP (elt, 0),
1191                                                    PREV_INSN (insn), i3)
1192                               : regno >= FIRST_PSEUDO_REGISTER))
1193                         return 0;
1194                     }
1195                   while (--i >= 0);
1196                 }
1197               break;
1198
1199               /* We can ignore CLOBBERs.  */
1200             case CLOBBER:
1201               break;
1202
1203             case SET:
1204               /* Ignore SETs whose result isn't used but not those that
1205                  have side-effects.  */
1206               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1207                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1208                       || INTVAL (XEXP (note, 0)) <= 0)
1209                   && ! side_effects_p (elt))
1210                 break;
1211
1212               /* If we have already found a SET, this is a second one and
1213                  so we cannot combine with this insn.  */
1214               if (set)
1215                 return 0;
1216
1217               set = elt;
1218               break;
1219
1220             default:
1221               /* Anything else means we can't combine.  */
1222               return 0;
1223             }
1224         }
1225
1226       if (set == 0
1227           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1228              so don't do anything with it.  */
1229           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1230         return 0;
1231     }
1232   else
1233     return 0;
1234
1235   if (set == 0)
1236     return 0;
1237
1238   set = expand_field_assignment (set);
1239   src = SET_SRC (set), dest = SET_DEST (set);
1240
1241   /* Don't eliminate a store in the stack pointer.  */
1242   if (dest == stack_pointer_rtx
1243       /* Don't combine with an insn that sets a register to itself if it has
1244          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1245       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1246       /* Can't merge an ASM_OPERANDS.  */
1247       || GET_CODE (src) == ASM_OPERANDS
1248       /* Can't merge a function call.  */
1249       || GET_CODE (src) == CALL
1250       /* Don't eliminate a function call argument.  */
1251       || (CALL_P (i3)
1252           && (find_reg_fusage (i3, USE, dest)
1253               || (REG_P (dest)
1254                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1255                   && global_regs[REGNO (dest)])))
1256       /* Don't substitute into an incremented register.  */
1257       || FIND_REG_INC_NOTE (i3, dest)
1258       || (succ && FIND_REG_INC_NOTE (succ, dest))
1259       /* Don't substitute into a non-local goto, this confuses CFG.  */
1260       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1261 #if 0
1262       /* Don't combine the end of a libcall into anything.  */
1263       /* ??? This gives worse code, and appears to be unnecessary, since no
1264          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1265          use REG_RETVAL notes for noconflict blocks, but other code here
1266          makes sure that those insns don't disappear.  */
1267       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1268 #endif
1269       /* Make sure that DEST is not used after SUCC but before I3.  */
1270       || (succ && ! all_adjacent
1271           && reg_used_between_p (dest, succ, i3))
1272       /* Make sure that the value that is to be substituted for the register
1273          does not use any registers whose values alter in between.  However,
1274          If the insns are adjacent, a use can't cross a set even though we
1275          think it might (this can happen for a sequence of insns each setting
1276          the same destination; last_set of that register might point to
1277          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1278          equivalent to the memory so the substitution is valid even if there
1279          are intervening stores.  Also, don't move a volatile asm or
1280          UNSPEC_VOLATILE across any other insns.  */
1281       || (! all_adjacent
1282           && (((!MEM_P (src)
1283                 || ! find_reg_note (insn, REG_EQUIV, src))
1284                && use_crosses_set_p (src, INSN_CUID (insn)))
1285               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1286               || GET_CODE (src) == UNSPEC_VOLATILE))
1287       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1288          better register allocation by not doing the combine.  */
1289       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1290       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1291       /* Don't combine across a CALL_INSN, because that would possibly
1292          change whether the life span of some REGs crosses calls or not,
1293          and it is a pain to update that information.
1294          Exception: if source is a constant, moving it later can't hurt.
1295          Accept that special case, because it helps -fforce-addr a lot.  */
1296       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1297     return 0;
1298
1299   /* DEST must either be a REG or CC0.  */
1300   if (REG_P (dest))
1301     {
1302       /* If register alignment is being enforced for multi-word items in all
1303          cases except for parameters, it is possible to have a register copy
1304          insn referencing a hard register that is not allowed to contain the
1305          mode being copied and which would not be valid as an operand of most
1306          insns.  Eliminate this problem by not combining with such an insn.
1307
1308          Also, on some machines we don't want to extend the life of a hard
1309          register.  */
1310
1311       if (REG_P (src)
1312           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1313                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1314               /* Don't extend the life of a hard register unless it is
1315                  user variable (if we have few registers) or it can't
1316                  fit into the desired register (meaning something special
1317                  is going on).
1318                  Also avoid substituting a return register into I3, because
1319                  reload can't handle a conflict with constraints of other
1320                  inputs.  */
1321               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1322                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1323         return 0;
1324     }
1325   else if (GET_CODE (dest) != CC0)
1326     return 0;
1327
1328
1329   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1330     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1331       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1332         {
1333           /* Don't substitute for a register intended as a clobberable
1334              operand.  */
1335           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1336           if (rtx_equal_p (reg, dest))
1337             return 0;
1338
1339           /* If the clobber represents an earlyclobber operand, we must not
1340              substitute an expression containing the clobbered register.
1341              As we do not analyze the constraint strings here, we have to
1342              make the conservative assumption.  However, if the register is
1343              a fixed hard reg, the clobber cannot represent any operand;
1344              we leave it up to the machine description to either accept or
1345              reject use-and-clobber patterns.  */
1346           if (!REG_P (reg)
1347               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1348               || !fixed_regs[REGNO (reg)])
1349             if (reg_overlap_mentioned_p (reg, src))
1350               return 0;
1351         }
1352
1353   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1354      or not), reject, unless nothing volatile comes between it and I3 */
1355
1356   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1357     {
1358       /* Make sure succ doesn't contain a volatile reference.  */
1359       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1360         return 0;
1361
1362       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1363         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1364           return 0;
1365     }
1366
1367   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1368      to be an explicit register variable, and was chosen for a reason.  */
1369
1370   if (GET_CODE (src) == ASM_OPERANDS
1371       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1372     return 0;
1373
1374   /* If there are any volatile insns between INSN and I3, reject, because
1375      they might affect machine state.  */
1376
1377   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1378     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1379       return 0;
1380
1381   /* If INSN contains an autoincrement or autodecrement, make sure that
1382      register is not used between there and I3, and not already used in
1383      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1384      Also insist that I3 not be a jump; if it were one
1385      and the incremented register were spilled, we would lose.  */
1386
1387 #ifdef AUTO_INC_DEC
1388   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1389     if (REG_NOTE_KIND (link) == REG_INC
1390         && (JUMP_P (i3)
1391             || reg_used_between_p (XEXP (link, 0), insn, i3)
1392             || (pred != NULL_RTX
1393                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1394             || (succ != NULL_RTX
1395                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1396             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1397       return 0;
1398 #endif
1399
1400 #ifdef HAVE_cc0
1401   /* Don't combine an insn that follows a CC0-setting insn.
1402      An insn that uses CC0 must not be separated from the one that sets it.
1403      We do, however, allow I2 to follow a CC0-setting insn if that insn
1404      is passed as I1; in that case it will be deleted also.
1405      We also allow combining in this case if all the insns are adjacent
1406      because that would leave the two CC0 insns adjacent as well.
1407      It would be more logical to test whether CC0 occurs inside I1 or I2,
1408      but that would be much slower, and this ought to be equivalent.  */
1409
1410   p = prev_nonnote_insn (insn);
1411   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1412       && ! all_adjacent)
1413     return 0;
1414 #endif
1415
1416   /* If we get here, we have passed all the tests and the combination is
1417      to be allowed.  */
1418
1419   *pdest = dest;
1420   *psrc = src;
1421
1422   return 1;
1423 }
1424 \f
1425 /* LOC is the location within I3 that contains its pattern or the component
1426    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1427
1428    One problem is if I3 modifies its output, as opposed to replacing it
1429    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1430    so would produce an insn that is not equivalent to the original insns.
1431
1432    Consider:
1433
1434          (set (reg:DI 101) (reg:DI 100))
1435          (set (subreg:SI (reg:DI 101) 0) <foo>)
1436
1437    This is NOT equivalent to:
1438
1439          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1440                     (set (reg:DI 101) (reg:DI 100))])
1441
1442    Not only does this modify 100 (in which case it might still be valid
1443    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1444
1445    We can also run into a problem if I2 sets a register that I1
1446    uses and I1 gets directly substituted into I3 (not via I2).  In that
1447    case, we would be getting the wrong value of I2DEST into I3, so we
1448    must reject the combination.  This case occurs when I2 and I1 both
1449    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1450    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1451    of a SET must prevent combination from occurring.
1452
1453    Before doing the above check, we first try to expand a field assignment
1454    into a set of logical operations.
1455
1456    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1457    we place a register that is both set and used within I3.  If more than one
1458    such register is detected, we fail.
1459
1460    Return 1 if the combination is valid, zero otherwise.  */
1461
1462 static int
1463 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1464                   int i1_not_in_src, rtx *pi3dest_killed)
1465 {
1466   rtx x = *loc;
1467
1468   if (GET_CODE (x) == SET)
1469     {
1470       rtx set = x ;
1471       rtx dest = SET_DEST (set);
1472       rtx src = SET_SRC (set);
1473       rtx inner_dest = dest;
1474       rtx subdest;
1475
1476       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1477              || GET_CODE (inner_dest) == SUBREG
1478              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1479         inner_dest = XEXP (inner_dest, 0);
1480
1481       /* Check for the case where I3 modifies its output, as discussed
1482          above.  We don't want to prevent pseudos from being combined
1483          into the address of a MEM, so only prevent the combination if
1484          i1 or i2 set the same MEM.  */
1485       if ((inner_dest != dest &&
1486            (!MEM_P (inner_dest)
1487             || rtx_equal_p (i2dest, inner_dest)
1488             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1489            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1490                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1491
1492           /* This is the same test done in can_combine_p except we can't test
1493              all_adjacent; we don't have to, since this instruction will stay
1494              in place, thus we are not considering increasing the lifetime of
1495              INNER_DEST.
1496
1497              Also, if this insn sets a function argument, combining it with
1498              something that might need a spill could clobber a previous
1499              function argument; the all_adjacent test in can_combine_p also
1500              checks this; here, we do a more specific test for this case.  */
1501
1502           || (REG_P (inner_dest)
1503               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1504               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1505                                         GET_MODE (inner_dest))))
1506           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1507         return 0;
1508
1509       /* If DEST is used in I3, it is being killed in this insn, so
1510          record that for later.  We have to consider paradoxical
1511          subregs here, since they kill the whole register, but we
1512          ignore partial subregs, STRICT_LOW_PART, etc.
1513          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1514          STACK_POINTER_REGNUM, since these are always considered to be
1515          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1516       subdest = dest;
1517       if (GET_CODE (subdest) == SUBREG
1518           && (GET_MODE_SIZE (GET_MODE (subdest))
1519               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1520         subdest = SUBREG_REG (subdest);
1521       if (pi3dest_killed
1522           && REG_P (subdest)
1523           && reg_referenced_p (subdest, PATTERN (i3))
1524           && REGNO (subdest) != FRAME_POINTER_REGNUM
1525 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1527 #endif
1528 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529           && (REGNO (subdest) != ARG_POINTER_REGNUM
1530               || ! fixed_regs [REGNO (subdest)])
1531 #endif
1532           && REGNO (subdest) != STACK_POINTER_REGNUM)
1533         {
1534           if (*pi3dest_killed)
1535             return 0;
1536
1537           *pi3dest_killed = subdest;
1538         }
1539     }
1540
1541   else if (GET_CODE (x) == PARALLEL)
1542     {
1543       int i;
1544
1545       for (i = 0; i < XVECLEN (x, 0); i++)
1546         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1547                                 i1_not_in_src, pi3dest_killed))
1548           return 0;
1549     }
1550
1551   return 1;
1552 }
1553 \f
1554 /* Return 1 if X is an arithmetic expression that contains a multiplication
1555    and division.  We don't count multiplications by powers of two here.  */
1556
1557 static int
1558 contains_muldiv (rtx x)
1559 {
1560   switch (GET_CODE (x))
1561     {
1562     case MOD:  case DIV:  case UMOD:  case UDIV:
1563       return 1;
1564
1565     case MULT:
1566       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1567                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1568     default:
1569       if (BINARY_P (x))
1570         return contains_muldiv (XEXP (x, 0))
1571             || contains_muldiv (XEXP (x, 1));
1572
1573       if (UNARY_P (x))
1574         return contains_muldiv (XEXP (x, 0));
1575
1576       return 0;
1577     }
1578 }
1579 \f
1580 /* Determine whether INSN can be used in a combination.  Return nonzero if
1581    not.  This is used in try_combine to detect early some cases where we
1582    can't perform combinations.  */
1583
1584 static int
1585 cant_combine_insn_p (rtx insn)
1586 {
1587   rtx set;
1588   rtx src, dest;
1589
1590   /* If this isn't really an insn, we can't do anything.
1591      This can occur when flow deletes an insn that it has merged into an
1592      auto-increment address.  */
1593   if (! INSN_P (insn))
1594     return 1;
1595
1596   /* Never combine loads and stores involving hard regs that are likely
1597      to be spilled.  The register allocator can usually handle such
1598      reg-reg moves by tying.  If we allow the combiner to make
1599      substitutions of likely-spilled regs, reload might die.
1600      As an exception, we allow combinations involving fixed regs; these are
1601      not available to the register allocator so there's no risk involved.  */
1602
1603   set = single_set (insn);
1604   if (! set)
1605     return 0;
1606   src = SET_SRC (set);
1607   dest = SET_DEST (set);
1608   if (GET_CODE (src) == SUBREG)
1609     src = SUBREG_REG (src);
1610   if (GET_CODE (dest) == SUBREG)
1611     dest = SUBREG_REG (dest);
1612   if (REG_P (src) && REG_P (dest)
1613       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1614            && ! fixed_regs[REGNO (src)]
1615            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1616           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1617               && ! fixed_regs[REGNO (dest)]
1618               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1619     return 1;
1620
1621   return 0;
1622 }
1623
1624 struct likely_spilled_retval_info
1625 {
1626   unsigned regno, nregs;
1627   unsigned mask;
1628 };
1629
1630 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1631    hard registers that are known to be written to / clobbered in full.  */
1632 static void
1633 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1634 {
1635   struct likely_spilled_retval_info *info = data;
1636   unsigned regno, nregs;
1637   unsigned new_mask;
1638
1639   if (!REG_P (XEXP (set, 0)))
1640     return;
1641   regno = REGNO (x);
1642   if (regno >= info->regno + info->nregs)
1643     return;
1644   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1645   if (regno + nregs <= info->regno)
1646     return;
1647   new_mask = (2U << (nregs - 1)) - 1;
1648   if (regno < info->regno)
1649     new_mask >>= info->regno - regno;
1650   else
1651     new_mask <<= regno - info->regno;
1652   info->mask &= new_mask;
1653 }
1654
1655 /* Return nonzero iff part of the return value is live during INSN, and
1656    it is likely spilled.  This can happen when more than one insn is needed
1657    to copy the return value, e.g. when we consider to combine into the
1658    second copy insn for a complex value.  */
1659
1660 static int
1661 likely_spilled_retval_p (rtx insn)
1662 {
1663   rtx use = BB_END (this_basic_block);
1664   rtx reg, p;
1665   unsigned regno, nregs;
1666   /* We assume here that no machine mode needs more than
1667      32 hard registers when the value overlaps with a register
1668      for which FUNCTION_VALUE_REGNO_P is true.  */
1669   unsigned mask;
1670   struct likely_spilled_retval_info info;
1671
1672   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1673     return 0;
1674   reg = XEXP (PATTERN (use), 0);
1675   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1676     return 0;
1677   regno = REGNO (reg);
1678   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1679   if (nregs == 1)
1680     return 0;
1681   mask = (2U << (nregs - 1)) - 1;
1682
1683   /* Disregard parts of the return value that are set later.  */
1684   info.regno = regno;
1685   info.nregs = nregs;
1686   info.mask = mask;
1687   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1688     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1689   mask = info.mask;
1690
1691   /* Check if any of the (probably) live return value registers is
1692      likely spilled.  */
1693   nregs --;
1694   do
1695     {
1696       if ((mask & 1 << nregs)
1697           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1698         return 1;
1699     } while (nregs--);
1700   return 0;
1701 }
1702
1703 /* Adjust INSN after we made a change to its destination.
1704
1705    Changing the destination can invalidate notes that say something about
1706    the results of the insn and a LOG_LINK pointing to the insn.  */
1707
1708 static void
1709 adjust_for_new_dest (rtx insn)
1710 {
1711   rtx *loc;
1712
1713   /* For notes, be conservative and simply remove them.  */
1714   loc = &REG_NOTES (insn);
1715   while (*loc)
1716     {
1717       enum reg_note kind = REG_NOTE_KIND (*loc);
1718       if (kind == REG_EQUAL || kind == REG_EQUIV)
1719         *loc = XEXP (*loc, 1);
1720       else
1721         loc = &XEXP (*loc, 1);
1722     }
1723
1724   /* The new insn will have a destination that was previously the destination
1725      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1726      the next use of that destination.  */
1727   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1728 }
1729
1730 /* Return TRUE if combine can reuse reg X in mode MODE.
1731    ADDED_SETS is nonzero if the original set is still required.  */
1732 static bool
1733 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1734 {
1735   unsigned int regno;
1736
1737   if (!REG_P(x))
1738     return false;
1739
1740   regno = REGNO (x);
1741   /* Allow hard registers if the new mode is legal, and occupies no more
1742      registers than the old mode.  */
1743   if (regno < FIRST_PSEUDO_REGISTER)
1744     return (HARD_REGNO_MODE_OK (regno, mode)
1745             && (hard_regno_nregs[regno][GET_MODE (x)]
1746                 >= hard_regno_nregs[regno][mode]));
1747
1748   /* Or a pseudo that is only used once.  */
1749   return (REG_N_SETS (regno) == 1 && !added_sets
1750           && !REG_USERVAR_P (x));
1751 }
1752
1753
1754 /* Check whether X, the destination of a set, refers to part of
1755    the register specified by REG.  */
1756
1757 static bool
1758 reg_subword_p (rtx x, rtx reg)
1759 {
1760   /* Check that reg is an integer mode register.  */
1761   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1762     return false;
1763
1764   if (GET_CODE (x) == STRICT_LOW_PART
1765       || GET_CODE (x) == ZERO_EXTRACT)
1766     x = XEXP (x, 0);
1767
1768   return GET_CODE (x) == SUBREG
1769          && SUBREG_REG (x) == reg
1770          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1771 }
1772
1773
1774 /* Try to combine the insns I1 and I2 into I3.
1775    Here I1 and I2 appear earlier than I3.
1776    I1 can be zero; then we combine just I2 into I3.
1777
1778    If we are combining three insns and the resulting insn is not recognized,
1779    try splitting it into two insns.  If that happens, I2 and I3 are retained
1780    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1781    are pseudo-deleted.
1782
1783    Return 0 if the combination does not work.  Then nothing is changed.
1784    If we did the combination, return the insn at which combine should
1785    resume scanning.
1786
1787    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1788    new direct jump instruction.  */
1789
1790 static rtx
1791 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1792 {
1793   /* New patterns for I3 and I2, respectively.  */
1794   rtx newpat, newi2pat = 0;
1795   rtvec newpat_vec_with_clobbers = 0;
1796   int substed_i2 = 0, substed_i1 = 0;
1797   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1798   int added_sets_1, added_sets_2;
1799   /* Total number of SETs to put into I3.  */
1800   int total_sets;
1801   /* Nonzero if I2's body now appears in I3.  */
1802   int i2_is_used;
1803   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1804   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1805   /* Contains I3 if the destination of I3 is used in its source, which means
1806      that the old life of I3 is being killed.  If that usage is placed into
1807      I2 and not in I3, a REG_DEAD note must be made.  */
1808   rtx i3dest_killed = 0;
1809   /* SET_DEST and SET_SRC of I2 and I1.  */
1810   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1811   /* PATTERN (I2), or a copy of it in certain cases.  */
1812   rtx i2pat;
1813   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1814   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1815   int i2dest_killed = 0, i1dest_killed = 0;
1816   int i1_feeds_i3 = 0;
1817   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1818   rtx new_i3_notes, new_i2_notes;
1819   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1820   int i3_subst_into_i2 = 0;
1821   /* Notes that I1, I2 or I3 is a MULT operation.  */
1822   int have_mult = 0;
1823   int swap_i2i3 = 0;
1824
1825   int maxreg;
1826   rtx temp;
1827   rtx link;
1828   int i;
1829
1830   /* Exit early if one of the insns involved can't be used for
1831      combinations.  */
1832   if (cant_combine_insn_p (i3)
1833       || cant_combine_insn_p (i2)
1834       || (i1 && cant_combine_insn_p (i1))
1835       || likely_spilled_retval_p (i3)
1836       /* We also can't do anything if I3 has a
1837          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1838          libcall.  */
1839 #if 0
1840       /* ??? This gives worse code, and appears to be unnecessary, since no
1841          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1842       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1843 #endif
1844       )
1845     return 0;
1846
1847   combine_attempts++;
1848   undobuf.other_insn = 0;
1849
1850   /* Reset the hard register usage information.  */
1851   CLEAR_HARD_REG_SET (newpat_used_regs);
1852
1853   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1854      code below, set I1 to be the earlier of the two insns.  */
1855   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1856     temp = i1, i1 = i2, i2 = temp;
1857
1858   added_links_insn = 0;
1859
1860   /* First check for one important special-case that the code below will
1861      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1862      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1863      we may be able to replace that destination with the destination of I3.
1864      This occurs in the common code where we compute both a quotient and
1865      remainder into a structure, in which case we want to do the computation
1866      directly into the structure to avoid register-register copies.
1867
1868      Note that this case handles both multiple sets in I2 and also
1869      cases where I2 has a number of CLOBBER or PARALLELs.
1870
1871      We make very conservative checks below and only try to handle the
1872      most common cases of this.  For example, we only handle the case
1873      where I2 and I3 are adjacent to avoid making difficult register
1874      usage tests.  */
1875
1876   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1877       && REG_P (SET_SRC (PATTERN (i3)))
1878       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1879       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1880       && GET_CODE (PATTERN (i2)) == PARALLEL
1881       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1882       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1883          below would need to check what is inside (and reg_overlap_mentioned_p
1884          doesn't support those codes anyway).  Don't allow those destinations;
1885          the resulting insn isn't likely to be recognized anyway.  */
1886       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1887       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1888       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1889                                     SET_DEST (PATTERN (i3)))
1890       && next_real_insn (i2) == i3)
1891     {
1892       rtx p2 = PATTERN (i2);
1893
1894       /* Make sure that the destination of I3,
1895          which we are going to substitute into one output of I2,
1896          is not used within another output of I2.  We must avoid making this:
1897          (parallel [(set (mem (reg 69)) ...)
1898                     (set (reg 69) ...)])
1899          which is not well-defined as to order of actions.
1900          (Besides, reload can't handle output reloads for this.)
1901
1902          The problem can also happen if the dest of I3 is a memory ref,
1903          if another dest in I2 is an indirect memory ref.  */
1904       for (i = 0; i < XVECLEN (p2, 0); i++)
1905         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1906              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1907             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1908                                         SET_DEST (XVECEXP (p2, 0, i))))
1909           break;
1910
1911       if (i == XVECLEN (p2, 0))
1912         for (i = 0; i < XVECLEN (p2, 0); i++)
1913           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1914                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1915               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1916             {
1917               combine_merges++;
1918
1919               subst_insn = i3;
1920               subst_low_cuid = INSN_CUID (i2);
1921
1922               added_sets_2 = added_sets_1 = 0;
1923               i2dest = SET_SRC (PATTERN (i3));
1924               i2dest_killed = dead_or_set_p (i2, i2dest);
1925
1926               /* Replace the dest in I2 with our dest and make the resulting
1927                  insn the new pattern for I3.  Then skip to where we
1928                  validate the pattern.  Everything was set up above.  */
1929               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1930                      SET_DEST (PATTERN (i3)));
1931
1932               newpat = p2;
1933               i3_subst_into_i2 = 1;
1934               goto validate_replacement;
1935             }
1936     }
1937
1938   /* If I2 is setting a pseudo to a constant and I3 is setting some
1939      sub-part of it to another constant, merge them by making a new
1940      constant.  */
1941   if (i1 == 0
1942       && (temp = single_set (i2)) != 0
1943       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1944           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1945       && GET_CODE (PATTERN (i3)) == SET
1946       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1947           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1948       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1949     {
1950       rtx dest = SET_DEST (PATTERN (i3));
1951       int offset = -1;
1952       int width = 0;
1953
1954       if (GET_CODE (dest) == ZERO_EXTRACT)
1955         {
1956           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1957               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1958             {
1959               width = INTVAL (XEXP (dest, 1));
1960               offset = INTVAL (XEXP (dest, 2));
1961               dest = XEXP (dest, 0);
1962               if (BITS_BIG_ENDIAN)
1963                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1964             }
1965         }
1966       else
1967         {
1968           if (GET_CODE (dest) == STRICT_LOW_PART)
1969             dest = XEXP (dest, 0);
1970           width = GET_MODE_BITSIZE (GET_MODE (dest));
1971           offset = 0;
1972         }
1973
1974       if (offset >= 0)
1975         {
1976           /* If this is the low part, we're done.  */
1977           if (subreg_lowpart_p (dest))
1978             ;
1979           /* Handle the case where inner is twice the size of outer.  */
1980           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1981                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1982             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1983           /* Otherwise give up for now.  */
1984           else
1985             offset = -1;
1986         }
1987
1988       if (offset >= 0)
1989         {
1990           HOST_WIDE_INT mhi, ohi, ihi;
1991           HOST_WIDE_INT mlo, olo, ilo;
1992           rtx inner = SET_SRC (PATTERN (i3));
1993           rtx outer = SET_SRC (temp);
1994
1995           if (GET_CODE (outer) == CONST_INT)
1996             {
1997               olo = INTVAL (outer);
1998               ohi = olo < 0 ? -1 : 0;
1999             }
2000           else
2001             {
2002               olo = CONST_DOUBLE_LOW (outer);
2003               ohi = CONST_DOUBLE_HIGH (outer);
2004             }
2005
2006           if (GET_CODE (inner) == CONST_INT)
2007             {
2008               ilo = INTVAL (inner);
2009               ihi = ilo < 0 ? -1 : 0;
2010             }
2011           else
2012             {
2013               ilo = CONST_DOUBLE_LOW (inner);
2014               ihi = CONST_DOUBLE_HIGH (inner);
2015             }
2016
2017           if (width < HOST_BITS_PER_WIDE_INT)
2018             {
2019               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2020               mhi = 0;
2021             }
2022           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2023             {
2024               mhi = ((unsigned HOST_WIDE_INT) 1
2025                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2026               mlo = -1;
2027             }
2028           else
2029             {
2030               mlo = -1;
2031               mhi = -1;
2032             }
2033
2034           ilo &= mlo;
2035           ihi &= mhi;
2036
2037           if (offset >= HOST_BITS_PER_WIDE_INT)
2038             {
2039               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2040               mlo = 0;
2041               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2042               ilo = 0;
2043             }
2044           else if (offset > 0)
2045             {
2046               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2047                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2048               mlo = mlo << offset;
2049               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2050                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2051               ilo = ilo << offset;
2052             }
2053
2054           olo = (olo & ~mlo) | ilo;
2055           ohi = (ohi & ~mhi) | ihi;
2056
2057           combine_merges++;
2058           subst_insn = i3;
2059           subst_low_cuid = INSN_CUID (i2);
2060           added_sets_2 = added_sets_1 = 0;
2061           i2dest = SET_DEST (temp);
2062           i2dest_killed = dead_or_set_p (i2, i2dest);
2063
2064           SUBST (SET_SRC (temp),
2065                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2066
2067           newpat = PATTERN (i2);
2068           goto validate_replacement;
2069         }
2070     }
2071
2072 #ifndef HAVE_cc0
2073   /* If we have no I1 and I2 looks like:
2074         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2075                    (set Y OP)])
2076      make up a dummy I1 that is
2077         (set Y OP)
2078      and change I2 to be
2079         (set (reg:CC X) (compare:CC Y (const_int 0)))
2080
2081      (We can ignore any trailing CLOBBERs.)
2082
2083      This undoes a previous combination and allows us to match a branch-and-
2084      decrement insn.  */
2085
2086   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2087       && XVECLEN (PATTERN (i2), 0) >= 2
2088       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2089       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2090           == MODE_CC)
2091       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2092       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2093       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2094       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2095       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2096                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2097     {
2098       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2099         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2100           break;
2101
2102       if (i == 1)
2103         {
2104           /* We make I1 with the same INSN_UID as I2.  This gives it
2105              the same INSN_CUID for value tracking.  Our fake I1 will
2106              never appear in the insn stream so giving it the same INSN_UID
2107              as I2 will not cause a problem.  */
2108
2109           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2110                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2111                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2112                              NULL_RTX);
2113
2114           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2115           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2116                  SET_DEST (PATTERN (i1)));
2117         }
2118     }
2119 #endif
2120
2121   /* Verify that I2 and I1 are valid for combining.  */
2122   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2123       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2124     {
2125       undo_all ();
2126       return 0;
2127     }
2128
2129   /* Record whether I2DEST is used in I2SRC and similarly for the other
2130      cases.  Knowing this will help in register status updating below.  */
2131   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2132   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2133   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2134   i2dest_killed = dead_or_set_p (i2, i2dest);
2135   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2136
2137   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2138      in I2SRC.  */
2139   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2140
2141   /* Ensure that I3's pattern can be the destination of combines.  */
2142   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2143                           i1 && i2dest_in_i1src && i1_feeds_i3,
2144                           &i3dest_killed))
2145     {
2146       undo_all ();
2147       return 0;
2148     }
2149
2150   /* See if any of the insns is a MULT operation.  Unless one is, we will
2151      reject a combination that is, since it must be slower.  Be conservative
2152      here.  */
2153   if (GET_CODE (i2src) == MULT
2154       || (i1 != 0 && GET_CODE (i1src) == MULT)
2155       || (GET_CODE (PATTERN (i3)) == SET
2156           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2157     have_mult = 1;
2158
2159   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2160      We used to do this EXCEPT in one case: I3 has a post-inc in an
2161      output operand.  However, that exception can give rise to insns like
2162         mov r3,(r3)+
2163      which is a famous insn on the PDP-11 where the value of r3 used as the
2164      source was model-dependent.  Avoid this sort of thing.  */
2165
2166 #if 0
2167   if (!(GET_CODE (PATTERN (i3)) == SET
2168         && REG_P (SET_SRC (PATTERN (i3)))
2169         && MEM_P (SET_DEST (PATTERN (i3)))
2170         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2171             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2172     /* It's not the exception.  */
2173 #endif
2174 #ifdef AUTO_INC_DEC
2175     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2176       if (REG_NOTE_KIND (link) == REG_INC
2177           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2178               || (i1 != 0
2179                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2180         {
2181           undo_all ();
2182           return 0;
2183         }
2184 #endif
2185
2186   /* See if the SETs in I1 or I2 need to be kept around in the merged
2187      instruction: whenever the value set there is still needed past I3.
2188      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2189
2190      For the SET in I1, we have two cases:  If I1 and I2 independently
2191      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2192      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2193      in I1 needs to be kept around unless I1DEST dies or is set in either
2194      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2195      I1DEST.  If so, we know I1 feeds into I2.  */
2196
2197   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2198
2199   added_sets_1
2200     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2201                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2202
2203   /* If the set in I2 needs to be kept around, we must make a copy of
2204      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2205      PATTERN (I2), we are only substituting for the original I1DEST, not into
2206      an already-substituted copy.  This also prevents making self-referential
2207      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2208      I2DEST.  */
2209
2210   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2211            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2212            : PATTERN (i2));
2213
2214   if (added_sets_2)
2215     i2pat = copy_rtx (i2pat);
2216
2217   combine_merges++;
2218
2219   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2220
2221   maxreg = max_reg_num ();
2222
2223   subst_insn = i3;
2224
2225 #ifndef HAVE_cc0
2226   /* Many machines that don't use CC0 have insns that can both perform an
2227      arithmetic operation and set the condition code.  These operations will
2228      be represented as a PARALLEL with the first element of the vector
2229      being a COMPARE of an arithmetic operation with the constant zero.
2230      The second element of the vector will set some pseudo to the result
2231      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2232      match such a pattern and so will generate an extra insn.   Here we test
2233      for this case, where both the comparison and the operation result are
2234      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2235      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2236
2237   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2238       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2239       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2240       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2241     {
2242 #ifdef SELECT_CC_MODE
2243       rtx *cc_use;
2244       enum machine_mode compare_mode;
2245 #endif
2246
2247       newpat = PATTERN (i3);
2248       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2249
2250       i2_is_used = 1;
2251
2252 #ifdef SELECT_CC_MODE
2253       /* See if a COMPARE with the operand we substituted in should be done
2254          with the mode that is currently being used.  If not, do the same
2255          processing we do in `subst' for a SET; namely, if the destination
2256          is used only once, try to replace it with a register of the proper
2257          mode and also replace the COMPARE.  */
2258       if (undobuf.other_insn == 0
2259           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2260                                         &undobuf.other_insn))
2261           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2262                                               i2src, const0_rtx))
2263               != GET_MODE (SET_DEST (newpat))))
2264         {
2265           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2266                                    compare_mode))
2267             {
2268               unsigned int regno = REGNO (SET_DEST (newpat));
2269               rtx new_dest;
2270
2271               if (regno < FIRST_PSEUDO_REGISTER)
2272                 new_dest = gen_rtx_REG (compare_mode, regno);
2273               else
2274                 {
2275                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2276                   new_dest = regno_reg_rtx[regno];
2277                 }
2278
2279               SUBST (SET_DEST (newpat), new_dest);
2280               SUBST (XEXP (*cc_use, 0), new_dest);
2281               SUBST (SET_SRC (newpat),
2282                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2283             }
2284           else
2285             undobuf.other_insn = 0;
2286         }
2287 #endif
2288     }
2289   else
2290 #endif
2291     {
2292       /* It is possible that the source of I2 or I1 may be performing
2293          an unneeded operation, such as a ZERO_EXTEND of something
2294          that is known to have the high part zero.  Handle that case
2295          by letting subst look at the innermost one of them.
2296
2297          Another way to do this would be to have a function that tries
2298          to simplify a single insn instead of merging two or more
2299          insns.  We don't do this because of the potential of infinite
2300          loops and because of the potential extra memory required.
2301          However, doing it the way we are is a bit of a kludge and
2302          doesn't catch all cases.
2303
2304          But only do this if -fexpensive-optimizations since it slows
2305          things down and doesn't usually win.
2306
2307          This is not done in the COMPARE case above because the
2308          unmodified I2PAT is used in the PARALLEL and so a pattern
2309          with a modified I2SRC would not match.  */
2310
2311       if (flag_expensive_optimizations)
2312         {
2313           /* Pass pc_rtx so no substitutions are done, just
2314              simplifications.  */
2315           if (i1)
2316             {
2317               subst_low_cuid = INSN_CUID (i1);
2318               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2319             }
2320           else
2321             {
2322               subst_low_cuid = INSN_CUID (i2);
2323               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2324             }
2325         }
2326
2327       n_occurrences = 0;                /* `subst' counts here */
2328
2329       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2330          need to make a unique copy of I2SRC each time we substitute it
2331          to avoid self-referential rtl.  */
2332
2333       subst_low_cuid = INSN_CUID (i2);
2334       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2335                       ! i1_feeds_i3 && i1dest_in_i1src);
2336       substed_i2 = 1;
2337
2338       /* Record whether i2's body now appears within i3's body.  */
2339       i2_is_used = n_occurrences;
2340     }
2341
2342   /* If we already got a failure, don't try to do more.  Otherwise,
2343      try to substitute in I1 if we have it.  */
2344
2345   if (i1 && GET_CODE (newpat) != CLOBBER)
2346     {
2347       /* Before we can do this substitution, we must redo the test done
2348          above (see detailed comments there) that ensures  that I1DEST
2349          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2350
2351       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2352                               0, (rtx*) 0))
2353         {
2354           undo_all ();
2355           return 0;
2356         }
2357
2358       n_occurrences = 0;
2359       subst_low_cuid = INSN_CUID (i1);
2360       newpat = subst (newpat, i1dest, i1src, 0, 0);
2361       substed_i1 = 1;
2362     }
2363
2364   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2365      to count all the ways that I2SRC and I1SRC can be used.  */
2366   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2367        && i2_is_used + added_sets_2 > 1)
2368       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2369           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2370               > 1))
2371       /* Fail if we tried to make a new register.  */
2372       || max_reg_num () != maxreg
2373       /* Fail if we couldn't do something and have a CLOBBER.  */
2374       || GET_CODE (newpat) == CLOBBER
2375       /* Fail if this new pattern is a MULT and we didn't have one before
2376          at the outer level.  */
2377       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2378           && ! have_mult))
2379     {
2380       undo_all ();
2381       return 0;
2382     }
2383
2384   /* If the actions of the earlier insns must be kept
2385      in addition to substituting them into the latest one,
2386      we must make a new PARALLEL for the latest insn
2387      to hold additional the SETs.  */
2388
2389   if (added_sets_1 || added_sets_2)
2390     {
2391       combine_extras++;
2392
2393       if (GET_CODE (newpat) == PARALLEL)
2394         {
2395           rtvec old = XVEC (newpat, 0);
2396           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2397           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2398           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2399                   sizeof (old->elem[0]) * old->num_elem);
2400         }
2401       else
2402         {
2403           rtx old = newpat;
2404           total_sets = 1 + added_sets_1 + added_sets_2;
2405           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2406           XVECEXP (newpat, 0, 0) = old;
2407         }
2408
2409       if (added_sets_1)
2410         XVECEXP (newpat, 0, --total_sets)
2411           = (GET_CODE (PATTERN (i1)) == PARALLEL
2412              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2413
2414       if (added_sets_2)
2415         {
2416           /* If there is no I1, use I2's body as is.  We used to also not do
2417              the subst call below if I2 was substituted into I3,
2418              but that could lose a simplification.  */
2419           if (i1 == 0)
2420             XVECEXP (newpat, 0, --total_sets) = i2pat;
2421           else
2422             /* See comment where i2pat is assigned.  */
2423             XVECEXP (newpat, 0, --total_sets)
2424               = subst (i2pat, i1dest, i1src, 0, 0);
2425         }
2426     }
2427
2428   /* We come here when we are replacing a destination in I2 with the
2429      destination of I3.  */
2430  validate_replacement:
2431
2432   /* Note which hard regs this insn has as inputs.  */
2433   mark_used_regs_combine (newpat);
2434
2435   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2436      consider splitting this pattern, we might need these clobbers.  */
2437   if (i1 && GET_CODE (newpat) == PARALLEL
2438       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2439     {
2440       int len = XVECLEN (newpat, 0);
2441
2442       newpat_vec_with_clobbers = rtvec_alloc (len);
2443       for (i = 0; i < len; i++)
2444         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2445     }
2446
2447   /* Is the result of combination a valid instruction?  */
2448   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2449
2450   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2451      the second SET's destination is a register that is unused and isn't
2452      marked as an instruction that might trap in an EH region.  In that case,
2453      we just need the first SET.   This can occur when simplifying a divmod
2454      insn.  We *must* test for this case here because the code below that
2455      splits two independent SETs doesn't handle this case correctly when it
2456      updates the register status.
2457
2458      It's pointless doing this if we originally had two sets, one from
2459      i3, and one from i2.  Combining then splitting the parallel results
2460      in the original i2 again plus an invalid insn (which we delete).
2461      The net effect is only to move instructions around, which makes
2462      debug info less accurate.
2463
2464      Also check the case where the first SET's destination is unused.
2465      That would not cause incorrect code, but does cause an unneeded
2466      insn to remain.  */
2467
2468   if (insn_code_number < 0
2469       && !(added_sets_2 && i1 == 0)
2470       && GET_CODE (newpat) == PARALLEL
2471       && XVECLEN (newpat, 0) == 2
2472       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2473       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2474       && asm_noperands (newpat) < 0)
2475     {
2476       rtx set0 = XVECEXP (newpat, 0, 0);
2477       rtx set1 = XVECEXP (newpat, 0, 1);
2478       rtx note;
2479
2480       if (((REG_P (SET_DEST (set1))
2481             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2482            || (GET_CODE (SET_DEST (set1)) == SUBREG
2483                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2484           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2485               || INTVAL (XEXP (note, 0)) <= 0)
2486           && ! side_effects_p (SET_SRC (set1)))
2487         {
2488           newpat = set0;
2489           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2490         }
2491
2492       else if (((REG_P (SET_DEST (set0))
2493                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2494                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2495                     && find_reg_note (i3, REG_UNUSED,
2496                                       SUBREG_REG (SET_DEST (set0)))))
2497                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2498                    || INTVAL (XEXP (note, 0)) <= 0)
2499                && ! side_effects_p (SET_SRC (set0)))
2500         {
2501           newpat = set1;
2502           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2503
2504           if (insn_code_number >= 0)
2505             {
2506               /* If we will be able to accept this, we have made a
2507                  change to the destination of I3.  This requires us to
2508                  do a few adjustments.  */
2509
2510               PATTERN (i3) = newpat;
2511               adjust_for_new_dest (i3);
2512             }
2513         }
2514     }
2515
2516   /* If we were combining three insns and the result is a simple SET
2517      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2518      insns.  There are two ways to do this.  It can be split using a
2519      machine-specific method (like when you have an addition of a large
2520      constant) or by combine in the function find_split_point.  */
2521
2522   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2523       && asm_noperands (newpat) < 0)
2524     {
2525       rtx m_split, *split;
2526
2527       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2528          use I2DEST as a scratch register will help.  In the latter case,
2529          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2530
2531       m_split = split_insns (newpat, i3);
2532
2533       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2534          inputs of NEWPAT.  */
2535
2536       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2537          possible to try that as a scratch reg.  This would require adding
2538          more code to make it work though.  */
2539
2540       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2541         {
2542           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2543
2544           /* First try to split using the original register as a
2545              scratch register.  */
2546           m_split = split_insns (gen_rtx_PARALLEL
2547                                  (VOIDmode,
2548                                   gen_rtvec (2, newpat,
2549                                              gen_rtx_CLOBBER (VOIDmode,
2550                                                               i2dest))),
2551                                  i3);
2552
2553           /* If that didn't work, try changing the mode of I2DEST if
2554              we can.  */
2555           if (m_split == 0
2556               && new_mode != GET_MODE (i2dest)
2557               && new_mode != VOIDmode
2558               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2559             {
2560               enum machine_mode old_mode = GET_MODE (i2dest);
2561               rtx ni2dest;
2562
2563               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2564                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2565               else
2566                 {
2567                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2568                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2569                 }
2570
2571               m_split = split_insns (gen_rtx_PARALLEL
2572                                      (VOIDmode,
2573                                       gen_rtvec (2, newpat,
2574                                                  gen_rtx_CLOBBER (VOIDmode,
2575                                                                   ni2dest))),
2576                                      i3);
2577
2578               if (m_split == 0
2579                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2580                 {
2581                   struct undo *buf;
2582
2583                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2584                   buf = undobuf.undos;
2585                   undobuf.undos = buf->next;
2586                   buf->next = undobuf.frees;
2587                   undobuf.frees = buf;
2588                 }
2589             }
2590         }
2591
2592       /* If recog_for_combine has discarded clobbers, try to use them
2593          again for the split.  */
2594       if (m_split == 0 && newpat_vec_with_clobbers)
2595         m_split
2596           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2597                                            newpat_vec_with_clobbers), i3);
2598
2599       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2600         {
2601           m_split = PATTERN (m_split);
2602           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2603           if (insn_code_number >= 0)
2604             newpat = m_split;
2605         }
2606       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2607                && (next_real_insn (i2) == i3
2608                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2609         {
2610           rtx i2set, i3set;
2611           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2612           newi2pat = PATTERN (m_split);
2613
2614           i3set = single_set (NEXT_INSN (m_split));
2615           i2set = single_set (m_split);
2616
2617           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2618
2619           /* If I2 or I3 has multiple SETs, we won't know how to track
2620              register status, so don't use these insns.  If I2's destination
2621              is used between I2 and I3, we also can't use these insns.  */
2622
2623           if (i2_code_number >= 0 && i2set && i3set
2624               && (next_real_insn (i2) == i3
2625                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2626             insn_code_number = recog_for_combine (&newi3pat, i3,
2627                                                   &new_i3_notes);
2628           if (insn_code_number >= 0)
2629             newpat = newi3pat;
2630
2631           /* It is possible that both insns now set the destination of I3.
2632              If so, we must show an extra use of it.  */
2633
2634           if (insn_code_number >= 0)
2635             {
2636               rtx new_i3_dest = SET_DEST (i3set);
2637               rtx new_i2_dest = SET_DEST (i2set);
2638
2639               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2640                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2641                      || GET_CODE (new_i3_dest) == SUBREG)
2642                 new_i3_dest = XEXP (new_i3_dest, 0);
2643
2644               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2645                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2646                      || GET_CODE (new_i2_dest) == SUBREG)
2647                 new_i2_dest = XEXP (new_i2_dest, 0);
2648
2649               if (REG_P (new_i3_dest)
2650                   && REG_P (new_i2_dest)
2651                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2652                 REG_N_SETS (REGNO (new_i2_dest))++;
2653             }
2654         }
2655
2656       /* If we can split it and use I2DEST, go ahead and see if that
2657          helps things be recognized.  Verify that none of the registers
2658          are set between I2 and I3.  */
2659       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2660 #ifdef HAVE_cc0
2661           && REG_P (i2dest)
2662 #endif
2663           /* We need I2DEST in the proper mode.  If it is a hard register
2664              or the only use of a pseudo, we can change its mode.
2665              Make sure we don't change a hard register to have a mode that
2666              isn't valid for it, or change the number of registers.  */
2667           && (GET_MODE (*split) == GET_MODE (i2dest)
2668               || GET_MODE (*split) == VOIDmode
2669               || can_change_dest_mode (i2dest, added_sets_2,
2670                                        GET_MODE (*split)))
2671           && (next_real_insn (i2) == i3
2672               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2673           /* We can't overwrite I2DEST if its value is still used by
2674              NEWPAT.  */
2675           && ! reg_referenced_p (i2dest, newpat))
2676         {
2677           rtx newdest = i2dest;
2678           enum rtx_code split_code = GET_CODE (*split);
2679           enum machine_mode split_mode = GET_MODE (*split);
2680           bool subst_done = false;
2681           newi2pat = NULL_RTX;
2682
2683           /* Get NEWDEST as a register in the proper mode.  We have already
2684              validated that we can do this.  */
2685           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2686             {
2687               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2688                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2689               else
2690                 {
2691                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2692                   newdest = regno_reg_rtx[REGNO (i2dest)];
2693                 }
2694             }
2695
2696           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2697              an ASHIFT.  This can occur if it was inside a PLUS and hence
2698              appeared to be a memory address.  This is a kludge.  */
2699           if (split_code == MULT
2700               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2701               && INTVAL (XEXP (*split, 1)) > 0
2702               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2703             {
2704               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2705                                              XEXP (*split, 0), GEN_INT (i)));
2706               /* Update split_code because we may not have a multiply
2707                  anymore.  */
2708               split_code = GET_CODE (*split);
2709             }
2710
2711 #ifdef INSN_SCHEDULING
2712           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2713              be written as a ZERO_EXTEND.  */
2714           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2715             {
2716 #ifdef LOAD_EXTEND_OP
2717               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2718                  what it really is.  */
2719               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2720                   == SIGN_EXTEND)
2721                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2722                                                     SUBREG_REG (*split)));
2723               else
2724 #endif
2725                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2726                                                     SUBREG_REG (*split)));
2727             }
2728 #endif
2729
2730           /* Attempt to split binary operators using arithmetic identities.  */
2731           if (BINARY_P (SET_SRC (newpat))
2732               && split_mode == GET_MODE (SET_SRC (newpat))
2733               && ! side_effects_p (SET_SRC (newpat)))
2734             {
2735               rtx setsrc = SET_SRC (newpat);
2736               enum machine_mode mode = GET_MODE (setsrc);
2737               enum rtx_code code = GET_CODE (setsrc);
2738               rtx src_op0 = XEXP (setsrc, 0);
2739               rtx src_op1 = XEXP (setsrc, 1);
2740
2741               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2742               if (rtx_equal_p (src_op0, src_op1))
2743                 {
2744                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2745                   SUBST (XEXP (setsrc, 0), newdest);
2746                   SUBST (XEXP (setsrc, 1), newdest);
2747                   subst_done = true;
2748                 }
2749               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2750               else if ((code == PLUS || code == MULT)
2751                        && GET_CODE (src_op0) == code
2752                        && GET_CODE (XEXP (src_op0, 0)) == code
2753                        && (INTEGRAL_MODE_P (mode)
2754                            || (FLOAT_MODE_P (mode)
2755                                && flag_unsafe_math_optimizations)))
2756                 {
2757                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2758                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2759                   rtx r = XEXP (src_op0, 1);
2760                   rtx s = src_op1;
2761
2762                   /* Split both "((X op Y) op X) op Y" and
2763                      "((X op Y) op Y) op X" as "T op T" where T is
2764                      "X op Y".  */
2765                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2766                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2767                     {
2768                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2769                                               XEXP (src_op0, 0));
2770                       SUBST (XEXP (setsrc, 0), newdest);
2771                       SUBST (XEXP (setsrc, 1), newdest);
2772                       subst_done = true;
2773                     }
2774                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2775                      T is "X op Y".  */
2776                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2777                     {
2778                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2779                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2780                       SUBST (XEXP (setsrc, 0), newdest);
2781                       SUBST (XEXP (setsrc, 1), newdest);
2782                       subst_done = true;
2783                     }
2784                 }
2785             }
2786
2787           if (!subst_done)
2788             {
2789               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2790               SUBST (*split, newdest);
2791             }
2792
2793           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2794
2795           /* recog_for_combine might have added CLOBBERs to newi2pat.
2796              Make sure NEWPAT does not depend on the clobbered regs.  */
2797           if (GET_CODE (newi2pat) == PARALLEL)
2798             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2799               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2800                 {
2801                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2802                   if (reg_overlap_mentioned_p (reg, newpat))
2803                     {
2804                       undo_all ();
2805                       return 0;
2806                     }
2807                 }
2808
2809           /* If the split point was a MULT and we didn't have one before,
2810              don't use one now.  */
2811           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2812             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2813         }
2814     }
2815
2816   /* Check for a case where we loaded from memory in a narrow mode and
2817      then sign extended it, but we need both registers.  In that case,
2818      we have a PARALLEL with both loads from the same memory location.
2819      We can split this into a load from memory followed by a register-register
2820      copy.  This saves at least one insn, more if register allocation can
2821      eliminate the copy.
2822
2823      We cannot do this if the destination of the first assignment is a
2824      condition code register or cc0.  We eliminate this case by making sure
2825      the SET_DEST and SET_SRC have the same mode.
2826
2827      We cannot do this if the destination of the second assignment is
2828      a register that we have already assumed is zero-extended.  Similarly
2829      for a SUBREG of such a register.  */
2830
2831   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2832            && GET_CODE (newpat) == PARALLEL
2833            && XVECLEN (newpat, 0) == 2
2834            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2835            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2836            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2837                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2838            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2839            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2840                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2841            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2842                                    INSN_CUID (i2))
2843            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2844            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2845            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2846                  (REG_P (temp)
2847                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2848                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2849                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2850                   && (reg_stat[REGNO (temp)].nonzero_bits
2851                       != GET_MODE_MASK (word_mode))))
2852            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2853                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2854                      (REG_P (temp)
2855                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2856                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2857                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2858                       && (reg_stat[REGNO (temp)].nonzero_bits
2859                           != GET_MODE_MASK (word_mode)))))
2860            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2861                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2862            && ! find_reg_note (i3, REG_UNUSED,
2863                                SET_DEST (XVECEXP (newpat, 0, 0))))
2864     {
2865       rtx ni2dest;
2866
2867       newi2pat = XVECEXP (newpat, 0, 0);
2868       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2869       newpat = XVECEXP (newpat, 0, 1);
2870       SUBST (SET_SRC (newpat),
2871              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2872       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2873
2874       if (i2_code_number >= 0)
2875         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2876
2877       if (insn_code_number >= 0)
2878         swap_i2i3 = 1;
2879     }
2880
2881   /* Similarly, check for a case where we have a PARALLEL of two independent
2882      SETs but we started with three insns.  In this case, we can do the sets
2883      as two separate insns.  This case occurs when some SET allows two
2884      other insns to combine, but the destination of that SET is still live.  */
2885
2886   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2887            && GET_CODE (newpat) == PARALLEL
2888            && XVECLEN (newpat, 0) == 2
2889            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2890            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2891            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2892            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2893            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2894            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2895            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2896                                    INSN_CUID (i2))
2897            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2898                                   XVECEXP (newpat, 0, 0))
2899            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2900                                   XVECEXP (newpat, 0, 1))
2901            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2902                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2903     {
2904       /* Normally, it doesn't matter which of the two is done first,
2905          but it does if one references cc0.  In that case, it has to
2906          be first.  */
2907 #ifdef HAVE_cc0
2908       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2909         {
2910           newi2pat = XVECEXP (newpat, 0, 0);
2911           newpat = XVECEXP (newpat, 0, 1);
2912         }
2913       else
2914 #endif
2915         {
2916           newi2pat = XVECEXP (newpat, 0, 1);
2917           newpat = XVECEXP (newpat, 0, 0);
2918         }
2919
2920       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2921
2922       if (i2_code_number >= 0)
2923         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2924     }
2925
2926   /* If it still isn't recognized, fail and change things back the way they
2927      were.  */
2928   if ((insn_code_number < 0
2929        /* Is the result a reasonable ASM_OPERANDS?  */
2930        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2931     {
2932       undo_all ();
2933       return 0;
2934     }
2935
2936   /* If we had to change another insn, make sure it is valid also.  */
2937   if (undobuf.other_insn)
2938     {
2939       rtx other_pat = PATTERN (undobuf.other_insn);
2940       rtx new_other_notes;
2941       rtx note, next;
2942
2943       CLEAR_HARD_REG_SET (newpat_used_regs);
2944
2945       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2946                                              &new_other_notes);
2947
2948       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2949         {
2950           undo_all ();
2951           return 0;
2952         }
2953
2954       PATTERN (undobuf.other_insn) = other_pat;
2955
2956       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2957          are still valid.  Then add any non-duplicate notes added by
2958          recog_for_combine.  */
2959       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2960         {
2961           next = XEXP (note, 1);
2962
2963           if (REG_NOTE_KIND (note) == REG_UNUSED
2964               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2965             {
2966               if (REG_P (XEXP (note, 0)))
2967                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2968
2969               remove_note (undobuf.other_insn, note);
2970             }
2971         }
2972
2973       for (note = new_other_notes; note; note = XEXP (note, 1))
2974         if (REG_P (XEXP (note, 0)))
2975           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2976
2977       distribute_notes (new_other_notes, undobuf.other_insn,
2978                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2979     }
2980 #ifdef HAVE_cc0
2981   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2982      they are adjacent to each other or not.  */
2983   {
2984     rtx p = prev_nonnote_insn (i3);
2985     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2986         && sets_cc0_p (newi2pat))
2987       {
2988         undo_all ();
2989         return 0;
2990       }
2991   }
2992 #endif
2993
2994   /* Only allow this combination if insn_rtx_costs reports that the
2995      replacement instructions are cheaper than the originals.  */
2996   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2997     {
2998       undo_all ();
2999       return 0;
3000     }
3001
3002   /* We now know that we can do this combination.  Merge the insns and
3003      update the status of registers and LOG_LINKS.  */
3004
3005   if (swap_i2i3)
3006     {
3007       rtx insn;
3008       rtx link;
3009       rtx ni2dest;
3010
3011       /* I3 now uses what used to be its destination and which is now
3012          I2's destination.  This requires us to do a few adjustments.  */
3013       PATTERN (i3) = newpat;
3014       adjust_for_new_dest (i3);
3015
3016       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3017          so we still will.
3018
3019          However, some later insn might be using I2's dest and have
3020          a LOG_LINK pointing at I3.  We must remove this link.
3021          The simplest way to remove the link is to point it at I1,
3022          which we know will be a NOTE.  */
3023
3024       /* newi2pat is usually a SET here; however, recog_for_combine might
3025          have added some clobbers.  */
3026       if (GET_CODE (newi2pat) == PARALLEL)
3027         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3028       else
3029         ni2dest = SET_DEST (newi2pat);
3030
3031       for (insn = NEXT_INSN (i3);
3032            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3033                     || insn != BB_HEAD (this_basic_block->next_bb));
3034            insn = NEXT_INSN (insn))
3035         {
3036           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3037             {
3038               for (link = LOG_LINKS (insn); link;
3039                    link = XEXP (link, 1))
3040                 if (XEXP (link, 0) == i3)
3041                   XEXP (link, 0) = i1;
3042
3043               break;
3044             }
3045         }
3046     }
3047
3048   {
3049     rtx i3notes, i2notes, i1notes = 0;
3050     rtx i3links, i2links, i1links = 0;
3051     rtx midnotes = 0;
3052     unsigned int regno;
3053     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3054        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3055        same as i3dest, in which case newi2pat may be setting i1dest.  */
3056     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3057                    || i2dest_in_i2src || i2dest_in_i1src
3058                    || !i2dest_killed
3059                    ? 0 : i2dest);
3060     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3061                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3062                    || !i1dest_killed
3063                    ? 0 : i1dest);
3064
3065     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3066        clear them.  */
3067     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3068     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3069     if (i1)
3070       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3071
3072     /* Ensure that we do not have something that should not be shared but
3073        occurs multiple times in the new insns.  Check this by first
3074        resetting all the `used' flags and then copying anything is shared.  */
3075
3076     reset_used_flags (i3notes);
3077     reset_used_flags (i2notes);
3078     reset_used_flags (i1notes);
3079     reset_used_flags (newpat);
3080     reset_used_flags (newi2pat);
3081     if (undobuf.other_insn)
3082       reset_used_flags (PATTERN (undobuf.other_insn));
3083
3084     i3notes = copy_rtx_if_shared (i3notes);
3085     i2notes = copy_rtx_if_shared (i2notes);
3086     i1notes = copy_rtx_if_shared (i1notes);
3087     newpat = copy_rtx_if_shared (newpat);
3088     newi2pat = copy_rtx_if_shared (newi2pat);
3089     if (undobuf.other_insn)
3090       reset_used_flags (PATTERN (undobuf.other_insn));
3091
3092     INSN_CODE (i3) = insn_code_number;
3093     PATTERN (i3) = newpat;
3094
3095     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3096       {
3097         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3098
3099         reset_used_flags (call_usage);
3100         call_usage = copy_rtx (call_usage);
3101
3102         if (substed_i2)
3103           replace_rtx (call_usage, i2dest, i2src);
3104
3105         if (substed_i1)
3106           replace_rtx (call_usage, i1dest, i1src);
3107
3108         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3109       }
3110
3111     if (undobuf.other_insn)
3112       INSN_CODE (undobuf.other_insn) = other_code_number;
3113
3114     /* We had one special case above where I2 had more than one set and
3115        we replaced a destination of one of those sets with the destination
3116        of I3.  In that case, we have to update LOG_LINKS of insns later
3117        in this basic block.  Note that this (expensive) case is rare.
3118
3119        Also, in this case, we must pretend that all REG_NOTEs for I2
3120        actually came from I3, so that REG_UNUSED notes from I2 will be
3121        properly handled.  */
3122
3123     if (i3_subst_into_i2)
3124       {
3125         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3126           if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
3127               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3128               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3129               && ! find_reg_note (i2, REG_UNUSED,
3130                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3131             for (temp = NEXT_INSN (i2);
3132                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3133                           || BB_HEAD (this_basic_block) != temp);
3134                  temp = NEXT_INSN (temp))
3135               if (temp != i3 && INSN_P (temp))
3136                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3137                   if (XEXP (link, 0) == i2)
3138                     XEXP (link, 0) = i3;
3139
3140         if (i3notes)
3141           {
3142             rtx link = i3notes;
3143             while (XEXP (link, 1))
3144               link = XEXP (link, 1);
3145             XEXP (link, 1) = i2notes;
3146           }
3147         else
3148           i3notes = i2notes;
3149         i2notes = 0;
3150       }
3151
3152     LOG_LINKS (i3) = 0;
3153     REG_NOTES (i3) = 0;
3154     LOG_LINKS (i2) = 0;
3155     REG_NOTES (i2) = 0;
3156
3157     if (newi2pat)
3158       {
3159         INSN_CODE (i2) = i2_code_number;
3160         PATTERN (i2) = newi2pat;
3161       }
3162     else
3163       SET_INSN_DELETED (i2);
3164
3165     if (i1)
3166       {
3167         LOG_LINKS (i1) = 0;
3168         REG_NOTES (i1) = 0;
3169         SET_INSN_DELETED (i1);
3170       }
3171
3172     /* Get death notes for everything that is now used in either I3 or
3173        I2 and used to die in a previous insn.  If we built two new
3174        patterns, move from I1 to I2 then I2 to I3 so that we get the
3175        proper movement on registers that I2 modifies.  */
3176
3177     if (newi2pat)
3178       {
3179         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3180         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3181       }
3182     else
3183       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3184                    i3, &midnotes);
3185
3186     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3187     if (i3notes)
3188       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3189                         elim_i2, elim_i1);
3190     if (i2notes)
3191       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3192                         elim_i2, elim_i1);
3193     if (i1notes)
3194       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3195                         elim_i2, elim_i1);
3196     if (midnotes)
3197       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3198                         elim_i2, elim_i1);
3199
3200     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3201        know these are REG_UNUSED and want them to go to the desired insn,
3202        so we always pass it as i3.  We have not counted the notes in
3203        reg_n_deaths yet, so we need to do so now.  */
3204
3205     if (newi2pat && new_i2_notes)
3206       {
3207         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3208           if (REG_P (XEXP (temp, 0)))
3209             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3210
3211         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3212       }
3213
3214     if (new_i3_notes)
3215       {
3216         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3217           if (REG_P (XEXP (temp, 0)))
3218             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3219
3220         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3221       }
3222
3223     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3224        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3225        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3226        in that case, it might delete I2.  Similarly for I2 and I1.
3227        Show an additional death due to the REG_DEAD note we make here.  If
3228        we discard it in distribute_notes, we will decrement it again.  */
3229
3230     if (i3dest_killed)
3231       {
3232         if (REG_P (i3dest_killed))
3233           REG_N_DEATHS (REGNO (i3dest_killed))++;
3234
3235         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3236           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3237                                                NULL_RTX),
3238                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3239         else
3240           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3241                                                NULL_RTX),
3242                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3243                             elim_i2, elim_i1);
3244       }
3245
3246     if (i2dest_in_i2src)
3247       {
3248         if (REG_P (i2dest))
3249           REG_N_DEATHS (REGNO (i2dest))++;
3250
3251         if (newi2pat && reg_set_p (i2dest, newi2pat))
3252           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3253                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3254         else
3255           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3256                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3257                             NULL_RTX, NULL_RTX);
3258       }
3259
3260     if (i1dest_in_i1src)
3261       {
3262         if (REG_P (i1dest))
3263           REG_N_DEATHS (REGNO (i1dest))++;
3264
3265         if (newi2pat && reg_set_p (i1dest, newi2pat))
3266           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3267                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3268         else
3269           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3270                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3271                             NULL_RTX, NULL_RTX);
3272       }
3273
3274     distribute_links (i3links);
3275     distribute_links (i2links);
3276     distribute_links (i1links);
3277
3278     if (REG_P (i2dest))
3279       {
3280         rtx link;
3281         rtx i2_insn = 0, i2_val = 0, set;
3282
3283         /* The insn that used to set this register doesn't exist, and
3284            this life of the register may not exist either.  See if one of
3285            I3's links points to an insn that sets I2DEST.  If it does,
3286            that is now the last known value for I2DEST. If we don't update
3287            this and I2 set the register to a value that depended on its old
3288            contents, we will get confused.  If this insn is used, thing
3289            will be set correctly in combine_instructions.  */
3290
3291         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3292           if ((set = single_set (XEXP (link, 0))) != 0
3293               && rtx_equal_p (i2dest, SET_DEST (set)))
3294             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3295
3296         record_value_for_reg (i2dest, i2_insn, i2_val);
3297
3298         /* If the reg formerly set in I2 died only once and that was in I3,
3299            zero its use count so it won't make `reload' do any work.  */
3300         if (! added_sets_2
3301             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3302             && ! i2dest_in_i2src)
3303           {
3304             regno = REGNO (i2dest);
3305             REG_N_SETS (regno)--;
3306           }
3307       }
3308
3309     if (i1 && REG_P (i1dest))
3310       {
3311         rtx link;
3312         rtx i1_insn = 0, i1_val = 0, set;
3313
3314         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3315           if ((set = single_set (XEXP (link, 0))) != 0
3316               && rtx_equal_p (i1dest, SET_DEST (set)))
3317             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3318
3319         record_value_for_reg (i1dest, i1_insn, i1_val);
3320
3321         regno = REGNO (i1dest);
3322         if (! added_sets_1 && ! i1dest_in_i1src)
3323           REG_N_SETS (regno)--;
3324       }
3325
3326     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3327        been made to this insn.  The order of
3328        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3329        can affect nonzero_bits of newpat */
3330     if (newi2pat)
3331       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3332     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3333
3334     /* Set new_direct_jump_p if a new return or simple jump instruction
3335        has been created.
3336
3337        If I3 is now an unconditional jump, ensure that it has a
3338        BARRIER following it since it may have initially been a
3339        conditional jump.  It may also be the last nonnote insn.  */
3340
3341     if (returnjump_p (i3) || any_uncondjump_p (i3))
3342       {
3343         *new_direct_jump_p = 1;
3344         mark_jump_label (PATTERN (i3), i3, 0);
3345
3346         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3347             || !BARRIER_P (temp))
3348           emit_barrier_after (i3);
3349       }
3350
3351     if (undobuf.other_insn != NULL_RTX
3352         && (returnjump_p (undobuf.other_insn)
3353             || any_uncondjump_p (undobuf.other_insn)))
3354       {
3355         *new_direct_jump_p = 1;
3356
3357         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3358             || !BARRIER_P (temp))
3359           emit_barrier_after (undobuf.other_insn);
3360       }
3361
3362     /* An NOOP jump does not need barrier, but it does need cleaning up
3363        of CFG.  */
3364     if (GET_CODE (newpat) == SET
3365         && SET_SRC (newpat) == pc_rtx
3366         && SET_DEST (newpat) == pc_rtx)
3367       *new_direct_jump_p = 1;
3368   }
3369
3370   combine_successes++;
3371   undo_commit ();
3372
3373   if (added_links_insn
3374       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3375       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3376     return added_links_insn;
3377   else
3378     return newi2pat ? i2 : i3;
3379 }
3380 \f
3381 /* Undo all the modifications recorded in undobuf.  */
3382
3383 static void
3384 undo_all (void)
3385 {
3386   struct undo *undo, *next;
3387
3388   for (undo = undobuf.undos; undo; undo = next)
3389     {
3390       next = undo->next;
3391       switch (undo->kind)
3392         {
3393         case UNDO_RTX:
3394           *undo->where.r = undo->old_contents.r;
3395           break;
3396         case UNDO_INT:
3397           *undo->where.i = undo->old_contents.i;
3398           break;
3399         case UNDO_MODE:
3400           PUT_MODE (*undo->where.r, undo->old_contents.m);
3401           break;
3402         default:
3403           gcc_unreachable ();
3404         }
3405
3406       undo->next = undobuf.frees;
3407       undobuf.frees = undo;
3408     }
3409
3410   undobuf.undos = 0;
3411 }
3412
3413 /* We've committed to accepting the changes we made.  Move all
3414    of the undos to the free list.  */
3415
3416 static void
3417 undo_commit (void)
3418 {
3419   struct undo *undo, *next;
3420
3421   for (undo = undobuf.undos; undo; undo = next)
3422     {
3423       next = undo->next;
3424       undo->next = undobuf.frees;
3425       undobuf.frees = undo;
3426     }
3427   undobuf.undos = 0;
3428 }
3429
3430 \f
3431 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3432    where we have an arithmetic expression and return that point.  LOC will
3433    be inside INSN.
3434
3435    try_combine will call this function to see if an insn can be split into
3436    two insns.  */
3437
3438 static rtx *
3439 find_split_point (rtx *loc, rtx insn)
3440 {
3441   rtx x = *loc;
3442   enum rtx_code code = GET_CODE (x);
3443   rtx *split;
3444   unsigned HOST_WIDE_INT len = 0;
3445   HOST_WIDE_INT pos = 0;
3446   int unsignedp = 0;
3447   rtx inner = NULL_RTX;
3448
3449   /* First special-case some codes.  */
3450   switch (code)
3451     {
3452     case SUBREG:
3453 #ifdef INSN_SCHEDULING
3454       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3455          point.  */
3456       if (MEM_P (SUBREG_REG (x)))
3457         return loc;
3458 #endif
3459       return find_split_point (&SUBREG_REG (x), insn);
3460
3461     case MEM:
3462 #ifdef HAVE_lo_sum
3463       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3464          using LO_SUM and HIGH.  */
3465       if (GET_CODE (XEXP (x, 0)) == CONST
3466           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3467         {
3468           SUBST (XEXP (x, 0),
3469                  gen_rtx_LO_SUM (Pmode,
3470                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3471                                  XEXP (x, 0)));
3472           return &XEXP (XEXP (x, 0), 0);
3473         }
3474 #endif
3475
3476       /* If we have a PLUS whose second operand is a constant and the
3477          address is not valid, perhaps will can split it up using
3478          the machine-specific way to split large constants.  We use
3479          the first pseudo-reg (one of the virtual regs) as a placeholder;
3480          it will not remain in the result.  */
3481       if (GET_CODE (XEXP (x, 0)) == PLUS
3482           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3483           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3484         {
3485           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3486           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3487                                  subst_insn);
3488
3489           /* This should have produced two insns, each of which sets our
3490              placeholder.  If the source of the second is a valid address,
3491              we can make put both sources together and make a split point
3492              in the middle.  */
3493
3494           if (seq
3495               && NEXT_INSN (seq) != NULL_RTX
3496               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3497               && NONJUMP_INSN_P (seq)
3498               && GET_CODE (PATTERN (seq)) == SET
3499               && SET_DEST (PATTERN (seq)) == reg
3500               && ! reg_mentioned_p (reg,
3501                                     SET_SRC (PATTERN (seq)))
3502               && NONJUMP_INSN_P (NEXT_INSN (seq))
3503               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3504               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3505               && memory_address_p (GET_MODE (x),
3506                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3507             {
3508               rtx src1 = SET_SRC (PATTERN (seq));
3509               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3510
3511               /* Replace the placeholder in SRC2 with SRC1.  If we can
3512                  find where in SRC2 it was placed, that can become our
3513                  split point and we can replace this address with SRC2.
3514                  Just try two obvious places.  */
3515
3516               src2 = replace_rtx (src2, reg, src1);
3517               split = 0;
3518               if (XEXP (src2, 0) == src1)
3519                 split = &XEXP (src2, 0);
3520               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3521                        && XEXP (XEXP (src2, 0), 0) == src1)
3522                 split = &XEXP (XEXP (src2, 0), 0);
3523
3524               if (split)
3525                 {
3526                   SUBST (XEXP (x, 0), src2);
3527                   return split;
3528                 }
3529             }
3530
3531           /* If that didn't work, perhaps the first operand is complex and
3532              needs to be computed separately, so make a split point there.
3533              This will occur on machines that just support REG + CONST
3534              and have a constant moved through some previous computation.  */
3535
3536           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3537                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3538                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3539             return &XEXP (XEXP (x, 0), 0);
3540         }
3541       break;
3542
3543     case SET:
3544 #ifdef HAVE_cc0
3545       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3546          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3547          we need to put the operand into a register.  So split at that
3548          point.  */
3549
3550       if (SET_DEST (x) == cc0_rtx
3551           && GET_CODE (SET_SRC (x)) != COMPARE
3552           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3553           && !OBJECT_P (SET_SRC (x))
3554           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3555                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3556         return &SET_SRC (x);
3557 #endif
3558
3559       /* See if we can split SET_SRC as it stands.  */
3560       split = find_split_point (&SET_SRC (x), insn);
3561       if (split && split != &SET_SRC (x))
3562         return split;
3563
3564       /* See if we can split SET_DEST as it stands.  */
3565       split = find_split_point (&SET_DEST (x), insn);
3566       if (split && split != &SET_DEST (x))
3567         return split;
3568
3569       /* See if this is a bitfield assignment with everything constant.  If
3570          so, this is an IOR of an AND, so split it into that.  */
3571       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3572           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3573               <= HOST_BITS_PER_WIDE_INT)
3574           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3575           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3576           && GET_CODE (SET_SRC (x)) == CONST_INT
3577           && ((INTVAL (XEXP (SET_DEST (x), 1))
3578                + INTVAL (XEXP (SET_DEST (x), 2)))
3579               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3580           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3581         {
3582           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3583           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3584           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3585           rtx dest = XEXP (SET_DEST (x), 0);
3586           enum machine_mode mode = GET_MODE (dest);
3587           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3588           rtx or_mask;
3589
3590           if (BITS_BIG_ENDIAN)
3591             pos = GET_MODE_BITSIZE (mode) - len - pos;
3592
3593           or_mask = gen_int_mode (src << pos, mode);
3594           if (src == mask)
3595             SUBST (SET_SRC (x),
3596                    simplify_gen_binary (IOR, mode, dest, or_mask));
3597           else
3598             {
3599               rtx negmask = gen_int_mode (~(mask << pos), mode);
3600               SUBST (SET_SRC (x),
3601                      simplify_gen_binary (IOR, mode,
3602                                           simplify_gen_binary (AND, mode,
3603                                                                dest, negmask),
3604                                           or_mask));
3605             }
3606
3607           SUBST (SET_DEST (x), dest);
3608
3609           split = find_split_point (&SET_SRC (x), insn);
3610           if (split && split != &SET_SRC (x))
3611             return split;
3612         }
3613
3614       /* Otherwise, see if this is an operation that we can split into two.
3615          If so, try to split that.  */
3616       code = GET_CODE (SET_SRC (x));
3617
3618       switch (code)
3619         {
3620         case AND:
3621           /* If we are AND'ing with a large constant that is only a single
3622              bit and the result is only being used in a context where we
3623              need to know if it is zero or nonzero, replace it with a bit
3624              extraction.  This will avoid the large constant, which might
3625              have taken more than one insn to make.  If the constant were
3626              not a valid argument to the AND but took only one insn to make,
3627              this is no worse, but if it took more than one insn, it will
3628              be better.  */
3629
3630           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3631               && REG_P (XEXP (SET_SRC (x), 0))
3632               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3633               && REG_P (SET_DEST (x))
3634               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3635               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3636               && XEXP (*split, 0) == SET_DEST (x)
3637               && XEXP (*split, 1) == const0_rtx)
3638             {
3639               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3640                                                 XEXP (SET_SRC (x), 0),
3641                                                 pos, NULL_RTX, 1, 1, 0, 0);
3642               if (extraction != 0)
3643                 {
3644                   SUBST (SET_SRC (x), extraction);
3645                   return find_split_point (loc, insn);
3646                 }
3647             }
3648           break;
3649
3650         case NE:
3651           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3652              is known to be on, this can be converted into a NEG of a shift.  */
3653           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3654               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3655               && 1 <= (pos = exact_log2
3656                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3657                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3658             {
3659               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3660
3661               SUBST (SET_SRC (x),
3662                      gen_rtx_NEG (mode,
3663                                   gen_rtx_LSHIFTRT (mode,
3664                                                     XEXP (SET_SRC (x), 0),
3665                                                     GEN_INT (pos))));
3666
3667               split = find_split_point (&SET_SRC (x), insn);
3668               if (split && split != &SET_SRC (x))
3669                 return split;
3670             }
3671           break;
3672
3673         case SIGN_EXTEND:
3674           inner = XEXP (SET_SRC (x), 0);
3675
3676           /* We can't optimize if either mode is a partial integer
3677              mode as we don't know how many bits are significant
3678              in those modes.  */
3679           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3680               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3681             break;
3682
3683           pos = 0;
3684           len = GET_MODE_BITSIZE (GET_MODE (inner));
3685           unsignedp = 0;
3686           break;
3687
3688         case SIGN_EXTRACT:
3689         case ZERO_EXTRACT:
3690           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3691               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3692             {
3693               inner = XEXP (SET_SRC (x), 0);
3694               len = INTVAL (XEXP (SET_SRC (x), 1));
3695               pos = INTVAL (XEXP (SET_SRC (x), 2));
3696
3697               if (BITS_BIG_ENDIAN)
3698                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3699               unsignedp = (code == ZERO_EXTRACT);
3700             }
3701           break;
3702
3703         default:
3704           break;
3705         }
3706
3707       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3708         {
3709           enum machine_mode mode = GET_MODE (SET_SRC (x));
3710
3711           /* For unsigned, we have a choice of a shift followed by an
3712              AND or two shifts.  Use two shifts for field sizes where the
3713              constant might be too large.  We assume here that we can
3714              always at least get 8-bit constants in an AND insn, which is
3715              true for every current RISC.  */
3716
3717           if (unsignedp && len <= 8)
3718             {
3719               SUBST (SET_SRC (x),
3720                      gen_rtx_AND (mode,
3721                                   gen_rtx_LSHIFTRT
3722                                   (mode, gen_lowpart (mode, inner),
3723                                    GEN_INT (pos)),
3724                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3725
3726               split = find_split_point (&SET_SRC (x), insn);
3727               if (split && split != &SET_SRC (x))
3728                 return split;
3729             }
3730           else
3731             {
3732               SUBST (SET_SRC (x),
3733                      gen_rtx_fmt_ee
3734                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3735                       gen_rtx_ASHIFT (mode,
3736                                       gen_lowpart (mode, inner),
3737                                       GEN_INT (GET_MODE_BITSIZE (mode)
3738                                                - len - pos)),
3739                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3740
3741               split = find_split_point (&SET_SRC (x), insn);
3742               if (split && split != &SET_SRC (x))
3743                 return split;
3744             }
3745         }
3746
3747       /* See if this is a simple operation with a constant as the second
3748          operand.  It might be that this constant is out of range and hence
3749          could be used as a split point.  */
3750       if (BINARY_P (SET_SRC (x))
3751           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3752           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3753               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3754                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3755         return &XEXP (SET_SRC (x), 1);
3756
3757       /* Finally, see if this is a simple operation with its first operand
3758          not in a register.  The operation might require this operand in a
3759          register, so return it as a split point.  We can always do this
3760          because if the first operand were another operation, we would have
3761          already found it as a split point.  */
3762       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3763           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3764         return &XEXP (SET_SRC (x), 0);
3765
3766       return 0;
3767
3768     case AND:
3769     case IOR:
3770       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3771          it is better to write this as (not (ior A B)) so we can split it.
3772          Similarly for IOR.  */
3773       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3774         {
3775           SUBST (*loc,
3776                  gen_rtx_NOT (GET_MODE (x),
3777                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3778                                               GET_MODE (x),
3779                                               XEXP (XEXP (x, 0), 0),
3780                                               XEXP (XEXP (x, 1), 0))));
3781           return find_split_point (loc, insn);
3782         }
3783
3784       /* Many RISC machines have a large set of logical insns.  If the
3785          second operand is a NOT, put it first so we will try to split the
3786          other operand first.  */
3787       if (GET_CODE (XEXP (x, 1)) == NOT)
3788         {
3789           rtx tem = XEXP (x, 0);
3790           SUBST (XEXP (x, 0), XEXP (x, 1));
3791           SUBST (XEXP (x, 1), tem);
3792         }
3793       break;
3794
3795     default:
3796       break;
3797     }
3798
3799   /* Otherwise, select our actions depending on our rtx class.  */
3800   switch (GET_RTX_CLASS (code))
3801     {
3802     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3803     case RTX_TERNARY:
3804       split = find_split_point (&XEXP (x, 2), insn);
3805       if (split)
3806         return split;
3807       /* ... fall through ...  */
3808     case RTX_BIN_ARITH:
3809     case RTX_COMM_ARITH:
3810     case RTX_COMPARE:
3811     case RTX_COMM_COMPARE:
3812       split = find_split_point (&XEXP (x, 1), insn);
3813       if (split)
3814         return split;
3815       /* ... fall through ...  */
3816     case RTX_UNARY:
3817       /* Some machines have (and (shift ...) ...) insns.  If X is not
3818          an AND, but XEXP (X, 0) is, use it as our split point.  */
3819       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3820         return &XEXP (x, 0);
3821
3822       split = find_split_point (&XEXP (x, 0), insn);
3823       if (split)
3824         return split;
3825       return loc;
3826
3827     default:
3828       /* Otherwise, we don't have a split point.  */
3829       return 0;
3830     }
3831 }
3832 \f
3833 /* Throughout X, replace FROM with TO, and return the result.
3834    The result is TO if X is FROM;
3835    otherwise the result is X, but its contents may have been modified.
3836    If they were modified, a record was made in undobuf so that
3837    undo_all will (among other things) return X to its original state.
3838
3839    If the number of changes necessary is too much to record to undo,
3840    the excess changes are not made, so the result is invalid.
3841    The changes already made can still be undone.
3842    undobuf.num_undo is incremented for such changes, so by testing that
3843    the caller can tell whether the result is valid.
3844
3845    `n_occurrences' is incremented each time FROM is replaced.
3846
3847    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3848
3849    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3850    by copying if `n_occurrences' is nonzero.  */
3851
3852 static rtx
3853 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3854 {
3855   enum rtx_code code = GET_CODE (x);
3856   enum machine_mode op0_mode = VOIDmode;
3857   const char *fmt;
3858   int len, i;
3859   rtx new;
3860
3861 /* Two expressions are equal if they are identical copies of a shared
3862    RTX or if they are both registers with the same register number
3863    and mode.  */
3864
3865 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3866   ((X) == (Y)                                           \
3867    || (REG_P (X) && REG_P (Y)   \
3868        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3869
3870   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3871     {
3872       n_occurrences++;
3873       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3874     }
3875
3876   /* If X and FROM are the same register but different modes, they will
3877      not have been seen as equal above.  However, flow.c will make a
3878      LOG_LINKS entry for that case.  If we do nothing, we will try to
3879      rerecognize our original insn and, when it succeeds, we will
3880      delete the feeding insn, which is incorrect.
3881
3882      So force this insn not to match in this (rare) case.  */
3883   if (! in_dest && code == REG && REG_P (from)
3884       && REGNO (x) == REGNO (from))
3885     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3886
3887   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3888      of which may contain things that can be combined.  */
3889   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3890     return x;
3891
3892   /* It is possible to have a subexpression appear twice in the insn.
3893      Suppose that FROM is a register that appears within TO.
3894      Then, after that subexpression has been scanned once by `subst',
3895      the second time it is scanned, TO may be found.  If we were
3896      to scan TO here, we would find FROM within it and create a
3897      self-referent rtl structure which is completely wrong.  */
3898   if (COMBINE_RTX_EQUAL_P (x, to))
3899     return to;
3900
3901   /* Parallel asm_operands need special attention because all of the
3902      inputs are shared across the arms.  Furthermore, unsharing the
3903      rtl results in recognition failures.  Failure to handle this case
3904      specially can result in circular rtl.
3905
3906      Solve this by doing a normal pass across the first entry of the
3907      parallel, and only processing the SET_DESTs of the subsequent
3908      entries.  Ug.  */
3909
3910   if (code == PARALLEL
3911       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3912       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3913     {
3914       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3915
3916       /* If this substitution failed, this whole thing fails.  */
3917       if (GET_CODE (new) == CLOBBER
3918           && XEXP (new, 0) == const0_rtx)
3919         return new;
3920
3921       SUBST (XVECEXP (x, 0, 0), new);
3922
3923       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3924         {
3925           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3926
3927           if (!REG_P (dest)
3928               && GET_CODE (dest) != CC0
3929               && GET_CODE (dest) != PC)
3930             {
3931               new = subst (dest, from, to, 0, unique_copy);
3932
3933               /* If this substitution failed, this whole thing fails.  */
3934               if (GET_CODE (new) == CLOBBER
3935                   && XEXP (new, 0) == const0_rtx)
3936                 return new;
3937
3938               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3939             }
3940         }
3941     }
3942   else
3943     {
3944       len = GET_RTX_LENGTH (code);
3945       fmt = GET_RTX_FORMAT (code);
3946
3947       /* We don't need to process a SET_DEST that is a register, CC0,
3948          or PC, so set up to skip this common case.  All other cases
3949          where we want to suppress replacing something inside a
3950          SET_SRC are handled via the IN_DEST operand.  */
3951       if (code == SET
3952           && (REG_P (SET_DEST (x))
3953               || GET_CODE (SET_DEST (x)) == CC0
3954               || GET_CODE (SET_DEST (x)) == PC))
3955         fmt = "ie";
3956
3957       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3958          constant.  */
3959       if (fmt[0] == 'e')
3960         op0_mode = GET_MODE (XEXP (x, 0));
3961
3962       for (i = 0; i < len; i++)
3963         {
3964           if (fmt[i] == 'E')
3965             {
3966               int j;
3967               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3968                 {
3969                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3970                     {
3971                       new = (unique_copy && n_occurrences
3972                              ? copy_rtx (to) : to);
3973                       n_occurrences++;
3974                     }
3975                   else
3976                     {
3977                       new = subst (XVECEXP (x, i, j), from, to, 0,
3978                                    unique_copy);
3979
3980                       /* If this substitution failed, this whole thing
3981                          fails.  */
3982                       if (GET_CODE (new) == CLOBBER
3983                           && XEXP (new, 0) == const0_rtx)
3984                         return new;
3985                     }
3986
3987                   SUBST (XVECEXP (x, i, j), new);
3988                 }
3989             }
3990           else if (fmt[i] == 'e')
3991             {
3992               /* If this is a register being set, ignore it.  */
3993               new = XEXP (x, i);
3994               if (in_dest
3995                   && i == 0
3996                   && (((code == SUBREG || code == ZERO_EXTRACT)
3997                        && REG_P (new))
3998                       || code == STRICT_LOW_PART))
3999                 ;
4000
4001               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4002                 {
4003                   /* In general, don't install a subreg involving two
4004                      modes not tieable.  It can worsen register
4005                      allocation, and can even make invalid reload
4006                      insns, since the reg inside may need to be copied
4007                      from in the outside mode, and that may be invalid
4008                      if it is an fp reg copied in integer mode.
4009
4010                      We allow two exceptions to this: It is valid if
4011                      it is inside another SUBREG and the mode of that
4012                      SUBREG and the mode of the inside of TO is
4013                      tieable and it is valid if X is a SET that copies
4014                      FROM to CC0.  */
4015
4016                   if (GET_CODE (to) == SUBREG
4017                       && ! MODES_TIEABLE_P (GET_MODE (to),
4018                                             GET_MODE (SUBREG_REG (to)))
4019                       && ! (code == SUBREG
4020                             && MODES_TIEABLE_P (GET_MODE (x),
4021                                                 GET_MODE (SUBREG_REG (to))))
4022 #ifdef HAVE_cc0
4023                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4024 #endif
4025                       )
4026                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4027
4028 #ifdef CANNOT_CHANGE_MODE_CLASS
4029                   if (code == SUBREG
4030                       && REG_P (to)
4031                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4032                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4033                                                    GET_MODE (to),
4034                                                    GET_MODE (x)))
4035                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4036 #endif
4037
4038                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4039                   n_occurrences++;
4040                 }
4041               else
4042                 /* If we are in a SET_DEST, suppress most cases unless we
4043                    have gone inside a MEM, in which case we want to
4044                    simplify the address.  We assume here that things that
4045                    are actually part of the destination have their inner
4046                    parts in the first expression.  This is true for SUBREG,
4047                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4048                    things aside from REG and MEM that should appear in a
4049                    SET_DEST.  */
4050                 new = subst (XEXP (x, i), from, to,
4051                              (((in_dest
4052                                 && (code == SUBREG || code == STRICT_LOW_PART
4053                                     || code == ZERO_EXTRACT))
4054                                || code == SET)
4055                               && i == 0), unique_copy);
4056
4057               /* If we found that we will have to reject this combination,
4058                  indicate that by returning the CLOBBER ourselves, rather than
4059                  an expression containing it.  This will speed things up as
4060                  well as prevent accidents where two CLOBBERs are considered
4061                  to be equal, thus producing an incorrect simplification.  */
4062
4063               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4064                 return new;
4065
4066               if (GET_CODE (x) == SUBREG
4067                   && (GET_CODE (new) == CONST_INT
4068                       || GET_CODE (new) == CONST_DOUBLE))
4069                 {
4070                   enum machine_mode mode = GET_MODE (x);
4071
4072                   x = simplify_subreg (GET_MODE (x), new,
4073                                        GET_MODE (SUBREG_REG (x)),
4074                                        SUBREG_BYTE (x));
4075                   if (! x)
4076                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4077                 }
4078               else if (GET_CODE (new) == CONST_INT
4079                        && GET_CODE (x) == ZERO_EXTEND)
4080                 {
4081                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4082                                                 new, GET_MODE (XEXP (x, 0)));
4083                   gcc_assert (x);
4084                 }
4085               else
4086                 SUBST (XEXP (x, i), new);
4087             }
4088         }
4089     }
4090
4091   /* Try to simplify X.  If the simplification changed the code, it is likely
4092      that further simplification will help, so loop, but limit the number
4093      of repetitions that will be performed.  */
4094
4095   for (i = 0; i < 4; i++)
4096     {
4097       /* If X is sufficiently simple, don't bother trying to do anything
4098          with it.  */
4099       if (code != CONST_INT && code != REG && code != CLOBBER)
4100         x = combine_simplify_rtx (x, op0_mode, in_dest);
4101
4102       if (GET_CODE (x) == code)
4103         break;
4104
4105       code = GET_CODE (x);
4106
4107       /* We no longer know the original mode of operand 0 since we
4108          have changed the form of X)  */
4109       op0_mode = VOIDmode;
4110     }
4111
4112   return x;
4113 }
4114 \f
4115 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4116    outer level; call `subst' to simplify recursively.  Return the new
4117    expression.
4118
4119    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4120    if we are inside a SET_DEST.  */
4121
4122 static rtx
4123 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4124 {
4125   enum rtx_code code = GET_CODE (x);
4126   enum machine_mode mode = GET_MODE (x);
4127   rtx temp;
4128   int i;
4129
4130   /* If this is a commutative operation, put a constant last and a complex
4131      expression first.  We don't need to do this for comparisons here.  */
4132   if (COMMUTATIVE_ARITH_P (x)
4133       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4134     {
4135       temp = XEXP (x, 0);
4136       SUBST (XEXP (x, 0), XEXP (x, 1));
4137       SUBST (XEXP (x, 1), temp);
4138     }
4139
4140   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4141      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4142      things.  Check for cases where both arms are testing the same
4143      condition.
4144
4145      Don't do anything if all operands are very simple.  */
4146
4147   if ((BINARY_P (x)
4148        && ((!OBJECT_P (XEXP (x, 0))
4149             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4150                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4151            || (!OBJECT_P (XEXP (x, 1))
4152                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4153                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4154       || (UNARY_P (x)
4155           && (!OBJECT_P (XEXP (x, 0))
4156                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4157                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4158     {
4159       rtx cond, true_rtx, false_rtx;
4160
4161       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4162       if (cond != 0
4163           /* If everything is a comparison, what we have is highly unlikely
4164              to be simpler, so don't use it.  */
4165           && ! (COMPARISON_P (x)
4166                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4167         {
4168           rtx cop1 = const0_rtx;
4169           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4170
4171           if (cond_code == NE && COMPARISON_P (cond))
4172             return x;
4173
4174           /* Simplify the alternative arms; this may collapse the true and
4175              false arms to store-flag values.  Be careful to use copy_rtx
4176              here since true_rtx or false_rtx might share RTL with x as a
4177              result of the if_then_else_cond call above.  */
4178           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4179           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4180
4181           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4182              is unlikely to be simpler.  */
4183           if (general_operand (true_rtx, VOIDmode)
4184               && general_operand (false_rtx, VOIDmode))
4185             {
4186               enum rtx_code reversed;
4187
4188               /* Restarting if we generate a store-flag expression will cause
4189                  us to loop.  Just drop through in this case.  */
4190
4191               /* If the result values are STORE_FLAG_VALUE and zero, we can
4192                  just make the comparison operation.  */
4193               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4194                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4195                                              cond, cop1);
4196               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4197                        && ((reversed = reversed_comparison_code_parts
4198                                         (cond_code, cond, cop1, NULL))
4199                            != UNKNOWN))
4200                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4201                                              cond, cop1);
4202
4203               /* Likewise, we can make the negate of a comparison operation
4204                  if the result values are - STORE_FLAG_VALUE and zero.  */
4205               else if (GET_CODE (true_rtx) == CONST_INT
4206                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4207                        && false_rtx == const0_rtx)
4208                 x = simplify_gen_unary (NEG, mode,
4209                                         simplify_gen_relational (cond_code,
4210                                                                  mode, VOIDmode,
4211                                                                  cond, cop1),
4212                                         mode);
4213               else if (GET_CODE (false_rtx) == CONST_INT
4214                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4215                        && true_rtx == const0_rtx
4216                        && ((reversed = reversed_comparison_code_parts
4217                                         (cond_code, cond, cop1, NULL))
4218                            != UNKNOWN))
4219                 x = simplify_gen_unary (NEG, mode,
4220                                         simplify_gen_relational (reversed,
4221                                                                  mode, VOIDmode,
4222                                                                  cond, cop1),
4223                                         mode);
4224               else
4225                 return gen_rtx_IF_THEN_ELSE (mode,
4226                                              simplify_gen_relational (cond_code,
4227                                                                       mode,
4228                                                                       VOIDmode,
4229                                                                       cond,
4230                                                                       cop1),
4231                                              true_rtx, false_rtx);
4232
4233               code = GET_CODE (x);
4234               op0_mode = VOIDmode;
4235             }
4236         }
4237     }
4238
4239   /* Try to fold this expression in case we have constants that weren't
4240      present before.  */
4241   temp = 0;
4242   switch (GET_RTX_CLASS (code))
4243     {
4244     case RTX_UNARY:
4245       if (op0_mode == VOIDmode)
4246         op0_mode = GET_MODE (XEXP (x, 0));
4247       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4248       break;
4249     case RTX_COMPARE:
4250     case RTX_COMM_COMPARE:
4251       {
4252         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4253         if (cmp_mode == VOIDmode)
4254           {
4255             cmp_mode = GET_MODE (XEXP (x, 1));
4256             if (cmp_mode == VOIDmode)
4257               cmp_mode = op0_mode;
4258           }
4259         temp = simplify_relational_operation (code, mode, cmp_mode,
4260                                               XEXP (x, 0), XEXP (x, 1));
4261       }
4262       break;
4263     case RTX_COMM_ARITH:
4264     case RTX_BIN_ARITH:
4265       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4266       break;
4267     case RTX_BITFIELD_OPS:
4268     case RTX_TERNARY:
4269       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4270                                          XEXP (x, 1), XEXP (x, 2));
4271       break;
4272     default:
4273       break;
4274     }
4275
4276   if (temp)
4277     {
4278       x = temp;
4279       code = GET_CODE (temp);
4280       op0_mode = VOIDmode;
4281       mode = GET_MODE (temp);
4282     }
4283
4284   /* First see if we can apply the inverse distributive law.  */
4285   if (code == PLUS || code == MINUS
4286       || code == AND || code == IOR || code == XOR)
4287     {
4288       x = apply_distributive_law (x);
4289       code = GET_CODE (x);
4290       op0_mode = VOIDmode;
4291     }
4292
4293   /* If CODE is an associative operation not otherwise handled, see if we
4294      can associate some operands.  This can win if they are constants or
4295      if they are logically related (i.e. (a & b) & a).  */
4296   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4297        || code == AND || code == IOR || code == XOR
4298        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4299       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4300           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4301     {
4302       if (GET_CODE (XEXP (x, 0)) == code)
4303         {
4304           rtx other = XEXP (XEXP (x, 0), 0);
4305           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4306           rtx inner_op1 = XEXP (x, 1);
4307           rtx inner;
4308
4309           /* Make sure we pass the constant operand if any as the second
4310              one if this is a commutative operation.  */
4311           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4312             {
4313               rtx tem = inner_op0;
4314               inner_op0 = inner_op1;
4315               inner_op1 = tem;
4316             }
4317           inner = simplify_binary_operation (code == MINUS ? PLUS
4318                                              : code == DIV ? MULT
4319                                              : code,
4320                                              mode, inner_op0, inner_op1);
4321
4322           /* For commutative operations, try the other pair if that one
4323              didn't simplify.  */
4324           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4325             {
4326               other = XEXP (XEXP (x, 0), 1);
4327               inner = simplify_binary_operation (code, mode,
4328                                                  XEXP (XEXP (x, 0), 0),
4329                                                  XEXP (x, 1));
4330             }
4331
4332           if (inner)
4333             return simplify_gen_binary (code, mode, other, inner);
4334         }
4335     }
4336
4337   /* A little bit of algebraic simplification here.  */
4338   switch (code)
4339     {
4340     case MEM:
4341       /* Ensure that our address has any ASHIFTs converted to MULT in case
4342          address-recognizing predicates are called later.  */
4343       temp = make_compound_operation (XEXP (x, 0), MEM);
4344       SUBST (XEXP (x, 0), temp);
4345       break;
4346
4347     case SUBREG:
4348       if (op0_mode == VOIDmode)
4349         op0_mode = GET_MODE (SUBREG_REG (x));
4350
4351       /* See if this can be moved to simplify_subreg.  */
4352       if (CONSTANT_P (SUBREG_REG (x))
4353           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4354              /* Don't call gen_lowpart if the inner mode
4355                 is VOIDmode and we cannot simplify it, as SUBREG without
4356                 inner mode is invalid.  */
4357           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4358               || gen_lowpart_common (mode, SUBREG_REG (x))))
4359         return gen_lowpart (mode, SUBREG_REG (x));
4360
4361       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4362         break;
4363       {
4364         rtx temp;
4365         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4366                                 SUBREG_BYTE (x));
4367         if (temp)
4368           return temp;
4369       }
4370
4371       /* Don't change the mode of the MEM if that would change the meaning
4372          of the address.  */
4373       if (MEM_P (SUBREG_REG (x))
4374           && (MEM_VOLATILE_P (SUBREG_REG (x))
4375               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4376         return gen_rtx_CLOBBER (mode, const0_rtx);
4377
4378       /* Note that we cannot do any narrowing for non-constants since
4379          we might have been counting on using the fact that some bits were
4380          zero.  We now do this in the SET.  */
4381
4382       break;
4383
4384     case NEG:
4385       temp = expand_compound_operation (XEXP (x, 0));
4386
4387       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4388          replaced by (lshiftrt X C).  This will convert
4389          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4390
4391       if (GET_CODE (temp) == ASHIFTRT
4392           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4393           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4394         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4395                                      INTVAL (XEXP (temp, 1)));
4396
4397       /* If X has only a single bit that might be nonzero, say, bit I, convert
4398          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4399          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4400          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4401          or a SUBREG of one since we'd be making the expression more
4402          complex if it was just a register.  */
4403
4404       if (!REG_P (temp)
4405           && ! (GET_CODE (temp) == SUBREG
4406                 && REG_P (SUBREG_REG (temp)))
4407           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4408         {
4409           rtx temp1 = simplify_shift_const
4410             (NULL_RTX, ASHIFTRT, mode,
4411              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4412                                    GET_MODE_BITSIZE (mode) - 1 - i),
4413              GET_MODE_BITSIZE (mode) - 1 - i);
4414
4415           /* If all we did was surround TEMP with the two shifts, we
4416              haven't improved anything, so don't use it.  Otherwise,
4417              we are better off with TEMP1.  */
4418           if (GET_CODE (temp1) != ASHIFTRT
4419               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4420               || XEXP (XEXP (temp1, 0), 0) != temp)
4421             return temp1;
4422         }
4423       break;
4424
4425     case TRUNCATE:
4426       /* We can't handle truncation to a partial integer mode here
4427          because we don't know the real bitsize of the partial
4428          integer mode.  */
4429       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4430         break;
4431
4432       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4433           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4434                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4435         SUBST (XEXP (x, 0),
4436                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4437                               GET_MODE_MASK (mode), 0));
4438
4439       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4440          whose value is a comparison can be replaced with a subreg if
4441          STORE_FLAG_VALUE permits.  */
4442       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4443           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4444           && (temp = get_last_value (XEXP (x, 0)))
4445           && COMPARISON_P (temp))
4446         return gen_lowpart (mode, XEXP (x, 0));
4447       break;
4448
4449 #ifdef HAVE_cc0
4450     case COMPARE:
4451       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4452          using cc0, in which case we want to leave it as a COMPARE
4453          so we can distinguish it from a register-register-copy.  */
4454       if (XEXP (x, 1) == const0_rtx)
4455         return XEXP (x, 0);
4456
4457       /* x - 0 is the same as x unless x's mode has signed zeros and
4458          allows rounding towards -infinity.  Under those conditions,
4459          0 - 0 is -0.  */
4460       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4461             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4462           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4463         return XEXP (x, 0);
4464       break;
4465 #endif
4466
4467     case CONST:
4468       /* (const (const X)) can become (const X).  Do it this way rather than
4469          returning the inner CONST since CONST can be shared with a
4470          REG_EQUAL note.  */
4471       if (GET_CODE (XEXP (x, 0)) == CONST)
4472         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4473       break;
4474
4475 #ifdef HAVE_lo_sum
4476     case LO_SUM:
4477       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4478          can add in an offset.  find_split_point will split this address up
4479          again if it doesn't match.  */
4480       if (GET_CODE (XEXP (x, 0)) == HIGH
4481           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4482         return XEXP (x, 1);
4483       break;
4484 #endif
4485
4486     case PLUS:
4487       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4488          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4489          bit-field and can be replaced by either a sign_extend or a
4490          sign_extract.  The `and' may be a zero_extend and the two
4491          <c>, -<c> constants may be reversed.  */
4492       if (GET_CODE (XEXP (x, 0)) == XOR
4493           && GET_CODE (XEXP (x, 1)) == CONST_INT
4494           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4495           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4496           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4497               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4498           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4499           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4500                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4501                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4502                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4503               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4504                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4505                       == (unsigned int) i + 1))))
4506         return simplify_shift_const
4507           (NULL_RTX, ASHIFTRT, mode,
4508            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4509                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4510                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4511            GET_MODE_BITSIZE (mode) - (i + 1));
4512
4513       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4514          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4515          the bitsize of the mode - 1.  This allows simplification of
4516          "a = (b & 8) == 0;"  */
4517       if (XEXP (x, 1) == constm1_rtx
4518           && !REG_P (XEXP (x, 0))
4519           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4520                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4521           && nonzero_bits (XEXP (x, 0), mode) == 1)
4522         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4523            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4524                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4525                                  GET_MODE_BITSIZE (mode) - 1),
4526            GET_MODE_BITSIZE (mode) - 1);
4527
4528       /* If we are adding two things that have no bits in common, convert
4529          the addition into an IOR.  This will often be further simplified,
4530          for example in cases like ((a & 1) + (a & 2)), which can
4531          become a & 3.  */
4532
4533       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4534           && (nonzero_bits (XEXP (x, 0), mode)
4535               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4536         {
4537           /* Try to simplify the expression further.  */
4538           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4539           temp = combine_simplify_rtx (tor, mode, in_dest);
4540
4541           /* If we could, great.  If not, do not go ahead with the IOR
4542              replacement, since PLUS appears in many special purpose
4543              address arithmetic instructions.  */
4544           if (GET_CODE (temp) != CLOBBER && temp != tor)
4545             return temp;
4546         }
4547       break;
4548
4549     case MINUS:
4550       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4551          (and <foo> (const_int pow2-1))  */
4552       if (GET_CODE (XEXP (x, 1)) == AND
4553           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4554           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4555           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4556         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4557                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4558       break;
4559
4560     case MULT:
4561       /* If we have (mult (plus A B) C), apply the distributive law and then
4562          the inverse distributive law to see if things simplify.  This
4563          occurs mostly in addresses, often when unrolling loops.  */
4564
4565       if (GET_CODE (XEXP (x, 0)) == PLUS)
4566         {
4567           rtx result = distribute_and_simplify_rtx (x, 0);
4568           if (result)
4569             return result;
4570         }
4571
4572       /* Try simplify a*(b/c) as (a*b)/c.  */
4573       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4574           && GET_CODE (XEXP (x, 0)) == DIV)
4575         {
4576           rtx tem = simplify_binary_operation (MULT, mode,
4577                                                XEXP (XEXP (x, 0), 0),
4578                                                XEXP (x, 1));
4579           if (tem)
4580             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4581         }
4582       break;
4583
4584     case UDIV:
4585       /* If this is a divide by a power of two, treat it as a shift if
4586          its first operand is a shift.  */
4587       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4588           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4589           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4590               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4591               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4592               || GET_CODE (XEXP (x, 0)) == ROTATE
4593               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4594         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4595       break;
4596
4597     case EQ:  case NE:
4598     case GT:  case GTU:  case GE:  case GEU:
4599     case LT:  case LTU:  case LE:  case LEU:
4600     case UNEQ:  case LTGT:
4601     case UNGT:  case UNGE:
4602     case UNLT:  case UNLE:
4603     case UNORDERED: case ORDERED:
4604       /* If the first operand is a condition code, we can't do anything
4605          with it.  */
4606       if (GET_CODE (XEXP (x, 0)) == COMPARE
4607           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4608               && ! CC0_P (XEXP (x, 0))))
4609         {
4610           rtx op0 = XEXP (x, 0);
4611           rtx op1 = XEXP (x, 1);
4612           enum rtx_code new_code;
4613
4614           if (GET_CODE (op0) == COMPARE)
4615             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4616
4617           /* Simplify our comparison, if possible.  */
4618           new_code = simplify_comparison (code, &op0, &op1);
4619
4620           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4621              if only the low-order bit is possibly nonzero in X (such as when
4622              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4623              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4624              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4625              (plus X 1).
4626
4627              Remove any ZERO_EXTRACT we made when thinking this was a
4628              comparison.  It may now be simpler to use, e.g., an AND.  If a
4629              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4630              the call to make_compound_operation in the SET case.  */
4631
4632           if (STORE_FLAG_VALUE == 1
4633               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4634               && op1 == const0_rtx
4635               && mode == GET_MODE (op0)
4636               && nonzero_bits (op0, mode) == 1)
4637             return gen_lowpart (mode,
4638                                 expand_compound_operation (op0));
4639
4640           else if (STORE_FLAG_VALUE == 1
4641                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4642                    && op1 == const0_rtx
4643                    && mode == GET_MODE (op0)
4644                    && (num_sign_bit_copies (op0, mode)
4645                        == GET_MODE_BITSIZE (mode)))
4646             {
4647               op0 = expand_compound_operation (op0);
4648               return simplify_gen_unary (NEG, mode,
4649                                          gen_lowpart (mode, op0),
4650                                          mode);
4651             }
4652
4653           else if (STORE_FLAG_VALUE == 1
4654                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4655                    && op1 == const0_rtx
4656                    && mode == GET_MODE (op0)
4657                    && nonzero_bits (op0, mode) == 1)
4658             {
4659               op0 = expand_compound_operation (op0);
4660               return simplify_gen_binary (XOR, mode,
4661                                           gen_lowpart (mode, op0),
4662                                           const1_rtx);
4663             }
4664
4665           else if (STORE_FLAG_VALUE == 1
4666                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4667                    && op1 == const0_rtx
4668                    && mode == GET_MODE (op0)
4669                    && (num_sign_bit_copies (op0, mode)
4670                        == GET_MODE_BITSIZE (mode)))
4671             {
4672               op0 = expand_compound_operation (op0);
4673               return plus_constant (gen_lowpart (mode, op0), 1);
4674             }
4675
4676           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4677              those above.  */
4678           if (STORE_FLAG_VALUE == -1
4679               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4680               && op1 == const0_rtx
4681               && (num_sign_bit_copies (op0, mode)
4682                   == GET_MODE_BITSIZE (mode)))
4683             return gen_lowpart (mode,
4684                                 expand_compound_operation (op0));
4685
4686           else if (STORE_FLAG_VALUE == -1
4687                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4688                    && op1 == const0_rtx
4689                    && mode == GET_MODE (op0)
4690                    && nonzero_bits (op0, mode) == 1)
4691             {
4692               op0 = expand_compound_operation (op0);
4693               return simplify_gen_unary (NEG, mode,
4694                                          gen_lowpart (mode, op0),
4695                                          mode);
4696             }
4697
4698           else if (STORE_FLAG_VALUE == -1
4699                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4700                    && op1 == const0_rtx
4701                    && mode == GET_MODE (op0)
4702                    && (num_sign_bit_copies (op0, mode)
4703                        == GET_MODE_BITSIZE (mode)))
4704             {
4705               op0 = expand_compound_operation (op0);
4706               return simplify_gen_unary (NOT, mode,
4707                                          gen_lowpart (mode, op0),
4708                                          mode);
4709             }
4710
4711           /* If X is 0/1, (eq X 0) is X-1.  */
4712           else if (STORE_FLAG_VALUE == -1
4713                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4714                    && op1 == const0_rtx
4715                    && mode == GET_MODE (op0)
4716                    && nonzero_bits (op0, mode) == 1)
4717             {
4718               op0 = expand_compound_operation (op0);
4719               return plus_constant (gen_lowpart (mode, op0), -1);
4720             }
4721
4722           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4723              one bit that might be nonzero, we can convert (ne x 0) to
4724              (ashift x c) where C puts the bit in the sign bit.  Remove any
4725              AND with STORE_FLAG_VALUE when we are done, since we are only
4726              going to test the sign bit.  */
4727           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4728               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4729               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4730                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4731               && op1 == const0_rtx
4732               && mode == GET_MODE (op0)
4733               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4734             {
4735               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4736                                         expand_compound_operation (op0),
4737                                         GET_MODE_BITSIZE (mode) - 1 - i);
4738               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4739                 return XEXP (x, 0);
4740               else
4741                 return x;
4742             }
4743
4744           /* If the code changed, return a whole new comparison.  */
4745           if (new_code != code)
4746             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4747
4748           /* Otherwise, keep this operation, but maybe change its operands.
4749              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4750           SUBST (XEXP (x, 0), op0);
4751           SUBST (XEXP (x, 1), op1);
4752         }
4753       break;
4754
4755     case IF_THEN_ELSE:
4756       return simplify_if_then_else (x);
4757
4758     case ZERO_EXTRACT:
4759     case SIGN_EXTRACT:
4760     case ZERO_EXTEND:
4761     case SIGN_EXTEND:
4762       /* If we are processing SET_DEST, we are done.  */
4763       if (in_dest)
4764         return x;
4765
4766       return expand_compound_operation (x);
4767
4768     case SET:
4769       return simplify_set (x);
4770
4771     case AND:
4772     case IOR:
4773       return simplify_logical (x);
4774
4775     case ASHIFT:
4776     case LSHIFTRT:
4777     case ASHIFTRT:
4778     case ROTATE:
4779     case ROTATERT:
4780       /* If this is a shift by a constant amount, simplify it.  */
4781       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4782         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4783                                      INTVAL (XEXP (x, 1)));
4784
4785       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4786         SUBST (XEXP (x, 1),
4787                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4788                               ((HOST_WIDE_INT) 1
4789                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4790                               - 1,
4791                               0));
4792       break;
4793
4794     default:
4795       break;
4796     }
4797
4798   return x;
4799 }
4800 \f
4801 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4802
4803 static rtx
4804 simplify_if_then_else (rtx x)
4805 {
4806   enum machine_mode mode = GET_MODE (x);
4807   rtx cond = XEXP (x, 0);
4808   rtx true_rtx = XEXP (x, 1);
4809   rtx false_rtx = XEXP (x, 2);
4810   enum rtx_code true_code = GET_CODE (cond);
4811   int comparison_p = COMPARISON_P (cond);
4812   rtx temp;
4813   int i;
4814   enum rtx_code false_code;
4815   rtx reversed;
4816
4817   /* Simplify storing of the truth value.  */
4818   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4819     return simplify_gen_relational (true_code, mode, VOIDmode,
4820                                     XEXP (cond, 0), XEXP (cond, 1));
4821
4822   /* Also when the truth value has to be reversed.  */
4823   if (comparison_p
4824       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4825       && (reversed = reversed_comparison (cond, mode)))
4826     return reversed;
4827
4828   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4829      in it is being compared against certain values.  Get the true and false
4830      comparisons and see if that says anything about the value of each arm.  */
4831
4832   if (comparison_p
4833       && ((false_code = reversed_comparison_code (cond, NULL))
4834           != UNKNOWN)
4835       && REG_P (XEXP (cond, 0)))
4836     {
4837       HOST_WIDE_INT nzb;
4838       rtx from = XEXP (cond, 0);
4839       rtx true_val = XEXP (cond, 1);
4840       rtx false_val = true_val;
4841       int swapped = 0;
4842
4843       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4844
4845       if (false_code == EQ)
4846         {
4847           swapped = 1, true_code = EQ, false_code = NE;
4848           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4849         }
4850
4851       /* If we are comparing against zero and the expression being tested has
4852          only a single bit that might be nonzero, that is its value when it is
4853          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4854
4855       if (true_code == EQ && true_val == const0_rtx
4856           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4857         false_code = EQ, false_val = GEN_INT (nzb);
4858       else if (true_code == EQ && true_val == const0_rtx
4859                && (num_sign_bit_copies (from, GET_MODE (from))
4860                    == GET_MODE_BITSIZE (GET_MODE (from))))
4861         false_code = EQ, false_val = constm1_rtx;
4862
4863       /* Now simplify an arm if we know the value of the register in the
4864          branch and it is used in the arm.  Be careful due to the potential
4865          of locally-shared RTL.  */
4866
4867       if (reg_mentioned_p (from, true_rtx))
4868         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4869                                       from, true_val),
4870                       pc_rtx, pc_rtx, 0, 0);
4871       if (reg_mentioned_p (from, false_rtx))
4872         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4873                                    from, false_val),
4874                        pc_rtx, pc_rtx, 0, 0);
4875
4876       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4877       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4878
4879       true_rtx = XEXP (x, 1);
4880       false_rtx = XEXP (x, 2);
4881       true_code = GET_CODE (cond);
4882     }
4883
4884   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4885      reversed, do so to avoid needing two sets of patterns for
4886      subtract-and-branch insns.  Similarly if we have a constant in the true
4887      arm, the false arm is the same as the first operand of the comparison, or
4888      the false arm is more complicated than the true arm.  */
4889
4890   if (comparison_p
4891       && reversed_comparison_code (cond, NULL) != UNKNOWN
4892       && (true_rtx == pc_rtx
4893           || (CONSTANT_P (true_rtx)
4894               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4895           || true_rtx == const0_rtx
4896           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4897           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4898               && !OBJECT_P (false_rtx))
4899           || reg_mentioned_p (true_rtx, false_rtx)
4900           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4901     {
4902       true_code = reversed_comparison_code (cond, NULL);
4903       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4904       SUBST (XEXP (x, 1), false_rtx);
4905       SUBST (XEXP (x, 2), true_rtx);
4906
4907       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4908       cond = XEXP (x, 0);
4909
4910       /* It is possible that the conditional has been simplified out.  */
4911       true_code = GET_CODE (cond);
4912       comparison_p = COMPARISON_P (cond);
4913     }
4914
4915   /* If the two arms are identical, we don't need the comparison.  */
4916
4917   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4918     return true_rtx;
4919
4920   /* Convert a == b ? b : a to "a".  */
4921   if (true_code == EQ && ! side_effects_p (cond)
4922       && !HONOR_NANS (mode)
4923       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4924       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4925     return false_rtx;
4926   else if (true_code == NE && ! side_effects_p (cond)
4927            && !HONOR_NANS (mode)
4928            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4929            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4930     return true_rtx;
4931
4932   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4933
4934   if (GET_MODE_CLASS (mode) == MODE_INT
4935       && GET_CODE (false_rtx) == NEG
4936       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4937       && comparison_p
4938       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4939       && ! side_effects_p (true_rtx))
4940     switch (true_code)
4941       {
4942       case GT:
4943       case GE:
4944         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4945       case LT:
4946       case LE:
4947         return
4948           simplify_gen_unary (NEG, mode,
4949                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4950                               mode);
4951       default:
4952         break;
4953       }
4954
4955   /* Look for MIN or MAX.  */
4956
4957   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4958       && comparison_p
4959       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4960       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4961       && ! side_effects_p (cond))
4962     switch (true_code)
4963       {
4964       case GE:
4965       case GT:
4966         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4967       case LE:
4968       case LT:
4969         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4970       case GEU:
4971       case GTU:
4972         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4973       case LEU:
4974       case LTU:
4975         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4976       default:
4977         break;
4978       }
4979
4980   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4981      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4982      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4983      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4984      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4985      neither 1 or -1, but it isn't worth checking for.  */
4986
4987   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4988       && comparison_p
4989       && GET_MODE_CLASS (mode) == MODE_INT
4990       && ! side_effects_p (x))
4991     {
4992       rtx t = make_compound_operation (true_rtx, SET);
4993       rtx f = make_compound_operation (false_rtx, SET);
4994       rtx cond_op0 = XEXP (cond, 0);
4995       rtx cond_op1 = XEXP (cond, 1);
4996       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4997       enum machine_mode m = mode;
4998       rtx z = 0, c1 = NULL_RTX;
4999
5000       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5001            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5002            || GET_CODE (t) == ASHIFT
5003            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5004           && rtx_equal_p (XEXP (t, 0), f))
5005         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5006
5007       /* If an identity-zero op is commutative, check whether there
5008          would be a match if we swapped the operands.  */
5009       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5010                 || GET_CODE (t) == XOR)
5011                && rtx_equal_p (XEXP (t, 1), f))
5012         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5013       else if (GET_CODE (t) == SIGN_EXTEND
5014                && (GET_CODE (XEXP (t, 0)) == PLUS
5015                    || GET_CODE (XEXP (t, 0)) == MINUS
5016                    || GET_CODE (XEXP (t, 0)) == IOR
5017                    || GET_CODE (XEXP (t, 0)) == XOR
5018                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5019                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5020                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5021                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5022                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5023                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5024                && (num_sign_bit_copies (f, GET_MODE (f))
5025                    > (unsigned int)
5026                      (GET_MODE_BITSIZE (mode)
5027                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5028         {
5029           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5030           extend_op = SIGN_EXTEND;
5031           m = GET_MODE (XEXP (t, 0));
5032         }
5033       else if (GET_CODE (t) == SIGN_EXTEND
5034                && (GET_CODE (XEXP (t, 0)) == PLUS
5035                    || GET_CODE (XEXP (t, 0)) == IOR
5036                    || GET_CODE (XEXP (t, 0)) == XOR)
5037                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5038                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5039                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5040                && (num_sign_bit_copies (f, GET_MODE (f))
5041                    > (unsigned int)
5042                      (GET_MODE_BITSIZE (mode)
5043                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5044         {
5045           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5046           extend_op = SIGN_EXTEND;
5047           m = GET_MODE (XEXP (t, 0));
5048         }
5049       else if (GET_CODE (t) == ZERO_EXTEND
5050                && (GET_CODE (XEXP (t, 0)) == PLUS
5051                    || GET_CODE (XEXP (t, 0)) == MINUS
5052                    || GET_CODE (XEXP (t, 0)) == IOR
5053                    || GET_CODE (XEXP (t, 0)) == XOR
5054                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5055                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5056                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5057                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5058                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5059                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5060                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5061                && ((nonzero_bits (f, GET_MODE (f))
5062                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5063                    == 0))
5064         {
5065           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5066           extend_op = ZERO_EXTEND;
5067           m = GET_MODE (XEXP (t, 0));
5068         }
5069       else if (GET_CODE (t) == ZERO_EXTEND
5070                && (GET_CODE (XEXP (t, 0)) == PLUS
5071                    || GET_CODE (XEXP (t, 0)) == IOR
5072                    || GET_CODE (XEXP (t, 0)) == XOR)
5073                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5074                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5075                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5076                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5077                && ((nonzero_bits (f, GET_MODE (f))
5078                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5079                    == 0))
5080         {
5081           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5082           extend_op = ZERO_EXTEND;
5083           m = GET_MODE (XEXP (t, 0));
5084         }
5085
5086       if (z)
5087         {
5088           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5089                                                  cond_op0, cond_op1),
5090                         pc_rtx, pc_rtx, 0, 0);
5091           temp = simplify_gen_binary (MULT, m, temp,
5092                                       simplify_gen_binary (MULT, m, c1,
5093                                                            const_true_rtx));
5094           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5095           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5096
5097           if (extend_op != UNKNOWN)
5098             temp = simplify_gen_unary (extend_op, mode, temp, m);
5099
5100           return temp;
5101         }
5102     }
5103
5104   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5105      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5106      negation of a single bit, we can convert this operation to a shift.  We
5107      can actually do this more generally, but it doesn't seem worth it.  */
5108
5109   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5110       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5111       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5112            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5113           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5114                == GET_MODE_BITSIZE (mode))
5115               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5116     return
5117       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5118                             gen_lowpart (mode, XEXP (cond, 0)), i);
5119
5120   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5121   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5122       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5123       && GET_MODE (XEXP (cond, 0)) == mode
5124       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5125           == nonzero_bits (XEXP (cond, 0), mode)
5126       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5127     return XEXP (cond, 0);
5128
5129   return x;
5130 }
5131 \f
5132 /* Simplify X, a SET expression.  Return the new expression.  */
5133
5134 static rtx
5135 simplify_set (rtx x)
5136 {
5137   rtx src = SET_SRC (x);
5138   rtx dest = SET_DEST (x);
5139   enum machine_mode mode
5140     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5141   rtx other_insn;
5142   rtx *cc_use;
5143
5144   /* (set (pc) (return)) gets written as (return).  */
5145   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5146     return src;
5147
5148   /* Now that we know for sure which bits of SRC we are using, see if we can
5149      simplify the expression for the object knowing that we only need the
5150      low-order bits.  */
5151
5152   if (GET_MODE_CLASS (mode) == MODE_INT
5153       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5154     {
5155       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5156       SUBST (SET_SRC (x), src);
5157     }
5158
5159   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5160      the comparison result and try to simplify it unless we already have used
5161      undobuf.other_insn.  */
5162   if ((GET_MODE_CLASS (mode) == MODE_CC
5163        || GET_CODE (src) == COMPARE
5164        || CC0_P (dest))
5165       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5166       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5167       && COMPARISON_P (*cc_use)
5168       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5169     {
5170       enum rtx_code old_code = GET_CODE (*cc_use);
5171       enum rtx_code new_code;
5172       rtx op0, op1, tmp;
5173       int other_changed = 0;
5174       enum machine_mode compare_mode = GET_MODE (dest);
5175
5176       if (GET_CODE (src) == COMPARE)
5177         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5178       else
5179         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5180
5181       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5182                                            op0, op1);
5183       if (!tmp)
5184         new_code = old_code;
5185       else if (!CONSTANT_P (tmp))
5186         {
5187           new_code = GET_CODE (tmp);
5188           op0 = XEXP (tmp, 0);
5189           op1 = XEXP (tmp, 1);
5190         }
5191       else
5192         {
5193           rtx pat = PATTERN (other_insn);
5194           undobuf.other_insn = other_insn;
5195           SUBST (*cc_use, tmp);
5196
5197           /* Attempt to simplify CC user.  */
5198           if (GET_CODE (pat) == SET)
5199             {
5200               rtx new = simplify_rtx (SET_SRC (pat));
5201               if (new != NULL_RTX)
5202                 SUBST (SET_SRC (pat), new);
5203             }
5204
5205           /* Convert X into a no-op move.  */
5206           SUBST (SET_DEST (x), pc_rtx);
5207           SUBST (SET_SRC (x), pc_rtx);
5208           return x;
5209         }
5210
5211       /* Simplify our comparison, if possible.  */
5212       new_code = simplify_comparison (new_code, &op0, &op1);
5213
5214 #ifdef SELECT_CC_MODE
5215       /* If this machine has CC modes other than CCmode, check to see if we
5216          need to use a different CC mode here.  */
5217       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5218         compare_mode = GET_MODE (op0);
5219       else
5220         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5221
5222 #ifndef HAVE_cc0
5223       /* If the mode changed, we have to change SET_DEST, the mode in the
5224          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5225          a hard register, just build new versions with the proper mode.  If it
5226          is a pseudo, we lose unless it is only time we set the pseudo, in
5227          which case we can safely change its mode.  */
5228       if (compare_mode != GET_MODE (dest))
5229         {
5230           if (can_change_dest_mode (dest, 0, compare_mode))
5231             {
5232               unsigned int regno = REGNO (dest);
5233               rtx new_dest;
5234
5235               if (regno < FIRST_PSEUDO_REGISTER)
5236                 new_dest = gen_rtx_REG (compare_mode, regno);
5237               else
5238                 {
5239                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5240                   new_dest = regno_reg_rtx[regno];
5241                 }
5242
5243               SUBST (SET_DEST (x), new_dest);
5244               SUBST (XEXP (*cc_use, 0), new_dest);
5245               other_changed = 1;
5246
5247               dest = new_dest;
5248             }
5249         }
5250 #endif  /* cc0 */
5251 #endif  /* SELECT_CC_MODE */
5252
5253       /* If the code changed, we have to build a new comparison in
5254          undobuf.other_insn.  */
5255       if (new_code != old_code)
5256         {
5257           int other_changed_previously = other_changed;
5258           unsigned HOST_WIDE_INT mask;
5259
5260           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5261                                           dest, const0_rtx));
5262           other_changed = 1;
5263
5264           /* If the only change we made was to change an EQ into an NE or
5265              vice versa, OP0 has only one bit that might be nonzero, and OP1
5266              is zero, check if changing the user of the condition code will
5267              produce a valid insn.  If it won't, we can keep the original code
5268              in that insn by surrounding our operation with an XOR.  */
5269
5270           if (((old_code == NE && new_code == EQ)
5271                || (old_code == EQ && new_code == NE))
5272               && ! other_changed_previously && op1 == const0_rtx
5273               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5274               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5275             {
5276               rtx pat = PATTERN (other_insn), note = 0;
5277
5278               if ((recog_for_combine (&pat, other_insn, &note) < 0
5279                    && ! check_asm_operands (pat)))
5280                 {
5281                   PUT_CODE (*cc_use, old_code);
5282                   other_changed = 0;
5283
5284                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5285                                              op0, GEN_INT (mask));
5286                 }
5287             }
5288         }
5289
5290       if (other_changed)
5291         undobuf.other_insn = other_insn;
5292
5293 #ifdef HAVE_cc0
5294       /* If we are now comparing against zero, change our source if
5295          needed.  If we do not use cc0, we always have a COMPARE.  */
5296       if (op1 == const0_rtx && dest == cc0_rtx)
5297         {
5298           SUBST (SET_SRC (x), op0);
5299           src = op0;
5300         }
5301       else
5302 #endif
5303
5304       /* Otherwise, if we didn't previously have a COMPARE in the
5305          correct mode, we need one.  */
5306       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5307         {
5308           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5309           src = SET_SRC (x);
5310         }
5311       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5312         {
5313           SUBST(SET_SRC (x), op0);
5314           src = SET_SRC (x);
5315         }
5316       else
5317         {
5318           /* Otherwise, update the COMPARE if needed.  */
5319           SUBST (XEXP (src, 0), op0);
5320           SUBST (XEXP (src, 1), op1);
5321         }
5322     }
5323   else
5324     {
5325       /* Get SET_SRC in a form where we have placed back any
5326          compound expressions.  Then do the checks below.  */
5327       src = make_compound_operation (src, SET);
5328       SUBST (SET_SRC (x), src);
5329     }
5330
5331   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5332      and X being a REG or (subreg (reg)), we may be able to convert this to
5333      (set (subreg:m2 x) (op)).
5334
5335      We can always do this if M1 is narrower than M2 because that means that
5336      we only care about the low bits of the result.
5337
5338      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5339      perform a narrower operation than requested since the high-order bits will
5340      be undefined.  On machine where it is defined, this transformation is safe
5341      as long as M1 and M2 have the same number of words.  */
5342
5343   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5344       && !OBJECT_P (SUBREG_REG (src))
5345       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5346            / UNITS_PER_WORD)
5347           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5348                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5349 #ifndef WORD_REGISTER_OPERATIONS
5350       && (GET_MODE_SIZE (GET_MODE (src))
5351         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5352 #endif
5353 #ifdef CANNOT_CHANGE_MODE_CLASS
5354       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5355             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5356                                          GET_MODE (SUBREG_REG (src)),
5357                                          GET_MODE (src)))
5358 #endif
5359       && (REG_P (dest)
5360           || (GET_CODE (dest) == SUBREG
5361               && REG_P (SUBREG_REG (dest)))))
5362     {
5363       SUBST (SET_DEST (x),
5364              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5365                                       dest));
5366       SUBST (SET_SRC (x), SUBREG_REG (src));
5367
5368       src = SET_SRC (x), dest = SET_DEST (x);
5369     }
5370
5371 #ifdef HAVE_cc0
5372   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5373      in SRC.  */
5374   if (dest == cc0_rtx
5375       && GET_CODE (src) == SUBREG
5376       && subreg_lowpart_p (src)
5377       && (GET_MODE_BITSIZE (GET_MODE (src))
5378           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5379     {
5380       rtx inner = SUBREG_REG (src);
5381       enum machine_mode inner_mode = GET_MODE (inner);
5382
5383       /* Here we make sure that we don't have a sign bit on.  */
5384       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5385           && (nonzero_bits (inner, inner_mode)
5386               < ((unsigned HOST_WIDE_INT) 1
5387                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5388         {
5389           SUBST (SET_SRC (x), inner);
5390           src = SET_SRC (x);
5391         }
5392     }
5393 #endif
5394
5395 #ifdef LOAD_EXTEND_OP
5396   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5397      would require a paradoxical subreg.  Replace the subreg with a
5398      zero_extend to avoid the reload that would otherwise be required.  */
5399
5400   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5401       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5402       && SUBREG_BYTE (src) == 0
5403       && (GET_MODE_SIZE (GET_MODE (src))
5404           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5405       && MEM_P (SUBREG_REG (src)))
5406     {
5407       SUBST (SET_SRC (x),
5408              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5409                             GET_MODE (src), SUBREG_REG (src)));
5410
5411       src = SET_SRC (x);
5412     }
5413 #endif
5414
5415   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5416      are comparing an item known to be 0 or -1 against 0, use a logical
5417      operation instead. Check for one of the arms being an IOR of the other
5418      arm with some value.  We compute three terms to be IOR'ed together.  In
5419      practice, at most two will be nonzero.  Then we do the IOR's.  */
5420
5421   if (GET_CODE (dest) != PC
5422       && GET_CODE (src) == IF_THEN_ELSE
5423       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5424       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5425       && XEXP (XEXP (src, 0), 1) == const0_rtx
5426       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5427 #ifdef HAVE_conditional_move
5428       && ! can_conditionally_move_p (GET_MODE (src))
5429 #endif
5430       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5431                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5432           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5433       && ! side_effects_p (src))
5434     {
5435       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5436                       ? XEXP (src, 1) : XEXP (src, 2));
5437       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5438                    ? XEXP (src, 2) : XEXP (src, 1));
5439       rtx term1 = const0_rtx, term2, term3;
5440
5441       if (GET_CODE (true_rtx) == IOR
5442           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5443         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5444       else if (GET_CODE (true_rtx) == IOR
5445                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5446         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5447       else if (GET_CODE (false_rtx) == IOR
5448                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5449         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5450       else if (GET_CODE (false_rtx) == IOR
5451                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5452         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5453
5454       term2 = simplify_gen_binary (AND, GET_MODE (src),
5455                                    XEXP (XEXP (src, 0), 0), true_rtx);
5456       term3 = simplify_gen_binary (AND, GET_MODE (src),
5457                                    simplify_gen_unary (NOT, GET_MODE (src),
5458                                                        XEXP (XEXP (src, 0), 0),
5459                                                        GET_MODE (src)),
5460                                    false_rtx);
5461
5462       SUBST (SET_SRC (x),
5463              simplify_gen_binary (IOR, GET_MODE (src),
5464                                   simplify_gen_binary (IOR, GET_MODE (src),
5465                                                        term1, term2),
5466                                   term3));
5467
5468       src = SET_SRC (x);
5469     }
5470
5471   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5472      whole thing fail.  */
5473   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5474     return src;
5475   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5476     return dest;
5477   else
5478     /* Convert this into a field assignment operation, if possible.  */
5479     return make_field_assignment (x);
5480 }
5481 \f
5482 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5483    result.  */
5484
5485 static rtx
5486 simplify_logical (rtx x)
5487 {
5488   enum machine_mode mode = GET_MODE (x);
5489   rtx op0 = XEXP (x, 0);
5490   rtx op1 = XEXP (x, 1);
5491
5492   switch (GET_CODE (x))
5493     {
5494     case AND:
5495       /* We can call simplify_and_const_int only if we don't lose
5496          any (sign) bits when converting INTVAL (op1) to
5497          "unsigned HOST_WIDE_INT".  */
5498       if (GET_CODE (op1) == CONST_INT
5499           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5500               || INTVAL (op1) > 0))
5501         {
5502           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5503           if (GET_CODE (x) != AND)
5504             return x;
5505
5506           op0 = XEXP (x, 0);
5507           op1 = XEXP (x, 1);
5508         }
5509
5510       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5511          apply the distributive law and then the inverse distributive
5512          law to see if things simplify.  */
5513       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5514         {
5515           rtx result = distribute_and_simplify_rtx (x, 0);
5516           if (result)
5517             return result;
5518         }
5519       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5520         {
5521           rtx result = distribute_and_simplify_rtx (x, 1);
5522           if (result)
5523             return result;
5524         }
5525       break;
5526
5527     case IOR:
5528       /* If we have (ior (and A B) C), apply the distributive law and then
5529          the inverse distributive law to see if things simplify.  */
5530
5531       if (GET_CODE (op0) == AND)
5532         {
5533           rtx result = distribute_and_simplify_rtx (x, 0);
5534           if (result)
5535             return result;
5536         }
5537
5538       if (GET_CODE (op1) == AND)
5539         {
5540           rtx result = distribute_and_simplify_rtx (x, 1);
5541           if (result)
5542             return result;
5543         }
5544       break;
5545
5546     default:
5547       gcc_unreachable ();
5548     }
5549
5550   return x;
5551 }
5552 \f
5553 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5554    operations" because they can be replaced with two more basic operations.
5555    ZERO_EXTEND is also considered "compound" because it can be replaced with
5556    an AND operation, which is simpler, though only one operation.
5557
5558    The function expand_compound_operation is called with an rtx expression
5559    and will convert it to the appropriate shifts and AND operations,
5560    simplifying at each stage.
5561
5562    The function make_compound_operation is called to convert an expression
5563    consisting of shifts and ANDs into the equivalent compound expression.
5564    It is the inverse of this function, loosely speaking.  */
5565
5566 static rtx
5567 expand_compound_operation (rtx x)
5568 {
5569   unsigned HOST_WIDE_INT pos = 0, len;
5570   int unsignedp = 0;
5571   unsigned int modewidth;
5572   rtx tem;
5573
5574   switch (GET_CODE (x))
5575     {
5576     case ZERO_EXTEND:
5577       unsignedp = 1;
5578     case SIGN_EXTEND:
5579       /* We can't necessarily use a const_int for a multiword mode;
5580          it depends on implicitly extending the value.
5581          Since we don't know the right way to extend it,
5582          we can't tell whether the implicit way is right.
5583
5584          Even for a mode that is no wider than a const_int,
5585          we can't win, because we need to sign extend one of its bits through
5586          the rest of it, and we don't know which bit.  */
5587       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5588         return x;
5589
5590       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5591          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5592          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5593          reloaded. If not for that, MEM's would very rarely be safe.
5594
5595          Reject MODEs bigger than a word, because we might not be able
5596          to reference a two-register group starting with an arbitrary register
5597          (and currently gen_lowpart might crash for a SUBREG).  */
5598
5599       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5600         return x;
5601
5602       /* Reject MODEs that aren't scalar integers because turning vector
5603          or complex modes into shifts causes problems.  */
5604
5605       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5606         return x;
5607
5608       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5609       /* If the inner object has VOIDmode (the only way this can happen
5610          is if it is an ASM_OPERANDS), we can't do anything since we don't
5611          know how much masking to do.  */
5612       if (len == 0)
5613         return x;
5614
5615       break;
5616
5617     case ZERO_EXTRACT:
5618       unsignedp = 1;
5619
5620       /* ... fall through ...  */
5621
5622     case SIGN_EXTRACT:
5623       /* If the operand is a CLOBBER, just return it.  */
5624       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5625         return XEXP (x, 0);
5626
5627       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5628           || GET_CODE (XEXP (x, 2)) != CONST_INT
5629           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5630         return x;
5631
5632       /* Reject MODEs that aren't scalar integers because turning vector
5633          or complex modes into shifts causes problems.  */
5634
5635       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5636         return x;
5637
5638       len = INTVAL (XEXP (x, 1));
5639       pos = INTVAL (XEXP (x, 2));
5640
5641       /* This should stay within the object being extracted, fail otherwise.  */
5642       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5643         return x;
5644
5645       if (BITS_BIG_ENDIAN)
5646         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5647
5648       break;
5649
5650     default:
5651       return x;
5652     }
5653   /* Convert sign extension to zero extension, if we know that the high
5654      bit is not set, as this is easier to optimize.  It will be converted
5655      back to cheaper alternative in make_extraction.  */
5656   if (GET_CODE (x) == SIGN_EXTEND
5657       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5658           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5659                 & ~(((unsigned HOST_WIDE_INT)
5660                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5661                      >> 1))
5662                == 0)))
5663     {
5664       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5665       rtx temp2 = expand_compound_operation (temp);
5666
5667       /* Make sure this is a profitable operation.  */
5668       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5669        return temp2;
5670       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5671        return temp;
5672       else
5673        return x;
5674     }
5675
5676   /* We can optimize some special cases of ZERO_EXTEND.  */
5677   if (GET_CODE (x) == ZERO_EXTEND)
5678     {
5679       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5680          know that the last value didn't have any inappropriate bits
5681          set.  */
5682       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5683           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5684           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5685           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5686               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5687         return XEXP (XEXP (x, 0), 0);
5688
5689       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5690       if (GET_CODE (XEXP (x, 0)) == SUBREG
5691           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5692           && subreg_lowpart_p (XEXP (x, 0))
5693           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5694           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5695               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5696         return SUBREG_REG (XEXP (x, 0));
5697
5698       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5699          is a comparison and STORE_FLAG_VALUE permits.  This is like
5700          the first case, but it works even when GET_MODE (x) is larger
5701          than HOST_WIDE_INT.  */
5702       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5703           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5704           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5705           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5706               <= HOST_BITS_PER_WIDE_INT)
5707           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5708               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5709         return XEXP (XEXP (x, 0), 0);
5710
5711       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5712       if (GET_CODE (XEXP (x, 0)) == SUBREG
5713           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5714           && subreg_lowpart_p (XEXP (x, 0))
5715           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5716           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5717               <= HOST_BITS_PER_WIDE_INT)
5718           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5719               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5720         return SUBREG_REG (XEXP (x, 0));
5721
5722     }
5723
5724   /* If we reach here, we want to return a pair of shifts.  The inner
5725      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5726      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5727      logical depending on the value of UNSIGNEDP.
5728
5729      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5730      converted into an AND of a shift.
5731
5732      We must check for the case where the left shift would have a negative
5733      count.  This can happen in a case like (x >> 31) & 255 on machines
5734      that can't shift by a constant.  On those machines, we would first
5735      combine the shift with the AND to produce a variable-position
5736      extraction.  Then the constant of 31 would be substituted in to produce
5737      a such a position.  */
5738
5739   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5740   if (modewidth + len >= pos)
5741     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5742                                 GET_MODE (x),
5743                                 simplify_shift_const (NULL_RTX, ASHIFT,
5744                                                       GET_MODE (x),
5745                                                       XEXP (x, 0),
5746                                                       modewidth - pos - len),
5747                                 modewidth - len);
5748
5749   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5750     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5751                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5752                                                         GET_MODE (x),
5753                                                         XEXP (x, 0), pos),
5754                                   ((HOST_WIDE_INT) 1 << len) - 1);
5755   else
5756     /* Any other cases we can't handle.  */
5757     return x;
5758
5759   /* If we couldn't do this for some reason, return the original
5760      expression.  */
5761   if (GET_CODE (tem) == CLOBBER)
5762     return x;
5763
5764   return tem;
5765 }
5766 \f
5767 /* X is a SET which contains an assignment of one object into
5768    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5769    or certain SUBREGS). If possible, convert it into a series of
5770    logical operations.
5771
5772    We half-heartedly support variable positions, but do not at all
5773    support variable lengths.  */
5774
5775 static rtx
5776 expand_field_assignment (rtx x)
5777 {
5778   rtx inner;
5779   rtx pos;                      /* Always counts from low bit.  */
5780   int len;
5781   rtx mask, cleared, masked;
5782   enum machine_mode compute_mode;
5783
5784   /* Loop until we find something we can't simplify.  */
5785   while (1)
5786     {
5787       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5788           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5789         {
5790           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5791           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5792           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5793         }
5794       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5795                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5796         {
5797           inner = XEXP (SET_DEST (x), 0);
5798           len = INTVAL (XEXP (SET_DEST (x), 1));
5799           pos = XEXP (SET_DEST (x), 2);
5800
5801           /* A constant position should stay within the width of INNER.  */
5802           if (GET_CODE (pos) == CONST_INT
5803               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5804             break;
5805
5806           if (BITS_BIG_ENDIAN)
5807             {
5808               if (GET_CODE (pos) == CONST_INT)
5809                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5810                                - INTVAL (pos));
5811               else if (GET_CODE (pos) == MINUS
5812                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5813                        && (INTVAL (XEXP (pos, 1))
5814                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5815                 /* If position is ADJUST - X, new position is X.  */
5816                 pos = XEXP (pos, 0);
5817               else
5818                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5819                                            GEN_INT (GET_MODE_BITSIZE (
5820                                                     GET_MODE (inner))
5821                                                     - len),
5822                                            pos);
5823             }
5824         }
5825
5826       /* A SUBREG between two modes that occupy the same numbers of words
5827          can be done by moving the SUBREG to the source.  */
5828       else if (GET_CODE (SET_DEST (x)) == SUBREG
5829                /* We need SUBREGs to compute nonzero_bits properly.  */
5830                && nonzero_sign_valid
5831                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5832                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5833                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5834                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5835         {
5836           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5837                            gen_lowpart
5838                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5839                             SET_SRC (x)));
5840           continue;
5841         }
5842       else
5843         break;
5844
5845       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5846         inner = SUBREG_REG (inner);
5847
5848       compute_mode = GET_MODE (inner);
5849
5850       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5851       if (! SCALAR_INT_MODE_P (compute_mode))
5852         {
5853           enum machine_mode imode;
5854
5855           /* Don't do anything for vector or complex integral types.  */
5856           if (! FLOAT_MODE_P (compute_mode))
5857             break;
5858
5859           /* Try to find an integral mode to pun with.  */
5860           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5861           if (imode == BLKmode)
5862             break;
5863
5864           compute_mode = imode;
5865           inner = gen_lowpart (imode, inner);
5866         }
5867
5868       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5869       if (len >= HOST_BITS_PER_WIDE_INT)
5870         break;
5871
5872       /* Now compute the equivalent expression.  Make a copy of INNER
5873          for the SET_DEST in case it is a MEM into which we will substitute;
5874          we don't want shared RTL in that case.  */
5875       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5876       cleared = simplify_gen_binary (AND, compute_mode,
5877                                      simplify_gen_unary (NOT, compute_mode,
5878                                        simplify_gen_binary (ASHIFT,
5879                                                             compute_mode,
5880                                                             mask, pos),
5881                                        compute_mode),
5882                                      inner);
5883       masked = simplify_gen_binary (ASHIFT, compute_mode,
5884                                     simplify_gen_binary (
5885                                       AND, compute_mode,
5886                                       gen_lowpart (compute_mode, SET_SRC (x)),
5887                                       mask),
5888                                     pos);
5889
5890       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5891                        simplify_gen_binary (IOR, compute_mode,
5892                                             cleared, masked));
5893     }
5894
5895   return x;
5896 }
5897 \f
5898 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5899    it is an RTX that represents a variable starting position; otherwise,
5900    POS is the (constant) starting bit position (counted from the LSB).
5901
5902    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5903    signed reference.
5904
5905    IN_DEST is nonzero if this is a reference in the destination of a
5906    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5907    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5908    be used.
5909
5910    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5911    ZERO_EXTRACT should be built even for bits starting at bit 0.
5912
5913    MODE is the desired mode of the result (if IN_DEST == 0).
5914
5915    The result is an RTX for the extraction or NULL_RTX if the target
5916    can't handle it.  */
5917
5918 static rtx
5919 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5920                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5921                  int in_dest, int in_compare)
5922 {
5923   /* This mode describes the size of the storage area
5924      to fetch the overall value from.  Within that, we
5925      ignore the POS lowest bits, etc.  */
5926   enum machine_mode is_mode = GET_MODE (inner);
5927   enum machine_mode inner_mode;
5928   enum machine_mode wanted_inner_mode;
5929   enum machine_mode wanted_inner_reg_mode = word_mode;
5930   enum machine_mode pos_mode = word_mode;
5931   enum machine_mode extraction_mode = word_mode;
5932   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5933   rtx new = 0;
5934   rtx orig_pos_rtx = pos_rtx;
5935   HOST_WIDE_INT orig_pos;
5936
5937   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5938     {
5939       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5940          consider just the QI as the memory to extract from.
5941          The subreg adds or removes high bits; its mode is
5942          irrelevant to the meaning of this extraction,
5943          since POS and LEN count from the lsb.  */
5944       if (MEM_P (SUBREG_REG (inner)))
5945         is_mode = GET_MODE (SUBREG_REG (inner));
5946       inner = SUBREG_REG (inner);
5947     }
5948   else if (GET_CODE (inner) == ASHIFT
5949            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5950            && pos_rtx == 0 && pos == 0
5951            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5952     {
5953       /* We're extracting the least significant bits of an rtx
5954          (ashift X (const_int C)), where LEN > C.  Extract the
5955          least significant (LEN - C) bits of X, giving an rtx
5956          whose mode is MODE, then shift it left C times.  */
5957       new = make_extraction (mode, XEXP (inner, 0),
5958                              0, 0, len - INTVAL (XEXP (inner, 1)),
5959                              unsignedp, in_dest, in_compare);
5960       if (new != 0)
5961         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5962     }
5963
5964   inner_mode = GET_MODE (inner);
5965
5966   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5967     pos = INTVAL (pos_rtx), pos_rtx = 0;
5968
5969   /* See if this can be done without an extraction.  We never can if the
5970      width of the field is not the same as that of some integer mode. For
5971      registers, we can only avoid the extraction if the position is at the
5972      low-order bit and this is either not in the destination or we have the
5973      appropriate STRICT_LOW_PART operation available.
5974
5975      For MEM, we can avoid an extract if the field starts on an appropriate
5976      boundary and we can change the mode of the memory reference.  */
5977
5978   if (tmode != BLKmode
5979       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5980            && !MEM_P (inner)
5981            && (inner_mode == tmode
5982                || !REG_P (inner)
5983                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5984                                          GET_MODE_BITSIZE (inner_mode))
5985                || reg_truncated_to_mode (tmode, inner))
5986            && (! in_dest
5987                || (REG_P (inner)
5988                    && have_insn_for (STRICT_LOW_PART, tmode))))
5989           || (MEM_P (inner) && pos_rtx == 0
5990               && (pos
5991                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5992                      : BITS_PER_UNIT)) == 0
5993               /* We can't do this if we are widening INNER_MODE (it
5994                  may not be aligned, for one thing).  */
5995               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5996               && (inner_mode == tmode
5997                   || (! mode_dependent_address_p (XEXP (inner, 0))
5998                       && ! MEM_VOLATILE_P (inner))))))
5999     {
6000       /* If INNER is a MEM, make a new MEM that encompasses just the desired
6001          field.  If the original and current mode are the same, we need not
6002          adjust the offset.  Otherwise, we do if bytes big endian.
6003
6004          If INNER is not a MEM, get a piece consisting of just the field
6005          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6006
6007       if (MEM_P (inner))
6008         {
6009           HOST_WIDE_INT offset;
6010
6011           /* POS counts from lsb, but make OFFSET count in memory order.  */
6012           if (BYTES_BIG_ENDIAN)
6013             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6014           else
6015             offset = pos / BITS_PER_UNIT;
6016
6017           new = adjust_address_nv (inner, tmode, offset);
6018         }
6019       else if (REG_P (inner))
6020         {
6021           if (tmode != inner_mode)
6022             {
6023               /* We can't call gen_lowpart in a DEST since we
6024                  always want a SUBREG (see below) and it would sometimes
6025                  return a new hard register.  */
6026               if (pos || in_dest)
6027                 {
6028                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6029
6030                   if (WORDS_BIG_ENDIAN
6031                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6032                     final_word = ((GET_MODE_SIZE (inner_mode)
6033                                    - GET_MODE_SIZE (tmode))
6034                                   / UNITS_PER_WORD) - final_word;
6035
6036                   final_word *= UNITS_PER_WORD;
6037                   if (BYTES_BIG_ENDIAN &&
6038                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6039                     final_word += (GET_MODE_SIZE (inner_mode)
6040                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6041
6042                   /* Avoid creating invalid subregs, for example when
6043                      simplifying (x>>32)&255.  */
6044                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6045                     return NULL_RTX;
6046
6047                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6048                 }
6049               else
6050                 new = gen_lowpart (tmode, inner);
6051             }
6052           else
6053             new = inner;
6054         }
6055       else
6056         new = force_to_mode (inner, tmode,
6057                              len >= HOST_BITS_PER_WIDE_INT
6058                              ? ~(unsigned HOST_WIDE_INT) 0
6059                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6060                              0);
6061
6062       /* If this extraction is going into the destination of a SET,
6063          make a STRICT_LOW_PART unless we made a MEM.  */
6064
6065       if (in_dest)
6066         return (MEM_P (new) ? new
6067                 : (GET_CODE (new) != SUBREG
6068                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6069                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6070
6071       if (mode == tmode)
6072         return new;
6073
6074       if (GET_CODE (new) == CONST_INT)
6075         return gen_int_mode (INTVAL (new), mode);
6076
6077       /* If we know that no extraneous bits are set, and that the high
6078          bit is not set, convert the extraction to the cheaper of
6079          sign and zero extension, that are equivalent in these cases.  */
6080       if (flag_expensive_optimizations
6081           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6082               && ((nonzero_bits (new, tmode)
6083                    & ~(((unsigned HOST_WIDE_INT)
6084                         GET_MODE_MASK (tmode))
6085                        >> 1))
6086                   == 0)))
6087         {
6088           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6089           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6090
6091           /* Prefer ZERO_EXTENSION, since it gives more information to
6092              backends.  */
6093           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6094             return temp;
6095           return temp1;
6096         }
6097
6098       /* Otherwise, sign- or zero-extend unless we already are in the
6099          proper mode.  */
6100
6101       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6102                              mode, new));
6103     }
6104
6105   /* Unless this is a COMPARE or we have a funny memory reference,
6106      don't do anything with zero-extending field extracts starting at
6107      the low-order bit since they are simple AND operations.  */
6108   if (pos_rtx == 0 && pos == 0 && ! in_dest
6109       && ! in_compare && unsignedp)
6110     return 0;
6111
6112   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6113      if the position is not a constant and the length is not 1.  In all
6114      other cases, we would only be going outside our object in cases when
6115      an original shift would have been undefined.  */
6116   if (MEM_P (inner)
6117       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6118           || (pos_rtx != 0 && len != 1)))
6119     return 0;
6120
6121   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6122      and the mode for the result.  */
6123   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6124     {
6125       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6126       pos_mode = mode_for_extraction (EP_insv, 2);
6127       extraction_mode = mode_for_extraction (EP_insv, 3);
6128     }
6129
6130   if (! in_dest && unsignedp
6131       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6132     {
6133       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6134       pos_mode = mode_for_extraction (EP_extzv, 3);
6135       extraction_mode = mode_for_extraction (EP_extzv, 0);
6136     }
6137
6138   if (! in_dest && ! unsignedp
6139       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6140     {
6141       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6142       pos_mode = mode_for_extraction (EP_extv, 3);
6143       extraction_mode = mode_for_extraction (EP_extv, 0);
6144     }
6145
6146   /* Never narrow an object, since that might not be safe.  */
6147
6148   if (mode != VOIDmode
6149       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6150     extraction_mode = mode;
6151
6152   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6153       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6154     pos_mode = GET_MODE (pos_rtx);
6155
6156   /* If this is not from memory, the desired mode is the preferred mode
6157      for an extraction pattern's first input operand, or word_mode if there
6158      is none.  */
6159   if (!MEM_P (inner))
6160     wanted_inner_mode = wanted_inner_reg_mode;
6161   else
6162     {
6163       /* Be careful not to go beyond the extracted object and maintain the
6164          natural alignment of the memory.  */
6165       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6166       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6167              > GET_MODE_BITSIZE (wanted_inner_mode))
6168         {
6169           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6170           gcc_assert (wanted_inner_mode != VOIDmode);
6171         }
6172
6173       /* If we have to change the mode of memory and cannot, the desired mode
6174          is EXTRACTION_MODE.  */
6175       if (inner_mode != wanted_inner_mode
6176           && (mode_dependent_address_p (XEXP (inner, 0))
6177               || MEM_VOLATILE_P (inner)
6178               || pos_rtx))
6179         wanted_inner_mode = extraction_mode;
6180     }
6181
6182   orig_pos = pos;
6183
6184   if (BITS_BIG_ENDIAN)
6185     {
6186       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6187          BITS_BIG_ENDIAN style.  If position is constant, compute new
6188          position.  Otherwise, build subtraction.
6189          Note that POS is relative to the mode of the original argument.
6190          If it's a MEM we need to recompute POS relative to that.
6191          However, if we're extracting from (or inserting into) a register,
6192          we want to recompute POS relative to wanted_inner_mode.  */
6193       int width = (MEM_P (inner)
6194                    ? GET_MODE_BITSIZE (is_mode)
6195                    : GET_MODE_BITSIZE (wanted_inner_mode));
6196
6197       if (pos_rtx == 0)
6198         pos = width - len - pos;
6199       else
6200         pos_rtx
6201           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6202       /* POS may be less than 0 now, but we check for that below.
6203          Note that it can only be less than 0 if !MEM_P (inner).  */
6204     }
6205
6206   /* If INNER has a wider mode, and this is a constant extraction, try to
6207      make it smaller and adjust the byte to point to the byte containing
6208      the value.  */
6209   if (wanted_inner_mode != VOIDmode
6210       && inner_mode != wanted_inner_mode
6211       && ! pos_rtx
6212       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6213       && MEM_P (inner)
6214       && ! mode_dependent_address_p (XEXP (inner, 0))
6215       && ! MEM_VOLATILE_P (inner))
6216     {
6217       int offset = 0;
6218
6219       /* The computations below will be correct if the machine is big
6220          endian in both bits and bytes or little endian in bits and bytes.
6221          If it is mixed, we must adjust.  */
6222
6223       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6224          adjust OFFSET to compensate.  */
6225       if (BYTES_BIG_ENDIAN
6226           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6227         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6228
6229       /* We can now move to the desired byte.  */
6230       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6231                 * GET_MODE_SIZE (wanted_inner_mode);
6232       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6233
6234       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6235           && is_mode != wanted_inner_mode)
6236         offset = (GET_MODE_SIZE (is_mode)
6237                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6238
6239       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6240     }
6241
6242   /* If INNER is not memory, we can always get it into the proper mode.  If we
6243      are changing its mode, POS must be a constant and smaller than the size
6244      of the new mode.  */
6245   else if (!MEM_P (inner))
6246     {
6247       if (GET_MODE (inner) != wanted_inner_mode
6248           && (pos_rtx != 0
6249               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6250         return 0;
6251
6252       inner = force_to_mode (inner, wanted_inner_mode,
6253                              pos_rtx
6254                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6255                              ? ~(unsigned HOST_WIDE_INT) 0
6256                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6257                                 << orig_pos),
6258                              0);
6259     }
6260
6261   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6262      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6263   if (pos_rtx != 0
6264       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6265     {
6266       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6267
6268       /* If we know that no extraneous bits are set, and that the high
6269          bit is not set, convert extraction to cheaper one - either
6270          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6271          cases.  */
6272       if (flag_expensive_optimizations
6273           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6274               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6275                    & ~(((unsigned HOST_WIDE_INT)
6276                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6277                        >> 1))
6278                   == 0)))
6279         {
6280           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6281
6282           /* Prefer ZERO_EXTENSION, since it gives more information to
6283              backends.  */
6284           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6285             temp = temp1;
6286         }
6287       pos_rtx = temp;
6288     }
6289   else if (pos_rtx != 0
6290            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6291     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6292
6293   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6294      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6295      be a CONST_INT.  */
6296   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6297     pos_rtx = orig_pos_rtx;
6298
6299   else if (pos_rtx == 0)
6300     pos_rtx = GEN_INT (pos);
6301
6302   /* Make the required operation.  See if we can use existing rtx.  */
6303   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6304                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6305   if (! in_dest)
6306     new = gen_lowpart (mode, new);
6307
6308   return new;
6309 }
6310 \f
6311 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6312    with any other operations in X.  Return X without that shift if so.  */
6313
6314 static rtx
6315 extract_left_shift (rtx x, int count)
6316 {
6317   enum rtx_code code = GET_CODE (x);
6318   enum machine_mode mode = GET_MODE (x);
6319   rtx tem;
6320
6321   switch (code)
6322     {
6323     case ASHIFT:
6324       /* This is the shift itself.  If it is wide enough, we will return
6325          either the value being shifted if the shift count is equal to
6326          COUNT or a shift for the difference.  */
6327       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6328           && INTVAL (XEXP (x, 1)) >= count)
6329         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6330                                      INTVAL (XEXP (x, 1)) - count);
6331       break;
6332
6333     case NEG:  case NOT:
6334       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6335         return simplify_gen_unary (code, mode, tem, mode);
6336
6337       break;
6338
6339     case PLUS:  case IOR:  case XOR:  case AND:
6340       /* If we can safely shift this constant and we find the inner shift,
6341          make a new operation.  */
6342       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6343           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6344           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6345         return simplify_gen_binary (code, mode, tem,
6346                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6347
6348       break;
6349
6350     default:
6351       break;
6352     }
6353
6354   return 0;
6355 }
6356 \f
6357 /* Look at the expression rooted at X.  Look for expressions
6358    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6359    Form these expressions.
6360
6361    Return the new rtx, usually just X.
6362
6363    Also, for machines like the VAX that don't have logical shift insns,
6364    try to convert logical to arithmetic shift operations in cases where
6365    they are equivalent.  This undoes the canonicalizations to logical
6366    shifts done elsewhere.
6367
6368    We try, as much as possible, to re-use rtl expressions to save memory.
6369
6370    IN_CODE says what kind of expression we are processing.  Normally, it is
6371    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6372    being kludges), it is MEM.  When processing the arguments of a comparison
6373    or a COMPARE against zero, it is COMPARE.  */
6374
6375 static rtx
6376 make_compound_operation (rtx x, enum rtx_code in_code)
6377 {
6378   enum rtx_code code = GET_CODE (x);
6379   enum machine_mode mode = GET_MODE (x);
6380   int mode_width = GET_MODE_BITSIZE (mode);
6381   rtx rhs, lhs;
6382   enum rtx_code next_code;
6383   int i;
6384   rtx new = 0;
6385   rtx tem;
6386   const char *fmt;
6387
6388   /* Select the code to be used in recursive calls.  Once we are inside an
6389      address, we stay there.  If we have a comparison, set to COMPARE,
6390      but once inside, go back to our default of SET.  */
6391
6392   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6393                : ((code == COMPARE || COMPARISON_P (x))
6394                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6395                : in_code == COMPARE ? SET : in_code);
6396
6397   /* Process depending on the code of this operation.  If NEW is set
6398      nonzero, it will be returned.  */
6399
6400   switch (code)
6401     {
6402     case ASHIFT:
6403       /* Convert shifts by constants into multiplications if inside
6404          an address.  */
6405       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6406           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6407           && INTVAL (XEXP (x, 1)) >= 0)
6408         {
6409           new = make_compound_operation (XEXP (x, 0), next_code);
6410           new = gen_rtx_MULT (mode, new,
6411                               GEN_INT ((HOST_WIDE_INT) 1
6412                                        << INTVAL (XEXP (x, 1))));
6413         }
6414       break;
6415
6416     case AND:
6417       /* If the second operand is not a constant, we can't do anything
6418          with it.  */
6419       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6420         break;
6421
6422       /* If the constant is a power of two minus one and the first operand
6423          is a logical right shift, make an extraction.  */
6424       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6425           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6426         {
6427           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6428           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6429                                  0, in_code == COMPARE);
6430         }
6431
6432       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6433       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6434                && subreg_lowpart_p (XEXP (x, 0))
6435                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6436                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6437         {
6438           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6439                                          next_code);
6440           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6441                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6442                                  0, in_code == COMPARE);
6443         }
6444       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6445       else if ((GET_CODE (XEXP (x, 0)) == XOR
6446                 || GET_CODE (XEXP (x, 0)) == IOR)
6447                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6448                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6449                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6450         {
6451           /* Apply the distributive law, and then try to make extractions.  */
6452           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6453                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6454                                              XEXP (x, 1)),
6455                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6456                                              XEXP (x, 1)));
6457           new = make_compound_operation (new, in_code);
6458         }
6459
6460       /* If we are have (and (rotate X C) M) and C is larger than the number
6461          of bits in M, this is an extraction.  */
6462
6463       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6464                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6465                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6466                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6467         {
6468           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6469           new = make_extraction (mode, new,
6470                                  (GET_MODE_BITSIZE (mode)
6471                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6472                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6473         }
6474
6475       /* On machines without logical shifts, if the operand of the AND is
6476          a logical shift and our mask turns off all the propagated sign
6477          bits, we can replace the logical shift with an arithmetic shift.  */
6478       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6479                && !have_insn_for (LSHIFTRT, mode)
6480                && have_insn_for (ASHIFTRT, mode)
6481                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6482                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6483                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6484                && mode_width <= HOST_BITS_PER_WIDE_INT)
6485         {
6486           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6487
6488           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6489           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6490             SUBST (XEXP (x, 0),
6491                    gen_rtx_ASHIFTRT (mode,
6492                                      make_compound_operation
6493                                      (XEXP (XEXP (x, 0), 0), next_code),
6494                                      XEXP (XEXP (x, 0), 1)));
6495         }
6496
6497       /* If the constant is one less than a power of two, this might be
6498          representable by an extraction even if no shift is present.
6499          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6500          we are in a COMPARE.  */
6501       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6502         new = make_extraction (mode,
6503                                make_compound_operation (XEXP (x, 0),
6504                                                         next_code),
6505                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6506
6507       /* If we are in a comparison and this is an AND with a power of two,
6508          convert this into the appropriate bit extract.  */
6509       else if (in_code == COMPARE
6510                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6511         new = make_extraction (mode,
6512                                make_compound_operation (XEXP (x, 0),
6513                                                         next_code),
6514                                i, NULL_RTX, 1, 1, 0, 1);
6515
6516       break;
6517
6518     case LSHIFTRT:
6519       /* If the sign bit is known to be zero, replace this with an
6520          arithmetic shift.  */
6521       if (have_insn_for (ASHIFTRT, mode)
6522           && ! have_insn_for (LSHIFTRT, mode)
6523           && mode_width <= HOST_BITS_PER_WIDE_INT
6524           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6525         {
6526           new = gen_rtx_ASHIFTRT (mode,
6527                                   make_compound_operation (XEXP (x, 0),
6528                                                            next_code),
6529                                   XEXP (x, 1));
6530           break;
6531         }
6532
6533       /* ... fall through ...  */
6534
6535     case ASHIFTRT:
6536       lhs = XEXP (x, 0);
6537       rhs = XEXP (x, 1);
6538
6539       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6540          this is a SIGN_EXTRACT.  */
6541       if (GET_CODE (rhs) == CONST_INT
6542           && GET_CODE (lhs) == ASHIFT
6543           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6544           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6545         {
6546           new = make_compound_operation (XEXP (lhs, 0), next_code);
6547           new = make_extraction (mode, new,
6548                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6549                                  NULL_RTX, mode_width - INTVAL (rhs),
6550                                  code == LSHIFTRT, 0, in_code == COMPARE);
6551           break;
6552         }
6553
6554       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6555          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6556          also do this for some cases of SIGN_EXTRACT, but it doesn't
6557          seem worth the effort; the case checked for occurs on Alpha.  */
6558
6559       if (!OBJECT_P (lhs)
6560           && ! (GET_CODE (lhs) == SUBREG
6561                 && (OBJECT_P (SUBREG_REG (lhs))))
6562           && GET_CODE (rhs) == CONST_INT
6563           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6564           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6565         new = make_extraction (mode, make_compound_operation (new, next_code),
6566                                0, NULL_RTX, mode_width - INTVAL (rhs),
6567                                code == LSHIFTRT, 0, in_code == COMPARE);
6568
6569       break;
6570
6571     case SUBREG:
6572       /* Call ourselves recursively on the inner expression.  If we are
6573          narrowing the object and it has a different RTL code from
6574          what it originally did, do this SUBREG as a force_to_mode.  */
6575
6576       tem = make_compound_operation (SUBREG_REG (x), in_code);
6577
6578       {
6579         rtx simplified;
6580         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6581                                       SUBREG_BYTE (x));
6582
6583         if (simplified)
6584           tem = simplified;
6585
6586         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6587             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6588             && subreg_lowpart_p (x))
6589           {
6590             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6591                                        0);
6592
6593             /* If we have something other than a SUBREG, we might have
6594                done an expansion, so rerun ourselves.  */
6595             if (GET_CODE (newer) != SUBREG)
6596               newer = make_compound_operation (newer, in_code);
6597
6598             return newer;
6599           }
6600
6601         if (simplified)
6602           return tem;
6603       }
6604       break;
6605
6606     default:
6607       break;
6608     }
6609
6610   if (new)
6611     {
6612       x = gen_lowpart (mode, new);
6613       code = GET_CODE (x);
6614     }
6615
6616   /* Now recursively process each operand of this operation.  */
6617   fmt = GET_RTX_FORMAT (code);
6618   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6619     if (fmt[i] == 'e')
6620       {
6621         new = make_compound_operation (XEXP (x, i), next_code);
6622         SUBST (XEXP (x, i), new);
6623       }
6624
6625   /* If this is a commutative operation, the changes to the operands
6626      may have made it noncanonical.  */
6627   if (COMMUTATIVE_ARITH_P (x)
6628       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6629     {
6630       tem = XEXP (x, 0);
6631       SUBST (XEXP (x, 0), XEXP (x, 1));
6632       SUBST (XEXP (x, 1), tem);
6633     }
6634
6635   return x;
6636 }
6637 \f
6638 /* Given M see if it is a value that would select a field of bits
6639    within an item, but not the entire word.  Return -1 if not.
6640    Otherwise, return the starting position of the field, where 0 is the
6641    low-order bit.
6642
6643    *PLEN is set to the length of the field.  */
6644
6645 static int
6646 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6647 {
6648   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6649   int pos = exact_log2 (m & -m);
6650   int len = 0;
6651
6652   if (pos >= 0)
6653     /* Now shift off the low-order zero bits and see if we have a
6654        power of two minus 1.  */
6655     len = exact_log2 ((m >> pos) + 1);
6656
6657   if (len <= 0)
6658     pos = -1;
6659
6660   *plen = len;
6661   return pos;
6662 }
6663 \f
6664 /* If X refers to a register that equals REG in value, replace these
6665    references with REG.  */
6666 static rtx
6667 canon_reg_for_combine (rtx x, rtx reg)
6668 {
6669   rtx op0, op1, op2;
6670   const char *fmt;
6671   int i;
6672   bool copied;
6673
6674   enum rtx_code code = GET_CODE (x);
6675   switch (GET_RTX_CLASS (code))
6676     {
6677     case RTX_UNARY:
6678       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6679       if (op0 != XEXP (x, 0))
6680         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6681                                    GET_MODE (reg));
6682       break;
6683
6684     case RTX_BIN_ARITH:
6685     case RTX_COMM_ARITH:
6686       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6687       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6688       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6689         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6690       break;
6691
6692     case RTX_COMPARE:
6693     case RTX_COMM_COMPARE:
6694       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6695       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6696       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6697         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6698                                         GET_MODE (op0), op0, op1);
6699       break;
6700
6701     case RTX_TERNARY:
6702     case RTX_BITFIELD_OPS:
6703       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6704       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6705       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6706       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6707         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6708                                      GET_MODE (op0), op0, op1, op2);
6709
6710     case RTX_OBJ:
6711       if (REG_P (x))
6712         {
6713           if (rtx_equal_p (get_last_value (reg), x)
6714               || rtx_equal_p (reg, get_last_value (x)))
6715             return reg;
6716           else
6717             break;
6718         }
6719
6720       /* fall through */
6721
6722     default:
6723       fmt = GET_RTX_FORMAT (code);
6724       copied = false;
6725       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6726         if (fmt[i] == 'e')
6727           {
6728             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6729             if (op != XEXP (x, i))
6730               {
6731                 if (!copied)
6732                   {
6733                     copied = true;
6734                     x = copy_rtx (x);
6735                   }
6736                 XEXP (x, i) = op;
6737               }
6738           }
6739         else if (fmt[i] == 'E')
6740           {
6741             int j;
6742             for (j = 0; j < XVECLEN (x, i); j++)
6743               {
6744                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6745                 if (op != XVECEXP (x, i, j))
6746                   {
6747                     if (!copied)
6748                       {
6749                         copied = true;
6750                         x = copy_rtx (x);
6751                       }
6752                     XVECEXP (x, i, j) = op;
6753                   }
6754               }
6755           }
6756
6757       break;
6758     }
6759
6760   return x;
6761 }
6762
6763 /* Return X converted to MODE.  If the value is already truncated to
6764    MODE we can just return a subreg even though in the general case we
6765    would need an explicit truncation.  */
6766
6767 static rtx
6768 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6769 {
6770   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6771       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6772                                 GET_MODE_BITSIZE (GET_MODE (x)))
6773       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6774     return gen_lowpart (mode, x);
6775   else
6776     return gen_rtx_TRUNCATE (mode, x);
6777 }
6778
6779 /* See if X can be simplified knowing that we will only refer to it in
6780    MODE and will only refer to those bits that are nonzero in MASK.
6781    If other bits are being computed or if masking operations are done
6782    that select a superset of the bits in MASK, they can sometimes be
6783    ignored.
6784
6785    Return a possibly simplified expression, but always convert X to
6786    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6787
6788    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6789    are all off in X.  This is used when X will be complemented, by either
6790    NOT, NEG, or XOR.  */
6791
6792 static rtx
6793 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6794                int just_select)
6795 {
6796   enum rtx_code code = GET_CODE (x);
6797   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6798   enum machine_mode op_mode;
6799   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6800   rtx op0, op1, temp;
6801
6802   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6803      code below will do the wrong thing since the mode of such an
6804      expression is VOIDmode.
6805
6806      Also do nothing if X is a CLOBBER; this can happen if X was
6807      the return value from a call to gen_lowpart.  */
6808   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6809     return x;
6810
6811   /* We want to perform the operation is its present mode unless we know
6812      that the operation is valid in MODE, in which case we do the operation
6813      in MODE.  */
6814   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6815               && have_insn_for (code, mode))
6816              ? mode : GET_MODE (x));
6817
6818   /* It is not valid to do a right-shift in a narrower mode
6819      than the one it came in with.  */
6820   if ((code == LSHIFTRT || code == ASHIFTRT)
6821       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6822     op_mode = GET_MODE (x);
6823
6824   /* Truncate MASK to fit OP_MODE.  */
6825   if (op_mode)
6826     mask &= GET_MODE_MASK (op_mode);
6827
6828   /* When we have an arithmetic operation, or a shift whose count we
6829      do not know, we need to assume that all bits up to the highest-order
6830      bit in MASK will be needed.  This is how we form such a mask.  */
6831   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6832     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6833   else
6834     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6835                    - 1);
6836
6837   /* Determine what bits of X are guaranteed to be (non)zero.  */
6838   nonzero = nonzero_bits (x, mode);
6839
6840   /* If none of the bits in X are needed, return a zero.  */
6841   if (! just_select && (nonzero & mask) == 0)
6842     x = const0_rtx;
6843
6844   /* If X is a CONST_INT, return a new one.  Do this here since the
6845      test below will fail.  */
6846   if (GET_CODE (x) == CONST_INT)
6847     {
6848       if (SCALAR_INT_MODE_P (mode))
6849         return gen_int_mode (INTVAL (x) & mask, mode);
6850       else
6851         {
6852           x = GEN_INT (INTVAL (x) & mask);
6853           return gen_lowpart_common (mode, x);
6854         }
6855     }
6856
6857   /* If X is narrower than MODE and we want all the bits in X's mode, just
6858      get X in the proper mode.  */
6859   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6860       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6861     return gen_lowpart (mode, x);
6862
6863   switch (code)
6864     {
6865     case CLOBBER:
6866       /* If X is a (clobber (const_int)), return it since we know we are
6867          generating something that won't match.  */
6868       return x;
6869
6870     case SIGN_EXTEND:
6871     case ZERO_EXTEND:
6872     case ZERO_EXTRACT:
6873     case SIGN_EXTRACT:
6874       x = expand_compound_operation (x);
6875       if (GET_CODE (x) != code)
6876         return force_to_mode (x, mode, mask, next_select);
6877       break;
6878
6879     case SUBREG:
6880       if (subreg_lowpart_p (x)
6881           /* We can ignore the effect of this SUBREG if it narrows the mode or
6882              if the constant masks to zero all the bits the mode doesn't
6883              have.  */
6884           && ((GET_MODE_SIZE (GET_MODE (x))
6885                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6886               || (0 == (mask
6887                         & GET_MODE_MASK (GET_MODE (x))
6888                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6889         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6890       break;
6891
6892     case AND:
6893       /* If this is an AND with a constant, convert it into an AND
6894          whose constant is the AND of that constant with MASK.  If it
6895          remains an AND of MASK, delete it since it is redundant.  */
6896
6897       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6898         {
6899           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6900                                       mask & INTVAL (XEXP (x, 1)));
6901
6902           /* If X is still an AND, see if it is an AND with a mask that
6903              is just some low-order bits.  If so, and it is MASK, we don't
6904              need it.  */
6905
6906           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6907               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6908                   == mask))
6909             x = XEXP (x, 0);
6910
6911           /* If it remains an AND, try making another AND with the bits
6912              in the mode mask that aren't in MASK turned on.  If the
6913              constant in the AND is wide enough, this might make a
6914              cheaper constant.  */
6915
6916           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6917               && GET_MODE_MASK (GET_MODE (x)) != mask
6918               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6919             {
6920               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6921                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6922               int width = GET_MODE_BITSIZE (GET_MODE (x));
6923               rtx y;
6924
6925               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6926                  number, sign extend it.  */
6927               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6928                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6929                 cval |= (HOST_WIDE_INT) -1 << width;
6930
6931               y = simplify_gen_binary (AND, GET_MODE (x),
6932                                        XEXP (x, 0), GEN_INT (cval));
6933               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6934                 x = y;
6935             }
6936
6937           break;
6938         }
6939
6940       goto binop;
6941
6942     case PLUS:
6943       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6944          low-order bits (as in an alignment operation) and FOO is already
6945          aligned to that boundary, mask C1 to that boundary as well.
6946          This may eliminate that PLUS and, later, the AND.  */
6947
6948       {
6949         unsigned int width = GET_MODE_BITSIZE (mode);
6950         unsigned HOST_WIDE_INT smask = mask;
6951
6952         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6953            number, sign extend it.  */
6954
6955         if (width < HOST_BITS_PER_WIDE_INT
6956             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6957           smask |= (HOST_WIDE_INT) -1 << width;
6958
6959         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6960             && exact_log2 (- smask) >= 0
6961             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6962             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6963           return force_to_mode (plus_constant (XEXP (x, 0),
6964                                                (INTVAL (XEXP (x, 1)) & smask)),
6965                                 mode, smask, next_select);
6966       }
6967
6968       /* ... fall through ...  */
6969
6970     case MULT:
6971       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6972          most significant bit in MASK since carries from those bits will
6973          affect the bits we are interested in.  */
6974       mask = fuller_mask;
6975       goto binop;
6976
6977     case MINUS:
6978       /* If X is (minus C Y) where C's least set bit is larger than any bit
6979          in the mask, then we may replace with (neg Y).  */
6980       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6981           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6982                                         & -INTVAL (XEXP (x, 0))))
6983               > mask))
6984         {
6985           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6986                                   GET_MODE (x));
6987           return force_to_mode (x, mode, mask, next_select);
6988         }
6989
6990       /* Similarly, if C contains every bit in the fuller_mask, then we may
6991          replace with (not Y).  */
6992       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6993           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6994               == INTVAL (XEXP (x, 0))))
6995         {
6996           x = simplify_gen_unary (NOT, GET_MODE (x),
6997                                   XEXP (x, 1), GET_MODE (x));
6998           return force_to_mode (x, mode, mask, next_select);
6999         }
7000
7001       mask = fuller_mask;
7002       goto binop;
7003
7004     case IOR:
7005     case XOR:
7006       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7007          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7008          operation which may be a bitfield extraction.  Ensure that the
7009          constant we form is not wider than the mode of X.  */
7010
7011       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7012           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7013           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7014           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7015           && GET_CODE (XEXP (x, 1)) == CONST_INT
7016           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7017                + floor_log2 (INTVAL (XEXP (x, 1))))
7018               < GET_MODE_BITSIZE (GET_MODE (x)))
7019           && (INTVAL (XEXP (x, 1))
7020               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7021         {
7022           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7023                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7024           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7025                                       XEXP (XEXP (x, 0), 0), temp);
7026           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7027                                    XEXP (XEXP (x, 0), 1));
7028           return force_to_mode (x, mode, mask, next_select);
7029         }
7030
7031     binop:
7032       /* For most binary operations, just propagate into the operation and
7033          change the mode if we have an operation of that mode.  */
7034
7035       op0 = gen_lowpart_or_truncate (op_mode,
7036                                      force_to_mode (XEXP (x, 0), mode, mask,
7037                                                     next_select));
7038       op1 = gen_lowpart_or_truncate (op_mode,
7039                                      force_to_mode (XEXP (x, 1), mode, mask,
7040                                         next_select));
7041
7042       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7043         x = simplify_gen_binary (code, op_mode, op0, op1);
7044       break;
7045
7046     case ASHIFT:
7047       /* For left shifts, do the same, but just for the first operand.
7048          However, we cannot do anything with shifts where we cannot
7049          guarantee that the counts are smaller than the size of the mode
7050          because such a count will have a different meaning in a
7051          wider mode.  */
7052
7053       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7054              && INTVAL (XEXP (x, 1)) >= 0
7055              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7056           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7057                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7058                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7059         break;
7060
7061       /* If the shift count is a constant and we can do arithmetic in
7062          the mode of the shift, refine which bits we need.  Otherwise, use the
7063          conservative form of the mask.  */
7064       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7065           && INTVAL (XEXP (x, 1)) >= 0
7066           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7067           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7068         mask >>= INTVAL (XEXP (x, 1));
7069       else
7070         mask = fuller_mask;
7071
7072       op0 = gen_lowpart_or_truncate (op_mode,
7073                                      force_to_mode (XEXP (x, 0), op_mode,
7074                                                     mask, next_select));
7075
7076       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7077         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7078       break;
7079
7080     case LSHIFTRT:
7081       /* Here we can only do something if the shift count is a constant,
7082          this shift constant is valid for the host, and we can do arithmetic
7083          in OP_MODE.  */
7084
7085       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7086           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7087           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7088         {
7089           rtx inner = XEXP (x, 0);
7090           unsigned HOST_WIDE_INT inner_mask;
7091
7092           /* Select the mask of the bits we need for the shift operand.  */
7093           inner_mask = mask << INTVAL (XEXP (x, 1));
7094
7095           /* We can only change the mode of the shift if we can do arithmetic
7096              in the mode of the shift and INNER_MASK is no wider than the
7097              width of X's mode.  */
7098           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7099             op_mode = GET_MODE (x);
7100
7101           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7102
7103           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7104             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7105         }
7106
7107       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7108          shift and AND produces only copies of the sign bit (C2 is one less
7109          than a power of two), we can do this with just a shift.  */
7110
7111       if (GET_CODE (x) == LSHIFTRT
7112           && GET_CODE (XEXP (x, 1)) == CONST_INT
7113           /* The shift puts one of the sign bit copies in the least significant
7114              bit.  */
7115           && ((INTVAL (XEXP (x, 1))
7116                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7117               >= GET_MODE_BITSIZE (GET_MODE (x)))
7118           && exact_log2 (mask + 1) >= 0
7119           /* Number of bits left after the shift must be more than the mask
7120              needs.  */
7121           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7122               <= GET_MODE_BITSIZE (GET_MODE (x)))
7123           /* Must be more sign bit copies than the mask needs.  */
7124           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7125               >= exact_log2 (mask + 1)))
7126         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7127                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7128                                           - exact_log2 (mask + 1)));
7129
7130       goto shiftrt;
7131
7132     case ASHIFTRT:
7133       /* If we are just looking for the sign bit, we don't need this shift at
7134          all, even if it has a variable count.  */
7135       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7136           && (mask == ((unsigned HOST_WIDE_INT) 1
7137                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7138         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7139
7140       /* If this is a shift by a constant, get a mask that contains those bits
7141          that are not copies of the sign bit.  We then have two cases:  If
7142          MASK only includes those bits, this can be a logical shift, which may
7143          allow simplifications.  If MASK is a single-bit field not within
7144          those bits, we are requesting a copy of the sign bit and hence can
7145          shift the sign bit to the appropriate location.  */
7146
7147       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7148           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7149         {
7150           int i;
7151
7152           /* If the considered data is wider than HOST_WIDE_INT, we can't
7153              represent a mask for all its bits in a single scalar.
7154              But we only care about the lower bits, so calculate these.  */
7155
7156           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7157             {
7158               nonzero = ~(HOST_WIDE_INT) 0;
7159
7160               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7161                  is the number of bits a full-width mask would have set.
7162                  We need only shift if these are fewer than nonzero can
7163                  hold.  If not, we must keep all bits set in nonzero.  */
7164
7165               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7166                   < HOST_BITS_PER_WIDE_INT)
7167                 nonzero >>= INTVAL (XEXP (x, 1))
7168                             + HOST_BITS_PER_WIDE_INT
7169                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7170             }
7171           else
7172             {
7173               nonzero = GET_MODE_MASK (GET_MODE (x));
7174               nonzero >>= INTVAL (XEXP (x, 1));
7175             }
7176
7177           if ((mask & ~nonzero) == 0)
7178             {
7179               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7180                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7181               if (GET_CODE (x) != ASHIFTRT)
7182                 return force_to_mode (x, mode, mask, next_select);
7183             }
7184
7185           else if ((i = exact_log2 (mask)) >= 0)
7186             {
7187               x = simplify_shift_const
7188                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7189                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7190
7191               if (GET_CODE (x) != ASHIFTRT)
7192                 return force_to_mode (x, mode, mask, next_select);
7193             }
7194         }
7195
7196       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7197          even if the shift count isn't a constant.  */
7198       if (mask == 1)
7199         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7200                                  XEXP (x, 0), XEXP (x, 1));
7201
7202     shiftrt:
7203
7204       /* If this is a zero- or sign-extension operation that just affects bits
7205          we don't care about, remove it.  Be sure the call above returned
7206          something that is still a shift.  */
7207
7208       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7209           && GET_CODE (XEXP (x, 1)) == CONST_INT
7210           && INTVAL (XEXP (x, 1)) >= 0
7211           && (INTVAL (XEXP (x, 1))
7212               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7213           && GET_CODE (XEXP (x, 0)) == ASHIFT
7214           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7215         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7216                               next_select);
7217
7218       break;
7219
7220     case ROTATE:
7221     case ROTATERT:
7222       /* If the shift count is constant and we can do computations
7223          in the mode of X, compute where the bits we care about are.
7224          Otherwise, we can't do anything.  Don't change the mode of
7225          the shift or propagate MODE into the shift, though.  */
7226       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7227           && INTVAL (XEXP (x, 1)) >= 0)
7228         {
7229           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7230                                             GET_MODE (x), GEN_INT (mask),
7231                                             XEXP (x, 1));
7232           if (temp && GET_CODE (temp) == CONST_INT)
7233             SUBST (XEXP (x, 0),
7234                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7235                                   INTVAL (temp), next_select));
7236         }
7237       break;
7238
7239     case NEG:
7240       /* If we just want the low-order bit, the NEG isn't needed since it
7241          won't change the low-order bit.  */
7242       if (mask == 1)
7243         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7244
7245       /* We need any bits less significant than the most significant bit in
7246          MASK since carries from those bits will affect the bits we are
7247          interested in.  */
7248       mask = fuller_mask;
7249       goto unop;
7250
7251     case NOT:
7252       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7253          same as the XOR case above.  Ensure that the constant we form is not
7254          wider than the mode of X.  */
7255
7256       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7257           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7258           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7259           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7260               < GET_MODE_BITSIZE (GET_MODE (x)))
7261           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7262         {
7263           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7264                                GET_MODE (x));
7265           temp = simplify_gen_binary (XOR, GET_MODE (x),
7266                                       XEXP (XEXP (x, 0), 0), temp);
7267           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7268                                    temp, XEXP (XEXP (x, 0), 1));
7269
7270           return force_to_mode (x, mode, mask, next_select);
7271         }
7272
7273       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7274          use the full mask inside the NOT.  */
7275       mask = fuller_mask;
7276
7277     unop:
7278       op0 = gen_lowpart_or_truncate (op_mode,
7279                                      force_to_mode (XEXP (x, 0), mode, mask,
7280                                                     next_select));
7281       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7282         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7283       break;
7284
7285     case NE:
7286       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7287          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7288          which is equal to STORE_FLAG_VALUE.  */
7289       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7290           && GET_MODE (XEXP (x, 0)) == mode
7291           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7292           && (nonzero_bits (XEXP (x, 0), mode)
7293               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7294         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7295
7296       break;
7297
7298     case IF_THEN_ELSE:
7299       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7300          written in a narrower mode.  We play it safe and do not do so.  */
7301
7302       SUBST (XEXP (x, 1),
7303              gen_lowpart_or_truncate (GET_MODE (x),
7304                                       force_to_mode (XEXP (x, 1), mode,
7305                                                      mask, next_select)));
7306       SUBST (XEXP (x, 2),
7307              gen_lowpart_or_truncate (GET_MODE (x),
7308                                       force_to_mode (XEXP (x, 2), mode,
7309                                                      mask, next_select)));
7310       break;
7311
7312     default:
7313       break;
7314     }
7315
7316   /* Ensure we return a value of the proper mode.  */
7317   return gen_lowpart_or_truncate (mode, x);
7318 }
7319 \f
7320 /* Return nonzero if X is an expression that has one of two values depending on
7321    whether some other value is zero or nonzero.  In that case, we return the
7322    value that is being tested, *PTRUE is set to the value if the rtx being
7323    returned has a nonzero value, and *PFALSE is set to the other alternative.
7324
7325    If we return zero, we set *PTRUE and *PFALSE to X.  */
7326
7327 static rtx
7328 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7329 {
7330   enum machine_mode mode = GET_MODE (x);
7331   enum rtx_code code = GET_CODE (x);
7332   rtx cond0, cond1, true0, true1, false0, false1;
7333   unsigned HOST_WIDE_INT nz;
7334
7335   /* If we are comparing a value against zero, we are done.  */
7336   if ((code == NE || code == EQ)
7337       && XEXP (x, 1) == const0_rtx)
7338     {
7339       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7340       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7341       return XEXP (x, 0);
7342     }
7343
7344   /* If this is a unary operation whose operand has one of two values, apply
7345      our opcode to compute those values.  */
7346   else if (UNARY_P (x)
7347            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7348     {
7349       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7350       *pfalse = simplify_gen_unary (code, mode, false0,
7351                                     GET_MODE (XEXP (x, 0)));
7352       return cond0;
7353     }
7354
7355   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7356      make can't possibly match and would suppress other optimizations.  */
7357   else if (code == COMPARE)
7358     ;
7359
7360   /* If this is a binary operation, see if either side has only one of two
7361      values.  If either one does or if both do and they are conditional on
7362      the same value, compute the new true and false values.  */
7363   else if (BINARY_P (x))
7364     {
7365       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7366       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7367
7368       if ((cond0 != 0 || cond1 != 0)
7369           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7370         {
7371           /* If if_then_else_cond returned zero, then true/false are the
7372              same rtl.  We must copy one of them to prevent invalid rtl
7373              sharing.  */
7374           if (cond0 == 0)
7375             true0 = copy_rtx (true0);
7376           else if (cond1 == 0)
7377             true1 = copy_rtx (true1);
7378
7379           if (COMPARISON_P (x))
7380             {
7381               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7382                                                 true0, true1);
7383               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7384                                                  false0, false1);
7385              }
7386           else
7387             {
7388               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7389               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7390             }
7391
7392           return cond0 ? cond0 : cond1;
7393         }
7394
7395       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7396          operands is zero when the other is nonzero, and vice-versa,
7397          and STORE_FLAG_VALUE is 1 or -1.  */
7398
7399       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7400           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7401               || code == UMAX)
7402           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7403         {
7404           rtx op0 = XEXP (XEXP (x, 0), 1);
7405           rtx op1 = XEXP (XEXP (x, 1), 1);
7406
7407           cond0 = XEXP (XEXP (x, 0), 0);
7408           cond1 = XEXP (XEXP (x, 1), 0);
7409
7410           if (COMPARISON_P (cond0)
7411               && COMPARISON_P (cond1)
7412               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7413                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7414                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7415                   || ((swap_condition (GET_CODE (cond0))
7416                        == reversed_comparison_code (cond1, NULL))
7417                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7418                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7419               && ! side_effects_p (x))
7420             {
7421               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7422               *pfalse = simplify_gen_binary (MULT, mode,
7423                                              (code == MINUS
7424                                               ? simplify_gen_unary (NEG, mode,
7425                                                                     op1, mode)
7426                                               : op1),
7427                                               const_true_rtx);
7428               return cond0;
7429             }
7430         }
7431
7432       /* Similarly for MULT, AND and UMIN, except that for these the result
7433          is always zero.  */
7434       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7435           && (code == MULT || code == AND || code == UMIN)
7436           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7437         {
7438           cond0 = XEXP (XEXP (x, 0), 0);
7439           cond1 = XEXP (XEXP (x, 1), 0);
7440
7441           if (COMPARISON_P (cond0)
7442               && COMPARISON_P (cond1)
7443               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7444                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7445                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7446                   || ((swap_condition (GET_CODE (cond0))
7447                        == reversed_comparison_code (cond1, NULL))
7448                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7449                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7450               && ! side_effects_p (x))
7451             {
7452               *ptrue = *pfalse = const0_rtx;
7453               return cond0;
7454             }
7455         }
7456     }
7457
7458   else if (code == IF_THEN_ELSE)
7459     {
7460       /* If we have IF_THEN_ELSE already, extract the condition and
7461          canonicalize it if it is NE or EQ.  */
7462       cond0 = XEXP (x, 0);
7463       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7464       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7465         return XEXP (cond0, 0);
7466       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7467         {
7468           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7469           return XEXP (cond0, 0);
7470         }
7471       else
7472         return cond0;
7473     }
7474
7475   /* If X is a SUBREG, we can narrow both the true and false values
7476      if the inner expression, if there is a condition.  */
7477   else if (code == SUBREG
7478            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7479                                                &true0, &false0)))
7480     {
7481       true0 = simplify_gen_subreg (mode, true0,
7482                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7483       false0 = simplify_gen_subreg (mode, false0,
7484                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7485       if (true0 && false0)
7486         {
7487           *ptrue = true0;
7488           *pfalse = false0;
7489           return cond0;
7490         }
7491     }
7492
7493   /* If X is a constant, this isn't special and will cause confusions
7494      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7495   else if (CONSTANT_P (x)
7496            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7497     ;
7498
7499   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7500      will be least confusing to the rest of the compiler.  */
7501   else if (mode == BImode)
7502     {
7503       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7504       return x;
7505     }
7506
7507   /* If X is known to be either 0 or -1, those are the true and
7508      false values when testing X.  */
7509   else if (x == constm1_rtx || x == const0_rtx
7510            || (mode != VOIDmode
7511                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7512     {
7513       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7514       return x;
7515     }
7516
7517   /* Likewise for 0 or a single bit.  */
7518   else if (SCALAR_INT_MODE_P (mode)
7519            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7520            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7521     {
7522       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7523       return x;
7524     }
7525
7526   /* Otherwise fail; show no condition with true and false values the same.  */
7527   *ptrue = *pfalse = x;
7528   return 0;
7529 }
7530 \f
7531 /* Return the value of expression X given the fact that condition COND
7532    is known to be true when applied to REG as its first operand and VAL
7533    as its second.  X is known to not be shared and so can be modified in
7534    place.
7535
7536    We only handle the simplest cases, and specifically those cases that
7537    arise with IF_THEN_ELSE expressions.  */
7538
7539 static rtx
7540 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7541 {
7542   enum rtx_code code = GET_CODE (x);
7543   rtx temp;
7544   const char *fmt;
7545   int i, j;
7546
7547   if (side_effects_p (x))
7548     return x;
7549
7550   /* If either operand of the condition is a floating point value,
7551      then we have to avoid collapsing an EQ comparison.  */
7552   if (cond == EQ
7553       && rtx_equal_p (x, reg)
7554       && ! FLOAT_MODE_P (GET_MODE (x))
7555       && ! FLOAT_MODE_P (GET_MODE (val)))
7556     return val;
7557
7558   if (cond == UNEQ && rtx_equal_p (x, reg))
7559     return val;
7560
7561   /* If X is (abs REG) and we know something about REG's relationship
7562      with zero, we may be able to simplify this.  */
7563
7564   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7565     switch (cond)
7566       {
7567       case GE:  case GT:  case EQ:
7568         return XEXP (x, 0);
7569       case LT:  case LE:
7570         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7571                                    XEXP (x, 0),
7572                                    GET_MODE (XEXP (x, 0)));
7573       default:
7574         break;
7575       }
7576
7577   /* The only other cases we handle are MIN, MAX, and comparisons if the
7578      operands are the same as REG and VAL.  */
7579
7580   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7581     {
7582       if (rtx_equal_p (XEXP (x, 0), val))
7583         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7584
7585       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7586         {
7587           if (COMPARISON_P (x))
7588             {
7589               if (comparison_dominates_p (cond, code))
7590                 return const_true_rtx;
7591
7592               code = reversed_comparison_code (x, NULL);
7593               if (code != UNKNOWN
7594                   && comparison_dominates_p (cond, code))
7595                 return const0_rtx;
7596               else
7597                 return x;
7598             }
7599           else if (code == SMAX || code == SMIN
7600                    || code == UMIN || code == UMAX)
7601             {
7602               int unsignedp = (code == UMIN || code == UMAX);
7603
7604               /* Do not reverse the condition when it is NE or EQ.
7605                  This is because we cannot conclude anything about
7606                  the value of 'SMAX (x, y)' when x is not equal to y,
7607                  but we can when x equals y.  */
7608               if ((code == SMAX || code == UMAX)
7609                   && ! (cond == EQ || cond == NE))
7610                 cond = reverse_condition (cond);
7611
7612               switch (cond)
7613                 {
7614                 case GE:   case GT:
7615                   return unsignedp ? x : XEXP (x, 1);
7616                 case LE:   case LT:
7617                   return unsignedp ? x : XEXP (x, 0);
7618                 case GEU:  case GTU:
7619                   return unsignedp ? XEXP (x, 1) : x;
7620                 case LEU:  case LTU:
7621                   return unsignedp ? XEXP (x, 0) : x;
7622                 default:
7623                   break;
7624                 }
7625             }
7626         }
7627     }
7628   else if (code == SUBREG)
7629     {
7630       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7631       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7632
7633       if (SUBREG_REG (x) != r)
7634         {
7635           /* We must simplify subreg here, before we lose track of the
7636              original inner_mode.  */
7637           new = simplify_subreg (GET_MODE (x), r,
7638                                  inner_mode, SUBREG_BYTE (x));
7639           if (new)
7640             return new;
7641           else
7642             SUBST (SUBREG_REG (x), r);
7643         }
7644
7645       return x;
7646     }
7647   /* We don't have to handle SIGN_EXTEND here, because even in the
7648      case of replacing something with a modeless CONST_INT, a
7649      CONST_INT is already (supposed to be) a valid sign extension for
7650      its narrower mode, which implies it's already properly
7651      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7652      story is different.  */
7653   else if (code == ZERO_EXTEND)
7654     {
7655       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7656       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7657
7658       if (XEXP (x, 0) != r)
7659         {
7660           /* We must simplify the zero_extend here, before we lose
7661              track of the original inner_mode.  */
7662           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7663                                           r, inner_mode);
7664           if (new)
7665             return new;
7666           else
7667             SUBST (XEXP (x, 0), r);
7668         }
7669
7670       return x;
7671     }
7672
7673   fmt = GET_RTX_FORMAT (code);
7674   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7675     {
7676       if (fmt[i] == 'e')
7677         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7678       else if (fmt[i] == 'E')
7679         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7680           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7681                                                 cond, reg, val));
7682     }
7683
7684   return x;
7685 }
7686 \f
7687 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7688    assignment as a field assignment.  */
7689
7690 static int
7691 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7692 {
7693   if (x == y || rtx_equal_p (x, y))
7694     return 1;
7695
7696   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7697     return 0;
7698
7699   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7700      Note that all SUBREGs of MEM are paradoxical; otherwise they
7701      would have been rewritten.  */
7702   if (MEM_P (x) && GET_CODE (y) == SUBREG
7703       && MEM_P (SUBREG_REG (y))
7704       && rtx_equal_p (SUBREG_REG (y),
7705                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7706     return 1;
7707
7708   if (MEM_P (y) && GET_CODE (x) == SUBREG
7709       && MEM_P (SUBREG_REG (x))
7710       && rtx_equal_p (SUBREG_REG (x),
7711                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7712     return 1;
7713
7714   /* We used to see if get_last_value of X and Y were the same but that's
7715      not correct.  In one direction, we'll cause the assignment to have
7716      the wrong destination and in the case, we'll import a register into this
7717      insn that might have already have been dead.   So fail if none of the
7718      above cases are true.  */
7719   return 0;
7720 }
7721 \f
7722 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7723    Return that assignment if so.
7724
7725    We only handle the most common cases.  */
7726
7727 static rtx
7728 make_field_assignment (rtx x)
7729 {
7730   rtx dest = SET_DEST (x);
7731   rtx src = SET_SRC (x);
7732   rtx assign;
7733   rtx rhs, lhs;
7734   HOST_WIDE_INT c1;
7735   HOST_WIDE_INT pos;
7736   unsigned HOST_WIDE_INT len;
7737   rtx other;
7738   enum machine_mode mode;
7739
7740   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7741      a clear of a one-bit field.  We will have changed it to
7742      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7743      for a SUBREG.  */
7744
7745   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7746       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7747       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7748       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7749     {
7750       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7751                                 1, 1, 1, 0);
7752       if (assign != 0)
7753         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7754       return x;
7755     }
7756
7757   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7758       && subreg_lowpart_p (XEXP (src, 0))
7759       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7760           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7761       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7762       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7763       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7764       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7765     {
7766       assign = make_extraction (VOIDmode, dest, 0,
7767                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7768                                 1, 1, 1, 0);
7769       if (assign != 0)
7770         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7771       return x;
7772     }
7773
7774   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7775      one-bit field.  */
7776   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7777       && XEXP (XEXP (src, 0), 0) == const1_rtx
7778       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7779     {
7780       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7781                                 1, 1, 1, 0);
7782       if (assign != 0)
7783         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7784       return x;
7785     }
7786
7787   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7788      SRC is an AND with all bits of that field set, then we can discard
7789      the AND.  */
7790   if (GET_CODE (dest) == ZERO_EXTRACT
7791       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7792       && GET_CODE (src) == AND
7793       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7794     {
7795       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7796       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7797       unsigned HOST_WIDE_INT ze_mask;
7798
7799       if (width >= HOST_BITS_PER_WIDE_INT)
7800         ze_mask = -1;
7801       else
7802         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7803
7804       /* Complete overlap.  We can remove the source AND.  */
7805       if ((and_mask & ze_mask) == ze_mask)
7806         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7807
7808       /* Partial overlap.  We can reduce the source AND.  */
7809       if ((and_mask & ze_mask) != and_mask)
7810         {
7811           mode = GET_MODE (src);
7812           src = gen_rtx_AND (mode, XEXP (src, 0),
7813                              gen_int_mode (and_mask & ze_mask, mode));
7814           return gen_rtx_SET (VOIDmode, dest, src);
7815         }
7816     }
7817
7818   /* The other case we handle is assignments into a constant-position
7819      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7820      a mask that has all one bits except for a group of zero bits and
7821      OTHER is known to have zeros where C1 has ones, this is such an
7822      assignment.  Compute the position and length from C1.  Shift OTHER
7823      to the appropriate position, force it to the required mode, and
7824      make the extraction.  Check for the AND in both operands.  */
7825
7826   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7827     return x;
7828
7829   rhs = expand_compound_operation (XEXP (src, 0));
7830   lhs = expand_compound_operation (XEXP (src, 1));
7831
7832   if (GET_CODE (rhs) == AND
7833       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7834       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7835     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7836   else if (GET_CODE (lhs) == AND
7837            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7838            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7839     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7840   else
7841     return x;
7842
7843   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7844   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7845       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7846       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7847     return x;
7848
7849   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7850   if (assign == 0)
7851     return x;
7852
7853   /* The mode to use for the source is the mode of the assignment, or of
7854      what is inside a possible STRICT_LOW_PART.  */
7855   mode = (GET_CODE (assign) == STRICT_LOW_PART
7856           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7857
7858   /* Shift OTHER right POS places and make it the source, restricting it
7859      to the proper length and mode.  */
7860
7861   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7862                                                      GET_MODE (src),
7863                                                      other, pos),
7864                                dest);
7865   src = force_to_mode (src, mode,
7866                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7867                        ? ~(unsigned HOST_WIDE_INT) 0
7868                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7869                        0);
7870
7871   /* If SRC is masked by an AND that does not make a difference in
7872      the value being stored, strip it.  */
7873   if (GET_CODE (assign) == ZERO_EXTRACT
7874       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7875       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7876       && GET_CODE (src) == AND
7877       && GET_CODE (XEXP (src, 1)) == CONST_INT
7878       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7879           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7880     src = XEXP (src, 0);
7881
7882   return gen_rtx_SET (VOIDmode, assign, src);
7883 }
7884 \f
7885 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7886    if so.  */
7887
7888 static rtx
7889 apply_distributive_law (rtx x)
7890 {
7891   enum rtx_code code = GET_CODE (x);
7892   enum rtx_code inner_code;
7893   rtx lhs, rhs, other;
7894   rtx tem;
7895
7896   /* Distributivity is not true for floating point as it can change the
7897      value.  So we don't do it unless -funsafe-math-optimizations.  */
7898   if (FLOAT_MODE_P (GET_MODE (x))
7899       && ! flag_unsafe_math_optimizations)
7900     return x;
7901
7902   /* The outer operation can only be one of the following:  */
7903   if (code != IOR && code != AND && code != XOR
7904       && code != PLUS && code != MINUS)
7905     return x;
7906
7907   lhs = XEXP (x, 0);
7908   rhs = XEXP (x, 1);
7909
7910   /* If either operand is a primitive we can't do anything, so get out
7911      fast.  */
7912   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7913     return x;
7914
7915   lhs = expand_compound_operation (lhs);
7916   rhs = expand_compound_operation (rhs);
7917   inner_code = GET_CODE (lhs);
7918   if (inner_code != GET_CODE (rhs))
7919     return x;
7920
7921   /* See if the inner and outer operations distribute.  */
7922   switch (inner_code)
7923     {
7924     case LSHIFTRT:
7925     case ASHIFTRT:
7926     case AND:
7927     case IOR:
7928       /* These all distribute except over PLUS.  */
7929       if (code == PLUS || code == MINUS)
7930         return x;
7931       break;
7932
7933     case MULT:
7934       if (code != PLUS && code != MINUS)
7935         return x;
7936       break;
7937
7938     case ASHIFT:
7939       /* This is also a multiply, so it distributes over everything.  */
7940       break;
7941
7942     case SUBREG:
7943       /* Non-paradoxical SUBREGs distributes over all operations,
7944          provided the inner modes and byte offsets are the same, this
7945          is an extraction of a low-order part, we don't convert an fp
7946          operation to int or vice versa, this is not a vector mode,
7947          and we would not be converting a single-word operation into a
7948          multi-word operation.  The latter test is not required, but
7949          it prevents generating unneeded multi-word operations.  Some
7950          of the previous tests are redundant given the latter test,
7951          but are retained because they are required for correctness.
7952
7953          We produce the result slightly differently in this case.  */
7954
7955       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7956           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7957           || ! subreg_lowpart_p (lhs)
7958           || (GET_MODE_CLASS (GET_MODE (lhs))
7959               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7960           || (GET_MODE_SIZE (GET_MODE (lhs))
7961               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7962           || VECTOR_MODE_P (GET_MODE (lhs))
7963           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7964           /* Result might need to be truncated.  Don't change mode if
7965              explicit truncation is needed.  */
7966           || !TRULY_NOOP_TRUNCATION
7967                (GET_MODE_BITSIZE (GET_MODE (x)),
7968                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7969         return x;
7970
7971       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7972                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7973       return gen_lowpart (GET_MODE (x), tem);
7974
7975     default:
7976       return x;
7977     }
7978
7979   /* Set LHS and RHS to the inner operands (A and B in the example
7980      above) and set OTHER to the common operand (C in the example).
7981      There is only one way to do this unless the inner operation is
7982      commutative.  */
7983   if (COMMUTATIVE_ARITH_P (lhs)
7984       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7985     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7986   else if (COMMUTATIVE_ARITH_P (lhs)
7987            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7988     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7989   else if (COMMUTATIVE_ARITH_P (lhs)
7990            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7991     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7992   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7993     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7994   else
7995     return x;
7996
7997   /* Form the new inner operation, seeing if it simplifies first.  */
7998   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
7999
8000   /* There is one exception to the general way of distributing:
8001      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8002   if (code == XOR && inner_code == IOR)
8003     {
8004       inner_code = AND;
8005       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8006     }
8007
8008   /* We may be able to continuing distributing the result, so call
8009      ourselves recursively on the inner operation before forming the
8010      outer operation, which we return.  */
8011   return simplify_gen_binary (inner_code, GET_MODE (x),
8012                               apply_distributive_law (tem), other);
8013 }
8014
8015 /* See if X is of the form (* (+ A B) C), and if so convert to
8016    (+ (* A C) (* B C)) and try to simplify.
8017
8018    Most of the time, this results in no change.  However, if some of
8019    the operands are the same or inverses of each other, simplifications
8020    will result.
8021
8022    For example, (and (ior A B) (not B)) can occur as the result of
8023    expanding a bit field assignment.  When we apply the distributive
8024    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8025    which then simplifies to (and (A (not B))).
8026
8027    Note that no checks happen on the validity of applying the inverse
8028    distributive law.  This is pointless since we can do it in the
8029    few places where this routine is called.
8030
8031    N is the index of the term that is decomposed (the arithmetic operation,
8032    i.e. (+ A B) in the first example above).  !N is the index of the term that
8033    is distributed, i.e. of C in the first example above.  */
8034 static rtx
8035 distribute_and_simplify_rtx (rtx x, int n)
8036 {
8037   enum machine_mode mode;
8038   enum rtx_code outer_code, inner_code;
8039   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8040
8041   decomposed = XEXP (x, n);
8042   if (!ARITHMETIC_P (decomposed))
8043     return NULL_RTX;
8044
8045   mode = GET_MODE (x);
8046   outer_code = GET_CODE (x);
8047   distributed = XEXP (x, !n);
8048
8049   inner_code = GET_CODE (decomposed);
8050   inner_op0 = XEXP (decomposed, 0);
8051   inner_op1 = XEXP (decomposed, 1);
8052
8053   /* Special case (and (xor B C) (not A)), which is equivalent to
8054      (xor (ior A B) (ior A C))  */
8055   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8056     {
8057       distributed = XEXP (distributed, 0);
8058       outer_code = IOR;
8059     }
8060
8061   if (n == 0)
8062     {
8063       /* Distribute the second term.  */
8064       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8065       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8066     }
8067   else
8068     {
8069       /* Distribute the first term.  */
8070       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8071       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8072     }
8073
8074   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8075                                                      new_op0, new_op1));
8076   if (GET_CODE (tmp) != outer_code
8077       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8078     return tmp;
8079
8080   return NULL_RTX;
8081 }
8082 \f
8083 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8084    in MODE.  Return an equivalent form, if different from (and VAROP
8085    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8086
8087 static rtx
8088 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8089                           unsigned HOST_WIDE_INT constop)
8090 {
8091   unsigned HOST_WIDE_INT nonzero;
8092   unsigned HOST_WIDE_INT orig_constop;
8093   rtx orig_varop;
8094   int i;
8095
8096   orig_varop = varop;
8097   orig_constop = constop;
8098   if (GET_CODE (varop) == CLOBBER)
8099     return NULL_RTX;
8100
8101   /* Simplify VAROP knowing that we will be only looking at some of the
8102      bits in it.
8103
8104      Note by passing in CONSTOP, we guarantee that the bits not set in
8105      CONSTOP are not significant and will never be examined.  We must
8106      ensure that is the case by explicitly masking out those bits
8107      before returning.  */
8108   varop = force_to_mode (varop, mode, constop, 0);
8109
8110   /* If VAROP is a CLOBBER, we will fail so return it.  */
8111   if (GET_CODE (varop) == CLOBBER)
8112     return varop;
8113
8114   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8115      to VAROP and return the new constant.  */
8116   if (GET_CODE (varop) == CONST_INT)
8117     return gen_int_mode (INTVAL (varop) & constop, mode);
8118
8119   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8120      a call to nonzero_bits, here we don't care about bits outside
8121      MODE.  */
8122
8123   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8124
8125   /* Turn off all bits in the constant that are known to already be zero.
8126      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8127      which is tested below.  */
8128
8129   constop &= nonzero;
8130
8131   /* If we don't have any bits left, return zero.  */
8132   if (constop == 0)
8133     return const0_rtx;
8134
8135   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8136      a power of two, we can replace this with an ASHIFT.  */
8137   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8138       && (i = exact_log2 (constop)) >= 0)
8139     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8140
8141   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8142      or XOR, then try to apply the distributive law.  This may eliminate
8143      operations if either branch can be simplified because of the AND.
8144      It may also make some cases more complex, but those cases probably
8145      won't match a pattern either with or without this.  */
8146
8147   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8148     return
8149       gen_lowpart
8150         (mode,
8151          apply_distributive_law
8152          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8153                                simplify_and_const_int (NULL_RTX,
8154                                                        GET_MODE (varop),
8155                                                        XEXP (varop, 0),
8156                                                        constop),
8157                                simplify_and_const_int (NULL_RTX,
8158                                                        GET_MODE (varop),
8159                                                        XEXP (varop, 1),
8160                                                        constop))));
8161
8162   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8163      the AND and see if one of the operands simplifies to zero.  If so, we
8164      may eliminate it.  */
8165
8166   if (GET_CODE (varop) == PLUS
8167       && exact_log2 (constop + 1) >= 0)
8168     {
8169       rtx o0, o1;
8170
8171       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8172       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8173       if (o0 == const0_rtx)
8174         return o1;
8175       if (o1 == const0_rtx)
8176         return o0;
8177     }
8178
8179   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8180   varop = gen_lowpart (mode, varop);
8181   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8182     return NULL_RTX;
8183
8184   /* If we are only masking insignificant bits, return VAROP.  */
8185   if (constop == nonzero)
8186     return varop;
8187
8188   if (varop == orig_varop && constop == orig_constop)
8189     return NULL_RTX;
8190
8191   /* Otherwise, return an AND.  */
8192   constop = trunc_int_for_mode (constop, mode);
8193   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8194 }
8195
8196
8197 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8198    in MODE.
8199
8200    Return an equivalent form, if different from X.  Otherwise, return X.  If
8201    X is zero, we are to always construct the equivalent form.  */
8202
8203 static rtx
8204 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8205                         unsigned HOST_WIDE_INT constop)
8206 {
8207   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8208   if (tem)
8209     return tem;
8210
8211   if (!x)
8212     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8213   if (GET_MODE (x) != mode)
8214     x = gen_lowpart (mode, x);
8215   return x;
8216 }
8217 \f
8218 /* Given a REG, X, compute which bits in X can be nonzero.
8219    We don't care about bits outside of those defined in MODE.
8220
8221    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8222    a shift, AND, or zero_extract, we can do better.  */
8223
8224 static rtx
8225 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8226                               rtx known_x ATTRIBUTE_UNUSED,
8227                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8228                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8229                               unsigned HOST_WIDE_INT *nonzero)
8230 {
8231   rtx tem;
8232
8233   /* If X is a register whose nonzero bits value is current, use it.
8234      Otherwise, if X is a register whose value we can find, use that
8235      value.  Otherwise, use the previously-computed global nonzero bits
8236      for this register.  */
8237
8238   if (reg_stat[REGNO (x)].last_set_value != 0
8239       && (reg_stat[REGNO (x)].last_set_mode == mode
8240           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8241               && GET_MODE_CLASS (mode) == MODE_INT))
8242       && (reg_stat[REGNO (x)].last_set_label == label_tick
8243           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8244               && REG_N_SETS (REGNO (x)) == 1
8245               && ! REGNO_REG_SET_P
8246                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8247                   REGNO (x))))
8248       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8249     {
8250       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8251       return NULL;
8252     }
8253
8254   tem = get_last_value (x);
8255
8256   if (tem)
8257     {
8258 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8259       /* If X is narrower than MODE and TEM is a non-negative
8260          constant that would appear negative in the mode of X,
8261          sign-extend it for use in reg_nonzero_bits because some
8262          machines (maybe most) will actually do the sign-extension
8263          and this is the conservative approach.
8264
8265          ??? For 2.5, try to tighten up the MD files in this regard
8266          instead of this kludge.  */
8267
8268       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8269           && GET_CODE (tem) == CONST_INT
8270           && INTVAL (tem) > 0
8271           && 0 != (INTVAL (tem)
8272                    & ((HOST_WIDE_INT) 1
8273                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8274         tem = GEN_INT (INTVAL (tem)
8275                        | ((HOST_WIDE_INT) (-1)
8276                           << GET_MODE_BITSIZE (GET_MODE (x))));
8277 #endif
8278       return tem;
8279     }
8280   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8281     {
8282       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8283
8284       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8285         /* We don't know anything about the upper bits.  */
8286         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8287       *nonzero &= mask;
8288     }
8289
8290   return NULL;
8291 }
8292
8293 /* Return the number of bits at the high-order end of X that are known to
8294    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8295    VOIDmode, X will be used in its own mode.  The returned value  will always
8296    be between 1 and the number of bits in MODE.  */
8297
8298 static rtx
8299 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8300                                      rtx known_x ATTRIBUTE_UNUSED,
8301                                      enum machine_mode known_mode
8302                                      ATTRIBUTE_UNUSED,
8303                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8304                                      unsigned int *result)
8305 {
8306   rtx tem;
8307
8308   if (reg_stat[REGNO (x)].last_set_value != 0
8309       && reg_stat[REGNO (x)].last_set_mode == mode
8310       && (reg_stat[REGNO (x)].last_set_label == label_tick
8311           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8312               && REG_N_SETS (REGNO (x)) == 1
8313               && ! REGNO_REG_SET_P
8314                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8315                   REGNO (x))))
8316       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8317     {
8318       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8319       return NULL;
8320     }
8321
8322   tem = get_last_value (x);
8323   if (tem != 0)
8324     return tem;
8325
8326   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8327       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8328     *result = reg_stat[REGNO (x)].sign_bit_copies;
8329
8330   return NULL;
8331 }
8332 \f
8333 /* Return the number of "extended" bits there are in X, when interpreted
8334    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8335    unsigned quantities, this is the number of high-order zero bits.
8336    For signed quantities, this is the number of copies of the sign bit
8337    minus 1.  In both case, this function returns the number of "spare"
8338    bits.  For example, if two quantities for which this function returns
8339    at least 1 are added, the addition is known not to overflow.
8340
8341    This function will always return 0 unless called during combine, which
8342    implies that it must be called from a define_split.  */
8343
8344 unsigned int
8345 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8346 {
8347   if (nonzero_sign_valid == 0)
8348     return 0;
8349
8350   return (unsignedp
8351           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8352              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8353                                - floor_log2 (nonzero_bits (x, mode)))
8354              : 0)
8355           : num_sign_bit_copies (x, mode) - 1);
8356 }
8357 \f
8358 /* This function is called from `simplify_shift_const' to merge two
8359    outer operations.  Specifically, we have already found that we need
8360    to perform operation *POP0 with constant *PCONST0 at the outermost
8361    position.  We would now like to also perform OP1 with constant CONST1
8362    (with *POP0 being done last).
8363
8364    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8365    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8366    complement the innermost operand, otherwise it is unchanged.
8367
8368    MODE is the mode in which the operation will be done.  No bits outside
8369    the width of this mode matter.  It is assumed that the width of this mode
8370    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8371
8372    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8373    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8374    result is simply *PCONST0.
8375
8376    If the resulting operation cannot be expressed as one operation, we
8377    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8378
8379 static int
8380 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8381 {
8382   enum rtx_code op0 = *pop0;
8383   HOST_WIDE_INT const0 = *pconst0;
8384
8385   const0 &= GET_MODE_MASK (mode);
8386   const1 &= GET_MODE_MASK (mode);
8387
8388   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8389   if (op0 == AND)
8390     const1 &= const0;
8391
8392   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8393      if OP0 is SET.  */
8394
8395   if (op1 == UNKNOWN || op0 == SET)
8396     return 1;
8397
8398   else if (op0 == UNKNOWN)
8399     op0 = op1, const0 = const1;
8400
8401   else if (op0 == op1)
8402     {
8403       switch (op0)
8404         {
8405         case AND:
8406           const0 &= const1;
8407           break;
8408         case IOR:
8409           const0 |= const1;
8410           break;
8411         case XOR:
8412           const0 ^= const1;
8413           break;
8414         case PLUS:
8415           const0 += const1;
8416           break;
8417         case NEG:
8418           op0 = UNKNOWN;
8419           break;
8420         default:
8421           break;
8422         }
8423     }
8424
8425   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8426   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8427     return 0;
8428
8429   /* If the two constants aren't the same, we can't do anything.  The
8430      remaining six cases can all be done.  */
8431   else if (const0 != const1)
8432     return 0;
8433
8434   else
8435     switch (op0)
8436       {
8437       case IOR:
8438         if (op1 == AND)
8439           /* (a & b) | b == b */
8440           op0 = SET;
8441         else /* op1 == XOR */
8442           /* (a ^ b) | b == a | b */
8443           {;}
8444         break;
8445
8446       case XOR:
8447         if (op1 == AND)
8448           /* (a & b) ^ b == (~a) & b */
8449           op0 = AND, *pcomp_p = 1;
8450         else /* op1 == IOR */
8451           /* (a | b) ^ b == a & ~b */
8452           op0 = AND, const0 = ~const0;
8453         break;
8454
8455       case AND:
8456         if (op1 == IOR)
8457           /* (a | b) & b == b */
8458         op0 = SET;
8459         else /* op1 == XOR */
8460           /* (a ^ b) & b) == (~a) & b */
8461           *pcomp_p = 1;
8462         break;
8463       default:
8464         break;
8465       }
8466
8467   /* Check for NO-OP cases.  */
8468   const0 &= GET_MODE_MASK (mode);
8469   if (const0 == 0
8470       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8471     op0 = UNKNOWN;
8472   else if (const0 == 0 && op0 == AND)
8473     op0 = SET;
8474   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8475            && op0 == AND)
8476     op0 = UNKNOWN;
8477
8478   /* ??? Slightly redundant with the above mask, but not entirely.
8479      Moving this above means we'd have to sign-extend the mode mask
8480      for the final test.  */
8481   const0 = trunc_int_for_mode (const0, mode);
8482
8483   *pop0 = op0;
8484   *pconst0 = const0;
8485
8486   return 1;
8487 }
8488 \f
8489 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8490    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8491    simplify it.  Otherwise, return a simplified value.
8492
8493    The shift is normally computed in the widest mode we find in VAROP, as
8494    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8495    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8496
8497 static rtx
8498 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8499                         rtx varop, int orig_count)
8500 {
8501   enum rtx_code orig_code = code;
8502   rtx orig_varop = varop;
8503   int count;
8504   enum machine_mode mode = result_mode;
8505   enum machine_mode shift_mode, tmode;
8506   unsigned int mode_words
8507     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8508   /* We form (outer_op (code varop count) (outer_const)).  */
8509   enum rtx_code outer_op = UNKNOWN;
8510   HOST_WIDE_INT outer_const = 0;
8511   int complement_p = 0;
8512   rtx new, x;
8513
8514   /* Make sure and truncate the "natural" shift on the way in.  We don't
8515      want to do this inside the loop as it makes it more difficult to
8516      combine shifts.  */
8517   if (SHIFT_COUNT_TRUNCATED)
8518     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8519
8520   /* If we were given an invalid count, don't do anything except exactly
8521      what was requested.  */
8522
8523   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8524     return NULL_RTX;
8525
8526   count = orig_count;
8527
8528   /* Unless one of the branches of the `if' in this loop does a `continue',
8529      we will `break' the loop after the `if'.  */
8530
8531   while (count != 0)
8532     {
8533       /* If we have an operand of (clobber (const_int 0)), fail.  */
8534       if (GET_CODE (varop) == CLOBBER)
8535         return NULL_RTX;
8536
8537       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8538          here would cause an infinite loop.  */
8539       if (complement_p)
8540         break;
8541
8542       /* Convert ROTATERT to ROTATE.  */
8543       if (code == ROTATERT)
8544         {
8545           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8546           code = ROTATE;
8547           if (VECTOR_MODE_P (result_mode))
8548             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8549           else
8550             count = bitsize - count;
8551         }
8552
8553       /* We need to determine what mode we will do the shift in.  If the
8554          shift is a right shift or a ROTATE, we must always do it in the mode
8555          it was originally done in.  Otherwise, we can do it in MODE, the
8556          widest mode encountered.  */
8557       shift_mode
8558         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8559            ? result_mode : mode);
8560
8561       /* Handle cases where the count is greater than the size of the mode
8562          minus 1.  For ASHIFT, use the size minus one as the count (this can
8563          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8564          take the count modulo the size.  For other shifts, the result is
8565          zero.
8566
8567          Since these shifts are being produced by the compiler by combining
8568          multiple operations, each of which are defined, we know what the
8569          result is supposed to be.  */
8570
8571       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8572         {
8573           if (code == ASHIFTRT)
8574             count = GET_MODE_BITSIZE (shift_mode) - 1;
8575           else if (code == ROTATE || code == ROTATERT)
8576             count %= GET_MODE_BITSIZE (shift_mode);
8577           else
8578             {
8579               /* We can't simply return zero because there may be an
8580                  outer op.  */
8581               varop = const0_rtx;
8582               count = 0;
8583               break;
8584             }
8585         }
8586
8587       /* An arithmetic right shift of a quantity known to be -1 or 0
8588          is a no-op.  */
8589       if (code == ASHIFTRT
8590           && (num_sign_bit_copies (varop, shift_mode)
8591               == GET_MODE_BITSIZE (shift_mode)))
8592         {
8593           count = 0;
8594           break;
8595         }
8596
8597       /* If we are doing an arithmetic right shift and discarding all but
8598          the sign bit copies, this is equivalent to doing a shift by the
8599          bitsize minus one.  Convert it into that shift because it will often
8600          allow other simplifications.  */
8601
8602       if (code == ASHIFTRT
8603           && (count + num_sign_bit_copies (varop, shift_mode)
8604               >= GET_MODE_BITSIZE (shift_mode)))
8605         count = GET_MODE_BITSIZE (shift_mode) - 1;
8606
8607       /* We simplify the tests below and elsewhere by converting
8608          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8609          `make_compound_operation' will convert it to an ASHIFTRT for
8610          those machines (such as VAX) that don't have an LSHIFTRT.  */
8611       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8612           && code == ASHIFTRT
8613           && ((nonzero_bits (varop, shift_mode)
8614                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8615               == 0))
8616         code = LSHIFTRT;
8617
8618       if (code == LSHIFTRT
8619           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8620           && !(nonzero_bits (varop, shift_mode) >> count))
8621         varop = const0_rtx;
8622       if (code == ASHIFT
8623           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8624           && !((nonzero_bits (varop, shift_mode) << count)
8625                & GET_MODE_MASK (shift_mode)))
8626         varop = const0_rtx;
8627
8628       switch (GET_CODE (varop))
8629         {
8630         case SIGN_EXTEND:
8631         case ZERO_EXTEND:
8632         case SIGN_EXTRACT:
8633         case ZERO_EXTRACT:
8634           new = expand_compound_operation (varop);
8635           if (new != varop)
8636             {
8637               varop = new;
8638               continue;
8639             }
8640           break;
8641
8642         case MEM:
8643           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8644              minus the width of a smaller mode, we can do this with a
8645              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8646           if ((code == ASHIFTRT || code == LSHIFTRT)
8647               && ! mode_dependent_address_p (XEXP (varop, 0))
8648               && ! MEM_VOLATILE_P (varop)
8649               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8650                                          MODE_INT, 1)) != BLKmode)
8651             {
8652               new = adjust_address_nv (varop, tmode,
8653                                        BYTES_BIG_ENDIAN ? 0
8654                                        : count / BITS_PER_UNIT);
8655
8656               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8657                                      : ZERO_EXTEND, mode, new);
8658               count = 0;
8659               continue;
8660             }
8661           break;
8662
8663         case SUBREG:
8664           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8665              the same number of words as what we've seen so far.  Then store
8666              the widest mode in MODE.  */
8667           if (subreg_lowpart_p (varop)
8668               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8669                   > GET_MODE_SIZE (GET_MODE (varop)))
8670               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8671                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8672                  == mode_words)
8673             {
8674               varop = SUBREG_REG (varop);
8675               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8676                 mode = GET_MODE (varop);
8677               continue;
8678             }
8679           break;
8680
8681         case MULT:
8682           /* Some machines use MULT instead of ASHIFT because MULT
8683              is cheaper.  But it is still better on those machines to
8684              merge two shifts into one.  */
8685           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8686               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8687             {
8688               varop
8689                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8690                                        XEXP (varop, 0),
8691                                        GEN_INT (exact_log2 (
8692                                                 INTVAL (XEXP (varop, 1)))));
8693               continue;
8694             }
8695           break;
8696
8697         case UDIV:
8698           /* Similar, for when divides are cheaper.  */
8699           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8700               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8701             {
8702               varop
8703                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8704                                        XEXP (varop, 0),
8705                                        GEN_INT (exact_log2 (
8706                                                 INTVAL (XEXP (varop, 1)))));
8707               continue;
8708             }
8709           break;
8710
8711         case ASHIFTRT:
8712           /* If we are extracting just the sign bit of an arithmetic
8713              right shift, that shift is not needed.  However, the sign
8714              bit of a wider mode may be different from what would be
8715              interpreted as the sign bit in a narrower mode, so, if
8716              the result is narrower, don't discard the shift.  */
8717           if (code == LSHIFTRT
8718               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8719               && (GET_MODE_BITSIZE (result_mode)
8720                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8721             {
8722               varop = XEXP (varop, 0);
8723               continue;
8724             }
8725
8726           /* ... fall through ...  */
8727
8728         case LSHIFTRT:
8729         case ASHIFT:
8730         case ROTATE:
8731           /* Here we have two nested shifts.  The result is usually the
8732              AND of a new shift with a mask.  We compute the result below.  */
8733           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8734               && INTVAL (XEXP (varop, 1)) >= 0
8735               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8736               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8737               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8738             {
8739               enum rtx_code first_code = GET_CODE (varop);
8740               unsigned int first_count = INTVAL (XEXP (varop, 1));
8741               unsigned HOST_WIDE_INT mask;
8742               rtx mask_rtx;
8743
8744               /* We have one common special case.  We can't do any merging if
8745                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8746                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8747                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8748                  we can convert it to
8749                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8750                  This simplifies certain SIGN_EXTEND operations.  */
8751               if (code == ASHIFT && first_code == ASHIFTRT
8752                   && count == (GET_MODE_BITSIZE (result_mode)
8753                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8754                 {
8755                   /* C3 has the low-order C1 bits zero.  */
8756
8757                   mask = (GET_MODE_MASK (mode)
8758                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8759
8760                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8761                                                   XEXP (varop, 0), mask);
8762                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8763                                                 varop, count);
8764                   count = first_count;
8765                   code = ASHIFTRT;
8766                   continue;
8767                 }
8768
8769               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8770                  than C1 high-order bits equal to the sign bit, we can convert
8771                  this to either an ASHIFT or an ASHIFTRT depending on the
8772                  two counts.
8773
8774                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8775
8776               if (code == ASHIFTRT && first_code == ASHIFT
8777                   && GET_MODE (varop) == shift_mode
8778                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8779                       > first_count))
8780                 {
8781                   varop = XEXP (varop, 0);
8782                   count -= first_count;
8783                   if (count < 0)
8784                     {
8785                       count = -count;
8786                       code = ASHIFT;
8787                     }
8788
8789                   continue;
8790                 }
8791
8792               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8793                  we can only do this if FIRST_CODE is also ASHIFTRT.
8794
8795                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8796                  ASHIFTRT.
8797
8798                  If the mode of this shift is not the mode of the outer shift,
8799                  we can't do this if either shift is a right shift or ROTATE.
8800
8801                  Finally, we can't do any of these if the mode is too wide
8802                  unless the codes are the same.
8803
8804                  Handle the case where the shift codes are the same
8805                  first.  */
8806
8807               if (code == first_code)
8808                 {
8809                   if (GET_MODE (varop) != result_mode
8810                       && (code == ASHIFTRT || code == LSHIFTRT
8811                           || code == ROTATE))
8812                     break;
8813
8814                   count += first_count;
8815                   varop = XEXP (varop, 0);
8816                   continue;
8817                 }
8818
8819               if (code == ASHIFTRT
8820                   || (code == ROTATE && first_code == ASHIFTRT)
8821                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8822                   || (GET_MODE (varop) != result_mode
8823                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8824                           || first_code == ROTATE
8825                           || code == ROTATE)))
8826                 break;
8827
8828               /* To compute the mask to apply after the shift, shift the
8829                  nonzero bits of the inner shift the same way the
8830                  outer shift will.  */
8831
8832               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8833
8834               mask_rtx
8835                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8836                                                    GEN_INT (count));
8837
8838               /* Give up if we can't compute an outer operation to use.  */
8839               if (mask_rtx == 0
8840                   || GET_CODE (mask_rtx) != CONST_INT
8841                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8842                                         INTVAL (mask_rtx),
8843                                         result_mode, &complement_p))
8844                 break;
8845
8846               /* If the shifts are in the same direction, we add the
8847                  counts.  Otherwise, we subtract them.  */
8848               if ((code == ASHIFTRT || code == LSHIFTRT)
8849                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8850                 count += first_count;
8851               else
8852                 count -= first_count;
8853
8854               /* If COUNT is positive, the new shift is usually CODE,
8855                  except for the two exceptions below, in which case it is
8856                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8857                  always be used  */
8858               if (count > 0
8859                   && ((first_code == ROTATE && code == ASHIFT)
8860                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8861                 code = first_code;
8862               else if (count < 0)
8863                 code = first_code, count = -count;
8864
8865               varop = XEXP (varop, 0);
8866               continue;
8867             }
8868
8869           /* If we have (A << B << C) for any shift, we can convert this to
8870              (A << C << B).  This wins if A is a constant.  Only try this if
8871              B is not a constant.  */
8872
8873           else if (GET_CODE (varop) == code
8874                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8875                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8876             {
8877               rtx new = simplify_const_binary_operation (code, mode,
8878                                                          XEXP (varop, 0),
8879                                                          GEN_INT (count));
8880               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8881               count = 0;
8882               continue;
8883             }
8884           break;
8885
8886         case NOT:
8887           /* Make this fit the case below.  */
8888           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8889                                GEN_INT (GET_MODE_MASK (mode)));
8890           continue;
8891
8892         case IOR:
8893         case AND:
8894         case XOR:
8895           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8896              with C the size of VAROP - 1 and the shift is logical if
8897              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8898              we have an (le X 0) operation.   If we have an arithmetic shift
8899              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8900              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8901
8902           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8903               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8904               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8905               && (code == LSHIFTRT || code == ASHIFTRT)
8906               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8907               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8908             {
8909               count = 0;
8910               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8911                                   const0_rtx);
8912
8913               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8914                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8915
8916               continue;
8917             }
8918
8919           /* If we have (shift (logical)), move the logical to the outside
8920              to allow it to possibly combine with another logical and the
8921              shift to combine with another shift.  This also canonicalizes to
8922              what a ZERO_EXTRACT looks like.  Also, some machines have
8923              (and (shift)) insns.  */
8924
8925           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8926               /* We can't do this if we have (ashiftrt (xor))  and the
8927                  constant has its sign bit set in shift_mode.  */
8928               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8929                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8930                                               shift_mode))
8931               && (new = simplify_const_binary_operation (code, result_mode,
8932                                                          XEXP (varop, 1),
8933                                                          GEN_INT (count))) != 0
8934               && GET_CODE (new) == CONST_INT
8935               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8936                                   INTVAL (new), result_mode, &complement_p))
8937             {
8938               varop = XEXP (varop, 0);
8939               continue;
8940             }
8941
8942           /* If we can't do that, try to simplify the shift in each arm of the
8943              logical expression, make a new logical expression, and apply
8944              the inverse distributive law.  This also can't be done
8945              for some (ashiftrt (xor)).  */
8946           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8947              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8948                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8949                                              shift_mode)))
8950             {
8951               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8952                                               XEXP (varop, 0), count);
8953               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8954                                               XEXP (varop, 1), count);
8955
8956               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8957                                            lhs, rhs);
8958               varop = apply_distributive_law (varop);
8959
8960               count = 0;
8961               continue;
8962             }
8963           break;
8964
8965         case EQ:
8966           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8967              says that the sign bit can be tested, FOO has mode MODE, C is
8968              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8969              that may be nonzero.  */
8970           if (code == LSHIFTRT
8971               && XEXP (varop, 1) == const0_rtx
8972               && GET_MODE (XEXP (varop, 0)) == result_mode
8973               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8974               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8975               && STORE_FLAG_VALUE == -1
8976               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8977               && merge_outer_ops (&outer_op, &outer_const, XOR,
8978                                   (HOST_WIDE_INT) 1, result_mode,
8979                                   &complement_p))
8980             {
8981               varop = XEXP (varop, 0);
8982               count = 0;
8983               continue;
8984             }
8985           break;
8986
8987         case NEG:
8988           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8989              than the number of bits in the mode is equivalent to A.  */
8990           if (code == LSHIFTRT
8991               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8992               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8993             {
8994               varop = XEXP (varop, 0);
8995               count = 0;
8996               continue;
8997             }
8998
8999           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9000              NEG outside to allow shifts to combine.  */
9001           if (code == ASHIFT
9002               && merge_outer_ops (&outer_op, &outer_const, NEG,
9003                                   (HOST_WIDE_INT) 0, result_mode,
9004                                   &complement_p))
9005             {
9006               varop = XEXP (varop, 0);
9007               continue;
9008             }
9009           break;
9010
9011         case PLUS:
9012           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9013              is one less than the number of bits in the mode is
9014              equivalent to (xor A 1).  */
9015           if (code == LSHIFTRT
9016               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9017               && XEXP (varop, 1) == constm1_rtx
9018               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9019               && merge_outer_ops (&outer_op, &outer_const, XOR,
9020                                   (HOST_WIDE_INT) 1, result_mode,
9021                                   &complement_p))
9022             {
9023               count = 0;
9024               varop = XEXP (varop, 0);
9025               continue;
9026             }
9027
9028           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9029              that might be nonzero in BAR are those being shifted out and those
9030              bits are known zero in FOO, we can replace the PLUS with FOO.
9031              Similarly in the other operand order.  This code occurs when
9032              we are computing the size of a variable-size array.  */
9033
9034           if ((code == ASHIFTRT || code == LSHIFTRT)
9035               && count < HOST_BITS_PER_WIDE_INT
9036               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9037               && (nonzero_bits (XEXP (varop, 1), result_mode)
9038                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9039             {
9040               varop = XEXP (varop, 0);
9041               continue;
9042             }
9043           else if ((code == ASHIFTRT || code == LSHIFTRT)
9044                    && count < HOST_BITS_PER_WIDE_INT
9045                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9046                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9047                             >> count)
9048                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9049                             & nonzero_bits (XEXP (varop, 1),
9050                                                  result_mode)))
9051             {
9052               varop = XEXP (varop, 1);
9053               continue;
9054             }
9055
9056           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9057           if (code == ASHIFT
9058               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9059               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9060                                                          XEXP (varop, 1),
9061                                                          GEN_INT (count))) != 0
9062               && GET_CODE (new) == CONST_INT
9063               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9064                                   INTVAL (new), result_mode, &complement_p))
9065             {
9066               varop = XEXP (varop, 0);
9067               continue;
9068             }
9069
9070           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9071              signbit', and attempt to change the PLUS to an XOR and move it to
9072              the outer operation as is done above in the AND/IOR/XOR case
9073              leg for shift(logical). See details in logical handling above
9074              for reasoning in doing so.  */
9075           if (code == LSHIFTRT
9076               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9077               && mode_signbit_p (result_mode, XEXP (varop, 1))
9078               && (new = simplify_const_binary_operation (code, result_mode,
9079                                                          XEXP (varop, 1),
9080                                                          GEN_INT (count))) != 0
9081               && GET_CODE (new) == CONST_INT
9082               && merge_outer_ops (&outer_op, &outer_const, XOR,
9083                                   INTVAL (new), result_mode, &complement_p))
9084             {
9085               varop = XEXP (varop, 0);
9086               continue;
9087             }
9088
9089           break;
9090
9091         case MINUS:
9092           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9093              with C the size of VAROP - 1 and the shift is logical if
9094              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9095              we have a (gt X 0) operation.  If the shift is arithmetic with
9096              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9097              we have a (neg (gt X 0)) operation.  */
9098
9099           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9100               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9101               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9102               && (code == LSHIFTRT || code == ASHIFTRT)
9103               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9104               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9105               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9106             {
9107               count = 0;
9108               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9109                                   const0_rtx);
9110
9111               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9112                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9113
9114               continue;
9115             }
9116           break;
9117
9118         case TRUNCATE:
9119           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9120              if the truncate does not affect the value.  */
9121           if (code == LSHIFTRT
9122               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9123               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9124               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9125                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9126                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9127             {
9128               rtx varop_inner = XEXP (varop, 0);
9129
9130               varop_inner
9131                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9132                                     XEXP (varop_inner, 0),
9133                                     GEN_INT
9134                                     (count + INTVAL (XEXP (varop_inner, 1))));
9135               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9136               count = 0;
9137               continue;
9138             }
9139           break;
9140
9141         default:
9142           break;
9143         }
9144
9145       break;
9146     }
9147
9148   /* We need to determine what mode to do the shift in.  If the shift is
9149      a right shift or ROTATE, we must always do it in the mode it was
9150      originally done in.  Otherwise, we can do it in MODE, the widest mode
9151      encountered.  The code we care about is that of the shift that will
9152      actually be done, not the shift that was originally requested.  */
9153   shift_mode
9154     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9155        ? result_mode : mode);
9156
9157   /* We have now finished analyzing the shift.  The result should be
9158      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9159      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9160      to the result of the shift.  OUTER_CONST is the relevant constant,
9161      but we must turn off all bits turned off in the shift.  */
9162
9163   if (outer_op == UNKNOWN
9164       && orig_code == code && orig_count == count
9165       && varop == orig_varop
9166       && shift_mode == GET_MODE (varop))
9167     return NULL_RTX;
9168
9169   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9170   varop = gen_lowpart (shift_mode, varop);
9171   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9172     return NULL_RTX;
9173
9174   /* If we have an outer operation and we just made a shift, it is
9175      possible that we could have simplified the shift were it not
9176      for the outer operation.  So try to do the simplification
9177      recursively.  */
9178
9179   if (outer_op != UNKNOWN)
9180     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9181   else
9182     x = NULL_RTX;
9183
9184   if (x == NULL_RTX)
9185     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9186
9187   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9188      turn off all the bits that the shift would have turned off.  */
9189   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9190     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9191                                 GET_MODE_MASK (result_mode) >> orig_count);
9192
9193   /* Do the remainder of the processing in RESULT_MODE.  */
9194   x = gen_lowpart (result_mode, x);
9195
9196   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9197      operation.  */
9198   if (complement_p)
9199     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9200
9201   if (outer_op != UNKNOWN)
9202     {
9203       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9204         outer_const = trunc_int_for_mode (outer_const, result_mode);
9205
9206       if (outer_op == AND)
9207         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9208       else if (outer_op == SET)
9209         /* This means that we have determined that the result is
9210            equivalent to a constant.  This should be rare.  */
9211         x = GEN_INT (outer_const);
9212       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9213         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9214       else
9215         x = simplify_gen_binary (outer_op, result_mode, x,
9216                                  GEN_INT (outer_const));
9217     }
9218
9219   return x;
9220 }
9221
9222 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9223    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9224    return X or, if it is NULL, synthesize the expression with
9225    simplify_gen_binary.  Otherwise, return a simplified value.
9226
9227    The shift is normally computed in the widest mode we find in VAROP, as
9228    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9229    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9230
9231 static rtx
9232 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9233                       rtx varop, int count)
9234 {
9235   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9236   if (tem)
9237     return tem;
9238
9239   if (!x)
9240     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9241   if (GET_MODE (x) != result_mode)
9242     x = gen_lowpart (result_mode, x);
9243   return x;
9244 }
9245
9246 \f
9247 /* Like recog, but we receive the address of a pointer to a new pattern.
9248    We try to match the rtx that the pointer points to.
9249    If that fails, we may try to modify or replace the pattern,
9250    storing the replacement into the same pointer object.
9251
9252    Modifications include deletion or addition of CLOBBERs.
9253
9254    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9255    the CLOBBERs are placed.
9256
9257    The value is the final insn code from the pattern ultimately matched,
9258    or -1.  */
9259
9260 static int
9261 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9262 {
9263   rtx pat = *pnewpat;
9264   int insn_code_number;
9265   int num_clobbers_to_add = 0;
9266   int i;
9267   rtx notes = 0;
9268   rtx old_notes, old_pat;
9269
9270   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9271      we use to indicate that something didn't match.  If we find such a
9272      thing, force rejection.  */
9273   if (GET_CODE (pat) == PARALLEL)
9274     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9275       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9276           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9277         return -1;
9278
9279   old_pat = PATTERN (insn);
9280   old_notes = REG_NOTES (insn);
9281   PATTERN (insn) = pat;
9282   REG_NOTES (insn) = 0;
9283
9284   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9285
9286   /* If it isn't, there is the possibility that we previously had an insn
9287      that clobbered some register as a side effect, but the combined
9288      insn doesn't need to do that.  So try once more without the clobbers
9289      unless this represents an ASM insn.  */
9290
9291   if (insn_code_number < 0 && ! check_asm_operands (pat)
9292       && GET_CODE (pat) == PARALLEL)
9293     {
9294       int pos;
9295
9296       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9297         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9298           {
9299             if (i != pos)
9300               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9301             pos++;
9302           }
9303
9304       SUBST_INT (XVECLEN (pat, 0), pos);
9305
9306       if (pos == 1)
9307         pat = XVECEXP (pat, 0, 0);
9308
9309       PATTERN (insn) = pat;
9310       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9311     }
9312   PATTERN (insn) = old_pat;
9313   REG_NOTES (insn) = old_notes;
9314
9315   /* Recognize all noop sets, these will be killed by followup pass.  */
9316   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9317     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9318
9319   /* If we had any clobbers to add, make a new pattern than contains
9320      them.  Then check to make sure that all of them are dead.  */
9321   if (num_clobbers_to_add)
9322     {
9323       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9324                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9325                                                   ? (XVECLEN (pat, 0)
9326                                                      + num_clobbers_to_add)
9327                                                   : num_clobbers_to_add + 1));
9328
9329       if (GET_CODE (pat) == PARALLEL)
9330         for (i = 0; i < XVECLEN (pat, 0); i++)
9331           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9332       else
9333         XVECEXP (newpat, 0, 0) = pat;
9334
9335       add_clobbers (newpat, insn_code_number);
9336
9337       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9338            i < XVECLEN (newpat, 0); i++)
9339         {
9340           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9341               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9342             return -1;
9343           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9344                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9345         }
9346       pat = newpat;
9347     }
9348
9349   *pnewpat = pat;
9350   *pnotes = notes;
9351
9352   return insn_code_number;
9353 }
9354 \f
9355 /* Like gen_lowpart_general but for use by combine.  In combine it
9356    is not possible to create any new pseudoregs.  However, it is
9357    safe to create invalid memory addresses, because combine will
9358    try to recognize them and all they will do is make the combine
9359    attempt fail.
9360
9361    If for some reason this cannot do its job, an rtx
9362    (clobber (const_int 0)) is returned.
9363    An insn containing that will not be recognized.  */
9364
9365 static rtx
9366 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9367 {
9368   enum machine_mode imode = GET_MODE (x);
9369   unsigned int osize = GET_MODE_SIZE (omode);
9370   unsigned int isize = GET_MODE_SIZE (imode);
9371   rtx result;
9372
9373   if (omode == imode)
9374     return x;
9375
9376   /* Return identity if this is a CONST or symbolic reference.  */
9377   if (omode == Pmode
9378       && (GET_CODE (x) == CONST
9379           || GET_CODE (x) == SYMBOL_REF
9380           || GET_CODE (x) == LABEL_REF))
9381     return x;
9382
9383   /* We can only support MODE being wider than a word if X is a
9384      constant integer or has a mode the same size.  */
9385   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9386       && ! ((imode == VOIDmode
9387              && (GET_CODE (x) == CONST_INT
9388                  || GET_CODE (x) == CONST_DOUBLE))
9389             || isize == osize))
9390     goto fail;
9391
9392   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9393      won't know what to do.  So we will strip off the SUBREG here and
9394      process normally.  */
9395   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9396     {
9397       x = SUBREG_REG (x);
9398
9399       /* For use in case we fall down into the address adjustments
9400          further below, we need to adjust the known mode and size of
9401          x; imode and isize, since we just adjusted x.  */
9402       imode = GET_MODE (x);
9403
9404       if (imode == omode)
9405         return x;
9406
9407       isize = GET_MODE_SIZE (imode);
9408     }
9409
9410   result = gen_lowpart_common (omode, x);
9411
9412 #ifdef CANNOT_CHANGE_MODE_CLASS
9413   if (result != 0 && GET_CODE (result) == SUBREG)
9414     record_subregs_of_mode (result);
9415 #endif
9416
9417   if (result)
9418     return result;
9419
9420   if (MEM_P (x))
9421     {
9422       int offset = 0;
9423
9424       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9425          address.  */
9426       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9427         goto fail;
9428
9429       /* If we want to refer to something bigger than the original memref,
9430          generate a paradoxical subreg instead.  That will force a reload
9431          of the original memref X.  */
9432       if (isize < osize)
9433         return gen_rtx_SUBREG (omode, x, 0);
9434
9435       if (WORDS_BIG_ENDIAN)
9436         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9437
9438       /* Adjust the address so that the address-after-the-data is
9439          unchanged.  */
9440       if (BYTES_BIG_ENDIAN)
9441         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9442
9443       return adjust_address_nv (x, omode, offset);
9444     }
9445
9446   /* If X is a comparison operator, rewrite it in a new mode.  This
9447      probably won't match, but may allow further simplifications.  */
9448   else if (COMPARISON_P (x))
9449     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9450
9451   /* If we couldn't simplify X any other way, just enclose it in a
9452      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9453      include an explicit SUBREG or we may simplify it further in combine.  */
9454   else
9455     {
9456       int offset = 0;
9457       rtx res;
9458
9459       offset = subreg_lowpart_offset (omode, imode);
9460       if (imode == VOIDmode)
9461         {
9462           imode = int_mode_for_mode (omode);
9463           x = gen_lowpart_common (imode, x);
9464           if (x == NULL)
9465             goto fail;
9466         }
9467       res = simplify_gen_subreg (omode, x, imode, offset);
9468       if (res)
9469         return res;
9470     }
9471
9472  fail:
9473   return gen_rtx_CLOBBER (imode, const0_rtx);
9474 }
9475 \f
9476 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9477    comparison code that will be tested.
9478
9479    The result is a possibly different comparison code to use.  *POP0 and
9480    *POP1 may be updated.
9481
9482    It is possible that we might detect that a comparison is either always
9483    true or always false.  However, we do not perform general constant
9484    folding in combine, so this knowledge isn't useful.  Such tautologies
9485    should have been detected earlier.  Hence we ignore all such cases.  */
9486
9487 static enum rtx_code
9488 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9489 {
9490   rtx op0 = *pop0;
9491   rtx op1 = *pop1;
9492   rtx tem, tem1;
9493   int i;
9494   enum machine_mode mode, tmode;
9495
9496   /* Try a few ways of applying the same transformation to both operands.  */
9497   while (1)
9498     {
9499 #ifndef WORD_REGISTER_OPERATIONS
9500       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9501          so check specially.  */
9502       if (code != GTU && code != GEU && code != LTU && code != LEU
9503           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9504           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9505           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9506           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9507           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9508           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9509               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9510           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9511           && XEXP (op0, 1) == XEXP (op1, 1)
9512           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9513           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9514           && (INTVAL (XEXP (op0, 1))
9515               == (GET_MODE_BITSIZE (GET_MODE (op0))
9516                   - (GET_MODE_BITSIZE
9517                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9518         {
9519           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9520           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9521         }
9522 #endif
9523
9524       /* If both operands are the same constant shift, see if we can ignore the
9525          shift.  We can if the shift is a rotate or if the bits shifted out of
9526          this shift are known to be zero for both inputs and if the type of
9527          comparison is compatible with the shift.  */
9528       if (GET_CODE (op0) == GET_CODE (op1)
9529           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9530           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9531               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9532                   && (code != GT && code != LT && code != GE && code != LE))
9533               || (GET_CODE (op0) == ASHIFTRT
9534                   && (code != GTU && code != LTU
9535                       && code != GEU && code != LEU)))
9536           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9537           && INTVAL (XEXP (op0, 1)) >= 0
9538           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9539           && XEXP (op0, 1) == XEXP (op1, 1))
9540         {
9541           enum machine_mode mode = GET_MODE (op0);
9542           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9543           int shift_count = INTVAL (XEXP (op0, 1));
9544
9545           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9546             mask &= (mask >> shift_count) << shift_count;
9547           else if (GET_CODE (op0) == ASHIFT)
9548             mask = (mask & (mask << shift_count)) >> shift_count;
9549
9550           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9551               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9552             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9553           else
9554             break;
9555         }
9556
9557       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9558          SUBREGs are of the same mode, and, in both cases, the AND would
9559          be redundant if the comparison was done in the narrower mode,
9560          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9561          and the operand's possibly nonzero bits are 0xffffff01; in that case
9562          if we only care about QImode, we don't need the AND).  This case
9563          occurs if the output mode of an scc insn is not SImode and
9564          STORE_FLAG_VALUE == 1 (e.g., the 386).
9565
9566          Similarly, check for a case where the AND's are ZERO_EXTEND
9567          operations from some narrower mode even though a SUBREG is not
9568          present.  */
9569
9570       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9571                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9572                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9573         {
9574           rtx inner_op0 = XEXP (op0, 0);
9575           rtx inner_op1 = XEXP (op1, 0);
9576           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9577           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9578           int changed = 0;
9579
9580           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9581               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9582                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9583               && (GET_MODE (SUBREG_REG (inner_op0))
9584                   == GET_MODE (SUBREG_REG (inner_op1)))
9585               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9586                   <= HOST_BITS_PER_WIDE_INT)
9587               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9588                                              GET_MODE (SUBREG_REG (inner_op0)))))
9589               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9590                                              GET_MODE (SUBREG_REG (inner_op1))))))
9591             {
9592               op0 = SUBREG_REG (inner_op0);
9593               op1 = SUBREG_REG (inner_op1);
9594
9595               /* The resulting comparison is always unsigned since we masked
9596                  off the original sign bit.  */
9597               code = unsigned_condition (code);
9598
9599               changed = 1;
9600             }
9601
9602           else if (c0 == c1)
9603             for (tmode = GET_CLASS_NARROWEST_MODE
9604                  (GET_MODE_CLASS (GET_MODE (op0)));
9605                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9606               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9607                 {
9608                   op0 = gen_lowpart (tmode, inner_op0);
9609                   op1 = gen_lowpart (tmode, inner_op1);
9610                   code = unsigned_condition (code);
9611                   changed = 1;
9612                   break;
9613                 }
9614
9615           if (! changed)
9616             break;
9617         }
9618
9619       /* If both operands are NOT, we can strip off the outer operation
9620          and adjust the comparison code for swapped operands; similarly for
9621          NEG, except that this must be an equality comparison.  */
9622       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9623                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9624                    && (code == EQ || code == NE)))
9625         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9626
9627       else
9628         break;
9629     }
9630
9631   /* If the first operand is a constant, swap the operands and adjust the
9632      comparison code appropriately, but don't do this if the second operand
9633      is already a constant integer.  */
9634   if (swap_commutative_operands_p (op0, op1))
9635     {
9636       tem = op0, op0 = op1, op1 = tem;
9637       code = swap_condition (code);
9638     }
9639
9640   /* We now enter a loop during which we will try to simplify the comparison.
9641      For the most part, we only are concerned with comparisons with zero,
9642      but some things may really be comparisons with zero but not start
9643      out looking that way.  */
9644
9645   while (GET_CODE (op1) == CONST_INT)
9646     {
9647       enum machine_mode mode = GET_MODE (op0);
9648       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9649       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9650       int equality_comparison_p;
9651       int sign_bit_comparison_p;
9652       int unsigned_comparison_p;
9653       HOST_WIDE_INT const_op;
9654
9655       /* We only want to handle integral modes.  This catches VOIDmode,
9656          CCmode, and the floating-point modes.  An exception is that we
9657          can handle VOIDmode if OP0 is a COMPARE or a comparison
9658          operation.  */
9659
9660       if (GET_MODE_CLASS (mode) != MODE_INT
9661           && ! (mode == VOIDmode
9662                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9663         break;
9664
9665       /* Get the constant we are comparing against and turn off all bits
9666          not on in our mode.  */
9667       const_op = INTVAL (op1);
9668       if (mode != VOIDmode)
9669         const_op = trunc_int_for_mode (const_op, mode);
9670       op1 = GEN_INT (const_op);
9671
9672       /* If we are comparing against a constant power of two and the value
9673          being compared can only have that single bit nonzero (e.g., it was
9674          `and'ed with that bit), we can replace this with a comparison
9675          with zero.  */
9676       if (const_op
9677           && (code == EQ || code == NE || code == GE || code == GEU
9678               || code == LT || code == LTU)
9679           && mode_width <= HOST_BITS_PER_WIDE_INT
9680           && exact_log2 (const_op) >= 0
9681           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9682         {
9683           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9684           op1 = const0_rtx, const_op = 0;
9685         }
9686
9687       /* Similarly, if we are comparing a value known to be either -1 or
9688          0 with -1, change it to the opposite comparison against zero.  */
9689
9690       if (const_op == -1
9691           && (code == EQ || code == NE || code == GT || code == LE
9692               || code == GEU || code == LTU)
9693           && num_sign_bit_copies (op0, mode) == mode_width)
9694         {
9695           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9696           op1 = const0_rtx, const_op = 0;
9697         }
9698
9699       /* Do some canonicalizations based on the comparison code.  We prefer
9700          comparisons against zero and then prefer equality comparisons.
9701          If we can reduce the size of a constant, we will do that too.  */
9702
9703       switch (code)
9704         {
9705         case LT:
9706           /* < C is equivalent to <= (C - 1) */
9707           if (const_op > 0)
9708             {
9709               const_op -= 1;
9710               op1 = GEN_INT (const_op);
9711               code = LE;
9712               /* ... fall through to LE case below.  */
9713             }
9714           else
9715             break;
9716
9717         case LE:
9718           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9719           if (const_op < 0)
9720             {
9721               const_op += 1;
9722               op1 = GEN_INT (const_op);
9723               code = LT;
9724             }
9725
9726           /* If we are doing a <= 0 comparison on a value known to have
9727              a zero sign bit, we can replace this with == 0.  */
9728           else if (const_op == 0
9729                    && mode_width <= HOST_BITS_PER_WIDE_INT
9730                    && (nonzero_bits (op0, mode)
9731                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9732             code = EQ;
9733           break;
9734
9735         case GE:
9736           /* >= C is equivalent to > (C - 1).  */
9737           if (const_op > 0)
9738             {
9739               const_op -= 1;
9740               op1 = GEN_INT (const_op);
9741               code = GT;
9742               /* ... fall through to GT below.  */
9743             }
9744           else
9745             break;
9746
9747         case GT:
9748           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9749           if (const_op < 0)
9750             {
9751               const_op += 1;
9752               op1 = GEN_INT (const_op);
9753               code = GE;
9754             }
9755
9756           /* If we are doing a > 0 comparison on a value known to have
9757              a zero sign bit, we can replace this with != 0.  */
9758           else if (const_op == 0
9759                    && mode_width <= HOST_BITS_PER_WIDE_INT
9760                    && (nonzero_bits (op0, mode)
9761                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9762             code = NE;
9763           break;
9764
9765         case LTU:
9766           /* < C is equivalent to <= (C - 1).  */
9767           if (const_op > 0)
9768             {
9769               const_op -= 1;
9770               op1 = GEN_INT (const_op);
9771               code = LEU;
9772               /* ... fall through ...  */
9773             }
9774
9775           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9776           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9777                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9778             {
9779               const_op = 0, op1 = const0_rtx;
9780               code = GE;
9781               break;
9782             }
9783           else
9784             break;
9785
9786         case LEU:
9787           /* unsigned <= 0 is equivalent to == 0 */
9788           if (const_op == 0)
9789             code = EQ;
9790
9791           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9792           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9793                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9794             {
9795               const_op = 0, op1 = const0_rtx;
9796               code = GE;
9797             }
9798           break;
9799
9800         case GEU:
9801           /* >= C is equivalent to > (C - 1).  */
9802           if (const_op > 1)
9803             {
9804               const_op -= 1;
9805               op1 = GEN_INT (const_op);
9806               code = GTU;
9807               /* ... fall through ...  */
9808             }
9809
9810           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9811           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9812                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9813             {
9814               const_op = 0, op1 = const0_rtx;
9815               code = LT;
9816               break;
9817             }
9818           else
9819             break;
9820
9821         case GTU:
9822           /* unsigned > 0 is equivalent to != 0 */
9823           if (const_op == 0)
9824             code = NE;
9825
9826           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9827           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9828                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9829             {
9830               const_op = 0, op1 = const0_rtx;
9831               code = LT;
9832             }
9833           break;
9834
9835         default:
9836           break;
9837         }
9838
9839       /* Compute some predicates to simplify code below.  */
9840
9841       equality_comparison_p = (code == EQ || code == NE);
9842       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9843       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9844                                || code == GEU);
9845
9846       /* If this is a sign bit comparison and we can do arithmetic in
9847          MODE, say that we will only be needing the sign bit of OP0.  */
9848       if (sign_bit_comparison_p
9849           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9850         op0 = force_to_mode (op0, mode,
9851                              ((HOST_WIDE_INT) 1
9852                               << (GET_MODE_BITSIZE (mode) - 1)),
9853                              0);
9854
9855       /* Now try cases based on the opcode of OP0.  If none of the cases
9856          does a "continue", we exit this loop immediately after the
9857          switch.  */
9858
9859       switch (GET_CODE (op0))
9860         {
9861         case ZERO_EXTRACT:
9862           /* If we are extracting a single bit from a variable position in
9863              a constant that has only a single bit set and are comparing it
9864              with zero, we can convert this into an equality comparison
9865              between the position and the location of the single bit.  */
9866           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9867              have already reduced the shift count modulo the word size.  */
9868           if (!SHIFT_COUNT_TRUNCATED
9869               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9870               && XEXP (op0, 1) == const1_rtx
9871               && equality_comparison_p && const_op == 0
9872               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9873             {
9874               if (BITS_BIG_ENDIAN)
9875                 {
9876                   enum machine_mode new_mode
9877                     = mode_for_extraction (EP_extzv, 1);
9878                   if (new_mode == MAX_MACHINE_MODE)
9879                     i = BITS_PER_WORD - 1 - i;
9880                   else
9881                     {
9882                       mode = new_mode;
9883                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9884                     }
9885                 }
9886
9887               op0 = XEXP (op0, 2);
9888               op1 = GEN_INT (i);
9889               const_op = i;
9890
9891               /* Result is nonzero iff shift count is equal to I.  */
9892               code = reverse_condition (code);
9893               continue;
9894             }
9895
9896           /* ... fall through ...  */
9897
9898         case SIGN_EXTRACT:
9899           tem = expand_compound_operation (op0);
9900           if (tem != op0)
9901             {
9902               op0 = tem;
9903               continue;
9904             }
9905           break;
9906
9907         case NOT:
9908           /* If testing for equality, we can take the NOT of the constant.  */
9909           if (equality_comparison_p
9910               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9911             {
9912               op0 = XEXP (op0, 0);
9913               op1 = tem;
9914               continue;
9915             }
9916
9917           /* If just looking at the sign bit, reverse the sense of the
9918              comparison.  */
9919           if (sign_bit_comparison_p)
9920             {
9921               op0 = XEXP (op0, 0);
9922               code = (code == GE ? LT : GE);
9923               continue;
9924             }
9925           break;
9926
9927         case NEG:
9928           /* If testing for equality, we can take the NEG of the constant.  */
9929           if (equality_comparison_p
9930               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9931             {
9932               op0 = XEXP (op0, 0);
9933               op1 = tem;
9934               continue;
9935             }
9936
9937           /* The remaining cases only apply to comparisons with zero.  */
9938           if (const_op != 0)
9939             break;
9940
9941           /* When X is ABS or is known positive,
9942              (neg X) is < 0 if and only if X != 0.  */
9943
9944           if (sign_bit_comparison_p
9945               && (GET_CODE (XEXP (op0, 0)) == ABS
9946                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9947                       && (nonzero_bits (XEXP (op0, 0), mode)
9948                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9949             {
9950               op0 = XEXP (op0, 0);
9951               code = (code == LT ? NE : EQ);
9952               continue;
9953             }
9954
9955           /* If we have NEG of something whose two high-order bits are the
9956              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9957           if (num_sign_bit_copies (op0, mode) >= 2)
9958             {
9959               op0 = XEXP (op0, 0);
9960               code = swap_condition (code);
9961               continue;
9962             }
9963           break;
9964
9965         case ROTATE:
9966           /* If we are testing equality and our count is a constant, we
9967              can perform the inverse operation on our RHS.  */
9968           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9969               && (tem = simplify_binary_operation (ROTATERT, mode,
9970                                                    op1, XEXP (op0, 1))) != 0)
9971             {
9972               op0 = XEXP (op0, 0);
9973               op1 = tem;
9974               continue;
9975             }
9976
9977           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9978              a particular bit.  Convert it to an AND of a constant of that
9979              bit.  This will be converted into a ZERO_EXTRACT.  */
9980           if (const_op == 0 && sign_bit_comparison_p
9981               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9982               && mode_width <= HOST_BITS_PER_WIDE_INT)
9983             {
9984               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9985                                             ((HOST_WIDE_INT) 1
9986                                              << (mode_width - 1
9987                                                  - INTVAL (XEXP (op0, 1)))));
9988               code = (code == LT ? NE : EQ);
9989               continue;
9990             }
9991
9992           /* Fall through.  */
9993
9994         case ABS:
9995           /* ABS is ignorable inside an equality comparison with zero.  */
9996           if (const_op == 0 && equality_comparison_p)
9997             {
9998               op0 = XEXP (op0, 0);
9999               continue;
10000             }
10001           break;
10002
10003         case SIGN_EXTEND:
10004           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10005              (compare FOO CONST) if CONST fits in FOO's mode and we
10006              are either testing inequality or have an unsigned
10007              comparison with ZERO_EXTEND or a signed comparison with
10008              SIGN_EXTEND.  But don't do it if we don't have a compare
10009              insn of the given mode, since we'd have to revert it
10010              later on, and then we wouldn't know whether to sign- or
10011              zero-extend.  */
10012           mode = GET_MODE (XEXP (op0, 0));
10013           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10014               && ! unsigned_comparison_p
10015               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10016               && ((unsigned HOST_WIDE_INT) const_op
10017                   < (((unsigned HOST_WIDE_INT) 1
10018                       << (GET_MODE_BITSIZE (mode) - 1))))
10019               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10020             {
10021               op0 = XEXP (op0, 0);
10022               continue;
10023             }
10024           break;
10025
10026         case SUBREG:
10027           /* Check for the case where we are comparing A - C1 with C2, that is
10028
10029                (subreg:MODE (plus (A) (-C1))) op (C2)
10030
10031              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10032              comparison in the wider mode.  One of the following two conditions
10033              must be true in order for this to be valid:
10034
10035                1. The mode extension results in the same bit pattern being added
10036                   on both sides and the comparison is equality or unsigned.  As
10037                   C2 has been truncated to fit in MODE, the pattern can only be
10038                   all 0s or all 1s.
10039
10040                2. The mode extension results in the sign bit being copied on
10041                   each side.
10042
10043              The difficulty here is that we have predicates for A but not for
10044              (A - C1) so we need to check that C1 is within proper bounds so
10045              as to perturbate A as little as possible.  */
10046
10047           if (mode_width <= HOST_BITS_PER_WIDE_INT
10048               && subreg_lowpart_p (op0)
10049               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10050               && GET_CODE (SUBREG_REG (op0)) == PLUS
10051               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10052             {
10053               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10054               rtx a = XEXP (SUBREG_REG (op0), 0);
10055               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10056
10057               if ((c1 > 0
10058                    && (unsigned HOST_WIDE_INT) c1
10059                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10060                    && (equality_comparison_p || unsigned_comparison_p)
10061                    /* (A - C1) zero-extends if it is positive and sign-extends
10062                       if it is negative, C2 both zero- and sign-extends.  */
10063                    && ((0 == (nonzero_bits (a, inner_mode)
10064                               & ~GET_MODE_MASK (mode))
10065                         && const_op >= 0)
10066                        /* (A - C1) sign-extends if it is positive and 1-extends
10067                           if it is negative, C2 both sign- and 1-extends.  */
10068                        || (num_sign_bit_copies (a, inner_mode)
10069                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10070                                              - mode_width)
10071                            && const_op < 0)))
10072                   || ((unsigned HOST_WIDE_INT) c1
10073                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10074                       /* (A - C1) always sign-extends, like C2.  */
10075                       && num_sign_bit_copies (a, inner_mode)
10076                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10077                                            - (mode_width - 1))))
10078                 {
10079                   op0 = SUBREG_REG (op0);
10080                   continue;
10081                 }
10082             }
10083
10084           /* If the inner mode is narrower and we are extracting the low part,
10085              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10086           if (subreg_lowpart_p (op0)
10087               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10088             /* Fall through */ ;
10089           else
10090             break;
10091
10092           /* ... fall through ...  */
10093
10094         case ZERO_EXTEND:
10095           mode = GET_MODE (XEXP (op0, 0));
10096           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10097               && (unsigned_comparison_p || equality_comparison_p)
10098               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10099               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10100               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10101             {
10102               op0 = XEXP (op0, 0);
10103               continue;
10104             }
10105           break;
10106
10107         case PLUS:
10108           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10109              this for equality comparisons due to pathological cases involving
10110              overflows.  */
10111           if (equality_comparison_p
10112               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10113                                                         op1, XEXP (op0, 1))))
10114             {
10115               op0 = XEXP (op0, 0);
10116               op1 = tem;
10117               continue;
10118             }
10119
10120           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10121           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10122               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10123             {
10124               op0 = XEXP (XEXP (op0, 0), 0);
10125               code = (code == LT ? EQ : NE);
10126               continue;
10127             }
10128           break;
10129
10130         case MINUS:
10131           /* We used to optimize signed comparisons against zero, but that
10132              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10133              arrive here as equality comparisons, or (GEU, LTU) are
10134              optimized away.  No need to special-case them.  */
10135
10136           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10137              (eq B (minus A C)), whichever simplifies.  We can only do
10138              this for equality comparisons due to pathological cases involving
10139              overflows.  */
10140           if (equality_comparison_p
10141               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10142                                                         XEXP (op0, 1), op1)))
10143             {
10144               op0 = XEXP (op0, 0);
10145               op1 = tem;
10146               continue;
10147             }
10148
10149           if (equality_comparison_p
10150               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10151                                                         XEXP (op0, 0), op1)))
10152             {
10153               op0 = XEXP (op0, 1);
10154               op1 = tem;
10155               continue;
10156             }
10157
10158           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10159              of bits in X minus 1, is one iff X > 0.  */
10160           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10161               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10162               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10163                  == mode_width - 1
10164               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10165             {
10166               op0 = XEXP (op0, 1);
10167               code = (code == GE ? LE : GT);
10168               continue;
10169             }
10170           break;
10171
10172         case XOR:
10173           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10174              if C is zero or B is a constant.  */
10175           if (equality_comparison_p
10176               && 0 != (tem = simplify_binary_operation (XOR, mode,
10177                                                         XEXP (op0, 1), op1)))
10178             {
10179               op0 = XEXP (op0, 0);
10180               op1 = tem;
10181               continue;
10182             }
10183           break;
10184
10185         case EQ:  case NE:
10186         case UNEQ:  case LTGT:
10187         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10188         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10189         case UNORDERED: case ORDERED:
10190           /* We can't do anything if OP0 is a condition code value, rather
10191              than an actual data value.  */
10192           if (const_op != 0
10193               || CC0_P (XEXP (op0, 0))
10194               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10195             break;
10196
10197           /* Get the two operands being compared.  */
10198           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10199             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10200           else
10201             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10202
10203           /* Check for the cases where we simply want the result of the
10204              earlier test or the opposite of that result.  */
10205           if (code == NE || code == EQ
10206               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10207                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10208                   && (STORE_FLAG_VALUE
10209                       & (((HOST_WIDE_INT) 1
10210                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10211                   && (code == LT || code == GE)))
10212             {
10213               enum rtx_code new_code;
10214               if (code == LT || code == NE)
10215                 new_code = GET_CODE (op0);
10216               else
10217                 new_code = reversed_comparison_code (op0, NULL);
10218
10219               if (new_code != UNKNOWN)
10220                 {
10221                   code = new_code;
10222                   op0 = tem;
10223                   op1 = tem1;
10224                   continue;
10225                 }
10226             }
10227           break;
10228
10229         case IOR:
10230           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10231              iff X <= 0.  */
10232           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10233               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10234               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10235             {
10236               op0 = XEXP (op0, 1);
10237               code = (code == GE ? GT : LE);
10238               continue;
10239             }
10240           break;
10241
10242         case AND:
10243           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10244              will be converted to a ZERO_EXTRACT later.  */
10245           if (const_op == 0 && equality_comparison_p
10246               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10247               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10248             {
10249               op0 = simplify_and_const_int
10250                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10251                                                    XEXP (op0, 1),
10252                                                    XEXP (XEXP (op0, 0), 1)),
10253                  (HOST_WIDE_INT) 1);
10254               continue;
10255             }
10256
10257           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10258              zero and X is a comparison and C1 and C2 describe only bits set
10259              in STORE_FLAG_VALUE, we can compare with X.  */
10260           if (const_op == 0 && equality_comparison_p
10261               && mode_width <= HOST_BITS_PER_WIDE_INT
10262               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10263               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10264               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10265               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10266               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10267             {
10268               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10269                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10270               if ((~STORE_FLAG_VALUE & mask) == 0
10271                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10272                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10273                           && COMPARISON_P (tem))))
10274                 {
10275                   op0 = XEXP (XEXP (op0, 0), 0);
10276                   continue;
10277                 }
10278             }
10279
10280           /* If we are doing an equality comparison of an AND of a bit equal
10281              to the sign bit, replace this with a LT or GE comparison of
10282              the underlying value.  */
10283           if (equality_comparison_p
10284               && const_op == 0
10285               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10286               && mode_width <= HOST_BITS_PER_WIDE_INT
10287               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10288                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10289             {
10290               op0 = XEXP (op0, 0);
10291               code = (code == EQ ? GE : LT);
10292               continue;
10293             }
10294
10295           /* If this AND operation is really a ZERO_EXTEND from a narrower
10296              mode, the constant fits within that mode, and this is either an
10297              equality or unsigned comparison, try to do this comparison in
10298              the narrower mode.
10299
10300              Note that in:
10301
10302              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10303              -> (ne:DI (reg:SI 4) (const_int 0))
10304
10305              unless TRULY_NOOP_TRUNCATION allows it or the register is
10306              known to hold a value of the required mode the
10307              transformation is invalid.  */
10308           if ((equality_comparison_p || unsigned_comparison_p)
10309               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10310               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10311                                    & GET_MODE_MASK (mode))
10312                                   + 1)) >= 0
10313               && const_op >> i == 0
10314               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10315               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10316                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10317                   || (REG_P (XEXP (op0, 0))
10318                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10319             {
10320               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10321               continue;
10322             }
10323
10324           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10325              fits in both M1 and M2 and the SUBREG is either paradoxical
10326              or represents the low part, permute the SUBREG and the AND
10327              and try again.  */
10328           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10329             {
10330               unsigned HOST_WIDE_INT c1;
10331               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10332               /* Require an integral mode, to avoid creating something like
10333                  (AND:SF ...).  */
10334               if (SCALAR_INT_MODE_P (tmode)
10335                   /* It is unsafe to commute the AND into the SUBREG if the
10336                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10337                      not defined.  As originally written the upper bits
10338                      have a defined value due to the AND operation.
10339                      However, if we commute the AND inside the SUBREG then
10340                      they no longer have defined values and the meaning of
10341                      the code has been changed.  */
10342                   && (0
10343 #ifdef WORD_REGISTER_OPERATIONS
10344                       || (mode_width > GET_MODE_BITSIZE (tmode)
10345                           && mode_width <= BITS_PER_WORD)
10346 #endif
10347                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10348                           && subreg_lowpart_p (XEXP (op0, 0))))
10349                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10350                   && mode_width <= HOST_BITS_PER_WIDE_INT
10351                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10352                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10353                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10354                   && c1 != mask
10355                   && c1 != GET_MODE_MASK (tmode))
10356                 {
10357                   op0 = simplify_gen_binary (AND, tmode,
10358                                              SUBREG_REG (XEXP (op0, 0)),
10359                                              gen_int_mode (c1, tmode));
10360                   op0 = gen_lowpart (mode, op0);
10361                   continue;
10362                 }
10363             }
10364
10365           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10366           if (const_op == 0 && equality_comparison_p
10367               && XEXP (op0, 1) == const1_rtx
10368               && GET_CODE (XEXP (op0, 0)) == NOT)
10369             {
10370               op0 = simplify_and_const_int
10371                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10372               code = (code == NE ? EQ : NE);
10373               continue;
10374             }
10375
10376           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10377              (eq (and (lshiftrt X) 1) 0).
10378              Also handle the case where (not X) is expressed using xor.  */
10379           if (const_op == 0 && equality_comparison_p
10380               && XEXP (op0, 1) == const1_rtx
10381               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10382             {
10383               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10384               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10385
10386               if (GET_CODE (shift_op) == NOT
10387                   || (GET_CODE (shift_op) == XOR
10388                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10389                       && GET_CODE (shift_count) == CONST_INT
10390                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10391                       && (INTVAL (XEXP (shift_op, 1))
10392                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10393                 {
10394                   op0 = simplify_and_const_int
10395                     (NULL_RTX, mode,
10396                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10397                      (HOST_WIDE_INT) 1);
10398                   code = (code == NE ? EQ : NE);
10399                   continue;
10400                 }
10401             }
10402           break;
10403
10404         case ASHIFT:
10405           /* If we have (compare (ashift FOO N) (const_int C)) and
10406              the high order N bits of FOO (N+1 if an inequality comparison)
10407              are known to be zero, we can do this by comparing FOO with C
10408              shifted right N bits so long as the low-order N bits of C are
10409              zero.  */
10410           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10411               && INTVAL (XEXP (op0, 1)) >= 0
10412               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10413                   < HOST_BITS_PER_WIDE_INT)
10414               && ((const_op
10415                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10416               && mode_width <= HOST_BITS_PER_WIDE_INT
10417               && (nonzero_bits (XEXP (op0, 0), mode)
10418                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10419                                + ! equality_comparison_p))) == 0)
10420             {
10421               /* We must perform a logical shift, not an arithmetic one,
10422                  as we want the top N bits of C to be zero.  */
10423               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10424
10425               temp >>= INTVAL (XEXP (op0, 1));
10426               op1 = gen_int_mode (temp, mode);
10427               op0 = XEXP (op0, 0);
10428               continue;
10429             }
10430
10431           /* If we are doing a sign bit comparison, it means we are testing
10432              a particular bit.  Convert it to the appropriate AND.  */
10433           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10434               && mode_width <= HOST_BITS_PER_WIDE_INT)
10435             {
10436               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10437                                             ((HOST_WIDE_INT) 1
10438                                              << (mode_width - 1
10439                                                  - INTVAL (XEXP (op0, 1)))));
10440               code = (code == LT ? NE : EQ);
10441               continue;
10442             }
10443
10444           /* If this an equality comparison with zero and we are shifting
10445              the low bit to the sign bit, we can convert this to an AND of the
10446              low-order bit.  */
10447           if (const_op == 0 && equality_comparison_p
10448               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10449               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10450                  == mode_width - 1)
10451             {
10452               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10453                                             (HOST_WIDE_INT) 1);
10454               continue;
10455             }
10456           break;
10457
10458         case ASHIFTRT:
10459           /* If this is an equality comparison with zero, we can do this
10460              as a logical shift, which might be much simpler.  */
10461           if (equality_comparison_p && const_op == 0
10462               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10463             {
10464               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10465                                           XEXP (op0, 0),
10466                                           INTVAL (XEXP (op0, 1)));
10467               continue;
10468             }
10469
10470           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10471              do the comparison in a narrower mode.  */
10472           if (! unsigned_comparison_p
10473               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10474               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10475               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10476               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10477                                          MODE_INT, 1)) != BLKmode
10478               && (((unsigned HOST_WIDE_INT) const_op
10479                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10480                   <= GET_MODE_MASK (tmode)))
10481             {
10482               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10483               continue;
10484             }
10485
10486           /* Likewise if OP0 is a PLUS of a sign extension with a
10487              constant, which is usually represented with the PLUS
10488              between the shifts.  */
10489           if (! unsigned_comparison_p
10490               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10491               && GET_CODE (XEXP (op0, 0)) == PLUS
10492               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10493               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10494               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10495               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10496                                          MODE_INT, 1)) != BLKmode
10497               && (((unsigned HOST_WIDE_INT) const_op
10498                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10499                   <= GET_MODE_MASK (tmode)))
10500             {
10501               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10502               rtx add_const = XEXP (XEXP (op0, 0), 1);
10503               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10504                                                    add_const, XEXP (op0, 1));
10505
10506               op0 = simplify_gen_binary (PLUS, tmode,
10507                                          gen_lowpart (tmode, inner),
10508                                          new_const);
10509               continue;
10510             }
10511
10512           /* ... fall through ...  */
10513         case LSHIFTRT:
10514           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10515              the low order N bits of FOO are known to be zero, we can do this
10516              by comparing FOO with C shifted left N bits so long as no
10517              overflow occurs.  */
10518           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10519               && INTVAL (XEXP (op0, 1)) >= 0
10520               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10521               && mode_width <= HOST_BITS_PER_WIDE_INT
10522               && (nonzero_bits (XEXP (op0, 0), mode)
10523                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10524               && (((unsigned HOST_WIDE_INT) const_op
10525                    + (GET_CODE (op0) != LSHIFTRT
10526                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10527                          + 1)
10528                       : 0))
10529                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10530             {
10531               /* If the shift was logical, then we must make the condition
10532                  unsigned.  */
10533               if (GET_CODE (op0) == LSHIFTRT)
10534                 code = unsigned_condition (code);
10535
10536               const_op <<= INTVAL (XEXP (op0, 1));
10537               op1 = GEN_INT (const_op);
10538               op0 = XEXP (op0, 0);
10539               continue;
10540             }
10541
10542           /* If we are using this shift to extract just the sign bit, we
10543              can replace this with an LT or GE comparison.  */
10544           if (const_op == 0
10545               && (equality_comparison_p || sign_bit_comparison_p)
10546               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10547               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10548                  == mode_width - 1)
10549             {
10550               op0 = XEXP (op0, 0);
10551               code = (code == NE || code == GT ? LT : GE);
10552               continue;
10553             }
10554           break;
10555
10556         default:
10557           break;
10558         }
10559
10560       break;
10561     }
10562
10563   /* Now make any compound operations involved in this comparison.  Then,
10564      check for an outmost SUBREG on OP0 that is not doing anything or is
10565      paradoxical.  The latter transformation must only be performed when
10566      it is known that the "extra" bits will be the same in op0 and op1 or
10567      that they don't matter.  There are three cases to consider:
10568
10569      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10570      care bits and we can assume they have any convenient value.  So
10571      making the transformation is safe.
10572
10573      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10574      In this case the upper bits of op0 are undefined.  We should not make
10575      the simplification in that case as we do not know the contents of
10576      those bits.
10577
10578      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10579      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10580      also be sure that they are the same as the upper bits of op1.
10581
10582      We can never remove a SUBREG for a non-equality comparison because
10583      the sign bit is in a different place in the underlying object.  */
10584
10585   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10586   op1 = make_compound_operation (op1, SET);
10587
10588   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10589       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10590       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10591       && (code == NE || code == EQ))
10592     {
10593       if (GET_MODE_SIZE (GET_MODE (op0))
10594           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10595         {
10596           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10597              implemented.  */
10598           if (REG_P (SUBREG_REG (op0)))
10599             {
10600               op0 = SUBREG_REG (op0);
10601               op1 = gen_lowpart (GET_MODE (op0), op1);
10602             }
10603         }
10604       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10605                 <= HOST_BITS_PER_WIDE_INT)
10606                && (nonzero_bits (SUBREG_REG (op0),
10607                                  GET_MODE (SUBREG_REG (op0)))
10608                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10609         {
10610           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10611
10612           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10613                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10614             op0 = SUBREG_REG (op0), op1 = tem;
10615         }
10616     }
10617
10618   /* We now do the opposite procedure: Some machines don't have compare
10619      insns in all modes.  If OP0's mode is an integer mode smaller than a
10620      word and we can't do a compare in that mode, see if there is a larger
10621      mode for which we can do the compare.  There are a number of cases in
10622      which we can use the wider mode.  */
10623
10624   mode = GET_MODE (op0);
10625   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10626       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10627       && ! have_insn_for (COMPARE, mode))
10628     for (tmode = GET_MODE_WIDER_MODE (mode);
10629          (tmode != VOIDmode
10630           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10631          tmode = GET_MODE_WIDER_MODE (tmode))
10632       if (have_insn_for (COMPARE, tmode))
10633         {
10634           int zero_extended;
10635
10636           /* If the only nonzero bits in OP0 and OP1 are those in the
10637              narrower mode and this is an equality or unsigned comparison,
10638              we can use the wider mode.  Similarly for sign-extended
10639              values, in which case it is true for all comparisons.  */
10640           zero_extended = ((code == EQ || code == NE
10641                             || code == GEU || code == GTU
10642                             || code == LEU || code == LTU)
10643                            && (nonzero_bits (op0, tmode)
10644                                & ~GET_MODE_MASK (mode)) == 0
10645                            && ((GET_CODE (op1) == CONST_INT
10646                                 || (nonzero_bits (op1, tmode)
10647                                     & ~GET_MODE_MASK (mode)) == 0)));
10648
10649           if (zero_extended
10650               || ((num_sign_bit_copies (op0, tmode)
10651                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10652                                      - GET_MODE_BITSIZE (mode)))
10653                   && (num_sign_bit_copies (op1, tmode)
10654                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10655                                         - GET_MODE_BITSIZE (mode)))))
10656             {
10657               /* If OP0 is an AND and we don't have an AND in MODE either,
10658                  make a new AND in the proper mode.  */
10659               if (GET_CODE (op0) == AND
10660                   && !have_insn_for (AND, mode))
10661                 op0 = simplify_gen_binary (AND, tmode,
10662                                            gen_lowpart (tmode,
10663                                                         XEXP (op0, 0)),
10664                                            gen_lowpart (tmode,
10665                                                         XEXP (op0, 1)));
10666
10667               op0 = gen_lowpart (tmode, op0);
10668               if (zero_extended && GET_CODE (op1) == CONST_INT)
10669                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10670               op1 = gen_lowpart (tmode, op1);
10671               break;
10672             }
10673
10674           /* If this is a test for negative, we can make an explicit
10675              test of the sign bit.  */
10676
10677           if (op1 == const0_rtx && (code == LT || code == GE)
10678               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10679             {
10680               op0 = simplify_gen_binary (AND, tmode,
10681                                          gen_lowpart (tmode, op0),
10682                                          GEN_INT ((HOST_WIDE_INT) 1
10683                                                   << (GET_MODE_BITSIZE (mode)
10684                                                       - 1)));
10685               code = (code == LT) ? NE : EQ;
10686               break;
10687             }
10688         }
10689
10690 #ifdef CANONICALIZE_COMPARISON
10691   /* If this machine only supports a subset of valid comparisons, see if we
10692      can convert an unsupported one into a supported one.  */
10693   CANONICALIZE_COMPARISON (code, op0, op1);
10694 #endif
10695
10696   *pop0 = op0;
10697   *pop1 = op1;
10698
10699   return code;
10700 }
10701 \f
10702 /* Utility function for record_value_for_reg.  Count number of
10703    rtxs in X.  */
10704 static int
10705 count_rtxs (rtx x)
10706 {
10707   enum rtx_code code = GET_CODE (x);
10708   const char *fmt;
10709   int i, ret = 1;
10710
10711   if (GET_RTX_CLASS (code) == '2'
10712       || GET_RTX_CLASS (code) == 'c')
10713     {
10714       rtx x0 = XEXP (x, 0);
10715       rtx x1 = XEXP (x, 1);
10716
10717       if (x0 == x1)
10718         return 1 + 2 * count_rtxs (x0);
10719
10720       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10721            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10722           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10723         return 2 + 2 * count_rtxs (x0)
10724                + count_rtxs (x == XEXP (x1, 0)
10725                              ? XEXP (x1, 1) : XEXP (x1, 0));
10726
10727       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10728            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10729           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10730         return 2 + 2 * count_rtxs (x1)
10731                + count_rtxs (x == XEXP (x0, 0)
10732                              ? XEXP (x0, 1) : XEXP (x0, 0));
10733     }
10734
10735   fmt = GET_RTX_FORMAT (code);
10736   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10737     if (fmt[i] == 'e')
10738       ret += count_rtxs (XEXP (x, i));
10739
10740   return ret;
10741 }
10742 \f
10743 /* Utility function for following routine.  Called when X is part of a value
10744    being stored into last_set_value.  Sets last_set_table_tick
10745    for each register mentioned.  Similar to mention_regs in cse.c  */
10746
10747 static void
10748 update_table_tick (rtx x)
10749 {
10750   enum rtx_code code = GET_CODE (x);
10751   const char *fmt = GET_RTX_FORMAT (code);
10752   int i;
10753
10754   if (code == REG)
10755     {
10756       unsigned int regno = REGNO (x);
10757       unsigned int endregno
10758         = regno + (regno < FIRST_PSEUDO_REGISTER
10759                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10760       unsigned int r;
10761
10762       for (r = regno; r < endregno; r++)
10763         reg_stat[r].last_set_table_tick = label_tick;
10764
10765       return;
10766     }
10767
10768   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10769     /* Note that we can't have an "E" in values stored; see
10770        get_last_value_validate.  */
10771     if (fmt[i] == 'e')
10772       {
10773         /* Check for identical subexpressions.  If x contains
10774            identical subexpression we only have to traverse one of
10775            them.  */
10776         if (i == 0 && ARITHMETIC_P (x))
10777           {
10778             /* Note that at this point x1 has already been
10779                processed.  */
10780             rtx x0 = XEXP (x, 0);
10781             rtx x1 = XEXP (x, 1);
10782
10783             /* If x0 and x1 are identical then there is no need to
10784                process x0.  */
10785             if (x0 == x1)
10786               break;
10787
10788             /* If x0 is identical to a subexpression of x1 then while
10789                processing x1, x0 has already been processed.  Thus we
10790                are done with x.  */
10791             if (ARITHMETIC_P (x1)
10792                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10793               break;
10794
10795             /* If x1 is identical to a subexpression of x0 then we
10796                still have to process the rest of x0.  */
10797             if (ARITHMETIC_P (x0)
10798                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10799               {
10800                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10801                 break;
10802               }
10803           }
10804
10805         update_table_tick (XEXP (x, i));
10806       }
10807 }
10808
10809 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10810    are saying that the register is clobbered and we no longer know its
10811    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10812    only permitted with VALUE also zero and is used to invalidate the
10813    register.  */
10814
10815 static void
10816 record_value_for_reg (rtx reg, rtx insn, rtx value)
10817 {
10818   unsigned int regno = REGNO (reg);
10819   unsigned int endregno
10820     = regno + (regno < FIRST_PSEUDO_REGISTER
10821                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10822   unsigned int i;
10823
10824   /* If VALUE contains REG and we have a previous value for REG, substitute
10825      the previous value.  */
10826   if (value && insn && reg_overlap_mentioned_p (reg, value))
10827     {
10828       rtx tem;
10829
10830       /* Set things up so get_last_value is allowed to see anything set up to
10831          our insn.  */
10832       subst_low_cuid = INSN_CUID (insn);
10833       tem = get_last_value (reg);
10834
10835       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10836          it isn't going to be useful and will take a lot of time to process,
10837          so just use the CLOBBER.  */
10838
10839       if (tem)
10840         {
10841           if (ARITHMETIC_P (tem)
10842               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10843               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10844             tem = XEXP (tem, 0);
10845           else if (count_occurrences (value, reg, 1) >= 2)
10846             {
10847               /* If there are two or more occurrences of REG in VALUE,
10848                  prevent the value from growing too much.  */
10849               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10850                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10851             }
10852
10853           value = replace_rtx (copy_rtx (value), reg, tem);
10854         }
10855     }
10856
10857   /* For each register modified, show we don't know its value, that
10858      we don't know about its bitwise content, that its value has been
10859      updated, and that we don't know the location of the death of the
10860      register.  */
10861   for (i = regno; i < endregno; i++)
10862     {
10863       if (insn)
10864         reg_stat[i].last_set = insn;
10865
10866       reg_stat[i].last_set_value = 0;
10867       reg_stat[i].last_set_mode = 0;
10868       reg_stat[i].last_set_nonzero_bits = 0;
10869       reg_stat[i].last_set_sign_bit_copies = 0;
10870       reg_stat[i].last_death = 0;
10871       reg_stat[i].truncated_to_mode = 0;
10872     }
10873
10874   /* Mark registers that are being referenced in this value.  */
10875   if (value)
10876     update_table_tick (value);
10877
10878   /* Now update the status of each register being set.
10879      If someone is using this register in this block, set this register
10880      to invalid since we will get confused between the two lives in this
10881      basic block.  This makes using this register always invalid.  In cse, we
10882      scan the table to invalidate all entries using this register, but this
10883      is too much work for us.  */
10884
10885   for (i = regno; i < endregno; i++)
10886     {
10887       reg_stat[i].last_set_label = label_tick;
10888       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10889         reg_stat[i].last_set_invalid = 1;
10890       else
10891         reg_stat[i].last_set_invalid = 0;
10892     }
10893
10894   /* The value being assigned might refer to X (like in "x++;").  In that
10895      case, we must replace it with (clobber (const_int 0)) to prevent
10896      infinite loops.  */
10897   if (value && ! get_last_value_validate (&value, insn,
10898                                           reg_stat[regno].last_set_label, 0))
10899     {
10900       value = copy_rtx (value);
10901       if (! get_last_value_validate (&value, insn,
10902                                      reg_stat[regno].last_set_label, 1))
10903         value = 0;
10904     }
10905
10906   /* For the main register being modified, update the value, the mode, the
10907      nonzero bits, and the number of sign bit copies.  */
10908
10909   reg_stat[regno].last_set_value = value;
10910
10911   if (value)
10912     {
10913       enum machine_mode mode = GET_MODE (reg);
10914       subst_low_cuid = INSN_CUID (insn);
10915       reg_stat[regno].last_set_mode = mode;
10916       if (GET_MODE_CLASS (mode) == MODE_INT
10917           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10918         mode = nonzero_bits_mode;
10919       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10920       reg_stat[regno].last_set_sign_bit_copies
10921         = num_sign_bit_copies (value, GET_MODE (reg));
10922     }
10923 }
10924
10925 /* Called via note_stores from record_dead_and_set_regs to handle one
10926    SET or CLOBBER in an insn.  DATA is the instruction in which the
10927    set is occurring.  */
10928
10929 static void
10930 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10931 {
10932   rtx record_dead_insn = (rtx) data;
10933
10934   if (GET_CODE (dest) == SUBREG)
10935     dest = SUBREG_REG (dest);
10936
10937   if (!record_dead_insn)
10938     {
10939       if (REG_P (dest))
10940         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10941       return;
10942     }
10943
10944   if (REG_P (dest))
10945     {
10946       /* If we are setting the whole register, we know its value.  Otherwise
10947          show that we don't know the value.  We can handle SUBREG in
10948          some cases.  */
10949       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10950         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10951       else if (GET_CODE (setter) == SET
10952                && GET_CODE (SET_DEST (setter)) == SUBREG
10953                && SUBREG_REG (SET_DEST (setter)) == dest
10954                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10955                && subreg_lowpart_p (SET_DEST (setter)))
10956         record_value_for_reg (dest, record_dead_insn,
10957                               gen_lowpart (GET_MODE (dest),
10958                                                        SET_SRC (setter)));
10959       else
10960         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10961     }
10962   else if (MEM_P (dest)
10963            /* Ignore pushes, they clobber nothing.  */
10964            && ! push_operand (dest, GET_MODE (dest)))
10965     mem_last_set = INSN_CUID (record_dead_insn);
10966 }
10967
10968 /* Update the records of when each REG was most recently set or killed
10969    for the things done by INSN.  This is the last thing done in processing
10970    INSN in the combiner loop.
10971
10972    We update reg_stat[], in particular fields last_set, last_set_value,
10973    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10974    last_death, and also the similar information mem_last_set (which insn
10975    most recently modified memory) and last_call_cuid (which insn was the
10976    most recent subroutine call).  */
10977
10978 static void
10979 record_dead_and_set_regs (rtx insn)
10980 {
10981   rtx link;
10982   unsigned int i;
10983
10984   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10985     {
10986       if (REG_NOTE_KIND (link) == REG_DEAD
10987           && REG_P (XEXP (link, 0)))
10988         {
10989           unsigned int regno = REGNO (XEXP (link, 0));
10990           unsigned int endregno
10991             = regno + (regno < FIRST_PSEUDO_REGISTER
10992                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10993                        : 1);
10994
10995           for (i = regno; i < endregno; i++)
10996             reg_stat[i].last_death = insn;
10997         }
10998       else if (REG_NOTE_KIND (link) == REG_INC)
10999         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11000     }
11001
11002   if (CALL_P (insn))
11003     {
11004       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11005         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11006           {
11007             reg_stat[i].last_set_value = 0;
11008             reg_stat[i].last_set_mode = 0;
11009             reg_stat[i].last_set_nonzero_bits = 0;
11010             reg_stat[i].last_set_sign_bit_copies = 0;
11011             reg_stat[i].last_death = 0;
11012             reg_stat[i].truncated_to_mode = 0;
11013           }
11014
11015       last_call_cuid = mem_last_set = INSN_CUID (insn);
11016
11017       /* We can't combine into a call pattern.  Remember, though, that
11018          the return value register is set at this CUID.  We could
11019          still replace a register with the return value from the
11020          wrong subroutine call!  */
11021       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11022     }
11023   else
11024     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11025 }
11026
11027 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11028    register present in the SUBREG, so for each such SUBREG go back and
11029    adjust nonzero and sign bit information of the registers that are
11030    known to have some zero/sign bits set.
11031
11032    This is needed because when combine blows the SUBREGs away, the
11033    information on zero/sign bits is lost and further combines can be
11034    missed because of that.  */
11035
11036 static void
11037 record_promoted_value (rtx insn, rtx subreg)
11038 {
11039   rtx links, set;
11040   unsigned int regno = REGNO (SUBREG_REG (subreg));
11041   enum machine_mode mode = GET_MODE (subreg);
11042
11043   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11044     return;
11045
11046   for (links = LOG_LINKS (insn); links;)
11047     {
11048       insn = XEXP (links, 0);
11049       set = single_set (insn);
11050
11051       if (! set || !REG_P (SET_DEST (set))
11052           || REGNO (SET_DEST (set)) != regno
11053           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11054         {
11055           links = XEXP (links, 1);
11056           continue;
11057         }
11058
11059       if (reg_stat[regno].last_set == insn)
11060         {
11061           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11062             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11063         }
11064
11065       if (REG_P (SET_SRC (set)))
11066         {
11067           regno = REGNO (SET_SRC (set));
11068           links = LOG_LINKS (insn);
11069         }
11070       else
11071         break;
11072     }
11073 }
11074
11075 /* Check if X, a register, is known to contain a value already
11076    truncated to MODE.  In this case we can use a subreg to refer to
11077    the truncated value even though in the generic case we would need
11078    an explicit truncation.  */
11079
11080 static bool
11081 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11082 {
11083   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11084
11085   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11086     return false;
11087   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11088     return true;
11089   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11090                              GET_MODE_BITSIZE (truncated)))
11091     return true;
11092   return false;
11093 }
11094
11095 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11096    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11097    a truncate into a subreg using this information.  */
11098
11099 static void
11100 record_truncated_value (rtx x)
11101 {
11102   enum machine_mode truncated_mode;
11103
11104   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11105     {
11106       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11107       truncated_mode = GET_MODE (x);
11108
11109       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11110         return;
11111
11112       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11113                                  GET_MODE_BITSIZE (original_mode)))
11114         return;
11115
11116       x = SUBREG_REG (x);
11117     }
11118   /* ??? For hard-regs we now record everthing.  We might be able to
11119      optimize this using last_set_mode.  */
11120   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11121     truncated_mode = GET_MODE (x);
11122   else
11123     return;
11124
11125   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11126       || reg_stat[REGNO (x)].truncation_label < label_tick
11127       || (GET_MODE_SIZE (truncated_mode)
11128           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11129     {
11130       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11131       reg_stat[REGNO (x)].truncation_label = label_tick;
11132     }
11133 }
11134
11135 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11136    found, note what it implies to the registers used in it.  */
11137
11138 static void
11139 check_conversions (rtx insn, rtx x)
11140 {
11141   if (GET_CODE (x) == SUBREG || REG_P (x))
11142     {
11143       if (GET_CODE (x) == SUBREG
11144           && SUBREG_PROMOTED_VAR_P (x)
11145           && REG_P (SUBREG_REG (x)))
11146         record_promoted_value (insn, x);
11147
11148       record_truncated_value (x);
11149     }
11150   else
11151     {
11152       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11153       int i, j;
11154
11155       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11156         switch (format[i])
11157           {
11158           case 'e':
11159             check_conversions (insn, XEXP (x, i));
11160             break;
11161           case 'V':
11162           case 'E':
11163             if (XVEC (x, i) != 0)
11164               for (j = 0; j < XVECLEN (x, i); j++)
11165                 check_conversions (insn, XVECEXP (x, i, j));
11166             break;
11167           }
11168     }
11169 }
11170 \f
11171 /* Utility routine for the following function.  Verify that all the registers
11172    mentioned in *LOC are valid when *LOC was part of a value set when
11173    label_tick == TICK.  Return 0 if some are not.
11174
11175    If REPLACE is nonzero, replace the invalid reference with
11176    (clobber (const_int 0)) and return 1.  This replacement is useful because
11177    we often can get useful information about the form of a value (e.g., if
11178    it was produced by a shift that always produces -1 or 0) even though
11179    we don't know exactly what registers it was produced from.  */
11180
11181 static int
11182 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11183 {
11184   rtx x = *loc;
11185   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11186   int len = GET_RTX_LENGTH (GET_CODE (x));
11187   int i;
11188
11189   if (REG_P (x))
11190     {
11191       unsigned int regno = REGNO (x);
11192       unsigned int endregno
11193         = regno + (regno < FIRST_PSEUDO_REGISTER
11194                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11195       unsigned int j;
11196
11197       for (j = regno; j < endregno; j++)
11198         if (reg_stat[j].last_set_invalid
11199             /* If this is a pseudo-register that was only set once and not
11200                live at the beginning of the function, it is always valid.  */
11201             || (! (regno >= FIRST_PSEUDO_REGISTER
11202                    && REG_N_SETS (regno) == 1
11203                    && (! REGNO_REG_SET_P
11204                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11205                         regno)))
11206                 && reg_stat[j].last_set_label > tick))
11207           {
11208             if (replace)
11209               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11210             return replace;
11211           }
11212
11213       return 1;
11214     }
11215   /* If this is a memory reference, make sure that there were
11216      no stores after it that might have clobbered the value.  We don't
11217      have alias info, so we assume any store invalidates it.  */
11218   else if (MEM_P (x) && !MEM_READONLY_P (x)
11219            && INSN_CUID (insn) <= mem_last_set)
11220     {
11221       if (replace)
11222         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11223       return replace;
11224     }
11225
11226   for (i = 0; i < len; i++)
11227     {
11228       if (fmt[i] == 'e')
11229         {
11230           /* Check for identical subexpressions.  If x contains
11231              identical subexpression we only have to traverse one of
11232              them.  */
11233           if (i == 1 && ARITHMETIC_P (x))
11234             {
11235               /* Note that at this point x0 has already been checked
11236                  and found valid.  */
11237               rtx x0 = XEXP (x, 0);
11238               rtx x1 = XEXP (x, 1);
11239
11240               /* If x0 and x1 are identical then x is also valid.  */
11241               if (x0 == x1)
11242                 return 1;
11243
11244               /* If x1 is identical to a subexpression of x0 then
11245                  while checking x0, x1 has already been checked.  Thus
11246                  it is valid and so as x.  */
11247               if (ARITHMETIC_P (x0)
11248                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11249                 return 1;
11250
11251               /* If x0 is identical to a subexpression of x1 then x is
11252                  valid iff the rest of x1 is valid.  */
11253               if (ARITHMETIC_P (x1)
11254                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11255                 return
11256                   get_last_value_validate (&XEXP (x1,
11257                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11258                                            insn, tick, replace);
11259             }
11260
11261           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11262                                        replace) == 0)
11263             return 0;
11264         }
11265       /* Don't bother with these.  They shouldn't occur anyway.  */
11266       else if (fmt[i] == 'E')
11267         return 0;
11268     }
11269
11270   /* If we haven't found a reason for it to be invalid, it is valid.  */
11271   return 1;
11272 }
11273
11274 /* Get the last value assigned to X, if known.  Some registers
11275    in the value may be replaced with (clobber (const_int 0)) if their value
11276    is known longer known reliably.  */
11277
11278 static rtx
11279 get_last_value (rtx x)
11280 {
11281   unsigned int regno;
11282   rtx value;
11283
11284   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11285      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11286      we cannot predict what values the "extra" bits might have.  */
11287   if (GET_CODE (x) == SUBREG
11288       && subreg_lowpart_p (x)
11289       && (GET_MODE_SIZE (GET_MODE (x))
11290           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11291       && (value = get_last_value (SUBREG_REG (x))) != 0)
11292     return gen_lowpart (GET_MODE (x), value);
11293
11294   if (!REG_P (x))
11295     return 0;
11296
11297   regno = REGNO (x);
11298   value = reg_stat[regno].last_set_value;
11299
11300   /* If we don't have a value, or if it isn't for this basic block and
11301      it's either a hard register, set more than once, or it's a live
11302      at the beginning of the function, return 0.
11303
11304      Because if it's not live at the beginning of the function then the reg
11305      is always set before being used (is never used without being set).
11306      And, if it's set only once, and it's always set before use, then all
11307      uses must have the same last value, even if it's not from this basic
11308      block.  */
11309
11310   if (value == 0
11311       || (reg_stat[regno].last_set_label != label_tick
11312           && (regno < FIRST_PSEUDO_REGISTER
11313               || REG_N_SETS (regno) != 1
11314               || (REGNO_REG_SET_P
11315                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11316                    regno)))))
11317     return 0;
11318
11319   /* If the value was set in a later insn than the ones we are processing,
11320      we can't use it even if the register was only set once.  */
11321   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11322     return 0;
11323
11324   /* If the value has all its registers valid, return it.  */
11325   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11326                                reg_stat[regno].last_set_label, 0))
11327     return value;
11328
11329   /* Otherwise, make a copy and replace any invalid register with
11330      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11331
11332   value = copy_rtx (value);
11333   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11334                                reg_stat[regno].last_set_label, 1))
11335     return value;
11336
11337   return 0;
11338 }
11339 \f
11340 /* Return nonzero if expression X refers to a REG or to memory
11341    that is set in an instruction more recent than FROM_CUID.  */
11342
11343 static int
11344 use_crosses_set_p (rtx x, int from_cuid)
11345 {
11346   const char *fmt;
11347   int i;
11348   enum rtx_code code = GET_CODE (x);
11349
11350   if (code == REG)
11351     {
11352       unsigned int regno = REGNO (x);
11353       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11354                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11355
11356 #ifdef PUSH_ROUNDING
11357       /* Don't allow uses of the stack pointer to be moved,
11358          because we don't know whether the move crosses a push insn.  */
11359       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11360         return 1;
11361 #endif
11362       for (; regno < endreg; regno++)
11363         if (reg_stat[regno].last_set
11364             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11365           return 1;
11366       return 0;
11367     }
11368
11369   if (code == MEM && mem_last_set > from_cuid)
11370     return 1;
11371
11372   fmt = GET_RTX_FORMAT (code);
11373
11374   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11375     {
11376       if (fmt[i] == 'E')
11377         {
11378           int j;
11379           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11380             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11381               return 1;
11382         }
11383       else if (fmt[i] == 'e'
11384                && use_crosses_set_p (XEXP (x, i), from_cuid))
11385         return 1;
11386     }
11387   return 0;
11388 }
11389 \f
11390 /* Define three variables used for communication between the following
11391    routines.  */
11392
11393 static unsigned int reg_dead_regno, reg_dead_endregno;
11394 static int reg_dead_flag;
11395
11396 /* Function called via note_stores from reg_dead_at_p.
11397
11398    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11399    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11400
11401 static void
11402 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11403 {
11404   unsigned int regno, endregno;
11405
11406   if (!REG_P (dest))
11407     return;
11408
11409   regno = REGNO (dest);
11410   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11411                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11412
11413   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11414     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11415 }
11416
11417 /* Return nonzero if REG is known to be dead at INSN.
11418
11419    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11420    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11421    live.  Otherwise, see if it is live or dead at the start of the basic
11422    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11423    must be assumed to be always live.  */
11424
11425 static int
11426 reg_dead_at_p (rtx reg, rtx insn)
11427 {
11428   basic_block block;
11429   unsigned int i;
11430
11431   /* Set variables for reg_dead_at_p_1.  */
11432   reg_dead_regno = REGNO (reg);
11433   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11434                                         ? hard_regno_nregs[reg_dead_regno]
11435                                                           [GET_MODE (reg)]
11436                                         : 1);
11437
11438   reg_dead_flag = 0;
11439
11440   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11441      we allow the machine description to decide whether use-and-clobber
11442      patterns are OK.  */
11443   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11444     {
11445       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11446         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11447           return 0;
11448     }
11449
11450   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11451      beginning of function.  */
11452   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11453        insn = prev_nonnote_insn (insn))
11454     {
11455       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11456       if (reg_dead_flag)
11457         return reg_dead_flag == 1 ? 1 : 0;
11458
11459       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11460         return 1;
11461     }
11462
11463   /* Get the basic block that we were in.  */
11464   if (insn == 0)
11465     block = ENTRY_BLOCK_PTR->next_bb;
11466   else
11467     {
11468       FOR_EACH_BB (block)
11469         if (insn == BB_HEAD (block))
11470           break;
11471
11472       if (block == EXIT_BLOCK_PTR)
11473         return 0;
11474     }
11475
11476   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11477     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11478       return 0;
11479
11480   return 1;
11481 }
11482 \f
11483 /* Note hard registers in X that are used.  This code is similar to
11484    that in flow.c, but much simpler since we don't care about pseudos.  */
11485
11486 static void
11487 mark_used_regs_combine (rtx x)
11488 {
11489   RTX_CODE code = GET_CODE (x);
11490   unsigned int regno;
11491   int i;
11492
11493   switch (code)
11494     {
11495     case LABEL_REF:
11496     case SYMBOL_REF:
11497     case CONST_INT:
11498     case CONST:
11499     case CONST_DOUBLE:
11500     case CONST_VECTOR:
11501     case PC:
11502     case ADDR_VEC:
11503     case ADDR_DIFF_VEC:
11504     case ASM_INPUT:
11505 #ifdef HAVE_cc0
11506     /* CC0 must die in the insn after it is set, so we don't need to take
11507        special note of it here.  */
11508     case CC0:
11509 #endif
11510       return;
11511
11512     case CLOBBER:
11513       /* If we are clobbering a MEM, mark any hard registers inside the
11514          address as used.  */
11515       if (MEM_P (XEXP (x, 0)))
11516         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11517       return;
11518
11519     case REG:
11520       regno = REGNO (x);
11521       /* A hard reg in a wide mode may really be multiple registers.
11522          If so, mark all of them just like the first.  */
11523       if (regno < FIRST_PSEUDO_REGISTER)
11524         {
11525           unsigned int endregno, r;
11526
11527           /* None of this applies to the stack, frame or arg pointers.  */
11528           if (regno == STACK_POINTER_REGNUM
11529 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11530               || regno == HARD_FRAME_POINTER_REGNUM
11531 #endif
11532 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11533               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11534 #endif
11535               || regno == FRAME_POINTER_REGNUM)
11536             return;
11537
11538           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11539           for (r = regno; r < endregno; r++)
11540             SET_HARD_REG_BIT (newpat_used_regs, r);
11541         }
11542       return;
11543
11544     case SET:
11545       {
11546         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11547            the address.  */
11548         rtx testreg = SET_DEST (x);
11549
11550         while (GET_CODE (testreg) == SUBREG
11551                || GET_CODE (testreg) == ZERO_EXTRACT
11552                || GET_CODE (testreg) == STRICT_LOW_PART)
11553           testreg = XEXP (testreg, 0);
11554
11555         if (MEM_P (testreg))
11556           mark_used_regs_combine (XEXP (testreg, 0));
11557
11558         mark_used_regs_combine (SET_SRC (x));
11559       }
11560       return;
11561
11562     default:
11563       break;
11564     }
11565
11566   /* Recursively scan the operands of this expression.  */
11567
11568   {
11569     const char *fmt = GET_RTX_FORMAT (code);
11570
11571     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11572       {
11573         if (fmt[i] == 'e')
11574           mark_used_regs_combine (XEXP (x, i));
11575         else if (fmt[i] == 'E')
11576           {
11577             int j;
11578
11579             for (j = 0; j < XVECLEN (x, i); j++)
11580               mark_used_regs_combine (XVECEXP (x, i, j));
11581           }
11582       }
11583   }
11584 }
11585 \f
11586 /* Remove register number REGNO from the dead registers list of INSN.
11587
11588    Return the note used to record the death, if there was one.  */
11589
11590 rtx
11591 remove_death (unsigned int regno, rtx insn)
11592 {
11593   rtx note = find_regno_note (insn, REG_DEAD, regno);
11594
11595   if (note)
11596     {
11597       REG_N_DEATHS (regno)--;
11598       remove_note (insn, note);
11599     }
11600
11601   return note;
11602 }
11603
11604 /* For each register (hardware or pseudo) used within expression X, if its
11605    death is in an instruction with cuid between FROM_CUID (inclusive) and
11606    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11607    list headed by PNOTES.
11608
11609    That said, don't move registers killed by maybe_kill_insn.
11610
11611    This is done when X is being merged by combination into TO_INSN.  These
11612    notes will then be distributed as needed.  */
11613
11614 static void
11615 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11616              rtx *pnotes)
11617 {
11618   const char *fmt;
11619   int len, i;
11620   enum rtx_code code = GET_CODE (x);
11621
11622   if (code == REG)
11623     {
11624       unsigned int regno = REGNO (x);
11625       rtx where_dead = reg_stat[regno].last_death;
11626       rtx before_dead, after_dead;
11627
11628       /* Don't move the register if it gets killed in between from and to.  */
11629       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11630           && ! reg_referenced_p (x, maybe_kill_insn))
11631         return;
11632
11633       /* WHERE_DEAD could be a USE insn made by combine, so first we
11634          make sure that we have insns with valid INSN_CUID values.  */
11635       before_dead = where_dead;
11636       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11637         before_dead = PREV_INSN (before_dead);
11638
11639       after_dead = where_dead;
11640       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11641         after_dead = NEXT_INSN (after_dead);
11642
11643       if (before_dead && after_dead
11644           && INSN_CUID (before_dead) >= from_cuid
11645           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11646               || (where_dead != after_dead
11647                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11648         {
11649           rtx note = remove_death (regno, where_dead);
11650
11651           /* It is possible for the call above to return 0.  This can occur
11652              when last_death points to I2 or I1 that we combined with.
11653              In that case make a new note.
11654
11655              We must also check for the case where X is a hard register
11656              and NOTE is a death note for a range of hard registers
11657              including X.  In that case, we must put REG_DEAD notes for
11658              the remaining registers in place of NOTE.  */
11659
11660           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11661               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11662                   > GET_MODE_SIZE (GET_MODE (x))))
11663             {
11664               unsigned int deadregno = REGNO (XEXP (note, 0));
11665               unsigned int deadend
11666                 = (deadregno + hard_regno_nregs[deadregno]
11667                                                [GET_MODE (XEXP (note, 0))]);
11668               unsigned int ourend
11669                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11670               unsigned int i;
11671
11672               for (i = deadregno; i < deadend; i++)
11673                 if (i < regno || i >= ourend)
11674                   REG_NOTES (where_dead)
11675                     = gen_rtx_EXPR_LIST (REG_DEAD,
11676                                          regno_reg_rtx[i],
11677                                          REG_NOTES (where_dead));
11678             }
11679
11680           /* If we didn't find any note, or if we found a REG_DEAD note that
11681              covers only part of the given reg, and we have a multi-reg hard
11682              register, then to be safe we must check for REG_DEAD notes
11683              for each register other than the first.  They could have
11684              their own REG_DEAD notes lying around.  */
11685           else if ((note == 0
11686                     || (note != 0
11687                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11688                             < GET_MODE_SIZE (GET_MODE (x)))))
11689                    && regno < FIRST_PSEUDO_REGISTER
11690                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11691             {
11692               unsigned int ourend
11693                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11694               unsigned int i, offset;
11695               rtx oldnotes = 0;
11696
11697               if (note)
11698                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11699               else
11700                 offset = 1;
11701
11702               for (i = regno + offset; i < ourend; i++)
11703                 move_deaths (regno_reg_rtx[i],
11704                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11705             }
11706
11707           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11708             {
11709               XEXP (note, 1) = *pnotes;
11710               *pnotes = note;
11711             }
11712           else
11713             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11714
11715           REG_N_DEATHS (regno)++;
11716         }
11717
11718       return;
11719     }
11720
11721   else if (GET_CODE (x) == SET)
11722     {
11723       rtx dest = SET_DEST (x);
11724
11725       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11726
11727       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11728          that accesses one word of a multi-word item, some
11729          piece of everything register in the expression is used by
11730          this insn, so remove any old death.  */
11731       /* ??? So why do we test for equality of the sizes?  */
11732
11733       if (GET_CODE (dest) == ZERO_EXTRACT
11734           || GET_CODE (dest) == STRICT_LOW_PART
11735           || (GET_CODE (dest) == SUBREG
11736               && (((GET_MODE_SIZE (GET_MODE (dest))
11737                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11738                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11739                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11740         {
11741           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11742           return;
11743         }
11744
11745       /* If this is some other SUBREG, we know it replaces the entire
11746          value, so use that as the destination.  */
11747       if (GET_CODE (dest) == SUBREG)
11748         dest = SUBREG_REG (dest);
11749
11750       /* If this is a MEM, adjust deaths of anything used in the address.
11751          For a REG (the only other possibility), the entire value is
11752          being replaced so the old value is not used in this insn.  */
11753
11754       if (MEM_P (dest))
11755         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11756                      to_insn, pnotes);
11757       return;
11758     }
11759
11760   else if (GET_CODE (x) == CLOBBER)
11761     return;
11762
11763   len = GET_RTX_LENGTH (code);
11764   fmt = GET_RTX_FORMAT (code);
11765
11766   for (i = 0; i < len; i++)
11767     {
11768       if (fmt[i] == 'E')
11769         {
11770           int j;
11771           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11772             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11773                          to_insn, pnotes);
11774         }
11775       else if (fmt[i] == 'e')
11776         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11777     }
11778 }
11779 \f
11780 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11781    pattern of an insn.  X must be a REG.  */
11782
11783 static int
11784 reg_bitfield_target_p (rtx x, rtx body)
11785 {
11786   int i;
11787
11788   if (GET_CODE (body) == SET)
11789     {
11790       rtx dest = SET_DEST (body);
11791       rtx target;
11792       unsigned int regno, tregno, endregno, endtregno;
11793
11794       if (GET_CODE (dest) == ZERO_EXTRACT)
11795         target = XEXP (dest, 0);
11796       else if (GET_CODE (dest) == STRICT_LOW_PART)
11797         target = SUBREG_REG (XEXP (dest, 0));
11798       else
11799         return 0;
11800
11801       if (GET_CODE (target) == SUBREG)
11802         target = SUBREG_REG (target);
11803
11804       if (!REG_P (target))
11805         return 0;
11806
11807       tregno = REGNO (target), regno = REGNO (x);
11808       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11809         return target == x;
11810
11811       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11812       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11813
11814       return endregno > tregno && regno < endtregno;
11815     }
11816
11817   else if (GET_CODE (body) == PARALLEL)
11818     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11819       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11820         return 1;
11821
11822   return 0;
11823 }
11824 \f
11825 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11826    as appropriate.  I3 and I2 are the insns resulting from the combination
11827    insns including FROM (I2 may be zero).
11828
11829    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11830    not need REG_DEAD notes because they are being substituted for.  This
11831    saves searching in the most common cases.
11832
11833    Each note in the list is either ignored or placed on some insns, depending
11834    on the type of note.  */
11835
11836 static void
11837 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11838                   rtx elim_i1)
11839 {
11840   rtx note, next_note;
11841   rtx tem;
11842
11843   for (note = notes; note; note = next_note)
11844     {
11845       rtx place = 0, place2 = 0;
11846
11847       next_note = XEXP (note, 1);
11848       switch (REG_NOTE_KIND (note))
11849         {
11850         case REG_BR_PROB:
11851         case REG_BR_PRED:
11852           /* Doesn't matter much where we put this, as long as it's somewhere.
11853              It is preferable to keep these notes on branches, which is most
11854              likely to be i3.  */
11855           place = i3;
11856           break;
11857
11858         case REG_VALUE_PROFILE:
11859           /* Just get rid of this note, as it is unused later anyway.  */
11860           break;
11861
11862         case REG_NON_LOCAL_GOTO:
11863           if (JUMP_P (i3))
11864             place = i3;
11865           else
11866             {
11867               gcc_assert (i2 && JUMP_P (i2));
11868               place = i2;
11869             }
11870           break;
11871
11872         case REG_EH_REGION:
11873           /* These notes must remain with the call or trapping instruction.  */
11874           if (CALL_P (i3))
11875             place = i3;
11876           else if (i2 && CALL_P (i2))
11877             place = i2;
11878           else
11879             {
11880               gcc_assert (flag_non_call_exceptions);
11881               if (may_trap_p (i3))
11882                 place = i3;
11883               else if (i2 && may_trap_p (i2))
11884                 place = i2;
11885               /* ??? Otherwise assume we've combined things such that we
11886                  can now prove that the instructions can't trap.  Drop the
11887                  note in this case.  */
11888             }
11889           break;
11890
11891         case REG_NORETURN:
11892         case REG_SETJMP:
11893           /* These notes must remain with the call.  It should not be
11894              possible for both I2 and I3 to be a call.  */
11895           if (CALL_P (i3))
11896             place = i3;
11897           else
11898             {
11899               gcc_assert (i2 && CALL_P (i2));
11900               place = i2;
11901             }
11902           break;
11903
11904         case REG_UNUSED:
11905           /* Any clobbers for i3 may still exist, and so we must process
11906              REG_UNUSED notes from that insn.
11907
11908              Any clobbers from i2 or i1 can only exist if they were added by
11909              recog_for_combine.  In that case, recog_for_combine created the
11910              necessary REG_UNUSED notes.  Trying to keep any original
11911              REG_UNUSED notes from these insns can cause incorrect output
11912              if it is for the same register as the original i3 dest.
11913              In that case, we will notice that the register is set in i3,
11914              and then add a REG_UNUSED note for the destination of i3, which
11915              is wrong.  However, it is possible to have REG_UNUSED notes from
11916              i2 or i1 for register which were both used and clobbered, so
11917              we keep notes from i2 or i1 if they will turn into REG_DEAD
11918              notes.  */
11919
11920           /* If this register is set or clobbered in I3, put the note there
11921              unless there is one already.  */
11922           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11923             {
11924               if (from_insn != i3)
11925                 break;
11926
11927               if (! (REG_P (XEXP (note, 0))
11928                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11929                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11930                 place = i3;
11931             }
11932           /* Otherwise, if this register is used by I3, then this register
11933              now dies here, so we must put a REG_DEAD note here unless there
11934              is one already.  */
11935           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11936                    && ! (REG_P (XEXP (note, 0))
11937                          ? find_regno_note (i3, REG_DEAD,
11938                                             REGNO (XEXP (note, 0)))
11939                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11940             {
11941               PUT_REG_NOTE_KIND (note, REG_DEAD);
11942               place = i3;
11943             }
11944           break;
11945
11946         case REG_EQUAL:
11947         case REG_EQUIV:
11948         case REG_NOALIAS:
11949           /* These notes say something about results of an insn.  We can
11950              only support them if they used to be on I3 in which case they
11951              remain on I3.  Otherwise they are ignored.
11952
11953              If the note refers to an expression that is not a constant, we
11954              must also ignore the note since we cannot tell whether the
11955              equivalence is still true.  It might be possible to do
11956              slightly better than this (we only have a problem if I2DEST
11957              or I1DEST is present in the expression), but it doesn't
11958              seem worth the trouble.  */
11959
11960           if (from_insn == i3
11961               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11962             place = i3;
11963           break;
11964
11965         case REG_INC:
11966         case REG_NO_CONFLICT:
11967           /* These notes say something about how a register is used.  They must
11968              be present on any use of the register in I2 or I3.  */
11969           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11970             place = i3;
11971
11972           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11973             {
11974               if (place)
11975                 place2 = i2;
11976               else
11977                 place = i2;
11978             }
11979           break;
11980
11981         case REG_LABEL:
11982           /* This can show up in several ways -- either directly in the
11983              pattern, or hidden off in the constant pool with (or without?)
11984              a REG_EQUAL note.  */
11985           /* ??? Ignore the without-reg_equal-note problem for now.  */
11986           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11987               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11988                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11989                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11990             place = i3;
11991
11992           if (i2
11993               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11994                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11995                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11996                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11997             {
11998               if (place)
11999                 place2 = i2;
12000               else
12001                 place = i2;
12002             }
12003
12004           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12005              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12006           if (place && JUMP_P (place))
12007             {
12008               rtx label = JUMP_LABEL (place);
12009
12010               if (!label)
12011                 JUMP_LABEL (place) = XEXP (note, 0);
12012               else
12013                 {
12014                   gcc_assert (label == XEXP (note, 0));
12015                   if (LABEL_P (label))
12016                     LABEL_NUSES (label)--;
12017                 }
12018               place = 0;
12019             }
12020           if (place2 && JUMP_P (place2))
12021             {
12022               rtx label = JUMP_LABEL (place2);
12023
12024               if (!label)
12025                 JUMP_LABEL (place2) = XEXP (note, 0);
12026               else
12027                 {
12028                   gcc_assert (label == XEXP (note, 0));
12029                   if (LABEL_P (label))
12030                     LABEL_NUSES (label)--;
12031                 }
12032               place2 = 0;
12033             }
12034           break;
12035
12036         case REG_NONNEG:
12037           /* This note says something about the value of a register prior
12038              to the execution of an insn.  It is too much trouble to see
12039              if the note is still correct in all situations.  It is better
12040              to simply delete it.  */
12041           break;
12042
12043         case REG_RETVAL:
12044           /* If the insn previously containing this note still exists,
12045              put it back where it was.  Otherwise move it to the previous
12046              insn.  Adjust the corresponding REG_LIBCALL note.  */
12047           if (!NOTE_P (from_insn))
12048             place = from_insn;
12049           else
12050             {
12051               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12052               place = prev_real_insn (from_insn);
12053               if (tem && place)
12054                 XEXP (tem, 0) = place;
12055               /* If we're deleting the last remaining instruction of a
12056                  libcall sequence, don't add the notes.  */
12057               else if (XEXP (note, 0) == from_insn)
12058                 tem = place = 0;
12059               /* Don't add the dangling REG_RETVAL note.  */
12060               else if (! tem)
12061                 place = 0;
12062             }
12063           break;
12064
12065         case REG_LIBCALL:
12066           /* This is handled similarly to REG_RETVAL.  */
12067           if (!NOTE_P (from_insn))
12068             place = from_insn;
12069           else
12070             {
12071               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12072               place = next_real_insn (from_insn);
12073               if (tem && place)
12074                 XEXP (tem, 0) = place;
12075               /* If we're deleting the last remaining instruction of a
12076                  libcall sequence, don't add the notes.  */
12077               else if (XEXP (note, 0) == from_insn)
12078                 tem = place = 0;
12079               /* Don't add the dangling REG_LIBCALL note.  */
12080               else if (! tem)
12081                 place = 0;
12082             }
12083           break;
12084
12085         case REG_DEAD:
12086           /* If the register is used as an input in I3, it dies there.
12087              Similarly for I2, if it is nonzero and adjacent to I3.
12088
12089              If the register is not used as an input in either I3 or I2
12090              and it is not one of the registers we were supposed to eliminate,
12091              there are two possibilities.  We might have a non-adjacent I2
12092              or we might have somehow eliminated an additional register
12093              from a computation.  For example, we might have had A & B where
12094              we discover that B will always be zero.  In this case we will
12095              eliminate the reference to A.
12096
12097              In both cases, we must search to see if we can find a previous
12098              use of A and put the death note there.  */
12099
12100           if (from_insn
12101               && CALL_P (from_insn)
12102               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12103             place = from_insn;
12104           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12105             place = i3;
12106           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12107                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12108             place = i2;
12109
12110           if (place == 0
12111               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12112                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12113             break;
12114
12115           if (place == 0)
12116             {
12117               basic_block bb = this_basic_block;
12118
12119               /* You might think you could search back from FROM_INSN
12120                  rather than from I3, but combine tries to split invalid
12121                  combined instructions.  This can result in the old I2
12122                  or I1 moving later in the insn sequence.  */
12123               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12124                 {
12125                   if (! INSN_P (tem))
12126                     {
12127                       if (tem == BB_HEAD (bb))
12128                         break;
12129                       continue;
12130                     }
12131
12132                   /* If the register is being set at TEM, see if that is all
12133                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12134                      into a REG_UNUSED note instead. Don't delete sets to
12135                      global register vars.  */
12136                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12137                        || !global_regs[REGNO (XEXP (note, 0))])
12138                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12139                     {
12140                       rtx set = single_set (tem);
12141                       rtx inner_dest = 0;
12142 #ifdef HAVE_cc0
12143                       rtx cc0_setter = NULL_RTX;
12144 #endif
12145
12146                       if (set != 0)
12147                         for (inner_dest = SET_DEST (set);
12148                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12149                               || GET_CODE (inner_dest) == SUBREG
12150                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12151                              inner_dest = XEXP (inner_dest, 0))
12152                           ;
12153
12154                       /* Verify that it was the set, and not a clobber that
12155                          modified the register.
12156
12157                          CC0 targets must be careful to maintain setter/user
12158                          pairs.  If we cannot delete the setter due to side
12159                          effects, mark the user with an UNUSED note instead
12160                          of deleting it.  */
12161
12162                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12163                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12164 #ifdef HAVE_cc0
12165                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12166                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12167                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12168 #endif
12169                           )
12170                         {
12171                           /* Move the notes and links of TEM elsewhere.
12172                              This might delete other dead insns recursively.
12173                              First set the pattern to something that won't use
12174                              any register.  */
12175                           rtx old_notes = REG_NOTES (tem);
12176
12177                           PATTERN (tem) = pc_rtx;
12178                           REG_NOTES (tem) = NULL;
12179
12180                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12181                                             NULL_RTX, NULL_RTX);
12182                           distribute_links (LOG_LINKS (tem));
12183
12184                           SET_INSN_DELETED (tem);
12185
12186 #ifdef HAVE_cc0
12187                           /* Delete the setter too.  */
12188                           if (cc0_setter)
12189                             {
12190                               PATTERN (cc0_setter) = pc_rtx;
12191                               old_notes = REG_NOTES (cc0_setter);
12192                               REG_NOTES (cc0_setter) = NULL;
12193
12194                               distribute_notes (old_notes, cc0_setter,
12195                                                 cc0_setter, NULL_RTX,
12196                                                 NULL_RTX, NULL_RTX);
12197                               distribute_links (LOG_LINKS (cc0_setter));
12198
12199                               SET_INSN_DELETED (cc0_setter);
12200                             }
12201 #endif
12202                         }
12203                       else
12204                         {
12205                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12206
12207                           /*  If there isn't already a REG_UNUSED note, put one
12208                               here.  Do not place a REG_DEAD note, even if
12209                               the register is also used here; that would not
12210                               match the algorithm used in lifetime analysis
12211                               and can cause the consistency check in the
12212                               scheduler to fail.  */
12213                           if (! find_regno_note (tem, REG_UNUSED,
12214                                                  REGNO (XEXP (note, 0))))
12215                             place = tem;
12216                           break;
12217                         }
12218                     }
12219                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12220                            || (CALL_P (tem)
12221                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12222                     {
12223                       /* This may not be the correct place for the death
12224                          note if FROM_INSN is before TEM, and the reg is
12225                          set between FROM_INSN and TEM.  The reg might
12226                          die two or more times.  An existing death note
12227                          means we are looking at the wrong live range.  */
12228                       if (from_insn
12229                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12230                           && find_regno_note (tem, REG_DEAD,
12231                                               REGNO (XEXP (note, 0))))
12232                         {
12233                           tem = from_insn;
12234                           if (tem == BB_HEAD (bb))
12235                             break;
12236                           continue;
12237                         }
12238
12239                       place = tem;
12240
12241                       /* If we are doing a 3->2 combination, and we have a
12242                          register which formerly died in i3 and was not used
12243                          by i2, which now no longer dies in i3 and is used in
12244                          i2 but does not die in i2, and place is between i2
12245                          and i3, then we may need to move a link from place to
12246                          i2.  */
12247                       if (i2 && INSN_UID (place) <= max_uid_cuid
12248                           && INSN_CUID (place) > INSN_CUID (i2)
12249                           && from_insn
12250                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12251                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12252                         {
12253                           rtx links = LOG_LINKS (place);
12254                           LOG_LINKS (place) = 0;
12255                           distribute_links (links);
12256                         }
12257                       break;
12258                     }
12259
12260                   if (tem == BB_HEAD (bb))
12261                     break;
12262                 }
12263
12264               /* We haven't found an insn for the death note and it
12265                  is still a REG_DEAD note, but we have hit the beginning
12266                  of the block.  If the existing life info says the reg
12267                  was dead, there's nothing left to do.  Otherwise, we'll
12268                  need to do a global life update after combine.  */
12269               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12270                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12271                                       REGNO (XEXP (note, 0))))
12272                 SET_BIT (refresh_blocks, this_basic_block->index);
12273             }
12274
12275           /* If the register is set or already dead at PLACE, we needn't do
12276              anything with this note if it is still a REG_DEAD note.
12277              We check here if it is set at all, not if is it totally replaced,
12278              which is what `dead_or_set_p' checks, so also check for it being
12279              set partially.  */
12280
12281           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12282             {
12283               unsigned int regno = REGNO (XEXP (note, 0));
12284
12285               /* Similarly, if the instruction on which we want to place
12286                  the note is a noop, we'll need do a global live update
12287                  after we remove them in delete_noop_moves.  */
12288               if (noop_move_p (place))
12289                 SET_BIT (refresh_blocks, this_basic_block->index);
12290
12291               if (dead_or_set_p (place, XEXP (note, 0))
12292                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12293                 {
12294                   /* Unless the register previously died in PLACE, clear
12295                      last_death.  [I no longer understand why this is
12296                      being done.] */
12297                   if (reg_stat[regno].last_death != place)
12298                     reg_stat[regno].last_death = 0;
12299                   place = 0;
12300                 }
12301               else
12302                 reg_stat[regno].last_death = place;
12303
12304               /* If this is a death note for a hard reg that is occupying
12305                  multiple registers, ensure that we are still using all
12306                  parts of the object.  If we find a piece of the object
12307                  that is unused, we must arrange for an appropriate REG_DEAD
12308                  note to be added for it.  However, we can't just emit a USE
12309                  and tag the note to it, since the register might actually
12310                  be dead; so we recourse, and the recursive call then finds
12311                  the previous insn that used this register.  */
12312
12313               if (place && regno < FIRST_PSEUDO_REGISTER
12314                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12315                 {
12316                   unsigned int endregno
12317                     = regno + hard_regno_nregs[regno]
12318                                               [GET_MODE (XEXP (note, 0))];
12319                   int all_used = 1;
12320                   unsigned int i;
12321
12322                   for (i = regno; i < endregno; i++)
12323                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12324                          && ! find_regno_fusage (place, USE, i))
12325                         || dead_or_set_regno_p (place, i))
12326                       all_used = 0;
12327
12328                   if (! all_used)
12329                     {
12330                       /* Put only REG_DEAD notes for pieces that are
12331                          not already dead or set.  */
12332
12333                       for (i = regno; i < endregno;
12334                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12335                         {
12336                           rtx piece = regno_reg_rtx[i];
12337                           basic_block bb = this_basic_block;
12338
12339                           if (! dead_or_set_p (place, piece)
12340                               && ! reg_bitfield_target_p (piece,
12341                                                           PATTERN (place)))
12342                             {
12343                               rtx new_note
12344                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12345
12346                               distribute_notes (new_note, place, place,
12347                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12348                             }
12349                           else if (! refers_to_regno_p (i, i + 1,
12350                                                         PATTERN (place), 0)
12351                                    && ! find_regno_fusage (place, USE, i))
12352                             for (tem = PREV_INSN (place); ;
12353                                  tem = PREV_INSN (tem))
12354                               {
12355                                 if (! INSN_P (tem))
12356                                   {
12357                                     if (tem == BB_HEAD (bb))
12358                                       {
12359                                         SET_BIT (refresh_blocks,
12360                                                  this_basic_block->index);
12361                                         break;
12362                                       }
12363                                     continue;
12364                                   }
12365                                 if (dead_or_set_p (tem, piece)
12366                                     || reg_bitfield_target_p (piece,
12367                                                               PATTERN (tem)))
12368                                   {
12369                                     REG_NOTES (tem)
12370                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12371                                                            REG_NOTES (tem));
12372                                     break;
12373                                   }
12374                               }
12375
12376                         }
12377
12378                       place = 0;
12379                     }
12380                 }
12381             }
12382           break;
12383
12384         default:
12385           /* Any other notes should not be present at this point in the
12386              compilation.  */
12387           gcc_unreachable ();
12388         }
12389
12390       if (place)
12391         {
12392           XEXP (note, 1) = REG_NOTES (place);
12393           REG_NOTES (place) = note;
12394         }
12395       else if ((REG_NOTE_KIND (note) == REG_DEAD
12396                 || REG_NOTE_KIND (note) == REG_UNUSED)
12397                && REG_P (XEXP (note, 0)))
12398         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12399
12400       if (place2)
12401         {
12402           if ((REG_NOTE_KIND (note) == REG_DEAD
12403                || REG_NOTE_KIND (note) == REG_UNUSED)
12404               && REG_P (XEXP (note, 0)))
12405             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12406
12407           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12408                                                REG_NOTE_KIND (note),
12409                                                XEXP (note, 0),
12410                                                REG_NOTES (place2));
12411         }
12412     }
12413 }
12414 \f
12415 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12416    I3, I2, and I1 to new locations.  This is also called to add a link
12417    pointing at I3 when I3's destination is changed.  */
12418
12419 static void
12420 distribute_links (rtx links)
12421 {
12422   rtx link, next_link;
12423
12424   for (link = links; link; link = next_link)
12425     {
12426       rtx place = 0;
12427       rtx insn;
12428       rtx set, reg;
12429
12430       next_link = XEXP (link, 1);
12431
12432       /* If the insn that this link points to is a NOTE or isn't a single
12433          set, ignore it.  In the latter case, it isn't clear what we
12434          can do other than ignore the link, since we can't tell which
12435          register it was for.  Such links wouldn't be used by combine
12436          anyway.
12437
12438          It is not possible for the destination of the target of the link to
12439          have been changed by combine.  The only potential of this is if we
12440          replace I3, I2, and I1 by I3 and I2.  But in that case the
12441          destination of I2 also remains unchanged.  */
12442
12443       if (NOTE_P (XEXP (link, 0))
12444           || (set = single_set (XEXP (link, 0))) == 0)
12445         continue;
12446
12447       reg = SET_DEST (set);
12448       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12449              || GET_CODE (reg) == STRICT_LOW_PART)
12450         reg = XEXP (reg, 0);
12451
12452       /* A LOG_LINK is defined as being placed on the first insn that uses
12453          a register and points to the insn that sets the register.  Start
12454          searching at the next insn after the target of the link and stop
12455          when we reach a set of the register or the end of the basic block.
12456
12457          Note that this correctly handles the link that used to point from
12458          I3 to I2.  Also note that not much searching is typically done here
12459          since most links don't point very far away.  */
12460
12461       for (insn = NEXT_INSN (XEXP (link, 0));
12462            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12463                      || BB_HEAD (this_basic_block->next_bb) != insn));
12464            insn = NEXT_INSN (insn))
12465         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12466           {
12467             if (reg_referenced_p (reg, PATTERN (insn)))
12468               place = insn;
12469             break;
12470           }
12471         else if (CALL_P (insn)
12472                  && find_reg_fusage (insn, USE, reg))
12473           {
12474             place = insn;
12475             break;
12476           }
12477         else if (INSN_P (insn) && reg_set_p (reg, insn))
12478           break;
12479
12480       /* If we found a place to put the link, place it there unless there
12481          is already a link to the same insn as LINK at that point.  */
12482
12483       if (place)
12484         {
12485           rtx link2;
12486
12487           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12488             if (XEXP (link2, 0) == XEXP (link, 0))
12489               break;
12490
12491           if (link2 == 0)
12492             {
12493               XEXP (link, 1) = LOG_LINKS (place);
12494               LOG_LINKS (place) = link;
12495
12496               /* Set added_links_insn to the earliest insn we added a
12497                  link to.  */
12498               if (added_links_insn == 0
12499                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12500                 added_links_insn = place;
12501             }
12502         }
12503     }
12504 }
12505 \f
12506 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12507    Check whether the expression pointer to by LOC is a register or
12508    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12509    Otherwise return zero.  */
12510
12511 static int
12512 unmentioned_reg_p_1 (rtx *loc, void *expr)
12513 {
12514   rtx x = *loc;
12515
12516   if (x != NULL_RTX
12517       && (REG_P (x) || MEM_P (x))
12518       && ! reg_mentioned_p (x, (rtx) expr))
12519     return 1;
12520   return 0;
12521 }
12522
12523 /* Check for any register or memory mentioned in EQUIV that is not
12524    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12525    of EXPR where some registers may have been replaced by constants.  */
12526
12527 static bool
12528 unmentioned_reg_p (rtx equiv, rtx expr)
12529 {
12530   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12531 }
12532 \f
12533 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12534
12535 static int
12536 insn_cuid (rtx insn)
12537 {
12538   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12539          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12540     insn = NEXT_INSN (insn);
12541
12542   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12543
12544   return INSN_CUID (insn);
12545 }
12546 \f
12547 void
12548 dump_combine_stats (FILE *file)
12549 {
12550   fprintf
12551     (file,
12552      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12553      combine_attempts, combine_merges, combine_extras, combine_successes);
12554 }
12555
12556 void
12557 dump_combine_total_stats (FILE *file)
12558 {
12559   fprintf
12560     (file,
12561      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12562      total_attempts, total_merges, total_extras, total_successes);
12563 }
12564 \f
12565
12566 static bool
12567 gate_handle_combine (void)
12568 {
12569   return (optimize > 0);
12570 }
12571
12572 /* Try combining insns through substitution.  */
12573 static void
12574 rest_of_handle_combine (void)
12575 {
12576   int rebuild_jump_labels_after_combine
12577     = combine_instructions (get_insns (), max_reg_num ());
12578
12579   /* Combining insns may have turned an indirect jump into a
12580      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12581      instructions.  */
12582   if (rebuild_jump_labels_after_combine)
12583     {
12584       timevar_push (TV_JUMP);
12585       rebuild_jump_labels (get_insns ());
12586       timevar_pop (TV_JUMP);
12587
12588       delete_dead_jumptables ();
12589       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12590     }
12591 }
12592
12593 struct tree_opt_pass pass_combine =
12594 {
12595   "combine",                            /* name */
12596   gate_handle_combine,                  /* gate */
12597   rest_of_handle_combine,               /* execute */
12598   NULL,                                 /* sub */
12599   NULL,                                 /* next */
12600   0,                                    /* static_pass_number */
12601   TV_COMBINE,                           /* tv_id */
12602   0,                                    /* properties_required */
12603   0,                                    /* properties_provided */
12604   0,                                    /* properties_destroyed */
12605   0,                                    /* todo_flags_start */
12606   TODO_dump_func |
12607   TODO_ggc_collect,                     /* todo_flags_finish */
12608   'c'                                   /* letter */
12609 };
12610