| blob | b9d19617bf185f686fb8b495155d015116078886 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
123 #ifndef CHECK_STACK_LIMIT
124 #define CHECK_STACK_LIMIT (-1)
125 #endif
127 /* Return index of given mode in mult and division cost tables. */
128 #define MODE_INDEX(mode) \
129 ((mode) == QImode ? 0 \
130 : (mode) == HImode ? 1 \
131 : (mode) == SImode ? 2 \
132 : (mode) == DImode ? 3 \
133 : 4)
135 /* Processor costs (relative to an add) */
136 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
137 #define COSTS_N_BYTES(N) ((N) * 2)
139 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
148 const
171 in QImode, HImode and SImode.
172 Relative to reg-reg move (2). */
176 in SFmode, DFmode and XFmode */
178 in SFmode, DFmode and XFmode */
181 in SImode and DImode */
183 in SImode and DImode */
186 in SImode, DImode and TImode */
188 in SImode, DImode and TImode */
201 ix86_size_memcpy,
202 ix86_size_memset,
214 };
216 /* Processor costs (relative to an add) */
219 DUMMY_STRINGOP_ALGS};
222 DUMMY_STRINGOP_ALGS};
224 static const
247 in QImode, HImode and SImode.
248 Relative to reg-reg move (2). */
252 in SFmode, DFmode and XFmode */
254 in SFmode, DFmode and XFmode */
257 in SImode and DImode */
259 in SImode and DImode */
262 in SImode, DImode and TImode */
264 in SImode, DImode and TImode */
277 i386_memcpy,
278 i386_memset,
290 };
294 DUMMY_STRINGOP_ALGS};
297 DUMMY_STRINGOP_ALGS};
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
342 shared for code and data, so 4kB is
343 not really precise. */
354 i486_memcpy,
355 i486_memset,
367 };
371 DUMMY_STRINGOP_ALGS};
374 DUMMY_STRINGOP_ALGS};
376 static const
399 in QImode, HImode and SImode.
400 Relative to reg-reg move (2). */
404 in SFmode, DFmode and XFmode */
406 in SFmode, DFmode and XFmode */
409 in SImode and DImode */
411 in SImode and DImode */
414 in SImode, DImode and TImode */
416 in SImode, DImode and TImode */
429 pentium_memcpy,
430 pentium_memset,
442 };
444 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
445 (we ensure the alignment). For small blocks inline loop is still a
446 noticeable win, for bigger blocks either rep movsl or rep movsb is
447 way to go. Rep movsb has apparently more expensive startup time in CPU,
448 but after 4K the difference is down in the noise. */
453 DUMMY_STRINGOP_ALGS};
458 DUMMY_STRINGOP_ALGS};
459 static const
482 in QImode, HImode and SImode.
483 Relative to reg-reg move (2). */
487 in SFmode, DFmode and XFmode */
489 in SFmode, DFmode and XFmode */
492 in SImode and DImode */
494 in SImode and DImode */
497 in SImode, DImode and TImode */
499 in SImode, DImode and TImode */
512 pentiumpro_memcpy,
513 pentiumpro_memset,
525 };
529 DUMMY_STRINGOP_ALGS};
532 DUMMY_STRINGOP_ALGS};
533 static const
556 in QImode, HImode and SImode.
557 Relative to reg-reg move (2). */
561 in SFmode, DFmode and XFmode */
563 in SFmode, DFmode and XFmode */
567 in SImode and DImode */
569 in SImode and DImode */
572 in SImode, DImode and TImode */
574 in SImode, DImode and TImode */
587 geode_memcpy,
588 geode_memset,
600 };
604 DUMMY_STRINGOP_ALGS};
607 DUMMY_STRINGOP_ALGS};
608 static const
631 in QImode, HImode and SImode.
632 Relative to reg-reg move (2). */
636 in SFmode, DFmode and XFmode */
638 in SFmode, DFmode and XFmode */
641 in SImode and DImode */
643 in SImode and DImode */
646 in SImode, DImode and TImode */
648 in SImode, DImode and TImode */
652 have integrated l2 cache, but
653 optimizing for k6 is not important
654 enough to worry about that. */
664 k6_memcpy,
665 k6_memset,
677 };
679 /* For some reason, Athlon deals better with REP prefix (relative to loops)
680 compared to K8. Alignment becomes important after 8 bytes for memcpy and
681 128 bytes for memset. */
684 DUMMY_STRINGOP_ALGS};
687 DUMMY_STRINGOP_ALGS};
688 static const
711 in QImode, HImode and SImode.
712 Relative to reg-reg move (2). */
716 in SFmode, DFmode and XFmode */
718 in SFmode, DFmode and XFmode */
721 in SImode and DImode */
723 in SImode and DImode */
726 in SImode, DImode and TImode */
728 in SImode, DImode and TImode */
741 athlon_memcpy,
742 athlon_memset,
754 };
756 /* K8 has optimized REP instruction for medium sized blocks, but for very
757 small blocks it is better to use loop. For large blocks, libcall can
758 do nontemporary accesses and beat inline considerably. */
769 static const
792 in QImode, HImode and SImode.
793 Relative to reg-reg move (2). */
797 in SFmode, DFmode and XFmode */
799 in SFmode, DFmode and XFmode */
802 in SImode and DImode */
804 in SImode and DImode */
807 in SImode, DImode and TImode */
809 in SImode, DImode and TImode */
814 /* New AMD processors never drop prefetches; if they cannot be performed
815 immediately, they are queued. We set number of simultaneous prefetches
816 to a large constant to reflect this (it probably is not a good idea not
817 to limit number of prefetches at all, as their execution also takes some
818 time). */
828 k8_memcpy,
829 k8_memset,
841 };
843 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
844 very small blocks it is better to use loop. For large blocks, libcall can
845 do nontemporary accesses and beat inline considerably. */
878 in QImode, HImode and SImode.
879 Relative to reg-reg move (2). */
883 in SFmode, DFmode and XFmode */
885 in SFmode, DFmode and XFmode */
888 in SImode and DImode */
890 in SImode and DImode */
893 in SImode, DImode and TImode */
895 in SImode, DImode and TImode */
897 /* On K8:
898 MOVD reg64, xmmreg Double FSTORE 4
899 MOVD reg32, xmmreg Double FSTORE 4
900 On AMDFAM10:
901 MOVD reg64, xmmreg Double FADD 3
902 1/1 1/1
903 MOVD reg32, xmmreg Double FADD 3
904 1/1 1/1 */
908 /* New AMD processors never drop prefetches; if they cannot be performed
909 immediately, they are queued. We set number of simultaneous prefetches
910 to a large constant to reflect this (it probably is not a good idea not
911 to limit number of prefetches at all, as their execution also takes some
912 time). */
922 amdfam10_memcpy,
923 amdfam10_memset,
935 };
937 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
938 very small blocks it is better to use loop. For large blocks, libcall
939 can do nontemporary accesses and beat inline considerably. */
973 in QImode, HImode and SImode.
974 Relative to reg-reg move (2). */
978 in SFmode, DFmode and XFmode */
980 in SFmode, DFmode and XFmode */
983 in SImode and DImode */
985 in SImode and DImode */
988 in SImode, DImode and TImode */
990 in SImode, DImode and TImode */
992 /* On K8:
993 MOVD reg64, xmmreg Double FSTORE 4
994 MOVD reg32, xmmreg Double FSTORE 4
995 On AMDFAM10:
996 MOVD reg64, xmmreg Double FADD 3
997 1/1 1/1
998 MOVD reg32, xmmreg Double FADD 3
999 1/1 1/1 */
1003 /* New AMD processors never drop prefetches; if they cannot be performed
1004 immediately, they are queued. We set number of simultaneous prefetches
1005 to a large constant to reflect this (it probably is not a good idea not
1006 to limit number of prefetches at all, as their execution also takes some
1007 time). */
1017 bdver1_memcpy,
1018 bdver1_memset,
1030 };
1032 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1033 very small blocks it is better to use loop. For large blocks, libcall
1034 can do nontemporary accesses and beat inline considerably. */
1069 in QImode, HImode and SImode.
1070 Relative to reg-reg move (2). */
1074 in SFmode, DFmode and XFmode */
1076 in SFmode, DFmode and XFmode */
1079 in SImode and DImode */
1081 in SImode and DImode */
1084 in SImode, DImode and TImode */
1086 in SImode, DImode and TImode */
1088 /* On K8:
1089 MOVD reg64, xmmreg Double FSTORE 4
1090 MOVD reg32, xmmreg Double FSTORE 4
1091 On AMDFAM10:
1092 MOVD reg64, xmmreg Double FADD 3
1093 1/1 1/1
1094 MOVD reg32, xmmreg Double FADD 3
1095 1/1 1/1 */
1099 /* New AMD processors never drop prefetches; if they cannot be performed
1100 immediately, they are queued. We set number of simultaneous prefetches
1101 to a large constant to reflect this (it probably is not a good idea not
1102 to limit number of prefetches at all, as their execution also takes some
1103 time). */
1113 bdver2_memcpy,
1114 bdver2_memset,
1126 };
1129 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1130 very small blocks it is better to use loop. For large blocks, libcall
1131 can do nontemporary accesses and beat inline considerably. */
1164 in QImode, HImode and SImode.
1165 Relative to reg-reg move (2). */
1169 in SFmode, DFmode and XFmode */
1171 in SFmode, DFmode and XFmode */
1174 in SImode and DImode */
1176 in SImode and DImode */
1179 in SImode, DImode and TImode */
1181 in SImode, DImode and TImode */
1186 /* New AMD processors never drop prefetches; if they cannot be performed
1187 immediately, they are queued. We set number of simultaneous prefetches
1188 to a large constant to reflect this (it probably is not a good idea not
1189 to limit number of prefetches at all, as their execution also takes some
1190 time). */
1200 bdver3_memcpy,
1201 bdver3_memset,
1213 };
1215 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1216 very small blocks it is better to use loop. For large blocks, libcall
1217 can do nontemporary accesses and beat inline considerably. */
1250 in QImode, HImode and SImode.
1251 Relative to reg-reg move (2). */
1255 in SFmode, DFmode and XFmode */
1257 in SFmode, DFmode and XFmode */
1260 in SImode and DImode */
1262 in SImode and DImode */
1265 in SImode, DImode and TImode */
1267 in SImode, DImode and TImode */
1272 /* New AMD processors never drop prefetches; if they cannot be performed
1273 immediately, they are queued. We set number of simultaneous prefetches
1274 to a large constant to reflect this (it probably is not a good idea not
1275 to limit number of prefetches at all, as their execution also takes some
1276 time). */
1286 bdver4_memcpy,
1287 bdver4_memset,
1299 };
1301 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1302 very small blocks it is better to use loop. For large blocks, libcall can
1303 do nontemporary accesses and beat inline considerably. */
1336 in QImode, HImode and SImode.
1337 Relative to reg-reg move (2). */
1341 in SFmode, DFmode and XFmode */
1343 in SFmode, DFmode and XFmode */
1346 in SImode and DImode */
1348 in SImode and DImode */
1351 in SImode, DImode and TImode */
1353 in SImode, DImode and TImode */
1355 /* On K8:
1356 MOVD reg64, xmmreg Double FSTORE 4
1357 MOVD reg32, xmmreg Double FSTORE 4
1358 On AMDFAM10:
1359 MOVD reg64, xmmreg Double FADD 3
1360 1/1 1/1
1361 MOVD reg32, xmmreg Double FADD 3
1362 1/1 1/1 */
1375 btver1_memcpy,
1376 btver1_memset,
1388 };
1422 in QImode, HImode and SImode.
1423 Relative to reg-reg move (2). */
1427 in SFmode, DFmode and XFmode */
1429 in SFmode, DFmode and XFmode */
1432 in SImode and DImode */
1434 in SImode and DImode */
1437 in SImode, DImode and TImode */
1439 in SImode, DImode and TImode */
1441 /* On K8:
1442 MOVD reg64, xmmreg Double FSTORE 4
1443 MOVD reg32, xmmreg Double FSTORE 4
1444 On AMDFAM10:
1445 MOVD reg64, xmmreg Double FADD 3
1446 1/1 1/1
1447 MOVD reg32, xmmreg Double FADD 3
1448 1/1 1/1 */
1460 btver2_memcpy,
1461 btver2_memset,
1473 };
1477 DUMMY_STRINGOP_ALGS};
1481 DUMMY_STRINGOP_ALGS};
1483 static const
1506 in QImode, HImode and SImode.
1507 Relative to reg-reg move (2). */
1511 in SFmode, DFmode and XFmode */
1513 in SFmode, DFmode and XFmode */
1516 in SImode and DImode */
1518 in SImode and DImode */
1521 in SImode, DImode and TImode */
1523 in SImode, DImode and TImode */
1536 pentium4_memcpy,
1537 pentium4_memset,
1549 };
1562 static const
1585 in QImode, HImode and SImode.
1586 Relative to reg-reg move (2). */
1590 in SFmode, DFmode and XFmode */
1592 in SFmode, DFmode and XFmode */
1595 in SImode and DImode */
1597 in SImode and DImode */
1600 in SImode, DImode and TImode */
1602 in SImode, DImode and TImode */
1615 nocona_memcpy,
1616 nocona_memset,
1628 };
1639 static const
1662 in QImode, HImode and SImode.
1663 Relative to reg-reg move (2). */
1667 in SFmode, DFmode and XFmode */
1669 in SFmode, DFmode and XFmode */
1672 in SImode and DImode */
1674 in SImode and DImode */
1677 in SImode, DImode and TImode */
1679 in SImode, DImode and TImode */
1692 atom_memcpy,
1693 atom_memset,
1705 };
1716 static const
1739 in QImode, HImode and SImode.
1740 Relative to reg-reg move (2). */
1744 in SFmode, DFmode and XFmode */
1746 in SFmode, DFmode and XFmode */
1749 in SImode and DImode */
1751 in SImode and DImode */
1754 in SImode, DImode and TImode */
1756 in SImode, DImode and TImode */
1769 slm_memcpy,
1770 slm_memset,
1782 };
1793 static const
1816 in QImode, HImode and SImode.
1817 Relative to reg-reg move (2). */
1821 in SFmode, DFmode and XFmode */
1823 in SFmode, DFmode and XFmode */
1826 in SImode and DImode */
1828 in SImode and DImode */
1831 in SImode, DImode and TImode */
1833 in SImode, DImode and TImode */
1846 intel_memcpy,
1847 intel_memset,
1859 };
1861 /* Generic should produce code tuned for Core-i7 (and newer chips)
1862 and btver1 (and newer chips). */
1874 static const
1877 /* On all chips taken into consideration lea is 2 cycles and more. With
1878 this cost however our current implementation of synth_mult results in
1879 use of unnecessary temporary registers causing regression on several
1880 SPECfp benchmarks. */
1901 in QImode, HImode and SImode.
1902 Relative to reg-reg move (2). */
1906 in SFmode, DFmode and XFmode */
1908 in SFmode, DFmode and XFmode */
1911 in SImode and DImode */
1913 in SImode and DImode */
1916 in SImode, DImode and TImode */
1918 in SImode, DImode and TImode */
1924 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1925 value is increased to perhaps more appropriate value of 5. */
1933 generic_memcpy,
1934 generic_memset,
1946 };
1948 /* core_cost should produce code tuned for Core familly of CPUs. */
1961 static const
1964 /* On all chips taken into consideration lea is 2 cycles and more. With
1965 this cost however our current implementation of synth_mult results in
1966 use of unnecessary temporary registers causing regression on several
1967 SPECfp benchmarks. */
1988 in QImode, HImode and SImode.
1989 Relative to reg-reg move (2). */
1993 in SFmode, DFmode and XFmode */
1995 in SFmode, DFmode and XFmode */
1998 in SImode and DImode */
2000 in SImode and DImode */
2003 in SImode, DImode and TImode */
2005 in SImode, DImode and TImode */
2011 /* FIXME perhaps more appropriate value is 5. */
2019 core_memcpy,
2020 core_memset,
2032 };
2035 /* Set by -mtune. */
2038 /* Set by -mtune or -Os. */
2041 /* Processor feature/optimization bitmasks. */
2042 #define m_386 (1<<PROCESSOR_I386)
2043 #define m_486 (1<<PROCESSOR_I486)
2044 #define m_PENT (1<<PROCESSOR_PENTIUM)
2045 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2046 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2047 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2048 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2049 #define m_CORE2 (1<<PROCESSOR_CORE2)
2050 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2051 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2052 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2053 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2054 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2055 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2056 #define m_KNL (1<<PROCESSOR_KNL)
2057 #define m_INTEL (1<<PROCESSOR_INTEL)
2059 #define m_GEODE (1<<PROCESSOR_GEODE)
2060 #define m_K6 (1<<PROCESSOR_K6)
2061 #define m_K6_GEODE (m_K6 | m_GEODE)
2062 #define m_K8 (1<<PROCESSOR_K8)
2063 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2064 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2065 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2066 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2067 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2068 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2069 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2070 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2071 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2072 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2073 #define m_BTVER (m_BTVER1 | m_BTVER2)
2074 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2076 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2079 #undef DEF_TUNE
2080 #define DEF_TUNE(tune, name, selector) name,
2082 #undef DEF_TUNE
2083 };
2085 /* Feature tests against the various tunings. */
2088 /* Feature tests against the various tunings used to create ix86_tune_features
2089 based on the processor mask. */
2091 #undef DEF_TUNE
2092 #define DEF_TUNE(tune, name, selector) selector,
2094 #undef DEF_TUNE
2095 };
2097 /* Feature tests against the various architecture variations. */
2100 /* Feature tests against the various architecture variations, used to create
2101 ix86_arch_features based on the processor mask. */
2103 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2106 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2109 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2112 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2115 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2117 };
2119 /* In case the average insn count for single function invocation is
2120 lower than this constant, emit fast (but longer) prologue and
2121 epilogue code. */
2122 #define FAST_PROLOGUE_INSN_COUNT 20
2124 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2129 /* Array of the smallest class containing reg number REGNO, indexed by
2130 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2133 {
2134 /* ax, dx, cx, bx */
2136 /* si, di, bp, sp */
2138 /* FP registers */
2141 /* arg pointer */
2142 NON_Q_REGS,
2143 /* flags, fpsr, fpcr, frame */
2145 /* SSE registers */
2148 /* MMX registers */
2151 /* REX registers */
2154 /* SSE REX registers */
2157 /* AVX-512 SSE registers */
2162 /* Mask registers. */
2165 /* MPX bound registers */
2167 };
2169 /* The "default" register map used in 32bit mode. */
2172 {
2184 };
2186 /* The "default" register map used in 64bit mode. */
2189 {
2201 };
2203 /* Define the register numbers to be used in Dwarf debugging information.
2204 The SVR4 reference port C compiler uses the following register numbers
2205 in its Dwarf output code:
2206 0 for %eax (gcc regno = 0)
2207 1 for %ecx (gcc regno = 2)
2208 2 for %edx (gcc regno = 1)
2209 3 for %ebx (gcc regno = 3)
2210 4 for %esp (gcc regno = 7)
2211 5 for %ebp (gcc regno = 6)
2212 6 for %esi (gcc regno = 4)
2213 7 for %edi (gcc regno = 5)
2214 The following three DWARF register numbers are never generated by
2215 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2216 believes these numbers have these meanings.
2217 8 for %eip (no gcc equivalent)
2218 9 for %eflags (gcc regno = 17)
2219 10 for %trapno (no gcc equivalent)
2220 It is not at all clear how we should number the FP stack registers
2221 for the x86 architecture. If the version of SDB on x86/svr4 were
2222 a bit less brain dead with respect to floating-point then we would
2223 have a precedent to follow with respect to DWARF register numbers
2224 for x86 FP registers, but the SDB on x86/svr4 is so completely
2225 broken with respect to FP registers that it is hardly worth thinking
2226 of it as something to strive for compatibility with.
2227 The version of x86/svr4 SDB I have at the moment does (partially)
2228 seem to believe that DWARF register number 11 is associated with
2229 the x86 register %st(0), but that's about all. Higher DWARF
2230 register numbers don't seem to be associated with anything in
2231 particular, and even for DWARF regno 11, SDB only seems to under-
2232 stand that it should say that a variable lives in %st(0) (when
2233 asked via an `=' command) if we said it was in DWARF regno 11,
2234 but SDB still prints garbage when asked for the value of the
2235 variable in question (via a `/' command).
2236 (Also note that the labels SDB prints for various FP stack regs
2237 when doing an `x' command are all wrong.)
2238 Note that these problems generally don't affect the native SVR4
2239 C compiler because it doesn't allow the use of -O with -g and
2240 because when it is *not* optimizing, it allocates a memory
2241 location for each floating-point variable, and the memory
2242 location is what gets described in the DWARF AT_location
2243 attribute for the variable in question.
2244 Regardless of the severe mental illness of the x86/svr4 SDB, we
2245 do something sensible here and we use the following DWARF
2246 register numbers. Note that these are all stack-top-relative
2247 numbers.
2248 11 for %st(0) (gcc regno = 8)
2249 12 for %st(1) (gcc regno = 9)
2250 13 for %st(2) (gcc regno = 10)
2251 14 for %st(3) (gcc regno = 11)
2252 15 for %st(4) (gcc regno = 12)
2253 16 for %st(5) (gcc regno = 13)
2254 17 for %st(6) (gcc regno = 14)
2255 18 for %st(7) (gcc regno = 15)
2256 */
2258 {
2270 };
2272 /* Define parameter passing and return registers. */
2275 {
2277 };
2280 {
2282 };
2285 {
2287 };
2289 /* Additional registers that are clobbered by SYSV calls. */
2292 {
2297 };
2299 /* Define the structure for the machine field in struct function. */
2304 rtx rtl;
2306 };
2308 /* Structure describing stack frame layout.
2309 Stack grows downward:
2311 [arguments]
2312 <- ARG_POINTER
2313 saved pc
2315 saved static chain if ix86_static_chain_on_stack
2317 saved frame pointer if frame_pointer_needed
2318 <- HARD_FRAME_POINTER
2319 [saved regs]
2320 <- regs_save_offset
2321 [padding0]
2323 [saved SSE regs]
2324 <- sse_regs_save_offset
2325 [padding1] |
2326 | <- FRAME_POINTER
2327 [va_arg registers] |
2328 |
2329 [frame] |
2330 |
2331 [padding2] | = to_allocate
2332 <- STACK_POINTER
2333 */
2334 struct ix86_frame
2335 {
2342 /* The offsets relative to ARG_POINTER. */
2343 HOST_WIDE_INT frame_pointer_offset;
2344 HOST_WIDE_INT hard_frame_pointer_offset;
2345 HOST_WIDE_INT stack_pointer_offset;
2346 HOST_WIDE_INT hfp_save_offset;
2347 HOST_WIDE_INT reg_save_offset;
2348 HOST_WIDE_INT sse_reg_save_offset;
2350 /* When save_regs_using_mov is set, emit prologue using
2351 move instead of push instructions. */
2353 };
2355 /* Which cpu are we scheduling for. */
2358 /* Which cpu are we optimizing for. */
2361 /* Which instruction set architecture to use. */
2364 /* True if processor has SSE prefetch instruction. */
2367 /* -mstackrealign option */
2384 /* Preferred alignment for stack boundary in bits. */
2387 /* Alignment for incoming stack boundary in bits specified at
2388 command line. */
2391 /* Default alignment for incoming stack boundary in bits. */
2394 /* Alignment for incoming stack boundary in bits. */
2397 /* Calling abi specific va_list type nodes. */
2401 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2405 /* Fence to use after loop using movnt. */
2406 tree x86_mfence;
2408 /* Register class used for passing given 64bit part of the argument.
2409 These represent classes as documented by the PS ABI, with the exception
2410 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2411 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2413 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2414 whenever possible (upper half does contain padding). */
2415 enum x86_64_reg_class
2416 {
2417 X86_64_NO_CLASS,
2418 X86_64_INTEGER_CLASS,
2419 X86_64_INTEGERSI_CLASS,
2420 X86_64_SSE_CLASS,
2421 X86_64_SSESF_CLASS,
2422 X86_64_SSEDF_CLASS,
2423 X86_64_SSEUP_CLASS,
2424 X86_64_X87_CLASS,
2425 X86_64_X87UP_CLASS,
2426 X86_64_COMPLEX_X87_CLASS,
2427 X86_64_MEMORY_CLASS
2428 };
2430 #define MAX_CLASSES 8
2432 /* Table of constants used by fldpi, fldln2, etc.... */
2436 \f
2441 const_tree);
2453 enum ix86_function_specific_strings
2454 {
2455 IX86_FUNCTION_SPECIFIC_ARCH,
2456 IX86_FUNCTION_SPECIFIC_TUNE,
2457 IX86_FUNCTION_SPECIFIC_MAX
2458 };
2480 \f
2481 #ifndef SUBTARGET32_DEFAULT_CPU
2483 #endif
2485 /* Whether -mtune= or -march= were specified */
2489 /* Vectorization library interface and handlers. */
2495 /* Processor target table, indexed by processor number */
2496 struct ptt
2497 {
2505 };
2507 /* This table must be in sync with enum processor_type in i386.h. */
2509 {
2536 };
2537 \f
2538 static unsigned int
2540 {
2543 /* vzeroupper instructions are inserted immediately after reload to
2544 account for possible spills from 256bit registers. The pass
2545 reuses mode switching infrastructure by re-running mode insertion
2546 pass, so disable entities that have already been processed. */
2552 /* Call optimize_mode_switching. */
2555 }
2560 {
2570 };
2573 {
2577 {}
2579 /* opt_pass methods: */
2581 {
2585 }
2588 {
2590 }
2596 rtl_opt_pass *
2598 {
2600 }
2602 /* Return true if a red-zone is in use. */
2606 {
2608 }
2609 \f
2610 /* Return a string that documents the current -m options. The caller is
2611 responsible for freeing the string. */
2617 {
2618 struct ix86_target_opts
2619 {
2622 };
2624 /* This table is ordered so that options like -msse4.2 that imply
2625 preceding options while match those first. */
2627 {
2680 };
2682 /* Flag options. */
2684 {
2713 };
2730 /* Add -march= option. */
2732 {
2735 }
2737 /* Add -mtune= option. */
2739 {
2742 }
2744 /* Add -m32/-m64/-mx32. */
2746 {
2749 else
2751 isa &= ~ (OPTION_MASK_ISA_64BIT
2752 | OPTION_MASK_ABI_64
2754 }
2755 else
2759 /* Pick out the options in isa options. */
2761 {
2763 {
2766 }
2767 }
2770 {
2773 isa);
2774 }
2776 /* Add flag options. */
2778 {
2780 {
2783 }
2784 }
2787 {
2790 }
2792 /* Add -fpmath= option. */
2794 {
2797 {
2812 }
2813 }
2815 /* Any options? */
2821 /* Size the string. */
2825 {
2830 }
2832 /* Build the string. */
2837 {
2844 {
2846 line_len++;
2849 {
2853 }
2854 }
2858 {
2862 }
2863 }
2869 }
2871 /* Return true, if profiling code should be emitted before
2872 prologue. Otherwise it returns false.
2873 Note: For x86 with "hotfix" it is sorried. */
2874 static bool
2876 {
2878 }
2880 /* Function that is callable from the debugger to print the current
2881 options. */
2882 void ATTRIBUTE_UNUSED
2884 {
2890 {
2893 }
2894 else
2898 }
2901 #define DEF_ENUM
2902 #define DEF_ALG(alg, name) #name,
2904 #undef DEF_ENUM
2905 #undef DEF_ALG
2906 };
2908 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2909 The string is of the following form (or comma separated list of it):
2911 strategy_alg:max_size:[align|noalign]
2913 where the full size range for the strategy is either [0, max_size] or
2914 [min_size, max_size], in which min_size is the max_size + 1 of the
2915 preceding range. The last size range must have max_size == -1.
2917 Examples:
2919 1.
2920 -mmemcpy-strategy=libcall:-1:noalign
2922 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2925 2.
2926 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2928 This is to tell the compiler to use the following strategy for memset
2929 1) when the expected size is between [1, 16], use rep_8byte strategy;
2930 2) when the size is between [17, 2048], use vector_loop;
2931 3) when the size is > 2048, use libcall. */
2933 struct stringop_size_range
2934 {
2936 stringop_alg alg;
2938 };
2940 static void
2942 {
2950 else
2955 do
2956 {
2966 {
2970 }
2973 {
2977 }
2984 {
2986 alg_name,
2989 }
2997 else
2998 {
3002 }
3003 n++;
3005 }
3009 {
3014 }
3017 {
3021 }
3023 /* Now override the default algs array. */
3025 {
3031 }
3032 }
3034 \f
3035 /* parse -mtune-ctrl= option. When DUMP is true,
3036 print the features that are explicitly set. */
3038 static void
3040 {
3048 do
3049 {
3056 {
3057 curr_feature_string++;
3059 }
3061 {
3063 {
3069 }
3070 }
3075 }
3078 }
3080 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3081 processor type. */
3083 static void
3085 {
3090 {
3093 else
3095 }
3098 {
3103 }
3106 }
3109 /* Override various settings based on options. If MAIN_ARGS_P, the
3110 options are from the command line, otherwise they are from
3111 attributes. */
3113 static void
3117 {
3125 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3126 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3127 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3128 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3129 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3130 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3131 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3132 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3133 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3134 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3135 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3136 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3137 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3138 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3139 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3140 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3141 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3142 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3143 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3144 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3145 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3146 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3147 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3148 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3149 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3150 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3151 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3152 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3153 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3154 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3155 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3156 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3157 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3158 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3159 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3160 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3161 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3162 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3163 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3164 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3165 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3166 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3167 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3168 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3169 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3170 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3171 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3172 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3173 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3174 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3175 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3176 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3177 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3178 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3179 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3180 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3181 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3183 #define PTA_CORE2 \
3184 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3185 | PTA_CX16 | PTA_FXSR)
3186 #define PTA_NEHALEM \
3187 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3188 #define PTA_WESTMERE \
3189 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3190 #define PTA_SANDYBRIDGE \
3191 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3192 #define PTA_IVYBRIDGE \
3193 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3194 #define PTA_HASWELL \
3195 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3196 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3197 #define PTA_BROADWELL \
3198 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3199 #define PTA_KNL \
3200 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3201 #define PTA_BONNELL \
3202 (PTA_CORE2 | PTA_MOVBE)
3203 #define PTA_SILVERMONT \
3204 (PTA_WESTMERE | PTA_MOVBE)
3206 /* if this reaches 64, need to widen struct pta flags below */
3208 static struct pta
3209 {
3214 }
3216 {
3250 PTA_SANDYBRIDGE},
3252 PTA_SANDYBRIDGE},
3254 PTA_IVYBRIDGE},
3256 PTA_IVYBRIDGE},
3348 PTA_64BIT
3350 };
3352 /* -mrecip options. */
3353 static struct
3354 {
3357 }
3359 {
3366 };
3370 /* Set up prefix/suffix so the error messages refer to either the command
3371 line argument, or the attribute(target). */
3373 {
3377 }
3378 else
3379 {
3383 }
3385 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3386 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3389 #ifdef TARGET_BI_ARCH
3390 else
3391 {
3392 #if TARGET_BI_ARCH == 1
3393 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3394 is on and OPTION_MASK_ABI_X32 is off. We turn off
3395 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3396 -mx32. */
3399 #else
3400 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3401 on and OPTION_MASK_ABI_64 is off. We turn off
3402 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3403 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3407 #endif
3408 }
3409 #endif
3412 {
3413 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3414 OPTION_MASK_ABI_64 for TARGET_X32. */
3417 }
3420 | OPTION_MASK_ABI_X32
3423 {
3424 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3425 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3428 }
3430 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3431 SUBTARGET_OVERRIDE_OPTIONS;
3432 #endif
3434 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3435 SUBSUBTARGET_OVERRIDE_OPTIONS;
3436 #endif
3438 /* -fPIC is the default for x86_64. */
3442 /* Need to check -mtune=generic first. */
3444 {
3445 /* As special support for cross compilers we read -mtune=native
3446 as -mtune=generic. With native compilers we won't see the
3447 -mtune=native, as it was changed by the driver. */
3449 {
3451 }
3456 }
3457 else
3458 {
3462 {
3463 opts->x_ix86_tune_string
3466 }
3468 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3469 or defaulted. We need to use a sensible tune option. */
3471 {
3473 }
3474 }
3478 {
3479 /* rep; movq isn't available in 32-bit code. */
3482 }
3485 opts->x_ix86_arch_string
3488 else
3492 {
3500 }
3501 else
3508 /* For targets using ms ABI enable ms-extensions, if not
3509 explicit turned off. For non-ms ABI we turn off this
3510 option. */
3515 {
3517 {
3561 {
3564 }
3572 }
3573 }
3574 else
3575 {
3576 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3577 use of rip-relative addressing. This eliminates fixups that
3578 would otherwise be needed if this object is to be placed in a
3579 DLL, and is essentially just as efficient as direct addressing. */
3585 else
3587 }
3589 {
3592 }
3600 {
3603 /* Default cpu tuning to the architecture. */
3781 }
3805 {
3809 {
3811 {
3813 {
3821 }
3822 else
3825 }
3826 }
3827 /* Intel CPUs have always interpreted SSE prefetch instructions as
3828 NOPs; so, we can enable SSE prefetch instructions even when
3829 -mtune (rather than -march) points us to a processor that has them.
3830 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3831 higher processors. */
3836 }
3844 #ifndef USE_IX86_FRAME_POINTER
3845 #define USE_IX86_FRAME_POINTER 0
3846 #endif
3848 #ifndef USE_X86_64_FRAME_POINTER
3849 #define USE_X86_64_FRAME_POINTER 0
3850 #endif
3852 /* Set the default values for switches whose default depends on TARGET_64BIT
3853 in case they weren't overwritten by command line options. */
3855 {
3863 opts->x_flag_unwind_tables
3867 }
3868 else
3869 {
3871 opts->x_flag_omit_frame_pointer
3877 }
3880 /* TODO: ix86_cost should be chosen at instruction or function granuality
3881 so for cold code we use size_cost even in !optimize_size compilation. */
3884 else
3887 /* Arrange to set up i386_stack_locals for all functions. */
3890 /* Validate -mregparm= value. */
3892 {
3896 {
3900 }
3901 }
3905 /* Default align_* from the processor table. */
3907 {
3910 }
3912 {
3915 }
3917 {
3919 }
3921 /* Provide default for -mbranch-cost= value. */
3926 {
3927 opts->x_target_flags
3930 /* Enable by default the SSE and MMX builtins. Do allow the user to
3931 explicitly disable any of these. In particular, disabling SSE and
3932 MMX for kernel code is extremely useful. */
3934 opts->x_ix86_isa_flags
3941 }
3942 else
3943 {
3944 opts->x_target_flags
3948 opts->x_ix86_isa_flags
3951 /* i386 ABI does not specify red zone. It still makes sense to use it
3952 when programmer takes care to stack from being destroyed. */
3955 }
3957 /* Keep nonleaf frame pointers. */
3963 /* If we're doing fast math, we don't care about comparison order
3964 wrt NaNs. This lets us use a shorter comparison sequence. */
3968 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3969 since the insns won't need emulation. */
3973 /* Likewise, if the target doesn't have a 387, or we've specified
3974 software floating point, don't use 387 inline intrinsics. */
3978 /* Turn on MMX builtins for -msse. */
3980 opts->x_ix86_isa_flags
3983 /* Enable SSE prefetch. */
3988 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3991 opts->x_ix86_isa_flags
3994 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3997 opts->x_ix86_isa_flags
4000 /* Enable lzcnt instruction for -mabm. */
4002 opts->x_ix86_isa_flags
4005 /* Validate -mpreferred-stack-boundary= value or default it to
4006 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4009 {
4016 {
4020 else
4023 }
4024 else
4025 ix86_preferred_stack_boundary
4027 }
4029 /* Set the default value for -mstackrealign. */
4035 /* Validate -mincoming-stack-boundary= value or default it to
4036 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4039 {
4046 else
4047 {
4048 ix86_user_incoming_stack_boundary
4050 ix86_incoming_stack_boundary
4052 }
4053 }
4055 #ifndef NO_PROFILE_COUNTERS
4058 #endif
4062 /* Accept -msseregparm only if at least SSE support is enabled. */
4068 {
4070 {
4072 {
4075 }
4078 {
4081 }
4082 }
4083 }
4084 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4085 fpmath=387. The second is however default at many targets since the
4086 extra 80bit precision of temporaries is considered to be part of ABI.
4087 Overwrite the default at least for -ffast-math.
4088 TODO: -mfpmath=both seems to produce same performing code with bit
4089 smaller binaries. It is however not clear if register allocation is
4090 ready for this setting.
4091 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4092 codegen. We may switch to 387 with -ffast-math for size optimized
4093 functions. */
4097 else
4100 /* If the i387 is disabled, then do not return values in it. */
4104 /* Use external vectorized library in vectorizing intrinsics. */
4107 {
4118 }
4124 /* If stack probes are required, the space used for large function
4125 arguments on the stack must also be probed, so enable
4126 -maccumulate-outgoing-args so this happens in the prologue. */
4129 {
4134 }
4136 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4137 {
4143 }
4145 /* When scheduling description is not available, disable scheduler pass
4146 so it won't slow down the compilation and make x87 code slower. */
4167 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4169 && HAVE_prefetch
4174 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4175 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4180 {
4183 {
4185 ix86_gen_tls_local_dynamic_base_64
4187 }
4188 else
4189 {
4191 ix86_gen_tls_local_dynamic_base_64
4193 }
4194 }
4195 else
4199 {
4209 }
4210 else
4211 {
4221 }
4223 #ifdef USE_IX86_CLD
4224 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4227 #endif
4230 {
4235 }
4237 {
4241 }
4243 {
4244 #if defined(PROFILE_BEFORE_PROLOGUE)
4246 #else
4248 #endif
4249 }
4259 /* Enable 128-bit AVX instruction generation
4260 for the auto-vectorizer. */
4266 {
4273 {
4276 {
4278 q++;
4279 }
4280 else
4285 else
4286 {
4289 {
4292 }
4295 {
4299 }
4300 }
4305 else
4307 }
4308 }
4315 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4316 for 64-bit Bionic. */
4321 ? MASK_LONG_DOUBLE_128
4324 /* Only one of them can be active. */
4328 /* Save the initial options in case the user does function specific
4329 options. */
4331 target_option_default_node = target_option_current_node
4334 /* Handle stack protector */
4336 opts->x_ix86_stack_protector_guard
4339 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4341 {
4345 }
4348 {
4352 }
4353 }
4355 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4357 static void
4359 {
4361 struct register_pass_info insert_vzeroupper_info
4364 };
4369 /* This needs to be done at start up. It's convenient to do it here. */
4371 }
4373 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4376 {
4380 }
4382 /* Update register usage after having seen the compiler flags. */
4384 static void
4386 {
4389 /* For 32-bit targets, squash the REX registers. */
4391 {
4398 }
4400 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4408 {
4409 /* Set/reset conditionally defined registers from
4410 CALL_USED_REGISTERS initializer. */
4414 /* Calculate registers of CLOBBERED_REGS register set
4415 as call used registers from GENERAL_REGS register set. */
4419 }
4421 /* If MMX is disabled, squash the registers. */
4427 /* If SSE is disabled, squash the registers. */
4433 /* If the FPU is disabled, squash the registers. */
4439 /* If AVX512F is disabled, squash the registers. */
4441 {
4447 }
4449 /* If MPX is disabled, squash the registers. */
4453 }
4455 \f
4456 /* Save the current options */
4458 static void
4461 {
4497 /* The fields are char but the variables are not; make sure the
4498 values fit in the fields. */
4503 }
4505 /* Restore the current options */
4507 static void
4510 {
4516 /* We don't change -fPIC. */
4554 /* TODO: ix86_cost should be chosen at instruction or function granuality
4555 so for cold code we use size_cost even in !optimize_size compilation. */
4558 else
4561 /* Recreate the arch feature tests if the arch changed */
4563 {
4568 }
4570 /* Recreate the tune optimization tests */
4573 }
4575 /* Adjust target options after streaming them in. This is mainly about
4576 reconciling them with global options. */
4578 static void
4580 {
4581 /* flag_pic is a global option, but ix86_cmodel is target saved option
4582 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4583 for PIC, or error out. */
4586 {
4605 }
4606 else
4608 {
4623 }
4624 }
4626 /* Print the current options */
4628 static void
4631 {
4649 {
4652 }
4653 }
4655 \f
4656 /* Inner function to process the attribute((target(...))), take an argument and
4657 set the current options from the argument. If we have a list, recursively go
4658 over the list. */
4660 static bool
4665 {
4669 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4670 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4671 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4672 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4673 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4675 enum ix86_opt_type
4676 {
4677 ix86_opt_unknown,
4678 ix86_opt_yes,
4679 ix86_opt_no,
4680 ix86_opt_str,
4681 ix86_opt_enum,
4682 ix86_opt_isa
4683 };
4685 static const struct
4686 {
4693 /* isa options */
4746 /* enum options */
4749 /* string options */
4753 /* flag options */
4755 OPT_mcld,
4756 MASK_CLD),
4759 OPT_mfancy_math_387,
4760 MASK_NO_FANCY_MATH_387),
4763 OPT_mieee_fp,
4764 MASK_IEEE_FP),
4767 OPT_minline_all_stringops,
4768 MASK_INLINE_ALL_STRINGOPS),
4771 OPT_minline_stringops_dynamically,
4772 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4775 OPT_mno_align_stringops,
4776 MASK_NO_ALIGN_STRINGOPS),
4779 OPT_mrecip,
4780 MASK_RECIP),
4782 };
4784 /* If this is a list, recurse to get the options. */
4786 {
4793 enum_opts_set))
4797 }
4800 {
4803 }
4805 /* Handle multiple arguments separated by commas. */
4809 {
4823 {
4827 }
4828 else
4829 {
4832 }
4834 /* Recognize no-xxx. */
4836 {
4840 }
4841 else
4844 /* Find the option. */
4848 {
4856 {
4861 }
4862 }
4864 /* Process the option. */
4866 {
4869 }
4872 {
4878 }
4881 {
4887 else
4889 }
4892 {
4894 {
4897 }
4898 else
4900 }
4903 {
4911 global_dc);
4912 else
4913 {
4916 }
4917 }
4919 else
4921 }
4924 }
4926 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4928 tree
4932 {
4947 /* Process each of the options on the chain. */
4952 /* If the changed options are different from the default, rerun
4953 ix86_option_override_internal, and then save the options away.
4954 The string options are are attribute options, and will be undone
4955 when we copy the save structure. */
4961 {
4962 /* If we are using the default tune= or arch=, undo the string assigned,
4963 and use the default. */
4974 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4979 {
4982 }
4984 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4987 /* Add any builtin functions with the new isa if any. */
4990 /* Save the current options unless we are validating options for
4991 #pragma. */
4998 /* Free up memory allocated to hold the strings */
5001 }
5004 }
5006 /* Hook to validate attribute((target("string"))). */
5008 static bool
5011 tree args,
5013 {
5018 /* attribute((target("default"))) does nothing, beyond
5019 affecting multi-versioning. */
5028 /* Get the optimization options of the current function. */
5034 /* Init func_options. */
5042 /* Initialize func_options to the default before its target options can
5043 be set. */
5056 {
5061 }
5064 }
5066 \f
5067 /* Hook to determine if one function can safely inline another. */
5069 static bool
5071 {
5076 /* If callee has no option attributes, then it is ok to inline. */
5080 /* If caller has no option attributes, but callee does then it is not ok to
5081 inline. */
5085 else
5086 {
5090 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5091 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5092 function. */
5097 /* See if we have the same non-isa options. */
5101 /* See if arch, tune, etc. are the same. */
5114 else
5116 }
5119 }
5121 \f
5122 /* Remember the last target of ix86_set_current_function. */
5125 /* Set targets globals to the default (or current #pragma GCC target
5126 if active). Invalidate ix86_previous_fndecl cache. */
5128 void
5130 {
5137 else
5140 }
5142 /* Establish appropriate back-end context for processing the function
5143 FNDECL. The argument might be NULL to indicate processing at top
5144 level, outside of any function scope. */
5145 static void
5147 {
5148 /* Only change the context if the function changes. This hook is called
5149 several times in the course of compiling a function, and we don't want to
5150 slow things down too much or call target_reinit when it isn't safe. */
5154 tree old_tree;
5159 else
5163 {
5167 }
5174 {
5180 else
5182 }
5184 }
5186 \f
5187 /* Return true if this goes in large data/bss. */
5189 static bool
5191 {
5195 /* Functions are never large data. */
5199 /* Automatic variables are never large data. */
5204 {
5210 }
5211 else
5212 {
5215 /* If this is an incomplete type with size 0, then we can't put it
5216 in data because it might be too big when completed. Also,
5217 int_size_in_bytes returns -1 if size can vary or is larger than
5218 an integer in which case also it is safer to assume that it goes in
5219 large data. */
5222 }
5225 }
5227 /* Switch to the appropriate section for output of DECL.
5228 DECL is either a `VAR_DECL' node or a constant of some sort.
5229 RELOC indicates whether forming the initial value of DECL requires
5230 link-time relocations. */
5235 {
5237 {
5241 {
5275 /* We don't split these for medium model. Place them into
5276 default sections and hope for best. */
5278 }
5280 {
5281 /* We might get called with string constants, but get_named_section
5282 doesn't like them as they are not DECLs. Also, we need to set
5283 flags in that case. */
5287 }
5288 }
5290 }
5292 /* Select a set of attributes for section NAME based on the properties
5293 of DECL and whether or not RELOC indicates that DECL's initializer
5294 might contain runtime relocations. */
5296 static unsigned int ATTRIBUTE_UNUSED
5298 {
5312 }
5314 /* Build up a unique section name, expressed as a
5315 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5316 RELOC indicates whether the initial value of EXP requires
5317 link-time relocations. */
5319 static void ATTRIBUTE_UNUSED
5321 {
5323 {
5325 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5329 {
5353 /* We don't split these for medium model. Place them into
5354 default sections and hope for best. */
5356 }
5358 {
5365 /* If we're using one_only, then there needs to be a .gnu.linkonce
5366 prefix to the section name. */
5373 }
5374 }
5376 }
5378 #ifdef COMMON_ASM_OP
5379 /* This says how to output assembler code to declare an
5380 uninitialized external linkage data object.
5382 For medium model x86-64 we need to use .largecomm opcode for
5383 large objects. */
5384 void
5388 {
5392 else
5397 }
5398 #endif
5400 /* Utility function for targets to use in implementing
5401 ASM_OUTPUT_ALIGNED_BSS. */
5403 void
5406 {
5410 else
5413 #ifdef ASM_DECLARE_OBJECT_NAME
5416 #else
5417 /* Standard thing is just output label for the object. */
5421 }
5422 \f
5423 /* Decide whether we must probe the stack before any space allocation
5424 on this target. It's essentially TARGET_STACK_PROBE except when
5425 -fstack-check causes the stack to be already probed differently. */
5427 bool
5429 {
5430 /* Do not probe the stack twice if static stack checking is enabled. */
5435 }
5436 \f
5437 /* Decide whether we can make a sibling call to a function. DECL is the
5438 declaration of the function being targeted by the call and EXP is the
5439 CALL_EXPR representing the call. */
5441 static bool
5443 {
5447 /* If we are generating position-independent code, we cannot sibcall
5448 optimize any indirect call, or a direct call to a global function,
5449 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5451 && !TARGET_64BIT
5452 && flag_pic
5456 /* If we need to align the outgoing stack, then sibcalling would
5457 unalign the stack, which may break the called function. */
5463 {
5466 }
5467 else
5468 {
5469 /* We're looking at the CALL_EXPR, we need the type of the function. */
5474 }
5476 /* Check that the return value locations are the same. Like
5477 if we are returning floats on the 80387 register stack, we cannot
5478 make a sibcall from a function that doesn't return a float to a
5479 function that does or, conversely, from a function that does return
5480 a float to a function that doesn't; the necessary stack adjustment
5481 would not be executed. This is also the place we notice
5482 differences in the return value ABI. Note that it is ok for one
5483 of the functions to have void return type as long as the return
5484 value of the other is passed in a register. */
5489 {
5492 }
5494 ;
5499 {
5500 /* The SYSV ABI has more call-clobbered registers;
5501 disallow sibcalls from MS to SYSV. */
5505 }
5506 else
5507 {
5508 /* If this call is indirect, we'll need to be able to use a
5509 call-clobbered register for the address of the target function.
5510 Make sure that all such registers are not used for passing
5511 parameters. Note that DLLIMPORT functions are indirect. */
5514 {
5516 {
5517 /* ??? Need to count the actual number of registers to be used,
5518 not the possible number of registers. Fix later. */
5520 }
5521 }
5522 }
5524 /* Otherwise okay. That also includes certain types of indirect calls. */
5526 }
5528 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5529 and "sseregparm" calling convention attributes;
5530 arguments as in struct attribute_spec.handler. */
5532 static tree
5534 tree args,
5537 {
5542 {
5544 name);
5547 }
5549 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5551 {
5552 tree cst;
5555 {
5557 }
5560 {
5562 }
5566 {
5569 name);
5571 }
5573 {
5577 }
5580 }
5583 {
5584 /* Do not warn when emulating the MS ABI. */
5589 name);
5592 }
5594 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5596 {
5598 {
5600 }
5602 {
5604 }
5606 {
5608 }
5610 {
5612 }
5613 }
5615 /* Can combine stdcall with fastcall (redundant), regparm and
5616 sseregparm. */
5618 {
5620 {
5622 }
5624 {
5626 }
5628 {
5630 }
5631 }
5633 /* Can combine cdecl with regparm and sseregparm. */
5635 {
5637 {
5639 }
5641 {
5643 }
5645 {
5647 }
5648 }
5650 {
5653 name);
5655 {
5657 }
5659 {
5661 }
5663 {
5665 }
5666 }
5668 /* Can combine sseregparm with all attributes. */
5671 }
5673 /* The transactional memory builtins are implicitly regparm or fastcall
5674 depending on the ABI. Override the generic do-nothing attribute that
5675 these builtins were declared with, and replace it with one of the two
5676 attributes that we expect elsewhere. */
5678 static tree
5681 {
5682 tree alt;
5684 /* In no case do we want to add the placeholder attribute. */
5687 /* The 64-bit ABI is unchanged for transactional memory. */
5691 /* ??? Is there a better way to validate 32-bit windows? We have
5692 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5695 else
5696 {
5699 }
5703 }
5705 /* This function determines from TYPE the calling-convention. */
5707 unsigned int
5709 {
5712 tree attrs;
5719 {
5729 /* Regparam isn't allowed for thiscall and fastcall. */
5731 {
5736 }
5740 }
5747 || is_stdarg
5753 }
5755 /* Return 0 if the attributes for two types are incompatible, 1 if they
5756 are compatible, and 2 if they are nearly compatible (which causes a
5757 warning to be generated). */
5759 static int
5761 {
5777 }
5778 \f
5779 /* Return the regparm value for a function with the indicated TYPE and DECL.
5780 DECL may be NULL when calling function indirectly
5781 or considering a libcall. */
5783 static int
5785 {
5786 tree attr;
5797 {
5800 {
5803 }
5804 }
5810 /* Use register calling convention for local functions when possible. */
5813 {
5818 /* Caller and callee must agree on the calling convention, so
5819 checking here just optimize means that with
5820 __attribute__((optimize (...))) caller could use regparm convention
5821 and callee not, or vice versa. Instead look at whether the callee
5822 is optimized or not. */
5825 {
5828 {
5831 /* Make sure no regparm register is taken by a
5832 fixed register variable. */
5834 local_regparm++)
5838 /* We don't want to use regparm(3) for nested functions as
5839 these use a static chain pointer in the third argument. */
5843 /* Save a register for the split stack. */
5847 /* Each fixed register usage increases register pressure,
5848 so less registers should be used for argument passing.
5849 This functionality can be overriden by an explicit
5850 regparm value. */
5853 globals++;
5855 local_regparm
5860 }
5861 }
5862 }
5865 }
5867 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5868 DFmode (2) arguments in SSE registers for a function with the
5869 indicated TYPE and DECL. DECL may be NULL when calling function
5870 indirectly or considering a libcall. Otherwise return 0. */
5872 static int
5874 {
5877 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5878 by the sseregparm attribute. */
5881 {
5883 {
5885 {
5889 else
5892 }
5894 }
5897 }
5906 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5907 (and DFmode for SSE2) arguments in SSE registers. */
5909 /* TARGET_SSE_MATH */
5913 {
5916 {
5917 /* Refuse to produce wrong code when local function with SSE enabled
5918 is called from SSE disabled function.
5919 We may work hard to work out these scenarios but hopefully
5920 it doesnot matter in practice. */
5922 {
5926 }
5929 }
5930 }
5933 }
5935 /* Return true if EAX is live at the start of the function. Used by
5936 ix86_expand_prologue to determine if we need special help before
5937 calling allocate_stack_worker. */
5939 static bool
5941 {
5942 /* Cheat. Don't bother working forward from ix86_function_regparm
5943 to the function type to whether an actual argument is located in
5944 eax. Instead just look at cfg info, which is still close enough
5945 to correct at this point. This gives false positives for broken
5946 functions that might use uninitialized data that happens to be
5947 allocated in eax, but who cares? */
5949 }
5951 static bool
5953 {
5954 tree attr;
5957 {
5963 /* For 32-bit MS-ABI the default is to keep aggregate
5964 return pointer. */
5967 }
5969 }
5971 /* Value is the number of bytes of arguments automatically
5972 popped when returning from a subroutine call.
5973 FUNDECL is the declaration node of the function (as a tree),
5974 FUNTYPE is the data type of the function (as a tree),
5975 or for a library call it is an identifier node for the subroutine name.
5976 SIZE is the number of bytes of arguments passed on the stack.
5978 On the 80386, the RTD insn may be used to pop them if the number
5979 of args is fixed, but if the number is variable then the caller
5980 must pop them all. RTD can't be used for library calls now
5981 because the library is compiled with the Unix compiler.
5982 Use of RTD is a selectable option, since it is incompatible with
5983 standard Unix calling sequences. If the option is not selected,
5984 the caller must always pop the args.
5986 The attribute stdcall is equivalent to RTD on a per module basis. */
5988 static int
5990 {
5993 /* None of the 64-bit ABIs pop arguments. */
6004 /* Lose any fake structure return argument if it is passed on the stack. */
6007 {
6011 }
6014 }
6016 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6018 static bool
6020 {
6021 /* Check operand constraints in case hard registers were propagated
6022 into insn pattern. This check prevents combine pass from
6023 generating insn patterns with invalid hard register operands.
6024 These invalid insns can eventually confuse reload to error out
6025 with a spill failure. See also PRs 46829 and 46843. */
6027 {
6036 {
6044 /* For pre-AVX disallow unaligned loads/stores where the
6045 instructions don't support it. */
6049 {
6053 }
6055 /* A unary operator may be accepted by the predicate, but it
6056 is irrelevant for matching constraints. */
6061 {
6069 }
6076 /* Operand has no constraints, anything is OK. */
6081 {
6086 && operands_match_p
6090 {
6093 }
6094 }
6098 }
6099 }
6102 }
6103 \f
6104 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6106 static unsigned HOST_WIDE_INT
6108 {
6112 }
6113 \f
6114 /* Argument support functions. */
6116 /* Return true when register may be used to pass function parameters. */
6117 bool
6119 {
6127 {
6131 else
6137 }
6143 /* TODO: The function should depend on current function ABI but
6144 builtins.c would need updating then. Therefore we use the
6145 default ABI. */
6147 /* RAX is used as hidden argument to va_arg functions. */
6153 else
6160 }
6162 /* Return if we do not know how to pass TYPE solely in registers. */
6164 static bool
6166 {
6170 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6171 The layout_type routine is crafty and tries to trick us into passing
6172 currently unsupported vector types on the stack by using TImode. */
6175 }
6177 /* It returns the size, in bytes, of the area reserved for arguments passed
6178 in registers for the function represented by fndecl dependent to the used
6179 abi format. */
6180 int
6182 {
6186 else
6191 }
6193 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6194 call abi used. */
6195 enum calling_abi
6197 {
6199 {
6202 {
6204 {
6206 {
6209 {
6212 }
6213 }
6215 }
6216 }
6220 }
6222 }
6224 /* We add this as a workaround in order to use libc_has_function
6225 hook in i386.md. */
6226 bool
6228 {
6230 }
6232 static bool
6234 {
6236 {
6240 else
6242 }
6244 }
6246 static enum calling_abi
6248 {
6252 }
6254 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6255 call abi used. */
6256 enum calling_abi
6258 {
6262 }
6264 /* Write the extra assembler code needed to declare a function properly. */
6266 void
6268 tree decl)
6269 {
6273 {
6279 }
6281 #ifdef SUBTARGET_ASM_UNWIND_INIT
6283 #endif
6287 /* Output magic byte marker, if hot-patch attribute is set. */
6289 {
6291 {
6292 /* leaq [%rsp + 0], %rsp */
6295 }
6296 else
6297 {
6298 /* movl.s %edi, %edi
6299 push %ebp
6300 movl.s %esp, %ebp */
6303 }
6304 }
6305 }
6307 /* regclass.c */
6310 /* Implementation of call abi switching target hook. Specific to FNDECL
6311 the specific call register sets are set. See also
6312 ix86_conditional_register_usage for more details. */
6313 void
6315 {
6318 else
6320 }
6322 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6323 expensive re-initialization of init_regs each time we switch function context
6324 since this is needed only during RTL expansion. */
6325 static void
6327 {
6331 }
6333 /* Return 1 if pseudo register should be created and used to hold
6334 GOT address for PIC code. */
6335 bool
6337 {
6344 }
6346 /* Initialize large model PIC register. */
6348 static void
6350 {
6352 rtx tmp_reg;
6361 label));
6365 }
6367 /* Create and initialize PIC register if required. */
6368 static void
6370 {
6371 edge entry_edge;
6380 {
6383 else
6385 }
6386 else
6387 {
6388 /* If there is future mcount call in the function it is more profitable
6389 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6398 }
6406 }
6408 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6409 for a call to a function whose data type is FNTYPE.
6410 For a library call, FNTYPE is 0. */
6412 void
6416 tree fndecl,
6418 {
6425 {
6428 {
6432 }
6433 else
6435 }
6436 else
6441 /* Set up the number of registers to use for passing arguments. */
6444 {
6446 ? X86_64_REGPARM_MAX
6448 }
6450 {
6453 {
6455 ? X86_64_SSE_REGPARM_MAX
6457 }
6458 }
6466 /* Because type might mismatch in between caller and callee, we need to
6467 use actual type of function for local calls.
6468 FIXME: cgraph_analyze can be told to actually record if function uses
6469 va_start so for local functions maybe_vaarg can be made aggressive
6470 helping K&R code.
6471 FIXME: once typesytem is fixed, we won't need this code anymore. */
6484 {
6485 /* If there are variable arguments, then we won't pass anything
6486 in registers in 32-bit mode. */
6488 {
6497 }
6499 /* Use ecx and edx registers if function has fastcall attribute,
6500 else look for regparm information. */
6502 {
6505 {
6508 }
6510 {
6513 }
6514 else
6516 }
6518 /* Set up the number of SSE registers used for passing SFmode
6519 and DFmode arguments. Warn for mismatching ABI. */
6521 }
6522 }
6524 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6525 But in the case of vector types, it is some vector mode.
6527 When we have only some of our vector isa extensions enabled, then there
6528 are some modes for which vector_mode_supported_p is false. For these
6529 modes, the generic vector support in gcc will choose some non-vector mode
6530 in order to implement the type. By computing the natural mode, we'll
6531 select the proper ABI location for the operand and not depend on whatever
6532 the middle-end decides to do with these vector types.
6534 The midde-end can't deal with the vector types > 16 bytes. In this
6535 case, we return the original mode and warn ABI change if CUM isn't
6536 NULL.
6538 If INT_RETURN is true, warn ABI change if the vector mode isn't
6539 available for function return value. */
6541 static machine_mode
6544 {
6548 {
6551 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6553 {
6558 else
6561 /* Get the mode which has this inner mode and number of units. */
6565 {
6567 {
6572 {
6576 }
6578 {
6582 }
6585 }
6587 {
6592 {
6596 }
6598 {
6602 }
6605 }
6608 {
6613 {
6617 }
6619 {
6623 }
6624 }
6626 {
6631 {
6635 }
6637 {
6641 }
6642 }
6644 }
6647 }
6648 }
6651 }
6653 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6654 this may not agree with the mode that the type system has chosen for the
6655 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6656 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6658 static rtx
6661 {
6662 rtx tmp;
6666 else
6667 {
6671 }
6674 }
6676 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6677 of this code is to classify each 8bytes of incoming argument by the register
6678 class and assign registers accordingly. */
6680 /* Return the union class of CLASS1 and CLASS2.
6681 See the x86-64 PS ABI for details. */
6683 static enum x86_64_reg_class
6685 {
6686 /* Rule #1: If both classes are equal, this is the resulting class. */
6690 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6691 the other class. */
6697 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6701 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6709 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6710 MEMORY is used. */
6719 /* Rule #6: Otherwise class SSE is used. */
6721 }
6723 /* Classify the argument of type TYPE and mode MODE.
6724 CLASSES will be filled by the register class used to pass each word
6725 of the operand. The number of words is returned. In case the parameter
6726 should be passed in memory, 0 is returned. As a special case for zero
6727 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6729 BIT_OFFSET is used internally for handling records and specifies offset
6730 of the offset in bits modulo 512 to avoid overflow cases.
6732 See the x86-64 PS ABI for details.
6733 */
6735 static int
6738 {
6739 HOST_WIDE_INT bytes =
6741 int words
6744 /* Variable sized entities are always passed/returned in memory. */
6752 /* Special case check for pointer to shared, on 64-bit target. */
6756 {
6759 }
6762 {
6764 tree field;
6767 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6774 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6775 signalize memory class, so handle it as special case. */
6777 {
6780 }
6782 /* Classify each field of record and merge classes. */
6784 {
6786 /* And now merge the fields of structure. */
6788 {
6790 {
6796 /* Bitfields are always classified as integer. Handle them
6797 early, since later code would consider them to be
6798 misaligned integers. */
6800 {
6809 }
6810 else
6811 {
6816 /* Flexible array member is ignored. */
6823 {
6827 {
6830 "the ABI of passing struct with"
6831 " a flexible array member has"
6833 }
6835 }
6837 subclasses,
6847 }
6848 }
6849 }
6853 /* Arrays are handled as small records. */
6854 {
6861 /* The partial classes are now full classes. */
6872 }
6875 /* Unions are similar to RECORD_TYPE but offset is always 0.
6876 */
6878 {
6880 {
6888 bit_offset);
6893 }
6894 }
6899 }
6902 {
6903 /* When size > 16 bytes, if the first one isn't
6904 X86_64_SSE_CLASS or any other ones aren't
6905 X86_64_SSEUP_CLASS, everything should be passed in
6906 memory. */
6913 }
6915 /* Final merger cleanup. */
6917 {
6918 /* If one class is MEMORY, everything should be passed in
6919 memory. */
6923 /* The X86_64_SSEUP_CLASS should be always preceded by
6924 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6928 {
6929 /* The first one should never be X86_64_SSEUP_CLASS. */
6932 }
6934 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6935 everything should be passed in memory. */
6938 {
6941 /* The first one should never be X86_64_X87UP_CLASS. */
6944 {
6947 "the ABI of passing union with long double"
6949 }
6951 }
6952 }
6954 }
6956 /* Compute alignment needed. We align all types to natural boundaries with
6957 exception of XFmode that is aligned to 64bits. */
6959 {
6968 /* Misaligned fields are always returned in memory. */
6971 }
6973 /* for V1xx modes, just use the base mode */
6978 /* Classification of atomic types. */
6980 {
6996 {
6999 /* Analyze last 128 bits only. */
7003 {
7006 }
7008 {
7011 }
7013 {
7017 }
7019 {
7022 }
7023 else
7025 }
7032 /* OImode shouldn't be used directly. */
7039 else
7057 else
7058 {
7062 {
7065 "the ABI of passing structure with complex float"
7067 }
7070 }
7079 /* This modes is larger than 16 bytes. */
7137 else
7141 }
7142 }
7144 /* Examine the argument and return set number of register required in each
7145 class. Return true iff parameter should be passed in memory. */
7147 static bool
7150 {
7161 {
7182 }
7185 }
7187 /* Construct container for the argument used by GCC interface. See
7188 FUNCTION_ARG for the detailed description. */
7190 static rtx
7194 {
7195 /* The following variables hold the static issued_error state. */
7200 machine_mode tmpmode;
7209 rtx ret;
7220 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7221 some less clueful developer tries to use floating-point anyway. */
7223 {
7225 {
7227 {
7230 }
7231 }
7233 {
7236 }
7238 }
7240 /* Likewise, error if the ABI requires us to return values in the
7241 x87 registers and the user specified -mno-80387. */
7247 {
7249 {
7252 }
7254 }
7256 /* First construct simple cases. Avoid SCmode, since we want to use
7257 single register to pass this type. */
7260 {
7275 /* Zero sized array, struct or class. */
7279 }
7318 /* Otherwise figure out the entries of the PARALLEL. */
7320 {
7324 {
7329 /* Merge TImodes on aligned occasions here too. */
7331 tmpmode
7335 else
7337 /* We've requested 24 bytes we
7338 don't have mode for. Use DImode. */
7345 intreg++;
7353 sse_regno++;
7361 sse_regno++;
7366 {
7372 {
7374 i++;
7375 }
7376 else
7401 }
7407 sse_regno++;
7411 }
7412 }
7414 /* Empty aligned struct, union or class. */
7422 }
7424 /* Update the data in CUM to advance over an argument of mode MODE
7425 and data type TYPE. (TYPE is null for libcalls where that information
7426 may not be available.)
7428 Return a number of integer regsiters advanced over. */
7430 static int
7433 HOST_WIDE_INT words)
7434 {
7438 {
7445 /* FALLTHRU */
7457 {
7460 }
7464 /* OImode shouldn't be used directly. */
7473 /* FALLTHRU */
7495 {
7500 {
7503 }
7504 }
7514 {
7519 {
7522 }
7523 }
7525 }
7528 }
7530 static int
7533 {
7536 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7543 {
7549 }
7550 else
7551 {
7556 }
7557 }
7559 static int
7561 HOST_WIDE_INT words)
7562 {
7563 /* Otherwise, this should be passed indirect. */
7568 {
7572 }
7574 }
7576 /* Update the data in CUM to advance over an argument of mode MODE and
7577 data type TYPE. (TYPE is null for libcalls where that information
7578 may not be available.) */
7580 static void
7583 {
7590 else
7599 {
7600 /* If we pass bounds in BT then just update remained bounds count. */
7602 {
7605 }
7607 /* Update remained number of bounds to force. */
7614 }
7616 /* The first arg not going to Bounds Tables resets this counter. */
7618 /* For unnamed args we always pass bounds to avoid bounds mess when
7619 passed and received types do not match. If bounds do not follow
7620 unnamed arg, still pretend required number of bounds were passed. */
7622 {
7625 }
7631 else
7634 /* For stdarg we expect bounds to be passed for each value passed
7635 in register. */
7638 /* For pointers passed in memory we expect bounds passed in Bounds
7639 Table. */
7642 }
7644 /* Define where to put the arguments to a function.
7645 Value is zero to push the argument on the stack,
7646 or a hard register in which to store the argument.
7648 MODE is the argument's machine mode.
7649 TYPE is the data type of the argument (as a tree).
7650 This is null for libcalls where that information may
7651 not be available.
7652 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7653 the preceding args and about the function being called.
7654 NAMED is nonzero if this argument is a named parameter
7655 (otherwise it is an extra parameter matching an ellipsis). */
7657 static rtx
7661 {
7662 /* Avoid the AL settings for the Unix64 ABI. */
7667 {
7674 /* FALLTHRU */
7680 {
7683 /* Fastcall allocates the first two DWORD (SImode) or
7684 smaller arguments to ECX and EDX if it isn't an
7685 aggregate type . */
7687 {
7693 /* ECX not EAX is the first allocated register. */
7696 }
7698 }
7707 /* FALLTHRU */
7709 /* In 32bit, we pass TImode in xmm registers. */
7717 {
7721 }
7726 /* OImode and XImode shouldn't be used directly. */
7742 {
7746 }
7756 {
7760 }
7762 }
7765 }
7767 static rtx
7770 {
7771 /* Handle a hidden AL argument containing number of registers
7772 for varargs x86-64 functions. */
7776 ? X86_64_SSE_REGPARM_MAX
7781 {
7797 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7801 }
7807 }
7809 static rtx
7812 HOST_WIDE_INT bytes)
7813 {
7816 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7817 We use value of -2 to specify that current function call is MSABI. */
7821 /* If we've run out of registers, it goes on the stack. */
7827 /* Only floating point modes are passed in anything but integer regs. */
7829 {
7832 else
7833 {
7836 /* Unnamed floating parameters are passed in both the
7837 SSE and integer registers. */
7843 }
7844 }
7845 /* Handle aggregated types passed in register. */
7847 {
7852 }
7855 }
7857 /* Return where to put the arguments to a function.
7858 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7860 MODE is the argument's machine mode. TYPE is the data type of the
7861 argument. It is null for libcalls where that information may not be
7862 available. CUM gives information about the preceding args and about
7863 the function being called. NAMED is nonzero if this argument is a
7864 named parameter (otherwise it is an extra parameter matching an
7865 ellipsis). */
7867 static rtx
7870 {
7874 rtx arg;
7876 /* All pointer bounds argumntas are handled separately here. */
7879 {
7880 /* Return NULL if bounds are forced to go in Bounds Table. */
7883 /* Return the next available bound reg if any. */
7886 /* Return the next special slot number otherwise. */
7887 else
7891 }
7895 else
7899 /* To simplify the code below, represent vector types with a vector mode
7900 even if MMX/SSE are not active. */
7908 else
7912 }
7914 /* A C expression that indicates when an argument must be passed by
7915 reference. If nonzero for an argument, a copy of that argument is
7916 made in memory and a pointer to the argument is passed instead of
7917 the argument itself. The pointer is passed in whatever way is
7918 appropriate for passing a pointer to that type. */
7920 static bool
7923 {
7926 /* Bounds are never passed by reference. */
7931 /* See Windows x64 Software Convention. */
7933 {
7936 {
7937 /* Arrays are passed by reference. */
7942 {
7943 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7944 are passed by reference. */
7946 }
7947 }
7949 /* __m128 is passed by reference. */
7955 }
7956 }
7961 }
7963 /* Return true when TYPE should be 128bit aligned for 32bit argument
7964 passing ABI. XXX: This function is obsolete and is only used for
7965 checking psABI compatibility with previous versions of GCC. */
7967 static bool
7969 {
7981 {
7982 /* Walk the aggregates recursively. */
7984 {
7988 {
7989 tree field;
7991 /* Walk all the structure fields. */
7993 {
7997 }
7999 }
8002 /* Just for use if some languages passes arrays by value. */
8009 }
8010 }
8012 }
8014 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8015 XXX: This function is obsolete and is only used for checking psABI
8016 compatibility with previous versions of GCC. */
8018 static unsigned int
8021 {
8022 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8023 natural boundaries. */
8025 {
8026 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8027 make an exception for SSE modes since these require 128bit
8028 alignment.
8030 The handling here differs from field_alignment. ICC aligns MMX
8031 arguments to 4 byte boundaries, while structure fields are aligned
8032 to 8 byte boundaries. */
8034 {
8037 }
8038 else
8039 {
8042 }
8043 }
8047 }
8049 /* Return true when TYPE should be 128bit aligned for 32bit argument
8050 passing ABI. */
8052 static bool
8054 {
8064 {
8065 /* Walk the aggregates recursively. */
8067 {
8071 {
8072 tree field;
8074 /* Walk all the structure fields. */
8076 field;
8078 {
8082 }
8084 }
8087 /* Just for use if some languages passes arrays by value. */
8094 }
8095 }
8096 else
8100 }
8102 /* Gives the alignment boundary, in bits, of an argument with the
8103 specified mode and type. */
8105 static unsigned int
8107 {
8110 {
8111 /* Since the main variant type is used for call, we convert it to
8112 the main variant type. */
8115 }
8116 else
8120 else
8121 {
8126 {
8127 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8129 {
8132 }
8138 }
8141 && !warned
8143 saved_align))
8144 {
8147 "The ABI for passing parameters with %d-byte"
8150 }
8151 }
8154 }
8156 /* Return true if N is a possible register number of function value. */
8158 static bool
8160 {
8162 {
8174 /* Complex values are returned in %st(0)/%st(1) pair. */
8177 /* TODO: The function should depend on current function ABI but
8178 builtins.c would need updating then. Therefore we use the
8179 default ABI. */
8184 /* Complex values are returned in %xmm0/%xmm1 pair. */
8193 }
8196 }
8198 /* Define how to find the value returned by a function.
8199 VALTYPE is the data type of the value (as a tree).
8200 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8201 otherwise, FUNC is 0. */
8203 static rtx
8206 {
8209 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8210 we normally prevent this case when mmx is not available. However
8211 some ABIs may require the result to be returned like DImode. */
8215 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8216 we prevent this case when sse is not available. However some ABIs
8217 may require the result to be returned like integer TImode. */
8222 /* 32-byte vector modes in %ymm0. */
8226 /* 64-byte vector modes in %zmm0. */
8230 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8233 else
8234 /* Most things go in %eax. */
8237 /* Override FP return register with %xmm0 for local functions when
8238 SSE math is enabled or for functions with sseregparm attribute. */
8240 {
8245 }
8247 /* OImode shouldn't be used directly. */
8251 }
8253 static rtx
8255 const_tree valtype)
8256 {
8257 rtx ret;
8259 /* Handle libcalls, which don't provide a type node. */
8261 {
8265 {
8284 }
8287 }
8290 {
8291 /* Pointers are always returned in word_mode. */
8293 }
8299 /* For zero sized structures, construct_container returns NULL, but we
8300 need to keep rest of compiler happy by returning meaningful value. */
8305 }
8307 static rtx
8309 const_tree valtype)
8310 {
8314 {
8316 {
8335 }
8336 }
8338 }
8340 static rtx
8343 {
8358 else
8360 }
8362 static rtx
8364 {
8370 }
8372 /* Return an RTX representing a place where a function returns
8373 or recieves pointer bounds or NULL if no bounds are returned.
8375 VALTYPE is a data type of a value returned by the function.
8377 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8378 or FUNCTION_TYPE of the function.
8380 If OUTGOING is false, return a place in which the caller will
8381 see the return value. Otherwise, return a place where a
8382 function returns a value. */
8384 static rtx
8386 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8388 {
8394 {
8395 bitmap slots;
8397 bitmap_iterator bi;
8405 {
8410 }
8416 }
8417 else
8421 }
8423 /* Pointer function arguments and return values are promoted to
8424 word_mode. */
8426 static machine_mode
8430 {
8432 {
8434 {
8437 }
8440 }
8442 for_return);
8443 }
8445 /* Return true if a structure, union or array with MODE containing FIELD
8446 should be accessed using BLKmode. */
8448 static bool
8450 {
8451 /* Union with XFmode must be in BLKmode. */
8455 }
8457 rtx
8459 {
8461 }
8463 /* Return true iff type is returned in memory. */
8465 static bool
8467 {
8468 #ifdef SUBTARGET_RETURN_IN_MEMORY
8470 #else
8472 HOST_WIDE_INT size;
8478 {
8480 {
8483 /* __m128 is returned in xmm0. */
8492 /* Otherwise, the size must be exactly in [1248]. */
8494 }
8495 else
8496 {
8501 }
8502 }
8503 else
8504 {
8514 {
8515 /* User-created vectors small enough to fit in EAX. */
8519 /* Unless ABI prescibes otherwise,
8520 MMX/3dNow values are returned in MM0 if available. */
8525 /* SSE values are returned in XMM0 if available. */
8529 /* AVX values are returned in YMM0 if available. */
8533 /* AVX512F values are returned in ZMM0 if available. */
8536 }
8544 /* OImode shouldn't be used directly. */
8548 }
8549 #endif
8550 }
8552 \f
8553 /* Create the va_list data type. */
8555 /* Returns the calling convention specific va_list date type.
8556 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8558 static tree
8560 {
8563 /* For i386 we use plain pointer to argument area. */
8573 unsigned_type_node);
8576 unsigned_type_node);
8579 ptr_type_node);
8582 ptr_type_node);
8601 /* The correct type is an array type of one element. */
8603 }
8605 /* Setup the builtin va_list data type and for 64-bit the additional
8606 calling convention specific va_list data types. */
8608 static tree
8610 {
8613 /* Initialize abi specific va_list builtin types. */
8615 {
8616 tree t;
8618 {
8623 }
8624 else
8625 {
8630 }
8632 {
8637 }
8638 else
8639 {
8644 }
8645 }
8648 }
8650 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8652 static void
8654 {
8656 alias_set_type set;
8659 /* GPR size of varargs save area. */
8662 else
8665 /* FPR size of varargs save area. We don't need it if we don't pass
8666 anything in SSE registers. */
8669 else
8683 {
8691 }
8694 {
8695 machine_mode smode;
8697 rtx test;
8699 /* Now emit code to save SSE registers. The AX parameter contains number
8700 of SSE parameter registers used to call this function, though all we
8701 actually check here is the zero/non-zero status. */
8706 label));
8708 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8709 we used movdqa (i.e. TImode) instead? Perhaps even better would
8710 be if we could determine the real mode of the data, via a hook
8711 into pass_stdarg. Ignore all that for now. */
8721 {
8730 }
8733 }
8734 }
8736 static void
8738 {
8742 /* Reset to zero, as there might be a sysv vaarg used
8743 before. */
8748 {
8759 }
8760 }
8762 static void
8765 {
8767 CUMULATIVE_ARGS next_cum;
8768 tree fntype;
8770 /* This argument doesn't appear to be used anymore. Which is good,
8771 because the old code here didn't suppress rtl generation. */
8779 /* For varargs, we do not want to skip the dummy va_dcl argument.
8780 For stdargs, we do want to skip the last named argument. */
8788 else
8790 }
8792 static void
8795 tree type,
8798 {
8800 CUMULATIVE_ARGS next_cum;
8801 tree fntype;
8802 rtx save_area;
8807 /* Do nothing if we use plain pointer to argument area. */
8813 /* For varargs, we do not want to skip the dummy va_dcl argument.
8814 For stdargs, we do want to skip the last named argument. */
8828 {
8833 rtx bounds;
8837 else
8838 {
8839 rtx ldx_addr =
8846 }
8852 bnd_reg++;
8853 }
8854 }
8857 /* Checks if TYPE is of kind va_list char *. */
8859 static bool
8861 {
8862 tree canonic;
8864 /* For 32-bit it is always true. */
8870 }
8872 /* Implement va_start. */
8874 static void
8876 {
8880 tree type;
8881 rtx ovf_rtx;
8885 {
8888 /* When we are splitting the stack, we can't refer to the stack
8889 arguments using internal_arg_pointer, because they may be on
8890 the old stack. The split stack prologue will arrange to
8891 leave a pointer to the old stack arguments in a scratch
8892 register, which we here copy to a pseudo-register. The split
8893 stack prologue can't set the pseudo-register directly because
8894 it (the prologue) runs before any registers have been saved. */
8898 {
8899 rtx reg;
8913 }
8914 }
8916 /* Only 64bit target needs something special. */
8918 {
8921 else
8922 {
8932 /* Store zero bounds for va_list. */
8936 next));
8938 }
8940 }
8949 /* The following should be folded into the MEM_REF offset. */
8959 /* Count number of gp and fp argument registers used. */
8965 {
8971 }
8974 {
8980 }
8982 /* Find the overflow area. */
8986 else
8992 /* Store zero bounds for overflow area pointer. */
9001 {
9002 /* Find the register save area.
9003 Prologue of the function save it right above stack frame. */
9009 /* Store zero bounds for save area pointer. */
9016 }
9017 }
9019 /* Implement va_arg. */
9021 static tree
9024 {
9031 rtx container;
9033 tree ptrtype;
9034 machine_mode nat_mode;
9037 /* Only 64bit target needs something special. */
9061 {
9074 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9076 {
9079 }
9087 }
9089 /* Pull the value out of the saved registers. */
9094 {
9108 /* In case we are passing structure, verify that it is consecutive block
9109 on the register save area. If not we need to do moves. */
9111 {
9112 /* Verify that all registers are strictly consecutive */
9114 {
9118 {
9123 }
9124 }
9125 else
9126 {
9130 {
9135 }
9136 }
9137 }
9139 {
9142 }
9143 else
9144 {
9147 }
9149 /* First ensure that we fit completely in registers. */
9151 {
9158 }
9160 {
9168 }
9170 /* Compute index to start of area used for integer regs. */
9172 {
9173 /* int_addr = gpr + sav; */
9176 }
9178 {
9179 /* sse_addr = fpr + sav; */
9182 }
9184 {
9188 /* addr = &temp; */
9193 {
9197 tree piece_type;
9198 tree addr_type;
9199 tree daddr_type;
9208 {
9213 }
9217 else
9224 {
9227 }
9228 else
9229 {
9232 }
9239 {
9244 }
9245 else
9246 {
9247 tree copy
9252 }
9254 }
9255 }
9258 {
9262 }
9265 {
9269 }
9274 }
9276 /* ... otherwise out of the overflow area. */
9278 /* When we align parameter on stack for caller, if the parameter
9279 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9280 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9281 here with caller. */
9286 /* Care for on-stack alignment if needed. */
9289 else
9290 {
9295 }
9312 }
9313 \f
9314 /* Return true if OPNUM's MEM should be matched
9315 in movabs* patterns. */
9317 bool
9319 {
9331 }
9332 \f
9333 /* Initialize the table of extra 80387 mathematical constants. */
9335 static void
9337 {
9339 {
9345 };
9349 {
9351 /* Ensure each constant is rounded to XFmode precision. */
9354 }
9357 }
9359 /* Return non-zero if the constant is something that
9360 can be loaded with a special instruction. */
9362 int
9364 {
9367 REAL_VALUE_TYPE r;
9379 /* For XFmode constants, try to find a special 80387 instruction when
9380 optimizing for size or on those CPUs that benefit from them. */
9383 {
9392 }
9394 /* Load of the constant -0.0 or -1.0 will be split as
9395 fldz;fchs or fld1;fchs sequence. */
9402 }
9404 /* Return the opcode of the special instruction to be used to load
9405 the constant X. */
9409 {
9411 {
9431 }
9432 }
9434 /* Return the CONST_DOUBLE representing the 80387 constant that is
9435 loaded by the specified special instruction. The argument IDX
9436 matches the return value from standard_80387_constant_p. */
9438 rtx
9440 {
9447 {
9458 }
9461 XFmode);
9462 }
9464 /* Return 1 if X is all 0s and 2 if x is all 1s
9465 in supported SSE/AVX vector mode. */
9467 int
9469 {
9476 {
9497 }
9500 }
9502 /* Return the opcode of the special instruction to be used to load
9503 the constant X. */
9507 {
9509 {
9512 {
9539 }
9549 else
9554 }
9556 }
9558 /* Returns true if OP contains a symbol reference */
9560 bool
9562 {
9571 {
9573 {
9579 }
9583 }
9586 }
9588 /* Return true if it is appropriate to emit `ret' instructions in the
9589 body of a function. Do this only if the epilogue is simple, needing a
9590 couple of insns. Prior to reloading, we can't tell how many registers
9591 must be saved, so return false then. Return false if there is no frame
9592 marker to de-allocate. */
9594 bool
9596 {
9602 /* Don't allow more than 32k pop, since that's all we can do
9603 with one instruction. */
9610 }
9611 \f
9612 /* Value should be nonzero if functions must have frame pointers.
9613 Zero means the frame pointer need not be set up (and parms may
9614 be accessed via the stack pointer) in functions that seem suitable. */
9616 static bool
9618 {
9619 /* If we accessed previous frames, then the generated code expects
9620 to be able to access the saved ebp value in our frame. */
9624 /* Several x86 os'es need a frame pointer for other reasons,
9625 usually pertaining to setjmp. */
9629 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9633 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9634 allocation is 4GB. */
9638 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9639 turns off the frame pointer by default. Turn it back on now if
9640 we've not got a leaf function. */
9650 }
9652 /* Record that the current function accesses previous call frames. */
9654 void
9656 {
9658 }
9659 \f
9660 #ifndef USE_HIDDEN_LINKONCE
9661 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9662 # define USE_HIDDEN_LINKONCE 1
9663 # else
9664 # define USE_HIDDEN_LINKONCE 0
9665 # endif
9666 #endif
9670 /* Fills in the label name that should be used for a pc thunk for
9671 the given register. */
9673 static void
9675 {
9680 else
9682 }
9685 /* This function generates code for -fpic that loads %ebx with
9686 the return address of the caller and then returns. */
9688 static void
9690 {
9695 {
9697 tree decl;
9713 #if TARGET_MACHO
9715 {
9724 }
9725 else
9726 #endif
9728 {
9739 }
9740 else
9741 {
9744 }
9750 /* Make sure unwind info is emitted for the thunk if needed. */
9753 /* Pad stack IP move with 4 instructions (two NOPs count
9754 as one instruction). */
9756 {
9761 }
9772 }
9776 }
9778 /* Emit code for the SET_GOT patterns. */
9782 {
9788 {
9789 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9794 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9795 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9796 an unadorned address. */
9801 }
9806 {
9808 /* We don't need a pic base, we're not producing pic. */
9815 }
9816 else
9817 {
9826 #if TARGET_MACHO
9827 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9828 This is what will be referenced by the Mach-O PIC subsystem. */
9832 /* When we are restoring the pic base at the site of a nonlocal label,
9833 and we decided to emit the pic base above, we will still output a
9834 local label used for calculating the correction offset (even though
9835 the offset will be 0 in that case). */
9839 #endif
9840 }
9846 }
9848 /* Generate an "push" pattern for input ARG. */
9850 static rtx
9852 {
9865 stack_pointer_rtx)),
9866 arg);
9867 }
9869 /* Generate an "pop" pattern for input ARG. */
9871 static rtx
9873 {
9878 arg,
9881 stack_pointer_rtx)));
9882 }
9884 /* Return >= 0 if there is an unused call-clobbered register available
9885 for the entire function. */
9887 static unsigned int
9889 {
9896 {
9898 /* Can't use the same register for both PIC and DRAP. */
9901 else
9906 }
9909 }
9911 /* Return TRUE if we need to save REGNO. */
9913 static bool
9915 {
9918 {
9920 {
9921 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9922 _mcount in prologue. */
9925 }
9932 }
9935 {
9938 {
9944 }
9945 }
9956 }
9958 /* Return number of saved general prupose registers. */
9960 static int
9962 {
9968 nregs ++;
9970 }
9972 /* Return number of saved SSE registrers. */
9974 static int
9976 {
9984 nregs ++;
9986 }
9988 /* Given FROM and TO register numbers, say whether this elimination is
9989 allowed. If stack alignment is needed, we can only replace argument
9990 pointer with hard frame pointer, or replace frame pointer with stack
9991 pointer. Otherwise, frame pointer elimination is automatically
9992 handled and all other eliminations are valid. */
9994 static bool
9996 {
10002 else
10004 }
10006 /* Return the offset between two registers, one to be eliminated, and the other
10007 its replacement, at the start of a routine. */
10009 HOST_WIDE_INT
10011 {
10020 else
10021 {
10029 }
10030 }
10032 /* In a dynamically-aligned function, we can't know the offset from
10033 stack pointer to frame pointer, so we must ensure that setjmp
10034 eliminates fp against the hard fp (%ebp) rather than trying to
10035 index from %esp up to the top of the frame across a gap that is
10036 of unknown (at compile-time) size. */
10037 static rtx
10039 {
10041 }
10043 /* When using -fsplit-stack, the allocation routines set a field in
10044 the TCB to the bottom of the stack plus this much space, measured
10045 in bytes. */
10047 #define SPLIT_STACK_AVAILABLE 256
10049 /* Fill structure ix86_frame about frame of currently computed function. */
10051 static void
10053 {
10055 HOST_WIDE_INT offset;
10058 HOST_WIDE_INT to_allocate;
10063 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10064 function prologues and leaf. */
10068 {
10071 }
10072 /* preferred_stack_boundary is never updated for call
10073 expanded from tls descriptor. Update it here. We don't update it in
10074 expand stage because according to the comments before
10075 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10076 away. */
10079 {
10083 }
10092 /* For SEH we have to limit the amount of code movement into the prologue.
10093 At present we do this via a BLOCKAGE, at which point there's very little
10094 scheduling that can be done, which means that there's very little point
10095 in doing anything except PUSHs. */
10099 /* During reload iteration the amount of registers saved can change.
10100 Recompute the value as needed. Do not recompute when amount of registers
10101 didn't change as reload does multiple calls to the function and does not
10102 expect the decision to change within single iteration. */
10105 {
10111 /* The fast prologue uses move instead of push to save registers. This
10112 is significantly longer, but also executes faster as modern hardware
10113 can execute the moves in parallel, but can't do that for push/pop.
10115 Be careful about choosing what prologue to emit: When function takes
10116 many instructions to execute we may use slow version as well as in
10117 case function is known to be outside hot spot (this is known with
10118 feedback only). Weight the size of function by number of registers
10119 to save as it is cheap to use one or two push instructions but very
10120 slow to use many of them. */
10124 || (flag_branch_probabilities
10127 else
10130 }
10132 frame->save_regs_using_mov
10134 /* If static stack checking is enabled and done with probes,
10135 the registers need to be saved before allocating the frame. */
10138 /* Skip return address. */
10141 /* Skip pushed static chain. */
10145 /* Skip saved base pointer. */
10150 /* The traditional frame pointer location is at the top of the frame. */
10153 /* Register save area */
10157 /* On SEH target, registers are pushed just before the frame pointer
10158 location. */
10162 /* Align and set SSE register save area. */
10164 {
10165 /* The only ABI that has saved SSE registers (Win64) also has a
10166 16-byte aligned default stack, and thus we don't need to be
10167 within the re-aligned local stack frame to save them. */
10171 }
10174 /* The re-aligned stack starts here. Values before this point are not
10175 directly comparable with values below this point. In order to make
10176 sure that no value happens to be the same before and after, force
10177 the alignment computation below to add a non-zero value. */
10181 /* Va-arg area */
10185 /* Align start of frame for local function. */
10194 /* Frame pointer points here. */
10199 /* Add outgoing arguments area. Can be skipped if we eliminated
10200 all the function calls as dead code.
10201 Skipping is however impossible when function calls alloca. Alloca
10202 expander assumes that last crtl->outgoing_args_size
10203 of stack frame are unused. */
10207 {
10210 }
10211 else
10214 /* Align stack boundary. Only needed if we're calling another function
10215 or using alloca. */
10220 /* We've reached end of stack frame. */
10223 /* Size prologue needs to allocate. */
10234 {
10240 }
10241 else
10245 /* The SEH frame pointer location is near the bottom of the frame.
10246 This is enforced by the fact that the difference between the
10247 stack pointer and the frame pointer is limited to 240 bytes in
10248 the unwind data structure. */
10250 {
10251 HOST_WIDE_INT diff;
10253 /* If we can leave the frame pointer where it is, do so. Also, returns
10254 the establisher frame for __builtin_frame_address (0). */
10259 {
10260 /* Ideally we'd determine what portion of the local stack frame
10261 (within the constraint of the lowest 240) is most heavily used.
10262 But without that complication, simply bias the frame pointer
10263 by 128 bytes so as to maximize the amount of the local stack
10264 frame that is addressable with 8-bit offsets. */
10266 }
10267 }
10268 }
10270 /* This is semi-inlined memory_address_length, but simplified
10271 since we know that we're always dealing with reg+offset, and
10272 to avoid having to create and discard all that rtl. */
10276 {
10280 {
10281 /* EBP and R13 cannot be encoded without an offset. */
10283 }
10287 /* ESP and R12 must be encoded with a SIB byte. */
10289 len++;
10292 }
10294 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10295 The valid base registers are taken from CFUN->MACHINE->FS. */
10297 static rtx
10299 {
10305 {
10306 /* Choose the base register most likely to allow the most scheduling
10307 opportunities. Generally FP is valid throughout the function,
10308 while DRAP must be reloaded within the epilogue. But choose either
10309 over the SP due to increased encoding size. */
10312 {
10315 }
10317 {
10320 }
10322 {
10325 }
10326 }
10327 else
10328 {
10329 HOST_WIDE_INT toffset;
10332 /* Choose the base register with the smallest address encoding.
10333 With a tie, choose FP > DRAP > SP. */
10335 {
10339 }
10341 {
10345 {
10349 }
10350 }
10352 {
10356 {
10360 }
10361 }
10362 }
10366 }
10368 /* Emit code to save registers in the prologue. */
10370 static void
10372 {
10374 rtx insn;
10378 {
10381 }
10382 }
10384 /* Emit a single register save at CFA - CFA_OFFSET. */
10386 static void
10388 HOST_WIDE_INT cfa_offset)
10389 {
10397 /* For SSE saves, we need to indicate the 128-bit alignment. */
10408 /* When saving registers into a re-aligned local stack frame, avoid
10409 any tricky guessing by dwarf2out. */
10411 {
10415 {
10416 /* A bit of a hack. We force the DRAP register to be saved in
10417 the re-aligned stack frame, which provides us with a copy
10418 of the CFA that will last past the prologue. Install it. */
10424 }
10425 else
10426 {
10427 /* The frame pointer is a stable reference within the
10428 aligned frame. Use it. */
10435 }
10436 }
10438 /* The memory may not be relative to the current CFA register,
10439 which means that we may need to generate a new pattern for
10440 use by the unwind info. */
10442 {
10447 }
10448 }
10450 /* Emit code to save registers using MOV insns.
10451 First register is stored at CFA - CFA_OFFSET. */
10452 static void
10454 {
10459 {
10462 }
10463 }
10465 /* Emit code to save SSE registers using MOV insns.
10466 First register is stored at CFA - CFA_OFFSET. */
10467 static void
10469 {
10474 {
10477 }
10478 }
10482 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10483 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10484 Don't add the note if the previously saved value will be left untouched
10485 within stack red-zone till return, as unwinders can find the same value
10486 in the register and on the stack. */
10488 static void
10490 {
10496 {
10499 }
10500 else
10501 queued_cfa_restores
10503 }
10505 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10507 static void
10509 {
10510 rtx last;
10514 ;
10519 }
10521 /* Expand prologue or epilogue stack adjustment.
10522 The pattern exist to put a dependency on all ebp-based memory accesses.
10523 STYLE should be negative if instructions should be marked as frame related,
10524 zero if %r11 register is live and cannot be freely used and positive
10525 otherwise. */
10527 static void
10530 {
10532 rtx insn;
10539 else
10540 {
10541 rtx tmp;
10542 /* r11 is used by indirect sibcall return as well, set before the
10543 epilogue and used after the epilogue. */
10546 else
10547 {
10551 }
10557 }
10564 {
10565 rtx r;
10575 }
10577 {
10580 {
10584 }
10585 }
10588 {
10593 {
10596 }
10598 {
10601 }
10602 else
10603 {
10604 /* Else there are two possibilities: SP itself, which we set
10605 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10606 taken care of this by hand along the eh_return path. */
10609 }
10613 }
10614 }
10616 /* Find an available register to be used as dynamic realign argument
10617 pointer regsiter. Such a register will be written in prologue and
10618 used in begin of body, so it must not be
10619 1. parameter passing register.
10620 2. GOT pointer.
10621 We reuse static-chain register if it is available. Otherwise, we
10622 use DI for i386 and R13 for x86-64. We chose R13 since it has
10623 shorter encoding.
10625 Return: the regno of chosen register. */
10627 static unsigned int
10629 {
10633 {
10634 /* Use R13 for nested function or function need static chain.
10635 Since function with tail call may use any caller-saved
10636 registers in epilogue, DRAP must not use caller-saved
10637 register in such case. */
10642 }
10643 else
10644 {
10645 /* Use DI for nested function or function need static chain.
10646 Since function with tail call may use any caller-saved
10647 registers in epilogue, DRAP must not use caller-saved
10648 register in such case. */
10652 /* Reuse static chain register if it isn't used for parameter
10653 passing. */
10655 {
10659 }
10661 }
10662 }
10664 /* Return minimum incoming stack alignment. */
10666 static unsigned int
10668 {
10671 /* Prefer the one specified at command line. */
10674 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10675 if -mstackrealign is used, it isn't used for sibcall check and
10676 estimated stack alignment is 128bit. */
10678 && !TARGET_64BIT
10679 && ix86_force_align_arg_pointer
10682 else
10685 /* Incoming stack alignment can be changed on individual functions
10686 via force_align_arg_pointer attribute. We use the smallest
10687 incoming stack boundary. */
10693 /* The incoming stack frame has to be aligned at least at
10694 parm_stack_boundary. */
10698 /* Stack at entrance of main is aligned by runtime. We use the
10699 smallest incoming stack boundary. */
10707 }
10709 /* Update incoming stack boundary and estimated stack alignment. */
10711 static void
10713 {
10714 ix86_incoming_stack_boundary
10717 /* x86_64 vararg needs 16byte stack alignment for register save
10718 area. */
10723 }
10725 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10726 needed or an rtx for DRAP otherwise. */
10728 static rtx
10730 {
10735 {
10736 /* Assign DRAP to vDRAP and returns vDRAP */
10738 rtx drap_vreg;
10739 rtx arg_ptr;
10752 {
10755 }
10757 }
10758 else
10760 }
10762 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10764 static rtx
10766 {
10768 }
10771 rtx reg;
10773 };
10775 /* Return a short-lived scratch register for use on function entry.
10776 In 32-bit mode, it is valid only after the registers are saved
10777 in the prologue. This register must be released by means of
10778 release_scratch_register_on_entry once it is dead. */
10780 static void
10782 {
10788 {
10789 /* We always use R11 in 64-bit mode. */
10791 }
10792 else
10793 {
10795 bool fastcall_p
10797 bool thiscall_p
10801 int drap_regno
10804 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10805 for the static chain register. */
10809 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10810 for the static chain register. */
10815 /* ecx is the static chain register. */
10817 && !static_chain_p
10822 /* esi is the static chain register. */
10828 else
10829 {
10832 }
10833 }
10837 {
10840 }
10841 }
10843 /* Release a scratch register obtained from the preceding function. */
10845 static void
10847 {
10849 {
10853 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10859 }
10860 }
10862 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10864 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10866 static void
10868 {
10869 /* We skip the probe for the first interval + a small dope of 4 words and
10870 probe that many bytes past the specified size to maintain a protection
10871 area at the botton of the stack. */
10875 /* See if we have a constant small number of probes to generate. If so,
10876 that's the easy case. The run-time loop is made up of 11 insns in the
10877 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10878 for n # of intervals. */
10880 {
10884 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10885 values of N from 1 until it exceeds SIZE. If only one probe is
10886 needed, this will not generate any code. Then adjust and probe
10887 to PROBE_INTERVAL + SIZE. */
10889 {
10891 {
10894 }
10895 else
10902 }
10906 else
10914 /* Adjust back to account for the additional first interval. */
10918 }
10920 /* Otherwise, do the same as above, but in a loop. Note that we must be
10921 extra careful with variables wrapping around because we might be at
10922 the very top (or the very bottom) of the address space and we have
10923 to be able to handle this case properly; in particular, we use an
10924 equality test for the loop condition. */
10925 else
10926 {
10927 HOST_WIDE_INT rounded_size;
10933 /* Step 1: round SIZE to the previous multiple of the interval. */
10938 /* Step 2: compute initial and final value of the loop counter. */
10940 /* SP = SP_0 + PROBE_INTERVAL. */
10945 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10949 stack_pointer_rtx)));
10952 /* Step 3: the loop
10954 while (SP != LAST_ADDR)
10955 {
10956 SP = SP + PROBE_INTERVAL
10957 probe at SP
10958 }
10960 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10961 values of N from 1 until it is equal to ROUNDED_SIZE. */
10966 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10967 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10970 {
10975 }
10977 /* Adjust back to account for the additional first interval. */
10983 }
10987 /* Even if the stack pointer isn't the CFA register, we need to correctly
10988 describe the adjustments made to it, in particular differentiate the
10989 frame-related ones from the frame-unrelated ones. */
10991 {
11004 }
11006 /* Make sure nothing is scheduled before we are done. */
11008 }
11010 /* Adjust the stack pointer up to REG while probing it. */
11014 {
11024 /* Jump to END_LAB if SP == LAST_ADDR. */
11032 /* SP = SP + PROBE_INTERVAL. */
11036 /* Probe at SP. */
11047 }
11049 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11050 inclusive. These are offsets from the current stack pointer. */
11052 static void
11054 {
11055 /* See if we have a constant small number of probes to generate. If so,
11056 that's the easy case. The run-time loop is made up of 7 insns in the
11057 generic case while the compile-time loop is made up of n insns for n #
11058 of intervals. */
11060 {
11061 HOST_WIDE_INT i;
11063 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11064 it exceeds SIZE. If only one probe is needed, this will not
11065 generate any code. Then probe at FIRST + SIZE. */
11072 }
11074 /* Otherwise, do the same as above, but in a loop. Note that we must be
11075 extra careful with variables wrapping around because we might be at
11076 the very top (or the very bottom) of the address space and we have
11077 to be able to handle this case properly; in particular, we use an
11078 equality test for the loop condition. */
11079 else
11080 {
11087 /* Step 1: round SIZE to the previous multiple of the interval. */
11092 /* Step 2: compute initial and final value of the loop counter. */
11094 /* TEST_OFFSET = FIRST. */
11097 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11101 /* Step 3: the loop
11103 while (TEST_ADDR != LAST_ADDR)
11104 {
11105 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11106 probe at TEST_ADDR
11107 }
11109 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11110 until it is equal to ROUNDED_SIZE. */
11115 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11116 that SIZE is equal to ROUNDED_SIZE. */
11121 stack_pointer_rtx,
11126 }
11128 /* Make sure nothing is scheduled before we are done. */
11130 }
11132 /* Probe a range of stack addresses from REG to END, inclusive. These are
11133 offsets from the current stack pointer. */
11137 {
11147 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11155 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11159 /* Probe at TEST_ADDR. */
11172 }
11174 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11175 to be generated in correct form. */
11176 static void
11178 {
11179 /* Check if stack realign is really needed after reload, and
11180 stores result in cfun */
11181 unsigned int incoming_stack_boundary
11190 {
11191 /* After stack_realign_needed is finalized, we can't no longer
11192 change it. */
11195 }
11197 /* If the only reason for frame_pointer_needed is that we conservatively
11198 assumed stack realignment might be needed, but in the end nothing that
11199 needed the stack alignment had been spilled, clear frame_pointer_needed
11200 and say we don't need stack realignment. */
11202 && frame_pointer_needed
11204 && flag_omit_frame_pointer
11206 && !ix86_current_function_calls_tls_descriptor
11215 {
11217 basic_block bb;
11224 HARD_FRAME_POINTER_REGNUM);
11226 {
11231 set_up_by_prologue))
11232 {
11236 }
11237 }
11239 /* If drap has been set, but it actually isn't live at the start
11240 of the function, there is no reason to set it up. */
11242 {
11245 {
11248 }
11249 }
11250 else
11265 }
11269 }
11271 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11273 static void
11275 {
11281 {
11284 {
11290 }
11291 }
11292 }
11294 /* Expand the prologue into a bunch of separate insns. */
11296 void
11298 {
11302 HOST_WIDE_INT allocate;
11308 /* DRAP should not coexist with stack_realign_fp */
11313 /* Initialize CFA state for before the prologue. */
11317 /* Track SP offset to the CFA. We continue tracking this after we've
11318 swapped the CFA register away from SP. In the case of re-alignment
11319 this is fudged; we're interested to offsets within the local frame. */
11326 {
11327 /* We should have already generated an error for any use of
11328 ms_hook on a nested function. */
11331 /* Check if profiling is active and we shall use profiling before
11332 prologue variant. If so sorry. */
11337 /* In ix86_asm_output_function_label we emitted:
11338 8b ff movl.s %edi,%edi
11339 55 push %ebp
11340 8b ec movl.s %esp,%ebp
11342 This matches the hookable function prologue in Win32 API
11343 functions in Microsoft Windows XP Service Pack 2 and newer.
11344 Wine uses this to enable Windows apps to hook the Win32 API
11345 functions provided by Wine.
11347 What that means is that we've already set up the frame pointer. */
11351 {
11354 /* We've decided to use the frame pointer already set up.
11355 Describe this to the unwinder by pretending that both
11356 push and mov insns happen right here.
11358 Putting the unwind info here at the end of the ms_hook
11359 is done so that we can make absolutely certain we get
11360 the required byte sequence at the start of the function,
11361 rather than relying on an assembler that can produce
11362 the exact encoding required.
11364 However it does mean (in the unpatched case) that we have
11365 a 1 insn window where the asynchronous unwind info is
11366 incorrect. However, if we placed the unwind info at
11367 its correct location we would have incorrect unwind info
11368 in the patched case. Which is probably all moot since
11369 I don't expect Wine generates dwarf2 unwind info for the
11370 system libraries that use this feature. */
11376 stack_pointer_rtx);
11384 /* Note that gen_push incremented m->fs.cfa_offset, even
11385 though we didn't emit the push insn here. */
11389 }
11390 else
11391 {
11392 /* The frame pointer is not needed so pop %ebp again.
11393 This leaves us with a pristine state. */
11395 }
11396 }
11398 /* The first insn of a function that accepts its static chain on the
11399 stack is to push the register that would be filled in by a direct
11400 call. This insn will be skipped by the trampoline. */
11402 {
11406 /* We don't want to interpret this push insn as a register save,
11407 only as a stack adjustment. The real copy of the register as
11408 a save will be done later, if needed. */
11413 }
11415 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11416 of DRAP is needed and stack realignment is really needed after reload */
11418 {
11421 /* Only need to push parameter pointer reg if it is caller saved. */
11423 {
11424 /* Push arg pointer reg */
11427 }
11429 /* Grab the argument pointer. */
11436 /* Align the stack. */
11438 stack_pointer_rtx,
11442 /* Replicate the return address on the stack so that return
11443 address can be reached via (argp - 1) slot. This is needed
11444 to implement macro RETURN_ADDR_RTX and intrinsic function
11445 expand_builtin_return_addr etc. */
11451 /* For the purposes of frame and register save area addressing,
11452 we've started over with a new frame. */
11455 }
11461 {
11462 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11463 slower on all targets. Also sdb doesn't like it. */
11467 /* Push registers now, before setting the frame pointer
11468 on SEH target. */
11470 && TARGET_SEH
11472 {
11476 }
11479 {
11487 }
11488 }
11491 {
11492 /* If saving registers via PUSH, do so now. */
11494 {
11498 }
11500 /* When using red zone we may start register saving before allocating
11501 the stack frame saving one cycle of the prologue. However, avoid
11502 doing this if we have to probe the stack; at least on x86_64 the
11503 stack probe can turn into a call that clobbers a red zone location. */
11505 && (! TARGET_STACK_PROBE
11507 {
11510 }
11511 }
11514 {
11518 /* The computation of the size of the re-aligned stack frame means
11519 that we must allocate the size of the register save area before
11520 performing the actual alignment. Otherwise we cannot guarantee
11521 that there's enough storage above the realignment point. */
11528 /* Align the stack. */
11530 stack_pointer_rtx,
11533 /* For the purposes of register save area addressing, the stack
11534 pointer is no longer valid. As for the value of sp_offset,
11535 see ix86_compute_frame_layout, which we need to match in order
11536 to pass verification of stack_pointer_offset at the end. */
11539 }
11544 {
11545 /* We start to count from ARG_POINTER. */
11548 /* If it was realigned, take into account the fake frame. */
11550 {
11557 /* This over-estimates by 1 minimal-stack-alignment-unit but
11558 mitigates that by counting in the new return address slot. */
11559 current_function_dynamic_stack_size
11561 }
11564 }
11566 /* On SEH target with very large frame size, allocate an area to save
11567 SSE registers (as the very large allocation won't be described). */
11571 {
11572 HOST_WIDE_INT sse_size =
11577 /* No need to do stack checking as the area will be immediately
11578 written. */
11585 }
11587 /* The stack has already been decremented by the instruction calling us
11588 so probe if the size is non-negative to preserve the protection area. */
11590 {
11591 /* We expect the registers to be saved when probes are used. */
11595 {
11598 {
11601 }
11602 }
11603 else
11604 {
11611 {
11613 {
11616 }
11617 else
11619 }
11620 else
11621 {
11623 {
11627 }
11628 else
11630 }
11631 }
11632 }
11635 ;
11638 {
11642 }
11643 else
11644 {
11656 {
11659 /* Note that SEH directives need to continue tracking the stack
11660 pointer even after the frame pointer has been set up. */
11662 {
11670 }
11671 }
11674 {
11679 {
11687 }
11688 }
11693 /* Use the fact that AX still contains ALLOCATE. */
11695 ? gen_pro_epilogue_adjust_stack_di_sub
11702 {
11710 }
11713 /* Use stack_pointer_rtx for relative addressing so that code
11714 works for realigned stack, too. */
11716 {
11723 }
11725 {
11730 }
11731 }
11734 /* If we havn't already set up the frame pointer, do so now. */
11736 {
11748 }
11755 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11756 in PROLOGUE. */
11758 {
11764 /* Deleting already emmitted SET_GOT if exist and allocated to
11765 REAL_PIC_OFFSET_TABLE_REGNUM. */
11767 }
11770 {
11771 /* vDRAP is setup but after reload it turns out stack realign
11772 isn't necessary, here we will emit prologue to setup DRAP
11773 without stack realign adjustment */
11776 }
11778 /* Prevent instructions from being scheduled into register save push
11779 sequence when access to the redzone area is done through frame pointer.
11780 The offset between the frame pointer and the stack pointer is calculated
11781 relative to the value of the stack pointer at the end of the function
11782 prologue, and moving instructions that access redzone area via frame
11783 pointer inside push sequence violates this assumption. */
11787 /* Emit cld instruction if stringops are used in the function. */
11791 /* SEH requires that the prologue end within 256 bytes of the start of
11792 the function. Prevent instruction schedules that would extend that.
11793 Further, prevent alloca modifications to the stack pointer from being
11794 combined with prologue modifications. */
11797 }
11799 /* Emit code to restore REG using a POP insn. */
11801 static void
11803 {
11812 {
11813 /* Previously we'd represented the CFA as an expression
11814 like *(%ebp - 8). We've just popped that value from
11815 the stack, which means we need to reset the CFA to
11816 the drap register. This will remain until we restore
11817 the stack pointer. */
11821 /* This means that the DRAP register is valid for addressing too. */
11824 }
11827 {
11834 }
11836 /* When the frame pointer is the CFA, and we pop it, we are
11837 swapping back to the stack pointer as the CFA. This happens
11838 for stack frames that don't allocate other data, so we assume
11839 the stack pointer is now pointing at the return address, i.e.
11840 the function entry state, which makes the offset be 1 word. */
11842 {
11845 {
11853 }
11854 }
11855 }
11857 /* Emit code to restore saved registers using POP insns. */
11859 static void
11861 {
11867 }
11869 /* Emit code and notes for the LEAVE instruction. */
11871 static void
11873 {
11885 {
11893 }
11896 }
11898 /* Emit code to restore saved registers using MOV insns.
11899 First register is restored from CFA - CFA_OFFSET. */
11900 static void
11903 {
11909 {
11918 {
11919 /* Previously we'd represented the CFA as an expression
11920 like *(%ebp - 8). We've just popped that value from
11921 the stack, which means we need to reset the CFA to
11922 the drap register. This will remain until we restore
11923 the stack pointer. */
11927 /* This means that the DRAP register is valid for addressing. */
11929 }
11930 else
11934 }
11935 }
11937 /* Emit code to restore saved registers using MOV insns.
11938 First register is restored from CFA - CFA_OFFSET. */
11939 static void
11942 {
11947 {
11949 rtx mem;
11959 }
11960 }
11962 /* Restore function stack, frame, and registers. */
11964 void
11966 {
11982 /* The FP must be valid if the frame pointer is present. */
11987 /* We must have *some* valid pointer to the stack frame. */
11990 /* The DRAP is never valid at this point. */
11993 /* See the comment about red zone and frame
11994 pointer usage in ix86_expand_prologue. */
12001 /* Determine the CFA offset of the end of the red-zone. */
12004 {
12005 /* The red-zone begins below the return address. */
12008 /* When the register save area is in the aligned portion of
12009 the stack, determine the maximum runtime displacement that
12010 matches up with the aligned frame. */
12014 }
12016 /* Special care must be taken for the normal return case of a function
12017 using eh_return: the eax and edx registers are marked as saved, but
12018 not restored along this path. Adjust the save location to match. */
12022 /* EH_RETURN requires the use of moves to function properly. */
12025 /* SEH requires the use of pops to identify the epilogue. */
12028 /* If we're only restoring one register and sp is not valid then
12029 using a move instruction to restore the register since it's
12030 less work than reloading sp and popping the register. */
12043 && TARGET_USE_LEAVE
12047 else
12051 {
12052 /* Ensure that the entire register save area is addressable via
12053 the stack pointer, if we will restore via sp. */
12058 {
12062 style,
12064 }
12065 }
12067 /* If there are any SSE registers to restore, then we have to do it
12068 via moves, since there's obviously no pop for SSE regs. */
12074 {
12075 rtx t;
12080 /* eh_return epilogues need %ecx added to the stack pointer. */
12082 {
12085 /* Stack align doesn't work with eh_return. */
12087 /* Neither does regparm nested functions. */
12091 {
12099 /* Note that we use SA as a temporary CFA, as the return
12100 address is at the proper place relative to it. We
12101 pretend this happens at the FP restore insn because
12102 prior to this insn the FP would be stored at the wrong
12103 offset relative to SA, and after this insn we have no
12104 other reasonable register to use for the CFA. We don't
12105 bother resetting the CFA to the SP for the duration of
12106 the return insn. */
12119 }
12120 else
12121 {
12129 {
12133 UNITS_PER_WORD));
12135 }
12136 }
12139 }
12140 }
12141 else
12142 {
12143 /* SEH requires that the function end with (1) a stack adjustment
12144 if necessary, (2) a sequence of pops, and (3) a return or
12145 jump instruction. Prevent insns from the function body from
12146 being scheduled into this sequence. */
12148 {
12149 /* Prevent a catch region from being adjacent to the standard
12150 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12151 several other flags that would be interesting to test are
12152 not yet set up. */
12155 else
12157 }
12159 /* First step is to deallocate the stack frame so that we can
12160 pop the registers. Also do it on SEH target for very large
12161 frame as the emitted instructions aren't allowed by the ABI in
12162 epilogues. */
12164 || (TARGET_SEH
12167 {
12172 }
12174 {
12178 style,
12180 }
12183 }
12185 /* If we used a stack pointer and haven't already got rid of it,
12186 then do so now. */
12188 {
12189 /* If the stack pointer is valid and pointing at the frame
12190 pointer store address, then we only need a pop. */
12193 /* Leave results in shorter dependency chains on CPUs that are
12194 able to grok it fast. */
12199 else
12200 {
12202 hard_frame_pointer_rtx,
12205 }
12206 }
12209 {
12211 rtx insn;
12237 }
12239 /* At this point the stack pointer must be valid, and we must have
12240 restored all of the registers. We may not have deallocated the
12241 entire stack frame. We've delayed this until now because it may
12242 be possible to merge the local stack deallocation with the
12243 deallocation forced by ix86_static_chain_on_stack. */
12248 {
12252 }
12253 else
12256 /* Sibcall epilogues don't want a return instruction. */
12258 {
12261 }
12264 {
12267 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12268 address, do explicit add, and jump indirectly to the caller. */
12271 {
12273 rtx insn;
12275 /* There is no "pascal" calling convention in any 64bit ABI. */
12292 }
12293 else
12295 }
12296 else
12299 /* Restore the state back to the state from the prologue,
12300 so that it's correct for the next epilogue. */
12302 }
12304 /* Reset from the function's potential modifications. */
12306 static void
12308 {
12312 #if TARGET_MACHO
12313 /* Mach-O doesn't support labels at the end of objects, so if
12314 it looks like we might want one, insert a NOP. */
12315 {
12321 {
12322 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12323 notes only, instead set their CODE_LABEL_NUMBER to -1,
12324 otherwise there would be code generation differences
12325 in between -g and -g0. */
12329 }
12339 }
12340 #endif
12342 }
12344 /* Return a scratch register to use in the split stack prologue. The
12345 split stack prologue is used for -fsplit-stack. It is the first
12346 instructions in the function, even before the regular prologue.
12347 The scratch register can be any caller-saved register which is not
12348 used for parameters or for the static chain. */
12350 static unsigned int
12352 {
12355 else
12356 {
12369 {
12371 {
12375 }
12377 }
12379 {
12383 }
12385 {
12388 else
12389 {
12391 {
12395 }
12397 }
12398 }
12399 else
12400 {
12401 /* FIXME: We could make this work by pushing a register
12402 around the addition and comparison. */
12405 }
12406 }
12407 }
12409 /* A SYMBOL_REF for the function which allocates new stackspace for
12410 -fsplit-stack. */
12414 /* A SYMBOL_REF for the more stack function when using the large
12415 model. */
12419 /* Handle -fsplit-stack. These are the first instructions in the
12420 function, even before the regular prologue. */
12422 void
12424 {
12426 HOST_WIDE_INT allocate;
12432 rtx fn;
12440 /* This is the label we will branch to if we have enough stack
12441 space. We expect the basic block reordering pass to reverse this
12442 branch if optimizing, so that we branch in the unlikely case. */
12445 /* We need to compare the stack pointer minus the frame size with
12446 the stack boundary in the TCB. The stack boundary always gives
12447 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12448 can compare directly. Otherwise we need to do an addition. */
12451 UNSPEC_STACK_CHECK);
12456 else
12457 {
12459 rtx offset;
12461 /* We need a scratch register to hold the stack pointer minus
12462 the required frame size. Since this is the very start of the
12463 function, the scratch register can be any caller-saved
12464 register which is not used for parameters. */
12471 {
12472 /* We don't use ix86_gen_add3 in this case because it will
12473 want to split to lea, but when not optimizing the insn
12474 will not be split after this point. */
12477 offset)));
12478 }
12479 else
12480 {
12483 stack_pointer_rtx));
12484 }
12486 }
12492 /* Mark the jump as very likely to be taken. */
12497 {
12500 }
12503 /* Get more stack space. We pass in the desired stack space and the
12504 size of the arguments to copy to the new stack. In 32-bit mode
12505 we push the parameters; __morestack will return on a new stack
12506 anyhow. In 64-bit mode we pass the parameters in r10 and
12507 r11. */
12512 {
12518 /* If this function uses a static chain, it will be in %r10.
12519 Preserve it across the call to __morestack. */
12521 {
12522 rtx rax;
12527 }
12531 {
12532 HOST_WIDE_INT argval;
12535 /* When using the large model we need to load the address
12536 into a register, and we've run out of registers. So we
12537 switch to a different calling convention, and we call a
12538 different function: __morestack_large. We pass the
12539 argument size in the upper 32 bits of r10 and pass the
12540 frame size in the lower 32 bits. */
12545 {
12546 split_stack_fn_large =
12549 }
12551 {
12553 rtx x;
12562 UNSPEC_GOT);
12568 }
12569 else
12576 }
12577 else
12578 {
12582 }
12585 }
12586 else
12587 {
12590 }
12596 /* In order to make call/return prediction work right, we now need
12597 to execute a return instruction. See
12598 libgcc/config/i386/morestack.S for the details on how this works.
12600 For flow purposes gcc must not see this as a return
12601 instruction--we need control flow to continue at the subsequent
12602 label. Therefore, we use an unspec. */
12606 /* If we are in 64-bit mode and this function uses a static chain,
12607 we saved %r10 in %rax before calling _morestack. */
12612 /* If this function calls va_start, we need to store a pointer to
12613 the arguments on the old stack, because they may not have been
12614 all copied to the new stack. At this point the old stack can be
12615 found at the frame pointer value used by __morestack, because
12616 __morestack has set that up before calling back to us. Here we
12617 store that pointer in a scratch register, and in
12618 ix86_expand_prologue we store the scratch register in a stack
12619 slot. */
12621 {
12623 rtx frame_reg;
12630 /* 64-bit:
12631 fp -> old fp value
12632 return address within this function
12633 return address of caller of this function
12634 stack arguments
12635 So we add three words to get to the stack arguments.
12637 32-bit:
12638 fp -> old fp value
12639 return address within this function
12640 first argument to __morestack
12641 second argument to __morestack
12642 return address of caller of this function
12643 stack arguments
12644 So we add five words to get to the stack arguments.
12645 */
12656 }
12661 /* If this function calls va_start, we now have to set the scratch
12662 register for the case where we do not call __morestack. In this
12663 case we need to set it based on the stack pointer. */
12665 {
12672 }
12673 }
12675 /* We may have to tell the dataflow pass that the split stack prologue
12676 is initializing a scratch register. */
12678 static void
12680 {
12682 {
12685 }
12686 }
12687 \f
12688 /* Extract the parts of an RTL expression that is a valid memory address
12689 for an instruction. Return 0 if the structure of the address is
12690 grossly off. Return -1 if the address contains ASHIFT, so it is not
12691 strictly valid, but still used for computing length of lea instruction. */
12693 int
12695 {
12700 rtx tmp;
12704 /* Allow zero-extended SImode addresses,
12705 they will be emitted with addr32 prefix. */
12707 {
12710 {
12714 }
12717 {
12724 }
12725 }
12727 /* Allow SImode subregs of DImode addresses,
12728 they will be emitted with addr32 prefix. */
12730 {
12733 {
12737 }
12738 }
12743 {
12746 else
12748 }
12750 {
12755 do
12756 {
12761 }
12768 {
12771 {
12796 /* FALLTHRU */
12800 && TARGET_TLS_DIRECT_SEG_REFS
12803 else
12810 /* FALLTHRU */
12817 else
12832 }
12833 }
12834 }
12836 {
12839 }
12841 {
12842 /* We're called for lea too, which implements ashift on occasion. */
12852 }
12853 else
12857 {
12859 ;
12862 ;
12863 else
12865 }
12867 /* Extract the integral value of scale. */
12869 {
12873 }
12878 /* Avoid useless 0 displacement. */
12882 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12887 {
12890 }
12892 /* Special case: %ebp cannot be encoded as a base without a displacement.
12893 Similarly %r13. */
12895 && base_reg
12904 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12905 Avoid this by transforming to [%esi+0].
12906 Reload calls address legitimization without cfun defined, so we need
12907 to test cfun for being non-NULL. */
12913 /* Special case: encode reg+reg instead of reg*2. */
12917 /* Special case: scaling cannot be encoded without base or displacement. */
12928 }
12929 \f
12930 /* Return cost of the memory address x.
12931 For i386, it is better to use a complex address than let gcc copy
12932 the address into a reg and make a new pseudo. But not if the address
12933 requires to two regs - that would mean more pseudos with longer
12934 lifetimes. */
12935 static int
12937 {
12949 /* Attempt to minimize number of registers in the address by increasing
12950 address cost for each used register. We don't increase address cost
12951 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
12952 is not invariant itself it most likely means that base or index is not
12953 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
12954 which is not profitable for x86. */
12958 || !pic_offset_table_rtx
12961 cost++;
12966 || !pic_offset_table_rtx
12969 cost++;
12971 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12972 since it's predecode logic can't detect the length of instructions
12973 and it degenerates to vector decoded. Increase cost of such
12974 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12975 to split such addresses or even refuse such addresses at all.
12977 Following addressing modes are affected:
12978 [base+scale*index]
12979 [scale*index+disp]
12980 [base+index]
12982 The first and last case may be avoidable by explicitly coding the zero in
12983 memory address, but I don't have AMD-K6 machine handy to check this
12984 theory. */
12993 }
12994 \f
12995 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12996 this is used for to form addresses to local data when -fPIC is in
12997 use. */
12999 static bool
13001 {
13004 }
13006 /* Determine if a given RTX is a valid constant. We already know this
13007 satisfies CONSTANT_P. */
13009 static bool
13011 {
13012 /* Pointer bounds constants are not valid. */
13017 {
13022 {
13026 }
13031 /* Only some unspecs are valid as "constants". */
13034 {
13050 }
13052 /* We must have drilled down to a symbol. */
13057 /* FALLTHRU */
13060 /* TLS symbols are never valid. */
13064 /* DLLIMPORT symbols are never valid. */
13069 #if TARGET_MACHO
13070 /* mdynamic-no-pic */
13073 #endif
13089 }
13091 /* Otherwise we handle everything else in the move patterns. */
13093 }
13095 /* Determine if it's legal to put X into the constant pool. This
13096 is not possible for the address of thread-local symbols, which
13097 is checked above. */
13099 static bool
13101 {
13102 /* We can always put integral constants and vectors in memory. */
13104 {
13112 }
13114 }
13116 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13117 otherwise zero. */
13119 static bool
13121 {
13127 }
13130 /* Nonzero if the constant value X is a legitimate general operand
13131 when generating PIC code. It is given that flag_pic is on and
13132 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
13134 bool
13136 {
13137 rtx inner;
13140 {
13147 /* Only some unspecs are valid as "constants". */
13150 {
13163 }
13164 /* FALLTHRU */
13172 }
13173 }
13175 /* Determine if a given CONST RTX is a valid memory displacement
13176 in PIC mode. */
13178 bool
13180 {
13183 /* In 64bit mode we can allow direct addresses of symbols and labels
13184 when they are not dynamic symbols. */
13186 {
13190 {
13214 /* FALLTHRU */
13217 /* TLS references should always be enclosed in UNSPEC.
13218 The dllimported symbol needs always to be resolved. */
13224 {
13232 /* Function-symbols need to be resolved only for
13233 large-model.
13234 For the small-model we don't need to resolve anything
13235 here. */
13240 /* Non-external symbols don't need to be resolved for
13241 large, and medium-model. */
13246 }
13249 || (HAVE_LD_PIE_COPYRELOC
13250 && flag_pie
13259 }
13260 }
13266 {
13267 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13268 of GOT tables. We should not need these anyway. */
13280 }
13284 {
13289 }
13298 {
13302 /* We need to check for both symbols and labels because VxWorks loads
13303 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13304 details. */
13308 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13309 While ABI specify also 32bit relocation but we don't produce it in
13310 small PIC model at all. */
13332 }
13335 }
13337 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
13338 replace the input X, or the original X if no replacement is called for.
13339 The output parameter *WIN is 1 if the calling macro should goto WIN,
13340 0 if it should not. */
13342 bool
13345 {
13346 /* Reload can generate:
13348 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
13349 (reg:DI 97))
13350 (reg:DI 2 cx))
13352 This RTX is rejected from ix86_legitimate_address_p due to
13353 non-strictness of base register 97. Following this rejection,
13354 reload pushes all three components into separate registers,
13355 creating invalid memory address RTX.
13357 Following code reloads only the invalid part of the
13358 memory address RTX. */
13364 {
13370 {
13375 }
13379 {
13384 }
13388 }
13391 }
13393 /* Determine if op is suitable RTX for an address register.
13394 Return naked register if a register or a register subreg is
13395 found, otherwise return NULL_RTX. */
13397 static rtx
13399 {
13402 /* Only SImode or DImode registers can form the address. */
13409 {
13417 /* Don't allow SUBREGs that span more than a word. It can
13418 lead to spill failures when the register is one word out
13419 of a two word structure. */
13423 /* Allow only SUBREGs of non-eliminable hard registers. */
13426 }
13428 /* Op is not a register. */
13430 }
13432 /* Recognizes RTL expressions that are valid memory addresses for an
13433 instruction. The MODE argument is the machine mode for the MEM
13434 expression that wants to use this address.
13436 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13437 convert common non-canonical forms to canonical form so that they will
13438 be recognized. */
13440 static bool
13442 {
13445 HOST_WIDE_INT scale;
13449 /* Decomposition failed. */
13458 /* Validate base register. */
13460 {
13468 /* Base is not valid. */
13470 }
13472 /* Validate index register. */
13474 {
13482 /* Index is not valid. */
13484 }
13486 /* Index and base should have the same mode. */
13491 /* Address override works only on the (%reg) part of %fs:(%reg). */
13497 /* Validate scale factor. */
13499 {
13501 /* Scale without index. */
13505 /* Scale is not a valid multiplier. */
13507 }
13509 /* Validate displacement. */
13511 {
13516 {
13517 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13518 used. While ABI specify also 32bit relocations, we don't produce
13519 them at all and use IP relative instead. */
13526 /* 64bit address unspec. */
13546 /* Invalid address unspec. */
13548 }
13551 && (flag_pic
13552 || (TARGET_MACHO
13553 #if TARGET_MACHO
13554 && MACHOPIC_INDIRECT
13556 #endif
13557 )))
13558 {
13560 is_legitimate_pic:
13562 {
13563 /* foo@dtpoff(%rX) is ok. */
13570 /* Non-constant pic memory reference. */
13572 }
13575 /* Displacement is an invalid pic construct. */
13577 #if TARGET_MACHO
13580 /* displacment must be referenced via non_lazy_pointer */
13582 #endif
13584 /* This code used to verify that a symbolic pic displacement
13585 includes the pic_offset_table_rtx register.
13587 While this is good idea, unfortunately these constructs may
13588 be created by "adds using lea" optimization for incorrect
13589 code like:
13591 int a;
13592 int foo(int i)
13593 {
13594 return *(&a+i);
13595 }
13597 This code is nonsensical, but results in addressing
13598 GOT table with pic_offset_table_rtx base. We can't
13599 just refuse it easily, since it gets matched by
13600 "addsi3" pattern, that later gets split to lea in the
13601 case output register differs from input. While this
13602 can be handled by separate addsi pattern for this case
13603 that never results in lea, this seems to be easier and
13604 correct fix for crash to disable this test. */
13605 }
13612 /* Displacement is not constant. */
13616 /* Displacement is out of range. */
13618 /* In x32 mode, constant addresses are sign extended to 64bit, so
13619 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13624 }
13626 /* Everything looks valid. */
13628 }
13630 /* Determine if a given RTX is a valid constant address. */
13632 bool
13634 {
13636 }
13637 \f
13638 /* Return a unique alias set for the GOT. */
13640 static alias_set_type
13642 {
13647 }
13649 /* Set regs_ever_live for PIC base address register
13650 to true if required. */
13651 static void
13653 {
13656 }
13658 /* Return a legitimate reference for ORIG (an address) using the
13659 register REG. If REG is 0, a new pseudo is generated.
13661 There are two types of references that must be handled:
13663 1. Global data references must load the address from the GOT, via
13664 the PIC reg. An insn is emitted to do this load, and the reg is
13665 returned.
13667 2. Static data references, constant pool addresses, and code labels
13668 compute the address as an offset from the GOT, whose base is in
13669 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13670 differentiate them from global data objects. The returned
13671 address is the PIC reg + an unspec constant.
13673 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13674 reg also appears in the address. */
13676 static rtx
13678 {
13682 #if TARGET_MACHO
13684 {
13687 /* Use the generic Mach-O PIC machinery. */
13689 }
13690 #endif
13693 {
13697 }
13703 {
13704 rtx tmpreg;
13705 /* This symbol may be referenced via a displacement from the PIC
13706 base address (@GOTOFF). */
13712 {
13714 UNSPEC_GOTOFF);
13716 }
13717 else
13722 else
13727 {
13731 }
13732 else
13734 }
13736 {
13737 /* This symbol may be referenced via a displacement from the PIC
13738 base address (@GOTOFF). */
13744 {
13746 UNSPEC_GOTOFF);
13748 }
13749 else
13755 {
13758 }
13759 }
13761 /* We can't use @GOTOFF for text labels on VxWorks;
13762 see gotoff_operand. */
13764 {
13769 /* For x64 PE-COFF there is no GOT table. So we use address
13770 directly. */
13772 {
13780 }
13782 {
13790 /* Use directly gen_movsi, otherwise the address is loaded
13791 into register for CSE. We don't want to CSE this addresses,
13792 instead we CSE addresses from the GOT table, so skip this. */
13795 }
13796 else
13797 {
13798 /* This symbol must be referenced via a load from the
13799 Global Offset Table (@GOT). */
13814 }
13815 }
13816 else
13817 {
13820 {
13822 {
13825 }
13826 else
13828 }
13830 {
13833 /* We must match stuff we generate before. Assume the only
13834 unspecs that can get here are ours. Not that we could do
13835 anything with them anyway.... */
13841 }
13843 {
13846 /* Check first to see if this is a constant offset from a @GOTOFF
13847 symbol reference. */
13850 {
13852 {
13855 UNSPEC_GOTOFF);
13861 {
13864 }
13865 }
13866 else
13867 {
13870 {
13874 }
13875 }
13876 }
13877 else
13878 {
13881 new_rtx
13885 {
13888 {
13891 new_rtx
13893 }
13894 else
13896 }
13897 else
13898 {
13901 {
13904 }
13906 }
13907 }
13908 }
13909 }
13911 }
13912 \f
13913 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13915 static rtx
13917 {
13921 {
13926 }
13932 }
13934 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13938 static rtx
13940 {
13942 {
13948 }
13951 {
13953 UNSPEC_PLTOFF);
13956 }
13959 }
13961 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13965 rtx
13967 {
13969 {
13970 ix86_tls_module_base_symbol
13975 }
13978 }
13980 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13981 false if we expect this to be used for a memory address and true if
13982 we expect to load the address into a register. */
13984 static rtx
13986 {
13992 /* Fall back to global dynamic model if tool chain cannot support local
13993 dynamic. */
14000 {
14005 {
14008 else
14009 {
14012 }
14013 }
14016 {
14019 else
14029 }
14030 else
14031 {
14035 {
14040 emit_call_insn
14050 }
14051 else
14053 }
14060 {
14063 else
14064 {
14067 }
14068 }
14071 {
14076 else
14082 }
14083 else
14084 {
14088 {
14091 rtx eqv;
14094 emit_call_insn
14099 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14100 share the LD_BASE result with other LD model accesses. */
14102 UNSPEC_TLS_LD_BASE);
14106 }
14107 else
14109 }
14117 {
14124 }
14129 {
14131 {
14132 /* The Sun linker took the AMD64 TLS spec literally
14133 and can only handle %rax as destination of the
14134 initial executable code sequence. */
14139 }
14141 /* Generate DImode references to avoid %fs:(%reg32)
14142 problems and linker IE->LE relaxation bug. */
14146 }
14148 {
14152 }
14154 {
14158 }
14159 else
14160 {
14163 }
14173 {
14178 }
14179 else
14180 {
14184 }
14194 {
14198 }
14199 else
14200 {
14204 }
14209 }
14212 }
14214 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14215 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14216 unique refptr-DECL symbol corresponding to symbol DECL. */
14219 {
14223 {
14225 }
14227 static void
14229 {
14235 else
14237 }
14238 };
14242 static tree
14244 {
14250 tree to;
14251 rtx rtl;
14278 else
14291 {
14293 #ifdef SUB_TARGET_RECORD_STUB
14295 #endif
14296 }
14305 }
14307 /* Expand SYMBOL into its corresponding far-addresse symbol.
14308 WANT_REG is true if we require the result be a register. */
14310 static rtx
14312 {
14313 tree imp_decl;
14314 rtx x;
14323 }
14325 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14326 true if we require the result be a register. */
14328 static rtx
14330 {
14331 tree imp_decl;
14332 rtx x;
14341 }
14343 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14344 is true if we require the result be a register. */
14346 static rtx
14348 {
14353 {
14360 {
14363 }
14364 }
14380 {
14383 }
14385 }
14387 /* Try machine-dependent ways of modifying an illegitimate address
14388 to be legitimate. If we find one, return the new, valid address.
14389 This macro is used in only one place: `memory_address' in explow.c.
14391 OLDX is the address as it was before break_out_memory_refs was called.
14392 In some cases it is useful to look at this to decide what needs to be done.
14394 It is always safe for this macro to do nothing. It exists to recognize
14395 opportunities to optimize the output.
14397 For the 80386, we handle X+REG by loading X into a register R and
14398 using R+REG. R will go in a general reg and indexing will be used.
14399 However, if REG is a broken-out memory address or multiplication,
14400 nothing needs to be done because REG can certainly go in a general reg.
14402 When -fpic is used, special handling is needed for symbolic references.
14403 See comments by legitimize_pic_address in i386.c for details. */
14405 static rtx
14407 {
14418 {
14422 }
14425 {
14429 }
14434 #if TARGET_MACHO
14437 #endif
14439 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14443 {
14448 }
14451 {
14452 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14457 {
14463 }
14468 {
14474 }
14476 /* Put multiply first if it isn't already. */
14478 {
14481 }
14483 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14484 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14485 created by virtual register instantiation, register elimination, and
14486 similar optimizations. */
14488 {
14494 }
14496 /* Canonicalize
14497 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14498 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14503 {
14504 rtx constant;
14508 {
14511 }
14513 {
14516 }
14517 else
14521 {
14528 }
14529 }
14535 {
14538 }
14541 {
14544 }
14552 {
14555 }
14561 {
14565 {
14568 }
14572 }
14575 {
14579 {
14582 }
14586 }
14587 }
14590 }
14591 \f
14592 /* Print an integer constant expression in assembler syntax. Addition
14593 and subtraction are the only arithmetic that may appear in these
14594 expressions. FILE is the stdio stream to write to, X is the rtx, and
14595 CODE is the operand print code from the output string. */
14597 static void
14599 {
14603 {
14612 else
14613 {
14616 /* Mark the decl as referenced so that cgraph will
14617 output the function. */
14621 #if TARGET_MACHO
14625 #endif
14627 }
14635 /* FALLTHRU */
14646 /* This used to output parentheses around the expression,
14647 but that does not work on the 386 (either ATT or BSD assembler). */
14653 {
14654 /* We can use %d if the number is <32 bits and positive. */
14659 else
14661 }
14662 else
14663 /* We can't handle floating point constants;
14664 TARGET_PRINT_OPERAND must handle them. */
14669 /* Some assemblers need integer constants to appear first. */
14671 {
14675 }
14676 else
14677 {
14682 }
14697 {
14701 }
14706 {
14725 /* FIXME: This might be @TPOFF in Sun ld too. */
14734 else
14744 else
14750 #if TARGET_MACHO
14755 #endif
14759 }
14764 }
14765 }
14767 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14768 We need to emit DTP-relative relocations. */
14770 static void ATTRIBUTE_UNUSED
14772 {
14777 {
14785 }
14786 }
14788 /* Return true if X is a representation of the PIC register. This copes
14789 with calls from ix86_find_base_term, where the register might have
14790 been replaced by a cselib value. */
14792 static bool
14794 {
14801 {
14809 }
14810 else
14812 }
14814 /* Helper function for ix86_delegitimize_address.
14815 Attempt to delegitimize TLS local-exec accesses. */
14817 static rtx
14819 {
14844 {
14849 }
14855 }
14857 /* In the name of slightly smaller debug output, and to cater to
14858 general assembler lossage, recognize PIC+GOTOFF and turn it back
14859 into a direct symbol reference.
14861 On Darwin, this is necessary to avoid a crash, because Darwin
14862 has a different PIC label for each routine but the DWARF debugging
14863 information is not associated with any particular routine, so it's
14864 necessary to remove references to the PIC label from RTL stored by
14865 the DWARF output code. */
14867 static rtx
14869 {
14871 /* addend is NULL or some rtx if x is something+GOTOFF where
14872 something doesn't include the PIC register. */
14874 /* reg_addend is NULL or a multiple of some register. */
14876 /* const_addend is NULL or a const_int. */
14878 /* This is the result, or NULL. */
14887 {
14894 {
14900 }
14907 {
14910 {
14915 }
14917 }
14922 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14923 and -mcmodel=medium -fpic. */
14924 }
14931 /* %ebx + GOT/GOTOFF */
14932 ;
14934 {
14935 /* %ebx + %reg * scale + GOT/GOTOFF */
14941 else
14942 {
14945 }
14946 }
14947 else
14953 {
14956 }
14977 {
14978 /* If the rest of original X doesn't involve the PIC register, add
14979 addend and subtract pic_offset_table_rtx. This can happen e.g.
14980 for code like:
14981 leal (%ebx, %ecx, 4), %ecx
14982 ...
14983 movl foo@GOTOFF(%ecx), %edx
14984 in which case we return (%ecx - %ebx) + foo
14985 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14986 and reload has completed. */
14990 pic_offset_table_rtx),
14991 result);
14993 {
14997 }
14998 else
15000 }
15002 {
15006 }
15008 }
15010 /* If X is a machine specific address (i.e. a symbol or label being
15011 referenced as a displacement from the GOT implemented using an
15012 UNSPEC), then return the base term. Otherwise return X. */
15014 rtx
15016 {
15017 rtx term;
15020 {
15034 }
15037 }
15038 \f
15039 static void
15042 {
15046 {
15049 }
15054 {
15057 {
15076 }
15080 {
15099 }
15106 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15107 Those same assemblers have the same but opposite lossage on cmov. */
15110 else
15115 {
15128 }
15135 else
15140 {
15153 }
15160 else
15170 else
15181 }
15183 }
15185 /* Print the name of register X to FILE based on its machine mode and number.
15186 If CODE is 'w', pretend the mode is HImode.
15187 If CODE is 'b', pretend the mode is QImode.
15188 If CODE is 'k', pretend the mode is SImode.
15189 If CODE is 'q', pretend the mode is DImode.
15190 If CODE is 'x', pretend the mode is V4SFmode.
15191 If CODE is 't', pretend the mode is V8SFmode.
15192 If CODE is 'g', pretend the mode is V16SFmode.
15193 If CODE is 'h', pretend the reg is the 'high' byte register.
15194 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15195 If CODE is 'd', duplicate the operand for AVX instruction.
15196 */
15198 void
15200 {
15209 {
15213 }
15240 else
15243 /* Irritatingly, AMD extended registers use different naming convention
15244 from the normal registers: "r%d[bwd]" */
15246 {
15251 {
15265 /* no suffix */
15270 }
15272 }
15276 {
15279 {
15282 }
15283 /* FALLTHRU */
15289 /* FALLTHRU */
15292 normal:
15307 {
15312 }
15315 {
15320 }
15324 }
15328 {
15331 else
15333 }
15334 }
15336 /* Meaning of CODE:
15337 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15338 C -- print opcode suffix for set/cmov insn.
15339 c -- like C, but print reversed condition
15340 F,f -- likewise, but for floating-point.
15341 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15342 otherwise nothing
15343 R -- print embeded rounding and sae.
15344 r -- print only sae.
15345 z -- print the opcode suffix for the size of the current operand.
15346 Z -- likewise, with special suffixes for x87 instructions.
15347 * -- print a star (in certain assembler syntax)
15348 A -- print an absolute memory reference.
15349 E -- print address with DImode register names if TARGET_64BIT.
15350 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15351 s -- print a shift double count, followed by the assemblers argument
15352 delimiter.
15353 b -- print the QImode name of the register for the indicated operand.
15354 %b0 would print %al if operands[0] is reg 0.
15355 w -- likewise, print the HImode name of the register.
15356 k -- likewise, print the SImode name of the register.
15357 q -- likewise, print the DImode name of the register.
15358 x -- likewise, print the V4SFmode name of the register.
15359 t -- likewise, print the V8SFmode name of the register.
15360 g -- likewise, print the V16SFmode name of the register.
15361 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15362 y -- print "st(0)" instead of "st" as a register.
15363 d -- print duplicated register operand for AVX instruction.
15364 D -- print condition for SSE cmp instruction.
15365 P -- if PIC, print an @PLT suffix.
15366 p -- print raw symbol name.
15367 X -- don't print any sort of PIC '@' suffix for a symbol.
15368 & -- print some in-use local-dynamic symbol name.
15369 H -- print a memory address offset by 8; used for sse high-parts
15370 Y -- print condition for XOP pcom* instruction.
15371 + -- print a branch hint as 'cs' or 'ds' prefix
15372 ; -- print a semicolon (after prefixes due to bug in older gas).
15373 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15374 @ -- print a segment register of thread base pointer load
15375 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15376 ! -- print MPX prefix for jxx/call/ret instructions if required.
15377 */
15379 void
15381 {
15383 {
15385 {
15388 {
15394 /* Intel syntax. For absolute addresses, registers should not
15395 be surrounded by braces. */
15397 {
15402 }
15407 }
15413 /* Wrap address in an UNSPEC to declare special handling. */
15451 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15456 {
15470 output_operand_lossage
15473 }
15476 #endif
15481 {
15482 /* Opcodes don't get size suffixes if using Intel opcodes. */
15487 {
15505 output_operand_lossage
15508 }
15509 }
15512 warning
15514 /* FALLTHRU */
15517 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15522 {
15524 {
15526 #ifdef HAVE_AS_IX86_FILDS
15528 #endif
15536 #ifdef HAVE_AS_IX86_FILDQ
15538 #else
15540 #endif
15545 }
15546 }
15548 {
15549 /* 387 opcodes don't get size suffixes
15550 if the operands are registers. */
15555 {
15571 }
15572 }
15573 else
15574 {
15575 output_operand_lossage
15578 }
15580 output_operand_lossage
15601 {
15604 }
15609 {
15660 }
15664 /* Little bit of braindamage here. The SSE compare instructions
15665 does use completely different names for the comparisons that the
15666 fp conditional moves. */
15668 {
15671 {
15674 }
15680 {
15683 }
15689 {
15692 }
15701 {
15704 }
15710 {
15713 }
15719 {
15722 }
15733 }
15738 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15741 #endif
15746 {
15750 }
15754 file);
15759 {
15763 }
15764 /* It doesn't actually matter what mode we use here, as we're
15765 only going to use this for printing. */
15767 /* Output 'qword ptr' for intel assembler dialect. */
15776 #ifdef HAVE_AS_IX86_HLE
15778 #else
15780 #endif
15782 #ifdef HAVE_AS_IX86_HLE
15784 #else
15786 #endif
15787 /* We do not want to print value of the operand. */
15816 {
15831 }
15844 {
15849 else
15852 }
15855 {
15856 rtx x;
15865 {
15870 {
15872 bool cputaken
15875 /* Emit hints only in the case default branch prediction
15876 heuristics would fail. */
15878 {
15879 /* We use 3e (DS) prefix for taken branches and
15880 2e (CS) prefix for not taken branches. */
15883 else
15885 }
15886 }
15887 }
15889 }
15892 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15894 #endif
15901 /* The kernel uses a different segment register for performance
15902 reasons; a system call would not have to trash the userspace
15903 segment register, which would be expensive. */
15906 else
15926 }
15927 }
15933 {
15934 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15937 {
15940 {
15949 else
15956 }
15958 /* Check for explicit size override (codes 'b', 'w', 'k',
15959 'q' and 'x') */
15973 }
15976 /* Avoid (%rip) for call operands. */
15982 else
15984 }
15987 {
15988 REAL_VALUE_TYPE r;
15996 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16000 else
16002 }
16005 {
16006 REAL_VALUE_TYPE r;
16015 }
16017 /* These float cases don't actually occur as immediate operands. */
16019 {
16024 }
16026 else
16027 {
16028 /* We have patterns that allow zero sets of memory, for instance.
16029 In 64-bit mode, we should probably support all 8-byte vectors,
16030 since we can in fact encode that into an immediate. */
16032 {
16035 }
16038 {
16040 {
16043 }
16046 {
16049 else
16051 }
16052 }
16057 else
16059 }
16060 }
16062 static bool
16064 {
16067 }
16068 \f
16069 /* Print a memory operand whose address is ADDR. */
16071 static void
16073 {
16082 {
16089 }
16091 {
16095 }
16097 {
16101 {
16104 }
16107 }
16109 {
16114 }
16115 else
16126 {
16137 }
16139 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16141 {
16153 }
16155 {
16156 /* Displacement only requires special attention. */
16159 {
16163 }
16166 else
16168 }
16169 else
16170 {
16171 /* Print SImode register names to force addr32 prefix. */
16173 {
16174 #ifdef ENABLE_CHECKING
16177 {
16188 }
16189 #endif
16192 }
16194 && TARGET_X32
16195 && disp
16198 {
16199 /* X32 runs in 64-bit mode, where displacement, DISP, in
16200 address DISP(%r64), is encoded as 32-bit immediate sign-
16201 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16202 address is %r64 + 0xffffffffbffffd00. When %r64 <
16203 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16204 which is invalid for x32. The correct address is %r64
16205 - 0x40000300 == 0xf7ffdd64. To properly encode
16206 -0x40000300(%r64) for x32, we zero-extend negative
16207 displacement by forcing addr32 prefix which truncates
16208 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16209 zero-extend all negative displacements, including -1(%rsp).
16210 However, for small negative displacements, sign-extension
16211 won't cause overflow. We only zero-extend negative
16212 displacements if they < -16*1024*1024, which is also used
16213 to check legitimate address displacements for PIC. */
16215 }
16218 {
16220 {
16225 else
16227 }
16233 {
16238 }
16240 }
16241 else
16242 {
16246 {
16247 /* Pull out the offset of a symbol; print any symbol itself. */
16251 {
16255 }
16263 else
16265 }
16269 {
16272 {
16276 }
16277 }
16280 else
16284 {
16289 }
16291 }
16292 }
16293 }
16295 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16297 static bool
16299 {
16300 rtx op;
16307 {
16310 /* FIXME: This might be @TPOFF in Sun ld. */
16321 else
16333 else
16340 #if TARGET_MACHO
16346 #endif
16349 {
16354 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16356 #else
16358 #endif
16361 }
16366 }
16369 }
16370 \f
16371 /* Split one or more double-mode RTL references into pairs of half-mode
16372 references. The RTL can be REG, offsettable MEM, integer constant, or
16373 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16374 split and "num" is its length. lo_half and hi_half are output arrays
16375 that parallel "operands". */
16377 void
16380 {
16381 machine_mode half_mode;
16385 {
16394 }
16399 {
16402 /* simplify_subreg refuse to split volatile memory addresses,
16403 but we still have to handle it. */
16405 {
16408 }
16409 else
16410 {
16417 }
16418 }
16419 }
16420 \f
16421 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16422 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16423 is the expression of the binary operation. The output may either be
16424 emitted here, or returned to the caller, like all output_* functions.
16426 There is no guarantee that the operands are the same mode, as they
16427 might be within FLOAT or FLOAT_EXTEND expressions. */
16429 #ifndef SYSV386_COMPAT
16430 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16431 wants to fix the assemblers because that causes incompatibility
16432 with gcc. No-one wants to fix gcc because that causes
16433 incompatibility with assemblers... You can use the option of
16434 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16435 #define SYSV386_COMPAT 1
16436 #endif
16440 {
16446 #ifdef ENABLE_CHECKING
16447 /* Even if we do not want to check the inputs, this documents input
16448 constraints. Which helps in understanding the following code. */
16458 else
16460 #endif
16463 {
16468 else
16477 else
16486 else
16495 else
16502 }
16505 {
16507 {
16511 else
16513 }
16514 else
16515 {
16519 else
16521 }
16523 }
16527 {
16533 /* know operands[0] == operands[1]. */
16536 {
16539 }
16542 {
16544 /* How is it that we are storing to a dead operand[2]?
16545 Well, presumably operands[1] is dead too. We can't
16546 store the result to st(0) as st(0) gets popped on this
16547 instruction. Instead store to operands[2] (which I
16548 think has to be st(1)). st(1) will be popped later.
16549 gcc <= 2.8.1 didn't have this check and generated
16550 assembly code that the Unixware assembler rejected. */
16552 else
16555 }
16559 else
16566 {
16569 }
16572 {
16575 }
16578 {
16579 #if SYSV386_COMPAT
16580 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16581 derived assemblers, confusingly reverse the direction of
16582 the operation for fsub{r} and fdiv{r} when the
16583 destination register is not st(0). The Intel assembler
16584 doesn't have this brain damage. Read !SYSV386_COMPAT to
16585 figure out what the hardware really does. */
16588 else
16590 #else
16592 /* As above for fmul/fadd, we can't store to st(0). */
16594 else
16596 #endif
16598 }
16601 {
16602 #if SYSV386_COMPAT
16605 else
16607 #else
16610 else
16612 #endif
16614 }
16617 {
16620 else
16623 }
16625 {
16626 #if SYSV386_COMPAT
16628 #else
16630 #endif
16631 }
16632 else
16633 {
16634 #if SYSV386_COMPAT
16636 #else
16638 #endif
16639 }
16644 }
16648 }
16650 /* Check if a 256bit AVX register is referenced inside of EXP. */
16652 static bool
16654 {
16660 }
16662 /* Return needed mode for entity in optimize_mode_switching pass. */
16664 static int
16666 {
16668 {
16669 rtx link;
16671 /* Needed mode is set to AVX_U128_CLEAN if there are
16672 no 256bit modes used in function arguments. */
16674 link;
16676 {
16678 {
16683 }
16684 }
16687 }
16689 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16690 changes state only when a 256bit register is written to, but we need
16691 to prevent the compiler from moving optimal insertion point above
16692 eventual read from 256bit register. */
16699 }
16701 /* Return mode that i387 must be switched into
16702 prior to the execution of insn. */
16704 static int
16706 {
16709 /* The mode UNINITIALIZED is used to store control word after a
16710 function call or ASM pattern. The mode ANY specify that function
16711 has no requirements on the control word and make no changes in the
16712 bits we are interested in. */
16726 {
16749 }
16752 }
16754 /* Return mode that entity must be switched into
16755 prior to the execution of insn. */
16757 static int
16759 {
16761 {
16771 }
16773 }
16775 /* Check if a 256bit AVX register is referenced in stores. */
16777 static void
16779 {
16781 {
16784 }
16785 }
16787 /* Calculate mode of upper 128bit AVX registers after the insn. */
16789 static int
16791 {
16798 /* We know that state is clean after CALL insn if there are no
16799 256bit registers used in the function return register. */
16801 {
16806 }
16808 /* Otherwise, return current mode. Remember that if insn
16809 references AVX 256bit registers, the mode was already changed
16810 to DIRTY from MODE_NEEDED. */
16812 }
16814 /* Return the mode that an insn results in. */
16816 static int
16818 {
16820 {
16830 }
16831 }
16833 static int
16835 {
16836 tree arg;
16838 /* Entry mode is set to AVX_U128_DIRTY if there are
16839 256bit modes used in function arguments. */
16842 {
16847 }
16850 }
16852 /* Return a mode that ENTITY is assumed to be
16853 switched to at function entry. */
16855 static int
16857 {
16859 {
16869 }
16870 }
16872 static int
16874 {
16877 /* Exit mode is set to AVX_U128_DIRTY if there are
16878 256bit modes used in the function return register. */
16883 }
16885 /* Return a mode that ENTITY is assumed to be
16886 switched to at function exit. */
16888 static int
16890 {
16892 {
16902 }
16903 }
16905 static int
16907 {
16909 }
16911 /* Output code to initialize control word copies used by trunc?f?i and
16912 rounding patterns. CURRENT_MODE is set to current control word,
16913 while NEW_MODE is set to new control word. */
16915 static void
16917 {
16919 rtx new_mode;
16930 {
16932 {
16934 /* round toward zero (truncate) */
16940 /* round down toward -oo */
16947 /* round up toward +oo */
16954 /* mask precision exception for nearbyint() */
16961 }
16962 }
16963 else
16964 {
16966 {
16968 /* round toward zero (truncate) */
16974 /* round down toward -oo */
16980 /* round up toward +oo */
16986 /* mask precision exception for nearbyint() */
16993 }
16994 }
17000 }
17002 /* Emit vzeroupper. */
17004 void
17006 {
17009 /* Cancel automatic vzeroupper insertion if there are
17010 live call-saved SSE registers at the insertion point. */
17022 }
17024 /* Generate one or more insns to set ENTITY to MODE. */
17026 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17027 is the set of hard registers live at the point where the insn(s)
17028 are to be inserted. */
17030 static void
17032 HARD_REG_SET regs_live)
17033 {
17035 {
17050 }
17051 }
17053 /* Output code for INSN to convert a float to a signed int. OPERANDS
17054 are the insn operands. The output may be [HSD]Imode and the input
17055 operand may be [SDX]Fmode. */
17059 {
17064 /* Jump through a hoop or two for DImode, since the hardware has no
17065 non-popping instruction. We used to do this a different way, but
17066 that was somewhat fragile and broke with post-reload splitters. */
17076 else
17077 {
17082 else
17086 }
17089 }
17091 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17092 have the values zero or one, indicates the ffreep insn's operand
17093 from the OPERANDS array. */
17097 {
17099 #ifdef HAVE_AS_IX86_FFREEP
17101 #else
17102 {
17112 }
17113 #endif
17116 }
17119 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17120 should be used. UNORDERED_P is true when fucom should be used. */
17124 {
17130 {
17133 }
17134 else
17135 {
17138 }
17141 {
17145 else
17147 else
17150 else
17152 }
17159 {
17161 {
17164 }
17165 else
17167 }
17170 && stack_top_dies
17173 {
17174 /* If both the top of the 387 stack dies, and the other operand
17175 is also a stack register that dies, then this must be a
17176 `fcompp' float compare */
17179 {
17180 /* There is no double popping fcomi variant. Fortunately,
17181 eflags is immune from the fstp's cc clobbering. */
17184 else
17187 }
17188 else
17189 {
17192 else
17194 }
17195 }
17196 else
17197 {
17198 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17201 {
17209 NULL,
17210 NULL,
17217 NULL,
17218 NULL,
17219 NULL,
17220 NULL
17221 };
17236 }
17237 }
17239 void
17241 {
17244 #ifdef ASM_QUAD
17247 #else
17249 #endif
17252 }
17254 void
17256 {
17259 #ifdef ASM_QUAD
17262 #else
17264 #endif
17265 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17271 #if TARGET_MACHO
17273 {
17277 }
17278 #endif
17279 else
17282 }
17283 \f
17284 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17285 for the target. */
17287 void
17289 {
17290 rtx tmp;
17292 /* We play register width games, which are only valid after reload. */
17295 /* Avoid HImode and its attendant prefix byte. */
17301 {
17304 }
17307 }
17309 /* X is an unchanging MEM. If it is a constant pool reference, return
17310 the constant pool rtx, else NULL. */
17312 rtx
17314 {
17321 }
17323 void
17325 {
17333 {
17334 rtx tmp;
17338 {
17344 }
17347 }
17351 {
17354 rtx tmp;
17359 else
17363 {
17370 }
17371 }
17375 {
17377 {
17378 #if TARGET_MACHO
17379 /* dynamic-no-pic */
17381 {
17382 rtx temp = ((reload_in_progress
17390 }
17392 {
17396 }
17399 else
17400 {
17408 }
17409 /* dynamic-no-pic */
17410 #endif
17411 }
17412 else
17413 {
17417 {
17423 }
17424 }
17425 }
17426 else
17427 {
17438 /* Force large constants in 64bit compilation into register
17439 to get them CSEed. */
17451 {
17452 /* If we are loading a floating point constant to a register,
17453 force the value to memory now, since we'll get better code
17454 out the back end. */
17458 {
17463 }
17464 }
17465 }
17468 }
17470 void
17472 {
17479 /* Force constants other than zero into memory. We do not know how
17480 the instructions used to build constants modify the upper 64 bits
17481 of the register, once we have that information we may be able
17482 to handle some of them more efficiently. */
17491 /* We need to check memory alignment for SSE mode since attribute
17492 can make operands unaligned. */
17497 {
17500 /* ix86_expand_vector_move_misalign() does not like constants ... */
17506 /* ... nor both arguments in memory. */
17514 }
17516 /* Make operand1 a register if it isn't already. */
17520 {
17523 }
17526 }
17528 /* Split 32-byte AVX unaligned load and store if needed. */
17530 static void
17532 {
17533 rtx m;
17537 machine_mode mode;
17540 {
17561 }
17564 {
17567 {
17574 }
17575 /* Normal *mov<mode>_internal pattern will handle
17576 unaligned loads just fine if misaligned_operand
17577 is true, and without the UNSPEC it can be combined
17578 with arithmetic instructions. */
17581 else
17583 }
17585 {
17588 {
17593 }
17594 else
17596 }
17597 else
17599 }
17601 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17602 straight to ix86_expand_vector_move. */
17603 /* Code generation for scalar reg-reg moves of single and double precision data:
17604 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17605 movaps reg, reg
17606 else
17607 movss reg, reg
17608 if (x86_sse_partial_reg_dependency == true)
17609 movapd reg, reg
17610 else
17611 movsd reg, reg
17613 Code generation for scalar loads of double precision data:
17614 if (x86_sse_split_regs == true)
17615 movlpd mem, reg (gas syntax)
17616 else
17617 movsd mem, reg
17619 Code generation for unaligned packed loads of single precision data
17620 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17621 if (x86_sse_unaligned_move_optimal)
17622 movups mem, reg
17624 if (x86_sse_partial_reg_dependency == true)
17625 {
17626 xorps reg, reg
17627 movlps mem, reg
17628 movhps mem+8, reg
17629 }
17630 else
17631 {
17632 movlps mem, reg
17633 movhps mem+8, reg
17634 }
17636 Code generation for unaligned packed loads of double precision data
17637 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17638 if (x86_sse_unaligned_move_optimal)
17639 movupd mem, reg
17641 if (x86_sse_split_regs == true)
17642 {
17643 movlpd mem, reg
17644 movhpd mem+8, reg
17645 }
17646 else
17647 {
17648 movsd mem, reg
17649 movhpd mem+8, reg
17650 }
17651 */
17653 void
17655 {
17664 {
17666 {
17670 {
17672 {
17675 }
17676 else
17678 }
17680 /* FALLTHRU */
17684 {
17699 }
17705 else
17713 }
17716 }
17720 {
17722 {
17726 {
17728 {
17731 }
17732 else
17734 }
17736 /* FALLTHRU */
17746 }
17749 }
17752 {
17753 /* Normal *mov<mode>_internal pattern will handle
17754 unaligned loads just fine if misaligned_operand
17755 is true, and without the UNSPEC it can be combined
17756 with arithmetic instructions. */
17762 /* ??? If we have typed data, then it would appear that using
17763 movdqu is the only way to get unaligned data loaded with
17764 integer type. */
17766 {
17768 {
17771 }
17773 /* We will eventually emit movups based on insn attributes. */
17777 }
17779 {
17780 rtx zero;
17783 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17784 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17786 {
17787 /* We will eventually emit movups based on insn attributes. */
17790 }
17792 /* When SSE registers are split into halves, we can avoid
17793 writing to the top half twice. */
17795 {
17798 }
17799 else
17800 {
17801 /* ??? Not sure about the best option for the Intel chips.
17802 The following would seem to satisfy; the register is
17803 entirely cleared, breaking the dependency chain. We
17804 then store to the upper half, with a dependency depth
17805 of one. A rumor has it that Intel recommends two movsd
17806 followed by an unpacklpd, but this is unconfirmed. And
17807 given that the dependency depth of the unpacklpd would
17808 still be one, I'm not sure why this would be better. */
17810 }
17816 }
17817 else
17818 {
17819 rtx t;
17822 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17823 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17825 {
17827 {
17830 }
17837 }
17841 else
17846 else
17855 }
17856 }
17858 {
17860 {
17863 /* We will eventually emit movups based on insn attributes. */
17865 }
17867 {
17869 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17870 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17872 /* We will eventually emit movups based on insn attributes. */
17874 else
17875 {
17880 }
17881 }
17882 else
17883 {
17888 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17889 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17891 {
17894 }
17895 else
17896 {
17901 }
17902 }
17903 }
17904 else
17906 }
17908 /* Helper function of ix86_fixup_binary_operands to canonicalize
17909 operand order. Returns true if the operands should be swapped. */
17911 static bool
17913 rtx operands[])
17914 {
17919 /* If the operation is not commutative, we can't do anything. */
17923 /* Highest priority is that src1 should match dst. */
17929 /* Next highest priority is that immediate constants come second. */
17935 /* Lowest priority is that memory references should come second. */
17942 }
17945 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17946 destination to use for the operation. If different from the true
17947 destination in operands[0], a copy operation will be required. */
17949 rtx
17951 rtx operands[])
17952 {
17957 /* Canonicalize operand order. */
17959 {
17960 /* It is invalid to swap operands of different modes. */
17964 }
17966 /* Both source operands cannot be in memory. */
17968 {
17969 /* Optimization: Only read from memory once. */
17971 {
17974 }
17977 else
17979 }
17981 /* If the destination is memory, and we do not have matching source
17982 operands, do things in registers. */
17986 /* Source 1 cannot be a constant. */
17990 /* Source 1 cannot be a non-matching memory. */
17994 /* Improve address combine. */
18003 }
18005 /* Similarly, but assume that the destination has already been
18006 set up properly. */
18008 void
18011 {
18014 }
18016 /* Attempt to expand a binary operator. Make the expansion closer to the
18017 actual machine, then just general_operand, which will allow 3 separate
18018 memory references (one output, two input) in a single insn. */
18020 void
18022 rtx operands[])
18023 {
18030 /* Emit the instruction. */
18034 {
18035 /* Reload doesn't know about the flags register, and doesn't know that
18036 it doesn't want to clobber it. We can only do this with PLUS. */
18039 }
18043 {
18044 /* This is going to be an LEA; avoid splitting it later. */
18046 }
18047 else
18048 {
18051 }
18053 /* Fix up the destination if needed. */
18056 }
18058 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18059 the given OPERANDS. */
18061 void
18063 rtx operands[])
18064 {
18067 {
18070 }
18072 {
18075 }
18076 /* Optimize (__m128i) d | (__m128i) e and similar code
18077 when d and e are float vectors into float vector logical
18078 insn. In C/C++ without using intrinsics there is no other way
18079 to express vector logical operation on float vectors than
18080 to cast them temporarily to integer vectors. */
18082 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18091 {
18092 rtx dst;
18094 {
18103 {
18106 }
18107 else
18108 {
18113 }
18124 }
18125 }
18134 }
18136 /* Return TRUE or FALSE depending on whether the binary operator meets the
18137 appropriate constraints. */
18139 bool
18142 {
18147 /* Both source operands cannot be in memory. */
18151 /* Canonicalize operand order for commutative operators. */
18155 /* If the destination is memory, we must have a matching source operand. */
18159 /* Source 1 cannot be a constant. */
18163 /* Source 1 cannot be a non-matching memory. */
18165 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18173 }
18175 /* Attempt to expand a unary operator. Make the expansion closer to the
18176 actual machine, then just general_operand, which will allow 2 separate
18177 memory references (one output, one input) in a single insn. */
18179 void
18181 rtx operands[])
18182 {
18189 /* If the destination is memory, and we do not have matching source
18190 operands, do things in registers. */
18192 {
18195 else
18197 }
18199 /* When source operand is memory, destination must match. */
18203 /* Emit the instruction. */
18207 {
18208 /* Reload doesn't know about the flags register, and doesn't know that
18209 it doesn't want to clobber it. */
18212 }
18213 else
18214 {
18217 }
18219 /* Fix up the destination if needed. */
18222 }
18224 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18225 divisor are within the range [0-255]. */
18227 void
18230 {
18239 {
18252 }
18259 /* Use 8bit unsigned divimod if dividend and divisor are within
18260 the range [0-255]. */
18269 pc_rtx);
18274 /* Generate original signed/unsigned divimod. */
18279 /* Branch to the end. */
18283 /* Generate 8bit unsigned divide. */
18285 /* Don't use operands[0] for result of 8bit divide since not all
18286 registers support QImode ZERO_EXTRACT. */
18293 {
18296 }
18297 else
18298 {
18301 }
18303 /* Extract remainder from AH. */
18307 else
18308 {
18309 /* Need a new scratch register since the old one has result
18310 of 8bit divide. */
18314 }
18317 /* Zero extend quotient from AL. */
18323 }
18325 #define LEA_MAX_STALL (3)
18326 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18328 /* Increase given DISTANCE in half-cycles according to
18329 dependencies between PREV and NEXT instructions.
18330 Add 1 half-cycle if there is no dependency and
18331 go to next cycle if there is some dependecy. */
18333 static unsigned int
18335 {
18351 }
18353 /* Function checks if instruction INSN defines register number
18354 REGNO1 or REGNO2. */
18356 static bool
18358 rtx insn)
18359 {
18360 df_ref def;
18370 }
18372 /* Function checks if instruction INSN uses register number
18373 REGNO as a part of address expression. */
18375 static bool
18377 {
18378 df_ref use;
18385 }
18387 /* Search backward for non-agu definition of register number REGNO1
18388 or register number REGNO2 in basic block starting from instruction
18389 START up to head of basic block or instruction INSN.
18391 Function puts true value into *FOUND var if definition was found
18392 and false otherwise.
18394 Distance in half-cycles between START and found instruction or head
18395 of BB is added to DISTANCE and returned. */
18397 static int
18401 {
18411 {
18413 {
18416 {
18419 {
18422 }
18423 }
18426 }
18431 }
18434 }
18436 /* Search backward for non-agu definition of register number REGNO1
18437 or register number REGNO2 in INSN's basic block until
18438 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18439 2. Reach neighbour BBs boundary, or
18440 3. Reach agu definition.
18441 Returns the distance between the non-agu definition point and INSN.
18442 If no definition point, returns -1. */
18444 static int
18447 {
18458 {
18459 edge e;
18460 edge_iterator ei;
18465 {
18468 }
18474 else
18475 {
18480 {
18481 int bb_dist
18487 {
18494 }
18495 }
18498 }
18499 }
18501 /* get_attr_type may modify recog data. We want to make sure
18502 that recog data is valid for instruction INSN, on which
18503 distance_non_agu_define is called. INSN is unchanged here. */
18510 }
18512 /* Return the distance in half-cycles between INSN and the next
18513 insn that uses register number REGNO in memory address added
18514 to DISTANCE. Return -1 if REGNO0 is set.
18516 Put true value into *FOUND if register usage was found and
18517 false otherwise.
18518 Put true value into *REDEFINED if register redefinition was
18519 found and false otherwise. */
18521 static int
18525 {
18534 {
18537 /* If insn and start belong to the same bb, set prev to insn,
18538 so the call to increase_distance will increase the distance
18539 between insns by 1. */
18541 }
18546 {
18548 {
18551 {
18552 /* Return DISTANCE if OP0 is used in memory
18553 address in NEXT. */
18556 }
18559 {
18560 /* Return -1 if OP0 is set in NEXT. */
18563 }
18566 }
18572 }
18575 }
18577 /* Return the distance between INSN and the next insn that uses
18578 register number REGNO0 in memory address. Return -1 if no such
18579 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18581 static int
18583 {
18595 {
18596 edge e;
18597 edge_iterator ei;
18602 {
18605 }
18611 else
18612 {
18618 {
18619 int bb_dist
18624 {
18631 }
18632 }
18635 }
18636 }
18642 }
18644 /* Define this macro to tune LEA priority vs ADD, it take effect when
18645 there is a dilemma of choicing LEA or ADD
18646 Negative value: ADD is more preferred than LEA
18647 Zero: Netrual
18648 Positive value: LEA is more preferred than ADD*/
18649 #define IX86_LEA_PRIORITY 0
18651 /* Return true if usage of lea INSN has performance advantage
18652 over a sequence of instructions. Instructions sequence has
18653 SPLIT_COST cycles higher latency than lea latency. */
18655 static bool
18658 {
18661 /* For Silvermont if using a 2-source or 3-source LEA for
18662 non-destructive destination purposes, or due to wanting
18663 ability to use SCALE, the use of LEA is justified. */
18665 {
18673 }
18679 {
18680 /* If there is no non AGU operand definition, no AGU
18681 operand usage and split cost is 0 then both lea
18682 and non lea variants have same priority. Currently
18683 we prefer lea for 64 bit code and non lea on 32 bit
18684 code. */
18687 else
18689 }
18691 /* With longer definitions distance lea is more preferable.
18692 Here we change it to take into account splitting cost and
18693 lea priority. */
18696 /* If there is no use in memory addess then we just check
18697 that split cost exceeds AGU stall. */
18701 /* If this insn has both backward non-agu dependence and forward
18702 agu dependence, the one with short distance takes effect. */
18704 }
18706 /* Return true if it is legal to clobber flags by INSN and
18707 false otherwise. */
18709 static bool
18711 {
18713 df_ref use;
18714 bitmap live;
18717 {
18719 {
18726 }
18732 }
18736 }
18738 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18739 move and add to avoid AGU stalls. */
18741 bool
18743 {
18746 /* Check if we need to optimize. */
18750 /* Check it is correct to split here. */
18758 /* We need to split only adds with non destructive
18759 destination operand. */
18762 else
18764 }
18766 /* Return true if we should emit lea instruction instead of mov
18767 instruction. */
18769 bool
18771 {
18774 /* Check if we need to optimize. */
18778 /* Use lea for reg to reg moves only. */
18786 }
18788 /* Return true if we need to split lea into a sequence of
18789 instructions to avoid AGU stalls. */
18791 bool
18793 {
18799 /* Check we need to optimize. */
18803 /* The "at least two components" test below might not catch simple
18804 move or zero extension insns if parts.base is non-NULL and parts.disp
18805 is const0_rtx as the only components in the address, e.g. if the
18806 register is %rbp or %r13. As this test is much cheaper and moves or
18807 zero extensions are the common case, do this check first. */
18813 /* Check if it is OK to split here. */
18820 /* There should be at least two components in the address. */
18825 /* We should not split into add if non legitimate pic
18826 operand is used as displacement. */
18841 /* Compute how many cycles we will add to execution time
18842 if split lea into a sequence of instructions. */
18844 {
18845 /* Have to use mov instruction if non desctructive
18846 destination form is used. */
18850 /* Have to add index to base if both exist. */
18854 /* Have to use shift and adds if scale is 2 or greater. */
18856 {
18861 else
18863 }
18865 /* Have to use add instruction with immediate if
18866 disp is non zero. */
18870 /* Subtract the price of lea. */
18872 }
18876 }
18878 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18879 matches destination. RTX includes clobber of FLAGS_REG. */
18881 static void
18884 {
18891 }
18893 /* Return true if regno1 def is nearest to the insn. */
18895 static bool
18897 {
18904 {
18906 {
18909 }
18915 }
18917 /* None of the regs is defined in the bb. */
18919 }
18921 /* Split lea instructions into a sequence of instructions
18922 which are executed on ALU to avoid AGU stalls.
18923 It is assumed that it is allowed to clobber flags register
18924 at lea position. */
18926 void
18928 {
18944 {
18947 }
18950 {
18953 }
18959 {
18960 /* Case r1 = r1 + ... */
18962 {
18963 /* If we have a case r1 = r1 + C * r2 then we
18964 should use multiplication which is very
18965 expensive. Assume cost model is wrong if we
18966 have such case here. */
18971 }
18972 else
18973 {
18974 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18978 /* Use shift for scaling. */
18987 }
18988 }
18990 {
18993 }
18994 else
18995 {
18997 {
19000 }
19002 {
19005 }
19006 else
19007 {
19012 else
19013 {
19014 rtx tmp1;
19016 /* Find better operand for SET instruction, depending
19017 on which definition is farther from the insn. */
19020 else
19030 }
19033 }
19037 }
19038 }
19040 /* Return true if it is ok to optimize an ADD operation to LEA
19041 operation to avoid flag register consumation. For most processors,
19042 ADD is faster than LEA. For the processors like BONNELL, if the
19043 destination register of LEA holds an actual address which will be
19044 used soon, LEA is better and otherwise ADD is better. */
19046 bool
19048 {
19053 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19061 }
19063 /* Return true if destination reg of SET_BODY is shift count of
19064 USE_BODY. */
19066 static bool
19068 {
19069 rtx set_dest;
19070 rtx shift_rtx;
19073 /* Retrieve destination of SET_BODY. */
19075 {
19084 use_body))
19089 }
19091 /* Retrieve shift count of USE_BODY. */
19093 {
19105 }
19113 {
19116 /* Return true if shift count is dest of SET_BODY. */
19118 {
19119 /* Add check since it can be invoked before register
19120 allocation in pre-reload schedule. */
19126 }
19127 }
19130 }
19132 /* Return true if destination reg of SET_INSN is shift count of
19133 USE_INSN. */
19135 bool
19137 {
19140 }
19142 /* Return TRUE or FALSE depending on whether the unary operator meets the
19143 appropriate constraints. */
19145 bool
19147 machine_mode,
19149 {
19150 /* If one of operands is memory, source and destination must match. */
19156 }
19158 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19159 are ok, keeping in mind the possible movddup alternative. */
19161 bool
19163 {
19169 }
19171 /* Post-reload splitter for converting an SF or DFmode value in an
19172 SSE register into an unsigned SImode. */
19174 void
19176 {
19177 machine_mode vecmode;
19187 /* Load up the value into the low element. We must ensure that the other
19188 elements are valid floats -- zero is the easiest such value. */
19190 {
19193 else
19195 }
19196 else
19197 {
19202 else
19204 }
19224 else
19229 }
19231 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19232 Expects the 64-bit DImode to be supplied in a pair of integral
19233 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19234 -mfpmath=sse, !optimize_size only. */
19236 void
19238 {
19242 rtx x;
19248 {
19251 }
19252 else
19253 {
19257 }
19265 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19268 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19269 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19270 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19271 (0x1.0p84 + double(fp_value_hi_xmm)).
19272 Note these exponents differ by 32. */
19276 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19277 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19286 /* Add the upper and lower DFmode values together. */
19289 else
19290 {
19294 }
19297 }
19299 /* Not used, but eases macroization of patterns. */
19300 void
19302 {
19304 }
19306 /* Convert an unsigned SImode value into a DFmode. Only currently used
19307 for SSE, but applicable anywhere. */
19309 void
19311 {
19312 REAL_VALUE_TYPE TWO31r;
19327 }
19329 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19330 32-bit mode; otherwise we have a direct convert instruction. */
19332 void
19334 {
19335 REAL_VALUE_TYPE TWO32r;
19353 }
19355 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19356 For x86_32, -mfpmath=sse, !optimize_size only. */
19357 void
19359 {
19360 REAL_VALUE_TYPE ONE16r;
19379 }
19381 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19382 a vector of unsigned ints VAL to vector of floats TARGET. */
19384 void
19386 {
19388 REAL_VALUE_TYPE TWO16r;
19395 else
19400 OPTAB_DIRECT);
19411 OPTAB_DIRECT);
19413 OPTAB_DIRECT);
19416 }
19418 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19419 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19420 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19421 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19423 rtx
19425 {
19426 REAL_VALUE_TYPE TWO31r;
19441 {
19447 }
19456 OPTAB_DIRECT);
19457 else
19458 {
19464 OPTAB_DIRECT);
19465 }
19468 }
19470 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19471 then replicate the value for all elements of the vector
19472 register. */
19474 rtx
19476 {
19478 rtvec v;
19479 machine_mode scalar_mode;
19482 {
19515 }
19516 }
19518 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19519 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19520 for an SSE register. If VECT is true, then replicate the mask for
19521 all elements of the vector register. If INVERT is true, then create
19522 a mask excluding the sign bit. */
19524 rtx
19526 {
19530 rtx v;
19531 rtx mask;
19533 /* Find the sign bit, sign extended to 2*HWI. */
19535 {
19559 else
19567 {
19570 }
19571 else
19572 {
19573 rtvec vec;
19579 {
19582 }
19583 else
19593 }
19598 }
19603 /* Force this value into the low part of a fp vector constant. */
19612 }
19614 /* Generate code for floating point ABS or NEG. */
19616 void
19618 rtx operands[])
19619 {
19630 {
19636 }
19638 /* NEG and ABS performed with SSE use bitwise mask operations.
19639 Create the appropriate mask now. */
19642 else
19652 {
19654 rtvec par;
19659 else
19660 {
19663 }
19665 }
19666 else
19668 }
19670 /* Expand a copysign operation. Special case operand 0 being a constant. */
19672 void
19674 {
19688 else
19692 {
19699 {
19702 else
19703 {
19707 }
19708 }
19718 else
19722 }
19723 else
19724 {
19734 else
19738 }
19739 }
19741 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19742 be a constant, and so has already been expanded into a vector constant. */
19744 void
19746 {
19762 {
19765 }
19766 }
19768 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19769 so we have to do two masks. */
19771 void
19773 {
19788 {
19789 /* Shouldn't happen often (it's useless, obviously), but when it does
19790 we'd generate incorrect code if we continue below. */
19793 }
19796 {
19807 }
19808 else
19809 {
19811 {
19813 }
19815 {
19819 }
19823 {
19826 }
19828 {
19833 }
19835 }
19839 }
19841 /* Return TRUE or FALSE depending on whether the first SET in INSN
19842 has source and destination with matching CC modes, and that the
19843 CC mode is at least as constrained as REQ_MODE. */
19845 bool
19847 {
19848 rtx set;
19849 machine_mode set_mode;
19859 {
19869 /* FALLTHRU */
19873 /* FALLTHRU */
19877 /* FALLTHRU */
19891 }
19894 }
19896 /* Generate insn patterns to do an integer compare of OPERANDS. */
19898 static rtx
19900 {
19901 machine_mode cmpmode;
19907 /* This is very simple, but making the interface the same as in the
19908 FP case makes the rest of the code easier. */
19912 /* Return the test that should be put into the flags user, i.e.
19913 the bcc, scc, or cmov instruction. */
19915 }
19917 /* Figure out whether to use ordered or unordered fp comparisons.
19918 Return the appropriate mode to use. */
19920 machine_mode
19922 {
19923 /* ??? In order to make all comparisons reversible, we do all comparisons
19924 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19925 all forms trapping and nontrapping comparisons, we can make inequality
19926 comparisons trapping again, since it results in better code when using
19927 FCOM based compares. */
19929 }
19931 machine_mode
19933 {
19937 {
19940 }
19943 {
19944 /* Only zero flag is needed. */
19948 /* Codes needing carry flag. */
19951 /* Detect overflow checks. They need just the carry flag. */
19955 else
19960 /* Codes possibly doable only with sign flag when
19961 comparing against zero. */
19966 else
19967 /* For other cases Carry flag is not required. */
19969 /* Codes doable only with sign flag when comparing
19970 against zero, but we miss jump instruction for it
19971 so we need to use relational tests against overflow
19972 that thus needs to be zero. */
19977 else
19979 /* strcmp pattern do (use flags) and combine may ask us for proper
19980 mode. */
19985 }
19986 }
19988 /* Return the fixed registers used for condition codes. */
19990 static bool
19992 {
19996 }
19998 /* If two condition code modes are compatible, return a condition code
19999 mode which is compatible with both. Otherwise, return
20000 VOIDmode. */
20002 static machine_mode
20004 {
20021 {
20035 {
20049 }
20053 /* These are only compatible with themselves, which we already
20054 checked above. */
20056 }
20057 }
20060 /* Return a comparison we can do and that it is equivalent to
20061 swap_condition (code) apart possibly from orderedness.
20062 But, never change orderedness if TARGET_IEEE_FP, returning
20063 UNKNOWN in that case if necessary. */
20065 static enum rtx_code
20067 {
20069 {
20080 }
20081 }
20083 /* Return cost of comparison CODE using the best strategy for performance.
20084 All following functions do use number of instructions as a cost metrics.
20085 In future this should be tweaked to compute bytes for optimize_size and
20086 take into account performance of various instructions on various CPUs. */
20088 static int
20090 {
20093 /* The cost of code using bit-twiddling on %ah. */
20095 {
20118 }
20121 {
20128 }
20129 }
20131 /* Return strategy to use for floating-point. We assume that fcomi is always
20132 preferrable where available, since that is also true when looking at size
20133 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20135 enum ix86_fpcmp_strategy
20137 {
20138 /* Do fcomi/sahf based test when profitable. */
20147 }
20149 /* Swap, force into registers, or otherwise massage the two operands
20150 to a fp comparison. The operands are updated in place; the new
20151 comparison code is returned. */
20153 static enum rtx_code
20155 {
20161 /* All of the unordered compare instructions only work on registers.
20162 The same is true of the fcomi compare instructions. The XFmode
20163 compare instructions require registers except when comparing
20164 against zero or when converting operand 1 from fixed point to
20165 floating point. */
20174 {
20177 }
20178 else
20179 {
20180 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20181 things around if they appear profitable, otherwise force op0
20182 into a register. */
20188 {
20191 {
20194 }
20195 }
20201 {
20206 {
20209 }
20210 else
20212 }
20213 }
20215 /* Try to rearrange the comparison to make it cheaper. */
20219 {
20224 }
20229 }
20231 /* Convert comparison codes we use to represent FP comparison to integer
20232 code that will result in proper branch. Return UNKNOWN if no such code
20233 is available. */
20235 enum rtx_code
20237 {
20239 {
20262 }
20263 }
20265 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20267 static rtx
20269 {
20276 /* Do fcomi/sahf based test when profitable. */
20278 {
20283 tmp);
20291 tmp);
20300 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20307 /* In the unordered case, we have to check C2 for NaN's, which
20308 doesn't happen to work out to anything nice combination-wise.
20309 So do some bit twiddling on the value we've got in AH to come
20310 up with an appropriate set of condition codes. */
20314 {
20318 {
20321 }
20322 else
20323 {
20329 }
20334 {
20339 }
20340 else
20341 {
20344 }
20349 {
20352 }
20353 else
20354 {
20358 }
20363 {
20369 }
20370 else
20371 {
20374 }
20379 {
20384 }
20385 else
20386 {
20389 }
20394 {
20399 }
20400 else
20401 {
20404 }
20418 }
20423 }
20425 /* Return the test that should be put into the flags user, i.e.
20426 the bcc, scc, or cmov instruction. */
20429 const0_rtx);
20430 }
20432 static rtx
20434 {
20435 rtx ret;
20441 {
20444 }
20445 else
20449 }
20451 void
20453 {
20455 rtx tmp;
20458 {
20465 simple:
20469 pc_rtx);
20477 /* Expand DImode branch into multiple compare+branch. */
20478 {
20482 machine_mode submode;
20485 {
20488 }
20495 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20496 avoid two branches. This costs one extra insn, so disable when
20497 optimizing for size. */
20502 {
20520 }
20522 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20523 op1 is a constant and the low word is zero, then we can just
20524 examine the high word. Similarly for low word -1 and
20525 less-or-equal-than or greater-than. */
20529 {
20532 {
20535 }
20539 {
20542 }
20546 }
20548 /* Otherwise, we need two or three jumps. */
20557 {
20571 }
20573 /*
20574 * a < b =>
20575 * if (hi(a) < hi(b)) goto true;
20576 * if (hi(a) > hi(b)) goto false;
20577 * if (lo(a) < lo(b)) goto true;
20578 * false:
20579 */
20591 }
20596 }
20597 }
20599 /* Split branch based on floating point condition. */
20600 void
20603 {
20604 rtx condition;
20605 rtx i;
20608 {
20611 }
20614 tmp);
20622 }
20624 void
20626 {
20627 rtx ret;
20634 }
20636 /* Expand comparison setting or clearing carry flag. Return true when
20637 successful and set pop for the operation. */
20638 static bool
20640 {
20641 machine_mode mode =
20644 /* Do not handle double-mode compares that go through special path. */
20649 {
20650 rtx compare_op;
20655 /* Shortcut: following common codes never translate
20656 into carry flag compares. */
20661 /* These comparisons require zero flag; swap operands so they won't. */
20664 {
20667 }
20669 /* Try to expand the comparison and verify that we end up with
20670 carry flag based comparison. This fails to be true only when
20671 we decide to expand comparison using arithmetic that is not
20672 too common scenario. */
20681 else
20690 }
20696 {
20701 /* Convert a==0 into (unsigned)a<1. */
20710 /* Convert a>b into b<a or a>=b-1. */
20714 {
20716 /* Bail out on overflow. We still can swap operands but that
20717 would force loading of the constant into register. */
20722 }
20723 else
20724 {
20727 }
20730 /* Convert a>=0 into (unsigned)a<0x80000000. */
20748 }
20749 /* Swapping operands may cause constant to appear as first operand. */
20751 {
20755 }
20759 }
20761 bool
20763 {
20766 rtx compare_op;
20788 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20789 HImode insns, we'd be swallowed in word prefix ops. */
20795 {
20799 HOST_WIDE_INT diff;
20802 /* Sign bit compares are better done using shifts than we do by using
20803 sbb. */
20806 {
20807 /* Detect overlap between destination and compare sources. */
20811 {
20812 rtx flags;
20821 {
20823 compare_code
20825 }
20827 /* To simplify rest of code, restrict to the GEU case. */
20829 {
20833 }
20834 else
20835 {
20838 reverse_condition_maybe_unordered
20840 else
20843 }
20852 else
20855 }
20856 else
20857 {
20860 else
20861 {
20864 }
20866 }
20869 {
20870 /*
20871 * cmpl op0,op1
20872 * sbbl dest,dest
20873 * [addl dest, ct]
20874 *
20875 * Size 5 - 8.
20876 */
20881 }
20883 {
20884 /*
20885 * cmpl op0,op1
20886 * sbbl dest,dest
20887 * orl $ct, dest
20888 *
20889 * Size 8.
20890 */
20894 }
20896 {
20897 /*
20898 * cmpl op0,op1
20899 * sbbl dest,dest
20900 * notl dest
20901 * [addl dest, cf]
20902 *
20903 * Size 8 - 11.
20904 */
20910 }
20911 else
20912 {
20913 /*
20914 * cmpl op0,op1
20915 * sbbl dest,dest
20916 * [notl dest]
20917 * andl cf - ct, dest
20918 * [addl dest, ct]
20919 *
20920 * Size 8 - 11.
20921 */
20924 {
20928 }
20938 }
20944 }
20947 {
20952 {
20955 /* We may be reversing unordered compare to normal compare, that
20956 is not valid in general (we may convert non-trapping condition
20957 to trapping one), however on i386 we currently emit all
20958 comparisons unordered. */
20960 }
20961 else
20964 {
20968 }
20969 }
20974 {
20979 {
20984 }
20985 }
20987 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20991 {
20992 /* If lea code below could be used, only optimize
20993 if it results in a 2 insn sequence. */
20999 {
21000 /*
21001 * notl op1 (if necessary)
21002 * sarl $31, op1
21003 * orl cf, op1
21004 */
21006 {
21010 }
21021 }
21022 }
21030 {
21031 /*
21032 * xorl dest,dest
21033 * cmpl op1,op2
21034 * setcc dest
21035 * lea cf(dest*(ct-cf)),dest
21036 *
21037 * Size 14.
21038 *
21039 * This also catches the degenerate setcc-only case.
21040 */
21042 rtx tmp;
21048 /* On x86_64 the lea instruction operates on Pmode, so we need
21049 to get arithmetics done in proper mode to match. */
21052 else
21053 {
21054 rtx out1;
21057 nops++;
21059 {
21061 nops++;
21062 }
21063 }
21065 {
21067 nops++;
21068 }
21070 {
21073 else
21075 }
21080 }
21082 /*
21083 * General case: Jumpful:
21084 * xorl dest,dest cmpl op1, op2
21085 * cmpl op1, op2 movl ct, dest
21086 * setcc dest jcc 1f
21087 * decl dest movl cf, dest
21088 * andl (cf-ct),dest 1:
21089 * addl ct,dest
21090 *
21091 * Size 20. Size 14.
21092 *
21093 * This is reasonably steep, but branch mispredict costs are
21094 * high on modern cpus, so consider failing only if optimizing
21095 * for space.
21096 */
21101 {
21103 {
21108 {
21111 /* We may be reversing unordered compare to normal compare,
21112 that is not valid in general (we may convert non-trapping
21113 condition to trapping one), however on i386 we currently
21114 emit all comparisons unordered. */
21116 }
21117 else
21118 {
21122 }
21125 {
21129 }
21130 }
21133 {
21134 /* notl op1 (if needed)
21135 sarl $31, op1
21136 andl (cf-ct), op1
21137 addl ct, op1
21139 For x < 0 (resp. x <= -1) there will be no notl,
21140 so if possible swap the constants to get rid of the
21141 complement.
21142 True/false will be -1/0 while code below (store flag
21143 followed by decrement) is 0/-1, so the constants need
21144 to be exchanged once more. */
21147 {
21150 }
21151 else
21155 }
21156 else
21157 {
21161 constm1_rtx,
21163 }
21175 }
21176 }
21179 {
21180 /* Try a few things more with specific constants and a variable. */
21182 optab op;
21188 /* If one of the two operands is an interesting constant, load a
21189 constant with the above and mask it in with a logical operation. */
21192 {
21198 else
21200 }
21202 {
21208 else
21210 }
21211 else
21218 /* Recurse to get the constant loaded. */
21222 /* Mask in the interesting variable. */
21224 OPTAB_WIDEN);
21229 }
21231 /*
21232 * For comparison with above,
21233 *
21234 * movl cf,dest
21235 * movl ct,tmp
21236 * cmpl op1,op2
21237 * cmovcc tmp,dest
21238 *
21239 * Size 15.
21240 */
21262 }
21264 /* Swap, force into registers, or otherwise massage the two operands
21265 to an sse comparison with a mask result. Thus we differ a bit from
21266 ix86_prepare_fp_compare_args which expects to produce a flags result.
21268 The DEST operand exists to help determine whether to commute commutative
21269 operators. The POP0/POP1 operands are updated in place. The new
21270 comparison code is returned, or UNKNOWN if not implementable. */
21272 static enum rtx_code
21275 {
21277 {
21280 /* AVX supports all the needed comparisons. */
21283 /* We have no LTGT as an operator. We could implement it with
21284 NE & ORDERED, but this requires an extra temporary. It's
21285 not clear that it's worth it. */
21292 /* These are supported directly. */
21299 /* AVX has 3 operand comparisons, no need to swap anything. */
21302 /* For commutative operators, try to canonicalize the destination
21303 operand to be first in the comparison - this helps reload to
21304 avoid extra moves. */
21307 /* FALLTHRU */
21313 /* These are not supported directly before AVX, and furthermore
21314 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21315 comparison operands to transform into something that is
21316 supported. */
21323 }
21326 }
21328 /* Detect conditional moves that exactly match min/max operational
21329 semantics. Note that this is IEEE safe, as long as we don't
21330 interchange the operands.
21332 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21333 and TRUE if the operation is successful and instructions are emitted. */
21335 static bool
21338 {
21339 machine_mode mode;
21341 rtx tmp;
21344 ;
21347 else
21354 else
21359 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21360 but MODE may be a vector mode and thus not appropriate. */
21362 {
21364 rtvec v;
21369 }
21370 else
21371 {
21374 }
21378 }
21380 /* Expand an sse vector comparison. Return the register with the result. */
21382 static rtx
21385 {
21389 /* In general case result of comparison can differ from operands' type. */
21390 machine_mode cmp_mode;
21392 /* In AVX512F the result of comparison is an integer mask. */
21394 rtx x;
21397 {
21402 }
21403 else
21416 /* Compare patterns for int modes are unspec in AVX512F only. */
21418 {
21422 {
21439 }
21442 {
21445 }
21446 }
21450 {
21453 }
21454 else
21458 }
21460 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21461 operations. This is used for both scalar and vector conditional moves. */
21463 static void
21465 {
21469 /* In AVX512F the result of comparison is an integer mask. */
21477 {
21479 }
21482 {
21486 }
21489 {
21494 }
21497 {
21501 }
21504 {
21512 op_true,
21513 op_false)));
21514 }
21515 else
21516 {
21526 {
21540 {
21547 }
21562 {
21569 }
21593 }
21596 {
21600 }
21601 else
21602 {
21608 else
21620 }
21621 }
21622 }
21624 /* Expand a floating-point conditional move. Return true if successful. */
21626 bool
21628 {
21636 {
21637 machine_mode cmode;
21639 /* Since we've no cmove for sse registers, don't force bad register
21640 allocation just to gain access to it. Deny movcc when the
21641 comparison mode doesn't match the move mode. */
21660 }
21667 /* The floating point conditional move instructions don't directly
21668 support conditions resulting from a signed integer comparison. */
21672 {
21677 }
21684 }
21686 /* Expand a floating-point vector conditional move; a vcond operation
21687 rather than a movcc operation. */
21689 bool
21691 {
21693 rtx cmp;
21698 {
21699 rtx temp;
21701 {
21718 }
21720 OPTAB_DIRECT);
21723 }
21733 }
21735 /* Expand a signed/unsigned integral vector conditional move. */
21737 bool
21739 {
21749 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21750 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21759 {
21763 {
21769 }
21772 {
21778 }
21779 }
21788 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21792 ;
21793 else
21794 {
21795 /* Canonicalize the comparison to EQ, GT, GTU. */
21797 {
21814 /* FALLTHRU */
21824 }
21826 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21828 {
21830 {
21832 /* SSE4.1 supports EQ. */
21839 /* SSE4.2 supports GT/GTU. */
21846 }
21847 }
21849 /* Unsigned parallel compare is not supported by the hardware.
21850 Play some tricks to turn this into a signed comparison
21851 against 0. */
21853 {
21857 {
21864 {
21869 {
21878 }
21879 /* Subtract (-(INT MAX) - 1) from both operands to make
21880 them signed. */
21891 }
21900 /* Perform a parallel unsigned saturating subtraction. */
21913 }
21914 }
21915 }
21917 /* Allow the comparison to be done in one mode, but the movcc to
21918 happen in another mode. */
21920 {
21923 }
21924 else
21925 {
21931 }
21936 }
21938 /* AVX512F does support 64-byte integer vector operations,
21939 thus the longest vector we are faced with is V64QImode. */
21940 #define MAX_VECT_LEN 64
21942 struct expand_vec_perm_d
21943 {
21946 machine_mode vmode;
21950 };
21952 static bool
21955 {
21956 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21957 expander, so args are either in d, or in op0, op1 etc. */
21963 {
21994 {
21997 }
22001 {
22004 }
22008 {
22011 }
22027 {
22030 }
22034 {
22037 }
22041 {
22044 }
22048 }
22053 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22054 expander, so args are either in d, or in op0, op1 etc. */
22056 {
22064 }
22068 }
22070 /* Expand a variable vector permutation. */
22072 void
22074 {
22085 /* Number of elements in the vector. */
22094 {
22096 {
22097 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22098 an constant shuffle operand. With a tiny bit of effort we can
22099 use VPERMD instead. A re-interpretation stall for V4DFmode is
22100 unfortunate but there's no avoiding it.
22101 Similarly for V16HImode we don't have instructions for variable
22102 shuffling, while for V32QImode we can use after preparing suitable
22103 masks vpshufb; vpshufb; vpermq; vpor. */
22106 {
22110 }
22111 else
22112 {
22116 }
22119 /* Replicate the low bits of the V4DImode mask into V8SImode:
22120 mask = { A B C D }
22121 t1 = { A A B B C C D D }. */
22129 else
22132 /* Multiply the shuffle indicies by two. */
22134 OPTAB_DIRECT);
22136 /* Add one to the odd shuffle indicies:
22137 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22139 {
22142 }
22146 OPTAB_DIRECT);
22148 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22153 }
22156 {
22158 /* The VPERMD and VPERMPS instructions already properly ignore
22159 the high bits of the shuffle elements. No need for us to
22160 perform an AND ourselves. */
22162 {
22167 }
22168 else
22169 {
22175 }
22182 else
22183 {
22189 }
22193 /* By combining the two 128-bit input vectors into one 256-bit
22194 input vector, we can use VPERMD and VPERMPS for the full
22195 two-operand shuffle. */
22227 /* From mask create two adjusted masks, which contain the same
22228 bits as mask in the low 7 bits of each vector element.
22229 The first mask will have the most significant bit clear
22230 if it requests element from the same 128-bit lane
22231 and MSB set if it requests element from the other 128-bit lane.
22232 The second mask will have the opposite values of the MSB,
22233 and additionally will have its 128-bit lanes swapped.
22234 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22235 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22236 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22237 stands for other 12 bytes. */
22238 /* The bit whether element is from the same lane or the other
22239 lane is bit 4, so shift it up by 3 to the MSB position. */
22243 /* Clear MSB bits from the mask just in case it had them set. */
22245 /* After this t1 will have MSB set for elements from other lane. */
22247 /* Clear bits other than MSB. */
22249 /* Or in the lower bits from mask into t3. */
22251 /* And invert MSB bits in t1, so MSB is set for elements from the same
22252 lane. */
22254 /* Swap 128-bit lanes in t3. */
22259 /* And or in the lower bits from mask into t1. */
22262 {
22263 /* Each of these shuffles will put 0s in places where
22264 element from the other 128-bit lane is needed, otherwise
22265 will shuffle in the requested value. */
22269 /* For t3 the 128-bit lanes are swapped again. */
22274 /* And oring both together leads to the result. */
22281 }
22284 /* Similarly to the above one_operand_shuffle code,
22285 just for repeated twice for each operand. merge_two:
22286 code will merge the two results together. */
22310 }
22311 }
22314 {
22315 /* The XOP VPPERM insn supports three inputs. By ignoring the
22316 one_operand_shuffle special case, we avoid creating another
22317 set of constant vectors in memory. */
22320 /* mask = mask & {2*w-1, ...} */
22322 }
22323 else
22324 {
22325 /* mask = mask & {w-1, ...} */
22327 }
22335 /* For non-QImode operations, convert the word permutation control
22336 into a byte permutation control. */
22338 {
22343 /* Convert mask to vector of chars. */
22346 /* Replicate each of the input bytes into byte positions:
22347 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22348 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22349 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22356 else
22359 /* Convert it into the byte positions by doing
22360 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22366 }
22368 /* The actual shuffle operations all operate on V16QImode. */
22373 {
22380 }
22382 {
22389 }
22390 else
22391 {
22395 /* Shuffle the two input vectors independently. */
22401 merge_two:
22402 /* Then merge them together. The key is whether any given control
22403 element contained a bit set that indicates the second word. */
22407 {
22408 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22409 more shuffle to convert the V2DI input mask into a V4SI
22410 input mask. At which point the masking that expand_int_vcond
22411 will work as desired. */
22419 }
22441 }
22442 }
22444 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22445 true if we should do zero extension, else sign extension. HIGH_P is
22446 true if we want the N/2 high elements, else the low elements. */
22448 void
22450 {
22452 rtx tmp;
22455 {
22461 {
22465 else
22468 extract
22474 else
22477 extract
22483 else
22486 extract
22492 else
22495 extract
22501 else
22504 extract
22510 else
22513 extract
22519 else
22525 else
22531 else
22536 }
22539 {
22542 }
22544 {
22545 /* Shift higher 8 bytes to lower 8 bytes. */
22550 }
22551 else
22555 }
22556 else
22557 {
22561 {
22565 else
22571 else
22577 else
22582 }
22586 else
22593 }
22594 }
22596 /* Expand conditional increment or decrement using adb/sbb instructions.
22597 The default case using setcc followed by the conditional move can be
22598 done by generic code. */
22599 bool
22601 {
22603 rtx flags;
22605 rtx compare_op;
22608 machine_mode mode;
22623 {
22626 }
22629 {
22633 reverse_condition_maybe_unordered
22635 else
22637 }
22641 /* Construct either adc or sbb insn. */
22643 {
22645 {
22660 }
22661 }
22662 else
22663 {
22665 {
22680 }
22681 }
22685 }
22688 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22689 but works for floating pointer parameters and nonoffsetable memories.
22690 For pushes, it returns just stack offsets; the values will be saved
22691 in the right order. Maximally three parts are generated. */
22693 static int
22695 {
22700 else
22706 /* Optimize constant pool reference to immediates. This is used by fp
22707 moves, that force all constants to memory to allow combining. */
22709 {
22713 }
22716 {
22717 /* The only non-offsetable memories we handle are pushes. */
22726 }
22729 {
22731 /* Caution: if we looked through a constant pool memory above,
22732 the operand may actually have a different mode now. That's
22733 ok, since we want to pun this all the way back to an integer. */
22737 }
22740 {
22743 else
22744 {
22748 {
22752 }
22754 {
22759 }
22761 {
22762 REAL_VALUE_TYPE r;
22767 {
22774 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22775 long double may not be 80-bit. */
22784 }
22787 }
22788 else
22790 }
22791 }
22792 else
22793 {
22797 {
22800 {
22804 }
22806 {
22810 }
22812 {
22813 REAL_VALUE_TYPE r;
22819 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22822 = gen_int_mode
22825 DImode);
22826 else
22833 = gen_int_mode
22836 DImode);
22837 else
22839 }
22840 else
22842 }
22843 }
22846 }
22848 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22849 Return false when normal moves are needed; true when all required
22850 insns have been emitted. Operands 2-4 contain the input values
22851 int the correct order; operands 5-7 contain the output values. */
22853 void
22855 {
22863 /* The DFmode expanders may ask us to move double.
22864 For 64bit target this is single move. By hiding the fact
22865 here we simplify i386.md splitters. */
22867 {
22868 /* Optimize constant pool reference to immediates. This is used by
22869 fp moves, that force all constants to memory to allow combining. */
22876 {
22879 }
22880 else
22885 }
22887 /* The only non-offsettable memory we handle is push. */
22890 else
22897 /* When emitting push, take care for source operands on the stack. */
22900 {
22903 /* Compensate for the stack decrement by 4. */
22908 /* src_base refers to the stack pointer and is
22909 automatically decreased by emitted push. */
22913 }
22915 /* We need to do copy in the right order in case an address register
22916 of the source overlaps the destination. */
22918 {
22919 rtx tmp;
22922 {
22926 collisions++;
22927 }
22929 /* Collision in the middle part can be handled by reordering. */
22931 {
22934 }
22938 {
22940 {
22943 }
22944 else
22945 {
22948 }
22949 }
22951 /* If there are more collisions, we can't handle it by reordering.
22952 Do an lea to the last part and use only one colliding move. */
22954 {
22955 rtx base;
22961 /* Handle the case when the last part isn't valid for lea.
22962 Happens in 64-bit mode storing the 12-byte XFmode. */
22969 {
22972 }
22973 }
22974 }
22977 {
22979 {
22981 {
22986 }
22988 {
22991 }
22992 }
22993 else
22994 {
22995 /* In 64bit mode we don't have 32bit push available. In case this is
22996 register, it is OK - we will just use larger counterpart. We also
22997 retype memory - these comes from attempt to avoid REX prefix on
22998 moving of second half of TFmode value. */
23000 {
23002 {
23013 }
23017 }
23018 }
23022 }
23024 /* Choose correct order to not overwrite the source before it is copied. */
23034 {
23036 {
23039 }
23040 }
23041 else
23042 {
23044 {
23047 }
23048 }
23050 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23052 {
23061 }
23067 }
23069 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23070 left shift by a constant, either using a single shift or
23071 a sequence of add instructions. */
23073 static void
23075 {
23081 {
23085 }
23086 else
23087 {
23090 }
23091 }
23093 void
23095 {
23104 {
23109 {
23115 }
23116 else
23117 {
23125 }
23127 }
23134 {
23135 /* Assuming we've chosen a QImode capable registers, then 1 << N
23136 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23138 {
23154 }
23156 /* Otherwise, we can get the same results by manually performing
23157 a bit extract operation on bit 5/6, and then performing the two
23158 shifts. The two methods of getting 0/1 into low/high are exactly
23159 the same size. Avoiding the shift in the bit extract case helps
23160 pentium4 a bit; no one else seems to care much either way. */
23161 else
23162 {
23163 machine_mode half_mode;
23167 HOST_WIDE_INT bits;
23168 rtx x;
23171 {
23177 }
23178 else
23179 {
23185 }
23189 else
23197 }
23202 }
23205 {
23206 /* For -1 << N, we can avoid the shld instruction, because we
23207 know that we're shifting 0...31/63 ones into a -1. */
23211 else
23213 }
23214 else
23215 {
23223 }
23228 {
23234 }
23235 else
23236 {
23241 }
23242 }
23244 void
23246 {
23256 {
23261 {
23267 }
23269 {
23278 }
23279 else
23280 {
23288 }
23289 }
23290 else
23291 {
23303 {
23311 scratch));
23312 }
23313 else
23314 {
23319 }
23320 }
23321 }
23323 void
23325 {
23335 {
23340 {
23347 }
23348 else
23349 {
23357 }
23358 }
23359 else
23360 {
23372 {
23378 scratch));
23379 }
23380 else
23381 {
23386 }
23387 }
23388 }
23390 /* Predict just emitted jump instruction to be taken with probability PROB. */
23391 static void
23393 {
23397 }
23399 /* Helper function for the string operations below. Dest VARIABLE whether
23400 it is aligned to VALUE bytes. If true, jump to the label. */
23403 {
23408 else
23414 else
23417 }
23419 /* Adjust COUNTER by the VALUE. */
23420 static void
23422 {
23427 }
23429 /* Zero extend possibly SImode EXP to Pmode register. */
23430 rtx
23432 {
23434 }
23436 /* Divide COUNTREG by SCALE. */
23437 static rtx
23439 {
23440 rtx sc;
23452 }
23454 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23455 DImode for constant loop counts. */
23457 static machine_mode
23459 {
23467 }
23469 /* Copy the address to a Pmode register. This is used for x32 to
23470 truncate DImode TLS address to a SImode register. */
23472 static rtx
23474 {
23477 else
23478 {
23481 }
23482 }
23484 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23485 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23486 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23487 memory by VALUE (supposed to be in MODE).
23489 The size is rounded down to whole number of chunk size moved at once.
23490 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23493 static void
23498 {
23505 rtx size;
23514 /* Those two should combine. */
23516 {
23520 }
23527 /* This assert could be relaxed - in this case we'll need to compute
23528 smallest power of two, containing in PIECE_SIZE_N and pass it to
23529 offset_address. */
23535 {
23539 /* When unrolling for chips that reorder memory reads and writes,
23540 we can save registers by using single temporary.
23541 Also using 4 temporaries is overkill in 32bit mode. */
23543 {
23545 {
23547 {
23548 destmem =
23550 srcmem =
23552 }
23554 }
23555 }
23556 else
23557 {
23561 {
23564 {
23565 srcmem =
23567 }
23569 }
23571 {
23573 {
23574 destmem =
23576 }
23578 }
23579 }
23580 }
23581 else
23583 {
23585 destmem =
23588 }
23598 {
23604 else
23606 }
23607 else
23615 {
23620 }
23622 }
23624 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23625 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23626 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23627 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23628 ORIG_VALUE is the original value passed to memset to fill the memory with.
23629 Other arguments have same meaning as for previous function. */
23631 static void
23634 rtx count,
23636 {
23637 rtx destexp;
23638 rtx srcexp;
23639 rtx countreg;
23640 HOST_WIDE_INT rounded_count;
23642 /* If possible, it is shorter to use rep movs.
23643 TODO: Maybe it is better to move this logic to decide_alg. */
23654 {
23658 }
23659 else
23662 {
23667 }
23672 {
23675 }
23676 else
23677 {
23681 {
23685 }
23686 else
23689 {
23694 }
23695 else
23696 {
23699 }
23702 }
23703 }
23705 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23706 DESTMEM.
23707 SRC is passed by pointer to be updated on return.
23708 Return value is updated DST. */
23709 static rtx
23711 HOST_WIDE_INT size_to_move)
23712 {
23715 machine_mode move_mode;
23718 /* Find the widest mode in which we could perform moves.
23719 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23720 it until move of such size is supported. */
23725 {
23729 }
23731 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23732 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23734 {
23739 {
23743 }
23744 }
23750 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23754 {
23755 /* We move from memory to memory, so we'll need to do it via
23756 a temporary register. */
23767 piece_size);
23769 piece_size);
23770 }
23772 /* Update DST and SRC rtx. */
23775 }
23777 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23778 static void
23781 {
23784 {
23789 /* For now MAX_SIZE should be a power of 2. This assert could be
23790 relaxed, but it'll require a bit more complicated epilogue
23791 expanding. */
23794 {
23797 }
23799 }
23801 {
23807 }
23809 /* When there are stringops, we can cheaply increase dest and src pointers.
23810 Otherwise we save code size by maintaining offset (zero is readily
23811 available from preceding rep operation) and using x86 addressing modes.
23812 */
23814 {
23816 {
23823 }
23825 {
23832 }
23834 {
23841 }
23842 }
23843 else
23844 {
23846 rtx tmp;
23849 {
23860 }
23862 {
23875 }
23877 {
23886 }
23887 }
23888 }
23890 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23891 with value PROMOTED_VAL.
23892 SRC is passed by pointer to be updated on return.
23893 Return value is updated DST. */
23894 static rtx
23896 HOST_WIDE_INT size_to_move)
23897 {
23900 machine_mode move_mode;
23903 /* Find the widest mode in which we could perform moves.
23904 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23905 it until move of such size is supported. */
23910 {
23913 }
23920 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23924 {
23926 {
23929 piece_size);
23931 }
23939 piece_size);
23940 }
23942 /* Update DST rtx. */
23944 }
23945 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23946 static void
23949 {
23950 count =
23956 }
23958 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23959 static void
23962 {
23963 rtx dest;
23966 {
23971 /* For now MAX_SIZE should be a power of 2. This assert could be
23972 relaxed, but it'll require a bit more complicated epilogue
23973 expanding. */
23976 {
23978 {
23981 else
23983 }
23984 }
23986 }
23988 {
23991 }
23993 {
23996 {
24001 }
24002 else
24003 {
24012 }
24015 }
24017 {
24020 {
24023 }
24024 else
24025 {
24030 }
24033 }
24035 {
24041 }
24043 {
24049 }
24051 {
24057 }
24058 }
24060 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24061 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24062 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24063 ignored.
24064 Return value is updated DESTMEM. */
24065 static rtx
24070 {
24073 {
24075 {
24078 {
24081 else
24083 }
24084 else
24090 }
24091 }
24093 }
24095 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24096 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24097 and jump to DONE_LABEL. */
24098 static void
24104 {
24107 rtx modesize;
24110 /* If we do not have vector value to copy, we must reduce size. */
24112 {
24114 {
24119 }
24120 else
24122 }
24123 else
24124 {
24125 /* Choose appropriate vector mode. */
24131 }
24136 {
24139 else
24140 {
24143 }
24145 }
24151 {
24155 }
24157 {
24160 else
24161 {
24164 }
24166 }
24172 }
24174 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24175 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24176 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24177 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24178 DONE_LABEL is a label after the whole copying sequence. The label is created
24179 on demand if *DONE_LABEL is NULL.
24180 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24181 bounds after the initial copies.
24183 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24184 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24185 we will dispatch to a library call for large blocks.
24187 In pseudocode we do:
24189 if (COUNT < SIZE)
24190 {
24191 Assume that SIZE is 4. Bigger sizes are handled analogously
24192 if (COUNT & 4)
24193 {
24194 copy 4 bytes from SRCPTR to DESTPTR
24195 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24196 goto done_label
24197 }
24198 if (!COUNT)
24199 goto done_label;
24200 copy 1 byte from SRCPTR to DESTPTR
24201 if (COUNT & 2)
24202 {
24203 copy 2 bytes from SRCPTR to DESTPTR
24204 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24205 }
24206 }
24207 else
24208 {
24209 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24210 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24212 OLD_DESPTR = DESTPTR;
24213 Align DESTPTR up to DESIRED_ALIGN
24214 SRCPTR += DESTPTR - OLD_DESTPTR
24215 COUNT -= DEST_PTR - OLD_DESTPTR
24216 if (DYNAMIC_CHECK)
24217 Round COUNT down to multiple of SIZE
24218 << optional caller supplied zero size guard is here >>
24219 << optional caller suppplied dynamic check is here >>
24220 << caller supplied main copy loop is here >>
24221 }
24222 done_label:
24223 */
24224 static void
24227 machine_mode mode,
24237 {
24240 rtx modesize;
24242 rtx mode_value;
24244 /* Chose proper value to copy. */
24247 else
24251 /* See if block is big or small, handle small blocks. */
24253 {
24264 /* Handle sizes > 3. */
24271 /* Nothing to copy? Jump to DONE_LABEL if so */
24275 /* Do a byte copy. */
24279 else
24280 {
24283 }
24285 /* Handle sizes 2 and 3. */
24292 else
24293 {
24298 }
24304 }
24305 else
24309 /* Start memcpy for COUNT >= SIZE. */
24311 {
24314 }
24316 /* Copy first desired_align bytes. */
24322 {
24325 else
24326 {
24329 }
24332 }
24335 /* Copy last SIZE bytes. */
24342 else
24343 {
24349 }
24351 {
24355 else
24356 {
24359 }
24360 }
24362 /* Align destination. */
24364 {
24368 /* Align destptr up, place it to new register. */
24375 /* See how many bytes we skipped. */
24379 /* Adjust srcptr and count. */
24385 /* We copied at most size + prolog_size. */
24388 else
24391 /* Our loops always round down the bock size, but for dispatch to library
24392 we need precise value. */
24396 }
24397 else
24398 {
24400 /* Decrease count, so we won't end up copying last word twice. */
24404 else
24408 }
24409 }
24412 /* This function is like the previous one, except here we know how many bytes
24413 need to be copied. That allows us to update alignment not only of DST, which
24414 is returned, but also of SRC, which is passed as a pointer for that
24415 reason. */
24416 static rtx
24421 {
24429 {
24433 }
24438 {
24440 {
24442 {
24445 else
24447 }
24448 else
24451 }
24452 }
24459 {
24465 {
24468 {
24472 }
24477 }
24481 }
24484 }
24486 /* Return true if ALG can be used in current context.
24487 Assume we expand memset if MEMSET is true. */
24488 static bool
24490 {
24495 /* Algorithms using the rep prefix want at least edi and ecx;
24496 additionally, memset wants eax and memcpy wants esi. Don't
24497 consider such algorithms if the user has appropriated those
24498 registers for their own purposes. */
24505 }
24507 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24508 static enum stringop_alg
24512 {
24523 /* Even if the string operation call is cold, we still might spend a lot
24524 of time processing large blocks. */
24530 else
24536 else
24539 /* See maximal size for user defined algorithm. */
24541 {
24548 }
24550 /* If expected size is not known but max size is small enough
24551 so inline version is a win, set expected size into
24552 the range. */
24557 /* If user specified the algorithm, honnor it if possible. */
24561 /* rep; movq or rep; movl is the smallest variant. */
24563 {
24568 else
24571 }
24572 /* Very tiny blocks are best handled via the loop, REP is expensive to
24573 setup. */
24577 {
24581 {
24582 /* We get here if the algorithms that were not libcall-based
24583 were rep-prefix based and we are unable to use rep prefixes
24584 based on global register usage. Break out of the loop and
24585 use the heuristic below. */
24589 {
24593 {
24596 }
24597 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24598 last non-libcall inline algorithm. */
24600 {
24601 /* When the current size is best to be copied by a libcall,
24602 but we are still forced to inline, run the heuristic below
24603 that will pick code for medium sized blocks. */
24605 {
24608 }
24611 }
24613 {
24616 }
24617 }
24618 }
24619 }
24620 /* When asked to inline the call anyway, try to pick meaningful choice.
24621 We look for maximal size of block that is faster to copy by hand and
24622 take blocks of at most of that size guessing that average size will
24623 be roughly half of the block.
24625 If this turns out to be bad, we might simply specify the preferred
24626 choice in ix86_costs. */
24630 {
24633 /* If there aren't any usable algorithms, then recursing on
24634 smaller sizes isn't going to find anything. Just return the
24635 simple byte-at-a-time copy loop. */
24637 {
24638 /* Pick something reasonable. */
24642 }
24650 else
24653 }
24656 }
24658 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24659 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24660 static int
24664 machine_mode move_mode)
24665 {
24676 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24677 copying whole cacheline at once. */
24690 }
24693 /* Helper function for memcpy. For QImode value 0xXY produce
24694 0xXYXYXYXY of wide specified by MODE. This is essentially
24695 a * 0x10101010, but we can do slightly better than
24696 synth_mult by unwinding the sequence by hand on CPUs with
24697 slow multiply. */
24698 static rtx
24700 {
24702 rtx tmp;
24709 {
24717 }
24726 nops--;
24731 {
24735 OPTAB_DIRECT);
24736 }
24737 else
24738 {
24744 else
24746 else
24747 {
24750 reg =
24752 }
24762 }
24763 }
24765 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24766 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24767 alignment from ALIGN to DESIRED_ALIGN. */
24768 static rtx
24771 {
24772 rtx promoted_val;
24781 else
24785 }
24787 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24788 operations when profitable. The code depends upon architecture, block size
24789 and alignment, but always has one of the following overall structures:
24791 Aligned move sequence:
24793 1) Prologue guard: Conditional that jumps up to epilogues for small
24794 blocks that can be handled by epilogue alone. This is faster
24795 but also needed for correctness, since prologue assume the block
24796 is larger than the desired alignment.
24798 Optional dynamic check for size and libcall for large
24799 blocks is emitted here too, with -minline-stringops-dynamically.
24801 2) Prologue: copy first few bytes in order to get destination
24802 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24803 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24804 copied. We emit either a jump tree on power of two sized
24805 blocks, or a byte loop.
24807 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24808 with specified algorithm.
24810 4) Epilogue: code copying tail of the block that is too small to be
24811 handled by main body (or up to size guarded by prologue guard).
24813 Misaligned move sequence
24815 1) missaligned move prologue/epilogue containing:
24816 a) Prologue handling small memory blocks and jumping to done_label
24817 (skipped if blocks are known to be large enough)
24818 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24819 needed by single possibly misaligned move
24820 (skipped if alignment is not needed)
24821 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24823 2) Zero size guard dispatching to done_label, if needed
24825 3) dispatch to library call, if needed,
24827 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24828 with specified algorithm. */
24829 bool
24835 {
24836 rtx destreg;
24839 rtx tmp;
24855 /* TODO: Once value ranges are available, fill in proper data. */
24863 /* i386 can do misaligned access on reasonably increased cost. */
24867 /* ALIGN is the minimum of destination and source alignment, but we care here
24868 just about destination alignment. */
24874 {
24877 /* When COUNT is 0, there is nothing to do. */
24880 }
24881 else
24882 {
24891 }
24893 /* Make sure we don't need to care about overflow later on. */
24897 /* Step 0: Decide on preferred algorithm, desired alignment and
24898 size of chunks to be copied by main loop. */
24900 issetmem,
24907 /* For now vector-version of memset is generated only for memory zeroing, as
24908 creating of promoted vector value is very cheap in this case. */
24921 {
24940 /* Find the widest supported mode. */
24946 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24947 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24949 {
24954 }
24966 }
24974 /* Step 1: Prologue guard. */
24976 /* Alignment code needs count to be in register. */
24978 {
24981 {
24982 align_bytes
24986 else
24988 }
24991 }
24994 /* Misaligned move sequences handle both prologue and epilogue at once.
24995 Default code generation results in a smaller code for large alignments
24996 and also avoids redundant job when sizes are known precisely. */
24997 misaligned_prologue_used
24998 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25004 /* Do the cheap promotion to allow better CSE across the
25005 main loop and epilogue (ie one load of the big constant in the
25006 front of all code.
25007 For now the misaligned move sequences do not have fast path
25008 without broadcasting. */
25010 {
25012 {
25018 }
25019 else
25020 {
25023 }
25024 }
25025 /* Misaligned move sequences handles both prologues and epilogues at once.
25026 Default code generation results in smaller code for large alignments and
25027 also avoids redundant job when sizes are known precisely. */
25029 {
25030 /* Misaligned move prologue handled small blocks by itself. */
25031 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25036 desired_align < align
25045 {
25046 /* It is possible that we copied enough so the main loop will not
25047 execute. */
25057 else
25059 }
25060 }
25061 /* Ensure that alignment prologue won't copy past end of block. */
25063 {
25065 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25066 Make sure it is power of 2. */
25069 /* To improve performance of small blocks, we jump around the VAL
25070 promoting mode. This mean that if the promoted VAL is not constant,
25071 we might not use it in the epilogue and have to use byte
25072 loop variant. */
25077 {
25078 /* If main algorithm works on QImode, no epilogue is needed.
25079 For small sizes just don't align anything. */
25082 else
25084 }
25087 {
25094 else
25096 }
25097 }
25099 /* Emit code to decide on runtime whether library call or inline should be
25100 used. */
25102 {
25104 {
25106 {
25110 }
25111 }
25112 else
25113 {
25123 else
25127 }
25128 }
25130 /* Step 2: Alignment prologue. */
25131 /* Do the expensive promotion once we branched off the small blocks. */
25137 {
25139 {
25140 /* Except for the first move in prologue, we no longer know
25141 constant offset in aliasing info. It don't seems to worth
25142 the pain to maintain it for the first move, so throw away
25143 the info early. */
25150 issetmem);
25151 /* At most desired_align - align bytes are copied. */
25154 else
25156 }
25157 else
25158 {
25159 /* If we know how many bytes need to be stored before dst is
25160 sufficiently aligned, maintain aliasing info accurately. */
25162 srcreg,
25163 promoted_val,
25164 vec_promoted_val,
25165 desired_align,
25166 align_bytes,
25167 issetmem);
25174 }
25176 && !min_size
25181 {
25182 /* It is possible that we copied enough so the main loop will not
25183 execute. */
25193 else
25195 }
25196 }
25198 {
25205 }
25209 /* Step 3: Main loop. */
25212 {
25235 }
25236 /* Adjust properly the offset of src and dest memory for aliasing. */
25238 {
25244 }
25245 else
25246 {
25250 }
25252 /* Step 4: Epilogue to copy the remaining bytes. */
25253 epilogue:
25255 {
25256 /* When the main loop is done, COUNT_EXP might hold original count,
25257 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25258 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25259 bytes. Compensate if needed. */
25262 {
25263 tmp =
25266 OPTAB_DIRECT);
25269 }
25272 }
25275 {
25278 epilogue_size_needed);
25279 else
25280 {
25284 epilogue_size_needed);
25285 else
25287 epilogue_size_needed);
25288 }
25289 }
25293 }
25296 /* Expand the appropriate insns for doing strlen if not just doing
25297 repnz; scasb
25299 out = result, initialized with the start address
25300 align_rtx = alignment of the address.
25301 scratch = scratch register, initialized with the startaddress when
25302 not aligned, otherwise undefined
25304 This is just the body. It needs the initializations mentioned above and
25305 some address computing at the end. These things are done in i386.md. */
25307 static void
25309 {
25311 rtx tmp;
25316 rtx mem;
25319 rtx cmp;
25325 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25327 /* Is there a known alignment and is it less than 4? */
25329 {
25332 /* Is there a known alignment and is it not 2? */
25334 {
25338 /* Leave just the 3 lower bits. */
25348 }
25349 else
25350 {
25351 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25352 check if is aligned to 4 - byte. */
25359 }
25363 /* Now compare the bytes. */
25365 /* Compare the first n unaligned byte on a byte per byte basis. */
25369 /* Increment the address. */
25372 /* Not needed with an alignment of 2 */
25374 {
25378 end_0_label);
25383 }
25386 end_0_label);
25389 }
25391 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25392 align this loop. It gives only huge programs, but does not help to
25393 speed up. */
25400 /* This formula yields a nonzero result iff one of the bytes is zero.
25401 This saves three branches inside loop and many cycles. */
25409 align_4_label);
25412 {
25418 /* If zero is not in the first two bytes, move two bytes forward. */
25424 reg,
25425 tmpreg)));
25426 /* Emit lea manually to avoid clobbering of flags. */
25434 reg2,
25435 out)));
25436 }
25437 else
25438 {
25440 /* Is zero in the first two bytes? */
25447 pc_rtx);
25451 /* Not in the first two. Move two bytes forward. */
25457 }
25459 /* Avoid branch in fixing the byte. */
25467 }
25469 /* Expand strlen. */
25471 bool
25473 {
25476 /* The generic case of strlen expander is long. Avoid it's
25477 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25480 && !TARGET_INLINE_ALL_STRINGOPS
25490 {
25491 /* Well it seems that some optimizer does not combine a call like
25492 foo(strlen(bar), strlen(bar));
25493 when the move and the subtraction is done here. It does calculate
25494 the length just once when these instructions are done inside of
25495 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25496 often used and I use one fewer register for the lifetime of
25497 output_strlen_unroll() this is better. */
25503 /* strlensi_unroll_1 returns the address of the zero at the end of
25504 the string, like memchr(), so compute the length by subtracting
25505 the start address. */
25507 }
25508 else
25509 {
25510 rtx unspec;
25512 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25525 /* If .md starts supporting :P, this can be done in .md. */
25531 }
25533 }
25535 /* For given symbol (function) construct code to compute address of it's PLT
25536 entry in large x86-64 PIC model. */
25537 static rtx
25539 {
25552 }
25554 rtx
25556 rtx callarg2,
25558 {
25568 {
25569 #if TARGET_MACHO
25572 #endif
25573 }
25574 else
25575 {
25576 /* Static functions and indirect calls don't need the pic register. */
25578 && (!TARGET_64BIT
25583 {
25587 pic_offset_table_rtx);
25588 }
25589 }
25591 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25592 parameters passed in vector registers. */
25597 {
25601 }
25604 && !TARGET_PECOFF
25612 {
25615 }
25620 {
25621 /* We should add bounds as destination register in case
25622 pointer with bounds may be returned. */
25624 {
25629 }
25632 }
25636 {
25640 }
25644 {
25645 int const cregs_size
25650 {
25655 }
25656 }
25665 }
25667 /* Output the assembly for a call instruction. */
25671 {
25677 {
25680 /* SEH epilogue detection requires the indirect branch case
25681 to include REX.W. */
25684 else
25689 }
25691 /* SEH unwinding can require an extra nop to be emitted in several
25692 circumstances. Determine if we have one of those. */
25694 {
25698 {
25699 /* If we get to another real insn, we don't need the nop. */
25703 /* If we get to the epilogue note, prevent a catch region from
25704 being adjacent to the standard epilogue sequence. If non-
25705 call-exceptions, we'll have done this during epilogue emission. */
25707 && !flag_non_call_exceptions
25709 {
25712 }
25713 }
25715 /* If we didn't find a real insn following the call, prevent the
25716 unwinder from looking into the next function. */
25719 }
25723 else
25732 }
25733 \f
25734 /* Clear stack slot assignments remembered from previous functions.
25735 This is called from INIT_EXPANDERS once before RTL is emitted for each
25736 function. */
25740 {
25748 }
25750 /* Return a MEM corresponding to a stack slot with mode MODE.
25751 Allocate a new slot if necessary.
25753 The RTL for a function can have several slots available: N is
25754 which slot to use. */
25756 rtx
25758 {
25775 }
25777 static void
25779 {
25785 }
25786 \f
25787 /* Check whether x86 address PARTS is a pc-relative address. */
25789 static bool
25791 {
25799 {
25801 {
25818 }
25819 }
25821 }
25823 /* Calculate the length of the memory address in the instruction encoding.
25824 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25825 or other prefixes. We never generate addr32 prefix for LEA insn. */
25827 int
25829 {
25846 /* If this is not LEA instruction, add the length of addr32 prefix. */
25851 len++;
25865 /* Rule of thumb:
25866 - esp as the base always wants an index,
25867 - ebp as the base always wants a displacement,
25868 - r12 as the base always wants an index,
25869 - r13 as the base always wants a displacement. */
25871 /* Register Indirect. */
25873 {
25874 /* esp (for its index) and ebp (for its displacement) need
25875 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25876 code. */
25883 len++;
25884 }
25886 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25887 is not disp32, but disp32(%rip), so for disp32
25888 SIB byte is needed, unless print_operand_address
25889 optimizes it into disp32(%rip) or (%rip) is implied
25890 by UNSPEC. */
25892 {
25895 len++;
25896 }
25897 else
25898 {
25899 /* Find the length of the displacement constant. */
25901 {
25904 else
25906 }
25907 /* ebp always wants a displacement. Similarly r13. */
25909 len++;
25911 /* An index requires the two-byte modrm form.... */
25913 /* ...like esp (or r12), which always wants an index. */
25917 len++;
25918 }
25921 }
25923 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25924 is set, expect that insn have 8bit immediate alternative. */
25925 int
25927 {
25933 {
25938 {
25941 {
25953 }
25955 {
25958 }
25959 }
25961 {
25971 /* Immediates for DImode instructions are encoded
25972 as 32bit sign extended values. */
25978 }
25979 }
25981 }
25983 /* Compute default value for "length_address" attribute. */
25984 int
25986 {
25990 {
26001 }
26006 {
26009 {
26014 constraints++;
26017 ;
26018 /* Skip ignored operands. */
26021 }
26023 }
26025 }
26027 /* Compute default value for "length_vex" attribute. It includes
26028 2 or 3 byte VEX prefix and 1 opcode byte. */
26030 int
26033 {
26036 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26037 byte VEX prefix. */
26041 /* We can always use 2 byte VEX prefix in 32bit. */
26049 {
26050 /* REX.W bit uses 3 byte VEX prefix. */
26054 }
26055 else
26056 {
26057 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26061 }
26064 }
26065 \f
26066 /* Return the maximum number of instructions a cpu can issue. */
26068 static int
26070 {
26072 {
26104 }
26105 }
26107 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26108 by DEP_INSN and nothing set by DEP_INSN. */
26110 static bool
26112 {
26115 /* Simplify the test for uninteresting insns. */
26123 {
26126 }
26131 {
26134 }
26135 else
26141 /* This test is true if the dependent insn reads the flags but
26142 not any other potentially set register. */
26150 }
26152 /* Return true iff USE_INSN has a memory address with operands set by
26153 SET_INSN. */
26155 bool
26157 {
26162 {
26165 }
26167 }
26169 /* Helper function for exact_store_load_dependency.
26170 Return true if addr is found in insn. */
26171 static bool
26173 {
26180 {
26186 CASE_CONST_ANY:
26195 }
26199 {
26201 {
26211 }
26212 }
26214 }
26216 /* Return true if there exists exact dependency for store & load, i.e.
26217 the same memory address is used in them. */
26218 static bool
26220 {
26234 }
26236 static int
26238 {
26244 /* Anti and output dependencies have zero cost on all CPUs. */
26250 /* If we can't recognize the insns, we can't really do anything. */
26258 {
26260 /* Address Generation Interlock adds a cycle of latency. */
26262 {
26273 }
26277 /* ??? Compares pair with jump/setcc. */
26281 /* Floating point stores require value to be ready one cycle earlier. */
26289 /* INT->FP conversion is expensive. */
26293 /* There is one cycle extra latency between an FP op and a store. */
26303 /* Show ability of reorder buffer to hide latency of load by executing
26304 in parallel with previous instruction in case
26305 previous instruction is not needed to compute the address. */
26308 {
26309 /* Claim moves to take one cycle, as core can issue one load
26310 at time and the next load can start cycle later. */
26315 cost--;
26316 }
26320 /* The esp dependency is resolved before
26321 the instruction is really finished. */
26326 /* INT->FP conversion is expensive. */
26332 /* Show ability of reorder buffer to hide latency of load by executing
26333 in parallel with previous instruction in case
26334 previous instruction is not needed to compute the address. */
26337 {
26338 /* Claim moves to take one cycle, as core can issue one load
26339 at time and the next load can start cycle later. */
26345 else
26347 }
26358 /* Stack engine allows to execute push&pop instructions in parall. */
26362 /* FALLTHRU */
26368 /* Show ability of reorder buffer to hide latency of load by executing
26369 in parallel with previous instruction in case
26370 previous instruction is not needed to compute the address. */
26373 {
26377 /* Because of the difference between the length of integer and
26378 floating unit pipeline preparation stages, the memory operands
26379 for floating point are cheaper.
26381 ??? For Athlon it the difference is most probably 2. */
26384 else
26389 else
26391 }
26398 /* Stack engine allows to execute push&pop instructions in parall. */
26405 /* Show ability of reorder buffer to hide latency of load by executing
26406 in parallel with previous instruction in case
26407 previous instruction is not needed to compute the address. */
26410 {
26413 else
26415 }
26424 /* Increase cost of integer loads. */
26427 {
26430 {
26433 else
26434 {
26435 /* Increase cost of ld/st for short int types only
26436 because of store forwarding issue. */
26440 {
26441 /* Increase cost of store/load insn if exact
26442 dependence exists and it is load insn. */
26447 }
26448 }
26449 }
26450 }
26454 }
26457 }
26459 /* How many alternative schedules to try. This should be as wide as the
26460 scheduling freedom in the DFA, but no wider. Making this value too
26461 large results extra work for the scheduler. */
26463 static int
26465 {
26467 {
26479 /* We use lookahead value 4 for BD both before and after reload
26480 schedules. Plan is to have value 8 included for O3. */
26491 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26492 as many instructions can be executed on a cycle, i.e.,
26493 issue_rate. I wonder why tuning for many CPUs does not do this. */
26496 /* Don't use lookahead for pre-reload schedule to save compile time. */
26501 }
26502 }
26504 /* Return true if target platform supports macro-fusion. */
26506 static bool
26508 {
26510 }
26512 /* Check whether current microarchitecture support macro fusion
26513 for insn pair "CONDGEN + CONDJMP". Refer to
26514 "Intel Architectures Optimization Reference Manual". */
26516 static bool
26518 {
26539 {
26544 {
26548 else
26550 }
26551 }
26558 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26559 supported. */
26566 /* No fusion for RIP-relative address. */
26573 ix86_address parts;
26579 }
26584 /* Check whether conditional jump use Sign or Overflow Flags. */
26592 /* Return true for TYPE_TEST and TYPE_ICMP. */
26597 /* The following is the case that macro-fusion for alu + jmp. */
26601 /* No fusion for alu op with memory destination operand. */
26606 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26607 supported. */
26616 }
26618 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26619 execution. It is applied if
26620 (1) IMUL instruction is on the top of list;
26621 (2) There exists the only producer of independent IMUL instruction in
26622 ready list.
26623 Return index of IMUL producer if it was found and -1 otherwise. */
26624 static int
26626 {
26629 sd_iterator_def sd_it;
26630 dep_t dep;
26637 /* Check that IMUL instruction is on the top of ready list. */
26646 /* Search for producer of independent IMUL instruction. */
26648 {
26652 /* Skip IMUL instruction. */
26662 {
26663 rtx con;
26674 {
26675 sd_iterator_def sd_it1;
26676 dep_t dep1;
26677 /* Check if there is no other dependee for IMUL. */
26680 {
26681 rtx pro;
26687 }
26690 }
26691 }
26694 }
26696 }
26698 /* Try to find the best candidate on the top of ready list if two insns
26699 have the same priority - candidate is best if its dependees were
26700 scheduled earlier. Applied for Silvermont only.
26701 Return true if top 2 insns must be interchanged. */
26702 static bool
26704 {
26707 rtx set;
26708 sd_iterator_def sd_it;
26709 dep_t dep;
26712 #define INSN_TICK(INSN) (HID (INSN)->tick)
26733 {
26736 /* Determine winner more precise. */
26738 {
26739 rtx pro;
26745 }
26747 {
26748 rtx pro;
26754 }
26757 {
26758 /* Determine winner - load must win. */
26764 }
26766 }
26768 #undef INSN_TICK
26769 }
26771 /* Perform possible reodering of ready list for Atom/Silvermont only.
26772 Return issue rate. */
26773 static int
26776 {
26783 /* Set up issue rate. */
26786 /* Do reodering for BONNELL/SILVERMONT only. */
26790 /* Nothing to do if ready list contains only 1 instruction. */
26794 /* Do reodering for post-reload scheduler only. */
26799 {
26804 /* Put IMUL producer (ready[index]) at the top of ready list. */
26810 }
26812 /* Skip selective scheduling since HID is not populated in it. */
26816 {
26820 /* Swap 2 top elements of ready list. */
26824 }
26826 }
26828 static bool
26831 /* Returns true if lhs of insn is HW function argument register and set up
26832 is_spilled to true if it is likely spilled HW register. */
26833 static bool
26835 {
26836 rtx dst;
26840 /* Call instructions are not movable, ignore it. */
26851 {
26852 /* Is it likely spilled HW register? */
26857 }
26859 }
26861 /* Add output dependencies for chain of function adjacent arguments if only
26862 there is a move to likely spilled HW register. Return first argument
26863 if at least one dependence was added or NULL otherwise. */
26866 {
26874 /* Find nearest to call argument passing instruction. */
26876 {
26885 }
26889 {
26896 {
26899 }
26901 {
26902 /* Add output depdendence between two function arguments if chain
26903 of output arguments contains likely spilled HW registers. */
26907 }
26908 else
26910 }
26914 }
26916 /* Add output or anti dependency from insn to first_arg to restrict its code
26917 motion. */
26918 static void
26920 {
26921 rtx set;
26922 rtx tmp;
26924 /* Add anti dependencies for bounds stores. */
26929 {
26932 }
26939 {
26940 /* Add output dependency to the first function argument. */
26943 }
26944 /* Add anti dependency. */
26946 }
26948 /* Avoid cross block motion of function argument through adding dependency
26949 from the first non-jump instruction in bb. */
26950 static void
26952 {
26956 {
26958 {
26961 {
26964 }
26965 }
26969 }
26970 }
26972 /* Hook for pre-reload schedule - avoid motion of function arguments
26973 passed in likely spilled HW registers. */
26974 static void
26976 {
26985 {
26988 {
26989 /* Add dependee for first argument to predecessors if only
26990 region contains more than one block. */
26994 /* Skip trivial regions and region head blocks that can have
26995 predecessors outside of region. */
26997 {
26998 edge e;
26999 edge_iterator ei;
27001 /* Regions are SCCs with the exception of selective
27002 scheduling with pipelining of outer blocks enabled.
27003 So also check that immediate predecessors of a non-head
27004 block are in the same region. */
27006 {
27007 /* Avoid creating of loop-carried dependencies through
27008 using topological ordering in the region. */
27012 }
27013 }
27017 }
27018 }
27021 }
27023 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27024 HW registers to maximum, to schedule them at soon as possible. These are
27025 moves from function argument registers at the top of the function entry
27026 and moves from function return value registers after call. */
27027 static int
27029 {
27030 rtx set;
27040 {
27047 }
27050 }
27052 /* Model decoder of Core 2/i7.
27053 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27054 track the instruction fetch block boundaries and make sure that long
27055 (9+ bytes) instructions are assigned to D0. */
27057 /* Maximum length of an insn that can be handled by
27058 a secondary decoder unit. '8' for Core 2/i7. */
27061 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27062 '16' for Core 2/i7. */
27065 /* Maximum number of instructions decoder can handle per cycle.
27066 '6' for Core 2/i7. */
27070 ix86_first_cycle_multipass_data_t;
27072 const_ix86_first_cycle_multipass_data_t;
27074 /* A variable to store target state across calls to max_issue within
27075 one cycle. */
27079 /* Initialize DATA. */
27080 static void
27082 {
27083 ix86_first_cycle_multipass_data_t data
27090 }
27092 /* Advancing the cycle; reset ifetch block counts. */
27093 static void
27095 {
27102 }
27106 /* Filter out insns from ready_try that the core will not be able to issue
27107 on current cycle due to decoder. */
27108 static void
27109 core2i7_first_cycle_multipass_filter_ready_try
27112 {
27114 {
27125 (!first_cycle_insn_p
27127 /* ... or it would not fit into the ifetch block ... */
27129 /* ... or the decoder is full already ... */
27131 /* ... mask the insn out. */
27132 {
27137 }
27138 }
27139 }
27141 /* Prepare for a new round of multipass lookahead scheduling. */
27142 static void
27146 {
27147 ix86_first_cycle_multipass_data_t data
27149 const_ix86_first_cycle_multipass_data_t prev_data
27152 /* Restore the state from the end of the previous round. */
27156 /* Filter instructions that cannot be issued on current cycle due to
27157 decoder restrictions. */
27159 first_cycle_insn_p);
27160 }
27162 /* INSN is being issued in current solution. Account for its impact on
27163 the decoder model. */
27164 static void
27168 {
27169 ix86_first_cycle_multipass_data_t data
27171 const_ix86_first_cycle_multipass_data_t prev_data
27181 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27183 {
27186 }
27188 {
27192 }
27195 /* Filter out insns from ready_try that the core will not be able to issue
27196 on current cycle due to decoder. */
27199 }
27201 /* Revert the effect on ready_try. */
27202 static void
27206 {
27207 const_ix86_first_cycle_multipass_data_t data
27210 sbitmap_iterator sbi;
27214 {
27216 }
27217 }
27219 /* Save the result of multipass lookahead scheduling for the next round. */
27220 static void
27222 {
27223 const_ix86_first_cycle_multipass_data_t data
27225 ix86_first_cycle_multipass_data_t next_data
27229 {
27232 }
27233 }
27235 /* Deallocate target data. */
27236 static void
27238 {
27239 ix86_first_cycle_multipass_data_t data
27243 {
27247 }
27248 }
27250 /* Prepare for scheduling pass. */
27251 static void
27253 {
27254 /* Install scheduling hooks for current CPU. Some of these hooks are used
27255 in time-critical parts of the scheduler, so we only set them up when
27256 they are actually used. */
27258 {
27263 /* Do not perform multipass scheduling for pre-reload schedule
27264 to save compile time. */
27266 {
27282 /* Set decoder parameters. */
27287 }
27288 /* ... Fall through ... */
27298 }
27299 }
27301 \f
27302 /* Compute the alignment given to a constant that is being placed in memory.
27303 EXP is the constant and ALIGN is the alignment that the object would
27304 ordinarily have.
27305 The value of this function is used instead of that alignment to align
27306 the object. */
27308 int
27310 {
27313 {
27318 }
27324 }
27326 /* Compute the alignment for a static variable.
27327 TYPE is the data type, and ALIGN is the alignment that
27328 the object would ordinarily have. The value of this function is used
27329 instead of that alignment to align the object. */
27331 int
27333 {
27334 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27335 for symbols from other compilation units or symbols that don't need
27336 to bind locally. In order to preserve some ABI compatibility with
27337 those compilers, ensure we don't decrease alignment from what we
27338 used to assume. */
27342 /* A data structure, equal or greater than the size of a cache line
27343 (64 bytes in the Pentium 4 and other recent Intel processors, including
27344 processors based on Intel Core microarchitecture) should be aligned
27345 so that its base address is a multiple of a cache line size. */
27347 int max_align
27354 {
27358 }
27364 {
27371 }
27373 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27374 to 16byte boundary. */
27376 {
27383 }
27389 {
27394 }
27396 {
27403 }
27408 {
27413 }
27416 {
27421 }
27424 }
27426 /* Compute the alignment for a local variable or a stack slot. EXP is
27427 the data type or decl itself, MODE is the widest mode available and
27428 ALIGN is the alignment that the object would ordinarily have. The
27429 value of this macro is used instead of that alignment to align the
27430 object. */
27432 unsigned int
27435 {
27439 {
27442 }
27443 else
27444 {
27447 }
27449 /* Don't do dynamic stack realignment for long long objects with
27450 -mpreferred-stack-boundary=2. */
27459 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27460 register in MODE. We will return the largest alignment of XF
27461 and DF. */
27463 {
27467 }
27469 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27470 to 16byte boundary. Exact wording is:
27472 An array uses the same alignment as its elements, except that a local or
27473 global array variable of length at least 16 bytes or
27474 a C99 variable-length array variable always has alignment of at least 16 bytes.
27476 This was added to allow use of aligned SSE instructions at arrays. This
27477 rule is meant for static storage (where compiler can not do the analysis
27478 by itself). We follow it for automatic variables only when convenient.
27479 We fully control everything in the function compiled and functions from
27480 other unit can not rely on the alignment.
27482 Exclude va_list type. It is the common case of local array where
27483 we can not benefit from the alignment.
27485 TODO: Probably one should optimize for size only when var is not escaping. */
27488 {
27498 }
27500 {
27505 }
27507 {
27513 }
27518 {
27523 }
27526 {
27532 }
27534 }
27536 /* Compute the minimum required alignment for dynamic stack realignment
27537 purposes for a local variable, parameter or a stack slot. EXP is
27538 the data type or decl itself, MODE is its mode and ALIGN is the
27539 alignment that the object would ordinarily have. */
27541 unsigned int
27544 {
27548 {
27551 }
27552 else
27553 {
27556 }
27561 /* Don't do dynamic stack realignment for long long objects with
27562 -mpreferred-stack-boundary=2. */
27569 }
27570 \f
27571 /* Find a location for the static chain incoming to a nested function.
27572 This is a register, unless all free registers are used by arguments. */
27574 static rtx
27576 {
27579 /* While this function won't be called by the middle-end when a static
27580 chain isn't needed, it's also used throughout the backend so it's
27581 easiest to keep this check centralized. */
27586 {
27587 /* We always use R10 in 64-bit mode. */
27589 }
27590 else
27591 {
27595 /* By default in 32-bit mode we use ECX to pass the static chain. */
27599 {
27602 }
27603 else
27604 {
27607 }
27611 {
27612 /* Fastcall functions use ecx/edx for arguments, which leaves
27613 us with EAX for the static chain.
27614 Thiscall functions use ecx for arguments, which also
27615 leaves us with EAX for the static chain. */
27617 }
27619 {
27620 /* Thiscall functions use ecx for arguments, which leaves
27621 us with EAX and EDX for the static chain.
27622 We are using for abi-compatibility EAX. */
27624 }
27626 {
27627 /* For regparm 3, we have no free call-clobbered registers in
27628 which to store the static chain. In order to implement this,
27629 we have the trampoline push the static chain to the stack.
27630 However, we can't push a value below the return address when
27631 we call the nested function directly, so we have to use an
27632 alternate entry point. For this we use ESI, and have the
27633 alternate entry point push ESI, so that things appear the
27634 same once we're executing the nested function. */
27636 {
27642 }
27644 }
27645 }
27648 }
27650 /* Emit RTL insns to initialize the variable parts of a trampoline.
27651 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27652 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27653 to be passed to the target function. */
27655 static void
27657 {
27665 {
27668 /* Load the function address to r11. Try to load address using
27669 the shorter movl instead of movabs. We may want to support
27670 movq for kernel mode, but kernel does not use trampolines at
27671 the moment. FNADDR is a 32bit address and may not be in
27672 DImode when ptr_mode == SImode. Always use movl in this
27673 case. */
27676 {
27685 }
27686 else
27687 {
27694 }
27696 /* Load static chain using movabs to r10. Use the shorter movl
27697 instead of movabs when ptr_mode == SImode. */
27699 {
27702 }
27703 else
27704 {
27707 }
27716 /* Jump to r11; the last (unused) byte is a nop, only there to
27717 pad the write out to a single 32-bit store. */
27721 }
27722 else
27723 {
27726 /* Depending on the static chain location, either load a register
27727 with a constant, or push the constant to the stack. All of the
27728 instructions are the same size. */
27731 {
27733 {
27740 }
27741 }
27742 else
27757 /* Compute offset from the end of the jmp to the target function.
27758 In the case in which the trampoline stores the static chain on
27759 the stack, we need to skip the first insn which pushes the
27760 (call-saved) register static chain; this push is 1 byte. */
27767 }
27771 #ifdef HAVE_ENABLE_EXECUTE_STACK
27772 #ifdef CHECK_EXECUTE_STACK_ENABLED
27774 #endif
27777 #endif
27778 }
27779 \f
27780 /* The following file contains several enumerations and data structures
27781 built from the definitions in i386-builtin-types.def. */
27785 /* Table for the ix86 builtin non-function types. */
27788 /* Retrieve an element from the above table, building some of
27789 the types lazily. */
27791 static tree
27793 {
27805 {
27806 machine_mode mode;
27813 }
27814 else
27815 {
27821 else
27829 }
27833 }
27835 /* Table for the ix86 builtin function types. */
27838 /* Retrieve an element from the above table, building some of
27839 the types lazily. */
27841 static tree
27843 {
27844 tree type;
27853 {
27861 {
27864 }
27867 }
27868 else
27869 {
27875 }
27879 }
27882 /* Codes for all the SSE/MMX builtins. */
27883 enum ix86_builtins
27884 {
27885 IX86_BUILTIN_ADDPS,
27886 IX86_BUILTIN_ADDSS,
27887 IX86_BUILTIN_DIVPS,
27888 IX86_BUILTIN_DIVSS,
27889 IX86_BUILTIN_MULPS,
27890 IX86_BUILTIN_MULSS,
27891 IX86_BUILTIN_SUBPS,
27892 IX86_BUILTIN_SUBSS,
27894 IX86_BUILTIN_CMPEQPS,
27895 IX86_BUILTIN_CMPLTPS,
27896 IX86_BUILTIN_CMPLEPS,
27897 IX86_BUILTIN_CMPGTPS,
27898 IX86_BUILTIN_CMPGEPS,
27899 IX86_BUILTIN_CMPNEQPS,
27900 IX86_BUILTIN_CMPNLTPS,
27901 IX86_BUILTIN_CMPNLEPS,
27902 IX86_BUILTIN_CMPNGTPS,
27903 IX86_BUILTIN_CMPNGEPS,
27904 IX86_BUILTIN_CMPORDPS,
27905 IX86_BUILTIN_CMPUNORDPS,
27906 IX86_BUILTIN_CMPEQSS,
27907 IX86_BUILTIN_CMPLTSS,
27908 IX86_BUILTIN_CMPLESS,
27909 IX86_BUILTIN_CMPNEQSS,
27910 IX86_BUILTIN_CMPNLTSS,
27911 IX86_BUILTIN_CMPNLESS,
27912 IX86_BUILTIN_CMPORDSS,
27913 IX86_BUILTIN_CMPUNORDSS,
27915 IX86_BUILTIN_COMIEQSS,
27916 IX86_BUILTIN_COMILTSS,
27917 IX86_BUILTIN_COMILESS,
27918 IX86_BUILTIN_COMIGTSS,
27919 IX86_BUILTIN_COMIGESS,
27920 IX86_BUILTIN_COMINEQSS,
27921 IX86_BUILTIN_UCOMIEQSS,
27922 IX86_BUILTIN_UCOMILTSS,
27923 IX86_BUILTIN_UCOMILESS,
27924 IX86_BUILTIN_UCOMIGTSS,
27925 IX86_BUILTIN_UCOMIGESS,
27926 IX86_BUILTIN_UCOMINEQSS,
27928 IX86_BUILTIN_CVTPI2PS,
27929 IX86_BUILTIN_CVTPS2PI,
27930 IX86_BUILTIN_CVTSI2SS,
27931 IX86_BUILTIN_CVTSI642SS,
27932 IX86_BUILTIN_CVTSS2SI,
27933 IX86_BUILTIN_CVTSS2SI64,
27934 IX86_BUILTIN_CVTTPS2PI,
27935 IX86_BUILTIN_CVTTSS2SI,
27936 IX86_BUILTIN_CVTTSS2SI64,
27938 IX86_BUILTIN_MAXPS,
27939 IX86_BUILTIN_MAXSS,
27940 IX86_BUILTIN_MINPS,
27941 IX86_BUILTIN_MINSS,
27943 IX86_BUILTIN_LOADUPS,
27944 IX86_BUILTIN_STOREUPS,
27945 IX86_BUILTIN_MOVSS,
27947 IX86_BUILTIN_MOVHLPS,
27948 IX86_BUILTIN_MOVLHPS,
27949 IX86_BUILTIN_LOADHPS,
27950 IX86_BUILTIN_LOADLPS,
27951 IX86_BUILTIN_STOREHPS,
27952 IX86_BUILTIN_STORELPS,
27954 IX86_BUILTIN_MASKMOVQ,
27955 IX86_BUILTIN_MOVMSKPS,
27956 IX86_BUILTIN_PMOVMSKB,
27958 IX86_BUILTIN_MOVNTPS,
27959 IX86_BUILTIN_MOVNTQ,
27961 IX86_BUILTIN_LOADDQU,
27962 IX86_BUILTIN_STOREDQU,
27964 IX86_BUILTIN_PACKSSWB,
27965 IX86_BUILTIN_PACKSSDW,
27966 IX86_BUILTIN_PACKUSWB,
27968 IX86_BUILTIN_PADDB,
27969 IX86_BUILTIN_PADDW,
27970 IX86_BUILTIN_PADDD,
27971 IX86_BUILTIN_PADDQ,
27972 IX86_BUILTIN_PADDSB,
27973 IX86_BUILTIN_PADDSW,
27974 IX86_BUILTIN_PADDUSB,
27975 IX86_BUILTIN_PADDUSW,
27976 IX86_BUILTIN_PSUBB,
27977 IX86_BUILTIN_PSUBW,
27978 IX86_BUILTIN_PSUBD,
27979 IX86_BUILTIN_PSUBQ,
27980 IX86_BUILTIN_PSUBSB,
27981 IX86_BUILTIN_PSUBSW,
27982 IX86_BUILTIN_PSUBUSB,
27983 IX86_BUILTIN_PSUBUSW,
27985 IX86_BUILTIN_PAND,
27986 IX86_BUILTIN_PANDN,
27987 IX86_BUILTIN_POR,
27988 IX86_BUILTIN_PXOR,
27990 IX86_BUILTIN_PAVGB,
27991 IX86_BUILTIN_PAVGW,
27993 IX86_BUILTIN_PCMPEQB,
27994 IX86_BUILTIN_PCMPEQW,
27995 IX86_BUILTIN_PCMPEQD,
27996 IX86_BUILTIN_PCMPGTB,
27997 IX86_BUILTIN_PCMPGTW,
27998 IX86_BUILTIN_PCMPGTD,
28000 IX86_BUILTIN_PMADDWD,
28002 IX86_BUILTIN_PMAXSW,
28003 IX86_BUILTIN_PMAXUB,
28004 IX86_BUILTIN_PMINSW,
28005 IX86_BUILTIN_PMINUB,
28007 IX86_BUILTIN_PMULHUW,
28008 IX86_BUILTIN_PMULHW,
28009 IX86_BUILTIN_PMULLW,
28011 IX86_BUILTIN_PSADBW,
28012 IX86_BUILTIN_PSHUFW,
28014 IX86_BUILTIN_PSLLW,
28015 IX86_BUILTIN_PSLLD,
28016 IX86_BUILTIN_PSLLQ,
28017 IX86_BUILTIN_PSRAW,
28018 IX86_BUILTIN_PSRAD,
28019 IX86_BUILTIN_PSRLW,
28020 IX86_BUILTIN_PSRLD,
28021 IX86_BUILTIN_PSRLQ,
28022 IX86_BUILTIN_PSLLWI,
28023 IX86_BUILTIN_PSLLDI,
28024 IX86_BUILTIN_PSLLQI,
28025 IX86_BUILTIN_PSRAWI,
28026 IX86_BUILTIN_PSRADI,
28027 IX86_BUILTIN_PSRLWI,
28028 IX86_BUILTIN_PSRLDI,
28029 IX86_BUILTIN_PSRLQI,
28031 IX86_BUILTIN_PUNPCKHBW,
28032 IX86_BUILTIN_PUNPCKHWD,
28033 IX86_BUILTIN_PUNPCKHDQ,
28034 IX86_BUILTIN_PUNPCKLBW,
28035 IX86_BUILTIN_PUNPCKLWD,
28036 IX86_BUILTIN_PUNPCKLDQ,
28038 IX86_BUILTIN_SHUFPS,
28040 IX86_BUILTIN_RCPPS,
28041 IX86_BUILTIN_RCPSS,
28042 IX86_BUILTIN_RSQRTPS,
28043 IX86_BUILTIN_RSQRTPS_NR,
28044 IX86_BUILTIN_RSQRTSS,
28045 IX86_BUILTIN_RSQRTF,
28046 IX86_BUILTIN_SQRTPS,
28047 IX86_BUILTIN_SQRTPS_NR,
28048 IX86_BUILTIN_SQRTSS,
28050 IX86_BUILTIN_UNPCKHPS,
28051 IX86_BUILTIN_UNPCKLPS,
28053 IX86_BUILTIN_ANDPS,
28054 IX86_BUILTIN_ANDNPS,
28055 IX86_BUILTIN_ORPS,
28056 IX86_BUILTIN_XORPS,
28058 IX86_BUILTIN_EMMS,
28059 IX86_BUILTIN_LDMXCSR,
28060 IX86_BUILTIN_STMXCSR,
28061 IX86_BUILTIN_SFENCE,
28063 IX86_BUILTIN_FXSAVE,
28064 IX86_BUILTIN_FXRSTOR,
28065 IX86_BUILTIN_FXSAVE64,
28066 IX86_BUILTIN_FXRSTOR64,
28068 IX86_BUILTIN_XSAVE,
28069 IX86_BUILTIN_XRSTOR,
28070 IX86_BUILTIN_XSAVE64,
28071 IX86_BUILTIN_XRSTOR64,
28073 IX86_BUILTIN_XSAVEOPT,
28074 IX86_BUILTIN_XSAVEOPT64,
28076 IX86_BUILTIN_XSAVEC,
28077 IX86_BUILTIN_XSAVEC64,
28079 IX86_BUILTIN_XSAVES,
28080 IX86_BUILTIN_XRSTORS,
28081 IX86_BUILTIN_XSAVES64,
28082 IX86_BUILTIN_XRSTORS64,
28084 /* 3DNow! Original */
28085 IX86_BUILTIN_FEMMS,
28086 IX86_BUILTIN_PAVGUSB,
28087 IX86_BUILTIN_PF2ID,
28088 IX86_BUILTIN_PFACC,
28089 IX86_BUILTIN_PFADD,
28090 IX86_BUILTIN_PFCMPEQ,
28091 IX86_BUILTIN_PFCMPGE,
28092 IX86_BUILTIN_PFCMPGT,
28093 IX86_BUILTIN_PFMAX,
28094 IX86_BUILTIN_PFMIN,
28095 IX86_BUILTIN_PFMUL,
28096 IX86_BUILTIN_PFRCP,
28097 IX86_BUILTIN_PFRCPIT1,
28098 IX86_BUILTIN_PFRCPIT2,
28099 IX86_BUILTIN_PFRSQIT1,
28100 IX86_BUILTIN_PFRSQRT,
28101 IX86_BUILTIN_PFSUB,
28102 IX86_BUILTIN_PFSUBR,
28103 IX86_BUILTIN_PI2FD,
28104 IX86_BUILTIN_PMULHRW,
28106 /* 3DNow! Athlon Extensions */
28107 IX86_BUILTIN_PF2IW,
28108 IX86_BUILTIN_PFNACC,
28109 IX86_BUILTIN_PFPNACC,
28110 IX86_BUILTIN_PI2FW,
28111 IX86_BUILTIN_PSWAPDSI,
28112 IX86_BUILTIN_PSWAPDSF,
28114 /* SSE2 */
28115 IX86_BUILTIN_ADDPD,
28116 IX86_BUILTIN_ADDSD,
28117 IX86_BUILTIN_DIVPD,
28118 IX86_BUILTIN_DIVSD,
28119 IX86_BUILTIN_MULPD,
28120 IX86_BUILTIN_MULSD,
28121 IX86_BUILTIN_SUBPD,
28122 IX86_BUILTIN_SUBSD,
28124 IX86_BUILTIN_CMPEQPD,
28125 IX86_BUILTIN_CMPLTPD,
28126 IX86_BUILTIN_CMPLEPD,
28127 IX86_BUILTIN_CMPGTPD,
28128 IX86_BUILTIN_CMPGEPD,
28129 IX86_BUILTIN_CMPNEQPD,
28130 IX86_BUILTIN_CMPNLTPD,
28131 IX86_BUILTIN_CMPNLEPD,
28132 IX86_BUILTIN_CMPNGTPD,
28133 IX86_BUILTIN_CMPNGEPD,
28134 IX86_BUILTIN_CMPORDPD,
28135 IX86_BUILTIN_CMPUNORDPD,
28136 IX86_BUILTIN_CMPEQSD,
28137 IX86_BUILTIN_CMPLTSD,
28138 IX86_BUILTIN_CMPLESD,
28139 IX86_BUILTIN_CMPNEQSD,
28140 IX86_BUILTIN_CMPNLTSD,
28141 IX86_BUILTIN_CMPNLESD,
28142 IX86_BUILTIN_CMPORDSD,
28143 IX86_BUILTIN_CMPUNORDSD,
28145 IX86_BUILTIN_COMIEQSD,
28146 IX86_BUILTIN_COMILTSD,
28147 IX86_BUILTIN_COMILESD,
28148 IX86_BUILTIN_COMIGTSD,
28149 IX86_BUILTIN_COMIGESD,
28150 IX86_BUILTIN_COMINEQSD,
28151 IX86_BUILTIN_UCOMIEQSD,
28152 IX86_BUILTIN_UCOMILTSD,
28153 IX86_BUILTIN_UCOMILESD,
28154 IX86_BUILTIN_UCOMIGTSD,
28155 IX86_BUILTIN_UCOMIGESD,
28156 IX86_BUILTIN_UCOMINEQSD,
28158 IX86_BUILTIN_MAXPD,
28159 IX86_BUILTIN_MAXSD,
28160 IX86_BUILTIN_MINPD,
28161 IX86_BUILTIN_MINSD,
28163 IX86_BUILTIN_ANDPD,
28164 IX86_BUILTIN_ANDNPD,
28165 IX86_BUILTIN_ORPD,
28166 IX86_BUILTIN_XORPD,
28168 IX86_BUILTIN_SQRTPD,
28169 IX86_BUILTIN_SQRTSD,
28171 IX86_BUILTIN_UNPCKHPD,
28172 IX86_BUILTIN_UNPCKLPD,
28174 IX86_BUILTIN_SHUFPD,
28176 IX86_BUILTIN_LOADUPD,
28177 IX86_BUILTIN_STOREUPD,
28178 IX86_BUILTIN_MOVSD,
28180 IX86_BUILTIN_LOADHPD,
28181 IX86_BUILTIN_LOADLPD,
28183 IX86_BUILTIN_CVTDQ2PD,
28184 IX86_BUILTIN_CVTDQ2PS,
28186 IX86_BUILTIN_CVTPD2DQ,
28187 IX86_BUILTIN_CVTPD2PI,
28188 IX86_BUILTIN_CVTPD2PS,
28189 IX86_BUILTIN_CVTTPD2DQ,
28190 IX86_BUILTIN_CVTTPD2PI,
28192 IX86_BUILTIN_CVTPI2PD,
28193 IX86_BUILTIN_CVTSI2SD,
28194 IX86_BUILTIN_CVTSI642SD,
28196 IX86_BUILTIN_CVTSD2SI,
28197 IX86_BUILTIN_CVTSD2SI64,
28198 IX86_BUILTIN_CVTSD2SS,
28199 IX86_BUILTIN_CVTSS2SD,
28200 IX86_BUILTIN_CVTTSD2SI,
28201 IX86_BUILTIN_CVTTSD2SI64,
28203 IX86_BUILTIN_CVTPS2DQ,
28204 IX86_BUILTIN_CVTPS2PD,
28205 IX86_BUILTIN_CVTTPS2DQ,
28207 IX86_BUILTIN_MOVNTI,
28208 IX86_BUILTIN_MOVNTI64,
28209 IX86_BUILTIN_MOVNTPD,
28210 IX86_BUILTIN_MOVNTDQ,
28212 IX86_BUILTIN_MOVQ128,
28214 /* SSE2 MMX */
28215 IX86_BUILTIN_MASKMOVDQU,
28216 IX86_BUILTIN_MOVMSKPD,
28217 IX86_BUILTIN_PMOVMSKB128,
28219 IX86_BUILTIN_PACKSSWB128,
28220 IX86_BUILTIN_PACKSSDW128,
28221 IX86_BUILTIN_PACKUSWB128,
28223 IX86_BUILTIN_PADDB128,
28224 IX86_BUILTIN_PADDW128,
28225 IX86_BUILTIN_PADDD128,
28226 IX86_BUILTIN_PADDQ128,
28227 IX86_BUILTIN_PADDSB128,
28228 IX86_BUILTIN_PADDSW128,
28229 IX86_BUILTIN_PADDUSB128,
28230 IX86_BUILTIN_PADDUSW128,
28231 IX86_BUILTIN_PSUBB128,
28232 IX86_BUILTIN_PSUBW128,
28233 IX86_BUILTIN_PSUBD128,
28234 IX86_BUILTIN_PSUBQ128,
28235 IX86_BUILTIN_PSUBSB128,
28236 IX86_BUILTIN_PSUBSW128,
28237 IX86_BUILTIN_PSUBUSB128,
28238 IX86_BUILTIN_PSUBUSW128,
28240 IX86_BUILTIN_PAND128,
28241 IX86_BUILTIN_PANDN128,
28242 IX86_BUILTIN_POR128,
28243 IX86_BUILTIN_PXOR128,
28245 IX86_BUILTIN_PAVGB128,
28246 IX86_BUILTIN_PAVGW128,
28248 IX86_BUILTIN_PCMPEQB128,
28249 IX86_BUILTIN_PCMPEQW128,
28250 IX86_BUILTIN_PCMPEQD128,
28251 IX86_BUILTIN_PCMPGTB128,
28252 IX86_BUILTIN_PCMPGTW128,
28253 IX86_BUILTIN_PCMPGTD128,
28255 IX86_BUILTIN_PMADDWD128,
28257 IX86_BUILTIN_PMAXSW128,
28258 IX86_BUILTIN_PMAXUB128,
28259 IX86_BUILTIN_PMINSW128,
28260 IX86_BUILTIN_PMINUB128,
28262 IX86_BUILTIN_PMULUDQ,
28263 IX86_BUILTIN_PMULUDQ128,
28264 IX86_BUILTIN_PMULHUW128,
28265 IX86_BUILTIN_PMULHW128,
28266 IX86_BUILTIN_PMULLW128,
28268 IX86_BUILTIN_PSADBW128,
28269 IX86_BUILTIN_PSHUFHW,
28270 IX86_BUILTIN_PSHUFLW,
28271 IX86_BUILTIN_PSHUFD,
28273 IX86_BUILTIN_PSLLDQI128,
28274 IX86_BUILTIN_PSLLWI128,
28275 IX86_BUILTIN_PSLLDI128,
28276 IX86_BUILTIN_PSLLQI128,
28277 IX86_BUILTIN_PSRAWI128,
28278 IX86_BUILTIN_PSRADI128,
28279 IX86_BUILTIN_PSRLDQI128,
28280 IX86_BUILTIN_PSRLWI128,
28281 IX86_BUILTIN_PSRLDI128,
28282 IX86_BUILTIN_PSRLQI128,
28284 IX86_BUILTIN_PSLLDQ128,
28285 IX86_BUILTIN_PSLLW128,
28286 IX86_BUILTIN_PSLLD128,
28287 IX86_BUILTIN_PSLLQ128,
28288 IX86_BUILTIN_PSRAW128,
28289 IX86_BUILTIN_PSRAD128,
28290 IX86_BUILTIN_PSRLW128,
28291 IX86_BUILTIN_PSRLD128,
28292 IX86_BUILTIN_PSRLQ128,
28294 IX86_BUILTIN_PUNPCKHBW128,
28295 IX86_BUILTIN_PUNPCKHWD128,
28296 IX86_BUILTIN_PUNPCKHDQ128,
28297 IX86_BUILTIN_PUNPCKHQDQ128,
28298 IX86_BUILTIN_PUNPCKLBW128,
28299 IX86_BUILTIN_PUNPCKLWD128,
28300 IX86_BUILTIN_PUNPCKLDQ128,
28301 IX86_BUILTIN_PUNPCKLQDQ128,
28303 IX86_BUILTIN_CLFLUSH,
28304 IX86_BUILTIN_MFENCE,
28305 IX86_BUILTIN_LFENCE,
28306 IX86_BUILTIN_PAUSE,
28308 IX86_BUILTIN_FNSTENV,
28309 IX86_BUILTIN_FLDENV,
28310 IX86_BUILTIN_FNSTSW,
28311 IX86_BUILTIN_FNCLEX,
28313 IX86_BUILTIN_BSRSI,
28314 IX86_BUILTIN_BSRDI,
28315 IX86_BUILTIN_RDPMC,
28316 IX86_BUILTIN_RDTSC,
28317 IX86_BUILTIN_RDTSCP,
28318 IX86_BUILTIN_ROLQI,
28319 IX86_BUILTIN_ROLHI,
28320 IX86_BUILTIN_RORQI,
28321 IX86_BUILTIN_RORHI,
28323 /* SSE3. */
28324 IX86_BUILTIN_ADDSUBPS,
28325 IX86_BUILTIN_HADDPS,
28326 IX86_BUILTIN_HSUBPS,
28327 IX86_BUILTIN_MOVSHDUP,
28328 IX86_BUILTIN_MOVSLDUP,
28329 IX86_BUILTIN_ADDSUBPD,
28330 IX86_BUILTIN_HADDPD,
28331 IX86_BUILTIN_HSUBPD,
28332 IX86_BUILTIN_LDDQU,
28334 IX86_BUILTIN_MONITOR,
28335 IX86_BUILTIN_MWAIT,
28337 /* SSSE3. */
28338 IX86_BUILTIN_PHADDW,
28339 IX86_BUILTIN_PHADDD,
28340 IX86_BUILTIN_PHADDSW,
28341 IX86_BUILTIN_PHSUBW,
28342 IX86_BUILTIN_PHSUBD,
28343 IX86_BUILTIN_PHSUBSW,
28344 IX86_BUILTIN_PMADDUBSW,
28345 IX86_BUILTIN_PMULHRSW,
28346 IX86_BUILTIN_PSHUFB,
28347 IX86_BUILTIN_PSIGNB,
28348 IX86_BUILTIN_PSIGNW,
28349 IX86_BUILTIN_PSIGND,
28350 IX86_BUILTIN_PALIGNR,
28351 IX86_BUILTIN_PABSB,
28352 IX86_BUILTIN_PABSW,
28353 IX86_BUILTIN_PABSD,
28355 IX86_BUILTIN_PHADDW128,
28356 IX86_BUILTIN_PHADDD128,
28357 IX86_BUILTIN_PHADDSW128,
28358 IX86_BUILTIN_PHSUBW128,
28359 IX86_BUILTIN_PHSUBD128,
28360 IX86_BUILTIN_PHSUBSW128,
28361 IX86_BUILTIN_PMADDUBSW128,
28362 IX86_BUILTIN_PMULHRSW128,
28363 IX86_BUILTIN_PSHUFB128,
28364 IX86_BUILTIN_PSIGNB128,
28365 IX86_BUILTIN_PSIGNW128,
28366 IX86_BUILTIN_PSIGND128,
28367 IX86_BUILTIN_PALIGNR128,
28368 IX86_BUILTIN_PABSB128,
28369 IX86_BUILTIN_PABSW128,
28370 IX86_BUILTIN_PABSD128,
28372 /* AMDFAM10 - SSE4A New Instructions. */
28373 IX86_BUILTIN_MOVNTSD,
28374 IX86_BUILTIN_MOVNTSS,
28375 IX86_BUILTIN_EXTRQI,
28376 IX86_BUILTIN_EXTRQ,
28377 IX86_BUILTIN_INSERTQI,
28378 IX86_BUILTIN_INSERTQ,
28380 /* SSE4.1. */
28381 IX86_BUILTIN_BLENDPD,
28382 IX86_BUILTIN_BLENDPS,
28383 IX86_BUILTIN_BLENDVPD,
28384 IX86_BUILTIN_BLENDVPS,
28385 IX86_BUILTIN_PBLENDVB128,
28386 IX86_BUILTIN_PBLENDW128,
28388 IX86_BUILTIN_DPPD,
28389 IX86_BUILTIN_DPPS,
28391 IX86_BUILTIN_INSERTPS128,
28393 IX86_BUILTIN_MOVNTDQA,
28394 IX86_BUILTIN_MPSADBW128,
28395 IX86_BUILTIN_PACKUSDW128,
28396 IX86_BUILTIN_PCMPEQQ,
28397 IX86_BUILTIN_PHMINPOSUW128,
28399 IX86_BUILTIN_PMAXSB128,
28400 IX86_BUILTIN_PMAXSD128,
28401 IX86_BUILTIN_PMAXUD128,
28402 IX86_BUILTIN_PMAXUW128,
28404 IX86_BUILTIN_PMINSB128,
28405 IX86_BUILTIN_PMINSD128,
28406 IX86_BUILTIN_PMINUD128,
28407 IX86_BUILTIN_PMINUW128,
28409 IX86_BUILTIN_PMOVSXBW128,
28410 IX86_BUILTIN_PMOVSXBD128,
28411 IX86_BUILTIN_PMOVSXBQ128,
28412 IX86_BUILTIN_PMOVSXWD128,
28413 IX86_BUILTIN_PMOVSXWQ128,
28414 IX86_BUILTIN_PMOVSXDQ128,
28416 IX86_BUILTIN_PMOVZXBW128,
28417 IX86_BUILTIN_PMOVZXBD128,
28418 IX86_BUILTIN_PMOVZXBQ128,
28419 IX86_BUILTIN_PMOVZXWD128,
28420 IX86_BUILTIN_PMOVZXWQ128,
28421 IX86_BUILTIN_PMOVZXDQ128,
28423 IX86_BUILTIN_PMULDQ128,
28424 IX86_BUILTIN_PMULLD128,
28426 IX86_BUILTIN_ROUNDSD,
28427 IX86_BUILTIN_ROUNDSS,
28429 IX86_BUILTIN_ROUNDPD,
28430 IX86_BUILTIN_ROUNDPS,
28432 IX86_BUILTIN_FLOORPD,
28433 IX86_BUILTIN_CEILPD,
28434 IX86_BUILTIN_TRUNCPD,
28435 IX86_BUILTIN_RINTPD,
28436 IX86_BUILTIN_ROUNDPD_AZ,
28438 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28439 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28440 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28442 IX86_BUILTIN_FLOORPS,
28443 IX86_BUILTIN_CEILPS,
28444 IX86_BUILTIN_TRUNCPS,
28445 IX86_BUILTIN_RINTPS,
28446 IX86_BUILTIN_ROUNDPS_AZ,
28448 IX86_BUILTIN_FLOORPS_SFIX,
28449 IX86_BUILTIN_CEILPS_SFIX,
28450 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28452 IX86_BUILTIN_PTESTZ,
28453 IX86_BUILTIN_PTESTC,
28454 IX86_BUILTIN_PTESTNZC,
28456 IX86_BUILTIN_VEC_INIT_V2SI,
28457 IX86_BUILTIN_VEC_INIT_V4HI,
28458 IX86_BUILTIN_VEC_INIT_V8QI,
28459 IX86_BUILTIN_VEC_EXT_V2DF,
28460 IX86_BUILTIN_VEC_EXT_V2DI,
28461 IX86_BUILTIN_VEC_EXT_V4SF,
28462 IX86_BUILTIN_VEC_EXT_V4SI,
28463 IX86_BUILTIN_VEC_EXT_V8HI,
28464 IX86_BUILTIN_VEC_EXT_V2SI,
28465 IX86_BUILTIN_VEC_EXT_V4HI,
28466 IX86_BUILTIN_VEC_EXT_V16QI,
28467 IX86_BUILTIN_VEC_SET_V2DI,
28468 IX86_BUILTIN_VEC_SET_V4SF,
28469 IX86_BUILTIN_VEC_SET_V4SI,
28470 IX86_BUILTIN_VEC_SET_V8HI,
28471 IX86_BUILTIN_VEC_SET_V4HI,
28472 IX86_BUILTIN_VEC_SET_V16QI,
28474 IX86_BUILTIN_VEC_PACK_SFIX,
28475 IX86_BUILTIN_VEC_PACK_SFIX256,
28477 /* SSE4.2. */
28478 IX86_BUILTIN_CRC32QI,
28479 IX86_BUILTIN_CRC32HI,
28480 IX86_BUILTIN_CRC32SI,
28481 IX86_BUILTIN_CRC32DI,
28483 IX86_BUILTIN_PCMPESTRI128,
28484 IX86_BUILTIN_PCMPESTRM128,
28485 IX86_BUILTIN_PCMPESTRA128,
28486 IX86_BUILTIN_PCMPESTRC128,
28487 IX86_BUILTIN_PCMPESTRO128,
28488 IX86_BUILTIN_PCMPESTRS128,
28489 IX86_BUILTIN_PCMPESTRZ128,
28490 IX86_BUILTIN_PCMPISTRI128,
28491 IX86_BUILTIN_PCMPISTRM128,
28492 IX86_BUILTIN_PCMPISTRA128,
28493 IX86_BUILTIN_PCMPISTRC128,
28494 IX86_BUILTIN_PCMPISTRO128,
28495 IX86_BUILTIN_PCMPISTRS128,
28496 IX86_BUILTIN_PCMPISTRZ128,
28498 IX86_BUILTIN_PCMPGTQ,
28500 /* AES instructions */
28501 IX86_BUILTIN_AESENC128,
28502 IX86_BUILTIN_AESENCLAST128,
28503 IX86_BUILTIN_AESDEC128,
28504 IX86_BUILTIN_AESDECLAST128,
28505 IX86_BUILTIN_AESIMC128,
28506 IX86_BUILTIN_AESKEYGENASSIST128,
28508 /* PCLMUL instruction */
28509 IX86_BUILTIN_PCLMULQDQ128,
28511 /* AVX */
28512 IX86_BUILTIN_ADDPD256,
28513 IX86_BUILTIN_ADDPS256,
28514 IX86_BUILTIN_ADDSUBPD256,
28515 IX86_BUILTIN_ADDSUBPS256,
28516 IX86_BUILTIN_ANDPD256,
28517 IX86_BUILTIN_ANDPS256,
28518 IX86_BUILTIN_ANDNPD256,
28519 IX86_BUILTIN_ANDNPS256,
28520 IX86_BUILTIN_BLENDPD256,
28521 IX86_BUILTIN_BLENDPS256,
28522 IX86_BUILTIN_BLENDVPD256,
28523 IX86_BUILTIN_BLENDVPS256,
28524 IX86_BUILTIN_DIVPD256,
28525 IX86_BUILTIN_DIVPS256,
28526 IX86_BUILTIN_DPPS256,
28527 IX86_BUILTIN_HADDPD256,
28528 IX86_BUILTIN_HADDPS256,
28529 IX86_BUILTIN_HSUBPD256,
28530 IX86_BUILTIN_HSUBPS256,
28531 IX86_BUILTIN_MAXPD256,
28532 IX86_BUILTIN_MAXPS256,
28533 IX86_BUILTIN_MINPD256,
28534 IX86_BUILTIN_MINPS256,
28535 IX86_BUILTIN_MULPD256,
28536 IX86_BUILTIN_MULPS256,
28537 IX86_BUILTIN_ORPD256,
28538 IX86_BUILTIN_ORPS256,
28539 IX86_BUILTIN_SHUFPD256,
28540 IX86_BUILTIN_SHUFPS256,
28541 IX86_BUILTIN_SUBPD256,
28542 IX86_BUILTIN_SUBPS256,
28543 IX86_BUILTIN_XORPD256,
28544 IX86_BUILTIN_XORPS256,
28545 IX86_BUILTIN_CMPSD,
28546 IX86_BUILTIN_CMPSS,
28547 IX86_BUILTIN_CMPPD,
28548 IX86_BUILTIN_CMPPS,
28549 IX86_BUILTIN_CMPPD256,
28550 IX86_BUILTIN_CMPPS256,
28551 IX86_BUILTIN_CVTDQ2PD256,
28552 IX86_BUILTIN_CVTDQ2PS256,
28553 IX86_BUILTIN_CVTPD2PS256,
28554 IX86_BUILTIN_CVTPS2DQ256,
28555 IX86_BUILTIN_CVTPS2PD256,
28556 IX86_BUILTIN_CVTTPD2DQ256,
28557 IX86_BUILTIN_CVTPD2DQ256,
28558 IX86_BUILTIN_CVTTPS2DQ256,
28559 IX86_BUILTIN_EXTRACTF128PD256,
28560 IX86_BUILTIN_EXTRACTF128PS256,
28561 IX86_BUILTIN_EXTRACTF128SI256,
28562 IX86_BUILTIN_VZEROALL,
28563 IX86_BUILTIN_VZEROUPPER,
28564 IX86_BUILTIN_VPERMILVARPD,
28565 IX86_BUILTIN_VPERMILVARPS,
28566 IX86_BUILTIN_VPERMILVARPD256,
28567 IX86_BUILTIN_VPERMILVARPS256,
28568 IX86_BUILTIN_VPERMILPD,
28569 IX86_BUILTIN_VPERMILPS,
28570 IX86_BUILTIN_VPERMILPD256,
28571 IX86_BUILTIN_VPERMILPS256,
28572 IX86_BUILTIN_VPERMIL2PD,
28573 IX86_BUILTIN_VPERMIL2PS,
28574 IX86_BUILTIN_VPERMIL2PD256,
28575 IX86_BUILTIN_VPERMIL2PS256,
28576 IX86_BUILTIN_VPERM2F128PD256,
28577 IX86_BUILTIN_VPERM2F128PS256,
28578 IX86_BUILTIN_VPERM2F128SI256,
28579 IX86_BUILTIN_VBROADCASTSS,
28580 IX86_BUILTIN_VBROADCASTSD256,
28581 IX86_BUILTIN_VBROADCASTSS256,
28582 IX86_BUILTIN_VBROADCASTPD256,
28583 IX86_BUILTIN_VBROADCASTPS256,
28584 IX86_BUILTIN_VINSERTF128PD256,
28585 IX86_BUILTIN_VINSERTF128PS256,
28586 IX86_BUILTIN_VINSERTF128SI256,
28587 IX86_BUILTIN_LOADUPD256,
28588 IX86_BUILTIN_LOADUPS256,
28589 IX86_BUILTIN_STOREUPD256,
28590 IX86_BUILTIN_STOREUPS256,
28591 IX86_BUILTIN_LDDQU256,
28592 IX86_BUILTIN_MOVNTDQ256,
28593 IX86_BUILTIN_MOVNTPD256,
28594 IX86_BUILTIN_MOVNTPS256,
28595 IX86_BUILTIN_LOADDQU256,
28596 IX86_BUILTIN_STOREDQU256,
28597 IX86_BUILTIN_MASKLOADPD,
28598 IX86_BUILTIN_MASKLOADPS,
28599 IX86_BUILTIN_MASKSTOREPD,
28600 IX86_BUILTIN_MASKSTOREPS,
28601 IX86_BUILTIN_MASKLOADPD256,
28602 IX86_BUILTIN_MASKLOADPS256,
28603 IX86_BUILTIN_MASKSTOREPD256,
28604 IX86_BUILTIN_MASKSTOREPS256,
28605 IX86_BUILTIN_MOVSHDUP256,
28606 IX86_BUILTIN_MOVSLDUP256,
28607 IX86_BUILTIN_MOVDDUP256,
28609 IX86_BUILTIN_SQRTPD256,
28610 IX86_BUILTIN_SQRTPS256,
28611 IX86_BUILTIN_SQRTPS_NR256,
28612 IX86_BUILTIN_RSQRTPS256,
28613 IX86_BUILTIN_RSQRTPS_NR256,
28615 IX86_BUILTIN_RCPPS256,
28617 IX86_BUILTIN_ROUNDPD256,
28618 IX86_BUILTIN_ROUNDPS256,
28620 IX86_BUILTIN_FLOORPD256,
28621 IX86_BUILTIN_CEILPD256,
28622 IX86_BUILTIN_TRUNCPD256,
28623 IX86_BUILTIN_RINTPD256,
28624 IX86_BUILTIN_ROUNDPD_AZ256,
28626 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28627 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28628 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28630 IX86_BUILTIN_FLOORPS256,
28631 IX86_BUILTIN_CEILPS256,
28632 IX86_BUILTIN_TRUNCPS256,
28633 IX86_BUILTIN_RINTPS256,
28634 IX86_BUILTIN_ROUNDPS_AZ256,
28636 IX86_BUILTIN_FLOORPS_SFIX256,
28637 IX86_BUILTIN_CEILPS_SFIX256,
28638 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28640 IX86_BUILTIN_UNPCKHPD256,
28641 IX86_BUILTIN_UNPCKLPD256,
28642 IX86_BUILTIN_UNPCKHPS256,
28643 IX86_BUILTIN_UNPCKLPS256,
28645 IX86_BUILTIN_SI256_SI,
28646 IX86_BUILTIN_PS256_PS,
28647 IX86_BUILTIN_PD256_PD,
28648 IX86_BUILTIN_SI_SI256,
28649 IX86_BUILTIN_PS_PS256,
28650 IX86_BUILTIN_PD_PD256,
28652 IX86_BUILTIN_VTESTZPD,
28653 IX86_BUILTIN_VTESTCPD,
28654 IX86_BUILTIN_VTESTNZCPD,
28655 IX86_BUILTIN_VTESTZPS,
28656 IX86_BUILTIN_VTESTCPS,
28657 IX86_BUILTIN_VTESTNZCPS,
28658 IX86_BUILTIN_VTESTZPD256,
28659 IX86_BUILTIN_VTESTCPD256,
28660 IX86_BUILTIN_VTESTNZCPD256,
28661 IX86_BUILTIN_VTESTZPS256,
28662 IX86_BUILTIN_VTESTCPS256,
28663 IX86_BUILTIN_VTESTNZCPS256,
28664 IX86_BUILTIN_PTESTZ256,
28665 IX86_BUILTIN_PTESTC256,
28666 IX86_BUILTIN_PTESTNZC256,
28668 IX86_BUILTIN_MOVMSKPD256,
28669 IX86_BUILTIN_MOVMSKPS256,
28671 /* AVX2 */
28672 IX86_BUILTIN_MPSADBW256,
28673 IX86_BUILTIN_PABSB256,
28674 IX86_BUILTIN_PABSW256,
28675 IX86_BUILTIN_PABSD256,
28676 IX86_BUILTIN_PACKSSDW256,
28677 IX86_BUILTIN_PACKSSWB256,
28678 IX86_BUILTIN_PACKUSDW256,
28679 IX86_BUILTIN_PACKUSWB256,
28680 IX86_BUILTIN_PADDB256,
28681 IX86_BUILTIN_PADDW256,
28682 IX86_BUILTIN_PADDD256,
28683 IX86_BUILTIN_PADDQ256,
28684 IX86_BUILTIN_PADDSB256,
28685 IX86_BUILTIN_PADDSW256,
28686 IX86_BUILTIN_PADDUSB256,
28687 IX86_BUILTIN_PADDUSW256,
28688 IX86_BUILTIN_PALIGNR256,
28689 IX86_BUILTIN_AND256I,
28690 IX86_BUILTIN_ANDNOT256I,
28691 IX86_BUILTIN_PAVGB256,
28692 IX86_BUILTIN_PAVGW256,
28693 IX86_BUILTIN_PBLENDVB256,
28694 IX86_BUILTIN_PBLENDVW256,
28695 IX86_BUILTIN_PCMPEQB256,
28696 IX86_BUILTIN_PCMPEQW256,
28697 IX86_BUILTIN_PCMPEQD256,
28698 IX86_BUILTIN_PCMPEQQ256,
28699 IX86_BUILTIN_PCMPGTB256,
28700 IX86_BUILTIN_PCMPGTW256,
28701 IX86_BUILTIN_PCMPGTD256,
28702 IX86_BUILTIN_PCMPGTQ256,
28703 IX86_BUILTIN_PHADDW256,
28704 IX86_BUILTIN_PHADDD256,
28705 IX86_BUILTIN_PHADDSW256,
28706 IX86_BUILTIN_PHSUBW256,
28707 IX86_BUILTIN_PHSUBD256,
28708 IX86_BUILTIN_PHSUBSW256,
28709 IX86_BUILTIN_PMADDUBSW256,
28710 IX86_BUILTIN_PMADDWD256,
28711 IX86_BUILTIN_PMAXSB256,
28712 IX86_BUILTIN_PMAXSW256,
28713 IX86_BUILTIN_PMAXSD256,
28714 IX86_BUILTIN_PMAXUB256,
28715 IX86_BUILTIN_PMAXUW256,
28716 IX86_BUILTIN_PMAXUD256,
28717 IX86_BUILTIN_PMINSB256,
28718 IX86_BUILTIN_PMINSW256,
28719 IX86_BUILTIN_PMINSD256,
28720 IX86_BUILTIN_PMINUB256,
28721 IX86_BUILTIN_PMINUW256,
28722 IX86_BUILTIN_PMINUD256,
28723 IX86_BUILTIN_PMOVMSKB256,
28724 IX86_BUILTIN_PMOVSXBW256,
28725 IX86_BUILTIN_PMOVSXBD256,
28726 IX86_BUILTIN_PMOVSXBQ256,
28727 IX86_BUILTIN_PMOVSXWD256,
28728 IX86_BUILTIN_PMOVSXWQ256,
28729 IX86_BUILTIN_PMOVSXDQ256,
28730 IX86_BUILTIN_PMOVZXBW256,
28731 IX86_BUILTIN_PMOVZXBD256,
28732 IX86_BUILTIN_PMOVZXBQ256,
28733 IX86_BUILTIN_PMOVZXWD256,
28734 IX86_BUILTIN_PMOVZXWQ256,
28735 IX86_BUILTIN_PMOVZXDQ256,
28736 IX86_BUILTIN_PMULDQ256,
28737 IX86_BUILTIN_PMULHRSW256,
28738 IX86_BUILTIN_PMULHUW256,
28739 IX86_BUILTIN_PMULHW256,
28740 IX86_BUILTIN_PMULLW256,
28741 IX86_BUILTIN_PMULLD256,
28742 IX86_BUILTIN_PMULUDQ256,
28743 IX86_BUILTIN_POR256,
28744 IX86_BUILTIN_PSADBW256,
28745 IX86_BUILTIN_PSHUFB256,
28746 IX86_BUILTIN_PSHUFD256,
28747 IX86_BUILTIN_PSHUFHW256,
28748 IX86_BUILTIN_PSHUFLW256,
28749 IX86_BUILTIN_PSIGNB256,
28750 IX86_BUILTIN_PSIGNW256,
28751 IX86_BUILTIN_PSIGND256,
28752 IX86_BUILTIN_PSLLDQI256,
28753 IX86_BUILTIN_PSLLWI256,
28754 IX86_BUILTIN_PSLLW256,
28755 IX86_BUILTIN_PSLLDI256,
28756 IX86_BUILTIN_PSLLD256,
28757 IX86_BUILTIN_PSLLQI256,
28758 IX86_BUILTIN_PSLLQ256,
28759 IX86_BUILTIN_PSRAWI256,
28760 IX86_BUILTIN_PSRAW256,
28761 IX86_BUILTIN_PSRADI256,
28762 IX86_BUILTIN_PSRAD256,
28763 IX86_BUILTIN_PSRLDQI256,
28764 IX86_BUILTIN_PSRLWI256,
28765 IX86_BUILTIN_PSRLW256,
28766 IX86_BUILTIN_PSRLDI256,
28767 IX86_BUILTIN_PSRLD256,
28768 IX86_BUILTIN_PSRLQI256,
28769 IX86_BUILTIN_PSRLQ256,
28770 IX86_BUILTIN_PSUBB256,
28771 IX86_BUILTIN_PSUBW256,
28772 IX86_BUILTIN_PSUBD256,
28773 IX86_BUILTIN_PSUBQ256,
28774 IX86_BUILTIN_PSUBSB256,
28775 IX86_BUILTIN_PSUBSW256,
28776 IX86_BUILTIN_PSUBUSB256,
28777 IX86_BUILTIN_PSUBUSW256,
28778 IX86_BUILTIN_PUNPCKHBW256,
28779 IX86_BUILTIN_PUNPCKHWD256,
28780 IX86_BUILTIN_PUNPCKHDQ256,
28781 IX86_BUILTIN_PUNPCKHQDQ256,
28782 IX86_BUILTIN_PUNPCKLBW256,
28783 IX86_BUILTIN_PUNPCKLWD256,
28784 IX86_BUILTIN_PUNPCKLDQ256,
28785 IX86_BUILTIN_PUNPCKLQDQ256,
28786 IX86_BUILTIN_PXOR256,
28787 IX86_BUILTIN_MOVNTDQA256,
28788 IX86_BUILTIN_VBROADCASTSS_PS,
28789 IX86_BUILTIN_VBROADCASTSS_PS256,
28790 IX86_BUILTIN_VBROADCASTSD_PD256,
28791 IX86_BUILTIN_VBROADCASTSI256,
28792 IX86_BUILTIN_PBLENDD256,
28793 IX86_BUILTIN_PBLENDD128,
28794 IX86_BUILTIN_PBROADCASTB256,
28795 IX86_BUILTIN_PBROADCASTW256,
28796 IX86_BUILTIN_PBROADCASTD256,
28797 IX86_BUILTIN_PBROADCASTQ256,
28798 IX86_BUILTIN_PBROADCASTB128,
28799 IX86_BUILTIN_PBROADCASTW128,
28800 IX86_BUILTIN_PBROADCASTD128,
28801 IX86_BUILTIN_PBROADCASTQ128,
28802 IX86_BUILTIN_VPERMVARSI256,
28803 IX86_BUILTIN_VPERMDF256,
28804 IX86_BUILTIN_VPERMVARSF256,
28805 IX86_BUILTIN_VPERMDI256,
28806 IX86_BUILTIN_VPERMTI256,
28807 IX86_BUILTIN_VEXTRACT128I256,
28808 IX86_BUILTIN_VINSERT128I256,
28809 IX86_BUILTIN_MASKLOADD,
28810 IX86_BUILTIN_MASKLOADQ,
28811 IX86_BUILTIN_MASKLOADD256,
28812 IX86_BUILTIN_MASKLOADQ256,
28813 IX86_BUILTIN_MASKSTORED,
28814 IX86_BUILTIN_MASKSTOREQ,
28815 IX86_BUILTIN_MASKSTORED256,
28816 IX86_BUILTIN_MASKSTOREQ256,
28817 IX86_BUILTIN_PSLLVV4DI,
28818 IX86_BUILTIN_PSLLVV2DI,
28819 IX86_BUILTIN_PSLLVV8SI,
28820 IX86_BUILTIN_PSLLVV4SI,
28821 IX86_BUILTIN_PSRAVV8SI,
28822 IX86_BUILTIN_PSRAVV4SI,
28823 IX86_BUILTIN_PSRLVV4DI,
28824 IX86_BUILTIN_PSRLVV2DI,
28825 IX86_BUILTIN_PSRLVV8SI,
28826 IX86_BUILTIN_PSRLVV4SI,
28828 IX86_BUILTIN_GATHERSIV2DF,
28829 IX86_BUILTIN_GATHERSIV4DF,
28830 IX86_BUILTIN_GATHERDIV2DF,
28831 IX86_BUILTIN_GATHERDIV4DF,
28832 IX86_BUILTIN_GATHERSIV4SF,
28833 IX86_BUILTIN_GATHERSIV8SF,
28834 IX86_BUILTIN_GATHERDIV4SF,
28835 IX86_BUILTIN_GATHERDIV8SF,
28836 IX86_BUILTIN_GATHERSIV2DI,
28837 IX86_BUILTIN_GATHERSIV4DI,
28838 IX86_BUILTIN_GATHERDIV2DI,
28839 IX86_BUILTIN_GATHERDIV4DI,
28840 IX86_BUILTIN_GATHERSIV4SI,
28841 IX86_BUILTIN_GATHERSIV8SI,
28842 IX86_BUILTIN_GATHERDIV4SI,
28843 IX86_BUILTIN_GATHERDIV8SI,
28845 /* AVX512F */
28846 IX86_BUILTIN_SI512_SI256,
28847 IX86_BUILTIN_PD512_PD256,
28848 IX86_BUILTIN_PS512_PS256,
28849 IX86_BUILTIN_SI512_SI,
28850 IX86_BUILTIN_PD512_PD,
28851 IX86_BUILTIN_PS512_PS,
28852 IX86_BUILTIN_ADDPD512,
28853 IX86_BUILTIN_ADDPS512,
28854 IX86_BUILTIN_ADDSD_ROUND,
28855 IX86_BUILTIN_ADDSS_ROUND,
28856 IX86_BUILTIN_ALIGND512,
28857 IX86_BUILTIN_ALIGNQ512,
28858 IX86_BUILTIN_BLENDMD512,
28859 IX86_BUILTIN_BLENDMPD512,
28860 IX86_BUILTIN_BLENDMPS512,
28861 IX86_BUILTIN_BLENDMQ512,
28862 IX86_BUILTIN_BROADCASTF32X4_512,
28863 IX86_BUILTIN_BROADCASTF64X4_512,
28864 IX86_BUILTIN_BROADCASTI32X4_512,
28865 IX86_BUILTIN_BROADCASTI64X4_512,
28866 IX86_BUILTIN_BROADCASTSD512,
28867 IX86_BUILTIN_BROADCASTSS512,
28868 IX86_BUILTIN_CMPD512,
28869 IX86_BUILTIN_CMPPD512,
28870 IX86_BUILTIN_CMPPS512,
28871 IX86_BUILTIN_CMPQ512,
28872 IX86_BUILTIN_CMPSD_MASK,
28873 IX86_BUILTIN_CMPSS_MASK,
28874 IX86_BUILTIN_COMIDF,
28875 IX86_BUILTIN_COMISF,
28876 IX86_BUILTIN_COMPRESSPD512,
28877 IX86_BUILTIN_COMPRESSPDSTORE512,
28878 IX86_BUILTIN_COMPRESSPS512,
28879 IX86_BUILTIN_COMPRESSPSSTORE512,
28880 IX86_BUILTIN_CVTDQ2PD512,
28881 IX86_BUILTIN_CVTDQ2PS512,
28882 IX86_BUILTIN_CVTPD2DQ512,
28883 IX86_BUILTIN_CVTPD2PS512,
28884 IX86_BUILTIN_CVTPD2UDQ512,
28885 IX86_BUILTIN_CVTPH2PS512,
28886 IX86_BUILTIN_CVTPS2DQ512,
28887 IX86_BUILTIN_CVTPS2PD512,
28888 IX86_BUILTIN_CVTPS2PH512,
28889 IX86_BUILTIN_CVTPS2UDQ512,
28890 IX86_BUILTIN_CVTSD2SS_ROUND,
28891 IX86_BUILTIN_CVTSI2SD64,
28892 IX86_BUILTIN_CVTSI2SS32,
28893 IX86_BUILTIN_CVTSI2SS64,
28894 IX86_BUILTIN_CVTSS2SD_ROUND,
28895 IX86_BUILTIN_CVTTPD2DQ512,
28896 IX86_BUILTIN_CVTTPD2UDQ512,
28897 IX86_BUILTIN_CVTTPS2DQ512,
28898 IX86_BUILTIN_CVTTPS2UDQ512,
28899 IX86_BUILTIN_CVTUDQ2PD512,
28900 IX86_BUILTIN_CVTUDQ2PS512,
28901 IX86_BUILTIN_CVTUSI2SD32,
28902 IX86_BUILTIN_CVTUSI2SD64,
28903 IX86_BUILTIN_CVTUSI2SS32,
28904 IX86_BUILTIN_CVTUSI2SS64,
28905 IX86_BUILTIN_DIVPD512,
28906 IX86_BUILTIN_DIVPS512,
28907 IX86_BUILTIN_DIVSD_ROUND,
28908 IX86_BUILTIN_DIVSS_ROUND,
28909 IX86_BUILTIN_EXPANDPD512,
28910 IX86_BUILTIN_EXPANDPD512Z,
28911 IX86_BUILTIN_EXPANDPDLOAD512,
28912 IX86_BUILTIN_EXPANDPDLOAD512Z,
28913 IX86_BUILTIN_EXPANDPS512,
28914 IX86_BUILTIN_EXPANDPS512Z,
28915 IX86_BUILTIN_EXPANDPSLOAD512,
28916 IX86_BUILTIN_EXPANDPSLOAD512Z,
28917 IX86_BUILTIN_EXTRACTF32X4,
28918 IX86_BUILTIN_EXTRACTF64X4,
28919 IX86_BUILTIN_EXTRACTI32X4,
28920 IX86_BUILTIN_EXTRACTI64X4,
28921 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28922 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28923 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28924 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28925 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28926 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28927 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28928 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28929 IX86_BUILTIN_GETEXPPD512,
28930 IX86_BUILTIN_GETEXPPS512,
28931 IX86_BUILTIN_GETEXPSD128,
28932 IX86_BUILTIN_GETEXPSS128,
28933 IX86_BUILTIN_GETMANTPD512,
28934 IX86_BUILTIN_GETMANTPS512,
28935 IX86_BUILTIN_GETMANTSD128,
28936 IX86_BUILTIN_GETMANTSS128,
28937 IX86_BUILTIN_INSERTF32X4,
28938 IX86_BUILTIN_INSERTF64X4,
28939 IX86_BUILTIN_INSERTI32X4,
28940 IX86_BUILTIN_INSERTI64X4,
28941 IX86_BUILTIN_LOADAPD512,
28942 IX86_BUILTIN_LOADAPS512,
28943 IX86_BUILTIN_LOADDQUDI512,
28944 IX86_BUILTIN_LOADDQUSI512,
28945 IX86_BUILTIN_LOADUPD512,
28946 IX86_BUILTIN_LOADUPS512,
28947 IX86_BUILTIN_MAXPD512,
28948 IX86_BUILTIN_MAXPS512,
28949 IX86_BUILTIN_MAXSD_ROUND,
28950 IX86_BUILTIN_MAXSS_ROUND,
28951 IX86_BUILTIN_MINPD512,
28952 IX86_BUILTIN_MINPS512,
28953 IX86_BUILTIN_MINSD_ROUND,
28954 IX86_BUILTIN_MINSS_ROUND,
28955 IX86_BUILTIN_MOVAPD512,
28956 IX86_BUILTIN_MOVAPS512,
28957 IX86_BUILTIN_MOVDDUP512,
28958 IX86_BUILTIN_MOVDQA32LOAD512,
28959 IX86_BUILTIN_MOVDQA32STORE512,
28960 IX86_BUILTIN_MOVDQA32_512,
28961 IX86_BUILTIN_MOVDQA64LOAD512,
28962 IX86_BUILTIN_MOVDQA64STORE512,
28963 IX86_BUILTIN_MOVDQA64_512,
28964 IX86_BUILTIN_MOVNTDQ512,
28965 IX86_BUILTIN_MOVNTDQA512,
28966 IX86_BUILTIN_MOVNTPD512,
28967 IX86_BUILTIN_MOVNTPS512,
28968 IX86_BUILTIN_MOVSHDUP512,
28969 IX86_BUILTIN_MOVSLDUP512,
28970 IX86_BUILTIN_MULPD512,
28971 IX86_BUILTIN_MULPS512,
28972 IX86_BUILTIN_MULSD_ROUND,
28973 IX86_BUILTIN_MULSS_ROUND,
28974 IX86_BUILTIN_PABSD512,
28975 IX86_BUILTIN_PABSQ512,
28976 IX86_BUILTIN_PADDD512,
28977 IX86_BUILTIN_PADDQ512,
28978 IX86_BUILTIN_PANDD512,
28979 IX86_BUILTIN_PANDND512,
28980 IX86_BUILTIN_PANDNQ512,
28981 IX86_BUILTIN_PANDQ512,
28982 IX86_BUILTIN_PBROADCASTD512,
28983 IX86_BUILTIN_PBROADCASTD512_GPR,
28984 IX86_BUILTIN_PBROADCASTMB512,
28985 IX86_BUILTIN_PBROADCASTMW512,
28986 IX86_BUILTIN_PBROADCASTQ512,
28987 IX86_BUILTIN_PBROADCASTQ512_GPR,
28988 IX86_BUILTIN_PCMPEQD512_MASK,
28989 IX86_BUILTIN_PCMPEQQ512_MASK,
28990 IX86_BUILTIN_PCMPGTD512_MASK,
28991 IX86_BUILTIN_PCMPGTQ512_MASK,
28992 IX86_BUILTIN_PCOMPRESSD512,
28993 IX86_BUILTIN_PCOMPRESSDSTORE512,
28994 IX86_BUILTIN_PCOMPRESSQ512,
28995 IX86_BUILTIN_PCOMPRESSQSTORE512,
28996 IX86_BUILTIN_PEXPANDD512,
28997 IX86_BUILTIN_PEXPANDD512Z,
28998 IX86_BUILTIN_PEXPANDDLOAD512,
28999 IX86_BUILTIN_PEXPANDDLOAD512Z,
29000 IX86_BUILTIN_PEXPANDQ512,
29001 IX86_BUILTIN_PEXPANDQ512Z,
29002 IX86_BUILTIN_PEXPANDQLOAD512,
29003 IX86_BUILTIN_PEXPANDQLOAD512Z,
29004 IX86_BUILTIN_PMAXSD512,
29005 IX86_BUILTIN_PMAXSQ512,
29006 IX86_BUILTIN_PMAXUD512,
29007 IX86_BUILTIN_PMAXUQ512,
29008 IX86_BUILTIN_PMINSD512,
29009 IX86_BUILTIN_PMINSQ512,
29010 IX86_BUILTIN_PMINUD512,
29011 IX86_BUILTIN_PMINUQ512,
29012 IX86_BUILTIN_PMOVDB512,
29013 IX86_BUILTIN_PMOVDB512_MEM,
29014 IX86_BUILTIN_PMOVDW512,
29015 IX86_BUILTIN_PMOVDW512_MEM,
29016 IX86_BUILTIN_PMOVQB512,
29017 IX86_BUILTIN_PMOVQB512_MEM,
29018 IX86_BUILTIN_PMOVQD512,
29019 IX86_BUILTIN_PMOVQD512_MEM,
29020 IX86_BUILTIN_PMOVQW512,
29021 IX86_BUILTIN_PMOVQW512_MEM,
29022 IX86_BUILTIN_PMOVSDB512,
29023 IX86_BUILTIN_PMOVSDB512_MEM,
29024 IX86_BUILTIN_PMOVSDW512,
29025 IX86_BUILTIN_PMOVSDW512_MEM,
29026 IX86_BUILTIN_PMOVSQB512,
29027 IX86_BUILTIN_PMOVSQB512_MEM,
29028 IX86_BUILTIN_PMOVSQD512,
29029 IX86_BUILTIN_PMOVSQD512_MEM,
29030 IX86_BUILTIN_PMOVSQW512,
29031 IX86_BUILTIN_PMOVSQW512_MEM,
29032 IX86_BUILTIN_PMOVSXBD512,
29033 IX86_BUILTIN_PMOVSXBQ512,
29034 IX86_BUILTIN_PMOVSXDQ512,
29035 IX86_BUILTIN_PMOVSXWD512,
29036 IX86_BUILTIN_PMOVSXWQ512,
29037 IX86_BUILTIN_PMOVUSDB512,
29038 IX86_BUILTIN_PMOVUSDB512_MEM,
29039 IX86_BUILTIN_PMOVUSDW512,
29040 IX86_BUILTIN_PMOVUSDW512_MEM,
29041 IX86_BUILTIN_PMOVUSQB512,
29042 IX86_BUILTIN_PMOVUSQB512_MEM,
29043 IX86_BUILTIN_PMOVUSQD512,
29044 IX86_BUILTIN_PMOVUSQD512_MEM,
29045 IX86_BUILTIN_PMOVUSQW512,
29046 IX86_BUILTIN_PMOVUSQW512_MEM,
29047 IX86_BUILTIN_PMOVZXBD512,
29048 IX86_BUILTIN_PMOVZXBQ512,
29049 IX86_BUILTIN_PMOVZXDQ512,
29050 IX86_BUILTIN_PMOVZXWD512,
29051 IX86_BUILTIN_PMOVZXWQ512,
29052 IX86_BUILTIN_PMULDQ512,
29053 IX86_BUILTIN_PMULLD512,
29054 IX86_BUILTIN_PMULUDQ512,
29055 IX86_BUILTIN_PORD512,
29056 IX86_BUILTIN_PORQ512,
29057 IX86_BUILTIN_PROLD512,
29058 IX86_BUILTIN_PROLQ512,
29059 IX86_BUILTIN_PROLVD512,
29060 IX86_BUILTIN_PROLVQ512,
29061 IX86_BUILTIN_PRORD512,
29062 IX86_BUILTIN_PRORQ512,
29063 IX86_BUILTIN_PRORVD512,
29064 IX86_BUILTIN_PRORVQ512,
29065 IX86_BUILTIN_PSHUFD512,
29066 IX86_BUILTIN_PSLLD512,
29067 IX86_BUILTIN_PSLLDI512,
29068 IX86_BUILTIN_PSLLQ512,
29069 IX86_BUILTIN_PSLLQI512,
29070 IX86_BUILTIN_PSLLVV16SI,
29071 IX86_BUILTIN_PSLLVV8DI,
29072 IX86_BUILTIN_PSRAD512,
29073 IX86_BUILTIN_PSRADI512,
29074 IX86_BUILTIN_PSRAQ512,
29075 IX86_BUILTIN_PSRAQI512,
29076 IX86_BUILTIN_PSRAVV16SI,
29077 IX86_BUILTIN_PSRAVV8DI,
29078 IX86_BUILTIN_PSRLD512,
29079 IX86_BUILTIN_PSRLDI512,
29080 IX86_BUILTIN_PSRLQ512,
29081 IX86_BUILTIN_PSRLQI512,
29082 IX86_BUILTIN_PSRLVV16SI,
29083 IX86_BUILTIN_PSRLVV8DI,
29084 IX86_BUILTIN_PSUBD512,
29085 IX86_BUILTIN_PSUBQ512,
29086 IX86_BUILTIN_PTESTMD512,
29087 IX86_BUILTIN_PTESTMQ512,
29088 IX86_BUILTIN_PTESTNMD512,
29089 IX86_BUILTIN_PTESTNMQ512,
29090 IX86_BUILTIN_PUNPCKHDQ512,
29091 IX86_BUILTIN_PUNPCKHQDQ512,
29092 IX86_BUILTIN_PUNPCKLDQ512,
29093 IX86_BUILTIN_PUNPCKLQDQ512,
29094 IX86_BUILTIN_PXORD512,
29095 IX86_BUILTIN_PXORQ512,
29096 IX86_BUILTIN_RCP14PD512,
29097 IX86_BUILTIN_RCP14PS512,
29098 IX86_BUILTIN_RCP14SD,
29099 IX86_BUILTIN_RCP14SS,
29100 IX86_BUILTIN_RNDSCALEPD,
29101 IX86_BUILTIN_RNDSCALEPS,
29102 IX86_BUILTIN_RNDSCALESD,
29103 IX86_BUILTIN_RNDSCALESS,
29104 IX86_BUILTIN_RSQRT14PD512,
29105 IX86_BUILTIN_RSQRT14PS512,
29106 IX86_BUILTIN_RSQRT14SD,
29107 IX86_BUILTIN_RSQRT14SS,
29108 IX86_BUILTIN_SCALEFPD512,
29109 IX86_BUILTIN_SCALEFPS512,
29110 IX86_BUILTIN_SCALEFSD,
29111 IX86_BUILTIN_SCALEFSS,
29112 IX86_BUILTIN_SHUFPD512,
29113 IX86_BUILTIN_SHUFPS512,
29114 IX86_BUILTIN_SHUF_F32x4,
29115 IX86_BUILTIN_SHUF_F64x2,
29116 IX86_BUILTIN_SHUF_I32x4,
29117 IX86_BUILTIN_SHUF_I64x2,
29118 IX86_BUILTIN_SQRTPD512,
29119 IX86_BUILTIN_SQRTPD512_MASK,
29120 IX86_BUILTIN_SQRTPS512_MASK,
29121 IX86_BUILTIN_SQRTPS_NR512,
29122 IX86_BUILTIN_SQRTSD_ROUND,
29123 IX86_BUILTIN_SQRTSS_ROUND,
29124 IX86_BUILTIN_STOREAPD512,
29125 IX86_BUILTIN_STOREAPS512,
29126 IX86_BUILTIN_STOREDQUDI512,
29127 IX86_BUILTIN_STOREDQUSI512,
29128 IX86_BUILTIN_STOREUPD512,
29129 IX86_BUILTIN_STOREUPS512,
29130 IX86_BUILTIN_SUBPD512,
29131 IX86_BUILTIN_SUBPS512,
29132 IX86_BUILTIN_SUBSD_ROUND,
29133 IX86_BUILTIN_SUBSS_ROUND,
29134 IX86_BUILTIN_UCMPD512,
29135 IX86_BUILTIN_UCMPQ512,
29136 IX86_BUILTIN_UNPCKHPD512,
29137 IX86_BUILTIN_UNPCKHPS512,
29138 IX86_BUILTIN_UNPCKLPD512,
29139 IX86_BUILTIN_UNPCKLPS512,
29140 IX86_BUILTIN_VCVTSD2SI32,
29141 IX86_BUILTIN_VCVTSD2SI64,
29142 IX86_BUILTIN_VCVTSD2USI32,
29143 IX86_BUILTIN_VCVTSD2USI64,
29144 IX86_BUILTIN_VCVTSS2SI32,
29145 IX86_BUILTIN_VCVTSS2SI64,
29146 IX86_BUILTIN_VCVTSS2USI32,
29147 IX86_BUILTIN_VCVTSS2USI64,
29148 IX86_BUILTIN_VCVTTSD2SI32,
29149 IX86_BUILTIN_VCVTTSD2SI64,
29150 IX86_BUILTIN_VCVTTSD2USI32,
29151 IX86_BUILTIN_VCVTTSD2USI64,
29152 IX86_BUILTIN_VCVTTSS2SI32,
29153 IX86_BUILTIN_VCVTTSS2SI64,
29154 IX86_BUILTIN_VCVTTSS2USI32,
29155 IX86_BUILTIN_VCVTTSS2USI64,
29156 IX86_BUILTIN_VFMADDPD512_MASK,
29157 IX86_BUILTIN_VFMADDPD512_MASK3,
29158 IX86_BUILTIN_VFMADDPD512_MASKZ,
29159 IX86_BUILTIN_VFMADDPS512_MASK,
29160 IX86_BUILTIN_VFMADDPS512_MASK3,
29161 IX86_BUILTIN_VFMADDPS512_MASKZ,
29162 IX86_BUILTIN_VFMADDSD3_ROUND,
29163 IX86_BUILTIN_VFMADDSS3_ROUND,
29164 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29165 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29166 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29167 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29168 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29169 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29170 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29171 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29172 IX86_BUILTIN_VFMSUBPD512_MASK3,
29173 IX86_BUILTIN_VFMSUBPS512_MASK3,
29174 IX86_BUILTIN_VFMSUBSD3_MASK3,
29175 IX86_BUILTIN_VFMSUBSS3_MASK3,
29176 IX86_BUILTIN_VFNMADDPD512_MASK,
29177 IX86_BUILTIN_VFNMADDPS512_MASK,
29178 IX86_BUILTIN_VFNMSUBPD512_MASK,
29179 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29180 IX86_BUILTIN_VFNMSUBPS512_MASK,
29181 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29182 IX86_BUILTIN_VPCLZCNTD512,
29183 IX86_BUILTIN_VPCLZCNTQ512,
29184 IX86_BUILTIN_VPCONFLICTD512,
29185 IX86_BUILTIN_VPCONFLICTQ512,
29186 IX86_BUILTIN_VPERMDF512,
29187 IX86_BUILTIN_VPERMDI512,
29188 IX86_BUILTIN_VPERMI2VARD512,
29189 IX86_BUILTIN_VPERMI2VARPD512,
29190 IX86_BUILTIN_VPERMI2VARPS512,
29191 IX86_BUILTIN_VPERMI2VARQ512,
29192 IX86_BUILTIN_VPERMILPD512,
29193 IX86_BUILTIN_VPERMILPS512,
29194 IX86_BUILTIN_VPERMILVARPD512,
29195 IX86_BUILTIN_VPERMILVARPS512,
29196 IX86_BUILTIN_VPERMT2VARD512,
29197 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29198 IX86_BUILTIN_VPERMT2VARPD512,
29199 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29200 IX86_BUILTIN_VPERMT2VARPS512,
29201 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29202 IX86_BUILTIN_VPERMT2VARQ512,
29203 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29204 IX86_BUILTIN_VPERMVARDF512,
29205 IX86_BUILTIN_VPERMVARDI512,
29206 IX86_BUILTIN_VPERMVARSF512,
29207 IX86_BUILTIN_VPERMVARSI512,
29208 IX86_BUILTIN_VTERNLOGD512_MASK,
29209 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29210 IX86_BUILTIN_VTERNLOGQ512_MASK,
29211 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29213 /* Mask arithmetic operations */
29214 IX86_BUILTIN_KAND16,
29215 IX86_BUILTIN_KANDN16,
29216 IX86_BUILTIN_KNOT16,
29217 IX86_BUILTIN_KOR16,
29218 IX86_BUILTIN_KORTESTC16,
29219 IX86_BUILTIN_KORTESTZ16,
29220 IX86_BUILTIN_KUNPCKBW,
29221 IX86_BUILTIN_KXNOR16,
29222 IX86_BUILTIN_KXOR16,
29223 IX86_BUILTIN_KMOV16,
29225 /* AVX512VL. */
29226 IX86_BUILTIN_PMOVUSQD256_MEM,
29227 IX86_BUILTIN_PMOVUSQD128_MEM,
29228 IX86_BUILTIN_PMOVSQD256_MEM,
29229 IX86_BUILTIN_PMOVSQD128_MEM,
29230 IX86_BUILTIN_PMOVQD256_MEM,
29231 IX86_BUILTIN_PMOVQD128_MEM,
29232 IX86_BUILTIN_PMOVUSQW256_MEM,
29233 IX86_BUILTIN_PMOVUSQW128_MEM,
29234 IX86_BUILTIN_PMOVSQW256_MEM,
29235 IX86_BUILTIN_PMOVSQW128_MEM,
29236 IX86_BUILTIN_PMOVQW256_MEM,
29237 IX86_BUILTIN_PMOVQW128_MEM,
29238 IX86_BUILTIN_PMOVUSQB256_MEM,
29239 IX86_BUILTIN_PMOVUSQB128_MEM,
29240 IX86_BUILTIN_PMOVSQB256_MEM,
29241 IX86_BUILTIN_PMOVSQB128_MEM,
29242 IX86_BUILTIN_PMOVQB256_MEM,
29243 IX86_BUILTIN_PMOVQB128_MEM,
29244 IX86_BUILTIN_PMOVUSDW256_MEM,
29245 IX86_BUILTIN_PMOVUSDW128_MEM,
29246 IX86_BUILTIN_PMOVSDW256_MEM,
29247 IX86_BUILTIN_PMOVSDW128_MEM,
29248 IX86_BUILTIN_PMOVDW256_MEM,
29249 IX86_BUILTIN_PMOVDW128_MEM,
29250 IX86_BUILTIN_PMOVUSDB256_MEM,
29251 IX86_BUILTIN_PMOVUSDB128_MEM,
29252 IX86_BUILTIN_PMOVSDB256_MEM,
29253 IX86_BUILTIN_PMOVSDB128_MEM,
29254 IX86_BUILTIN_PMOVDB256_MEM,
29255 IX86_BUILTIN_PMOVDB128_MEM,
29256 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29257 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29258 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29259 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29260 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29261 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29262 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29263 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29264 IX86_BUILTIN_LOADAPD256_MASK,
29265 IX86_BUILTIN_LOADAPD128_MASK,
29266 IX86_BUILTIN_LOADAPS256_MASK,
29267 IX86_BUILTIN_LOADAPS128_MASK,
29268 IX86_BUILTIN_STOREAPD256_MASK,
29269 IX86_BUILTIN_STOREAPD128_MASK,
29270 IX86_BUILTIN_STOREAPS256_MASK,
29271 IX86_BUILTIN_STOREAPS128_MASK,
29272 IX86_BUILTIN_LOADUPD256_MASK,
29273 IX86_BUILTIN_LOADUPD128_MASK,
29274 IX86_BUILTIN_LOADUPS256_MASK,
29275 IX86_BUILTIN_LOADUPS128_MASK,
29276 IX86_BUILTIN_STOREUPD256_MASK,
29277 IX86_BUILTIN_STOREUPD128_MASK,
29278 IX86_BUILTIN_STOREUPS256_MASK,
29279 IX86_BUILTIN_STOREUPS128_MASK,
29280 IX86_BUILTIN_LOADDQUDI256_MASK,
29281 IX86_BUILTIN_LOADDQUDI128_MASK,
29282 IX86_BUILTIN_LOADDQUSI256_MASK,
29283 IX86_BUILTIN_LOADDQUSI128_MASK,
29284 IX86_BUILTIN_LOADDQUHI256_MASK,
29285 IX86_BUILTIN_LOADDQUHI128_MASK,
29286 IX86_BUILTIN_LOADDQUQI256_MASK,
29287 IX86_BUILTIN_LOADDQUQI128_MASK,
29288 IX86_BUILTIN_STOREDQUDI256_MASK,
29289 IX86_BUILTIN_STOREDQUDI128_MASK,
29290 IX86_BUILTIN_STOREDQUSI256_MASK,
29291 IX86_BUILTIN_STOREDQUSI128_MASK,
29292 IX86_BUILTIN_STOREDQUHI256_MASK,
29293 IX86_BUILTIN_STOREDQUHI128_MASK,
29294 IX86_BUILTIN_STOREDQUQI256_MASK,
29295 IX86_BUILTIN_STOREDQUQI128_MASK,
29296 IX86_BUILTIN_COMPRESSPDSTORE256,
29297 IX86_BUILTIN_COMPRESSPDSTORE128,
29298 IX86_BUILTIN_COMPRESSPSSTORE256,
29299 IX86_BUILTIN_COMPRESSPSSTORE128,
29300 IX86_BUILTIN_PCOMPRESSQSTORE256,
29301 IX86_BUILTIN_PCOMPRESSQSTORE128,
29302 IX86_BUILTIN_PCOMPRESSDSTORE256,
29303 IX86_BUILTIN_PCOMPRESSDSTORE128,
29304 IX86_BUILTIN_EXPANDPDLOAD256,
29305 IX86_BUILTIN_EXPANDPDLOAD128,
29306 IX86_BUILTIN_EXPANDPSLOAD256,
29307 IX86_BUILTIN_EXPANDPSLOAD128,
29308 IX86_BUILTIN_PEXPANDQLOAD256,
29309 IX86_BUILTIN_PEXPANDQLOAD128,
29310 IX86_BUILTIN_PEXPANDDLOAD256,
29311 IX86_BUILTIN_PEXPANDDLOAD128,
29312 IX86_BUILTIN_EXPANDPDLOAD256Z,
29313 IX86_BUILTIN_EXPANDPDLOAD128Z,
29314 IX86_BUILTIN_EXPANDPSLOAD256Z,
29315 IX86_BUILTIN_EXPANDPSLOAD128Z,
29316 IX86_BUILTIN_PEXPANDQLOAD256Z,
29317 IX86_BUILTIN_PEXPANDQLOAD128Z,
29318 IX86_BUILTIN_PEXPANDDLOAD256Z,
29319 IX86_BUILTIN_PEXPANDDLOAD128Z,
29320 IX86_BUILTIN_PALIGNR256_MASK,
29321 IX86_BUILTIN_PALIGNR128_MASK,
29322 IX86_BUILTIN_MOVDQA64_256_MASK,
29323 IX86_BUILTIN_MOVDQA64_128_MASK,
29324 IX86_BUILTIN_MOVDQA32_256_MASK,
29325 IX86_BUILTIN_MOVDQA32_128_MASK,
29326 IX86_BUILTIN_MOVAPD256_MASK,
29327 IX86_BUILTIN_MOVAPD128_MASK,
29328 IX86_BUILTIN_MOVAPS256_MASK,
29329 IX86_BUILTIN_MOVAPS128_MASK,
29330 IX86_BUILTIN_MOVDQUHI256_MASK,
29331 IX86_BUILTIN_MOVDQUHI128_MASK,
29332 IX86_BUILTIN_MOVDQUQI256_MASK,
29333 IX86_BUILTIN_MOVDQUQI128_MASK,
29334 IX86_BUILTIN_MINPS128_MASK,
29335 IX86_BUILTIN_MAXPS128_MASK,
29336 IX86_BUILTIN_MINPD128_MASK,
29337 IX86_BUILTIN_MAXPD128_MASK,
29338 IX86_BUILTIN_MAXPD256_MASK,
29339 IX86_BUILTIN_MAXPS256_MASK,
29340 IX86_BUILTIN_MINPD256_MASK,
29341 IX86_BUILTIN_MINPS256_MASK,
29342 IX86_BUILTIN_MULPS128_MASK,
29343 IX86_BUILTIN_DIVPS128_MASK,
29344 IX86_BUILTIN_MULPD128_MASK,
29345 IX86_BUILTIN_DIVPD128_MASK,
29346 IX86_BUILTIN_DIVPD256_MASK,
29347 IX86_BUILTIN_DIVPS256_MASK,
29348 IX86_BUILTIN_MULPD256_MASK,
29349 IX86_BUILTIN_MULPS256_MASK,
29350 IX86_BUILTIN_ADDPD128_MASK,
29351 IX86_BUILTIN_ADDPD256_MASK,
29352 IX86_BUILTIN_ADDPS128_MASK,
29353 IX86_BUILTIN_ADDPS256_MASK,
29354 IX86_BUILTIN_SUBPD128_MASK,
29355 IX86_BUILTIN_SUBPD256_MASK,
29356 IX86_BUILTIN_SUBPS128_MASK,
29357 IX86_BUILTIN_SUBPS256_MASK,
29358 IX86_BUILTIN_XORPD256_MASK,
29359 IX86_BUILTIN_XORPD128_MASK,
29360 IX86_BUILTIN_XORPS256_MASK,
29361 IX86_BUILTIN_XORPS128_MASK,
29362 IX86_BUILTIN_ORPD256_MASK,
29363 IX86_BUILTIN_ORPD128_MASK,
29364 IX86_BUILTIN_ORPS256_MASK,
29365 IX86_BUILTIN_ORPS128_MASK,
29366 IX86_BUILTIN_BROADCASTF32x2_256,
29367 IX86_BUILTIN_BROADCASTI32x2_256,
29368 IX86_BUILTIN_BROADCASTI32x2_128,
29369 IX86_BUILTIN_BROADCASTF64X2_256,
29370 IX86_BUILTIN_BROADCASTI64X2_256,
29371 IX86_BUILTIN_BROADCASTF32X4_256,
29372 IX86_BUILTIN_BROADCASTI32X4_256,
29373 IX86_BUILTIN_EXTRACTF32X4_256,
29374 IX86_BUILTIN_EXTRACTI32X4_256,
29375 IX86_BUILTIN_DBPSADBW256,
29376 IX86_BUILTIN_DBPSADBW128,
29377 IX86_BUILTIN_CVTTPD2QQ256,
29378 IX86_BUILTIN_CVTTPD2QQ128,
29379 IX86_BUILTIN_CVTTPD2UQQ256,
29380 IX86_BUILTIN_CVTTPD2UQQ128,
29381 IX86_BUILTIN_CVTPD2QQ256,
29382 IX86_BUILTIN_CVTPD2QQ128,
29383 IX86_BUILTIN_CVTPD2UQQ256,
29384 IX86_BUILTIN_CVTPD2UQQ128,
29385 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29386 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29387 IX86_BUILTIN_CVTTPS2QQ256,
29388 IX86_BUILTIN_CVTTPS2QQ128,
29389 IX86_BUILTIN_CVTTPS2UQQ256,
29390 IX86_BUILTIN_CVTTPS2UQQ128,
29391 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29392 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29393 IX86_BUILTIN_CVTTPS2UDQ256,
29394 IX86_BUILTIN_CVTTPS2UDQ128,
29395 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29396 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29397 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29398 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29399 IX86_BUILTIN_CVTPD2DQ256_MASK,
29400 IX86_BUILTIN_CVTPD2DQ128_MASK,
29401 IX86_BUILTIN_CVTDQ2PD256_MASK,
29402 IX86_BUILTIN_CVTDQ2PD128_MASK,
29403 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29404 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29405 IX86_BUILTIN_CVTDQ2PS256_MASK,
29406 IX86_BUILTIN_CVTDQ2PS128_MASK,
29407 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29408 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29409 IX86_BUILTIN_CVTPS2PD256_MASK,
29410 IX86_BUILTIN_CVTPS2PD128_MASK,
29411 IX86_BUILTIN_PBROADCASTB256_MASK,
29412 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29413 IX86_BUILTIN_PBROADCASTB128_MASK,
29414 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29415 IX86_BUILTIN_PBROADCASTW256_MASK,
29416 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29417 IX86_BUILTIN_PBROADCASTW128_MASK,
29418 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29419 IX86_BUILTIN_PBROADCASTD256_MASK,
29420 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29421 IX86_BUILTIN_PBROADCASTD128_MASK,
29422 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29423 IX86_BUILTIN_PBROADCASTQ256_MASK,
29424 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29425 IX86_BUILTIN_PBROADCASTQ128_MASK,
29426 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29427 IX86_BUILTIN_BROADCASTSS256,
29428 IX86_BUILTIN_BROADCASTSS128,
29429 IX86_BUILTIN_BROADCASTSD256,
29430 IX86_BUILTIN_EXTRACTF64X2_256,
29431 IX86_BUILTIN_EXTRACTI64X2_256,
29432 IX86_BUILTIN_INSERTF32X4_256,
29433 IX86_BUILTIN_INSERTI32X4_256,
29434 IX86_BUILTIN_PMOVSXBW256_MASK,
29435 IX86_BUILTIN_PMOVSXBW128_MASK,
29436 IX86_BUILTIN_PMOVSXBD256_MASK,
29437 IX86_BUILTIN_PMOVSXBD128_MASK,
29438 IX86_BUILTIN_PMOVSXBQ256_MASK,
29439 IX86_BUILTIN_PMOVSXBQ128_MASK,
29440 IX86_BUILTIN_PMOVSXWD256_MASK,
29441 IX86_BUILTIN_PMOVSXWD128_MASK,
29442 IX86_BUILTIN_PMOVSXWQ256_MASK,
29443 IX86_BUILTIN_PMOVSXWQ128_MASK,
29444 IX86_BUILTIN_PMOVSXDQ256_MASK,
29445 IX86_BUILTIN_PMOVSXDQ128_MASK,
29446 IX86_BUILTIN_PMOVZXBW256_MASK,
29447 IX86_BUILTIN_PMOVZXBW128_MASK,
29448 IX86_BUILTIN_PMOVZXBD256_MASK,
29449 IX86_BUILTIN_PMOVZXBD128_MASK,
29450 IX86_BUILTIN_PMOVZXBQ256_MASK,
29451 IX86_BUILTIN_PMOVZXBQ128_MASK,
29452 IX86_BUILTIN_PMOVZXWD256_MASK,
29453 IX86_BUILTIN_PMOVZXWD128_MASK,
29454 IX86_BUILTIN_PMOVZXWQ256_MASK,
29455 IX86_BUILTIN_PMOVZXWQ128_MASK,
29456 IX86_BUILTIN_PMOVZXDQ256_MASK,
29457 IX86_BUILTIN_PMOVZXDQ128_MASK,
29458 IX86_BUILTIN_REDUCEPD256_MASK,
29459 IX86_BUILTIN_REDUCEPD128_MASK,
29460 IX86_BUILTIN_REDUCEPS256_MASK,
29461 IX86_BUILTIN_REDUCEPS128_MASK,
29462 IX86_BUILTIN_REDUCESD_MASK,
29463 IX86_BUILTIN_REDUCESS_MASK,
29464 IX86_BUILTIN_VPERMVARHI256_MASK,
29465 IX86_BUILTIN_VPERMVARHI128_MASK,
29466 IX86_BUILTIN_VPERMT2VARHI256,
29467 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29468 IX86_BUILTIN_VPERMT2VARHI128,
29469 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29470 IX86_BUILTIN_VPERMI2VARHI256,
29471 IX86_BUILTIN_VPERMI2VARHI128,
29472 IX86_BUILTIN_RCP14PD256,
29473 IX86_BUILTIN_RCP14PD128,
29474 IX86_BUILTIN_RCP14PS256,
29475 IX86_BUILTIN_RCP14PS128,
29476 IX86_BUILTIN_RSQRT14PD256_MASK,
29477 IX86_BUILTIN_RSQRT14PD128_MASK,
29478 IX86_BUILTIN_RSQRT14PS256_MASK,
29479 IX86_BUILTIN_RSQRT14PS128_MASK,
29480 IX86_BUILTIN_SQRTPD256_MASK,
29481 IX86_BUILTIN_SQRTPD128_MASK,
29482 IX86_BUILTIN_SQRTPS256_MASK,
29483 IX86_BUILTIN_SQRTPS128_MASK,
29484 IX86_BUILTIN_PADDB128_MASK,
29485 IX86_BUILTIN_PADDW128_MASK,
29486 IX86_BUILTIN_PADDD128_MASK,
29487 IX86_BUILTIN_PADDQ128_MASK,
29488 IX86_BUILTIN_PSUBB128_MASK,
29489 IX86_BUILTIN_PSUBW128_MASK,
29490 IX86_BUILTIN_PSUBD128_MASK,
29491 IX86_BUILTIN_PSUBQ128_MASK,
29492 IX86_BUILTIN_PADDSB128_MASK,
29493 IX86_BUILTIN_PADDSW128_MASK,
29494 IX86_BUILTIN_PSUBSB128_MASK,
29495 IX86_BUILTIN_PSUBSW128_MASK,
29496 IX86_BUILTIN_PADDUSB128_MASK,
29497 IX86_BUILTIN_PADDUSW128_MASK,
29498 IX86_BUILTIN_PSUBUSB128_MASK,
29499 IX86_BUILTIN_PSUBUSW128_MASK,
29500 IX86_BUILTIN_PADDB256_MASK,
29501 IX86_BUILTIN_PADDW256_MASK,
29502 IX86_BUILTIN_PADDD256_MASK,
29503 IX86_BUILTIN_PADDQ256_MASK,
29504 IX86_BUILTIN_PADDSB256_MASK,
29505 IX86_BUILTIN_PADDSW256_MASK,
29506 IX86_BUILTIN_PADDUSB256_MASK,
29507 IX86_BUILTIN_PADDUSW256_MASK,
29508 IX86_BUILTIN_PSUBB256_MASK,
29509 IX86_BUILTIN_PSUBW256_MASK,
29510 IX86_BUILTIN_PSUBD256_MASK,
29511 IX86_BUILTIN_PSUBQ256_MASK,
29512 IX86_BUILTIN_PSUBSB256_MASK,
29513 IX86_BUILTIN_PSUBSW256_MASK,
29514 IX86_BUILTIN_PSUBUSB256_MASK,
29515 IX86_BUILTIN_PSUBUSW256_MASK,
29516 IX86_BUILTIN_SHUF_F64x2_256,
29517 IX86_BUILTIN_SHUF_I64x2_256,
29518 IX86_BUILTIN_SHUF_I32x4_256,
29519 IX86_BUILTIN_SHUF_F32x4_256,
29520 IX86_BUILTIN_PMOVWB128,
29521 IX86_BUILTIN_PMOVWB256,
29522 IX86_BUILTIN_PMOVSWB128,
29523 IX86_BUILTIN_PMOVSWB256,
29524 IX86_BUILTIN_PMOVUSWB128,
29525 IX86_BUILTIN_PMOVUSWB256,
29526 IX86_BUILTIN_PMOVDB128,
29527 IX86_BUILTIN_PMOVDB256,
29528 IX86_BUILTIN_PMOVSDB128,
29529 IX86_BUILTIN_PMOVSDB256,
29530 IX86_BUILTIN_PMOVUSDB128,
29531 IX86_BUILTIN_PMOVUSDB256,
29532 IX86_BUILTIN_PMOVDW128,
29533 IX86_BUILTIN_PMOVDW256,
29534 IX86_BUILTIN_PMOVSDW128,
29535 IX86_BUILTIN_PMOVSDW256,
29536 IX86_BUILTIN_PMOVUSDW128,
29537 IX86_BUILTIN_PMOVUSDW256,
29538 IX86_BUILTIN_PMOVQB128,
29539 IX86_BUILTIN_PMOVQB256,
29540 IX86_BUILTIN_PMOVSQB128,
29541 IX86_BUILTIN_PMOVSQB256,
29542 IX86_BUILTIN_PMOVUSQB128,
29543 IX86_BUILTIN_PMOVUSQB256,
29544 IX86_BUILTIN_PMOVQW128,
29545 IX86_BUILTIN_PMOVQW256,
29546 IX86_BUILTIN_PMOVSQW128,
29547 IX86_BUILTIN_PMOVSQW256,
29548 IX86_BUILTIN_PMOVUSQW128,
29549 IX86_BUILTIN_PMOVUSQW256,
29550 IX86_BUILTIN_PMOVQD128,
29551 IX86_BUILTIN_PMOVQD256,
29552 IX86_BUILTIN_PMOVSQD128,
29553 IX86_BUILTIN_PMOVSQD256,
29554 IX86_BUILTIN_PMOVUSQD128,
29555 IX86_BUILTIN_PMOVUSQD256,
29556 IX86_BUILTIN_RANGEPD256,
29557 IX86_BUILTIN_RANGEPD128,
29558 IX86_BUILTIN_RANGEPS256,
29559 IX86_BUILTIN_RANGEPS128,
29560 IX86_BUILTIN_GETEXPPS256,
29561 IX86_BUILTIN_GETEXPPD256,
29562 IX86_BUILTIN_GETEXPPS128,
29563 IX86_BUILTIN_GETEXPPD128,
29564 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29565 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29566 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29567 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29568 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29569 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29570 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29571 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29572 IX86_BUILTIN_PABSQ256,
29573 IX86_BUILTIN_PABSQ128,
29574 IX86_BUILTIN_PABSD256_MASK,
29575 IX86_BUILTIN_PABSD128_MASK,
29576 IX86_BUILTIN_PMULHRSW256_MASK,
29577 IX86_BUILTIN_PMULHRSW128_MASK,
29578 IX86_BUILTIN_PMULHUW128_MASK,
29579 IX86_BUILTIN_PMULHUW256_MASK,
29580 IX86_BUILTIN_PMULHW256_MASK,
29581 IX86_BUILTIN_PMULHW128_MASK,
29582 IX86_BUILTIN_PMULLW256_MASK,
29583 IX86_BUILTIN_PMULLW128_MASK,
29584 IX86_BUILTIN_PMULLQ256,
29585 IX86_BUILTIN_PMULLQ128,
29586 IX86_BUILTIN_ANDPD256_MASK,
29587 IX86_BUILTIN_ANDPD128_MASK,
29588 IX86_BUILTIN_ANDPS256_MASK,
29589 IX86_BUILTIN_ANDPS128_MASK,
29590 IX86_BUILTIN_ANDNPD256_MASK,
29591 IX86_BUILTIN_ANDNPD128_MASK,
29592 IX86_BUILTIN_ANDNPS256_MASK,
29593 IX86_BUILTIN_ANDNPS128_MASK,
29594 IX86_BUILTIN_PSLLWI128_MASK,
29595 IX86_BUILTIN_PSLLDI128_MASK,
29596 IX86_BUILTIN_PSLLQI128_MASK,
29597 IX86_BUILTIN_PSLLW128_MASK,
29598 IX86_BUILTIN_PSLLD128_MASK,
29599 IX86_BUILTIN_PSLLQ128_MASK,
29600 IX86_BUILTIN_PSLLWI256_MASK ,
29601 IX86_BUILTIN_PSLLW256_MASK,
29602 IX86_BUILTIN_PSLLDI256_MASK,
29603 IX86_BUILTIN_PSLLD256_MASK,
29604 IX86_BUILTIN_PSLLQI256_MASK,
29605 IX86_BUILTIN_PSLLQ256_MASK,
29606 IX86_BUILTIN_PSRADI128_MASK,
29607 IX86_BUILTIN_PSRAD128_MASK,
29608 IX86_BUILTIN_PSRADI256_MASK,
29609 IX86_BUILTIN_PSRAD256_MASK,
29610 IX86_BUILTIN_PSRAQI128_MASK,
29611 IX86_BUILTIN_PSRAQ128_MASK,
29612 IX86_BUILTIN_PSRAQI256_MASK,
29613 IX86_BUILTIN_PSRAQ256_MASK,
29614 IX86_BUILTIN_PANDD256,
29615 IX86_BUILTIN_PANDD128,
29616 IX86_BUILTIN_PSRLDI128_MASK,
29617 IX86_BUILTIN_PSRLD128_MASK,
29618 IX86_BUILTIN_PSRLDI256_MASK,
29619 IX86_BUILTIN_PSRLD256_MASK,
29620 IX86_BUILTIN_PSRLQI128_MASK,
29621 IX86_BUILTIN_PSRLQ128_MASK,
29622 IX86_BUILTIN_PSRLQI256_MASK,
29623 IX86_BUILTIN_PSRLQ256_MASK,
29624 IX86_BUILTIN_PANDQ256,
29625 IX86_BUILTIN_PANDQ128,
29626 IX86_BUILTIN_PANDND256,
29627 IX86_BUILTIN_PANDND128,
29628 IX86_BUILTIN_PANDNQ256,
29629 IX86_BUILTIN_PANDNQ128,
29630 IX86_BUILTIN_PORD256,
29631 IX86_BUILTIN_PORD128,
29632 IX86_BUILTIN_PORQ256,
29633 IX86_BUILTIN_PORQ128,
29634 IX86_BUILTIN_PXORD256,
29635 IX86_BUILTIN_PXORD128,
29636 IX86_BUILTIN_PXORQ256,
29637 IX86_BUILTIN_PXORQ128,
29638 IX86_BUILTIN_PACKSSWB256_MASK,
29639 IX86_BUILTIN_PACKSSWB128_MASK,
29640 IX86_BUILTIN_PACKUSWB256_MASK,
29641 IX86_BUILTIN_PACKUSWB128_MASK,
29642 IX86_BUILTIN_RNDSCALEPS256,
29643 IX86_BUILTIN_RNDSCALEPD256,
29644 IX86_BUILTIN_RNDSCALEPS128,
29645 IX86_BUILTIN_RNDSCALEPD128,
29646 IX86_BUILTIN_VTERNLOGQ256_MASK,
29647 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29648 IX86_BUILTIN_VTERNLOGD256_MASK,
29649 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29650 IX86_BUILTIN_VTERNLOGQ128_MASK,
29651 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29652 IX86_BUILTIN_VTERNLOGD128_MASK,
29653 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29654 IX86_BUILTIN_SCALEFPD256,
29655 IX86_BUILTIN_SCALEFPS256,
29656 IX86_BUILTIN_SCALEFPD128,
29657 IX86_BUILTIN_SCALEFPS128,
29658 IX86_BUILTIN_VFMADDPD256_MASK,
29659 IX86_BUILTIN_VFMADDPD256_MASK3,
29660 IX86_BUILTIN_VFMADDPD256_MASKZ,
29661 IX86_BUILTIN_VFMADDPD128_MASK,
29662 IX86_BUILTIN_VFMADDPD128_MASK3,
29663 IX86_BUILTIN_VFMADDPD128_MASKZ,
29664 IX86_BUILTIN_VFMADDPS256_MASK,
29665 IX86_BUILTIN_VFMADDPS256_MASK3,
29666 IX86_BUILTIN_VFMADDPS256_MASKZ,
29667 IX86_BUILTIN_VFMADDPS128_MASK,
29668 IX86_BUILTIN_VFMADDPS128_MASK3,
29669 IX86_BUILTIN_VFMADDPS128_MASKZ,
29670 IX86_BUILTIN_VFMSUBPD256_MASK3,
29671 IX86_BUILTIN_VFMSUBPD128_MASK3,
29672 IX86_BUILTIN_VFMSUBPS256_MASK3,
29673 IX86_BUILTIN_VFMSUBPS128_MASK3,
29674 IX86_BUILTIN_VFNMADDPD256_MASK,
29675 IX86_BUILTIN_VFNMADDPD128_MASK,
29676 IX86_BUILTIN_VFNMADDPS256_MASK,
29677 IX86_BUILTIN_VFNMADDPS128_MASK,
29678 IX86_BUILTIN_VFNMSUBPD256_MASK,
29679 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29680 IX86_BUILTIN_VFNMSUBPD128_MASK,
29681 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29682 IX86_BUILTIN_VFNMSUBPS256_MASK,
29683 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29684 IX86_BUILTIN_VFNMSUBPS128_MASK,
29685 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29686 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29687 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29688 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29689 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29690 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29691 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29692 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29693 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29694 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29695 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29696 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29697 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29698 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29699 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29700 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29701 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29702 IX86_BUILTIN_INSERTF64X2_256,
29703 IX86_BUILTIN_INSERTI64X2_256,
29704 IX86_BUILTIN_PSRAVV16HI,
29705 IX86_BUILTIN_PSRAVV8HI,
29706 IX86_BUILTIN_PMADDUBSW256_MASK,
29707 IX86_BUILTIN_PMADDUBSW128_MASK,
29708 IX86_BUILTIN_PMADDWD256_MASK,
29709 IX86_BUILTIN_PMADDWD128_MASK,
29710 IX86_BUILTIN_PSRLVV16HI,
29711 IX86_BUILTIN_PSRLVV8HI,
29712 IX86_BUILTIN_CVTPS2DQ256_MASK,
29713 IX86_BUILTIN_CVTPS2DQ128_MASK,
29714 IX86_BUILTIN_CVTPS2UDQ256,
29715 IX86_BUILTIN_CVTPS2UDQ128,
29716 IX86_BUILTIN_CVTPS2QQ256,
29717 IX86_BUILTIN_CVTPS2QQ128,
29718 IX86_BUILTIN_CVTPS2UQQ256,
29719 IX86_BUILTIN_CVTPS2UQQ128,
29720 IX86_BUILTIN_GETMANTPS256,
29721 IX86_BUILTIN_GETMANTPS128,
29722 IX86_BUILTIN_GETMANTPD256,
29723 IX86_BUILTIN_GETMANTPD128,
29724 IX86_BUILTIN_MOVDDUP256_MASK,
29725 IX86_BUILTIN_MOVDDUP128_MASK,
29726 IX86_BUILTIN_MOVSHDUP256_MASK,
29727 IX86_BUILTIN_MOVSHDUP128_MASK,
29728 IX86_BUILTIN_MOVSLDUP256_MASK,
29729 IX86_BUILTIN_MOVSLDUP128_MASK,
29730 IX86_BUILTIN_CVTQQ2PS256,
29731 IX86_BUILTIN_CVTQQ2PS128,
29732 IX86_BUILTIN_CVTUQQ2PS256,
29733 IX86_BUILTIN_CVTUQQ2PS128,
29734 IX86_BUILTIN_CVTQQ2PD256,
29735 IX86_BUILTIN_CVTQQ2PD128,
29736 IX86_BUILTIN_CVTUQQ2PD256,
29737 IX86_BUILTIN_CVTUQQ2PD128,
29738 IX86_BUILTIN_VPERMT2VARQ256,
29739 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29740 IX86_BUILTIN_VPERMT2VARD256,
29741 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29742 IX86_BUILTIN_VPERMI2VARQ256,
29743 IX86_BUILTIN_VPERMI2VARD256,
29744 IX86_BUILTIN_VPERMT2VARPD256,
29745 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29746 IX86_BUILTIN_VPERMT2VARPS256,
29747 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29748 IX86_BUILTIN_VPERMI2VARPD256,
29749 IX86_BUILTIN_VPERMI2VARPS256,
29750 IX86_BUILTIN_VPERMT2VARQ128,
29751 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29752 IX86_BUILTIN_VPERMT2VARD128,
29753 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29754 IX86_BUILTIN_VPERMI2VARQ128,
29755 IX86_BUILTIN_VPERMI2VARD128,
29756 IX86_BUILTIN_VPERMT2VARPD128,
29757 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29758 IX86_BUILTIN_VPERMT2VARPS128,
29759 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29760 IX86_BUILTIN_VPERMI2VARPD128,
29761 IX86_BUILTIN_VPERMI2VARPS128,
29762 IX86_BUILTIN_PSHUFB256_MASK,
29763 IX86_BUILTIN_PSHUFB128_MASK,
29764 IX86_BUILTIN_PSHUFHW256_MASK,
29765 IX86_BUILTIN_PSHUFHW128_MASK,
29766 IX86_BUILTIN_PSHUFLW256_MASK,
29767 IX86_BUILTIN_PSHUFLW128_MASK,
29768 IX86_BUILTIN_PSHUFD256_MASK,
29769 IX86_BUILTIN_PSHUFD128_MASK,
29770 IX86_BUILTIN_SHUFPD256_MASK,
29771 IX86_BUILTIN_SHUFPD128_MASK,
29772 IX86_BUILTIN_SHUFPS256_MASK,
29773 IX86_BUILTIN_SHUFPS128_MASK,
29774 IX86_BUILTIN_PROLVQ256,
29775 IX86_BUILTIN_PROLVQ128,
29776 IX86_BUILTIN_PROLQ256,
29777 IX86_BUILTIN_PROLQ128,
29778 IX86_BUILTIN_PRORVQ256,
29779 IX86_BUILTIN_PRORVQ128,
29780 IX86_BUILTIN_PRORQ256,
29781 IX86_BUILTIN_PRORQ128,
29782 IX86_BUILTIN_PSRAVQ128,
29783 IX86_BUILTIN_PSRAVQ256,
29784 IX86_BUILTIN_PSLLVV4DI_MASK,
29785 IX86_BUILTIN_PSLLVV2DI_MASK,
29786 IX86_BUILTIN_PSLLVV8SI_MASK,
29787 IX86_BUILTIN_PSLLVV4SI_MASK,
29788 IX86_BUILTIN_PSRAVV8SI_MASK,
29789 IX86_BUILTIN_PSRAVV4SI_MASK,
29790 IX86_BUILTIN_PSRLVV4DI_MASK,
29791 IX86_BUILTIN_PSRLVV2DI_MASK,
29792 IX86_BUILTIN_PSRLVV8SI_MASK,
29793 IX86_BUILTIN_PSRLVV4SI_MASK,
29794 IX86_BUILTIN_PSRAWI256_MASK,
29795 IX86_BUILTIN_PSRAW256_MASK,
29796 IX86_BUILTIN_PSRAWI128_MASK,
29797 IX86_BUILTIN_PSRAW128_MASK,
29798 IX86_BUILTIN_PSRLWI256_MASK,
29799 IX86_BUILTIN_PSRLW256_MASK,
29800 IX86_BUILTIN_PSRLWI128_MASK,
29801 IX86_BUILTIN_PSRLW128_MASK,
29802 IX86_BUILTIN_PRORVD256,
29803 IX86_BUILTIN_PROLVD256,
29804 IX86_BUILTIN_PRORD256,
29805 IX86_BUILTIN_PROLD256,
29806 IX86_BUILTIN_PRORVD128,
29807 IX86_BUILTIN_PROLVD128,
29808 IX86_BUILTIN_PRORD128,
29809 IX86_BUILTIN_PROLD128,
29810 IX86_BUILTIN_FPCLASSPD256,
29811 IX86_BUILTIN_FPCLASSPD128,
29812 IX86_BUILTIN_FPCLASSSD,
29813 IX86_BUILTIN_FPCLASSPS256,
29814 IX86_BUILTIN_FPCLASSPS128,
29815 IX86_BUILTIN_FPCLASSSS,
29816 IX86_BUILTIN_CVTB2MASK128,
29817 IX86_BUILTIN_CVTB2MASK256,
29818 IX86_BUILTIN_CVTW2MASK128,
29819 IX86_BUILTIN_CVTW2MASK256,
29820 IX86_BUILTIN_CVTD2MASK128,
29821 IX86_BUILTIN_CVTD2MASK256,
29822 IX86_BUILTIN_CVTQ2MASK128,
29823 IX86_BUILTIN_CVTQ2MASK256,
29824 IX86_BUILTIN_CVTMASK2B128,
29825 IX86_BUILTIN_CVTMASK2B256,
29826 IX86_BUILTIN_CVTMASK2W128,
29827 IX86_BUILTIN_CVTMASK2W256,
29828 IX86_BUILTIN_CVTMASK2D128,
29829 IX86_BUILTIN_CVTMASK2D256,
29830 IX86_BUILTIN_CVTMASK2Q128,
29831 IX86_BUILTIN_CVTMASK2Q256,
29832 IX86_BUILTIN_PCMPEQB128_MASK,
29833 IX86_BUILTIN_PCMPEQB256_MASK,
29834 IX86_BUILTIN_PCMPEQW128_MASK,
29835 IX86_BUILTIN_PCMPEQW256_MASK,
29836 IX86_BUILTIN_PCMPEQD128_MASK,
29837 IX86_BUILTIN_PCMPEQD256_MASK,
29838 IX86_BUILTIN_PCMPEQQ128_MASK,
29839 IX86_BUILTIN_PCMPEQQ256_MASK,
29840 IX86_BUILTIN_PCMPGTB128_MASK,
29841 IX86_BUILTIN_PCMPGTB256_MASK,
29842 IX86_BUILTIN_PCMPGTW128_MASK,
29843 IX86_BUILTIN_PCMPGTW256_MASK,
29844 IX86_BUILTIN_PCMPGTD128_MASK,
29845 IX86_BUILTIN_PCMPGTD256_MASK,
29846 IX86_BUILTIN_PCMPGTQ128_MASK,
29847 IX86_BUILTIN_PCMPGTQ256_MASK,
29848 IX86_BUILTIN_PTESTMB128,
29849 IX86_BUILTIN_PTESTMB256,
29850 IX86_BUILTIN_PTESTMW128,
29851 IX86_BUILTIN_PTESTMW256,
29852 IX86_BUILTIN_PTESTMD128,
29853 IX86_BUILTIN_PTESTMD256,
29854 IX86_BUILTIN_PTESTMQ128,
29855 IX86_BUILTIN_PTESTMQ256,
29856 IX86_BUILTIN_PTESTNMB128,
29857 IX86_BUILTIN_PTESTNMB256,
29858 IX86_BUILTIN_PTESTNMW128,
29859 IX86_BUILTIN_PTESTNMW256,
29860 IX86_BUILTIN_PTESTNMD128,
29861 IX86_BUILTIN_PTESTNMD256,
29862 IX86_BUILTIN_PTESTNMQ128,
29863 IX86_BUILTIN_PTESTNMQ256,
29864 IX86_BUILTIN_PBROADCASTMB128,
29865 IX86_BUILTIN_PBROADCASTMB256,
29866 IX86_BUILTIN_PBROADCASTMW128,
29867 IX86_BUILTIN_PBROADCASTMW256,
29868 IX86_BUILTIN_COMPRESSPD256,
29869 IX86_BUILTIN_COMPRESSPD128,
29870 IX86_BUILTIN_COMPRESSPS256,
29871 IX86_BUILTIN_COMPRESSPS128,
29872 IX86_BUILTIN_PCOMPRESSQ256,
29873 IX86_BUILTIN_PCOMPRESSQ128,
29874 IX86_BUILTIN_PCOMPRESSD256,
29875 IX86_BUILTIN_PCOMPRESSD128,
29876 IX86_BUILTIN_EXPANDPD256,
29877 IX86_BUILTIN_EXPANDPD128,
29878 IX86_BUILTIN_EXPANDPS256,
29879 IX86_BUILTIN_EXPANDPS128,
29880 IX86_BUILTIN_PEXPANDQ256,
29881 IX86_BUILTIN_PEXPANDQ128,
29882 IX86_BUILTIN_PEXPANDD256,
29883 IX86_BUILTIN_PEXPANDD128,
29884 IX86_BUILTIN_EXPANDPD256Z,
29885 IX86_BUILTIN_EXPANDPD128Z,
29886 IX86_BUILTIN_EXPANDPS256Z,
29887 IX86_BUILTIN_EXPANDPS128Z,
29888 IX86_BUILTIN_PEXPANDQ256Z,
29889 IX86_BUILTIN_PEXPANDQ128Z,
29890 IX86_BUILTIN_PEXPANDD256Z,
29891 IX86_BUILTIN_PEXPANDD128Z,
29892 IX86_BUILTIN_PMAXSD256_MASK,
29893 IX86_BUILTIN_PMINSD256_MASK,
29894 IX86_BUILTIN_PMAXUD256_MASK,
29895 IX86_BUILTIN_PMINUD256_MASK,
29896 IX86_BUILTIN_PMAXSD128_MASK,
29897 IX86_BUILTIN_PMINSD128_MASK,
29898 IX86_BUILTIN_PMAXUD128_MASK,
29899 IX86_BUILTIN_PMINUD128_MASK,
29900 IX86_BUILTIN_PMAXSQ256_MASK,
29901 IX86_BUILTIN_PMINSQ256_MASK,
29902 IX86_BUILTIN_PMAXUQ256_MASK,
29903 IX86_BUILTIN_PMINUQ256_MASK,
29904 IX86_BUILTIN_PMAXSQ128_MASK,
29905 IX86_BUILTIN_PMINSQ128_MASK,
29906 IX86_BUILTIN_PMAXUQ128_MASK,
29907 IX86_BUILTIN_PMINUQ128_MASK,
29908 IX86_BUILTIN_PMINSB256_MASK,
29909 IX86_BUILTIN_PMINUB256_MASK,
29910 IX86_BUILTIN_PMAXSB256_MASK,
29911 IX86_BUILTIN_PMAXUB256_MASK,
29912 IX86_BUILTIN_PMINSB128_MASK,
29913 IX86_BUILTIN_PMINUB128_MASK,
29914 IX86_BUILTIN_PMAXSB128_MASK,
29915 IX86_BUILTIN_PMAXUB128_MASK,
29916 IX86_BUILTIN_PMINSW256_MASK,
29917 IX86_BUILTIN_PMINUW256_MASK,
29918 IX86_BUILTIN_PMAXSW256_MASK,
29919 IX86_BUILTIN_PMAXUW256_MASK,
29920 IX86_BUILTIN_PMINSW128_MASK,
29921 IX86_BUILTIN_PMINUW128_MASK,
29922 IX86_BUILTIN_PMAXSW128_MASK,
29923 IX86_BUILTIN_PMAXUW128_MASK,
29924 IX86_BUILTIN_VPCONFLICTQ256,
29925 IX86_BUILTIN_VPCONFLICTD256,
29926 IX86_BUILTIN_VPCLZCNTQ256,
29927 IX86_BUILTIN_VPCLZCNTD256,
29928 IX86_BUILTIN_UNPCKHPD256_MASK,
29929 IX86_BUILTIN_UNPCKHPD128_MASK,
29930 IX86_BUILTIN_UNPCKHPS256_MASK,
29931 IX86_BUILTIN_UNPCKHPS128_MASK,
29932 IX86_BUILTIN_UNPCKLPD256_MASK,
29933 IX86_BUILTIN_UNPCKLPD128_MASK,
29934 IX86_BUILTIN_UNPCKLPS256_MASK,
29935 IX86_BUILTIN_VPCONFLICTQ128,
29936 IX86_BUILTIN_VPCONFLICTD128,
29937 IX86_BUILTIN_VPCLZCNTQ128,
29938 IX86_BUILTIN_VPCLZCNTD128,
29939 IX86_BUILTIN_UNPCKLPS128_MASK,
29940 IX86_BUILTIN_ALIGND256,
29941 IX86_BUILTIN_ALIGNQ256,
29942 IX86_BUILTIN_ALIGND128,
29943 IX86_BUILTIN_ALIGNQ128,
29944 IX86_BUILTIN_CVTPS2PH256_MASK,
29945 IX86_BUILTIN_CVTPS2PH_MASK,
29946 IX86_BUILTIN_CVTPH2PS_MASK,
29947 IX86_BUILTIN_CVTPH2PS256_MASK,
29948 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29949 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29950 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29951 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29952 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29953 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29954 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29955 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29956 IX86_BUILTIN_PUNPCKHBW128_MASK,
29957 IX86_BUILTIN_PUNPCKHBW256_MASK,
29958 IX86_BUILTIN_PUNPCKHWD128_MASK,
29959 IX86_BUILTIN_PUNPCKHWD256_MASK,
29960 IX86_BUILTIN_PUNPCKLBW128_MASK,
29961 IX86_BUILTIN_PUNPCKLBW256_MASK,
29962 IX86_BUILTIN_PUNPCKLWD128_MASK,
29963 IX86_BUILTIN_PUNPCKLWD256_MASK,
29964 IX86_BUILTIN_PSLLVV16HI,
29965 IX86_BUILTIN_PSLLVV8HI,
29966 IX86_BUILTIN_PACKSSDW256_MASK,
29967 IX86_BUILTIN_PACKSSDW128_MASK,
29968 IX86_BUILTIN_PACKUSDW256_MASK,
29969 IX86_BUILTIN_PACKUSDW128_MASK,
29970 IX86_BUILTIN_PAVGB256_MASK,
29971 IX86_BUILTIN_PAVGW256_MASK,
29972 IX86_BUILTIN_PAVGB128_MASK,
29973 IX86_BUILTIN_PAVGW128_MASK,
29974 IX86_BUILTIN_VPERMVARSF256_MASK,
29975 IX86_BUILTIN_VPERMVARDF256_MASK,
29976 IX86_BUILTIN_VPERMDF256_MASK,
29977 IX86_BUILTIN_PABSB256_MASK,
29978 IX86_BUILTIN_PABSB128_MASK,
29979 IX86_BUILTIN_PABSW256_MASK,
29980 IX86_BUILTIN_PABSW128_MASK,
29981 IX86_BUILTIN_VPERMILVARPD_MASK,
29982 IX86_BUILTIN_VPERMILVARPS_MASK,
29983 IX86_BUILTIN_VPERMILVARPD256_MASK,
29984 IX86_BUILTIN_VPERMILVARPS256_MASK,
29985 IX86_BUILTIN_VPERMILPD_MASK,
29986 IX86_BUILTIN_VPERMILPS_MASK,
29987 IX86_BUILTIN_VPERMILPD256_MASK,
29988 IX86_BUILTIN_VPERMILPS256_MASK,
29989 IX86_BUILTIN_BLENDMQ256,
29990 IX86_BUILTIN_BLENDMD256,
29991 IX86_BUILTIN_BLENDMPD256,
29992 IX86_BUILTIN_BLENDMPS256,
29993 IX86_BUILTIN_BLENDMQ128,
29994 IX86_BUILTIN_BLENDMD128,
29995 IX86_BUILTIN_BLENDMPD128,
29996 IX86_BUILTIN_BLENDMPS128,
29997 IX86_BUILTIN_BLENDMW256,
29998 IX86_BUILTIN_BLENDMB256,
29999 IX86_BUILTIN_BLENDMW128,
30000 IX86_BUILTIN_BLENDMB128,
30001 IX86_BUILTIN_PMULLD256_MASK,
30002 IX86_BUILTIN_PMULLD128_MASK,
30003 IX86_BUILTIN_PMULUDQ256_MASK,
30004 IX86_BUILTIN_PMULDQ256_MASK,
30005 IX86_BUILTIN_PMULDQ128_MASK,
30006 IX86_BUILTIN_PMULUDQ128_MASK,
30007 IX86_BUILTIN_CVTPD2PS256_MASK,
30008 IX86_BUILTIN_CVTPD2PS_MASK,
30009 IX86_BUILTIN_VPERMVARSI256_MASK,
30010 IX86_BUILTIN_VPERMVARDI256_MASK,
30011 IX86_BUILTIN_VPERMDI256_MASK,
30012 IX86_BUILTIN_CMPQ256,
30013 IX86_BUILTIN_CMPD256,
30014 IX86_BUILTIN_UCMPQ256,
30015 IX86_BUILTIN_UCMPD256,
30016 IX86_BUILTIN_CMPB256,
30017 IX86_BUILTIN_CMPW256,
30018 IX86_BUILTIN_UCMPB256,
30019 IX86_BUILTIN_UCMPW256,
30020 IX86_BUILTIN_CMPPD256_MASK,
30021 IX86_BUILTIN_CMPPS256_MASK,
30022 IX86_BUILTIN_CMPQ128,
30023 IX86_BUILTIN_CMPD128,
30024 IX86_BUILTIN_UCMPQ128,
30025 IX86_BUILTIN_UCMPD128,
30026 IX86_BUILTIN_CMPB128,
30027 IX86_BUILTIN_CMPW128,
30028 IX86_BUILTIN_UCMPB128,
30029 IX86_BUILTIN_UCMPW128,
30030 IX86_BUILTIN_CMPPD128_MASK,
30031 IX86_BUILTIN_CMPPS128_MASK,
30033 IX86_BUILTIN_GATHER3SIV8SF,
30034 IX86_BUILTIN_GATHER3SIV4SF,
30035 IX86_BUILTIN_GATHER3SIV4DF,
30036 IX86_BUILTIN_GATHER3SIV2DF,
30037 IX86_BUILTIN_GATHER3DIV8SF,
30038 IX86_BUILTIN_GATHER3DIV4SF,
30039 IX86_BUILTIN_GATHER3DIV4DF,
30040 IX86_BUILTIN_GATHER3DIV2DF,
30041 IX86_BUILTIN_GATHER3SIV8SI,
30042 IX86_BUILTIN_GATHER3SIV4SI,
30043 IX86_BUILTIN_GATHER3SIV4DI,
30044 IX86_BUILTIN_GATHER3SIV2DI,
30045 IX86_BUILTIN_GATHER3DIV8SI,
30046 IX86_BUILTIN_GATHER3DIV4SI,
30047 IX86_BUILTIN_GATHER3DIV4DI,
30048 IX86_BUILTIN_GATHER3DIV2DI,
30049 IX86_BUILTIN_SCATTERSIV8SF,
30050 IX86_BUILTIN_SCATTERSIV4SF,
30051 IX86_BUILTIN_SCATTERSIV4DF,
30052 IX86_BUILTIN_SCATTERSIV2DF,
30053 IX86_BUILTIN_SCATTERDIV8SF,
30054 IX86_BUILTIN_SCATTERDIV4SF,
30055 IX86_BUILTIN_SCATTERDIV4DF,
30056 IX86_BUILTIN_SCATTERDIV2DF,
30057 IX86_BUILTIN_SCATTERSIV8SI,
30058 IX86_BUILTIN_SCATTERSIV4SI,
30059 IX86_BUILTIN_SCATTERSIV4DI,
30060 IX86_BUILTIN_SCATTERSIV2DI,
30061 IX86_BUILTIN_SCATTERDIV8SI,
30062 IX86_BUILTIN_SCATTERDIV4SI,
30063 IX86_BUILTIN_SCATTERDIV4DI,
30064 IX86_BUILTIN_SCATTERDIV2DI,
30066 /* AVX512DQ. */
30067 IX86_BUILTIN_RANGESD128,
30068 IX86_BUILTIN_RANGESS128,
30069 IX86_BUILTIN_KUNPCKWD,
30070 IX86_BUILTIN_KUNPCKDQ,
30071 IX86_BUILTIN_BROADCASTF32x2_512,
30072 IX86_BUILTIN_BROADCASTI32x2_512,
30073 IX86_BUILTIN_BROADCASTF64X2_512,
30074 IX86_BUILTIN_BROADCASTI64X2_512,
30075 IX86_BUILTIN_BROADCASTF32X8_512,
30076 IX86_BUILTIN_BROADCASTI32X8_512,
30077 IX86_BUILTIN_EXTRACTF64X2_512,
30078 IX86_BUILTIN_EXTRACTF32X8,
30079 IX86_BUILTIN_EXTRACTI64X2_512,
30080 IX86_BUILTIN_EXTRACTI32X8,
30081 IX86_BUILTIN_REDUCEPD512_MASK,
30082 IX86_BUILTIN_REDUCEPS512_MASK,
30083 IX86_BUILTIN_PMULLQ512,
30084 IX86_BUILTIN_XORPD512,
30085 IX86_BUILTIN_XORPS512,
30086 IX86_BUILTIN_ORPD512,
30087 IX86_BUILTIN_ORPS512,
30088 IX86_BUILTIN_ANDPD512,
30089 IX86_BUILTIN_ANDPS512,
30090 IX86_BUILTIN_ANDNPD512,
30091 IX86_BUILTIN_ANDNPS512,
30092 IX86_BUILTIN_INSERTF32X8,
30093 IX86_BUILTIN_INSERTI32X8,
30094 IX86_BUILTIN_INSERTF64X2_512,
30095 IX86_BUILTIN_INSERTI64X2_512,
30096 IX86_BUILTIN_FPCLASSPD512,
30097 IX86_BUILTIN_FPCLASSPS512,
30098 IX86_BUILTIN_CVTD2MASK512,
30099 IX86_BUILTIN_CVTQ2MASK512,
30100 IX86_BUILTIN_CVTMASK2D512,
30101 IX86_BUILTIN_CVTMASK2Q512,
30102 IX86_BUILTIN_CVTPD2QQ512,
30103 IX86_BUILTIN_CVTPS2QQ512,
30104 IX86_BUILTIN_CVTPD2UQQ512,
30105 IX86_BUILTIN_CVTPS2UQQ512,
30106 IX86_BUILTIN_CVTQQ2PS512,
30107 IX86_BUILTIN_CVTUQQ2PS512,
30108 IX86_BUILTIN_CVTQQ2PD512,
30109 IX86_BUILTIN_CVTUQQ2PD512,
30110 IX86_BUILTIN_CVTTPS2QQ512,
30111 IX86_BUILTIN_CVTTPS2UQQ512,
30112 IX86_BUILTIN_CVTTPD2QQ512,
30113 IX86_BUILTIN_CVTTPD2UQQ512,
30114 IX86_BUILTIN_RANGEPS512,
30115 IX86_BUILTIN_RANGEPD512,
30117 /* AVX512BW. */
30118 IX86_BUILTIN_PACKUSDW512,
30119 IX86_BUILTIN_PACKSSDW512,
30120 IX86_BUILTIN_LOADDQUHI512_MASK,
30121 IX86_BUILTIN_LOADDQUQI512_MASK,
30122 IX86_BUILTIN_PSLLDQ512,
30123 IX86_BUILTIN_PSRLDQ512,
30124 IX86_BUILTIN_STOREDQUHI512_MASK,
30125 IX86_BUILTIN_STOREDQUQI512_MASK,
30126 IX86_BUILTIN_PALIGNR512,
30127 IX86_BUILTIN_PALIGNR512_MASK,
30128 IX86_BUILTIN_MOVDQUHI512_MASK,
30129 IX86_BUILTIN_MOVDQUQI512_MASK,
30130 IX86_BUILTIN_PSADBW512,
30131 IX86_BUILTIN_DBPSADBW512,
30132 IX86_BUILTIN_PBROADCASTB512,
30133 IX86_BUILTIN_PBROADCASTB512_GPR,
30134 IX86_BUILTIN_PBROADCASTW512,
30135 IX86_BUILTIN_PBROADCASTW512_GPR,
30136 IX86_BUILTIN_PMOVSXBW512_MASK,
30137 IX86_BUILTIN_PMOVZXBW512_MASK,
30138 IX86_BUILTIN_VPERMVARHI512_MASK,
30139 IX86_BUILTIN_VPERMT2VARHI512,
30140 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30141 IX86_BUILTIN_VPERMI2VARHI512,
30142 IX86_BUILTIN_PAVGB512,
30143 IX86_BUILTIN_PAVGW512,
30144 IX86_BUILTIN_PADDB512,
30145 IX86_BUILTIN_PSUBB512,
30146 IX86_BUILTIN_PSUBSB512,
30147 IX86_BUILTIN_PADDSB512,
30148 IX86_BUILTIN_PSUBUSB512,
30149 IX86_BUILTIN_PADDUSB512,
30150 IX86_BUILTIN_PSUBW512,
30151 IX86_BUILTIN_PADDW512,
30152 IX86_BUILTIN_PSUBSW512,
30153 IX86_BUILTIN_PADDSW512,
30154 IX86_BUILTIN_PSUBUSW512,
30155 IX86_BUILTIN_PADDUSW512,
30156 IX86_BUILTIN_PMAXUW512,
30157 IX86_BUILTIN_PMAXSW512,
30158 IX86_BUILTIN_PMINUW512,
30159 IX86_BUILTIN_PMINSW512,
30160 IX86_BUILTIN_PMAXUB512,
30161 IX86_BUILTIN_PMAXSB512,
30162 IX86_BUILTIN_PMINUB512,
30163 IX86_BUILTIN_PMINSB512,
30164 IX86_BUILTIN_PMOVWB512,
30165 IX86_BUILTIN_PMOVSWB512,
30166 IX86_BUILTIN_PMOVUSWB512,
30167 IX86_BUILTIN_PMULHRSW512_MASK,
30168 IX86_BUILTIN_PMULHUW512_MASK,
30169 IX86_BUILTIN_PMULHW512_MASK,
30170 IX86_BUILTIN_PMULLW512_MASK,
30171 IX86_BUILTIN_PSLLWI512_MASK,
30172 IX86_BUILTIN_PSLLW512_MASK,
30173 IX86_BUILTIN_PACKSSWB512,
30174 IX86_BUILTIN_PACKUSWB512,
30175 IX86_BUILTIN_PSRAVV32HI,
30176 IX86_BUILTIN_PMADDUBSW512_MASK,
30177 IX86_BUILTIN_PMADDWD512_MASK,
30178 IX86_BUILTIN_PSRLVV32HI,
30179 IX86_BUILTIN_PUNPCKHBW512,
30180 IX86_BUILTIN_PUNPCKHWD512,
30181 IX86_BUILTIN_PUNPCKLBW512,
30182 IX86_BUILTIN_PUNPCKLWD512,
30183 IX86_BUILTIN_PSHUFB512,
30184 IX86_BUILTIN_PSHUFHW512,
30185 IX86_BUILTIN_PSHUFLW512,
30186 IX86_BUILTIN_PSRAWI512,
30187 IX86_BUILTIN_PSRAW512,
30188 IX86_BUILTIN_PSRLWI512,
30189 IX86_BUILTIN_PSRLW512,
30190 IX86_BUILTIN_CVTB2MASK512,
30191 IX86_BUILTIN_CVTW2MASK512,
30192 IX86_BUILTIN_CVTMASK2B512,
30193 IX86_BUILTIN_CVTMASK2W512,
30194 IX86_BUILTIN_PCMPEQB512_MASK,
30195 IX86_BUILTIN_PCMPEQW512_MASK,
30196 IX86_BUILTIN_PCMPGTB512_MASK,
30197 IX86_BUILTIN_PCMPGTW512_MASK,
30198 IX86_BUILTIN_PTESTMB512,
30199 IX86_BUILTIN_PTESTMW512,
30200 IX86_BUILTIN_PTESTNMB512,
30201 IX86_BUILTIN_PTESTNMW512,
30202 IX86_BUILTIN_PSLLVV32HI,
30203 IX86_BUILTIN_PABSB512,
30204 IX86_BUILTIN_PABSW512,
30205 IX86_BUILTIN_BLENDMW512,
30206 IX86_BUILTIN_BLENDMB512,
30207 IX86_BUILTIN_CMPB512,
30208 IX86_BUILTIN_CMPW512,
30209 IX86_BUILTIN_UCMPB512,
30210 IX86_BUILTIN_UCMPW512,
30212 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30213 where all operands are 32-byte or 64-byte wide respectively. */
30214 IX86_BUILTIN_GATHERALTSIV4DF,
30215 IX86_BUILTIN_GATHERALTDIV8SF,
30216 IX86_BUILTIN_GATHERALTSIV4DI,
30217 IX86_BUILTIN_GATHERALTDIV8SI,
30218 IX86_BUILTIN_GATHER3ALTDIV16SF,
30219 IX86_BUILTIN_GATHER3ALTDIV16SI,
30220 IX86_BUILTIN_GATHER3ALTSIV4DF,
30221 IX86_BUILTIN_GATHER3ALTDIV8SF,
30222 IX86_BUILTIN_GATHER3ALTSIV4DI,
30223 IX86_BUILTIN_GATHER3ALTDIV8SI,
30224 IX86_BUILTIN_GATHER3ALTSIV8DF,
30225 IX86_BUILTIN_GATHER3ALTSIV8DI,
30226 IX86_BUILTIN_GATHER3DIV16SF,
30227 IX86_BUILTIN_GATHER3DIV16SI,
30228 IX86_BUILTIN_GATHER3DIV8DF,
30229 IX86_BUILTIN_GATHER3DIV8DI,
30230 IX86_BUILTIN_GATHER3SIV16SF,
30231 IX86_BUILTIN_GATHER3SIV16SI,
30232 IX86_BUILTIN_GATHER3SIV8DF,
30233 IX86_BUILTIN_GATHER3SIV8DI,
30234 IX86_BUILTIN_SCATTERDIV16SF,
30235 IX86_BUILTIN_SCATTERDIV16SI,
30236 IX86_BUILTIN_SCATTERDIV8DF,
30237 IX86_BUILTIN_SCATTERDIV8DI,
30238 IX86_BUILTIN_SCATTERSIV16SF,
30239 IX86_BUILTIN_SCATTERSIV16SI,
30240 IX86_BUILTIN_SCATTERSIV8DF,
30241 IX86_BUILTIN_SCATTERSIV8DI,
30243 /* AVX512PF */
30244 IX86_BUILTIN_GATHERPFQPD,
30245 IX86_BUILTIN_GATHERPFDPS,
30246 IX86_BUILTIN_GATHERPFDPD,
30247 IX86_BUILTIN_GATHERPFQPS,
30248 IX86_BUILTIN_SCATTERPFDPD,
30249 IX86_BUILTIN_SCATTERPFDPS,
30250 IX86_BUILTIN_SCATTERPFQPD,
30251 IX86_BUILTIN_SCATTERPFQPS,
30253 /* AVX-512ER */
30254 IX86_BUILTIN_EXP2PD_MASK,
30255 IX86_BUILTIN_EXP2PS_MASK,
30256 IX86_BUILTIN_EXP2PS,
30257 IX86_BUILTIN_RCP28PD,
30258 IX86_BUILTIN_RCP28PS,
30259 IX86_BUILTIN_RCP28SD,
30260 IX86_BUILTIN_RCP28SS,
30261 IX86_BUILTIN_RSQRT28PD,
30262 IX86_BUILTIN_RSQRT28PS,
30263 IX86_BUILTIN_RSQRT28SD,
30264 IX86_BUILTIN_RSQRT28SS,
30266 /* AVX-512IFMA */
30267 IX86_BUILTIN_VPMADD52LUQ512,
30268 IX86_BUILTIN_VPMADD52HUQ512,
30269 IX86_BUILTIN_VPMADD52LUQ256,
30270 IX86_BUILTIN_VPMADD52HUQ256,
30271 IX86_BUILTIN_VPMADD52LUQ128,
30272 IX86_BUILTIN_VPMADD52HUQ128,
30273 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30274 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30275 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30276 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30277 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30278 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30280 /* AVX-512VBMI */
30281 IX86_BUILTIN_VPMULTISHIFTQB512,
30282 IX86_BUILTIN_VPMULTISHIFTQB256,
30283 IX86_BUILTIN_VPMULTISHIFTQB128,
30284 IX86_BUILTIN_VPERMVARQI512_MASK,
30285 IX86_BUILTIN_VPERMT2VARQI512,
30286 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30287 IX86_BUILTIN_VPERMI2VARQI512,
30288 IX86_BUILTIN_VPERMVARQI256_MASK,
30289 IX86_BUILTIN_VPERMVARQI128_MASK,
30290 IX86_BUILTIN_VPERMT2VARQI256,
30291 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30292 IX86_BUILTIN_VPERMT2VARQI128,
30293 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30294 IX86_BUILTIN_VPERMI2VARQI256,
30295 IX86_BUILTIN_VPERMI2VARQI128,
30297 /* SHA builtins. */
30298 IX86_BUILTIN_SHA1MSG1,
30299 IX86_BUILTIN_SHA1MSG2,
30300 IX86_BUILTIN_SHA1NEXTE,
30301 IX86_BUILTIN_SHA1RNDS4,
30302 IX86_BUILTIN_SHA256MSG1,
30303 IX86_BUILTIN_SHA256MSG2,
30304 IX86_BUILTIN_SHA256RNDS2,
30306 /* CLWB instructions. */
30307 IX86_BUILTIN_CLWB,
30309 /* PCOMMIT instructions. */
30310 IX86_BUILTIN_PCOMMIT,
30312 /* CLFLUSHOPT instructions. */
30313 IX86_BUILTIN_CLFLUSHOPT,
30315 /* TFmode support builtins. */
30316 IX86_BUILTIN_INFQ,
30317 IX86_BUILTIN_HUGE_VALQ,
30318 IX86_BUILTIN_FABSQ,
30319 IX86_BUILTIN_COPYSIGNQ,
30321 /* Vectorizer support builtins. */
30322 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30323 IX86_BUILTIN_CPYSGNPS,
30324 IX86_BUILTIN_CPYSGNPD,
30325 IX86_BUILTIN_CPYSGNPS256,
30326 IX86_BUILTIN_CPYSGNPS512,
30327 IX86_BUILTIN_CPYSGNPD256,
30328 IX86_BUILTIN_CPYSGNPD512,
30329 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30330 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30333 /* FMA4 instructions. */
30334 IX86_BUILTIN_VFMADDSS,
30335 IX86_BUILTIN_VFMADDSD,
30336 IX86_BUILTIN_VFMADDPS,
30337 IX86_BUILTIN_VFMADDPD,
30338 IX86_BUILTIN_VFMADDPS256,
30339 IX86_BUILTIN_VFMADDPD256,
30340 IX86_BUILTIN_VFMADDSUBPS,
30341 IX86_BUILTIN_VFMADDSUBPD,
30342 IX86_BUILTIN_VFMADDSUBPS256,
30343 IX86_BUILTIN_VFMADDSUBPD256,
30345 /* FMA3 instructions. */
30346 IX86_BUILTIN_VFMADDSS3,
30347 IX86_BUILTIN_VFMADDSD3,
30349 /* XOP instructions. */
30350 IX86_BUILTIN_VPCMOV,
30351 IX86_BUILTIN_VPCMOV_V2DI,
30352 IX86_BUILTIN_VPCMOV_V4SI,
30353 IX86_BUILTIN_VPCMOV_V8HI,
30354 IX86_BUILTIN_VPCMOV_V16QI,
30355 IX86_BUILTIN_VPCMOV_V4SF,
30356 IX86_BUILTIN_VPCMOV_V2DF,
30357 IX86_BUILTIN_VPCMOV256,
30358 IX86_BUILTIN_VPCMOV_V4DI256,
30359 IX86_BUILTIN_VPCMOV_V8SI256,
30360 IX86_BUILTIN_VPCMOV_V16HI256,
30361 IX86_BUILTIN_VPCMOV_V32QI256,
30362 IX86_BUILTIN_VPCMOV_V8SF256,
30363 IX86_BUILTIN_VPCMOV_V4DF256,
30365 IX86_BUILTIN_VPPERM,
30367 IX86_BUILTIN_VPMACSSWW,
30368 IX86_BUILTIN_VPMACSWW,
30369 IX86_BUILTIN_VPMACSSWD,
30370 IX86_BUILTIN_VPMACSWD,
30371 IX86_BUILTIN_VPMACSSDD,
30372 IX86_BUILTIN_VPMACSDD,
30373 IX86_BUILTIN_VPMACSSDQL,
30374 IX86_BUILTIN_VPMACSSDQH,
30375 IX86_BUILTIN_VPMACSDQL,
30376 IX86_BUILTIN_VPMACSDQH,
30377 IX86_BUILTIN_VPMADCSSWD,
30378 IX86_BUILTIN_VPMADCSWD,
30380 IX86_BUILTIN_VPHADDBW,
30381 IX86_BUILTIN_VPHADDBD,
30382 IX86_BUILTIN_VPHADDBQ,
30383 IX86_BUILTIN_VPHADDWD,
30384 IX86_BUILTIN_VPHADDWQ,
30385 IX86_BUILTIN_VPHADDDQ,
30386 IX86_BUILTIN_VPHADDUBW,
30387 IX86_BUILTIN_VPHADDUBD,
30388 IX86_BUILTIN_VPHADDUBQ,
30389 IX86_BUILTIN_VPHADDUWD,
30390 IX86_BUILTIN_VPHADDUWQ,
30391 IX86_BUILTIN_VPHADDUDQ,
30392 IX86_BUILTIN_VPHSUBBW,
30393 IX86_BUILTIN_VPHSUBWD,
30394 IX86_BUILTIN_VPHSUBDQ,
30396 IX86_BUILTIN_VPROTB,
30397 IX86_BUILTIN_VPROTW,
30398 IX86_BUILTIN_VPROTD,
30399 IX86_BUILTIN_VPROTQ,
30400 IX86_BUILTIN_VPROTB_IMM,
30401 IX86_BUILTIN_VPROTW_IMM,
30402 IX86_BUILTIN_VPROTD_IMM,
30403 IX86_BUILTIN_VPROTQ_IMM,
30405 IX86_BUILTIN_VPSHLB,
30406 IX86_BUILTIN_VPSHLW,
30407 IX86_BUILTIN_VPSHLD,
30408 IX86_BUILTIN_VPSHLQ,
30409 IX86_BUILTIN_VPSHAB,
30410 IX86_BUILTIN_VPSHAW,
30411 IX86_BUILTIN_VPSHAD,
30412 IX86_BUILTIN_VPSHAQ,
30414 IX86_BUILTIN_VFRCZSS,
30415 IX86_BUILTIN_VFRCZSD,
30416 IX86_BUILTIN_VFRCZPS,
30417 IX86_BUILTIN_VFRCZPD,
30418 IX86_BUILTIN_VFRCZPS256,
30419 IX86_BUILTIN_VFRCZPD256,
30421 IX86_BUILTIN_VPCOMEQUB,
30422 IX86_BUILTIN_VPCOMNEUB,
30423 IX86_BUILTIN_VPCOMLTUB,
30424 IX86_BUILTIN_VPCOMLEUB,
30425 IX86_BUILTIN_VPCOMGTUB,
30426 IX86_BUILTIN_VPCOMGEUB,
30427 IX86_BUILTIN_VPCOMFALSEUB,
30428 IX86_BUILTIN_VPCOMTRUEUB,
30430 IX86_BUILTIN_VPCOMEQUW,
30431 IX86_BUILTIN_VPCOMNEUW,
30432 IX86_BUILTIN_VPCOMLTUW,
30433 IX86_BUILTIN_VPCOMLEUW,
30434 IX86_BUILTIN_VPCOMGTUW,
30435 IX86_BUILTIN_VPCOMGEUW,
30436 IX86_BUILTIN_VPCOMFALSEUW,
30437 IX86_BUILTIN_VPCOMTRUEUW,
30439 IX86_BUILTIN_VPCOMEQUD,
30440 IX86_BUILTIN_VPCOMNEUD,
30441 IX86_BUILTIN_VPCOMLTUD,
30442 IX86_BUILTIN_VPCOMLEUD,
30443 IX86_BUILTIN_VPCOMGTUD,
30444 IX86_BUILTIN_VPCOMGEUD,
30445 IX86_BUILTIN_VPCOMFALSEUD,
30446 IX86_BUILTIN_VPCOMTRUEUD,
30448 IX86_BUILTIN_VPCOMEQUQ,
30449 IX86_BUILTIN_VPCOMNEUQ,
30450 IX86_BUILTIN_VPCOMLTUQ,
30451 IX86_BUILTIN_VPCOMLEUQ,
30452 IX86_BUILTIN_VPCOMGTUQ,
30453 IX86_BUILTIN_VPCOMGEUQ,
30454 IX86_BUILTIN_VPCOMFALSEUQ,
30455 IX86_BUILTIN_VPCOMTRUEUQ,
30457 IX86_BUILTIN_VPCOMEQB,
30458 IX86_BUILTIN_VPCOMNEB,
30459 IX86_BUILTIN_VPCOMLTB,
30460 IX86_BUILTIN_VPCOMLEB,
30461 IX86_BUILTIN_VPCOMGTB,
30462 IX86_BUILTIN_VPCOMGEB,
30463 IX86_BUILTIN_VPCOMFALSEB,
30464 IX86_BUILTIN_VPCOMTRUEB,
30466 IX86_BUILTIN_VPCOMEQW,
30467 IX86_BUILTIN_VPCOMNEW,
30468 IX86_BUILTIN_VPCOMLTW,
30469 IX86_BUILTIN_VPCOMLEW,
30470 IX86_BUILTIN_VPCOMGTW,
30471 IX86_BUILTIN_VPCOMGEW,
30472 IX86_BUILTIN_VPCOMFALSEW,
30473 IX86_BUILTIN_VPCOMTRUEW,
30475 IX86_BUILTIN_VPCOMEQD,
30476 IX86_BUILTIN_VPCOMNED,
30477 IX86_BUILTIN_VPCOMLTD,
30478 IX86_BUILTIN_VPCOMLED,
30479 IX86_BUILTIN_VPCOMGTD,
30480 IX86_BUILTIN_VPCOMGED,
30481 IX86_BUILTIN_VPCOMFALSED,
30482 IX86_BUILTIN_VPCOMTRUED,
30484 IX86_BUILTIN_VPCOMEQQ,
30485 IX86_BUILTIN_VPCOMNEQ,
30486 IX86_BUILTIN_VPCOMLTQ,
30487 IX86_BUILTIN_VPCOMLEQ,
30488 IX86_BUILTIN_VPCOMGTQ,
30489 IX86_BUILTIN_VPCOMGEQ,
30490 IX86_BUILTIN_VPCOMFALSEQ,
30491 IX86_BUILTIN_VPCOMTRUEQ,
30493 /* LWP instructions. */
30494 IX86_BUILTIN_LLWPCB,
30495 IX86_BUILTIN_SLWPCB,
30496 IX86_BUILTIN_LWPVAL32,
30497 IX86_BUILTIN_LWPVAL64,
30498 IX86_BUILTIN_LWPINS32,
30499 IX86_BUILTIN_LWPINS64,
30501 IX86_BUILTIN_CLZS,
30503 /* RTM */
30504 IX86_BUILTIN_XBEGIN,
30505 IX86_BUILTIN_XEND,
30506 IX86_BUILTIN_XABORT,
30507 IX86_BUILTIN_XTEST,
30509 /* MPX */
30510 IX86_BUILTIN_BNDMK,
30511 IX86_BUILTIN_BNDSTX,
30512 IX86_BUILTIN_BNDLDX,
30513 IX86_BUILTIN_BNDCL,
30514 IX86_BUILTIN_BNDCU,
30515 IX86_BUILTIN_BNDRET,
30516 IX86_BUILTIN_BNDNARROW,
30517 IX86_BUILTIN_BNDINT,
30518 IX86_BUILTIN_SIZEOF,
30519 IX86_BUILTIN_BNDLOWER,
30520 IX86_BUILTIN_BNDUPPER,
30522 /* BMI instructions. */
30523 IX86_BUILTIN_BEXTR32,
30524 IX86_BUILTIN_BEXTR64,
30525 IX86_BUILTIN_CTZS,
30527 /* TBM instructions. */
30528 IX86_BUILTIN_BEXTRI32,
30529 IX86_BUILTIN_BEXTRI64,
30531 /* BMI2 instructions. */
30532 IX86_BUILTIN_BZHI32,
30533 IX86_BUILTIN_BZHI64,
30534 IX86_BUILTIN_PDEP32,
30535 IX86_BUILTIN_PDEP64,
30536 IX86_BUILTIN_PEXT32,
30537 IX86_BUILTIN_PEXT64,
30539 /* ADX instructions. */
30540 IX86_BUILTIN_ADDCARRYX32,
30541 IX86_BUILTIN_ADDCARRYX64,
30543 /* SBB instructions. */
30544 IX86_BUILTIN_SBB32,
30545 IX86_BUILTIN_SBB64,
30547 /* FSGSBASE instructions. */
30548 IX86_BUILTIN_RDFSBASE32,
30549 IX86_BUILTIN_RDFSBASE64,
30550 IX86_BUILTIN_RDGSBASE32,
30551 IX86_BUILTIN_RDGSBASE64,
30552 IX86_BUILTIN_WRFSBASE32,
30553 IX86_BUILTIN_WRFSBASE64,
30554 IX86_BUILTIN_WRGSBASE32,
30555 IX86_BUILTIN_WRGSBASE64,
30557 /* RDRND instructions. */
30558 IX86_BUILTIN_RDRAND16_STEP,
30559 IX86_BUILTIN_RDRAND32_STEP,
30560 IX86_BUILTIN_RDRAND64_STEP,
30562 /* RDSEED instructions. */
30563 IX86_BUILTIN_RDSEED16_STEP,
30564 IX86_BUILTIN_RDSEED32_STEP,
30565 IX86_BUILTIN_RDSEED64_STEP,
30567 /* F16C instructions. */
30568 IX86_BUILTIN_CVTPH2PS,
30569 IX86_BUILTIN_CVTPH2PS256,
30570 IX86_BUILTIN_CVTPS2PH,
30571 IX86_BUILTIN_CVTPS2PH256,
30573 /* CFString built-in for darwin */
30574 IX86_BUILTIN_CFSTRING,
30576 /* Builtins to get CPU type and supported features. */
30577 IX86_BUILTIN_CPU_INIT,
30578 IX86_BUILTIN_CPU_IS,
30579 IX86_BUILTIN_CPU_SUPPORTS,
30581 /* Read/write FLAGS register built-ins. */
30582 IX86_BUILTIN_READ_FLAGS,
30583 IX86_BUILTIN_WRITE_FLAGS,
30585 IX86_BUILTIN_MAX
30586 };
30588 /* Table for the ix86 builtin decls. */
30591 /* Table of all of the builtin functions that are possible with different ISA's
30592 but are waiting to be built until a function is declared to use that
30593 ISA. */
30602 };
30607 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30608 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30609 function decl in the ix86_builtins array. Returns the function decl or
30610 NULL_TREE, if the builtin was not added.
30612 If the front end has a special hook for builtin functions, delay adding
30613 builtin functions that aren't in the current ISA until the ISA is changed
30614 with function specific optimization. Doing so, can save about 300K for the
30615 default compiler. When the builtin is expanded, check at that time whether
30616 it is valid.
30618 If the front end doesn't have a special hook, record all builtins, even if
30619 it isn't an instruction set in the current ISA in case the user uses
30620 function specific options for a different ISA, so that we don't get scope
30621 errors if a builtin is added in the middle of a function scope. */
30627 {
30631 {
30640 {
30646 }
30647 else
30648 {
30656 }
30657 }
30660 }
30662 /* Like def_builtin, but also marks the function decl "const". */
30667 {
30671 else
30675 }
30677 /* Add any new builtin functions for a given ISA that may not have been
30678 declared. This saves a bit of space compared to adding all of the
30679 declarations to the tree, even if we didn't use them. */
30681 static void
30683 {
30689 {
30692 {
30695 /* Don't define the builtin again. */
30701 NULL_TREE);
30708 NULL_TREE);
30711 }
30712 }
30715 }
30717 /* Bits for builtin_description.flag. */
30719 /* Set when we don't support the comparison natively, and should
30720 swap_comparison in order to support it. */
30721 #define BUILTIN_DESC_SWAP_OPERANDS 1
30723 struct builtin_description
30724 {
30731 };
30734 {
30735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30736 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30737 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30747 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30749 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30750 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30751 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30752 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30753 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30755 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30756 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30757 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30759 };
30762 {
30763 /* SSE4.2 */
30764 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30765 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30766 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30767 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30768 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30769 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30770 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30771 };
30774 {
30775 /* SSE4.2 */
30776 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30777 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30778 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30779 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30780 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30781 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30782 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30783 };
30785 /* Special builtins with variable number of arguments. */
30787 {
30788 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30789 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30790 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30792 /* 80387 (for use internally for atomic compound assignment). */
30793 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30794 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30795 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30796 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30798 /* MMX */
30799 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30801 /* 3DNow! */
30802 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30804 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30805 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30806 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30807 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30808 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30809 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30810 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30811 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30812 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30814 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30815 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30816 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30817 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30818 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30819 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30820 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30821 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30823 /* SSE */
30824 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30825 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30828 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30829 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30833 /* SSE or 3DNow!A */
30834 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30835 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30837 /* SSE2 */
30838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30845 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30852 /* SSE3 */
30853 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30855 /* SSE4.1 */
30856 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30858 /* SSE4A */
30859 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30860 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30862 /* AVX */
30863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30866 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30867 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30868 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30876 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30881 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30893 /* AVX2 */
30894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30904 /* AVX512F */
30905 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30906 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30907 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30908 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30909 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30910 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30953 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30954 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30955 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30956 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30957 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30958 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30960 /* FSGSBASE */
30961 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30962 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30963 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30964 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30965 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30966 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30967 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30968 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30970 /* RTM */
30971 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30972 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
30973 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
30975 /* AVX512BW */
30976 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
30977 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
30978 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
30979 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
30981 /* AVX512VL */
30982 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
30983 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
30984 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
30985 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
30986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
30987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
30988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
30989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
30990 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
30991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
30992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
30993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
30994 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
30995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
30996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
30997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
30998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
30999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31006 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31007 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31008 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31018 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31019 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31020 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31021 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31043 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31046 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31047 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31048 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31077 /* PCOMMIT. */
31078 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31079 };
31081 /* Builtins with variable number of arguments. */
31083 {
31084 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31085 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31086 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31087 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31088 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31089 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31090 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31092 /* MMX */
31093 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31096 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31097 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31098 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31101 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31103 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31105 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31106 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31109 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31110 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31113 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31117 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31156 /* 3DNow! */
31157 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31158 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31159 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31160 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31162 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31163 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31164 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31165 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31166 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31167 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31168 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31169 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31170 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31171 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31172 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31173 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31174 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31175 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31176 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31178 /* 3DNow!A */
31179 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31180 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31181 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31182 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31183 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31184 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31186 /* SSE */
31187 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31189 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31191 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31192 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31195 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31196 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31197 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31198 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31202 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31203 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31204 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31207 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31232 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31233 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31237 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31239 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31240 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31242 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31247 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31248 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31252 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31254 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31260 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31261 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31263 /* SSE MMX or 3Dnow!A */
31264 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31265 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31266 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31268 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31269 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31270 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31271 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31273 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31274 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31276 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31278 /* SSE2 */
31279 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31285 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31297 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31298 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31302 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31304 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31305 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31339 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31348 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31350 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31356 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31357 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31358 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31359 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31370 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31371 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31373 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31375 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31376 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31388 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31389 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31390 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31393 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31394 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31395 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31396 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31397 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31398 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31399 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31400 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31406 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31410 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31415 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31420 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31421 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31423 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31424 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31425 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31428 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31429 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31430 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31431 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31432 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31433 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31435 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31436 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31437 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31438 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31448 /* SSE2 MMX */
31449 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31452 /* SSE3 */
31453 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31454 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31456 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31457 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31458 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31459 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31460 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31461 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31463 /* SSSE3 */
31464 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31465 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31466 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31467 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31468 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31469 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31471 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31472 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31473 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31474 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31475 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31476 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31477 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31478 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31479 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31480 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31481 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31482 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31483 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31484 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31485 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31486 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31496 /* SSSE3. */
31497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31500 /* SSE4.1 */
31501 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31502 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31503 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31504 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31505 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31506 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31507 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31508 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31509 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31510 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31512 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31513 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31514 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31515 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31516 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31517 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31518 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31519 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31520 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31521 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31522 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31523 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31539 /* SSE4.1 */
31540 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31541 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31542 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31543 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31545 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31546 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31547 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31548 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31550 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31551 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31553 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31554 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31556 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31557 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31558 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31559 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31561 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31562 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31564 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31565 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31567 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31571 /* SSE4.2 */
31572 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31573 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31574 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31575 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31576 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31578 /* SSE4A */
31579 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31580 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31581 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31582 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31584 /* AES */
31585 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31586 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31588 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31589 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31590 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31591 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31593 /* PCLMUL */
31594 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31596 /* AVX */
31597 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31598 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31601 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31602 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31605 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31609 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31611 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31612 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31613 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31614 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31615 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31616 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31617 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31618 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31619 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31620 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31621 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31622 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31645 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31646 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31650 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31652 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31668 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31670 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31672 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31684 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31685 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31698 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31699 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31709 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31710 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31711 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31732 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31733 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31735 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31737 /* AVX2 */
31738 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31739 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31740 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31741 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31746 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31747 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31748 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31749 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31751 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31755 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31802 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31804 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31805 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31806 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31807 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31808 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31809 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31819 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31820 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31821 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31822 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31823 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31824 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31825 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31826 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31827 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31828 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31829 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31830 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31831 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31832 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31833 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31834 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31835 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31836 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31837 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31838 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31839 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31845 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31846 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31847 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31848 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31849 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31850 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31851 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31852 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31853 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31854 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31855 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31856 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31857 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31858 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31859 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31885 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31887 /* BMI */
31888 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31889 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31890 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31892 /* TBM */
31893 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31894 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31896 /* F16C */
31897 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31898 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31899 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31900 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31902 /* BMI2 */
31903 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31904 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31905 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31906 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31907 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31908 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31910 /* AVX512F */
31911 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31912 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31913 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31914 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31915 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31916 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31917 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31918 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31919 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31920 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31921 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31922 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31923 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31924 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31925 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31926 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31927 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31928 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31929 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31930 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31931 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31966 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31967 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
31994 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32077 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32078 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32079 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32080 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32112 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32117 /* Mask arithmetic operations */
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32129 /* SHA */
32130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32133 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32135 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32136 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32138 /* AVX512VL. */
32139 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32140 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32141 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32142 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32143 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32144 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32145 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32146 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32147 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32148 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32149 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32150 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32151 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32152 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32153 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32154 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32155 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32156 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32177 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32178 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32179 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32180 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32181 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32182 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32183 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32184 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32185 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32186 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32187 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32188 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32189 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32194 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32195 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32196 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32197 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32198 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32199 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32200 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32201 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32202 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32203 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32206 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32207 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32208 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32209 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32230 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32231 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32232 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32233 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32234 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32235 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32236 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32237 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32249 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32250 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32253 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32254 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32265 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32266 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32277 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32278 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32279 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32280 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32281 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32282 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32283 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32284 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32285 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32286 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32287 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32288 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32289 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32290 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32293 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32303 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32304 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32305 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32306 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32307 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32308 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32309 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32310 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32314 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32317 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32318 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32319 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32320 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32323 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32324 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32325 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32326 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32327 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32328 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32332 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32333 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32334 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32340 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32343 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32344 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32370 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32371 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32375 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32376 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32377 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32378 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32395 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32396 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32397 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32398 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32399 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32400 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32401 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32402 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32403 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32404 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32405 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32406 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32407 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32408 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32409 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32410 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32411 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32412 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32413 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32416 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32419 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32420 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32425 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32457 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32458 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32459 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32460 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32521 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32522 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32524 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32525 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32526 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32527 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32528 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32529 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32530 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32535 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32536 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32537 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32538 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32549 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32550 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32551 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32552 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32553 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32554 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32555 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32556 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32581 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32582 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32583 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32585 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32586 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32613 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32614 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32615 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32616 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32617 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32618 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32619 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32620 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32629 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32630 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32631 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32632 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32633 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32634 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32635 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32637 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32638 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32639 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32640 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32641 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32642 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32647 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32648 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32649 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32650 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32651 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32652 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32653 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32654 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32659 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32660 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32661 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32662 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32667 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32668 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32669 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32670 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32675 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32676 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32677 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32678 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32683 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32684 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32685 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32686 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32727 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32728 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32729 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32730 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32731 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32732 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32733 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32734 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32735 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32736 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32737 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32738 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32739 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32740 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32741 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32742 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32743 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32744 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32745 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32746 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32754 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32755 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32756 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32757 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32775 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32776 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32777 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32778 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32779 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32780 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32781 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32782 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32783 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32784 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32785 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32786 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32787 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32788 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32789 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32790 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32791 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32792 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32796 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32797 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32798 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32799 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32803 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32804 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32805 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32806 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32807 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32808 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32809 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32810 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32811 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32812 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32816 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32817 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32818 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32819 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32824 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32825 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32835 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32836 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32837 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32852 /* AVX512DQ. */
32853 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32854 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32855 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32856 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32857 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32858 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32859 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32860 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32861 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32862 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32863 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32864 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32865 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32866 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32867 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32868 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32869 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32870 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32871 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32872 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32873 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32874 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32875 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32876 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32877 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32878 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32879 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32880 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32881 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32882 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32883 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32885 /* AVX512BW. */
32886 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32887 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32888 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32889 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32890 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32891 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32892 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32893 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32894 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32895 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32896 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32897 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32898 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32899 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32900 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32901 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32902 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32903 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32904 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32905 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32906 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32907 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32908 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32909 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32910 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32911 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32912 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32913 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32914 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32915 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32916 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32917 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32918 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32919 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32920 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32921 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32922 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32923 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32924 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32925 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32926 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32927 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32928 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32929 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32930 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32931 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32932 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32933 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32934 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32935 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32936 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32937 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32938 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32939 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32940 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32941 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32942 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32943 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32944 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32945 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32946 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32947 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32948 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32949 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32950 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32951 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32952 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32953 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32954 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32955 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32956 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32957 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32958 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32959 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32960 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32961 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32962 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32963 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32964 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32965 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32966 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32967 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32968 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32969 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32970 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32971 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32972 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32973 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32974 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32975 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
32976 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
32978 /* AVX512IFMA */
32979 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32980 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32981 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32982 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32983 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32984 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32985 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32986 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32987 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32988 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32989 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32990 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32992 /* AVX512VBMI */
32993 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32994 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32995 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32996 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32997 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32998 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32999 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33000 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33001 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33002 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33003 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33004 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33005 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33006 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33007 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33008 };
33010 /* Builtins with rounding support. */
33012 {
33013 /* AVX512F */
33014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33033 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33035 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33042 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33044 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33094 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33096 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33098 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33100 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33102 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33104 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33106 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33108 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33134 /* AVX512ER */
33135 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33136 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33137 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33138 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33139 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33140 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33141 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33142 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33143 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33144 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33146 /* AVX512DQ. */
33147 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33148 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33149 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33150 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33151 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33152 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33153 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33154 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33155 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33156 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33157 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33158 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33159 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33160 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33161 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33162 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33163 };
33165 /* Bultins for MPX. */
33167 {
33168 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33169 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33170 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33171 };
33173 /* Const builtins for MPX. */
33175 {
33176 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33177 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33178 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33179 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33180 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33181 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33182 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33183 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33184 };
33186 /* FMA4 and XOP. */
33187 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33188 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33189 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33190 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33191 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33192 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33193 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33194 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33195 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33196 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33197 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33198 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33199 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33200 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33201 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33202 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33203 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33204 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33205 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33206 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33207 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33208 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33209 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33210 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33211 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33212 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33213 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33214 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33215 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33216 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33217 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33218 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33219 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33220 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33221 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33222 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33223 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33224 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33225 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33226 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33227 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33228 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33229 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33230 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33231 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33232 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33233 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33234 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33235 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33236 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33237 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33238 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33241 {
33282 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33283 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33284 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33285 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33286 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33287 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33288 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33290 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33291 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33292 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33293 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33294 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33295 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33296 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33298 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33300 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33301 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33302 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33303 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33304 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33305 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33306 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33440 };
33441 \f
33442 /* TM vector builtins. */
33444 /* Reuse the existing x86-specific `struct builtin_description' cause
33445 we're lazy. Add casts to make them fit. */
33447 {
33448 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33449 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33450 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33451 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33452 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33453 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33454 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33456 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33457 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33458 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33459 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33460 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33461 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33462 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33464 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33465 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33466 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33467 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33468 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33469 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33470 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33472 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33473 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33474 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33475 };
33477 /* TM callbacks. */
33479 /* Return the builtin decl needed to load a vector of TYPE. */
33481 static tree
33483 {
33485 {
33487 {
33494 }
33495 }
33497 }
33499 /* Return the builtin decl needed to store a vector of TYPE. */
33501 static tree
33503 {
33505 {
33507 {
33514 }
33515 }
33517 }
33518 \f
33519 /* Initialize the transactional memory vector load/store builtins. */
33521 static void
33523 {
33527 tree decl;
33534 /* If there are no builtins defined, we must be compiling in a
33535 language without trans-mem support. */
33539 /* Use whatever attributes a normal TM load has. */
33543 /* Use whatever attributes a normal TM store has. */
33547 /* Use whatever attributes a normal TM log has. */
33555 {
33559 {
33567 {
33570 }
33572 {
33575 }
33576 else
33577 {
33580 }
33582 /* The builtin without the prefix for
33583 calling it directly. */
33585 attrs);
33586 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33587 set the TYPE_ATTRIBUTES. */
33591 }
33592 }
33593 }
33595 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33596 in the current target ISA to allow the user to compile particular modules
33597 with different target specific options that differ from the command line
33598 options. */
33599 static void
33601 {
33606 /* Add all special builtins with variable number of operands. */
33610 {
33616 }
33618 /* Add all builtins with variable number of operands. */
33622 {
33628 }
33630 /* Add all builtins with rounding. */
33634 {
33640 }
33642 /* pcmpestr[im] insns. */
33646 {
33649 else
33652 }
33654 /* pcmpistr[im] insns. */
33658 {
33661 else
33664 }
33666 /* comi/ucomi insns. */
33668 {
33671 else
33674 }
33676 /* SSE */
33682 /* SSE or 3DNow!A */
33685 IX86_BUILTIN_MASKMOVQ);
33687 /* SSE2 */
33696 /* SSE3. */
33702 /* AES */
33716 /* PCLMUL */
33720 /* RDRND */
33727 IX86_BUILTIN_RDRAND64_STEP);
33729 /* AVX2 */
33731 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33732 IX86_BUILTIN_GATHERSIV2DF);
33735 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33736 IX86_BUILTIN_GATHERSIV4DF);
33739 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33740 IX86_BUILTIN_GATHERDIV2DF);
33743 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33744 IX86_BUILTIN_GATHERDIV4DF);
33747 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33748 IX86_BUILTIN_GATHERSIV4SF);
33751 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33752 IX86_BUILTIN_GATHERSIV8SF);
33755 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33756 IX86_BUILTIN_GATHERDIV4SF);
33759 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33760 IX86_BUILTIN_GATHERDIV8SF);
33763 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33764 IX86_BUILTIN_GATHERSIV2DI);
33767 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33768 IX86_BUILTIN_GATHERSIV4DI);
33771 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33772 IX86_BUILTIN_GATHERDIV2DI);
33775 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33776 IX86_BUILTIN_GATHERDIV4DI);
33779 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33780 IX86_BUILTIN_GATHERSIV4SI);
33783 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33784 IX86_BUILTIN_GATHERSIV8SI);
33787 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33788 IX86_BUILTIN_GATHERDIV4SI);
33791 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33792 IX86_BUILTIN_GATHERDIV8SI);
33795 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33796 IX86_BUILTIN_GATHERALTSIV4DF);
33799 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33800 IX86_BUILTIN_GATHERALTDIV8SF);
33803 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33804 IX86_BUILTIN_GATHERALTSIV4DI);
33807 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33808 IX86_BUILTIN_GATHERALTDIV8SI);
33810 /* AVX512F */
33812 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33813 IX86_BUILTIN_GATHER3SIV16SF);
33816 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33817 IX86_BUILTIN_GATHER3SIV8DF);
33820 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33821 IX86_BUILTIN_GATHER3DIV16SF);
33824 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33825 IX86_BUILTIN_GATHER3DIV8DF);
33828 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33829 IX86_BUILTIN_GATHER3SIV16SI);
33832 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33833 IX86_BUILTIN_GATHER3SIV8DI);
33836 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33837 IX86_BUILTIN_GATHER3DIV16SI);
33840 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33841 IX86_BUILTIN_GATHER3DIV8DI);
33844 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33845 IX86_BUILTIN_GATHER3ALTSIV8DF);
33848 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33849 IX86_BUILTIN_GATHER3ALTDIV16SF);
33852 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33853 IX86_BUILTIN_GATHER3ALTSIV8DI);
33856 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33857 IX86_BUILTIN_GATHER3ALTDIV16SI);
33860 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33861 IX86_BUILTIN_SCATTERSIV16SF);
33864 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33865 IX86_BUILTIN_SCATTERSIV8DF);
33868 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33869 IX86_BUILTIN_SCATTERDIV16SF);
33872 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33873 IX86_BUILTIN_SCATTERDIV8DF);
33876 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33877 IX86_BUILTIN_SCATTERSIV16SI);
33880 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33881 IX86_BUILTIN_SCATTERSIV8DI);
33884 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33885 IX86_BUILTIN_SCATTERDIV16SI);
33888 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33889 IX86_BUILTIN_SCATTERDIV8DI);
33891 /* AVX512VL */
33893 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33894 IX86_BUILTIN_GATHER3SIV2DF);
33897 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33898 IX86_BUILTIN_GATHER3SIV4DF);
33901 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33902 IX86_BUILTIN_GATHER3DIV2DF);
33905 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33906 IX86_BUILTIN_GATHER3DIV4DF);
33909 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33910 IX86_BUILTIN_GATHER3SIV4SF);
33913 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33914 IX86_BUILTIN_GATHER3SIV8SF);
33917 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33918 IX86_BUILTIN_GATHER3DIV4SF);
33921 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33922 IX86_BUILTIN_GATHER3DIV8SF);
33925 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33926 IX86_BUILTIN_GATHER3SIV2DI);
33929 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33930 IX86_BUILTIN_GATHER3SIV4DI);
33933 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33934 IX86_BUILTIN_GATHER3DIV2DI);
33937 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33938 IX86_BUILTIN_GATHER3DIV4DI);
33941 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33942 IX86_BUILTIN_GATHER3SIV4SI);
33945 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33946 IX86_BUILTIN_GATHER3SIV8SI);
33949 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33950 IX86_BUILTIN_GATHER3DIV4SI);
33953 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33954 IX86_BUILTIN_GATHER3DIV8SI);
33957 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33958 IX86_BUILTIN_GATHER3ALTSIV4DF);
33961 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33962 IX86_BUILTIN_GATHER3ALTDIV8SF);
33965 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33966 IX86_BUILTIN_GATHER3ALTSIV4DI);
33969 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33970 IX86_BUILTIN_GATHER3ALTDIV8SI);
33973 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
33974 IX86_BUILTIN_SCATTERSIV8SF);
33977 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
33978 IX86_BUILTIN_SCATTERSIV4SF);
33981 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
33982 IX86_BUILTIN_SCATTERSIV4DF);
33985 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
33986 IX86_BUILTIN_SCATTERSIV2DF);
33989 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
33990 IX86_BUILTIN_SCATTERDIV8SF);
33993 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
33994 IX86_BUILTIN_SCATTERDIV4SF);
33997 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
33998 IX86_BUILTIN_SCATTERDIV4DF);
34001 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34002 IX86_BUILTIN_SCATTERDIV2DF);
34005 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34006 IX86_BUILTIN_SCATTERSIV8SI);
34009 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34010 IX86_BUILTIN_SCATTERSIV4SI);
34013 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34014 IX86_BUILTIN_SCATTERSIV4DI);
34017 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34018 IX86_BUILTIN_SCATTERSIV2DI);
34021 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34022 IX86_BUILTIN_SCATTERDIV8SI);
34025 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34026 IX86_BUILTIN_SCATTERDIV4SI);
34029 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34030 IX86_BUILTIN_SCATTERDIV4DI);
34033 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34034 IX86_BUILTIN_SCATTERDIV2DI);
34036 /* AVX512PF */
34038 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34039 IX86_BUILTIN_GATHERPFDPD);
34041 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34042 IX86_BUILTIN_GATHERPFDPS);
34044 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34045 IX86_BUILTIN_GATHERPFQPD);
34047 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34048 IX86_BUILTIN_GATHERPFQPS);
34050 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34051 IX86_BUILTIN_SCATTERPFDPD);
34053 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34054 IX86_BUILTIN_SCATTERPFDPS);
34056 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34057 IX86_BUILTIN_SCATTERPFQPD);
34059 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34060 IX86_BUILTIN_SCATTERPFQPS);
34062 /* SHA */
34078 /* RTM. */
34082 /* MMX access to the vec_init patterns. */
34087 V4HI_FTYPE_HI_HI_HI_HI,
34088 IX86_BUILTIN_VEC_INIT_V4HI);
34091 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34092 IX86_BUILTIN_VEC_INIT_V8QI);
34094 /* Access to the vec_extract patterns. */
34116 /* Access to the vec_set patterns. */
34137 /* RDSEED */
34146 /* ADCX */
34151 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34152 IX86_BUILTIN_ADDCARRYX64);
34154 /* SBB */
34159 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34160 IX86_BUILTIN_SBB64);
34162 /* Read/write FLAGS. */
34172 /* CLFLUSHOPT. */
34176 /* CLWB. */
34180 /* Add FMA4 multi-arg argument instructions */
34182 {
34188 }
34189 }
34191 static void
34193 {
34196 tree decl;
34202 {
34209 /* With no leaf and nothrow flags for MPX builtins
34210 abnormal edges may follow its call when setjmp
34211 presents in the function. Since we may have a lot
34212 of MPX builtins calls it causes lots of useless
34213 edges and enormous PHI nodes. To avoid this we mark
34214 MPX builtins as leaf and nothrow. */
34216 {
34218 NULL_TREE);
34220 }
34221 else
34222 {
34225 }
34226 }
34231 {
34239 {
34241 NULL_TREE);
34243 }
34244 else
34245 {
34248 }
34249 }
34250 }
34252 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34253 to return a pointer to VERSION_DECL if the outcome of the expression
34254 formed by PREDICATE_CHAIN is true. This function will be called during
34255 version dispatch to decide which function version to execute. It returns
34256 the basic block at the end, to which more conditions can be added. */
34258 static basic_block
34261 {
34262 gimple return_stmt;
34264 gimple convert_stmt;
34265 gimple call_cond_stmt;
34266 gimple if_else_stmt;
34272 gimple_seq gseq;
34289 {
34297 }
34300 {
34315 else
34316 {
34317 gimple assign_stmt;
34318 /* Use MIN_EXPR to check if any integer is zero?.
34319 and_expr_var = min_expr <cond_var, and_expr_var> */
34327 }
34328 }
34331 integer_zero_node,
34361 }
34363 /* This parses the attribute arguments to target in DECL and determines
34364 the right builtin to use to match the platform specification.
34365 It returns the priority value for this version decl. If PREDICATE_LIST
34366 is not NULL, it stores the list of cpu features that need to be checked
34367 before dispatching this function. */
34369 static unsigned int
34371 {
34372 tree attrs;
34374 tree target_node;
34381 /* Priority of i386 features, greater value is higher priority. This is
34382 used to decide the order in which function dispatch must happen. For
34383 instance, a version specialized for SSE4.2 should be checked for dispatch
34384 before a version for SSE3, as SSE4.2 implies SSE3. */
34385 enum feature_priority
34386 {
34388 P_MMX,
34389 P_SSE,
34390 P_SSE2,
34391 P_SSE3,
34392 P_SSSE3,
34393 P_PROC_SSSE3,
34394 P_SSE4_A,
34395 P_PROC_SSE4_A,
34396 P_SSE4_1,
34397 P_SSE4_2,
34398 P_PROC_SSE4_2,
34399 P_POPCNT,
34400 P_AVX,
34401 P_PROC_AVX,
34402 P_BMI,
34403 P_PROC_BMI,
34404 P_FMA4,
34405 P_XOP,
34406 P_PROC_XOP,
34407 P_FMA,
34408 P_PROC_FMA,
34409 P_BMI2,
34410 P_AVX2,
34411 P_PROC_AVX2,
34412 P_AVX512F,
34413 P_PROC_AVX512F
34414 };
34418 /* These are the target attribute strings for which a dispatcher is
34419 available, from fold_builtin_cpu. */
34421 static struct _feature_list
34422 {
34425 }
34427 {
34445 };
34448 static unsigned int NUM_FEATURES
34464 /* Return priority zero for default function. */
34468 /* Handle arch= if specified. For priority, set it to be 1 more than
34469 the best instruction set the processor can handle. For instance, if
34470 there is a version for atom and a version for ssse3 (the highest ISA
34471 priority for atom), the atom version must be checked for dispatch
34472 before the ssse3 version. */
34474 {
34484 {
34486 {
34494 else
34495 /* We translate "arch=corei7" and "arch=nehalem" to
34496 "corei7" so that it will be mapped to M_INTEL_COREI7
34497 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34504 else
34511 else
34555 }
34556 }
34561 {
34565 }
34568 {
34570 /* For a C string literal the length includes the trailing NULL. */
34573 predicate_chain);
34574 }
34575 }
34577 /* Process feature name. */
34584 {
34585 /* Do not process "arch=" */
34587 {
34590 }
34592 {
34594 {
34596 {
34601 predicate_chain);
34602 }
34603 /* Find the maximum priority feature. */
34608 }
34609 }
34611 {
34615 }
34617 }
34621 {
34624 attrs_str);
34626 }
34628 {
34631 }
34634 }
34636 /* This compares the priority of target features in function DECL1
34637 and DECL2. It returns positive value if DECL1 is higher priority,
34638 negative value if DECL2 is higher priority and 0 if they are the
34639 same. */
34641 static int
34643 {
34648 }
34650 /* V1 and V2 point to function versions with different priorities
34651 based on the target ISA. This function compares their priorities. */
34653 static int
34655 {
34657 {
34658 tree version_decl;
34659 tree predicate_chain;
34666 }
34668 /* This function generates the dispatch function for
34669 multi-versioned functions. DISPATCH_DECL is the function which will
34670 contain the dispatch logic. FNDECLS are the function choices for
34671 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34672 in DISPATCH_DECL in which the dispatch code is generated. */
34674 static int
34678 {
34679 tree default_decl;
34680 gimple ifunc_cpu_init_stmt;
34681 gimple_seq gseq;
34683 tree ele;
34689 struct _function_version_info
34690 {
34691 tree version_decl;
34692 tree predicate_chain;
34700 /*fndecls_p is actually a vector. */
34703 /* At least one more version other than the default. */
34710 /* The first version in the vector is the default decl. */
34716 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34717 constructors, so explicity call __builtin_cpu_init here. */
34728 {
34732 /* Get attribute string, parse it and find the right predicate decl.
34733 The predicate function could be a lengthy combination of many
34734 features, like arch-type and various isa-variants. */
34745 actual_versions++;
34746 }
34748 /* Sort the versions according to descending order of dispatch priority. The
34749 priority is based on the ISA. This is not a perfect solution. There
34750 could still be ambiguity. If more than one function version is suitable
34751 to execute, which one should be dispatched? In future, allow the user
34752 to specify a dispatch priority next to the version. */
34762 /* dispatch default version at the end. */
34768 }
34770 /* Comparator function to be used in qsort routine to sort attribute
34771 specification strings to "target". */
34773 static int
34775 {
34779 }
34781 /* ARGLIST is the argument to target attribute. This function tokenizes
34782 the comma separated arguments, sorts them and returns a string which
34783 is a unique identifier for the comma separated arguments. It also
34784 replaces non-identifier characters "=,-" with "_". */
34788 {
34789 tree arg;
34798 {
34803 argnum++;
34806 argnum++;
34807 }
34812 {
34818 }
34820 /* Replace "=,-" with "_". */
34833 {
34835 i++;
34837 }
34844 {
34849 }
34854 }
34856 /* This function changes the assembler name for functions that are
34857 versions. If DECL is a function version and has a "target"
34858 attribute, it appends the attribute string to its assembler name. */
34860 static tree
34862 {
34863 tree version_attr;
34871 "Function versions cannot be marked as gnu_inline,"
34880 /* target attribute string cannot be NULL. */
34884 version_string
34895 /* Allow assembler name to be modified if already set. */
34903 }
34905 /* This function returns true if FN1 and FN2 are versions of the same function,
34906 that is, the target strings of the function decls are different. This assumes
34907 that FN1 and FN2 have the same signature. */
34909 static bool
34911 {
34923 /* At least one function decl should have the target attribute specified. */
34927 /* Diagnose missing target attribute if one of the decls is already
34928 multi-versioned. */
34930 {
34932 {
34934 {
34939 }
34942 fn2);
34945 /* Prevent diagnosing of the same error multiple times. */
34950 }
34952 }
34957 /* The sorted target strings must be different for fn1 and fn2
34958 to be versions. */
34961 else
34968 }
34970 static tree
34972 {
34973 /* For function version, add the target suffix to the assembler name. */
34977 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
34979 #endif
34982 }
34984 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
34985 is true, append the full path name of the source file. */
34989 {
34997 /* Get a unique name that can be used globally without any chances
34998 of collision at link time. */
35008 /* Use '.' to concatenate names as it is demangler friendly. */
35011 suffix);
35012 else
35016 }
35018 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35020 /* Make a dispatcher declaration for the multi-versioned function DECL.
35021 Calls to DECL function will be replaced with calls to the dispatcher
35022 by the front-end. Return the decl created. */
35024 static tree
35026 {
35027 tree func_decl;
35047 /* Mark this func as external, the resolver will flip it again if
35048 it gets generated. */
35050 /* This will be of type IFUNCs have to be externally visible. */
35054 }
35056 #endif
35058 /* Returns true if decl is multi-versioned and DECL is the default function,
35059 that is it is not tagged with target specific optimization. */
35061 static bool
35063 {
35072 }
35074 /* Make a dispatcher declaration for the multi-versioned function DECL.
35075 Calls to DECL function will be replaced with calls to the dispatcher
35076 by the front-end. Returns the decl of the dispatcher function. */
35078 static tree
35080 {
35102 /* Find the default version and make it the first node. */
35104 /* Go to the beginning of the chain. */
35109 {
35114 }
35116 /* If there is no default node, just return NULL. */
35120 /* Make default info the first node. */
35122 {
35129 }
35133 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35135 {
35140 /* Right now, the dispatching is done via ifunc. */
35146 dispatcher_version_info
35151 /* Set the dispatcher for all the versions. */
35154 {
35157 }
35158 }
35159 else
35160 #endif
35161 {
35163 "multiversioning needs ifunc which is not supported "
35165 }
35168 }
35170 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35171 it to CHAIN. */
35173 static tree
35175 {
35176 tree attr_name;
35177 tree attr_arg_name;
35178 tree attr_args;
35179 tree attr;
35186 }
35188 /* Make the resolver function decl to dispatch the versions of
35189 a multi-versioned function, DEFAULT_DECL. Create an
35190 empty basic block in the resolver and store the pointer in
35191 EMPTY_BB. Return the decl of the resolver function. */
35193 static tree
35197 {
35202 /* IFUNC's have to be globally visible. So, if the default_decl is
35203 not, then the name of the IFUNC should be made unique. */
35207 /* Append the filename to the resolver function if the versions are
35208 not externally visible. This is because the resolver function has
35209 to be externally visible for the loader to find it. So, appending
35210 the filename will prevent conflicts with a resolver function from
35211 another module which is based on the same version name. */
35214 /* The resolver function should return a (void *). */
35225 /* IFUNC resolvers have to be externally visible. */
35229 /* Resolver is not external, body is generated. */
35239 {
35240 /* In this case, each translation unit with a call to this
35241 versioned function will put out a resolver. Ensure it
35242 is comdat to keep just one copy. */
35245 }
35246 /* Build result decl and add to function_decl. */
35262 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35266 /* Create the alias for dispatch to resolver here. */
35267 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35271 }
35273 /* Generate the dispatching code body to dispatch multi-versioned function
35274 DECL. The target hook is called to process the "target" attributes and
35275 provide the code to dispatch the right function at run-time. NODE points
35276 to the dispatcher decl whose body will be created. */
35278 static tree
35280 {
35281 tree resolver_decl;
35282 basic_block empty_bb;
35283 tree default_ver_decl;
35299 /* The first version in the chain corresponds to the default version. */
35302 /* node is going to be an alias, so remove the finalized bit. */
35316 {
35318 /* Check for virtual functions here again, as by this time it should
35319 have been determined if this function needs a vtable index or
35320 not. This happens for methods in derived classes that override
35321 virtual methods in base classes but are not explicitly marked as
35322 virtual. */
35327 }
35333 }
35334 /* This builds the processor_model struct type defined in
35335 libgcc/config/i386/cpuinfo.c */
35337 static tree
35339 {
35346 /* The first 3 fields are unsigned int. */
35348 {
35354 }
35356 /* The last field is an array of unsigned integers of size one. */
35367 }
35369 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35371 static tree
35373 {
35374 tree new_decl;
35377 VAR_DECL,
35379 type);
35392 }
35394 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35395 into an integer defined in libgcc/config/i386/cpuinfo.c */
35397 static tree
35399 {
35405 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35406 enum processor_features
35407 {
35409 F_MMX,
35410 F_POPCNT,
35411 F_SSE,
35412 F_SSE2,
35413 F_SSE3,
35414 F_SSSE3,
35415 F_SSE4_1,
35416 F_SSE4_2,
35417 F_AVX,
35418 F_AVX2,
35419 F_SSE4_A,
35420 F_FMA4,
35421 F_XOP,
35422 F_FMA,
35423 F_AVX512F,
35424 F_BMI,
35425 F_BMI2,
35426 F_MAX
35427 };
35429 /* These are the values for vendor types and cpu types and subtypes
35430 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35431 the corresponding start value. */
35432 enum processor_model
35433 {
35435 M_AMD,
35436 M_CPU_TYPE_START,
35437 M_INTEL_BONNELL,
35438 M_INTEL_CORE2,
35439 M_INTEL_COREI7,
35440 M_AMDFAM10H,
35441 M_AMDFAM15H,
35442 M_INTEL_SILVERMONT,
35443 M_INTEL_KNL,
35444 M_AMD_BTVER1,
35445 M_AMD_BTVER2,
35446 M_CPU_SUBTYPE_START,
35447 M_INTEL_COREI7_NEHALEM,
35448 M_INTEL_COREI7_WESTMERE,
35449 M_INTEL_COREI7_SANDYBRIDGE,
35450 M_AMDFAM10H_BARCELONA,
35451 M_AMDFAM10H_SHANGHAI,
35452 M_AMDFAM10H_ISTANBUL,
35453 M_AMDFAM15H_BDVER1,
35454 M_AMDFAM15H_BDVER2,
35455 M_AMDFAM15H_BDVER3,
35456 M_AMDFAM15H_BDVER4,
35457 M_INTEL_COREI7_IVYBRIDGE,
35458 M_INTEL_COREI7_HASWELL,
35459 M_INTEL_COREI7_BROADWELL
35460 };
35462 static struct _arch_names_table
35463 {
35466 }
35468 {
35495 };
35497 static struct _isa_names_table
35498 {
35501 }
35503 {
35522 };
35536 {
35537 /* *args must be a expr that can contain other EXPRS leading to a
35538 STRING_CST. */
35540 {
35543 }
35545 }
35550 {
35551 tree ref;
35552 tree field;
35553 tree final;
35556 unsigned int NUM_ARCH_NAMES
35565 {
35569 }
35574 /* CPU types are stored in the next field. */
35577 {
35580 }
35582 /* CPU subtypes are stored in the next field. */
35584 {
35587 }
35589 /* Get the appropriate field in __cpu_model. */
35593 /* Check the value. */
35597 }
35599 {
35600 tree ref;
35601 tree array_elt;
35602 tree field;
35603 tree final;
35606 unsigned int NUM_ISA_NAMES
35615 {
35619 }
35622 /* Get the last field, which is __cpu_features. */
35626 /* Get the appropriate field: __cpu_model.__cpu_features */
35630 /* Access the 0th element of __cpu_features array. */
35635 /* Return __cpu_model.__cpu_features[0] & field_val */
35639 }
35641 }
35643 static tree
35646 {
35648 {
35653 {
35656 }
35657 }
35659 #ifdef SUBTARGET_FOLD_BUILTIN
35661 #endif
35664 }
35666 /* Make builtins to detect cpu type and features supported. NAME is
35667 the builtin name, CODE is the builtin code, and FTYPE is the function
35668 type of the builtin. */
35670 static void
35673 {
35674 tree decl;
35675 tree type;
35683 }
35685 /* Make builtins to get CPU type and features supported. The created
35686 builtins are :
35688 __builtin_cpu_init (), to detect cpu type and features,
35689 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35690 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35691 */
35693 static void
35695 {
35702 }
35704 /* Internal method for ix86_init_builtins. */
35706 static void
35708 {
35720 sysv_va_ref =
35723 fnvoid_va_end_ms =
35725 fnvoid_va_start_ms =
35727 fnvoid_va_end_sysv =
35729 fnvoid_va_start_sysv =
35731 NULL_TREE);
35732 fnvoid_va_copy_ms =
35734 NULL_TREE);
35735 fnvoid_va_copy_sysv =
35751 }
35753 static void
35755 {
35758 /* The __float80 type. */
35761 {
35762 /* The __float80 type. */
35767 }
35770 /* The __float128 type. */
35776 /* This macro is built by i386-builtin-types.awk. */
35777 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35778 }
35780 static void
35782 {
35783 tree t;
35787 /* Builtins to get CPU type and features. */
35790 /* TFmode support builtins. */
35796 /* We will expand them to normal call if SSE isn't available since
35797 they are used by libgcc. */
35817 #ifdef SUBTARGET_INIT_BUILTINS
35818 SUBTARGET_INIT_BUILTINS;
35819 #endif
35820 }
35822 /* Return the ix86 builtin for CODE. */
35824 static tree
35826 {
35831 }
35833 /* Errors in the source file can cause expand_expr to return const0_rtx
35834 where we expect a vector. To avoid crashing, use one of the vector
35835 clear instructions. */
35836 static rtx
35838 {
35842 }
35844 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35846 static rtx
35848 {
35849 rtx pat;
35869 {
35873 }
35887 }
35889 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35891 static rtx
35895 {
35896 rtx pat;
35904 rtx op;
35905 machine_mode mode;
35911 {
35991 }
36001 {
36008 {
36010 {
36013 {
36031 xop_rotl:
36033 {
36036 gcc_checking_assert
36038 }
36039 else
36040 {
36041 gcc_checking_assert
36052 }
36056 }
36057 }
36058 }
36059 else
36060 {
36061 non_constant:
36065 /* If we aren't optimizing, only allow one memory operand to be
36066 generated. */
36068 num_memory++;
36076 }
36080 }
36083 {
36094 else
36095 {
36101 }
36114 }
36121 }
36123 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36124 insns with vec_merge. */
36126 static rtx
36128 rtx target)
36129 {
36130 rtx pat;
36157 }
36159 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36161 static rtx
36164 {
36165 rtx pat;
36170 rtx op2;
36181 /* Swap operands if we have a comparison that isn't available in
36182 hardware. */
36204 }
36206 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36208 static rtx
36210 rtx target)
36211 {
36212 rtx pat;
36226 /* Swap operands if we have a comparison that isn't available in
36227 hardware. */
36250 const0_rtx)));
36253 }
36255 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36257 static rtx
36259 rtx target)
36260 {
36261 rtx pat;
36286 }
36288 static rtx
36291 {
36292 rtx pat;
36297 rtx op2;
36324 }
36326 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36328 static rtx
36330 rtx target)
36331 {
36332 rtx pat;
36365 const0_rtx)));
36368 }
36370 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36372 static rtx
36375 {
36376 rtx pat;
36414 {
36417 }
36420 {
36429 }
36431 {
36440 }
36441 else
36442 {
36449 }
36457 {
36462 emit_insn
36466 FLAGS_REG),
36467 const0_rtx)));
36469 }
36470 else
36472 }
36475 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36477 static rtx
36480 {
36481 rtx pat;
36509 {
36512 }
36515 {
36524 }
36526 {
36535 }
36536 else
36537 {
36544 }
36552 {
36557 emit_insn
36561 FLAGS_REG),
36562 const0_rtx)));
36564 }
36565 else
36567 }
36569 /* Subroutine of ix86_expand_builtin to take care of insns with
36570 variable number of operands. */
36572 static rtx
36575 {
36581 struct
36582 {
36583 rtx op;
36584 machine_mode mode;
36595 {
37305 }
37310 {
37313 }
37316 {
37323 }
37324 else
37325 {
37328 }
37331 {
37338 {
37339 /* SIMD shift insns take either an 8-bit immediate or
37340 register as count. But builtin functions take int as
37341 count. If count doesn't match, we put it in register. */
37343 {
37347 }
37348 }
37351 {
37354 {
37463 {
37467 {
37470 }
37476 }
37478 }
37479 }
37480 else
37481 {
37485 /* If we aren't optimizing, only allow one memory operand to
37486 be generated. */
37488 num_memory++;
37491 {
37494 }
37495 else
37496 {
37499 }
37500 }
37504 }
37507 {
37532 }
37539 }
37541 /* Transform pattern of following layout:
37542 (parallel [
37543 set (A B)
37544 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37545 ])
37546 into:
37547 (set (A B))
37549 Or:
37550 (parallel [ A B
37551 ...
37552 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37553 ...
37554 ])
37555 into:
37556 (parallel [ A B ... ]) */
37558 static rtx
37560 {
37567 {
37576 }
37577 else
37578 {
37584 {
37589 }
37591 /* No more than 1 occurence was removed. */
37595 }
37596 }
37598 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37599 with rounding. */
37600 static rtx
37603 {
37620 /* See avxintrin.h for values. */
37622 {
37626 };
37628 {
37633 };
37636 {
37639 }
37641 {
37644 }
37647 {
37650 }
37673 ? CODE_FOR_sse_ucomi_round
37680 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37682 {
37688 }
37689 else
37690 {
37693 }
37699 set_dst,
37700 const0_rtx)));
37703 }
37705 static rtx
37708 {
37709 rtx pat;
37711 struct
37712 {
37713 rtx op;
37714 machine_mode mode;
37723 {
37806 }
37816 {
37823 {
37825 {
37827 {
37843 }
37844 }
37845 }
37847 {
37849 {
37852 }
37854 /* If there is no rounding use normal version of the pattern. */
37857 }
37858 else
37859 {
37864 {
37867 }
37868 else
37869 {
37872 }
37873 }
37877 }
37880 {
37905 }
37915 }
37917 /* Subroutine of ix86_expand_builtin to take care of special insns
37918 with variable number of operands. */
37920 static rtx
37923 {
37924 tree arg;
37928 struct
37929 {
37930 rtx op;
37931 machine_mode mode;
37940 {
37980 {
37988 }
38007 /* Reserve memory operand for target. */
38010 {
38011 /* These builtins and instructions require the memory
38012 to be properly aligned. */
38031 }
38060 {
38061 /* These builtins and instructions require the memory
38062 to be properly aligned. */
38079 }
38080 /* FALLTHRU */
38118 /* Reserve memory operand for target. */
38145 {
38146 /* These builtins and instructions require the memory
38147 to be properly aligned. */
38170 }
38183 }
38188 {
38193 {
38196 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38197 on it. Try to improve it using get_pointer_alignment,
38198 and if the special builtin is one that requires strict
38199 mode alignment, also from it's GET_MODE_ALIGNMENT.
38200 Failure to do so could lead to ix86_legitimate_combined_insn
38201 rejecting all changes to such insns. */
38207 }
38208 else
38211 }
38212 else
38213 {
38220 }
38223 {
38232 {
38234 {
38240 else
38243 }
38244 }
38245 else
38246 {
38248 {
38249 /* This must be the memory operand. */
38252 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38253 on it. Try to improve it using get_pointer_alignment,
38254 and if the special builtin is one that requires strict
38255 mode alignment, also from it's GET_MODE_ALIGNMENT.
38256 Failure to do so could lead to ix86_legitimate_combined_insn
38257 rejecting all changes to such insns. */
38263 }
38264 else
38265 {
38266 /* This must be register. */
38272 else
38273 {
38276 }
38277 }
38278 }
38282 }
38285 {
38300 }
38306 }
38308 /* Return the integer constant in ARG. Constrain it to be in the range
38309 of the subparts of VEC_TYPE; issue an error if not. */
38311 static int
38313 {
38318 {
38321 }
38324 }
38326 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38327 ix86_expand_vector_init. We DO have language-level syntax for this, in
38328 the form of (type){ init-list }. Except that since we can't place emms
38329 instructions from inside the compiler, we can't allow the use of MMX
38330 registers unless the user explicitly asks for it. So we do *not* define
38331 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38332 we have builtins invoked by mmintrin.h that gives us license to emit
38333 these sorts of instructions. */
38335 static rtx
38337 {
38347 {
38350 }
38357 }
38359 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38360 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38361 had a language-level syntax for referencing vector elements. */
38363 static rtx
38365 {
38369 rtx op0;
38389 }
38391 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38392 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38393 a language-level syntax for referencing vector elements. */
38395 static rtx
38397 {
38421 /* OP0 is the source of these builtin functions and shouldn't be
38422 modified. Create a copy, use it and return it as target. */
38428 }
38430 /* Emit conditional move of SRC to DST with condition
38431 OP1 CODE OP2. */
38432 static void
38434 {
38435 rtx t;
38438 {
38443 }
38444 else
38445 {
38451 }
38452 }
38454 /* Choose max of DST and SRC and put it to DST. */
38455 static void
38457 {
38459 }
38461 /* Expand an expression EXP that calls a built-in function,
38462 with result going to TARGET if that's convenient
38463 (and in mode MODE if that's convenient).
38464 SUBTARGET may be used as the target for computing one of EXP's operands.
38465 IGNORE is nonzero if the value is to be ignored. */
38467 static rtx
38470 {
38480 /* For CPU builtins that can be folded, fold first and expand the fold. */
38482 {
38484 {
38485 /* Make it call __cpu_indicator_init in libgcc. */
38491 }
38494 {
38499 }
38500 }
38502 /* Determine whether the builtin function is available under the current ISA.
38503 Originally the builtin was not created if it wasn't applicable to the
38504 current ISA based on the command line switches. With function specific
38505 options, we need to check in the context of the function making the call
38506 whether it is supported. */
38509 {
38515 else
38516 {
38520 }
38522 }
38525 {
38543 /* Builtin arg1 is size of block but instruction op1 should
38544 be (size - 1). */
38635 /* If no bounds were specified for returned value,
38636 then use INIT bounds. It usually happens when
38637 some built-in function is expanded. */
38639 {
38648 }
38654 {
38657 /* Return value and lb. */
38659 /* Bounds. */
38661 /* Size. */
38668 /* Size was passed but we need to use (size - 1) as for bndmk. */
38672 /* Add LB to size and inverse to get UB. */
38682 /* We need to move bounds to memory before any computations. */
38685 else
38686 {
38689 }
38691 /* Generate mem expression to be used for access to LB and UB. */
38697 /* Compute LB. */
38702 /* Compute UB. UB is stored in 1's complement form. Therefore
38703 we also use max here. */
38712 }
38715 {
38733 /* Put first bounds to temporaries. */
38737 {
38741 }
38742 else
38743 {
38747 }
38749 /* Put second bounds to temporaries. */
38753 {
38757 }
38758 else
38759 {
38763 }
38765 /* Compute LB. */
38769 /* Compute UB. UB is stored in 1's complement form. Therefore
38770 we also use max here. */
38777 }
38780 {
38781 tree name;
38782 rtx symbol;
38800 }
38803 {
38814 /* We need to move bounds to memory first. */
38817 else
38818 {
38821 }
38823 /* Generate mem expression to access LB and load it. */
38828 }
38831 {
38842 /* We need to move bounds to memory first. */
38845 else
38846 {
38849 }
38851 /* Generate mem expression to access UB. */
38854 /* We need to inverse all bits of UB. */
38861 }
38866 ? CODE_FOR_mmx_maskmovq
38868 /* Note the arg order is different from the operand order. */
38989 {
38990 REAL_VALUE_TYPE inf;
38991 rtx tmp;
39003 }
39013 {
39019 insn = (TARGET_64BIT
39023 }
39025 {
39026 insn = (TARGET_64BIT
39030 }
39031 else
39032 {
39035 insn = (TARGET_64BIT
39043 {
39046 }
39048 }
39051 {
39052 /* mode is VOIDmode if __builtin_rd* has been called
39053 without lhs. */
39057 }
39060 {
39065 }
39078 {
39099 }
39105 {
39108 }
39134 {
39137 }
39143 {
39147 {
39186 }
39191 }
39192 else
39193 {
39195 {
39216 }
39218 }
39248 ? CODE_FOR_tbm_bextri_si
39251 {
39254 }
39255 else
39256 {
39265 }
39281 rdrand_step:
39288 {
39291 }
39297 /* Emit SImode conditional move. */
39299 {
39302 }
39305 else
39313 const0_rtx);
39332 rdseed_step:
39339 {
39342 }
39348 const0_rtx);
39377 addcarryx:
39385 /* Generate CF from input operand. */
39390 /* Gen ADCX instruction to compute X+Y+CF. */
39405 /* Store the result. */
39408 {
39411 }
39414 /* Return current CF value. */
39456 kortest:
39470 /* Emit kortest. */
39472 /* And use setcc to return result from flags. */
39730 gather_gen:
39731 rtx half;
39744 /* Note the arg order is different from the operand order. */
39755 else
39759 {
39783 else
39790 {
39795 }
39804 else
39811 {
39816 }
39820 }
39822 /* Force memory operand only with base register here. But we
39823 don't want to do it on memory operand for other builtin
39824 functions. */
39834 {
39837 }
39838 else
39839 {
39842 }
39844 {
39847 }
39849 /* Optimize. If mask is known to have all high bits set,
39850 replace op0 with pc_rtx to signal that the instruction
39851 overwrites the whole destination and doesn't use its
39852 previous contents. */
39854 {
39856 {
39859 }
39861 {
39864 {
39868 negative++;
39871 negative++;
39872 }
39875 }
39878 {
39879 /* Recognize also when mask is like:
39880 __v2df src = _mm_setzero_pd ();
39881 __v2df mask = _mm_cmpeq_pd (src, src);
39882 or
39883 __v8sf src = _mm256_setzero_ps ();
39884 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39885 as that is a cheaper way to load all ones into
39886 a register than having to load a constant from
39887 memory. */
39890 {
39895 {
39902 /* FALLTHRU */
39912 }
39913 }
39914 }
39915 }
39923 {
39949 }
39952 scatter_gen:
39968 /* Force memory operand only with base register here. But we
39969 don't want to do it on memory operand for other builtin
39970 functions. */
39977 {
39980 }
39981 else
39982 {
39985 }
39994 {
39997 }
40006 vec_prefetch_gen:
40024 {
40027 }
40029 {
40032 }
40037 /* Force memory operand only with base register here. But we
40038 don't want to do it on memory operand for other builtin
40039 functions. */
40046 {
40049 }
40052 {
40055 }
40071 {
40074 }
40080 }
40093 {
40097 /* Emit a normal call if SSE isn't available. */
40101 }
40130 }
40132 /* This returns the target-specific builtin with code CODE if
40133 current_function_decl has visibility on this builtin, which is checked
40134 using isa flags. Returns NULL_TREE otherwise. */
40137 {
40141 /* Determine the isa flags of current_function_decl. */
40153 else
40155 }
40157 /* Return function decl for target specific builtin
40158 for given MPX builtin passed i FCODE. */
40159 static tree
40161 {
40163 {
40199 }
40202 }
40204 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40206 Return an address to be used to load/store bounds for pointer
40207 passed in SLOT.
40209 SLOT_NO is an integer constant holding number of a target
40210 dependent special slot to be used in case SLOT is not a memory.
40212 SPECIAL_BASE is a pointer to be used as a base of fake address
40213 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40214 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40216 static rtx
40218 {
40221 /* NULL slot means we pass bounds for pointer not passed to the
40222 function at all. Register slot means we pass pointer in a
40223 register. In both these cases bounds are passed via Bounds
40224 Table. Since we do not have actual pointer stored in memory,
40225 we have to use fake addresses to access Bounds Table. We
40226 start with (special_base - sizeof (void*)) and decrease this
40227 address by pointer size to get addresses for other slots. */
40229 {
40233 }
40234 /* If pointer is passed in a memory then its address is used to
40235 access Bounds Table. */
40237 {
40241 }
40242 else
40246 }
40248 /* Expand pass uses this hook to load bounds for function parameter
40249 PTR passed in SLOT in case its bounds are not passed in a register.
40251 If SLOT is a memory, then bounds are loaded as for regular pointer
40252 loaded from memory. PTR may be NULL in case SLOT is a memory.
40253 In such case value of PTR (if required) may be loaded from SLOT.
40255 If SLOT is NULL or a register then SLOT_NO is an integer constant
40256 holding number of the target dependent special slot which should be
40257 used to obtain bounds.
40259 Return loaded bounds. */
40261 static rtx
40263 {
40265 rtx addr;
40267 /* Get address to be used to access Bounds Table. Special slots start
40268 at the location of return address of the current function. */
40271 /* Load pointer value from a memory if we don't have it. */
40273 {
40276 }
40283 }
40285 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40286 passed in SLOT in case BOUNDS are not passed in a register.
40288 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40289 stored in memory. PTR may be NULL in case SLOT is a memory.
40290 In such case value of PTR (if required) may be loaded from SLOT.
40292 If SLOT is NULL or a register then SLOT_NO is an integer constant
40293 holding number of the target dependent special slot which should be
40294 used to store BOUNDS. */
40296 static void
40298 {
40299 rtx addr;
40301 /* Get address to be used to access Bounds Table. Special slots start
40302 at the location of return address of a called function. */
40305 /* Load pointer value from a memory if we don't have it. */
40307 {
40310 }
40319 }
40321 /* Load and return bounds returned by function in SLOT. */
40323 static rtx
40325 {
40326 rtx res;
40333 }
40335 /* Store BOUNDS returned by function into SLOT. */
40337 static void
40339 {
40342 }
40344 /* Returns a function decl for a vectorized version of the builtin function
40345 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40346 if it is not available. */
40348 static tree
40350 tree type_in)
40351 {
40367 {
40370 {
40377 }
40382 {
40385 }
40390 {
40397 }
40403 /* The round insn does not trap on denormals. */
40408 {
40415 }
40421 /* The round insn does not trap on denormals. */
40426 {
40431 }
40437 /* The round insn does not trap on denormals. */
40442 {
40449 }
40455 /* The round insn does not trap on denormals. */
40460 {
40465 }
40472 {
40477 }
40484 {
40489 }
40495 /* The round insn does not trap on denormals. */
40500 {
40507 }
40513 /* The round insn does not trap on denormals. */
40518 {
40523 }
40528 {
40535 }
40540 {
40547 }
40551 /* The round insn does not trap on denormals. */
40556 {
40561 }
40565 /* The round insn does not trap on denormals. */
40570 {
40575 }
40579 /* The round insn does not trap on denormals. */
40584 {
40589 }
40593 /* The round insn does not trap on denormals. */
40598 {
40603 }
40607 /* The round insn does not trap on denormals. */
40612 {
40617 }
40621 /* The round insn does not trap on denormals. */
40626 {
40631 }
40635 /* The round insn does not trap on denormals. */
40640 {
40645 }
40649 /* The round insn does not trap on denormals. */
40654 {
40659 }
40663 /* The round insn does not trap on denormals. */
40668 {
40673 }
40677 /* The round insn does not trap on denormals. */
40682 {
40687 }
40692 {
40697 }
40702 {
40707 }
40712 }
40714 /* Dispatch to a handler for a vectorization library. */
40717 type_in);
40720 }
40722 /* Handler for an SVML-style interface to
40723 a library with vectorized intrinsics. */
40725 static tree
40727 {
40735 /* The SVML is suitable for unsafe math only. */
40748 {
40795 }
40804 {
40807 }
40808 else
40811 /* Convert to uppercase. */
40816 args;
40818 arity++;
40822 else
40825 /* Build a function declaration for the vectorized function. */
40834 }
40836 /* Handler for an ACML-style interface to
40837 a library with vectorized intrinsics. */
40839 static tree
40841 {
40849 /* The ACML is 64bits only and suitable for unsafe math only as
40850 it does not correctly support parts of IEEE with the required
40851 precision such as denormals. */
40865 {
40895 }
40902 args;
40904 arity++;
40908 else
40911 /* Build a function declaration for the vectorized function. */
40920 }
40922 /* Returns a decl of a function that implements gather load with
40923 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40924 Return NULL_TREE if it is not available. */
40926 static tree
40929 {
40945 /* v*gather* insn sign extends index to pointer mode. */
40957 {
40961 else
40967 else
40973 else
40979 else
40985 else
40991 else
40997 else
41003 else
41009 else
41015 else
41021 else
41027 else
41032 }
41035 }
41037 /* Returns a code for a target-specific builtin that implements
41038 reciprocal of the function, or NULL_TREE if not available. */
41040 static tree
41042 {
41049 /* Machine dependent builtins. */
41051 {
41052 /* Vectorized version of sqrt to rsqrt conversion. */
41061 }
41062 else
41063 /* Normal builtins. */
41065 {
41066 /* Sqrt to rsqrt conversion. */
41072 }
41073 }
41074 \f
41075 /* Helper for avx_vpermilps256_operand et al. This is also used by
41076 the expansion functions to turn the parallel back into a mask.
41077 The return value is 0 for no match and the imm8+1 for a match. */
41079 int
41081 {
41089 /* Validate that all of the elements are constants, and not totally
41090 out of range. Copy the data into an integral array to make the
41091 subsequent checks easier. */
41093 {
41103 }
41106 {
41108 /* In the 512-bit DFmode case, we can only move elements within
41109 a 128-bit lane. First fill the second part of the mask,
41110 then fallthru. */
41112 {
41116 }
41118 {
41122 }
41123 /* FALLTHRU */
41126 /* In the 256-bit DFmode case, we can only move elements within
41127 a 128-bit lane. */
41129 {
41133 }
41135 {
41139 }
41143 /* In 512 bit SFmode case, permutation in the upper 256 bits
41144 must mirror the permutation in the lower 256-bits. */
41148 /* FALLTHRU */
41151 /* In 256 bit SFmode case, we have full freedom of
41152 movement within the low 128-bit lane, but the high 128-bit
41153 lane must mirror the exact same pattern. */
41158 /* FALLTHRU */
41162 /* In the 128-bit case, we've full freedom in the placement of
41163 the elements from the source operand. */
41170 }
41172 /* Make sure success has a non-zero value by adding one. */
41174 }
41176 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41177 the expansion functions to turn the parallel back into a mask.
41178 The return value is 0 for no match and the imm8+1 for a match. */
41180 int
41182 {
41190 /* Validate that all of the elements are constants, and not totally
41191 out of range. Copy the data into an integral array to make the
41192 subsequent checks easier. */
41194 {
41204 }
41206 /* Validate that the halves of the permute are halves. */
41214 /* Reconstruct the mask. */
41216 {
41222 }
41224 /* Make sure success has a non-zero value by adding one. */
41226 }
41227 \f
41228 /* Return a register priority for hard reg REGNO. */
41229 static int
41231 {
41232 /* ebp and r13 as the base always wants a displacement, r12 as the
41233 base always wants an index. So discourage their usage in an
41234 address. */
41239 /* New x86-64 int registers result in bigger code size. Discourage
41240 them. */
41243 /* New x86-64 SSE registers result in bigger code size. Discourage
41244 them. */
41247 /* Usage of AX register results in smaller code. Prefer it. */
41251 }
41253 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41255 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41256 QImode must go into class Q_REGS.
41257 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41258 movdf to do mem-to-mem moves through integer regs. */
41260 static reg_class_t
41262 {
41265 /* We're only allowed to return a subclass of CLASS. Many of the
41266 following checks fail for NO_REGS, so eliminate that early. */
41270 /* All classes can load zeros. */
41274 /* Force constants into memory if we are loading a (nonzero) constant into
41275 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41276 instructions to load from a constant. */
41283 /* Prefer SSE regs only, if we can use them for math. */
41287 /* Floating-point constants need more complex checks. */
41289 {
41290 /* General regs can load everything. */
41294 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41295 zero above. We only want to wind up preferring 80387 registers if
41296 we plan on doing computation with them. */
41299 {
41300 /* Limit class to non-sse. */
41309 }
41312 }
41314 /* Generally when we see PLUS here, it's the function invariant
41315 (plus soft-fp const_int). Which can only be computed into general
41316 regs. */
41320 /* QImode constants are easy to load, but non-constant QImode data
41321 must go into Q_REGS. */
41323 {
41329 }
41332 }
41334 /* Discourage putting floating-point values in SSE registers unless
41335 SSE math is being used, and likewise for the 387 registers. */
41336 static reg_class_t
41338 {
41341 /* Restrict the output reload class to the register bank that we are doing
41342 math on. If we would like not to return a subset of CLASS, reject this
41343 alternative: if reload cannot do this, it will still use its choice. */
41349 {
41354 else
41356 }
41359 }
41361 static reg_class_t
41364 {
41365 /* Double-word spills from general registers to non-offsettable memory
41366 references (zero-extended addresses) require special handling. */
41372 {
41374 ? CODE_FOR_reload_noff_load
41376 /* Add the cost of moving address to a temporary. */
41380 }
41382 /* QImode spills from non-QI registers require
41383 intermediate register on 32bit targets. */
41389 {
41394 else
41400 /* Return Q_REGS if the operand is in memory. */
41403 }
41405 /* This condition handles corner case where an expression involving
41406 pointers gets vectorized. We're trying to use the address of a
41407 stack slot as a vector initializer.
41409 (set (reg:V2DI 74 [ vect_cst_.2 ])
41410 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41412 Eventually frame gets turned into sp+offset like this:
41414 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41415 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41416 (const_int 392 [0x188]))))
41418 That later gets turned into:
41420 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41421 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41422 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41424 We'll have the following reload recorded:
41426 Reload 0: reload_in (DI) =
41427 (plus:DI (reg/f:DI 7 sp)
41428 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41429 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41430 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41431 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41432 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41433 reload_reg_rtx: (reg:V2DI 22 xmm1)
41435 Which isn't going to work since SSE instructions can't handle scalar
41436 additions. Returning GENERAL_REGS forces the addition into integer
41437 register and reload can handle subsequent reloads without problems. */
41445 }
41447 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41449 static bool
41451 {
41453 {
41469 }
41472 }
41474 /* If we are copying between general and FP registers, we need a memory
41475 location. The same is true for SSE and MMX registers.
41477 To optimize register_move_cost performance, allow inline variant.
41479 The macro can't work reliably when one of the CLASSES is class containing
41480 registers from multiple units (SSE, MMX, integer). We avoid this by never
41481 combining those units in single alternative in the machine description.
41482 Ensure that this constraint holds to avoid unexpected surprises.
41484 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41485 enforce these sanity checks. */
41490 {
41499 {
41502 }
41507 /* Between mask and general, we have moves no larger than word size. */
41512 /* ??? This is a lie. We do have moves between mmx/general, and for
41513 mmx/sse2. But by saying we need secondary memory we discourage the
41514 register allocator from using the mmx registers unless needed. */
41519 {
41520 /* SSE1 doesn't have any direct moves from other classes. */
41524 /* If the target says that inter-unit moves are more expensive
41525 than moving through memory, then don't generate them. */
41530 /* Between SSE and general, we have moves no larger than word size. */
41533 }
41536 }
41538 bool
41541 {
41543 }
41545 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41547 On the 80386, this is the size of MODE in words,
41548 except in the FP regs, where a single reg is always enough. */
41550 static unsigned char
41552 {
41554 {
41559 else
41561 }
41562 else
41563 {
41566 else
41568 }
41569 }
41571 /* Return true if the registers in CLASS cannot represent the change from
41572 modes FROM to TO. */
41574 bool
41577 {
41581 /* x87 registers can't do subreg at all, as all values are reformatted
41582 to extended precision. */
41587 {
41588 /* Vector registers do not support QI or HImode loads. If we don't
41589 disallow a change to these modes, reload will assume it's ok to
41590 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41591 the vec_dupv4hi pattern. */
41594 }
41597 }
41599 /* Return the cost of moving data of mode M between a
41600 register and memory. A value of 2 is the default; this cost is
41601 relative to those in `REGISTER_MOVE_COST'.
41603 This function is used extensively by register_move_cost that is used to
41604 build tables at startup. Make it inline in this case.
41605 When IN is 2, return maximum of in and out move cost.
41607 If moving between registers and memory is more expensive than
41608 between two registers, you should define this macro to express the
41609 relative cost.
41611 Model also increased moving costs of QImode registers in non
41612 Q_REGS classes.
41613 */
41617 {
41620 {
41623 {
41635 }
41639 }
41641 {
41644 {
41656 }
41660 }
41662 {
41665 {
41674 }
41678 }
41680 {
41683 {
41689 else
41694 }
41695 else
41696 {
41701 else
41703 }
41710 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41717 else
41721 }
41722 }
41724 static int
41727 {
41729 }
41732 /* Return the cost of moving data from a register in class CLASS1 to
41733 one in class CLASS2.
41735 It is not required that the cost always equal 2 when FROM is the same as TO;
41736 on some machines it is expensive to move between registers if they are not
41737 general registers. */
41739 static int
41741 reg_class_t class2_i)
41742 {
41746 /* In case we require secondary memory, compute cost of the store followed
41747 by load. In order to avoid bad register allocation choices, we need
41748 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41751 {
41757 /* In case of copying from general_purpose_register we may emit multiple
41758 stores followed by single load causing memory size mismatch stall.
41759 Count this as arbitrarily high cost of 20. */
41764 /* In the case of FP/MMX moves, the registers actually overlap, and we
41765 have to switch modes in order to treat them differently. */
41771 }
41773 /* Moves between SSE/MMX and integer unit are expensive. */
41777 /* ??? By keeping returned value relatively high, we limit the number
41778 of moves between integer and MMX/SSE registers for all targets.
41779 Additionally, high value prevents problem with x86_modes_tieable_p(),
41780 where integer modes in MMX/SSE registers are not tieable
41781 because of missing QImode and HImode moves to, from or between
41782 MMX/SSE registers. */
41792 }
41794 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41795 MODE. */
41797 bool
41799 {
41800 /* Flags and only flags can only hold CCmode values. */
41811 || (TARGET_AVX512BW
41816 {
41817 /* We implement the move patterns for all vector modes into and
41818 out of SSE registers, even when no operation instructions
41819 are available. */
41821 /* For AVX-512 we allow, regardless of regno:
41822 - XI mode
41823 - any of 512-bit wide vector mode
41824 - any scalar mode. */
41831 /* TODO check for QI/HI scalars. */
41832 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41840 /* xmm16-xmm31 are only available for AVX-512. */
41844 /* OImode and AVX modes are available only when AVX is enabled. */
41851 }
41853 {
41854 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41855 so if the register is available at all, then we can move data of
41856 the given mode into or out of it. */
41859 }
41862 {
41863 /* Take care for QImode values - they can be in non-QI regs,
41864 but then they do cause partial register stalls. */
41869 /* LRA checks if the hard register is OK for the given mode.
41870 QImode values can live in non-QI regs, so we allow all
41871 registers here. */
41875 }
41876 /* We handle both integer and floats in the general purpose registers. */
41883 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41884 on to use that value in smaller contexts, this can easily force a
41885 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41886 supporting DImode, allow it. */
41891 }
41893 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41894 tieable integer mode. */
41896 static bool
41898 {
41900 {
41913 }
41914 }
41916 /* Return true if MODE1 is accessible in a register that can hold MODE2
41917 without copying. That is, all register classes that can hold MODE2
41918 can also hold MODE1. */
41920 bool
41922 {
41930 /* MODE2 being XFmode implies fp stack or general regs, which means we
41931 can tie any smaller floating point modes to it. Note that we do not
41932 tie this with TFmode. */
41936 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
41937 that we can tie it with SFmode. */
41941 /* If MODE2 is only appropriate for an SSE register, then tie with
41942 any other mode acceptable to SSE registers. */
41952 /* If MODE2 is appropriate for an MMX register, then tie
41953 with any other mode acceptable to MMX registers. */
41960 }
41962 /* Return the cost of moving between two registers of mode MODE. */
41964 static int
41966 {
41970 {
42002 }
42004 /* Return the cost of moving between two registers of mode MODE,
42005 assuming that the move will be in pieces of at most UNITS bytes. */
42007 }
42009 /* Compute a (partial) cost for rtx X. Return true if the complete
42010 cost has been computed, and false if subexpressions should be
42011 scanned. In either case, *TOTAL contains the cost result. */
42013 static bool
42016 {
42017 rtx mask;
42024 {
42028 {
42031 }
42043 && !(TARGET_64BIT
42048 else
42054 {
42057 }
42059 {
42069 }
42071 {
42074 {
42083 }
42084 }
42085 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42086 it'll probably end up. Add a penalty for size. */
42093 /* The zero extensions is often completely free on x86_64, so make
42094 it as cheap as possible. */
42100 else
42112 {
42115 {
42118 }
42121 {
42124 }
42125 }
42126 /* FALLTHRU */
42133 {
42134 /* ??? Should be SSE vector operation cost. */
42135 /* At least for published AMD latencies, this really is the same
42136 as the latency for a simple fpu operation like fabs. */
42137 /* V*QImode is emulated with 1-11 insns. */
42139 {
42142 {
42143 /* For XOP we use vpshab, which requires a broadcast of the
42144 value to the variable shift insn. For constants this
42145 means a V16Q const in mem; even when we can perform the
42146 shift with one insn set the cost to prefer paddb. */
42148 {
42153 }
42155 }
42159 }
42160 else
42162 }
42164 {
42166 {
42169 else
42171 }
42172 else
42173 {
42176 else
42178 }
42179 }
42180 else
42181 {
42186 {
42187 /* Return the cost after shift-and truncation. */
42190 }
42191 else
42193 }
42197 {
42198 rtx sub;
42203 /* ??? SSE scalar/vector cost should be used here. */
42204 /* ??? Bald assumption that fma has the same cost as fmul. */
42208 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42219 }
42223 {
42224 /* ??? SSE scalar cost should be used here. */
42227 }
42229 {
42232 }
42234 {
42235 /* ??? SSE vector cost should be used here. */
42238 }
42240 {
42241 /* V*QImode is emulated with 7-13 insns. */
42243 {
42250 }
42251 /* V*DImode is emulated with 5-8 insns. */
42253 {
42256 else
42258 }
42259 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42260 insns, including two PMULUDQ. */
42263 else
42266 }
42267 else
42268 {
42273 {
42276 nbits++;
42277 }
42278 else
42279 /* This is arbitrary. */
42282 /* Compute costs correctly for widening multiplication. */
42286 {
42293 {
42297 else
42299 }
42303 }
42311 }
42318 /* ??? SSE cost should be used here. */
42323 /* ??? SSE vector cost should be used here. */
42325 else
42332 {
42337 {
42340 {
42348 }
42349 }
42352 {
42355 {
42361 }
42362 }
42364 {
42372 }
42373 }
42374 /* FALLTHRU */
42378 {
42379 /* ??? SSE cost should be used here. */
42382 }
42384 {
42387 }
42389 {
42390 /* ??? SSE vector cost should be used here. */
42393 }
42394 /* FALLTHRU */
42401 {
42408 }
42409 /* FALLTHRU */
42413 {
42414 /* ??? SSE cost should be used here. */
42417 }
42419 {
42422 }
42424 {
42425 /* ??? SSE vector cost should be used here. */
42428 }
42429 /* FALLTHRU */
42433 {
42434 /* ??? Should be SSE vector operation cost. */
42435 /* At least for published AMD latencies, this really is the same
42436 as the latency for a simple fpu operation like fabs. */
42438 }
42441 else
42450 {
42451 /* This kind of construct is implemented using test[bwl].
42452 Treat it as if we had an AND. */
42457 }
42467 /* ??? SSE cost should be used here. */
42472 /* ??? SSE vector cost should be used here. */
42478 /* ??? SSE cost should be used here. */
42483 /* ??? SSE vector cost should be used here. */
42495 /* ??? Assume all of these vector manipulation patterns are
42496 recognizable. In which case they all pretty much have the
42497 same cost. */
42502 /* This is masked instruction, assume the same cost,
42503 as nonmasked variant. */
42506 else
42512 }
42513 }
42515 #if TARGET_MACHO
42519 /* Given a symbol name and its associated stub, write out the
42520 definition of the stub. */
42522 void
42524 {
42529 /* For 64-bit we shouldn't get here. */
42532 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42549 else
42556 {
42558 }
42560 {
42561 /* PIC stub. */
42562 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42568 }
42569 else
42572 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42573 it needs no stub-binding-helper. */
42580 {
42583 }
42584 else
42589 /* N.B. Keep the correspondence of these
42590 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42591 old-pic/new-pic/non-pic stubs; altering this will break
42592 compatibility with existing dylibs. */
42594 {
42595 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42597 }
42598 else
42599 /* 16-byte -mdynamic-no-pic stub. */
42605 }
42608 /* Order the registers for register allocator. */
42610 void
42612 {
42616 /* First allocate the local general purpose registers. */
42621 /* Global general purpose registers. */
42626 /* x87 registers come first in case we are doing FP math
42627 using them. */
42632 /* SSE registers. */
42638 /* Extended REX SSE registers. */
42642 /* Mask register. */
42646 /* MPX bound registers. */
42650 /* x87 registers. */
42658 /* Initialize the rest of array as we do not allocate some registers
42659 at all. */
42662 }
42664 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42665 in struct attribute_spec handler. */
42666 static tree
42668 tree args,
42671 {
42676 {
42678 name);
42681 }
42683 {
42685 name);
42688 }
42690 {
42691 tree cst;
42695 {
42698 name);
42700 }
42703 {
42706 name);
42708 }
42711 }
42714 }
42716 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42717 struct attribute_spec.handler. */
42718 static tree
42721 {
42726 {
42728 name);
42731 }
42733 /* Can combine regparm with all attributes but fastcall. */
42735 {
42737 {
42739 }
42742 }
42744 {
42746 {
42748 }
42751 }
42754 }
42756 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42757 struct attribute_spec.handler. */
42758 static tree
42761 {
42764 {
42767 }
42768 else
42772 {
42774 name);
42776 }
42782 {
42784 name);
42786 }
42789 }
42791 static tree
42794 {
42796 {
42798 name);
42800 }
42802 }
42804 static bool
42806 {
42810 }
42812 /* Returns an expression indicating where the this parameter is
42813 located on entry to the FUNCTION. */
42815 static rtx
42817 {
42823 {
42828 else
42831 }
42836 {
42843 {
42848 }
42849 else
42850 {
42853 {
42859 }
42860 }
42862 }
42866 }
42868 /* Determine whether x86_output_mi_thunk can succeed. */
42870 static bool
42872 const_tree function)
42873 {
42874 /* 64-bit can handle anything. */
42878 /* For 32-bit, everything's fine if we have one free register. */
42882 /* Need a free register for vcall_offset. */
42886 /* Need a free register for GOT references. */
42890 /* Otherwise ok. */
42892 }
42894 /* Output the assembler code for a thunk function. THUNK_DECL is the
42895 declaration for the thunk function itself, FUNCTION is the decl for
42896 the target function. DELTA is an immediate constant offset to be
42897 added to THIS. If VCALL_OFFSET is nonzero, the word at
42898 *(*this + vcall_offset) should be added to THIS. */
42900 static void
42903 {
42911 else
42912 {
42918 else
42920 }
42924 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
42925 pull it in now and let DELTA benefit. */
42929 {
42930 /* Put the this parameter into %eax. */
42933 }
42934 else
42937 /* Adjust the this parameter by a fixed constant. */
42939 {
42944 {
42946 {
42950 }
42951 }
42954 }
42956 /* Adjust the this parameter by a value stored in the vtable. */
42958 {
42968 /* Adjust the this parameter. */
42972 {
42976 }
42983 vcall_mem));
42984 else
42986 }
42988 /* If necessary, drop THIS back to its stack slot. */
42994 {
42997 ;
42998 else
42999 {
43003 }
43004 }
43005 else
43006 {
43008 ;
43009 #if TARGET_MACHO
43011 {
43014 }
43016 else
43017 {
43025 }
43026 }
43028 /* Our sibling call patterns do not allow memories, because we have no
43029 predicate that can distinguish between frame and non-frame memory.
43030 For our purposes here, we can get away with (ab)using a jump pattern,
43031 because we're going to do no optimization. */
43033 {
43035 {
43041 }
43042 else
43044 }
43045 else
43046 {
43048 {
43049 // CM_LARGE_PIC always uses pseudo PIC register which is
43050 // uninitialized. Since FUNCTION is local and calling it
43051 // doesn't go through PLT, we use scratch register %r11 as
43052 // PIC register and initialize it here.
43057 }
43060 {
43066 }
43072 }
43075 /* Emit just enough of rest_of_compilation to get the insns emitted.
43076 Note that use_thunk calls assemble_start_function et al. */
43082 }
43084 static void
43086 {
43090 #if TARGET_MACHO
43092 #endif
43099 }
43101 int
43103 {
43104 machine_mode mode;
43115 }
43117 /* Print call to TARGET to FILE. */
43119 static void
43121 {
43124 else
43126 }
43128 /* Output assembler code to FILE to increment profiler label # LABELNO
43129 for profiling a function entry. */
43130 void
43132 {
43136 {
43137 #ifndef NO_PROFILE_COUNTERS
43139 #endif
43143 else
43145 }
43147 {
43148 #ifndef NO_PROFILE_COUNTERS
43151 #endif
43153 }
43154 else
43155 {
43156 #ifndef NO_PROFILE_COUNTERS
43159 #endif
43161 }
43164 {
43168 }
43169 }
43171 /* We don't have exact information about the insn sizes, but we may assume
43172 quite safely that we are informed about all 1 byte insns and memory
43173 address sizes. This is enough to eliminate unnecessary padding in
43174 99% of cases. */
43176 static int
43178 {
43184 /* Discard alignments we've emit and jump instructions. */
43189 /* Important case - calls are always 5 bytes.
43190 It is common to have many calls in the row. */
43199 /* For normal instructions we rely on get_attr_length being exact,
43200 with a few exceptions. */
43202 {
43206 {
43216 /* Otherwise trust get_attr_length. */
43218 }
43223 }
43226 else
43228 }
43230 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43232 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43233 window. */
43235 static void
43237 {
43242 /* Look for all minimal intervals of instructions containing 4 jumps.
43243 The intervals are bounded by START and INSN. NBYTES is the total
43244 size of instructions in the interval including INSN and not including
43245 START. When the NBYTES is smaller than 16 bytes, it is possible
43246 that the end of START and INSN ends up in the same 16byte page.
43248 The smallest offset in the page INSN can start is the case where START
43249 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43250 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43252 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43253 have to, control transfer to label(s) can be performed through other
43254 means, and also we estimate minimum length of all asm stmts as 0. */
43256 {
43260 {
43266 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43267 already in the current 16 byte page, because otherwise
43268 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43269 bytes to reach 16 byte boundary. */
43277 {
43279 {
43284 else
43287 }
43288 }
43290 }
43299 njumps++;
43300 else
43304 {
43309 else
43312 }
43319 {
43326 }
43327 }
43328 }
43329 #endif
43331 /* AMD Athlon works faster
43332 when RET is not destination of conditional jump or directly preceded
43333 by other jump instruction. We avoid the penalty by inserting NOP just
43334 before the RET instructions in such cases. */
43335 static void
43337 {
43338 edge e;
43339 edge_iterator ei;
43342 {
43355 {
43356 edge e;
43357 edge_iterator ei;
43362 {
43365 }
43366 }
43368 {
43374 /* Empty functions get branch mispredict even when
43375 the jump destination is not visible to us. */
43378 }
43380 {
43383 }
43384 }
43385 }
43387 /* Count the minimum number of instructions in BB. Return 4 if the
43388 number of instructions >= 4. */
43390 static int
43392 {
43396 /* Count number of instructions in this block. Return 4 if the number
43397 of instructions >= 4. */
43399 {
43400 /* Only happen in exit blocks. */
43408 {
43409 insn_count++;
43412 }
43413 }
43416 }
43419 /* Count the minimum number of instructions in code path in BB.
43420 Return 4 if the number of instructions >= 4. */
43422 static int
43424 {
43425 edge e;
43426 edge_iterator ei;
43429 /* Only bother counting instructions along paths with no
43430 more than 2 basic blocks between entry and exit. Given
43431 that BB has an edge to exit, determine if a predecessor
43432 of BB has an edge from entry. If so, compute the number
43433 of instructions in the predecessor block. If there
43434 happen to be multiple such blocks, compute the minimum. */
43437 {
43438 edge prev_e;
43439 edge_iterator prev_ei;
43442 {
43445 }
43447 {
43449 {
43454 }
43455 }
43456 }
43462 }
43464 /* Pad short function to 4 instructions. */
43466 static void
43468 {
43469 edge e;
43470 edge_iterator ei;
43473 {
43476 {
43479 /* Pad short function. */
43481 {
43484 /* Find epilogue. */
43493 /* Two NOPs count as one instruction. */
43496 }
43497 }
43498 }
43499 }
43501 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43502 the epilogue, the Windows system unwinder will apply epilogue logic and
43503 produce incorrect offsets. This can be avoided by adding a nop between
43504 the last insn that can throw and the first insn of the epilogue. */
43506 static void
43508 {
43509 edge e;
43510 edge_iterator ei;
43513 {
43516 /* Find the beginning of the epilogue. */
43523 /* We only care about preceding insns that can throw. */
43528 /* Do not separate calls from their debug information. */
43534 else
43538 }
43539 }
43541 /* Implement machine specific optimizations. We implement padding of returns
43542 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43543 static void
43545 {
43546 /* We are freeing block_for_insn in the toplev to keep compatibility
43547 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43554 {
43559 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43562 #endif
43563 }
43564 }
43566 /* Return nonzero when QImode register that must be represented via REX prefix
43567 is used. */
43568 bool
43570 {
43578 }
43580 /* Return true when INSN mentions register that must be encoded using REX
43581 prefix. */
43582 bool
43584 {
43587 {
43592 }
43594 }
43596 /* If profitable, negate (without causing overflow) integer constant
43597 of mode MODE at location LOC. Return true in this case. */
43598 bool
43600 {
43601 HOST_WIDE_INT val;
43607 {
43609 /* DImode x86_64 constants must fit in 32 bits. */
43622 }
43624 /* Avoid overflows. */
43630 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43631 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43634 {
43637 }
43640 }
43642 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43643 optabs would emit if we didn't have TFmode patterns. */
43645 void
43647 {
43682 }
43683 \f
43689 /* Get a vector mode of the same size as the original but with elements
43690 twice as wide. This is only guaranteed to apply to integral vectors. */
43694 {
43695 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43700 }
43702 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43703 fill target with val via vec_duplicate. */
43705 static bool
43707 {
43710 rtx dup;
43712 /* First attempt to recognize VAL as-is. */
43716 {
43718 /* If that fails, force VAL into a register. */
43729 }
43731 }
43733 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43734 with all elements equal to VAR. Return true if successful. */
43736 static bool
43739 {
43743 {
43748 /* FALLTHRU */
43768 {
43769 rtx x;
43776 }
43789 {
43793 permute:
43801 /* Extend to SImode using a paradoxical SUBREG. */
43805 /* Insert the SImode value as low element of a V4SImode vector. */
43814 }
43825 widen:
43826 /* Replicate the value once into the next wider mode and recurse. */
43827 {
43829 rtx x;
43846 }
43852 else
43853 {
43862 }
43869 else
43870 {
43879 }
43884 }
43885 }
43887 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43888 whose ONE_VAR element is VAR, and other elements are zero. Return true
43889 if successful. */
43891 static bool
43894 {
43895 machine_mode vsimode;
43896 rtx new_target;
43901 {
43903 /* For SSE4.1, we normally use vector set. But if the second
43904 element is zero and inter-unit moves are OK, we use movq
43905 instead. */
43907 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
43929 /* Use ix86_expand_vector_set in 64bit mode only. */
43934 }
43937 {
43942 }
43945 {
43950 /* FALLTHRU */
43965 else
43972 {
43973 /* We need to shuffle the value to the correct position, so
43974 create a new pseudo to store the intermediate result. */
43976 /* With SSE2, we can use the integer shuffle insns. */
43978 {
43980 const1_rtx,
43987 }
43989 /* Otherwise convert the intermediate result to V4SFmode and
43990 use the SSE1 shuffle instructions. */
43992 {
43995 }
43996 else
44000 const1_rtx,
44009 }
44024 widen:
44028 /* Zero extend the variable element to SImode and recurse. */
44041 }
44042 }
44044 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44045 consisting of the values in VALS. It is known that all elements
44046 except ONE_VAR are constants. Return true if successful. */
44048 static bool
44051 {
44053 machine_mode wmode;
44061 {
44066 /* For the two element vectors, it's just as easy to use
44067 the general case. */
44071 /* Use ix86_expand_vector_set in 64bit mode only. */
44093 widen:
44094 /* There's no way to set one QImode entry easily. Combine
44095 the variable value with its adjacent constant value, and
44096 promote to an HImode set. */
44099 {
44104 }
44105 else
44106 {
44109 }
44123 }
44128 }
44130 /* A subroutine of ix86_expand_vector_init_general. Use vector
44131 concatenate to handle the most general case: all values variable,
44132 and none identical. */
44134 static void
44137 {
44140 rtvec v;
44144 {
44147 {
44192 }
44205 {
44220 }
44225 {
44244 }
44249 {
44262 }
44265 half:
44266 /* FIXME: We process inputs backward to help RA. PR 36222. */
44270 {
44275 }
44279 {
44283 {
44287 }
44290 {
44294 }
44297 }
44299 {
44302 {
44306 }
44309 }
44310 else
44316 }
44317 }
44319 /* A subroutine of ix86_expand_vector_init_general. Use vector
44320 interleave to handle the most general case: all values variable,
44321 and none identical. */
44323 static void
44326 {
44335 {
44356 }
44359 {
44360 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44364 /* Insert the SImode value as low element of V4SImode vector. */
44368 op0),
44370 const1_rtx);
44373 /* Cast the V4SImode vector back to a vector in orignal mode. */
44377 /* Load even elements into the second position. */
44381 const1_rtx));
44383 /* Cast vector to FIRST_IMODE vector. */
44386 }
44388 /* Interleave low FIRST_IMODE vectors. */
44390 {
44394 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44397 }
44399 /* Interleave low SECOND_IMODE vectors. */
44401 {
44404 {
44409 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44410 vector. */
44413 }
44416 /* FALLTHRU */
44423 /* Cast the SECOND_IMODE vector back to a vector on original
44424 mode. */
44431 }
44432 }
44434 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44435 all values variable, and none identical. */
44437 static void
44440 {
44447 {
44452 /* FALLTHRU */
44480 half:
44504 quarter:
44533 /* FALLTHRU */
44539 /* Don't use ix86_expand_vector_init_interleave if we can't
44540 move from GPR to SSE register directly. */
44556 }
44558 {
44560 machine_mode inner_mode;
44570 {
44574 {
44580 else
44581 {
44586 }
44587 }
44590 }
44595 {
44601 }
44603 {
44609 }
44610 else
44612 }
44613 }
44615 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44616 instructions unless MMX_OK is true. */
44618 void
44620 {
44627 rtx x;
44630 {
44640 }
44642 /* Constants are best loaded from the constant pool. */
44644 {
44647 }
44649 /* If all values are identical, broadcast the value. */
44655 /* Values where only one field is non-constant are best loaded from
44656 the pool and overwritten via move later. */
44658 {
44662 one_var))
44667 }
44670 }
44672 void
44674 {
44677 machine_mode half_mode;
44679 rtx tmp;
44681 = {
44688 };
44690 = {
44697 };
44701 {
44705 {
44710 else
44714 }
44726 else
44732 {
44735 /* For the two element vectors, we implement a VEC_CONCAT with
44736 the extraction of the other element. */
44743 else
44748 }
44757 {
44763 /* tmp = target = A B C D */
44765 /* target = A A B B */
44767 /* target = X A B B */
44769 /* target = A X C D */
44776 /* tmp = target = A B C D */
44778 /* tmp = X B C D */
44780 /* target = A B X D */
44787 /* tmp = target = A B C D */
44789 /* tmp = X B C D */
44791 /* target = A B X D */
44799 }
44807 /* Element 0 handled by vec_merge below. */
44809 {
44812 }
44815 {
44816 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44817 store into element 0, then shuffle them back. */
44834 }
44835 else
44836 {
44837 /* For SSE1, we have to reuse the V4SF code. */
44841 }
44894 half:
44895 /* Compute offset. */
44901 /* Extract the half. */
44905 /* Put val in tmp at elt. */
44908 /* Put it back. */
44914 {
44921 }
44922 else
44926 {
44933 }
44934 else
44938 {
44945 }
44946 else
44950 {
44957 }
44958 else
44962 {
44969 }
44970 else
44974 {
44981 }
44982 else
44987 }
44990 {
44994 }
44995 else
44996 {
45005 }
45006 }
45008 void
45010 {
45014 rtx tmp;
45017 {
45022 /* FALLTHRU */
45035 {
45055 }
45067 {
45069 {
45089 }
45093 }
45094 else
45095 {
45096 /* For SSE1, we have to reuse the V4SF code. */
45100 }
45116 {
45120 else
45124 }
45129 {
45133 else
45137 }
45142 {
45146 else
45150 }
45155 {
45159 else
45163 }
45168 {
45172 else
45176 }
45181 {
45185 else
45189 }
45194 {
45198 else
45202 }
45207 {
45211 else
45215 }
45222 else
45231 else
45240 else
45249 else
45255 /* ??? Could extract the appropriate HImode element and shift. */
45258 }
45261 {
45265 /* Let the rtl optimizers know about the zero extension performed. */
45267 {
45270 }
45273 }
45274 else
45275 {
45282 }
45283 }
45285 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45286 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45287 The upper bits of DEST are undefined, though they shouldn't cause
45288 exceptions (some bits from src or all zeros are ok). */
45290 static void
45292 {
45295 {
45299 else
45317 else
45324 else
45332 {
45337 const1_rtx);
45338 }
45339 else
45340 {
45344 }
45366 else
45388 }
45392 }
45394 /* Expand a vector reduction. FN is the binary pattern to reduce;
45395 DEST is the destination; IN is the input vector. */
45397 void
45399 {
45404 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45408 {
45411 }
45416 {
45421 else
45425 }
45426 }
45427 \f
45428 /* Target hook for scalar_mode_supported_p. */
45429 static bool
45431 {
45436 else
45438 }
45440 /* Implements target hook vector_mode_supported_p. */
45441 static bool
45443 {
45457 }
45459 /* Implement target hook libgcc_floating_mode_supported_p. */
45460 static bool
45462 {
45464 {
45471 #ifdef IX86_NO_LIBGCC_TFMODE
45473 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45475 #else
45477 #endif
45481 }
45482 }
45484 /* Target hook for c_mode_for_suffix. */
45485 static machine_mode
45487 {
45494 }
45496 /* Worker function for TARGET_MD_ASM_CLOBBERS.
45498 We do this in the new i386 backend to maintain source compatibility
45499 with the old cc0-based compiler. */
45501 static tree
45503 {
45505 clobbers);
45507 clobbers);
45509 }
45511 /* Implements target vector targetm.asm.encode_section_info. */
45513 static void ATTRIBUTE_UNUSED
45515 {
45520 }
45522 /* Worker function for REVERSE_CONDITION. */
45524 enum rtx_code
45526 {
45530 }
45532 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45533 to OPERANDS[0]. */
45537 {
45539 {
45542 {
45546 }
45550 }
45552 {
45556 else
45557 {
45558 /* There is no non-popping store to memory for XFmode.
45559 So if we need one, follow the store with a load. */
45562 else
45564 }
45565 }
45566 else
45568 }
45570 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45571 FP status register is set. */
45573 void
45575 {
45577 rtx temp;
45582 {
45587 }
45588 else
45589 {
45594 }
45598 pc_rtx);
45603 }
45605 /* Output code to perform a log1p XFmode calculation. */
45608 {
45614 rtx test;
45620 XFmode));
45634 }
45636 /* Emit code for round calculation. */
45638 {
45645 rtx insn;
45650 {
45662 }
45665 {
45686 }
45694 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45696 /* scratch = fxam(op1) */
45699 UNSPEC_FXAM)));
45700 /* e1 = fabs(op1) */
45703 /* e2 = e1 + 0.5 */
45708 /* res = floor(e2) */
45710 {
45715 }
45716 else
45720 {
45723 {
45730 UNSPEC_TRUNC_NOOP)));
45731 }
45747 }
45749 /* flags = signbit(a) */
45752 /* if (flags) then res = -res */
45756 pc_rtx);
45767 }
45769 /* Output code to perform a Newton-Rhapson approximation of a single precision
45770 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45773 {
45781 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45785 /* x0 = rcp(b) estimate */
45789 UNSPEC_RCP14)));
45790 else
45793 UNSPEC_RCP)));
45795 /* e0 = x0 * b */
45799 /* e0 = x0 * e0 */
45803 /* e1 = x0 + x0 */
45807 /* x1 = e1 - e0 */
45811 /* res = a * x1 */
45814 }
45816 /* Output code to perform a Newton-Rhapson approximation of a
45817 single precision floating point [reciprocal] square root. */
45821 {
45823 REAL_VALUE_TYPE r;
45840 {
45843 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45846 }
45848 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45849 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45853 /* x0 = rsqrt(a) estimate */
45856 unspec)));
45858 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45860 {
45868 /* Handle masked compare. */
45870 {
45872 /* Imm value 0x4 corresponds to not-equal comparison. */
45875 }
45876 else
45877 {
45883 }
45884 }
45886 /* e0 = x0 * a */
45889 /* e1 = e0 * x0 */
45893 /* e2 = e1 - 3. */
45900 /* e3 = -.5 * x0 */
45903 else
45904 /* e3 = -.5 * e0 */
45907 /* ret = e2 * e3 */
45910 }
45912 #ifdef TARGET_SOLARIS
45913 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45915 static void
45917 tree decl)
45918 {
45919 /* With Binutils 2.15, the "@unwind" marker must be specified on
45920 every occurrence of the ".eh_frame" section, not just the first
45921 one. */
45924 {
45928 }
45930 #ifndef USE_GAS
45932 {
45935 }
45936 #endif
45939 }
45942 /* Return the mangling of TYPE if it is an extended fundamental type. */
45946 {
45954 {
45956 /* __float128 is "g". */
45959 /* "long double" or __float80 is "e". */
45963 }
45964 }
45966 /* For 32-bit code we can save PIC register setup by using
45967 __stack_chk_fail_local hidden function instead of calling
45968 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
45969 register, so it is better to call __stack_chk_fail directly. */
45971 static tree ATTRIBUTE_UNUSED
45973 {
45974 return TARGET_64BIT
45977 }
45979 /* Select a format to encode pointers in exception handling data. CODE
45980 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
45981 true if the symbol may be affected by dynamic relocations.
45983 ??? All x86 object file formats are capable of representing this.
45984 After all, the relocation needed is the same as for the call insn.
45985 Whether or not a particular assembler allows us to enter such, I
45986 guess we'll have to see. */
45987 int
45989 {
45991 {
45998 }
46003 }
46004 \f
46005 /* Expand copysign from SIGN to the positive value ABS_VALUE
46006 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46007 the sign-bit. */
46008 static void
46010 {
46014 {
46015 machine_mode vmode;
46021 else
46026 {
46027 /* We need to generate a scalar mode mask in this case. */
46032 }
46033 }
46034 else
46040 }
46042 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46043 mask for masking out the sign-bit is stored in *SMASK, if that is
46044 non-null. */
46045 static rtx
46047 {
46056 else
46060 {
46061 /* We need to generate a scalar mode mask in this case. */
46066 }
46074 }
46076 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46077 swapping the operands if SWAP_OPERANDS is true. The expanded
46078 code is a forward jump to a newly created label in case the
46079 comparison is true. The generated label rtx is returned. */
46083 {
46086 rtx tmp;
46102 }
46104 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46105 using comparison code CODE. Operands are swapped for the comparison if
46106 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46107 static rtx
46110 {
46123 }
46125 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46126 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46127 static rtx
46129 {
46130 REAL_VALUE_TYPE TWO52r;
46131 rtx TWO52;
46138 }
46140 /* Expand SSE sequence for computing lround from OP1 storing
46141 into OP0. */
46142 void
46144 {
46145 /* C code for the stuff we're doing below:
46146 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46147 return (long)tmp;
46148 */
46152 rtx adj;
46154 /* load nextafter (0.5, 0.0) */
46159 /* adj = copysign (0.5, op1) */
46163 /* adj = op1 + adj */
46166 /* op0 = (imode)adj */
46168 }
46170 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46171 into OPERAND0. */
46172 void
46174 {
46175 /* C code for the stuff we're doing below (for do_floor):
46176 xi = (long)op1;
46177 xi -= (double)xi > op1 ? 1 : 0;
46178 return xi;
46179 */
46185 /* reg = (long)op1 */
46189 /* freg = (double)reg */
46193 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46204 }
46206 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46207 result in OPERAND0. */
46208 void
46210 {
46211 /* C code for the stuff we're doing below:
46212 xa = fabs (operand1);
46213 if (!isless (xa, 2**52))
46214 return operand1;
46215 xa = xa + 2**52 - 2**52;
46216 return copysign (xa, operand1);
46217 */
46225 /* xa = abs (operand1) */
46228 /* if (!isless (xa, TWO52)) goto label; */
46241 }
46243 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46244 into OPERAND0. */
46245 void
46247 {
46248 /* C code for the stuff we expand below.
46249 double xa = fabs (x), x2;
46250 if (!isless (xa, TWO52))
46251 return x;
46252 xa = xa + TWO52 - TWO52;
46253 x2 = copysign (xa, x);
46254 Compensate. Floor:
46255 if (x2 > x)
46256 x2 -= 1;
46257 Compensate. Ceil:
46258 if (x2 < x)
46259 x2 -= -1;
46260 return x2;
46261 */
46268 /* Temporary for holding the result, initialized to the input
46269 operand to ease control flow. */
46273 /* xa = abs (operand1) */
46276 /* if (!isless (xa, TWO52)) goto label; */
46279 /* xa = xa + TWO52 - TWO52; */
46283 /* xa = copysign (xa, operand1) */
46286 /* generate 1.0 or -1.0 */
46291 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46295 /* We always need to subtract here to preserve signed zero. */
46304 }
46306 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46307 into OPERAND0. */
46308 void
46310 {
46311 /* C code for the stuff we expand below.
46312 double xa = fabs (x), x2;
46313 if (!isless (xa, TWO52))
46314 return x;
46315 x2 = (double)(long)x;
46316 Compensate. Floor:
46317 if (x2 > x)
46318 x2 -= 1;
46319 Compensate. Ceil:
46320 if (x2 < x)
46321 x2 += 1;
46322 if (HONOR_SIGNED_ZEROS (mode))
46323 return copysign (x2, x);
46324 return x2;
46325 */
46332 /* Temporary for holding the result, initialized to the input
46333 operand to ease control flow. */
46337 /* xa = abs (operand1) */
46340 /* if (!isless (xa, TWO52)) goto label; */
46343 /* xa = (double)(long)x */
46348 /* generate 1.0 */
46351 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46366 }
46368 /* Expand SSE sequence for computing round from OPERAND1 storing
46369 into OPERAND0. Sequence that works without relying on DImode truncation
46370 via cvttsd2siq that is only available on 64bit targets. */
46371 void
46373 {
46374 /* C code for the stuff we expand below.
46375 double xa = fabs (x), xa2, x2;
46376 if (!isless (xa, TWO52))
46377 return x;
46378 Using the absolute value and copying back sign makes
46379 -0.0 -> -0.0 correct.
46380 xa2 = xa + TWO52 - TWO52;
46381 Compensate.
46382 dxa = xa2 - xa;
46383 if (dxa <= -0.5)
46384 xa2 += 1;
46385 else if (dxa > 0.5)
46386 xa2 -= 1;
46387 x2 = copysign (xa2, x);
46388 return x2;
46389 */
46396 /* Temporary for holding the result, initialized to the input
46397 operand to ease control flow. */
46401 /* xa = abs (operand1) */
46404 /* if (!isless (xa, TWO52)) goto label; */
46407 /* xa2 = xa + TWO52 - TWO52; */
46411 /* dxa = xa2 - xa; */
46414 /* generate 0.5, 1.0 and -0.5 */
46420 /* Compensate. */
46422 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46427 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46433 /* res = copysign (xa2, operand1) */
46440 }
46442 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46443 into OPERAND0. */
46444 void
46446 {
46447 /* C code for SSE variant we expand below.
46448 double xa = fabs (x), x2;
46449 if (!isless (xa, TWO52))
46450 return x;
46451 x2 = (double)(long)x;
46452 if (HONOR_SIGNED_ZEROS (mode))
46453 return copysign (x2, x);
46454 return x2;
46455 */
46462 /* Temporary for holding the result, initialized to the input
46463 operand to ease control flow. */
46467 /* xa = abs (operand1) */
46470 /* if (!isless (xa, TWO52)) goto label; */
46473 /* x = (double)(long)x */
46485 }
46487 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46488 into OPERAND0. */
46489 void
46491 {
46496 /* C code for SSE variant we expand below.
46497 double xa = fabs (x), x2;
46498 if (!isless (xa, TWO52))
46499 return x;
46500 xa2 = xa + TWO52 - TWO52;
46501 Compensate:
46502 if (xa2 > xa)
46503 xa2 -= 1.0;
46504 x2 = copysign (xa2, x);
46505 return x2;
46506 */
46510 /* Temporary for holding the result, initialized to the input
46511 operand to ease control flow. */
46515 /* xa = abs (operand1) */
46518 /* if (!isless (xa, TWO52)) goto label; */
46521 /* res = xa + TWO52 - TWO52; */
46526 /* generate 1.0 */
46529 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46537 /* res = copysign (res, operand1) */
46544 }
46546 /* Expand SSE sequence for computing round from OPERAND1 storing
46547 into OPERAND0. */
46548 void
46550 {
46551 /* C code for the stuff we're doing below:
46552 double xa = fabs (x);
46553 if (!isless (xa, TWO52))
46554 return x;
46555 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46556 return copysign (xa, x);
46557 */
46564 /* Temporary for holding the result, initialized to the input
46565 operand to ease control flow. */
46573 /* load nextafter (0.5, 0.0) */
46578 /* xa = xa + 0.5 */
46582 /* xa = (double)(int64_t)xa */
46587 /* res = copysign (xa, operand1) */
46594 }
46596 /* Expand SSE sequence for computing round
46597 from OP1 storing into OP0 using sse4 round insn. */
46598 void
46600 {
46609 {
46620 }
46622 /* round (a) = trunc (a + copysign (0.5, a)) */
46624 /* load nextafter (0.5, 0.0) */
46630 /* e1 = copysign (0.5, op1) */
46634 /* e2 = op1 + e1 */
46637 /* res = trunc (e2) */
46642 }
46643 \f
46645 /* Table of valid machine attributes. */
46647 {
46648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46649 affects_type_identity } */
46650 /* Stdcall attribute says callee is responsible for popping arguments
46651 if they are not variable. */
46654 /* Fastcall attribute says callee is responsible for popping arguments
46655 if they are not variable. */
46658 /* Thiscall attribute says callee is responsible for popping arguments
46659 if they are not variable. */
46662 /* Cdecl attribute says the callee is a normal C declaration */
46665 /* Regparm attribute specifies how many integer arguments are to be
46666 passed in registers. */
46669 /* Sseregparm attribute says we are using x86_64 calling conventions
46670 for FP arguments. */
46673 /* The transactional memory builtins are implicitly regparm or fastcall
46674 depending on the ABI. Override the generic do-nothing attribute that
46675 these builtins were declared with. */
46678 /* force_align_arg_pointer says this function realigns the stack at entry. */
46681 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46686 #endif
46691 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46692 SUBTARGET_ATTRIBUTE_TABLE,
46693 #endif
46694 /* ms_abi and sysv_abi calling convention function attributes. */
46701 /* End element. */
46703 };
46705 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46706 static int
46709 {
46713 {
46758 }
46759 }
46761 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46762 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46763 insn every time. */
46767 /* Initialize vselect_insn. */
46769 static void
46771 {
46773 rtx x;
46784 }
46786 /* Construct (set target (vec_select op0 (parallel perm))) and
46787 return true if that's a valid instruction in the active ISA. */
46789 static bool
46792 {
46818 }
46820 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46822 static bool
46826 {
46827 machine_mode v2mode;
46828 rtx x;
46843 }
46845 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46846 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46848 static bool
46850 {
46860 ;
46862 ;
46864 ;
46866 ;
46867 else
46870 /* This is a blend, not a permute. Elements must stay in their
46871 respective lanes. */
46873 {
46877 }
46882 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46883 decision should be extracted elsewhere, so that we only try that
46884 sequence once all budget==3 options have been tried. */
46891 {
46921 /* See if bytes move in pairs so we can use pblendw with
46922 an immediate argument, rather than pblendvb with a vector
46923 argument. */
46926 {
46927 use_pblendvb:
46931 finish_pblendvb:
46937 else
46942 }
46947 /* FALLTHRU */
46949 do_subreg:
46956 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46960 /* See if bytes move in quadruplets. If yes, vpblendd
46961 with immediate can be used. */
46966 {
46967 /* See if bytes move the same in both lanes. If yes,
46968 vpblendw with immediate can be used. */
46973 /* Use vpblendw. */
46978 }
46980 /* Use vpblendd. */
46987 /* See if words move in pairs. If yes, vpblendd can be used. */
46992 {
46993 /* See if words move the same in both lanes. If not,
46994 vpblendvb must be used. */
46997 {
46998 /* Use vpblendvb. */
47008 }
47010 /* Use vpblendw. */
47014 }
47016 /* Use vpblendd. */
47023 /* Use vpblendd. */
47031 }
47033 /* This matches five different patterns with the different modes. */
47041 }
47043 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47044 in terms of the variable form of vpermilps.
47046 Note that we will have already failed the immediate input vpermilps,
47047 which requires that the high and low part shuffle be identical; the
47048 variable form doesn't require that. */
47050 static bool
47052 {
47059 /* We can only permute within the 128-bit lane. */
47061 {
47065 }
47071 {
47074 /* Within each 128-bit lane, the elements of op0 are numbered
47075 from 0 and the elements of op1 are numbered from 4. */
47082 }
47089 }
47091 /* Return true if permutation D can be performed as VMODE permutation
47092 instead. */
47094 static bool
47096 {
47111 else
47117 }
47119 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47120 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47122 static bool
47124 {
47133 {
47135 {
47138 {
47142 /* Use vperm2i128 insn. The pattern uses
47143 V4DImode instead of V2TImode. */
47156 }
47158 }
47159 }
47160 else
47161 {
47163 {
47166 }
47168 {
47172 /* V4DImode should be already handled through
47173 expand_vselect by vpermq instruction. */
47180 {
47181 /* First see if vpermq can be used for
47182 V8SImode/V16HImode/V32QImode. */
47184 {
47192 {
47196 }
47198 }
47200 /* Next see if vpermd can be used. */
47203 }
47204 /* Or if vpermps can be used. */
47209 {
47210 /* vpshufb only works intra lanes, it is not
47211 possible to shuffle bytes in between the lanes. */
47215 }
47216 }
47218 {
47222 /* If vpermq didn't work, vpshufb won't work either. */
47230 {
47231 /* First see if vpermq can be used for
47232 V16SImode/V32HImode/V64QImode. */
47234 {
47242 {
47246 }
47248 }
47250 /* Next see if vpermd can be used. */
47253 }
47254 /* Or if vpermps can be used. */
47258 {
47259 /* vpshufb only works intra lanes, it is not
47260 possible to shuffle bytes in between the lanes. */
47264 }
47265 }
47266 else
47268 }
47279 else
47280 {
47288 else
47292 {
47296 }
47297 }
47308 {
47323 else
47325 }
47326 else
47327 {
47330 }
47335 }
47337 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47338 in a single instruction. */
47340 static bool
47342 {
47346 /* Check plain VEC_SELECT first, because AVX has instructions that could
47347 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47348 input where SEL+CONCAT may not. */
47350 {
47356 {
47362 }
47365 {
47369 }
47371 {
47372 /* Use vpbroadcast{b,w,d}. */
47375 {
47418 /* For other modes prefer other shuffles this function creates. */
47420 }
47422 {
47426 }
47427 }
47432 /* There are plenty of patterns in sse.md that are written for
47433 SEL+CONCAT and are not replicated for a single op. Perhaps
47434 that should be changed, to avoid the nastiness here. */
47436 /* Recognize interleave style patterns, which means incrementing
47437 every other permutation operand. */
47439 {
47442 }
47447 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47449 {
47451 {
47456 }
47461 }
47462 }
47464 /* Finally, try the fully general two operand permute. */
47469 /* Recognize interleave style patterns with reversed operands. */
47471 {
47473 {
47477 else
47480 }
47485 }
47487 /* Try the SSE4.1 blend variable merge instructions. */
47491 /* Try one of the AVX vpermil variable permutations. */
47495 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47496 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47500 /* Try the AVX2 vpalignr instruction. */
47504 /* Try the AVX512F vpermi2 instructions. */
47509 }
47511 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47512 in terms of a pair of pshuflw + pshufhw instructions. */
47514 static bool
47516 {
47524 /* The two permutations only operate in 64-bit lanes. */
47535 /* Emit the pshuflw. */
47542 /* Emit the pshufhw. */
47550 }
47552 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47553 the permutation using the SSSE3 palignr instruction. This succeeds
47554 when all of the elements in PERM fit within one vector and we merely
47555 need to shift them down so that a single vector permutation has a
47556 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47557 the vpalignr instruction itself can perform the requested permutation. */
47559 static bool
47561 {
47568 /* Even with AVX, palignr only operates on 128-bit vectors,
47569 in AVX2 palignr operates on both 128-bit lanes. */
47579 {
47583 {
47586 }
47595 }
47598 {
47607 }
47609 /* Given that we have SSSE3, we know we'll be able to implement the
47610 single operand permutation after the palignr with pshufb for
47611 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47612 first. */
47618 {
47623 }
47627 {
47633 else
47638 }
47644 /* For AVX2, test whether we can permute the result in one instruction. */
47646 {
47651 }
47655 {
47659 }
47660 else
47661 {
47666 shift));
47667 }
47671 /* Test for the degenerate case where the alignment by itself
47672 produces the desired permutation. */
47674 {
47677 }
47683 }
47685 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47686 the permutation using the SSE4_1 pblendv instruction. Potentially
47687 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47689 static bool
47691 {
47697 /* Use the same checks as in expand_vec_perm_blend. */
47701 ;
47703 ;
47705 ;
47706 else
47709 /* Figure out where permutation elements stay not in their
47710 respective lanes. */
47712 {
47716 }
47717 /* We can pblend the part where elements stay not in their
47718 respective lanes only when these elements are all in one
47719 half of a permutation.
47720 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47721 lanes, but both 8 and 9 >= 8
47722 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47723 respective lanes and 8 >= 8, but 2 not. */
47729 /* First we apply one operand permutation to the part where
47730 elements stay not in their respective lanes. */
47734 else
47746 else
47751 /* Next we put permuted elements into their positions. */
47755 else
47765 }
47769 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47770 a two vector permutation into a single vector permutation by using
47771 an interleave operation to merge the vectors. */
47773 static bool
47775 {
47784 {
47787 }
47789 {
47792 /* For 32-byte modes allow even d->one_operand_p.
47793 The lack of cross-lane shuffling in some instructions
47794 might prevent a single insn shuffle. */
47797 /* If expand_vec_perm_interleave3 can expand this into
47798 a 3 insn sequence, give up and let it be expanded as
47799 3 insn sequence. While that is one insn longer,
47800 it doesn't need a memory operand and in the common
47801 case that both interleave low and high permutations
47802 with the same operands are adjacent needs 4 insns
47803 for both after CSE. */
47806 }
47807 else
47810 /* Examine from whence the elements come. */
47819 {
47822 /* Split the two input vectors into 4 halves. */
47828 /* If the elements from the low halves use interleave low, and similarly
47829 for interleave high. If the elements are from mis-matched halves, we
47830 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47832 {
47833 /* punpckl* */
47835 {
47840 }
47843 }
47845 {
47846 /* punpckh* */
47848 {
47853 }
47856 }
47858 {
47859 /* shufps */
47861 {
47866 }
47868 {
47869 /* shufpd */
47874 }
47875 }
47877 {
47878 /* shufps */
47880 {
47885 }
47887 {
47888 /* shufpd */
47893 }
47894 }
47895 else
47897 }
47898 else
47899 {
47904 /* Split the two input vectors into 8 quarters. */
47910 {
47913 }
47916 {
47920 }
47922 {
47925 }
47928 {
47930 {
47931 /* Attempt to increase the likelihood that dfinal
47932 shuffle will be intra-lane. */
47936 }
47938 /* vperm2f128 or vperm2i128. */
47940 {
47945 }
47950 {
47954 {
47957 }
47958 }
47959 }
47964 {
47965 /* vpunpckl* */
47967 {
47976 }
47977 }
47980 {
47981 /* vpunpckh* */
47983 {
47992 }
47993 }
47994 else
47996 }
47998 /* Use the remapping array set up above to move the elements from their
47999 swizzled locations into their final destinations. */
48002 {
48005 /* If same_halves is true, both halves of the remapped vector are the
48006 same. Avoid cross-lane accesses if possible. */
48008 {
48011 }
48012 else
48014 }
48016 {
48019 }
48023 /* Test if the final remap can be done with a single insn. For V4SFmode or
48024 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48037 {
48040 }
48047 }
48049 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48050 a single vector cross-lane permutation into vpermq followed
48051 by any of the single insn permutations. */
48053 static bool
48055 {
48069 {
48072 }
48075 {
48080 }
48093 {
48100 }
48107 {
48112 ;
48115 else
48117 }
48126 }
48128 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48129 a vector permutation using two instructions, vperm2f128 resp.
48130 vperm2i128 followed by any single in-lane permutation. */
48132 static bool
48134 {
48148 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48149 immediate. For perm < 16 the second permutation uses
48150 d->op0 as first operand, for perm >= 16 it uses d->op1
48151 as first operand. The second operand is the result of
48152 vperm2[fi]128. */
48154 {
48155 /* Ignore permutations which do not move anything cross-lane. */
48157 {
48158 /* The second shuffle for e.g. V4DFmode has
48159 0123 and ABCD operands.
48160 Ignore AB23, as 23 is already in the second lane
48161 of the first operand. */
48163 /* And 01CD, as 01 is in the first lane of the first
48164 operand. */
48166 /* And 4567, as then the vperm2[fi]128 doesn't change
48167 anything on the original 4567 second operand. */
48169 }
48170 else
48171 {
48172 /* The second shuffle for e.g. V4DFmode has
48173 4567 and ABCD operands.
48174 Ignore AB67, as 67 is already in the second lane
48175 of the first operand. */
48177 /* And 45CD, as 45 is in the first lane of the first
48178 operand. */
48180 /* And 0123, as then the vperm2[fi]128 doesn't change
48181 anything on the original 0123 first operand. */
48183 }
48186 {
48192 else
48194 }
48197 {
48201 }
48202 else
48206 {
48210 /* Found a usable second shuffle. dfirst will be
48211 vperm2f128 on d->op0 and d->op1. */
48223 /* And dsecond is some single insn shuffle, taking
48224 d->op0 and result of vperm2f128 (if perm < 16) or
48225 d->op1 and result of vperm2f128 (otherwise). */
48234 }
48236 /* For one operand, the only useful vperm2f128 permutation is 0x01
48237 aka lanes swap. */
48240 }
48243 }
48245 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48246 a two vector permutation using 2 intra-lane interleave insns
48247 and cross-lane shuffle for 32-byte vectors. */
48249 static bool
48251 {
48258 ;
48260 ;
48261 else
48276 {
48280 else
48286 else
48292 else
48298 else
48304 else
48310 else
48315 }
48319 }
48321 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48322 a single vector permutation using a single intra-lane vector
48323 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48324 the non-swapped and swapped vectors together. */
48326 static bool
48328 {
48336 || TARGET_AVX2
48345 {
48352 }
48387 }
48389 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48390 permutation using two vperm2f128, followed by a vshufpd insn blending
48391 the two vectors together. */
48393 static bool
48395 {
48438 }
48440 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48441 permutation with two pshufb insns and an ior. We should have already
48442 failed all two instruction sequences. */
48444 static bool
48446 {
48460 /* Generate two permutation masks. If the required element is within
48461 the given vector it is shuffled into the proper lane. If the required
48462 element is in the other vector, force a zero into the lane by setting
48463 bit 7 in the permutation mask. */
48466 {
48473 {
48476 }
48477 }
48501 }
48503 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48504 with two vpshufb insns, vpermq and vpor. We should have already failed
48505 all two or three instruction sequences. */
48507 static bool
48509 {
48524 /* Generate two permutation masks. If the required element is within
48525 the same lane, it is shuffled in. If the required element from the
48526 other lane, force a zero by setting bit 7 in the permutation mask.
48527 In the other mask the mask has non-negative elements if element
48528 is requested from the other lane, but also moved to the other lane,
48529 so that the result of vpshufb can have the two V2TImode halves
48530 swapped. */
48533 {
48538 {
48541 }
48542 }
48551 /* Swap the 128-byte lanes of h into hp. */
48555 const1_rtx));
48572 }
48574 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48575 and extract-odd permutations of two V32QImode and V16QImode operand
48576 with two vpshufb insns, vpor and vpermq. We should have already
48577 failed all two or three instruction sequences. */
48579 static bool
48581 {
48600 /* Generate two permutation masks. In the first permutation mask
48601 the first quarter will contain indexes for the first half
48602 of the op0, the second quarter will contain bit 7 set, third quarter
48603 will contain indexes for the second half of the op0 and the
48604 last quarter bit 7 set. In the second permutation mask
48605 the first quarter will contain bit 7 set, the second quarter
48606 indexes for the first half of the op1, the third quarter bit 7 set
48607 and last quarter indexes for the second half of the op1.
48608 I.e. the first mask e.g. for V32QImode extract even will be:
48609 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48610 (all values masked with 0xf except for -128) and second mask
48611 for extract even will be
48612 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48615 {
48621 {
48624 }
48625 }
48644 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48652 }
48654 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48655 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48656 with two "and" and "pack" or two "shift" and "pack" insns. We should
48657 have already failed all two instruction sequences. */
48659 static bool
48661 {
48665 machine_mode half_mode;
48674 {
48676 /* Required for "pack". */
48687 /* No check as all instructions are SSE2. */
48718 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48719 general shuffles. */
48721 }
48723 /* Check that permutation is even or odd. */
48738 {
48745 }
48746 else
48747 {
48754 }
48755 /* In AVX2 for 256 bit case we need to permute pack result. */
48757 {
48763 const0_rtx,
48764 const2_rtx,
48765 const1_rtx,
48768 }
48769 else
48773 }
48775 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48776 and extract-odd permutations. */
48778 static bool
48780 {
48784 {
48791 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48795 /* Now an unpck[lh]pd will produce the result required. */
48798 else
48804 {
48813 /* Shuffle within the 128-bit lanes to produce:
48814 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48818 /* Shuffle the lanes around to produce:
48819 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48823 /* Shuffle within the 128-bit lanes to produce:
48824 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48827 /* Shuffle within the 128-bit lanes to produce:
48828 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48831 /* Shuffle the lanes around to produce:
48832 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48835 }
48842 /* These are always directly implementable by expand_vec_perm_1. */
48850 else
48851 {
48854 /* We need 2*log2(N)-1 operations to achieve odd/even
48855 with interleave. */
48864 else
48867 }
48879 {
48884 else
48889 {
48894 }
48896 }
48904 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48908 /* Now an vpunpck[lh]qdq will produce the result required. */
48911 else
48918 {
48923 else
48928 {
48933 }
48935 }
48946 /* Shuffle the lanes around into
48947 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
48955 /* Swap the 2nd and 3rd position in each lane into
48956 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
48962 /* Now an vpunpck[lh]qdq will produce
48963 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
48967 else
48976 }
48979 }
48981 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
48982 extract-even and extract-odd permutations. */
48984 static bool
48986 {
48998 }
49000 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49001 permutations. We assume that expand_vec_perm_1 has already failed. */
49003 static bool
49005 {
49013 {
49016 /* These are special-cased in sse.md so that we can optionally
49017 use the vbroadcast instruction. They expand to two insns
49018 if the input happens to be in a register. */
49025 /* These are always implementable using standard shuffle patterns. */
49030 /* These can be implemented via interleave. We save one insn by
49031 stopping once we have promoted to V4SImode and then use pshufd. */
49034 do
49035 {
49036 rtx dest;
49042 {
49046 }
49053 }
49069 /* For AVX2 broadcasts of the first element vpbroadcast* or
49070 vpermq should be used by expand_vec_perm_1. */
49076 }
49077 }
49079 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49080 broadcast permutations. */
49082 static bool
49084 {
49096 }
49098 /* Implement arbitrary permutations of two V64QImode operands
49099 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49100 static bool
49102 {
49112 machine_mode vmode;
49118 {
49125 }
49127 /* Prepare permutations such that the first one takes care of
49128 putting the even bytes into the right positions or one higher
49129 positions (ds[0]) and the second one takes care of
49130 putting the odd bytes into the right positions or one below
49131 (ds[1]). */
49134 {
49137 {
49140 }
49141 else
49142 {
49145 }
49146 }
49168 }
49170 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49171 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49172 all the shorter instruction sequences. */
49174 static bool
49176 {
49192 /* Generate 4 permutation masks. If the required element is within
49193 the same lane, it is shuffled in. If the required element from the
49194 other lane, force a zero by setting bit 7 in the permutation mask.
49195 In the other mask the mask has non-negative elements if element
49196 is requested from the other lane, but also moved to the other lane,
49197 so that the result of vpshufb can have the two V2TImode halves
49198 swapped. */
49201 {
49206 }
49212 {
49220 }
49223 {
49225 {
49228 }
49235 }
49237 /* Swap the 128-byte lanes of h[X]. */
49239 {
49245 const1_rtx));
49247 }
49250 {
49252 {
49255 }
49261 }
49264 {
49266 {
49270 }
49273 }
49283 }
49285 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49286 With all of the interface bits taken care of, perform the expansion
49287 in D and return true on success. */
49289 static bool
49291 {
49292 /* Try a single instruction expansion. */
49296 /* Try sequences of two instructions. */
49319 /* Try sequences of three instructions. */
49336 /* Try sequences of four instructions. */
49347 /* ??? Look for narrow permutations whose element orderings would
49348 allow the promotion to a wider mode. */
49350 /* ??? Look for sequences of interleave or a wider permute that place
49351 the data into the correct lanes for a half-vector shuffle like
49352 pshuf[lh]w or vpermilps. */
49354 /* ??? Look for sequences of interleave that produce the desired results.
49355 The combinatorics of punpck[lh] get pretty ugly... */
49360 /* Even longer sequences. */
49365 }
49367 /* If a permutation only uses one operand, make it clear. Returns true
49368 if the permutation references both operands. */
49370 static bool
49372 {
49380 {
49386 {
49389 }
49390 /* The elements of PERM do not suggest that only the first operand
49391 is used, but both operands are identical. Allow easier matching
49392 of the permutation by folding the permutation into the single
49393 input vector. */
49394 /* FALLTHRU */
49405 }
49408 }
49410 bool
49412 {
49417 rtx sel;
49434 {
49439 }
49446 /* If the selector says both arguments are needed, but the operands are the
49447 same, the above tried to expand with one_operand_p and flattened selector.
49448 If that didn't work, retry without one_operand_p; we succeeded with that
49449 during testing. */
49451 {
49455 }
49458 }
49460 /* Implement targetm.vectorize.vec_perm_const_ok. */
49462 static bool
49465 {
49474 /* Given sufficient ISA support we can just return true here
49475 for selected vector modes. */
49477 {
49483 /* All implementable with a single vpermi2 insn. */
49488 /* All implementable with a single vpermi2 insn. */
49493 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49501 /* All implementable with a single vpermi2 insn. */
49506 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49511 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49518 /* All implementable with a single vpperm insn. */
49521 /* All implementable with 2 pshufb + 1 ior. */
49527 /* All implementable with shufpd or unpck[lh]pd. */
49531 }
49533 /* Extract the values from the vector CST into the permutation
49534 array in D. */
49537 {
49541 }
49543 /* For all elements from second vector, fold the elements to first. */
49548 /* Check whether the mask can be applied to the vector type. */
49551 /* Implementable with shufps or pshufd. */
49555 /* Otherwise we have to go through the motions and see if we can
49556 figure out how to generate the requested permutation. */
49567 }
49569 void
49571 {
49586 /* We'll either be able to implement the permutation directly... */
49590 /* ... or we use the special-case patterns. */
49592 }
49594 static void
49596 {
49611 {
49614 }
49616 /* Note that for AVX this isn't one instruction. */
49619 }
49622 /* Expand a vector operation CODE for a V*QImode in terms of the
49623 same operation on V*HImode. */
49625 void
49627 {
49629 machine_mode himode;
49639 {
49657 }
49661 {
49663 /* Unpack data such that we've got a source byte in each low byte of
49664 each word. We don't care what goes into the high byte of each word.
49665 Rather than trying to get zero in there, most convenient is to let
49666 it be a copy of the low byte. */
49671 /* FALLTHRU */
49683 /* FALLTHRU */
49693 }
49695 /* Perform the operation. */
49702 /* Merge the data back into the right place. */
49712 {
49713 /* For SSE2, we used an full interleave, so the desired
49714 results are in the even elements. */
49717 }
49718 else
49719 {
49720 /* For AVX, the interleave used above was not cross-lane. So the
49721 extraction is evens but with the second and third quarter swapped.
49722 Happily, that is even one insn shorter than even extraction. */
49725 }
49732 }
49734 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49735 if op is CONST_VECTOR with all odd elements equal to their
49736 preceding element. */
49738 static bool
49740 {
49750 }
49752 void
49755 {
49758 rtx x;
49766 /* We only play even/odd games with vectors of SImode. */
49769 /* If we're looking for the odd results, shift those members down to
49770 the even slots. For some cpus this is faster than a PSHUFD. */
49772 {
49773 /* For XOP use vpmacsdqh, but only for smult, as it is only
49774 signed. */
49776 {
49780 }
49791 }
49794 {
49797 else
49799 }
49801 {
49804 else
49806 }
49811 else
49812 {
49815 /* The easiest way to implement this without PMULDQ is to go through
49816 the motions as if we are performing a full 64-bit multiply. With
49817 the exception that we need to do less shuffling of the elements. */
49819 /* Compute the sign-extension, aka highparts, of the two operands. */
49825 /* Multiply LO(A) * HI(B), and vice-versa. */
49831 /* Multiply LO(A) * LO(B). */
49835 /* Combine and shift the highparts into place. */
49840 /* Combine high and low parts. */
49843 }
49845 }
49847 void
49850 {
49856 {
49861 {
49862 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49863 shuffle the elements once so that all elements are in the right
49864 place for immediate use: { A C B D }. */
49869 }
49870 else
49871 {
49872 /* Put the elements into place for the multiply. */
49876 }
49881 /* Shuffle the elements between the lanes. After this we
49882 have { A B E F | C D G H } for each operand. */
49892 /* Shuffle the elements within the lanes. After this we
49893 have { A A B B | C C D D } or { E E F F | G G H H }. */
49934 }
49935 }
49937 void
49939 {
49949 /* Move the results in element 2 down to element 1; we don't care
49950 what goes in elements 2 and 3. Then we can merge the parts
49951 back together with an interleave.
49953 Note that two other sequences were tried:
49954 (1) Use interleaves at the start instead of psrldq, which allows
49955 us to use a single shufps to merge things back at the end.
49956 (2) Use shufps here to combine the two vectors, then pshufd to
49957 put the elements in the correct order.
49958 In both cases the cost of the reformatting stall was too high
49959 and the overall sequence slower. */
49970 }
49972 void
49974 {
49985 {
49986 /* op1: A,B,C,D, op2: E,F,G,H */
49995 /* t1: B,A,D,C */
50002 /* t2: (B*E),(A*F),(D*G),(C*H) */
50005 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50008 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50011 /* Multiply lower parts and add all */
50018 }
50019 else
50020 {
50021 machine_mode nmode;
50025 {
50028 }
50030 {
50033 }
50035 {
50038 }
50039 else
50043 /* Multiply low parts. */
50047 /* Shift input vectors right 32 bits so we can multiply high parts. */
50052 /* Multiply high parts by low parts. */
50058 /* Combine and shift the highparts back. */
50062 /* Combine high and low parts. */
50064 }
50068 }
50070 /* Return 1 if control tansfer instruction INSN
50071 should be encoded with bnd prefix.
50072 If insn is NULL then return 1 when control
50073 transfer instructions should be prefixed with
50074 bnd by default for current function. */
50076 bool
50078 {
50079 /* For call insns check special flag. */
50081 {
50085 }
50087 /* All other insns are prefixed only if function is instrumented. */
50089 }
50091 /* Calculate integer abs() using only SSE2 instructions. */
50093 void
50095 {
50100 {
50101 /* For 32-bit signed integer X, the best way to calculate the absolute
50102 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50114 /* For 16-bit signed integer X, the best way to calculate the absolute
50115 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50123 /* For 8-bit signed integer X, the best way to calculate the absolute
50124 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50125 as SSE2 provides the PMINUB insn. */
50135 }
50139 }
50141 /* Expand an insert into a vector register through pinsr insn.
50142 Return true if successful. */
50144 bool
50146 {
50154 {
50157 }
50163 {
50168 {
50175 {
50207 }
50221 }
50225 }
50226 }
50227 \f
50228 /* This function returns the calling abi specific va_list type node.
50229 It returns the FNDECL specific va_list type. */
50231 static tree
50233 {
50240 else
50242 }
50244 /* Returns the canonical va_list type specified by TYPE. If there
50245 is no valid TYPE provided, it return NULL_TREE. */
50247 static tree
50249 {
50252 /* Resolve references and pointers to va_list type. */
50261 {
50266 {
50267 /* If va_list is an array type, the argument may have decayed
50268 to a pointer type, e.g. by being passed to another function.
50269 In that case, unwrap both types so that we can compare the
50270 underlying records. */
50273 {
50276 }
50277 }
50284 {
50285 /* If va_list is an array type, the argument may have decayed
50286 to a pointer type, e.g. by being passed to another function.
50287 In that case, unwrap both types so that we can compare the
50288 underlying records. */
50291 {
50294 }
50295 }
50302 {
50303 /* If va_list is an array type, the argument may have decayed
50304 to a pointer type, e.g. by being passed to another function.
50305 In that case, unwrap both types so that we can compare the
50306 underlying records. */
50309 {
50312 }
50313 }
50317 }
50319 }
50321 /* Iterate through the target-specific builtin types for va_list.
50322 IDX denotes the iterator, *PTREE is set to the result type of
50323 the va_list builtin, and *PNAME to its internal type.
50324 Returns zero if there is no element for this index, otherwise
50325 IDX should be increased upon the next call.
50326 Note, do not iterate a base builtin's name like __builtin_va_list.
50327 Used from c_common_nodes_and_builtins. */
50329 static int
50331 {
50333 {
50335 {
50348 }
50349 }
50352 }
50354 #undef TARGET_SCHED_DISPATCH
50355 #define TARGET_SCHED_DISPATCH has_dispatch
50356 #undef TARGET_SCHED_DISPATCH_DO
50357 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50358 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50359 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50360 #undef TARGET_SCHED_REORDER
50361 #define TARGET_SCHED_REORDER ix86_sched_reorder
50362 #undef TARGET_SCHED_ADJUST_PRIORITY
50363 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50364 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50365 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50366 ix86_dependencies_evaluation_hook
50368 /* The size of the dispatch window is the total number of bytes of
50369 object code allowed in a window. */
50370 #define DISPATCH_WINDOW_SIZE 16
50372 /* Number of dispatch windows considered for scheduling. */
50373 #define MAX_DISPATCH_WINDOWS 3
50375 /* Maximum number of instructions in a window. */
50376 #define MAX_INSN 4
50378 /* Maximum number of immediate operands in a window. */
50379 #define MAX_IMM 4
50381 /* Maximum number of immediate bits allowed in a window. */
50382 #define MAX_IMM_SIZE 128
50384 /* Maximum number of 32 bit immediates allowed in a window. */
50385 #define MAX_IMM_32 4
50387 /* Maximum number of 64 bit immediates allowed in a window. */
50388 #define MAX_IMM_64 2
50390 /* Maximum total of loads or prefetches allowed in a window. */
50391 #define MAX_LOAD 2
50393 /* Maximum total of stores allowed in a window. */
50394 #define MAX_STORE 1
50396 #undef BIG
50397 #define BIG 100
50400 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50403 disp_load,
50404 disp_store,
50405 disp_load_store,
50406 disp_prefetch,
50407 disp_imm,
50408 disp_imm_32,
50409 disp_imm_64,
50410 disp_branch,
50411 disp_cmp,
50412 disp_jcc,
50413 disp_last
50414 };
50416 /* Number of allowable groups in a dispatch window. It is an array
50417 indexed by dispatch_group enum. 100 is used as a big number,
50418 because the number of these kind of operations does not have any
50419 effect in dispatch window, but we need them for other reasons in
50420 the table. */
50423 };
50429 };
50431 /* Instruction path. */
50437 last_path
50438 };
50440 /* sched_insn_info defines a window to the instructions scheduled in
50441 the basic block. It contains a pointer to the insn_info table and
50442 the instruction scheduled.
50444 Windows are allocated for each basic block and are linked
50445 together. */
50447 rtx insn;
50454 /* Linked list of dispatch windows. This is a two way list of
50455 dispatch windows of a basic block. It contains information about
50456 the number of uops in the window and the total number of
50457 instructions and of bytes in the object code for this dispatch
50458 window. */
50476 /* Immediate valuse used in an insn. */
50478 {
50487 /* Get dispatch group of insn. */
50489 static enum dispatch_group
50491 {
50507 }
50509 /* Return true if insn is a compare instruction. */
50511 static bool
50513 {
50521 }
50523 /* Return true if a dispatch violation encountered. */
50525 static bool
50527 {
50531 }
50533 /* Return true if insn is a branch instruction. */
50535 static bool
50537 {
50539 }
50541 /* Return true if insn is a prefetch instruction. */
50543 static bool
50545 {
50547 }
50549 /* This function initializes a dispatch window and the list container holding a
50550 pointer to the window. */
50552 static void
50554 {
50560 else
50578 {
50584 }
50586 }
50588 /* This function allocates and initializes a dispatch window and the
50589 list container holding a pointer to the window. */
50593 {
50598 }
50600 /* This routine initializes the dispatch scheduling information. It
50601 initiates building dispatch scheduler tables and constructs the
50602 first dispatch window. */
50604 static void
50606 {
50607 /* Allocate a dispatch list and a window. */
50612 }
50614 /* This function returns true if a branch is detected. End of a basic block
50615 does not have to be a branch, but here we assume only branches end a
50616 window. */
50618 static bool
50620 {
50622 }
50624 /* This function is called when the end of a window processing is reached. */
50626 static void
50628 {
50631 {
50636 }
50638 }
50640 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50641 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50642 for 48 bytes of instructions. Note that these windows are not dispatch
50643 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50647 {
50649 {
50654 }
50660 }
50662 /* Compute number of immediate operands of an instruction. */
50664 static void
50666 {
50673 {
50680 else
50691 {
50694 }
50699 }
50700 }
50702 /* Return total size of immediate operands of an instruction along with number
50703 of corresponding immediate-operands. It initializes its parameters to zero
50704 befor calling FIND_CONSTANT.
50705 INSN is the input instruction. IMM is the total of immediates.
50706 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50707 bit immediates. */
50709 static int
50711 {
50719 }
50721 /* This function indicates if an operand of an instruction is an
50722 immediate. */
50724 static bool
50726 {
50735 }
50737 /* Return single or double path for instructions. */
50739 static enum insn_path
50741 {
50751 }
50753 /* Return insn dispatch group. */
50755 static enum dispatch_group
50757 {
50775 }
50777 /* Count number of GROUP restricted instructions in a dispatch
50778 window WINDOW_LIST. */
50780 static int
50782 {
50793 {
50812 }
50825 }
50827 /* This function returns true if insn satisfies dispatch rules on the
50828 last window scheduled. */
50830 static bool
50832 {
50840 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50841 instructions should be given the lowest priority in the
50842 scheduling process in Haifa scheduler to make sure they will be
50843 scheduled in the same dispatch window as the reference to them. */
50847 /* Check nonrestricted. */
50851 /* Get last dispatch window. */
50856 {
50861 /* Window 1 is full. Go for next window. */
50863 }
50870 /* See if it fits in the first window. */
50872 {
50873 /* The first widow should have only single and double path
50874 uops. */
50880 }
50882 }
50884 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50885 dispatch window WINDOW_LIST. */
50887 static void
50889 {
50907 /* Initialize window with new instruction. */
50928 {
50931 }
50932 }
50934 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50935 If the total bytes of instructions or the number of instructions in
50936 the window exceed allowable, it allocates a new window. */
50938 static void
50940 {
50963 /* Get the last dispatch window. */
50971 else
50974 /* If current window is full, get a new window.
50975 Window number zero is full, if MAX_INSN uops are scheduled in it.
50976 Window number one is full, if window zero's bytes plus window
50977 one's bytes is 32, or if the bytes of the new instruction added
50978 to the total makes it greater than 48, or it has already MAX_INSN
50979 instructions in it. */
50988 {
50991 }
50994 {
50998 {
51001 }
51002 }
51004 {
51009 {
51012 }
51015 }
51016 else
51020 {
51021 /* End of basic block is reached do end-basic-block process. */
51024 }
51025 }
51027 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51029 DEBUG_FUNCTION static void
51031 {
51037 else
51051 {
51054 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51060 }
51061 }
51063 /* Print to stdout a dispatch window. */
51065 DEBUG_FUNCTION void
51067 {
51069 }
51071 /* Print INSN dispatch information to FILE. */
51073 DEBUG_FUNCTION static void
51075 {
51098 }
51100 /* Print to STDERR the status of the ready list with respect to
51101 dispatch windows. */
51103 DEBUG_FUNCTION void
51105 {
51113 }
51115 /* This routine is the driver of the dispatch scheduler. */
51117 static void
51119 {
51124 }
51126 /* Return TRUE if Dispatch Scheduling is supported. */
51128 static bool
51130 {
51134 {
51150 }
51153 }
51155 /* Implementation of reassociation_width target hook used by
51156 reassoc phase to identify parallelism level in reassociated
51157 tree. Statements tree_code is passed in OPC. Arguments type
51158 is passed in MODE.
51160 Currently parallel reassociation is enabled for Atom
51161 processors only and we set reassociation width to be 2
51162 because Atom may issue up to 2 instructions per cycle.
51164 Return value should be fixed if parallel reassociation is
51165 enabled for other processors. */
51167 static int
51169 {
51170 /* Vector part. */
51172 {
51175 else
51177 }
51179 /* Scalar part. */
51184 else
51186 }
51188 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51189 place emms and femms instructions. */
51191 static machine_mode
51193 {
51198 {
51217 else
51229 /* FALLTHRU */
51233 }
51234 }
51236 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51237 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51238 256bit and 128bit vectors. */
51240 static unsigned int
51242 {
51245 }
51247 \f
51249 /* Return class of registers which could be used for pseudo of MODE
51250 and of class RCLASS for spilling instead of memory. Return NO_REGS
51251 if it is not possible or non-profitable. */
51252 static reg_class_t
51254 {
51260 }
51262 /* Implement targetm.vectorize.init_cost. */
51266 {
51270 }
51272 /* Implement targetm.vectorize.add_stmt_cost. */
51274 static unsigned
51278 {
51285 /* Statements in an inner loop relative to the loop being
51286 vectorized are weighted more heavily. The value here is
51287 arbitrary and could potentially be improved with analysis. */
51293 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51294 for Silvermont as it has out of order integer pipeline and can execute
51295 2 scalar instruction per tick, but has in order SIMD pipeline. */
51298 {
51302 }
51307 }
51309 /* Implement targetm.vectorize.finish_cost. */
51311 static void
51314 {
51319 }
51321 /* Implement targetm.vectorize.destroy_cost_data. */
51323 static void
51325 {
51327 }
51329 /* Validate target specific memory model bits in VAL. */
51331 static unsigned HOST_WIDE_INT
51333 {
51340 {
51344 }
51347 {
51351 }
51353 {
51357 }
51359 }
51361 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51362 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51363 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51364 or number of vecsize_mangle variants that should be emitted. */
51366 static int
51370 {
51377 {
51381 }
51386 {
51393 /* case SCmode: */
51394 /* case DCmode: */
51400 }
51402 tree t;
51406 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51408 {
51415 /* case SCmode: */
51416 /* case DCmode: */
51422 }
51425 {
51426 /* Parse here processor clause. If not present, default to 'b'. */
51428 }
51430 {
51431 /* If the function isn't exported, we can pick up just one ISA
51432 for the clones. */
51437 else
51440 }
51441 else
51442 {
51445 }
51447 {
51460 }
51462 {
51465 else
51470 }
51472 }
51474 /* Add target attribute to SIMD clone NODE if needed. */
51476 static void
51478 {
51482 {
51497 }
51507 }
51509 /* If SIMD clone NODE can't be used in a vectorized loop
51510 in current function, return -1, otherwise return a badness of using it
51511 (0 if it is most desirable from vecsize_mangle point of view, 1
51512 slightly less desirable, etc.). */
51514 static int
51516 {
51518 {
51536 }
51537 }
51539 /* This function adjusts the unroll factor based on
51540 the hardware capabilities. For ex, bdver3 has
51541 a loop buffer which makes unrolling of smaller
51542 loops less important. This function decides the
51543 unroll factor using number of memory references
51544 (value 32 is used) as a heuristic. */
51546 static unsigned
51548 {
51557 /* Count the number of memory references within the loop body.
51558 This value determines the unrolling factor for bdver3 and bdver4
51559 architectures. */
51568 {
51573 else
51575 }
51582 }
51585 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51587 static bool
51589 {
51590 /* For x87 floating point with standard excess precision handling,
51591 there is no adddf3 pattern (since x87 floating point only has
51592 XFmode operations) so the default hook implementation gets this
51593 wrong. */
51595 }
51597 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51599 static void
51601 {
51606 {
51621 hold_fnclex);
51634 }
51636 {
51645 mxcsr_orig_var,
51655 ldmxcsr_hold_call);
51658 else
51663 ldmxcsr_clear_call);
51664 else
51668 stxmcsr_update_call);
51670 {
51676 exceptions_assign);
51677 }
51678 else
51683 ldmxcsr_update_call);
51684 }
51685 tree atomic_feraiseexcept
51690 atomic_feraiseexcept_call);
51691 }
51693 /* Return mode to be used for bounds or VOIDmode
51694 if bounds are not supported. */
51696 static enum machine_mode
51698 {
51699 /* Do not support pointer checker if MPX
51700 is not enabled. */
51702 {
51707 }
51710 }
51712 /* Return constant used to statically initialize constant bounds.
51714 This function is used to create special bound values. For now
51715 only INIT bounds and NONE bounds are expected. More special
51716 values may be added later. */
51718 static tree
51720 {
51726 /* This function is supposed to be used to create INIT and
51727 NONE bounds only. */
51732 }
51734 /* Generate a list of statements STMTS to initialize pointer bounds
51735 variable VAR with bounds LB and UB. Return the number of generated
51736 statements. */
51738 static int
51740 {
51758 }
51760 /* Initialize the GCC target structure. */
51761 #undef TARGET_RETURN_IN_MEMORY
51762 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51764 #undef TARGET_LEGITIMIZE_ADDRESS
51765 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51767 #undef TARGET_ATTRIBUTE_TABLE
51768 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51769 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51770 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51771 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51772 # undef TARGET_MERGE_DECL_ATTRIBUTES
51773 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51774 #endif
51776 #undef TARGET_COMP_TYPE_ATTRIBUTES
51777 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51779 #undef TARGET_INIT_BUILTINS
51780 #define TARGET_INIT_BUILTINS ix86_init_builtins
51781 #undef TARGET_BUILTIN_DECL
51782 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51783 #undef TARGET_EXPAND_BUILTIN
51784 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51786 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51787 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51788 ix86_builtin_vectorized_function
51790 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51791 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51793 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51794 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51796 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51797 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51799 #undef TARGET_BUILTIN_RECIPROCAL
51800 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51802 #undef TARGET_ASM_FUNCTION_EPILOGUE
51803 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51805 #undef TARGET_ENCODE_SECTION_INFO
51806 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51807 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51808 #else
51809 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51810 #endif
51812 #undef TARGET_ASM_OPEN_PAREN
51814 #undef TARGET_ASM_CLOSE_PAREN
51817 #undef TARGET_ASM_BYTE_OP
51818 #define TARGET_ASM_BYTE_OP ASM_BYTE
51820 #undef TARGET_ASM_ALIGNED_HI_OP
51821 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51822 #undef TARGET_ASM_ALIGNED_SI_OP
51823 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51824 #ifdef ASM_QUAD
51825 #undef TARGET_ASM_ALIGNED_DI_OP
51826 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51827 #endif
51829 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51830 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51832 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51833 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51835 #undef TARGET_ASM_UNALIGNED_HI_OP
51836 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51837 #undef TARGET_ASM_UNALIGNED_SI_OP
51838 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51839 #undef TARGET_ASM_UNALIGNED_DI_OP
51840 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
51842 #undef TARGET_PRINT_OPERAND
51843 #define TARGET_PRINT_OPERAND ix86_print_operand
51844 #undef TARGET_PRINT_OPERAND_ADDRESS
51845 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
51846 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
51847 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
51848 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
51849 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
51851 #undef TARGET_SCHED_INIT_GLOBAL
51852 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
51853 #undef TARGET_SCHED_ADJUST_COST
51854 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
51855 #undef TARGET_SCHED_ISSUE_RATE
51856 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
51857 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
51858 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
51859 ia32_multipass_dfa_lookahead
51860 #undef TARGET_SCHED_MACRO_FUSION_P
51861 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
51862 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
51863 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
51865 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
51866 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
51868 #undef TARGET_MEMMODEL_CHECK
51869 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
51871 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
51872 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
51874 #ifdef HAVE_AS_TLS
51875 #undef TARGET_HAVE_TLS
51876 #define TARGET_HAVE_TLS true
51877 #endif
51878 #undef TARGET_CANNOT_FORCE_CONST_MEM
51879 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
51880 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
51881 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
51883 #undef TARGET_DELEGITIMIZE_ADDRESS
51884 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
51886 #undef TARGET_MS_BITFIELD_LAYOUT_P
51887 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
51889 #if TARGET_MACHO
51890 #undef TARGET_BINDS_LOCAL_P
51891 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
51892 #endif
51893 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51894 #undef TARGET_BINDS_LOCAL_P
51895 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
51896 #endif
51898 #undef TARGET_ASM_OUTPUT_MI_THUNK
51899 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
51900 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
51901 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
51903 #undef TARGET_ASM_FILE_START
51904 #define TARGET_ASM_FILE_START x86_file_start
51906 #undef TARGET_OPTION_OVERRIDE
51907 #define TARGET_OPTION_OVERRIDE ix86_option_override
51909 #undef TARGET_REGISTER_MOVE_COST
51910 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
51911 #undef TARGET_MEMORY_MOVE_COST
51912 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
51913 #undef TARGET_RTX_COSTS
51914 #define TARGET_RTX_COSTS ix86_rtx_costs
51915 #undef TARGET_ADDRESS_COST
51916 #define TARGET_ADDRESS_COST ix86_address_cost
51918 #undef TARGET_FIXED_CONDITION_CODE_REGS
51919 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
51920 #undef TARGET_CC_MODES_COMPATIBLE
51921 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
51923 #undef TARGET_MACHINE_DEPENDENT_REORG
51924 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
51926 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
51927 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
51929 #undef TARGET_BUILD_BUILTIN_VA_LIST
51930 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
51932 #undef TARGET_FOLD_BUILTIN
51933 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
51935 #undef TARGET_COMPARE_VERSION_PRIORITY
51936 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
51938 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
51939 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
51940 ix86_generate_version_dispatcher_body
51942 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
51943 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
51944 ix86_get_function_versions_dispatcher
51946 #undef TARGET_ENUM_VA_LIST_P
51947 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
51949 #undef TARGET_FN_ABI_VA_LIST
51950 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
51952 #undef TARGET_CANONICAL_VA_LIST_TYPE
51953 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
51955 #undef TARGET_EXPAND_BUILTIN_VA_START
51956 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
51958 #undef TARGET_MD_ASM_CLOBBERS
51959 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
51961 #undef TARGET_PROMOTE_PROTOTYPES
51962 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
51963 #undef TARGET_SETUP_INCOMING_VARARGS
51964 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
51965 #undef TARGET_MUST_PASS_IN_STACK
51966 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
51967 #undef TARGET_FUNCTION_ARG_ADVANCE
51968 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
51969 #undef TARGET_FUNCTION_ARG
51970 #define TARGET_FUNCTION_ARG ix86_function_arg
51971 #undef TARGET_INIT_PIC_REG
51972 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
51973 #undef TARGET_USE_PSEUDO_PIC_REG
51974 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
51975 #undef TARGET_FUNCTION_ARG_BOUNDARY
51976 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
51977 #undef TARGET_PASS_BY_REFERENCE
51978 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
51979 #undef TARGET_INTERNAL_ARG_POINTER
51980 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
51981 #undef TARGET_UPDATE_STACK_BOUNDARY
51982 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
51983 #undef TARGET_GET_DRAP_RTX
51984 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
51985 #undef TARGET_STRICT_ARGUMENT_NAMING
51986 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
51987 #undef TARGET_STATIC_CHAIN
51988 #define TARGET_STATIC_CHAIN ix86_static_chain
51989 #undef TARGET_TRAMPOLINE_INIT
51990 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
51991 #undef TARGET_RETURN_POPS_ARGS
51992 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
51994 #undef TARGET_LEGITIMATE_COMBINED_INSN
51995 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
51997 #undef TARGET_ASAN_SHADOW_OFFSET
51998 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52000 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52001 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52003 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52004 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52006 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52007 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52009 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52010 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52011 ix86_libgcc_floating_mode_supported_p
52013 #undef TARGET_C_MODE_FOR_SUFFIX
52014 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52016 #ifdef HAVE_AS_TLS
52017 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52018 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52019 #endif
52021 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52022 #undef TARGET_INSERT_ATTRIBUTES
52023 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52024 #endif
52026 #undef TARGET_MANGLE_TYPE
52027 #define TARGET_MANGLE_TYPE ix86_mangle_type
52029 #if !TARGET_MACHO
52030 #undef TARGET_STACK_PROTECT_FAIL
52031 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52032 #endif
52034 #undef TARGET_FUNCTION_VALUE
52035 #define TARGET_FUNCTION_VALUE ix86_function_value
52037 #undef TARGET_FUNCTION_VALUE_REGNO_P
52038 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52040 #undef TARGET_PROMOTE_FUNCTION_MODE
52041 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52043 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52044 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52046 #undef TARGET_INSTANTIATE_DECLS
52047 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52049 #undef TARGET_SECONDARY_RELOAD
52050 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52052 #undef TARGET_CLASS_MAX_NREGS
52053 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52055 #undef TARGET_PREFERRED_RELOAD_CLASS
52056 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52057 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52058 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52059 #undef TARGET_CLASS_LIKELY_SPILLED_P
52060 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52062 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52063 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52064 ix86_builtin_vectorization_cost
52065 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52066 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52067 ix86_vectorize_vec_perm_const_ok
52068 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52069 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52070 ix86_preferred_simd_mode
52071 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52072 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52073 ix86_autovectorize_vector_sizes
52074 #undef TARGET_VECTORIZE_INIT_COST
52075 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52076 #undef TARGET_VECTORIZE_ADD_STMT_COST
52077 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52078 #undef TARGET_VECTORIZE_FINISH_COST
52079 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52080 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52081 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52083 #undef TARGET_SET_CURRENT_FUNCTION
52084 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52086 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52087 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52089 #undef TARGET_OPTION_SAVE
52090 #define TARGET_OPTION_SAVE ix86_function_specific_save
52092 #undef TARGET_OPTION_RESTORE
52093 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52095 #undef TARGET_OPTION_POST_STREAM_IN
52096 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52098 #undef TARGET_OPTION_PRINT
52099 #define TARGET_OPTION_PRINT ix86_function_specific_print
52101 #undef TARGET_OPTION_FUNCTION_VERSIONS
52102 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52104 #undef TARGET_CAN_INLINE_P
52105 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52107 #undef TARGET_EXPAND_TO_RTL_HOOK
52108 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52110 #undef TARGET_LEGITIMATE_ADDRESS_P
52111 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52113 #undef TARGET_LRA_P
52114 #define TARGET_LRA_P hook_bool_void_true
52116 #undef TARGET_REGISTER_PRIORITY
52117 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52119 #undef TARGET_REGISTER_USAGE_LEVELING_P
52120 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52122 #undef TARGET_LEGITIMATE_CONSTANT_P
52123 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52125 #undef TARGET_FRAME_POINTER_REQUIRED
52126 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52128 #undef TARGET_CAN_ELIMINATE
52129 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52131 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52132 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52134 #undef TARGET_ASM_CODE_END
52135 #define TARGET_ASM_CODE_END ix86_code_end
52137 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52138 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52140 #if TARGET_MACHO
52141 #undef TARGET_INIT_LIBFUNCS
52142 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52143 #endif
52145 #undef TARGET_LOOP_UNROLL_ADJUST
52146 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52148 #undef TARGET_SPILL_CLASS
52149 #define TARGET_SPILL_CLASS ix86_spill_class
52151 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52152 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52153 ix86_simd_clone_compute_vecsize_and_simdlen
52155 #undef TARGET_SIMD_CLONE_ADJUST
52156 #define TARGET_SIMD_CLONE_ADJUST \
52157 ix86_simd_clone_adjust
52159 #undef TARGET_SIMD_CLONE_USABLE
52160 #define TARGET_SIMD_CLONE_USABLE \
52161 ix86_simd_clone_usable
52163 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52164 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52165 ix86_float_exceptions_rounding_supported_p
52167 #undef TARGET_MODE_EMIT
52168 #define TARGET_MODE_EMIT ix86_emit_mode_set
52170 #undef TARGET_MODE_NEEDED
52171 #define TARGET_MODE_NEEDED ix86_mode_needed
52173 #undef TARGET_MODE_AFTER
52174 #define TARGET_MODE_AFTER ix86_mode_after
52176 #undef TARGET_MODE_ENTRY
52177 #define TARGET_MODE_ENTRY ix86_mode_entry
52179 #undef TARGET_MODE_EXIT
52180 #define TARGET_MODE_EXIT ix86_mode_exit
52182 #undef TARGET_MODE_PRIORITY
52183 #define TARGET_MODE_PRIORITY ix86_mode_priority
52185 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52186 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52188 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52189 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52191 #undef TARGET_STORE_BOUNDS_FOR_ARG
52192 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52194 #undef TARGET_LOAD_RETURNED_BOUNDS
52195 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52197 #undef TARGET_STORE_RETURNED_BOUNDS
52198 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52200 #undef TARGET_CHKP_BOUND_MODE
52201 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52203 #undef TARGET_BUILTIN_CHKP_FUNCTION
52204 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52206 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52207 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52209 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52210 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52212 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52213 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52215 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52216 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52218 #undef TARGET_OFFLOAD_OPTIONS
52219 #define TARGET_OFFLOAD_OPTIONS \
52220 ix86_offload_options
52222 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52223 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52226 \f