| blob | 4d3aadcf9058c91fdc43406d604f022e4c365068 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; UNSPEC usage
27 ;;
29 (define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
54 ])
56 ;;
57 ;; UNSPEC_VOLATILE usage
58 ;;
60 (define_constants
61 [(UNSPECV_BLOCK 0)
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
63 ])
64 \f
65 ;; Define an insn type attribute. This is used in function unit delay
66 ;; computations.
67 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
70 ;; Length (in bytes).
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
76 (const_int -32768))
77 (lt (minus (match_dup 0) (pc))
78 (const_int 32764)))
79 (const_int 4)
80 (const_int 8))
81 (const_int 4)))
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
89 (automata_option "ndfa")
91 (include "rios1.md")
92 (include "rios2.md")
93 (include "rs64.md")
94 (include "mpc.md")
95 (include "40x.md")
96 (include "440.md")
97 (include "603.md")
98 (include "6xx.md")
99 (include "7xx.md")
100 (include "7450.md")
101 (include "8540.md")
102 (include "power4.md")
103 (include "power5.md")
104 (include "darwin.md")
106 \f
107 ;; This mode macro allows :P to be used for patterns that operate on
108 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
109 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
111 ;; Start with fixed-point load and store insns. Here we put only the more
112 ;; complex forms. Basic data transfer is done later.
114 (define_expand "zero_extendqidi2"
115 [(set (match_operand:DI 0 "gpc_reg_operand" "")
116 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
117 "TARGET_POWERPC64"
118 "")
120 (define_insn ""
121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
122 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
123 "TARGET_POWERPC64"
124 "@
125 lbz%U1%X1 %0,%1
126 rldicl %0,%1,0,56"
127 [(set_attr "type" "load,*")])
129 (define_insn ""
130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
131 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
132 (const_int 0)))
133 (clobber (match_scratch:DI 2 "=r,r"))]
134 "TARGET_64BIT"
135 "@
136 rldicl. %2,%1,0,56
137 #"
138 [(set_attr "type" "compare")
139 (set_attr "length" "4,8")])
141 (define_split
142 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
143 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
144 (const_int 0)))
145 (clobber (match_scratch:DI 2 ""))]
146 "TARGET_POWERPC64 && reload_completed"
147 [(set (match_dup 2)
148 (zero_extend:DI (match_dup 1)))
149 (set (match_dup 0)
150 (compare:CC (match_dup 2)
151 (const_int 0)))]
152 "")
154 (define_insn ""
155 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
156 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
157 (const_int 0)))
158 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
159 (zero_extend:DI (match_dup 1)))]
160 "TARGET_64BIT"
161 "@
162 rldicl. %0,%1,0,56
163 #"
164 [(set_attr "type" "compare")
165 (set_attr "length" "4,8")])
167 (define_split
168 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
169 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
170 (const_int 0)))
171 (set (match_operand:DI 0 "gpc_reg_operand" "")
172 (zero_extend:DI (match_dup 1)))]
173 "TARGET_POWERPC64 && reload_completed"
174 [(set (match_dup 0)
175 (zero_extend:DI (match_dup 1)))
176 (set (match_dup 2)
177 (compare:CC (match_dup 0)
178 (const_int 0)))]
179 "")
181 (define_insn "extendqidi2"
182 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
183 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
184 "TARGET_POWERPC64"
185 "extsb %0,%1")
187 (define_insn ""
188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
190 (const_int 0)))
191 (clobber (match_scratch:DI 2 "=r,r"))]
192 "TARGET_64BIT"
193 "@
194 extsb. %2,%1
195 #"
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
199 (define_split
200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
202 (const_int 0)))
203 (clobber (match_scratch:DI 2 ""))]
204 "TARGET_POWERPC64 && reload_completed"
205 [(set (match_dup 2)
206 (sign_extend:DI (match_dup 1)))
207 (set (match_dup 0)
208 (compare:CC (match_dup 2)
209 (const_int 0)))]
210 "")
212 (define_insn ""
213 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
215 (const_int 0)))
216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 (sign_extend:DI (match_dup 1)))]
218 "TARGET_64BIT"
219 "@
220 extsb. %0,%1
221 #"
222 [(set_attr "type" "compare")
223 (set_attr "length" "4,8")])
225 (define_split
226 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
228 (const_int 0)))
229 (set (match_operand:DI 0 "gpc_reg_operand" "")
230 (sign_extend:DI (match_dup 1)))]
231 "TARGET_POWERPC64 && reload_completed"
232 [(set (match_dup 0)
233 (sign_extend:DI (match_dup 1)))
234 (set (match_dup 2)
235 (compare:CC (match_dup 0)
236 (const_int 0)))]
237 "")
239 (define_expand "zero_extendhidi2"
240 [(set (match_operand:DI 0 "gpc_reg_operand" "")
241 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
242 "TARGET_POWERPC64"
243 "")
245 (define_insn ""
246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
247 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
248 "TARGET_POWERPC64"
249 "@
250 lhz%U1%X1 %0,%1
251 rldicl %0,%1,0,48"
252 [(set_attr "type" "load,*")])
254 (define_insn ""
255 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
256 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
257 (const_int 0)))
258 (clobber (match_scratch:DI 2 "=r,r"))]
259 "TARGET_64BIT"
260 "@
261 rldicl. %2,%1,0,48
262 #"
263 [(set_attr "type" "compare")
264 (set_attr "length" "4,8")])
266 (define_split
267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
268 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
269 (const_int 0)))
270 (clobber (match_scratch:DI 2 ""))]
271 "TARGET_POWERPC64 && reload_completed"
272 [(set (match_dup 2)
273 (zero_extend:DI (match_dup 1)))
274 (set (match_dup 0)
275 (compare:CC (match_dup 2)
276 (const_int 0)))]
277 "")
279 (define_insn ""
280 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
281 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
282 (const_int 0)))
283 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
284 (zero_extend:DI (match_dup 1)))]
285 "TARGET_64BIT"
286 "@
287 rldicl. %0,%1,0,48
288 #"
289 [(set_attr "type" "compare")
290 (set_attr "length" "4,8")])
292 (define_split
293 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
294 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
295 (const_int 0)))
296 (set (match_operand:DI 0 "gpc_reg_operand" "")
297 (zero_extend:DI (match_dup 1)))]
298 "TARGET_POWERPC64 && reload_completed"
299 [(set (match_dup 0)
300 (zero_extend:DI (match_dup 1)))
301 (set (match_dup 2)
302 (compare:CC (match_dup 0)
303 (const_int 0)))]
304 "")
306 (define_expand "extendhidi2"
307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
308 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
309 "TARGET_POWERPC64"
310 "")
312 (define_insn ""
313 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
314 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
315 "TARGET_POWERPC64"
316 "@
317 lha%U1%X1 %0,%1
318 extsh %0,%1"
319 [(set_attr "type" "load_ext,*")])
321 (define_insn ""
322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
323 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
324 (const_int 0)))
325 (clobber (match_scratch:DI 2 "=r,r"))]
326 "TARGET_64BIT"
327 "@
328 extsh. %2,%1
329 #"
330 [(set_attr "type" "compare")
331 (set_attr "length" "4,8")])
333 (define_split
334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
335 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
336 (const_int 0)))
337 (clobber (match_scratch:DI 2 ""))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 2)
340 (sign_extend:DI (match_dup 1)))
341 (set (match_dup 0)
342 (compare:CC (match_dup 2)
343 (const_int 0)))]
344 "")
346 (define_insn ""
347 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
348 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
349 (const_int 0)))
350 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
351 (sign_extend:DI (match_dup 1)))]
352 "TARGET_64BIT"
353 "@
354 extsh. %0,%1
355 #"
356 [(set_attr "type" "compare")
357 (set_attr "length" "4,8")])
359 (define_split
360 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
361 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
362 (const_int 0)))
363 (set (match_operand:DI 0 "gpc_reg_operand" "")
364 (sign_extend:DI (match_dup 1)))]
365 "TARGET_POWERPC64 && reload_completed"
366 [(set (match_dup 0)
367 (sign_extend:DI (match_dup 1)))
368 (set (match_dup 2)
369 (compare:CC (match_dup 0)
370 (const_int 0)))]
371 "")
373 (define_expand "zero_extendsidi2"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
375 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
376 "TARGET_POWERPC64"
377 "")
379 (define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
381 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
382 "TARGET_POWERPC64"
383 "@
384 lwz%U1%X1 %0,%1
385 rldicl %0,%1,0,32"
386 [(set_attr "type" "load,*")])
388 (define_insn ""
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
390 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
391 (const_int 0)))
392 (clobber (match_scratch:DI 2 "=r,r"))]
393 "TARGET_64BIT"
394 "@
395 rldicl. %2,%1,0,32
396 #"
397 [(set_attr "type" "compare")
398 (set_attr "length" "4,8")])
400 (define_split
401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
402 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
403 (const_int 0)))
404 (clobber (match_scratch:DI 2 ""))]
405 "TARGET_POWERPC64 && reload_completed"
406 [(set (match_dup 2)
407 (zero_extend:DI (match_dup 1)))
408 (set (match_dup 0)
409 (compare:CC (match_dup 2)
410 (const_int 0)))]
411 "")
413 (define_insn ""
414 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
415 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
416 (const_int 0)))
417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
418 (zero_extend:DI (match_dup 1)))]
419 "TARGET_64BIT"
420 "@
421 rldicl. %0,%1,0,32
422 #"
423 [(set_attr "type" "compare")
424 (set_attr "length" "4,8")])
426 (define_split
427 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
428 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
429 (const_int 0)))
430 (set (match_operand:DI 0 "gpc_reg_operand" "")
431 (zero_extend:DI (match_dup 1)))]
432 "TARGET_POWERPC64 && reload_completed"
433 [(set (match_dup 0)
434 (zero_extend:DI (match_dup 1)))
435 (set (match_dup 2)
436 (compare:CC (match_dup 0)
437 (const_int 0)))]
438 "")
440 (define_expand "extendsidi2"
441 [(set (match_operand:DI 0 "gpc_reg_operand" "")
442 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
443 "TARGET_POWERPC64"
444 "")
446 (define_insn ""
447 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
448 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
449 "TARGET_POWERPC64"
450 "@
451 lwa%U1%X1 %0,%1
452 extsw %0,%1"
453 [(set_attr "type" "load_ext,*")])
455 (define_insn ""
456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
457 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
458 (const_int 0)))
459 (clobber (match_scratch:DI 2 "=r,r"))]
460 "TARGET_64BIT"
461 "@
462 extsw. %2,%1
463 #"
464 [(set_attr "type" "compare")
465 (set_attr "length" "4,8")])
467 (define_split
468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
469 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
470 (const_int 0)))
471 (clobber (match_scratch:DI 2 ""))]
472 "TARGET_POWERPC64 && reload_completed"
473 [(set (match_dup 2)
474 (sign_extend:DI (match_dup 1)))
475 (set (match_dup 0)
476 (compare:CC (match_dup 2)
477 (const_int 0)))]
478 "")
480 (define_insn ""
481 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
482 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
483 (const_int 0)))
484 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
485 (sign_extend:DI (match_dup 1)))]
486 "TARGET_64BIT"
487 "@
488 extsw. %0,%1
489 #"
490 [(set_attr "type" "compare")
491 (set_attr "length" "4,8")])
493 (define_split
494 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
495 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
496 (const_int 0)))
497 (set (match_operand:DI 0 "gpc_reg_operand" "")
498 (sign_extend:DI (match_dup 1)))]
499 "TARGET_POWERPC64 && reload_completed"
500 [(set (match_dup 0)
501 (sign_extend:DI (match_dup 1)))
502 (set (match_dup 2)
503 (compare:CC (match_dup 0)
504 (const_int 0)))]
505 "")
507 (define_expand "zero_extendqisi2"
508 [(set (match_operand:SI 0 "gpc_reg_operand" "")
509 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
510 ""
511 "")
513 (define_insn ""
514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
515 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
516 ""
517 "@
518 lbz%U1%X1 %0,%1
519 {rlinm|rlwinm} %0,%1,0,0xff"
520 [(set_attr "type" "load,*")])
522 (define_insn ""
523 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
524 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
525 (const_int 0)))
526 (clobber (match_scratch:SI 2 "=r,r"))]
527 ""
528 "@
529 {andil.|andi.} %2,%1,0xff
530 #"
531 [(set_attr "type" "compare")
532 (set_attr "length" "4,8")])
534 (define_split
535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
536 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
537 (const_int 0)))
538 (clobber (match_scratch:SI 2 ""))]
539 "reload_completed"
540 [(set (match_dup 2)
541 (zero_extend:SI (match_dup 1)))
542 (set (match_dup 0)
543 (compare:CC (match_dup 2)
544 (const_int 0)))]
545 "")
547 (define_insn ""
548 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
549 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
550 (const_int 0)))
551 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
552 (zero_extend:SI (match_dup 1)))]
553 ""
554 "@
555 {andil.|andi.} %0,%1,0xff
556 #"
557 [(set_attr "type" "compare")
558 (set_attr "length" "4,8")])
560 (define_split
561 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
562 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
563 (const_int 0)))
564 (set (match_operand:SI 0 "gpc_reg_operand" "")
565 (zero_extend:SI (match_dup 1)))]
566 "reload_completed"
567 [(set (match_dup 0)
568 (zero_extend:SI (match_dup 1)))
569 (set (match_dup 2)
570 (compare:CC (match_dup 0)
571 (const_int 0)))]
572 "")
574 (define_expand "extendqisi2"
575 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
576 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
577 ""
578 "
579 {
580 if (TARGET_POWERPC)
581 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
582 else if (TARGET_POWER)
583 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
584 else
585 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
586 DONE;
587 }")
589 (define_insn "extendqisi2_ppc"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
591 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
592 "TARGET_POWERPC"
593 "extsb %0,%1")
595 (define_insn ""
596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
597 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
598 (const_int 0)))
599 (clobber (match_scratch:SI 2 "=r,r"))]
600 "TARGET_POWERPC"
601 "@
602 extsb. %2,%1
603 #"
604 [(set_attr "type" "compare")
605 (set_attr "length" "4,8")])
607 (define_split
608 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
609 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
610 (const_int 0)))
611 (clobber (match_scratch:SI 2 ""))]
612 "TARGET_POWERPC && reload_completed"
613 [(set (match_dup 2)
614 (sign_extend:SI (match_dup 1)))
615 (set (match_dup 0)
616 (compare:CC (match_dup 2)
617 (const_int 0)))]
618 "")
620 (define_insn ""
621 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
623 (const_int 0)))
624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
625 (sign_extend:SI (match_dup 1)))]
626 "TARGET_POWERPC"
627 "@
628 extsb. %0,%1
629 #"
630 [(set_attr "type" "compare")
631 (set_attr "length" "4,8")])
633 (define_split
634 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
635 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
636 (const_int 0)))
637 (set (match_operand:SI 0 "gpc_reg_operand" "")
638 (sign_extend:SI (match_dup 1)))]
639 "TARGET_POWERPC && reload_completed"
640 [(set (match_dup 0)
641 (sign_extend:SI (match_dup 1)))
642 (set (match_dup 2)
643 (compare:CC (match_dup 0)
644 (const_int 0)))]
645 "")
647 (define_expand "extendqisi2_power"
648 [(parallel [(set (match_dup 2)
649 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
650 (const_int 24)))
651 (clobber (scratch:SI))])
652 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
653 (ashiftrt:SI (match_dup 2)
654 (const_int 24)))
655 (clobber (scratch:SI))])]
656 "TARGET_POWER"
657 "
658 { operands[1] = gen_lowpart (SImode, operands[1]);
659 operands[2] = gen_reg_rtx (SImode); }")
661 (define_expand "extendqisi2_no_power"
662 [(set (match_dup 2)
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
664 (const_int 24)))
665 (set (match_operand:SI 0 "gpc_reg_operand" "")
666 (ashiftrt:SI (match_dup 2)
667 (const_int 24)))]
668 "! TARGET_POWER && ! TARGET_POWERPC"
669 "
670 { operands[1] = gen_lowpart (SImode, operands[1]);
671 operands[2] = gen_reg_rtx (SImode); }")
673 (define_expand "zero_extendqihi2"
674 [(set (match_operand:HI 0 "gpc_reg_operand" "")
675 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
676 ""
677 "")
679 (define_insn ""
680 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
681 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
682 ""
683 "@
684 lbz%U1%X1 %0,%1
685 {rlinm|rlwinm} %0,%1,0,0xff"
686 [(set_attr "type" "load,*")])
688 (define_insn ""
689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
690 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (clobber (match_scratch:HI 2 "=r,r"))]
693 ""
694 "@
695 {andil.|andi.} %2,%1,0xff
696 #"
697 [(set_attr "type" "compare")
698 (set_attr "length" "4,8")])
700 (define_split
701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
702 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
703 (const_int 0)))
704 (clobber (match_scratch:HI 2 ""))]
705 "reload_completed"
706 [(set (match_dup 2)
707 (zero_extend:HI (match_dup 1)))
708 (set (match_dup 0)
709 (compare:CC (match_dup 2)
710 (const_int 0)))]
711 "")
713 (define_insn ""
714 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
715 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
716 (const_int 0)))
717 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
718 (zero_extend:HI (match_dup 1)))]
719 ""
720 "@
721 {andil.|andi.} %0,%1,0xff
722 #"
723 [(set_attr "type" "compare")
724 (set_attr "length" "4,8")])
726 (define_split
727 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
728 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
729 (const_int 0)))
730 (set (match_operand:HI 0 "gpc_reg_operand" "")
731 (zero_extend:HI (match_dup 1)))]
732 "reload_completed"
733 [(set (match_dup 0)
734 (zero_extend:HI (match_dup 1)))
735 (set (match_dup 2)
736 (compare:CC (match_dup 0)
737 (const_int 0)))]
738 "")
740 (define_expand "extendqihi2"
741 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
742 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
743 ""
744 "
745 {
746 if (TARGET_POWERPC)
747 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
748 else if (TARGET_POWER)
749 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
750 else
751 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
752 DONE;
753 }")
755 (define_insn "extendqihi2_ppc"
756 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
757 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
758 "TARGET_POWERPC"
759 "extsb %0,%1")
761 (define_insn ""
762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
763 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
764 (const_int 0)))
765 (clobber (match_scratch:HI 2 "=r,r"))]
766 "TARGET_POWERPC"
767 "@
768 extsb. %2,%1
769 #"
770 [(set_attr "type" "compare")
771 (set_attr "length" "4,8")])
773 (define_split
774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
775 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
776 (const_int 0)))
777 (clobber (match_scratch:HI 2 ""))]
778 "TARGET_POWERPC && reload_completed"
779 [(set (match_dup 2)
780 (sign_extend:HI (match_dup 1)))
781 (set (match_dup 0)
782 (compare:CC (match_dup 2)
783 (const_int 0)))]
784 "")
786 (define_insn ""
787 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
788 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
789 (const_int 0)))
790 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
791 (sign_extend:HI (match_dup 1)))]
792 "TARGET_POWERPC"
793 "@
794 extsb. %0,%1
795 #"
796 [(set_attr "type" "compare")
797 (set_attr "length" "4,8")])
799 (define_split
800 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
801 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
802 (const_int 0)))
803 (set (match_operand:HI 0 "gpc_reg_operand" "")
804 (sign_extend:HI (match_dup 1)))]
805 "TARGET_POWERPC && reload_completed"
806 [(set (match_dup 0)
807 (sign_extend:HI (match_dup 1)))
808 (set (match_dup 2)
809 (compare:CC (match_dup 0)
810 (const_int 0)))]
811 "")
813 (define_expand "extendqihi2_power"
814 [(parallel [(set (match_dup 2)
815 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
816 (const_int 24)))
817 (clobber (scratch:SI))])
818 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
819 (ashiftrt:SI (match_dup 2)
820 (const_int 24)))
821 (clobber (scratch:SI))])]
822 "TARGET_POWER"
823 "
824 { operands[0] = gen_lowpart (SImode, operands[0]);
825 operands[1] = gen_lowpart (SImode, operands[1]);
826 operands[2] = gen_reg_rtx (SImode); }")
828 (define_expand "extendqihi2_no_power"
829 [(set (match_dup 2)
830 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
831 (const_int 24)))
832 (set (match_operand:HI 0 "gpc_reg_operand" "")
833 (ashiftrt:SI (match_dup 2)
834 (const_int 24)))]
835 "! TARGET_POWER && ! TARGET_POWERPC"
836 "
837 { operands[0] = gen_lowpart (SImode, operands[0]);
838 operands[1] = gen_lowpart (SImode, operands[1]);
839 operands[2] = gen_reg_rtx (SImode); }")
841 (define_expand "zero_extendhisi2"
842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
843 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
844 ""
845 "")
847 (define_insn ""
848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
849 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
850 ""
851 "@
852 lhz%U1%X1 %0,%1
853 {rlinm|rlwinm} %0,%1,0,0xffff"
854 [(set_attr "type" "load,*")])
856 (define_insn ""
857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
858 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
859 (const_int 0)))
860 (clobber (match_scratch:SI 2 "=r,r"))]
861 ""
862 "@
863 {andil.|andi.} %2,%1,0xffff
864 #"
865 [(set_attr "type" "compare")
866 (set_attr "length" "4,8")])
868 (define_split
869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
870 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
871 (const_int 0)))
872 (clobber (match_scratch:SI 2 ""))]
873 "reload_completed"
874 [(set (match_dup 2)
875 (zero_extend:SI (match_dup 1)))
876 (set (match_dup 0)
877 (compare:CC (match_dup 2)
878 (const_int 0)))]
879 "")
881 (define_insn ""
882 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
883 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
884 (const_int 0)))
885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
886 (zero_extend:SI (match_dup 1)))]
887 ""
888 "@
889 {andil.|andi.} %0,%1,0xffff
890 #"
891 [(set_attr "type" "compare")
892 (set_attr "length" "4,8")])
894 (define_split
895 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
896 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
897 (const_int 0)))
898 (set (match_operand:SI 0 "gpc_reg_operand" "")
899 (zero_extend:SI (match_dup 1)))]
900 "reload_completed"
901 [(set (match_dup 0)
902 (zero_extend:SI (match_dup 1)))
903 (set (match_dup 2)
904 (compare:CC (match_dup 0)
905 (const_int 0)))]
906 "")
908 (define_expand "extendhisi2"
909 [(set (match_operand:SI 0 "gpc_reg_operand" "")
910 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
911 ""
912 "")
914 (define_insn ""
915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
916 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
917 ""
918 "@
919 lha%U1%X1 %0,%1
920 {exts|extsh} %0,%1"
921 [(set_attr "type" "load_ext,*")])
923 (define_insn ""
924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
925 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
926 (const_int 0)))
927 (clobber (match_scratch:SI 2 "=r,r"))]
928 ""
929 "@
930 {exts.|extsh.} %2,%1
931 #"
932 [(set_attr "type" "compare")
933 (set_attr "length" "4,8")])
935 (define_split
936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
937 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
938 (const_int 0)))
939 (clobber (match_scratch:SI 2 ""))]
940 "reload_completed"
941 [(set (match_dup 2)
942 (sign_extend:SI (match_dup 1)))
943 (set (match_dup 0)
944 (compare:CC (match_dup 2)
945 (const_int 0)))]
946 "")
948 (define_insn ""
949 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
950 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
951 (const_int 0)))
952 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
953 (sign_extend:SI (match_dup 1)))]
954 ""
955 "@
956 {exts.|extsh.} %0,%1
957 #"
958 [(set_attr "type" "compare")
959 (set_attr "length" "4,8")])
960 \f
961 (define_split
962 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
963 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
964 (const_int 0)))
965 (set (match_operand:SI 0 "gpc_reg_operand" "")
966 (sign_extend:SI (match_dup 1)))]
967 "reload_completed"
968 [(set (match_dup 0)
969 (sign_extend:SI (match_dup 1)))
970 (set (match_dup 2)
971 (compare:CC (match_dup 0)
972 (const_int 0)))]
973 "")
975 ;; Fixed-point arithmetic insns.
977 ;; Discourage ai/addic because of carry but provide it in an alternative
978 ;; allowing register zero as source.
979 (define_expand "addsi3"
980 [(set (match_operand:SI 0 "gpc_reg_operand" "")
981 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
982 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
983 ""
984 "
985 {
986 if (GET_CODE (operands[2]) == CONST_INT
987 && ! add_operand (operands[2], SImode))
988 {
989 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
990 ? operands[0] : gen_reg_rtx (SImode));
992 HOST_WIDE_INT val = INTVAL (operands[2]);
993 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
994 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
996 /* The ordering here is important for the prolog expander.
997 When space is allocated from the stack, adding 'low' first may
998 produce a temporary deallocation (which would be bad). */
999 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1000 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1001 DONE;
1002 }
1003 }")
1005 (define_insn "*addsi3_internal1"
1006 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1007 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1008 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1009 ""
1010 "@
1011 {cax|add} %0,%1,%2
1012 {cal %0,%2(%1)|addi %0,%1,%2}
1013 {ai|addic} %0,%1,%2
1014 {cau|addis} %0,%1,%v2"
1015 [(set_attr "length" "4,4,4,4")])
1017 (define_insn "addsi3_high"
1018 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1019 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1020 (high:SI (match_operand 2 "" ""))))]
1021 "TARGET_MACHO && !TARGET_64BIT"
1022 "{cau|addis} %0,%1,ha16(%2)"
1023 [(set_attr "length" "4")])
1025 (define_insn "*addsi3_internal2"
1026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1027 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1028 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1029 (const_int 0)))
1030 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1031 "TARGET_32BIT"
1032 "@
1033 {cax.|add.} %3,%1,%2
1034 {ai.|addic.} %3,%1,%2
1035 #
1036 #"
1037 [(set_attr "type" "fast_compare,compare,compare,compare")
1038 (set_attr "length" "4,4,8,8")])
1040 (define_split
1041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1043 (match_operand:SI 2 "reg_or_short_operand" ""))
1044 (const_int 0)))
1045 (clobber (match_scratch:SI 3 ""))]
1046 "TARGET_32BIT && reload_completed"
1047 [(set (match_dup 3)
1048 (plus:SI (match_dup 1)
1049 (match_dup 2)))
1050 (set (match_dup 0)
1051 (compare:CC (match_dup 3)
1052 (const_int 0)))]
1053 "")
1055 (define_insn "*addsi3_internal3"
1056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1057 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1058 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1059 (const_int 0)))
1060 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1061 (plus:SI (match_dup 1)
1062 (match_dup 2)))]
1063 "TARGET_32BIT"
1064 "@
1065 {cax.|add.} %0,%1,%2
1066 {ai.|addic.} %0,%1,%2
1067 #
1068 #"
1069 [(set_attr "type" "fast_compare,compare,compare,compare")
1070 (set_attr "length" "4,4,8,8")])
1072 (define_split
1073 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1074 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1075 (match_operand:SI 2 "reg_or_short_operand" ""))
1076 (const_int 0)))
1077 (set (match_operand:SI 0 "gpc_reg_operand" "")
1078 (plus:SI (match_dup 1) (match_dup 2)))]
1079 "TARGET_32BIT && reload_completed"
1080 [(set (match_dup 0)
1081 (plus:SI (match_dup 1)
1082 (match_dup 2)))
1083 (set (match_dup 3)
1084 (compare:CC (match_dup 0)
1085 (const_int 0)))]
1086 "")
1088 ;; Split an add that we can't do in one insn into two insns, each of which
1089 ;; does one 16-bit part. This is used by combine. Note that the low-order
1090 ;; add should be last in case the result gets used in an address.
1092 (define_split
1093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1094 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1095 (match_operand:SI 2 "non_add_cint_operand" "")))]
1096 ""
1097 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1098 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1099 "
1100 {
1101 HOST_WIDE_INT val = INTVAL (operands[2]);
1102 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1103 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1105 operands[3] = GEN_INT (rest);
1106 operands[4] = GEN_INT (low);
1107 }")
1109 (define_insn "one_cmplsi2"
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1111 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1112 ""
1113 "nor %0,%1,%1")
1115 (define_insn ""
1116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1117 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1118 (const_int 0)))
1119 (clobber (match_scratch:SI 2 "=r,r"))]
1120 "TARGET_32BIT"
1121 "@
1122 nor. %2,%1,%1
1123 #"
1124 [(set_attr "type" "compare")
1125 (set_attr "length" "4,8")])
1127 (define_split
1128 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1129 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1130 (const_int 0)))
1131 (clobber (match_scratch:SI 2 ""))]
1132 "TARGET_32BIT && reload_completed"
1133 [(set (match_dup 2)
1134 (not:SI (match_dup 1)))
1135 (set (match_dup 0)
1136 (compare:CC (match_dup 2)
1137 (const_int 0)))]
1138 "")
1140 (define_insn ""
1141 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1142 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1143 (const_int 0)))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1145 (not:SI (match_dup 1)))]
1146 "TARGET_32BIT"
1147 "@
1148 nor. %0,%1,%1
1149 #"
1150 [(set_attr "type" "compare")
1151 (set_attr "length" "4,8")])
1153 (define_split
1154 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1155 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1156 (const_int 0)))
1157 (set (match_operand:SI 0 "gpc_reg_operand" "")
1158 (not:SI (match_dup 1)))]
1159 "TARGET_32BIT && reload_completed"
1160 [(set (match_dup 0)
1161 (not:SI (match_dup 1)))
1162 (set (match_dup 2)
1163 (compare:CC (match_dup 0)
1164 (const_int 0)))]
1165 "")
1167 (define_insn ""
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1170 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1171 "! TARGET_POWERPC"
1172 "{sf%I1|subf%I1c} %0,%2,%1")
1174 (define_insn ""
1175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1176 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1177 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1178 "TARGET_POWERPC"
1179 "@
1180 subf %0,%2,%1
1181 subfic %0,%2,%1")
1183 (define_insn ""
1184 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1185 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1186 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1187 (const_int 0)))
1188 (clobber (match_scratch:SI 3 "=r,r"))]
1189 "! TARGET_POWERPC"
1190 "@
1191 {sf.|subfc.} %3,%2,%1
1192 #"
1193 [(set_attr "type" "compare")
1194 (set_attr "length" "4,8")])
1196 (define_insn ""
1197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1198 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1199 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1200 (const_int 0)))
1201 (clobber (match_scratch:SI 3 "=r,r"))]
1202 "TARGET_POWERPC && TARGET_32BIT"
1203 "@
1204 subf. %3,%2,%1
1205 #"
1206 [(set_attr "type" "fast_compare")
1207 (set_attr "length" "4,8")])
1209 (define_split
1210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1211 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1212 (match_operand:SI 2 "gpc_reg_operand" ""))
1213 (const_int 0)))
1214 (clobber (match_scratch:SI 3 ""))]
1215 "TARGET_32BIT && reload_completed"
1216 [(set (match_dup 3)
1217 (minus:SI (match_dup 1)
1218 (match_dup 2)))
1219 (set (match_dup 0)
1220 (compare:CC (match_dup 3)
1221 (const_int 0)))]
1222 "")
1224 (define_insn ""
1225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1226 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1227 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1228 (const_int 0)))
1229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1230 (minus:SI (match_dup 1) (match_dup 2)))]
1231 "! TARGET_POWERPC"
1232 "@
1233 {sf.|subfc.} %0,%2,%1
1234 #"
1235 [(set_attr "type" "compare")
1236 (set_attr "length" "4,8")])
1238 (define_insn ""
1239 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1240 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1241 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1242 (const_int 0)))
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1244 (minus:SI (match_dup 1)
1245 (match_dup 2)))]
1246 "TARGET_POWERPC && TARGET_32BIT"
1247 "@
1248 subf. %0,%2,%1
1249 #"
1250 [(set_attr "type" "fast_compare")
1251 (set_attr "length" "4,8")])
1253 (define_split
1254 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1255 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1256 (match_operand:SI 2 "gpc_reg_operand" ""))
1257 (const_int 0)))
1258 (set (match_operand:SI 0 "gpc_reg_operand" "")
1259 (minus:SI (match_dup 1)
1260 (match_dup 2)))]
1261 "TARGET_32BIT && reload_completed"
1262 [(set (match_dup 0)
1263 (minus:SI (match_dup 1)
1264 (match_dup 2)))
1265 (set (match_dup 3)
1266 (compare:CC (match_dup 0)
1267 (const_int 0)))]
1268 "")
1270 (define_expand "subsi3"
1271 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1272 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1273 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1274 ""
1275 "
1276 {
1277 if (GET_CODE (operands[2]) == CONST_INT)
1278 {
1279 emit_insn (gen_addsi3 (operands[0], operands[1],
1280 negate_rtx (SImode, operands[2])));
1281 DONE;
1282 }
1283 }")
1285 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1286 ;; instruction and some auxiliary computations. Then we just have a single
1287 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1288 ;; combine.
1290 (define_expand "sminsi3"
1291 [(set (match_dup 3)
1292 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1293 (match_operand:SI 2 "reg_or_short_operand" ""))
1294 (const_int 0)
1295 (minus:SI (match_dup 2) (match_dup 1))))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "")
1297 (minus:SI (match_dup 2) (match_dup 3)))]
1298 "TARGET_POWER || TARGET_ISEL"
1299 "
1300 {
1301 if (TARGET_ISEL)
1302 {
1303 operands[2] = force_reg (SImode, operands[2]);
1304 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1305 DONE;
1306 }
1308 operands[3] = gen_reg_rtx (SImode);
1309 }")
1311 (define_split
1312 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1314 (match_operand:SI 2 "reg_or_short_operand" "")))
1315 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1316 "TARGET_POWER"
1317 [(set (match_dup 3)
1318 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1319 (const_int 0)
1320 (minus:SI (match_dup 2) (match_dup 1))))
1321 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1322 "")
1324 (define_expand "smaxsi3"
1325 [(set (match_dup 3)
1326 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1327 (match_operand:SI 2 "reg_or_short_operand" ""))
1328 (const_int 0)
1329 (minus:SI (match_dup 2) (match_dup 1))))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "")
1331 (plus:SI (match_dup 3) (match_dup 1)))]
1332 "TARGET_POWER || TARGET_ISEL"
1333 "
1334 {
1335 if (TARGET_ISEL)
1336 {
1337 operands[2] = force_reg (SImode, operands[2]);
1338 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1339 DONE;
1340 }
1341 operands[3] = gen_reg_rtx (SImode);
1342 }")
1344 (define_split
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1346 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1347 (match_operand:SI 2 "reg_or_short_operand" "")))
1348 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1349 "TARGET_POWER"
1350 [(set (match_dup 3)
1351 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1352 (const_int 0)
1353 (minus:SI (match_dup 2) (match_dup 1))))
1354 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1355 "")
1357 (define_expand "uminsi3"
1358 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1359 (match_dup 5)))
1360 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1361 (match_dup 5)))
1362 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1363 (const_int 0)
1364 (minus:SI (match_dup 4) (match_dup 3))))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "")
1366 (minus:SI (match_dup 2) (match_dup 3)))]
1367 "TARGET_POWER || TARGET_ISEL"
1368 "
1369 {
1370 if (TARGET_ISEL)
1371 {
1372 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1373 DONE;
1374 }
1375 operands[3] = gen_reg_rtx (SImode);
1376 operands[4] = gen_reg_rtx (SImode);
1377 operands[5] = GEN_INT (-2147483647 - 1);
1378 }")
1380 (define_expand "umaxsi3"
1381 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1382 (match_dup 5)))
1383 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1384 (match_dup 5)))
1385 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1386 (const_int 0)
1387 (minus:SI (match_dup 4) (match_dup 3))))
1388 (set (match_operand:SI 0 "gpc_reg_operand" "")
1389 (plus:SI (match_dup 3) (match_dup 1)))]
1390 "TARGET_POWER || TARGET_ISEL"
1391 "
1392 {
1393 if (TARGET_ISEL)
1394 {
1395 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1396 DONE;
1397 }
1398 operands[3] = gen_reg_rtx (SImode);
1399 operands[4] = gen_reg_rtx (SImode);
1400 operands[5] = GEN_INT (-2147483647 - 1);
1401 }")
1403 (define_insn ""
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1406 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1407 (const_int 0)
1408 (minus:SI (match_dup 2) (match_dup 1))))]
1409 "TARGET_POWER"
1410 "doz%I2 %0,%1,%2")
1412 (define_insn ""
1413 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1414 (compare:CC
1415 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1416 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1417 (const_int 0)
1418 (minus:SI (match_dup 2) (match_dup 1)))
1419 (const_int 0)))
1420 (clobber (match_scratch:SI 3 "=r,r"))]
1421 "TARGET_POWER"
1422 "@
1423 doz%I2. %3,%1,%2
1424 #"
1425 [(set_attr "type" "delayed_compare")
1426 (set_attr "length" "4,8")])
1428 (define_split
1429 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1430 (compare:CC
1431 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1432 (match_operand:SI 2 "reg_or_short_operand" ""))
1433 (const_int 0)
1434 (minus:SI (match_dup 2) (match_dup 1)))
1435 (const_int 0)))
1436 (clobber (match_scratch:SI 3 ""))]
1437 "TARGET_POWER && reload_completed"
1438 [(set (match_dup 3)
1439 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1440 (const_int 0)
1441 (minus:SI (match_dup 2) (match_dup 1))))
1442 (set (match_dup 0)
1443 (compare:CC (match_dup 3)
1444 (const_int 0)))]
1445 "")
1447 (define_insn ""
1448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1449 (compare:CC
1450 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1451 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1452 (const_int 0)
1453 (minus:SI (match_dup 2) (match_dup 1)))
1454 (const_int 0)))
1455 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1456 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1457 (const_int 0)
1458 (minus:SI (match_dup 2) (match_dup 1))))]
1459 "TARGET_POWER"
1460 "@
1461 doz%I2. %0,%1,%2
1462 #"
1463 [(set_attr "type" "delayed_compare")
1464 (set_attr "length" "4,8")])
1466 (define_split
1467 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1468 (compare:CC
1469 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1470 (match_operand:SI 2 "reg_or_short_operand" ""))
1471 (const_int 0)
1472 (minus:SI (match_dup 2) (match_dup 1)))
1473 (const_int 0)))
1474 (set (match_operand:SI 0 "gpc_reg_operand" "")
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1476 (const_int 0)
1477 (minus:SI (match_dup 2) (match_dup 1))))]
1478 "TARGET_POWER && reload_completed"
1479 [(set (match_dup 0)
1480 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1481 (const_int 0)
1482 (minus:SI (match_dup 2) (match_dup 1))))
1483 (set (match_dup 3)
1484 (compare:CC (match_dup 0)
1485 (const_int 0)))]
1486 "")
1488 ;; We don't need abs with condition code because such comparisons should
1489 ;; never be done.
1490 (define_expand "abssi2"
1491 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1492 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1493 ""
1494 "
1495 {
1496 if (TARGET_ISEL)
1497 {
1498 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1499 DONE;
1500 }
1501 else if (! TARGET_POWER)
1502 {
1503 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1504 DONE;
1505 }
1506 }")
1508 (define_insn "*abssi2_power"
1509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1510 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1511 "TARGET_POWER"
1512 "abs %0,%1")
1514 (define_insn_and_split "abssi2_isel"
1515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1516 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1517 (clobber (match_scratch:SI 2 "=&b"))
1518 (clobber (match_scratch:CC 3 "=y"))]
1519 "TARGET_ISEL"
1520 "#"
1521 "&& reload_completed"
1522 [(set (match_dup 2) (neg:SI (match_dup 1)))
1523 (set (match_dup 3)
1524 (compare:CC (match_dup 1)
1525 (const_int 0)))
1526 (set (match_dup 0)
1527 (if_then_else:SI (ge (match_dup 3)
1528 (const_int 0))
1529 (match_dup 1)
1530 (match_dup 2)))]
1531 "")
1533 (define_insn_and_split "abssi2_nopower"
1534 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1535 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1536 (clobber (match_scratch:SI 2 "=&r,&r"))]
1537 "! TARGET_POWER && ! TARGET_ISEL"
1538 "#"
1539 "&& reload_completed"
1540 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1541 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1542 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1543 "")
1545 (define_insn "*nabs_power"
1546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1547 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1548 "TARGET_POWER"
1549 "nabs %0,%1")
1551 (define_insn_and_split "*nabs_nopower"
1552 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1553 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1554 (clobber (match_scratch:SI 2 "=&r,&r"))]
1555 "! TARGET_POWER"
1556 "#"
1557 "&& reload_completed"
1558 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1559 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1560 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1561 "")
1563 (define_insn "negsi2"
1564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1565 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1566 ""
1567 "neg %0,%1")
1569 (define_insn ""
1570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1571 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1572 (const_int 0)))
1573 (clobber (match_scratch:SI 2 "=r,r"))]
1574 "TARGET_32BIT"
1575 "@
1576 neg. %2,%1
1577 #"
1578 [(set_attr "type" "fast_compare")
1579 (set_attr "length" "4,8")])
1581 (define_split
1582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1583 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:SI 2 ""))]
1586 "TARGET_32BIT && reload_completed"
1587 [(set (match_dup 2)
1588 (neg:SI (match_dup 1)))
1589 (set (match_dup 0)
1590 (compare:CC (match_dup 2)
1591 (const_int 0)))]
1592 "")
1594 (define_insn ""
1595 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1596 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1597 (const_int 0)))
1598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1599 (neg:SI (match_dup 1)))]
1600 "TARGET_32BIT"
1601 "@
1602 neg. %0,%1
1603 #"
1604 [(set_attr "type" "fast_compare")
1605 (set_attr "length" "4,8")])
1607 (define_split
1608 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1609 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1610 (const_int 0)))
1611 (set (match_operand:SI 0 "gpc_reg_operand" "")
1612 (neg:SI (match_dup 1)))]
1613 "TARGET_32BIT && reload_completed"
1614 [(set (match_dup 0)
1615 (neg:SI (match_dup 1)))
1616 (set (match_dup 2)
1617 (compare:CC (match_dup 0)
1618 (const_int 0)))]
1619 "")
1621 (define_insn "clzsi2"
1622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1623 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1624 ""
1625 "{cntlz|cntlzw} %0,%1")
1627 (define_expand "ctzsi2"
1628 [(set (match_dup 2)
1629 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1630 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1631 (match_dup 2)))
1632 (clobber (scratch:CC))])
1633 (set (match_dup 4) (clz:SI (match_dup 3)))
1634 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1635 (minus:SI (const_int 31) (match_dup 4)))]
1636 ""
1637 {
1638 operands[2] = gen_reg_rtx (SImode);
1639 operands[3] = gen_reg_rtx (SImode);
1640 operands[4] = gen_reg_rtx (SImode);
1641 })
1643 (define_expand "ffssi2"
1644 [(set (match_dup 2)
1645 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1646 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1647 (match_dup 2)))
1648 (clobber (scratch:CC))])
1649 (set (match_dup 4) (clz:SI (match_dup 3)))
1650 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1651 (minus:SI (const_int 32) (match_dup 4)))]
1652 ""
1653 {
1654 operands[2] = gen_reg_rtx (SImode);
1655 operands[3] = gen_reg_rtx (SImode);
1656 operands[4] = gen_reg_rtx (SImode);
1657 })
1659 (define_expand "mulsi3"
1660 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1661 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1662 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1663 ""
1664 "
1665 {
1666 if (TARGET_POWER)
1667 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1668 else
1669 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1670 DONE;
1671 }")
1673 (define_insn "mulsi3_mq"
1674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1675 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1676 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1677 (clobber (match_scratch:SI 3 "=q,q"))]
1678 "TARGET_POWER"
1679 "@
1680 {muls|mullw} %0,%1,%2
1681 {muli|mulli} %0,%1,%2"
1682 [(set (attr "type")
1683 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1684 (const_string "imul3")
1685 (match_operand:SI 2 "short_cint_operand" "")
1686 (const_string "imul2")]
1687 (const_string "imul")))])
1689 (define_insn "mulsi3_no_mq"
1690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1691 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1692 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1693 "! TARGET_POWER"
1694 "@
1695 {muls|mullw} %0,%1,%2
1696 {muli|mulli} %0,%1,%2"
1697 [(set (attr "type")
1698 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1699 (const_string "imul3")
1700 (match_operand:SI 2 "short_cint_operand" "")
1701 (const_string "imul2")]
1702 (const_string "imul")))])
1704 (define_insn "*mulsi3_mq_internal1"
1705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1706 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1707 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1708 (const_int 0)))
1709 (clobber (match_scratch:SI 3 "=r,r"))
1710 (clobber (match_scratch:SI 4 "=q,q"))]
1711 "TARGET_POWER"
1712 "@
1713 {muls.|mullw.} %3,%1,%2
1714 #"
1715 [(set_attr "type" "imul_compare")
1716 (set_attr "length" "4,8")])
1718 (define_split
1719 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1720 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1721 (match_operand:SI 2 "gpc_reg_operand" ""))
1722 (const_int 0)))
1723 (clobber (match_scratch:SI 3 ""))
1724 (clobber (match_scratch:SI 4 ""))]
1725 "TARGET_POWER && reload_completed"
1726 [(parallel [(set (match_dup 3)
1727 (mult:SI (match_dup 1) (match_dup 2)))
1728 (clobber (match_dup 4))])
1729 (set (match_dup 0)
1730 (compare:CC (match_dup 3)
1731 (const_int 0)))]
1732 "")
1734 (define_insn "*mulsi3_no_mq_internal1"
1735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1736 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1737 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1738 (const_int 0)))
1739 (clobber (match_scratch:SI 3 "=r,r"))]
1740 "! TARGET_POWER"
1741 "@
1742 {muls.|mullw.} %3,%1,%2
1743 #"
1744 [(set_attr "type" "imul_compare")
1745 (set_attr "length" "4,8")])
1747 (define_split
1748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1749 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1750 (match_operand:SI 2 "gpc_reg_operand" ""))
1751 (const_int 0)))
1752 (clobber (match_scratch:SI 3 ""))]
1753 "! TARGET_POWER && reload_completed"
1754 [(set (match_dup 3)
1755 (mult:SI (match_dup 1) (match_dup 2)))
1756 (set (match_dup 0)
1757 (compare:CC (match_dup 3)
1758 (const_int 0)))]
1759 "")
1761 (define_insn "*mulsi3_mq_internal2"
1762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1763 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1765 (const_int 0)))
1766 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_dup 1) (match_dup 2)))
1768 (clobber (match_scratch:SI 4 "=q,q"))]
1769 "TARGET_POWER"
1770 "@
1771 {muls.|mullw.} %0,%1,%2
1772 #"
1773 [(set_attr "type" "imul_compare")
1774 (set_attr "length" "4,8")])
1776 (define_split
1777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1778 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1779 (match_operand:SI 2 "gpc_reg_operand" ""))
1780 (const_int 0)))
1781 (set (match_operand:SI 0 "gpc_reg_operand" "")
1782 (mult:SI (match_dup 1) (match_dup 2)))
1783 (clobber (match_scratch:SI 4 ""))]
1784 "TARGET_POWER && reload_completed"
1785 [(parallel [(set (match_dup 0)
1786 (mult:SI (match_dup 1) (match_dup 2)))
1787 (clobber (match_dup 4))])
1788 (set (match_dup 3)
1789 (compare:CC (match_dup 0)
1790 (const_int 0)))]
1791 "")
1793 (define_insn "*mulsi3_no_mq_internal2"
1794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1795 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1796 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1797 (const_int 0)))
1798 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1799 (mult:SI (match_dup 1) (match_dup 2)))]
1800 "! TARGET_POWER"
1801 "@
1802 {muls.|mullw.} %0,%1,%2
1803 #"
1804 [(set_attr "type" "imul_compare")
1805 (set_attr "length" "4,8")])
1807 (define_split
1808 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1809 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1810 (match_operand:SI 2 "gpc_reg_operand" ""))
1811 (const_int 0)))
1812 (set (match_operand:SI 0 "gpc_reg_operand" "")
1813 (mult:SI (match_dup 1) (match_dup 2)))]
1814 "! TARGET_POWER && reload_completed"
1815 [(set (match_dup 0)
1816 (mult:SI (match_dup 1) (match_dup 2)))
1817 (set (match_dup 3)
1818 (compare:CC (match_dup 0)
1819 (const_int 0)))]
1820 "")
1822 ;; Operand 1 is divided by operand 2; quotient goes to operand
1823 ;; 0 and remainder to operand 3.
1824 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1826 (define_expand "divmodsi4"
1827 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1828 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1829 (match_operand:SI 2 "gpc_reg_operand" "")))
1830 (set (match_operand:SI 3 "register_operand" "")
1831 (mod:SI (match_dup 1) (match_dup 2)))])]
1832 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1833 "
1834 {
1835 if (! TARGET_POWER && ! TARGET_POWERPC)
1836 {
1837 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1838 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1839 emit_insn (gen_divss_call ());
1840 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1841 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1842 DONE;
1843 }
1844 }")
1846 (define_insn "*divmodsi4_internal"
1847 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1849 (match_operand:SI 2 "gpc_reg_operand" "r")))
1850 (set (match_operand:SI 3 "register_operand" "=q")
1851 (mod:SI (match_dup 1) (match_dup 2)))]
1852 "TARGET_POWER"
1853 "divs %0,%1,%2"
1854 [(set_attr "type" "idiv")])
1856 (define_expand "udivsi3"
1857 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1858 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1859 (match_operand:SI 2 "gpc_reg_operand" "")))]
1860 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1861 "
1862 {
1863 if (! TARGET_POWER && ! TARGET_POWERPC)
1864 {
1865 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1866 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1867 emit_insn (gen_quous_call ());
1868 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1869 DONE;
1870 }
1871 else if (TARGET_POWER)
1872 {
1873 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1874 DONE;
1875 }
1876 }")
1878 (define_insn "udivsi3_mq"
1879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1880 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1881 (match_operand:SI 2 "gpc_reg_operand" "r")))
1882 (clobber (match_scratch:SI 3 "=q"))]
1883 "TARGET_POWERPC && TARGET_POWER"
1884 "divwu %0,%1,%2"
1885 [(set_attr "type" "idiv")])
1887 (define_insn "*udivsi3_no_mq"
1888 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1889 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1890 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1891 "TARGET_POWERPC && ! TARGET_POWER"
1892 "divwu %0,%1,%2"
1893 [(set_attr "type" "idiv")])
1895 ;; For powers of two we can do srai/aze for divide and then adjust for
1896 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1897 ;; used; for PowerPC, force operands into register and do a normal divide;
1898 ;; for AIX common-mode, use quoss call on register operands.
1899 (define_expand "divsi3"
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1901 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1902 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1903 ""
1904 "
1905 {
1906 if (GET_CODE (operands[2]) == CONST_INT
1907 && INTVAL (operands[2]) > 0
1908 && exact_log2 (INTVAL (operands[2])) >= 0)
1909 ;
1910 else if (TARGET_POWERPC)
1911 {
1912 operands[2] = force_reg (SImode, operands[2]);
1913 if (TARGET_POWER)
1914 {
1915 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1916 DONE;
1917 }
1918 }
1919 else if (TARGET_POWER)
1920 FAIL;
1921 else
1922 {
1923 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1924 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1925 emit_insn (gen_quoss_call ());
1926 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1927 DONE;
1928 }
1929 }")
1931 (define_insn "divsi3_mq"
1932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1933 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1934 (match_operand:SI 2 "gpc_reg_operand" "r")))
1935 (clobber (match_scratch:SI 3 "=q"))]
1936 "TARGET_POWERPC && TARGET_POWER"
1937 "divw %0,%1,%2"
1938 [(set_attr "type" "idiv")])
1940 (define_insn "*divsi3_no_mq"
1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1942 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1943 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1944 "TARGET_POWERPC && ! TARGET_POWER"
1945 "divw %0,%1,%2"
1946 [(set_attr "type" "idiv")])
1948 (define_expand "modsi3"
1949 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1950 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1951 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1952 ""
1953 "
1954 {
1955 int i;
1956 rtx temp1;
1957 rtx temp2;
1959 if (GET_CODE (operands[2]) != CONST_INT
1960 || INTVAL (operands[2]) <= 0
1961 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1962 FAIL;
1964 temp1 = gen_reg_rtx (SImode);
1965 temp2 = gen_reg_rtx (SImode);
1967 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1968 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1969 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1970 DONE;
1971 }")
1973 (define_insn ""
1974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1975 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1976 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1977 ""
1978 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1979 [(set_attr "type" "two")
1980 (set_attr "length" "8")])
1982 (define_insn ""
1983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1984 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1985 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1986 (const_int 0)))
1987 (clobber (match_scratch:SI 3 "=r,r"))]
1988 ""
1989 "@
1990 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1991 #"
1992 [(set_attr "type" "compare")
1993 (set_attr "length" "8,12")])
1995 (define_split
1996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1997 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1999 (const_int 0)))
2000 (clobber (match_scratch:SI 3 ""))]
2001 "reload_completed"
2002 [(set (match_dup 3)
2003 (div:SI (match_dup 1) (match_dup 2)))
2004 (set (match_dup 0)
2005 (compare:CC (match_dup 3)
2006 (const_int 0)))]
2007 "")
2009 (define_insn ""
2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2011 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2012 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2013 (const_int 0)))
2014 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2015 (div:SI (match_dup 1) (match_dup 2)))]
2016 ""
2017 "@
2018 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2019 #"
2020 [(set_attr "type" "compare")
2021 (set_attr "length" "8,12")])
2023 (define_split
2024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2025 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2026 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2027 (const_int 0)))
2028 (set (match_operand:SI 0 "gpc_reg_operand" "")
2029 (div:SI (match_dup 1) (match_dup 2)))]
2030 "reload_completed"
2031 [(set (match_dup 0)
2032 (div:SI (match_dup 1) (match_dup 2)))
2033 (set (match_dup 3)
2034 (compare:CC (match_dup 0)
2035 (const_int 0)))]
2036 "")
2038 (define_insn ""
2039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2040 (udiv:SI
2041 (plus:DI (ashift:DI
2042 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2043 (const_int 32))
2044 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2045 (match_operand:SI 3 "gpc_reg_operand" "r")))
2046 (set (match_operand:SI 2 "register_operand" "=*q")
2047 (umod:SI
2048 (plus:DI (ashift:DI
2049 (zero_extend:DI (match_dup 1)) (const_int 32))
2050 (zero_extend:DI (match_dup 4)))
2051 (match_dup 3)))]
2052 "TARGET_POWER"
2053 "div %0,%1,%3"
2054 [(set_attr "type" "idiv")])
2056 ;; To do unsigned divide we handle the cases of the divisor looking like a
2057 ;; negative number. If it is a constant that is less than 2**31, we don't
2058 ;; have to worry about the branches. So make a few subroutines here.
2059 ;;
2060 ;; First comes the normal case.
2061 (define_expand "udivmodsi4_normal"
2062 [(set (match_dup 4) (const_int 0))
2063 (parallel [(set (match_operand:SI 0 "" "")
2064 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2065 (const_int 32))
2066 (zero_extend:DI (match_operand:SI 1 "" "")))
2067 (match_operand:SI 2 "" "")))
2068 (set (match_operand:SI 3 "" "")
2069 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2070 (const_int 32))
2071 (zero_extend:DI (match_dup 1)))
2072 (match_dup 2)))])]
2073 "TARGET_POWER"
2074 "
2075 { operands[4] = gen_reg_rtx (SImode); }")
2077 ;; This handles the branches.
2078 (define_expand "udivmodsi4_tests"
2079 [(set (match_operand:SI 0 "" "") (const_int 0))
2080 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2081 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2082 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2083 (label_ref (match_operand:SI 4 "" "")) (pc)))
2084 (set (match_dup 0) (const_int 1))
2085 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2086 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2087 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2088 (label_ref (match_dup 4)) (pc)))]
2089 "TARGET_POWER"
2090 "
2091 { operands[5] = gen_reg_rtx (CCUNSmode);
2092 operands[6] = gen_reg_rtx (CCmode);
2093 }")
2095 (define_expand "udivmodsi4"
2096 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2097 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2098 (match_operand:SI 2 "reg_or_cint_operand" "")))
2099 (set (match_operand:SI 3 "gpc_reg_operand" "")
2100 (umod:SI (match_dup 1) (match_dup 2)))])]
2101 ""
2102 "
2103 {
2104 rtx label = 0;
2106 if (! TARGET_POWER)
2107 {
2108 if (! TARGET_POWERPC)
2109 {
2110 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2111 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2112 emit_insn (gen_divus_call ());
2113 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2114 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2115 DONE;
2116 }
2117 else
2118 FAIL;
2119 }
2121 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2122 {
2123 operands[2] = force_reg (SImode, operands[2]);
2124 label = gen_label_rtx ();
2125 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2126 operands[3], label));
2127 }
2128 else
2129 operands[2] = force_reg (SImode, operands[2]);
2131 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2132 operands[3]));
2133 if (label)
2134 emit_label (label);
2136 DONE;
2137 }")
2139 ;; AIX architecture-independent common-mode multiply (DImode),
2140 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2141 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2142 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2143 ;; assumed unused if generating common-mode, so ignore.
2144 (define_insn "mulh_call"
2145 [(set (reg:SI 3)
2146 (truncate:SI
2147 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2148 (sign_extend:DI (reg:SI 4)))
2149 (const_int 32))))
2150 (clobber (match_scratch:SI 0 "=l"))]
2151 "! TARGET_POWER && ! TARGET_POWERPC"
2152 "bla __mulh"
2153 [(set_attr "type" "imul")])
2155 (define_insn "mull_call"
2156 [(set (reg:DI 3)
2157 (mult:DI (sign_extend:DI (reg:SI 3))
2158 (sign_extend:DI (reg:SI 4))))
2159 (clobber (match_scratch:SI 0 "=l"))
2160 (clobber (reg:SI 0))]
2161 "! TARGET_POWER && ! TARGET_POWERPC"
2162 "bla __mull"
2163 [(set_attr "type" "imul")])
2165 (define_insn "divss_call"
2166 [(set (reg:SI 3)
2167 (div:SI (reg:SI 3) (reg:SI 4)))
2168 (set (reg:SI 4)
2169 (mod:SI (reg:SI 3) (reg:SI 4)))
2170 (clobber (match_scratch:SI 0 "=l"))
2171 (clobber (reg:SI 0))]
2172 "! TARGET_POWER && ! TARGET_POWERPC"
2173 "bla __divss"
2174 [(set_attr "type" "idiv")])
2176 (define_insn "divus_call"
2177 [(set (reg:SI 3)
2178 (udiv:SI (reg:SI 3) (reg:SI 4)))
2179 (set (reg:SI 4)
2180 (umod:SI (reg:SI 3) (reg:SI 4)))
2181 (clobber (match_scratch:SI 0 "=l"))
2182 (clobber (reg:SI 0))
2183 (clobber (match_scratch:CC 1 "=x"))
2184 (clobber (reg:CC 69))]
2185 "! TARGET_POWER && ! TARGET_POWERPC"
2186 "bla __divus"
2187 [(set_attr "type" "idiv")])
2189 (define_insn "quoss_call"
2190 [(set (reg:SI 3)
2191 (div:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))]
2193 "! TARGET_POWER && ! TARGET_POWERPC"
2194 "bla __quoss"
2195 [(set_attr "type" "idiv")])
2197 (define_insn "quous_call"
2198 [(set (reg:SI 3)
2199 (udiv:SI (reg:SI 3) (reg:SI 4)))
2200 (clobber (match_scratch:SI 0 "=l"))
2201 (clobber (reg:SI 0))
2202 (clobber (match_scratch:CC 1 "=x"))
2203 (clobber (reg:CC 69))]
2204 "! TARGET_POWER && ! TARGET_POWERPC"
2205 "bla __quous"
2206 [(set_attr "type" "idiv")])
2207 \f
2208 ;; Logical instructions
2209 ;; The logical instructions are mostly combined by using match_operator,
2210 ;; but the plain AND insns are somewhat different because there is no
2211 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2212 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2214 (define_insn "andsi3"
2215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2216 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2217 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2218 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2219 ""
2220 "@
2221 and %0,%1,%2
2222 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2223 {andil.|andi.} %0,%1,%b2
2224 {andiu.|andis.} %0,%1,%u2"
2225 [(set_attr "type" "*,*,compare,compare")])
2227 ;; Note to set cr's other than cr0 we do the and immediate and then
2228 ;; the test again -- this avoids a mfcr which on the higher end
2229 ;; machines causes an execution serialization
2231 (define_insn "*andsi3_internal2"
2232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2233 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2234 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2235 (const_int 0)))
2236 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2237 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2238 "TARGET_32BIT"
2239 "@
2240 and. %3,%1,%2
2241 {andil.|andi.} %3,%1,%b2
2242 {andiu.|andis.} %3,%1,%u2
2243 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2244 #
2245 #
2246 #
2247 #"
2248 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2249 (set_attr "length" "4,4,4,4,8,8,8,8")])
2251 (define_insn "*andsi3_internal3"
2252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2253 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2254 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2255 (const_int 0)))
2256 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2257 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2258 "TARGET_64BIT"
2259 "@
2260 #
2261 {andil.|andi.} %3,%1,%b2
2262 {andiu.|andis.} %3,%1,%u2
2263 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2264 #
2265 #
2266 #
2267 #"
2268 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2269 (set_attr "length" "8,4,4,4,8,8,8,8")])
2271 (define_split
2272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2273 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2274 (match_operand:SI 2 "and_operand" ""))
2275 (const_int 0)))
2276 (clobber (match_scratch:SI 3 ""))
2277 (clobber (match_scratch:CC 4 ""))]
2278 "reload_completed"
2279 [(parallel [(set (match_dup 3)
2280 (and:SI (match_dup 1)
2281 (match_dup 2)))
2282 (clobber (match_dup 4))])
2283 (set (match_dup 0)
2284 (compare:CC (match_dup 3)
2285 (const_int 0)))]
2286 "")
2288 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2289 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2291 (define_split
2292 [(set (match_operand:CC 0 "cc_reg_operand" "")
2293 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2294 (match_operand:SI 2 "gpc_reg_operand" ""))
2295 (const_int 0)))
2296 (clobber (match_scratch:SI 3 ""))
2297 (clobber (match_scratch:CC 4 ""))]
2298 "TARGET_POWERPC64 && reload_completed"
2299 [(parallel [(set (match_dup 3)
2300 (and:SI (match_dup 1)
2301 (match_dup 2)))
2302 (clobber (match_dup 4))])
2303 (set (match_dup 0)
2304 (compare:CC (match_dup 3)
2305 (const_int 0)))]
2306 "")
2308 (define_insn "*andsi3_internal4"
2309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2310 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2311 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2312 (const_int 0)))
2313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2314 (and:SI (match_dup 1)
2315 (match_dup 2)))
2316 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2317 "TARGET_32BIT"
2318 "@
2319 and. %0,%1,%2
2320 {andil.|andi.} %0,%1,%b2
2321 {andiu.|andis.} %0,%1,%u2
2322 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2323 #
2324 #
2325 #
2326 #"
2327 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2328 (set_attr "length" "4,4,4,4,8,8,8,8")])
2330 (define_insn "*andsi3_internal5"
2331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2332 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2333 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2334 (const_int 0)))
2335 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2336 (and:SI (match_dup 1)
2337 (match_dup 2)))
2338 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2339 "TARGET_64BIT"
2340 "@
2341 #
2342 {andil.|andi.} %0,%1,%b2
2343 {andiu.|andis.} %0,%1,%u2
2344 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2345 #
2346 #
2347 #
2348 #"
2349 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2350 (set_attr "length" "8,4,4,4,8,8,8,8")])
2352 (define_split
2353 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2354 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2355 (match_operand:SI 2 "and_operand" ""))
2356 (const_int 0)))
2357 (set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (and:SI (match_dup 1)
2359 (match_dup 2)))
2360 (clobber (match_scratch:CC 4 ""))]
2361 "reload_completed"
2362 [(parallel [(set (match_dup 0)
2363 (and:SI (match_dup 1)
2364 (match_dup 2)))
2365 (clobber (match_dup 4))])
2366 (set (match_dup 3)
2367 (compare:CC (match_dup 0)
2368 (const_int 0)))]
2369 "")
2371 (define_split
2372 [(set (match_operand:CC 3 "cc_reg_operand" "")
2373 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2374 (match_operand:SI 2 "gpc_reg_operand" ""))
2375 (const_int 0)))
2376 (set (match_operand:SI 0 "gpc_reg_operand" "")
2377 (and:SI (match_dup 1)
2378 (match_dup 2)))
2379 (clobber (match_scratch:CC 4 ""))]
2380 "TARGET_POWERPC64 && reload_completed"
2381 [(parallel [(set (match_dup 0)
2382 (and:SI (match_dup 1)
2383 (match_dup 2)))
2384 (clobber (match_dup 4))])
2385 (set (match_dup 3)
2386 (compare:CC (match_dup 0)
2387 (const_int 0)))]
2388 "")
2390 ;; Handle the PowerPC64 rlwinm corner case
2392 (define_insn_and_split "*andsi3_internal6"
2393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2394 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2395 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2396 "TARGET_POWERPC64"
2397 "#"
2398 "TARGET_POWERPC64"
2399 [(set (match_dup 0)
2400 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2401 (match_dup 4)))
2402 (set (match_dup 0)
2403 (rotate:SI (match_dup 0) (match_dup 5)))]
2404 "
2405 {
2406 int mb = extract_MB (operands[2]);
2407 int me = extract_ME (operands[2]);
2408 operands[3] = GEN_INT (me + 1);
2409 operands[5] = GEN_INT (32 - (me + 1));
2410 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2411 }"
2412 [(set_attr "length" "8")])
2414 (define_expand "iorsi3"
2415 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2416 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2417 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2418 ""
2419 "
2420 {
2421 if (GET_CODE (operands[2]) == CONST_INT
2422 && ! logical_operand (operands[2], SImode))
2423 {
2424 HOST_WIDE_INT value = INTVAL (operands[2]);
2425 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2426 ? operands[0] : gen_reg_rtx (SImode));
2428 emit_insn (gen_iorsi3 (tmp, operands[1],
2429 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2430 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2431 DONE;
2432 }
2433 }")
2435 (define_expand "xorsi3"
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2437 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2438 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2439 ""
2440 "
2441 {
2442 if (GET_CODE (operands[2]) == CONST_INT
2443 && ! logical_operand (operands[2], SImode))
2444 {
2445 HOST_WIDE_INT value = INTVAL (operands[2]);
2446 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2447 ? operands[0] : gen_reg_rtx (SImode));
2449 emit_insn (gen_xorsi3 (tmp, operands[1],
2450 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2451 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2452 DONE;
2453 }
2454 }")
2456 (define_insn "*boolsi3_internal1"
2457 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2458 (match_operator:SI 3 "boolean_or_operator"
2459 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2460 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2461 ""
2462 "@
2463 %q3 %0,%1,%2
2464 {%q3il|%q3i} %0,%1,%b2
2465 {%q3iu|%q3is} %0,%1,%u2")
2467 (define_insn "*boolsi3_internal2"
2468 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2469 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2470 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2471 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2472 (const_int 0)))
2473 (clobber (match_scratch:SI 3 "=r,r"))]
2474 "TARGET_32BIT"
2475 "@
2476 %q4. %3,%1,%2
2477 #"
2478 [(set_attr "type" "compare")
2479 (set_attr "length" "4,8")])
2481 (define_split
2482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2483 (compare:CC (match_operator:SI 4 "boolean_operator"
2484 [(match_operand:SI 1 "gpc_reg_operand" "")
2485 (match_operand:SI 2 "gpc_reg_operand" "")])
2486 (const_int 0)))
2487 (clobber (match_scratch:SI 3 ""))]
2488 "TARGET_32BIT && reload_completed"
2489 [(set (match_dup 3) (match_dup 4))
2490 (set (match_dup 0)
2491 (compare:CC (match_dup 3)
2492 (const_int 0)))]
2493 "")
2495 (define_insn "*boolsi3_internal3"
2496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2497 (compare:CC (match_operator:SI 4 "boolean_operator"
2498 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2499 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2500 (const_int 0)))
2501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2502 (match_dup 4))]
2503 "TARGET_32BIT"
2504 "@
2505 %q4. %0,%1,%2
2506 #"
2507 [(set_attr "type" "compare")
2508 (set_attr "length" "4,8")])
2510 (define_split
2511 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2512 (compare:CC (match_operator:SI 4 "boolean_operator"
2513 [(match_operand:SI 1 "gpc_reg_operand" "")
2514 (match_operand:SI 2 "gpc_reg_operand" "")])
2515 (const_int 0)))
2516 (set (match_operand:SI 0 "gpc_reg_operand" "")
2517 (match_dup 4))]
2518 "TARGET_32BIT && reload_completed"
2519 [(set (match_dup 0) (match_dup 4))
2520 (set (match_dup 3)
2521 (compare:CC (match_dup 0)
2522 (const_int 0)))]
2523 "")
2525 ;; Split a logical operation that we can't do in one insn into two insns,
2526 ;; each of which does one 16-bit part. This is used by combine.
2528 (define_split
2529 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2530 (match_operator:SI 3 "boolean_or_operator"
2531 [(match_operand:SI 1 "gpc_reg_operand" "")
2532 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2533 ""
2534 [(set (match_dup 0) (match_dup 4))
2535 (set (match_dup 0) (match_dup 5))]
2536 "
2537 {
2538 rtx i;
2539 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2540 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2541 operands[1], i);
2542 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2543 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2544 operands[0], i);
2545 }")
2547 (define_insn "*boolcsi3_internal1"
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2549 (match_operator:SI 3 "boolean_operator"
2550 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2551 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2552 ""
2553 "%q3 %0,%2,%1")
2555 (define_insn "*boolcsi3_internal2"
2556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2557 (compare:CC (match_operator:SI 4 "boolean_operator"
2558 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2559 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2560 (const_int 0)))
2561 (clobber (match_scratch:SI 3 "=r,r"))]
2562 "TARGET_32BIT"
2563 "@
2564 %q4. %3,%2,%1
2565 #"
2566 [(set_attr "type" "compare")
2567 (set_attr "length" "4,8")])
2569 (define_split
2570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2571 (compare:CC (match_operator:SI 4 "boolean_operator"
2572 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2573 (match_operand:SI 2 "gpc_reg_operand" "")])
2574 (const_int 0)))
2575 (clobber (match_scratch:SI 3 ""))]
2576 "TARGET_32BIT && reload_completed"
2577 [(set (match_dup 3) (match_dup 4))
2578 (set (match_dup 0)
2579 (compare:CC (match_dup 3)
2580 (const_int 0)))]
2581 "")
2583 (define_insn "*boolcsi3_internal3"
2584 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2585 (compare:CC (match_operator:SI 4 "boolean_operator"
2586 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2587 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2588 (const_int 0)))
2589 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2590 (match_dup 4))]
2591 "TARGET_32BIT"
2592 "@
2593 %q4. %0,%2,%1
2594 #"
2595 [(set_attr "type" "compare")
2596 (set_attr "length" "4,8")])
2598 (define_split
2599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2600 (compare:CC (match_operator:SI 4 "boolean_operator"
2601 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2602 (match_operand:SI 2 "gpc_reg_operand" "")])
2603 (const_int 0)))
2604 (set (match_operand:SI 0 "gpc_reg_operand" "")
2605 (match_dup 4))]
2606 "TARGET_32BIT && reload_completed"
2607 [(set (match_dup 0) (match_dup 4))
2608 (set (match_dup 3)
2609 (compare:CC (match_dup 0)
2610 (const_int 0)))]
2611 "")
2613 (define_insn "*boolccsi3_internal1"
2614 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2615 (match_operator:SI 3 "boolean_operator"
2616 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2617 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2618 ""
2619 "%q3 %0,%1,%2")
2621 (define_insn "*boolccsi3_internal2"
2622 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2623 (compare:CC (match_operator:SI 4 "boolean_operator"
2624 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2625 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2626 (const_int 0)))
2627 (clobber (match_scratch:SI 3 "=r,r"))]
2628 "TARGET_32BIT"
2629 "@
2630 %q4. %3,%1,%2
2631 #"
2632 [(set_attr "type" "compare")
2633 (set_attr "length" "4,8")])
2635 (define_split
2636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2637 (compare:CC (match_operator:SI 4 "boolean_operator"
2638 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2639 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2640 (const_int 0)))
2641 (clobber (match_scratch:SI 3 ""))]
2642 "TARGET_32BIT && reload_completed"
2643 [(set (match_dup 3) (match_dup 4))
2644 (set (match_dup 0)
2645 (compare:CC (match_dup 3)
2646 (const_int 0)))]
2647 "")
2649 (define_insn "*boolccsi3_internal3"
2650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2651 (compare:CC (match_operator:SI 4 "boolean_operator"
2652 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2653 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2654 (const_int 0)))
2655 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2656 (match_dup 4))]
2657 "TARGET_32BIT"
2658 "@
2659 %q4. %0,%1,%2
2660 #"
2661 [(set_attr "type" "compare")
2662 (set_attr "length" "4,8")])
2664 (define_split
2665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2666 (compare:CC (match_operator:SI 4 "boolean_operator"
2667 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2668 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2669 (const_int 0)))
2670 (set (match_operand:SI 0 "gpc_reg_operand" "")
2671 (match_dup 4))]
2672 "TARGET_32BIT && reload_completed"
2673 [(set (match_dup 0) (match_dup 4))
2674 (set (match_dup 3)
2675 (compare:CC (match_dup 0)
2676 (const_int 0)))]
2677 "")
2679 ;; maskir insn. We need four forms because things might be in arbitrary
2680 ;; orders. Don't define forms that only set CR fields because these
2681 ;; would modify an input register.
2683 (define_insn "*maskir_internal1"
2684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2685 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2686 (match_operand:SI 1 "gpc_reg_operand" "0"))
2687 (and:SI (match_dup 2)
2688 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2689 "TARGET_POWER"
2690 "maskir %0,%3,%2")
2692 (define_insn "*maskir_internal2"
2693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2694 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2695 (match_operand:SI 1 "gpc_reg_operand" "0"))
2696 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2697 (match_dup 2))))]
2698 "TARGET_POWER"
2699 "maskir %0,%3,%2")
2701 (define_insn "*maskir_internal3"
2702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2703 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2704 (match_operand:SI 3 "gpc_reg_operand" "r"))
2705 (and:SI (not:SI (match_dup 2))
2706 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2707 "TARGET_POWER"
2708 "maskir %0,%3,%2")
2710 (define_insn "*maskir_internal4"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2712 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2713 (match_operand:SI 2 "gpc_reg_operand" "r"))
2714 (and:SI (not:SI (match_dup 2))
2715 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2716 "TARGET_POWER"
2717 "maskir %0,%3,%2")
2719 (define_insn "*maskir_internal5"
2720 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2721 (compare:CC
2722 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2723 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2724 (and:SI (match_dup 2)
2725 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2726 (const_int 0)))
2727 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2728 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2729 (and:SI (match_dup 2) (match_dup 3))))]
2730 "TARGET_POWER"
2731 "@
2732 maskir. %0,%3,%2
2733 #"
2734 [(set_attr "type" "compare")
2735 (set_attr "length" "4,8")])
2737 (define_split
2738 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2739 (compare:CC
2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2741 (match_operand:SI 1 "gpc_reg_operand" ""))
2742 (and:SI (match_dup 2)
2743 (match_operand:SI 3 "gpc_reg_operand" "")))
2744 (const_int 0)))
2745 (set (match_operand:SI 0 "gpc_reg_operand" "")
2746 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2747 (and:SI (match_dup 2) (match_dup 3))))]
2748 "TARGET_POWER && reload_completed"
2749 [(set (match_dup 0)
2750 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2751 (and:SI (match_dup 2) (match_dup 3))))
2752 (set (match_dup 4)
2753 (compare:CC (match_dup 0)
2754 (const_int 0)))]
2755 "")
2757 (define_insn "*maskir_internal6"
2758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2759 (compare:CC
2760 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2761 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2762 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2763 (match_dup 2)))
2764 (const_int 0)))
2765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2766 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2767 (and:SI (match_dup 3) (match_dup 2))))]
2768 "TARGET_POWER"
2769 "@
2770 maskir. %0,%3,%2
2771 #"
2772 [(set_attr "type" "compare")
2773 (set_attr "length" "4,8")])
2775 (define_split
2776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2777 (compare:CC
2778 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2779 (match_operand:SI 1 "gpc_reg_operand" ""))
2780 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2781 (match_dup 2)))
2782 (const_int 0)))
2783 (set (match_operand:SI 0 "gpc_reg_operand" "")
2784 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2785 (and:SI (match_dup 3) (match_dup 2))))]
2786 "TARGET_POWER && reload_completed"
2787 [(set (match_dup 0)
2788 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2789 (and:SI (match_dup 3) (match_dup 2))))
2790 (set (match_dup 4)
2791 (compare:CC (match_dup 0)
2792 (const_int 0)))]
2793 "")
2795 (define_insn "*maskir_internal7"
2796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2797 (compare:CC
2798 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2799 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2800 (and:SI (not:SI (match_dup 2))
2801 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2804 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2805 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2806 "TARGET_POWER"
2807 "@
2808 maskir. %0,%3,%2
2809 #"
2810 [(set_attr "type" "compare")
2811 (set_attr "length" "4,8")])
2813 (define_split
2814 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2815 (compare:CC
2816 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2817 (match_operand:SI 3 "gpc_reg_operand" ""))
2818 (and:SI (not:SI (match_dup 2))
2819 (match_operand:SI 1 "gpc_reg_operand" "")))
2820 (const_int 0)))
2821 (set (match_operand:SI 0 "gpc_reg_operand" "")
2822 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2823 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2824 "TARGET_POWER && reload_completed"
2825 [(set (match_dup 0)
2826 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2827 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2828 (set (match_dup 4)
2829 (compare:CC (match_dup 0)
2830 (const_int 0)))]
2831 "")
2833 (define_insn "*maskir_internal8"
2834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2835 (compare:CC
2836 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2837 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2838 (and:SI (not:SI (match_dup 2))
2839 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2840 (const_int 0)))
2841 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2842 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2843 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2844 "TARGET_POWER"
2845 "@
2846 maskir. %0,%3,%2
2847 #"
2848 [(set_attr "type" "compare")
2849 (set_attr "length" "4,8")])
2851 (define_split
2852 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2853 (compare:CC
2854 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2855 (match_operand:SI 2 "gpc_reg_operand" ""))
2856 (and:SI (not:SI (match_dup 2))
2857 (match_operand:SI 1 "gpc_reg_operand" "")))
2858 (const_int 0)))
2859 (set (match_operand:SI 0 "gpc_reg_operand" "")
2860 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2861 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2862 "TARGET_POWER && reload_completed"
2863 [(set (match_dup 0)
2864 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2865 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2866 (set (match_dup 4)
2867 (compare:CC (match_dup 0)
2868 (const_int 0)))]
2869 "")
2870 \f
2871 ;; Rotate and shift insns, in all their variants. These support shifts,
2872 ;; field inserts and extracts, and various combinations thereof.
2873 (define_expand "insv"
2874 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2875 (match_operand:SI 1 "const_int_operand" "")
2876 (match_operand:SI 2 "const_int_operand" ""))
2877 (match_operand 3 "gpc_reg_operand" ""))]
2878 ""
2879 "
2880 {
2881 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2882 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2883 compiler if the address of the structure is taken later. */
2884 if (GET_CODE (operands[0]) == SUBREG
2885 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2886 FAIL;
2888 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2889 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2890 else
2891 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2892 DONE;
2893 }")
2895 (define_insn "insvsi"
2896 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2897 (match_operand:SI 1 "const_int_operand" "i")
2898 (match_operand:SI 2 "const_int_operand" "i"))
2899 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2900 ""
2901 "*
2902 {
2903 int start = INTVAL (operands[2]) & 31;
2904 int size = INTVAL (operands[1]) & 31;
2906 operands[4] = GEN_INT (32 - start - size);
2907 operands[1] = GEN_INT (start + size - 1);
2908 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2909 }"
2910 [(set_attr "type" "insert_word")])
2912 (define_insn "*insvsi_internal1"
2913 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2914 (match_operand:SI 1 "const_int_operand" "i")
2915 (match_operand:SI 2 "const_int_operand" "i"))
2916 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2917 (match_operand:SI 4 "const_int_operand" "i")))]
2918 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2919 "*
2920 {
2921 int shift = INTVAL (operands[4]) & 31;
2922 int start = INTVAL (operands[2]) & 31;
2923 int size = INTVAL (operands[1]) & 31;
2925 operands[4] = GEN_INT (shift - start - size);
2926 operands[1] = GEN_INT (start + size - 1);
2927 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2928 }"
2929 [(set_attr "type" "insert_word")])
2931 (define_insn "*insvsi_internal2"
2932 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2933 (match_operand:SI 1 "const_int_operand" "i")
2934 (match_operand:SI 2 "const_int_operand" "i"))
2935 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2936 (match_operand:SI 4 "const_int_operand" "i")))]
2937 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2938 "*
2939 {
2940 int shift = INTVAL (operands[4]) & 31;
2941 int start = INTVAL (operands[2]) & 31;
2942 int size = INTVAL (operands[1]) & 31;
2944 operands[4] = GEN_INT (32 - shift - start - size);
2945 operands[1] = GEN_INT (start + size - 1);
2946 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2947 }"
2948 [(set_attr "type" "insert_word")])
2950 (define_insn "*insvsi_internal3"
2951 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2952 (match_operand:SI 1 "const_int_operand" "i")
2953 (match_operand:SI 2 "const_int_operand" "i"))
2954 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2955 (match_operand:SI 4 "const_int_operand" "i")))]
2956 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2957 "*
2958 {
2959 int shift = INTVAL (operands[4]) & 31;
2960 int start = INTVAL (operands[2]) & 31;
2961 int size = INTVAL (operands[1]) & 31;
2963 operands[4] = GEN_INT (32 - shift - start - size);
2964 operands[1] = GEN_INT (start + size - 1);
2965 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2966 }"
2967 [(set_attr "type" "insert_word")])
2969 (define_insn "*insvsi_internal4"
2970 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2971 (match_operand:SI 1 "const_int_operand" "i")
2972 (match_operand:SI 2 "const_int_operand" "i"))
2973 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2974 (match_operand:SI 4 "const_int_operand" "i")
2975 (match_operand:SI 5 "const_int_operand" "i")))]
2976 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2977 "*
2978 {
2979 int extract_start = INTVAL (operands[5]) & 31;
2980 int extract_size = INTVAL (operands[4]) & 31;
2981 int insert_start = INTVAL (operands[2]) & 31;
2982 int insert_size = INTVAL (operands[1]) & 31;
2984 /* Align extract field with insert field */
2985 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2986 operands[1] = GEN_INT (insert_start + insert_size - 1);
2987 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2988 }"
2989 [(set_attr "type" "insert_word")])
2991 ;; combine patterns for rlwimi
2992 (define_insn "*insvsi_internal5"
2993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2994 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
2995 (match_operand:SI 1 "mask_operand" "i"))
2996 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2997 (match_operand:SI 2 "const_int_operand" "i"))
2998 (match_operand:SI 5 "mask_operand" "i"))))]
2999 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3000 "*
3001 {
3002 int me = extract_ME(operands[5]);
3003 int mb = extract_MB(operands[5]);
3004 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3005 operands[2] = GEN_INT(mb);
3006 operands[1] = GEN_INT(me);
3007 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3008 }"
3009 [(set_attr "type" "insert_word")])
3011 (define_insn "*insvsi_internal6"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3013 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3014 (match_operand:SI 2 "const_int_operand" "i"))
3015 (match_operand:SI 5 "mask_operand" "i"))
3016 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3017 (match_operand:SI 1 "mask_operand" "i"))))]
3018 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3019 "*
3020 {
3021 int me = extract_ME(operands[5]);
3022 int mb = extract_MB(operands[5]);
3023 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3024 operands[2] = GEN_INT(mb);
3025 operands[1] = GEN_INT(me);
3026 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3027 }"
3028 [(set_attr "type" "insert_word")])
3030 (define_insn "insvdi"
3031 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3032 (match_operand:SI 1 "const_int_operand" "i")
3033 (match_operand:SI 2 "const_int_operand" "i"))
3034 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3035 "TARGET_POWERPC64"
3036 "*
3037 {
3038 int start = INTVAL (operands[2]) & 63;
3039 int size = INTVAL (operands[1]) & 63;
3041 operands[1] = GEN_INT (64 - start - size);
3042 return \"rldimi %0,%3,%H1,%H2\";
3043 }")
3045 (define_insn "*insvdi_internal2"
3046 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3047 (match_operand:SI 1 "const_int_operand" "i")
3048 (match_operand:SI 2 "const_int_operand" "i"))
3049 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3050 (match_operand:SI 4 "const_int_operand" "i")))]
3051 "TARGET_POWERPC64
3052 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3053 "*
3054 {
3055 int shift = INTVAL (operands[4]) & 63;
3056 int start = (INTVAL (operands[2]) & 63) - 32;
3057 int size = INTVAL (operands[1]) & 63;
3059 operands[4] = GEN_INT (64 - shift - start - size);
3060 operands[2] = GEN_INT (start);
3061 operands[1] = GEN_INT (start + size - 1);
3062 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3063 }")
3065 (define_insn "*insvdi_internal3"
3066 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3067 (match_operand:SI 1 "const_int_operand" "i")
3068 (match_operand:SI 2 "const_int_operand" "i"))
3069 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3070 (match_operand:SI 4 "const_int_operand" "i")))]
3071 "TARGET_POWERPC64
3072 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3073 "*
3074 {
3075 int shift = INTVAL (operands[4]) & 63;
3076 int start = (INTVAL (operands[2]) & 63) - 32;
3077 int size = INTVAL (operands[1]) & 63;
3079 operands[4] = GEN_INT (64 - shift - start - size);
3080 operands[2] = GEN_INT (start);
3081 operands[1] = GEN_INT (start + size - 1);
3082 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3083 }")
3085 (define_expand "extzv"
3086 [(set (match_operand 0 "gpc_reg_operand" "")
3087 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3088 (match_operand:SI 2 "const_int_operand" "")
3089 (match_operand:SI 3 "const_int_operand" "")))]
3090 ""
3091 "
3092 {
3093 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3094 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3095 compiler if the address of the structure is taken later. */
3096 if (GET_CODE (operands[0]) == SUBREG
3097 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3098 FAIL;
3100 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3101 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3102 else
3103 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3104 DONE;
3105 }")
3107 (define_insn "extzvsi"
3108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3109 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3110 (match_operand:SI 2 "const_int_operand" "i")
3111 (match_operand:SI 3 "const_int_operand" "i")))]
3112 ""
3113 "*
3114 {
3115 int start = INTVAL (operands[3]) & 31;
3116 int size = INTVAL (operands[2]) & 31;
3118 if (start + size >= 32)
3119 operands[3] = const0_rtx;
3120 else
3121 operands[3] = GEN_INT (start + size);
3122 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3123 }")
3125 (define_insn "*extzvsi_internal1"
3126 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3127 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3128 (match_operand:SI 2 "const_int_operand" "i,i")
3129 (match_operand:SI 3 "const_int_operand" "i,i"))
3130 (const_int 0)))
3131 (clobber (match_scratch:SI 4 "=r,r"))]
3132 ""
3133 "*
3134 {
3135 int start = INTVAL (operands[3]) & 31;
3136 int size = INTVAL (operands[2]) & 31;
3138 /* Force split for non-cc0 compare. */
3139 if (which_alternative == 1)
3140 return \"#\";
3142 /* If the bit-field being tested fits in the upper or lower half of a
3143 word, it is possible to use andiu. or andil. to test it. This is
3144 useful because the condition register set-use delay is smaller for
3145 andi[ul]. than for rlinm. This doesn't work when the starting bit
3146 position is 0 because the LT and GT bits may be set wrong. */
3148 if ((start > 0 && start + size <= 16) || start >= 16)
3149 {
3150 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3151 - (1 << (16 - (start & 15) - size))));
3152 if (start < 16)
3153 return \"{andiu.|andis.} %4,%1,%3\";
3154 else
3155 return \"{andil.|andi.} %4,%1,%3\";
3156 }
3158 if (start + size >= 32)
3159 operands[3] = const0_rtx;
3160 else
3161 operands[3] = GEN_INT (start + size);
3162 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3163 }"
3164 [(set_attr "type" "compare")
3165 (set_attr "length" "4,8")])
3167 (define_split
3168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3169 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3170 (match_operand:SI 2 "const_int_operand" "")
3171 (match_operand:SI 3 "const_int_operand" ""))
3172 (const_int 0)))
3173 (clobber (match_scratch:SI 4 ""))]
3174 "reload_completed"
3175 [(set (match_dup 4)
3176 (zero_extract:SI (match_dup 1) (match_dup 2)
3177 (match_dup 3)))
3178 (set (match_dup 0)
3179 (compare:CC (match_dup 4)
3180 (const_int 0)))]
3181 "")
3183 (define_insn "*extzvsi_internal2"
3184 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3185 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3186 (match_operand:SI 2 "const_int_operand" "i,i")
3187 (match_operand:SI 3 "const_int_operand" "i,i"))
3188 (const_int 0)))
3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3190 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3191 ""
3192 "*
3193 {
3194 int start = INTVAL (operands[3]) & 31;
3195 int size = INTVAL (operands[2]) & 31;
3197 /* Force split for non-cc0 compare. */
3198 if (which_alternative == 1)
3199 return \"#\";
3201 /* Since we are using the output value, we can't ignore any need for
3202 a shift. The bit-field must end at the LSB. */
3203 if (start >= 16 && start + size == 32)
3204 {
3205 operands[3] = GEN_INT ((1 << size) - 1);
3206 return \"{andil.|andi.} %0,%1,%3\";
3207 }
3209 if (start + size >= 32)
3210 operands[3] = const0_rtx;
3211 else
3212 operands[3] = GEN_INT (start + size);
3213 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3214 }"
3215 [(set_attr "type" "compare")
3216 (set_attr "length" "4,8")])
3218 (define_split
3219 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3220 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3221 (match_operand:SI 2 "const_int_operand" "")
3222 (match_operand:SI 3 "const_int_operand" ""))
3223 (const_int 0)))
3224 (set (match_operand:SI 0 "gpc_reg_operand" "")
3225 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3226 "reload_completed"
3227 [(set (match_dup 0)
3228 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3229 (set (match_dup 4)
3230 (compare:CC (match_dup 0)
3231 (const_int 0)))]
3232 "")
3234 (define_insn "extzvdi"
3235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3236 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3237 (match_operand:SI 2 "const_int_operand" "i")
3238 (match_operand:SI 3 "const_int_operand" "i")))]
3239 "TARGET_POWERPC64"
3240 "*
3241 {
3242 int start = INTVAL (operands[3]) & 63;
3243 int size = INTVAL (operands[2]) & 63;
3245 if (start + size >= 64)
3246 operands[3] = const0_rtx;
3247 else
3248 operands[3] = GEN_INT (start + size);
3249 operands[2] = GEN_INT (64 - size);
3250 return \"rldicl %0,%1,%3,%2\";
3251 }")
3253 (define_insn "*extzvdi_internal1"
3254 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3255 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i")
3257 (match_operand:SI 3 "const_int_operand" "i"))
3258 (const_int 0)))
3259 (clobber (match_scratch:DI 4 "=r"))]
3260 "TARGET_64BIT"
3261 "*
3262 {
3263 int start = INTVAL (operands[3]) & 63;
3264 int size = INTVAL (operands[2]) & 63;
3266 if (start + size >= 64)
3267 operands[3] = const0_rtx;
3268 else
3269 operands[3] = GEN_INT (start + size);
3270 operands[2] = GEN_INT (64 - size);
3271 return \"rldicl. %4,%1,%3,%2\";
3272 }"
3273 [(set_attr "type" "compare")])
3275 (define_insn "*extzvdi_internal2"
3276 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3277 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3278 (match_operand:SI 2 "const_int_operand" "i")
3279 (match_operand:SI 3 "const_int_operand" "i"))
3280 (const_int 0)))
3281 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3282 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3283 "TARGET_64BIT"
3284 "*
3285 {
3286 int start = INTVAL (operands[3]) & 63;
3287 int size = INTVAL (operands[2]) & 63;
3289 if (start + size >= 64)
3290 operands[3] = const0_rtx;
3291 else
3292 operands[3] = GEN_INT (start + size);
3293 operands[2] = GEN_INT (64 - size);
3294 return \"rldicl. %0,%1,%3,%2\";
3295 }"
3296 [(set_attr "type" "compare")])
3298 (define_insn "rotlsi3"
3299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3300 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3301 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3302 ""
3303 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3305 (define_insn "*rotlsi3_internal2"
3306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3307 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3309 (const_int 0)))
3310 (clobber (match_scratch:SI 3 "=r,r"))]
3311 ""
3312 "@
3313 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3314 #"
3315 [(set_attr "type" "delayed_compare")
3316 (set_attr "length" "4,8")])
3318 (define_split
3319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3320 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3321 (match_operand:SI 2 "reg_or_cint_operand" ""))
3322 (const_int 0)))
3323 (clobber (match_scratch:SI 3 ""))]
3324 "reload_completed"
3325 [(set (match_dup 3)
3326 (rotate:SI (match_dup 1) (match_dup 2)))
3327 (set (match_dup 0)
3328 (compare:CC (match_dup 3)
3329 (const_int 0)))]
3330 "")
3332 (define_insn "*rotlsi3_internal3"
3333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3334 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3336 (const_int 0)))
3337 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3338 (rotate:SI (match_dup 1) (match_dup 2)))]
3339 ""
3340 "@
3341 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3342 #"
3343 [(set_attr "type" "delayed_compare")
3344 (set_attr "length" "4,8")])
3346 (define_split
3347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3348 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3349 (match_operand:SI 2 "reg_or_cint_operand" ""))
3350 (const_int 0)))
3351 (set (match_operand:SI 0 "gpc_reg_operand" "")
3352 (rotate:SI (match_dup 1) (match_dup 2)))]
3353 "reload_completed"
3354 [(set (match_dup 0)
3355 (rotate:SI (match_dup 1) (match_dup 2)))
3356 (set (match_dup 3)
3357 (compare:CC (match_dup 0)
3358 (const_int 0)))]
3359 "")
3361 (define_insn "*rotlsi3_internal4"
3362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3363 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3364 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3365 (match_operand:SI 3 "mask_operand" "n")))]
3366 ""
3367 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3369 (define_insn "*rotlsi3_internal5"
3370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3371 (compare:CC (and:SI
3372 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3374 (match_operand:SI 3 "mask_operand" "n,n"))
3375 (const_int 0)))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3377 ""
3378 "@
3379 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3380 #"
3381 [(set_attr "type" "delayed_compare")
3382 (set_attr "length" "4,8")])
3384 (define_split
3385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3386 (compare:CC (and:SI
3387 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3388 (match_operand:SI 2 "reg_or_cint_operand" ""))
3389 (match_operand:SI 3 "mask_operand" ""))
3390 (const_int 0)))
3391 (clobber (match_scratch:SI 4 ""))]
3392 "reload_completed"
3393 [(set (match_dup 4)
3394 (and:SI (rotate:SI (match_dup 1)
3395 (match_dup 2))
3396 (match_dup 3)))
3397 (set (match_dup 0)
3398 (compare:CC (match_dup 4)
3399 (const_int 0)))]
3400 "")
3402 (define_insn "*rotlsi3_internal6"
3403 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3404 (compare:CC (and:SI
3405 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3406 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3407 (match_operand:SI 3 "mask_operand" "n,n"))
3408 (const_int 0)))
3409 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3410 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3411 ""
3412 "@
3413 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3414 #"
3415 [(set_attr "type" "delayed_compare")
3416 (set_attr "length" "4,8")])
3418 (define_split
3419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3420 (compare:CC (and:SI
3421 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3422 (match_operand:SI 2 "reg_or_cint_operand" ""))
3423 (match_operand:SI 3 "mask_operand" ""))
3424 (const_int 0)))
3425 (set (match_operand:SI 0 "gpc_reg_operand" "")
3426 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3427 "reload_completed"
3428 [(set (match_dup 0)
3429 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3430 (set (match_dup 4)
3431 (compare:CC (match_dup 0)
3432 (const_int 0)))]
3433 "")
3435 (define_insn "*rotlsi3_internal7"
3436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3437 (zero_extend:SI
3438 (subreg:QI
3439 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3440 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3441 ""
3442 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3444 (define_insn "*rotlsi3_internal8"
3445 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3446 (compare:CC (zero_extend:SI
3447 (subreg:QI
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3449 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3450 (const_int 0)))
3451 (clobber (match_scratch:SI 3 "=r,r"))]
3452 ""
3453 "@
3454 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3455 #"
3456 [(set_attr "type" "delayed_compare")
3457 (set_attr "length" "4,8")])
3459 (define_split
3460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3461 (compare:CC (zero_extend:SI
3462 (subreg:QI
3463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3464 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3465 (const_int 0)))
3466 (clobber (match_scratch:SI 3 ""))]
3467 "reload_completed"
3468 [(set (match_dup 3)
3469 (zero_extend:SI (subreg:QI
3470 (rotate:SI (match_dup 1)
3471 (match_dup 2)) 0)))
3472 (set (match_dup 0)
3473 (compare:CC (match_dup 3)
3474 (const_int 0)))]
3475 "")
3477 (define_insn "*rotlsi3_internal9"
3478 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3479 (compare:CC (zero_extend:SI
3480 (subreg:QI
3481 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3482 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3483 (const_int 0)))
3484 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3485 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3486 ""
3487 "@
3488 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3489 #"
3490 [(set_attr "type" "delayed_compare")
3491 (set_attr "length" "4,8")])
3493 (define_split
3494 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3495 (compare:CC (zero_extend:SI
3496 (subreg:QI
3497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3498 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3499 (const_int 0)))
3500 (set (match_operand:SI 0 "gpc_reg_operand" "")
3501 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3502 "reload_completed"
3503 [(set (match_dup 0)
3504 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3505 (set (match_dup 3)
3506 (compare:CC (match_dup 0)
3507 (const_int 0)))]
3508 "")
3510 (define_insn "*rotlsi3_internal10"
3511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3512 (zero_extend:SI
3513 (subreg:HI
3514 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3515 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3516 ""
3517 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3519 (define_insn "*rotlsi3_internal11"
3520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3521 (compare:CC (zero_extend:SI
3522 (subreg:HI
3523 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3524 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3525 (const_int 0)))
3526 (clobber (match_scratch:SI 3 "=r,r"))]
3527 ""
3528 "@
3529 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3530 #"
3531 [(set_attr "type" "delayed_compare")
3532 (set_attr "length" "4,8")])
3534 (define_split
3535 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3536 (compare:CC (zero_extend:SI
3537 (subreg:HI
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3539 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3540 (const_int 0)))
3541 (clobber (match_scratch:SI 3 ""))]
3542 "reload_completed"
3543 [(set (match_dup 3)
3544 (zero_extend:SI (subreg:HI
3545 (rotate:SI (match_dup 1)
3546 (match_dup 2)) 0)))
3547 (set (match_dup 0)
3548 (compare:CC (match_dup 3)
3549 (const_int 0)))]
3550 "")
3552 (define_insn "*rotlsi3_internal12"
3553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3554 (compare:CC (zero_extend:SI
3555 (subreg:HI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3558 (const_int 0)))
3559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3560 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3561 ""
3562 "@
3563 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3564 #"
3565 [(set_attr "type" "delayed_compare")
3566 (set_attr "length" "4,8")])
3568 (define_split
3569 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3570 (compare:CC (zero_extend:SI
3571 (subreg:HI
3572 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3573 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3574 (const_int 0)))
3575 (set (match_operand:SI 0 "gpc_reg_operand" "")
3576 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3577 "reload_completed"
3578 [(set (match_dup 0)
3579 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3580 (set (match_dup 3)
3581 (compare:CC (match_dup 0)
3582 (const_int 0)))]
3583 "")
3585 ;; Note that we use "sle." instead of "sl." so that we can set
3586 ;; SHIFT_COUNT_TRUNCATED.
3588 (define_expand "ashlsi3"
3589 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3590 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3591 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3592 ""
3593 "
3594 {
3595 if (TARGET_POWER)
3596 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3597 else
3598 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3599 DONE;
3600 }")
3602 (define_insn "ashlsi3_power"
3603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3604 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3605 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3606 (clobber (match_scratch:SI 3 "=q,X"))]
3607 "TARGET_POWER"
3608 "@
3609 sle %0,%1,%2
3610 {sli|slwi} %0,%1,%h2")
3612 (define_insn "ashlsi3_no_power"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3616 "! TARGET_POWER"
3617 "{sl|slw}%I2 %0,%1,%h2")
3619 (define_insn ""
3620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3621 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3622 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3623 (const_int 0)))
3624 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3625 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3626 "TARGET_POWER"
3627 "@
3628 sle. %3,%1,%2
3629 {sli.|slwi.} %3,%1,%h2
3630 #
3631 #"
3632 [(set_attr "type" "delayed_compare")
3633 (set_attr "length" "4,4,8,8")])
3635 (define_split
3636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3637 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3638 (match_operand:SI 2 "reg_or_cint_operand" ""))
3639 (const_int 0)))
3640 (clobber (match_scratch:SI 3 ""))
3641 (clobber (match_scratch:SI 4 ""))]
3642 "TARGET_POWER && reload_completed"
3643 [(parallel [(set (match_dup 3)
3644 (ashift:SI (match_dup 1) (match_dup 2)))
3645 (clobber (match_dup 4))])
3646 (set (match_dup 0)
3647 (compare:CC (match_dup 3)
3648 (const_int 0)))]
3649 "")
3651 (define_insn ""
3652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3653 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3654 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3655 (const_int 0)))
3656 (clobber (match_scratch:SI 3 "=r,r"))]
3657 "! TARGET_POWER && TARGET_32BIT"
3658 "@
3659 {sl|slw}%I2. %3,%1,%h2
3660 #"
3661 [(set_attr "type" "delayed_compare")
3662 (set_attr "length" "4,8")])
3664 (define_split
3665 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3666 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3667 (match_operand:SI 2 "reg_or_cint_operand" ""))
3668 (const_int 0)))
3669 (clobber (match_scratch:SI 3 ""))]
3670 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3671 [(set (match_dup 3)
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (set (match_dup 0)
3674 (compare:CC (match_dup 3)
3675 (const_int 0)))]
3676 "")
3678 (define_insn ""
3679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3680 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3682 (const_int 0)))
3683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3684 (ashift:SI (match_dup 1) (match_dup 2)))
3685 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3686 "TARGET_POWER"
3687 "@
3688 sle. %0,%1,%2
3689 {sli.|slwi.} %0,%1,%h2
3690 #
3691 #"
3692 [(set_attr "type" "delayed_compare")
3693 (set_attr "length" "4,4,8,8")])
3695 (define_split
3696 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3697 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3698 (match_operand:SI 2 "reg_or_cint_operand" ""))
3699 (const_int 0)))
3700 (set (match_operand:SI 0 "gpc_reg_operand" "")
3701 (ashift:SI (match_dup 1) (match_dup 2)))
3702 (clobber (match_scratch:SI 4 ""))]
3703 "TARGET_POWER && reload_completed"
3704 [(parallel [(set (match_dup 0)
3705 (ashift:SI (match_dup 1) (match_dup 2)))
3706 (clobber (match_dup 4))])
3707 (set (match_dup 3)
3708 (compare:CC (match_dup 0)
3709 (const_int 0)))]
3710 "")
3712 (define_insn ""
3713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3714 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3715 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3716 (const_int 0)))
3717 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3718 (ashift:SI (match_dup 1) (match_dup 2)))]
3719 "! TARGET_POWER && TARGET_32BIT"
3720 "@
3721 {sl|slw}%I2. %0,%1,%h2
3722 #"
3723 [(set_attr "type" "delayed_compare")
3724 (set_attr "length" "4,8")])
3726 (define_split
3727 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3728 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3729 (match_operand:SI 2 "reg_or_cint_operand" ""))
3730 (const_int 0)))
3731 (set (match_operand:SI 0 "gpc_reg_operand" "")
3732 (ashift:SI (match_dup 1) (match_dup 2)))]
3733 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3734 [(set (match_dup 0)
3735 (ashift:SI (match_dup 1) (match_dup 2)))
3736 (set (match_dup 3)
3737 (compare:CC (match_dup 0)
3738 (const_int 0)))]
3739 "")
3741 (define_insn ""
3742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3743 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3744 (match_operand:SI 2 "const_int_operand" "i"))
3745 (match_operand:SI 3 "mask_operand" "n")))]
3746 "includes_lshift_p (operands[2], operands[3])"
3747 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3749 (define_insn ""
3750 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3751 (compare:CC
3752 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3753 (match_operand:SI 2 "const_int_operand" "i,i"))
3754 (match_operand:SI 3 "mask_operand" "n,n"))
3755 (const_int 0)))
3756 (clobber (match_scratch:SI 4 "=r,r"))]
3757 "includes_lshift_p (operands[2], operands[3])"
3758 "@
3759 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3760 #"
3761 [(set_attr "type" "delayed_compare")
3762 (set_attr "length" "4,8")])
3764 (define_split
3765 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3766 (compare:CC
3767 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3768 (match_operand:SI 2 "const_int_operand" ""))
3769 (match_operand:SI 3 "mask_operand" ""))
3770 (const_int 0)))
3771 (clobber (match_scratch:SI 4 ""))]
3772 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3773 [(set (match_dup 4)
3774 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3775 (match_dup 3)))
3776 (set (match_dup 0)
3777 (compare:CC (match_dup 4)
3778 (const_int 0)))]
3779 "")
3781 (define_insn ""
3782 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3783 (compare:CC
3784 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3785 (match_operand:SI 2 "const_int_operand" "i,i"))
3786 (match_operand:SI 3 "mask_operand" "n,n"))
3787 (const_int 0)))
3788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3789 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3790 "includes_lshift_p (operands[2], operands[3])"
3791 "@
3792 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3793 #"
3794 [(set_attr "type" "delayed_compare")
3795 (set_attr "length" "4,8")])
3797 (define_split
3798 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3799 (compare:CC
3800 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3801 (match_operand:SI 2 "const_int_operand" ""))
3802 (match_operand:SI 3 "mask_operand" ""))
3803 (const_int 0)))
3804 (set (match_operand:SI 0 "gpc_reg_operand" "")
3805 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3806 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3807 [(set (match_dup 0)
3808 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3809 (set (match_dup 4)
3810 (compare:CC (match_dup 0)
3811 (const_int 0)))]
3812 "")
3814 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3815 ;; "sli x,x,0".
3816 (define_expand "lshrsi3"
3817 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3818 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3819 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3820 ""
3821 "
3822 {
3823 if (TARGET_POWER)
3824 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3825 else
3826 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3827 DONE;
3828 }")
3830 (define_insn "lshrsi3_power"
3831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3832 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3833 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3834 (clobber (match_scratch:SI 3 "=q,X,X"))]
3835 "TARGET_POWER"
3836 "@
3837 sre %0,%1,%2
3838 mr %0,%1
3839 {s%A2i|s%A2wi} %0,%1,%h2")
3841 (define_insn "lshrsi3_no_power"
3842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3843 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3845 "! TARGET_POWER"
3846 "@
3847 mr %0,%1
3848 {sr|srw}%I2 %0,%1,%h2")
3850 (define_insn ""
3851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3852 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3853 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3854 (const_int 0)))
3855 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3856 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3857 "TARGET_POWER"
3858 "@
3859 sre. %3,%1,%2
3860 mr. %1,%1
3861 {s%A2i.|s%A2wi.} %3,%1,%h2
3862 #
3863 #
3864 #"
3865 [(set_attr "type" "delayed_compare")
3866 (set_attr "length" "4,4,4,8,8,8")])
3868 (define_split
3869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3870 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3871 (match_operand:SI 2 "reg_or_cint_operand" ""))
3872 (const_int 0)))
3873 (clobber (match_scratch:SI 3 ""))
3874 (clobber (match_scratch:SI 4 ""))]
3875 "TARGET_POWER && reload_completed"
3876 [(parallel [(set (match_dup 3)
3877 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3878 (clobber (match_dup 4))])
3879 (set (match_dup 0)
3880 (compare:CC (match_dup 3)
3881 (const_int 0)))]
3882 "")
3884 (define_insn ""
3885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3886 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3887 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3888 (const_int 0)))
3889 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3890 "! TARGET_POWER && TARGET_32BIT"
3891 "@
3892 mr. %1,%1
3893 {sr|srw}%I2. %3,%1,%h2
3894 #
3895 #"
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,8,8")])
3899 (define_split
3900 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3903 (const_int 0)))
3904 (clobber (match_scratch:SI 3 ""))]
3905 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3906 [(set (match_dup 3)
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3908 (set (match_dup 0)
3909 (compare:CC (match_dup 3)
3910 (const_int 0)))]
3911 "")
3913 (define_insn ""
3914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3915 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3919 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3920 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3921 "TARGET_POWER"
3922 "@
3923 sre. %0,%1,%2
3924 mr. %0,%1
3925 {s%A2i.|s%A2wi.} %0,%1,%h2
3926 #
3927 #
3928 #"
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,4,4,8,8,8")])
3932 (define_split
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3935 (match_operand:SI 2 "reg_or_cint_operand" ""))
3936 (const_int 0)))
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3939 (clobber (match_scratch:SI 4 ""))]
3940 "TARGET_POWER && reload_completed"
3941 [(parallel [(set (match_dup 0)
3942 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3943 (clobber (match_dup 4))])
3944 (set (match_dup 3)
3945 (compare:CC (match_dup 0)
3946 (const_int 0)))]
3947 "")
3949 (define_insn ""
3950 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3951 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3952 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3953 (const_int 0)))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3955 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3956 "! TARGET_POWER && TARGET_32BIT"
3957 "@
3958 mr. %0,%1
3959 {sr|srw}%I2. %0,%1,%h2
3960 #
3961 #"
3962 [(set_attr "type" "delayed_compare")
3963 (set_attr "length" "4,4,8,8")])
3965 (define_split
3966 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3967 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3968 (match_operand:SI 2 "reg_or_cint_operand" ""))
3969 (const_int 0)))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3972 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3973 [(set (match_dup 0)
3974 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3975 (set (match_dup 3)
3976 (compare:CC (match_dup 0)
3977 (const_int 0)))]
3978 "")
3980 (define_insn ""
3981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3982 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3983 (match_operand:SI 2 "const_int_operand" "i"))
3984 (match_operand:SI 3 "mask_operand" "n")))]
3985 "includes_rshift_p (operands[2], operands[3])"
3986 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3988 (define_insn ""
3989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3990 (compare:CC
3991 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3992 (match_operand:SI 2 "const_int_operand" "i,i"))
3993 (match_operand:SI 3 "mask_operand" "n,n"))
3994 (const_int 0)))
3995 (clobber (match_scratch:SI 4 "=r,r"))]
3996 "includes_rshift_p (operands[2], operands[3])"
3997 "@
3998 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3999 #"
4000 [(set_attr "type" "delayed_compare")
4001 (set_attr "length" "4,8")])
4003 (define_split
4004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4005 (compare:CC
4006 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "const_int_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4009 (const_int 0)))
4010 (clobber (match_scratch:SI 4 ""))]
4011 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4012 [(set (match_dup 4)
4013 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4014 (match_dup 3)))
4015 (set (match_dup 0)
4016 (compare:CC (match_dup 4)
4017 (const_int 0)))]
4018 "")
4020 (define_insn ""
4021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4022 (compare:CC
4023 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4024 (match_operand:SI 2 "const_int_operand" "i,i"))
4025 (match_operand:SI 3 "mask_operand" "n,n"))
4026 (const_int 0)))
4027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4028 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4029 "includes_rshift_p (operands[2], operands[3])"
4030 "@
4031 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4032 #"
4033 [(set_attr "type" "delayed_compare")
4034 (set_attr "length" "4,8")])
4036 (define_split
4037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4038 (compare:CC
4039 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "const_int_operand" ""))
4041 (match_operand:SI 3 "mask_operand" ""))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4045 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4046 [(set (match_dup 0)
4047 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4048 (set (match_dup 4)
4049 (compare:CC (match_dup 0)
4050 (const_int 0)))]
4051 "")
4053 (define_insn ""
4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4055 (zero_extend:SI
4056 (subreg:QI
4057 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4058 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4059 "includes_rshift_p (operands[2], GEN_INT (255))"
4060 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4062 (define_insn ""
4063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4064 (compare:CC
4065 (zero_extend:SI
4066 (subreg:QI
4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4069 (const_int 0)))
4070 (clobber (match_scratch:SI 3 "=r,r"))]
4071 "includes_rshift_p (operands[2], GEN_INT (255))"
4072 "@
4073 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4074 #"
4075 [(set_attr "type" "delayed_compare")
4076 (set_attr "length" "4,8")])
4078 (define_split
4079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4080 (compare:CC
4081 (zero_extend:SI
4082 (subreg:QI
4083 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "const_int_operand" "")) 0))
4085 (const_int 0)))
4086 (clobber (match_scratch:SI 3 ""))]
4087 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4088 [(set (match_dup 3)
4089 (zero_extend:SI (subreg:QI
4090 (lshiftrt:SI (match_dup 1)
4091 (match_dup 2)) 0)))
4092 (set (match_dup 0)
4093 (compare:CC (match_dup 3)
4094 (const_int 0)))]
4095 "")
4097 (define_insn ""
4098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4099 (compare:CC
4100 (zero_extend:SI
4101 (subreg:QI
4102 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4104 (const_int 0)))
4105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4106 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4107 "includes_rshift_p (operands[2], GEN_INT (255))"
4108 "@
4109 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4110 #"
4111 [(set_attr "type" "delayed_compare")
4112 (set_attr "length" "4,8")])
4114 (define_split
4115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4116 (compare:CC
4117 (zero_extend:SI
4118 (subreg:QI
4119 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "const_int_operand" "")) 0))
4121 (const_int 0)))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "")
4123 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4124 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4125 [(set (match_dup 0)
4126 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4127 (set (match_dup 3)
4128 (compare:CC (match_dup 0)
4129 (const_int 0)))]
4130 "")
4132 (define_insn ""
4133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4134 (zero_extend:SI
4135 (subreg:HI
4136 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4137 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4138 "includes_rshift_p (operands[2], GEN_INT (65535))"
4139 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4141 (define_insn ""
4142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4143 (compare:CC
4144 (zero_extend:SI
4145 (subreg:HI
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4148 (const_int 0)))
4149 (clobber (match_scratch:SI 3 "=r,r"))]
4150 "includes_rshift_p (operands[2], GEN_INT (65535))"
4151 "@
4152 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4153 #"
4154 [(set_attr "type" "delayed_compare")
4155 (set_attr "length" "4,8")])
4157 (define_split
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4159 (compare:CC
4160 (zero_extend:SI
4161 (subreg:HI
4162 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4163 (match_operand:SI 2 "const_int_operand" "")) 0))
4164 (const_int 0)))
4165 (clobber (match_scratch:SI 3 ""))]
4166 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4167 [(set (match_dup 3)
4168 (zero_extend:SI (subreg:HI
4169 (lshiftrt:SI (match_dup 1)
4170 (match_dup 2)) 0)))
4171 (set (match_dup 0)
4172 (compare:CC (match_dup 3)
4173 (const_int 0)))]
4174 "")
4176 (define_insn ""
4177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4178 (compare:CC
4179 (zero_extend:SI
4180 (subreg:HI
4181 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4182 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4183 (const_int 0)))
4184 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4185 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4186 "includes_rshift_p (operands[2], GEN_INT (65535))"
4187 "@
4188 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4189 #"
4190 [(set_attr "type" "delayed_compare")
4191 (set_attr "length" "4,8")])
4193 (define_split
4194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4195 (compare:CC
4196 (zero_extend:SI
4197 (subreg:HI
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4199 (match_operand:SI 2 "const_int_operand" "")) 0))
4200 (const_int 0)))
4201 (set (match_operand:SI 0 "gpc_reg_operand" "")
4202 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4203 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4204 [(set (match_dup 0)
4205 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4206 (set (match_dup 3)
4207 (compare:CC (match_dup 0)
4208 (const_int 0)))]
4209 "")
4211 (define_insn ""
4212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4213 (const_int 1)
4214 (match_operand:SI 1 "gpc_reg_operand" "r"))
4215 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4216 (const_int 31)))]
4217 "TARGET_POWER"
4218 "rrib %0,%1,%2")
4220 (define_insn ""
4221 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4222 (const_int 1)
4223 (match_operand:SI 1 "gpc_reg_operand" "r"))
4224 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4225 (const_int 31)))]
4226 "TARGET_POWER"
4227 "rrib %0,%1,%2")
4229 (define_insn ""
4230 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4231 (const_int 1)
4232 (match_operand:SI 1 "gpc_reg_operand" "r"))
4233 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4234 (const_int 1)
4235 (const_int 0)))]
4236 "TARGET_POWER"
4237 "rrib %0,%1,%2")
4239 (define_expand "ashrsi3"
4240 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4241 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4242 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4243 ""
4244 "
4245 {
4246 if (TARGET_POWER)
4247 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4248 else
4249 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4250 DONE;
4251 }")
4253 (define_insn "ashrsi3_power"
4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4255 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4256 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4257 (clobber (match_scratch:SI 3 "=q,X"))]
4258 "TARGET_POWER"
4259 "@
4260 srea %0,%1,%2
4261 {srai|srawi} %0,%1,%h2")
4263 (define_insn "ashrsi3_no_power"
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4267 "! TARGET_POWER"
4268 "{sra|sraw}%I2 %0,%1,%h2")
4270 (define_insn ""
4271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4272 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4273 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4274 (const_int 0)))
4275 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4276 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4277 "TARGET_POWER"
4278 "@
4279 srea. %3,%1,%2
4280 {srai.|srawi.} %3,%1,%h2
4281 #
4282 #"
4283 [(set_attr "type" "delayed_compare")
4284 (set_attr "length" "4,4,8,8")])
4286 (define_split
4287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4288 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4289 (match_operand:SI 2 "reg_or_cint_operand" ""))
4290 (const_int 0)))
4291 (clobber (match_scratch:SI 3 ""))
4292 (clobber (match_scratch:SI 4 ""))]
4293 "TARGET_POWER && reload_completed"
4294 [(parallel [(set (match_dup 3)
4295 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4296 (clobber (match_dup 4))])
4297 (set (match_dup 0)
4298 (compare:CC (match_dup 3)
4299 (const_int 0)))]
4300 "")
4302 (define_insn ""
4303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4304 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4305 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4306 (const_int 0)))
4307 (clobber (match_scratch:SI 3 "=r,r"))]
4308 "! TARGET_POWER"
4309 "@
4310 {sra|sraw}%I2. %3,%1,%h2
4311 #"
4312 [(set_attr "type" "delayed_compare")
4313 (set_attr "length" "4,8")])
4315 (define_split
4316 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4317 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4318 (match_operand:SI 2 "reg_or_cint_operand" ""))
4319 (const_int 0)))
4320 (clobber (match_scratch:SI 3 ""))]
4321 "! TARGET_POWER && reload_completed"
4322 [(set (match_dup 3)
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (set (match_dup 0)
4325 (compare:CC (match_dup 3)
4326 (const_int 0)))]
4327 "")
4329 (define_insn ""
4330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4331 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4332 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4333 (const_int 0)))
4334 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4335 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4336 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4337 "TARGET_POWER"
4338 "@
4339 srea. %0,%1,%2
4340 {srai.|srawi.} %0,%1,%h2
4341 #
4342 #"
4343 [(set_attr "type" "delayed_compare")
4344 (set_attr "length" "4,4,8,8")])
4346 (define_split
4347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4348 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4349 (match_operand:SI 2 "reg_or_cint_operand" ""))
4350 (const_int 0)))
4351 (set (match_operand:SI 0 "gpc_reg_operand" "")
4352 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4353 (clobber (match_scratch:SI 4 ""))]
4354 "TARGET_POWER && reload_completed"
4355 [(parallel [(set (match_dup 0)
4356 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4357 (clobber (match_dup 4))])
4358 (set (match_dup 3)
4359 (compare:CC (match_dup 0)
4360 (const_int 0)))]
4361 "")
4363 (define_insn ""
4364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4367 (const_int 0)))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4369 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4370 "! TARGET_POWER"
4371 "@
4372 {sra|sraw}%I2. %0,%1,%h2
4373 #"
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,8")])
4376 \f
4377 (define_split
4378 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4381 (const_int 0)))
4382 (set (match_operand:SI 0 "gpc_reg_operand" "")
4383 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4384 "! TARGET_POWER && reload_completed"
4385 [(set (match_dup 0)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 3)
4388 (compare:CC (match_dup 0)
4389 (const_int 0)))]
4390 "")
4392 ;; Floating-point insns, excluding normal data motion.
4393 ;;
4394 ;; PowerPC has a full set of single-precision floating point instructions.
4395 ;;
4396 ;; For the POWER architecture, we pretend that we have both SFmode and
4397 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4398 ;; The only conversions we will do will be when storing to memory. In that
4399 ;; case, we will use the "frsp" instruction before storing.
4400 ;;
4401 ;; Note that when we store into a single-precision memory location, we need to
4402 ;; use the frsp insn first. If the register being stored isn't dead, we
4403 ;; need a scratch register for the frsp. But this is difficult when the store
4404 ;; is done by reload. It is not incorrect to do the frsp on the register in
4405 ;; this case, we just lose precision that we would have otherwise gotten but
4406 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4408 (define_expand "extendsfdf2"
4409 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4410 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4411 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4412 "")
4414 (define_insn_and_split "*extendsfdf2_fpr"
4415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4416 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4417 "TARGET_HARD_FLOAT && TARGET_FPRS"
4418 "@
4419 #
4420 fmr %0,%1
4421 lfs%U1%X1 %0,%1"
4422 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4423 [(const_int 0)]
4424 {
4425 emit_note (NOTE_INSN_DELETED);
4426 DONE;
4427 }
4428 [(set_attr "type" "fp,fp,fpload")])
4430 (define_expand "truncdfsf2"
4431 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4432 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4433 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4434 "")
4436 (define_insn "*truncdfsf2_fpr"
4437 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4438 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4439 "TARGET_HARD_FLOAT && TARGET_FPRS"
4440 "frsp %0,%1"
4441 [(set_attr "type" "fp")])
4443 (define_insn "aux_truncdfsf2"
4444 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4445 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4446 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4447 "frsp %0,%1"
4448 [(set_attr "type" "fp")])
4450 (define_expand "negsf2"
4451 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4452 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4453 "TARGET_HARD_FLOAT"
4454 "")
4456 (define_insn "*negsf2"
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4458 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4459 "TARGET_HARD_FLOAT && TARGET_FPRS"
4460 "fneg %0,%1"
4461 [(set_attr "type" "fp")])
4463 (define_expand "abssf2"
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4465 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4466 "TARGET_HARD_FLOAT"
4467 "")
4469 (define_insn "*abssf2"
4470 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4471 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4472 "TARGET_HARD_FLOAT && TARGET_FPRS"
4473 "fabs %0,%1"
4474 [(set_attr "type" "fp")])
4476 (define_insn ""
4477 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4478 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4479 "TARGET_HARD_FLOAT && TARGET_FPRS"
4480 "fnabs %0,%1"
4481 [(set_attr "type" "fp")])
4483 (define_expand "addsf3"
4484 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4485 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4486 (match_operand:SF 2 "gpc_reg_operand" "")))]
4487 "TARGET_HARD_FLOAT"
4488 "")
4490 (define_insn ""
4491 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4492 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4493 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4494 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4495 "fadds %0,%1,%2"
4496 [(set_attr "type" "fp")])
4498 (define_insn ""
4499 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4500 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4501 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4502 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4503 "{fa|fadd} %0,%1,%2"
4504 [(set_attr "type" "fp")])
4506 (define_expand "subsf3"
4507 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4508 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4509 (match_operand:SF 2 "gpc_reg_operand" "")))]
4510 "TARGET_HARD_FLOAT"
4511 "")
4513 (define_insn ""
4514 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4515 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4516 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4517 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4518 "fsubs %0,%1,%2"
4519 [(set_attr "type" "fp")])
4521 (define_insn ""
4522 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4523 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4524 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4525 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4526 "{fs|fsub} %0,%1,%2"
4527 [(set_attr "type" "fp")])
4529 (define_expand "mulsf3"
4530 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4531 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4532 (match_operand:SF 2 "gpc_reg_operand" "")))]
4533 "TARGET_HARD_FLOAT"
4534 "")
4536 (define_insn ""
4537 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4538 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4539 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4540 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4541 "fmuls %0,%1,%2"
4542 [(set_attr "type" "fp")])
4544 (define_insn ""
4545 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4546 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4547 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4548 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4549 "{fm|fmul} %0,%1,%2"
4550 [(set_attr "type" "dmul")])
4552 (define_expand "divsf3"
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4554 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4555 (match_operand:SF 2 "gpc_reg_operand" "")))]
4556 "TARGET_HARD_FLOAT"
4557 "")
4559 (define_insn ""
4560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4561 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4562 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4563 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4564 "fdivs %0,%1,%2"
4565 [(set_attr "type" "sdiv")])
4567 (define_insn ""
4568 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4569 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4570 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4571 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4572 "{fd|fdiv} %0,%1,%2"
4573 [(set_attr "type" "ddiv")])
4575 (define_insn ""
4576 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4577 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4578 (match_operand:SF 2 "gpc_reg_operand" "f"))
4579 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4580 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4581 "fmadds %0,%1,%2,%3"
4582 [(set_attr "type" "fp")])
4584 (define_insn ""
4585 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4586 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4587 (match_operand:SF 2 "gpc_reg_operand" "f"))
4588 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4589 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4590 "{fma|fmadd} %0,%1,%2,%3"
4591 [(set_attr "type" "dmul")])
4593 (define_insn ""
4594 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4595 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4596 (match_operand:SF 2 "gpc_reg_operand" "f"))
4597 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4598 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4599 "fmsubs %0,%1,%2,%3"
4600 [(set_attr "type" "fp")])
4602 (define_insn ""
4603 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4604 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4605 (match_operand:SF 2 "gpc_reg_operand" "f"))
4606 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4607 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4608 "{fms|fmsub} %0,%1,%2,%3"
4609 [(set_attr "type" "dmul")])
4611 (define_insn ""
4612 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4613 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4614 (match_operand:SF 2 "gpc_reg_operand" "f"))
4615 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4616 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4617 && HONOR_SIGNED_ZEROS (SFmode)"
4618 "fnmadds %0,%1,%2,%3"
4619 [(set_attr "type" "fp")])
4621 (define_insn ""
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4623 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4624 (match_operand:SF 2 "gpc_reg_operand" "f"))
4625 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4626 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4627 && ! HONOR_SIGNED_ZEROS (SFmode)"
4628 "fnmadds %0,%1,%2,%3"
4629 [(set_attr "type" "fp")])
4631 (define_insn ""
4632 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4633 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4634 (match_operand:SF 2 "gpc_reg_operand" "f"))
4635 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4636 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4637 "{fnma|fnmadd} %0,%1,%2,%3"
4638 [(set_attr "type" "dmul")])
4640 (define_insn ""
4641 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4642 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4643 (match_operand:SF 2 "gpc_reg_operand" "f"))
4644 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4645 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4646 && ! HONOR_SIGNED_ZEROS (SFmode)"
4647 "{fnma|fnmadd} %0,%1,%2,%3"
4648 [(set_attr "type" "dmul")])
4650 (define_insn ""
4651 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4652 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4653 (match_operand:SF 2 "gpc_reg_operand" "f"))
4654 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4655 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4656 && HONOR_SIGNED_ZEROS (SFmode)"
4657 "fnmsubs %0,%1,%2,%3"
4658 [(set_attr "type" "fp")])
4660 (define_insn ""
4661 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4662 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4663 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4664 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4665 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4666 && ! HONOR_SIGNED_ZEROS (SFmode)"
4667 "fnmsubs %0,%1,%2,%3"
4668 [(set_attr "type" "fp")])
4670 (define_insn ""
4671 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4672 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4673 (match_operand:SF 2 "gpc_reg_operand" "f"))
4674 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4675 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4676 "{fnms|fnmsub} %0,%1,%2,%3"
4677 [(set_attr "type" "dmul")])
4679 (define_insn ""
4680 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4681 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4682 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4683 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4684 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4685 && ! HONOR_SIGNED_ZEROS (SFmode)"
4686 "{fnms|fnmsub} %0,%1,%2,%3"
4687 [(set_attr "type" "fp")])
4689 (define_expand "sqrtsf2"
4690 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4691 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4692 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4693 "")
4695 (define_insn ""
4696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4697 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4698 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4699 "fsqrts %0,%1"
4700 [(set_attr "type" "ssqrt")])
4702 (define_insn ""
4703 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4704 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4705 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4706 "fsqrt %0,%1"
4707 [(set_attr "type" "dsqrt")])
4709 (define_expand "copysignsf3"
4710 [(set (match_dup 3)
4711 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4712 (set (match_dup 4)
4713 (neg:SF (abs:SF (match_dup 1))))
4714 (set (match_operand:SF 0 "gpc_reg_operand" "")
4715 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4716 (match_dup 5))
4717 (match_dup 3)
4718 (match_dup 4)))]
4719 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4720 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4721 {
4722 operands[3] = gen_reg_rtx (SFmode);
4723 operands[4] = gen_reg_rtx (SFmode);
4724 operands[5] = CONST0_RTX (SFmode);
4725 })
4727 (define_expand "copysigndf3"
4728 [(set (match_dup 3)
4729 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4730 (set (match_dup 4)
4731 (neg:DF (abs:DF (match_dup 1))))
4732 (set (match_operand:DF 0 "gpc_reg_operand" "")
4733 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4734 (match_dup 5))
4735 (match_dup 3)
4736 (match_dup 4)))]
4737 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4738 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4739 {
4740 operands[3] = gen_reg_rtx (DFmode);
4741 operands[4] = gen_reg_rtx (DFmode);
4742 operands[5] = CONST0_RTX (DFmode);
4743 })
4745 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4746 ;; fsel instruction and some auxiliary computations. Then we just have a
4747 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4748 ;; combine.
4749 (define_expand "smaxsf3"
4750 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4751 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4752 (match_operand:SF 2 "gpc_reg_operand" ""))
4753 (match_dup 1)
4754 (match_dup 2)))]
4755 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4756 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4758 (define_expand "sminsf3"
4759 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4760 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4761 (match_operand:SF 2 "gpc_reg_operand" ""))
4762 (match_dup 2)
4763 (match_dup 1)))]
4764 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4765 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4767 (define_split
4768 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4769 (match_operator:SF 3 "min_max_operator"
4770 [(match_operand:SF 1 "gpc_reg_operand" "")
4771 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4772 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4773 [(const_int 0)]
4774 "
4775 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4776 operands[1], operands[2]);
4777 DONE;
4778 }")
4780 (define_expand "movsicc"
4781 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4782 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4783 (match_operand:SI 2 "gpc_reg_operand" "")
4784 (match_operand:SI 3 "gpc_reg_operand" "")))]
4785 "TARGET_ISEL"
4786 "
4787 {
4788 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4789 DONE;
4790 else
4791 FAIL;
4792 }")
4794 ;; We use the BASE_REGS for the isel input operands because, if rA is
4795 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4796 ;; because we may switch the operands and rB may end up being rA.
4797 ;;
4798 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4799 ;; leave out the mode in operand 4 and use one pattern, but reload can
4800 ;; change the mode underneath our feet and then gets confused trying
4801 ;; to reload the value.
4802 (define_insn "isel_signed"
4803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4804 (if_then_else:SI
4805 (match_operator 1 "comparison_operator"
4806 [(match_operand:CC 4 "cc_reg_operand" "y")
4807 (const_int 0)])
4808 (match_operand:SI 2 "gpc_reg_operand" "b")
4809 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4810 "TARGET_ISEL"
4811 "*
4812 { return output_isel (operands); }"
4813 [(set_attr "length" "4")])
4815 (define_insn "isel_unsigned"
4816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4817 (if_then_else:SI
4818 (match_operator 1 "comparison_operator"
4819 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4820 (const_int 0)])
4821 (match_operand:SI 2 "gpc_reg_operand" "b")
4822 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4823 "TARGET_ISEL"
4824 "*
4825 { return output_isel (operands); }"
4826 [(set_attr "length" "4")])
4828 (define_expand "movsfcc"
4829 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4830 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4831 (match_operand:SF 2 "gpc_reg_operand" "")
4832 (match_operand:SF 3 "gpc_reg_operand" "")))]
4833 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4834 "
4835 {
4836 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4837 DONE;
4838 else
4839 FAIL;
4840 }")
4842 (define_insn "*fselsfsf4"
4843 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4844 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4845 (match_operand:SF 4 "zero_fp_constant" "F"))
4846 (match_operand:SF 2 "gpc_reg_operand" "f")
4847 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4848 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4849 "fsel %0,%1,%2,%3"
4850 [(set_attr "type" "fp")])
4852 (define_insn "*fseldfsf4"
4853 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4854 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4855 (match_operand:DF 4 "zero_fp_constant" "F"))
4856 (match_operand:SF 2 "gpc_reg_operand" "f")
4857 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4858 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4859 "fsel %0,%1,%2,%3"
4860 [(set_attr "type" "fp")])
4862 (define_expand "negdf2"
4863 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4864 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4865 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4866 "")
4868 (define_insn "*negdf2_fpr"
4869 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4870 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4871 "TARGET_HARD_FLOAT && TARGET_FPRS"
4872 "fneg %0,%1"
4873 [(set_attr "type" "fp")])
4875 (define_expand "absdf2"
4876 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4877 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4878 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4879 "")
4881 (define_insn "*absdf2_fpr"
4882 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4883 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS"
4885 "fabs %0,%1"
4886 [(set_attr "type" "fp")])
4888 (define_insn "*nabsdf2_fpr"
4889 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4890 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4891 "TARGET_HARD_FLOAT && TARGET_FPRS"
4892 "fnabs %0,%1"
4893 [(set_attr "type" "fp")])
4895 (define_expand "adddf3"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4897 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4898 (match_operand:DF 2 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4900 "")
4902 (define_insn "*adddf3_fpr"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4904 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4905 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4906 "TARGET_HARD_FLOAT && TARGET_FPRS"
4907 "{fa|fadd} %0,%1,%2"
4908 [(set_attr "type" "fp")])
4910 (define_expand "subdf3"
4911 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4912 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4913 (match_operand:DF 2 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4915 "")
4917 (define_insn "*subdf3_fpr"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4919 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4920 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4921 "TARGET_HARD_FLOAT && TARGET_FPRS"
4922 "{fs|fsub} %0,%1,%2"
4923 [(set_attr "type" "fp")])
4925 (define_expand "muldf3"
4926 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4927 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4928 (match_operand:DF 2 "gpc_reg_operand" "")))]
4929 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4930 "")
4932 (define_insn "*muldf3_fpr"
4933 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4934 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4935 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4936 "TARGET_HARD_FLOAT && TARGET_FPRS"
4937 "{fm|fmul} %0,%1,%2"
4938 [(set_attr "type" "dmul")])
4940 (define_expand "divdf3"
4941 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4942 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4943 (match_operand:DF 2 "gpc_reg_operand" "")))]
4944 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4945 "")
4947 (define_insn "*divdf3_fpr"
4948 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4949 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4950 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4951 "TARGET_HARD_FLOAT && TARGET_FPRS"
4952 "{fd|fdiv} %0,%1,%2"
4953 [(set_attr "type" "ddiv")])
4955 (define_insn ""
4956 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4957 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4958 (match_operand:DF 2 "gpc_reg_operand" "f"))
4959 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4960 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4961 "{fma|fmadd} %0,%1,%2,%3"
4962 [(set_attr "type" "dmul")])
4964 (define_insn ""
4965 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4966 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4967 (match_operand:DF 2 "gpc_reg_operand" "f"))
4968 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4970 "{fms|fmsub} %0,%1,%2,%3"
4971 [(set_attr "type" "dmul")])
4973 (define_insn ""
4974 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4975 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4976 (match_operand:DF 2 "gpc_reg_operand" "f"))
4977 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4979 && HONOR_SIGNED_ZEROS (DFmode)"
4980 "{fnma|fnmadd} %0,%1,%2,%3"
4981 [(set_attr "type" "dmul")])
4983 (define_insn ""
4984 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4985 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4986 (match_operand:DF 2 "gpc_reg_operand" "f"))
4987 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4988 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4989 && ! HONOR_SIGNED_ZEROS (DFmode)"
4990 "{fnma|fnmadd} %0,%1,%2,%3"
4991 [(set_attr "type" "dmul")])
4993 (define_insn ""
4994 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4995 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4996 (match_operand:DF 2 "gpc_reg_operand" "f"))
4997 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4998 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4999 && HONOR_SIGNED_ZEROS (DFmode)"
5000 "{fnms|fnmsub} %0,%1,%2,%3"
5001 [(set_attr "type" "dmul")])
5003 (define_insn ""
5004 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5005 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5006 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5007 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5008 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5009 && ! HONOR_SIGNED_ZEROS (DFmode)"
5010 "{fnms|fnmsub} %0,%1,%2,%3"
5011 [(set_attr "type" "dmul")])
5013 (define_insn "sqrtdf2"
5014 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5015 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5016 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5017 "fsqrt %0,%1"
5018 [(set_attr "type" "dsqrt")])
5020 ;; The conditional move instructions allow us to perform max and min
5021 ;; operations even when
5023 (define_expand "smaxdf3"
5024 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5025 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5026 (match_operand:DF 2 "gpc_reg_operand" ""))
5027 (match_dup 1)
5028 (match_dup 2)))]
5029 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5030 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5032 (define_expand "smindf3"
5033 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5034 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5035 (match_operand:DF 2 "gpc_reg_operand" ""))
5036 (match_dup 2)
5037 (match_dup 1)))]
5038 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5039 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5041 (define_split
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5043 (match_operator:DF 3 "min_max_operator"
5044 [(match_operand:DF 1 "gpc_reg_operand" "")
5045 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5046 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5047 [(const_int 0)]
5048 "
5049 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5050 operands[1], operands[2]);
5051 DONE;
5052 }")
5054 (define_expand "movdfcc"
5055 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5056 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5057 (match_operand:DF 2 "gpc_reg_operand" "")
5058 (match_operand:DF 3 "gpc_reg_operand" "")))]
5059 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5060 "
5061 {
5062 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5063 DONE;
5064 else
5065 FAIL;
5066 }")
5068 (define_insn "*fseldfdf4"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5070 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5071 (match_operand:DF 4 "zero_fp_constant" "F"))
5072 (match_operand:DF 2 "gpc_reg_operand" "f")
5073 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5074 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5075 "fsel %0,%1,%2,%3"
5076 [(set_attr "type" "fp")])
5078 (define_insn "*fselsfdf4"
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5080 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5081 (match_operand:SF 4 "zero_fp_constant" "F"))
5082 (match_operand:DF 2 "gpc_reg_operand" "f")
5083 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5084 "TARGET_PPC_GFXOPT"
5085 "fsel %0,%1,%2,%3"
5086 [(set_attr "type" "fp")])
5087 \f
5088 ;; Conversions to and from floating-point.
5090 (define_expand "fixuns_truncsfsi2"
5091 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5092 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5093 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5094 "")
5096 (define_expand "fix_truncsfsi2"
5097 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5098 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5099 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5100 "")
5102 ; For each of these conversions, there is a define_expand, a define_insn
5103 ; with a '#' template, and a define_split (with C code). The idea is
5104 ; to allow constant folding with the template of the define_insn,
5105 ; then to have the insns split later (between sched1 and final).
5107 (define_expand "floatsidf2"
5108 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5109 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5110 (use (match_dup 2))
5111 (use (match_dup 3))
5112 (clobber (match_dup 4))
5113 (clobber (match_dup 5))
5114 (clobber (match_dup 6))])]
5115 "TARGET_HARD_FLOAT && TARGET_FPRS"
5116 "
5117 {
5118 if (TARGET_E500_DOUBLE)
5119 {
5120 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5121 DONE;
5122 }
5123 if (TARGET_POWERPC64)
5124 {
5125 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5126 rtx t1 = gen_reg_rtx (DImode);
5127 rtx t2 = gen_reg_rtx (DImode);
5128 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5129 DONE;
5130 }
5132 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5133 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5134 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5135 operands[5] = gen_reg_rtx (DFmode);
5136 operands[6] = gen_reg_rtx (SImode);
5137 }")
5139 (define_insn "*floatsidf2_internal"
5140 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5141 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5142 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5143 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5144 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5145 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5146 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5147 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5148 "#"
5149 [(set_attr "length" "24")])
5151 (define_split
5152 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5153 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5154 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5155 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5156 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5157 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5158 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5159 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5160 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5161 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5162 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5163 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5164 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5165 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5166 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5167 "
5168 {
5169 rtx lowword, highword;
5170 if (GET_CODE (operands[4]) != MEM)
5171 abort();
5172 highword = XEXP (operands[4], 0);
5173 lowword = plus_constant (highword, 4);
5174 if (! WORDS_BIG_ENDIAN)
5175 {
5176 rtx tmp;
5177 tmp = highword; highword = lowword; lowword = tmp;
5178 }
5180 emit_insn (gen_xorsi3 (operands[6], operands[1],
5181 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5182 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5183 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5184 emit_move_insn (operands[5], operands[4]);
5185 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5186 DONE;
5187 }")
5189 (define_expand "floatunssisf2"
5190 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5191 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5192 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5193 "")
5195 (define_expand "floatunssidf2"
5196 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5197 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5198 (use (match_dup 2))
5199 (use (match_dup 3))
5200 (clobber (match_dup 4))
5201 (clobber (match_dup 5))])]
5202 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5203 "
5204 {
5205 if (TARGET_E500_DOUBLE)
5206 {
5207 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5208 DONE;
5209 }
5210 if (TARGET_POWERPC64)
5211 {
5212 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5213 rtx t1 = gen_reg_rtx (DImode);
5214 rtx t2 = gen_reg_rtx (DImode);
5215 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5216 t1, t2));
5217 DONE;
5218 }
5220 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5221 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5222 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5223 operands[5] = gen_reg_rtx (DFmode);
5224 }")
5226 (define_insn "*floatunssidf2_internal"
5227 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5228 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5229 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5230 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5231 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5232 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5233 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5234 "#"
5235 [(set_attr "length" "20")])
5237 (define_split
5238 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5239 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5240 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5241 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5242 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5243 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5244 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5245 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5246 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5247 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5248 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5249 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5250 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5251 "
5252 {
5253 rtx lowword, highword;
5254 if (GET_CODE (operands[4]) != MEM)
5255 abort();
5256 highword = XEXP (operands[4], 0);
5257 lowword = plus_constant (highword, 4);
5258 if (! WORDS_BIG_ENDIAN)
5259 {
5260 rtx tmp;
5261 tmp = highword; highword = lowword; lowword = tmp;
5262 }
5264 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5265 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5266 emit_move_insn (operands[5], operands[4]);
5267 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5268 DONE;
5269 }")
5271 (define_expand "fix_truncdfsi2"
5272 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5273 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5274 (clobber (match_dup 2))
5275 (clobber (match_dup 3))])]
5276 "(TARGET_POWER2 || TARGET_POWERPC)
5277 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5278 "
5279 {
5280 if (TARGET_E500_DOUBLE)
5281 {
5282 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5283 DONE;
5284 }
5285 operands[2] = gen_reg_rtx (DImode);
5286 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5287 }")
5289 (define_insn "*fix_truncdfsi2_internal"
5290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5291 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5292 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5293 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5294 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5295 "#"
5296 [(set_attr "length" "16")])
5298 (define_split
5299 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5300 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5301 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5302 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5303 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5304 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5305 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5306 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5307 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5308 "
5309 {
5310 rtx lowword;
5311 if (GET_CODE (operands[3]) != MEM)
5312 abort();
5313 lowword = XEXP (operands[3], 0);
5314 if (WORDS_BIG_ENDIAN)
5315 lowword = plus_constant (lowword, 4);
5317 emit_insn (gen_fctiwz (operands[2], operands[1]));
5318 emit_move_insn (operands[3], operands[2]);
5319 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5320 DONE;
5321 }")
5323 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5324 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5325 ; because the first makes it clear that operand 0 is not live
5326 ; before the instruction.
5327 (define_insn "fctiwz"
5328 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5329 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5330 UNSPEC_FCTIWZ))]
5331 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5332 "{fcirz|fctiwz} %0,%1"
5333 [(set_attr "type" "fp")])
5335 (define_expand "floatsisf2"
5336 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5337 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5338 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5339 "")
5341 (define_insn "floatdidf2"
5342 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5343 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5344 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5345 "fcfid %0,%1"
5346 [(set_attr "type" "fp")])
5348 (define_insn_and_split "floatsidf_ppc64"
5349 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5350 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5351 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5352 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5353 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5354 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5355 "#"
5356 "&& 1"
5357 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5358 (set (match_dup 2) (match_dup 3))
5359 (set (match_dup 4) (match_dup 2))
5360 (set (match_dup 0) (float:DF (match_dup 4)))]
5361 "")
5363 (define_insn_and_split "floatunssidf_ppc64"
5364 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5365 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5366 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5367 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5368 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5369 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5370 "#"
5371 "&& 1"
5372 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5373 (set (match_dup 2) (match_dup 3))
5374 (set (match_dup 4) (match_dup 2))
5375 (set (match_dup 0) (float:DF (match_dup 4)))]
5376 "")
5378 (define_insn "fix_truncdfdi2"
5379 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5380 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5381 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5382 "fctidz %0,%1"
5383 [(set_attr "type" "fp")])
5385 (define_expand "floatdisf2"
5386 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5387 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5388 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5389 "
5390 {
5391 rtx val = operands[1];
5392 if (!flag_unsafe_math_optimizations)
5393 {
5394 rtx label = gen_label_rtx ();
5395 val = gen_reg_rtx (DImode);
5396 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5397 emit_label (label);
5398 }
5399 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5400 DONE;
5401 }")
5403 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5404 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5405 ;; from double rounding.
5406 (define_insn_and_split "floatdisf2_internal1"
5407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5408 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5409 (clobber (match_scratch:DF 2 "=f"))]
5410 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5411 "#"
5412 "&& reload_completed"
5413 [(set (match_dup 2)
5414 (float:DF (match_dup 1)))
5415 (set (match_dup 0)
5416 (float_truncate:SF (match_dup 2)))]
5417 "")
5419 ;; Twiddles bits to avoid double rounding.
5420 ;; Bits that might be truncated when converting to DFmode are replaced
5421 ;; by a bit that won't be lost at that stage, but is below the SFmode
5422 ;; rounding position.
5423 (define_expand "floatdisf2_internal2"
5424 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5425 (const_int 53)))
5426 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5427 (const_int 2047)))
5428 (clobber (scratch:CC))])
5429 (set (match_dup 3) (plus:DI (match_dup 3)
5430 (const_int 1)))
5431 (set (match_dup 0) (plus:DI (match_dup 0)
5432 (const_int 2047)))
5433 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5434 (const_int 2)))
5435 (set (match_dup 0) (ior:DI (match_dup 0)
5436 (match_dup 1)))
5437 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5438 (const_int -2048)))
5439 (clobber (scratch:CC))])
5440 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5441 (label_ref (match_operand:DI 2 "" ""))
5442 (pc)))
5443 (set (match_dup 0) (match_dup 1))]
5444 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5445 "
5446 {
5447 operands[3] = gen_reg_rtx (DImode);
5448 operands[4] = gen_reg_rtx (CCUNSmode);
5449 }")
5450 \f
5451 ;; Define the DImode operations that can be done in a small number
5452 ;; of instructions. The & constraints are to prevent the register
5453 ;; allocator from allocating registers that overlap with the inputs
5454 ;; (for example, having an input in 7,8 and an output in 6,7). We
5455 ;; also allow for the output being the same as one of the inputs.
5457 (define_insn "*adddi3_noppc64"
5458 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5459 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5460 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5461 "! TARGET_POWERPC64"
5462 "*
5463 {
5464 if (WORDS_BIG_ENDIAN)
5465 return (GET_CODE (operands[2])) != CONST_INT
5466 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5467 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5468 else
5469 return (GET_CODE (operands[2])) != CONST_INT
5470 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5471 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5472 }"
5473 [(set_attr "type" "two")
5474 (set_attr "length" "8")])
5476 (define_insn "*subdi3_noppc64"
5477 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5478 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5479 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5480 "! TARGET_POWERPC64"
5481 "*
5482 {
5483 if (WORDS_BIG_ENDIAN)
5484 return (GET_CODE (operands[1]) != CONST_INT)
5485 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5486 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5487 else
5488 return (GET_CODE (operands[1]) != CONST_INT)
5489 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5490 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5491 }"
5492 [(set_attr "type" "two")
5493 (set_attr "length" "8")])
5495 (define_insn "*negdi2_noppc64"
5496 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5497 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5498 "! TARGET_POWERPC64"
5499 "*
5500 {
5501 return (WORDS_BIG_ENDIAN)
5502 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5503 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5504 }"
5505 [(set_attr "type" "two")
5506 (set_attr "length" "8")])
5508 (define_expand "mulsidi3"
5509 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5510 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5511 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5512 "! TARGET_POWERPC64"
5513 "
5514 {
5515 if (! TARGET_POWER && ! TARGET_POWERPC)
5516 {
5517 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5518 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5519 emit_insn (gen_mull_call ());
5520 if (WORDS_BIG_ENDIAN)
5521 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5522 else
5523 {
5524 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5525 gen_rtx_REG (SImode, 3));
5526 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5527 gen_rtx_REG (SImode, 4));
5528 }
5529 DONE;
5530 }
5531 else if (TARGET_POWER)
5532 {
5533 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5534 DONE;
5535 }
5536 }")
5538 (define_insn "mulsidi3_mq"
5539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5540 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5541 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5542 (clobber (match_scratch:SI 3 "=q"))]
5543 "TARGET_POWER"
5544 "mul %0,%1,%2\;mfmq %L0"
5545 [(set_attr "type" "imul")
5546 (set_attr "length" "8")])
5548 (define_insn "*mulsidi3_no_mq"
5549 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5550 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5551 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5552 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5553 "*
5554 {
5555 return (WORDS_BIG_ENDIAN)
5556 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5557 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5558 }"
5559 [(set_attr "type" "imul")
5560 (set_attr "length" "8")])
5562 (define_split
5563 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5564 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5565 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5566 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5567 [(set (match_dup 3)
5568 (truncate:SI
5569 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5570 (sign_extend:DI (match_dup 2)))
5571 (const_int 32))))
5572 (set (match_dup 4)
5573 (mult:SI (match_dup 1)
5574 (match_dup 2)))]
5575 "
5576 {
5577 int endian = (WORDS_BIG_ENDIAN == 0);
5578 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5579 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5580 }")
5582 (define_expand "umulsidi3"
5583 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5584 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5585 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5586 "TARGET_POWERPC && ! TARGET_POWERPC64"
5587 "
5588 {
5589 if (TARGET_POWER)
5590 {
5591 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5592 DONE;
5593 }
5594 }")
5596 (define_insn "umulsidi3_mq"
5597 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5598 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5599 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5600 (clobber (match_scratch:SI 3 "=q"))]
5601 "TARGET_POWERPC && TARGET_POWER"
5602 "*
5603 {
5604 return (WORDS_BIG_ENDIAN)
5605 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5606 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5607 }"
5608 [(set_attr "type" "imul")
5609 (set_attr "length" "8")])
5611 (define_insn "*umulsidi3_no_mq"
5612 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5613 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5614 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5615 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5616 "*
5617 {
5618 return (WORDS_BIG_ENDIAN)
5619 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5620 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5621 }"
5622 [(set_attr "type" "imul")
5623 (set_attr "length" "8")])
5625 (define_split
5626 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5627 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5628 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5629 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5630 [(set (match_dup 3)
5631 (truncate:SI
5632 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5633 (zero_extend:DI (match_dup 2)))
5634 (const_int 32))))
5635 (set (match_dup 4)
5636 (mult:SI (match_dup 1)
5637 (match_dup 2)))]
5638 "
5639 {
5640 int endian = (WORDS_BIG_ENDIAN == 0);
5641 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5642 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5643 }")
5645 (define_expand "smulsi3_highpart"
5646 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5647 (truncate:SI
5648 (lshiftrt:DI (mult:DI (sign_extend:DI
5649 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5650 (sign_extend:DI
5651 (match_operand:SI 2 "gpc_reg_operand" "r")))
5652 (const_int 32))))]
5653 ""
5654 "
5655 {
5656 if (! TARGET_POWER && ! TARGET_POWERPC)
5657 {
5658 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5659 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5660 emit_insn (gen_mulh_call ());
5661 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5662 DONE;
5663 }
5664 else if (TARGET_POWER)
5665 {
5666 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5667 DONE;
5668 }
5669 }")
5671 (define_insn "smulsi3_highpart_mq"
5672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5673 (truncate:SI
5674 (lshiftrt:DI (mult:DI (sign_extend:DI
5675 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5676 (sign_extend:DI
5677 (match_operand:SI 2 "gpc_reg_operand" "r")))
5678 (const_int 32))))
5679 (clobber (match_scratch:SI 3 "=q"))]
5680 "TARGET_POWER"
5681 "mul %0,%1,%2"
5682 [(set_attr "type" "imul")])
5684 (define_insn "*smulsi3_highpart_no_mq"
5685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5686 (truncate:SI
5687 (lshiftrt:DI (mult:DI (sign_extend:DI
5688 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5689 (sign_extend:DI
5690 (match_operand:SI 2 "gpc_reg_operand" "r")))
5691 (const_int 32))))]
5692 "TARGET_POWERPC && ! TARGET_POWER"
5693 "mulhw %0,%1,%2"
5694 [(set_attr "type" "imul")])
5696 (define_expand "umulsi3_highpart"
5697 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5698 (truncate:SI
5699 (lshiftrt:DI (mult:DI (zero_extend:DI
5700 (match_operand:SI 1 "gpc_reg_operand" ""))
5701 (zero_extend:DI
5702 (match_operand:SI 2 "gpc_reg_operand" "")))
5703 (const_int 32))))]
5704 "TARGET_POWERPC"
5705 "
5706 {
5707 if (TARGET_POWER)
5708 {
5709 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5710 DONE;
5711 }
5712 }")
5714 (define_insn "umulsi3_highpart_mq"
5715 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5716 (truncate:SI
5717 (lshiftrt:DI (mult:DI (zero_extend:DI
5718 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5719 (zero_extend:DI
5720 (match_operand:SI 2 "gpc_reg_operand" "r")))
5721 (const_int 32))))
5722 (clobber (match_scratch:SI 3 "=q"))]
5723 "TARGET_POWERPC && TARGET_POWER"
5724 "mulhwu %0,%1,%2"
5725 [(set_attr "type" "imul")])
5727 (define_insn "*umulsi3_highpart_no_mq"
5728 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5729 (truncate:SI
5730 (lshiftrt:DI (mult:DI (zero_extend:DI
5731 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5732 (zero_extend:DI
5733 (match_operand:SI 2 "gpc_reg_operand" "r")))
5734 (const_int 32))))]
5735 "TARGET_POWERPC && ! TARGET_POWER"
5736 "mulhwu %0,%1,%2"
5737 [(set_attr "type" "imul")])
5739 ;; If operands 0 and 2 are in the same register, we have a problem. But
5740 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5741 ;; why we have the strange constraints below.
5742 (define_insn "ashldi3_power"
5743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5744 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5745 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5746 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5747 "TARGET_POWER"
5748 "@
5749 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5750 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5751 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5752 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5753 [(set_attr "length" "8")])
5755 (define_insn "lshrdi3_power"
5756 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5757 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5758 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5759 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5760 "TARGET_POWER"
5761 "@
5762 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5763 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5764 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5765 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5766 [(set_attr "length" "8")])
5768 ;; Shift by a variable amount is too complex to be worth open-coding. We
5769 ;; just handle shifts by constants.
5770 (define_insn "ashrdi3_power"
5771 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5772 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5773 (match_operand:SI 2 "const_int_operand" "M,i")))
5774 (clobber (match_scratch:SI 3 "=X,q"))]
5775 "TARGET_POWER"
5776 "@
5777 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5778 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5779 [(set_attr "length" "8")])
5781 (define_insn "ashrdi3_no_power"
5782 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5783 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5784 (match_operand:SI 2 "const_int_operand" "M,i")))]
5785 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5786 "@
5787 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5788 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5789 [(set_attr "type" "two,three")
5790 (set_attr "length" "8,12")])
5792 (define_insn "*ashrdisi3_noppc64"
5793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5794 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5795 (const_int 32)) 4))]
5796 "TARGET_32BIT && !TARGET_POWERPC64"
5797 "*
5798 {
5799 if (REGNO (operands[0]) == REGNO (operands[1]))
5800 return \"\";
5801 else
5802 return \"mr %0,%1\";
5803 }"
5804 [(set_attr "length" "4")])
5806 \f
5807 ;; PowerPC64 DImode operations.
5809 (define_expand "adddi3"
5810 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5811 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5812 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5813 ""
5814 "
5815 {
5816 if (! TARGET_POWERPC64)
5817 {
5818 if (non_short_cint_operand (operands[2], DImode))
5819 FAIL;
5820 }
5821 else
5822 if (GET_CODE (operands[2]) == CONST_INT
5823 && ! add_operand (operands[2], DImode))
5824 {
5825 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5826 ? operands[0] : gen_reg_rtx (DImode));
5828 HOST_WIDE_INT val = INTVAL (operands[2]);
5829 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5830 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5832 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5833 FAIL;
5835 /* The ordering here is important for the prolog expander.
5836 When space is allocated from the stack, adding 'low' first may
5837 produce a temporary deallocation (which would be bad). */
5838 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5839 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5840 DONE;
5841 }
5842 }")
5844 ;; Discourage ai/addic because of carry but provide it in an alternative
5845 ;; allowing register zero as source.
5847 (define_insn "*adddi3_internal1"
5848 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5849 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5850 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5851 "TARGET_POWERPC64"
5852 "@
5853 add %0,%1,%2
5854 addi %0,%1,%2
5855 addic %0,%1,%2
5856 addis %0,%1,%v2")
5858 (define_insn "*adddi3_internal2"
5859 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5860 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5861 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5862 (const_int 0)))
5863 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5864 "TARGET_64BIT"
5865 "@
5866 add. %3,%1,%2
5867 addic. %3,%1,%2
5868 #
5869 #"
5870 [(set_attr "type" "fast_compare,compare,compare,compare")
5871 (set_attr "length" "4,4,8,8")])
5873 (define_split
5874 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5875 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5876 (match_operand:DI 2 "reg_or_short_operand" ""))
5877 (const_int 0)))
5878 (clobber (match_scratch:DI 3 ""))]
5879 "TARGET_POWERPC64 && reload_completed"
5880 [(set (match_dup 3)
5881 (plus:DI (match_dup 1) (match_dup 2)))
5882 (set (match_dup 0)
5883 (compare:CC (match_dup 3)
5884 (const_int 0)))]
5885 "")
5887 (define_insn "*adddi3_internal3"
5888 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5889 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5890 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5891 (const_int 0)))
5892 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5893 (plus:DI (match_dup 1) (match_dup 2)))]
5894 "TARGET_64BIT"
5895 "@
5896 add. %0,%1,%2
5897 addic. %0,%1,%2
5898 #
5899 #"
5900 [(set_attr "type" "fast_compare,compare,compare,compare")
5901 (set_attr "length" "4,4,8,8")])
5903 (define_split
5904 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5905 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5906 (match_operand:DI 2 "reg_or_short_operand" ""))
5907 (const_int 0)))
5908 (set (match_operand:DI 0 "gpc_reg_operand" "")
5909 (plus:DI (match_dup 1) (match_dup 2)))]
5910 "TARGET_POWERPC64 && reload_completed"
5911 [(set (match_dup 0)
5912 (plus:DI (match_dup 1) (match_dup 2)))
5913 (set (match_dup 3)
5914 (compare:CC (match_dup 0)
5915 (const_int 0)))]
5916 "")
5918 ;; Split an add that we can't do in one insn into two insns, each of which
5919 ;; does one 16-bit part. This is used by combine. Note that the low-order
5920 ;; add should be last in case the result gets used in an address.
5922 (define_split
5923 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5924 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5925 (match_operand:DI 2 "non_add_cint_operand" "")))]
5926 "TARGET_POWERPC64"
5927 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5928 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5929 "
5930 {
5931 HOST_WIDE_INT val = INTVAL (operands[2]);
5932 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5933 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5935 operands[4] = GEN_INT (low);
5936 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5937 operands[3] = GEN_INT (rest);
5938 else if (! no_new_pseudos)
5939 {
5940 operands[3] = gen_reg_rtx (DImode);
5941 emit_move_insn (operands[3], operands[2]);
5942 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5943 DONE;
5944 }
5945 else
5946 FAIL;
5947 }")
5949 (define_insn "one_cmpldi2"
5950 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5951 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5952 "TARGET_POWERPC64"
5953 "nor %0,%1,%1")
5955 (define_insn ""
5956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5957 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5958 (const_int 0)))
5959 (clobber (match_scratch:DI 2 "=r,r"))]
5960 "TARGET_64BIT"
5961 "@
5962 nor. %2,%1,%1
5963 #"
5964 [(set_attr "type" "compare")
5965 (set_attr "length" "4,8")])
5967 (define_split
5968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5969 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5970 (const_int 0)))
5971 (clobber (match_scratch:DI 2 ""))]
5972 "TARGET_POWERPC64 && reload_completed"
5973 [(set (match_dup 2)
5974 (not:DI (match_dup 1)))
5975 (set (match_dup 0)
5976 (compare:CC (match_dup 2)
5977 (const_int 0)))]
5978 "")
5980 (define_insn ""
5981 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5982 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5983 (const_int 0)))
5984 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5985 (not:DI (match_dup 1)))]
5986 "TARGET_64BIT"
5987 "@
5988 nor. %0,%1,%1
5989 #"
5990 [(set_attr "type" "compare")
5991 (set_attr "length" "4,8")])
5993 (define_split
5994 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5995 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5996 (const_int 0)))
5997 (set (match_operand:DI 0 "gpc_reg_operand" "")
5998 (not:DI (match_dup 1)))]
5999 "TARGET_POWERPC64 && reload_completed"
6000 [(set (match_dup 0)
6001 (not:DI (match_dup 1)))
6002 (set (match_dup 2)
6003 (compare:CC (match_dup 0)
6004 (const_int 0)))]
6005 "")
6007 (define_insn ""
6008 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6009 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
6010 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
6011 "TARGET_POWERPC64"
6012 "@
6013 subf %0,%2,%1
6014 subfic %0,%2,%1")
6016 (define_insn ""
6017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6018 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6019 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6020 (const_int 0)))
6021 (clobber (match_scratch:DI 3 "=r,r"))]
6022 "TARGET_64BIT"
6023 "@
6024 subf. %3,%2,%1
6025 #"
6026 [(set_attr "type" "fast_compare")
6027 (set_attr "length" "4,8")])
6029 (define_split
6030 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6031 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6032 (match_operand:DI 2 "gpc_reg_operand" ""))
6033 (const_int 0)))
6034 (clobber (match_scratch:DI 3 ""))]
6035 "TARGET_POWERPC64 && reload_completed"
6036 [(set (match_dup 3)
6037 (minus:DI (match_dup 1) (match_dup 2)))
6038 (set (match_dup 0)
6039 (compare:CC (match_dup 3)
6040 (const_int 0)))]
6041 "")
6043 (define_insn ""
6044 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6045 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6046 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6047 (const_int 0)))
6048 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6049 (minus:DI (match_dup 1) (match_dup 2)))]
6050 "TARGET_64BIT"
6051 "@
6052 subf. %0,%2,%1
6053 #"
6054 [(set_attr "type" "fast_compare")
6055 (set_attr "length" "4,8")])
6057 (define_split
6058 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6059 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6060 (match_operand:DI 2 "gpc_reg_operand" ""))
6061 (const_int 0)))
6062 (set (match_operand:DI 0 "gpc_reg_operand" "")
6063 (minus:DI (match_dup 1) (match_dup 2)))]
6064 "TARGET_POWERPC64 && reload_completed"
6065 [(set (match_dup 0)
6066 (minus:DI (match_dup 1) (match_dup 2)))
6067 (set (match_dup 3)
6068 (compare:CC (match_dup 0)
6069 (const_int 0)))]
6070 "")
6072 (define_expand "subdi3"
6073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6074 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6075 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6076 ""
6077 "
6078 {
6079 if (GET_CODE (operands[2]) == CONST_INT)
6080 {
6081 emit_insn (gen_adddi3 (operands[0], operands[1],
6082 negate_rtx (DImode, operands[2])));
6083 DONE;
6084 }
6085 }")
6087 (define_insn_and_split "absdi2"
6088 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6089 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6090 (clobber (match_scratch:DI 2 "=&r,&r"))]
6091 "TARGET_POWERPC64"
6092 "#"
6093 "&& reload_completed"
6094 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6095 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6096 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6097 "")
6099 (define_insn_and_split "*nabsdi2"
6100 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6101 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6102 (clobber (match_scratch:DI 2 "=&r,&r"))]
6103 "TARGET_POWERPC64"
6104 "#"
6105 "&& reload_completed"
6106 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6107 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6108 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6109 "")
6111 (define_expand "negdi2"
6112 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6113 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6114 ""
6115 "")
6117 (define_insn ""
6118 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6119 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6120 "TARGET_POWERPC64"
6121 "neg %0,%1")
6123 (define_insn ""
6124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6125 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6126 (const_int 0)))
6127 (clobber (match_scratch:DI 2 "=r,r"))]
6128 "TARGET_64BIT"
6129 "@
6130 neg. %2,%1
6131 #"
6132 [(set_attr "type" "fast_compare")
6133 (set_attr "length" "4,8")])
6135 (define_split
6136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6137 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6138 (const_int 0)))
6139 (clobber (match_scratch:DI 2 ""))]
6140 "TARGET_POWERPC64 && reload_completed"
6141 [(set (match_dup 2)
6142 (neg:DI (match_dup 1)))
6143 (set (match_dup 0)
6144 (compare:CC (match_dup 2)
6145 (const_int 0)))]
6146 "")
6148 (define_insn ""
6149 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6150 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6151 (const_int 0)))
6152 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6153 (neg:DI (match_dup 1)))]
6154 "TARGET_64BIT"
6155 "@
6156 neg. %0,%1
6157 #"
6158 [(set_attr "type" "fast_compare")
6159 (set_attr "length" "4,8")])
6161 (define_split
6162 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6163 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6164 (const_int 0)))
6165 (set (match_operand:DI 0 "gpc_reg_operand" "")
6166 (neg:DI (match_dup 1)))]
6167 "TARGET_POWERPC64 && reload_completed"
6168 [(set (match_dup 0)
6169 (neg:DI (match_dup 1)))
6170 (set (match_dup 2)
6171 (compare:CC (match_dup 0)
6172 (const_int 0)))]
6173 "")
6175 (define_insn "clzdi2"
6176 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6177 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6178 "TARGET_POWERPC64"
6179 "cntlzd %0,%1")
6181 (define_expand "ctzdi2"
6182 [(set (match_dup 2)
6183 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6184 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6185 (match_dup 2)))
6186 (clobber (scratch:CC))])
6187 (set (match_dup 4) (clz:DI (match_dup 3)))
6188 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6189 (minus:DI (const_int 63) (match_dup 4)))]
6190 "TARGET_POWERPC64"
6191 {
6192 operands[2] = gen_reg_rtx (DImode);
6193 operands[3] = gen_reg_rtx (DImode);
6194 operands[4] = gen_reg_rtx (DImode);
6195 })
6197 (define_expand "ffsdi2"
6198 [(set (match_dup 2)
6199 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6200 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6201 (match_dup 2)))
6202 (clobber (scratch:CC))])
6203 (set (match_dup 4) (clz:DI (match_dup 3)))
6204 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6205 (minus:DI (const_int 64) (match_dup 4)))]
6206 "TARGET_POWERPC64"
6207 {
6208 operands[2] = gen_reg_rtx (DImode);
6209 operands[3] = gen_reg_rtx (DImode);
6210 operands[4] = gen_reg_rtx (DImode);
6211 })
6213 (define_insn "muldi3"
6214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6215 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6216 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6217 "TARGET_POWERPC64"
6218 "mulld %0,%1,%2"
6219 [(set_attr "type" "lmul")])
6221 (define_insn "*muldi3_internal1"
6222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6223 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6224 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6225 (const_int 0)))
6226 (clobber (match_scratch:DI 3 "=r,r"))]
6227 "TARGET_POWERPC64"
6228 "@
6229 mulld. %3,%1,%2
6230 #"
6231 [(set_attr "type" "lmul_compare")
6232 (set_attr "length" "4,8")])
6234 (define_split
6235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6236 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6237 (match_operand:DI 2 "gpc_reg_operand" ""))
6238 (const_int 0)))
6239 (clobber (match_scratch:DI 3 ""))]
6240 "TARGET_POWERPC64 && reload_completed"
6241 [(set (match_dup 3)
6242 (mult:DI (match_dup 1) (match_dup 2)))
6243 (set (match_dup 0)
6244 (compare:CC (match_dup 3)
6245 (const_int 0)))]
6246 "")
6248 (define_insn "*muldi3_internal2"
6249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6250 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6251 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6252 (const_int 0)))
6253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6254 (mult:DI (match_dup 1) (match_dup 2)))]
6255 "TARGET_POWERPC64"
6256 "@
6257 mulld. %0,%1,%2
6258 #"
6259 [(set_attr "type" "lmul_compare")
6260 (set_attr "length" "4,8")])
6262 (define_split
6263 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6264 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "gpc_reg_operand" ""))
6266 (const_int 0)))
6267 (set (match_operand:DI 0 "gpc_reg_operand" "")
6268 (mult:DI (match_dup 1) (match_dup 2)))]
6269 "TARGET_POWERPC64 && reload_completed"
6270 [(set (match_dup 0)
6271 (mult:DI (match_dup 1) (match_dup 2)))
6272 (set (match_dup 3)
6273 (compare:CC (match_dup 0)
6274 (const_int 0)))]
6275 "")
6277 (define_insn "smuldi3_highpart"
6278 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6279 (truncate:DI
6280 (lshiftrt:TI (mult:TI (sign_extend:TI
6281 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6282 (sign_extend:TI
6283 (match_operand:DI 2 "gpc_reg_operand" "r")))
6284 (const_int 64))))]
6285 "TARGET_POWERPC64"
6286 "mulhd %0,%1,%2"
6287 [(set_attr "type" "lmul")])
6289 (define_insn "umuldi3_highpart"
6290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6291 (truncate:DI
6292 (lshiftrt:TI (mult:TI (zero_extend:TI
6293 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6294 (zero_extend:TI
6295 (match_operand:DI 2 "gpc_reg_operand" "r")))
6296 (const_int 64))))]
6297 "TARGET_POWERPC64"
6298 "mulhdu %0,%1,%2"
6299 [(set_attr "type" "lmul")])
6301 (define_expand "divdi3"
6302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6303 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6304 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6305 "TARGET_POWERPC64"
6306 "
6307 {
6308 if (GET_CODE (operands[2]) == CONST_INT
6309 && INTVAL (operands[2]) > 0
6310 && exact_log2 (INTVAL (operands[2])) >= 0)
6311 ;
6312 else
6313 operands[2] = force_reg (DImode, operands[2]);
6314 }")
6316 (define_expand "moddi3"
6317 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6318 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6319 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6320 "TARGET_POWERPC64"
6321 "
6322 {
6323 int i;
6324 rtx temp1;
6325 rtx temp2;
6327 if (GET_CODE (operands[2]) != CONST_INT
6328 || INTVAL (operands[2]) <= 0
6329 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6330 FAIL;
6332 temp1 = gen_reg_rtx (DImode);
6333 temp2 = gen_reg_rtx (DImode);
6335 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6336 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6337 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6338 DONE;
6339 }")
6341 (define_insn ""
6342 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6343 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6344 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6345 "TARGET_POWERPC64"
6346 "sradi %0,%1,%p2\;addze %0,%0"
6347 [(set_attr "type" "two")
6348 (set_attr "length" "8")])
6350 (define_insn ""
6351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6352 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6353 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6354 (const_int 0)))
6355 (clobber (match_scratch:DI 3 "=r,r"))]
6356 "TARGET_64BIT"
6357 "@
6358 sradi %3,%1,%p2\;addze. %3,%3
6359 #"
6360 [(set_attr "type" "compare")
6361 (set_attr "length" "8,12")])
6363 (define_split
6364 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6365 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6366 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6367 (const_int 0)))
6368 (clobber (match_scratch:DI 3 ""))]
6369 "TARGET_POWERPC64 && reload_completed"
6370 [(set (match_dup 3)
6371 (div:DI (match_dup 1) (match_dup 2)))
6372 (set (match_dup 0)
6373 (compare:CC (match_dup 3)
6374 (const_int 0)))]
6375 "")
6377 (define_insn ""
6378 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6379 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6380 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6381 (const_int 0)))
6382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6383 (div:DI (match_dup 1) (match_dup 2)))]
6384 "TARGET_64BIT"
6385 "@
6386 sradi %0,%1,%p2\;addze. %0,%0
6387 #"
6388 [(set_attr "type" "compare")
6389 (set_attr "length" "8,12")])
6391 (define_split
6392 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6393 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6394 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6395 (const_int 0)))
6396 (set (match_operand:DI 0 "gpc_reg_operand" "")
6397 (div:DI (match_dup 1) (match_dup 2)))]
6398 "TARGET_POWERPC64 && reload_completed"
6399 [(set (match_dup 0)
6400 (div:DI (match_dup 1) (match_dup 2)))
6401 (set (match_dup 3)
6402 (compare:CC (match_dup 0)
6403 (const_int 0)))]
6404 "")
6406 (define_insn ""
6407 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6408 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6409 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6410 "TARGET_POWERPC64"
6411 "divd %0,%1,%2"
6412 [(set_attr "type" "ldiv")])
6414 (define_insn "udivdi3"
6415 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6416 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6417 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6418 "TARGET_POWERPC64"
6419 "divdu %0,%1,%2"
6420 [(set_attr "type" "ldiv")])
6422 (define_insn "rotldi3"
6423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6424 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6425 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6426 "TARGET_POWERPC64"
6427 "rld%I2cl %0,%1,%H2,0")
6429 (define_insn "*rotldi3_internal2"
6430 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6431 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6432 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6433 (const_int 0)))
6434 (clobber (match_scratch:DI 3 "=r,r"))]
6435 "TARGET_64BIT"
6436 "@
6437 rld%I2cl. %3,%1,%H2,0
6438 #"
6439 [(set_attr "type" "delayed_compare")
6440 (set_attr "length" "4,8")])
6442 (define_split
6443 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6444 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6445 (match_operand:DI 2 "reg_or_cint_operand" ""))
6446 (const_int 0)))
6447 (clobber (match_scratch:DI 3 ""))]
6448 "TARGET_POWERPC64 && reload_completed"
6449 [(set (match_dup 3)
6450 (rotate:DI (match_dup 1) (match_dup 2)))
6451 (set (match_dup 0)
6452 (compare:CC (match_dup 3)
6453 (const_int 0)))]
6454 "")
6456 (define_insn "*rotldi3_internal3"
6457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6458 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6459 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6460 (const_int 0)))
6461 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6462 (rotate:DI (match_dup 1) (match_dup 2)))]
6463 "TARGET_64BIT"
6464 "@
6465 rld%I2cl. %0,%1,%H2,0
6466 #"
6467 [(set_attr "type" "delayed_compare")
6468 (set_attr "length" "4,8")])
6470 (define_split
6471 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6472 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6473 (match_operand:DI 2 "reg_or_cint_operand" ""))
6474 (const_int 0)))
6475 (set (match_operand:DI 0 "gpc_reg_operand" "")
6476 (rotate:DI (match_dup 1) (match_dup 2)))]
6477 "TARGET_POWERPC64 && reload_completed"
6478 [(set (match_dup 0)
6479 (rotate:DI (match_dup 1) (match_dup 2)))
6480 (set (match_dup 3)
6481 (compare:CC (match_dup 0)
6482 (const_int 0)))]
6483 "")
6485 (define_insn "*rotldi3_internal4"
6486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6487 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6488 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6489 (match_operand:DI 3 "mask64_operand" "n")))]
6490 "TARGET_POWERPC64"
6491 "rld%I2c%B3 %0,%1,%H2,%S3")
6493 (define_insn "*rotldi3_internal5"
6494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6495 (compare:CC (and:DI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6498 (match_operand:DI 3 "mask64_operand" "n,n"))
6499 (const_int 0)))
6500 (clobber (match_scratch:DI 4 "=r,r"))]
6501 "TARGET_64BIT"
6502 "@
6503 rld%I2c%B3. %4,%1,%H2,%S3
6504 #"
6505 [(set_attr "type" "delayed_compare")
6506 (set_attr "length" "4,8")])
6508 (define_split
6509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6510 (compare:CC (and:DI
6511 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6512 (match_operand:DI 2 "reg_or_cint_operand" ""))
6513 (match_operand:DI 3 "mask64_operand" ""))
6514 (const_int 0)))
6515 (clobber (match_scratch:DI 4 ""))]
6516 "TARGET_POWERPC64 && reload_completed"
6517 [(set (match_dup 4)
6518 (and:DI (rotate:DI (match_dup 1)
6519 (match_dup 2))
6520 (match_dup 3)))
6521 (set (match_dup 0)
6522 (compare:CC (match_dup 4)
6523 (const_int 0)))]
6524 "")
6526 (define_insn "*rotldi3_internal6"
6527 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6528 (compare:CC (and:DI
6529 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6530 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6531 (match_operand:DI 3 "mask64_operand" "n,n"))
6532 (const_int 0)))
6533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6534 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6535 "TARGET_64BIT"
6536 "@
6537 rld%I2c%B3. %0,%1,%H2,%S3
6538 #"
6539 [(set_attr "type" "delayed_compare")
6540 (set_attr "length" "4,8")])
6542 (define_split
6543 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6544 (compare:CC (and:DI
6545 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6546 (match_operand:DI 2 "reg_or_cint_operand" ""))
6547 (match_operand:DI 3 "mask64_operand" ""))
6548 (const_int 0)))
6549 (set (match_operand:DI 0 "gpc_reg_operand" "")
6550 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6551 "TARGET_POWERPC64 && reload_completed"
6552 [(set (match_dup 0)
6553 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6554 (set (match_dup 4)
6555 (compare:CC (match_dup 0)
6556 (const_int 0)))]
6557 "")
6559 (define_insn "*rotldi3_internal7"
6560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6561 (zero_extend:DI
6562 (subreg:QI
6563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6564 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6565 "TARGET_POWERPC64"
6566 "rld%I2cl %0,%1,%H2,56")
6568 (define_insn "*rotldi3_internal8"
6569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6570 (compare:CC (zero_extend:DI
6571 (subreg:QI
6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6573 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 "=r,r"))]
6576 "TARGET_64BIT"
6577 "@
6578 rld%I2cl. %3,%1,%H2,56
6579 #"
6580 [(set_attr "type" "delayed_compare")
6581 (set_attr "length" "4,8")])
6583 (define_split
6584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6585 (compare:CC (zero_extend:DI
6586 (subreg:QI
6587 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6588 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6589 (const_int 0)))
6590 (clobber (match_scratch:DI 3 ""))]
6591 "TARGET_POWERPC64 && reload_completed"
6592 [(set (match_dup 3)
6593 (zero_extend:DI (subreg:QI
6594 (rotate:DI (match_dup 1)
6595 (match_dup 2)) 0)))
6596 (set (match_dup 0)
6597 (compare:CC (match_dup 3)
6598 (const_int 0)))]
6599 "")
6601 (define_insn "*rotldi3_internal9"
6602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6603 (compare:CC (zero_extend:DI
6604 (subreg:QI
6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6606 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6607 (const_int 0)))
6608 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6609 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6610 "TARGET_64BIT"
6611 "@
6612 rld%I2cl. %0,%1,%H2,56
6613 #"
6614 [(set_attr "type" "delayed_compare")
6615 (set_attr "length" "4,8")])
6617 (define_split
6618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6619 (compare:CC (zero_extend:DI
6620 (subreg:QI
6621 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6622 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6623 (const_int 0)))
6624 (set (match_operand:DI 0 "gpc_reg_operand" "")
6625 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6626 "TARGET_POWERPC64 && reload_completed"
6627 [(set (match_dup 0)
6628 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6629 (set (match_dup 3)
6630 (compare:CC (match_dup 0)
6631 (const_int 0)))]
6632 "")
6634 (define_insn "*rotldi3_internal10"
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6636 (zero_extend:DI
6637 (subreg:HI
6638 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6639 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6640 "TARGET_POWERPC64"
6641 "rld%I2cl %0,%1,%H2,48")
6643 (define_insn "*rotldi3_internal11"
6644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6645 (compare:CC (zero_extend:DI
6646 (subreg:HI
6647 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6648 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6649 (const_int 0)))
6650 (clobber (match_scratch:DI 3 "=r,r"))]
6651 "TARGET_64BIT"
6652 "@
6653 rld%I2cl. %3,%1,%H2,48
6654 #"
6655 [(set_attr "type" "delayed_compare")
6656 (set_attr "length" "4,8")])
6658 (define_split
6659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6660 (compare:CC (zero_extend:DI
6661 (subreg:HI
6662 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6663 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6664 (const_int 0)))
6665 (clobber (match_scratch:DI 3 ""))]
6666 "TARGET_POWERPC64 && reload_completed"
6667 [(set (match_dup 3)
6668 (zero_extend:DI (subreg:HI
6669 (rotate:DI (match_dup 1)
6670 (match_dup 2)) 0)))
6671 (set (match_dup 0)
6672 (compare:CC (match_dup 3)
6673 (const_int 0)))]
6674 "")
6676 (define_insn "*rotldi3_internal12"
6677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6678 (compare:CC (zero_extend:DI
6679 (subreg:HI
6680 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6681 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6682 (const_int 0)))
6683 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6684 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6685 "TARGET_64BIT"
6686 "@
6687 rld%I2cl. %0,%1,%H2,48
6688 #"
6689 [(set_attr "type" "delayed_compare")
6690 (set_attr "length" "4,8")])
6692 (define_split
6693 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6694 (compare:CC (zero_extend:DI
6695 (subreg:HI
6696 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6697 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6698 (const_int 0)))
6699 (set (match_operand:DI 0 "gpc_reg_operand" "")
6700 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6701 "TARGET_POWERPC64 && reload_completed"
6702 [(set (match_dup 0)
6703 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6704 (set (match_dup 3)
6705 (compare:CC (match_dup 0)
6706 (const_int 0)))]
6707 "")
6709 (define_insn "*rotldi3_internal13"
6710 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6711 (zero_extend:DI
6712 (subreg:SI
6713 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6714 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6715 "TARGET_POWERPC64"
6716 "rld%I2cl %0,%1,%H2,32")
6718 (define_insn "*rotldi3_internal14"
6719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6720 (compare:CC (zero_extend:DI
6721 (subreg:SI
6722 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6723 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6724 (const_int 0)))
6725 (clobber (match_scratch:DI 3 "=r,r"))]
6726 "TARGET_64BIT"
6727 "@
6728 rld%I2cl. %3,%1,%H2,32
6729 #"
6730 [(set_attr "type" "delayed_compare")
6731 (set_attr "length" "4,8")])
6733 (define_split
6734 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6735 (compare:CC (zero_extend:DI
6736 (subreg:SI
6737 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6738 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6739 (const_int 0)))
6740 (clobber (match_scratch:DI 3 ""))]
6741 "TARGET_POWERPC64 && reload_completed"
6742 [(set (match_dup 3)
6743 (zero_extend:DI (subreg:SI
6744 (rotate:DI (match_dup 1)
6745 (match_dup 2)) 0)))
6746 (set (match_dup 0)
6747 (compare:CC (match_dup 3)
6748 (const_int 0)))]
6749 "")
6751 (define_insn "*rotldi3_internal15"
6752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6753 (compare:CC (zero_extend:DI
6754 (subreg:SI
6755 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6756 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6757 (const_int 0)))
6758 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6759 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6760 "TARGET_64BIT"
6761 "@
6762 rld%I2cl. %0,%1,%H2,32
6763 #"
6764 [(set_attr "type" "delayed_compare")
6765 (set_attr "length" "4,8")])
6767 (define_split
6768 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6769 (compare:CC (zero_extend:DI
6770 (subreg:SI
6771 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6772 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6773 (const_int 0)))
6774 (set (match_operand:DI 0 "gpc_reg_operand" "")
6775 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6776 "TARGET_POWERPC64 && reload_completed"
6777 [(set (match_dup 0)
6778 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6779 (set (match_dup 3)
6780 (compare:CC (match_dup 0)
6781 (const_int 0)))]
6782 "")
6784 (define_expand "ashldi3"
6785 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6786 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6787 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6788 "TARGET_POWERPC64 || TARGET_POWER"
6789 "
6790 {
6791 if (TARGET_POWERPC64)
6792 ;
6793 else if (TARGET_POWER)
6794 {
6795 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6796 DONE;
6797 }
6798 else
6799 FAIL;
6800 }")
6802 (define_insn "*ashldi3_internal1"
6803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6804 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6805 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6806 "TARGET_POWERPC64"
6807 "sld%I2 %0,%1,%H2")
6809 (define_insn "*ashldi3_internal2"
6810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6811 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6812 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6813 (const_int 0)))
6814 (clobber (match_scratch:DI 3 "=r,r"))]
6815 "TARGET_64BIT"
6816 "@
6817 sld%I2. %3,%1,%H2
6818 #"
6819 [(set_attr "type" "delayed_compare")
6820 (set_attr "length" "4,8")])
6822 (define_split
6823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6824 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6825 (match_operand:SI 2 "reg_or_cint_operand" ""))
6826 (const_int 0)))
6827 (clobber (match_scratch:DI 3 ""))]
6828 "TARGET_POWERPC64 && reload_completed"
6829 [(set (match_dup 3)
6830 (ashift:DI (match_dup 1) (match_dup 2)))
6831 (set (match_dup 0)
6832 (compare:CC (match_dup 3)
6833 (const_int 0)))]
6834 "")
6836 (define_insn "*ashldi3_internal3"
6837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6838 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6839 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6840 (const_int 0)))
6841 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6842 (ashift:DI (match_dup 1) (match_dup 2)))]
6843 "TARGET_64BIT"
6844 "@
6845 sld%I2. %0,%1,%H2
6846 #"
6847 [(set_attr "type" "delayed_compare")
6848 (set_attr "length" "4,8")])
6850 (define_split
6851 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6852 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6853 (match_operand:SI 2 "reg_or_cint_operand" ""))
6854 (const_int 0)))
6855 (set (match_operand:DI 0 "gpc_reg_operand" "")
6856 (ashift:DI (match_dup 1) (match_dup 2)))]
6857 "TARGET_POWERPC64 && reload_completed"
6858 [(set (match_dup 0)
6859 (ashift:DI (match_dup 1) (match_dup 2)))
6860 (set (match_dup 3)
6861 (compare:CC (match_dup 0)
6862 (const_int 0)))]
6863 "")
6865 (define_insn "*ashldi3_internal4"
6866 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6867 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6868 (match_operand:SI 2 "const_int_operand" "i"))
6869 (match_operand:DI 3 "const_int_operand" "n")))]
6870 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6871 "rldic %0,%1,%H2,%W3")
6873 (define_insn "ashldi3_internal5"
6874 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6875 (compare:CC
6876 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6877 (match_operand:SI 2 "const_int_operand" "i,i"))
6878 (match_operand:DI 3 "const_int_operand" "n,n"))
6879 (const_int 0)))
6880 (clobber (match_scratch:DI 4 "=r,r"))]
6881 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6882 "@
6883 rldic. %4,%1,%H2,%W3
6884 #"
6885 [(set_attr "type" "delayed_compare")
6886 (set_attr "length" "4,8")])
6888 (define_split
6889 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6890 (compare:CC
6891 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6892 (match_operand:SI 2 "const_int_operand" ""))
6893 (match_operand:DI 3 "const_int_operand" ""))
6894 (const_int 0)))
6895 (clobber (match_scratch:DI 4 ""))]
6896 "TARGET_POWERPC64 && reload_completed
6897 && includes_rldic_lshift_p (operands[2], operands[3])"
6898 [(set (match_dup 4)
6899 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6900 (match_dup 3)))
6901 (set (match_dup 0)
6902 (compare:CC (match_dup 4)
6903 (const_int 0)))]
6904 "")
6906 (define_insn "*ashldi3_internal6"
6907 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6908 (compare:CC
6909 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6910 (match_operand:SI 2 "const_int_operand" "i,i"))
6911 (match_operand:DI 3 "const_int_operand" "n,n"))
6912 (const_int 0)))
6913 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6914 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6915 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6916 "@
6917 rldic. %0,%1,%H2,%W3
6918 #"
6919 [(set_attr "type" "delayed_compare")
6920 (set_attr "length" "4,8")])
6922 (define_split
6923 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6924 (compare:CC
6925 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6926 (match_operand:SI 2 "const_int_operand" ""))
6927 (match_operand:DI 3 "const_int_operand" ""))
6928 (const_int 0)))
6929 (set (match_operand:DI 0 "gpc_reg_operand" "")
6930 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6931 "TARGET_POWERPC64 && reload_completed
6932 && includes_rldic_lshift_p (operands[2], operands[3])"
6933 [(set (match_dup 0)
6934 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6935 (match_dup 3)))
6936 (set (match_dup 4)
6937 (compare:CC (match_dup 0)
6938 (const_int 0)))]
6939 "")
6941 (define_insn "*ashldi3_internal7"
6942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6943 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6944 (match_operand:SI 2 "const_int_operand" "i"))
6945 (match_operand:DI 3 "mask64_operand" "n")))]
6946 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6947 "rldicr %0,%1,%H2,%S3")
6949 (define_insn "ashldi3_internal8"
6950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6951 (compare:CC
6952 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6953 (match_operand:SI 2 "const_int_operand" "i,i"))
6954 (match_operand:DI 3 "mask64_operand" "n,n"))
6955 (const_int 0)))
6956 (clobber (match_scratch:DI 4 "=r,r"))]
6957 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6958 "@
6959 rldicr. %4,%1,%H2,%S3
6960 #"
6961 [(set_attr "type" "delayed_compare")
6962 (set_attr "length" "4,8")])
6964 (define_split
6965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6966 (compare:CC
6967 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6968 (match_operand:SI 2 "const_int_operand" ""))
6969 (match_operand:DI 3 "mask64_operand" ""))
6970 (const_int 0)))
6971 (clobber (match_scratch:DI 4 ""))]
6972 "TARGET_POWERPC64 && reload_completed
6973 && includes_rldicr_lshift_p (operands[2], operands[3])"
6974 [(set (match_dup 4)
6975 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6976 (match_dup 3)))
6977 (set (match_dup 0)
6978 (compare:CC (match_dup 4)
6979 (const_int 0)))]
6980 "")
6982 (define_insn "*ashldi3_internal9"
6983 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6984 (compare:CC
6985 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6986 (match_operand:SI 2 "const_int_operand" "i,i"))
6987 (match_operand:DI 3 "mask64_operand" "n,n"))
6988 (const_int 0)))
6989 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6990 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6991 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6992 "@
6993 rldicr. %0,%1,%H2,%S3
6994 #"
6995 [(set_attr "type" "delayed_compare")
6996 (set_attr "length" "4,8")])
6998 (define_split
6999 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7000 (compare:CC
7001 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7002 (match_operand:SI 2 "const_int_operand" ""))
7003 (match_operand:DI 3 "mask64_operand" ""))
7004 (const_int 0)))
7005 (set (match_operand:DI 0 "gpc_reg_operand" "")
7006 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7007 "TARGET_POWERPC64 && reload_completed
7008 && includes_rldicr_lshift_p (operands[2], operands[3])"
7009 [(set (match_dup 0)
7010 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7011 (match_dup 3)))
7012 (set (match_dup 4)
7013 (compare:CC (match_dup 0)
7014 (const_int 0)))]
7015 "")
7017 (define_expand "lshrdi3"
7018 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7019 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7021 "TARGET_POWERPC64 || TARGET_POWER"
7022 "
7023 {
7024 if (TARGET_POWERPC64)
7025 ;
7026 else if (TARGET_POWER)
7027 {
7028 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7029 DONE;
7030 }
7031 else
7032 FAIL;
7033 }")
7035 (define_insn "*lshrdi3_internal1"
7036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7037 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7038 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7039 "TARGET_POWERPC64"
7040 "srd%I2 %0,%1,%H2")
7042 (define_insn "*lshrdi3_internal2"
7043 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7044 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7045 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7046 (const_int 0)))
7047 (clobber (match_scratch:DI 3 "=r,r"))]
7048 "TARGET_64BIT "
7049 "@
7050 srd%I2. %3,%1,%H2
7051 #"
7052 [(set_attr "type" "delayed_compare")
7053 (set_attr "length" "4,8")])
7055 (define_split
7056 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7057 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7058 (match_operand:SI 2 "reg_or_cint_operand" ""))
7059 (const_int 0)))
7060 (clobber (match_scratch:DI 3 ""))]
7061 "TARGET_POWERPC64 && reload_completed"
7062 [(set (match_dup 3)
7063 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7064 (set (match_dup 0)
7065 (compare:CC (match_dup 3)
7066 (const_int 0)))]
7067 "")
7069 (define_insn "*lshrdi3_internal3"
7070 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7071 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7072 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7073 (const_int 0)))
7074 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7075 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7076 "TARGET_64BIT"
7077 "@
7078 srd%I2. %0,%1,%H2
7079 #"
7080 [(set_attr "type" "delayed_compare")
7081 (set_attr "length" "4,8")])
7083 (define_split
7084 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7085 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7086 (match_operand:SI 2 "reg_or_cint_operand" ""))
7087 (const_int 0)))
7088 (set (match_operand:DI 0 "gpc_reg_operand" "")
7089 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7090 "TARGET_POWERPC64 && reload_completed"
7091 [(set (match_dup 0)
7092 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7093 (set (match_dup 3)
7094 (compare:CC (match_dup 0)
7095 (const_int 0)))]
7096 "")
7098 (define_expand "ashrdi3"
7099 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7100 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7101 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7102 "WORDS_BIG_ENDIAN"
7103 "
7104 {
7105 if (TARGET_POWERPC64)
7106 ;
7107 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7108 {
7109 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7110 DONE;
7111 }
7112 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7113 && WORDS_BIG_ENDIAN)
7114 {
7115 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7116 DONE;
7117 }
7118 else
7119 FAIL;
7120 }")
7122 (define_insn "*ashrdi3_internal1"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7124 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7125 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7126 "TARGET_POWERPC64"
7127 "srad%I2 %0,%1,%H2")
7129 (define_insn "*ashrdi3_internal2"
7130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7131 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7132 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7133 (const_int 0)))
7134 (clobber (match_scratch:DI 3 "=r,r"))]
7135 "TARGET_64BIT"
7136 "@
7137 srad%I2. %3,%1,%H2
7138 #"
7139 [(set_attr "type" "delayed_compare")
7140 (set_attr "length" "4,8")])
7142 (define_split
7143 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7144 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7145 (match_operand:SI 2 "reg_or_cint_operand" ""))
7146 (const_int 0)))
7147 (clobber (match_scratch:DI 3 ""))]
7148 "TARGET_POWERPC64 && reload_completed"
7149 [(set (match_dup 3)
7150 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7151 (set (match_dup 0)
7152 (compare:CC (match_dup 3)
7153 (const_int 0)))]
7154 "")
7156 (define_insn "*ashrdi3_internal3"
7157 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7158 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7159 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7160 (const_int 0)))
7161 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7162 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7163 "TARGET_64BIT"
7164 "@
7165 srad%I2. %0,%1,%H2
7166 #"
7167 [(set_attr "type" "delayed_compare")
7168 (set_attr "length" "4,8")])
7170 (define_split
7171 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7172 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7173 (match_operand:SI 2 "reg_or_cint_operand" ""))
7174 (const_int 0)))
7175 (set (match_operand:DI 0 "gpc_reg_operand" "")
7176 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7177 "TARGET_POWERPC64 && reload_completed"
7178 [(set (match_dup 0)
7179 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7180 (set (match_dup 3)
7181 (compare:CC (match_dup 0)
7182 (const_int 0)))]
7183 "")
7185 (define_insn "anddi3"
7186 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7187 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7188 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7189 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7190 "TARGET_POWERPC64"
7191 "@
7192 and %0,%1,%2
7193 rldic%B2 %0,%1,0,%S2
7194 rlwinm %0,%1,0,%m2,%M2
7195 andi. %0,%1,%b2
7196 andis. %0,%1,%u2
7197 #"
7198 [(set_attr "type" "*,*,*,compare,compare,*")
7199 (set_attr "length" "4,4,4,4,4,8")])
7201 (define_split
7202 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7203 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7204 (match_operand:DI 2 "mask64_2_operand" "")))
7205 (clobber (match_scratch:CC 3 ""))]
7206 "TARGET_POWERPC64
7207 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7208 && !mask64_operand (operands[2], DImode)"
7209 [(set (match_dup 0)
7210 (and:DI (rotate:DI (match_dup 1)
7211 (match_dup 4))
7212 (match_dup 5)))
7213 (set (match_dup 0)
7214 (and:DI (rotate:DI (match_dup 0)
7215 (match_dup 6))
7216 (match_dup 7)))]
7217 {
7218 build_mask64_2_operands (operands[2], &operands[4]);
7219 })
7221 (define_insn "*anddi3_internal2"
7222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7223 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7224 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7225 (const_int 0)))
7226 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7227 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7228 "TARGET_64BIT"
7229 "@
7230 and. %3,%1,%2
7231 rldic%B2. %3,%1,0,%S2
7232 andi. %3,%1,%b2
7233 andis. %3,%1,%u2
7234 #
7235 #
7236 #
7237 #
7238 #
7239 #"
7240 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7241 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7243 (define_split
7244 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7245 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7246 (match_operand:DI 2 "and64_operand" ""))
7247 (const_int 0)))
7248 (clobber (match_scratch:DI 3 ""))
7249 (clobber (match_scratch:CC 4 ""))]
7250 "TARGET_POWERPC64 && reload_completed"
7251 [(parallel [(set (match_dup 3)
7252 (and:DI (match_dup 1)
7253 (match_dup 2)))
7254 (clobber (match_dup 4))])
7255 (set (match_dup 0)
7256 (compare:CC (match_dup 3)
7257 (const_int 0)))]
7258 "")
7260 (define_split
7261 [(set (match_operand:CC 0 "cc_reg_operand" "")
7262 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7263 (match_operand:DI 2 "mask64_2_operand" ""))
7264 (const_int 0)))
7265 (clobber (match_scratch:DI 3 ""))
7266 (clobber (match_scratch:CC 4 ""))]
7267 "TARGET_POWERPC64 && reload_completed
7268 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7269 && !mask64_operand (operands[2], DImode)"
7270 [(set (match_dup 3)
7271 (and:DI (rotate:DI (match_dup 1)
7272 (match_dup 5))
7273 (match_dup 6)))
7274 (parallel [(set (match_dup 0)
7275 (compare:CC (and:DI (rotate:DI (match_dup 3)
7276 (match_dup 7))
7277 (match_dup 8))
7278 (const_int 0)))
7279 (clobber (match_dup 3))])]
7280 "
7281 {
7282 build_mask64_2_operands (operands[2], &operands[5]);
7283 }")
7285 (define_insn "*anddi3_internal3"
7286 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7287 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7288 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7289 (const_int 0)))
7290 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7291 (and:DI (match_dup 1) (match_dup 2)))
7292 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7293 "TARGET_64BIT"
7294 "@
7295 and. %0,%1,%2
7296 rldic%B2. %0,%1,0,%S2
7297 andi. %0,%1,%b2
7298 andis. %0,%1,%u2
7299 #
7300 #
7301 #
7302 #
7303 #
7304 #"
7305 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7306 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7308 (define_split
7309 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7310 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7311 (match_operand:DI 2 "and64_operand" ""))
7312 (const_int 0)))
7313 (set (match_operand:DI 0 "gpc_reg_operand" "")
7314 (and:DI (match_dup 1) (match_dup 2)))
7315 (clobber (match_scratch:CC 4 ""))]
7316 "TARGET_POWERPC64 && reload_completed"
7317 [(parallel [(set (match_dup 0)
7318 (and:DI (match_dup 1) (match_dup 2)))
7319 (clobber (match_dup 4))])
7320 (set (match_dup 3)
7321 (compare:CC (match_dup 0)
7322 (const_int 0)))]
7323 "")
7325 (define_split
7326 [(set (match_operand:CC 3 "cc_reg_operand" "")
7327 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7328 (match_operand:DI 2 "mask64_2_operand" ""))
7329 (const_int 0)))
7330 (set (match_operand:DI 0 "gpc_reg_operand" "")
7331 (and:DI (match_dup 1) (match_dup 2)))
7332 (clobber (match_scratch:CC 4 ""))]
7333 "TARGET_POWERPC64 && reload_completed
7334 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7335 && !mask64_operand (operands[2], DImode)"
7336 [(set (match_dup 0)
7337 (and:DI (rotate:DI (match_dup 1)
7338 (match_dup 5))
7339 (match_dup 6)))
7340 (parallel [(set (match_dup 3)
7341 (compare:CC (and:DI (rotate:DI (match_dup 0)
7342 (match_dup 7))
7343 (match_dup 8))
7344 (const_int 0)))
7345 (set (match_dup 0)
7346 (and:DI (rotate:DI (match_dup 0)
7347 (match_dup 7))
7348 (match_dup 8)))])]
7349 "
7350 {
7351 build_mask64_2_operands (operands[2], &operands[5]);
7352 }")
7354 (define_expand "iordi3"
7355 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7356 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7357 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7358 "TARGET_POWERPC64"
7359 "
7360 {
7361 if (non_logical_cint_operand (operands[2], DImode))
7362 {
7363 HOST_WIDE_INT value;
7364 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7365 ? operands[0] : gen_reg_rtx (DImode));
7367 if (GET_CODE (operands[2]) == CONST_INT)
7368 {
7369 value = INTVAL (operands[2]);
7370 emit_insn (gen_iordi3 (tmp, operands[1],
7371 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7372 }
7373 else
7374 {
7375 value = CONST_DOUBLE_LOW (operands[2]);
7376 emit_insn (gen_iordi3 (tmp, operands[1],
7377 immed_double_const (value
7378 & (~ (HOST_WIDE_INT) 0xffff),
7379 0, DImode)));
7380 }
7382 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7383 DONE;
7384 }
7385 }")
7387 (define_expand "xordi3"
7388 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7389 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7390 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7391 "TARGET_POWERPC64"
7392 "
7393 {
7394 if (non_logical_cint_operand (operands[2], DImode))
7395 {
7396 HOST_WIDE_INT value;
7397 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7398 ? operands[0] : gen_reg_rtx (DImode));
7400 if (GET_CODE (operands[2]) == CONST_INT)
7401 {
7402 value = INTVAL (operands[2]);
7403 emit_insn (gen_xordi3 (tmp, operands[1],
7404 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7405 }
7406 else
7407 {
7408 value = CONST_DOUBLE_LOW (operands[2]);
7409 emit_insn (gen_xordi3 (tmp, operands[1],
7410 immed_double_const (value
7411 & (~ (HOST_WIDE_INT) 0xffff),
7412 0, DImode)));
7413 }
7415 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7416 DONE;
7417 }
7418 }")
7420 (define_insn "*booldi3_internal1"
7421 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7422 (match_operator:DI 3 "boolean_or_operator"
7423 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7424 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7425 "TARGET_POWERPC64"
7426 "@
7427 %q3 %0,%1,%2
7428 %q3i %0,%1,%b2
7429 %q3is %0,%1,%u2")
7431 (define_insn "*booldi3_internal2"
7432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7433 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7434 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7435 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7436 (const_int 0)))
7437 (clobber (match_scratch:DI 3 "=r,r"))]
7438 "TARGET_64BIT"
7439 "@
7440 %q4. %3,%1,%2
7441 #"
7442 [(set_attr "type" "compare")
7443 (set_attr "length" "4,8")])
7445 (define_split
7446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7447 (compare:CC (match_operator:DI 4 "boolean_operator"
7448 [(match_operand:DI 1 "gpc_reg_operand" "")
7449 (match_operand:DI 2 "gpc_reg_operand" "")])
7450 (const_int 0)))
7451 (clobber (match_scratch:DI 3 ""))]
7452 "TARGET_POWERPC64 && reload_completed"
7453 [(set (match_dup 3) (match_dup 4))
7454 (set (match_dup 0)
7455 (compare:CC (match_dup 3)
7456 (const_int 0)))]
7457 "")
7459 (define_insn "*booldi3_internal3"
7460 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7461 (compare:CC (match_operator:DI 4 "boolean_operator"
7462 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7463 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7464 (const_int 0)))
7465 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7466 (match_dup 4))]
7467 "TARGET_64BIT"
7468 "@
7469 %q4. %0,%1,%2
7470 #"
7471 [(set_attr "type" "compare")
7472 (set_attr "length" "4,8")])
7474 (define_split
7475 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7476 (compare:CC (match_operator:DI 4 "boolean_operator"
7477 [(match_operand:DI 1 "gpc_reg_operand" "")
7478 (match_operand:DI 2 "gpc_reg_operand" "")])
7479 (const_int 0)))
7480 (set (match_operand:DI 0 "gpc_reg_operand" "")
7481 (match_dup 4))]
7482 "TARGET_POWERPC64 && reload_completed"
7483 [(set (match_dup 0) (match_dup 4))
7484 (set (match_dup 3)
7485 (compare:CC (match_dup 0)
7486 (const_int 0)))]
7487 "")
7489 ;; Split a logical operation that we can't do in one insn into two insns,
7490 ;; each of which does one 16-bit part. This is used by combine.
7492 (define_split
7493 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7494 (match_operator:DI 3 "boolean_or_operator"
7495 [(match_operand:DI 1 "gpc_reg_operand" "")
7496 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7497 "TARGET_POWERPC64"
7498 [(set (match_dup 0) (match_dup 4))
7499 (set (match_dup 0) (match_dup 5))]
7500 "
7501 {
7502 rtx i3,i4;
7504 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7505 {
7506 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7507 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7508 0, DImode);
7509 i4 = GEN_INT (value & 0xffff);
7510 }
7511 else
7512 {
7513 i3 = GEN_INT (INTVAL (operands[2])
7514 & (~ (HOST_WIDE_INT) 0xffff));
7515 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7516 }
7517 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7518 operands[1], i3);
7519 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7520 operands[0], i4);
7521 }")
7523 (define_insn "*boolcdi3_internal1"
7524 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7525 (match_operator:DI 3 "boolean_operator"
7526 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7527 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7528 "TARGET_POWERPC64"
7529 "%q3 %0,%2,%1")
7531 (define_insn "*boolcdi3_internal2"
7532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7533 (compare:CC (match_operator:DI 4 "boolean_operator"
7534 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7535 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7536 (const_int 0)))
7537 (clobber (match_scratch:DI 3 "=r,r"))]
7538 "TARGET_64BIT"
7539 "@
7540 %q4. %3,%2,%1
7541 #"
7542 [(set_attr "type" "compare")
7543 (set_attr "length" "4,8")])
7545 (define_split
7546 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7547 (compare:CC (match_operator:DI 4 "boolean_operator"
7548 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7549 (match_operand:DI 2 "gpc_reg_operand" "")])
7550 (const_int 0)))
7551 (clobber (match_scratch:DI 3 ""))]
7552 "TARGET_POWERPC64 && reload_completed"
7553 [(set (match_dup 3) (match_dup 4))
7554 (set (match_dup 0)
7555 (compare:CC (match_dup 3)
7556 (const_int 0)))]
7557 "")
7559 (define_insn "*boolcdi3_internal3"
7560 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7561 (compare:CC (match_operator:DI 4 "boolean_operator"
7562 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7563 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7564 (const_int 0)))
7565 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7566 (match_dup 4))]
7567 "TARGET_64BIT"
7568 "@
7569 %q4. %0,%2,%1
7570 #"
7571 [(set_attr "type" "compare")
7572 (set_attr "length" "4,8")])
7574 (define_split
7575 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7576 (compare:CC (match_operator:DI 4 "boolean_operator"
7577 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7578 (match_operand:DI 2 "gpc_reg_operand" "")])
7579 (const_int 0)))
7580 (set (match_operand:DI 0 "gpc_reg_operand" "")
7581 (match_dup 4))]
7582 "TARGET_POWERPC64 && reload_completed"
7583 [(set (match_dup 0) (match_dup 4))
7584 (set (match_dup 3)
7585 (compare:CC (match_dup 0)
7586 (const_int 0)))]
7587 "")
7589 (define_insn "*boolccdi3_internal1"
7590 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7591 (match_operator:DI 3 "boolean_operator"
7592 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7593 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7594 "TARGET_POWERPC64"
7595 "%q3 %0,%1,%2")
7597 (define_insn "*boolccdi3_internal2"
7598 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7599 (compare:CC (match_operator:DI 4 "boolean_operator"
7600 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7601 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7602 (const_int 0)))
7603 (clobber (match_scratch:DI 3 "=r,r"))]
7604 "TARGET_64BIT"
7605 "@
7606 %q4. %3,%1,%2
7607 #"
7608 [(set_attr "type" "compare")
7609 (set_attr "length" "4,8")])
7611 (define_split
7612 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7613 (compare:CC (match_operator:DI 4 "boolean_operator"
7614 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7615 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7616 (const_int 0)))
7617 (clobber (match_scratch:DI 3 ""))]
7618 "TARGET_POWERPC64 && reload_completed"
7619 [(set (match_dup 3) (match_dup 4))
7620 (set (match_dup 0)
7621 (compare:CC (match_dup 3)
7622 (const_int 0)))]
7623 "")
7625 (define_insn "*boolccdi3_internal3"
7626 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7627 (compare:CC (match_operator:DI 4 "boolean_operator"
7628 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7629 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7630 (const_int 0)))
7631 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7632 (match_dup 4))]
7633 "TARGET_64BIT"
7634 "@
7635 %q4. %0,%1,%2
7636 #"
7637 [(set_attr "type" "compare")
7638 (set_attr "length" "4,8")])
7640 (define_split
7641 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7642 (compare:CC (match_operator:DI 4 "boolean_operator"
7643 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7644 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7645 (const_int 0)))
7646 (set (match_operand:DI 0 "gpc_reg_operand" "")
7647 (match_dup 4))]
7648 "TARGET_POWERPC64 && reload_completed"
7649 [(set (match_dup 0) (match_dup 4))
7650 (set (match_dup 3)
7651 (compare:CC (match_dup 0)
7652 (const_int 0)))]
7653 "")
7654 \f
7655 ;; Now define ways of moving data around.
7657 ;; Elf specific ways of loading addresses for non-PIC code.
7658 ;; The output of this could be r0, but we make a very strong
7659 ;; preference for a base register because it will usually
7660 ;; be needed there.
7661 (define_insn "elf_high"
7662 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7663 (high:SI (match_operand 1 "" "")))]
7664 "TARGET_ELF && ! TARGET_64BIT"
7665 "{liu|lis} %0,%1@ha")
7667 (define_insn "elf_low"
7668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7669 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7670 (match_operand 2 "" "")))]
7671 "TARGET_ELF && ! TARGET_64BIT"
7672 "@
7673 {cal|la} %0,%2@l(%1)
7674 {ai|addic} %0,%1,%K2")
7677 ;; Set up a register with a value from the GOT table
7679 (define_expand "movsi_got"
7680 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7681 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7682 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7683 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7684 "
7685 {
7686 if (GET_CODE (operands[1]) == CONST)
7687 {
7688 rtx offset = const0_rtx;
7689 HOST_WIDE_INT value;
7691 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7692 value = INTVAL (offset);
7693 if (value != 0)
7694 {
7695 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7696 emit_insn (gen_movsi_got (tmp, operands[1]));
7697 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7698 DONE;
7699 }
7700 }
7702 operands[2] = rs6000_got_register (operands[1]);
7703 }")
7705 (define_insn "*movsi_got_internal"
7706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7707 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7708 (match_operand:SI 2 "gpc_reg_operand" "b")]
7709 UNSPEC_MOVSI_GOT))]
7710 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7711 "{l|lwz} %0,%a1@got(%2)"
7712 [(set_attr "type" "load")])
7714 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7715 ;; didn't get allocated to a hard register.
7716 (define_split
7717 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7718 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7719 (match_operand:SI 2 "memory_operand" "")]
7720 UNSPEC_MOVSI_GOT))]
7721 "DEFAULT_ABI == ABI_V4
7722 && flag_pic == 1
7723 && (reload_in_progress || reload_completed)"
7724 [(set (match_dup 0) (match_dup 2))
7725 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7726 UNSPEC_MOVSI_GOT))]
7727 "")
7729 ;; For SI, we special-case integers that can't be loaded in one insn. We
7730 ;; do the load 16-bits at a time. We could do this by loading from memory,
7731 ;; and this is even supposed to be faster, but it is simpler not to get
7732 ;; integers in the TOC.
7733 (define_expand "movsi"
7734 [(set (match_operand:SI 0 "general_operand" "")
7735 (match_operand:SI 1 "any_operand" ""))]
7736 ""
7737 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7739 (define_insn "movsi_low"
7740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7741 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7742 (match_operand 2 "" ""))))]
7743 "TARGET_MACHO && ! TARGET_64BIT"
7744 "{l|lwz} %0,lo16(%2)(%1)"
7745 [(set_attr "type" "load")
7746 (set_attr "length" "4")])
7748 (define_insn "*movsi_internal1"
7749 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7750 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7751 "gpc_reg_operand (operands[0], SImode)
7752 || gpc_reg_operand (operands[1], SImode)"
7753 "@
7754 mr %0,%1
7755 {cal|la} %0,%a1
7756 {l%U1%X1|lwz%U1%X1} %0,%1
7757 {st%U0%X0|stw%U0%X0} %1,%0
7758 {lil|li} %0,%1
7759 {liu|lis} %0,%v1
7760 #
7761 {cal|la} %0,%a1
7762 mf%1 %0
7763 mt%0 %1
7764 mt%0 %1
7765 mt%0 %1
7766 {cror 0,0,0|nop}"
7767 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7768 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7770 ;; Split a load of a large constant into the appropriate two-insn
7771 ;; sequence.
7773 (define_split
7774 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7775 (match_operand:SI 1 "const_int_operand" ""))]
7776 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7777 && (INTVAL (operands[1]) & 0xffff) != 0"
7778 [(set (match_dup 0)
7779 (match_dup 2))
7780 (set (match_dup 0)
7781 (ior:SI (match_dup 0)
7782 (match_dup 3)))]
7783 "
7784 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7786 if (tem == operands[0])
7787 DONE;
7788 else
7789 FAIL;
7790 }")
7792 (define_insn "*movsi_internal2"
7793 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7794 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7795 (const_int 0)))
7796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7797 "TARGET_32BIT"
7798 "@
7799 {cmpi|cmpwi} %2,%0,0
7800 mr. %0,%1
7801 #"
7802 [(set_attr "type" "cmp,compare,cmp")
7803 (set_attr "length" "4,4,8")])
7805 (define_split
7806 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7807 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7808 (const_int 0)))
7809 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7810 "TARGET_32BIT && reload_completed"
7811 [(set (match_dup 0) (match_dup 1))
7812 (set (match_dup 2)
7813 (compare:CC (match_dup 0)
7814 (const_int 0)))]
7815 "")
7816 \f
7817 (define_expand "movhi"
7818 [(set (match_operand:HI 0 "general_operand" "")
7819 (match_operand:HI 1 "any_operand" ""))]
7820 ""
7821 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7823 (define_insn "*movhi_internal"
7824 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7825 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7826 "gpc_reg_operand (operands[0], HImode)
7827 || gpc_reg_operand (operands[1], HImode)"
7828 "@
7829 mr %0,%1
7830 lhz%U1%X1 %0,%1
7831 sth%U0%X0 %1,%0
7832 {lil|li} %0,%w1
7833 mf%1 %0
7834 mt%0 %1
7835 mt%0 %1
7836 {cror 0,0,0|nop}"
7837 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7839 (define_expand "movqi"
7840 [(set (match_operand:QI 0 "general_operand" "")
7841 (match_operand:QI 1 "any_operand" ""))]
7842 ""
7843 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7845 (define_insn "*movqi_internal"
7846 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7847 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7848 "gpc_reg_operand (operands[0], QImode)
7849 || gpc_reg_operand (operands[1], QImode)"
7850 "@
7851 mr %0,%1
7852 lbz%U1%X1 %0,%1
7853 stb%U0%X0 %1,%0
7854 {lil|li} %0,%1
7855 mf%1 %0
7856 mt%0 %1
7857 mt%0 %1
7858 {cror 0,0,0|nop}"
7859 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7860 \f
7861 ;; Here is how to move condition codes around. When we store CC data in
7862 ;; an integer register or memory, we store just the high-order 4 bits.
7863 ;; This lets us not shift in the most common case of CR0.
7864 (define_expand "movcc"
7865 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7866 (match_operand:CC 1 "nonimmediate_operand" ""))]
7867 ""
7868 "")
7870 (define_insn "*movcc_internal1"
7871 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7872 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7873 "register_operand (operands[0], CCmode)
7874 || register_operand (operands[1], CCmode)"
7875 "@
7876 mcrf %0,%1
7877 mtcrf 128,%1
7878 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7879 mfcr %0%Q1
7880 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7881 mr %0,%1
7882 mf%1 %0
7883 mt%0 %1
7884 mt%0 %1
7885 {l%U1%X1|lwz%U1%X1} %0,%1
7886 {st%U0%U1|stw%U0%U1} %1,%0"
7887 [(set (attr "type")
7888 (cond [(eq_attr "alternative" "0")
7889 (const_string "cr_logical")
7890 (eq_attr "alternative" "1,2")
7891 (const_string "mtcr")
7892 (eq_attr "alternative" "5,7")
7893 (const_string "integer")
7894 (eq_attr "alternative" "6")
7895 (const_string "mfjmpr")
7896 (eq_attr "alternative" "8")
7897 (const_string "mtjmpr")
7898 (eq_attr "alternative" "9")
7899 (const_string "load")
7900 (eq_attr "alternative" "10")
7901 (const_string "store")
7902 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7903 (const_string "mfcrf")
7904 ]
7905 (const_string "mfcr")))
7906 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7907 \f
7908 ;; For floating-point, we normally deal with the floating-point registers
7909 ;; unless -msoft-float is used. The sole exception is that parameter passing
7910 ;; can produce floating-point values in fixed-point registers. Unless the
7911 ;; value is a simple constant or already in memory, we deal with this by
7912 ;; allocating memory and copying the value explicitly via that memory location.
7913 (define_expand "movsf"
7914 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7915 (match_operand:SF 1 "any_operand" ""))]
7916 ""
7917 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7919 (define_split
7920 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7921 (match_operand:SF 1 "const_double_operand" ""))]
7922 "reload_completed
7923 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7924 || (GET_CODE (operands[0]) == SUBREG
7925 && GET_CODE (SUBREG_REG (operands[0])) == REG
7926 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7927 [(set (match_dup 2) (match_dup 3))]
7928 "
7929 {
7930 long l;
7931 REAL_VALUE_TYPE rv;
7933 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7934 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7936 if (! TARGET_POWERPC64)
7937 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7938 else
7939 operands[2] = gen_lowpart (SImode, operands[0]);
7941 operands[3] = gen_int_mode (l, SImode);
7942 }")
7944 (define_insn "*movsf_hardfloat"
7945 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7946 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7947 "(gpc_reg_operand (operands[0], SFmode)
7948 || gpc_reg_operand (operands[1], SFmode))
7949 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7950 "@
7951 mr %0,%1
7952 {l%U1%X1|lwz%U1%X1} %0,%1
7953 {st%U0%X0|stw%U0%X0} %1,%0
7954 fmr %0,%1
7955 lfs%U1%X1 %0,%1
7956 stfs%U0%X0 %1,%0
7957 mt%0 %1
7958 mt%0 %1
7959 mf%1 %0
7960 {cror 0,0,0|nop}
7961 #
7962 #"
7963 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7964 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7966 (define_insn "*movsf_softfloat"
7967 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7968 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7969 "(gpc_reg_operand (operands[0], SFmode)
7970 || gpc_reg_operand (operands[1], SFmode))
7971 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7972 "@
7973 mr %0,%1
7974 mt%0 %1
7975 mt%0 %1
7976 mf%1 %0
7977 {l%U1%X1|lwz%U1%X1} %0,%1
7978 {st%U0%X0|stw%U0%X0} %1,%0
7979 {lil|li} %0,%1
7980 {liu|lis} %0,%v1
7981 {cal|la} %0,%a1
7982 #
7983 #
7984 {cror 0,0,0|nop}"
7985 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7986 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7988 \f
7989 (define_expand "movdf"
7990 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7991 (match_operand:DF 1 "any_operand" ""))]
7992 ""
7993 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7995 (define_split
7996 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7997 (match_operand:DF 1 "const_int_operand" ""))]
7998 "! TARGET_POWERPC64 && reload_completed
7999 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8000 || (GET_CODE (operands[0]) == SUBREG
8001 && GET_CODE (SUBREG_REG (operands[0])) == REG
8002 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8003 [(set (match_dup 2) (match_dup 4))
8004 (set (match_dup 3) (match_dup 1))]
8005 "
8006 {
8007 int endian = (WORDS_BIG_ENDIAN == 0);
8008 HOST_WIDE_INT value = INTVAL (operands[1]);
8010 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8011 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8012 #if HOST_BITS_PER_WIDE_INT == 32
8013 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8014 #else
8015 operands[4] = GEN_INT (value >> 32);
8016 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8017 #endif
8018 }")
8020 (define_split
8021 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8022 (match_operand:DF 1 "const_double_operand" ""))]
8023 "! TARGET_POWERPC64 && reload_completed
8024 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8025 || (GET_CODE (operands[0]) == SUBREG
8026 && GET_CODE (SUBREG_REG (operands[0])) == REG
8027 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8028 [(set (match_dup 2) (match_dup 4))
8029 (set (match_dup 3) (match_dup 5))]
8030 "
8031 {
8032 int endian = (WORDS_BIG_ENDIAN == 0);
8033 long l[2];
8034 REAL_VALUE_TYPE rv;
8036 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8037 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8039 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8040 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8041 operands[4] = gen_int_mode (l[endian], SImode);
8042 operands[5] = gen_int_mode (l[1 - endian], SImode);
8043 }")
8045 (define_split
8046 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8047 (match_operand:DF 1 "const_double_operand" ""))]
8048 "TARGET_POWERPC64 && reload_completed
8049 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8050 || (GET_CODE (operands[0]) == SUBREG
8051 && GET_CODE (SUBREG_REG (operands[0])) == REG
8052 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8053 [(set (match_dup 2) (match_dup 3))]
8054 "
8055 {
8056 int endian = (WORDS_BIG_ENDIAN == 0);
8057 long l[2];
8058 REAL_VALUE_TYPE rv;
8059 #if HOST_BITS_PER_WIDE_INT >= 64
8060 HOST_WIDE_INT val;
8061 #endif
8063 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8064 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8066 operands[2] = gen_lowpart (DImode, operands[0]);
8067 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8068 #if HOST_BITS_PER_WIDE_INT >= 64
8069 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8070 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8072 operands[3] = gen_int_mode (val, DImode);
8073 #else
8074 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8075 #endif
8076 }")
8078 ;; Don't have reload use general registers to load a constant. First,
8079 ;; it might not work if the output operand is the equivalent of
8080 ;; a non-offsettable memref, but also it is less efficient than loading
8081 ;; the constant into an FP register, since it will probably be used there.
8082 ;; The "??" is a kludge until we can figure out a more reasonable way
8083 ;; of handling these non-offsettable values.
8084 (define_insn "*movdf_hardfloat32"
8085 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8086 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8087 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8088 && (gpc_reg_operand (operands[0], DFmode)
8089 || gpc_reg_operand (operands[1], DFmode))"
8090 "*
8091 {
8092 switch (which_alternative)
8093 {
8094 default:
8095 abort ();
8096 case 0:
8097 /* We normally copy the low-numbered register first. However, if
8098 the first register operand 0 is the same as the second register
8099 of operand 1, we must copy in the opposite order. */
8100 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8101 return \"mr %L0,%L1\;mr %0,%1\";
8102 else
8103 return \"mr %0,%1\;mr %L0,%L1\";
8104 case 1:
8105 if (GET_CODE (operands[1]) == MEM
8106 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8107 reload_completed || reload_in_progress)
8108 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0))
8109 || GET_CODE (XEXP (operands[1], 0)) == REG
8110 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8111 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8112 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8113 {
8114 /* If the low-address word is used in the address, we must load
8115 it last. Otherwise, load it first. Note that we cannot have
8116 auto-increment in that case since the address register is
8117 known to be dead. */
8118 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8119 operands[1], 0))
8120 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8121 else
8122 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8123 }
8124 else
8125 {
8126 rtx addreg;
8128 addreg = find_addr_reg (XEXP (operands[1], 0));
8129 if (refers_to_regno_p (REGNO (operands[0]),
8130 REGNO (operands[0]) + 1,
8131 operands[1], 0))
8132 {
8133 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8134 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8135 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8136 return \"{lx|lwzx} %0,%1\";
8137 }
8138 else
8139 {
8140 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8141 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8142 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8143 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8144 return \"\";
8145 }
8146 }
8147 case 2:
8148 if (GET_CODE (operands[0]) == MEM
8149 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8150 reload_completed || reload_in_progress)
8151 || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0))
8152 || GET_CODE (XEXP (operands[0], 0)) == REG
8153 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8154 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8155 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8156 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8157 else
8158 {
8159 rtx addreg;
8161 addreg = find_addr_reg (XEXP (operands[0], 0));
8162 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8163 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8164 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8165 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8166 return \"\";
8167 }
8168 case 3:
8169 return \"fmr %0,%1\";
8170 case 4:
8171 return \"lfd%U1%X1 %0,%1\";
8172 case 5:
8173 return \"stfd%U0%X0 %1,%0\";
8174 case 6:
8175 case 7:
8176 case 8:
8177 return \"#\";
8178 }
8179 }"
8180 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8181 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8183 (define_insn "*movdf_softfloat32"
8184 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8185 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8186 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8187 && (gpc_reg_operand (operands[0], DFmode)
8188 || gpc_reg_operand (operands[1], DFmode))"
8189 "*
8190 {
8191 switch (which_alternative)
8192 {
8193 default:
8194 abort ();
8195 case 0:
8196 /* We normally copy the low-numbered register first. However, if
8197 the first register operand 0 is the same as the second register of
8198 operand 1, we must copy in the opposite order. */
8199 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8200 return \"mr %L0,%L1\;mr %0,%1\";
8201 else
8202 return \"mr %0,%1\;mr %L0,%L1\";
8203 case 1:
8204 /* If the low-address word is used in the address, we must load
8205 it last. Otherwise, load it first. Note that we cannot have
8206 auto-increment in that case since the address register is
8207 known to be dead. */
8208 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8209 operands[1], 0))
8210 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8211 else
8212 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8213 case 2:
8214 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8215 case 3:
8216 case 4:
8217 case 5:
8218 return \"#\";
8219 }
8220 }"
8221 [(set_attr "type" "two,load,store,*,*,*")
8222 (set_attr "length" "8,8,8,8,12,16")])
8224 ; ld/std require word-aligned displacements -> 'Y' constraint.
8225 ; List Y->r and r->Y before r->r for reload.
8226 (define_insn "*movdf_hardfloat64"
8227 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8228 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8229 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8230 && (gpc_reg_operand (operands[0], DFmode)
8231 || gpc_reg_operand (operands[1], DFmode))"
8232 "@
8233 std%U0%X0 %1,%0
8234 ld%U1%X1 %0,%1
8235 mr %0,%1
8236 fmr %0,%1
8237 lfd%U1%X1 %0,%1
8238 stfd%U0%X0 %1,%0
8239 mt%0 %1
8240 mf%1 %0
8241 {cror 0,0,0|nop}
8242 #
8243 #
8244 #"
8245 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8246 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8248 (define_insn "*movdf_softfloat64"
8249 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8250 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8251 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8252 && (gpc_reg_operand (operands[0], DFmode)
8253 || gpc_reg_operand (operands[1], DFmode))"
8254 "@
8255 ld%U1%X1 %0,%1
8256 std%U0%X0 %1,%0
8257 mr %0,%1
8258 mt%0 %1
8259 mf%1 %0
8260 #
8261 #
8262 #
8263 {cror 0,0,0|nop}"
8264 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8265 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8266 \f
8267 (define_expand "movtf"
8268 [(set (match_operand:TF 0 "general_operand" "")
8269 (match_operand:TF 1 "any_operand" ""))]
8270 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8271 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8272 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8274 ; It's important to list the o->f and f->o moves before f->f because
8275 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8276 ; which doesn't make progress. Likewise r->Y must be before r->r.
8277 (define_insn_and_split "*movtf_internal"
8278 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8279 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8280 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8281 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8282 && (gpc_reg_operand (operands[0], TFmode)
8283 || gpc_reg_operand (operands[1], TFmode))"
8284 "#"
8285 "&& reload_completed"
8286 [(pc)]
8287 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8288 [(set_attr "length" "8,8,8,20,20,16")])
8290 (define_expand "extenddftf2"
8291 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8292 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8293 (use (match_dup 2))])]
8294 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8295 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8296 {
8297 operands[2] = CONST0_RTX (DFmode);
8298 })
8300 (define_insn_and_split "*extenddftf2_internal"
8301 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8302 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8303 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8304 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8305 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8306 "#"
8307 "&& reload_completed"
8308 [(pc)]
8309 {
8310 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8311 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8312 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8313 operands[1]);
8314 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8315 operands[2]);
8316 DONE;
8317 })
8319 (define_expand "extendsftf2"
8320 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8321 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8322 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8323 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8324 {
8325 rtx tmp = gen_reg_rtx (DFmode);
8326 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8327 emit_insn (gen_extenddftf2 (operands[0], tmp));
8328 DONE;
8329 })
8331 (define_expand "trunctfdf2"
8332 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8333 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8334 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8335 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8336 "")
8338 (define_insn_and_split "trunctfdf2_internal1"
8339 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8340 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8341 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8342 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8343 "@
8344 #
8345 fmr %0,%1"
8346 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8347 [(const_int 0)]
8348 {
8349 emit_note (NOTE_INSN_DELETED);
8350 DONE;
8351 }
8352 [(set_attr "type" "fp")])
8354 (define_insn "trunctfdf2_internal2"
8355 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8356 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8357 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8359 "fadd %0,%1,%L1"
8360 [(set_attr "type" "fp")])
8362 (define_insn_and_split "trunctfsf2"
8363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8364 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8365 (clobber (match_scratch:DF 2 "=f"))]
8366 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8367 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8368 "#"
8369 "&& reload_completed"
8370 [(set (match_dup 2)
8371 (float_truncate:DF (match_dup 1)))
8372 (set (match_dup 0)
8373 (float_truncate:SF (match_dup 2)))]
8374 "")
8376 (define_expand "floatsitf2"
8377 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8378 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8379 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8380 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8381 {
8382 rtx tmp = gen_reg_rtx (DFmode);
8383 expand_float (tmp, operands[1], false);
8384 emit_insn (gen_extenddftf2 (operands[0], tmp));
8385 DONE;
8386 })
8388 ; fadd, but rounding towards zero.
8389 ; This is probably not the optimal code sequence.
8390 (define_insn "fix_trunc_helper"
8391 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8392 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8393 UNSPEC_FIX_TRUNC_TF))
8394 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8395 "TARGET_HARD_FLOAT && TARGET_FPRS"
8396 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8397 [(set_attr "type" "fp")
8398 (set_attr "length" "20")])
8400 (define_expand "fix_trunctfsi2"
8401 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8402 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8403 (clobber (match_dup 2))
8404 (clobber (match_dup 3))
8405 (clobber (match_dup 4))
8406 (clobber (match_dup 5))])]
8407 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8408 && (TARGET_POWER2 || TARGET_POWERPC)
8409 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8410 {
8411 operands[2] = gen_reg_rtx (DFmode);
8412 operands[3] = gen_reg_rtx (DFmode);
8413 operands[4] = gen_reg_rtx (DImode);
8414 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8415 })
8417 (define_insn_and_split "*fix_trunctfsi2_internal"
8418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8419 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8420 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8421 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8422 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8423 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8424 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8425 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8426 "#"
8427 "&& reload_completed"
8428 [(pc)]
8429 {
8430 rtx lowword;
8431 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8433 if (GET_CODE (operands[5]) != MEM)
8434 abort();
8435 lowword = XEXP (operands[5], 0);
8436 if (WORDS_BIG_ENDIAN)
8437 lowword = plus_constant (lowword, 4);
8439 emit_insn (gen_fctiwz (operands[4], operands[2]));
8440 emit_move_insn (operands[5], operands[4]);
8441 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8442 DONE;
8443 })
8445 (define_insn "negtf2"
8446 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8447 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8448 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8449 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8450 "*
8451 {
8452 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8453 return \"fneg %L0,%L1\;fneg %0,%1\";
8454 else
8455 return \"fneg %0,%1\;fneg %L0,%L1\";
8456 }"
8457 [(set_attr "type" "fp")
8458 (set_attr "length" "8")])
8460 (define_expand "abstf2"
8461 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8462 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8463 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8464 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8465 "
8466 {
8467 rtx label = gen_label_rtx ();
8468 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8469 emit_label (label);
8470 DONE;
8471 }")
8473 (define_expand "abstf2_internal"
8474 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8475 (match_operand:TF 1 "gpc_reg_operand" "f"))
8476 (set (match_dup 3) (match_dup 5))
8477 (set (match_dup 5) (abs:DF (match_dup 5)))
8478 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8479 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8480 (label_ref (match_operand 2 "" ""))
8481 (pc)))
8482 (set (match_dup 6) (neg:DF (match_dup 6)))]
8483 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8484 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8485 "
8486 {
8487 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8488 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8489 operands[3] = gen_reg_rtx (DFmode);
8490 operands[4] = gen_reg_rtx (CCFPmode);
8491 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8492 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8493 }")
8495 (define_expand "copysigntf3"
8496 [(match_operand:TF 0 "general_operand" "")
8497 (match_operand:TF 1 "general_operand" "")
8498 (match_operand:TF 2 "general_operand" "")]
8499 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8500 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8501 {
8502 rtx target, op0, op1, temp;
8503 bool op0_is_abs = false;
8505 target = operands[0];
8506 op0 = operands[1];
8507 op1 = operands[2];
8509 if (GET_CODE (op0) == CONST_DOUBLE)
8510 {
8511 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
8512 op0 = simplify_unary_operation (ABS, TFmode, op0, TFmode);
8513 op0_is_abs = true;
8514 }
8516 temp = expand_copysign_absneg (TFmode, op0, op1, target, 127, op0_is_abs);
8517 if (temp != target)
8518 emit_move_insn (target, temp);
8519 DONE;
8520 })
8521 \f
8522 ;; Next come the multi-word integer load and store and the load and store
8523 ;; multiple insns.
8524 (define_expand "movdi"
8525 [(set (match_operand:DI 0 "general_operand" "")
8526 (match_operand:DI 1 "any_operand" ""))]
8527 ""
8528 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8530 ; List r->r after r->"o<>", otherwise reload will try to reload a
8531 ; non-offsettable address by using r->r which won't make progress.
8532 (define_insn "*movdi_internal32"
8533 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8534 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8535 "! TARGET_POWERPC64
8536 && (gpc_reg_operand (operands[0], DImode)
8537 || gpc_reg_operand (operands[1], DImode))"
8538 "@
8539 #
8540 #
8541 #
8542 fmr %0,%1
8543 lfd%U1%X1 %0,%1
8544 stfd%U0%X0 %1,%0
8545 #"
8546 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8548 (define_split
8549 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8550 (match_operand:DI 1 "const_int_operand" ""))]
8551 "! TARGET_POWERPC64 && reload_completed"
8552 [(set (match_dup 2) (match_dup 4))
8553 (set (match_dup 3) (match_dup 1))]
8554 "
8555 {
8556 HOST_WIDE_INT value = INTVAL (operands[1]);
8557 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8558 DImode);
8559 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8560 DImode);
8561 #if HOST_BITS_PER_WIDE_INT == 32
8562 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8563 #else
8564 operands[4] = GEN_INT (value >> 32);
8565 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8566 #endif
8567 }")
8569 (define_split
8570 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8571 (match_operand:DI 1 "input_operand" ""))]
8572 "reload_completed && !TARGET_POWERPC64
8573 && gpr_or_gpr_p (operands[0], operands[1])"
8574 [(pc)]
8575 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8577 (define_insn "*movdi_internal64"
8578 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8579 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8580 "TARGET_POWERPC64
8581 && (gpc_reg_operand (operands[0], DImode)
8582 || gpc_reg_operand (operands[1], DImode))"
8583 "@
8584 mr %0,%1
8585 ld%U1%X1 %0,%1
8586 std%U0%X0 %1,%0
8587 li %0,%1
8588 lis %0,%v1
8589 #
8590 {cal|la} %0,%a1
8591 fmr %0,%1
8592 lfd%U1%X1 %0,%1
8593 stfd%U0%X0 %1,%0
8594 mf%1 %0
8595 mt%0 %1
8596 {cror 0,0,0|nop}"
8597 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8598 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8600 ;; immediate value valid for a single instruction hiding in a const_double
8601 (define_insn ""
8602 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8603 (match_operand:DI 1 "const_double_operand" "F"))]
8604 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8605 && GET_CODE (operands[1]) == CONST_DOUBLE
8606 && num_insns_constant (operands[1], DImode) == 1"
8607 "*
8608 {
8609 return ((unsigned HOST_WIDE_INT)
8610 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8611 ? \"li %0,%1\" : \"lis %0,%v1\";
8612 }")
8614 ;; Generate all one-bits and clear left or right.
8615 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8616 (define_split
8617 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8618 (match_operand:DI 1 "mask64_operand" ""))]
8619 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8620 [(set (match_dup 0) (const_int -1))
8621 (set (match_dup 0)
8622 (and:DI (rotate:DI (match_dup 0)
8623 (const_int 0))
8624 (match_dup 1)))]
8625 "")
8627 ;; Split a load of a large constant into the appropriate five-instruction
8628 ;; sequence. Handle anything in a constant number of insns.
8629 ;; When non-easy constants can go in the TOC, this should use
8630 ;; easy_fp_constant predicate.
8631 (define_split
8632 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8633 (match_operand:DI 1 "const_int_operand" ""))]
8634 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8635 [(set (match_dup 0) (match_dup 2))
8636 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8637 "
8638 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8640 if (tem == operands[0])
8641 DONE;
8642 else
8643 FAIL;
8644 }")
8646 (define_split
8647 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8648 (match_operand:DI 1 "const_double_operand" ""))]
8649 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8650 [(set (match_dup 0) (match_dup 2))
8651 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8652 "
8653 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8655 if (tem == operands[0])
8656 DONE;
8657 else
8658 FAIL;
8659 }")
8661 (define_insn "*movdi_internal2"
8662 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8663 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8664 (const_int 0)))
8665 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8666 "TARGET_64BIT"
8667 "@
8668 cmpdi %2,%0,0
8669 mr. %0,%1
8670 #"
8671 [(set_attr "type" "cmp,compare,cmp")
8672 (set_attr "length" "4,4,8")])
8674 (define_split
8675 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8676 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8677 (const_int 0)))
8678 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8679 "TARGET_POWERPC64 && reload_completed"
8680 [(set (match_dup 0) (match_dup 1))
8681 (set (match_dup 2)
8682 (compare:CC (match_dup 0)
8683 (const_int 0)))]
8684 "")
8685 \f
8686 ;; TImode is similar, except that we usually want to compute the address into
8687 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8688 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8689 (define_expand "movti"
8690 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8691 (match_operand:TI 1 "general_operand" ""))
8692 (clobber (scratch:SI))])]
8693 ""
8694 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8696 ;; We say that MQ is clobbered in the last alternative because the first
8697 ;; alternative would never get used otherwise since it would need a reload
8698 ;; while the 2nd alternative would not. We put memory cases first so they
8699 ;; are preferred. Otherwise, we'd try to reload the output instead of
8700 ;; giving the SCRATCH mq.
8702 (define_insn "*movti_power"
8703 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8704 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8705 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8706 "TARGET_POWER && ! TARGET_POWERPC64
8707 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8708 "*
8709 {
8710 switch (which_alternative)
8711 {
8712 default:
8713 abort ();
8715 case 0:
8716 if (TARGET_STRING)
8717 return \"{stsi|stswi} %1,%P0,16\";
8718 case 1:
8719 case 2:
8720 return \"#\";
8721 case 3:
8722 /* If the address is not used in the output, we can use lsi. Otherwise,
8723 fall through to generating four loads. */
8724 if (TARGET_STRING
8725 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8726 return \"{lsi|lswi} %0,%P1,16\";
8727 /* ... fall through ... */
8728 case 4:
8729 case 5:
8730 return \"#\";
8731 }
8732 }"
8733 [(set_attr "type" "store,store,*,load,load,*")])
8735 (define_insn "*movti_string"
8736 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8737 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8738 "! TARGET_POWER && ! TARGET_POWERPC64
8739 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8740 "*
8741 {
8742 switch (which_alternative)
8743 {
8744 default:
8745 abort ();
8746 case 0:
8747 if (TARGET_STRING)
8748 return \"{stsi|stswi} %1,%P0,16\";
8749 case 1:
8750 case 2:
8751 return \"#\";
8752 case 3:
8753 /* If the address is not used in the output, we can use lsi. Otherwise,
8754 fall through to generating four loads. */
8755 if (TARGET_STRING
8756 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8757 return \"{lsi|lswi} %0,%P1,16\";
8758 /* ... fall through ... */
8759 case 4:
8760 case 5:
8761 return \"#\";
8762 }
8763 }"
8764 [(set_attr "type" "store,store,*,load,load,*")])
8766 (define_insn "*movti_ppc64"
8767 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8768 (match_operand:TI 1 "input_operand" "r,r,m"))]
8769 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8770 || gpc_reg_operand (operands[1], TImode))"
8771 "#"
8772 [(set_attr "type" "*,load,store")])
8774 (define_split
8775 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8776 (match_operand:TI 1 "const_double_operand" ""))]
8777 "TARGET_POWERPC64"
8778 [(set (match_dup 2) (match_dup 4))
8779 (set (match_dup 3) (match_dup 5))]
8780 "
8781 {
8782 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8783 TImode);
8784 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8785 TImode);
8786 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8787 {
8788 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8789 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8790 }
8791 else if (GET_CODE (operands[1]) == CONST_INT)
8792 {
8793 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8794 operands[5] = operands[1];
8795 }
8796 else
8797 FAIL;
8798 }")
8800 (define_split
8801 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8802 (match_operand:TI 1 "input_operand" ""))]
8803 "reload_completed
8804 && gpr_or_gpr_p (operands[0], operands[1])"
8805 [(pc)]
8806 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8807 \f
8808 (define_expand "load_multiple"
8809 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8810 (match_operand:SI 1 "" ""))
8811 (use (match_operand:SI 2 "" ""))])]
8812 "TARGET_STRING && !TARGET_POWERPC64"
8813 "
8814 {
8815 int regno;
8816 int count;
8817 rtx op1;
8818 int i;
8820 /* Support only loading a constant number of fixed-point registers from
8821 memory and only bother with this if more than two; the machine
8822 doesn't support more than eight. */
8823 if (GET_CODE (operands[2]) != CONST_INT
8824 || INTVAL (operands[2]) <= 2
8825 || INTVAL (operands[2]) > 8
8826 || GET_CODE (operands[1]) != MEM
8827 || GET_CODE (operands[0]) != REG
8828 || REGNO (operands[0]) >= 32)
8829 FAIL;
8831 count = INTVAL (operands[2]);
8832 regno = REGNO (operands[0]);
8834 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8835 op1 = replace_equiv_address (operands[1],
8836 force_reg (SImode, XEXP (operands[1], 0)));
8838 for (i = 0; i < count; i++)
8839 XVECEXP (operands[3], 0, i)
8840 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8841 adjust_address_nv (op1, SImode, i * 4));
8842 }")
8844 (define_insn "*ldmsi8"
8845 [(match_parallel 0 "load_multiple_operation"
8846 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8848 (set (match_operand:SI 3 "gpc_reg_operand" "")
8849 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8850 (set (match_operand:SI 4 "gpc_reg_operand" "")
8851 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8852 (set (match_operand:SI 5 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8854 (set (match_operand:SI 6 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8856 (set (match_operand:SI 7 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8858 (set (match_operand:SI 8 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8860 (set (match_operand:SI 9 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8863 "*
8864 { return rs6000_output_load_multiple (operands); }"
8865 [(set_attr "type" "load")
8866 (set_attr "length" "32")])
8868 (define_insn "*ldmsi7"
8869 [(match_parallel 0 "load_multiple_operation"
8870 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8871 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8872 (set (match_operand:SI 3 "gpc_reg_operand" "")
8873 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8874 (set (match_operand:SI 4 "gpc_reg_operand" "")
8875 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8876 (set (match_operand:SI 5 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8878 (set (match_operand:SI 6 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8880 (set (match_operand:SI 7 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8882 (set (match_operand:SI 8 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8884 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8885 "*
8886 { return rs6000_output_load_multiple (operands); }"
8887 [(set_attr "type" "load")
8888 (set_attr "length" "32")])
8890 (define_insn "*ldmsi6"
8891 [(match_parallel 0 "load_multiple_operation"
8892 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8893 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8894 (set (match_operand:SI 3 "gpc_reg_operand" "")
8895 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8896 (set (match_operand:SI 4 "gpc_reg_operand" "")
8897 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8898 (set (match_operand:SI 5 "gpc_reg_operand" "")
8899 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8900 (set (match_operand:SI 6 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8902 (set (match_operand:SI 7 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8904 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8905 "*
8906 { return rs6000_output_load_multiple (operands); }"
8907 [(set_attr "type" "load")
8908 (set_attr "length" "32")])
8910 (define_insn "*ldmsi5"
8911 [(match_parallel 0 "load_multiple_operation"
8912 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8913 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8914 (set (match_operand:SI 3 "gpc_reg_operand" "")
8915 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8916 (set (match_operand:SI 4 "gpc_reg_operand" "")
8917 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8918 (set (match_operand:SI 5 "gpc_reg_operand" "")
8919 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8920 (set (match_operand:SI 6 "gpc_reg_operand" "")
8921 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8922 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8923 "*
8924 { return rs6000_output_load_multiple (operands); }"
8925 [(set_attr "type" "load")
8926 (set_attr "length" "32")])
8928 (define_insn "*ldmsi4"
8929 [(match_parallel 0 "load_multiple_operation"
8930 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8931 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8932 (set (match_operand:SI 3 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8934 (set (match_operand:SI 4 "gpc_reg_operand" "")
8935 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8936 (set (match_operand:SI 5 "gpc_reg_operand" "")
8937 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8938 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8939 "*
8940 { return rs6000_output_load_multiple (operands); }"
8941 [(set_attr "type" "load")
8942 (set_attr "length" "32")])
8944 (define_insn "*ldmsi3"
8945 [(match_parallel 0 "load_multiple_operation"
8946 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8947 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8948 (set (match_operand:SI 3 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8950 (set (match_operand:SI 4 "gpc_reg_operand" "")
8951 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8952 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8953 "*
8954 { return rs6000_output_load_multiple (operands); }"
8955 [(set_attr "type" "load")
8956 (set_attr "length" "32")])
8958 (define_expand "store_multiple"
8959 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8960 (match_operand:SI 1 "" ""))
8961 (clobber (scratch:SI))
8962 (use (match_operand:SI 2 "" ""))])]
8963 "TARGET_STRING && !TARGET_POWERPC64"
8964 "
8965 {
8966 int regno;
8967 int count;
8968 rtx to;
8969 rtx op0;
8970 int i;
8972 /* Support only storing a constant number of fixed-point registers to
8973 memory and only bother with this if more than two; the machine
8974 doesn't support more than eight. */
8975 if (GET_CODE (operands[2]) != CONST_INT
8976 || INTVAL (operands[2]) <= 2
8977 || INTVAL (operands[2]) > 8
8978 || GET_CODE (operands[0]) != MEM
8979 || GET_CODE (operands[1]) != REG
8980 || REGNO (operands[1]) >= 32)
8981 FAIL;
8983 count = INTVAL (operands[2]);
8984 regno = REGNO (operands[1]);
8986 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8987 to = force_reg (SImode, XEXP (operands[0], 0));
8988 op0 = replace_equiv_address (operands[0], to);
8990 XVECEXP (operands[3], 0, 0)
8991 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8992 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8993 gen_rtx_SCRATCH (SImode));
8995 for (i = 1; i < count; i++)
8996 XVECEXP (operands[3], 0, i + 1)
8997 = gen_rtx_SET (VOIDmode,
8998 adjust_address_nv (op0, SImode, i * 4),
8999 gen_rtx_REG (SImode, regno + i));
9000 }")
9002 (define_insn "*store_multiple_power"
9003 [(match_parallel 0 "store_multiple_operation"
9004 [(set (match_operand:SI 1 "indirect_operand" "=Q")
9005 (match_operand:SI 2 "gpc_reg_operand" "r"))
9006 (clobber (match_scratch:SI 3 "=q"))])]
9007 "TARGET_STRING && TARGET_POWER"
9008 "{stsi|stswi} %2,%P1,%O0"
9009 [(set_attr "type" "store")])
9011 (define_insn "*stmsi8"
9012 [(match_parallel 0 "store_multiple_operation"
9013 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9014 (match_operand:SI 2 "gpc_reg_operand" "r"))
9015 (clobber (match_scratch:SI 3 "X"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9017 (match_operand:SI 4 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9019 (match_operand:SI 5 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9021 (match_operand:SI 6 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9023 (match_operand:SI 7 "gpc_reg_operand" "r"))
9024 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9025 (match_operand:SI 8 "gpc_reg_operand" "r"))
9026 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9027 (match_operand:SI 9 "gpc_reg_operand" "r"))
9028 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9029 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9030 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9031 "{stsi|stswi} %2,%1,%O0"
9032 [(set_attr "type" "store")])
9034 (define_insn "*stmsi7"
9035 [(match_parallel 0 "store_multiple_operation"
9036 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9037 (match_operand:SI 2 "gpc_reg_operand" "r"))
9038 (clobber (match_scratch:SI 3 "X"))
9039 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9040 (match_operand:SI 4 "gpc_reg_operand" "r"))
9041 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9042 (match_operand:SI 5 "gpc_reg_operand" "r"))
9043 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9044 (match_operand:SI 6 "gpc_reg_operand" "r"))
9045 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9046 (match_operand:SI 7 "gpc_reg_operand" "r"))
9047 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9048 (match_operand:SI 8 "gpc_reg_operand" "r"))
9049 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9050 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9051 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9052 "{stsi|stswi} %2,%1,%O0"
9053 [(set_attr "type" "store")])
9055 (define_insn "*stmsi6"
9056 [(match_parallel 0 "store_multiple_operation"
9057 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9058 (match_operand:SI 2 "gpc_reg_operand" "r"))
9059 (clobber (match_scratch:SI 3 "X"))
9060 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9061 (match_operand:SI 4 "gpc_reg_operand" "r"))
9062 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9063 (match_operand:SI 5 "gpc_reg_operand" "r"))
9064 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9065 (match_operand:SI 6 "gpc_reg_operand" "r"))
9066 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9067 (match_operand:SI 7 "gpc_reg_operand" "r"))
9068 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9069 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9070 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9071 "{stsi|stswi} %2,%1,%O0"
9072 [(set_attr "type" "store")])
9074 (define_insn "*stmsi5"
9075 [(match_parallel 0 "store_multiple_operation"
9076 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9077 (match_operand:SI 2 "gpc_reg_operand" "r"))
9078 (clobber (match_scratch:SI 3 "X"))
9079 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9080 (match_operand:SI 4 "gpc_reg_operand" "r"))
9081 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9082 (match_operand:SI 5 "gpc_reg_operand" "r"))
9083 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9084 (match_operand:SI 6 "gpc_reg_operand" "r"))
9085 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9086 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9087 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9088 "{stsi|stswi} %2,%1,%O0"
9089 [(set_attr "type" "store")])
9091 (define_insn "*stmsi4"
9092 [(match_parallel 0 "store_multiple_operation"
9093 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9094 (match_operand:SI 2 "gpc_reg_operand" "r"))
9095 (clobber (match_scratch:SI 3 "X"))
9096 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9097 (match_operand:SI 4 "gpc_reg_operand" "r"))
9098 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9099 (match_operand:SI 5 "gpc_reg_operand" "r"))
9100 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9101 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9102 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9103 "{stsi|stswi} %2,%1,%O0"
9104 [(set_attr "type" "store")])
9106 (define_insn "*stmsi3"
9107 [(match_parallel 0 "store_multiple_operation"
9108 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9109 (match_operand:SI 2 "gpc_reg_operand" "r"))
9110 (clobber (match_scratch:SI 3 "X"))
9111 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9112 (match_operand:SI 4 "gpc_reg_operand" "r"))
9113 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9114 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9115 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9116 "{stsi|stswi} %2,%1,%O0"
9117 [(set_attr "type" "store")])
9118 \f
9119 (define_expand "clrmemsi"
9120 [(parallel [(set (match_operand:BLK 0 "" "")
9121 (const_int 0))
9122 (use (match_operand:SI 1 "" ""))
9123 (use (match_operand:SI 2 "" ""))])]
9124 ""
9125 "
9126 {
9127 if (expand_block_clear (operands))
9128 DONE;
9129 else
9130 FAIL;
9131 }")
9133 ;; String/block move insn.
9134 ;; Argument 0 is the destination
9135 ;; Argument 1 is the source
9136 ;; Argument 2 is the length
9137 ;; Argument 3 is the alignment
9139 (define_expand "movmemsi"
9140 [(parallel [(set (match_operand:BLK 0 "" "")
9141 (match_operand:BLK 1 "" ""))
9142 (use (match_operand:SI 2 "" ""))
9143 (use (match_operand:SI 3 "" ""))])]
9144 ""
9145 "
9146 {
9147 if (expand_block_move (operands))
9148 DONE;
9149 else
9150 FAIL;
9151 }")
9153 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9154 ;; register allocator doesn't have a clue about allocating 8 word registers.
9155 ;; rD/rS = r5 is preferred, efficient form.
9156 (define_expand "movmemsi_8reg"
9157 [(parallel [(set (match_operand 0 "" "")
9158 (match_operand 1 "" ""))
9159 (use (match_operand 2 "" ""))
9160 (use (match_operand 3 "" ""))
9161 (clobber (reg:SI 5))
9162 (clobber (reg:SI 6))
9163 (clobber (reg:SI 7))
9164 (clobber (reg:SI 8))
9165 (clobber (reg:SI 9))
9166 (clobber (reg:SI 10))
9167 (clobber (reg:SI 11))
9168 (clobber (reg:SI 12))
9169 (clobber (match_scratch:SI 4 ""))])]
9170 "TARGET_STRING"
9171 "")
9173 (define_insn ""
9174 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9175 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9176 (use (match_operand:SI 2 "immediate_operand" "i"))
9177 (use (match_operand:SI 3 "immediate_operand" "i"))
9178 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9179 (clobber (reg:SI 6))
9180 (clobber (reg:SI 7))
9181 (clobber (reg:SI 8))
9182 (clobber (reg:SI 9))
9183 (clobber (reg:SI 10))
9184 (clobber (reg:SI 11))
9185 (clobber (reg:SI 12))
9186 (clobber (match_scratch:SI 5 "=q"))]
9187 "TARGET_STRING && TARGET_POWER
9188 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9189 || INTVAL (operands[2]) == 0)
9190 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9191 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9192 && REGNO (operands[4]) == 5"
9193 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9194 [(set_attr "type" "load")
9195 (set_attr "length" "8")])
9197 (define_insn ""
9198 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9199 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9200 (use (match_operand:SI 2 "immediate_operand" "i"))
9201 (use (match_operand:SI 3 "immediate_operand" "i"))
9202 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9203 (clobber (reg:SI 6))
9204 (clobber (reg:SI 7))
9205 (clobber (reg:SI 8))
9206 (clobber (reg:SI 9))
9207 (clobber (reg:SI 10))
9208 (clobber (reg:SI 11))
9209 (clobber (reg:SI 12))
9210 (clobber (match_scratch:SI 5 "X"))]
9211 "TARGET_STRING && ! TARGET_POWER
9212 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9213 || INTVAL (operands[2]) == 0)
9214 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9215 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9216 && REGNO (operands[4]) == 5"
9217 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9218 [(set_attr "type" "load")
9219 (set_attr "length" "8")])
9221 (define_insn ""
9222 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9223 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9224 (use (match_operand:SI 2 "immediate_operand" "i"))
9225 (use (match_operand:SI 3 "immediate_operand" "i"))
9226 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9227 (clobber (reg:SI 6))
9228 (clobber (reg:SI 7))
9229 (clobber (reg:SI 8))
9230 (clobber (reg:SI 9))
9231 (clobber (reg:SI 10))
9232 (clobber (reg:SI 11))
9233 (clobber (reg:SI 12))
9234 (clobber (match_scratch:SI 5 "X"))]
9235 "TARGET_STRING && TARGET_POWERPC64
9236 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9237 || INTVAL (operands[2]) == 0)
9238 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9239 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9240 && REGNO (operands[4]) == 5"
9241 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9242 [(set_attr "type" "load")
9243 (set_attr "length" "8")])
9245 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9246 ;; register allocator doesn't have a clue about allocating 6 word registers.
9247 ;; rD/rS = r5 is preferred, efficient form.
9248 (define_expand "movmemsi_6reg"
9249 [(parallel [(set (match_operand 0 "" "")
9250 (match_operand 1 "" ""))
9251 (use (match_operand 2 "" ""))
9252 (use (match_operand 3 "" ""))
9253 (clobber (reg:SI 5))
9254 (clobber (reg:SI 6))
9255 (clobber (reg:SI 7))
9256 (clobber (reg:SI 8))
9257 (clobber (reg:SI 9))
9258 (clobber (reg:SI 10))
9259 (clobber (match_scratch:SI 4 ""))])]
9260 "TARGET_STRING"
9261 "")
9263 (define_insn ""
9264 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9265 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9266 (use (match_operand:SI 2 "immediate_operand" "i"))
9267 (use (match_operand:SI 3 "immediate_operand" "i"))
9268 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9269 (clobber (reg:SI 6))
9270 (clobber (reg:SI 7))
9271 (clobber (reg:SI 8))
9272 (clobber (reg:SI 9))
9273 (clobber (reg:SI 10))
9274 (clobber (match_scratch:SI 5 "=q"))]
9275 "TARGET_STRING && TARGET_POWER
9276 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9277 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9278 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9279 && REGNO (operands[4]) == 5"
9280 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9281 [(set_attr "type" "load")
9282 (set_attr "length" "8")])
9284 (define_insn ""
9285 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9286 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9287 (use (match_operand:SI 2 "immediate_operand" "i"))
9288 (use (match_operand:SI 3 "immediate_operand" "i"))
9289 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9290 (clobber (reg:SI 6))
9291 (clobber (reg:SI 7))
9292 (clobber (reg:SI 8))
9293 (clobber (reg:SI 9))
9294 (clobber (reg:SI 10))
9295 (clobber (match_scratch:SI 5 "X"))]
9296 "TARGET_STRING && ! TARGET_POWER
9297 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9298 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9299 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9300 && REGNO (operands[4]) == 5"
9301 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9302 [(set_attr "type" "load")
9303 (set_attr "length" "8")])
9305 (define_insn ""
9306 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9307 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9308 (use (match_operand:SI 2 "immediate_operand" "i"))
9309 (use (match_operand:SI 3 "immediate_operand" "i"))
9310 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9311 (clobber (reg:SI 6))
9312 (clobber (reg:SI 7))
9313 (clobber (reg:SI 8))
9314 (clobber (reg:SI 9))
9315 (clobber (reg:SI 10))
9316 (clobber (match_scratch:SI 5 "X"))]
9317 "TARGET_STRING && TARGET_POWERPC64
9318 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9319 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9320 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9321 && REGNO (operands[4]) == 5"
9322 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9323 [(set_attr "type" "load")
9324 (set_attr "length" "8")])
9326 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9327 ;; problems with TImode.
9328 ;; rD/rS = r5 is preferred, efficient form.
9329 (define_expand "movmemsi_4reg"
9330 [(parallel [(set (match_operand 0 "" "")
9331 (match_operand 1 "" ""))
9332 (use (match_operand 2 "" ""))
9333 (use (match_operand 3 "" ""))
9334 (clobber (reg:SI 5))
9335 (clobber (reg:SI 6))
9336 (clobber (reg:SI 7))
9337 (clobber (reg:SI 8))
9338 (clobber (match_scratch:SI 4 ""))])]
9339 "TARGET_STRING"
9340 "")
9342 (define_insn ""
9343 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9344 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9345 (use (match_operand:SI 2 "immediate_operand" "i"))
9346 (use (match_operand:SI 3 "immediate_operand" "i"))
9347 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9348 (clobber (reg:SI 6))
9349 (clobber (reg:SI 7))
9350 (clobber (reg:SI 8))
9351 (clobber (match_scratch:SI 5 "=q"))]
9352 "TARGET_STRING && TARGET_POWER
9353 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9354 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9355 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9356 && REGNO (operands[4]) == 5"
9357 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9358 [(set_attr "type" "load")
9359 (set_attr "length" "8")])
9361 (define_insn ""
9362 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9363 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9364 (use (match_operand:SI 2 "immediate_operand" "i"))
9365 (use (match_operand:SI 3 "immediate_operand" "i"))
9366 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9367 (clobber (reg:SI 6))
9368 (clobber (reg:SI 7))
9369 (clobber (reg:SI 8))
9370 (clobber (match_scratch:SI 5 "X"))]
9371 "TARGET_STRING && ! TARGET_POWER
9372 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9373 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9374 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9375 && REGNO (operands[4]) == 5"
9376 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9377 [(set_attr "type" "load")
9378 (set_attr "length" "8")])
9380 (define_insn ""
9381 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9382 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9383 (use (match_operand:SI 2 "immediate_operand" "i"))
9384 (use (match_operand:SI 3 "immediate_operand" "i"))
9385 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9386 (clobber (reg:SI 6))
9387 (clobber (reg:SI 7))
9388 (clobber (reg:SI 8))
9389 (clobber (match_scratch:SI 5 "X"))]
9390 "TARGET_STRING && TARGET_POWERPC64
9391 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9392 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9393 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9394 && REGNO (operands[4]) == 5"
9395 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9396 [(set_attr "type" "load")
9397 (set_attr "length" "8")])
9399 ;; Move up to 8 bytes at a time.
9400 (define_expand "movmemsi_2reg"
9401 [(parallel [(set (match_operand 0 "" "")
9402 (match_operand 1 "" ""))
9403 (use (match_operand 2 "" ""))
9404 (use (match_operand 3 "" ""))
9405 (clobber (match_scratch:DI 4 ""))
9406 (clobber (match_scratch:SI 5 ""))])]
9407 "TARGET_STRING && ! TARGET_POWERPC64"
9408 "")
9410 (define_insn ""
9411 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9412 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9413 (use (match_operand:SI 2 "immediate_operand" "i"))
9414 (use (match_operand:SI 3 "immediate_operand" "i"))
9415 (clobber (match_scratch:DI 4 "=&r"))
9416 (clobber (match_scratch:SI 5 "=q"))]
9417 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9418 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9419 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9420 [(set_attr "type" "load")
9421 (set_attr "length" "8")])
9423 (define_insn ""
9424 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9425 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9426 (use (match_operand:SI 2 "immediate_operand" "i"))
9427 (use (match_operand:SI 3 "immediate_operand" "i"))
9428 (clobber (match_scratch:DI 4 "=&r"))
9429 (clobber (match_scratch:SI 5 "X"))]
9430 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9431 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9432 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9433 [(set_attr "type" "load")
9434 (set_attr "length" "8")])
9436 ;; Move up to 4 bytes at a time.
9437 (define_expand "movmemsi_1reg"
9438 [(parallel [(set (match_operand 0 "" "")
9439 (match_operand 1 "" ""))
9440 (use (match_operand 2 "" ""))
9441 (use (match_operand 3 "" ""))
9442 (clobber (match_scratch:SI 4 ""))
9443 (clobber (match_scratch:SI 5 ""))])]
9444 "TARGET_STRING"
9445 "")
9447 (define_insn ""
9448 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9449 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9450 (use (match_operand:SI 2 "immediate_operand" "i"))
9451 (use (match_operand:SI 3 "immediate_operand" "i"))
9452 (clobber (match_scratch:SI 4 "=&r"))
9453 (clobber (match_scratch:SI 5 "=q"))]
9454 "TARGET_STRING && TARGET_POWER
9455 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9456 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9457 [(set_attr "type" "load")
9458 (set_attr "length" "8")])
9460 (define_insn ""
9461 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9462 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9463 (use (match_operand:SI 2 "immediate_operand" "i"))
9464 (use (match_operand:SI 3 "immediate_operand" "i"))
9465 (clobber (match_scratch:SI 4 "=&r"))
9466 (clobber (match_scratch:SI 5 "X"))]
9467 "TARGET_STRING && ! TARGET_POWER
9468 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9469 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9470 [(set_attr "type" "load")
9471 (set_attr "length" "8")])
9473 (define_insn ""
9474 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9475 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9476 (use (match_operand:SI 2 "immediate_operand" "i"))
9477 (use (match_operand:SI 3 "immediate_operand" "i"))
9478 (clobber (match_scratch:SI 4 "=&r"))
9479 (clobber (match_scratch:SI 5 "X"))]
9480 "TARGET_STRING && TARGET_POWERPC64
9481 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9482 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9483 [(set_attr "type" "load")
9484 (set_attr "length" "8")])
9486 \f
9487 ;; Define insns that do load or store with update. Some of these we can
9488 ;; get by using pre-decrement or pre-increment, but the hardware can also
9489 ;; do cases where the increment is not the size of the object.
9490 ;;
9491 ;; In all these cases, we use operands 0 and 1 for the register being
9492 ;; incremented because those are the operands that local-alloc will
9493 ;; tie and these are the pair most likely to be tieable (and the ones
9494 ;; that will benefit the most).
9496 (define_insn "*movdi_update1"
9497 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9498 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9500 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9501 (plus:DI (match_dup 1) (match_dup 2)))]
9502 "TARGET_POWERPC64 && TARGET_UPDATE"
9503 "@
9504 ldux %3,%0,%2
9505 ldu %3,%2(%0)"
9506 [(set_attr "type" "load_ux,load_u")])
9508 (define_insn "movdi_<mode>_update"
9509 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9510 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9511 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9512 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9513 (plus:P (match_dup 1) (match_dup 2)))]
9514 "TARGET_POWERPC64 && TARGET_UPDATE"
9515 "@
9516 stdux %3,%0,%2
9517 stdu %3,%2(%0)"
9518 [(set_attr "type" "store_ux,store_u")])
9520 (define_insn "*movsi_update1"
9521 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9522 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9523 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9525 (plus:SI (match_dup 1) (match_dup 2)))]
9526 "TARGET_UPDATE"
9527 "@
9528 {lux|lwzux} %3,%0,%2
9529 {lu|lwzu} %3,%2(%0)"
9530 [(set_attr "type" "load_ux,load_u")])
9532 (define_insn "*movsi_update2"
9533 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9534 (sign_extend:DI
9535 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9536 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9537 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9538 (plus:DI (match_dup 1) (match_dup 2)))]
9539 "TARGET_POWERPC64"
9540 "lwaux %3,%0,%2"
9541 [(set_attr "type" "load_ext_ux")])
9543 (define_insn "movsi_update"
9544 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9545 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9546 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9547 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9548 (plus:SI (match_dup 1) (match_dup 2)))]
9549 "TARGET_UPDATE"
9550 "@
9551 {stux|stwux} %3,%0,%2
9552 {stu|stwu} %3,%2(%0)"
9553 [(set_attr "type" "store_ux,store_u")])
9555 (define_insn "*movhi_update1"
9556 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9557 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9558 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9559 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9560 (plus:SI (match_dup 1) (match_dup 2)))]
9561 "TARGET_UPDATE"
9562 "@
9563 lhzux %3,%0,%2
9564 lhzu %3,%2(%0)"
9565 [(set_attr "type" "load_ux,load_u")])
9567 (define_insn "*movhi_update2"
9568 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9569 (zero_extend:SI
9570 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9571 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9572 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9573 (plus:SI (match_dup 1) (match_dup 2)))]
9574 "TARGET_UPDATE"
9575 "@
9576 lhzux %3,%0,%2
9577 lhzu %3,%2(%0)"
9578 [(set_attr "type" "load_ux,load_u")])
9580 (define_insn "*movhi_update3"
9581 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9582 (sign_extend:SI
9583 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9584 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9585 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9586 (plus:SI (match_dup 1) (match_dup 2)))]
9587 "TARGET_UPDATE"
9588 "@
9589 lhaux %3,%0,%2
9590 lhau %3,%2(%0)"
9591 [(set_attr "type" "load_ext_ux,load_ext_u")])
9593 (define_insn "*movhi_update4"
9594 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9595 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9596 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9597 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9598 (plus:SI (match_dup 1) (match_dup 2)))]
9599 "TARGET_UPDATE"
9600 "@
9601 sthux %3,%0,%2
9602 sthu %3,%2(%0)"
9603 [(set_attr "type" "store_ux,store_u")])
9605 (define_insn "*movqi_update1"
9606 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9607 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9608 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9609 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9610 (plus:SI (match_dup 1) (match_dup 2)))]
9611 "TARGET_UPDATE"
9612 "@
9613 lbzux %3,%0,%2
9614 lbzu %3,%2(%0)"
9615 [(set_attr "type" "load_ux,load_u")])
9617 (define_insn "*movqi_update2"
9618 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9619 (zero_extend:SI
9620 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9621 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9622 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9623 (plus:SI (match_dup 1) (match_dup 2)))]
9624 "TARGET_UPDATE"
9625 "@
9626 lbzux %3,%0,%2
9627 lbzu %3,%2(%0)"
9628 [(set_attr "type" "load_ux,load_u")])
9630 (define_insn "*movqi_update3"
9631 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9632 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9633 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9634 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9635 (plus:SI (match_dup 1) (match_dup 2)))]
9636 "TARGET_UPDATE"
9637 "@
9638 stbux %3,%0,%2
9639 stbu %3,%2(%0)"
9640 [(set_attr "type" "store_ux,store_u")])
9642 (define_insn "*movsf_update1"
9643 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9644 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9645 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9646 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9647 (plus:SI (match_dup 1) (match_dup 2)))]
9648 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9649 "@
9650 lfsux %3,%0,%2
9651 lfsu %3,%2(%0)"
9652 [(set_attr "type" "fpload_ux,fpload_u")])
9654 (define_insn "*movsf_update2"
9655 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9656 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9657 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9658 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9659 (plus:SI (match_dup 1) (match_dup 2)))]
9660 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9661 "@
9662 stfsux %3,%0,%2
9663 stfsu %3,%2(%0)"
9664 [(set_attr "type" "fpstore_ux,fpstore_u")])
9666 (define_insn "*movsf_update3"
9667 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9668 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9669 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9670 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9671 (plus:SI (match_dup 1) (match_dup 2)))]
9672 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9673 "@
9674 {lux|lwzux} %3,%0,%2
9675 {lu|lwzu} %3,%2(%0)"
9676 [(set_attr "type" "load_ux,load_u")])
9678 (define_insn "*movsf_update4"
9679 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9680 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9681 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9682 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9683 (plus:SI (match_dup 1) (match_dup 2)))]
9684 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9685 "@
9686 {stux|stwux} %3,%0,%2
9687 {stu|stwu} %3,%2(%0)"
9688 [(set_attr "type" "store_ux,store_u")])
9690 (define_insn "*movdf_update1"
9691 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9692 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9693 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9694 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9695 (plus:SI (match_dup 1) (match_dup 2)))]
9696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9697 "@
9698 lfdux %3,%0,%2
9699 lfdu %3,%2(%0)"
9700 [(set_attr "type" "fpload_ux,fpload_u")])
9702 (define_insn "*movdf_update2"
9703 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9704 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9705 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9706 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9707 (plus:SI (match_dup 1) (match_dup 2)))]
9708 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9709 "@
9710 stfdux %3,%0,%2
9711 stfdu %3,%2(%0)"
9712 [(set_attr "type" "fpstore_ux,fpstore_u")])
9714 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9716 (define_insn "*lfq_power2"
9717 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9718 (match_operand:TF 1 "memory_operand" ""))]
9719 "TARGET_POWER2
9720 && TARGET_HARD_FLOAT && TARGET_FPRS"
9721 "lfq%U1%X1 %0,%1")
9723 (define_peephole2
9724 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9725 (match_operand:DF 1 "memory_operand" ""))
9726 (set (match_operand:DF 2 "gpc_reg_operand" "")
9727 (match_operand:DF 3 "memory_operand" ""))]
9728 "TARGET_POWER2
9729 && TARGET_HARD_FLOAT && TARGET_FPRS
9730 && registers_ok_for_quad_peep (operands[0], operands[2])
9731 && mems_ok_for_quad_peep (operands[1], operands[3])"
9732 [(set (match_dup 0)
9733 (match_dup 1))]
9734 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9735 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9737 (define_insn "*stfq_power2"
9738 [(set (match_operand:TF 0 "memory_operand" "")
9739 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9740 "TARGET_POWER2
9741 && TARGET_HARD_FLOAT && TARGET_FPRS"
9742 "stfq%U0%X0 %1,%0")
9745 (define_peephole2
9746 [(set (match_operand:DF 0 "memory_operand" "")
9747 (match_operand:DF 1 "gpc_reg_operand" ""))
9748 (set (match_operand:DF 2 "memory_operand" "")
9749 (match_operand:DF 3 "gpc_reg_operand" ""))]
9750 "TARGET_POWER2
9751 && TARGET_HARD_FLOAT && TARGET_FPRS
9752 && registers_ok_for_quad_peep (operands[1], operands[3])
9753 && mems_ok_for_quad_peep (operands[0], operands[2])"
9754 [(set (match_dup 0)
9755 (match_dup 1))]
9756 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9757 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9759 ;; after inserting conditional returns we can sometimes have
9760 ;; unnecessary register moves. Unfortunately we cannot have a
9761 ;; modeless peephole here, because some single SImode sets have early
9762 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9763 ;; sequences, using get_attr_length here will smash the operands
9764 ;; array. Neither is there an early_cobbler_p predicate.
9765 (define_peephole2
9766 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9767 (match_operand:DF 1 "any_operand" ""))
9768 (set (match_operand:DF 2 "gpc_reg_operand" "")
9769 (match_dup 0))]
9770 "peep2_reg_dead_p (2, operands[0])"
9771 [(set (match_dup 2) (match_dup 1))])
9773 (define_peephole2
9774 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9775 (match_operand:SF 1 "any_operand" ""))
9776 (set (match_operand:SF 2 "gpc_reg_operand" "")
9777 (match_dup 0))]
9778 "peep2_reg_dead_p (2, operands[0])"
9779 [(set (match_dup 2) (match_dup 1))])
9781 \f
9782 ;; TLS support.
9784 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9785 (define_insn "tls_gd_32"
9786 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9787 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9788 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9789 UNSPEC_TLSGD))]
9790 "HAVE_AS_TLS && !TARGET_64BIT"
9791 "addi %0,%1,%2@got@tlsgd")
9793 (define_insn "tls_gd_64"
9794 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9795 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9796 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9797 UNSPEC_TLSGD))]
9798 "HAVE_AS_TLS && TARGET_64BIT"
9799 "addi %0,%1,%2@got@tlsgd")
9801 (define_insn "tls_ld_32"
9802 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9803 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9804 UNSPEC_TLSLD))]
9805 "HAVE_AS_TLS && !TARGET_64BIT"
9806 "addi %0,%1,%&@got@tlsld")
9808 (define_insn "tls_ld_64"
9809 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9810 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9811 UNSPEC_TLSLD))]
9812 "HAVE_AS_TLS && TARGET_64BIT"
9813 "addi %0,%1,%&@got@tlsld")
9815 (define_insn "tls_dtprel_32"
9816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9817 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9818 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9819 UNSPEC_TLSDTPREL))]
9820 "HAVE_AS_TLS && !TARGET_64BIT"
9821 "addi %0,%1,%2@dtprel")
9823 (define_insn "tls_dtprel_64"
9824 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9825 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9826 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9827 UNSPEC_TLSDTPREL))]
9828 "HAVE_AS_TLS && TARGET_64BIT"
9829 "addi %0,%1,%2@dtprel")
9831 (define_insn "tls_dtprel_ha_32"
9832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9833 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9834 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9835 UNSPEC_TLSDTPRELHA))]
9836 "HAVE_AS_TLS && !TARGET_64BIT"
9837 "addis %0,%1,%2@dtprel@ha")
9839 (define_insn "tls_dtprel_ha_64"
9840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9841 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9842 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9843 UNSPEC_TLSDTPRELHA))]
9844 "HAVE_AS_TLS && TARGET_64BIT"
9845 "addis %0,%1,%2@dtprel@ha")
9847 (define_insn "tls_dtprel_lo_32"
9848 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9849 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9850 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9851 UNSPEC_TLSDTPRELLO))]
9852 "HAVE_AS_TLS && !TARGET_64BIT"
9853 "addi %0,%1,%2@dtprel@l")
9855 (define_insn "tls_dtprel_lo_64"
9856 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9857 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9858 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9859 UNSPEC_TLSDTPRELLO))]
9860 "HAVE_AS_TLS && TARGET_64BIT"
9861 "addi %0,%1,%2@dtprel@l")
9863 (define_insn "tls_got_dtprel_32"
9864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9865 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9866 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9867 UNSPEC_TLSGOTDTPREL))]
9868 "HAVE_AS_TLS && !TARGET_64BIT"
9869 "lwz %0,%2@got@dtprel(%1)")
9871 (define_insn "tls_got_dtprel_64"
9872 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9873 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9874 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9875 UNSPEC_TLSGOTDTPREL))]
9876 "HAVE_AS_TLS && TARGET_64BIT"
9877 "ld %0,%2@got@dtprel(%1)")
9879 (define_insn "tls_tprel_32"
9880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9881 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9882 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9883 UNSPEC_TLSTPREL))]
9884 "HAVE_AS_TLS && !TARGET_64BIT"
9885 "addi %0,%1,%2@tprel")
9887 (define_insn "tls_tprel_64"
9888 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9889 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9890 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9891 UNSPEC_TLSTPREL))]
9892 "HAVE_AS_TLS && TARGET_64BIT"
9893 "addi %0,%1,%2@tprel")
9895 (define_insn "tls_tprel_ha_32"
9896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9897 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9898 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9899 UNSPEC_TLSTPRELHA))]
9900 "HAVE_AS_TLS && !TARGET_64BIT"
9901 "addis %0,%1,%2@tprel@ha")
9903 (define_insn "tls_tprel_ha_64"
9904 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9905 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9906 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9907 UNSPEC_TLSTPRELHA))]
9908 "HAVE_AS_TLS && TARGET_64BIT"
9909 "addis %0,%1,%2@tprel@ha")
9911 (define_insn "tls_tprel_lo_32"
9912 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9913 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9914 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9915 UNSPEC_TLSTPRELLO))]
9916 "HAVE_AS_TLS && !TARGET_64BIT"
9917 "addi %0,%1,%2@tprel@l")
9919 (define_insn "tls_tprel_lo_64"
9920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9921 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9922 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9923 UNSPEC_TLSTPRELLO))]
9924 "HAVE_AS_TLS && TARGET_64BIT"
9925 "addi %0,%1,%2@tprel@l")
9927 ;; "b" output constraint here and on tls_tls input to support linker tls
9928 ;; optimization. The linker may edit the instructions emitted by a
9929 ;; tls_got_tprel/tls_tls pair to addis,addi.
9930 (define_insn "tls_got_tprel_32"
9931 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9932 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9933 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9934 UNSPEC_TLSGOTTPREL))]
9935 "HAVE_AS_TLS && !TARGET_64BIT"
9936 "lwz %0,%2@got@tprel(%1)")
9938 (define_insn "tls_got_tprel_64"
9939 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9940 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9941 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9942 UNSPEC_TLSGOTTPREL))]
9943 "HAVE_AS_TLS && TARGET_64BIT"
9944 "ld %0,%2@got@tprel(%1)")
9946 (define_insn "tls_tls_32"
9947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9948 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9949 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9950 UNSPEC_TLSTLS))]
9951 "HAVE_AS_TLS && !TARGET_64BIT"
9952 "add %0,%1,%2@tls")
9954 (define_insn "tls_tls_64"
9955 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9956 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9957 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9958 UNSPEC_TLSTLS))]
9959 "HAVE_AS_TLS && TARGET_64BIT"
9960 "add %0,%1,%2@tls")
9961 \f
9962 ;; Next come insns related to the calling sequence.
9963 ;;
9964 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9965 ;; We move the back-chain and decrement the stack pointer.
9967 (define_expand "allocate_stack"
9968 [(set (match_operand 0 "gpc_reg_operand" "=r")
9969 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9970 (set (reg 1)
9971 (minus (reg 1) (match_dup 1)))]
9972 ""
9973 "
9974 { rtx chain = gen_reg_rtx (Pmode);
9975 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9976 rtx neg_op0;
9978 emit_move_insn (chain, stack_bot);
9980 /* Check stack bounds if necessary. */
9981 if (current_function_limit_stack)
9982 {
9983 rtx available;
9984 available = expand_binop (Pmode, sub_optab,
9985 stack_pointer_rtx, stack_limit_rtx,
9986 NULL_RTX, 1, OPTAB_WIDEN);
9987 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9988 }
9990 if (GET_CODE (operands[1]) != CONST_INT
9991 || INTVAL (operands[1]) < -32767
9992 || INTVAL (operands[1]) > 32768)
9993 {
9994 neg_op0 = gen_reg_rtx (Pmode);
9995 if (TARGET_32BIT)
9996 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9997 else
9998 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9999 }
10000 else
10001 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10003 if (TARGET_UPDATE)
10004 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10005 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10007 else
10008 {
10009 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10010 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10011 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10012 }
10014 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10015 DONE;
10016 }")
10018 ;; These patterns say how to save and restore the stack pointer. We need not
10019 ;; save the stack pointer at function level since we are careful to
10020 ;; preserve the backchain. At block level, we have to restore the backchain
10021 ;; when we restore the stack pointer.
10022 ;;
10023 ;; For nonlocal gotos, we must save both the stack pointer and its
10024 ;; backchain and restore both. Note that in the nonlocal case, the
10025 ;; save area is a memory location.
10027 (define_expand "save_stack_function"
10028 [(match_operand 0 "any_operand" "")
10029 (match_operand 1 "any_operand" "")]
10030 ""
10031 "DONE;")
10033 (define_expand "restore_stack_function"
10034 [(match_operand 0 "any_operand" "")
10035 (match_operand 1 "any_operand" "")]
10036 ""
10037 "DONE;")
10039 ;; Adjust stack pointer (op0) to a new value (op1).
10040 ;; First copy old stack backchain to new location, and ensure that the
10041 ;; scheduler won't reorder the sp assignment before the backchain write.
10042 (define_expand "restore_stack_block"
10043 [(set (match_dup 2) (match_dup 3))
10044 (set (match_dup 4) (match_dup 2))
10045 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10046 (set (match_operand 0 "register_operand" "")
10047 (match_operand 1 "register_operand" ""))]
10048 ""
10049 "
10050 {
10051 operands[2] = gen_reg_rtx (Pmode);
10052 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10053 operands[4] = gen_rtx_MEM (Pmode, operands[1]);
10054 operands[5] = gen_rtx_MEM (BLKmode, operands[0]);
10055 }")
10057 (define_expand "save_stack_nonlocal"
10058 [(set (match_dup 3) (match_dup 4))
10059 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10060 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10061 ""
10062 "
10063 {
10064 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10066 /* Copy the backchain to the first word, sp to the second. */
10067 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10068 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10069 operands[3] = gen_reg_rtx (Pmode);
10070 operands[4] = gen_rtx_MEM (Pmode, operands[1]);
10071 }")
10073 (define_expand "restore_stack_nonlocal"
10074 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10075 (set (match_dup 3) (match_dup 4))
10076 (set (match_dup 5) (match_dup 2))
10077 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10078 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10079 ""
10080 "
10081 {
10082 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10084 /* Restore the backchain from the first word, sp from the second. */
10085 operands[2] = gen_reg_rtx (Pmode);
10086 operands[3] = gen_reg_rtx (Pmode);
10087 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10088 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10089 operands[5] = gen_rtx_MEM (Pmode, operands[3]);
10090 operands[6] = gen_rtx_MEM (BLKmode, operands[0]);
10091 }")
10092 \f
10093 ;; TOC register handling.
10095 ;; Code to initialize the TOC register...
10097 (define_insn "load_toc_aix_si"
10098 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10099 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10100 (use (reg:SI 2))])]
10101 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10102 "*
10103 {
10104 char buf[30];
10105 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10106 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10107 operands[2] = gen_rtx_REG (Pmode, 2);
10108 return \"{l|lwz} %0,%1(%2)\";
10109 }"
10110 [(set_attr "type" "load")])
10112 (define_insn "load_toc_aix_di"
10113 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10114 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10115 (use (reg:DI 2))])]
10116 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10117 "*
10118 {
10119 char buf[30];
10120 #ifdef TARGET_RELOCATABLE
10121 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10122 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10123 #else
10124 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10125 #endif
10126 if (TARGET_ELF)
10127 strcat (buf, \"@toc\");
10128 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10129 operands[2] = gen_rtx_REG (Pmode, 2);
10130 return \"ld %0,%1(%2)\";
10131 }"
10132 [(set_attr "type" "load")])
10134 (define_insn "load_toc_v4_pic_si"
10135 [(set (match_operand:SI 0 "register_operand" "=l")
10136 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10137 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10138 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10139 [(set_attr "type" "branch")
10140 (set_attr "length" "4")])
10142 (define_insn "load_toc_v4_PIC_1"
10143 [(set (match_operand:SI 0 "register_operand" "=l")
10144 (match_operand:SI 1 "immediate_operand" "s"))
10145 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10146 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10147 "bcl 20,31,%1\\n%1:"
10148 [(set_attr "type" "branch")
10149 (set_attr "length" "4")])
10151 (define_insn "load_toc_v4_PIC_1b"
10152 [(set (match_operand:SI 0 "register_operand" "=l")
10153 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10154 UNSPEC_TOCPTR))]
10155 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10156 "bcl 20,31,$+8\\n\\t.long %1-$"
10157 [(set_attr "type" "branch")
10158 (set_attr "length" "8")])
10160 (define_insn "load_toc_v4_PIC_2"
10161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10162 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10163 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10164 (match_operand:SI 3 "immediate_operand" "s")))))]
10165 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10166 "{l|lwz} %0,%2-%3(%1)"
10167 [(set_attr "type" "load")])
10170 ;; If the TOC is shared over a translation unit, as happens with all
10171 ;; the kinds of PIC that we support, we need to restore the TOC
10172 ;; pointer only when jumping over units of translation.
10173 ;; On Darwin, we need to reload the picbase.
10175 (define_expand "builtin_setjmp_receiver"
10176 [(use (label_ref (match_operand 0 "" "")))]
10177 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10178 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10179 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10180 "
10181 {
10182 #if TARGET_MACHO
10183 if (DEFAULT_ABI == ABI_DARWIN)
10184 {
10185 const char *picbase = machopic_function_base_name ();
10186 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10187 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10188 rtx tmplabrtx;
10189 char tmplab[20];
10191 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10192 CODE_LABEL_NUMBER (operands[0]));
10193 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10195 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10196 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10197 }
10198 else
10199 #endif
10200 rs6000_emit_load_toc_table (FALSE);
10201 DONE;
10202 }")
10203 \f
10204 ;; A function pointer under AIX is a pointer to a data area whose first word
10205 ;; contains the actual address of the function, whose second word contains a
10206 ;; pointer to its TOC, and whose third word contains a value to place in the
10207 ;; static chain register (r11). Note that if we load the static chain, our
10208 ;; "trampoline" need not have any executable code.
10210 (define_expand "call_indirect_aix32"
10211 [(set (match_dup 2)
10212 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10213 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10214 (reg:SI 2))
10215 (set (reg:SI 2)
10216 (mem:SI (plus:SI (match_dup 0)
10217 (const_int 4))))
10218 (set (reg:SI 11)
10219 (mem:SI (plus:SI (match_dup 0)
10220 (const_int 8))))
10221 (parallel [(call (mem:SI (match_dup 2))
10222 (match_operand 1 "" ""))
10223 (use (reg:SI 2))
10224 (use (reg:SI 11))
10225 (set (reg:SI 2)
10226 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10227 (clobber (scratch:SI))])]
10228 "TARGET_32BIT"
10229 "
10230 { operands[2] = gen_reg_rtx (SImode); }")
10232 (define_expand "call_indirect_aix64"
10233 [(set (match_dup 2)
10234 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10235 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10236 (reg:DI 2))
10237 (set (reg:DI 2)
10238 (mem:DI (plus:DI (match_dup 0)
10239 (const_int 8))))
10240 (set (reg:DI 11)
10241 (mem:DI (plus:DI (match_dup 0)
10242 (const_int 16))))
10243 (parallel [(call (mem:SI (match_dup 2))
10244 (match_operand 1 "" ""))
10245 (use (reg:DI 2))
10246 (use (reg:DI 11))
10247 (set (reg:DI 2)
10248 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10249 (clobber (scratch:SI))])]
10250 "TARGET_64BIT"
10251 "
10252 { operands[2] = gen_reg_rtx (DImode); }")
10254 (define_expand "call_value_indirect_aix32"
10255 [(set (match_dup 3)
10256 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10257 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10258 (reg:SI 2))
10259 (set (reg:SI 2)
10260 (mem:SI (plus:SI (match_dup 1)
10261 (const_int 4))))
10262 (set (reg:SI 11)
10263 (mem:SI (plus:SI (match_dup 1)
10264 (const_int 8))))
10265 (parallel [(set (match_operand 0 "" "")
10266 (call (mem:SI (match_dup 3))
10267 (match_operand 2 "" "")))
10268 (use (reg:SI 2))
10269 (use (reg:SI 11))
10270 (set (reg:SI 2)
10271 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10272 (clobber (scratch:SI))])]
10273 "TARGET_32BIT"
10274 "
10275 { operands[3] = gen_reg_rtx (SImode); }")
10277 (define_expand "call_value_indirect_aix64"
10278 [(set (match_dup 3)
10279 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10280 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10281 (reg:DI 2))
10282 (set (reg:DI 2)
10283 (mem:DI (plus:DI (match_dup 1)
10284 (const_int 8))))
10285 (set (reg:DI 11)
10286 (mem:DI (plus:DI (match_dup 1)
10287 (const_int 16))))
10288 (parallel [(set (match_operand 0 "" "")
10289 (call (mem:SI (match_dup 3))
10290 (match_operand 2 "" "")))
10291 (use (reg:DI 2))
10292 (use (reg:DI 11))
10293 (set (reg:DI 2)
10294 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10295 (clobber (scratch:SI))])]
10296 "TARGET_64BIT"
10297 "
10298 { operands[3] = gen_reg_rtx (DImode); }")
10300 ;; Now the definitions for the call and call_value insns
10301 (define_expand "call"
10302 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10303 (match_operand 1 "" ""))
10304 (use (match_operand 2 "" ""))
10305 (clobber (scratch:SI))])]
10306 ""
10307 "
10308 {
10309 #if TARGET_MACHO
10310 if (MACHOPIC_INDIRECT)
10311 operands[0] = machopic_indirect_call_target (operands[0]);
10312 #endif
10314 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10315 abort ();
10317 operands[0] = XEXP (operands[0], 0);
10319 if (GET_CODE (operands[0]) != SYMBOL_REF
10320 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10321 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10322 {
10323 if (INTVAL (operands[2]) & CALL_LONG)
10324 operands[0] = rs6000_longcall_ref (operands[0]);
10326 if (DEFAULT_ABI == ABI_V4
10327 || DEFAULT_ABI == ABI_DARWIN)
10328 operands[0] = force_reg (Pmode, operands[0]);
10330 else if (DEFAULT_ABI == ABI_AIX)
10331 {
10332 /* AIX function pointers are really pointers to a three word
10333 area. */
10334 emit_call_insn (TARGET_32BIT
10335 ? gen_call_indirect_aix32 (force_reg (SImode,
10336 operands[0]),
10337 operands[1])
10338 : gen_call_indirect_aix64 (force_reg (DImode,
10339 operands[0]),
10340 operands[1]));
10341 DONE;
10342 }
10343 else
10344 abort ();
10345 }
10346 }")
10348 (define_expand "call_value"
10349 [(parallel [(set (match_operand 0 "" "")
10350 (call (mem:SI (match_operand 1 "address_operand" ""))
10351 (match_operand 2 "" "")))
10352 (use (match_operand 3 "" ""))
10353 (clobber (scratch:SI))])]
10354 ""
10355 "
10356 {
10357 #if TARGET_MACHO
10358 if (MACHOPIC_INDIRECT)
10359 operands[1] = machopic_indirect_call_target (operands[1]);
10360 #endif
10362 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10363 abort ();
10365 operands[1] = XEXP (operands[1], 0);
10367 if (GET_CODE (operands[1]) != SYMBOL_REF
10368 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10369 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10370 {
10371 if (INTVAL (operands[3]) & CALL_LONG)
10372 operands[1] = rs6000_longcall_ref (operands[1]);
10374 if (DEFAULT_ABI == ABI_V4
10375 || DEFAULT_ABI == ABI_DARWIN)
10376 operands[1] = force_reg (Pmode, operands[1]);
10378 else if (DEFAULT_ABI == ABI_AIX)
10379 {
10380 /* AIX function pointers are really pointers to a three word
10381 area. */
10382 emit_call_insn (TARGET_32BIT
10383 ? gen_call_value_indirect_aix32 (operands[0],
10384 force_reg (SImode,
10385 operands[1]),
10386 operands[2])
10387 : gen_call_value_indirect_aix64 (operands[0],
10388 force_reg (DImode,
10389 operands[1]),
10390 operands[2]));
10391 DONE;
10392 }
10393 else
10394 abort ();
10395 }
10396 }")
10398 ;; Call to function in current module. No TOC pointer reload needed.
10399 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10400 ;; either the function was not prototyped, or it was prototyped as a
10401 ;; variable argument function. It is > 0 if FP registers were passed
10402 ;; and < 0 if they were not.
10404 (define_insn "*call_local32"
10405 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10406 (match_operand 1 "" "g,g"))
10407 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10408 (clobber (match_scratch:SI 3 "=l,l"))]
10409 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10410 "*
10411 {
10412 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10413 output_asm_insn (\"crxor 6,6,6\", operands);
10415 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10416 output_asm_insn (\"creqv 6,6,6\", operands);
10418 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10419 }"
10420 [(set_attr "type" "branch")
10421 (set_attr "length" "4,8")])
10423 (define_insn "*call_local64"
10424 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10425 (match_operand 1 "" "g,g"))
10426 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10427 (clobber (match_scratch:SI 3 "=l,l"))]
10428 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10429 "*
10430 {
10431 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10432 output_asm_insn (\"crxor 6,6,6\", operands);
10434 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10435 output_asm_insn (\"creqv 6,6,6\", operands);
10437 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10438 }"
10439 [(set_attr "type" "branch")
10440 (set_attr "length" "4,8")])
10442 (define_insn "*call_value_local32"
10443 [(set (match_operand 0 "" "")
10444 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10445 (match_operand 2 "" "g,g")))
10446 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10447 (clobber (match_scratch:SI 4 "=l,l"))]
10448 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10449 "*
10450 {
10451 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10452 output_asm_insn (\"crxor 6,6,6\", operands);
10454 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10455 output_asm_insn (\"creqv 6,6,6\", operands);
10457 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10458 }"
10459 [(set_attr "type" "branch")
10460 (set_attr "length" "4,8")])
10463 (define_insn "*call_value_local64"
10464 [(set (match_operand 0 "" "")
10465 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10466 (match_operand 2 "" "g,g")))
10467 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10468 (clobber (match_scratch:SI 4 "=l,l"))]
10469 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10470 "*
10471 {
10472 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10473 output_asm_insn (\"crxor 6,6,6\", operands);
10475 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10476 output_asm_insn (\"creqv 6,6,6\", operands);
10478 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10479 }"
10480 [(set_attr "type" "branch")
10481 (set_attr "length" "4,8")])
10483 ;; Call to function which may be in another module. Restore the TOC
10484 ;; pointer (r2) after the call unless this is System V.
10485 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10486 ;; either the function was not prototyped, or it was prototyped as a
10487 ;; variable argument function. It is > 0 if FP registers were passed
10488 ;; and < 0 if they were not.
10490 (define_insn "*call_indirect_nonlocal_aix32"
10491 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10492 (match_operand 1 "" "g,g"))
10493 (use (reg:SI 2))
10494 (use (reg:SI 11))
10495 (set (reg:SI 2)
10496 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10497 (clobber (match_scratch:SI 2 "=l,l"))]
10498 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10499 "b%T0l\;{l|lwz} 2,20(1)"
10500 [(set_attr "type" "jmpreg")
10501 (set_attr "length" "8")])
10503 (define_insn "*call_nonlocal_aix32"
10504 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10505 (match_operand 1 "" "g"))
10506 (use (match_operand:SI 2 "immediate_operand" "O"))
10507 (clobber (match_scratch:SI 3 "=l"))]
10508 "TARGET_32BIT
10509 && DEFAULT_ABI == ABI_AIX
10510 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10511 "bl %z0\;%."
10512 [(set_attr "type" "branch")
10513 (set_attr "length" "8")])
10515 (define_insn "*call_indirect_nonlocal_aix64"
10516 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10517 (match_operand 1 "" "g,g"))
10518 (use (reg:DI 2))
10519 (use (reg:DI 11))
10520 (set (reg:DI 2)
10521 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10522 (clobber (match_scratch:SI 2 "=l,l"))]
10523 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10524 "b%T0l\;ld 2,40(1)"
10525 [(set_attr "type" "jmpreg")
10526 (set_attr "length" "8")])
10528 (define_insn "*call_nonlocal_aix64"
10529 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10530 (match_operand 1 "" "g"))
10531 (use (match_operand:SI 2 "immediate_operand" "O"))
10532 (clobber (match_scratch:SI 3 "=l"))]
10533 "TARGET_64BIT
10534 && DEFAULT_ABI == ABI_AIX
10535 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10536 "bl %z0\;%."
10537 [(set_attr "type" "branch")
10538 (set_attr "length" "8")])
10540 (define_insn "*call_value_indirect_nonlocal_aix32"
10541 [(set (match_operand 0 "" "")
10542 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10543 (match_operand 2 "" "g,g")))
10544 (use (reg:SI 2))
10545 (use (reg:SI 11))
10546 (set (reg:SI 2)
10547 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10548 (clobber (match_scratch:SI 3 "=l,l"))]
10549 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10550 "b%T1l\;{l|lwz} 2,20(1)"
10551 [(set_attr "type" "jmpreg")
10552 (set_attr "length" "8")])
10554 (define_insn "*call_value_nonlocal_aix32"
10555 [(set (match_operand 0 "" "")
10556 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10557 (match_operand 2 "" "g")))
10558 (use (match_operand:SI 3 "immediate_operand" "O"))
10559 (clobber (match_scratch:SI 4 "=l"))]
10560 "TARGET_32BIT
10561 && DEFAULT_ABI == ABI_AIX
10562 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10563 "bl %z1\;%."
10564 [(set_attr "type" "branch")
10565 (set_attr "length" "8")])
10567 (define_insn "*call_value_indirect_nonlocal_aix64"
10568 [(set (match_operand 0 "" "")
10569 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10570 (match_operand 2 "" "g,g")))
10571 (use (reg:DI 2))
10572 (use (reg:DI 11))
10573 (set (reg:DI 2)
10574 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10575 (clobber (match_scratch:SI 3 "=l,l"))]
10576 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10577 "b%T1l\;ld 2,40(1)"
10578 [(set_attr "type" "jmpreg")
10579 (set_attr "length" "8")])
10581 (define_insn "*call_value_nonlocal_aix64"
10582 [(set (match_operand 0 "" "")
10583 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10584 (match_operand 2 "" "g")))
10585 (use (match_operand:SI 3 "immediate_operand" "O"))
10586 (clobber (match_scratch:SI 4 "=l"))]
10587 "TARGET_64BIT
10588 && DEFAULT_ABI == ABI_AIX
10589 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10590 "bl %z1\;%."
10591 [(set_attr "type" "branch")
10592 (set_attr "length" "8")])
10594 ;; A function pointer under System V is just a normal pointer
10595 ;; operands[0] is the function pointer
10596 ;; operands[1] is the stack size to clean up
10597 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10598 ;; which indicates how to set cr1
10600 (define_insn "*call_indirect_nonlocal_sysv"
10601 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10602 (match_operand 1 "" "g,g,g,g"))
10603 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10604 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10605 "DEFAULT_ABI == ABI_V4
10606 || DEFAULT_ABI == ABI_DARWIN"
10607 {
10608 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10609 output_asm_insn ("crxor 6,6,6", operands);
10611 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10612 output_asm_insn ("creqv 6,6,6", operands);
10614 return "b%T0l";
10615 }
10616 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10617 (set_attr "length" "4,4,8,8")])
10619 (define_insn "*call_nonlocal_sysv"
10620 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10621 (match_operand 1 "" "g,g"))
10622 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10623 (clobber (match_scratch:SI 3 "=l,l"))]
10624 "(DEFAULT_ABI == ABI_DARWIN
10625 || (DEFAULT_ABI == ABI_V4
10626 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10627 {
10628 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10629 output_asm_insn ("crxor 6,6,6", operands);
10631 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10632 output_asm_insn ("creqv 6,6,6", operands);
10634 #if TARGET_MACHO
10635 return output_call(insn, operands, 0, 2);
10636 #else
10637 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10638 #endif
10639 }
10640 [(set_attr "type" "branch,branch")
10641 (set_attr "length" "4,8")])
10643 (define_insn "*call_value_indirect_nonlocal_sysv"
10644 [(set (match_operand 0 "" "")
10645 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10646 (match_operand 2 "" "g,g,g,g")))
10647 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10648 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10649 "DEFAULT_ABI == ABI_V4
10650 || DEFAULT_ABI == ABI_DARWIN"
10651 {
10652 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10653 output_asm_insn ("crxor 6,6,6", operands);
10655 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10656 output_asm_insn ("creqv 6,6,6", operands);
10658 return "b%T1l";
10659 }
10660 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10661 (set_attr "length" "4,4,8,8")])
10663 (define_insn "*call_value_nonlocal_sysv"
10664 [(set (match_operand 0 "" "")
10665 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10666 (match_operand 2 "" "g,g")))
10667 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10668 (clobber (match_scratch:SI 4 "=l,l"))]
10669 "(DEFAULT_ABI == ABI_DARWIN
10670 || (DEFAULT_ABI == ABI_V4
10671 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10672 {
10673 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10674 output_asm_insn ("crxor 6,6,6", operands);
10676 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10677 output_asm_insn ("creqv 6,6,6", operands);
10679 #if TARGET_MACHO
10680 return output_call(insn, operands, 1, 3);
10681 #else
10682 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10683 #endif
10684 }
10685 [(set_attr "type" "branch,branch")
10686 (set_attr "length" "4,8")])
10688 ;; Call subroutine returning any type.
10689 (define_expand "untyped_call"
10690 [(parallel [(call (match_operand 0 "" "")
10691 (const_int 0))
10692 (match_operand 1 "" "")
10693 (match_operand 2 "" "")])]
10694 ""
10695 "
10696 {
10697 int i;
10699 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10701 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10702 {
10703 rtx set = XVECEXP (operands[2], 0, i);
10704 emit_move_insn (SET_DEST (set), SET_SRC (set));
10705 }
10707 /* The optimizer does not know that the call sets the function value
10708 registers we stored in the result block. We avoid problems by
10709 claiming that all hard registers are used and clobbered at this
10710 point. */
10711 emit_insn (gen_blockage ());
10713 DONE;
10714 }")
10716 ;; sibling call patterns
10717 (define_expand "sibcall"
10718 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10719 (match_operand 1 "" ""))
10720 (use (match_operand 2 "" ""))
10721 (use (match_operand 3 "" ""))
10722 (return)])]
10723 ""
10724 "
10725 {
10726 #if TARGET_MACHO
10727 if (MACHOPIC_INDIRECT)
10728 operands[0] = machopic_indirect_call_target (operands[0]);
10729 #endif
10731 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10732 abort ();
10734 operands[0] = XEXP (operands[0], 0);
10735 operands[3] = gen_reg_rtx (SImode);
10737 }")
10739 ;; this and similar patterns must be marked as using LR, otherwise
10740 ;; dataflow will try to delete the store into it. This is true
10741 ;; even when the actual reg to jump to is in CTR, when LR was
10742 ;; saved and restored around the PIC-setting BCL.
10743 (define_insn "*sibcall_local32"
10744 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10745 (match_operand 1 "" "g,g"))
10746 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10747 (use (match_operand:SI 3 "register_operand" "l,l"))
10748 (return)]
10749 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10750 "*
10751 {
10752 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10753 output_asm_insn (\"crxor 6,6,6\", operands);
10755 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10756 output_asm_insn (\"creqv 6,6,6\", operands);
10758 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10759 }"
10760 [(set_attr "type" "branch")
10761 (set_attr "length" "4,8")])
10763 (define_insn "*sibcall_local64"
10764 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10765 (match_operand 1 "" "g,g"))
10766 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10767 (use (match_operand:SI 3 "register_operand" "l,l"))
10768 (return)]
10769 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10770 "*
10771 {
10772 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10773 output_asm_insn (\"crxor 6,6,6\", operands);
10775 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10776 output_asm_insn (\"creqv 6,6,6\", operands);
10778 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10779 }"
10780 [(set_attr "type" "branch")
10781 (set_attr "length" "4,8")])
10783 (define_insn "*sibcall_value_local32"
10784 [(set (match_operand 0 "" "")
10785 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10786 (match_operand 2 "" "g,g")))
10787 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10788 (use (match_operand:SI 4 "register_operand" "l,l"))
10789 (return)]
10790 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10791 "*
10792 {
10793 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10794 output_asm_insn (\"crxor 6,6,6\", operands);
10796 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10797 output_asm_insn (\"creqv 6,6,6\", operands);
10799 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10800 }"
10801 [(set_attr "type" "branch")
10802 (set_attr "length" "4,8")])
10805 (define_insn "*sibcall_value_local64"
10806 [(set (match_operand 0 "" "")
10807 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10808 (match_operand 2 "" "g,g")))
10809 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10810 (use (match_operand:SI 4 "register_operand" "l,l"))
10811 (return)]
10812 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10813 "*
10814 {
10815 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10816 output_asm_insn (\"crxor 6,6,6\", operands);
10818 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10819 output_asm_insn (\"creqv 6,6,6\", operands);
10821 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10822 }"
10823 [(set_attr "type" "branch")
10824 (set_attr "length" "4,8")])
10826 (define_insn "*sibcall_nonlocal_aix32"
10827 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10828 (match_operand 1 "" "g"))
10829 (use (match_operand:SI 2 "immediate_operand" "O"))
10830 (use (match_operand:SI 3 "register_operand" "l"))
10831 (return)]
10832 "TARGET_32BIT
10833 && DEFAULT_ABI == ABI_AIX
10834 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10835 "b %z0"
10836 [(set_attr "type" "branch")
10837 (set_attr "length" "4")])
10839 (define_insn "*sibcall_nonlocal_aix64"
10840 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10841 (match_operand 1 "" "g"))
10842 (use (match_operand:SI 2 "immediate_operand" "O"))
10843 (use (match_operand:SI 3 "register_operand" "l"))
10844 (return)]
10845 "TARGET_64BIT
10846 && DEFAULT_ABI == ABI_AIX
10847 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10848 "b %z0"
10849 [(set_attr "type" "branch")
10850 (set_attr "length" "4")])
10852 (define_insn "*sibcall_value_nonlocal_aix32"
10853 [(set (match_operand 0 "" "")
10854 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10855 (match_operand 2 "" "g")))
10856 (use (match_operand:SI 3 "immediate_operand" "O"))
10857 (use (match_operand:SI 4 "register_operand" "l"))
10858 (return)]
10859 "TARGET_32BIT
10860 && DEFAULT_ABI == ABI_AIX
10861 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10862 "b %z1"
10863 [(set_attr "type" "branch")
10864 (set_attr "length" "4")])
10866 (define_insn "*sibcall_value_nonlocal_aix64"
10867 [(set (match_operand 0 "" "")
10868 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10869 (match_operand 2 "" "g")))
10870 (use (match_operand:SI 3 "immediate_operand" "O"))
10871 (use (match_operand:SI 4 "register_operand" "l"))
10872 (return)]
10873 "TARGET_64BIT
10874 && DEFAULT_ABI == ABI_AIX
10875 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10876 "b %z1"
10877 [(set_attr "type" "branch")
10878 (set_attr "length" "4")])
10880 (define_insn "*sibcall_nonlocal_sysv"
10881 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10882 (match_operand 1 "" ""))
10883 (use (match_operand 2 "immediate_operand" "O,n"))
10884 (use (match_operand:SI 3 "register_operand" "l,l"))
10885 (return)]
10886 "(DEFAULT_ABI == ABI_DARWIN
10887 || DEFAULT_ABI == ABI_V4)
10888 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10889 "*
10890 {
10891 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10892 output_asm_insn (\"crxor 6,6,6\", operands);
10894 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10895 output_asm_insn (\"creqv 6,6,6\", operands);
10897 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10898 }"
10899 [(set_attr "type" "branch,branch")
10900 (set_attr "length" "4,8")])
10902 (define_expand "sibcall_value"
10903 [(parallel [(set (match_operand 0 "register_operand" "")
10904 (call (mem:SI (match_operand 1 "address_operand" ""))
10905 (match_operand 2 "" "")))
10906 (use (match_operand 3 "" ""))
10907 (use (match_operand 4 "" ""))
10908 (return)])]
10909 ""
10910 "
10911 {
10912 #if TARGET_MACHO
10913 if (MACHOPIC_INDIRECT)
10914 operands[1] = machopic_indirect_call_target (operands[1]);
10915 #endif
10917 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10918 abort ();
10920 operands[1] = XEXP (operands[1], 0);
10921 operands[4] = gen_reg_rtx (SImode);
10923 }")
10925 (define_insn "*sibcall_value_nonlocal_sysv"
10926 [(set (match_operand 0 "" "")
10927 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10928 (match_operand 2 "" "")))
10929 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10930 (use (match_operand:SI 4 "register_operand" "l,l"))
10931 (return)]
10932 "(DEFAULT_ABI == ABI_DARWIN
10933 || DEFAULT_ABI == ABI_V4)
10934 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10935 "*
10936 {
10937 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10938 output_asm_insn (\"crxor 6,6,6\", operands);
10940 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10941 output_asm_insn (\"creqv 6,6,6\", operands);
10943 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10944 }"
10945 [(set_attr "type" "branch,branch")
10946 (set_attr "length" "4,8")])
10948 (define_expand "sibcall_epilogue"
10949 [(use (const_int 0))]
10950 "TARGET_SCHED_PROLOG"
10951 "
10952 {
10953 rs6000_emit_epilogue (TRUE);
10954 DONE;
10955 }")
10957 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10958 ;; all of memory. This blocks insns from being moved across this point.
10960 (define_insn "blockage"
10961 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10962 ""
10963 "")
10964 \f
10965 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10966 ;; signed & unsigned, and one type of branch.
10967 ;;
10968 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10969 ;; insns, and branches. We store the operands of compares until we see
10970 ;; how it is used.
10971 (define_expand "cmpsi"
10972 [(set (cc0)
10973 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10974 (match_operand:SI 1 "reg_or_short_operand" "")))]
10975 ""
10976 "
10977 {
10978 /* Take care of the possibility that operands[1] might be negative but
10979 this might be a logical operation. That insn doesn't exist. */
10980 if (GET_CODE (operands[1]) == CONST_INT
10981 && INTVAL (operands[1]) < 0)
10982 operands[1] = force_reg (SImode, operands[1]);
10984 rs6000_compare_op0 = operands[0];
10985 rs6000_compare_op1 = operands[1];
10986 rs6000_compare_fp_p = 0;
10987 DONE;
10988 }")
10990 (define_expand "cmpdi"
10991 [(set (cc0)
10992 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10993 (match_operand:DI 1 "reg_or_short_operand" "")))]
10994 "TARGET_POWERPC64"
10995 "
10996 {
10997 /* Take care of the possibility that operands[1] might be negative but
10998 this might be a logical operation. That insn doesn't exist. */
10999 if (GET_CODE (operands[1]) == CONST_INT
11000 && INTVAL (operands[1]) < 0)
11001 operands[1] = force_reg (DImode, operands[1]);
11003 rs6000_compare_op0 = operands[0];
11004 rs6000_compare_op1 = operands[1];
11005 rs6000_compare_fp_p = 0;
11006 DONE;
11007 }")
11009 (define_expand "cmpsf"
11010 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
11011 (match_operand:SF 1 "gpc_reg_operand" "")))]
11012 "TARGET_HARD_FLOAT"
11013 "
11014 {
11015 rs6000_compare_op0 = operands[0];
11016 rs6000_compare_op1 = operands[1];
11017 rs6000_compare_fp_p = 1;
11018 DONE;
11019 }")
11021 (define_expand "cmpdf"
11022 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
11023 (match_operand:DF 1 "gpc_reg_operand" "")))]
11024 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
11025 "
11026 {
11027 rs6000_compare_op0 = operands[0];
11028 rs6000_compare_op1 = operands[1];
11029 rs6000_compare_fp_p = 1;
11030 DONE;
11031 }")
11033 (define_expand "cmptf"
11034 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
11035 (match_operand:TF 1 "gpc_reg_operand" "")))]
11036 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11037 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11038 "
11039 {
11040 rs6000_compare_op0 = operands[0];
11041 rs6000_compare_op1 = operands[1];
11042 rs6000_compare_fp_p = 1;
11043 DONE;
11044 }")
11046 (define_expand "beq"
11047 [(use (match_operand 0 "" ""))]
11048 ""
11049 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11051 (define_expand "bne"
11052 [(use (match_operand 0 "" ""))]
11053 ""
11054 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11056 (define_expand "bge"
11057 [(use (match_operand 0 "" ""))]
11058 ""
11059 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11061 (define_expand "bgt"
11062 [(use (match_operand 0 "" ""))]
11063 ""
11064 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11066 (define_expand "ble"
11067 [(use (match_operand 0 "" ""))]
11068 ""
11069 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11071 (define_expand "blt"
11072 [(use (match_operand 0 "" ""))]
11073 ""
11074 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11076 (define_expand "bgeu"
11077 [(use (match_operand 0 "" ""))]
11078 ""
11079 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11081 (define_expand "bgtu"
11082 [(use (match_operand 0 "" ""))]
11083 ""
11084 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11086 (define_expand "bleu"
11087 [(use (match_operand 0 "" ""))]
11088 ""
11089 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11091 (define_expand "bltu"
11092 [(use (match_operand 0 "" ""))]
11093 ""
11094 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11096 (define_expand "bunordered"
11097 [(use (match_operand 0 "" ""))]
11098 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11099 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11101 (define_expand "bordered"
11102 [(use (match_operand 0 "" ""))]
11103 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11104 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11106 (define_expand "buneq"
11107 [(use (match_operand 0 "" ""))]
11108 ""
11109 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11111 (define_expand "bunge"
11112 [(use (match_operand 0 "" ""))]
11113 ""
11114 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11116 (define_expand "bungt"
11117 [(use (match_operand 0 "" ""))]
11118 ""
11119 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11121 (define_expand "bunle"
11122 [(use (match_operand 0 "" ""))]
11123 ""
11124 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11126 (define_expand "bunlt"
11127 [(use (match_operand 0 "" ""))]
11128 ""
11129 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11131 (define_expand "bltgt"
11132 [(use (match_operand 0 "" ""))]
11133 ""
11134 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11136 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11137 ;; For SEQ, likewise, except that comparisons with zero should be done
11138 ;; with an scc insns. However, due to the order that combine see the
11139 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11140 ;; the cases we don't want to handle.
11141 (define_expand "seq"
11142 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11143 ""
11144 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11146 (define_expand "sne"
11147 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11148 ""
11149 "
11150 {
11151 if (! rs6000_compare_fp_p)
11152 FAIL;
11154 rs6000_emit_sCOND (NE, operands[0]);
11155 DONE;
11156 }")
11158 ;; A >= 0 is best done the portable way for A an integer.
11159 (define_expand "sge"
11160 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11161 ""
11162 "
11163 {
11164 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11165 FAIL;
11167 rs6000_emit_sCOND (GE, operands[0]);
11168 DONE;
11169 }")
11171 ;; A > 0 is best done using the portable sequence, so fail in that case.
11172 (define_expand "sgt"
11173 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11174 ""
11175 "
11176 {
11177 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11178 FAIL;
11180 rs6000_emit_sCOND (GT, operands[0]);
11181 DONE;
11182 }")
11184 ;; A <= 0 is best done the portable way for A an integer.
11185 (define_expand "sle"
11186 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11187 ""
11188 "
11189 {
11190 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11191 FAIL;
11193 rs6000_emit_sCOND (LE, operands[0]);
11194 DONE;
11195 }")
11197 ;; A < 0 is best done in the portable way for A an integer.
11198 (define_expand "slt"
11199 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11200 ""
11201 "
11202 {
11203 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11204 FAIL;
11206 rs6000_emit_sCOND (LT, operands[0]);
11207 DONE;
11208 }")
11210 (define_expand "sgeu"
11211 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11212 ""
11213 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11215 (define_expand "sgtu"
11216 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11217 ""
11218 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11220 (define_expand "sleu"
11221 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11222 ""
11223 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11225 (define_expand "sltu"
11226 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11227 ""
11228 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11230 (define_expand "sunordered"
11231 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11232 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11233 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11235 (define_expand "sordered"
11236 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11237 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11238 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11240 (define_expand "suneq"
11241 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11242 ""
11243 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11245 (define_expand "sunge"
11246 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11247 ""
11248 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11250 (define_expand "sungt"
11251 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11252 ""
11253 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11255 (define_expand "sunle"
11256 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11257 ""
11258 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11260 (define_expand "sunlt"
11261 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11262 ""
11263 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11265 (define_expand "sltgt"
11266 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11267 ""
11268 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11270 \f
11271 ;; Here are the actual compare insns.
11272 (define_insn "*cmpsi_internal1"
11273 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11274 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11275 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11276 ""
11277 "{cmp%I2|cmpw%I2} %0,%1,%2"
11278 [(set_attr "type" "cmp")])
11280 (define_insn "*cmpdi_internal1"
11281 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11282 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11283 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11284 "TARGET_POWERPC64"
11285 "cmpd%I2 %0,%1,%2"
11286 [(set_attr "type" "cmp")])
11288 ;; If we are comparing a register for equality with a large constant,
11289 ;; we can do this with an XOR followed by a compare. But we need a scratch
11290 ;; register for the result of the XOR.
11292 (define_split
11293 [(set (match_operand:CC 0 "cc_reg_operand" "")
11294 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11295 (match_operand:SI 2 "non_short_cint_operand" "")))
11296 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11297 "find_single_use (operands[0], insn, 0)
11298 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11299 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11300 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11301 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11302 "
11303 {
11304 /* Get the constant we are comparing against, C, and see what it looks like
11305 sign-extended to 16 bits. Then see what constant could be XOR'ed
11306 with C to get the sign-extended value. */
11308 HOST_WIDE_INT c = INTVAL (operands[2]);
11309 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11310 HOST_WIDE_INT xorv = c ^ sextc;
11312 operands[4] = GEN_INT (xorv);
11313 operands[5] = GEN_INT (sextc);
11314 }")
11316 (define_insn "*cmpsi_internal2"
11317 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11318 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11319 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11320 ""
11321 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11322 [(set_attr "type" "cmp")])
11324 (define_insn "*cmpdi_internal2"
11325 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11326 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11327 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11328 ""
11329 "cmpld%I2 %0,%1,%b2"
11330 [(set_attr "type" "cmp")])
11332 ;; The following two insns don't exist as single insns, but if we provide
11333 ;; them, we can swap an add and compare, which will enable us to overlap more
11334 ;; of the required delay between a compare and branch. We generate code for
11335 ;; them by splitting.
11337 (define_insn ""
11338 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11339 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11340 (match_operand:SI 2 "short_cint_operand" "i")))
11341 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11342 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11343 ""
11344 "#"
11345 [(set_attr "length" "8")])
11347 (define_insn ""
11348 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11349 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11350 (match_operand:SI 2 "u_short_cint_operand" "i")))
11351 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11352 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11353 ""
11354 "#"
11355 [(set_attr "length" "8")])
11357 (define_split
11358 [(set (match_operand:CC 3 "cc_reg_operand" "")
11359 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11360 (match_operand:SI 2 "short_cint_operand" "")))
11361 (set (match_operand:SI 0 "gpc_reg_operand" "")
11362 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11363 ""
11364 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11365 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11367 (define_split
11368 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11369 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11370 (match_operand:SI 2 "u_short_cint_operand" "")))
11371 (set (match_operand:SI 0 "gpc_reg_operand" "")
11372 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11373 ""
11374 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11375 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11377 (define_insn "*cmpsf_internal1"
11378 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11379 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11380 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11381 "TARGET_HARD_FLOAT && TARGET_FPRS"
11382 "fcmpu %0,%1,%2"
11383 [(set_attr "type" "fpcompare")])
11385 (define_insn "*cmpdf_internal1"
11386 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11387 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11388 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11389 "TARGET_HARD_FLOAT && TARGET_FPRS"
11390 "fcmpu %0,%1,%2"
11391 [(set_attr "type" "fpcompare")])
11393 ;; Only need to compare second words if first words equal
11394 (define_insn "*cmptf_internal1"
11395 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11396 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11397 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11398 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11399 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11400 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11401 [(set_attr "type" "fpcompare")
11402 (set_attr "length" "12")])
11404 (define_insn_and_split "*cmptf_internal2"
11405 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11406 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11407 (match_operand:TF 2 "gpc_reg_operand" "f")))
11408 (clobber (match_scratch:DF 3 "=f"))
11409 (clobber (match_scratch:DF 4 "=f"))
11410 (clobber (match_scratch:DF 5 "=f"))
11411 (clobber (match_scratch:DF 6 "=f"))
11412 (clobber (match_scratch:DF 7 "=f"))
11413 (clobber (match_scratch:DF 8 "=f"))
11414 (clobber (match_scratch:DF 9 "=f"))
11415 (clobber (match_scratch:DF 10 "=f"))]
11416 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11417 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11418 "#"
11419 "&& reload_completed"
11420 [(set (match_dup 3) (match_dup 13))
11421 (set (match_dup 4) (match_dup 14))
11422 (set (match_dup 9) (abs:DF (match_dup 5)))
11423 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11424 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11425 (label_ref (match_dup 11))
11426 (pc)))
11427 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11428 (set (pc) (label_ref (match_dup 12)))
11429 (match_dup 11)
11430 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11431 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11432 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11433 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11434 (match_dup 12)]
11435 {
11436 REAL_VALUE_TYPE rv;
11437 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11438 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11440 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11441 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11442 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11443 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11444 operands[11] = gen_label_rtx ();
11445 operands[12] = gen_label_rtx ();
11446 real_inf (&rv);
11447 operands[13] = force_const_mem (DFmode,
11448 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11449 operands[14] = force_const_mem (DFmode,
11450 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11451 DFmode));
11452 if (TARGET_TOC)
11453 {
11454 operands[13] = gen_const_mem (DFmode,
11455 create_TOC_reference (XEXP (operands[13], 0)));
11456 operands[14] = gen_const_mem (DFmode,
11457 create_TOC_reference (XEXP (operands[14], 0)));
11458 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11459 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11460 }
11461 })
11462 \f
11463 ;; Now we have the scc insns. We can do some combinations because of the
11464 ;; way the machine works.
11465 ;;
11466 ;; Note that this is probably faster if we can put an insn between the
11467 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11468 ;; cases the insns below which don't use an intermediate CR field will
11469 ;; be used instead.
11470 (define_insn ""
11471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11472 (match_operator:SI 1 "scc_comparison_operator"
11473 [(match_operand 2 "cc_reg_operand" "y")
11474 (const_int 0)]))]
11475 ""
11476 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11477 [(set (attr "type")
11478 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11479 (const_string "mfcrf")
11480 ]
11481 (const_string "mfcr")))
11482 (set_attr "length" "8")])
11484 ;; Same as above, but get the GT bit.
11485 (define_insn "move_from_CR_gt_bit"
11486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11487 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11488 "TARGET_E500"
11489 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11490 [(set_attr "type" "mfcr")
11491 (set_attr "length" "8")])
11493 ;; Same as above, but get the OV/ORDERED bit.
11494 (define_insn "move_from_CR_ov_bit"
11495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11496 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11497 "TARGET_ISEL"
11498 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11499 [(set_attr "type" "mfcr")
11500 (set_attr "length" "8")])
11502 (define_insn ""
11503 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11504 (match_operator:DI 1 "scc_comparison_operator"
11505 [(match_operand 2 "cc_reg_operand" "y")
11506 (const_int 0)]))]
11507 "TARGET_POWERPC64"
11508 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11509 [(set (attr "type")
11510 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11511 (const_string "mfcrf")
11512 ]
11513 (const_string "mfcr")))
11514 (set_attr "length" "8")])
11516 (define_insn ""
11517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11518 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11519 [(match_operand 2 "cc_reg_operand" "y,y")
11520 (const_int 0)])
11521 (const_int 0)))
11522 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11523 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11524 "TARGET_32BIT"
11525 "@
11526 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11527 #"
11528 [(set_attr "type" "delayed_compare")
11529 (set_attr "length" "8,16")])
11531 (define_split
11532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11533 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11534 [(match_operand 2 "cc_reg_operand" "")
11535 (const_int 0)])
11536 (const_int 0)))
11537 (set (match_operand:SI 3 "gpc_reg_operand" "")
11538 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11539 "TARGET_32BIT && reload_completed"
11540 [(set (match_dup 3)
11541 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11542 (set (match_dup 0)
11543 (compare:CC (match_dup 3)
11544 (const_int 0)))]
11545 "")
11547 (define_insn ""
11548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11549 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11550 [(match_operand 2 "cc_reg_operand" "y")
11551 (const_int 0)])
11552 (match_operand:SI 3 "const_int_operand" "n")))]
11553 ""
11554 "*
11555 {
11556 int is_bit = ccr_bit (operands[1], 1);
11557 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11558 int count;
11560 if (is_bit >= put_bit)
11561 count = is_bit - put_bit;
11562 else
11563 count = 32 - (put_bit - is_bit);
11565 operands[4] = GEN_INT (count);
11566 operands[5] = GEN_INT (put_bit);
11568 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11569 }"
11570 [(set (attr "type")
11571 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11572 (const_string "mfcrf")
11573 ]
11574 (const_string "mfcr")))
11575 (set_attr "length" "8")])
11577 (define_insn ""
11578 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11579 (compare:CC
11580 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11581 [(match_operand 2 "cc_reg_operand" "y,y")
11582 (const_int 0)])
11583 (match_operand:SI 3 "const_int_operand" "n,n"))
11584 (const_int 0)))
11585 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11586 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11587 (match_dup 3)))]
11588 ""
11589 "*
11590 {
11591 int is_bit = ccr_bit (operands[1], 1);
11592 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11593 int count;
11595 /* Force split for non-cc0 compare. */
11596 if (which_alternative == 1)
11597 return \"#\";
11599 if (is_bit >= put_bit)
11600 count = is_bit - put_bit;
11601 else
11602 count = 32 - (put_bit - is_bit);
11604 operands[5] = GEN_INT (count);
11605 operands[6] = GEN_INT (put_bit);
11607 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11608 }"
11609 [(set_attr "type" "delayed_compare")
11610 (set_attr "length" "8,16")])
11612 (define_split
11613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11614 (compare:CC
11615 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11616 [(match_operand 2 "cc_reg_operand" "")
11617 (const_int 0)])
11618 (match_operand:SI 3 "const_int_operand" ""))
11619 (const_int 0)))
11620 (set (match_operand:SI 4 "gpc_reg_operand" "")
11621 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11622 (match_dup 3)))]
11623 "reload_completed"
11624 [(set (match_dup 4)
11625 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11626 (match_dup 3)))
11627 (set (match_dup 0)
11628 (compare:CC (match_dup 4)
11629 (const_int 0)))]
11630 "")
11632 ;; There is a 3 cycle delay between consecutive mfcr instructions
11633 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11635 (define_peephole
11636 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11637 (match_operator:SI 1 "scc_comparison_operator"
11638 [(match_operand 2 "cc_reg_operand" "y")
11639 (const_int 0)]))
11640 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11641 (match_operator:SI 4 "scc_comparison_operator"
11642 [(match_operand 5 "cc_reg_operand" "y")
11643 (const_int 0)]))]
11644 "REGNO (operands[2]) != REGNO (operands[5])"
11645 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11646 [(set_attr "type" "mfcr")
11647 (set_attr "length" "12")])
11649 (define_peephole
11650 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11651 (match_operator:DI 1 "scc_comparison_operator"
11652 [(match_operand 2 "cc_reg_operand" "y")
11653 (const_int 0)]))
11654 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11655 (match_operator:DI 4 "scc_comparison_operator"
11656 [(match_operand 5 "cc_reg_operand" "y")
11657 (const_int 0)]))]
11658 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11659 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11660 [(set_attr "type" "mfcr")
11661 (set_attr "length" "12")])
11663 ;; There are some scc insns that can be done directly, without a compare.
11664 ;; These are faster because they don't involve the communications between
11665 ;; the FXU and branch units. In fact, we will be replacing all of the
11666 ;; integer scc insns here or in the portable methods in emit_store_flag.
11667 ;;
11668 ;; Also support (neg (scc ..)) since that construct is used to replace
11669 ;; branches, (plus (scc ..) ..) since that construct is common and
11670 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11671 ;; cases where it is no more expensive than (neg (scc ..)).
11673 ;; Have reload force a constant into a register for the simple insns that
11674 ;; otherwise won't accept constants. We do this because it is faster than
11675 ;; the cmp/mfcr sequence we would otherwise generate.
11677 (define_insn ""
11678 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11679 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11680 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11681 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11682 "TARGET_32BIT"
11683 "@
11684 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11685 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11686 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11687 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11688 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11689 [(set_attr "type" "three,two,three,three,three")
11690 (set_attr "length" "12,8,12,12,12")])
11692 (define_insn ""
11693 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11694 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11695 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11696 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11697 "TARGET_64BIT"
11698 "@
11699 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11700 subfic %3,%1,0\;adde %0,%3,%1
11701 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11702 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11703 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11704 [(set_attr "type" "three,two,three,three,three")
11705 (set_attr "length" "12,8,12,12,12")])
11707 (define_insn ""
11708 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11709 (compare:CC
11710 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11711 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11712 (const_int 0)))
11713 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11714 (eq:SI (match_dup 1) (match_dup 2)))
11715 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11716 "TARGET_32BIT"
11717 "@
11718 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11719 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11720 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11721 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11722 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11723 #
11724 #
11725 #
11726 #
11727 #"
11728 [(set_attr "type" "compare")
11729 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11731 (define_split
11732 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11733 (compare:CC
11734 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11735 (match_operand:SI 2 "reg_or_cint_operand" ""))
11736 (const_int 0)))
11737 (set (match_operand:SI 0 "gpc_reg_operand" "")
11738 (eq:SI (match_dup 1) (match_dup 2)))
11739 (clobber (match_scratch:SI 3 ""))]
11740 "TARGET_32BIT && reload_completed"
11741 [(parallel [(set (match_dup 0)
11742 (eq:SI (match_dup 1) (match_dup 2)))
11743 (clobber (match_dup 3))])
11744 (set (match_dup 4)
11745 (compare:CC (match_dup 0)
11746 (const_int 0)))]
11747 "")
11749 (define_insn ""
11750 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11751 (compare:CC
11752 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11753 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11754 (const_int 0)))
11755 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11756 (eq:DI (match_dup 1) (match_dup 2)))
11757 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11758 "TARGET_64BIT"
11759 "@
11760 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11761 subfic %3,%1,0\;adde. %0,%3,%1
11762 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11763 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11764 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11765 #
11766 #
11767 #
11768 #
11769 #"
11770 [(set_attr "type" "compare")
11771 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11773 (define_split
11774 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11775 (compare:CC
11776 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11777 (match_operand:DI 2 "reg_or_cint_operand" ""))
11778 (const_int 0)))
11779 (set (match_operand:DI 0 "gpc_reg_operand" "")
11780 (eq:DI (match_dup 1) (match_dup 2)))
11781 (clobber (match_scratch:DI 3 ""))]
11782 "TARGET_64BIT && reload_completed"
11783 [(parallel [(set (match_dup 0)
11784 (eq:DI (match_dup 1) (match_dup 2)))
11785 (clobber (match_dup 3))])
11786 (set (match_dup 4)
11787 (compare:CC (match_dup 0)
11788 (const_int 0)))]
11789 "")
11791 ;; We have insns of the form shown by the first define_insn below. If
11792 ;; there is something inside the comparison operation, we must split it.
11793 (define_split
11794 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11795 (plus:SI (match_operator 1 "comparison_operator"
11796 [(match_operand:SI 2 "" "")
11797 (match_operand:SI 3
11798 "reg_or_cint_operand" "")])
11799 (match_operand:SI 4 "gpc_reg_operand" "")))
11800 (clobber (match_operand:SI 5 "register_operand" ""))]
11801 "! gpc_reg_operand (operands[2], SImode)"
11802 [(set (match_dup 5) (match_dup 2))
11803 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11804 (match_dup 4)))])
11806 (define_insn ""
11807 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11808 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11809 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11810 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11811 "TARGET_32BIT"
11812 "@
11813 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11814 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11815 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11816 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11817 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11818 [(set_attr "type" "three,two,three,three,three")
11819 (set_attr "length" "12,8,12,12,12")])
11821 (define_insn ""
11822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11823 (compare:CC
11824 (plus:SI
11825 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11826 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11827 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11828 (const_int 0)))
11829 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11830 "TARGET_32BIT"
11831 "@
11832 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11833 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11834 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11835 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11836 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11837 #
11838 #
11839 #
11840 #
11841 #"
11842 [(set_attr "type" "compare")
11843 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11845 (define_split
11846 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11847 (compare:CC
11848 (plus:SI
11849 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11850 (match_operand:SI 2 "reg_or_cint_operand" ""))
11851 (match_operand:SI 3 "gpc_reg_operand" ""))
11852 (const_int 0)))
11853 (clobber (match_scratch:SI 4 ""))]
11854 "TARGET_32BIT && reload_completed"
11855 [(set (match_dup 4)
11856 (plus:SI (eq:SI (match_dup 1)
11857 (match_dup 2))
11858 (match_dup 3)))
11859 (set (match_dup 0)
11860 (compare:CC (match_dup 4)
11861 (const_int 0)))]
11862 "")
11864 (define_insn ""
11865 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11866 (compare:CC
11867 (plus:SI
11868 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11869 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11870 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11871 (const_int 0)))
11872 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11873 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11874 "TARGET_32BIT"
11875 "@
11876 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11877 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11878 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11879 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11880 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11881 #
11882 #
11883 #
11884 #
11885 #"
11886 [(set_attr "type" "compare")
11887 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11889 (define_split
11890 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11891 (compare:CC
11892 (plus:SI
11893 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11894 (match_operand:SI 2 "reg_or_cint_operand" ""))
11895 (match_operand:SI 3 "gpc_reg_operand" ""))
11896 (const_int 0)))
11897 (set (match_operand:SI 0 "gpc_reg_operand" "")
11898 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11899 "TARGET_32BIT && reload_completed"
11900 [(set (match_dup 0)
11901 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11902 (set (match_dup 4)
11903 (compare:CC (match_dup 0)
11904 (const_int 0)))]
11905 "")
11907 (define_insn ""
11908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11909 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11910 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11911 "TARGET_32BIT"
11912 "@
11913 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11914 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11915 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11916 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11917 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11918 [(set_attr "type" "three,two,three,three,three")
11919 (set_attr "length" "12,8,12,12,12")])
11921 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11922 ;; since it nabs/sr is just as fast.
11923 (define_insn "*ne0"
11924 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11925 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11926 (const_int 31)))
11927 (clobber (match_scratch:SI 2 "=&r"))]
11928 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11929 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11930 [(set_attr "type" "two")
11931 (set_attr "length" "8")])
11933 (define_insn ""
11934 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11935 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11936 (const_int 63)))
11937 (clobber (match_scratch:DI 2 "=&r"))]
11938 "TARGET_64BIT"
11939 "addic %2,%1,-1\;subfe %0,%2,%1"
11940 [(set_attr "type" "two")
11941 (set_attr "length" "8")])
11943 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11944 (define_insn ""
11945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11946 (plus:SI (lshiftrt:SI
11947 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11948 (const_int 31))
11949 (match_operand:SI 2 "gpc_reg_operand" "r")))
11950 (clobber (match_scratch:SI 3 "=&r"))]
11951 "TARGET_32BIT"
11952 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11953 [(set_attr "type" "two")
11954 (set_attr "length" "8")])
11956 (define_insn ""
11957 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11958 (plus:DI (lshiftrt:DI
11959 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11960 (const_int 63))
11961 (match_operand:DI 2 "gpc_reg_operand" "r")))
11962 (clobber (match_scratch:DI 3 "=&r"))]
11963 "TARGET_64BIT"
11964 "addic %3,%1,-1\;addze %0,%2"
11965 [(set_attr "type" "two")
11966 (set_attr "length" "8")])
11968 (define_insn ""
11969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11970 (compare:CC
11971 (plus:SI (lshiftrt:SI
11972 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11973 (const_int 31))
11974 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11975 (const_int 0)))
11976 (clobber (match_scratch:SI 3 "=&r,&r"))
11977 (clobber (match_scratch:SI 4 "=X,&r"))]
11978 "TARGET_32BIT"
11979 "@
11980 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11981 #"
11982 [(set_attr "type" "compare")
11983 (set_attr "length" "8,12")])
11985 (define_split
11986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11987 (compare:CC
11988 (plus:SI (lshiftrt:SI
11989 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11990 (const_int 31))
11991 (match_operand:SI 2 "gpc_reg_operand" ""))
11992 (const_int 0)))
11993 (clobber (match_scratch:SI 3 ""))
11994 (clobber (match_scratch:SI 4 ""))]
11995 "TARGET_32BIT && reload_completed"
11996 [(parallel [(set (match_dup 3)
11997 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11998 (const_int 31))
11999 (match_dup 2)))
12000 (clobber (match_dup 4))])
12001 (set (match_dup 0)
12002 (compare:CC (match_dup 3)
12003 (const_int 0)))]
12004 "")
12006 (define_insn ""
12007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12008 (compare:CC
12009 (plus:DI (lshiftrt:DI
12010 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12011 (const_int 63))
12012 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12013 (const_int 0)))
12014 (clobber (match_scratch:DI 3 "=&r,&r"))]
12015 "TARGET_64BIT"
12016 "@
12017 addic %3,%1,-1\;addze. %3,%2
12018 #"
12019 [(set_attr "type" "compare")
12020 (set_attr "length" "8,12")])
12022 (define_split
12023 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12024 (compare:CC
12025 (plus:DI (lshiftrt:DI
12026 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12027 (const_int 63))
12028 (match_operand:DI 2 "gpc_reg_operand" ""))
12029 (const_int 0)))
12030 (clobber (match_scratch:DI 3 ""))]
12031 "TARGET_64BIT && reload_completed"
12032 [(set (match_dup 3)
12033 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12034 (const_int 63))
12035 (match_dup 2)))
12036 (set (match_dup 0)
12037 (compare:CC (match_dup 3)
12038 (const_int 0)))]
12039 "")
12041 (define_insn ""
12042 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12043 (compare:CC
12044 (plus:SI (lshiftrt:SI
12045 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12046 (const_int 31))
12047 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12048 (const_int 0)))
12049 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12050 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12051 (match_dup 2)))
12052 (clobber (match_scratch:SI 3 "=&r,&r"))]
12053 "TARGET_32BIT"
12054 "@
12055 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12056 #"
12057 [(set_attr "type" "compare")
12058 (set_attr "length" "8,12")])
12060 (define_split
12061 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12062 (compare:CC
12063 (plus:SI (lshiftrt:SI
12064 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12065 (const_int 31))
12066 (match_operand:SI 2 "gpc_reg_operand" ""))
12067 (const_int 0)))
12068 (set (match_operand:SI 0 "gpc_reg_operand" "")
12069 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12070 (match_dup 2)))
12071 (clobber (match_scratch:SI 3 ""))]
12072 "TARGET_32BIT && reload_completed"
12073 [(parallel [(set (match_dup 0)
12074 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12075 (match_dup 2)))
12076 (clobber (match_dup 3))])
12077 (set (match_dup 4)
12078 (compare:CC (match_dup 0)
12079 (const_int 0)))]
12080 "")
12082 (define_insn ""
12083 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12084 (compare:CC
12085 (plus:DI (lshiftrt:DI
12086 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12087 (const_int 63))
12088 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12089 (const_int 0)))
12090 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12091 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12092 (match_dup 2)))
12093 (clobber (match_scratch:DI 3 "=&r,&r"))]
12094 "TARGET_64BIT"
12095 "@
12096 addic %3,%1,-1\;addze. %0,%2
12097 #"
12098 [(set_attr "type" "compare")
12099 (set_attr "length" "8,12")])
12101 (define_split
12102 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12103 (compare:CC
12104 (plus:DI (lshiftrt:DI
12105 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12106 (const_int 63))
12107 (match_operand:DI 2 "gpc_reg_operand" ""))
12108 (const_int 0)))
12109 (set (match_operand:DI 0 "gpc_reg_operand" "")
12110 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12111 (match_dup 2)))
12112 (clobber (match_scratch:DI 3 ""))]
12113 "TARGET_64BIT && reload_completed"
12114 [(parallel [(set (match_dup 0)
12115 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12116 (match_dup 2)))
12117 (clobber (match_dup 3))])
12118 (set (match_dup 4)
12119 (compare:CC (match_dup 0)
12120 (const_int 0)))]
12121 "")
12123 (define_insn ""
12124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12125 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12126 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12127 (clobber (match_scratch:SI 3 "=r,X"))]
12128 "TARGET_POWER"
12129 "@
12130 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12131 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12132 [(set_attr "length" "12")])
12134 (define_insn ""
12135 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12136 (compare:CC
12137 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12138 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12139 (const_int 0)))
12140 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12141 (le:SI (match_dup 1) (match_dup 2)))
12142 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12143 "TARGET_POWER"
12144 "@
12145 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12146 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12147 #
12148 #"
12149 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12150 (set_attr "length" "12,12,16,16")])
12152 (define_split
12153 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12154 (compare:CC
12155 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12156 (match_operand:SI 2 "reg_or_short_operand" ""))
12157 (const_int 0)))
12158 (set (match_operand:SI 0 "gpc_reg_operand" "")
12159 (le:SI (match_dup 1) (match_dup 2)))
12160 (clobber (match_scratch:SI 3 ""))]
12161 "TARGET_POWER && reload_completed"
12162 [(parallel [(set (match_dup 0)
12163 (le:SI (match_dup 1) (match_dup 2)))
12164 (clobber (match_dup 3))])
12165 (set (match_dup 4)
12166 (compare:CC (match_dup 0)
12167 (const_int 0)))]
12168 "")
12170 (define_insn ""
12171 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12172 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12173 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12174 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12175 "TARGET_POWER"
12176 "@
12177 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12178 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12179 [(set_attr "length" "12")])
12181 (define_insn ""
12182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12183 (compare:CC
12184 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12185 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12186 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12187 (const_int 0)))
12188 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12189 "TARGET_POWER"
12190 "@
12191 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12192 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12193 #
12194 #"
12195 [(set_attr "type" "compare")
12196 (set_attr "length" "12,12,16,16")])
12198 (define_split
12199 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12200 (compare:CC
12201 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12202 (match_operand:SI 2 "reg_or_short_operand" ""))
12203 (match_operand:SI 3 "gpc_reg_operand" ""))
12204 (const_int 0)))
12205 (clobber (match_scratch:SI 4 ""))]
12206 "TARGET_POWER && reload_completed"
12207 [(set (match_dup 4)
12208 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12209 (match_dup 3)))
12210 (set (match_dup 0)
12211 (compare:CC (match_dup 4)
12212 (const_int 0)))]
12213 "")
12215 (define_insn ""
12216 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12217 (compare:CC
12218 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12219 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12220 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12221 (const_int 0)))
12222 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12223 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12224 "TARGET_POWER"
12225 "@
12226 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12227 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12228 #
12229 #"
12230 [(set_attr "type" "compare")
12231 (set_attr "length" "12,12,16,16")])
12233 (define_split
12234 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12235 (compare:CC
12236 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12237 (match_operand:SI 2 "reg_or_short_operand" ""))
12238 (match_operand:SI 3 "gpc_reg_operand" ""))
12239 (const_int 0)))
12240 (set (match_operand:SI 0 "gpc_reg_operand" "")
12241 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12242 "TARGET_POWER && reload_completed"
12243 [(set (match_dup 0)
12244 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12245 (set (match_dup 4)
12246 (compare:CC (match_dup 0)
12247 (const_int 0)))]
12248 "")
12250 (define_insn ""
12251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12252 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12253 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12254 "TARGET_POWER"
12255 "@
12256 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12257 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12258 [(set_attr "length" "12")])
12260 (define_insn ""
12261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12262 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12263 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12264 "TARGET_32BIT"
12265 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12266 [(set_attr "type" "three")
12267 (set_attr "length" "12")])
12269 (define_insn ""
12270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12271 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12272 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12273 "TARGET_64BIT"
12274 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12275 [(set_attr "type" "three")
12276 (set_attr "length" "12")])
12278 (define_insn ""
12279 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12280 (compare:CC
12281 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12282 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12283 (const_int 0)))
12284 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12285 (leu:DI (match_dup 1) (match_dup 2)))]
12286 "TARGET_64BIT"
12287 "@
12288 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12289 #"
12290 [(set_attr "type" "compare")
12291 (set_attr "length" "12,16")])
12293 (define_split
12294 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12295 (compare:CC
12296 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12297 (match_operand:DI 2 "reg_or_short_operand" ""))
12298 (const_int 0)))
12299 (set (match_operand:DI 0 "gpc_reg_operand" "")
12300 (leu:DI (match_dup 1) (match_dup 2)))]
12301 "TARGET_64BIT && reload_completed"
12302 [(set (match_dup 0)
12303 (leu:DI (match_dup 1) (match_dup 2)))
12304 (set (match_dup 3)
12305 (compare:CC (match_dup 0)
12306 (const_int 0)))]
12307 "")
12309 (define_insn ""
12310 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12311 (compare:CC
12312 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12313 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12314 (const_int 0)))
12315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12316 (leu:SI (match_dup 1) (match_dup 2)))]
12317 "TARGET_32BIT"
12318 "@
12319 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12320 #"
12321 [(set_attr "type" "compare")
12322 (set_attr "length" "12,16")])
12324 (define_split
12325 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12326 (compare:CC
12327 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12328 (match_operand:SI 2 "reg_or_short_operand" ""))
12329 (const_int 0)))
12330 (set (match_operand:SI 0 "gpc_reg_operand" "")
12331 (leu:SI (match_dup 1) (match_dup 2)))]
12332 "TARGET_32BIT && reload_completed"
12333 [(set (match_dup 0)
12334 (leu:SI (match_dup 1) (match_dup 2)))
12335 (set (match_dup 3)
12336 (compare:CC (match_dup 0)
12337 (const_int 0)))]
12338 "")
12340 (define_insn ""
12341 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12342 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12343 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12344 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12345 "TARGET_32BIT"
12346 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12347 [(set_attr "type" "two")
12348 (set_attr "length" "8")])
12350 (define_insn ""
12351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12352 (compare:CC
12353 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12354 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12355 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12356 (const_int 0)))
12357 (clobber (match_scratch:SI 4 "=&r,&r"))]
12358 "TARGET_32BIT"
12359 "@
12360 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12361 #"
12362 [(set_attr "type" "compare")
12363 (set_attr "length" "8,12")])
12365 (define_split
12366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12367 (compare:CC
12368 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12369 (match_operand:SI 2 "reg_or_short_operand" ""))
12370 (match_operand:SI 3 "gpc_reg_operand" ""))
12371 (const_int 0)))
12372 (clobber (match_scratch:SI 4 ""))]
12373 "TARGET_32BIT && reload_completed"
12374 [(set (match_dup 4)
12375 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12376 (match_dup 3)))
12377 (set (match_dup 0)
12378 (compare:CC (match_dup 4)
12379 (const_int 0)))]
12380 "")
12382 (define_insn ""
12383 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12384 (compare:CC
12385 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12386 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12387 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12388 (const_int 0)))
12389 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12390 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12391 "TARGET_32BIT"
12392 "@
12393 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12394 #"
12395 [(set_attr "type" "compare")
12396 (set_attr "length" "8,12")])
12398 (define_split
12399 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12400 (compare:CC
12401 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12402 (match_operand:SI 2 "reg_or_short_operand" ""))
12403 (match_operand:SI 3 "gpc_reg_operand" ""))
12404 (const_int 0)))
12405 (set (match_operand:SI 0 "gpc_reg_operand" "")
12406 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12407 "TARGET_32BIT && reload_completed"
12408 [(set (match_dup 0)
12409 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12410 (set (match_dup 4)
12411 (compare:CC (match_dup 0)
12412 (const_int 0)))]
12413 "")
12415 (define_insn ""
12416 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12417 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12418 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12419 "TARGET_32BIT"
12420 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12421 [(set_attr "type" "three")
12422 (set_attr "length" "12")])
12424 (define_insn ""
12425 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12426 (and:SI (neg:SI
12427 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12428 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12429 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12430 "TARGET_32BIT"
12431 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12432 [(set_attr "type" "three")
12433 (set_attr "length" "12")])
12435 (define_insn ""
12436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12437 (compare:CC
12438 (and:SI (neg:SI
12439 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12440 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12441 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12442 (const_int 0)))
12443 (clobber (match_scratch:SI 4 "=&r,&r"))]
12444 "TARGET_32BIT"
12445 "@
12446 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12447 #"
12448 [(set_attr "type" "compare")
12449 (set_attr "length" "12,16")])
12451 (define_split
12452 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12453 (compare:CC
12454 (and:SI (neg:SI
12455 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12456 (match_operand:SI 2 "reg_or_short_operand" "")))
12457 (match_operand:SI 3 "gpc_reg_operand" ""))
12458 (const_int 0)))
12459 (clobber (match_scratch:SI 4 ""))]
12460 "TARGET_32BIT && reload_completed"
12461 [(set (match_dup 4)
12462 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12463 (match_dup 3)))
12464 (set (match_dup 0)
12465 (compare:CC (match_dup 4)
12466 (const_int 0)))]
12467 "")
12469 (define_insn ""
12470 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12471 (compare:CC
12472 (and:SI (neg:SI
12473 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12474 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12475 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12476 (const_int 0)))
12477 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12478 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12479 "TARGET_32BIT"
12480 "@
12481 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12482 #"
12483 [(set_attr "type" "compare")
12484 (set_attr "length" "12,16")])
12486 (define_split
12487 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12488 (compare:CC
12489 (and:SI (neg:SI
12490 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12491 (match_operand:SI 2 "reg_or_short_operand" "")))
12492 (match_operand:SI 3 "gpc_reg_operand" ""))
12493 (const_int 0)))
12494 (set (match_operand:SI 0 "gpc_reg_operand" "")
12495 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12496 "TARGET_32BIT && reload_completed"
12497 [(set (match_dup 0)
12498 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12499 (match_dup 3)))
12500 (set (match_dup 4)
12501 (compare:CC (match_dup 0)
12502 (const_int 0)))]
12503 "")
12505 (define_insn ""
12506 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12507 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12508 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12509 "TARGET_POWER"
12510 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12511 [(set_attr "length" "12")])
12513 (define_insn ""
12514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12515 (compare:CC
12516 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12517 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12518 (const_int 0)))
12519 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12520 (lt:SI (match_dup 1) (match_dup 2)))]
12521 "TARGET_POWER"
12522 "@
12523 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12524 #"
12525 [(set_attr "type" "delayed_compare")
12526 (set_attr "length" "12,16")])
12528 (define_split
12529 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12530 (compare:CC
12531 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12532 (match_operand:SI 2 "reg_or_short_operand" ""))
12533 (const_int 0)))
12534 (set (match_operand:SI 0 "gpc_reg_operand" "")
12535 (lt:SI (match_dup 1) (match_dup 2)))]
12536 "TARGET_POWER && reload_completed"
12537 [(set (match_dup 0)
12538 (lt:SI (match_dup 1) (match_dup 2)))
12539 (set (match_dup 3)
12540 (compare:CC (match_dup 0)
12541 (const_int 0)))]
12542 "")
12544 (define_insn ""
12545 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12546 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12547 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12548 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12549 "TARGET_POWER"
12550 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12551 [(set_attr "length" "12")])
12553 (define_insn ""
12554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12555 (compare:CC
12556 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12557 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12558 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12559 (const_int 0)))
12560 (clobber (match_scratch:SI 4 "=&r,&r"))]
12561 "TARGET_POWER"
12562 "@
12563 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12564 #"
12565 [(set_attr "type" "compare")
12566 (set_attr "length" "12,16")])
12568 (define_split
12569 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12570 (compare:CC
12571 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12572 (match_operand:SI 2 "reg_or_short_operand" ""))
12573 (match_operand:SI 3 "gpc_reg_operand" ""))
12574 (const_int 0)))
12575 (clobber (match_scratch:SI 4 ""))]
12576 "TARGET_POWER && reload_completed"
12577 [(set (match_dup 4)
12578 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12579 (match_dup 3)))
12580 (set (match_dup 0)
12581 (compare:CC (match_dup 4)
12582 (const_int 0)))]
12583 "")
12585 (define_insn ""
12586 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12587 (compare:CC
12588 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12589 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12590 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12591 (const_int 0)))
12592 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12593 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12594 "TARGET_POWER"
12595 "@
12596 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12597 #"
12598 [(set_attr "type" "compare")
12599 (set_attr "length" "12,16")])
12601 (define_split
12602 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12603 (compare:CC
12604 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12605 (match_operand:SI 2 "reg_or_short_operand" ""))
12606 (match_operand:SI 3 "gpc_reg_operand" ""))
12607 (const_int 0)))
12608 (set (match_operand:SI 0 "gpc_reg_operand" "")
12609 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12610 "TARGET_POWER && reload_completed"
12611 [(set (match_dup 0)
12612 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12613 (set (match_dup 4)
12614 (compare:CC (match_dup 0)
12615 (const_int 0)))]
12616 "")
12618 (define_insn ""
12619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12620 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12621 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12622 "TARGET_POWER"
12623 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12624 [(set_attr "length" "12")])
12626 (define_insn_and_split ""
12627 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12628 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12629 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12630 "TARGET_32BIT"
12631 "#"
12632 "TARGET_32BIT"
12633 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12634 (set (match_dup 0) (neg:SI (match_dup 0)))]
12635 "")
12637 (define_insn_and_split ""
12638 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12639 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12640 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12641 "TARGET_64BIT"
12642 "#"
12643 "TARGET_64BIT"
12644 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12645 (set (match_dup 0) (neg:DI (match_dup 0)))]
12646 "")
12648 (define_insn ""
12649 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12650 (compare:CC
12651 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12652 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12653 (const_int 0)))
12654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12655 (ltu:SI (match_dup 1) (match_dup 2)))]
12656 "TARGET_32BIT"
12657 "@
12658 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12659 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12660 #
12661 #"
12662 [(set_attr "type" "compare")
12663 (set_attr "length" "12,12,16,16")])
12665 (define_split
12666 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12667 (compare:CC
12668 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12669 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12670 (const_int 0)))
12671 (set (match_operand:SI 0 "gpc_reg_operand" "")
12672 (ltu:SI (match_dup 1) (match_dup 2)))]
12673 "TARGET_32BIT && reload_completed"
12674 [(set (match_dup 0)
12675 (ltu:SI (match_dup 1) (match_dup 2)))
12676 (set (match_dup 3)
12677 (compare:CC (match_dup 0)
12678 (const_int 0)))]
12679 "")
12681 (define_insn_and_split ""
12682 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12683 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12684 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12685 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12686 "TARGET_32BIT"
12687 "#"
12688 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12689 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12690 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12691 "")
12693 (define_insn_and_split ""
12694 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12695 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12696 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12697 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12698 "TARGET_64BIT"
12699 "#"
12700 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12701 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12702 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12703 "")
12705 (define_insn ""
12706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12707 (compare:CC
12708 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12709 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12710 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12711 (const_int 0)))
12712 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12713 "TARGET_32BIT"
12714 "@
12715 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12716 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12717 #
12718 #"
12719 [(set_attr "type" "compare")
12720 (set_attr "length" "12,12,16,16")])
12722 (define_split
12723 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12724 (compare:CC
12725 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12726 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12727 (match_operand:SI 3 "gpc_reg_operand" ""))
12728 (const_int 0)))
12729 (clobber (match_scratch:SI 4 ""))]
12730 "TARGET_32BIT && reload_completed"
12731 [(set (match_dup 4)
12732 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12733 (match_dup 3)))
12734 (set (match_dup 0)
12735 (compare:CC (match_dup 4)
12736 (const_int 0)))]
12737 "")
12739 (define_insn ""
12740 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12741 (compare:CC
12742 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12743 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12744 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12745 (const_int 0)))
12746 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12747 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12748 "TARGET_32BIT"
12749 "@
12750 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12751 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12752 #
12753 #"
12754 [(set_attr "type" "compare")
12755 (set_attr "length" "12,12,16,16")])
12757 (define_split
12758 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12759 (compare:CC
12760 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12761 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12762 (match_operand:SI 3 "gpc_reg_operand" ""))
12763 (const_int 0)))
12764 (set (match_operand:SI 0 "gpc_reg_operand" "")
12765 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12766 "TARGET_32BIT && reload_completed"
12767 [(set (match_dup 0)
12768 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12769 (set (match_dup 4)
12770 (compare:CC (match_dup 0)
12771 (const_int 0)))]
12772 "")
12774 (define_insn ""
12775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12776 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12777 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12778 "TARGET_32BIT"
12779 "@
12780 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12781 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12782 [(set_attr "type" "two")
12783 (set_attr "length" "8")])
12785 (define_insn ""
12786 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12787 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12788 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12789 "TARGET_64BIT"
12790 "@
12791 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12792 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12793 [(set_attr "type" "two")
12794 (set_attr "length" "8")])
12796 (define_insn ""
12797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12798 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12799 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12800 (clobber (match_scratch:SI 3 "=r"))]
12801 "TARGET_POWER"
12802 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12803 [(set_attr "length" "12")])
12805 (define_insn ""
12806 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12807 (compare:CC
12808 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12809 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12810 (const_int 0)))
12811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12812 (ge:SI (match_dup 1) (match_dup 2)))
12813 (clobber (match_scratch:SI 3 "=r,r"))]
12814 "TARGET_POWER"
12815 "@
12816 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12817 #"
12818 [(set_attr "type" "compare")
12819 (set_attr "length" "12,16")])
12821 (define_split
12822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12823 (compare:CC
12824 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12825 (match_operand:SI 2 "reg_or_short_operand" ""))
12826 (const_int 0)))
12827 (set (match_operand:SI 0 "gpc_reg_operand" "")
12828 (ge:SI (match_dup 1) (match_dup 2)))
12829 (clobber (match_scratch:SI 3 ""))]
12830 "TARGET_POWER && reload_completed"
12831 [(parallel [(set (match_dup 0)
12832 (ge:SI (match_dup 1) (match_dup 2)))
12833 (clobber (match_dup 3))])
12834 (set (match_dup 4)
12835 (compare:CC (match_dup 0)
12836 (const_int 0)))]
12837 "")
12839 (define_insn ""
12840 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12841 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12842 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12843 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12844 "TARGET_POWER"
12845 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12846 [(set_attr "length" "12")])
12848 (define_insn ""
12849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12850 (compare:CC
12851 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12852 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12853 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12854 (const_int 0)))
12855 (clobber (match_scratch:SI 4 "=&r,&r"))]
12856 "TARGET_POWER"
12857 "@
12858 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12859 #"
12860 [(set_attr "type" "compare")
12861 (set_attr "length" "12,16")])
12863 (define_split
12864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12865 (compare:CC
12866 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12867 (match_operand:SI 2 "reg_or_short_operand" ""))
12868 (match_operand:SI 3 "gpc_reg_operand" ""))
12869 (const_int 0)))
12870 (clobber (match_scratch:SI 4 ""))]
12871 "TARGET_POWER && reload_completed"
12872 [(set (match_dup 4)
12873 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12874 (match_dup 3)))
12875 (set (match_dup 0)
12876 (compare:CC (match_dup 4)
12877 (const_int 0)))]
12878 "")
12880 (define_insn ""
12881 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12882 (compare:CC
12883 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12884 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12885 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12886 (const_int 0)))
12887 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12888 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12889 "TARGET_POWER"
12890 "@
12891 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12892 #"
12893 [(set_attr "type" "compare")
12894 (set_attr "length" "12,16")])
12896 (define_split
12897 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12898 (compare:CC
12899 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12900 (match_operand:SI 2 "reg_or_short_operand" ""))
12901 (match_operand:SI 3 "gpc_reg_operand" ""))
12902 (const_int 0)))
12903 (set (match_operand:SI 0 "gpc_reg_operand" "")
12904 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12905 "TARGET_POWER && reload_completed"
12906 [(set (match_dup 0)
12907 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12908 (set (match_dup 4)
12909 (compare:CC (match_dup 0)
12910 (const_int 0)))]
12911 "")
12913 (define_insn ""
12914 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12915 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12916 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12917 "TARGET_POWER"
12918 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12919 [(set_attr "length" "12")])
12921 (define_insn ""
12922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12923 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12924 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12925 "TARGET_32BIT"
12926 "@
12927 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12928 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12929 [(set_attr "type" "three")
12930 (set_attr "length" "12")])
12932 (define_insn ""
12933 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12934 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12935 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12936 "TARGET_64BIT"
12937 "@
12938 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12939 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12940 [(set_attr "type" "three")
12941 (set_attr "length" "12")])
12943 (define_insn ""
12944 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12945 (compare:CC
12946 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12947 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12948 (const_int 0)))
12949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12950 (geu:SI (match_dup 1) (match_dup 2)))]
12951 "TARGET_32BIT"
12952 "@
12953 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12954 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12955 #
12956 #"
12957 [(set_attr "type" "compare")
12958 (set_attr "length" "12,12,16,16")])
12960 (define_split
12961 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12962 (compare:CC
12963 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12964 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12965 (const_int 0)))
12966 (set (match_operand:SI 0 "gpc_reg_operand" "")
12967 (geu:SI (match_dup 1) (match_dup 2)))]
12968 "TARGET_32BIT && reload_completed"
12969 [(set (match_dup 0)
12970 (geu:SI (match_dup 1) (match_dup 2)))
12971 (set (match_dup 3)
12972 (compare:CC (match_dup 0)
12973 (const_int 0)))]
12974 "")
12976 (define_insn ""
12977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12978 (compare:CC
12979 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12980 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12981 (const_int 0)))
12982 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12983 (geu:DI (match_dup 1) (match_dup 2)))]
12984 "TARGET_64BIT"
12985 "@
12986 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12987 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12988 #
12989 #"
12990 [(set_attr "type" "compare")
12991 (set_attr "length" "12,12,16,16")])
12993 (define_split
12994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12995 (compare:CC
12996 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12997 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12998 (const_int 0)))
12999 (set (match_operand:DI 0 "gpc_reg_operand" "")
13000 (geu:DI (match_dup 1) (match_dup 2)))]
13001 "TARGET_64BIT && reload_completed"
13002 [(set (match_dup 0)
13003 (geu:DI (match_dup 1) (match_dup 2)))
13004 (set (match_dup 3)
13005 (compare:CC (match_dup 0)
13006 (const_int 0)))]
13007 "")
13009 (define_insn ""
13010 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13011 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13012 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
13013 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13014 "TARGET_32BIT"
13015 "@
13016 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13017 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13018 [(set_attr "type" "two")
13019 (set_attr "length" "8")])
13021 (define_insn ""
13022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13023 (compare:CC
13024 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13025 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13026 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13027 (const_int 0)))
13028 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13029 "TARGET_32BIT"
13030 "@
13031 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13032 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13033 #
13034 #"
13035 [(set_attr "type" "compare")
13036 (set_attr "length" "8,8,12,12")])
13038 (define_split
13039 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13040 (compare:CC
13041 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13042 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13043 (match_operand:SI 3 "gpc_reg_operand" ""))
13044 (const_int 0)))
13045 (clobber (match_scratch:SI 4 ""))]
13046 "TARGET_32BIT && reload_completed"
13047 [(set (match_dup 4)
13048 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13049 (match_dup 3)))
13050 (set (match_dup 0)
13051 (compare:CC (match_dup 4)
13052 (const_int 0)))]
13053 "")
13055 (define_insn ""
13056 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13057 (compare:CC
13058 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13059 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13060 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13061 (const_int 0)))
13062 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13063 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13064 "TARGET_32BIT"
13065 "@
13066 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13067 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13068 #
13069 #"
13070 [(set_attr "type" "compare")
13071 (set_attr "length" "8,8,12,12")])
13073 (define_split
13074 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13075 (compare:CC
13076 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13077 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13078 (match_operand:SI 3 "gpc_reg_operand" ""))
13079 (const_int 0)))
13080 (set (match_operand:SI 0 "gpc_reg_operand" "")
13081 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13082 "TARGET_32BIT && reload_completed"
13083 [(set (match_dup 0)
13084 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13085 (set (match_dup 4)
13086 (compare:CC (match_dup 0)
13087 (const_int 0)))]
13088 "")
13090 (define_insn ""
13091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13092 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13093 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
13094 "TARGET_32BIT"
13095 "@
13096 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13097 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13098 [(set_attr "type" "three")
13099 (set_attr "length" "12")])
13101 (define_insn ""
13102 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13103 (and:SI (neg:SI
13104 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13105 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
13106 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13107 "TARGET_32BIT"
13108 "@
13109 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13110 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13111 [(set_attr "type" "three")
13112 (set_attr "length" "12")])
13114 (define_insn ""
13115 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13116 (compare:CC
13117 (and:SI (neg:SI
13118 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13119 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13120 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13121 (const_int 0)))
13122 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13123 "TARGET_32BIT"
13124 "@
13125 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13126 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13127 #
13128 #"
13129 [(set_attr "type" "compare")
13130 (set_attr "length" "12,12,16,16")])
13132 (define_split
13133 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13134 (compare:CC
13135 (and:SI (neg:SI
13136 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13137 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13138 (match_operand:SI 3 "gpc_reg_operand" ""))
13139 (const_int 0)))
13140 (clobber (match_scratch:SI 4 ""))]
13141 "TARGET_32BIT && reload_completed"
13142 [(set (match_dup 4)
13143 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13144 (match_dup 3)))
13145 (set (match_dup 0)
13146 (compare:CC (match_dup 4)
13147 (const_int 0)))]
13148 "")
13150 (define_insn ""
13151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13152 (compare:CC
13153 (and:SI (neg:SI
13154 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13155 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13156 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13157 (const_int 0)))
13158 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13159 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13160 "TARGET_32BIT"
13161 "@
13162 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13163 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13164 #
13165 #"
13166 [(set_attr "type" "compare")
13167 (set_attr "length" "12,12,16,16")])
13169 (define_split
13170 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13171 (compare:CC
13172 (and:SI (neg:SI
13173 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13174 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13175 (match_operand:SI 3 "gpc_reg_operand" ""))
13176 (const_int 0)))
13177 (set (match_operand:SI 0 "gpc_reg_operand" "")
13178 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13179 "TARGET_32BIT && reload_completed"
13180 [(set (match_dup 0)
13181 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13182 (set (match_dup 4)
13183 (compare:CC (match_dup 0)
13184 (const_int 0)))]
13185 "")
13187 (define_insn ""
13188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13189 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13190 (const_int 0)))]
13191 "TARGET_32BIT"
13192 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13193 [(set_attr "type" "three")
13194 (set_attr "length" "12")])
13196 (define_insn ""
13197 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13198 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13199 (const_int 0)))]
13200 "TARGET_64BIT"
13201 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13202 [(set_attr "type" "three")
13203 (set_attr "length" "12")])
13205 (define_insn ""
13206 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13207 (compare:CC
13208 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13209 (const_int 0))
13210 (const_int 0)))
13211 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13212 (gt:SI (match_dup 1) (const_int 0)))]
13213 "TARGET_32BIT"
13214 "@
13215 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13216 #"
13217 [(set_attr "type" "delayed_compare")
13218 (set_attr "length" "12,16")])
13220 (define_split
13221 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13222 (compare:CC
13223 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13224 (const_int 0))
13225 (const_int 0)))
13226 (set (match_operand:SI 0 "gpc_reg_operand" "")
13227 (gt:SI (match_dup 1) (const_int 0)))]
13228 "TARGET_32BIT && reload_completed"
13229 [(set (match_dup 0)
13230 (gt:SI (match_dup 1) (const_int 0)))
13231 (set (match_dup 2)
13232 (compare:CC (match_dup 0)
13233 (const_int 0)))]
13234 "")
13236 (define_insn ""
13237 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13238 (compare:CC
13239 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13240 (const_int 0))
13241 (const_int 0)))
13242 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13243 (gt:DI (match_dup 1) (const_int 0)))]
13244 "TARGET_64BIT"
13245 "@
13246 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13247 #"
13248 [(set_attr "type" "delayed_compare")
13249 (set_attr "length" "12,16")])
13251 (define_split
13252 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13253 (compare:CC
13254 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13255 (const_int 0))
13256 (const_int 0)))
13257 (set (match_operand:DI 0 "gpc_reg_operand" "")
13258 (gt:DI (match_dup 1) (const_int 0)))]
13259 "TARGET_64BIT && reload_completed"
13260 [(set (match_dup 0)
13261 (gt:DI (match_dup 1) (const_int 0)))
13262 (set (match_dup 2)
13263 (compare:CC (match_dup 0)
13264 (const_int 0)))]
13265 "")
13267 (define_insn ""
13268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13269 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13270 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13271 "TARGET_POWER"
13272 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13273 [(set_attr "length" "12")])
13275 (define_insn ""
13276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13277 (compare:CC
13278 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13279 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13280 (const_int 0)))
13281 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13282 (gt:SI (match_dup 1) (match_dup 2)))]
13283 "TARGET_POWER"
13284 "@
13285 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13286 #"
13287 [(set_attr "type" "delayed_compare")
13288 (set_attr "length" "12,16")])
13290 (define_split
13291 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13292 (compare:CC
13293 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13294 (match_operand:SI 2 "reg_or_short_operand" ""))
13295 (const_int 0)))
13296 (set (match_operand:SI 0 "gpc_reg_operand" "")
13297 (gt:SI (match_dup 1) (match_dup 2)))]
13298 "TARGET_POWER && reload_completed"
13299 [(set (match_dup 0)
13300 (gt:SI (match_dup 1) (match_dup 2)))
13301 (set (match_dup 3)
13302 (compare:CC (match_dup 0)
13303 (const_int 0)))]
13304 "")
13306 (define_insn ""
13307 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13308 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13309 (const_int 0))
13310 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13311 "TARGET_32BIT"
13312 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13313 [(set_attr "type" "three")
13314 (set_attr "length" "12")])
13316 (define_insn ""
13317 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13318 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13319 (const_int 0))
13320 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13321 "TARGET_64BIT"
13322 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13323 [(set_attr "type" "three")
13324 (set_attr "length" "12")])
13326 (define_insn ""
13327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13328 (compare:CC
13329 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13330 (const_int 0))
13331 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13332 (const_int 0)))
13333 (clobber (match_scratch:SI 3 "=&r,&r"))]
13334 "TARGET_32BIT"
13335 "@
13336 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13337 #"
13338 [(set_attr "type" "compare")
13339 (set_attr "length" "12,16")])
13341 (define_split
13342 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13343 (compare:CC
13344 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13345 (const_int 0))
13346 (match_operand:SI 2 "gpc_reg_operand" ""))
13347 (const_int 0)))
13348 (clobber (match_scratch:SI 3 ""))]
13349 "TARGET_32BIT && reload_completed"
13350 [(set (match_dup 3)
13351 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13352 (match_dup 2)))
13353 (set (match_dup 0)
13354 (compare:CC (match_dup 3)
13355 (const_int 0)))]
13356 "")
13358 (define_insn ""
13359 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13360 (compare:CC
13361 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13362 (const_int 0))
13363 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13364 (const_int 0)))
13365 (clobber (match_scratch:DI 3 "=&r,&r"))]
13366 "TARGET_64BIT"
13367 "@
13368 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13369 #"
13370 [(set_attr "type" "compare")
13371 (set_attr "length" "12,16")])
13373 (define_split
13374 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13375 (compare:CC
13376 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13377 (const_int 0))
13378 (match_operand:DI 2 "gpc_reg_operand" ""))
13379 (const_int 0)))
13380 (clobber (match_scratch:DI 3 ""))]
13381 "TARGET_64BIT && reload_completed"
13382 [(set (match_dup 3)
13383 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13384 (match_dup 2)))
13385 (set (match_dup 0)
13386 (compare:CC (match_dup 3)
13387 (const_int 0)))]
13388 "")
13390 (define_insn ""
13391 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13392 (compare:CC
13393 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13394 (const_int 0))
13395 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13396 (const_int 0)))
13397 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13398 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13399 "TARGET_32BIT"
13400 "@
13401 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13402 #"
13403 [(set_attr "type" "compare")
13404 (set_attr "length" "12,16")])
13406 (define_split
13407 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13408 (compare:CC
13409 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13410 (const_int 0))
13411 (match_operand:SI 2 "gpc_reg_operand" ""))
13412 (const_int 0)))
13413 (set (match_operand:SI 0 "gpc_reg_operand" "")
13414 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13415 "TARGET_32BIT && reload_completed"
13416 [(set (match_dup 0)
13417 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13418 (set (match_dup 3)
13419 (compare:CC (match_dup 0)
13420 (const_int 0)))]
13421 "")
13423 (define_insn ""
13424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13425 (compare:CC
13426 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13427 (const_int 0))
13428 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13429 (const_int 0)))
13430 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13431 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13432 "TARGET_64BIT"
13433 "@
13434 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13435 #"
13436 [(set_attr "type" "compare")
13437 (set_attr "length" "12,16")])
13439 (define_split
13440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13441 (compare:CC
13442 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13443 (const_int 0))
13444 (match_operand:DI 2 "gpc_reg_operand" ""))
13445 (const_int 0)))
13446 (set (match_operand:DI 0 "gpc_reg_operand" "")
13447 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13448 "TARGET_64BIT && reload_completed"
13449 [(set (match_dup 0)
13450 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13451 (set (match_dup 3)
13452 (compare:CC (match_dup 0)
13453 (const_int 0)))]
13454 "")
13456 (define_insn ""
13457 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13458 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13459 (match_operand:SI 2 "reg_or_short_operand" "r"))
13460 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13461 "TARGET_POWER"
13462 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13463 [(set_attr "length" "12")])
13465 (define_insn ""
13466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13467 (compare:CC
13468 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13469 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13470 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13471 (const_int 0)))
13472 (clobber (match_scratch:SI 4 "=&r,&r"))]
13473 "TARGET_POWER"
13474 "@
13475 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13476 #"
13477 [(set_attr "type" "compare")
13478 (set_attr "length" "12,16")])
13480 (define_split
13481 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13482 (compare:CC
13483 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13484 (match_operand:SI 2 "reg_or_short_operand" ""))
13485 (match_operand:SI 3 "gpc_reg_operand" ""))
13486 (const_int 0)))
13487 (clobber (match_scratch:SI 4 ""))]
13488 "TARGET_POWER && reload_completed"
13489 [(set (match_dup 4)
13490 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13491 (set (match_dup 0)
13492 (compare:CC (match_dup 4)
13493 (const_int 0)))]
13494 "")
13496 (define_insn ""
13497 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13498 (compare:CC
13499 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13500 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13501 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13502 (const_int 0)))
13503 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13504 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13505 "TARGET_POWER"
13506 "@
13507 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13508 #"
13509 [(set_attr "type" "compare")
13510 (set_attr "length" "12,16")])
13512 (define_split
13513 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13514 (compare:CC
13515 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13516 (match_operand:SI 2 "reg_or_short_operand" ""))
13517 (match_operand:SI 3 "gpc_reg_operand" ""))
13518 (const_int 0)))
13519 (set (match_operand:SI 0 "gpc_reg_operand" "")
13520 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13521 "TARGET_POWER && reload_completed"
13522 [(set (match_dup 0)
13523 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13524 (set (match_dup 4)
13525 (compare:CC (match_dup 0)
13526 (const_int 0)))]
13527 "")
13529 (define_insn ""
13530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13531 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13532 (const_int 0))))]
13533 "TARGET_32BIT"
13534 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13535 [(set_attr "type" "three")
13536 (set_attr "length" "12")])
13538 (define_insn ""
13539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13540 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13541 (const_int 0))))]
13542 "TARGET_64BIT"
13543 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13544 [(set_attr "type" "three")
13545 (set_attr "length" "12")])
13547 (define_insn ""
13548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13549 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13550 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13551 "TARGET_POWER"
13552 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13553 [(set_attr "length" "12")])
13555 (define_insn_and_split ""
13556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13557 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13558 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13559 "TARGET_32BIT"
13560 "#"
13561 "TARGET_32BIT"
13562 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13563 (set (match_dup 0) (neg:SI (match_dup 0)))]
13564 "")
13566 (define_insn_and_split ""
13567 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13568 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13569 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13570 "TARGET_64BIT"
13571 "#"
13572 "TARGET_64BIT"
13573 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13574 (set (match_dup 0) (neg:DI (match_dup 0)))]
13575 "")
13577 (define_insn ""
13578 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13579 (compare:CC
13580 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13581 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13582 (const_int 0)))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13584 (gtu:SI (match_dup 1) (match_dup 2)))]
13585 "TARGET_32BIT"
13586 "@
13587 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13588 #"
13589 [(set_attr "type" "compare")
13590 (set_attr "length" "12,16")])
13592 (define_split
13593 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13594 (compare:CC
13595 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13596 (match_operand:SI 2 "reg_or_short_operand" ""))
13597 (const_int 0)))
13598 (set (match_operand:SI 0 "gpc_reg_operand" "")
13599 (gtu:SI (match_dup 1) (match_dup 2)))]
13600 "TARGET_32BIT && reload_completed"
13601 [(set (match_dup 0)
13602 (gtu:SI (match_dup 1) (match_dup 2)))
13603 (set (match_dup 3)
13604 (compare:CC (match_dup 0)
13605 (const_int 0)))]
13606 "")
13608 (define_insn ""
13609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13610 (compare:CC
13611 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13612 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13613 (const_int 0)))
13614 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13615 (gtu:DI (match_dup 1) (match_dup 2)))]
13616 "TARGET_64BIT"
13617 "@
13618 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13619 #"
13620 [(set_attr "type" "compare")
13621 (set_attr "length" "12,16")])
13623 (define_split
13624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13625 (compare:CC
13626 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13627 (match_operand:DI 2 "reg_or_short_operand" ""))
13628 (const_int 0)))
13629 (set (match_operand:DI 0 "gpc_reg_operand" "")
13630 (gtu:DI (match_dup 1) (match_dup 2)))]
13631 "TARGET_64BIT && reload_completed"
13632 [(set (match_dup 0)
13633 (gtu:DI (match_dup 1) (match_dup 2)))
13634 (set (match_dup 3)
13635 (compare:CC (match_dup 0)
13636 (const_int 0)))]
13637 "")
13639 (define_insn_and_split ""
13640 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13641 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13642 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13643 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13644 "TARGET_32BIT"
13645 "#"
13646 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13647 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13648 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13649 "")
13651 (define_insn_and_split ""
13652 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13653 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13654 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13655 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13656 "TARGET_64BIT"
13657 "#"
13658 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13659 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13660 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13661 "")
13663 (define_insn ""
13664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13665 (compare:CC
13666 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13667 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13668 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13669 (const_int 0)))
13670 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13671 "TARGET_32BIT"
13672 "@
13673 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13674 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13675 #
13676 #"
13677 [(set_attr "type" "compare")
13678 (set_attr "length" "8,12,12,16")])
13680 (define_split
13681 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13682 (compare:CC
13683 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13684 (match_operand:SI 2 "reg_or_short_operand" ""))
13685 (match_operand:SI 3 "gpc_reg_operand" ""))
13686 (const_int 0)))
13687 (clobber (match_scratch:SI 4 ""))]
13688 "TARGET_32BIT && reload_completed"
13689 [(set (match_dup 4)
13690 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13691 (match_dup 3)))
13692 (set (match_dup 0)
13693 (compare:CC (match_dup 4)
13694 (const_int 0)))]
13695 "")
13697 (define_insn ""
13698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13699 (compare:CC
13700 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13701 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13702 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13703 (const_int 0)))
13704 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13705 "TARGET_64BIT"
13706 "@
13707 addic %4,%1,%k2\;addze. %4,%3
13708 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13709 #
13710 #"
13711 [(set_attr "type" "compare")
13712 (set_attr "length" "8,12,12,16")])
13714 (define_split
13715 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13716 (compare:CC
13717 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13718 (match_operand:DI 2 "reg_or_short_operand" ""))
13719 (match_operand:DI 3 "gpc_reg_operand" ""))
13720 (const_int 0)))
13721 (clobber (match_scratch:DI 4 ""))]
13722 "TARGET_64BIT && reload_completed"
13723 [(set (match_dup 4)
13724 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13725 (match_dup 3)))
13726 (set (match_dup 0)
13727 (compare:CC (match_dup 4)
13728 (const_int 0)))]
13729 "")
13731 (define_insn ""
13732 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13733 (compare:CC
13734 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13735 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13736 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13737 (const_int 0)))
13738 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13739 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13740 "TARGET_32BIT"
13741 "@
13742 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13743 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13744 #
13745 #"
13746 [(set_attr "type" "compare")
13747 (set_attr "length" "8,12,12,16")])
13749 (define_split
13750 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13751 (compare:CC
13752 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13753 (match_operand:SI 2 "reg_or_short_operand" ""))
13754 (match_operand:SI 3 "gpc_reg_operand" ""))
13755 (const_int 0)))
13756 (set (match_operand:SI 0 "gpc_reg_operand" "")
13757 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13758 "TARGET_32BIT && reload_completed"
13759 [(set (match_dup 0)
13760 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13761 (set (match_dup 4)
13762 (compare:CC (match_dup 0)
13763 (const_int 0)))]
13764 "")
13766 (define_insn ""
13767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13768 (compare:CC
13769 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13770 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13771 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13772 (const_int 0)))
13773 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13774 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13775 "TARGET_64BIT"
13776 "@
13777 addic %0,%1,%k2\;addze. %0,%3
13778 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13779 #
13780 #"
13781 [(set_attr "type" "compare")
13782 (set_attr "length" "8,12,12,16")])
13784 (define_split
13785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13786 (compare:CC
13787 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13788 (match_operand:DI 2 "reg_or_short_operand" ""))
13789 (match_operand:DI 3 "gpc_reg_operand" ""))
13790 (const_int 0)))
13791 (set (match_operand:DI 0 "gpc_reg_operand" "")
13792 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13793 "TARGET_64BIT && reload_completed"
13794 [(set (match_dup 0)
13795 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13796 (set (match_dup 4)
13797 (compare:CC (match_dup 0)
13798 (const_int 0)))]
13799 "")
13801 (define_insn ""
13802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13803 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13804 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13805 "TARGET_32BIT"
13806 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13807 [(set_attr "type" "two")
13808 (set_attr "length" "8")])
13810 (define_insn ""
13811 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13812 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13813 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13814 "TARGET_64BIT"
13815 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13816 [(set_attr "type" "two")
13817 (set_attr "length" "8")])
13818 \f
13819 ;; Define both directions of branch and return. If we need a reload
13820 ;; register, we'd rather use CR0 since it is much easier to copy a
13821 ;; register CC value to there.
13823 (define_insn ""
13824 [(set (pc)
13825 (if_then_else (match_operator 1 "branch_comparison_operator"
13826 [(match_operand 2
13827 "cc_reg_operand" "y")
13828 (const_int 0)])
13829 (label_ref (match_operand 0 "" ""))
13830 (pc)))]
13831 ""
13832 "*
13833 {
13834 return output_cbranch (operands[1], \"%l0\", 0, insn);
13835 }"
13836 [(set_attr "type" "branch")])
13838 (define_insn ""
13839 [(set (pc)
13840 (if_then_else (match_operator 0 "branch_comparison_operator"
13841 [(match_operand 1
13842 "cc_reg_operand" "y")
13843 (const_int 0)])
13844 (return)
13845 (pc)))]
13846 "direct_return ()"
13847 "*
13848 {
13849 return output_cbranch (operands[0], NULL, 0, insn);
13850 }"
13851 [(set_attr "type" "branch")
13852 (set_attr "length" "4")])
13854 (define_insn ""
13855 [(set (pc)
13856 (if_then_else (match_operator 1 "branch_comparison_operator"
13857 [(match_operand 2
13858 "cc_reg_operand" "y")
13859 (const_int 0)])
13860 (pc)
13861 (label_ref (match_operand 0 "" ""))))]
13862 ""
13863 "*
13864 {
13865 return output_cbranch (operands[1], \"%l0\", 1, insn);
13866 }"
13867 [(set_attr "type" "branch")])
13869 (define_insn ""
13870 [(set (pc)
13871 (if_then_else (match_operator 0 "branch_comparison_operator"
13872 [(match_operand 1
13873 "cc_reg_operand" "y")
13874 (const_int 0)])
13875 (pc)
13876 (return)))]
13877 "direct_return ()"
13878 "*
13879 {
13880 return output_cbranch (operands[0], NULL, 1, insn);
13881 }"
13882 [(set_attr "type" "branch")
13883 (set_attr "length" "4")])
13885 ;; Logic on condition register values.
13887 ; This pattern matches things like
13888 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13889 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13890 ; (const_int 1)))
13891 ; which are generated by the branch logic.
13892 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13894 (define_insn "*cceq_ior_compare"
13895 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13896 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13897 [(match_operator:SI 2
13898 "branch_positive_comparison_operator"
13899 [(match_operand 3
13900 "cc_reg_operand" "y,y")
13901 (const_int 0)])
13902 (match_operator:SI 4
13903 "branch_positive_comparison_operator"
13904 [(match_operand 5
13905 "cc_reg_operand" "0,y")
13906 (const_int 0)])])
13907 (const_int 1)))]
13908 ""
13909 "cr%q1 %E0,%j2,%j4"
13910 [(set_attr "type" "cr_logical,delayed_cr")])
13912 ; Why is the constant -1 here, but 1 in the previous pattern?
13913 ; Because ~1 has all but the low bit set.
13914 (define_insn ""
13915 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13916 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13917 [(not:SI (match_operator:SI 2
13918 "branch_positive_comparison_operator"
13919 [(match_operand 3
13920 "cc_reg_operand" "y,y")
13921 (const_int 0)]))
13922 (match_operator:SI 4
13923 "branch_positive_comparison_operator"
13924 [(match_operand 5
13925 "cc_reg_operand" "0,y")
13926 (const_int 0)])])
13927 (const_int -1)))]
13928 ""
13929 "cr%q1 %E0,%j2,%j4"
13930 [(set_attr "type" "cr_logical,delayed_cr")])
13932 (define_insn "*cceq_rev_compare"
13933 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13934 (compare:CCEQ (match_operator:SI 1
13935 "branch_positive_comparison_operator"
13936 [(match_operand 2
13937 "cc_reg_operand" "0,y")
13938 (const_int 0)])
13939 (const_int 0)))]
13940 ""
13941 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13942 [(set_attr "type" "cr_logical,delayed_cr")])
13944 ;; If we are comparing the result of two comparisons, this can be done
13945 ;; using creqv or crxor.
13947 (define_insn_and_split ""
13948 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13949 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13950 [(match_operand 2 "cc_reg_operand" "y")
13951 (const_int 0)])
13952 (match_operator 3 "branch_comparison_operator"
13953 [(match_operand 4 "cc_reg_operand" "y")
13954 (const_int 0)])))]
13955 ""
13956 "#"
13957 ""
13958 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13959 (match_dup 5)))]
13960 "
13961 {
13962 int positive_1, positive_2;
13964 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13965 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13967 if (! positive_1)
13968 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13969 GET_CODE (operands[1])),
13970 SImode,
13971 operands[2], const0_rtx);
13972 else if (GET_MODE (operands[1]) != SImode)
13973 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13974 operands[2], const0_rtx);
13976 if (! positive_2)
13977 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13978 GET_CODE (operands[3])),
13979 SImode,
13980 operands[4], const0_rtx);
13981 else if (GET_MODE (operands[3]) != SImode)
13982 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13983 operands[4], const0_rtx);
13985 if (positive_1 == positive_2)
13986 {
13987 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13988 operands[5] = constm1_rtx;
13989 }
13990 else
13991 {
13992 operands[5] = const1_rtx;
13993 }
13994 }")
13996 ;; Unconditional branch and return.
13998 (define_insn "jump"
13999 [(set (pc)
14000 (label_ref (match_operand 0 "" "")))]
14001 ""
14002 "b %l0"
14003 [(set_attr "type" "branch")])
14005 (define_insn "return"
14006 [(return)]
14007 "direct_return ()"
14008 "{br|blr}"
14009 [(set_attr "type" "jmpreg")])
14011 (define_expand "indirect_jump"
14012 [(set (pc) (match_operand 0 "register_operand" ""))]
14013 ""
14014 "
14015 {
14016 if (TARGET_32BIT)
14017 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
14018 else
14019 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
14020 DONE;
14021 }")
14023 (define_insn "indirect_jumpsi"
14024 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
14025 "TARGET_32BIT"
14026 "@
14027 bctr
14028 {br|blr}"
14029 [(set_attr "type" "jmpreg")])
14031 (define_insn "indirect_jumpdi"
14032 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
14033 "TARGET_64BIT"
14034 "@
14035 bctr
14036 blr"
14037 [(set_attr "type" "jmpreg")])
14039 ;; Table jump for switch statements:
14040 (define_expand "tablejump"
14041 [(use (match_operand 0 "" ""))
14042 (use (label_ref (match_operand 1 "" "")))]
14043 ""
14044 "
14045 {
14046 if (TARGET_32BIT)
14047 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14048 else
14049 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14050 DONE;
14051 }")
14053 (define_expand "tablejumpsi"
14054 [(set (match_dup 3)
14055 (plus:SI (match_operand:SI 0 "" "")
14056 (match_dup 2)))
14057 (parallel [(set (pc) (match_dup 3))
14058 (use (label_ref (match_operand 1 "" "")))])]
14059 "TARGET_32BIT"
14060 "
14061 { operands[0] = force_reg (SImode, operands[0]);
14062 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14063 operands[3] = gen_reg_rtx (SImode);
14064 }")
14066 (define_expand "tablejumpdi"
14067 [(set (match_dup 4)
14068 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
14069 (set (match_dup 3)
14070 (plus:DI (match_dup 4)
14071 (match_dup 2)))
14072 (parallel [(set (pc) (match_dup 3))
14073 (use (label_ref (match_operand 1 "" "")))])]
14074 "TARGET_64BIT"
14075 "
14076 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14077 operands[3] = gen_reg_rtx (DImode);
14078 operands[4] = gen_reg_rtx (DImode);
14079 }")
14081 (define_insn ""
14082 [(set (pc)
14083 (match_operand:SI 0 "register_operand" "c,*l"))
14084 (use (label_ref (match_operand 1 "" "")))]
14085 "TARGET_32BIT"
14086 "@
14087 bctr
14088 {br|blr}"
14089 [(set_attr "type" "jmpreg")])
14091 (define_insn ""
14092 [(set (pc)
14093 (match_operand:DI 0 "register_operand" "c,*l"))
14094 (use (label_ref (match_operand 1 "" "")))]
14095 "TARGET_64BIT"
14096 "@
14097 bctr
14098 blr"
14099 [(set_attr "type" "jmpreg")])
14101 (define_insn "nop"
14102 [(const_int 0)]
14103 ""
14104 "{cror 0,0,0|nop}")
14105 \f
14106 ;; Define the subtract-one-and-jump insns, starting with the template
14107 ;; so loop.c knows what to generate.
14109 (define_expand "doloop_end"
14110 [(use (match_operand 0 "" "")) ; loop pseudo
14111 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14112 (use (match_operand 2 "" "")) ; max iterations
14113 (use (match_operand 3 "" "")) ; loop level
14114 (use (match_operand 4 "" ""))] ; label
14115 ""
14116 "
14117 {
14118 /* Only use this on innermost loops. */
14119 if (INTVAL (operands[3]) > 1)
14120 FAIL;
14121 if (TARGET_64BIT)
14122 {
14123 if (GET_MODE (operands[0]) != DImode)
14124 FAIL;
14125 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14126 }
14127 else
14128 {
14129 if (GET_MODE (operands[0]) != SImode)
14130 FAIL;
14131 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14132 }
14133 DONE;
14134 }")
14136 (define_expand "ctrsi"
14137 [(parallel [(set (pc)
14138 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
14139 (const_int 1))
14140 (label_ref (match_operand 1 "" ""))
14141 (pc)))
14142 (set (match_dup 0)
14143 (plus:SI (match_dup 0)
14144 (const_int -1)))
14145 (clobber (match_scratch:CC 2 ""))
14146 (clobber (match_scratch:SI 3 ""))])]
14147 "TARGET_32BIT"
14148 "")
14150 (define_expand "ctrdi"
14151 [(parallel [(set (pc)
14152 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
14153 (const_int 1))
14154 (label_ref (match_operand 1 "" ""))
14155 (pc)))
14156 (set (match_dup 0)
14157 (plus:DI (match_dup 0)
14158 (const_int -1)))
14159 (clobber (match_scratch:CC 2 ""))
14160 (clobber (match_scratch:DI 3 ""))])]
14161 "TARGET_64BIT"
14162 "")
14164 ;; We need to be able to do this for any operand, including MEM, or we
14165 ;; will cause reload to blow up since we don't allow output reloads on
14166 ;; JUMP_INSNs.
14167 ;; For the length attribute to be calculated correctly, the
14168 ;; label MUST be operand 0.
14170 (define_insn "*ctrsi_internal1"
14171 [(set (pc)
14172 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14173 (const_int 1))
14174 (label_ref (match_operand 0 "" ""))
14175 (pc)))
14176 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14177 (plus:SI (match_dup 1)
14178 (const_int -1)))
14179 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14180 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14181 "TARGET_32BIT"
14182 "*
14183 {
14184 if (which_alternative != 0)
14185 return \"#\";
14186 else if (get_attr_length (insn) == 4)
14187 return \"{bdn|bdnz} %l0\";
14188 else
14189 return \"bdz $+8\;b %l0\";
14190 }"
14191 [(set_attr "type" "branch")
14192 (set_attr "length" "*,12,16,16")])
14194 (define_insn "*ctrsi_internal2"
14195 [(set (pc)
14196 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14197 (const_int 1))
14198 (pc)
14199 (label_ref (match_operand 0 "" ""))))
14200 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14201 (plus:SI (match_dup 1)
14202 (const_int -1)))
14203 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14204 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14205 "TARGET_32BIT"
14206 "*
14207 {
14208 if (which_alternative != 0)
14209 return \"#\";
14210 else if (get_attr_length (insn) == 4)
14211 return \"bdz %l0\";
14212 else
14213 return \"{bdn|bdnz} $+8\;b %l0\";
14214 }"
14215 [(set_attr "type" "branch")
14216 (set_attr "length" "*,12,16,16")])
14218 (define_insn "*ctrdi_internal1"
14219 [(set (pc)
14220 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14221 (const_int 1))
14222 (label_ref (match_operand 0 "" ""))
14223 (pc)))
14224 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14225 (plus:DI (match_dup 1)
14226 (const_int -1)))
14227 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14228 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14229 "TARGET_64BIT"
14230 "*
14231 {
14232 if (which_alternative != 0)
14233 return \"#\";
14234 else if (get_attr_length (insn) == 4)
14235 return \"{bdn|bdnz} %l0\";
14236 else
14237 return \"bdz $+8\;b %l0\";
14238 }"
14239 [(set_attr "type" "branch")
14240 (set_attr "length" "*,12,16,16")])
14242 (define_insn "*ctrdi_internal2"
14243 [(set (pc)
14244 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14245 (const_int 1))
14246 (pc)
14247 (label_ref (match_operand 0 "" ""))))
14248 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14249 (plus:DI (match_dup 1)
14250 (const_int -1)))
14251 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14252 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14253 "TARGET_64BIT"
14254 "*
14255 {
14256 if (which_alternative != 0)
14257 return \"#\";
14258 else if (get_attr_length (insn) == 4)
14259 return \"bdz %l0\";
14260 else
14261 return \"{bdn|bdnz} $+8\;b %l0\";
14262 }"
14263 [(set_attr "type" "branch")
14264 (set_attr "length" "*,12,16,16")])
14266 ;; Similar but use EQ
14268 (define_insn "*ctrsi_internal5"
14269 [(set (pc)
14270 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14271 (const_int 1))
14272 (label_ref (match_operand 0 "" ""))
14273 (pc)))
14274 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14275 (plus:SI (match_dup 1)
14276 (const_int -1)))
14277 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14278 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14279 "TARGET_32BIT"
14280 "*
14281 {
14282 if (which_alternative != 0)
14283 return \"#\";
14284 else if (get_attr_length (insn) == 4)
14285 return \"bdz %l0\";
14286 else
14287 return \"{bdn|bdnz} $+8\;b %l0\";
14288 }"
14289 [(set_attr "type" "branch")
14290 (set_attr "length" "*,12,16,16")])
14292 (define_insn "*ctrsi_internal6"
14293 [(set (pc)
14294 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14295 (const_int 1))
14296 (pc)
14297 (label_ref (match_operand 0 "" ""))))
14298 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14299 (plus:SI (match_dup 1)
14300 (const_int -1)))
14301 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14302 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14303 "TARGET_32BIT"
14304 "*
14305 {
14306 if (which_alternative != 0)
14307 return \"#\";
14308 else if (get_attr_length (insn) == 4)
14309 return \"{bdn|bdnz} %l0\";
14310 else
14311 return \"bdz $+8\;b %l0\";
14312 }"
14313 [(set_attr "type" "branch")
14314 (set_attr "length" "*,12,16,16")])
14316 (define_insn "*ctrdi_internal5"
14317 [(set (pc)
14318 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14319 (const_int 1))
14320 (label_ref (match_operand 0 "" ""))
14321 (pc)))
14322 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14323 (plus:DI (match_dup 1)
14324 (const_int -1)))
14325 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14326 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14327 "TARGET_64BIT"
14328 "*
14329 {
14330 if (which_alternative != 0)
14331 return \"#\";
14332 else if (get_attr_length (insn) == 4)
14333 return \"bdz %l0\";
14334 else
14335 return \"{bdn|bdnz} $+8\;b %l0\";
14336 }"
14337 [(set_attr "type" "branch")
14338 (set_attr "length" "*,12,16,16")])
14340 (define_insn "*ctrdi_internal6"
14341 [(set (pc)
14342 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14343 (const_int 1))
14344 (pc)
14345 (label_ref (match_operand 0 "" ""))))
14346 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14347 (plus:DI (match_dup 1)
14348 (const_int -1)))
14349 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14350 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14351 "TARGET_64BIT"
14352 "*
14353 {
14354 if (which_alternative != 0)
14355 return \"#\";
14356 else if (get_attr_length (insn) == 4)
14357 return \"{bdn|bdnz} %l0\";
14358 else
14359 return \"bdz $+8\;b %l0\";
14360 }"
14361 [(set_attr "type" "branch")
14362 (set_attr "length" "*,12,16,16")])
14364 ;; Now the splitters if we could not allocate the CTR register
14366 (define_split
14367 [(set (pc)
14368 (if_then_else (match_operator 2 "comparison_operator"
14369 [(match_operand:SI 1 "gpc_reg_operand" "")
14370 (const_int 1)])
14371 (match_operand 5 "" "")
14372 (match_operand 6 "" "")))
14373 (set (match_operand:SI 0 "gpc_reg_operand" "")
14374 (plus:SI (match_dup 1)
14375 (const_int -1)))
14376 (clobber (match_scratch:CC 3 ""))
14377 (clobber (match_scratch:SI 4 ""))]
14378 "TARGET_32BIT && reload_completed"
14379 [(parallel [(set (match_dup 3)
14380 (compare:CC (plus:SI (match_dup 1)
14381 (const_int -1))
14382 (const_int 0)))
14383 (set (match_dup 0)
14384 (plus:SI (match_dup 1)
14385 (const_int -1)))])
14386 (set (pc) (if_then_else (match_dup 7)
14387 (match_dup 5)
14388 (match_dup 6)))]
14389 "
14390 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14391 operands[3], const0_rtx); }")
14393 (define_split
14394 [(set (pc)
14395 (if_then_else (match_operator 2 "comparison_operator"
14396 [(match_operand:SI 1 "gpc_reg_operand" "")
14397 (const_int 1)])
14398 (match_operand 5 "" "")
14399 (match_operand 6 "" "")))
14400 (set (match_operand:SI 0 "nonimmediate_operand" "")
14401 (plus:SI (match_dup 1) (const_int -1)))
14402 (clobber (match_scratch:CC 3 ""))
14403 (clobber (match_scratch:SI 4 ""))]
14404 "TARGET_32BIT && reload_completed
14405 && ! gpc_reg_operand (operands[0], SImode)"
14406 [(parallel [(set (match_dup 3)
14407 (compare:CC (plus:SI (match_dup 1)
14408 (const_int -1))
14409 (const_int 0)))
14410 (set (match_dup 4)
14411 (plus:SI (match_dup 1)
14412 (const_int -1)))])
14413 (set (match_dup 0)
14414 (match_dup 4))
14415 (set (pc) (if_then_else (match_dup 7)
14416 (match_dup 5)
14417 (match_dup 6)))]
14418 "
14419 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14420 operands[3], const0_rtx); }")
14421 (define_split
14422 [(set (pc)
14423 (if_then_else (match_operator 2 "comparison_operator"
14424 [(match_operand:DI 1 "gpc_reg_operand" "")
14425 (const_int 1)])
14426 (match_operand 5 "" "")
14427 (match_operand 6 "" "")))
14428 (set (match_operand:DI 0 "gpc_reg_operand" "")
14429 (plus:DI (match_dup 1)
14430 (const_int -1)))
14431 (clobber (match_scratch:CC 3 ""))
14432 (clobber (match_scratch:DI 4 ""))]
14433 "TARGET_64BIT && reload_completed"
14434 [(parallel [(set (match_dup 3)
14435 (compare:CC (plus:DI (match_dup 1)
14436 (const_int -1))
14437 (const_int 0)))
14438 (set (match_dup 0)
14439 (plus:DI (match_dup 1)
14440 (const_int -1)))])
14441 (set (pc) (if_then_else (match_dup 7)
14442 (match_dup 5)
14443 (match_dup 6)))]
14444 "
14445 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14446 operands[3], const0_rtx); }")
14448 (define_split
14449 [(set (pc)
14450 (if_then_else (match_operator 2 "comparison_operator"
14451 [(match_operand:DI 1 "gpc_reg_operand" "")
14452 (const_int 1)])
14453 (match_operand 5 "" "")
14454 (match_operand 6 "" "")))
14455 (set (match_operand:DI 0 "nonimmediate_operand" "")
14456 (plus:DI (match_dup 1) (const_int -1)))
14457 (clobber (match_scratch:CC 3 ""))
14458 (clobber (match_scratch:DI 4 ""))]
14459 "TARGET_64BIT && reload_completed
14460 && ! gpc_reg_operand (operands[0], DImode)"
14461 [(parallel [(set (match_dup 3)
14462 (compare:CC (plus:DI (match_dup 1)
14463 (const_int -1))
14464 (const_int 0)))
14465 (set (match_dup 4)
14466 (plus:DI (match_dup 1)
14467 (const_int -1)))])
14468 (set (match_dup 0)
14469 (match_dup 4))
14470 (set (pc) (if_then_else (match_dup 7)
14471 (match_dup 5)
14472 (match_dup 6)))]
14473 "
14474 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14475 operands[3], const0_rtx); }")
14476 \f
14477 (define_insn "trap"
14478 [(trap_if (const_int 1) (const_int 0))]
14479 ""
14480 "{t 31,0,0|trap}")
14482 (define_expand "conditional_trap"
14483 [(trap_if (match_operator 0 "trap_comparison_operator"
14484 [(match_dup 2) (match_dup 3)])
14485 (match_operand 1 "const_int_operand" ""))]
14486 ""
14487 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14488 operands[2] = rs6000_compare_op0;
14489 operands[3] = rs6000_compare_op1;")
14491 (define_insn ""
14492 [(trap_if (match_operator 0 "trap_comparison_operator"
14493 [(match_operand:SI 1 "register_operand" "r")
14494 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14495 (const_int 0))]
14496 ""
14497 "{t|tw}%V0%I2 %1,%2")
14499 (define_insn ""
14500 [(trap_if (match_operator 0 "trap_comparison_operator"
14501 [(match_operand:DI 1 "register_operand" "r")
14502 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14503 (const_int 0))]
14504 "TARGET_POWERPC64"
14505 "td%V0%I2 %1,%2")
14506 \f
14507 ;; Insns related to generating the function prologue and epilogue.
14509 (define_expand "prologue"
14510 [(use (const_int 0))]
14511 "TARGET_SCHED_PROLOG"
14512 "
14513 {
14514 rs6000_emit_prologue ();
14515 DONE;
14516 }")
14518 (define_insn "*movesi_from_cr_one"
14519 [(match_parallel 0 "mfcr_operation"
14520 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14521 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14522 (match_operand 3 "immediate_operand" "n")]
14523 UNSPEC_MOVESI_FROM_CR))])]
14524 "TARGET_MFCRF"
14525 "*
14526 {
14527 int mask = 0;
14528 int i;
14529 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14530 {
14531 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14532 operands[4] = GEN_INT (mask);
14533 output_asm_insn (\"mfcr %1,%4\", operands);
14534 }
14535 return \"\";
14536 }"
14537 [(set_attr "type" "mfcrf")])
14539 (define_insn "movesi_from_cr"
14540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14541 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14542 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14543 UNSPEC_MOVESI_FROM_CR))]
14544 ""
14545 "mfcr %0"
14546 [(set_attr "type" "mfcr")])
14548 (define_insn "*stmw"
14549 [(match_parallel 0 "stmw_operation"
14550 [(set (match_operand:SI 1 "memory_operand" "=m")
14551 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14552 "TARGET_MULTIPLE"
14553 "{stm|stmw} %2,%1")
14555 (define_insn "*save_fpregs_si"
14556 [(match_parallel 0 "any_parallel_operand"
14557 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14558 (use (match_operand:SI 2 "call_operand" "s"))
14559 (set (match_operand:DF 3 "memory_operand" "=m")
14560 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14561 "TARGET_32BIT"
14562 "bl %z2"
14563 [(set_attr "type" "branch")
14564 (set_attr "length" "4")])
14566 (define_insn "*save_fpregs_di"
14567 [(match_parallel 0 "any_parallel_operand"
14568 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14569 (use (match_operand:DI 2 "call_operand" "s"))
14570 (set (match_operand:DF 3 "memory_operand" "=m")
14571 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14572 "TARGET_64BIT"
14573 "bl %z2"
14574 [(set_attr "type" "branch")
14575 (set_attr "length" "4")])
14577 ; These are to explain that changes to the stack pointer should
14578 ; not be moved over stores to stack memory.
14579 (define_insn "stack_tie"
14580 [(set (match_operand:BLK 0 "memory_operand" "+m")
14581 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14582 ""
14583 ""
14584 [(set_attr "length" "0")])
14587 (define_expand "epilogue"
14588 [(use (const_int 0))]
14589 "TARGET_SCHED_PROLOG"
14590 "
14591 {
14592 rs6000_emit_epilogue (FALSE);
14593 DONE;
14594 }")
14596 ; On some processors, doing the mtcrf one CC register at a time is
14597 ; faster (like on the 604e). On others, doing them all at once is
14598 ; faster; for instance, on the 601 and 750.
14600 (define_expand "movsi_to_cr_one"
14601 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14602 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14603 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14604 ""
14605 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14607 (define_insn "*movsi_to_cr"
14608 [(match_parallel 0 "mtcrf_operation"
14609 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14610 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14611 (match_operand 3 "immediate_operand" "n")]
14612 UNSPEC_MOVESI_TO_CR))])]
14613 ""
14614 "*
14615 {
14616 int mask = 0;
14617 int i;
14618 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14619 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14620 operands[4] = GEN_INT (mask);
14621 return \"mtcrf %4,%2\";
14622 }"
14623 [(set_attr "type" "mtcr")])
14625 (define_insn "*mtcrfsi"
14626 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14627 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14628 (match_operand 2 "immediate_operand" "n")]
14629 UNSPEC_MOVESI_TO_CR))]
14630 "GET_CODE (operands[0]) == REG
14631 && CR_REGNO_P (REGNO (operands[0]))
14632 && GET_CODE (operands[2]) == CONST_INT
14633 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14634 "mtcrf %R0,%1"
14635 [(set_attr "type" "mtcr")])
14637 ; The load-multiple instructions have similar properties.
14638 ; Note that "load_multiple" is a name known to the machine-independent
14639 ; code that actually corresponds to the powerpc load-string.
14641 (define_insn "*lmw"
14642 [(match_parallel 0 "lmw_operation"
14643 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14644 (match_operand:SI 2 "memory_operand" "m"))])]
14645 "TARGET_MULTIPLE"
14646 "{lm|lmw} %1,%2")
14648 (define_insn "*return_internal_si"
14649 [(return)
14650 (use (match_operand:SI 0 "register_operand" "lc"))]
14651 "TARGET_32BIT"
14652 "b%T0"
14653 [(set_attr "type" "jmpreg")])
14655 (define_insn "*return_internal_di"
14656 [(return)
14657 (use (match_operand:DI 0 "register_operand" "lc"))]
14658 "TARGET_64BIT"
14659 "b%T0"
14660 [(set_attr "type" "jmpreg")])
14662 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14663 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14665 (define_insn "*return_and_restore_fpregs_si"
14666 [(match_parallel 0 "any_parallel_operand"
14667 [(return)
14668 (use (match_operand:SI 1 "register_operand" "l"))
14669 (use (match_operand:SI 2 "call_operand" "s"))
14670 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14671 (match_operand:DF 4 "memory_operand" "m"))])]
14672 "TARGET_32BIT"
14673 "b %z2")
14675 (define_insn "*return_and_restore_fpregs_di"
14676 [(match_parallel 0 "any_parallel_operand"
14677 [(return)
14678 (use (match_operand:DI 1 "register_operand" "l"))
14679 (use (match_operand:DI 2 "call_operand" "s"))
14680 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14681 (match_operand:DF 4 "memory_operand" "m"))])]
14682 "TARGET_64BIT"
14683 "b %z2")
14685 ; This is used in compiling the unwind routines.
14686 (define_expand "eh_return"
14687 [(use (match_operand 0 "general_operand" ""))]
14688 ""
14689 "
14690 {
14691 if (TARGET_32BIT)
14692 emit_insn (gen_eh_set_lr_si (operands[0]));
14693 else
14694 emit_insn (gen_eh_set_lr_di (operands[0]));
14695 DONE;
14696 }")
14698 ; We can't expand this before we know where the link register is stored.
14699 (define_insn "eh_set_lr_si"
14700 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14701 UNSPECV_EH_RR)
14702 (clobber (match_scratch:SI 1 "=&b"))]
14703 "TARGET_32BIT"
14704 "#")
14706 (define_insn "eh_set_lr_di"
14707 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14708 UNSPECV_EH_RR)
14709 (clobber (match_scratch:DI 1 "=&b"))]
14710 "TARGET_64BIT"
14711 "#")
14713 (define_split
14714 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14715 (clobber (match_scratch 1 ""))]
14716 "reload_completed"
14717 [(const_int 0)]
14718 "
14719 {
14720 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14721 DONE;
14722 }")
14724 (define_insn "prefetch"
14725 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14726 (match_operand:SI 1 "const_int_operand" "n")
14727 (match_operand:SI 2 "const_int_operand" "n"))]
14728 "TARGET_POWERPC"
14729 "*
14730 {
14731 if (GET_CODE (operands[0]) == REG)
14732 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14733 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14734 }"
14735 [(set_attr "type" "load")])
14737 (include "altivec.md")
14738 (include "spe.md")