1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
47 #include "target-def.h"
50 #define FRV_INLINE inline
53 /* Temporary register allocation support structure. */
54 typedef struct frv_tmp_reg_struct
56 HARD_REG_SET regs
; /* possible registers to allocate */
57 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
61 /* Register state information for VLIW re-packing phase. These values must fit
62 within an unsigned char. */
63 #define REGSTATE_DEAD 0x00 /* register is currently dead */
64 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
65 #define REGSTATE_LIVE 0x08 /* register is live */
66 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
67 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
68 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
69 #define REGSTATE_UNUSED 0x80 /* bit for hire */
70 #define REGSTATE_MASK 0xff /* mask for the bits to set */
72 /* conditional expression used */
73 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
75 /* the following is not sure in the reg_state bytes, so can have a larger value
77 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
79 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
87 /* Information required by frv_frame_access. */
90 /* This field is FRV_LOAD if registers are to be loaded from the stack and
91 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
92 the move is being done by the prologue code while FRV_LOAD implies it
93 is being done by the epilogue. */
96 /* The base register to use when accessing the stack. This may be the
97 frame pointer, stack pointer, or a temporary. The choice of register
98 depends on which part of the frame is being accessed and how big the
102 /* The offset of BASE from the bottom of the current frame, in bytes. */
104 } frv_frame_accessor_t
;
106 /* Define the information needed to generate branch and scc insns. This is
107 stored from the compare operation. */
111 /* Conditional execution support gathered together in one structure */
114 /* Linked list of insns to add if the conditional execution conversion was
115 successful. Each link points to an EXPR_LIST which points to the pattern
116 of the insn to add, and the insn to be inserted before. */
117 rtx added_insns_list
;
119 /* Identify which registers are safe to allocate for if conversions to
120 conditional execution. We keep the last allocated register in the
121 register classes between COND_EXEC statements. This will mean we allocate
122 different registers for each different COND_EXEC group if we can. This
123 might allow the scheduler to intermix two different COND_EXEC sections. */
124 frv_tmp_reg_t tmp_reg
;
126 /* For nested IFs, identify which CC registers are used outside of setting
127 via a compare isnsn, and using via a check insn. This will allow us to
128 know if we can rewrite the register to use a different register that will
129 be paired with the CR register controlling the nested IF-THEN blocks. */
130 HARD_REG_SET nested_cc_ok_rewrite
;
132 /* Temporary registers allocated to hold constants during conditional
134 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
136 /* Current number of temp registers available. */
137 int cur_scratch_regs
;
139 /* Number of nested conditional execution blocks */
140 int num_nested_cond_exec
;
142 /* Map of insns that set up constants in scratch registers. */
143 bitmap scratch_insns_bitmap
;
145 /* Conditional execution test register (CC0..CC7) */
148 /* Conditional execution compare register that is paired with cr_reg, so that
149 nested compares can be done. The csubcc and caddcc instructions don't
150 have enough bits to specify both a CC register to be set and a CR register
151 to do the test on, so the same bit number is used for both. Needless to
152 say, this is rather inconvient for GCC. */
155 /* Extra CR registers used for &&, ||. */
159 /* Previous CR used in nested if, to make sure we are dealing with the same
160 nested if as the previous statement. */
161 rtx last_nested_if_cr
;
165 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
167 /* Map register number to smallest register class. */
168 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
170 /* Map class letter into register class */
171 enum reg_class reg_class_from_letter
[256];
173 /* Cached value of frv_stack_info */
174 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
176 /* -mbranch-cost= support */
177 const char *frv_branch_cost_string
;
178 int frv_branch_cost_int
= DEFAULT_BRANCH_COST
;
181 const char *frv_cpu_string
; /* -mcpu= option */
182 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
184 /* -mcond-exec-insns= support */
185 const char *frv_condexec_insns_str
; /* -mcond-exec-insns= option */
186 int frv_condexec_insns
= DEFAULT_CONDEXEC_INSNS
; /* value of -mcond-exec-insns*/
188 /* -mcond-exec-temps= support */
189 const char *frv_condexec_temps_str
; /* -mcond-exec-temps= option */
190 int frv_condexec_temps
= DEFAULT_CONDEXEC_TEMPS
; /* value of -mcond-exec-temps*/
192 /* -msched-lookahead=n */
193 const char *frv_sched_lookahead_str
; /* -msched-lookahead=n */
194 int frv_sched_lookahead
= 4; /* -msched-lookahead=n */
196 /* Forward references */
197 static int frv_default_flags_for_cpu
PARAMS ((void));
198 static int frv_string_begins_with
PARAMS ((tree
, const char *));
199 static FRV_INLINE
int symbol_ref_small_data_p
PARAMS ((rtx
));
200 static FRV_INLINE
int const_small_data_p
PARAMS ((rtx
));
201 static FRV_INLINE
int plus_small_data_p
PARAMS ((rtx
, rtx
));
202 static void frv_print_operand_memory_reference_reg
203 PARAMS ((FILE *, rtx
));
204 static void frv_print_operand_memory_reference
PARAMS ((FILE *, rtx
, int));
205 static int frv_print_operand_jump_hint
PARAMS ((rtx
));
206 static FRV_INLINE
int frv_regno_ok_for_base_p
PARAMS ((int, int));
207 static rtx single_set_pattern
PARAMS ((rtx
));
208 static int frv_function_contains_far_jump
PARAMS ((void));
209 static rtx frv_alloc_temp_reg
PARAMS ((frv_tmp_reg_t
*,
213 static rtx frv_frame_offset_rtx
PARAMS ((int));
214 static rtx frv_frame_mem
PARAMS ((enum machine_mode
,
216 static rtx frv_dwarf_store
PARAMS ((rtx
, int));
217 static void frv_frame_insn
PARAMS ((rtx
, rtx
));
218 static void frv_frame_access
PARAMS ((frv_frame_accessor_t
*,
220 static void frv_frame_access_multi
PARAMS ((frv_frame_accessor_t
*,
221 frv_stack_t
*, int));
222 static void frv_frame_access_standard_regs
PARAMS ((enum frv_stack_op
,
224 static struct machine_function
*frv_init_machine_status
PARAMS ((void));
225 static int frv_legitimate_memory_operand
PARAMS ((rtx
,
228 static rtx frv_int_to_acc
PARAMS ((enum insn_code
,
230 static enum machine_mode frv_matching_accg_mode
PARAMS ((enum machine_mode
));
231 static rtx frv_read_argument
PARAMS ((tree
*));
232 static int frv_check_constant_argument
PARAMS ((enum insn_code
,
234 static rtx frv_legitimize_target
PARAMS ((enum insn_code
, rtx
));
235 static rtx frv_legitimize_argument
PARAMS ((enum insn_code
,
237 static rtx frv_expand_set_builtin
PARAMS ((enum insn_code
,
239 static rtx frv_expand_unop_builtin
PARAMS ((enum insn_code
,
241 static rtx frv_expand_binop_builtin
PARAMS ((enum insn_code
,
243 static rtx frv_expand_cut_builtin
PARAMS ((enum insn_code
,
245 static rtx frv_expand_binopimm_builtin
PARAMS ((enum insn_code
,
247 static rtx frv_expand_voidbinop_builtin
PARAMS ((enum insn_code
,
249 static rtx frv_expand_voidtriop_builtin
PARAMS ((enum insn_code
,
251 static rtx frv_expand_voidaccop_builtin
PARAMS ((enum insn_code
,
253 static rtx frv_expand_mclracc_builtin
PARAMS ((tree
));
254 static rtx frv_expand_mrdacc_builtin
PARAMS ((enum insn_code
,
256 static rtx frv_expand_mwtacc_builtin
PARAMS ((enum insn_code
,
258 static rtx frv_expand_noargs_builtin
PARAMS ((enum insn_code
));
259 static rtx frv_emit_comparison
PARAMS ((enum rtx_code
, rtx
,
261 static int frv_clear_registers_used
PARAMS ((rtx
*, void *));
262 static void frv_ifcvt_add_insn
PARAMS ((rtx
, rtx
, int));
263 static rtx frv_ifcvt_rewrite_mem
PARAMS ((rtx
,
266 static rtx frv_ifcvt_load_value
PARAMS ((rtx
, rtx
));
267 static void frv_registers_update
PARAMS ((rtx
, unsigned char [],
268 int [], int *, int));
269 static int frv_registers_used_p
PARAMS ((rtx
, unsigned char [],
271 static int frv_registers_set_p
PARAMS ((rtx
, unsigned char [],
273 static void frv_pack_insns
PARAMS ((void));
274 static void frv_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
275 static void frv_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
276 static bool frv_assemble_integer
PARAMS ((rtx
, unsigned, int));
277 static const char * frv_strip_name_encoding
PARAMS ((const char *));
278 static void frv_encode_section_info
PARAMS ((tree
, int));
279 static void frv_init_builtins
PARAMS ((void));
280 static rtx frv_expand_builtin
PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
281 static bool frv_in_small_data_p
PARAMS ((tree
));
283 /* Initialize the GCC target structure. */
284 #undef TARGET_ASM_FUNCTION_PROLOGUE
285 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
286 #undef TARGET_ASM_FUNCTION_EPILOGUE
287 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
288 #undef TARGET_ASM_INTEGER
289 #define TARGET_ASM_INTEGER frv_assemble_integer
290 #undef TARGET_STRIP_NAME_ENCODING
291 #define TARGET_STRIP_NAME_ENCODING frv_strip_name_encoding
292 #undef TARGET_ENCODE_SECTION_INFO
293 #define TARGET_ENCODE_SECTION_INFO frv_encode_section_info
294 #undef TARGET_INIT_BUILTINS
295 #define TARGET_INIT_BUILTINS frv_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
298 #undef TARGET_IN_SMALL_DATA_P
299 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
301 struct gcc_target targetm
= TARGET_INITIALIZER
;
303 /* Given a SYMBOL_REF, return true if it points to small data. */
305 static FRV_INLINE
int
306 symbol_ref_small_data_p (x
)
309 return SDATA_NAME_P (XSTR (x
, 0));
312 /* Given a CONST, return true if the symbol_ref points to small data. */
314 static FRV_INLINE
int
315 const_small_data_p (x
)
320 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
323 x0
= XEXP (XEXP (x
, 0), 0);
324 if (GET_CODE (x0
) != SYMBOL_REF
|| !SDATA_NAME_P (XSTR (x0
, 0)))
327 x1
= XEXP (XEXP (x
, 0), 1);
328 if (GET_CODE (x1
) != CONST_INT
329 || !IN_RANGE_P (INTVAL (x1
), -2048, 2047))
335 /* Given a PLUS, return true if this is a small data reference. */
337 static FRV_INLINE
int
338 plus_small_data_p (op0
, op1
)
342 if (GET_MODE (op0
) == SImode
343 && GET_CODE (op0
) == REG
344 && REGNO (op0
) == SDA_BASE_REG
)
346 if (GET_CODE (op1
) == SYMBOL_REF
)
347 return symbol_ref_small_data_p (op1
);
349 if (GET_CODE (op1
) == CONST
)
350 return const_small_data_p (op1
);
358 frv_default_flags_for_cpu ()
360 switch (frv_cpu_type
)
362 case FRV_CPU_GENERIC
:
363 return MASK_DEFAULT_FRV
;
367 return MASK_DEFAULT_FR500
;
370 return MASK_DEFAULT_FR400
;
374 return MASK_DEFAULT_SIMPLE
;
379 /* Sometimes certain combinations of command options do not make
380 sense on a particular target machine. You can define a macro
381 `OVERRIDE_OPTIONS' to take account of this. This macro, if
382 defined, is executed once just after all the command options have
385 Don't use this macro to turn on various extra optimizations for
386 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
389 frv_override_options ()
393 /* Set the cpu type */
396 if (strcmp (frv_cpu_string
, "simple") == 0)
397 frv_cpu_type
= FRV_CPU_SIMPLE
;
399 else if (strcmp (frv_cpu_string
, "tomcat") == 0)
400 frv_cpu_type
= FRV_CPU_TOMCAT
;
402 else if (strncmp (frv_cpu_string
, "fr", sizeof ("fr")-1) != 0)
403 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
407 const char *p
= frv_cpu_string
+ sizeof ("fr") - 1;
408 if (strcmp (p
, "500") == 0)
409 frv_cpu_type
= FRV_CPU_FR500
;
411 else if (strcmp (p
, "400") == 0)
412 frv_cpu_type
= FRV_CPU_FR400
;
414 else if (strcmp (p
, "300") == 0)
415 frv_cpu_type
= FRV_CPU_FR300
;
417 else if (strcmp (p
, "v") == 0)
418 frv_cpu_type
= FRV_CPU_GENERIC
;
421 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
425 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
427 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
428 linker about linking pic and non-pic code. */
431 if (!flag_pic
) /* -fPIC */
434 if (! g_switch_set
) /* -G0 */
441 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
443 if (write_symbols
== DWARF_DEBUG
&& flag_pic
)
444 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
446 /* Change the branch cost value */
447 if (frv_branch_cost_string
)
448 frv_branch_cost_int
= atoi (frv_branch_cost_string
);
450 /* Change the # of insns to be converted to conditional execution */
451 if (frv_condexec_insns_str
)
452 frv_condexec_insns
= atoi (frv_condexec_insns_str
);
454 /* Change # of temporary registers used to hold integer constants */
455 if (frv_condexec_temps_str
)
456 frv_condexec_temps
= atoi (frv_condexec_temps_str
);
458 /* Change scheduling look ahead. */
459 if (frv_sched_lookahead_str
)
460 frv_sched_lookahead
= atoi (frv_sched_lookahead_str
);
462 /* A C expression whose value is a register class containing hard
463 register REGNO. In general there is more than one such class;
464 choose a class which is "minimal", meaning that no smaller class
465 also contains the register. */
467 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
469 enum reg_class
class;
473 int gpr_reg
= regno
- GPR_FIRST
;
474 if ((gpr_reg
& 3) == 0)
477 else if ((gpr_reg
& 1) == 0)
484 else if (FPR_P (regno
))
486 int fpr_reg
= regno
- GPR_FIRST
;
487 if ((fpr_reg
& 3) == 0)
488 class = QUAD_FPR_REGS
;
490 else if ((fpr_reg
& 1) == 0)
497 else if (regno
== LR_REGNO
)
500 else if (regno
== LCR_REGNO
)
503 else if (ICC_P (regno
))
506 else if (FCC_P (regno
))
509 else if (ICR_P (regno
))
512 else if (FCR_P (regno
))
515 else if (ACC_P (regno
))
517 int r
= regno
- ACC_FIRST
;
519 class = QUAD_ACC_REGS
;
520 else if ((r
& 1) == 0)
521 class = EVEN_ACC_REGS
;
526 else if (ACCG_P (regno
))
532 regno_reg_class
[regno
] = class;
535 /* Check for small data option */
537 g_switch_value
= SDATA_DEFAULT_SIZE
;
539 /* A C expression which defines the machine-dependent operand
540 constraint letters for register classes. If CHAR is such a
541 letter, the value should be the register class corresponding to
542 it. Otherwise, the value should be `NO_REGS'. The register
543 letter `r', corresponding to class `GENERAL_REGS', will not be
544 passed to this macro; you do not need to handle it.
546 The following letters are unavailable, due to being used as
551 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
552 'Q', 'R', 'S', 'T', 'U'
554 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
556 for (i
= 0; i
< 256; i
++)
557 reg_class_from_letter
[i
] = NO_REGS
;
559 reg_class_from_letter
['a'] = ACC_REGS
;
560 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
561 reg_class_from_letter
['c'] = CC_REGS
;
562 reg_class_from_letter
['d'] = GPR_REGS
;
563 reg_class_from_letter
['e'] = EVEN_REGS
;
564 reg_class_from_letter
['f'] = FPR_REGS
;
565 reg_class_from_letter
['h'] = FEVEN_REGS
;
566 reg_class_from_letter
['l'] = LR_REG
;
567 reg_class_from_letter
['q'] = QUAD_REGS
;
568 reg_class_from_letter
['t'] = ICC_REGS
;
569 reg_class_from_letter
['u'] = FCC_REGS
;
570 reg_class_from_letter
['v'] = ICR_REGS
;
571 reg_class_from_letter
['w'] = FCR_REGS
;
572 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
573 reg_class_from_letter
['y'] = LCR_REG
;
574 reg_class_from_letter
['z'] = SPR_REGS
;
575 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
576 reg_class_from_letter
['B'] = ACCG_REGS
;
577 reg_class_from_letter
['C'] = CR_REGS
;
579 /* There is no single unaligned SI op for PIC code. Sometimes we
580 need to use ".4byte" and sometimes we need to use ".picptr".
581 See frv_assemble_integer for details. */
583 targetm
.asm_out
.unaligned_op
.si
= 0;
585 init_machine_status
= frv_init_machine_status
;
589 /* Some machines may desire to change what optimizations are performed for
590 various optimization levels. This macro, if defined, is executed once just
591 after the optimization level is determined and before the remainder of the
592 command options have been parsed. Values set in this macro are used as the
593 default values for the other command line options.
595 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
596 `-O' is specified, and 0 if neither is specified.
598 SIZE is nonzero if `-Os' is specified, 0 otherwise.
600 You should not use this macro to change options that are not
601 machine-specific. These should uniformly selected by the same optimization
602 level on all supported machines. Use this macro to enable machbine-specific
605 *Do not examine `write_symbols' in this macro!* The debugging options are
606 *not supposed to alter the generated code. */
608 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
609 scheduling pass at the current time. */
611 frv_optimization_options (level
, size
)
613 int size ATTRIBUTE_UNUSED
;
617 #ifdef DISABLE_SCHED2
618 flag_schedule_insns_after_reload
= 0;
627 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
630 frv_string_begins_with (name
, prefix
)
634 int prefix_len
= strlen (prefix
);
636 /* Remember: NAME's length includes the null terminator. */
637 return (TREE_STRING_LENGTH (name
) > prefix_len
638 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
641 /* Encode section information of DECL, which is either a VAR_DECL,
642 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
644 For the FRV we want to record:
646 - whether the object lives in .sdata/.sbss.
647 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
652 frv_encode_section_info (decl
, first
)
658 if (TREE_CODE (decl
) == VAR_DECL
)
660 int size
= int_size_in_bytes (TREE_TYPE (decl
));
661 tree section_name
= DECL_SECTION_NAME (decl
);
664 /* Don't apply the -G flag to internal compiler structures. We
665 should leave such structures in the main data section, partly
666 for efficiency and partly because the size of some of them
667 (such as C++ typeinfos) is not known until later. */
668 if (!DECL_ARTIFICIAL (decl
) && size
> 0 && size
<= g_switch_value
)
671 /* If we already know which section the decl should be in, see if
672 it's a small data section. */
675 if (TREE_CODE (section_name
) == STRING_CST
)
677 if (frv_string_begins_with (section_name
, ".sdata"))
679 if (frv_string_begins_with (section_name
, ".sbss"))
688 rtx sym_ref
= XEXP (DECL_RTL (decl
), 0);
689 char * str
= xmalloc (2 + strlen (XSTR (sym_ref
, 0)));
691 str
[0] = SDATA_FLAG_CHAR
;
692 strcpy (&str
[1], XSTR (sym_ref
, 0));
693 XSTR (sym_ref
, 0) = str
;
699 /* Zero or more C statements that may conditionally modify two variables
700 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
701 been initialized from the two preceding macros.
703 This is necessary in case the fixed or call-clobbered registers depend on
706 You need not define this macro if it has no work to do.
708 If the usage of an entire class of registers depends on the target flags,
709 you may indicate this to GCC by using this macro to modify `fixed_regs' and
710 `call_used_regs' to 1 for each of the registers in the classes which should
711 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
712 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
714 (However, if this class is not included in `GENERAL_REGS' and all of the
715 insn patterns whose constraints permit this class are controlled by target
716 switches, then GCC will automatically avoid using these registers when the
717 target switches are opposed to them.) */
720 frv_conditional_register_usage ()
724 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
725 fixed_regs
[i
] = call_used_regs
[i
] = 1;
727 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
728 fixed_regs
[i
] = call_used_regs
[i
] = 1;
730 for (i
= ACC_FIRST
+ NUM_ACCS
; i
<= ACC_LAST
; i
++)
731 fixed_regs
[i
] = call_used_regs
[i
] = 1;
733 for (i
= ACCG_FIRST
+ NUM_ACCS
; i
<= ACCG_LAST
; i
++)
734 fixed_regs
[i
] = call_used_regs
[i
] = 1;
736 /* Reserve the registers used for conditional execution. At present, we need
737 1 ICC and 1 ICR register. */
738 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
739 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
743 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
744 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
745 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
746 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
750 /* If -fpic, SDA_BASE_REG is the PIC register. */
751 if (g_switch_value
== 0 && !flag_pic
)
752 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
755 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
761 * Compute the stack frame layout
764 * +---------------+-----------------------+-----------------------+
765 * |Register |type |caller-save/callee-save|
766 * +---------------+-----------------------+-----------------------+
767 * |GR0 |Zero register | - |
768 * |GR1 |Stack pointer(SP) | - |
769 * |GR2 |Frame pointer(FP) | - |
770 * |GR3 |Hidden parameter | caller save |
771 * |GR4-GR7 | - | caller save |
772 * |GR8-GR13 |Argument register | caller save |
773 * |GR14-GR15 | - | caller save |
774 * |GR16-GR31 | - | callee save |
775 * |GR32-GR47 | - | caller save |
776 * |GR48-GR63 | - | callee save |
777 * |FR0-FR15 | - | caller save |
778 * |FR16-FR31 | - | callee save |
779 * |FR32-FR47 | - | caller save |
780 * |FR48-FR63 | - | callee save |
781 * +---------------+-----------------------+-----------------------+
785 * SP-> |-----------------------------------|
787 * |-----------------------------------|
788 * | Register save area |
789 * |-----------------------------------|
790 * | Local variable save area |
791 * FP-> |-----------------------------------|
793 * |-----------------------------------|
794 * | Hidden parameter save area |
795 * |-----------------------------------|
796 * | Return address(LR) storage area |
797 * |-----------------------------------|
798 * | Padding for alignment |
799 * |-----------------------------------|
800 * | Register argument area |
801 * OLD SP-> |-----------------------------------|
803 * |-----------------------------------|
806 * Argument area/Parameter area:
808 * When a function is called, this area is used for argument transfer. When
809 * the argument is set up by the caller function, this area is referred to as
810 * the argument area. When the argument is referenced by the callee function,
811 * this area is referred to as the parameter area. The area is allocated when
812 * all arguments cannot be placed on the argument register at the time of
815 * Register save area:
817 * This is a register save area that must be guaranteed for the caller
818 * function. This area is not secured when the register save operation is not
821 * Local variable save area:
823 * This is the area for local variables and temporary variables.
827 * This area stores the FP value of the caller function.
829 * Hidden parameter save area:
831 * This area stores the start address of the return value storage
832 * area for a struct/union return function.
833 * When a struct/union is used as the return value, the caller
834 * function stores the return value storage area start address in
835 * register GR3 and passes it to the caller function.
836 * The callee function interprets the address stored in the GR3
837 * as the return value storage area start address.
838 * When register GR3 needs to be saved into memory, the callee
839 * function saves it in the hidden parameter save area. This
840 * area is not secured when the save operation is not needed.
842 * Return address(LR) storage area:
844 * This area saves the LR. The LR stores the address of a return to the caller
845 * function for the purpose of function calling.
847 * Argument register area:
849 * This area saves the argument register. This area is not secured when the
850 * save operation is not needed.
854 * Arguments, the count of which equals the count of argument registers (6
855 * words), are positioned in registers GR8 to GR13 and delivered to the callee
856 * function. When a struct/union return function is called, the return value
857 * area address is stored in register GR3. Arguments not placed in the
858 * argument registers will be stored in the stack argument area for transfer
859 * purposes. When an 8-byte type argument is to be delivered using registers,
860 * it is divided into two and placed in two registers for transfer. When
861 * argument registers must be saved to memory, the callee function secures an
862 * argument register save area in the stack. In this case, a continuous
863 * argument register save area must be established in the parameter area. The
864 * argument register save area must be allocated as needed to cover the size of
865 * the argument register to be saved. If the function has a variable count of
866 * arguments, it saves all argument registers in the argument register save
869 * Argument Extension Format:
871 * When an argument is to be stored in the stack, its type is converted to an
872 * extended type in accordance with the individual argument type. The argument
873 * is freed by the caller function after the return from the callee function is
876 * +-----------------------+---------------+------------------------+
877 * | Argument Type |Extended Type |Stack Storage Size(byte)|
878 * +-----------------------+---------------+------------------------+
880 * |signed char |int | 4 |
881 * |unsigned char |int | 4 |
882 * |[signed] short int |int | 4 |
883 * |unsigned short int |int | 4 |
884 * |[signed] int |No extension | 4 |
885 * |unsigned int |No extension | 4 |
886 * |[signed] long int |No extension | 4 |
887 * |unsigned long int |No extension | 4 |
888 * |[signed] long long int |No extension | 8 |
889 * |unsigned long long int |No extension | 8 |
890 * |float |double | 8 |
891 * |double |No extension | 8 |
892 * |long double |No extension | 8 |
893 * |pointer |No extension | 4 |
894 * |struct/union |- | 4 (*1) |
895 * +-----------------------+---------------+------------------------+
897 * When a struct/union is to be delivered as an argument, the caller copies it
898 * to the local variable area and delivers the address of that area.
902 * +-------------------------------+----------------------+
903 * |Return Value Type |Return Value Interface|
904 * +-------------------------------+----------------------+
906 * |[signed|unsigned] char |GR8 |
907 * |[signed|unsigned] short int |GR8 |
908 * |[signed|unsigned] int |GR8 |
909 * |[signed|unsigned] long int |GR8 |
911 * |[signed|unsigned] long long int|GR8 & GR9 |
913 * |double |GR8 & GR9 |
914 * |long double |GR8 & GR9 |
915 * |struct/union |(*1) |
916 * +-------------------------------+----------------------+
918 * When a struct/union is used as the return value, the caller function stores
919 * the start address of the return value storage area into GR3 and then passes
920 * it to the callee function. The callee function interprets GR3 as the start
921 * address of the return value storage area. When this address needs to be
922 * saved in memory, the callee function secures the hidden parameter save area
923 * and saves the address in that area.
929 static frv_stack_t info
, zero_info
;
930 frv_stack_t
*info_ptr
= &info
;
931 tree fndecl
= current_function_decl
;
939 /* If we've already calculated the values and reload is complete, just return now */
941 return frv_stack_cache
;
943 /* Zero all fields */
946 /* Set up the register range information */
947 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
948 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
949 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
950 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
952 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
953 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
954 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
955 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
957 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
958 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
959 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
960 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
962 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
963 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
964 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
965 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
967 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
968 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
969 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
971 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
972 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
973 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
974 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
975 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
977 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
978 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= STRUCT_VALUE_REGNUM
;
979 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= STRUCT_VALUE_REGNUM
;
980 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
982 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
983 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
984 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
985 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
987 /* Determine if this is a stdarg function. If so, allocate space to store
994 /* Find the last argument, and see if it is __builtin_va_alist. */
995 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
997 next_arg
= TREE_CHAIN (cur_arg
);
998 if (next_arg
== (tree
)0)
1000 if (DECL_NAME (cur_arg
)
1001 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1009 /* Iterate over all of the register ranges */
1010 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1012 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1013 int first
= reg_ptr
->first
;
1014 int last
= reg_ptr
->last
;
1016 int size_2words
= 0;
1019 /* Calculate which registers need to be saved & save area size */
1023 for (regno
= first
; regno
<= last
; regno
++)
1025 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
1026 || (current_function_calls_eh_return
1027 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1028 || (flag_pic
&& cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1030 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1031 size_1word
+= UNITS_PER_WORD
;
1036 /* Calculate whether we need to create a frame after everything else
1037 has been processed. */
1042 if (regs_ever_live
[LR_REGNO
]
1044 || frame_pointer_needed
1045 || (flag_pic
&& cfun
->uses_pic_offset_table
))
1047 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1048 size_1word
+= UNITS_PER_WORD
;
1052 case STACK_REGS_STDARG
:
1055 /* If this is a stdarg function with an non varardic argument split
1056 between registers and the stack, adjust the saved registers
1058 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
1061 for (regno
= first
; regno
<= last
; regno
++)
1063 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1064 size_1word
+= UNITS_PER_WORD
;
1067 info_ptr
->stdarg_size
= size_1word
;
1071 case STACK_REGS_STRUCT
:
1072 if (cfun
->returns_struct
)
1074 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1075 size_1word
+= UNITS_PER_WORD
;
1083 /* If this is a field, it only takes one word */
1084 if (reg_ptr
->field_p
)
1085 size_1word
= UNITS_PER_WORD
;
1087 /* Determine which register pairs can be saved together */
1088 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1090 for (regno
= first
; regno
< last
; regno
+= 2)
1092 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1094 size_2words
+= 2 * UNITS_PER_WORD
;
1095 size_1word
-= 2 * UNITS_PER_WORD
;
1096 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1097 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1102 reg_ptr
->size_1word
= size_1word
;
1103 reg_ptr
->size_2words
= size_2words
;
1105 if (! reg_ptr
->special_p
)
1107 info_ptr
->regs_size_1word
+= size_1word
;
1108 info_ptr
->regs_size_2words
+= size_2words
;
1113 /* Set up the sizes of each each field in the frame body, making the sizes
1114 of each be divisible by the size of a dword if dword operations might
1115 be used, or the size of a word otherwise. */
1116 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1118 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1119 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1120 + info_ptr
->regs_size_1word
,
1122 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1124 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1126 /* Work out the size of the frame, excluding the header. Both the frame
1127 body and register parameter area will be dword-aligned. */
1128 info_ptr
->total_size
1129 = (ADDR_ALIGN (info_ptr
->parameter_size
1130 + info_ptr
->regs_size
1131 + info_ptr
->vars_size
,
1133 + ADDR_ALIGN (info_ptr
->pretend_size
1134 + info_ptr
->stdarg_size
,
1135 2 * UNITS_PER_WORD
));
1137 /* See if we need to create a frame at all, if so add header area. */
1138 if (info_ptr
->total_size
> 0
1139 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1140 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1142 offset
= info_ptr
->parameter_size
;
1143 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1144 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1146 /* Calculate the offsets to save normal register pairs */
1147 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1149 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1150 if (! reg_ptr
->special_p
)
1152 int first
= reg_ptr
->first
;
1153 int last
= reg_ptr
->last
;
1156 for (regno
= first
; regno
<= last
; regno
++)
1157 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1158 && regno
!= FRAME_POINTER_REGNUM
1159 && (regno
< FIRST_ARG_REGNUM
1160 || regno
> LAST_ARG_REGNUM
))
1162 info_ptr
->reg_offset
[regno
] = offset
;
1163 offset
+= 2 * UNITS_PER_WORD
;
1168 /* Calculate the offsets to save normal single registers */
1169 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1171 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1172 if (! reg_ptr
->special_p
)
1174 int first
= reg_ptr
->first
;
1175 int last
= reg_ptr
->last
;
1178 for (regno
= first
; regno
<= last
; regno
++)
1179 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1180 && regno
!= FRAME_POINTER_REGNUM
1181 && (regno
< FIRST_ARG_REGNUM
1182 || regno
> LAST_ARG_REGNUM
))
1184 info_ptr
->reg_offset
[regno
] = offset
;
1185 offset
+= UNITS_PER_WORD
;
1190 /* Calculate the offset to save the local variables at. */
1191 offset
= ADDR_ALIGN (offset
, alignment
);
1192 if (info_ptr
->vars_size
)
1194 info_ptr
->vars_offset
= offset
;
1195 offset
+= info_ptr
->vars_size
;
1198 /* Align header to a dword-boundary. */
1199 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1201 /* Calculate the offsets in the fixed frame. */
1202 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1203 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1204 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1206 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1207 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1208 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1210 if (cfun
->returns_struct
)
1212 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1213 info_ptr
->reg_offset
[STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1214 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1217 /* Calculate the offsets to store the arguments passed in registers
1218 for stdarg functions. The register pairs are first and the single
1219 register if any is last. The register save area starts on a
1221 if (info_ptr
->stdarg_size
)
1223 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1224 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1227 /* Skip the header. */
1228 offset
+= 4 * UNITS_PER_WORD
;
1229 for (regno
= first
; regno
<= last
; regno
++)
1231 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1233 info_ptr
->reg_offset
[regno
] = offset
;
1234 offset
+= 2 * UNITS_PER_WORD
;
1236 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1238 info_ptr
->reg_offset
[regno
] = offset
;
1239 offset
+= UNITS_PER_WORD
;
1245 if (reload_completed
)
1246 frv_stack_cache
= info_ptr
;
1252 /* Print the information about the frv stack offsets, etc. when debugging. */
1255 frv_debug_stack (info
)
1261 info
= frv_stack_info ();
1263 fprintf (stderr
, "\nStack information for function %s:\n",
1264 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1265 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1268 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1269 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1270 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1271 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1272 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1274 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1275 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1276 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1277 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1279 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1281 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1282 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1284 int first
= regs
->first
;
1285 int last
= regs
->last
;
1288 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1289 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1290 regs
->size_1word
, regs
->size_2words
);
1292 for (regno
= first
; regno
<= last
; regno
++)
1294 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1295 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1296 info
->reg_offset
[regno
]);
1298 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1299 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1300 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1303 fputc ('\n', stderr
);
1313 /* The following variable value is TRUE if the next output insn should
1314 finish cpu cycle. In order words the insn will have packing bit
1315 (which means absence of asm code suffix `.p' on assembler. */
1317 static int frv_insn_packing_flag
;
1319 /* True if the current function contains a far jump. */
1322 frv_function_contains_far_jump ()
1324 rtx insn
= get_insns ();
1326 && !(GET_CODE (insn
) == JUMP_INSN
1327 /* Ignore tablejump patterns. */
1328 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1329 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1330 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1331 insn
= NEXT_INSN (insn
);
1332 return (insn
!= NULL
);
1335 /* For the FRV, this function makes sure that a function with far jumps
1336 will return correctly. It also does the VLIW packing. */
1339 frv_function_prologue (file
, size
)
1341 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1343 /* If no frame was created, check whether the function uses a call
1344 instruction to implement a far jump. If so, save the link in gr3 and
1345 replace all returns to LR with returns to GR3. GR3 is used because it
1346 is call-clobbered, because is not available to the register allocator,
1347 and because all functions that take a hidden argument pointer will have
1349 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1353 /* Just to check that the above comment is true. */
1354 if (regs_ever_live
[GPR_FIRST
+ 3])
1357 /* Generate the instruction that saves the link register. */
1358 fprintf (file
, "\tmovsg lr,gr3\n");
1360 /* Replace the LR with GR3 in *return_internal patterns. The insn
1361 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1362 simply emit a different assembly directive because bralr and jmpl
1363 execute in different units. */
1364 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1365 if (GET_CODE (insn
) == JUMP_INSN
)
1367 rtx pattern
= PATTERN (insn
);
1368 if (GET_CODE (pattern
) == PARALLEL
1369 && XVECLEN (pattern
, 0) >= 2
1370 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1371 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1373 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1374 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1375 REGNO (address
) = GPR_FIRST
+ 3;
1381 frv_insn_packing_flag
= TRUE
;
1385 /* Return the next available temporary register in a given class. */
1388 frv_alloc_temp_reg (info
, class, mode
, mark_as_used
, no_abort
)
1389 frv_tmp_reg_t
*info
; /* which registers are available */
1390 enum reg_class
class; /* register class desired */
1391 enum machine_mode mode
; /* mode to allocate register with */
1392 int mark_as_used
; /* register not available after allocation */
1393 int no_abort
; /* return NULL instead of aborting */
1395 int regno
= info
->next_reg
[ (int)class ];
1396 int orig_regno
= regno
;
1397 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1402 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1403 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1406 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1408 if (regno
== orig_regno
)
1417 nr
= HARD_REGNO_NREGS (regno
, mode
);
1418 info
->next_reg
[ (int)class ] = regno
+ nr
;
1421 for (i
= 0; i
< nr
; i
++)
1422 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1424 return gen_rtx_REG (mode
, regno
);
1428 /* Return an rtx with the value OFFSET, which will either be a register or a
1429 signed 12-bit integer. It can be used as the second operand in an "add"
1430 instruction, or as the index in a load or store.
1432 The function returns a constant rtx if OFFSET is small enough, otherwise
1433 it loads the constant into register OFFSET_REGNO and returns that. */
1435 frv_frame_offset_rtx (offset
)
1438 rtx offset_rtx
= GEN_INT (offset
);
1439 if (IN_RANGE_P (offset
, -2048, 2047))
1443 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1444 if (IN_RANGE_P (offset
, -32768, 32767))
1445 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1448 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1449 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1455 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1456 prologue and epilogue uses such expressions to access the stack. */
1458 frv_frame_mem (mode
, base
, offset
)
1459 enum machine_mode mode
;
1463 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1465 frv_frame_offset_rtx (offset
)));
1468 /* Generate a frame-related expression:
1470 (set REG (mem (plus (sp) (const_int OFFSET)))).
1472 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1473 instructions. Marking the expressions as frame-related is superfluous if
1474 the note contains just a single set. But if the note contains a PARALLEL
1475 or SEQUENCE that has several sets, each set must be individually marked
1476 as frame-related. */
1478 frv_dwarf_store (reg
, offset
)
1482 rtx set
= gen_rtx_SET (VOIDmode
,
1483 gen_rtx_MEM (GET_MODE (reg
),
1484 plus_constant (stack_pointer_rtx
,
1487 RTX_FRAME_RELATED_P (set
) = 1;
1491 /* Emit a frame-related instruction whose pattern is PATTERN. The
1492 instruction is the last in a sequence that cumulatively performs the
1493 operation described by DWARF_PATTERN. The instruction is marked as
1494 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1497 frv_frame_insn (pattern
, dwarf_pattern
)
1501 rtx insn
= emit_insn (pattern
);
1502 RTX_FRAME_RELATED_P (insn
) = 1;
1503 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1508 /* Emit instructions that transfer REG to or from the memory location (sp +
1509 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1510 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1511 function to store registers and only the epilogue uses it to load them.
1513 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1514 The generated instruction will use BASE as its base register. BASE may
1515 simply be the stack pointer, but if several accesses are being made to a
1516 region far away from the stack pointer, it may be more efficient to set
1517 up a temporary instead.
1519 Store instructions will be frame-related and will be annotated with the
1520 overall effect of the store. Load instructions will be followed by a
1521 (use) to prevent later optimizations from zapping them.
1523 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1524 as a temporary in such cases. */
1526 frv_frame_access (accessor
, reg
, stack_offset
)
1527 frv_frame_accessor_t
*accessor
;
1531 enum machine_mode mode
= GET_MODE (reg
);
1532 rtx mem
= frv_frame_mem (mode
,
1534 stack_offset
- accessor
->base_offset
);
1536 if (accessor
->op
== FRV_LOAD
)
1538 if (SPR_P (REGNO (reg
)))
1540 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1541 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1542 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1545 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1546 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1550 if (SPR_P (REGNO (reg
)))
1552 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1553 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1554 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1555 frv_dwarf_store (reg
, stack_offset
));
1557 else if (GET_MODE (reg
) == DImode
)
1559 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1560 with a separate save for each register. */
1561 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1562 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1563 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1564 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1565 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1566 gen_rtx_PARALLEL (VOIDmode
,
1567 gen_rtvec (2, set1
, set2
)));
1570 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1571 frv_dwarf_store (reg
, stack_offset
));
1575 /* A function that uses frv_frame_access to transfer a group of registers to
1576 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1577 is the stack information generated by frv_stack_info, and REG_SET is the
1578 number of the register set to transfer. */
1580 frv_frame_access_multi (accessor
, info
, reg_set
)
1581 frv_frame_accessor_t
*accessor
;
1585 frv_stack_regs_t
*regs_info
;
1588 regs_info
= &info
->regs
[reg_set
];
1589 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1590 if (info
->save_p
[regno
])
1591 frv_frame_access (accessor
,
1592 info
->save_p
[regno
] == REG_SAVE_2WORDS
1593 ? gen_rtx_REG (DImode
, regno
)
1594 : gen_rtx_REG (SImode
, regno
),
1595 info
->reg_offset
[regno
]);
1598 /* Save or restore callee-saved registers that are kept outside the frame
1599 header. The function saves the registers if OP is FRV_STORE and restores
1600 them if OP is FRV_LOAD. INFO is the stack information generated by
1603 frv_frame_access_standard_regs (op
, info
)
1604 enum frv_stack_op op
;
1607 frv_frame_accessor_t accessor
;
1610 accessor
.base
= stack_pointer_rtx
;
1611 accessor
.base_offset
= 0;
1612 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1613 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1614 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1618 /* Called after register allocation to add any instructions needed for the
1619 prologue. Using a prologue insn is favored compared to putting all of the
1620 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1621 to intermix instructions with the saves of the caller saved registers. In
1622 some cases, it might be necessary to emit a barrier instruction as the last
1623 insn to prevent such scheduling.
1625 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1626 so that the debug info generation code can handle them properly. */
1628 frv_expand_prologue ()
1630 frv_stack_t
*info
= frv_stack_info ();
1631 rtx sp
= stack_pointer_rtx
;
1632 rtx fp
= frame_pointer_rtx
;
1633 frv_frame_accessor_t accessor
;
1635 if (TARGET_DEBUG_STACK
)
1636 frv_debug_stack (info
);
1638 if (info
->total_size
== 0)
1641 /* We're interested in three areas of the frame here:
1643 A: the register save area
1645 C: the header after B
1647 If the frame pointer isn't used, we'll have to set up A, B and C
1648 using the stack pointer. If the frame pointer is used, we'll access
1652 B: set up using sp or a temporary (see below)
1655 We set up B using the stack pointer if the frame is small enough.
1656 Otherwise, it's more efficient to copy the old stack pointer into a
1657 temporary and use that.
1659 Note that it's important to make sure the prologue and epilogue use the
1660 same registers to access A and C, since doing otherwise will confuse
1661 the aliasing code. */
1663 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1664 isn't used, the same method will serve for C. */
1665 accessor
.op
= FRV_STORE
;
1666 if (frame_pointer_needed
&& info
->total_size
> 2048)
1670 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1671 accessor
.base_offset
= info
->total_size
;
1672 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1676 accessor
.base
= stack_pointer_rtx
;
1677 accessor
.base_offset
= 0;
1680 /* Allocate the stack space. */
1682 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1683 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1685 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1688 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1691 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1692 and point the new one to that location. */
1693 if (frame_pointer_needed
)
1695 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1697 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1698 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1700 rtx asm_src
= plus_constant (accessor
.base
,
1701 fp_offset
- accessor
.base_offset
);
1702 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1704 /* Store the old frame pointer at (sp + FP_OFFSET). */
1705 frv_frame_access (&accessor
, fp
, fp_offset
);
1707 /* Set up the new frame pointer. */
1708 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1709 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1711 /* Access region C from the frame pointer. */
1713 accessor
.base_offset
= fp_offset
;
1716 /* Set up region C. */
1717 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1718 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1719 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1721 /* Set up region A. */
1722 frv_frame_access_standard_regs (FRV_STORE
, info
);
1724 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1725 scheduler from moving loads before the stores saving the registers. */
1726 if (info
->stdarg_size
> 0)
1727 emit_insn (gen_blockage ());
1729 /* Set up pic register/small data register for this function. */
1730 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1731 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1732 gen_rtx_REG (Pmode
, LR_REGNO
),
1733 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1737 /* Under frv, all of the work is done via frv_expand_epilogue, but
1738 this function provides a convient place to do cleanup. */
1741 frv_function_epilogue (file
, size
)
1742 FILE *file ATTRIBUTE_UNUSED
;
1743 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1745 frv_stack_cache
= (frv_stack_t
*)0;
1747 /* zap last used registers for conditional execution. */
1748 memset ((PTR
) &frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1750 /* release the bitmap of created insns. */
1751 BITMAP_XFREE (frv_ifcvt
.scratch_insns_bitmap
);
1755 /* Called after register allocation to add any instructions needed for the
1756 epilogue. Using a epilogue insn is favored compared to putting all of the
1757 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1758 to intermix instructions with the saves of the caller saved registers. In
1759 some cases, it might be necessary to emit a barrier instruction as the last
1760 insn to prevent such scheduling.
1762 If SIBCALL_P is true, the final branch back to the calling function is
1763 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1764 we must not clobber any arguments used for parameter passing or any stack
1765 slots for arguments passed to the current function. */
1768 frv_expand_epilogue (sibcall_p
)
1771 frv_stack_t
*info
= frv_stack_info ();
1772 rtx fp
= frame_pointer_rtx
;
1773 rtx sp
= stack_pointer_rtx
;
1777 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1779 /* Restore the stack pointer to its original value if alloca or the like
1781 if (! current_function_sp_is_unchanging
)
1782 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1784 /* Restore the callee-saved registers that were used in this function. */
1785 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1787 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1788 no return instruction should be emitted. */
1791 else if (info
->save_p
[LR_REGNO
])
1796 /* Use the same method to access the link register's slot as we did in
1797 the prologue. In other words, use the frame pointer if available,
1798 otherwise use the stack pointer.
1800 LR_OFFSET is the offset of the link register's slot from the start
1801 of the frame and MEM is a memory rtx for it. */
1802 lr_offset
= info
->reg_offset
[LR_REGNO
];
1803 if (frame_pointer_needed
)
1804 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1806 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1808 /* Load the old link register into a GPR. */
1809 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1810 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1813 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1815 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1816 the load is preserved. */
1817 if (frame_pointer_needed
)
1819 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1820 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1823 /* Deallocate the stack frame. */
1824 if (info
->total_size
!= 0)
1826 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1827 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1830 /* If this function uses eh_return, add the final stack adjustment now. */
1831 if (current_function_calls_eh_return
)
1832 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1835 emit_jump_insn (gen_epilogue_return (return_addr
));
1839 /* A C compound statement that outputs the assembler code for a thunk function,
1840 used to implement C++ virtual function calls with multiple inheritance. The
1841 thunk acts as a wrapper around a virtual function, adjusting the implicit
1842 object parameter before handing control off to the real function.
1844 First, emit code to add the integer DELTA to the location that contains the
1845 incoming first argument. Assume that this argument contains a pointer, and
1846 is the one used to pass the `this' pointer in C++. This is the incoming
1847 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1848 addition must preserve the values of all other incoming arguments.
1850 After the addition, emit code to jump to FUNCTION, which is a
1851 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1852 the return address. Hence returning from FUNCTION will return to whoever
1853 called the current `thunk'.
1855 The effect must be as if FUNCTION had been called directly with the adjusted
1856 first argument. This macro is responsible for emitting all of the code for
1857 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1860 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1861 extracted from it.) It might possibly be useful on some targets, but
1864 If you do not define this macro, the target-independent code in the C++
1865 frontend will generate a less efficient heavyweight thunk that calls
1866 FUNCTION instead of jumping to it. The generic approach does not support
1870 frv_asm_output_mi_thunk (file
, thunk_fndecl
, delta
, function
)
1872 tree thunk_fndecl ATTRIBUTE_UNUSED
;
1876 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1877 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1878 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1879 const char *parallel
= ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1881 /* Do the add using an addi if possible */
1882 if (IN_RANGE_P (delta
, -2048, 2047))
1883 fprintf (file
, "\taddi %s,#%ld,%s\n", name_arg0
, delta
, name_arg0
);
1886 const char *name_add
= reg_names
[TEMP_REGNO
];
1887 fprintf (file
, "\tsethi%s #hi(%ld),%s\n", parallel
, delta
, name_add
);
1888 fprintf (file
, "\tsetlo #lo(%ld),%s\n", delta
, name_add
);
1889 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1894 fprintf (file
, "\tsethi%s #hi(", parallel
);
1895 assemble_name (file
, name_func
);
1896 fprintf (file
, "),%s\n", name_jmp
);
1898 fprintf (file
, "\tsetlo #lo(");
1899 assemble_name (file
, name_func
);
1900 fprintf (file
, "),%s\n", name_jmp
);
1904 /* Use JUMP_REGNO as a temporary PIC register. */
1905 const char *name_lr
= reg_names
[LR_REGNO
];
1906 const char *name_gppic
= name_jmp
;
1907 const char *name_tmp
= reg_names
[TEMP_REGNO
];
1909 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
1910 fprintf (file
, "\tcall 1f\n");
1911 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
1912 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
1913 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
1914 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
1915 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
1917 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
1918 assemble_name (file
, name_func
);
1919 fprintf (file
, "),%s\n", name_tmp
);
1921 fprintf (file
, "\tsetlo #gprello(");
1922 assemble_name (file
, name_func
);
1923 fprintf (file
, "),%s\n", name_tmp
);
1925 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
1928 /* Jump to the function address */
1929 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
1933 /* A C expression which is nonzero if a function must have and use a frame
1934 pointer. This expression is evaluated in the reload pass. If its value is
1935 nonzero the function will have a frame pointer.
1937 The expression can in principle examine the current function and decide
1938 according to the facts, but on most machines the constant 0 or the constant
1939 1 suffices. Use 0 when the machine allows code to be generated with no
1940 frame pointer, and doing so saves some time or space. Use 1 when there is
1941 no possible advantage to avoiding a frame pointer.
1943 In certain cases, the compiler does not know how to produce valid code
1944 without a frame pointer. The compiler recognizes those cases and
1945 automatically gives the function a frame pointer regardless of what
1946 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1948 In a function that does not require a frame pointer, the frame pointer
1949 register can be allocated for ordinary usage, unless you mark it as a fixed
1950 register. See `FIXED_REGISTERS' for more information. */
1952 /* On frv, create a frame whenever we need to create stack */
1955 frv_frame_pointer_required ()
1957 if (! current_function_is_leaf
)
1960 if (get_frame_size () != 0)
1966 if (!current_function_sp_is_unchanging
)
1969 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1975 if (cfun
->machine
->frame_needed
)
1982 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1983 initial difference between the specified pair of registers. This macro must
1984 be defined if `ELIMINABLE_REGS' is defined. */
1986 /* See frv_stack_info for more details on the frv stack frame. */
1989 frv_initial_elimination_offset (from
, to
)
1993 frv_stack_t
*info
= frv_stack_info ();
1996 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
1997 ret
= info
->total_size
- info
->pretend_size
;
1999 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2000 ret
= - info
->reg_offset
[FRAME_POINTER_REGNUM
];
2002 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2003 ret
= (info
->total_size
2004 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2005 - info
->pretend_size
);
2010 if (TARGET_DEBUG_STACK
)
2011 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2012 reg_names
[from
], reg_names
[to
], ret
);
2018 /* This macro offers an alternative to using `__builtin_saveregs' and defining
2019 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
2020 arguments into the stack so that all the arguments appear to have been
2021 passed consecutively on the stack. Once this is done, you can use the
2022 standard implementation of varargs that works for machines that pass all
2023 their arguments on the stack.
2025 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
2026 the values that obtain after processing of the named arguments. The
2027 arguments MODE and TYPE describe the last named argument--its machine mode
2028 and its data type as a tree node.
2030 The macro implementation should do two things: first, push onto the stack
2031 all the argument registers *not* used for the named arguments, and second,
2032 store the size of the data thus pushed into the `int'-valued variable whose
2033 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
2034 store here will serve as additional offset for setting up the stack frame.
2036 Because you must generate code to push the anonymous arguments at compile
2037 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
2038 useful on machines that have just a single category of argument register and
2039 use it uniformly for all data types.
2041 If the argument SECOND_TIME is nonzero, it means that the arguments of the
2042 function are being analyzed for the second time. This happens for an inline
2043 function, which is not actually compiled until the end of the source file.
2044 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
2048 frv_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, second_time
)
2049 CUMULATIVE_ARGS
*cum
;
2050 enum machine_mode mode
;
2051 tree type ATTRIBUTE_UNUSED
;
2055 if (TARGET_DEBUG_ARG
)
2057 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2058 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2062 /* If defined, is a C expression that produces the machine-specific code for a
2063 call to `__builtin_saveregs'. This code will be moved to the very beginning
2064 of the function, before any parameter access are made. The return value of
2065 this function should be an RTX that contains the value to use as the return
2066 of `__builtin_saveregs'.
2068 If this macro is not defined, the compiler will output an ordinary call to
2069 the library function `__builtin_saveregs'. */
2072 frv_expand_builtin_saveregs ()
2074 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2076 if (TARGET_DEBUG_ARG
)
2077 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2080 return gen_rtx (PLUS
, Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2084 /* Expand __builtin_va_start to do the va_start macro. */
2087 frv_expand_builtin_va_start (valist
, nextarg
)
2092 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2094 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2095 GEN_INT (UNITS_PER_WORD
* num
));
2097 if (TARGET_DEBUG_ARG
)
2099 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2100 cfun
->args_info
, num
);
2102 debug_rtx (nextarg
);
2105 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2106 make_tree (ptr_type_node
, nextarg
));
2107 TREE_SIDE_EFFECTS (t
) = 1;
2109 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2113 /* Expand __builtin_va_arg to do the va_arg macro. */
2116 frv_expand_builtin_va_arg(valist
, type
)
2124 if (TARGET_DEBUG_ARG
)
2126 fprintf (stderr
, "va_arg:\n");
2130 if (! AGGREGATE_TYPE_P (type
))
2131 return std_expand_builtin_va_arg (valist
, type
);
2133 addr
= std_expand_builtin_va_arg (valist
, ptr_type_node
);
2134 mem
= gen_rtx_MEM (Pmode
, addr
);
2135 reg
= gen_reg_rtx (Pmode
);
2137 set_mem_alias_set (mem
, get_varargs_alias_set ());
2138 emit_move_insn (reg
, mem
);
2144 /* Expand a block move operation, and return 1 if successful. Return 0
2145 if we should let the compiler generate normal code.
2147 operands[0] is the destination
2148 operands[1] is the source
2149 operands[2] is the length
2150 operands[3] is the alignment */
2152 /* Maximum number of loads to do before doing the stores */
2153 #ifndef MAX_MOVE_REG
2154 #define MAX_MOVE_REG 4
2157 /* Maximum number of total loads to do. */
2158 #ifndef TOTAL_MOVE_REG
2159 #define TOTAL_MOVE_REG 8
2163 frv_expand_block_move (operands
)
2166 rtx orig_dest
= operands
[0];
2167 rtx orig_src
= operands
[1];
2168 rtx bytes_rtx
= operands
[2];
2169 rtx align_rtx
= operands
[3];
2170 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2183 rtx stores
[MAX_MOVE_REG
];
2185 enum machine_mode mode
;
2187 /* If this is not a fixed size move, just call memcpy */
2191 /* If this is not a fixed size alignment, abort */
2192 if (GET_CODE (align_rtx
) != CONST_INT
)
2195 align
= INTVAL (align_rtx
);
2197 /* Anything to move? */
2198 bytes
= INTVAL (bytes_rtx
);
2202 /* Don't support real large moves. */
2203 if (bytes
> TOTAL_MOVE_REG
*align
)
2206 /* Move the address into scratch registers. */
2207 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2208 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2210 num_reg
= offset
= 0;
2211 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2213 /* Calculate the correct offset for src/dest */
2217 dest_addr
= dest_reg
;
2221 src_addr
= plus_constant (src_reg
, offset
);
2222 dest_addr
= plus_constant (dest_reg
, offset
);
2225 /* Generate the appropriate load and store, saving the stores
2227 if (bytes
>= 4 && align
>= 4)
2229 else if (bytes
>= 2 && align
>= 2)
2234 move_bytes
= GET_MODE_SIZE (mode
);
2235 tmp_reg
= gen_reg_rtx (mode
);
2236 src_mem
= change_address (orig_src
, mode
, src_addr
);
2237 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2238 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2239 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2241 if (num_reg
>= MAX_MOVE_REG
)
2243 for (i
= 0; i
< num_reg
; i
++)
2244 emit_insn (stores
[i
]);
2249 for (i
= 0; i
< num_reg
; i
++)
2250 emit_insn (stores
[i
]);
2256 /* Expand a block clear operation, and return 1 if successful. Return 0
2257 if we should let the compiler generate normal code.
2259 operands[0] is the destination
2260 operands[1] is the length
2261 operands[2] is the alignment */
2264 frv_expand_block_clear (operands
)
2267 rtx orig_dest
= operands
[0];
2268 rtx bytes_rtx
= operands
[1];
2269 rtx align_rtx
= operands
[2];
2270 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2279 enum machine_mode mode
;
2281 /* If this is not a fixed size move, just call memcpy */
2285 /* If this is not a fixed size alignment, abort */
2286 if (GET_CODE (align_rtx
) != CONST_INT
)
2289 align
= INTVAL (align_rtx
);
2291 /* Anything to move? */
2292 bytes
= INTVAL (bytes_rtx
);
2296 /* Don't support real large clears. */
2297 if (bytes
> TOTAL_MOVE_REG
*align
)
2300 /* Move the address into a scratch register. */
2301 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2303 num_reg
= offset
= 0;
2304 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2306 /* Calculate the correct offset for src/dest */
2307 dest_addr
= ((offset
== 0)
2309 : plus_constant (dest_reg
, offset
));
2311 /* Generate the appropriate store of gr0 */
2312 if (bytes
>= 4 && align
>= 4)
2314 else if (bytes
>= 2 && align
>= 2)
2319 clear_bytes
= GET_MODE_SIZE (mode
);
2320 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2321 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2328 /* The following variable is used to output modifiers of assembler
2329 code of the current output insn.. */
2331 static rtx
*frv_insn_operands
;
2333 /* The following function is used to add assembler insn code suffix .p
2334 if it is necessary. */
2337 frv_asm_output_opcode (f
, ptr
)
2343 if (! PACKING_FLAG_USED_P())
2346 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2349 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2350 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2352 int letter
= *ptr
++;
2355 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2356 while ((c
= *ptr
) >= '0' && c
<= '9')
2363 if (!frv_insn_packing_flag
)
2369 /* The following function sets up the packing bit for the current
2370 output insn. Remember that the function is not called for asm
2374 frv_final_prescan_insn (insn
, opvec
, noperands
)
2377 int noperands ATTRIBUTE_UNUSED
;
2379 if (! PACKING_FLAG_USED_P())
2382 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
2385 frv_insn_operands
= opvec
;
2387 /* Look for the next printable instruction. frv_pack_insns () has set
2388 things up so that any printable instruction will have TImode if it
2389 starts a new packet and VOIDmode if it should be packed with the
2390 previous instruction.
2392 Printable instructions will be asm_operands or match one of the .md
2393 patterns. Since asm instructions cannot be packed -- and will
2394 therefore have TImode -- this loop terminates on any recognisable
2395 instruction, and on any unrecognisable instruction with TImode. */
2396 for (insn
= NEXT_INSN (insn
); insn
; insn
= NEXT_INSN (insn
))
2400 else if (!INSN_P (insn
))
2402 else if (GET_MODE (insn
) == TImode
|| INSN_CODE (insn
) != -1)
2406 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2407 be packed with this one. Set it to TRUE otherwise. If the next
2408 instruction is an asm insntruction, this statement will set the
2409 flag to TRUE, and that value will still hold when the asm operands
2410 themselves are printed. */
2411 frv_insn_packing_flag
= ! (insn
&& INSN_P (insn
)
2412 && GET_MODE (insn
) != TImode
);
2417 /* A C expression whose value is RTL representing the address in a stack frame
2418 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2419 an RTL expression for the address of the stack frame itself.
2421 If you don't define this macro, the default is to return the value of
2422 FRAMEADDR--that is, the stack frame address is also the address of the stack
2423 word that points to the previous frame. */
2425 /* The default is correct, but we need to make sure the frame gets created. */
2427 frv_dynamic_chain_address (frame
)
2430 cfun
->machine
->frame_needed
= 1;
2435 /* A C expression whose value is RTL representing the value of the return
2436 address for the frame COUNT steps up from the current frame, after the
2437 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2438 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2441 The value of the expression must always be the correct address when COUNT is
2442 zero, but may be `NULL_RTX' if there is not way to determine the return
2443 address of other frames. */
2446 frv_return_addr_rtx (count
, frame
)
2447 int count ATTRIBUTE_UNUSED
;
2450 cfun
->machine
->frame_needed
= 1;
2451 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2454 /* Given a memory reference MEMREF, interpret the referenced memory as
2455 an array of MODE values, and return a reference to the element
2456 specified by INDEX. Assume that any pre-modification implicit in
2457 MEMREF has already happened.
2459 MEMREF must be a legitimate operand for modes larger than SImode.
2460 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2461 this function cannot handle. */
2463 frv_index_memory (memref
, mode
, index
)
2465 enum machine_mode mode
;
2468 rtx base
= XEXP (memref
, 0);
2469 if (GET_CODE (base
) == PRE_MODIFY
)
2470 base
= XEXP (base
, 0);
2471 return change_address (memref
, mode
,
2472 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2476 /* Print a memory address as an operand to reference that memory location. */
2478 frv_print_operand_address (stream
, x
)
2482 if (GET_CODE (x
) == MEM
)
2485 switch (GET_CODE (x
))
2488 fputs (reg_names
[ REGNO (x
)], stream
);
2492 fprintf (stream
, "%ld", (long) INTVAL (x
));
2496 assemble_name (stream
, XSTR (x
, 0));
2501 output_addr_const (stream
, x
);
2508 fatal_insn ("Bad insn to frv_print_operand_address:", x
);
2513 frv_print_operand_memory_reference_reg (stream
, x
)
2517 int regno
= true_regnum (x
);
2519 fputs (reg_names
[regno
], stream
);
2521 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x
);
2524 /* Print a memory reference suitable for the ld/st instructions. */
2527 frv_print_operand_memory_reference (stream
, x
, addr_offset
)
2535 switch (GET_CODE (x
))
2542 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2544 x1
= XEXP (XEXP (x
, 1), 1);
2554 if (GET_CODE (x0
) == CONST_INT
)
2562 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2571 else if (GET_CODE (x1
) != CONST_INT
)
2572 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2575 fputs ("@(", stream
);
2577 fputs (reg_names
[GPR_R0
], stream
);
2578 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2579 frv_print_operand_memory_reference_reg (stream
, x0
);
2581 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2583 fputs (",", stream
);
2585 fputs (reg_names
[GPR_R0
], stream
);
2589 switch (GET_CODE (x1
))
2593 frv_print_operand_memory_reference_reg (stream
, x1
);
2597 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2601 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2602 && symbol_ref_small_data_p (x1
))
2604 fputs ("#gprel12(", stream
);
2605 assemble_name (stream
, XSTR (x1
, 0));
2606 fputs (")", stream
);
2609 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2613 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2614 && const_small_data_p (x1
))
2616 fputs ("#gprel12(", stream
);
2617 assemble_name (stream
, XSTR (XEXP (XEXP (x1
, 0), 0), 0));
2618 fprintf (stream
, "+%d)", INTVAL (XEXP (XEXP (x1
, 0), 1)));
2621 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2625 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2629 fputs (")", stream
);
2633 /* Return 2 for likely branches and 0 for non-likely branches */
2635 #define FRV_JUMP_LIKELY 2
2636 #define FRV_JUMP_NOT_LIKELY 0
2639 frv_print_operand_jump_hint (insn
)
2645 HOST_WIDE_INT prob
= -1;
2646 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2648 if (GET_CODE (insn
) != JUMP_INSN
)
2651 /* Assume any non-conditional jump is likely. */
2652 if (! any_condjump_p (insn
))
2653 ret
= FRV_JUMP_LIKELY
;
2657 labelref
= condjump_label (insn
);
2660 rtx label
= XEXP (labelref
, 0);
2661 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2666 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2668 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2672 prob
= INTVAL (XEXP (note
, 0));
2673 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2675 : FRV_JUMP_NOT_LIKELY
);
2687 case UNKNOWN
: direction
= "unknown jump direction"; break;
2688 case BACKWARD
: direction
= "jump backward"; break;
2689 case FORWARD
: direction
= "jump forward"; break;
2693 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2694 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2695 (long)INSN_UID (insn
), direction
, (long)prob
,
2696 (long)REG_BR_PROB_BASE
, ret
);
2704 /* Print an operand to a assembler instruction.
2706 `%' followed by a letter and a digit says to output an operand in an
2707 alternate fashion. Four letters have standard, built-in meanings described
2708 below. The machine description macro `PRINT_OPERAND' can define additional
2709 letters with nonstandard meanings.
2711 `%cDIGIT' can be used to substitute an operand that is a constant value
2712 without the syntax that normally indicates an immediate operand.
2714 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2717 `%aDIGIT' can be used to substitute an operand as if it were a memory
2718 reference, with the actual operand treated as the address. This may be
2719 useful when outputting a "load address" instruction, because often the
2720 assembler syntax for such an instruction requires you to write the operand
2721 as if it were a memory reference.
2723 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2725 `%=' outputs a number which is unique to each instruction in the entire
2726 compilation. This is useful for making local labels to be referred to more
2727 than once in a single template that generates multiple assembler
2730 `%' followed by a punctuation character specifies a substitution that does
2731 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2732 assembler code. Other nonstandard cases can be defined in the
2733 `PRINT_OPERAND' macro. You must also define which punctuation characters
2734 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2737 frv_print_operand (file
, x
, code
)
2742 HOST_WIDE_INT value
;
2745 if (code
!= 0 && !isalpha (code
))
2748 else if (GET_CODE (x
) == CONST_INT
)
2751 else if (GET_CODE (x
) == CONST_DOUBLE
)
2753 if (GET_MODE (x
) == SFmode
)
2758 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2759 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2763 else if (GET_MODE (x
) == VOIDmode
)
2764 value
= CONST_DOUBLE_LOW (x
);
2767 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x
);
2778 fputs (reg_names
[GPR_R0
], file
);
2782 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2785 case SDATA_FLAG_CHAR
:
2786 /* Output small data area base register (gr16). */
2787 fputs (reg_names
[SDA_BASE_REG
], file
);
2791 /* Output pic register (gr17). */
2792 fputs (reg_names
[PIC_REGNO
], file
);
2796 /* Output the temporary integer CCR register */
2797 fputs (reg_names
[ICR_TEMP
], file
);
2801 /* Output the temporary integer CC register */
2802 fputs (reg_names
[ICC_TEMP
], file
);
2805 /* case 'a': print an address */
2808 /* Print appropriate test for integer branch false operation */
2809 switch (GET_CODE (x
))
2812 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x
);
2814 case EQ
: fputs ("ne", file
); break;
2815 case NE
: fputs ("eq", file
); break;
2816 case LT
: fputs ("ge", file
); break;
2817 case LE
: fputs ("gt", file
); break;
2818 case GT
: fputs ("le", file
); break;
2819 case GE
: fputs ("lt", file
); break;
2820 case LTU
: fputs ("nc", file
); break;
2821 case LEU
: fputs ("hi", file
); break;
2822 case GTU
: fputs ("ls", file
); break;
2823 case GEU
: fputs ("c", file
); break;
2827 /* case 'c': print a constant without the constant prefix. If
2828 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2831 /* Print appropriate test for integer branch true operation */
2832 switch (GET_CODE (x
))
2835 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x
);
2837 case EQ
: fputs ("eq", file
); break;
2838 case NE
: fputs ("ne", file
); break;
2839 case LT
: fputs ("lt", file
); break;
2840 case LE
: fputs ("le", file
); break;
2841 case GT
: fputs ("gt", file
); break;
2842 case GE
: fputs ("ge", file
); break;
2843 case LTU
: fputs ("c", file
); break;
2844 case LEU
: fputs ("ls", file
); break;
2845 case GTU
: fputs ("hi", file
); break;
2846 case GEU
: fputs ("nc", file
); break;
2851 /* Print 1 for a NE and 0 for an EQ to give the final argument
2852 for a conditional instruction. */
2853 if (GET_CODE (x
) == NE
)
2856 else if (GET_CODE (x
) == EQ
)
2860 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x
);
2864 /* Print appropriate test for floating point branch false operation */
2865 switch (GET_CODE (x
))
2868 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x
);
2870 case EQ
: fputs ("ne", file
); break;
2871 case NE
: fputs ("eq", file
); break;
2872 case LT
: fputs ("uge", file
); break;
2873 case LE
: fputs ("ug", file
); break;
2874 case GT
: fputs ("ule", file
); break;
2875 case GE
: fputs ("ul", file
); break;
2880 /* Print appropriate test for floating point branch true operation */
2881 switch (GET_CODE (x
))
2884 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x
);
2886 case EQ
: fputs ("eq", file
); break;
2887 case NE
: fputs ("ne", file
); break;
2888 case LT
: fputs ("lt", file
); break;
2889 case LE
: fputs ("le", file
); break;
2890 case GT
: fputs ("gt", file
); break;
2891 case GE
: fputs ("ge", file
); break;
2896 /* Print 'i' if the operand is a constant, or is a memory reference that
2898 if (GET_CODE (x
) == MEM
)
2899 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2900 ? XEXP (XEXP (x
, 0), 1)
2903 switch (GET_CODE (x
))
2917 /* For jump instructions, print 'i' if the operand is a constant or
2918 is an expression that adds a constant */
2919 if (GET_CODE (x
) == CONST_INT
)
2924 if (GET_CODE (x
) == CONST_INT
2925 || (GET_CODE (x
) == PLUS
2926 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2927 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2933 /* Print the lower register of a double word register pair */
2934 if (GET_CODE (x
) == REG
)
2935 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2937 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x
);
2940 /* case 'l': print a LABEL_REF */
2944 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2945 for the second word of double memory operations. */
2946 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2947 switch (GET_CODE (x
))
2950 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x
);
2953 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2961 frv_print_operand_memory_reference (file
, x
, offset
);
2967 /* Print the opcode of a command. */
2968 switch (GET_CODE (x
))
2971 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x
);
2973 case PLUS
: fputs ("add", file
); break;
2974 case MINUS
: fputs ("sub", file
); break;
2975 case AND
: fputs ("and", file
); break;
2976 case IOR
: fputs ("or", file
); break;
2977 case XOR
: fputs ("xor", file
); break;
2978 case ASHIFT
: fputs ("sll", file
); break;
2979 case ASHIFTRT
: fputs ("sra", file
); break;
2980 case LSHIFTRT
: fputs ("srl", file
); break;
2984 /* case 'n': negate and print a constant int */
2987 /* Print PIC label using operand as the number. */
2988 if (GET_CODE (x
) != CONST_INT
)
2989 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x
);
2991 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2995 /* Print 'u' if the operand is a update load/store */
2996 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
3001 /* If value is 0, print gr0, otherwise it must be a register */
3002 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3003 fputs (reg_names
[GPR_R0
], file
);
3005 else if (GET_CODE (x
) == REG
)
3006 fputs (reg_names
[REGNO (x
)], file
);
3009 fatal_insn ("Bad insn in frv_print_operand, z case", x
);
3013 /* Print constant in hex */
3014 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3016 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3023 if (GET_CODE (x
) == REG
)
3024 fputs (reg_names
[REGNO (x
)], file
);
3026 else if (GET_CODE (x
) == CONST_INT
3027 || GET_CODE (x
) == CONST_DOUBLE
)
3028 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3030 else if (GET_CODE (x
) == MEM
)
3031 frv_print_operand_address (file
, XEXP (x
, 0));
3033 else if (CONSTANT_ADDRESS_P (x
))
3034 frv_print_operand_address (file
, x
);
3037 fatal_insn ("Bad insn in frv_print_operand, 0 case", x
);
3042 fatal_insn ("frv_print_operand: unknown code", x
);
3050 /* A C statement (sans semicolon) for initializing the variable CUM for the
3051 state at the beginning of the argument list. The variable has type
3052 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3053 of the function which will receive the args, or 0 if the args are to a
3054 compiler support library function. The value of INDIRECT is nonzero when
3055 processing an indirect call, for example a call through a function pointer.
3056 The value of INDIRECT is zero for a call to an explicitly named function, a
3057 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3058 arguments for the function being compiled.
3060 When processing a call to a compiler support library function, LIBNAME
3061 identifies which one. It is a `symbol_ref' rtx which contains the name of
3062 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3063 being processed. Thus, each time this macro is called, either LIBNAME or
3064 FNTYPE is nonzero, but never both of them at once. */
3067 frv_init_cumulative_args (cum
, fntype
, libname
, indirect
, incoming
)
3068 CUMULATIVE_ARGS
*cum
;
3074 *cum
= FIRST_ARG_REGNUM
;
3076 if (TARGET_DEBUG_ARG
)
3078 fprintf (stderr
, "\ninit_cumulative_args:");
3080 fputs (" indirect", stderr
);
3083 fputs (" incoming", stderr
);
3087 tree ret_type
= TREE_TYPE (fntype
);
3088 fprintf (stderr
, " return=%s,",
3089 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3092 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3093 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3095 if (cfun
->returns_struct
)
3096 fprintf (stderr
, " return-struct");
3098 putc ('\n', stderr
);
3103 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3104 argument with the specified mode and type. If it is not defined,
3105 `PARM_BOUNDARY' is used for all arguments. */
3108 frv_function_arg_boundary (mode
, type
)
3109 enum machine_mode mode ATTRIBUTE_UNUSED
;
3110 tree type ATTRIBUTE_UNUSED
;
3112 return BITS_PER_WORD
;
3116 /* A C expression that controls whether a function argument is passed in a
3117 register, and which register.
3119 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
3120 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
3121 arguments so far passed in registers; MODE, the machine mode of the argument;
3122 TYPE, the data type of the argument as a tree node or 0 if that is not known
3123 (which happens for C support library functions); and NAMED, which is 1 for an
3124 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3125 called function's prototype.
3127 The value of the expression should either be a `reg' RTX for the hard
3128 register in which to pass the argument, or zero to pass the argument on the
3131 For machines like the VAX and 68000, where normally all arguments are
3132 pushed, zero suffices as a definition.
3134 The usual way to make the ANSI library `stdarg.h' work on a machine where
3135 some arguments are usually passed in registers, is to cause nameless
3136 arguments to be passed on the stack instead. This is done by making
3137 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3139 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3140 this macro to determine if this argument is of a type that must be passed in
3141 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3142 returns nonzero for such an argument, the compiler will abort. If
3143 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3144 stack and then loaded into a register. */
3147 frv_function_arg (cum
, mode
, type
, named
, incoming
)
3148 CUMULATIVE_ARGS
*cum
;
3149 enum machine_mode mode
;
3150 tree type ATTRIBUTE_UNUSED
;
3152 int incoming ATTRIBUTE_UNUSED
;
3154 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3159 /* Return a marker for use in the call instruction. */
3160 if (xmode
== VOIDmode
)
3166 else if (arg_num
<= LAST_ARG_REGNUM
)
3168 ret
= gen_rtx (REG
, xmode
, arg_num
);
3169 debstr
= reg_names
[arg_num
];
3178 if (TARGET_DEBUG_ARG
)
3180 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3181 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3187 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3188 advance past an argument in the argument list. The values MODE, TYPE and
3189 NAMED describe that argument. Once this is done, the variable CUM is
3190 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3192 This macro need not do anything if the argument in question was passed on
3193 the stack. The compiler knows how to track the amount of stack space used
3194 for arguments without any special help. */
3197 frv_function_arg_advance (cum
, mode
, type
, named
)
3198 CUMULATIVE_ARGS
*cum
;
3199 enum machine_mode mode
;
3200 tree type ATTRIBUTE_UNUSED
;
3203 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3204 int bytes
= GET_MODE_SIZE (xmode
);
3205 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3208 *cum
= arg_num
+ words
;
3210 if (TARGET_DEBUG_ARG
)
3212 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3213 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3217 /* A C expression for the number of words, at the beginning of an argument,
3218 must be put in registers. The value must be zero for arguments that are
3219 passed entirely in registers or that are entirely pushed on the stack.
3221 On some machines, certain arguments must be passed partially in registers
3222 and partially in memory. On these machines, typically the first N words of
3223 arguments are passed in registers, and the rest on the stack. If a
3224 multi-word argument (a `double' or a structure) crosses that boundary, its
3225 first few words must be passed in registers and the rest must be pushed.
3226 This macro tells the compiler when this occurs, and how many of the words
3227 should go in registers.
3229 `FUNCTION_ARG' for these arguments should return the first register to be
3230 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3231 the called function. */
3234 frv_function_arg_partial_nregs (cum
, mode
, type
, named
)
3235 CUMULATIVE_ARGS
*cum
;
3236 enum machine_mode mode
;
3237 tree type ATTRIBUTE_UNUSED
;
3238 int named ATTRIBUTE_UNUSED
;
3240 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3241 int bytes
= GET_MODE_SIZE (xmode
);
3242 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3246 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3247 ? LAST_ARG_REGNUM
- arg_num
+ 1
3250 if (TARGET_DEBUG_ARG
&& ret
)
3251 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
3259 /* A C expression that indicates when an argument must be passed by reference.
3260 If nonzero for an argument, a copy of that argument is made in memory and a
3261 pointer to the argument is passed instead of the argument itself. The
3262 pointer is passed in whatever way is appropriate for passing a pointer to
3265 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3266 definition of this macro might be
3267 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3268 MUST_PASS_IN_STACK (MODE, TYPE) */
3271 frv_function_arg_pass_by_reference (cum
, mode
, type
, named
)
3272 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3273 enum machine_mode mode
;
3275 int named ATTRIBUTE_UNUSED
;
3277 return MUST_PASS_IN_STACK (mode
, type
);
3280 /* If defined, a C expression that indicates when it is the called function's
3281 responsibility to make a copy of arguments passed by invisible reference.
3282 Normally, the caller makes a copy and passes the address of the copy to the
3283 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3284 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3285 the "live" value. The called function must not modify this value. If it
3286 can be determined that the value won't be modified, it need not make a copy;
3287 otherwise a copy must be made. */
3290 frv_function_arg_callee_copies (cum
, mode
, type
, named
)
3291 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3292 enum machine_mode mode ATTRIBUTE_UNUSED
;
3293 tree type ATTRIBUTE_UNUSED
;
3294 int named ATTRIBUTE_UNUSED
;
3299 /* If defined, a C expression that indicates when it is more desirable to keep
3300 an argument passed by invisible reference as a reference, rather than
3301 copying it to a pseudo register. */
3304 frv_function_arg_keep_as_reference (cum
, mode
, type
, named
)
3305 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
3306 enum machine_mode mode ATTRIBUTE_UNUSED
;
3307 tree type ATTRIBUTE_UNUSED
;
3308 int named ATTRIBUTE_UNUSED
;
3314 /* Return true if a register is ok to use as a base or index register. */
3316 static FRV_INLINE
int
3317 frv_regno_ok_for_base_p (regno
, strict_p
)
3325 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3327 if (regno
== ARG_POINTER_REGNUM
)
3330 return (regno
>= FIRST_PSEUDO_REGISTER
);
3334 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3335 RTX) is a legitimate memory address on the target machine for a memory
3336 operand of mode MODE.
3338 It usually pays to define several simpler macros to serve as subroutines for
3339 this one. Otherwise it may be too complicated to understand.
3341 This macro must exist in two variants: a strict variant and a non-strict
3342 one. The strict variant is used in the reload pass. It must be defined so
3343 that any pseudo-register that has not been allocated a hard register is
3344 considered a memory reference. In contexts where some kind of register is
3345 required, a pseudo-register with no hard register must be rejected.
3347 The non-strict variant is used in other passes. It must be defined to
3348 accept all pseudo-registers in every context where some kind of register is
3351 Compiler source files that want to use the strict variant of this macro
3352 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3353 conditional to define the strict variant in that case and the non-strict
3356 Subroutines to check for acceptable registers for various purposes (one for
3357 base registers, one for index registers, and so on) are typically among the
3358 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3359 subroutine macros need have two variants; the higher levels of macros may be
3360 the same whether strict or not.
3362 Normally, constant addresses which are the sum of a `symbol_ref' and an
3363 integer are stored inside a `const' RTX to mark them as constant.
3364 Therefore, there is no need to recognize such sums specifically as
3365 legitimate addresses. Normally you would simply recognize any `const' as
3368 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3369 are not marked with `const'. It assumes that a naked `plus' indicates
3370 indexing. If so, then you *must* reject such naked constant sums as
3371 illegitimate addresses, so that none of them will be given to
3372 `PRINT_OPERAND_ADDRESS'.
3374 On some machines, whether a symbolic address is legitimate depends on the
3375 section that the address refers to. On these machines, define the macro
3376 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3377 then check for it here. When you see a `const', you will have to look
3378 inside it to find the `symbol_ref' in order to determine the section.
3380 The best way to modify the name string is by adding text to the beginning,
3381 with suitable punctuation to prevent any ambiguity. Allocate the new name
3382 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3383 remove and decode the added text and output the name accordingly, and define
3384 `(* targetm.strip_name_encoding)' to access the original name string.
3386 You can check the information stored here into the `symbol_ref' in the
3387 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3388 `PRINT_OPERAND_ADDRESS'. */
3391 frv_legitimate_address_p (mode
, x
, strict_p
, condexec_p
)
3392 enum machine_mode mode
;
3399 HOST_WIDE_INT value
;
3402 switch (GET_CODE (x
))
3409 if (GET_CODE (x
) != REG
)
3415 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3421 if (GET_CODE (x0
) != REG
3422 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3423 || GET_CODE (x1
) != PLUS
3424 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3425 || GET_CODE (XEXP (x1
, 1)) != REG
3426 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3433 /* 12 bit immediate */
3438 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3440 /* If we can't use load/store double operations, make sure we can
3441 address the second word. */
3442 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3443 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3452 if (GET_CODE (x0
) == SUBREG
)
3453 x0
= SUBREG_REG (x0
);
3455 if (GET_CODE (x0
) != REG
)
3458 regno0
= REGNO (x0
);
3459 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3462 switch (GET_CODE (x1
))
3468 x1
= SUBREG_REG (x1
);
3469 if (GET_CODE (x1
) != REG
)
3475 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3476 on having move double instructions */
3477 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3480 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3484 /* 12 bit immediate */
3489 value
= INTVAL (x1
);
3490 ret
= IN_RANGE_P (value
, -2048, 2047);
3492 /* If we can't use load/store double operations, make sure we can
3493 address the second word. */
3494 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3495 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3501 && regno0
== SDA_BASE_REG
3502 && symbol_ref_small_data_p (x1
))
3507 if (!condexec_p
&& regno0
== SDA_BASE_REG
&& const_small_data_p (x1
))
3515 if (TARGET_DEBUG_ADDR
)
3517 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3518 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3519 (condexec_p
) ? ", inside conditional code" : "");
3527 /* A C compound statement that attempts to replace X with a valid memory
3528 address for an operand of mode MODE. WIN will be a C statement label
3529 elsewhere in the code; the macro definition may use
3531 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3533 to avoid further processing if the address has become legitimate.
3535 X will always be the result of a call to `break_out_memory_refs', and OLDX
3536 will be the operand that was given to that function to produce X.
3538 The code generated by this macro should not alter the substructure of X. If
3539 it transforms X into a more legitimate form, it should assign X (which will
3540 always be a C variable) a new value.
3542 It is not necessary for this macro to come up with a legitimate address.
3543 The compiler has standard ways of doing so in all cases. In fact, it is
3544 safe for this macro to do nothing. But often a machine-dependent strategy
3545 can generate better code. */
3548 frv_legitimize_address (x
, oldx
, mode
)
3550 rtx oldx ATTRIBUTE_UNUSED
;
3551 enum machine_mode mode ATTRIBUTE_UNUSED
;
3555 /* Don't try to legitimize addresses if we are not optimizing, since the
3556 address we generate is not a general operand, and will horribly mess
3557 things up when force_reg is called to try and put it in a register because
3558 we aren't optimizing. */
3560 && ((GET_CODE (x
) == SYMBOL_REF
&& symbol_ref_small_data_p (x
))
3561 || (GET_CODE (x
) == CONST
&& const_small_data_p (x
))))
3563 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, SDA_BASE_REG
), x
);
3565 cfun
->uses_pic_offset_table
= TRUE
;
3568 if (TARGET_DEBUG_ADDR
&& ret
!= NULL_RTX
)
3570 fprintf (stderr
, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3571 GET_MODE_NAME (mode
));
3578 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3579 the operand is used by a predicated instruction. */
3582 frv_legitimate_memory_operand (op
, mode
, condexec_p
)
3584 enum machine_mode mode
;
3587 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3588 && GET_CODE (op
) == MEM
3589 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3590 reload_completed
, condexec_p
));
3594 /* Return 1 is OP is a memory operand, or will be turned into one by
3597 int frv_load_operand (op
, mode
)
3599 enum machine_mode mode
;
3601 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3604 if (reload_in_progress
)
3607 if (GET_CODE (tmp
) == SUBREG
)
3608 tmp
= SUBREG_REG (tmp
);
3609 if (GET_CODE (tmp
) == REG
3610 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
3611 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
3614 return op
&& memory_operand (op
, mode
);
3618 /* Return 1 if operand is a GPR register or a FPR register. */
3620 int gpr_or_fpr_operand (op
, mode
)
3622 enum machine_mode mode
;
3626 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3629 if (GET_CODE (op
) == SUBREG
)
3631 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3632 return register_operand (op
, mode
);
3634 op
= SUBREG_REG (op
);
3637 if (GET_CODE (op
) != REG
)
3641 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3647 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3649 int gpr_or_int12_operand (op
, mode
)
3651 enum machine_mode mode
;
3653 if (GET_CODE (op
) == CONST_INT
)
3654 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3656 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3659 if (GET_CODE (op
) == SUBREG
)
3661 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3662 return register_operand (op
, mode
);
3664 op
= SUBREG_REG (op
);
3667 if (GET_CODE (op
) != REG
)
3670 return GPR_OR_PSEUDO_P (REGNO (op
));
3673 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3674 signed immediate. */
3676 int gpr_fpr_or_int12_operand (op
, mode
)
3678 enum machine_mode mode
;
3682 if (GET_CODE (op
) == CONST_INT
)
3683 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3685 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3688 if (GET_CODE (op
) == SUBREG
)
3690 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3691 return register_operand (op
, mode
);
3693 op
= SUBREG_REG (op
);
3696 if (GET_CODE (op
) != REG
)
3700 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3706 /* Return 1 if operand is a register or 6 bit signed immediate. */
3708 int fpr_or_int6_operand (op
, mode
)
3710 enum machine_mode mode
;
3712 if (GET_CODE (op
) == CONST_INT
)
3713 return IN_RANGE_P (INTVAL (op
), -32, 31);
3715 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3718 if (GET_CODE (op
) == SUBREG
)
3720 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3721 return register_operand (op
, mode
);
3723 op
= SUBREG_REG (op
);
3726 if (GET_CODE (op
) != REG
)
3729 return FPR_OR_PSEUDO_P (REGNO (op
));
3732 /* Return 1 if operand is a register or 10 bit signed immediate. */
3734 int gpr_or_int10_operand (op
, mode
)
3736 enum machine_mode mode
;
3738 if (GET_CODE (op
) == CONST_INT
)
3739 return IN_RANGE_P (INTVAL (op
), -512, 511);
3741 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3744 if (GET_CODE (op
) == SUBREG
)
3746 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3747 return register_operand (op
, mode
);
3749 op
= SUBREG_REG (op
);
3752 if (GET_CODE (op
) != REG
)
3755 return GPR_OR_PSEUDO_P (REGNO (op
));
3758 /* Return 1 if operand is a register or an integer immediate. */
3760 int gpr_or_int_operand (op
, mode
)
3762 enum machine_mode mode
;
3764 if (GET_CODE (op
) == CONST_INT
)
3767 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3770 if (GET_CODE (op
) == SUBREG
)
3772 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3773 return register_operand (op
, mode
);
3775 op
= SUBREG_REG (op
);
3778 if (GET_CODE (op
) != REG
)
3781 return GPR_OR_PSEUDO_P (REGNO (op
));
3784 /* Return 1 if operand is a 12 bit signed immediate. */
3786 int int12_operand (op
, mode
)
3788 enum machine_mode mode ATTRIBUTE_UNUSED
;
3790 if (GET_CODE (op
) != CONST_INT
)
3793 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3796 /* Return 1 if operand is a 6 bit signed immediate. */
3798 int int6_operand (op
, mode
)
3800 enum machine_mode mode ATTRIBUTE_UNUSED
;
3802 if (GET_CODE (op
) != CONST_INT
)
3805 return IN_RANGE_P (INTVAL (op
), -32, 31);
3808 /* Return 1 if operand is a 5 bit signed immediate. */
3810 int int5_operand (op
, mode
)
3812 enum machine_mode mode ATTRIBUTE_UNUSED
;
3814 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), -16, 15);
3817 /* Return 1 if operand is a 5 bit unsigned immediate. */
3819 int uint5_operand (op
, mode
)
3821 enum machine_mode mode ATTRIBUTE_UNUSED
;
3823 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 31);
3826 /* Return 1 if operand is a 4 bit unsigned immediate. */
3828 int uint4_operand (op
, mode
)
3830 enum machine_mode mode ATTRIBUTE_UNUSED
;
3832 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 15);
3835 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3837 int uint1_operand (op
, mode
)
3839 enum machine_mode mode ATTRIBUTE_UNUSED
;
3841 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 1);
3844 /* Return 1 if operand is an integer constant that takes 2 instructions
3845 to load up and can be split into sethi/setlo instructions.. */
3847 int int_2word_operand (op
, mode
)
3849 enum machine_mode mode ATTRIBUTE_UNUSED
;
3851 HOST_WIDE_INT value
;
3855 switch (GET_CODE (op
))
3861 return (flag_pic
== 0);
3864 /* small data references are already 1 word */
3865 return (flag_pic
== 0) && (! const_small_data_p (op
));
3868 /* small data references are already 1 word */
3869 return (flag_pic
== 0) && (! symbol_ref_small_data_p (op
));
3872 return ! IN_RANGE_P (INTVAL (op
), -32768, 32767);
3875 if (GET_MODE (op
) == SFmode
)
3877 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
3878 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
3880 return ! IN_RANGE_P (value
, -32768, 32767);
3882 else if (GET_MODE (op
) == VOIDmode
)
3884 value
= CONST_DOUBLE_LOW (op
);
3885 return ! IN_RANGE_P (value
, -32768, 32767);
3893 /* Return 1 if operand is the pic address register. */
3895 pic_register_operand (op
, mode
)
3897 enum machine_mode mode ATTRIBUTE_UNUSED
;
3902 if (GET_CODE (op
) != REG
)
3905 if (REGNO (op
) != PIC_REGNO
)
3911 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3912 that takes 3 seperate instructions to form. */
3914 int pic_symbolic_operand (op
, mode
)
3916 enum machine_mode mode ATTRIBUTE_UNUSED
;
3921 switch (GET_CODE (op
))
3930 /* small data references are already 1 word */
3931 return ! symbol_ref_small_data_p (op
);
3934 /* small data references are already 1 word */
3935 return ! const_small_data_p (op
);
3941 /* Return 1 if operand is the small data register. */
3943 small_data_register_operand (op
, mode
)
3945 enum machine_mode mode ATTRIBUTE_UNUSED
;
3947 if (GET_CODE (op
) != REG
)
3950 if (REGNO (op
) != SDA_BASE_REG
)
3956 /* Return 1 if operand is a symbolic reference to a small data area static or
3959 int small_data_symbolic_operand (op
, mode
)
3961 enum machine_mode mode ATTRIBUTE_UNUSED
;
3963 switch (GET_CODE (op
))
3969 return const_small_data_p (op
);
3972 return symbol_ref_small_data_p (op
);
3978 /* Return 1 if operand is a 16 bit unsigned immediate */
3980 int uint16_operand (op
, mode
)
3982 enum machine_mode mode ATTRIBUTE_UNUSED
;
3984 if (GET_CODE (op
) != CONST_INT
)
3987 return IN_RANGE_P (INTVAL (op
), 0, 0xffff);
3990 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
3992 int upper_int16_operand (op
, mode
)
3994 enum machine_mode mode ATTRIBUTE_UNUSED
;
3996 if (GET_CODE (op
) != CONST_INT
)
3999 return ((INTVAL (op
) & 0xffff) == 0);
4002 /* Return true if operand is a GPR register. */
4005 integer_register_operand (op
, mode
)
4007 enum machine_mode mode
;
4009 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4012 if (GET_CODE (op
) == SUBREG
)
4014 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4015 return register_operand (op
, mode
);
4017 op
= SUBREG_REG (op
);
4020 if (GET_CODE (op
) != REG
)
4023 return GPR_OR_PSEUDO_P (REGNO (op
));
4026 /* Return true if operand is a GPR register. Do not allow SUBREG's
4027 here, in order to prevent a combine bug. */
4030 gpr_no_subreg_operand (op
, mode
)
4032 enum machine_mode mode
;
4034 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4037 if (GET_CODE (op
) != REG
)
4040 return GPR_OR_PSEUDO_P (REGNO (op
));
4043 /* Return true if operand is a FPR register. */
4046 fpr_operand (op
, mode
)
4048 enum machine_mode mode
;
4050 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4053 if (GET_CODE (op
) == SUBREG
)
4055 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4056 return register_operand (op
, mode
);
4058 op
= SUBREG_REG (op
);
4061 if (GET_CODE (op
) != REG
)
4064 return FPR_OR_PSEUDO_P (REGNO (op
));
4067 /* Return true if operand is an even GPR or FPR register. */
4070 even_reg_operand (op
, mode
)
4072 enum machine_mode mode
;
4076 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4079 if (GET_CODE (op
) == SUBREG
)
4081 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4082 return register_operand (op
, mode
);
4084 op
= SUBREG_REG (op
);
4087 if (GET_CODE (op
) != REG
)
4091 if (regno
>= FIRST_PSEUDO_REGISTER
)
4095 return (((regno
- GPR_FIRST
) & 1) == 0);
4098 return (((regno
- FPR_FIRST
) & 1) == 0);
4103 /* Return true if operand is an odd GPR register. */
4106 odd_reg_operand (op
, mode
)
4108 enum machine_mode mode
;
4112 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4115 if (GET_CODE (op
) == SUBREG
)
4117 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4118 return register_operand (op
, mode
);
4120 op
= SUBREG_REG (op
);
4123 if (GET_CODE (op
) != REG
)
4127 /* assume that reload will give us an even register */
4128 if (regno
>= FIRST_PSEUDO_REGISTER
)
4132 return (((regno
- GPR_FIRST
) & 1) != 0);
4135 return (((regno
- FPR_FIRST
) & 1) != 0);
4140 /* Return true if operand is an even GPR register. */
4143 even_gpr_operand (op
, mode
)
4145 enum machine_mode mode
;
4149 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4152 if (GET_CODE (op
) == SUBREG
)
4154 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4155 return register_operand (op
, mode
);
4157 op
= SUBREG_REG (op
);
4160 if (GET_CODE (op
) != REG
)
4164 if (regno
>= FIRST_PSEUDO_REGISTER
)
4167 if (! GPR_P (regno
))
4170 return (((regno
- GPR_FIRST
) & 1) == 0);
4173 /* Return true if operand is an odd GPR register. */
4176 odd_gpr_operand (op
, mode
)
4178 enum machine_mode mode
;
4182 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4185 if (GET_CODE (op
) == SUBREG
)
4187 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4188 return register_operand (op
, mode
);
4190 op
= SUBREG_REG (op
);
4193 if (GET_CODE (op
) != REG
)
4197 /* assume that reload will give us an even register */
4198 if (regno
>= FIRST_PSEUDO_REGISTER
)
4201 if (! GPR_P (regno
))
4204 return (((regno
- GPR_FIRST
) & 1) != 0);
4207 /* Return true if operand is a quad aligned FPR register. */
4210 quad_fpr_operand (op
, mode
)
4212 enum machine_mode mode
;
4216 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4219 if (GET_CODE (op
) == SUBREG
)
4221 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4222 return register_operand (op
, mode
);
4224 op
= SUBREG_REG (op
);
4227 if (GET_CODE (op
) != REG
)
4231 if (regno
>= FIRST_PSEUDO_REGISTER
)
4234 if (! FPR_P (regno
))
4237 return (((regno
- FPR_FIRST
) & 3) == 0);
4240 /* Return true if operand is an even FPR register. */
4243 even_fpr_operand (op
, mode
)
4245 enum machine_mode mode
;
4249 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4252 if (GET_CODE (op
) == SUBREG
)
4254 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4255 return register_operand (op
, mode
);
4257 op
= SUBREG_REG (op
);
4260 if (GET_CODE (op
) != REG
)
4264 if (regno
>= FIRST_PSEUDO_REGISTER
)
4267 if (! FPR_P (regno
))
4270 return (((regno
- FPR_FIRST
) & 1) == 0);
4273 /* Return true if operand is an odd FPR register. */
4276 odd_fpr_operand (op
, mode
)
4278 enum machine_mode mode
;
4282 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4285 if (GET_CODE (op
) == SUBREG
)
4287 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4288 return register_operand (op
, mode
);
4290 op
= SUBREG_REG (op
);
4293 if (GET_CODE (op
) != REG
)
4297 /* assume that reload will give us an even register */
4298 if (regno
>= FIRST_PSEUDO_REGISTER
)
4301 if (! FPR_P (regno
))
4304 return (((regno
- FPR_FIRST
) & 1) != 0);
4307 /* Return true if operand is a 2 word memory address that can be loaded in one
4308 instruction to load or store. We assume the stack and frame pointers are
4309 suitably aligned, and variables in the small data area. FIXME -- at some we
4310 should recognize other globals and statics. We can't assume that any old
4311 pointer is aligned, given that arguments could be passed on an odd word on
4312 the stack and the address taken and passed through to another function. */
4315 dbl_memory_one_insn_operand (op
, mode
)
4317 enum machine_mode mode
;
4325 if (GET_CODE (op
) != MEM
)
4328 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4331 addr
= XEXP (op
, 0);
4332 if (GET_CODE (addr
) == REG
)
4335 else if (GET_CODE (addr
) == PLUS
)
4337 rtx addr0
= XEXP (addr
, 0);
4338 rtx addr1
= XEXP (addr
, 1);
4340 if (GET_CODE (addr0
) != REG
)
4343 if (plus_small_data_p (addr0
, addr1
))
4346 if (GET_CODE (addr1
) != CONST_INT
)
4349 if ((INTVAL (addr1
) & 7) != 0)
4358 if (addr_reg
== frame_pointer_rtx
|| addr_reg
== stack_pointer_rtx
)
4364 /* Return true if operand is a 2 word memory address that needs to
4365 use two instructions to load or store. */
4368 dbl_memory_two_insn_operand (op
, mode
)
4370 enum machine_mode mode
;
4372 if (GET_CODE (op
) != MEM
)
4375 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4381 return ! dbl_memory_one_insn_operand (op
, mode
);
4384 /* Return true if operand is something that can be an output for a move
4388 move_destination_operand (op
, mode
)
4390 enum machine_mode mode
;
4395 switch (GET_CODE (op
))
4401 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4404 subreg
= SUBREG_REG (op
);
4405 code
= GET_CODE (subreg
);
4407 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4408 reload_completed
, FALSE
);
4410 return (code
== REG
);
4413 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4419 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4422 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4428 /* Return true if operand is something that can be an input for a move
4432 move_source_operand (op
, mode
)
4434 enum machine_mode mode
;
4439 switch (GET_CODE (op
))
4449 return immediate_operand (op
, mode
);
4452 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4455 subreg
= SUBREG_REG (op
);
4456 code
= GET_CODE (subreg
);
4458 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4459 reload_completed
, FALSE
);
4461 return (code
== REG
);
4464 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4470 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4473 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4479 /* Return true if operand is something that can be an output for a conditional
4483 condexec_dest_operand (op
, mode
)
4485 enum machine_mode mode
;
4490 switch (GET_CODE (op
))
4496 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4499 subreg
= SUBREG_REG (op
);
4500 code
= GET_CODE (subreg
);
4502 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4503 reload_completed
, TRUE
);
4505 return (code
== REG
);
4508 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4514 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4517 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4523 /* Return true if operand is something that can be an input for a conditional
4527 condexec_source_operand (op
, mode
)
4529 enum machine_mode mode
;
4534 switch (GET_CODE (op
))
4544 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4547 subreg
= SUBREG_REG (op
);
4548 code
= GET_CODE (subreg
);
4550 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4551 reload_completed
, TRUE
);
4553 return (code
== REG
);
4556 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4562 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4565 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4571 /* Return true if operand is a register of any flavor or a 0 of the
4572 appropriate type. */
4575 reg_or_0_operand (op
, mode
)
4577 enum machine_mode mode
;
4579 switch (GET_CODE (op
))
4586 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4589 return register_operand (op
, mode
);
4599 /* Return true if operand is the link register */
4602 lr_operand (op
, mode
)
4604 enum machine_mode mode
;
4606 if (GET_CODE (op
) != REG
)
4609 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4612 if (REGNO (op
) != LR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4618 /* Return true if operand is a gpr register or a valid memory operation. */
4621 gpr_or_memory_operand (op
, mode
)
4623 enum machine_mode mode
;
4625 return (integer_register_operand (op
, mode
)
4626 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4629 /* Return true if operand is a fpr register or a valid memory operation. */
4632 fpr_or_memory_operand (op
, mode
)
4634 enum machine_mode mode
;
4636 return (fpr_operand (op
, mode
)
4637 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4640 /* Return true if operand is an icc register */
4643 icc_operand (op
, mode
)
4645 enum machine_mode mode
;
4649 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4652 if (GET_CODE (op
) != REG
)
4656 return ICC_OR_PSEUDO_P (regno
);
4659 /* Return true if operand is an fcc register */
4662 fcc_operand (op
, mode
)
4664 enum machine_mode mode
;
4668 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4671 if (GET_CODE (op
) != REG
)
4675 return FCC_OR_PSEUDO_P (regno
);
4678 /* Return true if operand is either an fcc or icc register */
4681 cc_operand (op
, mode
)
4683 enum machine_mode mode
;
4687 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4690 if (GET_CODE (op
) != REG
)
4694 if (CC_OR_PSEUDO_P (regno
))
4700 /* Return true if operand is an integer CCR register */
4703 icr_operand (op
, mode
)
4705 enum machine_mode mode
;
4709 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4712 if (GET_CODE (op
) != REG
)
4716 return ICR_OR_PSEUDO_P (regno
);
4719 /* Return true if operand is an fcc register */
4722 fcr_operand (op
, mode
)
4724 enum machine_mode mode
;
4728 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4731 if (GET_CODE (op
) != REG
)
4735 return FCR_OR_PSEUDO_P (regno
);
4738 /* Return true if operand is either an fcc or icc register */
4741 cr_operand (op
, mode
)
4743 enum machine_mode mode
;
4747 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4750 if (GET_CODE (op
) != REG
)
4754 if (CR_OR_PSEUDO_P (regno
))
4760 /* Return true if operand is a memory reference suitable for a call. */
4763 call_operand (op
, mode
)
4765 enum machine_mode mode
;
4767 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4770 if (GET_CODE (op
) == SYMBOL_REF
)
4773 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4774 never occur anyway), but prevents reload from not handling the case
4775 properly of a call through a pointer on a function that calls
4776 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4777 return gpr_or_int12_operand (op
, mode
);
4780 /* Return true if operator is an kind of relational operator */
4783 relational_operator (op
, mode
)
4785 enum machine_mode mode
;
4791 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4794 switch (GET_CODE (op
))
4813 if (op1
!= const0_rtx
)
4817 if (GET_CODE (op0
) != REG
)
4820 regno
= REGNO (op0
);
4821 switch (GET_MODE (op0
))
4828 return ICC_OR_PSEUDO_P (regno
);
4831 return FCC_OR_PSEUDO_P (regno
);
4834 return CR_OR_PSEUDO_P (regno
);
4840 /* Return true if operator is a signed integer relational operator */
4843 signed_relational_operator (op
, mode
)
4845 enum machine_mode mode
;
4851 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4854 switch (GET_CODE (op
))
4869 if (op1
!= const0_rtx
)
4873 if (GET_CODE (op0
) != REG
)
4876 regno
= REGNO (op0
);
4877 if (GET_MODE (op0
) == CCmode
&& ICC_OR_PSEUDO_P (regno
))
4880 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4886 /* Return true if operator is a signed integer relational operator */
4889 unsigned_relational_operator (op
, mode
)
4891 enum machine_mode mode
;
4897 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4900 switch (GET_CODE (op
))
4913 if (op1
!= const0_rtx
)
4917 if (GET_CODE (op0
) != REG
)
4920 regno
= REGNO (op0
);
4921 if (GET_MODE (op0
) == CC_UNSmode
&& ICC_OR_PSEUDO_P (regno
))
4924 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4930 /* Return true if operator is a floating point relational operator */
4933 float_relational_operator (op
, mode
)
4935 enum machine_mode mode
;
4941 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4944 switch (GET_CODE (op
))
4963 if (op1
!= const0_rtx
)
4967 if (GET_CODE (op0
) != REG
)
4970 regno
= REGNO (op0
);
4971 if (GET_MODE (op0
) == CC_FPmode
&& FCC_OR_PSEUDO_P (regno
))
4974 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4980 /* Return true if operator is EQ/NE of a conditional execution register. */
4983 ccr_eqne_operator (op
, mode
)
4985 enum machine_mode mode
;
4987 enum machine_mode op_mode
= GET_MODE (op
);
4992 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4995 switch (GET_CODE (op
))
5006 if (op1
!= const0_rtx
)
5010 if (GET_CODE (op0
) != REG
)
5013 regno
= REGNO (op0
);
5014 if (op_mode
== CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
5020 /* Return true if operator is a minimum or maximum operator (both signed and
5024 minmax_operator (op
, mode
)
5026 enum machine_mode mode
;
5028 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
5031 switch (GET_CODE (op
))
5043 if (! integer_register_operand (XEXP (op
, 0), mode
))
5046 if (! gpr_or_int10_operand (XEXP (op
, 1), mode
))
5052 /* Return true if operator is an integer binary operator that can executed
5053 conditionally and takes 1 cycle. */
5056 condexec_si_binary_operator (op
, mode
)
5058 enum machine_mode mode
;
5060 enum machine_mode op_mode
= GET_MODE (op
);
5062 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5065 switch (GET_CODE (op
))
5082 /* Return true if operator is an integer binary operator that can be
5083 executed conditionally by a media instruction. */
5086 condexec_si_media_operator (op
, mode
)
5088 enum machine_mode mode
;
5090 enum machine_mode op_mode
= GET_MODE (op
);
5092 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5095 switch (GET_CODE (op
))
5107 /* Return true if operator is an integer division operator that can executed
5111 condexec_si_divide_operator (op
, mode
)
5113 enum machine_mode mode
;
5115 enum machine_mode op_mode
= GET_MODE (op
);
5117 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5120 switch (GET_CODE (op
))
5131 /* Return true if operator is an integer unary operator that can executed
5135 condexec_si_unary_operator (op
, mode
)
5137 enum machine_mode mode
;
5139 enum machine_mode op_mode
= GET_MODE (op
);
5141 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5144 switch (GET_CODE (op
))
5155 /* Return true if operator is a conversion-type expression that can be
5156 evaluated conditionally by floating-point instructions. */
5159 condexec_sf_conv_operator (op
, mode
)
5161 enum machine_mode mode
;
5163 enum machine_mode op_mode
= GET_MODE (op
);
5165 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5168 switch (GET_CODE (op
))
5179 /* Return true if operator is an addition or subtraction expression.
5180 Such expressions can be evaluated conditionally by floating-point
5184 condexec_sf_add_operator (op
, mode
)
5186 enum machine_mode mode
;
5188 enum machine_mode op_mode
= GET_MODE (op
);
5190 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5193 switch (GET_CODE (op
))
5204 /* Return true if the memory operand is one that can be conditionally
5208 condexec_memory_operand (op
, mode
)
5210 enum machine_mode mode
;
5212 enum machine_mode op_mode
= GET_MODE (op
);
5215 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5230 if (GET_CODE (op
) != MEM
)
5233 addr
= XEXP (op
, 0);
5234 if (GET_CODE (addr
) == ADDRESSOF
)
5237 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
);
5240 /* Return true if operator is an integer binary operator that can be combined
5241 with a setcc operation. Do not allow the arithmetic operations that could
5242 potentially overflow since the FR-V sets the condition code based on the
5243 "true" value of the result, not the result after truncating to a 32-bit
5247 intop_compare_operator (op
, mode
)
5249 enum machine_mode mode
;
5251 enum machine_mode op_mode
= GET_MODE (op
);
5253 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5256 switch (GET_CODE (op
))
5269 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5272 if (! gpr_or_int10_operand (XEXP (op
, 1), SImode
))
5278 /* Return true if operator is an integer binary operator that can be combined
5279 with a setcc operation inside of a conditional execution. */
5282 condexec_intop_cmp_operator (op
, mode
)
5284 enum machine_mode mode
;
5286 enum machine_mode op_mode
= GET_MODE (op
);
5288 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5291 switch (GET_CODE (op
))
5304 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5307 if (! integer_register_operand (XEXP (op
, 1), SImode
))
5313 /* Return 1 if operand is a valid ACC register number */
5316 acc_operand (op
, mode
)
5318 enum machine_mode mode
;
5322 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5325 if (GET_CODE (op
) == SUBREG
)
5327 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5328 return register_operand (op
, mode
);
5330 op
= SUBREG_REG (op
);
5333 if (GET_CODE (op
) != REG
)
5337 return ACC_OR_PSEUDO_P (regno
);
5340 /* Return 1 if operand is a valid even ACC register number */
5343 even_acc_operand (op
, mode
)
5345 enum machine_mode mode
;
5349 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5352 if (GET_CODE (op
) == SUBREG
)
5354 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5355 return register_operand (op
, mode
);
5357 op
= SUBREG_REG (op
);
5360 if (GET_CODE (op
) != REG
)
5364 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 1) == 0);
5367 /* Return 1 if operand is zero or four */
5370 quad_acc_operand (op
, mode
)
5372 enum machine_mode mode
;
5376 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5379 if (GET_CODE (op
) == SUBREG
)
5381 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5382 return register_operand (op
, mode
);
5384 op
= SUBREG_REG (op
);
5387 if (GET_CODE (op
) != REG
)
5391 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 3) == 0);
5394 /* Return 1 if operand is a valid ACCG register number */
5397 accg_operand (op
, mode
)
5399 enum machine_mode mode
;
5401 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5404 if (GET_CODE (op
) == SUBREG
)
5406 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5407 return register_operand (op
, mode
);
5409 op
= SUBREG_REG (op
);
5412 if (GET_CODE (op
) != REG
)
5415 return ACCG_OR_PSEUDO_P (REGNO (op
));
5419 /* Return true if the bare return instruction can be used outside of the
5420 epilog code. For frv, we only do it if there was no stack allocation. */
5427 if (!reload_completed
)
5430 info
= frv_stack_info ();
5431 return (info
->total_size
== 0);
5435 /* Emit code to handle a MOVSI, adding in the small data register or pic
5436 register if needed to load up addresses. Return TRUE if the appropriate
5437 instructions are emitted. */
5440 frv_emit_movsi (dest
, src
)
5444 int base_regno
= -1;
5446 if (!reload_in_progress
5447 && !reload_completed
5448 && !register_operand (dest
, SImode
)
5449 && (!reg_or_0_operand (src
, SImode
)
5450 /* Virtual registers will almost always be replaced by an
5451 add instruction, so expose this to CSE by copying to
5452 an intermediate register */
5453 || (GET_CODE (src
) == REG
5454 && IN_RANGE_P (REGNO (src
),
5455 FIRST_VIRTUAL_REGISTER
,
5456 LAST_VIRTUAL_REGISTER
))))
5458 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
5462 /* Explicitly add in the PIC or small data register if needed. */
5463 switch (GET_CODE (src
))
5470 base_regno
= PIC_REGNO
;
5475 if (const_small_data_p (src
))
5476 base_regno
= SDA_BASE_REG
;
5479 base_regno
= PIC_REGNO
;
5484 if (symbol_ref_small_data_p (src
))
5485 base_regno
= SDA_BASE_REG
;
5488 base_regno
= PIC_REGNO
;
5493 if (base_regno
>= 0)
5495 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
5496 gen_rtx_PLUS (Pmode
,
5497 gen_rtx_REG (Pmode
, base_regno
),
5500 if (base_regno
== PIC_REGNO
)
5501 cfun
->uses_pic_offset_table
= TRUE
;
5510 /* Return a string to output a single word move. */
5513 output_move_single (operands
, insn
)
5517 rtx dest
= operands
[0];
5518 rtx src
= operands
[1];
5520 if (GET_CODE (dest
) == REG
)
5522 int dest_regno
= REGNO (dest
);
5523 enum machine_mode mode
= GET_MODE (dest
);
5525 if (GPR_P (dest_regno
))
5527 if (GET_CODE (src
) == REG
)
5529 /* gpr <- some sort of register */
5530 int src_regno
= REGNO (src
);
5532 if (GPR_P (src_regno
))
5533 return "mov %1, %0";
5535 else if (FPR_P (src_regno
))
5536 return "movfg %1, %0";
5538 else if (SPR_P (src_regno
))
5539 return "movsg %1, %0";
5542 else if (GET_CODE (src
) == MEM
)
5551 return "ldsb%I1%U1 %M1,%0";
5554 return "ldsh%I1%U1 %M1,%0";
5558 return "ld%I1%U1 %M1, %0";
5562 else if (GET_CODE (src
) == CONST_INT
5563 || GET_CODE (src
) == CONST_DOUBLE
)
5565 /* gpr <- integer/floating constant */
5566 HOST_WIDE_INT value
;
5568 if (GET_CODE (src
) == CONST_INT
)
5569 value
= INTVAL (src
);
5571 else if (mode
== SFmode
)
5576 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
5577 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5582 value
= CONST_DOUBLE_LOW (src
);
5584 if (IN_RANGE_P (value
, -32768, 32767))
5585 return "setlos %1, %0";
5590 else if (GET_CODE (src
) == SYMBOL_REF
5591 || GET_CODE (src
) == LABEL_REF
5592 || GET_CODE (src
) == CONST
)
5594 /* Silently fix up instances where the small data pointer is not
5595 used in the address. */
5596 if (small_data_symbolic_operand (src
, GET_MODE (src
)))
5597 return "addi %@, #gprel12(%1), %0";
5603 else if (FPR_P (dest_regno
))
5605 if (GET_CODE (src
) == REG
)
5607 /* fpr <- some sort of register */
5608 int src_regno
= REGNO (src
);
5610 if (GPR_P (src_regno
))
5611 return "movgf %1, %0";
5613 else if (FPR_P (src_regno
))
5615 if (TARGET_HARD_FLOAT
)
5616 return "fmovs %1, %0";
5618 return "mor %1, %1, %0";
5622 else if (GET_CODE (src
) == MEM
)
5631 return "ldbf%I1%U1 %M1,%0";
5634 return "ldhf%I1%U1 %M1,%0";
5638 return "ldf%I1%U1 %M1, %0";
5642 else if (ZERO_P (src
))
5643 return "movgf %., %0";
5646 else if (SPR_P (dest_regno
))
5648 if (GET_CODE (src
) == REG
)
5650 /* spr <- some sort of register */
5651 int src_regno
= REGNO (src
);
5653 if (GPR_P (src_regno
))
5654 return "movgs %1, %0";
5659 else if (GET_CODE (dest
) == MEM
)
5661 if (GET_CODE (src
) == REG
)
5663 int src_regno
= REGNO (src
);
5664 enum machine_mode mode
= GET_MODE (dest
);
5666 if (GPR_P (src_regno
))
5674 return "stb%I0%U0 %1, %M0";
5677 return "sth%I0%U0 %1, %M0";
5681 return "st%I0%U0 %1, %M0";
5685 else if (FPR_P (src_regno
))
5693 return "stbf%I0%U0 %1, %M0";
5696 return "sthf%I0%U0 %1, %M0";
5700 return "stf%I0%U0 %1, %M0";
5705 else if (ZERO_P (src
))
5707 switch (GET_MODE (dest
))
5713 return "stb%I0%U0 %., %M0";
5716 return "sth%I0%U0 %., %M0";
5720 return "st%I0%U0 %., %M0";
5725 fatal_insn ("Bad output_move_single operand", insn
);
5730 /* Return a string to output a double word move. */
5733 output_move_double (operands
, insn
)
5737 rtx dest
= operands
[0];
5738 rtx src
= operands
[1];
5739 enum machine_mode mode
= GET_MODE (dest
);
5741 if (GET_CODE (dest
) == REG
)
5743 int dest_regno
= REGNO (dest
);
5745 if (GPR_P (dest_regno
))
5747 if (GET_CODE (src
) == REG
)
5749 /* gpr <- some sort of register */
5750 int src_regno
= REGNO (src
);
5752 if (GPR_P (src_regno
))
5755 else if (FPR_P (src_regno
))
5757 if (((dest_regno
- GPR_FIRST
) & 1) == 0
5758 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5759 return "movfgd %1, %0";
5765 else if (GET_CODE (src
) == MEM
)
5768 if (dbl_memory_one_insn_operand (src
, mode
))
5769 return "ldd%I1%U1 %M1, %0";
5774 else if (GET_CODE (src
) == CONST_INT
5775 || GET_CODE (src
) == CONST_DOUBLE
)
5779 else if (FPR_P (dest_regno
))
5781 if (GET_CODE (src
) == REG
)
5783 /* fpr <- some sort of register */
5784 int src_regno
= REGNO (src
);
5786 if (GPR_P (src_regno
))
5788 if (((dest_regno
- FPR_FIRST
) & 1) == 0
5789 && ((src_regno
- GPR_FIRST
) & 1) == 0)
5790 return "movgfd %1, %0";
5795 else if (FPR_P (src_regno
))
5798 && ((dest_regno
- FPR_FIRST
) & 1) == 0
5799 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5800 return "fmovd %1, %0";
5806 else if (GET_CODE (src
) == MEM
)
5809 if (dbl_memory_one_insn_operand (src
, mode
))
5810 return "lddf%I1%U1 %M1, %0";
5815 else if (ZERO_P (src
))
5820 else if (GET_CODE (dest
) == MEM
)
5822 if (GET_CODE (src
) == REG
)
5824 int src_regno
= REGNO (src
);
5826 if (GPR_P (src_regno
))
5828 if (((src_regno
- GPR_FIRST
) & 1) == 0
5829 && dbl_memory_one_insn_operand (dest
, mode
))
5830 return "std%I0%U0 %1, %M0";
5835 if (FPR_P (src_regno
))
5837 if (((src_regno
- FPR_FIRST
) & 1) == 0
5838 && dbl_memory_one_insn_operand (dest
, mode
))
5839 return "stdf%I0%U0 %1, %M0";
5845 else if (ZERO_P (src
))
5847 if (dbl_memory_one_insn_operand (dest
, mode
))
5848 return "std%I0%U0 %., %M0";
5854 fatal_insn ("Bad output_move_double operand", insn
);
5859 /* Return a string to output a single word conditional move.
5860 Operand0 -- EQ/NE of ccr register and 0
5861 Operand1 -- CCR register
5862 Operand2 -- destination
5863 Operand3 -- source */
5866 output_condmove_single (operands
, insn
)
5870 rtx dest
= operands
[2];
5871 rtx src
= operands
[3];
5873 if (GET_CODE (dest
) == REG
)
5875 int dest_regno
= REGNO (dest
);
5876 enum machine_mode mode
= GET_MODE (dest
);
5878 if (GPR_P (dest_regno
))
5880 if (GET_CODE (src
) == REG
)
5882 /* gpr <- some sort of register */
5883 int src_regno
= REGNO (src
);
5885 if (GPR_P (src_regno
))
5886 return "cmov %z3, %2, %1, %e0";
5888 else if (FPR_P (src_regno
))
5889 return "cmovfg %3, %2, %1, %e0";
5892 else if (GET_CODE (src
) == MEM
)
5901 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5904 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5908 return "cld%I3%U3 %M3, %2, %1, %e0";
5912 else if (ZERO_P (src
))
5913 return "cmov %., %2, %1, %e0";
5916 else if (FPR_P (dest_regno
))
5918 if (GET_CODE (src
) == REG
)
5920 /* fpr <- some sort of register */
5921 int src_regno
= REGNO (src
);
5923 if (GPR_P (src_regno
))
5924 return "cmovgf %3, %2, %1, %e0";
5926 else if (FPR_P (src_regno
))
5928 if (TARGET_HARD_FLOAT
)
5929 return "cfmovs %3,%2,%1,%e0";
5931 return "cmor %3, %3, %2, %1, %e0";
5935 else if (GET_CODE (src
) == MEM
)
5938 if (mode
== SImode
|| mode
== SFmode
)
5939 return "cldf%I3%U3 %M3, %2, %1, %e0";
5942 else if (ZERO_P (src
))
5943 return "cmovgf %., %2, %1, %e0";
5947 else if (GET_CODE (dest
) == MEM
)
5949 if (GET_CODE (src
) == REG
)
5951 int src_regno
= REGNO (src
);
5952 enum machine_mode mode
= GET_MODE (dest
);
5954 if (GPR_P (src_regno
))
5962 return "cstb%I2%U2 %3, %M2, %1, %e0";
5965 return "csth%I2%U2 %3, %M2, %1, %e0";
5969 return "cst%I2%U2 %3, %M2, %1, %e0";
5973 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
5974 return "cstf%I2%U2 %3, %M2, %1, %e0";
5977 else if (ZERO_P (src
))
5979 enum machine_mode mode
= GET_MODE (dest
);
5986 return "cstb%I2%U2 %., %M2, %1, %e0";
5989 return "csth%I2%U2 %., %M2, %1, %e0";
5993 return "cst%I2%U2 %., %M2, %1, %e0";
5998 fatal_insn ("Bad output_condmove_single operand", insn
);
6003 /* Emit the appropriate code to do a comparison, returning the register the
6004 comparison was done it. */
6007 frv_emit_comparison (test
, op0
, op1
)
6012 enum machine_mode cc_mode
;
6015 /* Floating point doesn't have comparison against a constant */
6016 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
6017 op1
= force_reg (GET_MODE (op0
), op1
);
6019 /* Possibly disable using anything but a fixed register in order to work
6020 around cse moving comparisons past function calls. */
6021 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
6022 cc_reg
= ((TARGET_ALLOC_CC
)
6023 ? gen_reg_rtx (cc_mode
)
6024 : gen_rtx_REG (cc_mode
,
6025 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
6027 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6028 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
6034 /* Emit code for a conditional branch. The comparison operands were previously
6035 stored in frv_compare_op0 and frv_compare_op1.
6037 XXX: I originally wanted to add a clobber of a CCR register to use in
6038 conditional execution, but that confuses the rest of the compiler. */
6041 frv_emit_cond_branch (test
, label
)
6048 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6049 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6051 /* Branches generate:
6053 (if_then_else (<test>, <cc_reg>, (const_int 0))
6054 (label_ref <branch_label>)
6056 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
6057 test_rtx
= gen_rtx (test
, cc_mode
, cc_reg
, const0_rtx
);
6058 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
6059 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
6064 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
6065 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
6068 frv_emit_scc (test
, target
)
6076 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6078 /* SCC instructions generate:
6079 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6080 (clobber (<ccr_reg>))]) */
6081 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
6082 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
6084 cr_reg
= ((TARGET_ALLOC_CC
)
6085 ? gen_reg_rtx (CC_CCRmode
)
6086 : gen_rtx_REG (CC_CCRmode
,
6087 ((GET_MODE (cc_reg
) == CC_FPmode
)
6091 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6092 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
6097 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6098 the seperate insns. */
6101 frv_split_scc (dest
, test
, cc_reg
, cr_reg
, value
)
6106 HOST_WIDE_INT value
;
6112 /* Set the appropriate CCR bit. */
6113 emit_insn (gen_rtx_SET (VOIDmode
,
6115 gen_rtx_fmt_ee (GET_CODE (test
),
6120 /* Move the value into the destination. */
6121 emit_move_insn (dest
, GEN_INT (value
));
6123 /* Move 0 into the destination if the test failed */
6124 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6125 gen_rtx_EQ (GET_MODE (cr_reg
),
6128 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
6130 /* Finish up, return sequence. */
6137 /* Emit the code for a conditional move, return TRUE if we could do the
6141 frv_emit_cond_move (dest
, test_rtx
, src1
, src2
)
6152 enum rtx_code test
= GET_CODE (test_rtx
);
6153 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
6154 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
6156 /* Conditional move instructions generate:
6157 (parallel [(set <target>
6158 (if_then_else (<test> <cc_reg> (const_int 0))
6161 (clobber (<ccr_reg>))]) */
6163 /* Handle various cases of conditional move involving two constants. */
6164 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6166 HOST_WIDE_INT value1
= INTVAL (src1
);
6167 HOST_WIDE_INT value2
= INTVAL (src2
);
6169 /* having 0 as one of the constants can be done by loading the other
6170 constant, and optionally moving in gr0. */
6171 if (value1
== 0 || value2
== 0)
6174 /* If the first value is within an addi range and also the difference
6175 between the two fits in an addi's range, load up the difference, then
6176 conditionally move in 0, and then unconditionally add the first
6178 else if (IN_RANGE_P (value1
, -2048, 2047)
6179 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6182 /* If neither condition holds, just force the constant into a
6186 src1
= force_reg (GET_MODE (dest
), src1
);
6187 src2
= force_reg (GET_MODE (dest
), src2
);
6191 /* If one value is a register, insure the other value is either 0 or a
6195 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
6196 src1
= force_reg (GET_MODE (dest
), src1
);
6198 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6199 src2
= force_reg (GET_MODE (dest
), src2
);
6202 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
6203 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
6205 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
6207 cr_reg
= ((TARGET_ALLOC_CC
)
6208 ? gen_reg_rtx (CC_CCRmode
)
6209 : gen_rtx_REG (CC_CCRmode
,
6210 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
6212 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
6213 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
6218 /* Split a conditonal move into constituent parts, returning a SEQUENCE
6219 containing all of the insns. */
6222 frv_split_cond_move (operands
)
6225 rtx dest
= operands
[0];
6226 rtx test
= operands
[1];
6227 rtx cc_reg
= operands
[2];
6228 rtx src1
= operands
[3];
6229 rtx src2
= operands
[4];
6230 rtx cr_reg
= operands
[5];
6232 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6236 /* Set the appropriate CCR bit. */
6237 emit_insn (gen_rtx_SET (VOIDmode
,
6239 gen_rtx_fmt_ee (GET_CODE (test
),
6244 /* Handle various cases of conditional move involving two constants. */
6245 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
6247 HOST_WIDE_INT value1
= INTVAL (src1
);
6248 HOST_WIDE_INT value2
= INTVAL (src2
);
6250 /* having 0 as one of the constants can be done by loading the other
6251 constant, and optionally moving in gr0. */
6254 emit_move_insn (dest
, src2
);
6255 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6256 gen_rtx_NE (cr_mode
, cr_reg
,
6258 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6261 else if (value2
== 0)
6263 emit_move_insn (dest
, src1
);
6264 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6265 gen_rtx_EQ (cr_mode
, cr_reg
,
6267 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6270 /* If the first value is within an addi range and also the difference
6271 between the two fits in an addi's range, load up the difference, then
6272 conditionally move in 0, and then unconditionally add the first
6274 else if (IN_RANGE_P (value1
, -2048, 2047)
6275 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6277 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
6279 : gen_rtx_SUBREG (SImode
, dest
, 0));
6281 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
6282 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6283 gen_rtx_NE (cr_mode
, cr_reg
,
6285 gen_rtx_SET (VOIDmode
, dest_si
,
6287 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
6295 /* Emit the conditional move for the test being true if needed. */
6296 if (! rtx_equal_p (dest
, src1
))
6297 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6298 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6299 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6301 /* Emit the conditional move for the test being false if needed. */
6302 if (! rtx_equal_p (dest
, src2
))
6303 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6304 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6305 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6308 /* Finish up, return sequence. */
6315 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6316 memory location that is not known to be dword-aligned. */
6318 frv_split_double_load (dest
, source
)
6322 int regno
= REGNO (dest
);
6323 rtx dest1
= gen_highpart (SImode
, dest
);
6324 rtx dest2
= gen_lowpart (SImode
, dest
);
6325 rtx address
= XEXP (source
, 0);
6327 /* If the address is pre-modified, load the lower-numbered register
6328 first, then load the other register using an integer offset from
6329 the modified base register. This order should always be safe,
6330 since the pre-modification cannot affect the same registers as the
6333 The situation for other loads is more complicated. Loading one
6334 of the registers could affect the value of ADDRESS, so we must
6335 be careful which order we do them in. */
6336 if (GET_CODE (address
) == PRE_MODIFY
6337 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
6339 /* It is safe to load the lower-numbered register first. */
6340 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6341 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6345 /* ADDRESS is not pre-modified and the address depends on the
6346 lower-numbered register. Load the higher-numbered register
6348 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6349 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6353 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6354 and SOURCE is either a double register or the constant zero. */
6356 frv_split_double_store (dest
, source
)
6360 rtx dest1
= change_address (dest
, SImode
, NULL
);
6361 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
6362 if (ZERO_P (source
))
6364 emit_move_insn (dest1
, CONST0_RTX (SImode
));
6365 emit_move_insn (dest2
, CONST0_RTX (SImode
));
6369 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
6370 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
6375 /* Split a min/max operation returning a SEQUENCE containing all of the
6379 frv_split_minmax (operands
)
6382 rtx dest
= operands
[0];
6383 rtx minmax
= operands
[1];
6384 rtx src1
= operands
[2];
6385 rtx src2
= operands
[3];
6386 rtx cc_reg
= operands
[4];
6387 rtx cr_reg
= operands
[5];
6389 enum rtx_code test_code
;
6390 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6394 /* Figure out which test to use */
6395 switch (GET_CODE (minmax
))
6400 case SMIN
: test_code
= LT
; break;
6401 case SMAX
: test_code
= GT
; break;
6402 case UMIN
: test_code
= LTU
; break;
6403 case UMAX
: test_code
= GTU
; break;
6406 /* Issue the compare instruction. */
6407 emit_insn (gen_rtx_SET (VOIDmode
,
6409 gen_rtx_COMPARE (GET_MODE (cc_reg
),
6412 /* Set the appropriate CCR bit. */
6413 emit_insn (gen_rtx_SET (VOIDmode
,
6415 gen_rtx_fmt_ee (test_code
,
6420 /* If are taking the min/max of a nonzero constant, load that first, and
6421 then do a conditional move of the other value. */
6422 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6424 if (rtx_equal_p (dest
, src1
))
6427 emit_move_insn (dest
, src2
);
6428 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6429 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6430 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6433 /* Otherwise, do each half of the move. */
6436 /* Emit the conditional move for the test being true if needed. */
6437 if (! rtx_equal_p (dest
, src1
))
6438 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6439 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6440 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6442 /* Emit the conditional move for the test being false if needed. */
6443 if (! rtx_equal_p (dest
, src2
))
6444 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6445 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6446 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6449 /* Finish up, return sequence. */
6456 /* Split an integer abs operation returning a SEQUENCE containing all of the
6460 frv_split_abs (operands
)
6463 rtx dest
= operands
[0];
6464 rtx src
= operands
[1];
6465 rtx cc_reg
= operands
[2];
6466 rtx cr_reg
= operands
[3];
6471 /* Issue the compare < 0 instruction. */
6472 emit_insn (gen_rtx_SET (VOIDmode
,
6474 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
6476 /* Set the appropriate CCR bit. */
6477 emit_insn (gen_rtx_SET (VOIDmode
,
6479 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
6481 /* Emit the conditional negate if the value is negative */
6482 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6483 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
6484 gen_negsi2 (dest
, src
)));
6486 /* Emit the conditional move for the test being false if needed. */
6487 if (! rtx_equal_p (dest
, src
))
6488 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6489 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
6490 gen_rtx_SET (VOIDmode
, dest
, src
)));
6492 /* Finish up, return sequence. */
6499 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6500 register used in an insn. */
6503 frv_clear_registers_used (ptr
, data
)
6507 if (GET_CODE (*ptr
) == REG
)
6509 int regno
= REGNO (*ptr
);
6510 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
6512 if (regno
< FIRST_PSEUDO_REGISTER
)
6514 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
6516 while (regno
< reg_max
)
6518 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
6528 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6530 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6531 initialize the static storage. */
6533 frv_ifcvt_init_extra_fields (ce_info
)
6534 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
6536 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6537 frv_ifcvt
.cur_scratch_regs
= 0;
6538 frv_ifcvt
.num_nested_cond_exec
= 0;
6539 frv_ifcvt
.cr_reg
= NULL_RTX
;
6540 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
6541 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
6542 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
6543 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6547 /* Internal function to add a potenial insn to the list of insns to be inserted
6548 if the conditional execution conversion is successful. */
6551 frv_ifcvt_add_insn (pattern
, insn
, before_p
)
6556 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
6558 link
->jump
= before_p
; /* mark to add this before or after insn */
6559 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
6560 frv_ifcvt
.added_insns_list
);
6562 if (TARGET_DEBUG_COND_EXEC
)
6565 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6566 (before_p
) ? "before" : "after",
6567 (int)INSN_UID (insn
));
6569 debug_rtx (pattern
);
6574 /* A C expression to modify the code described by the conditional if
6575 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6576 FALSE_EXPR for converting if-then and if-then-else code to conditional
6577 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6578 tests cannot be converted. */
6581 frv_ifcvt_modify_tests (ce_info
, p_true
, p_false
)
6582 ce_if_block_t
*ce_info
;
6586 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
6587 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
6588 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
6589 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
6590 rtx true_expr
= *p_true
;
6594 enum machine_mode mode
= GET_MODE (true_expr
);
6598 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
6600 rtx sub_cond_exec_reg
;
6602 enum rtx_code code_true
;
6603 enum rtx_code code_false
;
6604 enum reg_class cc_class
;
6605 enum reg_class cr_class
;
6609 /* Make sure we are only dealing with hard registers. Also honor the
6610 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6612 if (!reload_completed
|| TARGET_NO_COND_EXEC
6613 || (TARGET_NO_NESTED_CE
&& ce_info
->pass
> 1))
6616 /* Figure out which registers we can allocate for our own purposes. Only
6617 consider registers that are not preserved across function calls and are
6618 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6619 if we did not need to use them in reloading other registers. */
6620 memset ((PTR
) &tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
6621 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
6622 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
6623 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
6624 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
6626 /* If this is a nested IF, we need to discover whether the CC registers that
6627 are set/used inside of the block are used anywhere else. If not, we can
6628 change them to be the CC register that is paired with the CR register that
6629 controls the outermost IF block. */
6630 if (ce_info
->pass
> 1)
6632 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
6633 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6634 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6636 if (REGNO_REG_SET_P (then_bb
->global_live_at_start
, j
))
6639 if (else_bb
&& REGNO_REG_SET_P (else_bb
->global_live_at_start
, j
))
6642 if (join_bb
&& REGNO_REG_SET_P (join_bb
->global_live_at_start
, j
))
6645 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
6649 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
6650 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
6652 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6653 frv_ifcvt
.cur_scratch_regs
= 0;
6655 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
6656 * sizeof (basic_block
));
6662 /* Remove anything live at the beginning of the join block from being
6663 available for allocation. */
6664 EXECUTE_IF_SET_IN_REG_SET (join_bb
->global_live_at_start
, 0, regno
,
6666 if (regno
< FIRST_PSEUDO_REGISTER
)
6667 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6671 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6673 if (ce_info
->num_multiple_test_blocks
)
6675 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
6677 while (multiple_test_bb
!= test_bb
)
6679 bb
[num_bb
++] = multiple_test_bb
;
6680 multiple_test_bb
= multiple_test_bb
->pred
->src
;
6684 /* Add in the THEN and ELSE blocks to be scanned. */
6685 bb
[num_bb
++] = then_bb
;
6687 bb
[num_bb
++] = else_bb
;
6689 sub_cond_exec_reg
= NULL_RTX
;
6690 frv_ifcvt
.num_nested_cond_exec
= 0;
6692 /* Scan all of the blocks for registers that must not be allocated. */
6693 for (j
= 0; j
< num_bb
; j
++)
6695 rtx last_insn
= bb
[j
]->end
;
6696 rtx insn
= bb
[j
]->head
;
6700 fprintf (rtl_dump_file
, "Scanning %s block %d, start %d, end %d\n",
6701 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
6703 (int) INSN_UID (bb
[j
]->head
),
6704 (int) INSN_UID (bb
[j
]->end
));
6706 /* Anything live at the beginning of the block is obviously unavailable
6708 EXECUTE_IF_SET_IN_REG_SET (bb
[j
]->global_live_at_start
, 0, regno
,
6710 if (regno
< FIRST_PSEUDO_REGISTER
)
6711 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6714 /* loop through the insns in the block. */
6717 /* Mark any new registers that are created as being unavailable for
6718 allocation. Also see if the CC register used in nested IFs can be
6724 int skip_nested_if
= FALSE
;
6726 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6727 (void *)&tmp_reg
->regs
);
6729 pattern
= PATTERN (insn
);
6730 if (GET_CODE (pattern
) == COND_EXEC
)
6732 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
6734 if (reg
!= sub_cond_exec_reg
)
6736 sub_cond_exec_reg
= reg
;
6737 frv_ifcvt
.num_nested_cond_exec
++;
6741 set
= single_set_pattern (pattern
);
6744 rtx dest
= SET_DEST (set
);
6745 rtx src
= SET_SRC (set
);
6747 if (GET_CODE (dest
) == REG
)
6749 int regno
= REGNO (dest
);
6750 enum rtx_code src_code
= GET_CODE (src
);
6752 if (CC_P (regno
) && src_code
== COMPARE
)
6753 skip_nested_if
= TRUE
;
6755 else if (CR_P (regno
)
6756 && (src_code
== IF_THEN_ELSE
6757 || GET_RTX_CLASS (src_code
) == '<'))
6758 skip_nested_if
= TRUE
;
6762 if (! skip_nested_if
)
6763 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6764 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
6767 if (insn
== last_insn
)
6770 insn
= NEXT_INSN (insn
);
6774 /* If this is a nested if, rewrite the CC registers that are available to
6775 include the ones that can be rewritten, to increase the chance of being
6776 able to allocate a paired CC/CR register combination. */
6777 if (ce_info
->pass
> 1)
6779 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6780 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
6781 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
6783 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
6789 fprintf (rtl_dump_file
, "Available GPRs: ");
6791 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
6792 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6794 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6795 if (++num_gprs
> GPR_TEMP_NUM
+2)
6799 fprintf (rtl_dump_file
, "%s\nAvailable CRs: ",
6800 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
6802 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
6803 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6804 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6806 fputs ("\n", rtl_dump_file
);
6808 if (ce_info
->pass
> 1)
6810 fprintf (rtl_dump_file
, "Modifiable CCs: ");
6811 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6812 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6813 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6815 fprintf (rtl_dump_file
, "\n%d nested COND_EXEC statements\n",
6816 frv_ifcvt
.num_nested_cond_exec
);
6820 /* Allocate the appropriate temporary condition code register. Try to
6821 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6822 that conditional cmp's can be done. */
6823 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6825 cr_class
= ICR_REGS
;
6826 cc_class
= ICC_REGS
;
6827 cc_first
= ICC_FIRST
;
6830 else if (mode
== CC_FPmode
)
6832 cr_class
= FCR_REGS
;
6833 cc_class
= FCC_REGS
;
6834 cc_first
= FCC_FIRST
;
6839 cc_first
= cc_last
= 0;
6840 cr_class
= cc_class
= NO_REGS
;
6843 cc
= XEXP (true_expr
, 0);
6844 nested_cc
= cr
= NULL_RTX
;
6845 if (cc_class
!= NO_REGS
)
6847 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6848 so we can execute a csubcc/caddcc/cfcmps instruction. */
6851 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
6853 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
6855 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
6856 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
6858 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
6859 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
6862 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
6863 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
6873 fprintf (rtl_dump_file
, "Could not allocate a CR temporary register\n");
6879 fprintf (rtl_dump_file
,
6880 "Will use %s for conditional execution, %s for nested comparisons\n",
6881 reg_names
[ REGNO (cr
)],
6882 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
6884 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6885 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6886 bit being true. We don't do this for floating point, because of NaNs. */
6887 code
= GET_CODE (true_expr
);
6888 if (GET_MODE (cc
) != CC_FPmode
)
6890 code
= reverse_condition (code
);
6900 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
6901 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
6903 /* Record the check insn to be inserted later. */
6904 frv_ifcvt_add_insn (check_insn
, test_bb
->end
, TRUE
);
6906 /* Update the tests. */
6907 frv_ifcvt
.cr_reg
= cr
;
6908 frv_ifcvt
.nested_cc_reg
= nested_cc
;
6909 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
6910 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
6913 /* Fail, don't do this conditional execution. */
6916 *p_false
= NULL_RTX
;
6918 fprintf (rtl_dump_file
, "Disabling this conditional execution.\n");
6924 /* A C expression to modify the code described by the conditional if
6925 information CE_INFO, for the basic block BB, possibly updating the tests in
6926 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6927 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6928 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6930 /* p_true and p_false are given expressions of the form:
6932 (and (eq:CC_CCR (reg:CC_CCR)
6938 frv_ifcvt_modify_multiple_tests (ce_info
, bb
, p_true
, p_false
)
6939 ce_if_block_t
*ce_info
;
6944 rtx old_true
= XEXP (*p_true
, 0);
6945 rtx old_false
= XEXP (*p_false
, 0);
6946 rtx true_expr
= XEXP (*p_true
, 1);
6947 rtx false_expr
= XEXP (*p_false
, 1);
6950 rtx cr
= XEXP (old_true
, 0);
6952 rtx new_cr
= NULL_RTX
;
6953 rtx
*p_new_cr
= (rtx
*)0;
6957 enum reg_class cr_class
;
6958 enum machine_mode mode
= GET_MODE (true_expr
);
6959 rtx (*logical_func
)(rtx
, rtx
, rtx
);
6961 if (TARGET_DEBUG_COND_EXEC
)
6964 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6965 ce_info
->and_and_p
? "&&" : "||");
6967 debug_rtx (*p_true
);
6969 fputs ("\nfalse insn:\n", stderr
);
6970 debug_rtx (*p_false
);
6973 if (TARGET_NO_MULTI_CE
)
6976 if (GET_CODE (cr
) != REG
)
6979 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6981 cr_class
= ICR_REGS
;
6982 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
6984 else if (mode
== CC_FPmode
)
6986 cr_class
= FCR_REGS
;
6987 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
6992 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6993 more &&/|| tests. */
6997 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
6998 CC_CCRmode
, TRUE
, TRUE
);
7003 if (ce_info
->and_and_p
)
7005 old_test
= old_false
;
7006 test_expr
= true_expr
;
7007 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
7008 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7009 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7013 old_test
= old_false
;
7014 test_expr
= false_expr
;
7015 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
7016 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
7017 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
7020 /* First add the andcr/andncr/orcr/orncr, which will be added after the
7021 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
7023 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), bb
->end
, TRUE
);
7025 /* Now add the conditional check insn. */
7026 cc
= XEXP (test_expr
, 0);
7027 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
7028 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
7030 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
7032 /* add the new check insn to the list of check insns that need to be
7034 frv_ifcvt_add_insn (check_insn
, bb
->end
, TRUE
);
7036 if (TARGET_DEBUG_COND_EXEC
)
7038 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
7041 debug_rtx (*p_true
);
7043 fputs ("\nfalse insn:\n", stderr
);
7044 debug_rtx (*p_false
);
7050 *p_true
= *p_false
= NULL_RTX
;
7052 /* If we allocated a CR register, release it. */
7055 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
7056 *p_new_cr
= NULL_RTX
;
7059 if (TARGET_DEBUG_COND_EXEC
)
7060 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
7066 /* Return a register which will be loaded with a value if an IF block is
7067 converted to conditional execution. This is used to rewrite instructions
7068 that use constants to ones that just use registers. */
7071 frv_ifcvt_load_value (value
, insn
)
7073 rtx insn ATTRIBUTE_UNUSED
;
7075 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
7079 /* We know gr0 == 0, so replace any errant uses. */
7080 if (value
== const0_rtx
)
7081 return gen_rtx_REG (SImode
, GPR_FIRST
);
7083 /* First search all registers currently loaded to see if we have an
7084 applicable constant. */
7085 if (CONSTANT_P (value
)
7086 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
7088 for (i
= 0; i
< num_alloc
; i
++)
7090 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
7091 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
7095 /* Have we exhausted the number of registers available? */
7096 if (num_alloc
>= GPR_TEMP_NUM
)
7099 fprintf (rtl_dump_file
, "Too many temporary registers allocated\n");
7104 /* Allocate the new register. */
7105 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
7109 fputs ("Could not find a scratch register\n", rtl_dump_file
);
7114 frv_ifcvt
.cur_scratch_regs
++;
7115 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
7119 if (GET_CODE (value
) == CONST_INT
)
7120 fprintf (rtl_dump_file
, "Register %s will hold %ld\n",
7121 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
7123 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
7124 fprintf (rtl_dump_file
, "Register %s will hold LR\n",
7125 reg_names
[ REGNO (reg
)]);
7128 fprintf (rtl_dump_file
, "Register %s will hold a saved value\n",
7129 reg_names
[ REGNO (reg
)]);
7136 /* Update a MEM used in conditional code that might contain an offset to put
7137 the offset into a scratch register, so that the conditional load/store
7138 operations can be used. This function returns the original pointer if the
7139 MEM is valid to use in conditional code, NULL if we can't load up the offset
7140 into a temporary register, or the new MEM if we were successful. */
7143 frv_ifcvt_rewrite_mem (mem
, mode
, insn
)
7145 enum machine_mode mode
;
7148 rtx addr
= XEXP (mem
, 0);
7150 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
))
7152 if (GET_CODE (addr
) == PLUS
)
7154 rtx addr_op0
= XEXP (addr
, 0);
7155 rtx addr_op1
= XEXP (addr
, 1);
7157 if (plus_small_data_p (addr_op0
, addr_op1
))
7158 addr
= frv_ifcvt_load_value (addr
, insn
);
7160 else if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
7162 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
7166 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
7173 else if (CONSTANT_P (addr
))
7174 addr
= frv_ifcvt_load_value (addr
, insn
);
7179 if (addr
== NULL_RTX
)
7182 else if (XEXP (mem
, 0) != addr
)
7183 return change_address (mem
, mode
, addr
);
7190 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7191 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7194 single_set_pattern (pattern
)
7200 if (GET_CODE (pattern
) == COND_EXEC
)
7201 pattern
= COND_EXEC_CODE (pattern
);
7203 if (GET_CODE (pattern
) == SET
)
7206 else if (GET_CODE (pattern
) == PARALLEL
)
7208 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
7210 rtx sub
= XVECEXP (pattern
, 0, i
);
7212 switch (GET_CODE (sub
))
7236 /* A C expression to modify the code described by the conditional if
7237 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7238 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7239 insn cannot be converted to be executed conditionally. */
7242 frv_ifcvt_modify_insn (ce_info
, pattern
, insn
)
7243 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7247 rtx orig_ce_pattern
= pattern
;
7253 if (GET_CODE (pattern
) != COND_EXEC
)
7256 test
= COND_EXEC_TEST (pattern
);
7257 if (GET_CODE (test
) == AND
)
7259 rtx cr
= frv_ifcvt
.cr_reg
;
7262 op0
= XEXP (test
, 0);
7263 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
7266 op1
= XEXP (test
, 1);
7267 test_reg
= XEXP (op1
, 0);
7268 if (GET_CODE (test_reg
) != REG
)
7271 /* Is this the first nested if block in this sequence? If so, generate
7272 an andcr or andncr. */
7273 if (! frv_ifcvt
.last_nested_if_cr
)
7277 frv_ifcvt
.last_nested_if_cr
= test_reg
;
7278 if (GET_CODE (op0
) == NE
)
7279 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
7281 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
7283 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
7286 /* If this isn't the first statement in the nested if sequence, see if we
7287 are dealing with the same register. */
7288 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
7291 COND_EXEC_TEST (pattern
) = test
= op1
;
7294 /* If this isn't a nested if, reset state variables. */
7297 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
7300 set
= single_set_pattern (pattern
);
7303 rtx dest
= SET_DEST (set
);
7304 rtx src
= SET_SRC (set
);
7305 enum machine_mode mode
= GET_MODE (dest
);
7307 /* Check for normal binary operators */
7309 && (GET_RTX_CLASS (GET_CODE (src
)) == '2'
7310 || GET_RTX_CLASS (GET_CODE (src
)) == 'c'))
7312 op0
= XEXP (src
, 0);
7313 op1
= XEXP (src
, 1);
7315 /* Special case load of small data address which looks like:
7317 if (GET_CODE (src
) == PLUS
&& plus_small_data_p (op0
, op1
))
7319 src
= frv_ifcvt_load_value (src
, insn
);
7321 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7326 else if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
7328 op1
= frv_ifcvt_load_value (op1
, insn
);
7330 COND_EXEC_CODE (pattern
)
7331 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
7339 /* For multiply by a constant, we need to handle the sign extending
7340 correctly. Add a USE of the value after the multiply to prevent flow
7341 from cratering because only one register out of the two were used. */
7342 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
7344 op0
= XEXP (src
, 0);
7345 op1
= XEXP (src
, 1);
7346 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
7348 op1
= frv_ifcvt_load_value (op1
, insn
);
7351 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
7352 COND_EXEC_CODE (pattern
)
7353 = gen_rtx_SET (VOIDmode
, dest
,
7354 gen_rtx_MULT (DImode
, op0
, op1
));
7360 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
7363 /* If we are just loading a constant created for a nested conditional
7364 execution statement, just load the constant without any conditional
7365 execution, since we know that the constant will not interfere with any
7367 else if (frv_ifcvt
.scratch_insns_bitmap
7368 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
7372 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
7375 int changed_p
= FALSE
;
7377 /* Check for just loading up a constant */
7378 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
7380 src
= frv_ifcvt_load_value (src
, insn
);
7387 /* See if we need to fix up stores */
7388 if (GET_CODE (dest
) == MEM
)
7390 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
7395 else if (new_mem
!= dest
)
7402 /* See if we need to fix up loads */
7403 if (GET_CODE (src
) == MEM
)
7405 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
7410 else if (new_mem
!= src
)
7417 /* If either src or destination changed, redo SET. */
7419 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7422 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7423 rewriting the CC register to be the same as the paired CC/CR register
7425 else if (mode
== CC_CCRmode
&& GET_RTX_CLASS (GET_CODE (src
)) == '<')
7427 int regno
= REGNO (XEXP (src
, 0));
7430 if (ce_info
->pass
> 1
7431 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
7432 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
7434 src
= gen_rtx_fmt_ee (GET_CODE (src
),
7436 frv_ifcvt
.nested_cc_reg
,
7440 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
7441 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
7444 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7445 else if (ce_info
->pass
> 1
7446 && GET_CODE (dest
) == REG
7447 && CC_P (REGNO (dest
))
7448 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
7449 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
7451 && GET_CODE (src
) == COMPARE
)
7453 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
7454 COND_EXEC_CODE (pattern
)
7455 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
7459 if (TARGET_DEBUG_COND_EXEC
)
7461 rtx orig_pattern
= PATTERN (insn
);
7463 PATTERN (insn
) = pattern
;
7465 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7469 PATTERN (insn
) = orig_pattern
;
7475 if (TARGET_DEBUG_COND_EXEC
)
7477 rtx orig_pattern
= PATTERN (insn
);
7479 PATTERN (insn
) = orig_ce_pattern
;
7481 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7485 PATTERN (insn
) = orig_pattern
;
7492 /* A C expression to perform any final machine dependent modifications in
7493 converting code to conditional execution in the code described by the
7494 conditional if information CE_INFO. */
7497 frv_ifcvt_modify_final (ce_info
)
7498 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7502 rtx p
= frv_ifcvt
.added_insns_list
;
7505 /* Loop inserting the check insns. The last check insn is the first test,
7506 and is the appropriate place to insert constants. */
7512 rtx check_and_insert_insns
= XEXP (p
, 0);
7515 check_insn
= XEXP (check_and_insert_insns
, 0);
7516 existing_insn
= XEXP (check_and_insert_insns
, 1);
7519 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7520 the existing insn, otherwise it is to be inserted AFTER. */
7521 if (check_and_insert_insns
->jump
)
7523 emit_insn_before (check_insn
, existing_insn
);
7524 check_and_insert_insns
->jump
= 0;
7527 emit_insn_after (check_insn
, existing_insn
);
7529 free_EXPR_LIST_node (check_and_insert_insns
);
7530 free_EXPR_LIST_node (old_p
);
7532 while (p
!= NULL_RTX
);
7534 /* Load up any constants needed into temp gprs */
7535 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7537 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
7538 if (! frv_ifcvt
.scratch_insns_bitmap
)
7539 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_XMALLOC ();
7540 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
7541 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7544 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7545 frv_ifcvt
.cur_scratch_regs
= 0;
7549 /* A C expression to cancel any machine dependent modifications in converting
7550 code to conditional execution in the code described by the conditional if
7551 information CE_INFO. */
7554 frv_ifcvt_modify_cancel (ce_info
)
7555 ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
;
7558 rtx p
= frv_ifcvt
.added_insns_list
;
7560 /* Loop freeing up the EXPR_LIST's allocated. */
7561 while (p
!= NULL_RTX
)
7563 rtx check_and_jump
= XEXP (p
, 0);
7567 free_EXPR_LIST_node (check_and_jump
);
7568 free_EXPR_LIST_node (old_p
);
7571 /* Release any temporary gprs allocated. */
7572 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7573 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7575 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7576 frv_ifcvt
.cur_scratch_regs
= 0;
7580 /* A C expression for the size in bytes of the trampoline, as an integer.
7584 setlo #0, <static_chain>
7586 sethi #0, <static_chain>
7587 jmpl @(gr0,<jmp_reg>) */
7590 frv_trampoline_size ()
7592 return 5 /* instructions */ * 4 /* instruction size */;
7596 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7597 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7598 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7599 should be passed to the function when it is called.
7604 setlo #0, <static_chain>
7606 sethi #0, <static_chain>
7607 jmpl @(gr0,<jmp_reg>) */
7610 frv_initialize_trampoline (addr
, fnaddr
, static_chain
)
7615 rtx sc_reg
= force_reg (Pmode
, static_chain
);
7617 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
7620 GEN_INT (frv_trampoline_size ()), SImode
,
7626 /* Many machines have some registers that cannot be copied directly to or from
7627 memory or even from other types of registers. An example is the `MQ'
7628 register, which on most machines, can only be copied to or from general
7629 registers, but not memory. Some machines allow copying all registers to and
7630 from memory, but require a scratch register for stores to some memory
7631 locations (e.g., those with symbolic address on the RT, and those with
7632 certain symbolic address on the SPARC when compiling PIC). In some cases,
7633 both an intermediate and a scratch register are required.
7635 You should define these macros to indicate to the reload phase that it may
7636 need to allocate at least one register for a reload in addition to the
7637 register to contain the data. Specifically, if copying X to a register
7638 CLASS in MODE requires an intermediate register, you should define
7639 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7640 whose registers can be used as intermediate registers or scratch registers.
7642 If copying a register CLASS in MODE to X requires an intermediate or scratch
7643 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7644 largest register class required. If the requirements for input and output
7645 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7646 instead of defining both macros identically.
7648 The values returned by these macros are often `GENERAL_REGS'. Return
7649 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7650 to or from a register of CLASS in MODE without requiring a scratch register.
7651 Do not define this macro if it would always return `NO_REGS'.
7653 If a scratch register is required (either with or without an intermediate
7654 register), you should define patterns for `reload_inM' or `reload_outM', as
7655 required.. These patterns, which will normally be implemented with a
7656 `define_expand', should be similar to the `movM' patterns, except that
7657 operand 2 is the scratch register.
7659 Define constraints for the reload register and scratch register that contain
7660 a single register class. If the original reload register (whose class is
7661 CLASS) can meet the constraint given in the pattern, the value returned by
7662 these macros is used for the class of the scratch register. Otherwise, two
7663 additional reload registers are required. Their classes are obtained from
7664 the constraints in the insn pattern.
7666 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7667 either be in a hard register or in memory. Use `true_regnum' to find out;
7668 it will return -1 if the pseudo is in memory and the hard register number if
7669 it is in a register.
7671 These macros should not be used in the case where a particular class of
7672 registers can only be copied to memory and not to another class of
7673 registers. In that case, secondary reload registers are not needed and
7674 would not be helpful. Instead, a stack location must be used to perform the
7675 copy and the `movM' pattern should use memory as a intermediate storage.
7676 This case often occurs between floating-point and general registers. */
7679 frv_secondary_reload_class (class, mode
, x
, in_p
)
7680 enum reg_class
class;
7681 enum machine_mode mode ATTRIBUTE_UNUSED
;
7683 int in_p ATTRIBUTE_UNUSED
;
7693 /* Accumulators/Accumulator guard registers need to go through floating
7699 if (x
&& GET_CODE (x
) == REG
)
7701 int regno
= REGNO (x
);
7703 if (ACC_P (regno
) || ACCG_P (regno
))
7708 /* Nonzero constants should be loaded into an FPR through a GPR. */
7712 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
7718 /* All of these types need gpr registers. */
7730 /* The accumulators need fpr registers */
7743 /* A C expression whose value is nonzero if pseudos that have been assigned to
7744 registers of class CLASS would likely be spilled because registers of CLASS
7745 are needed for spill registers.
7747 The default value of this macro returns 1 if CLASS has exactly one register
7748 and zero otherwise. On most machines, this default should be used. Only
7749 define this macro to some other expression if pseudo allocated by
7750 `local-alloc.c' end up in memory because their hard registers were needed
7751 for spill registers. If this macro returns nonzero for those classes, those
7752 pseudos will only be allocated by `global.c', which knows how to reallocate
7753 the pseudo to another register. If there would not be another register
7754 available for reallocation, you should not change the definition of this
7755 macro since the only effect of such a definition would be to slow down
7756 register allocation. */
7759 frv_class_likely_spilled_p (class)
7760 enum reg_class
class;
7787 /* An expression for the alignment of a structure field FIELD if the
7788 alignment computed in the usual way is COMPUTED. GNU CC uses this
7789 value instead of the value in `BIGGEST_ALIGNMENT' or
7790 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7792 /* The definition type of the bit field data is either char, short, long or
7793 long long. The maximum bit size is the number of bits of its own type.
7795 The bit field data is assigned to a storage unit that has an adequate size
7796 for bit field data retention and is located at the smallest address.
7798 Consecutive bit field data are packed at consecutive bits having the same
7799 storage unit, with regard to the type, beginning with the MSB and continuing
7802 If a field to be assigned lies over a bit field type boundary, its
7803 assignment is completed by aligning it with a boundary suitable for the
7806 When a bit field having a bit length of 0 is declared, it is forcibly
7807 assigned to the next storage unit.
7820 &x 00000000 00000000 00000000 00000000
7823 &x+4 00000000 00000000 00000000 00000000
7826 &x+8 00000000 00000000 00000000 00000000
7829 &x+12 00000000 00000000 00000000 00000000
7835 frv_adjust_field_align (field
, computed
)
7839 /* C++ provides a null DECL_CONTEXT if the bit field is wider than its
7841 if (DECL_BIT_FIELD (field
) && DECL_CONTEXT (field
))
7843 tree parent
= DECL_CONTEXT (field
);
7844 tree prev
= NULL_TREE
;
7847 /* Loop finding the previous field to the current one */
7848 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
7850 if (TREE_CODE (cur
) != FIELD_DECL
)
7859 /* If this isn't a :0 field and if the previous element is a bitfield
7860 also, see if the type is different, if so, we will need to align the
7861 bit-field to the next boundary */
7863 && ! DECL_PACKED (field
)
7864 && ! integer_zerop (DECL_SIZE (field
))
7865 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
7867 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
7868 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
7869 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
7877 /* A C expression that is nonzero if it is permissible to store a value of mode
7878 MODE in hard register number REGNO (or in several registers starting with
7879 that one). For a machine where all registers are equivalent, a suitable
7882 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7884 It is not necessary for this macro to check for the numbers of fixed
7885 registers, because the allocation mechanism considers them to be always
7888 On some machines, double-precision values must be kept in even/odd register
7889 pairs. The way to implement that is to define this macro to reject odd
7890 register numbers for such modes.
7892 The minimum requirement for a mode to be OK in a register is that the
7893 `movMODE' instruction pattern support moves between the register and any
7894 other hard register for which the mode is OK; and that moving a value into
7895 the register and back out not alter it.
7897 Since the same instruction used to move `SImode' will work for all narrower
7898 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7899 to distinguish between these modes, provided you define patterns `movhi',
7900 etc., to take advantage of this. This is useful because of the interaction
7901 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7902 all integer modes to be tieable.
7904 Many machines have special registers for floating point arithmetic. Often
7905 people assume that floating point machine modes are allowed only in floating
7906 point registers. This is not true. Any registers that can hold integers
7907 can safely *hold* a floating point machine mode, whether or not floating
7908 arithmetic can be done on it in those registers. Integer move instructions
7909 can be used to move the values.
7911 On some machines, though, the converse is true: fixed-point machine modes
7912 may not go in floating registers. This is true if the floating registers
7913 normalize any value stored in them, because storing a non-floating value
7914 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7915 fixed-point machine modes in floating registers. But if the floating
7916 registers do not automatically normalize, if you can store any bit pattern
7917 in one and retrieve it unchanged without a trap, then any machine mode may
7918 go in a floating register, so you can define this macro to say so.
7920 The primary significance of special floating registers is rather that they
7921 are the registers acceptable in floating point arithmetic instructions.
7922 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7923 writing the proper constraints for those instructions.
7925 On some machines, the floating registers are especially slow to access, so
7926 that it is better to store a value in a stack frame than in such a register
7927 if floating point arithmetic is not being done. As long as the floating
7928 registers are not in class `GENERAL_REGS', they will not be used unless some
7929 pattern's constraint asks for one. */
7932 frv_hard_regno_mode_ok (regno
, mode
)
7934 enum machine_mode mode
;
7943 return ICC_P (regno
) || GPR_P (regno
);
7946 return CR_P (regno
) || GPR_P (regno
);
7949 return FCC_P (regno
) || GPR_P (regno
);
7955 /* Set BASE to the first register in REGNO's class. Set MASK to the
7956 bits that must be clear in (REGNO - BASE) for the register to be
7958 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
7962 /* ACCGs store one byte. Two-byte quantities must start in
7963 even-numbered registers, four-byte ones in registers whose
7964 numbers are divisible by four, and so on. */
7966 mask
= GET_MODE_SIZE (mode
) - 1;
7970 /* The other registers store one word. */
7974 else if (FPR_P (regno
))
7977 else if (ACC_P (regno
))
7983 /* Anything smaller than an SI is OK in any word-sized register. */
7984 if (GET_MODE_SIZE (mode
) < 4)
7987 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
7989 return (((regno
- base
) & mask
) == 0);
7996 /* A C expression for the number of consecutive hard registers, starting at
7997 register number REGNO, required to hold a value of mode MODE.
7999 On a machine where all registers are exactly one word, a suitable definition
8002 #define HARD_REGNO_NREGS(REGNO, MODE) \
8003 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
8004 / UNITS_PER_WORD)) */
8006 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
8007 that we can build the appropriate instructions to properly reload the
8008 values. Also, make the byte-sized accumulator guards use one guard
8012 frv_hard_regno_nregs (regno
, mode
)
8014 enum machine_mode mode
;
8017 return GET_MODE_SIZE (mode
);
8019 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8023 /* A C expression for the maximum number of consecutive registers of
8024 class CLASS needed to hold a value of mode MODE.
8026 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
8027 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
8028 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
8030 This macro helps control the handling of multiple-word values in
8033 This declaration is required. */
8036 frv_class_max_nregs (class, mode
)
8037 enum reg_class
class;
8038 enum machine_mode mode
;
8040 if (class == ACCG_REGS
)
8041 /* An N-byte value requires N accumulator guards. */
8042 return GET_MODE_SIZE (mode
);
8044 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8048 /* A C expression that is nonzero if X is a legitimate constant for an
8049 immediate operand on the target machine. You can assume that X satisfies
8050 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
8051 definition for this macro on machines where anything `CONSTANT_P' is valid. */
8054 frv_legitimate_constant_p (x
)
8057 enum machine_mode mode
= GET_MODE (x
);
8059 /* All of the integer constants are ok */
8060 if (GET_CODE (x
) != CONST_DOUBLE
)
8063 /* double integer constants are ok */
8064 if (mode
== VOIDmode
|| mode
== DImode
)
8067 /* 0 is always ok */
8068 if (x
== CONST0_RTX (mode
))
8071 /* If floating point is just emulated, allow any constant, since it will be
8072 constructed in the GPRs */
8073 if (!TARGET_HAS_FPRS
)
8076 if (mode
== DFmode
&& !TARGET_DOUBLE
)
8079 /* Otherwise store the constant away and do a load. */
8083 /* A C expression for the cost of moving data from a register in class FROM to
8084 one in class TO. The classes are expressed using the enumeration values
8085 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8086 interpreted relative to that.
8088 It is not required that the cost always equal 2 when FROM is the same as TO;
8089 on some machines it is expensive to move between registers if they are not
8092 If reload sees an insn consisting of a single `set' between two hard
8093 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8094 value of 2, reload does not check to ensure that the constraints of the insn
8095 are met. Setting a cost of other than 2 will allow reload to verify that
8096 the constraints are met. You should do this if the `movM' pattern's
8097 constraints do not allow such copying. */
8099 #define HIGH_COST 40
8100 #define MEDIUM_COST 3
8104 frv_register_move_cost (from
, to
)
8105 enum reg_class from
;
8190 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8191 use ".picptr" to generate safe relocations for PIC code. We also
8192 need a fixup entry for aligned (non-debugging) code. */
8195 frv_assemble_integer (value
, size
, aligned_p
)
8200 if (flag_pic
&& size
== UNITS_PER_WORD
)
8202 if (GET_CODE (value
) == CONST
8203 || GET_CODE (value
) == SYMBOL_REF
8204 || GET_CODE (value
) == LABEL_REF
)
8208 static int label_num
= 0;
8212 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
8213 p
= (* targetm
.strip_name_encoding
) (buf
);
8215 fprintf (asm_out_file
, "%s:\n", p
);
8216 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
8217 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
8218 fprintf (asm_out_file
, "\t.previous\n");
8220 assemble_integer_with_op ("\t.picptr\t", value
);
8225 /* We've set the unaligned SI op to NULL, so we always have to
8226 handle the unaligned case here. */
8227 assemble_integer_with_op ("\t.4byte\t", value
);
8231 return default_assemble_integer (value
, size
, aligned_p
);
8234 /* Function to set up the backend function structure. */
8236 static struct machine_function
*
8237 frv_init_machine_status ()
8239 return ggc_alloc_cleared (sizeof (struct machine_function
));
8243 /* Update the register state information, to know about which registers are set
8247 frv_registers_update (x
, reg_state
, modified
, p_num_mod
, flag
)
8249 unsigned char reg_state
[];
8261 switch (GET_CODE (x
))
8266 /* Clobber just modifies a register, it doesn't make it live. */
8268 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8269 flag
| REGSTATE_MODIFIED
);
8272 /* Pre modify updates the first argument, just references the second. */
8275 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
8276 flag
| REGSTATE_MODIFIED
| REGSTATE_LIVE
);
8277 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
, flag
);
8280 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8281 statement, but just to be sure, make sure it is the type of cond_exec
8285 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8286 && GET_CODE (XEXP (cond
, 0)) == REG
8287 && CR_P (REGNO (XEXP (cond
, 0)))
8288 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8289 && INTVAL (XEXP (cond
, 1)) == 0
8290 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8292 frv_registers_update (cond
, reg_state
, modified
, p_num_mod
, flag
);
8293 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8294 | ((GET_CODE (cond
) == NE
)
8296 : REGSTATE_IF_FALSE
));
8298 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
,
8303 fatal_insn ("frv_registers_update", x
);
8305 /* MEM resets the modification bits. */
8307 flag
&= ~REGSTATE_MODIFIED
;
8310 /* See if we need to set the modified flag. */
8312 reg
= SUBREG_REG (x
);
8313 if (GET_CODE (reg
) == REG
)
8315 regno
= subreg_regno (x
);
8316 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8323 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8327 if (flag
& REGSTATE_MODIFIED
)
8329 flag
&= REGSTATE_MASK
;
8330 while (regno
< reg_max
)
8332 int rs
= reg_state
[regno
];
8336 if ((rs
& REGSTATE_MODIFIED
) == 0)
8338 modified
[ *p_num_mod
] = regno
;
8342 /* If the previous register state had the register as
8343 modified, possibly in some conditional execution context,
8344 and the current insn modifies in some other context, or
8345 outside of conditional execution, just mark the variable
8348 flag
&= ~(REGSTATE_IF_EITHER
| REGSTATE_CC_MASK
);
8350 reg_state
[regno
] = (rs
| flag
);
8359 length
= GET_RTX_LENGTH (GET_CODE (x
));
8360 format
= GET_RTX_FORMAT (GET_CODE (x
));
8362 for (j
= 0; j
< length
; ++j
)
8367 frv_registers_update (XEXP (x
, j
), reg_state
, modified
, p_num_mod
,
8373 if (XVEC (x
, j
) != 0)
8376 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8377 frv_registers_update (XVECEXP (x
, j
, k
), reg_state
, modified
,
8383 /* Nothing to do. */
8392 /* Return if any registers in a hard register set were used an insn. */
8395 frv_registers_used_p (x
, reg_state
, flag
)
8397 unsigned char reg_state
[];
8409 switch (GET_CODE (x
))
8414 /* Skip clobber, that doesn't use the previous value */
8418 /* For SET, if a conditional jump has occurred in the same insn, only
8419 allow a set of a CR register if that register is not currently live.
8420 This is because on the FR-V, B0/B1 instructions are always last.
8421 Otherwise, don't look at the result, except within a MEM, but do look
8424 dest
= SET_DEST (x
);
8425 if (flag
& REGSTATE_CONDJUMP
8426 && GET_CODE (dest
) == REG
&& CR_P (REGNO (dest
))
8427 && (reg_state
[ REGNO (dest
) ] & REGSTATE_LIVE
) != 0)
8430 if (GET_CODE (dest
) == MEM
)
8432 result
= frv_registers_used_p (XEXP (dest
, 0), reg_state
, flag
);
8437 return frv_registers_used_p (SET_SRC (x
), reg_state
, flag
);
8439 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8440 statement, but just to be sure, make sure it is the type of cond_exec
8444 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8445 && GET_CODE (XEXP (cond
, 0)) == REG
8446 && CR_P (REGNO (XEXP (cond
, 0)))
8447 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8448 && INTVAL (XEXP (cond
, 1)) == 0
8449 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8451 result
= frv_registers_used_p (cond
, reg_state
, flag
);
8455 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8456 | ((GET_CODE (cond
) == NE
)
8458 : REGSTATE_IF_FALSE
));
8460 return frv_registers_used_p (XEXP (x
, 1), reg_state
, flag
);
8463 fatal_insn ("frv_registers_used_p", x
);
8465 /* See if a register or subreg was modified in the same VLIW insn. */
8467 reg
= SUBREG_REG (x
);
8468 if (GET_CODE (reg
) == REG
)
8470 regno
= subreg_regno (x
);
8471 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8478 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8482 while (regno
< reg_max
)
8484 int rs
= reg_state
[regno
];
8486 if (rs
& REGSTATE_MODIFIED
)
8488 int rs_if
= rs
& REGSTATE_IF_EITHER
;
8489 int flag_if
= flag
& REGSTATE_IF_EITHER
;
8491 /* Simple modification, no conditional execution */
8492 if ((rs
& REGSTATE_IF_EITHER
) == 0)
8495 /* See if the variable is only modified in a conditional
8496 execution expression opposite to the conditional execution
8497 expression that governs this expression (ie, true vs. false
8498 for the same CC register). If this isn't two halves of the
8499 same conditional expression, consider the register
8501 if (((rs_if
== REGSTATE_IF_TRUE
&& flag_if
== REGSTATE_IF_FALSE
)
8502 || (rs_if
== REGSTATE_IF_FALSE
&& flag_if
== REGSTATE_IF_TRUE
))
8503 && ((rs
& REGSTATE_CC_MASK
) == (flag
& REGSTATE_CC_MASK
)))
8515 length
= GET_RTX_LENGTH (GET_CODE (x
));
8516 format
= GET_RTX_FORMAT (GET_CODE (x
));
8518 for (j
= 0; j
< length
; ++j
)
8523 result
= frv_registers_used_p (XEXP (x
, j
), reg_state
, flag
);
8530 if (XVEC (x
, j
) != 0)
8533 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8535 result
= frv_registers_used_p (XVECEXP (x
, j
, k
), reg_state
,
8544 /* Nothing to do. */
8552 /* Return if any registers in a hard register set were set in an insn. */
8555 frv_registers_set_p (x
, reg_state
, modify_p
)
8557 unsigned char reg_state
[];
8567 switch (GET_CODE (x
))
8573 return frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
);
8577 return (frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
)
8578 || frv_registers_set_p (XEXP (x
, 1), reg_state
, FALSE
));
8582 /* just to be sure, make sure it is the type of cond_exec we
8584 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8585 && GET_CODE (XEXP (cond
, 0)) == REG
8586 && CR_P (REGNO (XEXP (cond
, 0)))
8587 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8588 && INTVAL (XEXP (cond
, 1)) == 0
8590 return frv_registers_set_p (XEXP (x
, 1), reg_state
, modify_p
);
8592 fatal_insn ("frv_registers_set_p", x
);
8594 /* MEM resets the modification bits. */
8599 /* See if we need to set the modified modify_p. */
8601 reg
= SUBREG_REG (x
);
8602 if (GET_CODE (reg
) == REG
)
8604 regno
= subreg_regno (x
);
8605 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8612 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8617 while (regno
< reg_max
)
8619 int rs
= reg_state
[regno
];
8621 if (rs
& REGSTATE_MODIFIED
)
8629 length
= GET_RTX_LENGTH (GET_CODE (x
));
8630 format
= GET_RTX_FORMAT (GET_CODE (x
));
8632 for (j
= 0; j
< length
; ++j
)
8637 if (frv_registers_set_p (XEXP (x
, j
), reg_state
, modify_p
))
8643 if (XVEC (x
, j
) != 0)
8646 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8647 if (frv_registers_set_p (XVECEXP (x
, j
, k
), reg_state
,
8654 /* Nothing to do. */
8663 /* In rare cases, correct code generation requires extra machine dependent
8664 processing between the second jump optimization pass and delayed branch
8665 scheduling. On those machines, define this macro as a C statement to act on
8666 the code starting at INSN. */
8668 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8669 conditional branches/calls/jumps, etc. with previous insns where it can. It
8670 does not reorder the instructions. We assume the scheduler left the flow
8671 information in a reasonable state. */
8676 state_t frv_state
; /* frv state machine */
8677 int cur_start_vliw_p
; /* current insn starts a VLIW insn */
8678 int next_start_vliw_p
; /* next insn starts a VLIW insn */
8679 int cur_condjump_p
; /* flag if current insn is a cond jump*/
8680 int next_condjump_p
; /* flag if next insn is a cond jump */
8684 int num_mod
= 0; /* # of modified registers */
8685 int modified
[FIRST_PSEUDO_REGISTER
]; /* registers modified in current VLIW */
8686 /* register state information */
8687 unsigned char reg_state
[FIRST_PSEUDO_REGISTER
];
8689 /* If we weren't going to pack the insns, don't bother with this pass. */
8690 if (!optimize
|| !flag_schedule_insns_after_reload
|| TARGET_NO_VLIW_BRANCH
)
8693 switch (frv_cpu_type
)
8696 case FRV_CPU_FR300
: /* FR300/simple are single issue */
8697 case FRV_CPU_SIMPLE
:
8700 case FRV_CPU_GENERIC
: /* FR-V and FR500 are multi-issue */
8703 case FRV_CPU_TOMCAT
:
8707 /* Set up the instruction and register states. */
8709 frv_state
= (state_t
) xmalloc (state_size ());
8710 memset ((PTR
) reg_state
, REGSTATE_DEAD
, sizeof (reg_state
));
8712 /* Go through the insns, and repack the insns. */
8713 state_reset (frv_state
);
8714 cur_start_vliw_p
= FALSE
;
8715 next_start_vliw_p
= TRUE
;
8717 next_condjump_p
= 0;
8719 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
8721 enum rtx_code code
= GET_CODE (insn
);
8722 enum rtx_code pattern_code
;
8724 /* For basic block begin notes redo the live information, and skip other
8728 if (NOTE_LINE_NUMBER (insn
) == (int)NOTE_INSN_BASIC_BLOCK
)
8732 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
8733 reg_state
[j
] &= ~ REGSTATE_LIVE
;
8735 live
= NOTE_BASIC_BLOCK (insn
)->global_live_at_start
;
8736 EXECUTE_IF_SET_IN_REG_SET(live
, 0, j
,
8738 reg_state
[j
] |= REGSTATE_LIVE
;
8745 /* things like labels reset everything. */
8746 if (GET_RTX_CLASS (code
) != 'i')
8748 next_start_vliw_p
= TRUE
;
8752 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8753 set on the USE insn that preceeds the return, and potentially on
8754 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8755 holding the case table labels. */
8756 pattern_code
= GET_CODE (PATTERN (insn
));
8757 if (pattern_code
== USE
|| pattern_code
== CLOBBER
8758 || pattern_code
== ADDR_VEC
|| pattern_code
== ADDR_DIFF_VEC
)
8760 CLEAR_VLIW_START (insn
);
8764 cur_start_vliw_p
= next_start_vliw_p
;
8765 next_start_vliw_p
= FALSE
;
8767 cur_condjump_p
|= next_condjump_p
;
8768 next_condjump_p
= 0;
8770 /* Unconditional branches and calls end the current VLIW insn. */
8771 if (code
== CALL_INSN
)
8773 next_start_vliw_p
= TRUE
;
8775 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8776 if (frv_cpu_type
== FRV_CPU_TOMCAT
)
8777 cur_start_vliw_p
= TRUE
;
8779 else if (code
== JUMP_INSN
)
8781 if (any_condjump_p (insn
))
8782 next_condjump_p
= REGSTATE_CONDJUMP
;
8784 next_start_vliw_p
= TRUE
;
8787 /* Only allow setting a CCR register after a conditional branch. */
8788 else if (((cur_condjump_p
& REGSTATE_CONDJUMP
) != 0)
8789 && get_attr_type (insn
) != TYPE_CCR
)
8790 cur_start_vliw_p
= TRUE
;
8792 /* Determine if we need to start a new VLIW instruction. */
8793 if (cur_start_vliw_p
8794 /* Do not check for register conflicts in a setlo instruction
8795 because any output or true dependencies will be with the
8796 partnering sethi instruction, with which it can be packed.
8798 Although output dependencies are rare they are still
8799 possible. So check output dependencies in VLIW insn. */
8800 || (get_attr_type (insn
) != TYPE_SETLO
8801 && (frv_registers_used_p (PATTERN (insn
),
8804 || frv_registers_set_p (PATTERN (insn
), reg_state
, FALSE
)))
8805 || state_transition (frv_state
, insn
) >= 0)
8807 SET_VLIW_START (insn
);
8808 state_reset (frv_state
);
8809 state_transition (frv_state
, insn
);
8812 /* Update the modified registers. */
8813 for (j
= 0; j
< num_mod
; j
++)
8814 reg_state
[ modified
[j
] ] &= ~(REGSTATE_CC_MASK
8815 | REGSTATE_IF_EITHER
8816 | REGSTATE_MODIFIED
);
8821 CLEAR_VLIW_START (insn
);
8823 /* Record which registers are modified. */
8824 frv_registers_update (PATTERN (insn
), reg_state
, modified
, &num_mod
, 0);
8826 /* Process the death notices */
8827 for (link
= REG_NOTES (insn
);
8829 link
= XEXP (link
, 1))
8831 rtx reg
= XEXP (link
, 0);
8833 if (REG_NOTE_KIND (link
) == REG_DEAD
&& GET_CODE (reg
) == REG
)
8835 int regno
= REGNO (reg
);
8836 int n
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8837 for (; regno
< n
; regno
++)
8838 reg_state
[regno
] &= ~REGSTATE_LIVE
;
8843 free ((PTR
) frv_state
);
8849 #define def_builtin(name, type, code) \
8850 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8852 struct builtin_description
8854 enum insn_code icode
;
8856 enum frv_builtins code
;
8857 enum rtx_code comparison
;
8861 /* Media intrinsics that take a single, constant argument. */
8863 static struct builtin_description bdesc_set
[] =
8865 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8868 /* Media intrinsics that take just one argument. */
8870 static struct builtin_description bdesc_1arg
[] =
8872 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
8873 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
8874 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
8875 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
8876 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 }
8879 /* Media intrinsics that take two arguments. */
8881 static struct builtin_description bdesc_2arg
[] =
8883 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
8884 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
8885 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
8886 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
8887 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
8888 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
8889 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
8890 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
8891 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
8892 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
8893 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
8894 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
8895 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
8896 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
8897 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
8898 { CODE_FOR_mdpackh
, "__MDPACKH", FRV_BUILTIN_MDPACKH
, 0, 0 },
8899 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
8900 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
8901 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
8902 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 }
8905 /* Media intrinsics that take two arguments, the first being an ACC number. */
8907 static struct builtin_description bdesc_cut
[] =
8909 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
8910 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
8911 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
8914 /* Two-argument media intrinsics with an immediate second argument. */
8916 static struct builtin_description bdesc_2argimm
[] =
8918 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
8919 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
8920 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
8921 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
8922 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
8923 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
8924 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
8925 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
8926 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
8927 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
8928 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
8929 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
8930 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
8931 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
8932 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 }
8935 /* Media intrinsics that take two arguments and return void, the first argument
8936 being a pointer to 4 words in memory. */
8938 static struct builtin_description bdesc_void2arg
[] =
8940 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
8941 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
8944 /* Media intrinsics that take three arguments, the first being a const_int that
8945 denotes an accumulator, and that return void. */
8947 static struct builtin_description bdesc_void3arg
[] =
8949 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
8950 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
8951 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
8952 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
8953 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
8954 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
8955 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
8956 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
8957 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
8958 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
8959 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
8960 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
8961 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
8962 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
8963 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
8964 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
8965 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
8966 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
8967 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
8968 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
8969 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
8970 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
8971 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
8972 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
8973 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
8976 /* Media intrinsics that take two accumulator numbers as argument and
8979 static struct builtin_description bdesc_voidacc
[] =
8981 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
8982 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
8983 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
8984 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
8985 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
8986 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
8989 /* Initialize media builtins. */
8992 frv_init_builtins ()
8994 tree endlink
= void_list_node
;
8995 tree accumulator
= integer_type_node
;
8996 tree integer
= integer_type_node
;
8997 tree voidt
= void_type_node
;
8998 tree uhalf
= short_unsigned_type_node
;
8999 tree sword1
= long_integer_type_node
;
9000 tree uword1
= long_unsigned_type_node
;
9001 tree sword2
= long_long_integer_type_node
;
9002 tree uword2
= long_long_unsigned_type_node
;
9003 tree uword4
= build_pointer_type (uword1
);
9005 #define UNARY(RET, T1) \
9006 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9008 #define BINARY(RET, T1, T2) \
9009 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9010 tree_cons (NULL_TREE, T2, endlink)))
9012 #define TRINARY(RET, T1, T2, T3) \
9013 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9014 tree_cons (NULL_TREE, T2, \
9015 tree_cons (NULL_TREE, T3, endlink))))
9017 tree void_ftype_void
= build_function_type (voidt
, endlink
);
9019 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
9020 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
9021 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
9022 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
9023 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
9024 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
9025 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
9026 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
9027 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
9029 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
9030 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
9031 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
9032 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
9033 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
9034 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
9035 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
9036 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
9037 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
9038 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
9039 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
9041 tree sw1_ftype_int
= UNARY (sword1
, integer
);
9042 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
9043 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
9045 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
9046 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
9047 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
9048 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
9049 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
9051 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
9053 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
9054 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
9055 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
9056 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
9057 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
9058 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
9059 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
9060 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
9061 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
9062 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
9063 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
9064 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
9065 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
9066 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
9067 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
9068 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
9069 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
9070 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
9071 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
9072 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
9073 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
9074 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
9075 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
9076 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
9077 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
9078 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
9079 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
9080 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
9081 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
9082 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
9083 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
9084 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
9085 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
9086 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
9087 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
9088 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
9089 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
9090 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
9091 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
9092 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
9093 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
9094 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
9095 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
9096 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
9097 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
9098 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
9099 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
9100 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
9101 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
9102 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MDPACKH
);
9103 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
9104 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
9105 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
9106 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
9107 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
9108 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
9109 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
9110 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
9111 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
9112 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
9113 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
9114 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
9115 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
9116 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
9117 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
9118 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
9119 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
9120 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
9121 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
9122 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
9123 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
9124 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
9125 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
9126 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
9127 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
9128 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
9129 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
9130 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
9131 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
9132 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
9133 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
9134 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
9135 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
9136 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
9143 /* Convert an integer constant to an accumulator register. ICODE is the
9144 code of the target instruction, OPNUM is the number of the
9145 accumulator operand and OPVAL is the constant integer. Try both
9146 ACC and ACCG registers; only report an error if neither fit the
9150 frv_int_to_acc (icode
, opnum
, opval
)
9151 enum insn_code icode
;
9157 if (GET_CODE (opval
) != CONST_INT
)
9159 error ("accumulator is not a constant integer");
9162 if (! IN_RANGE_P (INTVAL (opval
), 0, NUM_ACCS
- 1))
9164 error ("accumulator number is out of bounds");
9168 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
9169 ACC_FIRST
+ INTVAL (opval
));
9170 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9171 REGNO (reg
) = ACCG_FIRST
+ INTVAL (opval
);
9173 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
9175 error ("inappropriate accumulator for `%s'", insn_data
[icode
].name
);
9181 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9184 static enum machine_mode
9185 frv_matching_accg_mode (mode
)
9186 enum machine_mode mode
;
9204 /* Return the accumulator guard that should be paired with accumulator
9205 register ACC. The mode of the returned register is in the same
9206 class as ACC, but is four times smaller. */
9209 frv_matching_accg_for_acc (acc
)
9212 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
9213 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
9216 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9217 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9221 frv_read_argument (arglistptr
)
9224 tree next
= TREE_VALUE (*arglistptr
);
9225 *arglistptr
= TREE_CHAIN (*arglistptr
);
9226 return expand_expr (next
, NULL_RTX
, VOIDmode
, 0);
9229 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9230 The instruction should require a constant operand of some sort. The
9231 function prints an error if OPVAL is not valid. */
9234 frv_check_constant_argument (icode
, opnum
, opval
)
9235 enum insn_code icode
;
9239 if (GET_CODE (opval
) != CONST_INT
)
9241 error ("`%s' expects a constant argument", insn_data
[icode
].name
);
9244 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
9246 error ("constant argument out of range for `%s'", insn_data
[icode
].name
);
9252 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9253 if it's not null, has the right mode, and satisfies operand 0's
9257 frv_legitimize_target (icode
, target
)
9258 enum insn_code icode
;
9261 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
9264 || GET_MODE (target
) != mode
9265 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
9266 return gen_reg_rtx (mode
);
9271 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9272 check whether ARG satisfies the operand's contraints. If it doesn't,
9273 copy ARG to a temporary register and return that. Otherwise return ARG
9277 frv_legitimize_argument (icode
, opnum
, arg
)
9278 enum insn_code icode
;
9282 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
9284 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
9287 return copy_to_mode_reg (mode
, arg
);
9290 /* Expand builtins that take a single, constant argument. At the moment,
9291 only MHDSETS falls into this category. */
9294 frv_expand_set_builtin (icode
, arglist
, target
)
9295 enum insn_code icode
;
9300 rtx op0
= frv_read_argument (&arglist
);
9302 if (! frv_check_constant_argument (icode
, 1, op0
))
9305 target
= frv_legitimize_target (icode
, target
);
9306 pat
= GEN_FCN (icode
) (target
, op0
);
9314 /* Expand builtins that take one operand. */
9317 frv_expand_unop_builtin (icode
, arglist
, target
)
9318 enum insn_code icode
;
9323 rtx op0
= frv_read_argument (&arglist
);
9325 target
= frv_legitimize_target (icode
, target
);
9326 op0
= frv_legitimize_argument (icode
, 1, op0
);
9327 pat
= GEN_FCN (icode
) (target
, op0
);
9335 /* Expand builtins that take two operands. */
9338 frv_expand_binop_builtin (icode
, arglist
, target
)
9339 enum insn_code icode
;
9344 rtx op0
= frv_read_argument (&arglist
);
9345 rtx op1
= frv_read_argument (&arglist
);
9347 target
= frv_legitimize_target (icode
, target
);
9348 op0
= frv_legitimize_argument (icode
, 1, op0
);
9349 op1
= frv_legitimize_argument (icode
, 2, op1
);
9350 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9358 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9362 frv_expand_cut_builtin (icode
, arglist
, target
)
9363 enum insn_code icode
;
9368 rtx op0
= frv_read_argument (&arglist
);
9369 rtx op1
= frv_read_argument (&arglist
);
9372 target
= frv_legitimize_target (icode
, target
);
9373 op0
= frv_int_to_acc (icode
, 1, op0
);
9377 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
9379 if (! frv_check_constant_argument (icode
, 2, op1
))
9383 op1
= frv_legitimize_argument (icode
, 2, op1
);
9385 op2
= frv_matching_accg_for_acc (op0
);
9386 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
9394 /* Expand builtins that take two operands and the second is immediate. */
9397 frv_expand_binopimm_builtin (icode
, arglist
, target
)
9398 enum insn_code icode
;
9403 rtx op0
= frv_read_argument (&arglist
);
9404 rtx op1
= frv_read_argument (&arglist
);
9406 if (! frv_check_constant_argument (icode
, 2, op1
))
9409 target
= frv_legitimize_target (icode
, target
);
9410 op0
= frv_legitimize_argument (icode
, 1, op0
);
9411 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9419 /* Expand builtins that take two operands, the first operand being a pointer to
9420 ints and return void. */
9423 frv_expand_voidbinop_builtin (icode
, arglist
)
9424 enum insn_code icode
;
9428 rtx op0
= frv_read_argument (&arglist
);
9429 rtx op1
= frv_read_argument (&arglist
);
9430 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
9433 if (GET_CODE (op0
) != MEM
)
9437 if (! offsettable_address_p (0, mode0
, op0
))
9439 reg
= gen_reg_rtx (Pmode
);
9440 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
9443 op0
= gen_rtx_MEM (SImode
, reg
);
9446 addr
= XEXP (op0
, 0);
9447 if (! offsettable_address_p (0, mode0
, addr
))
9448 addr
= copy_to_mode_reg (Pmode
, op0
);
9450 op0
= change_address (op0
, V4SImode
, addr
);
9451 op1
= frv_legitimize_argument (icode
, 1, op1
);
9452 pat
= GEN_FCN (icode
) (op0
, op1
);
9460 /* Expand builtins that take three operands and return void. The first
9461 argument must be a constant that describes a pair or quad accumulators. A
9462 fourth argument is created that is the accumulator guard register that
9463 corresponds to the accumulator. */
9466 frv_expand_voidtriop_builtin (icode
, arglist
)
9467 enum insn_code icode
;
9471 rtx op0
= frv_read_argument (&arglist
);
9472 rtx op1
= frv_read_argument (&arglist
);
9473 rtx op2
= frv_read_argument (&arglist
);
9476 op0
= frv_int_to_acc (icode
, 0, op0
);
9480 op1
= frv_legitimize_argument (icode
, 1, op1
);
9481 op2
= frv_legitimize_argument (icode
, 2, op2
);
9482 op3
= frv_matching_accg_for_acc (op0
);
9483 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9491 /* Expand builtins that perform accumulator-to-accumulator operations.
9492 These builtins take two accumulator numbers as argument and return
9496 frv_expand_voidaccop_builtin (icode
, arglist
)
9497 enum insn_code icode
;
9501 rtx op0
= frv_read_argument (&arglist
);
9502 rtx op1
= frv_read_argument (&arglist
);
9506 op0
= frv_int_to_acc (icode
, 0, op0
);
9510 op1
= frv_int_to_acc (icode
, 1, op1
);
9514 op2
= frv_matching_accg_for_acc (op0
);
9515 op3
= frv_matching_accg_for_acc (op1
);
9516 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9524 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9525 number as argument. */
9528 frv_expand_mclracc_builtin (arglist
)
9531 enum insn_code icode
= CODE_FOR_mclracc
;
9533 rtx op0
= frv_read_argument (&arglist
);
9535 op0
= frv_int_to_acc (icode
, 0, op0
);
9539 pat
= GEN_FCN (icode
) (op0
);
9546 /* Expand builtins that take no arguments. */
9549 frv_expand_noargs_builtin (icode
)
9550 enum insn_code icode
;
9552 rtx pat
= GEN_FCN (icode
) (GEN_INT (0));
9559 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9560 number or accumulator guard number as argument and return an SI integer. */
9563 frv_expand_mrdacc_builtin (icode
, arglist
)
9564 enum insn_code icode
;
9568 rtx target
= gen_reg_rtx (SImode
);
9569 rtx op0
= frv_read_argument (&arglist
);
9571 op0
= frv_int_to_acc (icode
, 1, op0
);
9575 pat
= GEN_FCN (icode
) (target
, op0
);
9583 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9584 accumulator guard as their first argument and an SImode value as their
9588 frv_expand_mwtacc_builtin (icode
, arglist
)
9589 enum insn_code icode
;
9593 rtx op0
= frv_read_argument (&arglist
);
9594 rtx op1
= frv_read_argument (&arglist
);
9596 op0
= frv_int_to_acc (icode
, 0, op0
);
9600 op1
= frv_legitimize_argument (icode
, 1, op1
);
9601 pat
= GEN_FCN (icode
) (op0
, op1
);
9608 /* Expand builtins. */
9611 frv_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9614 rtx subtarget ATTRIBUTE_UNUSED
;
9615 enum machine_mode mode ATTRIBUTE_UNUSED
;
9616 int ignore ATTRIBUTE_UNUSED
;
9618 tree arglist
= TREE_OPERAND (exp
, 1);
9619 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9620 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9622 struct builtin_description
*d
;
9626 error ("media functions are not available unless -mmedia is used");
9632 case FRV_BUILTIN_MCOP1
:
9633 case FRV_BUILTIN_MCOP2
:
9634 case FRV_BUILTIN_MDUNPACKH
:
9635 case FRV_BUILTIN_MBTOHE
:
9636 if (! TARGET_MEDIA_REV1
)
9638 error ("this media function is only available on the fr500");
9643 case FRV_BUILTIN_MQXMACHS
:
9644 case FRV_BUILTIN_MQXMACXHS
:
9645 case FRV_BUILTIN_MQMACXHS
:
9646 case FRV_BUILTIN_MADDACCS
:
9647 case FRV_BUILTIN_MSUBACCS
:
9648 case FRV_BUILTIN_MASACCS
:
9649 case FRV_BUILTIN_MDADDACCS
:
9650 case FRV_BUILTIN_MDSUBACCS
:
9651 case FRV_BUILTIN_MDASACCS
:
9652 case FRV_BUILTIN_MABSHS
:
9653 case FRV_BUILTIN_MDROTLI
:
9654 case FRV_BUILTIN_MCPLHI
:
9655 case FRV_BUILTIN_MCPLI
:
9656 case FRV_BUILTIN_MDCUTSSI
:
9657 case FRV_BUILTIN_MQSATHS
:
9658 case FRV_BUILTIN_MHSETLOS
:
9659 case FRV_BUILTIN_MHSETLOH
:
9660 case FRV_BUILTIN_MHSETHIS
:
9661 case FRV_BUILTIN_MHSETHIH
:
9662 case FRV_BUILTIN_MHDSETS
:
9663 case FRV_BUILTIN_MHDSETH
:
9664 if (! TARGET_MEDIA_REV2
)
9666 error ("this media function is only available on the fr400");
9675 /* Expand unique builtins. */
9679 case FRV_BUILTIN_MTRAP
:
9680 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9682 case FRV_BUILTIN_MCLRACC
:
9683 return frv_expand_mclracc_builtin (arglist
);
9685 case FRV_BUILTIN_MCLRACCA
:
9687 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9689 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9691 case FRV_BUILTIN_MRDACC
:
9692 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, arglist
);
9694 case FRV_BUILTIN_MRDACCG
:
9695 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, arglist
);
9697 case FRV_BUILTIN_MWTACC
:
9698 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, arglist
);
9700 case FRV_BUILTIN_MWTACCG
:
9701 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, arglist
);
9707 /* Expand groups of builtins. */
9709 for (i
= 0, d
= bdesc_set
; i
< sizeof (bdesc_set
) / sizeof *d
; i
++, d
++)
9710 if (d
->code
== fcode
)
9711 return frv_expand_set_builtin (d
->icode
, arglist
, target
);
9713 for (i
= 0, d
= bdesc_1arg
; i
< sizeof (bdesc_1arg
) / sizeof *d
; i
++, d
++)
9714 if (d
->code
== fcode
)
9715 return frv_expand_unop_builtin (d
->icode
, arglist
, target
);
9717 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
9718 if (d
->code
== fcode
)
9719 return frv_expand_binop_builtin (d
->icode
, arglist
, target
);
9721 for (i
= 0, d
= bdesc_cut
; i
< sizeof (bdesc_cut
) / sizeof *d
; i
++, d
++)
9722 if (d
->code
== fcode
)
9723 return frv_expand_cut_builtin (d
->icode
, arglist
, target
);
9725 for (i
= 0, d
= bdesc_2argimm
;
9726 i
< sizeof (bdesc_2argimm
) / sizeof *d
;
9729 if (d
->code
== fcode
)
9730 return frv_expand_binopimm_builtin (d
->icode
, arglist
, target
);
9733 for (i
= 0, d
= bdesc_void2arg
;
9734 i
< sizeof (bdesc_void2arg
) / sizeof *d
;
9737 if (d
->code
== fcode
)
9738 return frv_expand_voidbinop_builtin (d
->icode
, arglist
);
9741 for (i
= 0, d
= bdesc_void3arg
;
9742 i
< sizeof (bdesc_void3arg
) / sizeof *d
;
9745 if (d
->code
== fcode
)
9746 return frv_expand_voidtriop_builtin (d
->icode
, arglist
);
9749 for (i
= 0, d
= bdesc_voidacc
;
9750 i
< sizeof (bdesc_voidacc
) / sizeof *d
;
9753 if (d
->code
== fcode
)
9754 return frv_expand_voidaccop_builtin (d
->icode
, arglist
);
9760 frv_strip_name_encoding (str
)
9763 while (*str
== '*' || *str
== SDATA_FLAG_CHAR
)
9769 frv_in_small_data_p (decl
)
9772 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
9774 return symbol_ref_small_data_p (XEXP (DECL_RTL (decl
), 0))
9775 && size
> 0 && size
<= g_switch_value
;