1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The integrated register allocator (IRA) is a
23 regional register allocator performing graph coloring on a top-down
24 traversal of nested regions. Graph coloring in a region is based
25 on Chaitin-Briggs algorithm. It is called integrated because
26 register coalescing, register live range splitting, and choosing a
27 better hard register are done on-the-fly during coloring. Register
28 coalescing and choosing a cheaper hard register is done by hard
29 register preferencing during hard register assigning. The live
30 range splitting is a byproduct of the regional register allocation.
32 Major IRA notions are:
34 o *Region* is a part of CFG where graph coloring based on
35 Chaitin-Briggs algorithm is done. IRA can work on any set of
36 nested CFG regions forming a tree. Currently the regions are
37 the entire function for the root region and natural loops for
38 the other regions. Therefore data structure representing a
39 region is called loop_tree_node.
41 o *Allocno class* is a register class used for allocation of
42 given allocno. It means that only hard register of given
43 register class can be assigned to given allocno. In reality,
44 even smaller subset of (*profitable*) hard registers can be
45 assigned. In rare cases, the subset can be even smaller
46 because our modification of Chaitin-Briggs algorithm requires
47 that sets of hard registers can be assigned to allocnos forms a
48 forest, i.e. the sets can be ordered in a way where any
49 previous set is not intersected with given set or is a superset
52 o *Pressure class* is a register class belonging to a set of
53 register classes containing all of the hard-registers available
54 for register allocation. The set of all pressure classes for a
55 target is defined in the corresponding machine-description file
56 according some criteria. Register pressure is calculated only
57 for pressure classes and it affects some IRA decisions as
58 forming allocation regions.
60 o *Allocno* represents the live range of a pseudo-register in a
61 region. Besides the obvious attributes like the corresponding
62 pseudo-register number, allocno class, conflicting allocnos and
63 conflicting hard-registers, there are a few allocno attributes
64 which are important for understanding the allocation algorithm:
66 - *Live ranges*. This is a list of ranges of *program points*
67 where the allocno lives. Program points represent places
68 where a pseudo can be born or become dead (there are
69 approximately two times more program points than the insns)
70 and they are represented by integers starting with 0. The
71 live ranges are used to find conflicts between allocnos.
72 They also play very important role for the transformation of
73 the IRA internal representation of several regions into a one
74 region representation. The later is used during the reload
75 pass work because each allocno represents all of the
76 corresponding pseudo-registers.
78 - *Hard-register costs*. This is a vector of size equal to the
79 number of available hard-registers of the allocno class. The
80 cost of a callee-clobbered hard-register for an allocno is
81 increased by the cost of save/restore code around the calls
82 through the given allocno's life. If the allocno is a move
83 instruction operand and another operand is a hard-register of
84 the allocno class, the cost of the hard-register is decreased
87 When an allocno is assigned, the hard-register with minimal
88 full cost is used. Initially, a hard-register's full cost is
89 the corresponding value from the hard-register's cost vector.
90 If the allocno is connected by a *copy* (see below) to
91 another allocno which has just received a hard-register, the
92 cost of the hard-register is decreased. Before choosing a
93 hard-register for an allocno, the allocno's current costs of
94 the hard-registers are modified by the conflict hard-register
95 costs of all of the conflicting allocnos which are not
98 - *Conflict hard-register costs*. This is a vector of the same
99 size as the hard-register costs vector. To permit an
100 unassigned allocno to get a better hard-register, IRA uses
101 this vector to calculate the final full cost of the
102 available hard-registers. Conflict hard-register costs of an
103 unassigned allocno are also changed with a change of the
104 hard-register cost of the allocno when a copy involving the
105 allocno is processed as described above. This is done to
106 show other unassigned allocnos that a given allocno prefers
107 some hard-registers in order to remove the move instruction
108 corresponding to the copy.
110 o *Cap*. If a pseudo-register does not live in a region but
111 lives in a nested region, IRA creates a special allocno called
112 a cap in the outer region. A region cap is also created for a
115 o *Copy*. Allocnos can be connected by copies. Copies are used
116 to modify hard-register costs for allocnos during coloring.
117 Such modifications reflects a preference to use the same
118 hard-register for the allocnos connected by copies. Usually
119 copies are created for move insns (in this case it results in
120 register coalescing). But IRA also creates copies for operands
121 of an insn which should be assigned to the same hard-register
122 due to constraints in the machine description (it usually
123 results in removing a move generated in reload to satisfy
124 the constraints) and copies referring to the allocno which is
125 the output operand of an instruction and the allocno which is
126 an input operand dying in the instruction (creation of such
127 copies results in less register shuffling). IRA *does not*
128 create copies between the same register allocnos from different
129 regions because we use another technique for propagating
130 hard-register preference on the borders of regions.
132 Allocnos (including caps) for the upper region in the region tree
133 *accumulate* information important for coloring from allocnos with
134 the same pseudo-register from nested regions. This includes
135 hard-register and memory costs, conflicts with hard-registers,
136 allocno conflicts, allocno copies and more. *Thus, attributes for
137 allocnos in a region have the same values as if the region had no
138 subregions*. It means that attributes for allocnos in the
139 outermost region corresponding to the function have the same values
140 as though the allocation used only one region which is the entire
141 function. It also means that we can look at IRA work as if the
142 first IRA did allocation for all function then it improved the
143 allocation for loops then their subloops and so on.
145 IRA major passes are:
147 o Building IRA internal representation which consists of the
150 * First, IRA builds regions and creates allocnos (file
151 ira-build.c) and initializes most of their attributes.
153 * Then IRA finds an allocno class for each allocno and
154 calculates its initial (non-accumulated) cost of memory and
155 each hard-register of its allocno class (file ira-cost.c).
157 * IRA creates live ranges of each allocno, calulates register
158 pressure for each pressure class in each region, sets up
159 conflict hard registers for each allocno and info about calls
160 the allocno lives through (file ira-lives.c).
162 * IRA removes low register pressure loops from the regions
163 mostly to speed IRA up (file ira-build.c).
165 * IRA propagates accumulated allocno info from lower region
166 allocnos to corresponding upper region allocnos (file
169 * IRA creates all caps (file ira-build.c).
171 * Having live-ranges of allocnos and their classes, IRA creates
172 conflicting allocnos for each allocno. Conflicting allocnos
173 are stored as a bit vector or array of pointers to the
174 conflicting allocnos whatever is more profitable (file
175 ira-conflicts.c). At this point IRA creates allocno copies.
177 o Coloring. Now IRA has all necessary info to start graph coloring
178 process. It is done in each region on top-down traverse of the
179 region tree (file ira-color.c). There are following subpasses:
181 * Finding profitable hard registers of corresponding allocno
182 class for each allocno. For example, only callee-saved hard
183 registers are frequently profitable for allocnos living
184 through colors. If the profitable hard register set of
185 allocno does not form a tree based on subset relation, we use
186 some approximation to form the tree. This approximation is
187 used to figure out trivial colorability of allocnos. The
188 approximation is a pretty rare case.
190 * Putting allocnos onto the coloring stack. IRA uses Briggs
191 optimistic coloring which is a major improvement over
192 Chaitin's coloring. Therefore IRA does not spill allocnos at
193 this point. There is some freedom in the order of putting
194 allocnos on the stack which can affect the final result of
195 the allocation. IRA uses some heuristics to improve the
198 We also use a modification of Chaitin-Briggs algorithm which
199 works for intersected register classes of allocnos. To
200 figure out trivial colorability of allocnos, the mentioned
201 above tree of hard register sets is used. To get an idea how
202 the algorithm works in i386 example, let us consider an
203 allocno to which any general hard register can be assigned.
204 If the allocno conflicts with eight allocnos to which only
205 EAX register can be assigned, given allocno is still
206 trivially colorable because all conflicting allocnos might be
207 assigned only to EAX and all other general hard registers are
210 To get an idea of the used trivial colorability criterion, it
211 is also useful to read article "Graph-Coloring Register
212 Allocation for Irregular Architectures" by Michael D. Smith
213 and Glen Holloway. Major difference between the article
214 approach and approach used in IRA is that Smith's approach
215 takes register classes only from machine description and IRA
216 calculate register classes from intermediate code too
217 (e.g. an explicit usage of hard registers in RTL code for
218 parameter passing can result in creation of additional
219 register classes which contain or exclude the hard
220 registers). That makes IRA approach useful for improving
221 coloring even for architectures with regular register files
222 and in fact some benchmarking shows the improvement for
223 regular class architectures is even bigger than for irregular
224 ones. Another difference is that Smith's approach chooses
225 intersection of classes of all insn operands in which a given
226 pseudo occurs. IRA can use bigger classes if it is still
227 more profitable than memory usage.
229 * Popping the allocnos from the stack and assigning them hard
230 registers. If IRA can not assign a hard register to an
231 allocno and the allocno is coalesced, IRA undoes the
232 coalescing and puts the uncoalesced allocnos onto the stack in
233 the hope that some such allocnos will get a hard register
234 separately. If IRA fails to assign hard register or memory
235 is more profitable for it, IRA spills the allocno. IRA
236 assigns the allocno the hard-register with minimal full
237 allocation cost which reflects the cost of usage of the
238 hard-register for the allocno and cost of usage of the
239 hard-register for allocnos conflicting with given allocno.
241 * Chaitin-Briggs coloring assigns as many pseudos as possible
242 to hard registers. After coloringh we try to improve
243 allocation with cost point of view. We improve the
244 allocation by spilling some allocnos and assigning the freed
245 hard registers to other allocnos if it decreases the overall
248 * After allono assigning in the region, IRA modifies the hard
249 register and memory costs for the corresponding allocnos in
250 the subregions to reflect the cost of possible loads, stores,
251 or moves on the border of the region and its subregions.
252 When default regional allocation algorithm is used
253 (-fira-algorithm=mixed), IRA just propagates the assignment
254 for allocnos if the register pressure in the region for the
255 corresponding pressure class is less than number of available
256 hard registers for given pressure class.
258 o Spill/restore code moving. When IRA performs an allocation
259 by traversing regions in top-down order, it does not know what
260 happens below in the region tree. Therefore, sometimes IRA
261 misses opportunities to perform a better allocation. A simple
262 optimization tries to improve allocation in a region having
263 subregions and containing in another region. If the
264 corresponding allocnos in the subregion are spilled, it spills
265 the region allocno if it is profitable. The optimization
266 implements a simple iterative algorithm performing profitable
267 transformations while they are still possible. It is fast in
268 practice, so there is no real need for a better time complexity
271 o Code change. After coloring, two allocnos representing the
272 same pseudo-register outside and inside a region respectively
273 may be assigned to different locations (hard-registers or
274 memory). In this case IRA creates and uses a new
275 pseudo-register inside the region and adds code to move allocno
276 values on the region's borders. This is done during top-down
277 traversal of the regions (file ira-emit.c). In some
278 complicated cases IRA can create a new allocno to move allocno
279 values (e.g. when a swap of values stored in two hard-registers
280 is needed). At this stage, the new allocno is marked as
281 spilled. IRA still creates the pseudo-register and the moves
282 on the region borders even when both allocnos were assigned to
283 the same hard-register. If the reload pass spills a
284 pseudo-register for some reason, the effect will be smaller
285 because another allocno will still be in the hard-register. In
286 most cases, this is better then spilling both allocnos. If
287 reload does not change the allocation for the two
288 pseudo-registers, the trivial move will be removed by
289 post-reload optimizations. IRA does not generate moves for
290 allocnos assigned to the same hard register when the default
291 regional allocation algorithm is used and the register pressure
292 in the region for the corresponding pressure class is less than
293 number of available hard registers for given pressure class.
294 IRA also does some optimizations to remove redundant stores and
295 to reduce code duplication on the region borders.
297 o Flattening internal representation. After changing code, IRA
298 transforms its internal representation for several regions into
299 one region representation (file ira-build.c). This process is
300 called IR flattening. Such process is more complicated than IR
301 rebuilding would be, but is much faster.
303 o After IR flattening, IRA tries to assign hard registers to all
304 spilled allocnos. This is impelemented by a simple and fast
305 priority coloring algorithm (see function
306 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
307 created during the code change pass can be assigned to hard
310 o At the end IRA calls the reload pass. The reload pass
311 communicates with IRA through several functions in file
312 ira-color.c to improve its decisions in
314 * sharing stack slots for the spilled pseudos based on IRA info
315 about pseudo-register conflicts.
317 * reassigning hard-registers to all spilled pseudos at the end
318 of each reload iteration.
320 * choosing a better hard-register to spill based on IRA info
321 about pseudo-register live ranges and the register pressure
322 in places where the pseudo-register lives.
324 IRA uses a lot of data representing the target processors. These
325 data are initilized in file ira.c.
327 If function has no loops (or the loops are ignored when
328 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
329 coloring (only instead of separate pass of coalescing, we use hard
330 register preferencing). In such case, IRA works much faster
331 because many things are not made (like IR flattening, the
332 spill/restore optimization, and the code change).
334 Literature is worth to read for better understanding the code:
336 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
337 Graph Coloring Register Allocation.
339 o David Callahan, Brian Koblenz. Register allocation via
340 hierarchical graph coloring.
342 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
343 Coloring Register Allocation: A Study of the Chaitin-Briggs and
344 Callahan-Koblenz Algorithms.
346 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
347 Register Allocation Based on Graph Fusion.
349 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
350 Allocation for Irregular Architectures
352 o Vladimir Makarov. The Integrated Register Allocator for GCC.
354 o Vladimir Makarov. The top-down register allocator for irregular
355 register file architectures.
362 #include "coretypes.h"
371 #include "hard-reg-set.h"
372 #include "basic-block.h"
377 #include "tree-pass.h"
381 #include "diagnostic-core.h"
382 #include "function.h"
388 struct target_ira default_target_ira
;
389 struct target_ira_int default_target_ira_int
;
390 #if SWITCHABLE_TARGET
391 struct target_ira
*this_target_ira
= &default_target_ira
;
392 struct target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
395 /* A modified value of flag `-fira-verbose' used internally. */
396 int internal_flag_ira_verbose
;
398 /* Dump file of the allocator if it is not NULL. */
401 /* The number of elements in the following array. */
402 int ira_spilled_reg_stack_slots_num
;
404 /* The following array contains info about spilled pseudo-registers
405 stack slots used in current function so far. */
406 struct ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
408 /* Correspondingly overall cost of the allocation, overall cost before
409 reload, cost of the allocnos assigned to hard-registers, cost of
410 the allocnos assigned to memory, cost of loads, stores and register
411 move insns generated for pseudo-register live range splitting (see
413 int ira_overall_cost
, overall_cost_before
;
414 int ira_reg_cost
, ira_mem_cost
;
415 int ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
416 int ira_move_loops_num
, ira_additional_jumps_num
;
418 /* All registers that can be eliminated. */
420 HARD_REG_SET eliminable_regset
;
422 /* Temporary hard reg set used for a different calculation. */
423 static HARD_REG_SET temp_hard_regset
;
425 #define last_mode_for_init_move_cost \
426 (this_target_ira_int->x_last_mode_for_init_move_cost)
429 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
431 setup_reg_mode_hard_regset (void)
433 int i
, m
, hard_regno
;
435 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
436 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
438 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
439 for (i
= hard_regno_nregs
[hard_regno
][m
] - 1; i
>= 0; i
--)
440 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
441 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
447 #define no_unit_alloc_regs \
448 (this_target_ira_int->x_no_unit_alloc_regs)
450 /* The function sets up the three arrays declared above. */
452 setup_class_hard_regs (void)
454 int cl
, i
, hard_regno
, n
;
455 HARD_REG_SET processed_hard_reg_set
;
457 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
458 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
460 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
461 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
462 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
463 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
465 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
466 ira_class_hard_reg_index
[cl
][i
] = -1;
468 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
470 #ifdef REG_ALLOC_ORDER
471 hard_regno
= reg_alloc_order
[i
];
475 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
477 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
478 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
479 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
482 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
483 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
486 ira_class_hard_regs_num
[cl
] = n
;
487 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
488 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
489 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
490 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
494 /* Set up global variables defining info about hard registers for the
495 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
496 that we can use the hard frame pointer for the allocation. */
498 setup_alloc_regs (bool use_hard_frame_p
)
500 #ifdef ADJUST_REG_ALLOC_ORDER
501 ADJUST_REG_ALLOC_ORDER
;
503 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_reg_set
);
504 if (! use_hard_frame_p
)
505 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
506 setup_class_hard_regs ();
511 #define alloc_reg_class_subclasses \
512 (this_target_ira_int->x_alloc_reg_class_subclasses)
514 /* Initialize the table of subclasses of each reg class. */
516 setup_reg_subclasses (void)
519 HARD_REG_SET temp_hard_regset2
;
521 for (i
= 0; i
< N_REG_CLASSES
; i
++)
522 for (j
= 0; j
< N_REG_CLASSES
; j
++)
523 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
525 for (i
= 0; i
< N_REG_CLASSES
; i
++)
527 if (i
== (int) NO_REGS
)
530 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
531 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
532 if (hard_reg_set_empty_p (temp_hard_regset
))
534 for (j
= 0; j
< N_REG_CLASSES
; j
++)
539 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[j
]);
540 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
541 if (! hard_reg_set_subset_p (temp_hard_regset
,
544 p
= &alloc_reg_class_subclasses
[j
][0];
545 while (*p
!= LIM_REG_CLASSES
) p
++;
546 *p
= (enum reg_class
) i
;
553 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
555 setup_class_subset_and_memory_move_costs (void)
557 int cl
, cl2
, mode
, cost
;
558 HARD_REG_SET temp_hard_regset2
;
560 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
561 ira_memory_move_cost
[mode
][NO_REGS
][0]
562 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
563 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
565 if (cl
!= (int) NO_REGS
)
566 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
568 ira_max_memory_move_cost
[mode
][cl
][0]
569 = ira_memory_move_cost
[mode
][cl
][0]
570 = memory_move_cost ((enum machine_mode
) mode
,
571 (reg_class_t
) cl
, false);
572 ira_max_memory_move_cost
[mode
][cl
][1]
573 = ira_memory_move_cost
[mode
][cl
][1]
574 = memory_move_cost ((enum machine_mode
) mode
,
575 (reg_class_t
) cl
, true);
576 /* Costs for NO_REGS are used in cost calculation on the
577 1st pass when the preferred register classes are not
578 known yet. In this case we take the best scenario. */
579 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
580 > ira_memory_move_cost
[mode
][cl
][0])
581 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
582 = ira_memory_move_cost
[mode
][NO_REGS
][0]
583 = ira_memory_move_cost
[mode
][cl
][0];
584 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
585 > ira_memory_move_cost
[mode
][cl
][1])
586 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
587 = ira_memory_move_cost
[mode
][NO_REGS
][1]
588 = ira_memory_move_cost
[mode
][cl
][1];
591 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
592 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
594 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
595 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
596 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
597 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
598 ira_class_subset_p
[cl
][cl2
]
599 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
600 if (! hard_reg_set_empty_p (temp_hard_regset2
)
601 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
602 reg_class_contents
[cl
]))
603 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
605 cost
= ira_memory_move_cost
[mode
][cl2
][0];
606 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
607 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
608 cost
= ira_memory_move_cost
[mode
][cl2
][1];
609 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
610 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
613 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
614 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
616 ira_memory_move_cost
[mode
][cl
][0]
617 = ira_max_memory_move_cost
[mode
][cl
][0];
618 ira_memory_move_cost
[mode
][cl
][1]
619 = ira_max_memory_move_cost
[mode
][cl
][1];
621 setup_reg_subclasses ();
626 /* Define the following macro if allocation through malloc if
628 #define IRA_NO_OBSTACK
630 #ifndef IRA_NO_OBSTACK
631 /* Obstack used for storing all dynamic data (except bitmaps) of the
633 static struct obstack ira_obstack
;
636 /* Obstack used for storing all bitmaps of the IRA. */
637 static struct bitmap_obstack ira_bitmap_obstack
;
639 /* Allocate memory of size LEN for IRA data. */
641 ira_allocate (size_t len
)
645 #ifndef IRA_NO_OBSTACK
646 res
= obstack_alloc (&ira_obstack
, len
);
653 /* Free memory ADDR allocated for IRA data. */
655 ira_free (void *addr ATTRIBUTE_UNUSED
)
657 #ifndef IRA_NO_OBSTACK
665 /* Allocate and returns bitmap for IRA. */
667 ira_allocate_bitmap (void)
669 return BITMAP_ALLOC (&ira_bitmap_obstack
);
672 /* Free bitmap B allocated for IRA. */
674 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
681 /* Output information about allocation of all allocnos (except for
682 caps) into file F. */
684 ira_print_disposition (FILE *f
)
690 fprintf (f
, "Disposition:");
691 max_regno
= max_reg_num ();
692 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
693 for (a
= ira_regno_allocno_map
[i
];
695 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
700 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
701 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
702 fprintf (f
, "b%-3d", bb
->index
);
704 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
705 if (ALLOCNO_HARD_REGNO (a
) >= 0)
706 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
713 /* Outputs information about allocation of all allocnos into
716 ira_debug_disposition (void)
718 ira_print_disposition (stderr
);
723 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
724 register class containing stack registers or NO_REGS if there are
725 no stack registers. To find this class, we iterate through all
726 register pressure classes and choose the first register pressure
727 class containing all the stack registers and having the biggest
730 setup_stack_reg_pressure_class (void)
732 ira_stack_reg_pressure_class
= NO_REGS
;
737 HARD_REG_SET temp_hard_regset2
;
739 CLEAR_HARD_REG_SET (temp_hard_regset
);
740 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
741 SET_HARD_REG_BIT (temp_hard_regset
, i
);
743 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
745 cl
= ira_pressure_classes
[i
];
746 COPY_HARD_REG_SET (temp_hard_regset2
, temp_hard_regset
);
747 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
748 size
= hard_reg_set_size (temp_hard_regset2
);
752 ira_stack_reg_pressure_class
= cl
;
759 /* Find pressure classes which are register classes for which we
760 calculate register pressure in IRA, register pressure sensitive
761 insn scheduling, and register pressure sensitive loop invariant
764 To make register pressure calculation easy, we always use
765 non-intersected register pressure classes. A move of hard
766 registers from one register pressure class is not more expensive
767 than load and store of the hard registers. Most likely an allocno
768 class will be a subset of a register pressure class and in many
769 cases a register pressure class. That makes usage of register
770 pressure classes a good approximation to find a high register
773 setup_pressure_classes (void)
775 int cost
, i
, n
, curr
;
777 enum reg_class pressure_classes
[N_REG_CLASSES
];
779 HARD_REG_SET temp_hard_regset2
;
783 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
785 if (ira_class_hard_regs_num
[cl
] == 0)
787 if (ira_class_hard_regs_num
[cl
] != 1
788 /* A register class without subclasses may contain a few
789 hard registers and movement between them is costly
790 (e.g. SPARC FPCC registers). We still should consider it
791 as a candidate for a pressure class. */
792 && alloc_reg_class_subclasses
[cl
][0] != LIM_REG_CLASSES
)
794 /* Check that the moves between any hard registers of the
795 current class are not more expensive for a legal mode
796 than load/store of the hard registers of the current
797 class. Such class is a potential candidate to be a
798 register pressure class. */
799 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
801 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
802 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
803 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
804 ira_prohibited_class_mode_regs
[cl
][m
]);
805 if (hard_reg_set_empty_p (temp_hard_regset
))
807 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
808 cost
= ira_register_move_cost
[m
][cl
][cl
];
809 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
810 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
813 if (m
>= NUM_MACHINE_MODES
)
818 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
819 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
820 /* Remove so far added pressure classes which are subset of the
821 current candidate class. Prefer GENERAL_REGS as a pressure
822 register class to another class containing the same
823 allocatable hard registers. We do this because machine
824 dependent cost hooks might give wrong costs for the latter
825 class but always give the right cost for the former class
827 for (i
= 0; i
< n
; i
++)
829 cl2
= pressure_classes
[i
];
830 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
831 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
832 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
833 && (! hard_reg_set_equal_p (temp_hard_regset
, temp_hard_regset2
)
834 || cl2
== (int) GENERAL_REGS
))
836 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
840 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
841 && (! hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
)
842 || cl
== (int) GENERAL_REGS
))
844 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
846 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
848 /* If the current candidate is a subset of a so far added
849 pressure class, don't add it to the list of the pressure
852 pressure_classes
[curr
++] = (enum reg_class
) cl
;
855 #ifdef ENABLE_IRA_CHECKING
857 HARD_REG_SET ignore_hard_regs
;
859 /* Check pressure classes correctness: here we check that hard
860 registers from all register pressure classes contains all hard
861 registers available for the allocation. */
862 CLEAR_HARD_REG_SET (temp_hard_regset
);
863 CLEAR_HARD_REG_SET (temp_hard_regset2
);
864 COPY_HARD_REG_SET (ignore_hard_regs
, no_unit_alloc_regs
);
865 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
867 /* For some targets (like MIPS with MD_REGS), there are some
868 classes with hard registers available for allocation but
869 not able to hold value of any mode. */
870 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
871 if (contains_reg_of_mode
[cl
][m
])
873 if (m
>= NUM_MACHINE_MODES
)
875 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
878 for (i
= 0; i
< n
; i
++)
879 if ((int) pressure_classes
[i
] == cl
)
881 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
883 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
885 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
886 /* Some targets (like SPARC with ICC reg) have alocatable regs
887 for which no reg class is defined. */
888 if (REGNO_REG_CLASS (i
) == NO_REGS
)
889 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
890 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
891 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
892 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
895 ira_pressure_classes_num
= 0;
896 for (i
= 0; i
< n
; i
++)
898 cl
= (int) pressure_classes
[i
];
899 ira_reg_pressure_class_p
[cl
] = true;
900 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
902 setup_stack_reg_pressure_class ();
905 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
906 whose register move cost between any registers of the class is the
907 same as for all its subclasses. We use the data to speed up the
908 2nd pass of calculations of allocno costs. */
910 setup_uniform_class_p (void)
914 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
916 ira_uniform_class_p
[cl
] = false;
917 if (ira_class_hard_regs_num
[cl
] == 0)
919 /* We can not use alloc_reg_class_subclasses here because move
920 cost hooks does not take into account that some registers are
921 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
922 is element of alloc_reg_class_subclasses for GENERAL_REGS
923 because SSE regs are unavailable. */
924 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
926 if (ira_class_hard_regs_num
[cl2
] == 0)
928 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
929 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
931 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
932 if (ira_register_move_cost
[m
][cl
][cl
]
933 != ira_register_move_cost
[m
][cl2
][cl2
])
936 if (m
< NUM_MACHINE_MODES
)
939 if (cl2
== LIM_REG_CLASSES
)
940 ira_uniform_class_p
[cl
] = true;
944 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
945 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
947 Target may have many subtargets and not all target hard regiters can
948 be used for allocation, e.g. x86 port in 32-bit mode can not use
949 hard registers introduced in x86-64 like r8-r15). Some classes
950 might have the same allocatable hard registers, e.g. INDEX_REGS
951 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
952 calculations efforts we introduce allocno classes which contain
953 unique non-empty sets of allocatable hard-registers.
955 Pseudo class cost calculation in ira-costs.c is very expensive.
956 Therefore we are trying to decrease number of classes involved in
957 such calculation. Register classes used in the cost calculation
958 are called important classes. They are allocno classes and other
959 non-empty classes whose allocatable hard register sets are inside
960 of an allocno class hard register set. From the first sight, it
961 looks like that they are just allocno classes. It is not true. In
962 example of x86-port in 32-bit mode, allocno classes will contain
963 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
964 registers are the same for the both classes). The important
965 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
966 because a machine description insn constraint may refers for
967 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
968 of the insn constraints. */
970 setup_allocno_and_important_classes (void)
974 HARD_REG_SET temp_hard_regset2
;
975 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
978 /* Collect classes which contain unique sets of allocatable hard
979 registers. Prefer GENERAL_REGS to other classes containing the
980 same set of hard registers. */
981 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
983 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
984 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
985 for (j
= 0; j
< n
; j
++)
988 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
989 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
991 if (hard_reg_set_equal_p (temp_hard_regset
,
996 classes
[n
++] = (enum reg_class
) i
;
997 else if (i
== GENERAL_REGS
)
998 /* Prefer general regs. For i386 example, it means that
999 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1000 (all of them consists of the same available hard
1002 classes
[j
] = (enum reg_class
) i
;
1004 classes
[n
] = LIM_REG_CLASSES
;
1006 /* Set up classes which can be used for allocnos as classes
1007 conatining non-empty unique sets of allocatable hard
1009 ira_allocno_classes_num
= 0;
1010 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1011 if (ira_class_hard_regs_num
[cl
] > 0)
1012 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1013 ira_important_classes_num
= 0;
1014 /* Add non-allocno classes containing to non-empty set of
1015 allocatable hard regs. */
1016 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1017 if (ira_class_hard_regs_num
[cl
] > 0)
1019 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1020 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1022 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1024 COPY_HARD_REG_SET (temp_hard_regset2
,
1025 reg_class_contents
[ira_allocno_classes
[j
]]);
1026 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1027 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1029 else if (hard_reg_set_subset_p (temp_hard_regset
,
1033 if (set_p
&& j
>= ira_allocno_classes_num
)
1034 ira_important_classes
[ira_important_classes_num
++]
1035 = (enum reg_class
) cl
;
1037 /* Now add allocno classes to the important classes. */
1038 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1039 ira_important_classes
[ira_important_classes_num
++]
1040 = ira_allocno_classes
[j
];
1041 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1043 ira_reg_allocno_class_p
[cl
] = false;
1044 ira_reg_pressure_class_p
[cl
] = false;
1046 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1047 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1048 setup_pressure_classes ();
1049 setup_uniform_class_p ();
1052 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1053 given by array CLASSES of length CLASSES_NUM. The function is used
1054 make translation any reg class to an allocno class or to an
1055 pressure class. This translation is necessary for some
1056 calculations when we can use only allocno or pressure classes and
1057 such translation represents an approximate representation of all
1060 The translation in case when allocatable hard register set of a
1061 given class is subset of allocatable hard register set of a class
1062 in CLASSES is pretty simple. We use smallest classes from CLASSES
1063 containing a given class. If allocatable hard register set of a
1064 given class is not a subset of any corresponding set of a class
1065 from CLASSES, we use the cheapest (with load/store point of view)
1066 class from CLASSES whose set intersects with given class set */
1068 setup_class_translate_array (enum reg_class
*class_translate
,
1069 int classes_num
, enum reg_class
*classes
)
1072 enum reg_class aclass
, best_class
, *cl_ptr
;
1073 int i
, cost
, min_cost
, best_cost
;
1075 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1076 class_translate
[cl
] = NO_REGS
;
1078 for (i
= 0; i
< classes_num
; i
++)
1080 aclass
= classes
[i
];
1081 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1082 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1084 if (class_translate
[cl
] == NO_REGS
)
1085 class_translate
[cl
] = aclass
;
1086 class_translate
[aclass
] = aclass
;
1088 /* For classes which are not fully covered by one of given classes
1089 (in other words covered by more one given class), use the
1091 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1093 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1095 best_class
= NO_REGS
;
1096 best_cost
= INT_MAX
;
1097 for (i
= 0; i
< classes_num
; i
++)
1099 aclass
= classes
[i
];
1100 COPY_HARD_REG_SET (temp_hard_regset
,
1101 reg_class_contents
[aclass
]);
1102 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1103 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1104 if (! hard_reg_set_empty_p (temp_hard_regset
))
1107 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1109 cost
= (ira_memory_move_cost
[mode
][cl
][0]
1110 + ira_memory_move_cost
[mode
][cl
][1]);
1111 if (min_cost
> cost
)
1114 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1116 best_class
= aclass
;
1117 best_cost
= min_cost
;
1121 class_translate
[cl
] = best_class
;
1125 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1126 IRA_PRESSURE_CLASS_TRANSLATE. */
1128 setup_class_translate (void)
1130 setup_class_translate_array (ira_allocno_class_translate
,
1131 ira_allocno_classes_num
, ira_allocno_classes
);
1132 setup_class_translate_array (ira_pressure_class_translate
,
1133 ira_pressure_classes_num
, ira_pressure_classes
);
1136 /* Order numbers of allocno classes in original target allocno class
1137 array, -1 for non-allocno classes. */
1138 static int allocno_class_order
[N_REG_CLASSES
];
1140 /* The function used to sort the important classes. */
1142 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1144 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1145 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1146 enum reg_class tcl1
, tcl2
;
1149 tcl1
= ira_allocno_class_translate
[cl1
];
1150 tcl2
= ira_allocno_class_translate
[cl2
];
1151 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1152 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1154 return (int) cl1
- (int) cl2
;
1157 /* For correct work of function setup_reg_class_relation we need to
1158 reorder important classes according to the order of their allocno
1159 classes. It places important classes containing the same
1160 allocatable hard register set adjacent to each other and allocno
1161 class with the allocatable hard register set right after the other
1162 important classes with the same set.
1164 In example from comments of function
1165 setup_allocno_and_important_classes, it places LEGACY_REGS and
1166 GENERAL_REGS close to each other and GENERAL_REGS is after
1169 reorder_important_classes (void)
1173 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1174 allocno_class_order
[i
] = -1;
1175 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1176 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1177 qsort (ira_important_classes
, ira_important_classes_num
,
1178 sizeof (enum reg_class
), comp_reg_classes_func
);
1179 for (i
= 0; i
< ira_important_classes_num
; i
++)
1180 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1183 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1184 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1185 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1186 please see corresponding comments in ira-int.h. */
1188 setup_reg_class_relations (void)
1190 int i
, cl1
, cl2
, cl3
;
1191 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1192 bool important_class_p
[N_REG_CLASSES
];
1194 memset (important_class_p
, 0, sizeof (important_class_p
));
1195 for (i
= 0; i
< ira_important_classes_num
; i
++)
1196 important_class_p
[ira_important_classes
[i
]] = true;
1197 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1199 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1200 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1202 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1203 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1204 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl1
]);
1205 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1206 COPY_HARD_REG_SET (temp_set2
, reg_class_contents
[cl2
]);
1207 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1208 if (hard_reg_set_empty_p (temp_hard_regset
)
1209 && hard_reg_set_empty_p (temp_set2
))
1211 /* The both classes have no allocatable hard registers
1212 -- take all class hard registers into account and use
1213 reg_class_subunion and reg_class_superunion. */
1216 cl3
= reg_class_subclasses
[cl1
][i
];
1217 if (cl3
== LIM_REG_CLASSES
)
1219 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1220 (enum reg_class
) cl3
))
1221 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1223 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1224 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1227 ira_reg_classes_intersect_p
[cl1
][cl2
]
1228 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1229 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1230 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1232 /* CL1 and CL2 are important classes and CL1 allocatable
1233 hard register set is inside of CL2 allocatable hard
1234 registers -- make CL1 a superset of CL2. */
1237 p
= &ira_reg_class_super_classes
[cl1
][0];
1238 while (*p
!= LIM_REG_CLASSES
)
1240 *p
++ = (enum reg_class
) cl2
;
1241 *p
= LIM_REG_CLASSES
;
1243 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1244 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1245 COPY_HARD_REG_SET (intersection_set
, reg_class_contents
[cl1
]);
1246 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1247 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1248 COPY_HARD_REG_SET (union_set
, reg_class_contents
[cl1
]);
1249 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1250 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1251 for (i
= 0; i
< ira_important_classes_num
; i
++)
1253 cl3
= ira_important_classes
[i
];
1254 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl3
]);
1255 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1256 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1258 /* CL3 allocatable hard register set is inside of
1259 intersection of allocatable hard register sets
1263 reg_class_contents
[(int)
1264 ira_reg_class_intersect
[cl1
][cl2
]]);
1265 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1266 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1267 /* If the allocatable hard register sets are the
1268 same, prefer GENERAL_REGS or the smallest
1269 class for debugging purposes. */
1270 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1271 && (cl3
== GENERAL_REGS
1272 || (ira_reg_class_intersect
[cl1
][cl2
] != GENERAL_REGS
1273 && hard_reg_set_subset_p
1274 (reg_class_contents
[cl3
],
1276 [(int) ira_reg_class_intersect
[cl1
][cl2
]])))))
1277 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1279 if (hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1281 /* CL3 allocatbale hard register set is inside of
1282 union of allocatable hard register sets of CL1
1286 reg_class_contents
[(int) ira_reg_class_subunion
[cl1
][cl2
]]);
1287 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1288 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1289 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1291 && (! hard_reg_set_equal_p (temp_set2
,
1293 || cl3
== GENERAL_REGS
1294 /* If the allocatable hard register sets are the
1295 same, prefer GENERAL_REGS or the smallest
1296 class for debugging purposes. */
1297 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1298 && hard_reg_set_subset_p
1299 (reg_class_contents
[cl3
],
1301 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1302 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1304 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1306 /* CL3 allocatable hard register set contains union
1307 of allocatable hard register sets of CL1 and
1311 reg_class_contents
[(int) ira_reg_class_superunion
[cl1
][cl2
]]);
1312 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1313 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1314 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1316 && (! hard_reg_set_equal_p (temp_set2
,
1318 || cl3
== GENERAL_REGS
1319 /* If the allocatable hard register sets are the
1320 same, prefer GENERAL_REGS or the smallest
1321 class for debugging purposes. */
1322 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1323 && hard_reg_set_subset_p
1324 (reg_class_contents
[cl3
],
1326 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1327 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1334 /* Output all unifrom and important classes into file F. */
1336 print_unform_and_important_classes (FILE *f
)
1338 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1341 fprintf (f
, "Uniform classes:\n");
1342 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1343 if (ira_uniform_class_p
[cl
])
1344 fprintf (f
, " %s", reg_class_names
[cl
]);
1345 fprintf (f
, "\nImportant classes:\n");
1346 for (i
= 0; i
< ira_important_classes_num
; i
++)
1347 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1351 /* Output all possible allocno or pressure classes and their
1352 translation map into file F. */
1354 print_translated_classes (FILE *f
, bool pressure_p
)
1356 int classes_num
= (pressure_p
1357 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1358 enum reg_class
*classes
= (pressure_p
1359 ? ira_pressure_classes
: ira_allocno_classes
);
1360 enum reg_class
*class_translate
= (pressure_p
1361 ? ira_pressure_class_translate
1362 : ira_allocno_class_translate
);
1363 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1366 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1367 for (i
= 0; i
< classes_num
; i
++)
1368 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1369 fprintf (f
, "\nClass translation:\n");
1370 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1371 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1372 reg_class_names
[class_translate
[i
]]);
1375 /* Output all possible allocno and translation classes and the
1376 translation maps into stderr. */
1378 ira_debug_allocno_classes (void)
1380 print_unform_and_important_classes (stderr
);
1381 print_translated_classes (stderr
, false);
1382 print_translated_classes (stderr
, true);
1385 /* Set up different arrays concerning class subsets, allocno and
1386 important classes. */
1388 find_reg_classes (void)
1390 setup_allocno_and_important_classes ();
1391 setup_class_translate ();
1392 reorder_important_classes ();
1393 setup_reg_class_relations ();
1398 /* Set up the array above. */
1400 setup_hard_regno_aclass (void)
1404 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1407 ira_hard_regno_allocno_class
[i
]
1408 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1410 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1414 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1415 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1417 cl
= ira_allocno_classes
[j
];
1418 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1420 ira_hard_regno_allocno_class
[i
] = cl
;
1430 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1432 setup_reg_class_nregs (void)
1436 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1438 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1439 ira_reg_class_max_nregs
[cl
][m
]
1440 = ira_reg_class_min_nregs
[cl
][m
]
1441 = targetm
.class_max_nregs ((reg_class_t
) cl
, (enum machine_mode
) m
);
1442 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1444 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1446 if (ira_reg_class_min_nregs
[cl2
][m
]
1447 < ira_reg_class_min_nregs
[cl
][m
])
1448 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1454 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS. */
1456 setup_prohibited_class_mode_regs (void)
1458 int j
, k
, hard_regno
, cl
;
1460 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1462 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1464 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1465 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1467 hard_regno
= ira_class_hard_regs
[cl
][k
];
1468 if (! HARD_REGNO_MODE_OK (hard_regno
, (enum machine_mode
) j
))
1469 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1476 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1477 spanning from one register pressure class to another one. It is
1478 called after defining the pressure classes. */
1480 clarify_prohibited_class_mode_regs (void)
1482 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1484 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1485 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1486 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1488 hard_regno
= ira_class_hard_regs
[cl
][k
];
1489 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1491 nregs
= hard_regno_nregs
[hard_regno
][j
];
1492 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1494 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1498 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1499 for (nregs
-- ;nregs
>= 0; nregs
--)
1500 if (((enum reg_class
) pclass
1501 != ira_pressure_class_translate
[REGNO_REG_CLASS
1502 (hard_regno
+ nregs
)]))
1504 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1511 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1512 and IRA_MAY_MOVE_OUT_COST for MODE. */
1514 ira_init_register_move_cost (enum machine_mode mode
)
1516 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1517 bool all_match
= true;
1518 unsigned int cl1
, cl2
;
1520 ira_assert (ira_register_move_cost
[mode
] == NULL
1521 && ira_may_move_in_cost
[mode
] == NULL
1522 && ira_may_move_out_cost
[mode
] == NULL
);
1523 ira_assert (have_regs_of_mode
[mode
]);
1524 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1525 if (contains_reg_of_mode
[cl1
][mode
])
1526 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1529 if (!contains_reg_of_mode
[cl2
][mode
])
1533 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1534 (enum reg_class
) cl2
);
1535 ira_assert (cost
< 65535);
1537 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1538 last_move_cost
[cl1
][cl2
] = cost
;
1540 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1542 ira_register_move_cost
[mode
]
1543 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1544 ira_may_move_in_cost
[mode
]
1545 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1546 ira_may_move_out_cost
[mode
]
1547 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1550 last_mode_for_init_move_cost
= mode
;
1551 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1552 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1553 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1554 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1555 if (contains_reg_of_mode
[cl1
][mode
])
1556 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1559 enum reg_class
*p1
, *p2
;
1561 if (last_move_cost
[cl1
][cl2
] == 65535)
1563 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1564 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1565 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1569 cost
= last_move_cost
[cl1
][cl2
];
1571 for (p2
= ®_class_subclasses
[cl2
][0];
1572 *p2
!= LIM_REG_CLASSES
; p2
++)
1573 if (ira_class_hard_regs_num
[*p2
] > 0
1574 && (ira_reg_class_max_nregs
[*p2
][mode
]
1575 <= ira_class_hard_regs_num
[*p2
]))
1576 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1578 for (p1
= ®_class_subclasses
[cl1
][0];
1579 *p1
!= LIM_REG_CLASSES
; p1
++)
1580 if (ira_class_hard_regs_num
[*p1
] > 0
1581 && (ira_reg_class_max_nregs
[*p1
][mode
]
1582 <= ira_class_hard_regs_num
[*p1
]))
1583 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1585 ira_assert (cost
<= 65535);
1586 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1588 if (ira_class_subset_p
[cl1
][cl2
])
1589 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1591 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1593 if (ira_class_subset_p
[cl2
][cl1
])
1594 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1596 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1600 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1602 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1603 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1604 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1609 /* This is called once during compiler work. It sets up
1610 different arrays whose values don't depend on the compiled
1613 ira_init_once (void)
1615 ira_init_costs_once ();
1618 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1619 ira_may_move_out_cost for each mode. */
1621 free_register_move_costs (void)
1625 /* Reset move_cost and friends, making sure we only free shared
1626 table entries once. */
1627 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1628 if (ira_register_move_cost
[mode
])
1631 i
< mode
&& (ira_register_move_cost
[i
]
1632 != ira_register_move_cost
[mode
]);
1637 free (ira_register_move_cost
[mode
]);
1638 free (ira_may_move_in_cost
[mode
]);
1639 free (ira_may_move_out_cost
[mode
]);
1642 memset (ira_register_move_cost
, 0, sizeof ira_register_move_cost
);
1643 memset (ira_may_move_in_cost
, 0, sizeof ira_may_move_in_cost
);
1644 memset (ira_may_move_out_cost
, 0, sizeof ira_may_move_out_cost
);
1645 last_mode_for_init_move_cost
= -1;
1648 /* This is called every time when register related information is
1653 free_register_move_costs ();
1654 setup_reg_mode_hard_regset ();
1655 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1656 setup_class_subset_and_memory_move_costs ();
1657 setup_reg_class_nregs ();
1658 setup_prohibited_class_mode_regs ();
1659 find_reg_classes ();
1660 clarify_prohibited_class_mode_regs ();
1661 setup_hard_regno_aclass ();
1665 /* Function called once at the end of compiler work. */
1667 ira_finish_once (void)
1669 ira_finish_costs_once ();
1670 free_register_move_costs ();
1674 #define ira_prohibited_mode_move_regs_initialized_p \
1675 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1677 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1679 setup_prohibited_mode_move_regs (void)
1682 rtx test_reg1
, test_reg2
, move_pat
, move_insn
;
1684 if (ira_prohibited_mode_move_regs_initialized_p
)
1686 ira_prohibited_mode_move_regs_initialized_p
= true;
1687 test_reg1
= gen_rtx_REG (VOIDmode
, 0);
1688 test_reg2
= gen_rtx_REG (VOIDmode
, 0);
1689 move_pat
= gen_rtx_SET (VOIDmode
, test_reg1
, test_reg2
);
1690 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, 0, move_pat
, 0, -1, 0);
1691 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1693 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1694 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1696 if (! HARD_REGNO_MODE_OK (j
, (enum machine_mode
) i
))
1698 SET_REGNO_RAW (test_reg1
, j
);
1699 PUT_MODE (test_reg1
, (enum machine_mode
) i
);
1700 SET_REGNO_RAW (test_reg2
, j
);
1701 PUT_MODE (test_reg2
, (enum machine_mode
) i
);
1702 INSN_CODE (move_insn
) = -1;
1703 recog_memoized (move_insn
);
1704 if (INSN_CODE (move_insn
) < 0)
1706 extract_insn (move_insn
);
1707 if (! constrain_operands (1))
1709 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1716 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
1718 ira_bad_reload_regno_1 (int regno
, rtx x
)
1722 enum reg_class pref
;
1724 /* We only deal with pseudo regs. */
1725 if (! x
|| GET_CODE (x
) != REG
)
1728 x_regno
= REGNO (x
);
1729 if (x_regno
< FIRST_PSEUDO_REGISTER
)
1732 /* If the pseudo prefers REGNO explicitly, then do not consider
1733 REGNO a bad spill choice. */
1734 pref
= reg_preferred_class (x_regno
);
1735 if (reg_class_size
[pref
] == 1)
1736 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
1738 /* If the pseudo conflicts with REGNO, then we consider REGNO a
1739 poor choice for a reload regno. */
1740 a
= ira_regno_allocno_map
[x_regno
];
1741 n
= ALLOCNO_NUM_OBJECTS (a
);
1742 for (i
= 0; i
< n
; i
++)
1744 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
1745 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
1751 /* Return nonzero if REGNO is a particularly bad choice for reloading
1754 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
1756 return (ira_bad_reload_regno_1 (regno
, in
)
1757 || ira_bad_reload_regno_1 (regno
, out
));
1760 /* Return TRUE if *LOC contains an asm. */
1762 insn_contains_asm_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
1766 if (GET_CODE (*loc
) == ASM_OPERANDS
)
1772 /* Return TRUE if INSN contains an ASM. */
1774 insn_contains_asm (rtx insn
)
1776 return for_each_rtx (&insn
, insn_contains_asm_1
, NULL
);
1779 /* Add register clobbers from asm statements. */
1781 compute_regs_asm_clobbered (void)
1788 FOR_BB_INSNS_REVERSE (bb
, insn
)
1792 if (insn_contains_asm (insn
))
1793 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1795 df_ref def
= *def_rec
;
1796 unsigned int dregno
= DF_REF_REGNO (def
);
1797 if (HARD_REGISTER_NUM_P (dregno
))
1798 add_to_hard_reg_set (&crtl
->asm_clobbers
,
1799 GET_MODE (DF_REF_REAL_REG (def
)),
1807 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE. */
1809 ira_setup_eliminable_regset (void)
1811 #ifdef ELIMINABLE_REGS
1813 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1815 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
1816 sp for alloca. So we can't eliminate the frame pointer in that
1817 case. At some point, we should improve this by emitting the
1818 sp-adjusting insns for this case. */
1820 = (! flag_omit_frame_pointer
1821 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
1822 /* We need the frame pointer to catch stack overflow exceptions
1823 if the stack pointer is moving. */
1824 || (flag_stack_check
&& STACK_CHECK_MOVING_SP
)
1825 || crtl
->accesses_prior_frames
1826 || crtl
->stack_realign_needed
1827 || targetm
.frame_pointer_required ());
1829 frame_pointer_needed
= need_fp
;
1831 COPY_HARD_REG_SET (ira_no_alloc_regs
, no_unit_alloc_regs
);
1832 CLEAR_HARD_REG_SET (eliminable_regset
);
1834 compute_regs_asm_clobbered ();
1836 /* Build the regset of all eliminable registers and show we can't
1837 use those that we already know won't be eliminated. */
1838 #ifdef ELIMINABLE_REGS
1839 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
1842 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
1843 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& need_fp
));
1845 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
1847 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
1850 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
1852 else if (cannot_elim
)
1853 error ("%s cannot be used in asm here",
1854 reg_names
[eliminables
[i
].from
]);
1856 df_set_regs_ever_live (eliminables
[i
].from
, true);
1858 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1859 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
1861 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
1863 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
1866 error ("%s cannot be used in asm here",
1867 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
1869 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
1873 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
1875 SET_HARD_REG_BIT (eliminable_regset
, FRAME_POINTER_REGNUM
);
1877 SET_HARD_REG_BIT (ira_no_alloc_regs
, FRAME_POINTER_REGNUM
);
1880 error ("%s cannot be used in asm here", reg_names
[FRAME_POINTER_REGNUM
]);
1882 df_set_regs_ever_live (FRAME_POINTER_REGNUM
, true);
1888 /* The length of the following two arrays. */
1889 int ira_reg_equiv_len
;
1891 /* The element value is TRUE if the corresponding regno value is
1893 bool *ira_reg_equiv_invariant_p
;
1895 /* The element value is equiv constant of given pseudo-register or
1897 rtx
*ira_reg_equiv_const
;
1899 /* Set up the two arrays declared above. */
1901 find_reg_equiv_invariant_const (void)
1905 rtx list
, insn
, note
, constant
, x
;
1907 for (i
= FIRST_PSEUDO_REGISTER
; i
< VEC_length (reg_equivs_t
, reg_equivs
); i
++)
1909 constant
= NULL_RTX
;
1910 invariant_p
= false;
1911 for (list
= reg_equiv_init (i
); list
!= NULL_RTX
; list
= XEXP (list
, 1))
1913 insn
= XEXP (list
, 0);
1914 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
1916 if (note
== NULL_RTX
)
1921 if (! CONSTANT_P (x
)
1922 || ! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
1924 /* It can happen that a REG_EQUIV note contains a MEM
1925 that is not a legitimate memory operand. As later
1926 stages of the reload assume that all addresses found
1927 in the reg_equiv_* arrays were originally legitimate,
1928 we ignore such REG_EQUIV notes. */
1929 if (memory_operand (x
, VOIDmode
))
1930 invariant_p
= MEM_READONLY_P (x
);
1931 else if (function_invariant_p (x
))
1933 if (GET_CODE (x
) == PLUS
1934 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
1941 ira_reg_equiv_invariant_p
[i
] = invariant_p
;
1942 ira_reg_equiv_const
[i
] = constant
;
1948 /* Vector of substitutions of register numbers,
1949 used to map pseudo regs into hardware regs.
1950 This is set up as a result of register allocation.
1951 Element N is the hard reg assigned to pseudo reg N,
1952 or is -1 if no hard reg was assigned.
1953 If N is a hard reg number, element N is N. */
1954 short *reg_renumber
;
1956 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
1957 the allocation found by IRA. */
1959 setup_reg_renumber (void)
1961 int regno
, hard_regno
;
1963 ira_allocno_iterator ai
;
1965 caller_save_needed
= 0;
1966 FOR_EACH_ALLOCNO (a
, ai
)
1968 /* There are no caps at this point. */
1969 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
1970 if (! ALLOCNO_ASSIGNED_P (a
))
1971 /* It can happen if A is not referenced but partially anticipated
1972 somewhere in a region. */
1973 ALLOCNO_ASSIGNED_P (a
) = true;
1974 ira_free_allocno_updated_costs (a
);
1975 hard_regno
= ALLOCNO_HARD_REGNO (a
);
1976 regno
= ALLOCNO_REGNO (a
);
1977 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
1978 if (hard_regno
>= 0)
1981 enum reg_class pclass
;
1984 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1985 nwords
= ALLOCNO_NUM_OBJECTS (a
);
1986 for (i
= 0; i
< nwords
; i
++)
1988 obj
= ALLOCNO_OBJECT (a
, i
);
1989 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1990 reg_class_contents
[pclass
]);
1992 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
1993 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
1996 ira_assert (!optimize
|| flag_caller_saves
1997 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
1998 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
1999 || regno
>= ira_reg_equiv_len
2000 || ira_reg_equiv_const
[regno
]
2001 || ira_reg_equiv_invariant_p
[regno
]);
2002 caller_save_needed
= 1;
2008 /* Set up allocno assignment flags for further allocation
2011 setup_allocno_assignment_flags (void)
2015 ira_allocno_iterator ai
;
2017 FOR_EACH_ALLOCNO (a
, ai
)
2019 if (! ALLOCNO_ASSIGNED_P (a
))
2020 /* It can happen if A is not referenced but partially anticipated
2021 somewhere in a region. */
2022 ira_free_allocno_updated_costs (a
);
2023 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2024 /* Don't assign hard registers to allocnos which are destination
2025 of removed store at the end of loop. It has no sense to keep
2026 the same value in different hard registers. It is also
2027 impossible to assign hard registers correctly to such
2028 allocnos because the cost info and info about intersected
2029 calls are incorrect for them. */
2030 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2031 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2032 || (ALLOCNO_MEMORY_COST (a
)
2033 - ALLOCNO_CLASS_COST (a
)) < 0);
2036 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2037 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2041 /* Evaluate overall allocation cost and the costs for using hard
2042 registers and memory for allocnos. */
2044 calculate_allocation_cost (void)
2046 int hard_regno
, cost
;
2048 ira_allocno_iterator ai
;
2050 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2051 FOR_EACH_ALLOCNO (a
, ai
)
2053 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2054 ira_assert (hard_regno
< 0
2055 || (ira_hard_reg_in_set_p
2056 (hard_regno
, ALLOCNO_MODE (a
),
2057 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2060 cost
= ALLOCNO_MEMORY_COST (a
);
2061 ira_mem_cost
+= cost
;
2063 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2065 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2066 [ira_class_hard_reg_index
2067 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2068 ira_reg_cost
+= cost
;
2072 cost
= ALLOCNO_CLASS_COST (a
);
2073 ira_reg_cost
+= cost
;
2075 ira_overall_cost
+= cost
;
2078 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2080 fprintf (ira_dump_file
,
2081 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
2082 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2083 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2084 fprintf (ira_dump_file
, "+++ move loops %d, new jumps %d\n",
2085 ira_move_loops_num
, ira_additional_jumps_num
);
2090 #ifdef ENABLE_IRA_CHECKING
2091 /* Check the correctness of the allocation. We do need this because
2092 of complicated code to transform more one region internal
2093 representation into one region representation. */
2095 check_allocation (void)
2098 int hard_regno
, nregs
, conflict_nregs
;
2099 ira_allocno_iterator ai
;
2101 FOR_EACH_ALLOCNO (a
, ai
)
2103 int n
= ALLOCNO_NUM_OBJECTS (a
);
2106 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2107 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2109 nregs
= hard_regno_nregs
[hard_regno
][ALLOCNO_MODE (a
)];
2111 /* We allocated a single hard register. */
2114 /* We allocated multiple hard registers, and we will test
2115 conflicts in a granularity of single hard regs. */
2118 for (i
= 0; i
< n
; i
++)
2120 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2121 ira_object_t conflict_obj
;
2122 ira_object_conflict_iterator oci
;
2123 int this_regno
= hard_regno
;
2126 if (REG_WORDS_BIG_ENDIAN
)
2127 this_regno
+= n
- i
- 1;
2131 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2133 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2134 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2135 if (conflict_hard_regno
< 0)
2140 [conflict_hard_regno
][ALLOCNO_MODE (conflict_a
)]);
2142 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2143 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2145 if (REG_WORDS_BIG_ENDIAN
)
2146 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2147 - OBJECT_SUBWORD (conflict_obj
) - 1);
2149 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2153 if ((conflict_hard_regno
<= this_regno
2154 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2155 || (this_regno
<= conflict_hard_regno
2156 && conflict_hard_regno
< this_regno
+ nregs
))
2158 fprintf (stderr
, "bad allocation for %d and %d\n",
2159 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2168 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2171 fix_reg_equiv_init (void)
2173 unsigned int max_regno
= max_reg_num ();
2174 int i
, new_regno
, max
;
2175 rtx x
, prev
, next
, insn
, set
;
2177 if (VEC_length (reg_equivs_t
, reg_equivs
) < max_regno
)
2179 max
= VEC_length (reg_equivs_t
, reg_equivs
);
2181 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2182 for (prev
= NULL_RTX
, x
= reg_equiv_init (i
);
2188 set
= single_set (insn
);
2189 ira_assert (set
!= NULL_RTX
2190 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2191 if (REG_P (SET_DEST (set
))
2192 && ((int) REGNO (SET_DEST (set
)) == i
2193 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2194 new_regno
= REGNO (SET_DEST (set
));
2195 else if (REG_P (SET_SRC (set
))
2196 && ((int) REGNO (SET_SRC (set
)) == i
2197 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2198 new_regno
= REGNO (SET_SRC (set
));
2205 if (prev
== NULL_RTX
)
2206 reg_equiv_init (i
) = next
;
2208 XEXP (prev
, 1) = next
;
2209 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2210 reg_equiv_init (new_regno
) = x
;
2216 #ifdef ENABLE_IRA_CHECKING
2217 /* Print redundant memory-memory copies. */
2219 print_redundant_copies (void)
2223 ira_copy_t cp
, next_cp
;
2224 ira_allocno_iterator ai
;
2226 FOR_EACH_ALLOCNO (a
, ai
)
2228 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2231 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2232 if (hard_regno
>= 0)
2234 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2236 next_cp
= cp
->next_first_allocno_copy
;
2239 next_cp
= cp
->next_second_allocno_copy
;
2240 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2241 && cp
->insn
!= NULL_RTX
2242 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2243 fprintf (ira_dump_file
,
2244 " Redundant move from %d(freq %d):%d\n",
2245 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2251 /* Setup preferred and alternative classes for new pseudo-registers
2252 created by IRA starting with START. */
2254 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2257 int max_regno
= max_reg_num ();
2259 for (i
= start
; i
< max_regno
; i
++)
2261 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2262 ira_assert (i
!= old_regno
);
2263 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2264 reg_alternate_class (old_regno
),
2265 reg_allocno_class (old_regno
));
2266 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2267 fprintf (ira_dump_file
,
2268 " New r%d: setting preferred %s, alternative %s\n",
2269 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2270 reg_class_names
[reg_alternate_class (old_regno
)]);
2275 /* The number of entries allocated in teg_info. */
2276 static int allocated_reg_info_size
;
2278 /* Regional allocation can create new pseudo-registers. This function
2279 expands some arrays for pseudo-registers. */
2281 expand_reg_info (void)
2284 int size
= max_reg_num ();
2287 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2288 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2289 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2290 allocated_reg_info_size
= size
;
2293 /* Return TRUE if there is too high register pressure in the function.
2294 It is used to decide when stack slot sharing is worth to do. */
2296 too_high_register_pressure_p (void)
2299 enum reg_class pclass
;
2301 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2303 pclass
= ira_pressure_classes
[i
];
2304 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2312 /* Indicate that hard register number FROM was eliminated and replaced with
2313 an offset from hard register number TO. The status of hard registers live
2314 at the start of a basic block is updated by replacing a use of FROM with
2318 mark_elimination (int from
, int to
)
2324 /* We don't use LIVE info in IRA. */
2325 bitmap r
= DF_LR_IN (bb
);
2327 if (REGNO_REG_SET_P (r
, from
))
2329 CLEAR_REGNO_REG_SET (r
, from
);
2330 SET_REGNO_REG_SET (r
, to
);
2339 /* Set when a REG_EQUIV note is found or created. Use to
2340 keep track of what memory accesses might be created later,
2344 /* The list of each instruction which initializes this register. */
2346 /* Loop depth is used to recognize equivalences which appear
2347 to be present within the same loop (or in an inner loop). */
2349 /* Nonzero if this had a preexisting REG_EQUIV note. */
2350 int is_arg_equivalence
;
2351 /* Set when an attempt should be made to replace a register
2352 with the associated src_p entry. */
2356 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2357 structure for that register. */
2358 static struct equivalence
*reg_equiv
;
2360 /* Used for communication between the following two functions: contains
2361 a MEM that we wish to ensure remains unchanged. */
2362 static rtx equiv_mem
;
2364 /* Set nonzero if EQUIV_MEM is modified. */
2365 static int equiv_mem_modified
;
2367 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2368 Called via note_stores. */
2370 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2371 void *data ATTRIBUTE_UNUSED
)
2374 && reg_overlap_mentioned_p (dest
, equiv_mem
))
2376 && true_dependence (dest
, VOIDmode
, equiv_mem
)))
2377 equiv_mem_modified
= 1;
2380 /* Verify that no store between START and the death of REG invalidates
2381 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2382 by storing into an overlapping memory location, or with a non-const
2385 Return 1 if MEMREF remains valid. */
2387 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
2393 equiv_mem_modified
= 0;
2395 /* If the memory reference has side effects or is volatile, it isn't a
2396 valid equivalence. */
2397 if (side_effects_p (memref
))
2400 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
2402 if (! INSN_P (insn
))
2405 if (find_reg_note (insn
, REG_DEAD
, reg
))
2408 /* This used to ignore readonly memory and const/pure calls. The problem
2409 is the equivalent form may reference a pseudo which gets assigned a
2410 call clobbered hard reg. When we later replace REG with its
2411 equivalent form, the value in the call-clobbered reg has been
2412 changed and all hell breaks loose. */
2416 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
2418 /* If a register mentioned in MEMREF is modified via an
2419 auto-increment, we lose the equivalence. Do the same if one
2420 dies; although we could extend the life, it doesn't seem worth
2423 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2424 if ((REG_NOTE_KIND (note
) == REG_INC
2425 || REG_NOTE_KIND (note
) == REG_DEAD
)
2426 && REG_P (XEXP (note
, 0))
2427 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
2434 /* Returns zero if X is known to be invariant. */
2436 equiv_init_varies_p (rtx x
)
2438 RTX_CODE code
= GET_CODE (x
);
2445 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
2454 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
2457 if (MEM_VOLATILE_P (x
))
2466 fmt
= GET_RTX_FORMAT (code
);
2467 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2470 if (equiv_init_varies_p (XEXP (x
, i
)))
2473 else if (fmt
[i
] == 'E')
2476 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2477 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
2484 /* Returns nonzero if X (used to initialize register REGNO) is movable.
2485 X is only movable if the registers it uses have equivalent initializations
2486 which appear to be within the same loop (or in an inner loop) and movable
2487 or if they are not candidates for local_alloc and don't vary. */
2489 equiv_init_movable_p (rtx x
, int regno
)
2493 enum rtx_code code
= GET_CODE (x
);
2498 return equiv_init_movable_p (SET_SRC (x
), regno
);
2513 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
2514 && reg_equiv
[REGNO (x
)].replace
)
2515 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
2516 && ! rtx_varies_p (x
, 0)));
2518 case UNSPEC_VOLATILE
:
2522 if (MEM_VOLATILE_P (x
))
2531 fmt
= GET_RTX_FORMAT (code
);
2532 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2536 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
2540 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2541 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
2549 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
2552 contains_replace_regs (rtx x
)
2556 enum rtx_code code
= GET_CODE (x
);
2570 return reg_equiv
[REGNO (x
)].replace
;
2576 fmt
= GET_RTX_FORMAT (code
);
2577 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2581 if (contains_replace_regs (XEXP (x
, i
)))
2585 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2586 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
2594 /* TRUE if X references a memory location that would be affected by a store
2597 memref_referenced_p (rtx memref
, rtx x
)
2601 enum rtx_code code
= GET_CODE (x
);
2616 return (reg_equiv
[REGNO (x
)].replacement
2617 && memref_referenced_p (memref
,
2618 reg_equiv
[REGNO (x
)].replacement
));
2621 if (true_dependence (memref
, VOIDmode
, x
))
2626 /* If we are setting a MEM, it doesn't count (its address does), but any
2627 other SET_DEST that has a MEM in it is referencing the MEM. */
2628 if (MEM_P (SET_DEST (x
)))
2630 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
2633 else if (memref_referenced_p (memref
, SET_DEST (x
)))
2636 return memref_referenced_p (memref
, SET_SRC (x
));
2642 fmt
= GET_RTX_FORMAT (code
);
2643 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2647 if (memref_referenced_p (memref
, XEXP (x
, i
)))
2651 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2652 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
2660 /* TRUE if some insn in the range (START, END] references a memory location
2661 that would be affected by a store to MEMREF. */
2663 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
2667 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
2668 insn
= NEXT_INSN (insn
))
2670 if (!NONDEBUG_INSN_P (insn
))
2673 if (memref_referenced_p (memref
, PATTERN (insn
)))
2676 /* Nonconst functions may access memory. */
2677 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
2684 /* Mark REG as having no known equivalence.
2685 Some instructions might have been processed before and furnished
2686 with REG_EQUIV notes for this register; these notes will have to be
2688 STORE is the piece of RTL that does the non-constant / conflicting
2689 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
2690 but needs to be there because this function is called from note_stores. */
2692 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
2693 void *data ATTRIBUTE_UNUSED
)
2700 regno
= REGNO (reg
);
2701 list
= reg_equiv
[regno
].init_insns
;
2702 if (list
== const0_rtx
)
2704 reg_equiv
[regno
].init_insns
= const0_rtx
;
2705 reg_equiv
[regno
].replacement
= NULL_RTX
;
2706 /* This doesn't matter for equivalences made for argument registers, we
2707 should keep their initialization insns. */
2708 if (reg_equiv
[regno
].is_arg_equivalence
)
2710 reg_equiv_init (regno
) = NULL_RTX
;
2711 for (; list
; list
= XEXP (list
, 1))
2713 rtx insn
= XEXP (list
, 0);
2714 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
2718 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
2719 equivalent replacement. */
2722 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
2726 bitmap cleared_regs
= (bitmap
) data
;
2727 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
2728 return simplify_replace_fn_rtx (*reg_equiv
[REGNO (loc
)].src_p
,
2729 NULL_RTX
, adjust_cleared_regs
, data
);
2734 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
2735 static int recorded_label_ref
;
2737 /* Find registers that are equivalent to a single value throughout the
2738 compilation (either because they can be referenced in memory or are
2739 set once from a single constant). Lower their priority for a
2742 If such a register is only referenced once, try substituting its
2743 value into the using insn. If it succeeds, we can eliminate the
2744 register completely.
2746 Initialize the REG_EQUIV_INIT array of initializing insns.
2748 Return non-zero if jump label rebuilding should be done. */
2750 update_equiv_regs (void)
2755 bitmap cleared_regs
;
2757 /* We need to keep track of whether or not we recorded a LABEL_REF so
2758 that we know if the jump optimizer needs to be rerun. */
2759 recorded_label_ref
= 0;
2761 reg_equiv
= XCNEWVEC (struct equivalence
, max_regno
);
2764 init_alias_analysis ();
2766 /* Scan the insns and find which registers have equivalences. Do this
2767 in a separate scan of the insns because (due to -fcse-follow-jumps)
2768 a register can be set below its use. */
2771 loop_depth
= bb_loop_depth (bb
);
2773 for (insn
= BB_HEAD (bb
);
2774 insn
!= NEXT_INSN (BB_END (bb
));
2775 insn
= NEXT_INSN (insn
))
2782 if (! INSN_P (insn
))
2785 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2786 if (REG_NOTE_KIND (note
) == REG_INC
)
2787 no_equiv (XEXP (note
, 0), note
, NULL
);
2789 set
= single_set (insn
);
2791 /* If this insn contains more (or less) than a single SET,
2792 only mark all destinations as having no known equivalence. */
2795 note_stores (PATTERN (insn
), no_equiv
, NULL
);
2798 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2802 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
2804 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
2806 note_stores (part
, no_equiv
, NULL
);
2810 dest
= SET_DEST (set
);
2811 src
= SET_SRC (set
);
2813 /* See if this is setting up the equivalence between an argument
2814 register and its stack slot. */
2815 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
2818 gcc_assert (REG_P (dest
));
2819 regno
= REGNO (dest
);
2821 /* Note that we don't want to clear reg_equiv_init even if there
2822 are multiple sets of this register. */
2823 reg_equiv
[regno
].is_arg_equivalence
= 1;
2825 /* Record for reload that this is an equivalencing insn. */
2826 if (rtx_equal_p (src
, XEXP (note
, 0)))
2827 reg_equiv_init (regno
)
2828 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init (regno
));
2830 /* Continue normally in case this is a candidate for
2837 /* We only handle the case of a pseudo register being set
2838 once, or always to the same value. */
2839 /* ??? The mn10200 port breaks if we add equivalences for
2840 values that need an ADDRESS_REGS register and set them equivalent
2841 to a MEM of a pseudo. The actual problem is in the over-conservative
2842 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
2843 calculate_needs, but we traditionally work around this problem
2844 here by rejecting equivalences when the destination is in a register
2845 that's likely spilled. This is fragile, of course, since the
2846 preferred class of a pseudo depends on all instructions that set
2850 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
2851 || reg_equiv
[regno
].init_insns
== const0_rtx
2852 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
2853 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
2855 /* This might be setting a SUBREG of a pseudo, a pseudo that is
2856 also set somewhere else to a constant. */
2857 note_stores (set
, no_equiv
, NULL
);
2861 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
2863 /* cse sometimes generates function invariants, but doesn't put a
2864 REG_EQUAL note on the insn. Since this note would be redundant,
2865 there's no point creating it earlier than here. */
2866 if (! note
&& ! rtx_varies_p (src
, 0))
2867 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
2869 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
2870 since it represents a function call */
2871 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
2874 if (DF_REG_DEF_COUNT (regno
) != 1
2876 || rtx_varies_p (XEXP (note
, 0), 0)
2877 || (reg_equiv
[regno
].replacement
2878 && ! rtx_equal_p (XEXP (note
, 0),
2879 reg_equiv
[regno
].replacement
))))
2881 no_equiv (dest
, set
, NULL
);
2884 /* Record this insn as initializing this register. */
2885 reg_equiv
[regno
].init_insns
2886 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
2888 /* If this register is known to be equal to a constant, record that
2889 it is always equivalent to the constant. */
2890 if (DF_REG_DEF_COUNT (regno
) == 1
2891 && note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
2893 rtx note_value
= XEXP (note
, 0);
2894 remove_note (insn
, note
);
2895 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
2898 /* If this insn introduces a "constant" register, decrease the priority
2899 of that register. Record this insn if the register is only used once
2900 more and the equivalence value is the same as our source.
2902 The latter condition is checked for two reasons: First, it is an
2903 indication that it may be more efficient to actually emit the insn
2904 as written (if no registers are available, reload will substitute
2905 the equivalence). Secondly, it avoids problems with any registers
2906 dying in this insn whose death notes would be missed.
2908 If we don't have a REG_EQUIV note, see if this insn is loading
2909 a register used only in one basic block from a MEM. If so, and the
2910 MEM remains unchanged for the life of the register, add a REG_EQUIV
2913 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
2915 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
2916 && MEM_P (SET_SRC (set
))
2917 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
2918 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (SET_SRC (set
)));
2922 int regno
= REGNO (dest
);
2923 rtx x
= XEXP (note
, 0);
2925 /* If we haven't done so, record for reload that this is an
2926 equivalencing insn. */
2927 if (!reg_equiv
[regno
].is_arg_equivalence
)
2928 reg_equiv_init (regno
)
2929 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init (regno
));
2931 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
2932 We might end up substituting the LABEL_REF for uses of the
2933 pseudo here or later. That kind of transformation may turn an
2934 indirect jump into a direct jump, in which case we must rerun the
2935 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
2936 if (GET_CODE (x
) == LABEL_REF
2937 || (GET_CODE (x
) == CONST
2938 && GET_CODE (XEXP (x
, 0)) == PLUS
2939 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)))
2940 recorded_label_ref
= 1;
2942 reg_equiv
[regno
].replacement
= x
;
2943 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
2944 reg_equiv
[regno
].loop_depth
= loop_depth
;
2946 /* Don't mess with things live during setjmp. */
2947 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
2949 /* Note that the statement below does not affect the priority
2951 REG_LIVE_LENGTH (regno
) *= 2;
2953 /* If the register is referenced exactly twice, meaning it is
2954 set once and used once, indicate that the reference may be
2955 replaced by the equivalence we computed above. Do this
2956 even if the register is only used in one block so that
2957 dependencies can be handled where the last register is
2958 used in a different block (i.e. HIGH / LO_SUM sequences)
2959 and to reduce the number of registers alive across
2962 if (REG_N_REFS (regno
) == 2
2963 && (rtx_equal_p (x
, src
)
2964 || ! equiv_init_varies_p (src
))
2965 && NONJUMP_INSN_P (insn
)
2966 && equiv_init_movable_p (PATTERN (insn
), regno
))
2967 reg_equiv
[regno
].replace
= 1;
2976 /* A second pass, to gather additional equivalences with memory. This needs
2977 to be done after we know which registers we are going to replace. */
2979 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
2984 if (! INSN_P (insn
))
2987 set
= single_set (insn
);
2991 dest
= SET_DEST (set
);
2992 src
= SET_SRC (set
);
2994 /* If this sets a MEM to the contents of a REG that is only used
2995 in a single basic block, see if the register is always equivalent
2996 to that memory location and if moving the store from INSN to the
2997 insn that set REG is safe. If so, put a REG_EQUIV note on the
3000 Don't add a REG_EQUIV note if the insn already has one. The existing
3001 REG_EQUIV is likely more useful than the one we are adding.
3003 If one of the regs in the address has reg_equiv[REGNO].replace set,
3004 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
3005 optimization may move the set of this register immediately before
3006 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
3007 the mention in the REG_EQUIV note would be to an uninitialized
3010 if (MEM_P (dest
) && REG_P (src
)
3011 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3012 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3013 && DF_REG_DEF_COUNT (regno
) == 1
3014 && reg_equiv
[regno
].init_insns
!= 0
3015 && reg_equiv
[regno
].init_insns
!= const0_rtx
3016 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
3017 REG_EQUIV
, NULL_RTX
)
3018 && ! contains_replace_regs (XEXP (dest
, 0)))
3020 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3021 if (validate_equiv_mem (init_insn
, src
, dest
)
3022 && ! memref_used_between_p (dest
, init_insn
, insn
)
3023 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3025 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3027 /* This insn makes the equivalence, not the one initializing
3029 reg_equiv_init (regno
)
3030 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3031 df_notes_rescan (init_insn
);
3036 cleared_regs
= BITMAP_ALLOC (NULL
);
3037 /* Now scan all regs killed in an insn to see if any of them are
3038 registers only used that once. If so, see if we can replace the
3039 reference with the equivalent form. If we can, delete the
3040 initializing reference and this register will go away. If we
3041 can't replace the reference, and the initializing reference is
3042 within the same loop (or in an inner loop), then move the register
3043 initialization just before the use, so that they are in the same
3045 FOR_EACH_BB_REVERSE (bb
)
3047 loop_depth
= bb_loop_depth (bb
);
3048 for (insn
= BB_END (bb
);
3049 insn
!= PREV_INSN (BB_HEAD (bb
));
3050 insn
= PREV_INSN (insn
))
3054 if (! INSN_P (insn
))
3057 /* Don't substitute into a non-local goto, this confuses CFG. */
3059 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3062 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
3064 if (REG_NOTE_KIND (link
) == REG_DEAD
3065 /* Make sure this insn still refers to the register. */
3066 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
3068 int regno
= REGNO (XEXP (link
, 0));
3071 if (! reg_equiv
[regno
].replace
3072 || reg_equiv
[regno
].loop_depth
< loop_depth
3073 /* There is no sense to move insns if we did
3074 register pressure-sensitive scheduling was
3075 done because it will not improve allocation
3076 but worsen insn schedule with a big
3078 || (flag_sched_pressure
&& flag_schedule_insns
))
3081 /* reg_equiv[REGNO].replace gets set only when
3082 REG_N_REFS[REGNO] is 2, i.e. the register is set
3083 once and used once. (If it were only set, but not used,
3084 flow would have deleted the setting insns.) Hence
3085 there can only be one insn in reg_equiv[REGNO].init_insns. */
3086 gcc_assert (reg_equiv
[regno
].init_insns
3087 && !XEXP (reg_equiv
[regno
].init_insns
, 1));
3088 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3090 /* We may not move instructions that can throw, since
3091 that changes basic block boundaries and we are not
3092 prepared to adjust the CFG to match. */
3093 if (can_throw_internal (equiv_insn
))
3096 if (asm_noperands (PATTERN (equiv_insn
)) < 0
3097 && validate_replace_rtx (regno_reg_rtx
[regno
],
3098 *(reg_equiv
[regno
].src_p
), insn
))
3104 /* Find the last note. */
3105 for (last_link
= link
; XEXP (last_link
, 1);
3106 last_link
= XEXP (last_link
, 1))
3109 /* Append the REG_DEAD notes from equiv_insn. */
3110 equiv_link
= REG_NOTES (equiv_insn
);
3114 equiv_link
= XEXP (equiv_link
, 1);
3115 if (REG_NOTE_KIND (note
) == REG_DEAD
)
3117 remove_note (equiv_insn
, note
);
3118 XEXP (last_link
, 1) = note
;
3119 XEXP (note
, 1) = NULL_RTX
;
3124 remove_death (regno
, insn
);
3125 SET_REG_N_REFS (regno
, 0);
3126 REG_FREQ (regno
) = 0;
3127 delete_insn (equiv_insn
);
3129 reg_equiv
[regno
].init_insns
3130 = XEXP (reg_equiv
[regno
].init_insns
, 1);
3132 reg_equiv_init (regno
) = NULL_RTX
;
3133 bitmap_set_bit (cleared_regs
, regno
);
3135 /* Move the initialization of the register to just before
3136 INSN. Update the flow information. */
3137 else if (prev_nondebug_insn (insn
) != equiv_insn
)
3141 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
3142 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
3143 REG_NOTES (equiv_insn
) = 0;
3144 /* Rescan it to process the notes. */
3145 df_insn_rescan (new_insn
);
3147 /* Make sure this insn is recognized before
3148 reload begins, otherwise
3149 eliminate_regs_in_insn will die. */
3150 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
3152 delete_insn (equiv_insn
);
3154 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3156 REG_BASIC_BLOCK (regno
) = bb
->index
;
3157 REG_N_CALLS_CROSSED (regno
) = 0;
3158 REG_FREQ_CALLS_CROSSED (regno
) = 0;
3159 REG_N_THROWING_CALLS_CROSSED (regno
) = 0;
3160 REG_LIVE_LENGTH (regno
) = 2;
3162 if (insn
== BB_HEAD (bb
))
3163 BB_HEAD (bb
) = PREV_INSN (insn
);
3165 reg_equiv_init (regno
)
3166 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3167 bitmap_set_bit (cleared_regs
, regno
);
3174 if (!bitmap_empty_p (cleared_regs
))
3178 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3179 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3180 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3181 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3184 /* Last pass - adjust debug insns referencing cleared regs. */
3185 if (MAY_HAVE_DEBUG_INSNS
)
3186 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3187 if (DEBUG_INSN_P (insn
))
3189 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3190 INSN_VAR_LOCATION_LOC (insn
)
3191 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3192 adjust_cleared_regs
,
3193 (void *) cleared_regs
);
3194 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3195 df_insn_rescan (insn
);
3199 BITMAP_FREE (cleared_regs
);
3204 end_alias_analysis ();
3206 return recorded_label_ref
;
3211 /* Print chain C to FILE. */
3213 print_insn_chain (FILE *file
, struct insn_chain
*c
)
3215 fprintf (file
, "insn=%d, ", INSN_UID(c
->insn
));
3216 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
3217 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
3221 /* Print all reload_insn_chains to FILE. */
3223 print_insn_chains (FILE *file
)
3225 struct insn_chain
*c
;
3226 for (c
= reload_insn_chain
; c
; c
= c
->next
)
3227 print_insn_chain (file
, c
);
3230 /* Return true if pseudo REGNO should be added to set live_throughout
3231 or dead_or_set of the insn chains for reload consideration. */
3233 pseudo_for_reload_consideration_p (int regno
)
3235 /* Consider spilled pseudos too for IRA because they still have a
3236 chance to get hard-registers in the reload when IRA is used. */
3237 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
3240 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using
3241 REG to the number of nregs, and INIT_VALUE to get the
3242 initialization. ALLOCNUM need not be the regno of REG. */
3244 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
3245 bitmap live_subregs_used
, int allocnum
, rtx reg
)
3247 unsigned int regno
= REGNO (SUBREG_REG (reg
));
3248 int size
= GET_MODE_SIZE (GET_MODE (regno_reg_rtx
[regno
]));
3250 gcc_assert (size
> 0);
3252 /* Been there, done that. */
3253 if (bitmap_bit_p (live_subregs_used
, allocnum
))
3256 /* Create a new one. */
3257 if (live_subregs
[allocnum
] == NULL
)
3258 live_subregs
[allocnum
] = sbitmap_alloc (size
);
3260 /* If the entire reg was live before blasting into subregs, we need
3261 to init all of the subregs to ones else init to 0. */
3263 sbitmap_ones (live_subregs
[allocnum
]);
3265 sbitmap_zero (live_subregs
[allocnum
]);
3267 bitmap_set_bit (live_subregs_used
, allocnum
);
3270 /* Walk the insns of the current function and build reload_insn_chain,
3271 and record register life information. */
3273 build_insn_chain (void)
3276 struct insn_chain
**p
= &reload_insn_chain
;
3278 struct insn_chain
*c
= NULL
;
3279 struct insn_chain
*next
= NULL
;
3280 bitmap live_relevant_regs
= BITMAP_ALLOC (NULL
);
3281 bitmap elim_regset
= BITMAP_ALLOC (NULL
);
3282 /* live_subregs is a vector used to keep accurate information about
3283 which hardregs are live in multiword pseudos. live_subregs and
3284 live_subregs_used are indexed by pseudo number. The live_subreg
3285 entry for a particular pseudo is only used if the corresponding
3286 element is non zero in live_subregs_used. The sbitmap size of
3287 live_subreg[allocno] is number of bytes that the pseudo can
3289 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
3290 bitmap live_subregs_used
= BITMAP_ALLOC (NULL
);
3292 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3293 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
3294 bitmap_set_bit (elim_regset
, i
);
3295 FOR_EACH_BB_REVERSE (bb
)
3300 CLEAR_REG_SET (live_relevant_regs
);
3301 bitmap_clear (live_subregs_used
);
3303 EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb
), 0, i
, bi
)
3305 if (i
>= FIRST_PSEUDO_REGISTER
)
3307 bitmap_set_bit (live_relevant_regs
, i
);
3310 EXECUTE_IF_SET_IN_BITMAP (DF_LR_OUT (bb
),
3311 FIRST_PSEUDO_REGISTER
, i
, bi
)
3313 if (pseudo_for_reload_consideration_p (i
))
3314 bitmap_set_bit (live_relevant_regs
, i
);
3317 FOR_BB_INSNS_REVERSE (bb
, insn
)
3319 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
3321 unsigned int uid
= INSN_UID (insn
);
3325 c
= new_insn_chain ();
3332 c
->block
= bb
->index
;
3335 for (def_rec
= DF_INSN_UID_DEFS (uid
); *def_rec
; def_rec
++)
3337 df_ref def
= *def_rec
;
3338 unsigned int regno
= DF_REF_REGNO (def
);
3340 /* Ignore may clobbers because these are generated
3341 from calls. However, every other kind of def is
3342 added to dead_or_set. */
3343 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
3345 if (regno
< FIRST_PSEUDO_REGISTER
)
3347 if (!fixed_regs
[regno
])
3348 bitmap_set_bit (&c
->dead_or_set
, regno
);
3350 else if (pseudo_for_reload_consideration_p (regno
))
3351 bitmap_set_bit (&c
->dead_or_set
, regno
);
3354 if ((regno
< FIRST_PSEUDO_REGISTER
3355 || reg_renumber
[regno
] >= 0
3357 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
3359 rtx reg
= DF_REF_REG (def
);
3361 /* We can model subregs, but not if they are
3362 wrapped in ZERO_EXTRACTS. */
3363 if (GET_CODE (reg
) == SUBREG
3364 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
))
3366 unsigned int start
= SUBREG_BYTE (reg
);
3367 unsigned int last
= start
3368 + GET_MODE_SIZE (GET_MODE (reg
));
3371 (bitmap_bit_p (live_relevant_regs
, regno
),
3372 live_subregs
, live_subregs_used
, regno
, reg
);
3374 if (!DF_REF_FLAGS_IS_SET
3375 (def
, DF_REF_STRICT_LOW_PART
))
3377 /* Expand the range to cover entire words.
3378 Bytes added here are "don't care". */
3380 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
3381 last
= ((last
+ UNITS_PER_WORD
- 1)
3382 / UNITS_PER_WORD
* UNITS_PER_WORD
);
3385 /* Ignore the paradoxical bits. */
3386 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
3387 last
= SBITMAP_SIZE (live_subregs
[regno
]);
3389 while (start
< last
)
3391 RESET_BIT (live_subregs
[regno
], start
);
3395 if (sbitmap_empty_p (live_subregs
[regno
]))
3397 bitmap_clear_bit (live_subregs_used
, regno
);
3398 bitmap_clear_bit (live_relevant_regs
, regno
);
3401 /* Set live_relevant_regs here because
3402 that bit has to be true to get us to
3403 look at the live_subregs fields. */
3404 bitmap_set_bit (live_relevant_regs
, regno
);
3408 /* DF_REF_PARTIAL is generated for
3409 subregs, STRICT_LOW_PART, and
3410 ZERO_EXTRACT. We handle the subreg
3411 case above so here we have to keep from
3412 modeling the def as a killing def. */
3413 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
3415 bitmap_clear_bit (live_subregs_used
, regno
);
3416 bitmap_clear_bit (live_relevant_regs
, regno
);
3422 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
3423 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
3426 for (use_rec
= DF_INSN_UID_USES (uid
); *use_rec
; use_rec
++)
3428 df_ref use
= *use_rec
;
3429 unsigned int regno
= DF_REF_REGNO (use
);
3430 rtx reg
= DF_REF_REG (use
);
3432 /* DF_REF_READ_WRITE on a use means that this use
3433 is fabricated from a def that is a partial set
3434 to a multiword reg. Here, we only model the
3435 subreg case that is not wrapped in ZERO_EXTRACT
3436 precisely so we do not need to look at the
3438 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
3439 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
3440 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
3443 /* Add the last use of each var to dead_or_set. */
3444 if (!bitmap_bit_p (live_relevant_regs
, regno
))
3446 if (regno
< FIRST_PSEUDO_REGISTER
)
3448 if (!fixed_regs
[regno
])
3449 bitmap_set_bit (&c
->dead_or_set
, regno
);
3451 else if (pseudo_for_reload_consideration_p (regno
))
3452 bitmap_set_bit (&c
->dead_or_set
, regno
);
3455 if (regno
< FIRST_PSEUDO_REGISTER
3456 || pseudo_for_reload_consideration_p (regno
))
3458 if (GET_CODE (reg
) == SUBREG
3459 && !DF_REF_FLAGS_IS_SET (use
,
3461 | DF_REF_ZERO_EXTRACT
))
3463 unsigned int start
= SUBREG_BYTE (reg
);
3464 unsigned int last
= start
3465 + GET_MODE_SIZE (GET_MODE (reg
));
3468 (bitmap_bit_p (live_relevant_regs
, regno
),
3469 live_subregs
, live_subregs_used
, regno
, reg
);
3471 /* Ignore the paradoxical bits. */
3472 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
3473 last
= SBITMAP_SIZE (live_subregs
[regno
]);
3475 while (start
< last
)
3477 SET_BIT (live_subregs
[regno
], start
);
3482 /* Resetting the live_subregs_used is
3483 effectively saying do not use the subregs
3484 because we are reading the whole
3486 bitmap_clear_bit (live_subregs_used
, regno
);
3487 bitmap_set_bit (live_relevant_regs
, regno
);
3493 /* FIXME!! The following code is a disaster. Reload needs to see the
3494 labels and jump tables that are just hanging out in between
3495 the basic blocks. See pr33676. */
3496 insn
= BB_HEAD (bb
);
3498 /* Skip over the barriers and cruft. */
3499 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
3500 || BLOCK_FOR_INSN (insn
) == bb
))
3501 insn
= PREV_INSN (insn
);
3503 /* While we add anything except barriers and notes, the focus is
3504 to get the labels and jump tables into the
3505 reload_insn_chain. */
3508 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
3510 if (BLOCK_FOR_INSN (insn
))
3513 c
= new_insn_chain ();
3519 /* The block makes no sense here, but it is what the old
3521 c
->block
= bb
->index
;
3523 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
3525 insn
= PREV_INSN (insn
);
3529 reload_insn_chain
= c
;
3532 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
3533 if (live_subregs
[i
] != NULL
)
3534 sbitmap_free (live_subregs
[i
]);
3535 free (live_subregs
);
3536 BITMAP_FREE (live_subregs_used
);
3537 BITMAP_FREE (live_relevant_regs
);
3538 BITMAP_FREE (elim_regset
);
3541 print_insn_chains (dump_file
);
3544 /* Examine the rtx found in *LOC, which is read or written to as determined
3545 by TYPE. Return false if we find a reason why an insn containing this
3546 rtx should not be moved (such as accesses to non-constant memory), true
3549 rtx_moveable_p (rtx
*loc
, enum op_type type
)
3553 enum rtx_code code
= GET_CODE (x
);
3556 code
= GET_CODE (x
);
3566 return type
== OP_IN
;
3572 if (x
== frame_pointer_rtx
)
3574 if (HARD_REGISTER_P (x
))
3580 if (type
== OP_IN
&& MEM_READONLY_P (x
))
3581 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
3585 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
3586 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
3588 case STRICT_LOW_PART
:
3589 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
3593 return (rtx_moveable_p (&XEXP (x
, 0), type
)
3594 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
3595 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
3598 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
3604 fmt
= GET_RTX_FORMAT (code
);
3605 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3609 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
3612 else if (fmt
[i
] == 'E')
3613 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3615 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
3622 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
3623 to give dominance relationships between two insns I1 and I2. */
3625 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
3627 basic_block bb1
= BLOCK_FOR_INSN (i1
);
3628 basic_block bb2
= BLOCK_FOR_INSN (i2
);
3631 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
3632 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
3635 /* Record the range of register numbers added by find_moveable_pseudos. */
3636 int first_moveable_pseudo
, last_moveable_pseudo
;
3638 /* These two vectors hold data for every register added by
3639 find_movable_pseudos, with index 0 holding data for the
3640 first_moveable_pseudo. */
3641 /* The original home register. */
3642 static VEC (rtx
, heap
) *pseudo_replaced_reg
;
3644 /* Look for instances where we have an instruction that is known to increase
3645 register pressure, and whose result is not used immediately. If it is
3646 possible to move the instruction downwards to just before its first use,
3647 split its lifetime into two ranges. We create a new pseudo to compute the
3648 value, and emit a move instruction just before the first use. If, after
3649 register allocation, the new pseudo remains unallocated, the function
3650 move_unallocated_pseudos then deletes the move instruction and places
3651 the computation just before the first use.
3653 Such a move is safe and profitable if all the input registers remain live
3654 and unchanged between the original computation and its first use. In such
3655 a situation, the computation is known to increase register pressure, and
3656 moving it is known to at least not worsen it.
3658 We restrict moves to only those cases where a register remains unallocated,
3659 in order to avoid interfering too much with the instruction schedule. As
3660 an exception, we may move insns which only modify their input register
3661 (typically induction variables), as this increases the freedom for our
3662 intended transformation, and does not limit the second instruction
3666 find_moveable_pseudos (void)
3669 int max_regs
= max_reg_num ();
3670 int max_uid
= get_max_uid ();
3672 int *uid_luid
= XNEWVEC (int, max_uid
);
3673 rtx
*closest_uses
= XNEWVEC (rtx
, max_regs
);
3674 /* A set of registers which are live but not modified throughout a block. */
3675 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
, last_basic_block
);
3676 /* A set of registers which only exist in a given basic block. */
3677 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
, last_basic_block
);
3678 /* A set of registers which are set once, in an instruction that can be
3679 moved freely downwards, but are otherwise transparent to a block. */
3680 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
, last_basic_block
);
3681 bitmap_head live
, used
, set
, interesting
, unusable_as_input
;
3683 bitmap_initialize (&interesting
, 0);
3685 first_moveable_pseudo
= max_regs
;
3686 VEC_free (rtx
, heap
, pseudo_replaced_reg
);
3687 VEC_safe_grow (rtx
, heap
, pseudo_replaced_reg
, max_regs
);
3690 calculate_dominance_info (CDI_DOMINATORS
);
3693 bitmap_initialize (&live
, 0);
3694 bitmap_initialize (&used
, 0);
3695 bitmap_initialize (&set
, 0);
3696 bitmap_initialize (&unusable_as_input
, 0);
3700 bitmap transp
= bb_transp_live
+ bb
->index
;
3701 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
3702 bitmap local
= bb_local
+ bb
->index
;
3704 bitmap_initialize (local
, 0);
3705 bitmap_initialize (transp
, 0);
3706 bitmap_initialize (moveable
, 0);
3707 bitmap_copy (&live
, df_get_live_out (bb
));
3708 bitmap_and_into (&live
, df_get_live_in (bb
));
3709 bitmap_copy (transp
, &live
);
3710 bitmap_clear (moveable
);
3711 bitmap_clear (&live
);
3712 bitmap_clear (&used
);
3713 bitmap_clear (&set
);
3714 FOR_BB_INSNS (bb
, insn
)
3715 if (NONDEBUG_INSN_P (insn
))
3717 df_ref
*u_rec
, *d_rec
;
3719 uid_luid
[INSN_UID (insn
)] = i
++;
3721 u_rec
= DF_INSN_USES (insn
);
3722 d_rec
= DF_INSN_DEFS (insn
);
3723 if (d_rec
[0] != NULL
&& d_rec
[1] == NULL
3724 && u_rec
[0] != NULL
&& u_rec
[1] == NULL
3725 && DF_REF_REGNO (*u_rec
) == DF_REF_REGNO (*d_rec
)
3726 && !bitmap_bit_p (&set
, DF_REF_REGNO (*u_rec
))
3727 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
3729 unsigned regno
= DF_REF_REGNO (*u_rec
);
3730 bitmap_set_bit (moveable
, regno
);
3731 bitmap_set_bit (&set
, regno
);
3732 bitmap_set_bit (&used
, regno
);
3733 bitmap_clear_bit (transp
, regno
);
3738 unsigned regno
= DF_REF_REGNO (*u_rec
);
3739 bitmap_set_bit (&used
, regno
);
3740 if (bitmap_clear_bit (moveable
, regno
))
3741 bitmap_clear_bit (transp
, regno
);
3747 unsigned regno
= DF_REF_REGNO (*d_rec
);
3748 bitmap_set_bit (&set
, regno
);
3749 bitmap_clear_bit (transp
, regno
);
3750 bitmap_clear_bit (moveable
, regno
);
3756 bitmap_clear (&live
);
3757 bitmap_clear (&used
);
3758 bitmap_clear (&set
);
3762 bitmap local
= bb_local
+ bb
->index
;
3765 FOR_BB_INSNS (bb
, insn
)
3766 if (NONDEBUG_INSN_P (insn
))
3768 rtx def_insn
, closest_use
, note
;
3769 df_ref
*def_rec
, def
, use
;
3771 bool all_dominated
, all_local
;
3772 enum machine_mode mode
;
3774 def_rec
= DF_INSN_DEFS (insn
);
3775 /* There must be exactly one def in this insn. */
3777 if (!def
|| def_rec
[1] || !single_set (insn
))
3779 /* This must be the only definition of the reg. We also limit
3780 which modes we deal with so that we can assume we can generate
3781 move instructions. */
3782 regno
= DF_REF_REGNO (def
);
3783 mode
= GET_MODE (DF_REF_REG (def
));
3784 if (DF_REG_DEF_COUNT (regno
) != 1
3785 || !DF_REF_INSN_INFO (def
)
3786 || HARD_REGISTER_NUM_P (regno
)
3787 || DF_REG_EQ_USE_COUNT (regno
) > 0
3788 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
3790 def_insn
= DF_REF_INSN (def
);
3792 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
3793 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
3799 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
3801 bitmap_set_bit (&unusable_as_input
, regno
);
3805 use
= DF_REG_USE_CHAIN (regno
);
3806 all_dominated
= true;
3808 closest_use
= NULL_RTX
;
3809 for (; use
; use
= DF_REF_NEXT_REG (use
))
3812 if (!DF_REF_INSN_INFO (use
))
3814 all_dominated
= false;
3818 insn
= DF_REF_INSN (use
);
3819 if (DEBUG_INSN_P (insn
))
3821 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
3823 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
3824 all_dominated
= false;
3825 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
3827 if (closest_use
== NULL_RTX
)
3829 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
3831 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
3832 closest_use
= const0_rtx
;
3838 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
3843 bitmap_set_bit (local
, regno
);
3844 if (closest_use
== const0_rtx
|| closest_use
== NULL
3845 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
3848 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
3849 closest_use
== const0_rtx
|| closest_use
== NULL
3850 ? " (no unique first use)" : "");
3854 if (reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
3857 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
3862 bitmap_set_bit (&interesting
, regno
);
3863 closest_uses
[regno
] = closest_use
;
3865 if (dump_file
&& (all_local
|| all_dominated
))
3867 fprintf (dump_file
, "Reg %u:", regno
);
3869 fprintf (dump_file
, " local to bb %d", bb
->index
);
3871 fprintf (dump_file
, " def dominates all uses");
3872 if (closest_use
!= const0_rtx
)
3873 fprintf (dump_file
, " has unique first use");
3874 fputs ("\n", dump_file
);
3879 EXECUTE_IF_SET_IN_BITMAP (&interesting
, 0, i
, bi
)
3881 df_ref def
= DF_REG_DEF_CHAIN (i
);
3882 rtx def_insn
= DF_REF_INSN (def
);
3883 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
3884 bitmap def_bb_local
= bb_local
+ def_block
->index
;
3885 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
3886 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
3887 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
3888 rtx use_insn
= closest_uses
[i
];
3889 df_ref
*def_insn_use_rec
= DF_INSN_USES (def_insn
);
3891 bool all_transp
= true;
3893 if (!REG_P (DF_REF_REG (def
)))
3899 fprintf (dump_file
, "Reg %u not local to one basic block\n",
3903 if (reg_equiv_init (i
) != NULL_RTX
)
3906 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
3910 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
3913 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
3914 INSN_UID (def_insn
), i
);
3918 fprintf (dump_file
, "Examining insn %d, def for %d\n",
3919 INSN_UID (def_insn
), i
);
3920 while (*def_insn_use_rec
!= NULL
)
3922 df_ref use
= *def_insn_use_rec
;
3923 unsigned regno
= DF_REF_REGNO (use
);
3924 if (bitmap_bit_p (&unusable_as_input
, regno
))
3928 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
3931 if (!bitmap_bit_p (def_bb_transp
, regno
))
3933 if (bitmap_bit_p (def_bb_moveable
, regno
)
3934 && !control_flow_insn_p (use_insn
)
3936 && !sets_cc0_p (use_insn
)
3940 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
3942 rtx x
= NEXT_INSN (def_insn
);
3943 while (!modified_in_p (DF_REF_REG (use
), x
))
3945 gcc_assert (x
!= use_insn
);
3949 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
3950 regno
, INSN_UID (x
));
3951 emit_insn_after (PATTERN (x
), use_insn
);
3952 set_insn_deleted (x
);
3957 fprintf (dump_file
, " input reg %u modified between def and use\n",
3970 if (!dbg_cnt (ira_move
))
3973 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
3977 rtx def_reg
= DF_REF_REG (def
);
3978 rtx newreg
= ira_create_new_reg (def_reg
);
3979 if (validate_change (def_insn
, DF_REF_LOC (def
), newreg
, 0))
3981 unsigned nregno
= REGNO (newreg
);
3982 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
3984 VEC_replace (rtx
, pseudo_replaced_reg
, nregno
, def_reg
);
3991 bitmap_clear (bb_local
+ bb
->index
);
3992 bitmap_clear (bb_transp_live
+ bb
->index
);
3993 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
3995 bitmap_clear (&interesting
);
3996 bitmap_clear (&unusable_as_input
);
3998 free (closest_uses
);
4000 free (bb_transp_live
);
4001 free (bb_moveable_reg_sets
);
4003 last_moveable_pseudo
= max_reg_num ();
4005 fix_reg_equiv_init ();
4007 regstat_free_n_sets_and_refs ();
4009 regstat_init_n_sets_and_refs ();
4010 regstat_compute_ri ();
4011 free_dominance_info (CDI_DOMINATORS
);
4014 /* Perform the second half of the transformation started in
4015 find_moveable_pseudos. We look for instances where the newly introduced
4016 pseudo remains unallocated, and remove it by moving the definition to
4017 just before its use, replacing the move instruction generated by
4018 find_moveable_pseudos. */
4020 move_unallocated_pseudos (void)
4023 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
4024 if (reg_renumber
[i
] < 0)
4026 int idx
= i
- first_moveable_pseudo
;
4027 rtx other_reg
= VEC_index (rtx
, pseudo_replaced_reg
, idx
);
4028 rtx def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
4029 /* The use must follow all definitions of OTHER_REG, so we can
4030 insert the new definition immediately after any of them. */
4031 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
4032 rtx move_insn
= DF_REF_INSN (other_def
);
4033 rtx newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
4038 fprintf (dump_file
, "moving def of %d (insn %d now) ",
4039 REGNO (other_reg
), INSN_UID (def_insn
));
4041 delete_insn (move_insn
);
4042 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
4043 delete_insn (DF_REF_INSN (other_def
));
4044 delete_insn (def_insn
);
4046 set
= single_set (newinsn
);
4047 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
4048 gcc_assert (success
);
4050 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
4051 INSN_UID (newinsn
), i
);
4052 SET_REG_N_REFS (i
, 0);
4056 /* If the backend knows where to allocate pseudos for hard
4057 register initial values, register these allocations now. */
4059 allocate_initial_values (void)
4061 if (targetm
.allocate_initial_value
)
4066 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
4068 if (! initial_value_entry (i
, &hreg
, &preg
))
4071 x
= targetm
.allocate_initial_value (hreg
);
4072 regno
= REGNO (preg
);
4073 if (x
&& REG_N_SETS (regno
) <= 1)
4076 reg_equiv_memory_loc (regno
) = x
;
4082 gcc_assert (REG_P (x
));
4083 new_regno
= REGNO (x
);
4084 reg_renumber
[regno
] = new_regno
;
4085 /* Poke the regno right into regno_reg_rtx so that even
4086 fixed regs are accepted. */
4087 SET_REGNO (preg
, new_regno
);
4088 /* Update global register liveness information. */
4091 if (REGNO_REG_SET_P(df_get_live_in (bb
), regno
))
4092 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
4093 if (REGNO_REG_SET_P(df_get_live_out (bb
), regno
))
4094 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
4100 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
4105 /* All natural loops. */
4106 struct loops ira_loops
;
4108 /* True if we have allocno conflicts. It is false for non-optimized
4109 mode or when the conflict table is too big. */
4110 bool ira_conflicts_p
;
4112 /* Saved between IRA and reload. */
4113 static int saved_flag_ira_share_spill_slots
;
4115 /* This is the main entry of IRA. */
4120 int max_regno_before_ira
, ira_max_point_before_emit
;
4123 if (flag_caller_saves
)
4124 init_caller_save ();
4126 if (flag_ira_verbose
< 10)
4128 internal_flag_ira_verbose
= flag_ira_verbose
;
4133 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
4134 ira_dump_file
= stderr
;
4137 ira_conflicts_p
= optimize
> 0;
4138 setup_prohibited_mode_move_regs ();
4140 df_note_add_problem ();
4144 df_live_add_problem ();
4145 df_live_set_all_dirty ();
4147 #ifdef ENABLE_CHECKING
4148 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
4151 df_clear_flags (DF_NO_INSN_RESCAN
);
4152 regstat_init_n_sets_and_refs ();
4153 regstat_compute_ri ();
4155 /* If we are not optimizing, then this is the only place before
4156 register allocation where dataflow is done. And that is needed
4157 to generate these warnings. */
4159 generate_setjmp_warnings ();
4161 /* Determine if the current function is a leaf before running IRA
4162 since this can impact optimizations done by the prologue and
4163 epilogue thus changing register elimination offsets. */
4164 crtl
->is_leaf
= leaf_function_p ();
4166 if (resize_reg_info () && flag_ira_loop_pressure
)
4167 ira_set_pseudo_classes (ira_dump_file
);
4169 rebuild_p
= update_equiv_regs ();
4171 #ifndef IRA_NO_OBSTACK
4172 gcc_obstack_init (&ira_obstack
);
4174 bitmap_obstack_initialize (&ira_bitmap_obstack
);
4177 max_regno
= max_reg_num ();
4178 ira_reg_equiv_len
= max_regno
;
4179 ira_reg_equiv_invariant_p
4180 = (bool *) ira_allocate (max_regno
* sizeof (bool));
4181 memset (ira_reg_equiv_invariant_p
, 0, max_regno
* sizeof (bool));
4182 ira_reg_equiv_const
= (rtx
*) ira_allocate (max_regno
* sizeof (rtx
));
4183 memset (ira_reg_equiv_const
, 0, max_regno
* sizeof (rtx
));
4184 find_reg_equiv_invariant_const ();
4187 timevar_push (TV_JUMP
);
4188 rebuild_jump_labels (get_insns ());
4189 if (purge_all_dead_edges ())
4190 delete_unreachable_blocks ();
4191 timevar_pop (TV_JUMP
);
4195 allocated_reg_info_size
= max_reg_num ();
4197 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
4200 /* It is not worth to do such improvement when we use a simple
4201 allocation because of -O0 usage or because the function is too
4203 if (ira_conflicts_p
)
4204 find_moveable_pseudos ();
4206 max_regno_before_ira
= max_reg_num ();
4207 ira_setup_eliminable_regset ();
4209 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
4210 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
4211 ira_move_loops_num
= ira_additional_jumps_num
= 0;
4213 ira_assert (current_loops
== NULL
);
4214 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
4216 flow_loops_find (&ira_loops
);
4217 record_loop_exits ();
4218 current_loops
= &ira_loops
;
4221 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
4222 fprintf (ira_dump_file
, "Building IRA IR\n");
4223 loops_p
= ira_build ();
4225 ira_assert (ira_conflicts_p
|| !loops_p
);
4227 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
4228 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
4229 /* It is just wasting compiler's time to pack spilled pseudos into
4230 stack slots in this case -- prohibit it. We also do this if
4231 there is setjmp call because a variable not modified between
4232 setjmp and longjmp the compiler is required to preserve its
4233 value and sharing slots does not guarantee it. */
4234 flag_ira_share_spill_slots
= FALSE
;
4238 ira_max_point_before_emit
= ira_max_point
;
4240 ira_initiate_emit_data ();
4244 if (ira_conflicts_p
)
4246 max_regno
= max_reg_num ();
4249 ira_initiate_assign ();
4254 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
4255 fprintf (ira_dump_file
, "Flattening IR\n");
4256 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
4257 /* New insns were generated: add notes and recalculate live
4261 flow_loops_find (&ira_loops
);
4262 record_loop_exits ();
4263 current_loops
= &ira_loops
;
4265 setup_allocno_assignment_flags ();
4266 ira_initiate_assign ();
4267 ira_reassign_conflict_allocnos (max_regno
);
4271 ira_finish_emit_data ();
4273 setup_reg_renumber ();
4275 calculate_allocation_cost ();
4277 #ifdef ENABLE_IRA_CHECKING
4278 if (ira_conflicts_p
)
4279 check_allocation ();
4282 if (max_regno
!= max_regno_before_ira
)
4284 regstat_free_n_sets_and_refs ();
4286 regstat_init_n_sets_and_refs ();
4287 regstat_compute_ri ();
4290 overall_cost_before
= ira_overall_cost
;
4291 if (! ira_conflicts_p
)
4295 fix_reg_equiv_init ();
4297 #ifdef ENABLE_IRA_CHECKING
4298 print_redundant_copies ();
4301 ira_spilled_reg_stack_slots_num
= 0;
4302 ira_spilled_reg_stack_slots
4303 = ((struct ira_spilled_reg_stack_slot
*)
4304 ira_allocate (max_regno
4305 * sizeof (struct ira_spilled_reg_stack_slot
)));
4306 memset (ira_spilled_reg_stack_slots
, 0,
4307 max_regno
* sizeof (struct ira_spilled_reg_stack_slot
));
4309 allocate_initial_values ();
4311 /* See comment for find_moveable_pseudos call. */
4312 if (ira_conflicts_p
)
4313 move_unallocated_pseudos ();
4322 if (flag_ira_verbose
< 10)
4323 ira_dump_file
= dump_file
;
4325 df_set_flags (DF_NO_INSN_RESCAN
);
4326 build_insn_chain ();
4328 need_dce
= reload (get_insns (), ira_conflicts_p
);
4330 timevar_push (TV_IRA
);
4332 if (ira_conflicts_p
)
4334 ira_free (ira_spilled_reg_stack_slots
);
4336 ira_finish_assign ();
4338 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
4339 && overall_cost_before
!= ira_overall_cost
)
4340 fprintf (ira_dump_file
, "+++Overall after reload %d\n", ira_overall_cost
);
4343 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
4345 if (current_loops
!= NULL
)
4347 flow_loops_free (&ira_loops
);
4348 free_dominance_info (CDI_DOMINATORS
);
4351 bb
->loop_father
= NULL
;
4352 current_loops
= NULL
;
4355 regstat_free_n_sets_and_refs ();
4359 cleanup_cfg (CLEANUP_EXPENSIVE
);
4361 ira_free (ira_reg_equiv_invariant_p
);
4362 ira_free (ira_reg_equiv_const
);
4365 bitmap_obstack_release (&ira_bitmap_obstack
);
4366 #ifndef IRA_NO_OBSTACK
4367 obstack_free (&ira_obstack
, NULL
);
4370 /* The code after the reload has changed so much that at this point
4371 we might as well just rescan everything. Note that
4372 df_rescan_all_insns is not going to help here because it does not
4373 touch the artificial uses and defs. */
4374 df_finish_pass (true);
4376 df_live_add_problem ();
4377 df_scan_alloc (NULL
);
4383 if (need_dce
&& optimize
)
4386 timevar_pop (TV_IRA
);
4389 /* Run the integrated register allocator. */
4391 rest_of_handle_ira (void)
4397 struct rtl_opt_pass pass_ira
=
4403 rest_of_handle_ira
, /* execute */
4406 0, /* static_pass_number */
4408 0, /* properties_required */
4409 0, /* properties_provided */
4410 0, /* properties_destroyed */
4411 0, /* todo_flags_start */
4412 0, /* todo_flags_finish */
4417 rest_of_handle_reload (void)
4423 struct rtl_opt_pass pass_reload
=
4427 "reload", /* name */
4429 rest_of_handle_reload
, /* execute */
4432 0, /* static_pass_number */
4433 TV_RELOAD
, /* tv_id */
4434 0, /* properties_required */
4435 0, /* properties_provided */
4436 0, /* properties_destroyed */
4437 0, /* todo_flags_start */
4438 TODO_ggc_collect
/* todo_flags_finish */