1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
43 #ifndef REGISTER_MOVE_COST
44 #define REGISTER_MOVE_COST(x, y) 2
47 static void init_reg_sets_1
PROTO((void));
48 static void init_reg_modes
PROTO((void));
50 /* If we have auto-increment or auto-decrement and we can have secondary
51 reloads, we are not allowed to use classes requiring secondary
52 reloads for pseudos auto-incremented since reload can't handle it. */
55 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
56 #define FORBIDDEN_INC_DEC_CLASSES
60 /* Register tables used by many passes. */
62 /* Indexed by hard register number, contains 1 for registers
63 that are fixed use (stack pointer, pc, frame pointer, etc.).
64 These are the registers that cannot be used to allocate
65 a pseudo reg for general use. */
67 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
69 /* Same info as a HARD_REG_SET. */
71 HARD_REG_SET fixed_reg_set
;
73 /* Data for initializing the above. */
75 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
77 /* Indexed by hard register number, contains 1 for registers
78 that are fixed use or are clobbered by function calls.
79 These are the registers that cannot be used to allocate
80 a pseudo reg whose life crosses calls unless we are able
81 to save/restore them across the calls. */
83 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
85 /* Same info as a HARD_REG_SET. */
87 HARD_REG_SET call_used_reg_set
;
89 /* HARD_REG_SET of registers we want to avoid caller saving. */
90 HARD_REG_SET losing_caller_save_reg_set
;
92 /* Data for initializing the above. */
94 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
96 /* Indexed by hard register number, contains 1 for registers that are
97 fixed use or call used registers that cannot hold quantities across
98 calls even if we are willing to save and restore them. call fixed
99 registers are a subset of call used registers. */
101 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
103 /* The same info as a HARD_REG_SET. */
105 HARD_REG_SET call_fixed_reg_set
;
107 /* Number of non-fixed registers. */
109 int n_non_fixed_regs
;
111 /* Indexed by hard register number, contains 1 for registers
112 that are being used for global register decls.
113 These must be exempt from ordinary flow analysis
114 and are also considered fixed. */
116 char global_regs
[FIRST_PSEUDO_REGISTER
];
118 /* Table of register numbers in the order in which to try to use them. */
119 #ifdef REG_ALLOC_ORDER
120 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
123 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
125 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
127 /* The same information, but as an array of unsigned ints. We copy from
128 these unsigned ints to the table above. We do this so the tm.h files
129 do not have to be aware of the wordsize for machines with <= 64 regs. */
132 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
134 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
135 = REG_CLASS_CONTENTS
;
137 /* For each reg class, number of regs it contains. */
139 int reg_class_size
[N_REG_CLASSES
];
141 /* For each reg class, table listing all the containing classes. */
143 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
145 /* For each reg class, table listing all the classes contained in it. */
147 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
149 /* For each pair of reg classes,
150 a largest reg class contained in their union. */
152 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
154 /* For each pair of reg classes,
155 the smallest reg class containing their union. */
157 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
159 /* Array containing all of the register names */
161 const char *reg_names
[] = REGISTER_NAMES
;
163 /* For each hard register, the widest mode object that it can contain.
164 This will be a MODE_INT mode if the register can hold integers. Otherwise
165 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
168 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
170 /* Maximum cost of moving from a register in one class to a register in
171 another class. Based on REGISTER_MOVE_COST. */
173 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
175 /* Similar, but here we don't have to move if the first index is a subset
176 of the second so in that case the cost is zero. */
178 static int may_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
180 #ifdef FORBIDDEN_INC_DEC_CLASSES
182 /* These are the classes that regs which are auto-incremented or decremented
185 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
187 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
190 static char *in_inc_dec
;
192 #endif /* FORBIDDEN_INC_DEC_CLASSES */
194 #ifdef HAVE_SECONDARY_RELOADS
196 /* Sample MEM values for use by memory_move_secondary_cost. */
198 static rtx top_of_stack
[MAX_MACHINE_MODE
];
200 #endif /* HAVE_SECONDARY_RELOADS */
202 /* Linked list of reg_info structures allocated for reg_n_info array.
203 Grouping all of the allocated structures together in one lump
204 means only one call to bzero to clear them, rather than n smaller
206 struct reg_info_data
{
207 struct reg_info_data
*next
; /* next set of reg_info structures */
208 size_t min_index
; /* minimum index # */
209 size_t max_index
; /* maximum index # */
210 char used_p
; /* non-zero if this has been used previously */
211 reg_info data
[1]; /* beginning of the reg_info data */
214 static struct reg_info_data
*reg_info_head
;
217 /* Function called only once to initialize the above data on reg usage.
218 Once this is done, various switches may override. */
225 /* First copy the register information from the initial int form into
228 for (i
= 0; i
< N_REG_CLASSES
; i
++)
230 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
232 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
233 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
234 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
235 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
238 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
239 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
240 bzero (global_regs
, sizeof global_regs
);
242 /* Do any additional initialization regsets may need */
243 INIT_ONCE_REG_SET ();
246 /* After switches have been processed, which perhaps alter
247 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
252 register unsigned int i
, j
;
254 /* This macro allows the fixed or call-used registers
255 and the register classes to depend on target flags. */
257 #ifdef CONDITIONAL_REGISTER_USAGE
258 CONDITIONAL_REGISTER_USAGE
;
261 /* Compute number of hard regs in each class. */
263 bzero ((char *) reg_class_size
, sizeof reg_class_size
);
264 for (i
= 0; i
< N_REG_CLASSES
; i
++)
265 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
266 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
269 /* Initialize the table of subunions.
270 reg_class_subunion[I][J] gets the largest-numbered reg-class
271 that is contained in the union of classes I and J. */
273 for (i
= 0; i
< N_REG_CLASSES
; i
++)
275 for (j
= 0; j
< N_REG_CLASSES
; j
++)
278 register /* Declare it register if it's a scalar. */
283 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
284 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
285 for (k
= 0; k
< N_REG_CLASSES
; k
++)
287 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
292 /* keep the largest subclass */ /* SPEE 900308 */
293 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
294 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
296 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
303 /* Initialize the table of superunions.
304 reg_class_superunion[I][J] gets the smallest-numbered reg-class
305 containing the union of classes I and J. */
307 for (i
= 0; i
< N_REG_CLASSES
; i
++)
309 for (j
= 0; j
< N_REG_CLASSES
; j
++)
312 register /* Declare it register if it's a scalar. */
317 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
318 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
319 for (k
= 0; k
< N_REG_CLASSES
; k
++)
320 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
323 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
327 /* Initialize the tables of subclasses and superclasses of each reg class.
328 First clear the whole table, then add the elements as they are found. */
330 for (i
= 0; i
< N_REG_CLASSES
; i
++)
332 for (j
= 0; j
< N_REG_CLASSES
; j
++)
334 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
335 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
339 for (i
= 0; i
< N_REG_CLASSES
; i
++)
341 if (i
== (int) NO_REGS
)
344 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
348 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
352 /* Reg class I is a subclass of J.
353 Add J to the table of superclasses of I. */
354 p
= ®_class_superclasses
[i
][0];
355 while (*p
!= LIM_REG_CLASSES
) p
++;
356 *p
= (enum reg_class
) j
;
357 /* Add I to the table of superclasses of J. */
358 p
= ®_class_subclasses
[j
][0];
359 while (*p
!= LIM_REG_CLASSES
) p
++;
360 *p
= (enum reg_class
) i
;
364 /* Initialize "constant" tables. */
366 CLEAR_HARD_REG_SET (fixed_reg_set
);
367 CLEAR_HARD_REG_SET (call_used_reg_set
);
368 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
370 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
372 n_non_fixed_regs
= 0;
374 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
377 SET_HARD_REG_BIT (fixed_reg_set
, i
);
381 if (call_used_regs
[i
])
382 SET_HARD_REG_BIT (call_used_reg_set
, i
);
383 if (call_fixed_regs
[i
])
384 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
385 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
386 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
389 /* Initialize the move cost table. Find every subset of each class
390 and take the maximum cost of moving any subset to any other. */
392 for (i
= 0; i
< N_REG_CLASSES
; i
++)
393 for (j
= 0; j
< N_REG_CLASSES
; j
++)
395 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
396 enum reg_class
*p1
, *p2
;
398 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
400 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
402 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
405 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
407 for (p2
= ®_class_subclasses
[j
][0];
408 *p2
!= LIM_REG_CLASSES
; p2
++)
410 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
413 move_cost
[i
][j
] = cost
;
415 if (reg_class_subset_p (i
, j
))
418 may_move_cost
[i
][j
] = cost
;
422 /* Compute the table of register modes.
423 These values are used to record death information for individual registers
424 (as opposed to a multi-register mode). */
431 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
433 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
435 /* If we couldn't find a valid mode, just use the previous mode.
436 ??? One situation in which we need to do this is on the mips where
437 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
438 to use DF mode for the even registers and VOIDmode for the odd
439 (for the cpu models where the odd ones are inaccessible). */
440 if (reg_raw_mode
[i
] == VOIDmode
)
441 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
445 /* Finish initializing the register sets and
446 initialize the register modes. */
451 /* This finishes what was started by init_reg_sets, but couldn't be done
452 until after register usage was specified. */
457 #ifdef HAVE_SECONDARY_RELOADS
459 /* Make some fake stack-frame MEM references for use in
460 memory_move_secondary_cost. */
462 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
463 top_of_stack
[i
] = gen_rtx_MEM (i
, stack_pointer_rtx
);
464 ggc_add_rtx_root (top_of_stack
, MAX_MACHINE_MODE
);
469 #ifdef HAVE_SECONDARY_RELOADS
471 /* Compute extra cost of moving registers to/from memory due to reloads.
472 Only needed if secondary reloads are required for memory moves. */
475 memory_move_secondary_cost (mode
, class, in
)
476 enum machine_mode mode
;
477 enum reg_class
class;
480 enum reg_class altclass
;
481 int partial_cost
= 0;
482 /* We need a memory reference to feed to SECONDARY... macros. */
483 rtx mem
= top_of_stack
[(int) mode
];
487 #ifdef SECONDARY_INPUT_RELOAD_CLASS
488 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
495 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
496 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
502 if (altclass
== NO_REGS
)
506 partial_cost
= REGISTER_MOVE_COST (altclass
, class);
508 partial_cost
= REGISTER_MOVE_COST (class, altclass
);
510 if (class == altclass
)
511 /* This isn't simply a copy-to-temporary situation. Can't guess
512 what it is, so MEMORY_MOVE_COST really ought not to be calling
515 I'm tempted to put in an abort here, but returning this will
516 probably only give poor estimates, which is what we would've
517 had before this code anyways. */
520 /* Check if the secondary reload register will also need a
522 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
526 /* Return a machine mode that is legitimate for hard reg REGNO and large
527 enough to save nregs. If we can't find one, return VOIDmode. */
530 choose_hard_reg_mode (regno
, nregs
)
534 enum machine_mode found_mode
= VOIDmode
, mode
;
536 /* We first look for the largest integer mode that can be validly
537 held in REGNO. If none, we look for the largest floating-point mode.
538 If we still didn't find a valid mode, try CCmode. */
540 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
542 mode
= GET_MODE_WIDER_MODE (mode
))
543 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
544 && HARD_REGNO_MODE_OK (regno
, mode
))
547 if (found_mode
!= VOIDmode
)
550 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
552 mode
= GET_MODE_WIDER_MODE (mode
))
553 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
554 && HARD_REGNO_MODE_OK (regno
, mode
))
557 if (found_mode
!= VOIDmode
)
560 if (HARD_REGNO_NREGS (regno
, CCmode
) == nregs
561 && HARD_REGNO_MODE_OK (regno
, CCmode
))
564 /* We can't find a mode valid for this register. */
568 /* Specify the usage characteristics of the register named NAME.
569 It should be a fixed register if FIXED and a
570 call-used register if CALL_USED. */
573 fix_register (name
, fixed
, call_used
)
575 int fixed
, call_used
;
579 /* Decode the name and update the primary form of
580 the register info. */
582 if ((i
= decode_reg_name (name
)) >= 0)
584 if ((i
== STACK_POINTER_REGNUM
585 #ifdef HARD_FRAME_POINTER_REGNUM
586 || i
== HARD_FRAME_POINTER_REGNUM
588 || i
== FRAME_POINTER_REGNUM
591 && (fixed
== 0 || call_used
== 0))
593 static const char * const what_option
[2][2] = {
594 { "call-saved", "call-used" },
595 { "no-such-option", "fixed" }};
597 error ("can't use '%s' as a %s register", name
,
598 what_option
[fixed
][call_used
]);
602 fixed_regs
[i
] = fixed
;
603 call_used_regs
[i
] = call_used
;
608 warning ("unknown register name: %s", name
);
612 /* Mark register number I as global. */
620 warning ("register used for two global register variables");
624 if (call_used_regs
[i
] && ! fixed_regs
[i
])
625 warning ("call-clobbered register used for global register variable");
629 /* If already fixed, nothing else to do. */
633 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
636 SET_HARD_REG_BIT (fixed_reg_set
, i
);
637 SET_HARD_REG_BIT (call_used_reg_set
, i
);
638 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
641 /* Now the data and code for the `regclass' pass, which happens
642 just before local-alloc. */
644 /* The `costs' struct records the cost of using a hard register of each class
645 and of using memory for each pseudo. We use this data to set up
646 register class preferences. */
650 int cost
[N_REG_CLASSES
];
654 /* Record the cost of each class for each pseudo. */
656 static struct costs
*costs
;
658 /* Initialized once, and used to initialize cost values for each insn. */
660 static struct costs init_cost
;
662 /* Record the same data by operand number, accumulated for each alternative
663 in an insn. The contribution to a pseudo is that of the minimum-cost
666 static struct costs op_costs
[MAX_RECOG_OPERANDS
];
668 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
669 This is available after `regclass' is run. */
671 static char *prefclass
;
673 /* altclass[R] is a register class that we should use for allocating
674 pseudo number R if no register in the preferred class is available.
675 If no register in this class is available, memory is preferred.
677 It might appear to be more general to have a bitmask of classes here,
678 but since it is recommended that there be a class corresponding to the
679 union of most major pair of classes, that generality is not required.
681 This is available after `regclass' is run. */
683 static char *altclass
;
685 /* Allocated buffers for prefclass and altclass. */
686 static char *prefclass_buffer
;
687 static char *altclass_buffer
;
689 /* Record the depth of loops that we are in. */
691 static int loop_depth
;
693 /* Account for the fact that insns within a loop are executed very commonly,
694 but don't keep doing this as loops go too deep. */
696 static int loop_cost
;
698 static rtx scan_one_insn
PROTO((rtx
, int));
699 static void record_reg_classes
PROTO((int, int, rtx
*, enum machine_mode
*,
700 char *, const char **, rtx
));
701 static int copy_cost
PROTO((rtx
, enum machine_mode
,
702 enum reg_class
, int));
703 static void record_address_regs
PROTO((rtx
, enum reg_class
, int));
704 #ifdef FORBIDDEN_INC_DEC_CLASSES
705 static int auto_inc_dec_reg_p
PROTO((rtx
, enum machine_mode
));
707 static void reg_scan_mark_refs
PROTO((rtx
, rtx
, int, int));
709 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
710 This function is sometimes called before the info has been computed.
711 When that happens, just return GENERAL_REGS, which is innocuous. */
714 reg_preferred_class (regno
)
719 return (enum reg_class
) prefclass
[regno
];
723 reg_alternate_class (regno
)
729 return (enum reg_class
) altclass
[regno
];
732 /* Initialize some global data for this pass. */
739 init_cost
.mem_cost
= 10000;
740 for (i
= 0; i
< N_REG_CLASSES
; i
++)
741 init_cost
.cost
[i
] = 10000;
743 /* This prevents dump_flow_info from losing if called
744 before regclass is run. */
748 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
749 time it would save code to put a certain register in a certain class.
750 PASS, when nonzero, inhibits some optimizations which need only be done
752 Return the last insn processed, so that the scan can be continued from
756 scan_one_insn (insn
, pass
)
760 enum rtx_code code
= GET_CODE (insn
);
761 enum rtx_code pat_code
;
762 const char *constraints
[MAX_RECOG_OPERANDS
];
763 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
764 char subreg_changes_size
[MAX_RECOG_OPERANDS
];
768 /* Show that an insn inside a loop is likely to be executed three
769 times more than insns outside a loop. This is much more aggressive
770 than the assumptions made elsewhere and is being tried as an
775 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
776 loop_depth
++, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
777 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
778 loop_depth
--, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
783 if (GET_RTX_CLASS (code
) != 'i')
786 pat_code
= GET_CODE (PATTERN (insn
));
788 || pat_code
== CLOBBER
789 || pat_code
== ASM_INPUT
790 || pat_code
== ADDR_VEC
791 || pat_code
== ADDR_DIFF_VEC
)
794 set
= single_set (insn
);
797 for (i
= 0; i
< recog_data
.n_operands
; i
++)
799 constraints
[i
] = recog_data
.constraints
[i
];
800 modes
[i
] = recog_data
.operand_mode
[i
];
802 memset (subreg_changes_size
, 0, sizeof (subreg_changes_size
));
804 /* If this insn loads a parameter from its stack slot, then
805 it represents a savings, rather than a cost, if the
806 parameter is stored in memory. Record this fact. */
808 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
809 && GET_CODE (SET_SRC (set
)) == MEM
810 && (note
= find_reg_note (insn
, REG_EQUIV
,
812 && GET_CODE (XEXP (note
, 0)) == MEM
)
814 costs
[REGNO (SET_DEST (set
))].mem_cost
815 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
818 record_address_regs (XEXP (SET_SRC (set
), 0),
819 BASE_REG_CLASS
, loop_cost
* 2);
823 /* Improve handling of two-address insns such as
824 (set X (ashift CONST Y)) where CONST must be made to
825 match X. Change it into two insns: (set X CONST)
826 (set X (ashift X Y)). If we left this for reloading, it
827 would probably get three insns because X and Y might go
828 in the same place. This prevents X and Y from receiving
831 We can only do this if the modes of operands 0 and 1
832 (which might not be the same) are tieable and we only need
833 do this during our first pass. */
835 if (pass
== 0 && optimize
836 && recog_data
.n_operands
>= 3
837 && recog_data
.constraints
[1][0] == '0'
838 && recog_data
.constraints
[1][1] == 0
839 && CONSTANT_P (recog_data
.operand
[1])
840 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[1])
841 && ! rtx_equal_p (recog_data
.operand
[0], recog_data
.operand
[2])
842 && GET_CODE (recog_data
.operand
[0]) == REG
843 && MODES_TIEABLE_P (GET_MODE (recog_data
.operand
[0]),
844 recog_data
.operand_mode
[1]))
846 rtx previnsn
= prev_real_insn (insn
);
848 = gen_lowpart (recog_data
.operand_mode
[1],
849 recog_data
.operand
[0]);
851 = emit_insn_before (gen_move_insn (dest
, recog_data
.operand
[1]), insn
);
853 /* If this insn was the start of a basic block,
854 include the new insn in that block.
855 We need not check for code_label here;
856 while a basic block can start with a code_label,
857 INSN could not be at the beginning of that block. */
858 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
861 for (b
= 0; b
< n_basic_blocks
; b
++)
862 if (insn
== BLOCK_HEAD (b
))
863 BLOCK_HEAD (b
) = newinsn
;
866 /* This makes one more setting of new insns's dest. */
867 REG_N_SETS (REGNO (recog_data
.operand
[0]))++;
869 *recog_data
.operand_loc
[1] = recog_data
.operand
[0];
870 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
871 if (recog_data
.dup_num
[i
] == 1)
872 *recog_data
.dup_loc
[i
] = recog_data
.operand
[0];
874 return PREV_INSN (newinsn
);
877 /* If we get here, we are set up to record the costs of all the
878 operands for this insn. Start by initializing the costs.
879 Then handle any address registers. Finally record the desired
880 classes for any pseudos, doing it twice if some pair of
881 operands are commutative. */
883 for (i
= 0; i
< recog_data
.n_operands
; i
++)
885 op_costs
[i
] = init_cost
;
887 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
889 rtx inner
= SUBREG_REG (recog_data
.operand
[i
]);
890 if (GET_MODE_SIZE (modes
[i
]) != GET_MODE_SIZE (GET_MODE (inner
)))
891 subreg_changes_size
[i
] = 1;
892 recog_data
.operand
[i
] = inner
;
895 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
896 record_address_regs (XEXP (recog_data
.operand
[i
], 0),
897 BASE_REG_CLASS
, loop_cost
* 2);
898 else if (constraints
[i
][0] == 'p')
899 record_address_regs (recog_data
.operand
[i
],
900 BASE_REG_CLASS
, loop_cost
* 2);
903 /* Check for commutative in a separate loop so everything will
904 have been initialized. We must do this even if one operand
905 is a constant--see addsi3 in m68k.md. */
907 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
908 if (constraints
[i
][0] == '%')
910 const char *xconstraints
[MAX_RECOG_OPERANDS
];
913 /* Handle commutative operands by swapping the constraints.
914 We assume the modes are the same. */
916 for (j
= 0; j
< recog_data
.n_operands
; j
++)
917 xconstraints
[j
] = constraints
[j
];
919 xconstraints
[i
] = constraints
[i
+1];
920 xconstraints
[i
+1] = constraints
[i
];
921 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
922 recog_data
.operand
, modes
, subreg_changes_size
,
926 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
927 recog_data
.operand
, modes
, subreg_changes_size
,
930 /* Now add the cost for each operand to the total costs for
933 for (i
= 0; i
< recog_data
.n_operands
; i
++)
934 if (GET_CODE (recog_data
.operand
[i
]) == REG
935 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
937 int regno
= REGNO (recog_data
.operand
[i
]);
938 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
940 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
941 for (j
= 0; j
< N_REG_CLASSES
; j
++)
942 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
948 /* This is a pass of the compiler that scans all instructions
949 and calculates the preferred class for each pseudo-register.
950 This information can be accessed later by calling `reg_preferred_class'.
951 This pass comes just before local register allocation. */
964 costs
= (struct costs
*) xmalloc (nregs
* sizeof (struct costs
));
966 #ifdef FORBIDDEN_INC_DEC_CLASSES
968 in_inc_dec
= (char *) xmalloc (nregs
);
970 /* Initialize information about which register classes can be used for
971 pseudos that are auto-incremented or auto-decremented. It would
972 seem better to put this in init_reg_sets, but we need to be able
973 to allocate rtx, which we can't do that early. */
975 for (i
= 0; i
< N_REG_CLASSES
; i
++)
977 rtx r
= gen_rtx_REG (VOIDmode
, 0);
981 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
982 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
986 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
987 m
= (enum machine_mode
) ((int) m
+ 1))
988 if (HARD_REGNO_MODE_OK (j
, m
))
992 /* If a register is not directly suitable for an
993 auto-increment or decrement addressing mode and
994 requires secondary reloads, disallow its class from
995 being used in such addresses. */
998 #ifdef SECONDARY_RELOAD_CLASS
999 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1002 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1003 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1006 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1007 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
1012 && ! auto_inc_dec_reg_p (r
, m
))
1013 forbidden_inc_dec_class
[i
] = 1;
1017 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1019 /* Normally we scan the insns once and determine the best class to use for
1020 each register. However, if -fexpensive_optimizations are on, we do so
1021 twice, the second time using the tentative best classes to guide the
1024 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
1026 /* Zero out our accumulation of the cost of each class for each reg. */
1028 bzero ((char *) costs
, nregs
* sizeof (struct costs
));
1030 #ifdef FORBIDDEN_INC_DEC_CLASSES
1031 bzero (in_inc_dec
, nregs
);
1034 loop_depth
= 0, loop_cost
= 1;
1036 /* Scan the instructions and record each time it would
1037 save code to put a certain register in a certain class. */
1039 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1041 insn
= scan_one_insn (insn
, pass
);
1044 /* Now for each register look at how desirable each class is
1045 and find which class is preferred. Store that in
1046 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1047 class any of whose registers is better than memory. */
1051 prefclass
= prefclass_buffer
;
1052 altclass
= altclass_buffer
;
1055 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
1057 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1058 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
1059 /* This is an enum reg_class, but we call it an int
1060 to save lots of casts. */
1062 register struct costs
*p
= &costs
[i
];
1064 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1066 /* Ignore classes that are too small for this operand or
1067 invalid for a operand that was auto-incremented. */
1068 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
1069 > reg_class_size
[class]
1070 #ifdef FORBIDDEN_INC_DEC_CLASSES
1071 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1075 else if (p
->cost
[class] < best_cost
)
1077 best_cost
= p
->cost
[class];
1078 best
= (enum reg_class
) class;
1080 else if (p
->cost
[class] == best_cost
)
1081 best
= reg_class_subunion
[(int)best
][class];
1084 /* Record the alternate register class; i.e., a class for which
1085 every register in it is better than using memory. If adding a
1086 class would make a smaller class (i.e., no union of just those
1087 classes exists), skip that class. The major unions of classes
1088 should be provided as a register class. Don't do this if we
1089 will be doing it again later. */
1091 if (pass
== 1 || ! flag_expensive_optimizations
)
1092 for (class = 0; class < N_REG_CLASSES
; class++)
1093 if (p
->cost
[class] < p
->mem_cost
1094 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1095 > reg_class_size
[(int) alt
])
1096 #ifdef FORBIDDEN_INC_DEC_CLASSES
1097 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1100 alt
= reg_class_subunion
[(int) alt
][class];
1102 /* If we don't add any classes, nothing to try. */
1106 /* We cast to (int) because (char) hits bugs in some compilers. */
1107 prefclass
[i
] = (int) best
;
1108 altclass
[i
] = (int) alt
;
1112 #ifdef FORBIDDEN_INC_DEC_CLASSES
1118 /* Record the cost of using memory or registers of various classes for
1119 the operands in INSN.
1121 N_ALTS is the number of alternatives.
1123 N_OPS is the number of operands.
1125 OPS is an array of the operands.
1127 MODES are the modes of the operands, in case any are VOIDmode.
1129 CONSTRAINTS are the constraints to use for the operands. This array
1130 is modified by this procedure.
1132 This procedure works alternative by alternative. For each alternative
1133 we assume that we will be able to allocate all pseudos to their ideal
1134 register class and calculate the cost of using that alternative. Then
1135 we compute for each operand that is a pseudo-register, the cost of
1136 having the pseudo allocated to each register class and using it in that
1137 alternative. To this cost is added the cost of the alternative.
1139 The cost of each class for this insn is its lowest cost among all the
1143 record_reg_classes (n_alts
, n_ops
, ops
, modes
, subreg_changes_size
,
1148 enum machine_mode
*modes
;
1149 char *subreg_changes_size
;
1150 const char **constraints
;
1157 /* Process each alternative, each time minimizing an operand's cost with
1158 the cost for each operand in that alternative. */
1160 for (alt
= 0; alt
< n_alts
; alt
++)
1162 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1165 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1166 int allows_mem
[MAX_RECOG_OPERANDS
];
1169 for (i
= 0; i
< n_ops
; i
++)
1171 const char *p
= constraints
[i
];
1173 enum machine_mode mode
= modes
[i
];
1174 int allows_addr
= 0;
1178 /* Initially show we know nothing about the register class. */
1179 classes
[i
] = NO_REGS
;
1182 /* If this operand has no constraints at all, we can conclude
1183 nothing about it since anything is valid. */
1187 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1188 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
1193 /* If this alternative is only relevant when this operand
1194 matches a previous operand, we do different things depending
1195 on whether this operand is a pseudo-reg or not. We must process
1196 any modifiers for the operand before we can make this test. */
1198 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
1201 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1203 /* Copy class and whether memory is allowed from the matching
1204 alternative. Then perform any needed cost computations
1205 and/or adjustments. */
1207 classes
[i
] = classes
[j
];
1208 allows_mem
[i
] = allows_mem
[j
];
1210 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1212 /* If this matches the other operand, we have no added
1214 if (rtx_equal_p (ops
[j
], op
))
1217 /* If we can put the other operand into a register, add to
1218 the cost of this alternative the cost to copy this
1219 operand to the register used for the other operand. */
1221 else if (classes
[j
] != NO_REGS
)
1222 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1224 else if (GET_CODE (ops
[j
]) != REG
1225 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1227 /* This op is a pseudo but the one it matches is not. */
1229 /* If we can't put the other operand into a register, this
1230 alternative can't be used. */
1232 if (classes
[j
] == NO_REGS
)
1235 /* Otherwise, add to the cost of this alternative the cost
1236 to copy the other operand to the register used for this
1240 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1244 /* The costs of this operand are not the same as the other
1245 operand since move costs are not symmetric. Moreover,
1246 if we cannot tie them, this alternative needs to do a
1247 copy, which is one instruction. */
1249 struct costs
*pp
= &this_op_costs
[i
];
1251 for (class = 0; class < N_REG_CLASSES
; class++)
1253 = (recog_data
.operand_type
[i
] == OP_IN
1254 ? may_move_cost
[class][(int) classes
[i
]]
1255 : may_move_cost
[(int) classes
[i
]][class]);
1257 /* If the alternative actually allows memory, make things
1258 a bit cheaper since we won't need an extra insn to
1262 = (MEMORY_MOVE_COST (mode
, classes
[i
],
1263 recog_data
.operand_type
[i
] == OP_IN
)
1266 /* If we have assigned a class to this register in our
1267 first pass, add a cost to this alternative corresponding
1268 to what we would add if this register were not in the
1269 appropriate class. */
1273 += (may_move_cost
[(unsigned char) prefclass
[REGNO (op
)]]
1274 [(int) classes
[i
]]);
1276 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1277 && ! find_reg_note (insn
, REG_DEAD
, op
))
1280 /* This is in place of ordinary cost computation
1281 for this operand, so skip to the end of the
1282 alternative (should be just one character). */
1283 while (*p
&& *p
++ != ',')
1291 /* Scan all the constraint letters. See if the operand matches
1292 any of the constraints. Collect the valid register classes
1293 and see if this operand accepts memory. */
1295 while (*p
&& (c
= *p
++) != ',')
1299 /* Ignore the next letter for this pass. */
1305 case '!': case '#': case '&':
1306 case '0': case '1': case '2': case '3': case '4':
1307 case '5': case '6': case '7': case '8': case '9':
1312 win
= address_operand (op
, GET_MODE (op
));
1313 /* We know this operand is an address, so we want it to be
1314 allocated to a register that can be the base of an
1315 address, ie BASE_REG_CLASS. */
1317 = reg_class_subunion
[(int) classes
[i
]]
1318 [(int) BASE_REG_CLASS
];
1321 case 'm': case 'o': case 'V':
1322 /* It doesn't seem worth distinguishing between offsettable
1323 and non-offsettable addresses here. */
1325 if (GET_CODE (op
) == MEM
)
1330 if (GET_CODE (op
) == MEM
1331 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1332 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1337 if (GET_CODE (op
) == MEM
1338 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1339 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1344 #ifndef REAL_ARITHMETIC
1345 /* Match any floating double constant, but only if
1346 we can examine the bits of it reliably. */
1347 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1348 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1349 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1352 if (GET_CODE (op
) == CONST_DOUBLE
)
1357 if (GET_CODE (op
) == CONST_DOUBLE
)
1363 if (GET_CODE (op
) == CONST_DOUBLE
1364 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1369 if (GET_CODE (op
) == CONST_INT
1370 || (GET_CODE (op
) == CONST_DOUBLE
1371 && GET_MODE (op
) == VOIDmode
))
1375 #ifdef LEGITIMATE_PIC_OPERAND_P
1376 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1383 if (GET_CODE (op
) == CONST_INT
1384 || (GET_CODE (op
) == CONST_DOUBLE
1385 && GET_MODE (op
) == VOIDmode
))
1397 if (GET_CODE (op
) == CONST_INT
1398 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1406 #ifdef EXTRA_CONSTRAINT
1412 if (EXTRA_CONSTRAINT (op
, c
))
1418 if (GET_CODE (op
) == MEM
1420 #ifdef LEGITIMATE_PIC_OPERAND_P
1421 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1428 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1433 = reg_class_subunion
[(int) classes
[i
]]
1434 [(int) REG_CLASS_FROM_LETTER (c
)];
1439 #ifdef CLASS_CANNOT_CHANGE_SIZE
1440 /* If we noted a subreg earlier, and the selected class is a
1441 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1442 if (subreg_changes_size
[i
]
1443 && (reg_class_subunion
[(int) CLASS_CANNOT_CHANGE_SIZE
]
1445 == CLASS_CANNOT_CHANGE_SIZE
))
1446 classes
[i
] = NO_REGS
;
1449 /* How we account for this operand now depends on whether it is a
1450 pseudo register or not. If it is, we first check if any
1451 register classes are valid. If not, we ignore this alternative,
1452 since we want to assume that all pseudos get allocated for
1453 register preferencing. If some register class is valid, compute
1454 the costs of moving the pseudo into that class. */
1456 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1458 if (classes
[i
] == NO_REGS
)
1460 /* We must always fail if the operand is a REG, but
1461 we did not find a suitable class.
1463 Otherwise we may perform an uninitialized read
1464 from this_op_costs after the `continue' statement
1470 struct costs
*pp
= &this_op_costs
[i
];
1472 for (class = 0; class < N_REG_CLASSES
; class++)
1474 = (recog_data
.operand_type
[i
] == OP_IN
1475 ? may_move_cost
[class][(int) classes
[i
]]
1476 : may_move_cost
[(int) classes
[i
]][class]);
1478 /* If the alternative actually allows memory, make things
1479 a bit cheaper since we won't need an extra insn to
1483 = (MEMORY_MOVE_COST (mode
, classes
[i
],
1484 recog_data
.operand_type
[i
] == OP_IN
)
1487 /* If we have assigned a class to this register in our
1488 first pass, add a cost to this alternative corresponding
1489 to what we would add if this register were not in the
1490 appropriate class. */
1494 += (may_move_cost
[(unsigned char) prefclass
[REGNO (op
)]]
1495 [(int) classes
[i
]]);
1499 /* Otherwise, if this alternative wins, either because we
1500 have already determined that or if we have a hard register of
1501 the proper class, there is no cost for this alternative. */
1504 || (GET_CODE (op
) == REG
1505 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1508 /* If registers are valid, the cost of this alternative includes
1509 copying the object to and/or from a register. */
1511 else if (classes
[i
] != NO_REGS
)
1513 if (recog_data
.operand_type
[i
] != OP_OUT
)
1514 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1516 if (recog_data
.operand_type
[i
] != OP_IN
)
1517 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1520 /* The only other way this alternative can be used is if this is a
1521 constant that could be placed into memory. */
1523 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
1524 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1532 /* Finally, update the costs with the information we've calculated
1533 about this alternative. */
1535 for (i
= 0; i
< n_ops
; i
++)
1536 if (GET_CODE (ops
[i
]) == REG
1537 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1539 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1540 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
1542 pp
->mem_cost
= MIN (pp
->mem_cost
,
1543 (qq
->mem_cost
+ alt_cost
) * scale
);
1545 for (class = 0; class < N_REG_CLASSES
; class++)
1546 pp
->cost
[class] = MIN (pp
->cost
[class],
1547 (qq
->cost
[class] + alt_cost
) * scale
);
1551 /* If this insn is a single set copying operand 1 to operand 0
1552 and one is a pseudo with the other a hard reg that is in its
1553 own register class, set the cost of that register class to -1. */
1555 if ((set
= single_set (insn
)) != 0
1556 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1557 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
)
1558 for (i
= 0; i
<= 1; i
++)
1559 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1561 int regno
= REGNO (ops
[!i
]);
1562 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1566 if (regno
>= FIRST_PSEUDO_REGISTER
&& prefclass
!= 0
1567 && (reg_class_size
[(unsigned char) prefclass
[regno
]]
1568 == CLASS_MAX_NREGS (prefclass
[regno
], mode
)))
1569 op_costs
[i
].cost
[(unsigned char) prefclass
[regno
]] = -1;
1570 else if (regno
< FIRST_PSEUDO_REGISTER
)
1571 for (class = 0; class < N_REG_CLASSES
; class++)
1572 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1573 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1575 if (reg_class_size
[class] == 1)
1576 op_costs
[i
].cost
[class] = -1;
1579 for (nr
= 0; nr
< HARD_REGNO_NREGS(regno
, mode
); nr
++)
1581 if (!TEST_HARD_REG_BIT (reg_class_contents
[class], regno
+ nr
))
1585 if (nr
== HARD_REGNO_NREGS(regno
,mode
))
1586 op_costs
[i
].cost
[class] = -1;
1592 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1593 TO_P is zero) a register of class CLASS in mode MODE.
1595 X must not be a pseudo. */
1598 copy_cost (x
, mode
, class, to_p
)
1600 enum machine_mode mode
;
1601 enum reg_class
class;
1604 #ifdef HAVE_SECONDARY_RELOADS
1605 enum reg_class secondary_class
= NO_REGS
;
1608 /* If X is a SCRATCH, there is actually nothing to move since we are
1609 assuming optimal allocation. */
1611 if (GET_CODE (x
) == SCRATCH
)
1614 /* Get the class we will actually use for a reload. */
1615 class = PREFERRED_RELOAD_CLASS (x
, class);
1617 #ifdef HAVE_SECONDARY_RELOADS
1618 /* If we need a secondary reload (we assume here that we are using
1619 the secondary reload as an intermediate, not a scratch register), the
1620 cost is that to load the input into the intermediate register, then
1621 to copy them. We use a special value of TO_P to avoid recursion. */
1623 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1625 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1628 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1630 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1633 if (secondary_class
!= NO_REGS
)
1634 return (move_cost
[(int) secondary_class
][(int) class]
1635 + copy_cost (x
, mode
, secondary_class
, 2));
1636 #endif /* HAVE_SECONDARY_RELOADS */
1638 /* For memory, use the memory move cost, for (hard) registers, use the
1639 cost to move between the register classes, and use 2 for everything
1640 else (constants). */
1642 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1643 return MEMORY_MOVE_COST (mode
, class, to_p
);
1645 else if (GET_CODE (x
) == REG
)
1646 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1649 /* If this is a constant, we may eventually want to call rtx_cost here. */
1653 /* Record the pseudo registers we must reload into hard registers
1654 in a subexpression of a memory address, X.
1656 CLASS is the class that the register needs to be in and is either
1657 BASE_REG_CLASS or INDEX_REG_CLASS.
1659 SCALE is twice the amount to multiply the cost by (it is twice so we
1660 can represent half-cost adjustments). */
1663 record_address_regs (x
, class, scale
)
1665 enum reg_class
class;
1668 register enum rtx_code code
= GET_CODE (x
);
1681 /* When we have an address that is a sum,
1682 we must determine whether registers are "base" or "index" regs.
1683 If there is a sum of two registers, we must choose one to be
1684 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1685 to make a good choice most of the time. We only need to do this
1686 on machines that can have two registers in an address and where
1687 the base and index register classes are different.
1689 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1690 that seems bogus since it should only be set when we are sure
1691 the register is being used as a pointer. */
1694 rtx arg0
= XEXP (x
, 0);
1695 rtx arg1
= XEXP (x
, 1);
1696 register enum rtx_code code0
= GET_CODE (arg0
);
1697 register enum rtx_code code1
= GET_CODE (arg1
);
1699 /* Look inside subregs. */
1700 if (code0
== SUBREG
)
1701 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1702 if (code1
== SUBREG
)
1703 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1705 /* If this machine only allows one register per address, it must
1706 be in the first operand. */
1708 if (MAX_REGS_PER_ADDRESS
== 1)
1709 record_address_regs (arg0
, class, scale
);
1711 /* If index and base registers are the same on this machine, just
1712 record registers in any non-constant operands. We assume here,
1713 as well as in the tests below, that all addresses are in
1716 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1718 record_address_regs (arg0
, class, scale
);
1719 if (! CONSTANT_P (arg1
))
1720 record_address_regs (arg1
, class, scale
);
1723 /* If the second operand is a constant integer, it doesn't change
1724 what class the first operand must be. */
1726 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1727 record_address_regs (arg0
, class, scale
);
1729 /* If the second operand is a symbolic constant, the first operand
1730 must be an index register. */
1732 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1733 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1735 /* If both operands are registers but one is already a hard register
1736 of index or base class, give the other the class that the hard
1739 #ifdef REG_OK_FOR_BASE_P
1740 else if (code0
== REG
&& code1
== REG
1741 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1742 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1743 record_address_regs (arg1
,
1744 REG_OK_FOR_BASE_P (arg0
)
1745 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1747 else if (code0
== REG
&& code1
== REG
1748 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1749 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1750 record_address_regs (arg0
,
1751 REG_OK_FOR_BASE_P (arg1
)
1752 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1756 /* If one operand is known to be a pointer, it must be the base
1757 with the other operand the index. Likewise if the other operand
1760 else if ((code0
== REG
&& REGNO_POINTER_FLAG (REGNO (arg0
)))
1763 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1764 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1766 else if ((code1
== REG
&& REGNO_POINTER_FLAG (REGNO (arg1
)))
1769 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1770 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1773 /* Otherwise, count equal chances that each might be a base
1774 or index register. This case should be rare. */
1778 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1779 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1780 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1781 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1790 /* Double the importance of a pseudo register that is incremented
1791 or decremented, since it would take two extra insns
1792 if it ends up in the wrong place. If the operand is a pseudo,
1793 show it is being used in an INC_DEC context. */
1795 #ifdef FORBIDDEN_INC_DEC_CLASSES
1796 if (GET_CODE (XEXP (x
, 0)) == REG
1797 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1798 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1801 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1806 register struct costs
*pp
= &costs
[REGNO (x
)];
1809 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
1811 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1812 pp
->cost
[i
] += (may_move_cost
[i
][(int) class] * scale
) / 2;
1818 register const char *fmt
= GET_RTX_FORMAT (code
);
1820 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1822 record_address_regs (XEXP (x
, i
), class, scale
);
1827 #ifdef FORBIDDEN_INC_DEC_CLASSES
1829 /* Return 1 if REG is valid as an auto-increment memory reference
1830 to an object of MODE. */
1833 auto_inc_dec_reg_p (reg
, mode
)
1835 enum machine_mode mode
;
1837 if (HAVE_POST_INCREMENT
1838 && memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
1841 if (HAVE_POST_DECREMENT
1842 && memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
1845 if (HAVE_PRE_INCREMENT
1846 && memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
1849 if (HAVE_PRE_DECREMENT
1850 && memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
1857 static short *renumber
= (short *)0;
1858 static size_t regno_allocated
= 0;
1860 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1861 reg_scan and flow_analysis that are indexed by the register number. If
1862 NEW_P is non zero, initialize all of the registers, otherwise only
1863 initialize the new registers allocated. The same table is kept from
1864 function to function, only reallocating it when we need more room. If
1865 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1868 allocate_reg_info (num_regs
, new_p
, renumber_p
)
1874 size_t size_renumber
;
1875 size_t min
= (new_p
) ? 0 : reg_n_max
;
1876 struct reg_info_data
*reg_data
;
1877 struct reg_info_data
*reg_next
;
1879 if (num_regs
> regno_allocated
)
1881 size_t old_allocated
= regno_allocated
;
1883 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
1884 size_renumber
= regno_allocated
* sizeof (short);
1888 VARRAY_REG_INIT (reg_n_info
, regno_allocated
, "reg_n_info");
1889 renumber
= (short *) xmalloc (size_renumber
);
1890 prefclass_buffer
= (char *) xmalloc (regno_allocated
);
1891 altclass_buffer
= (char *) xmalloc (regno_allocated
);
1896 VARRAY_GROW (reg_n_info
, regno_allocated
);
1898 if (new_p
) /* if we're zapping everything, no need to realloc */
1900 free ((char *)renumber
);
1901 free ((char *)prefclass_buffer
);
1902 free ((char *)altclass_buffer
);
1903 renumber
= (short *) xmalloc (size_renumber
);
1904 prefclass_buffer
= (char *) xmalloc (regno_allocated
);
1905 altclass_buffer
= (char *) xmalloc (regno_allocated
);
1910 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
1911 prefclass_buffer
= (char *) xrealloc ((char *)prefclass_buffer
,
1914 altclass_buffer
= (char *) xrealloc ((char *)altclass_buffer
,
1919 size_info
= (regno_allocated
- old_allocated
) * sizeof (reg_info
)
1920 + sizeof (struct reg_info_data
) - sizeof (reg_info
);
1921 reg_data
= (struct reg_info_data
*) xcalloc (size_info
, 1);
1922 reg_data
->min_index
= old_allocated
;
1923 reg_data
->max_index
= regno_allocated
- 1;
1924 reg_data
->next
= reg_info_head
;
1925 reg_info_head
= reg_data
;
1928 reg_n_max
= num_regs
;
1931 /* Loop through each of the segments allocated for the actual
1932 reg_info pages, and set up the pointers, zero the pages, etc. */
1933 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
1935 size_t min_index
= reg_data
->min_index
;
1936 size_t max_index
= reg_data
->max_index
;
1938 reg_next
= reg_data
->next
;
1939 if (min
<= max_index
)
1941 size_t max
= max_index
;
1942 size_t local_min
= min
- min_index
;
1945 if (min
< min_index
)
1947 if (!reg_data
->used_p
) /* page just allocated with calloc */
1948 reg_data
->used_p
= 1; /* no need to zero */
1950 bzero ((char *) ®_data
->data
[local_min
],
1951 sizeof (reg_info
) * (max
- min_index
- local_min
+ 1));
1953 for (i
= min_index
+local_min
; i
<= max
; i
++)
1955 VARRAY_REG (reg_n_info
, i
) = ®_data
->data
[i
-min_index
];
1956 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
1958 prefclass_buffer
[i
] = (char) NO_REGS
;
1959 altclass_buffer
[i
] = (char) NO_REGS
;
1965 /* If {pref,alt}class have already been allocated, update the pointers to
1966 the newly realloced ones. */
1969 prefclass
= prefclass_buffer
;
1970 altclass
= altclass_buffer
;
1974 reg_renumber
= renumber
;
1976 /* Tell the regset code about the new number of registers */
1977 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
1980 /* Free up the space allocated by allocate_reg_info. */
1986 struct reg_info_data
*reg_data
;
1987 struct reg_info_data
*reg_next
;
1989 VARRAY_FREE (reg_n_info
);
1990 for (reg_data
= reg_info_head
; reg_data
; reg_data
= reg_next
)
1992 reg_next
= reg_data
->next
;
1993 free ((char *)reg_data
);
1996 free (prefclass_buffer
);
1997 free (altclass_buffer
);
1998 prefclass_buffer
= (char *)0;
1999 altclass_buffer
= (char *)0;
2000 reg_info_head
= (struct reg_info_data
*)0;
2001 renumber
= (short *)0;
2003 regno_allocated
= 0;
2007 /* This is the `regscan' pass of the compiler, run just before cse
2008 and again just before loop.
2010 It finds the first and last use of each pseudo-register
2011 and records them in the vectors regno_first_uid, regno_last_uid
2012 and counts the number of sets in the vector reg_n_sets.
2014 REPEAT is nonzero the second time this is called. */
2016 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2017 Always at least 3, since the combiner could put that many together
2018 and we want this to remain correct for all the remaining passes. */
2023 reg_scan (f
, nregs
, repeat
)
2030 allocate_reg_info (nregs
, TRUE
, FALSE
);
2033 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
2034 if (GET_CODE (insn
) == INSN
2035 || GET_CODE (insn
) == CALL_INSN
2036 || GET_CODE (insn
) == JUMP_INSN
)
2038 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2039 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2040 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2041 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, 0);
2043 if (REG_NOTES (insn
))
2044 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, 0);
2048 /* Update 'regscan' information by looking at the insns
2049 from FIRST to LAST. Some new REGs have been created,
2050 and any REG with number greater than OLD_MAX_REGNO is
2051 such a REG. We only update information for those. */
2054 reg_scan_update(first
, last
, old_max_regno
)
2061 allocate_reg_info (max_reg_num (), FALSE
, FALSE
);
2063 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
2064 if (GET_CODE (insn
) == INSN
2065 || GET_CODE (insn
) == CALL_INSN
2066 || GET_CODE (insn
) == JUMP_INSN
)
2068 if (GET_CODE (PATTERN (insn
)) == PARALLEL
2069 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
2070 max_parallel
= XVECLEN (PATTERN (insn
), 0);
2071 reg_scan_mark_refs (PATTERN (insn
), insn
, 0, old_max_regno
);
2073 if (REG_NOTES (insn
))
2074 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1, old_max_regno
);
2078 /* X is the expression to scan. INSN is the insn it appears in.
2079 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2080 We should only record information for REGs with numbers
2081 greater than or equal to MIN_REGNO. */
2084 reg_scan_mark_refs (x
, insn
, note_flag
, min_regno
)
2090 register enum rtx_code code
;
2094 code
= GET_CODE (x
);
2110 register int regno
= REGNO (x
);
2112 if (regno
>= min_regno
)
2114 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
2116 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
2117 if (REGNO_FIRST_UID (regno
) == 0)
2118 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
2125 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
, min_regno
);
2127 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2132 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
, min_regno
);
2136 /* Count a set of the destination if it is a register. */
2137 for (dest
= SET_DEST (x
);
2138 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
2139 || GET_CODE (dest
) == ZERO_EXTEND
;
2140 dest
= XEXP (dest
, 0))
2143 if (GET_CODE (dest
) == REG
2144 && REGNO (dest
) >= min_regno
)
2145 REG_N_SETS (REGNO (dest
))++;
2147 /* If this is setting a pseudo from another pseudo or the sum of a
2148 pseudo and a constant integer and the other pseudo is known to be
2149 a pointer, set the destination to be a pointer as well.
2151 Likewise if it is setting the destination from an address or from a
2152 value equivalent to an address or to the sum of an address and
2155 But don't do any of this if the pseudo corresponds to a user
2156 variable since it should have already been set as a pointer based
2159 if (GET_CODE (SET_DEST (x
)) == REG
2160 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
2161 && REGNO (SET_DEST (x
)) >= min_regno
2162 /* If the destination pseudo is set more than once, then other
2163 sets might not be to a pointer value (consider access to a
2164 union in two threads of control in the presense of global
2165 optimizations). So only set REGNO_POINTER_FLAG on the destination
2166 pseudo if this is the only set of that pseudo. */
2167 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
2168 && ! REG_USERVAR_P (SET_DEST (x
))
2169 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
2170 && ((GET_CODE (SET_SRC (x
)) == REG
2171 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
2172 || ((GET_CODE (SET_SRC (x
)) == PLUS
2173 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2174 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2175 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2176 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
2177 || GET_CODE (SET_SRC (x
)) == CONST
2178 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
2179 || GET_CODE (SET_SRC (x
)) == LABEL_REF
2180 || (GET_CODE (SET_SRC (x
)) == HIGH
2181 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
2182 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
2183 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
2184 || ((GET_CODE (SET_SRC (x
)) == PLUS
2185 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
2186 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
2187 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
2188 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
2189 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
2190 && (GET_CODE (XEXP (note
, 0)) == CONST
2191 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
2192 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
2193 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
2195 /* ... fall through ... */
2199 register const char *fmt
= GET_RTX_FORMAT (code
);
2201 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2204 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
, min_regno
);
2205 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
2208 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2209 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
, min_regno
);
2216 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2220 reg_class_subset_p (c1
, c2
)
2221 register enum reg_class c1
;
2222 register enum reg_class c2
;
2224 if (c1
== c2
) return 1;
2229 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2230 reg_class_contents
[(int)c2
],
2235 /* Return nonzero if there is a register that is in both C1 and C2. */
2238 reg_classes_intersect_p (c1
, c2
)
2239 register enum reg_class c1
;
2240 register enum reg_class c2
;
2247 if (c1
== c2
) return 1;
2249 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2252 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2253 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2255 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2262 /* Release any memory allocated by register sets. */
2265 regset_release_memory ()
2267 bitmap_release_memory ();