1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2019 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 ; Predicate for stack protector guard's address in
35 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
36 (define_predicate "guard_addr_operand"
39 return (CONSTANT_ADDRESS_P (op)
40 || !targetm.cannot_force_const_mem (mode, op));
43 ; Predicate for stack protector guard in stack_protect_combined_set and
44 ; stack_protect_combined_test patterns
45 (define_predicate "guard_operand"
48 return guard_addr_operand (XEXP (op, 0), mode);
51 (define_predicate "imm_for_neon_inv_logic_operand"
52 (match_code "const_vector")
55 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
58 (define_predicate "neon_inv_logic_op2"
59 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
60 (match_operand 0 "s_register_operand")))
62 (define_predicate "imm_for_neon_logic_operand"
63 (match_code "const_vector")
66 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
69 (define_predicate "neon_logic_op2"
70 (ior (match_operand 0 "imm_for_neon_logic_operand")
71 (match_operand 0 "s_register_operand")))
73 ;; Any general register.
74 (define_predicate "arm_hard_general_register_operand"
77 return REGNO (op) <= LAST_ARM_REGNUM;
81 (define_predicate "low_register_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
85 ;; A low register or const_int.
86 (define_predicate "low_reg_or_int_operand"
87 (ior (match_code "const_int")
88 (match_operand 0 "low_register_operand")))
90 ;; Any core register, or any pseudo. */
91 (define_predicate "arm_general_register_operand"
92 (match_code "reg,subreg")
94 if (GET_CODE (op) == SUBREG)
98 && (REGNO (op) <= LAST_ARM_REGNUM
99 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
102 (define_predicate "arm_general_adddi_operand"
103 (ior (match_operand 0 "arm_general_register_operand")
104 (and (match_code "const_int")
105 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
107 (define_predicate "vfp_register_operand"
108 (match_code "reg,subreg")
110 if (GET_CODE (op) == SUBREG)
111 op = SUBREG_REG (op);
113 /* We don't consider registers whose class is NO_REGS
114 to be a register operand. */
116 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
117 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
118 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
120 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
123 (define_predicate "vfp_hard_register_operand"
126 return (IS_VFP_REGNUM (REGNO (op)));
129 (define_predicate "zero_operand"
130 (and (match_code "const_int,const_double,const_vector")
131 (match_test "op == CONST0_RTX (mode)")))
133 ;; Match a register, or zero in the appropriate mode.
134 (define_predicate "reg_or_zero_operand"
135 (ior (match_operand 0 "s_register_operand")
136 (match_operand 0 "zero_operand")))
138 (define_special_predicate "subreg_lowpart_operator"
139 (and (match_code "subreg")
140 (match_test "subreg_lowpart_p (op)")))
142 ;; Reg, subreg(reg) or const_int.
143 (define_predicate "reg_or_int_operand"
144 (ior (match_code "const_int")
145 (match_operand 0 "s_register_operand")))
147 (define_predicate "arm_immediate_operand"
148 (and (match_code "const_int")
149 (match_test "const_ok_for_arm (INTVAL (op))")))
151 ;; A constant value which fits into two instructions, each taking
152 ;; an arithmetic constant operand for one of the words.
153 (define_predicate "arm_immediate_di_operand"
154 (and (match_code "const_int,const_double")
155 (match_test "arm_const_double_by_immediates (op)")))
157 (define_predicate "arm_neg_immediate_operand"
158 (and (match_code "const_int")
159 (match_test "const_ok_for_arm (-INTVAL (op))")))
161 (define_predicate "arm_not_immediate_operand"
162 (and (match_code "const_int")
163 (match_test "const_ok_for_arm (~INTVAL (op))")))
165 (define_predicate "const0_operand"
166 (match_test "op == CONST0_RTX (mode)"))
168 ;; Something valid on the RHS of an ARM data-processing instruction
169 (define_predicate "arm_rhs_operand"
170 (ior (match_operand 0 "s_register_operand")
171 (match_operand 0 "arm_immediate_operand")))
173 (define_predicate "arm_rhsm_operand"
174 (ior (match_operand 0 "arm_rhs_operand")
175 (match_operand 0 "memory_operand")))
177 (define_predicate "const_int_I_operand"
178 (and (match_operand 0 "const_int_operand")
179 (match_test "satisfies_constraint_I (op)")))
181 (define_predicate "const_int_M_operand"
182 (and (match_operand 0 "const_int_operand")
183 (match_test "satisfies_constraint_M (op)")))
185 ;; This doesn't have to do much because the constant is already checked
186 ;; in the shift_operator predicate.
187 (define_predicate "shift_amount_operand"
188 (ior (and (match_test "TARGET_ARM")
189 (match_operand 0 "s_register_operand"))
190 (match_operand 0 "const_int_operand")))
192 (define_predicate "const_neon_scalar_shift_amount_operand"
193 (and (match_code "const_int")
194 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
196 (define_predicate "ldrd_strd_offset_operand"
197 (and (match_operand 0 "const_int_operand")
198 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
200 (define_predicate "arm_add_operand"
201 (ior (match_operand 0 "arm_rhs_operand")
202 (match_operand 0 "arm_neg_immediate_operand")))
204 (define_predicate "arm_adddi_operand"
205 (ior (match_operand 0 "s_register_operand")
206 (and (match_code "const_int")
207 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
209 (define_predicate "arm_addimm_operand"
210 (ior (match_operand 0 "arm_immediate_operand")
211 (match_operand 0 "arm_neg_immediate_operand")))
213 (define_predicate "arm_not_operand"
214 (ior (match_operand 0 "arm_rhs_operand")
215 (match_operand 0 "arm_not_immediate_operand")))
217 (define_predicate "arm_di_operand"
218 (ior (match_operand 0 "s_register_operand")
219 (match_operand 0 "arm_immediate_di_operand")))
221 ;; True if the operand is a memory reference which contains an
222 ;; offsettable address.
223 (define_predicate "offsettable_memory_operand"
224 (and (match_code "mem")
226 "offsettable_address_p (reload_completed | reload_in_progress,
227 mode, XEXP (op, 0))")))
229 ;; True if the operand is a memory operand that does not have an
230 ;; automodified base register (and thus will not generate output reloads).
231 (define_predicate "call_memory_operand"
232 (and (match_code "mem")
233 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
235 (match_operand 0 "memory_operand"))))
237 (define_predicate "arm_reload_memory_operand"
238 (and (match_code "mem,reg,subreg")
239 (match_test "(!CONSTANT_P (op)
240 && (true_regnum(op) == -1
242 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
244 (define_predicate "vfp_compare_operand"
245 (ior (match_operand 0 "s_register_operand")
246 (and (match_code "const_double")
247 (match_test "arm_const_double_rtx (op)"))))
249 ;; True for valid index operands.
250 (define_predicate "index_operand"
251 (ior (match_operand 0 "s_register_operand")
252 (and (match_operand 0 "immediate_operand")
253 (match_test "(!CONST_INT_P (op)
254 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
256 ;; True for operators that can be combined with a shift in ARM state.
257 (define_special_predicate "shiftable_operator"
258 (and (match_code "plus,minus,ior,xor,and")
259 (match_test "mode == GET_MODE (op)")))
261 (define_special_predicate "shiftable_operator_strict_it"
262 (and (match_code "plus,and")
263 (match_test "mode == GET_MODE (op)")))
265 ;; True for logical binary operators.
266 (define_special_predicate "logical_binary_operator"
267 (and (match_code "ior,xor,and")
268 (match_test "mode == GET_MODE (op)")))
270 ;; True for commutative operators
271 (define_special_predicate "commutative_binary_operator"
272 (and (match_code "ior,xor,and,plus")
273 (match_test "mode == GET_MODE (op)")))
275 ;; True for shift operators.
277 ;; * mult is only permitted with a constant shift amount
278 ;; * patterns that permit register shift amounts only in ARM mode use
279 ;; shift_amount_operand, patterns that always allow registers do not,
280 ;; so we don't have to worry about that sort of thing here.
281 (define_special_predicate "shift_operator"
282 (and (ior (ior (and (match_code "mult")
283 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
284 (and (match_code "rotate")
285 (match_test "CONST_INT_P (XEXP (op, 1))
286 && (UINTVAL (XEXP (op, 1))) < 32")))
287 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
288 (match_test "!CONST_INT_P (XEXP (op, 1))
289 || (UINTVAL (XEXP (op, 1))) < 32")))
290 (match_test "mode == GET_MODE (op)")))
292 (define_special_predicate "shift_nomul_operator"
293 (and (ior (and (match_code "rotate")
294 (match_test "CONST_INT_P (XEXP (op, 1))
295 && (UINTVAL (XEXP (op, 1))) < 32"))
296 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
297 (match_test "!CONST_INT_P (XEXP (op, 1))
298 || (UINTVAL (XEXP (op, 1))) < 32")))
299 (match_test "mode == GET_MODE (op)")))
301 ;; True for shift operators which can be used with saturation instructions.
302 (define_special_predicate "sat_shift_operator"
303 (and (ior (and (match_code "mult")
304 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
305 (and (match_code "ashift,ashiftrt")
306 (match_test "CONST_INT_P (XEXP (op, 1))
307 && (UINTVAL (XEXP (op, 1)) < 32)")))
308 (match_test "mode == GET_MODE (op)")))
310 ;; True for MULT, to identify which variant of shift_operator is in use.
311 (define_special_predicate "mult_operator"
314 ;; True for operators that have 16-bit thumb variants. */
315 (define_special_predicate "thumb_16bit_operator"
316 (match_code "plus,minus,and,ior,xor"))
319 (define_special_predicate "equality_operator"
320 (match_code "eq,ne"))
322 ;; True for integer comparisons and, if FP is active, for comparisons
323 ;; other than LTGT or UNEQ.
324 (define_special_predicate "expandable_comparison_operator"
325 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
326 unordered,ordered,unlt,unle,unge,ungt"))
328 ;; Likewise, but only accept comparisons that are directly supported
329 ;; by ARM condition codes.
330 (define_special_predicate "arm_comparison_operator"
331 (and (match_operand 0 "expandable_comparison_operator")
332 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
334 ;; Likewise, but don't ignore the mode.
335 ;; RTL SET operations require their operands source and destination have
336 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
337 (define_predicate "arm_comparison_operator_mode"
338 (and (match_operand 0 "expandable_comparison_operator")
339 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
341 (define_special_predicate "lt_ge_comparison_operator"
342 (match_code "lt,ge"))
344 ;; Match a "borrow" operation for use with SBC. The precise code will
345 ;; depend on the form of the comparison. This is generally the inverse of
346 ;; a carry operation, since the logic of SBC uses "not borrow" in it's
348 (define_special_predicate "arm_borrow_operation"
349 (match_code "geu,ltu")
351 if (XEXP (op, 1) != const0_rtx)
353 rtx op0 = XEXP (op, 0);
354 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
356 machine_mode ccmode = GET_MODE (op0);
357 if (ccmode == CC_Cmode)
358 return GET_CODE (op) == GEU;
359 else if (ccmode == CCmode)
360 return GET_CODE (op) == LTU;
365 ;; The vsel instruction only accepts the ARM condition codes listed below.
366 (define_special_predicate "arm_vsel_comparison_operator"
367 (and (match_operand 0 "expandable_comparison_operator")
368 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
369 || maybe_get_arm_condition_code (op) == ARM_GT
370 || maybe_get_arm_condition_code (op) == ARM_EQ
371 || maybe_get_arm_condition_code (op) == ARM_VS
372 || maybe_get_arm_condition_code (op) == ARM_LT
373 || maybe_get_arm_condition_code (op) == ARM_LE
374 || maybe_get_arm_condition_code (op) == ARM_NE
375 || maybe_get_arm_condition_code (op) == ARM_VC")))
377 (define_special_predicate "arm_cond_move_operator"
378 (if_then_else (match_test "arm_restrict_it")
379 (and (match_test "TARGET_VFP5")
380 (match_operand 0 "arm_vsel_comparison_operator"))
381 (match_operand 0 "expandable_comparison_operator")))
383 (define_special_predicate "noov_comparison_operator"
384 (match_code "lt,ge,eq,ne"))
386 (define_special_predicate "minmax_operator"
387 (and (match_code "smin,smax,umin,umax")
388 (match_test "mode == GET_MODE (op)")))
390 (define_special_predicate "cc_register"
391 (and (match_code "reg")
392 (and (match_test "REGNO (op) == CC_REGNUM")
393 (ior (match_test "mode == GET_MODE (op)")
394 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
396 (define_special_predicate "dominant_cc_register"
399 if (mode == VOIDmode)
401 mode = GET_MODE (op);
403 if (GET_MODE_CLASS (mode) != MODE_CC)
407 return (cc_register (op, mode)
408 && (mode == CC_DNEmode
409 || mode == CC_DEQmode
410 || mode == CC_DLEmode
411 || mode == CC_DLTmode
412 || mode == CC_DGEmode
413 || mode == CC_DGTmode
414 || mode == CC_DLEUmode
415 || mode == CC_DLTUmode
416 || mode == CC_DGEUmode
417 || mode == CC_DGTUmode));
420 ;; Any register, including CC
421 (define_predicate "cc_register_operand"
422 (and (match_code "reg")
423 (ior (match_operand 0 "s_register_operand")
424 (match_operand 0 "cc_register"))))
426 (define_special_predicate "arm_extendqisi_mem_op"
427 (and (match_operand 0 "memory_operand")
428 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
432 : memory_address_p (QImode, XEXP (op, 0))")))
434 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
435 (ior (match_operand 0 "arm_extendqisi_mem_op")
436 (match_operand 0 "s_register_operand")))
438 (define_predicate "power_of_two_operand"
439 (match_code "const_int")
441 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
443 return value != 0 && (value & (value - 1)) == 0;
446 (define_predicate "nonimmediate_di_operand"
447 (match_code "reg,subreg,mem")
449 if (s_register_operand (op, mode))
452 if (GET_CODE (op) == SUBREG)
453 op = SUBREG_REG (op);
455 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
458 (define_predicate "di_operand"
459 (ior (match_code "const_int,const_double")
460 (and (match_code "reg,subreg,mem")
461 (match_operand 0 "nonimmediate_di_operand"))))
463 (define_predicate "nonimmediate_soft_df_operand"
464 (match_code "reg,subreg,mem")
466 if (s_register_operand (op, mode))
469 if (GET_CODE (op) == SUBREG)
470 op = SUBREG_REG (op);
472 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
475 (define_predicate "soft_df_operand"
476 (ior (match_code "const_double")
477 (and (match_code "reg,subreg,mem")
478 (match_operand 0 "nonimmediate_soft_df_operand"))))
480 ;; Predicate for thumb2_movsf_vfp. Compared to general_operand, this
481 ;; forbids constant loaded via literal pool iff literal pools are disabled.
482 (define_predicate "hard_sf_operand"
483 (and (match_operand 0 "general_operand")
484 (ior (not (match_code "const_double"))
485 (not (match_test "arm_disable_literal_pool"))
486 (match_test "satisfies_constraint_Dv (op)"))))
488 ;; Predicate for thumb2_movdf_vfp. Compared to soft_df_operand used in
489 ;; movdf_soft_insn, this forbids constant loaded via literal pool iff
490 ;; literal pools are disabled.
491 (define_predicate "hard_df_operand"
492 (and (match_operand 0 "soft_df_operand")
493 (ior (not (match_code "const_double"))
494 (not (match_test "arm_disable_literal_pool"))
495 (match_test "satisfies_constraint_Dy (op)")
496 (match_test "satisfies_constraint_G (op)"))))
498 (define_special_predicate "load_multiple_operation"
499 (match_code "parallel")
501 return ldm_stm_operation_p (op, /*load=*/true, SImode,
502 /*consecutive=*/false,
503 /*return_pc=*/false);
506 (define_special_predicate "store_multiple_operation"
507 (match_code "parallel")
509 return ldm_stm_operation_p (op, /*load=*/false, SImode,
510 /*consecutive=*/false,
511 /*return_pc=*/false);
514 (define_special_predicate "pop_multiple_return"
515 (match_code "parallel")
517 return ldm_stm_operation_p (op, /*load=*/true, SImode,
518 /*consecutive=*/false,
522 (define_special_predicate "pop_multiple_fp"
523 (match_code "parallel")
525 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
526 /*consecutive=*/true,
527 /*return_pc=*/false);
530 (define_special_predicate "multi_register_push"
531 (match_code "parallel")
533 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
534 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
535 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
541 (define_predicate "push_mult_memory_operand"
544 /* ??? Given how PUSH_MULT is generated in the prologues, is there
545 any point in testing for thumb1 specially? All of the variants
546 use the same form. */
549 /* ??? No attempt is made to represent STMIA, or validate that
550 the stack adjustment matches the register count. This is
551 true of the ARM/Thumb2 path as well. */
552 rtx x = XEXP (op, 0);
553 if (GET_CODE (x) != PRE_MODIFY)
555 if (XEXP (x, 0) != stack_pointer_rtx)
558 if (GET_CODE (x) != PLUS)
560 if (XEXP (x, 0) != stack_pointer_rtx)
562 return CONST_INT_P (XEXP (x, 1));
565 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
566 return memory_operand (op, mode);
569 ;;-------------------------------------------------------------------------
574 (define_predicate "thumb1_cmp_operand"
575 (ior (and (match_code "reg,subreg")
576 (match_operand 0 "s_register_operand"))
577 (and (match_code "const_int")
578 (match_test "(UINTVAL (op)) < 256"))))
580 (define_predicate "thumb1_cmpneg_operand"
581 (and (match_code "const_int")
582 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
584 ;; Return TRUE if a result can be stored in OP without clobbering the
585 ;; condition code register. Prior to reload we only accept a
586 ;; register. After reload we have to be able to handle memory as
587 ;; well, since a pseudo may not get a hard reg and reload cannot
588 ;; handle output-reloads on jump insns.
590 ;; We could possibly handle mem before reload as well, but that might
591 ;; complicate things with the need to handle increment
593 (define_predicate "thumb_cbrch_target_operand"
594 (and (match_code "reg,subreg,mem")
595 (ior (match_operand 0 "s_register_operand")
596 (and (match_test "reload_in_progress || reload_completed")
597 (match_operand 0 "memory_operand")))))
599 ;;-------------------------------------------------------------------------
604 (define_predicate "imm_or_reg_operand"
605 (ior (match_operand 0 "immediate_operand")
606 (match_operand 0 "register_operand")))
610 (define_predicate "const_multiple_of_8_operand"
611 (match_code "const_int")
613 unsigned HOST_WIDE_INT val = INTVAL (op);
614 return (val & 7) == 0;
617 (define_predicate "imm_for_neon_mov_operand"
618 (match_code "const_vector,const_int")
620 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
623 (define_predicate "imm_for_neon_lshift_operand"
624 (match_code "const_vector")
626 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
629 (define_predicate "imm_for_neon_rshift_operand"
630 (match_code "const_vector")
632 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
635 (define_predicate "imm_lshift_or_reg_neon"
636 (ior (match_operand 0 "s_register_operand")
637 (match_operand 0 "imm_for_neon_lshift_operand")))
639 (define_predicate "imm_rshift_or_reg_neon"
640 (ior (match_operand 0 "s_register_operand")
641 (match_operand 0 "imm_for_neon_rshift_operand")))
643 ;; Predicates for named expanders that overlap multiple ISAs.
645 (define_predicate "cmpdi_operand"
646 (and (match_test "TARGET_32BIT")
647 (match_operand 0 "arm_di_operand")))
649 ;; True if the operand is memory reference suitable for a ldrex/strex.
650 (define_predicate "arm_sync_memory_operand"
651 (and (match_operand 0 "memory_operand")
652 (match_code "reg" "0")))
654 ;; Predicates for parallel expanders based on mode.
655 (define_special_predicate "vect_par_constant_high"
656 (match_code "parallel")
658 return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
661 (define_special_predicate "vect_par_constant_low"
662 (match_code "parallel")
664 return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
667 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
668 (and (match_code "const_double")
669 (match_test "TARGET_32BIT
670 && vfp3_const_double_for_fract_bits (op)")))
672 (define_predicate "const_double_vcvt_power_of_two"
673 (and (match_code "const_double")
674 (match_test "TARGET_32BIT
675 && vfp3_const_double_for_bits (op) > 0")))
677 (define_predicate "neon_struct_operand"
678 (and (match_code "mem")
679 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
681 (define_predicate "neon_permissive_struct_operand"
682 (and (match_code "mem")
683 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
685 (define_predicate "neon_perm_struct_or_reg_operand"
686 (ior (match_operand 0 "neon_permissive_struct_operand")
687 (match_operand 0 "s_register_operand")))
689 (define_special_predicate "add_operator"
692 (define_predicate "mem_noofs_operand"
693 (and (match_code "mem")
694 (match_code "reg" "0")))
696 (define_predicate "call_insn_operand"
697 (ior (and (match_code "symbol_ref")
698 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
699 (match_operand 0 "s_register_operand")))