| blob | 86158ea4fd278180d5e2321c66c6c2b5e5c460b0 |
1 ;; Patterns for the Intel Wireless MMX technology architecture.
2 ;; Copyright (C) 2003-2019 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it under
8 ;; the terms of the GNU General Public License as published by the Free
9 ;; Software Foundation; either version 3, or (at your option) any later
10 ;; version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h
22 (define_constants
23 [(WCGR0 96)
24 (WCGR1 97)
25 (WCGR2 98)
26 (WCGR3 99)
27 ]
28 )
30 (define_insn "tbcstv8qi"
31 [(set (match_operand:V8QI 0 "register_operand" "=y")
32 (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
33 "TARGET_REALLY_IWMMXT"
34 "tbcstb%?\\t%0, %1"
35 [(set_attr "predicable" "yes")
36 (set_attr "type" "wmmx_tbcst")]
37 )
39 (define_insn "tbcstv4hi"
40 [(set (match_operand:V4HI 0 "register_operand" "=y")
41 (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
42 "TARGET_REALLY_IWMMXT"
43 "tbcsth%?\\t%0, %1"
44 [(set_attr "predicable" "yes")
45 (set_attr "type" "wmmx_tbcst")]
46 )
48 (define_insn "tbcstv2si"
49 [(set (match_operand:V2SI 0 "register_operand" "=y")
50 (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
51 "TARGET_REALLY_IWMMXT"
52 "tbcstw%?\\t%0, %1"
53 [(set_attr "predicable" "yes")
54 (set_attr "type" "wmmx_tbcst")]
55 )
57 (define_insn "iwmmxt_iordi3"
58 [(set (match_operand:DI 0 "register_operand" "=y")
59 (ior:DI (match_operand:DI 1 "register_operand" "%y")
60 (match_operand:DI 2 "register_operand" "y")))]
61 "TARGET_REALLY_IWMMXT"
62 "wor%?\\t%0, %1, %2"
63 [(set_attr "predicable" "yes")
64 (set_attr "length" "4")
65 (set_attr "type" "wmmx_wor")]
66 )
68 (define_insn "iwmmxt_xordi3"
69 [(set (match_operand:DI 0 "register_operand" "=y")
70 (xor:DI (match_operand:DI 1 "register_operand" "%y")
71 (match_operand:DI 2 "register_operand" "y")))]
72 "TARGET_REALLY_IWMMXT"
73 "wxor%?\\t%0, %1, %2"
74 [(set_attr "predicable" "yes")
75 (set_attr "length" "4")
76 (set_attr "type" "wmmx_wxor")]
77 )
79 (define_insn "iwmmxt_anddi3"
80 [(set (match_operand:DI 0 "register_operand" "=y")
81 (and:DI (match_operand:DI 1 "register_operand" "%y")
82 (match_operand:DI 2 "register_operand" "y")))]
83 "TARGET_REALLY_IWMMXT"
84 "wand%?\\t%0, %1, %2"
85 [(set_attr "predicable" "yes")
86 (set_attr "length" "4")
87 (set_attr "type" "wmmx_wand")]
88 )
90 (define_insn "iwmmxt_nanddi3"
91 [(set (match_operand:DI 0 "register_operand" "=y")
92 (and:DI (match_operand:DI 1 "register_operand" "y")
93 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
94 "TARGET_REALLY_IWMMXT"
95 "wandn%?\\t%0, %1, %2"
96 [(set_attr "predicable" "yes")
97 (set_attr "type" "wmmx_wandn")]
98 )
100 (define_insn "*iwmmxt_arm_movdi"
101 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv")
102 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))]
103 "TARGET_REALLY_IWMMXT
104 && ( register_operand (operands[0], DImode)
105 || register_operand (operands[1], DImode))"
106 "*
107 switch (which_alternative)
108 {
109 case 0:
110 case 1:
111 case 2:
112 return \"#\";
113 case 3: case 4:
114 return output_move_double (operands, true, NULL);
115 case 5:
116 return \"wmov%?\\t%0,%1\";
117 case 6:
118 return \"tmcrr%?\\t%0,%Q1,%R1\";
119 case 7:
120 return \"tmrrc%?\\t%Q0,%R0,%1\";
121 case 8:
122 return \"wldrd%?\\t%0,%1\";
123 case 9:
124 return \"wstrd%?\\t%1,%0\";
125 case 10:
126 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
127 case 11:
128 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
129 case 12:
130 if (TARGET_VFP_SINGLE)
131 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
132 else
133 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
134 case 13: case 14:
135 return output_move_vfp (operands);
136 default:
137 gcc_unreachable ();
138 }
139 "
140 [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
141 (eq_attr "alternative" "1") (const_int 12)
142 (eq_attr "alternative" "2") (const_int 16)
143 (eq_attr "alternative" "12")
144 (if_then_else
145 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
146 (const_int 8)
147 (const_int 4))]
148 (const_int 4)))
149 (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\
150 ffarithd,f_loadd,f_stored")
151 (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
152 (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")]
153 )
155 (define_insn "*iwmmxt_movsi_insn"
156 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv")
157 (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))]
158 "TARGET_REALLY_IWMMXT
159 && ( register_operand (operands[0], SImode)
160 || register_operand (operands[1], SImode))"
161 "*
162 switch (which_alternative)
163 {
164 case 0: return \"mov\\t%0, %1\";
165 case 1: return \"mov\\t%0, %1\";
166 case 2: return \"mvn\\t%0, #%B1\";
167 case 3: return \"movw\\t%0, %1\";
168 case 4: return \"ldr\\t%0, %1\";
169 case 5: return \"str\\t%1, %0\";
170 case 6: return \"tmcr\\t%0, %1\";
171 case 7: return \"tmrc\\t%0, %1\";
172 case 8: return arm_output_load_gr (operands);
173 case 9: return \"wstrw\\t%1, %0\";
174 case 10:return \"fmsr\\t%0, %1\";
175 case 11:return \"fmrs\\t%0, %1\";
176 case 12:return \"fcpys\\t%0, %1\\t%@ int\";
177 case 13: case 14:
178 return output_move_vfp (operands);
179 default:
180 gcc_unreachable ();
181 }"
182 [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\
183 fmov,f_loads,f_stores")
184 (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
185 (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
186 (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
187 ;; Note - the "predicable" attribute is not allowed to have alternatives.
188 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
189 ;; predicating any of the alternatives in this template. Instead,
190 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
191 (set_attr "predicable" "no")
192 ;; Also - we have to pretend that these insns clobber the condition code
193 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
194 ;; them.
195 (set_attr "conds" "clob")]
196 )
198 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
199 ;; cond_exec version explicitly, with appropriate constraints.
201 (define_insn "*cond_iwmmxt_movsi_insn"
202 [(cond_exec
203 (match_operator 2 "arm_comparison_operator"
204 [(match_operand 3 "cc_register" "")
205 (const_int 0)])
206 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
207 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
208 "TARGET_REALLY_IWMMXT
209 && ( register_operand (operands[0], SImode)
210 || register_operand (operands[1], SImode))"
211 "*
212 switch (which_alternative)
213 {
214 case 0: return \"mov%?\\t%0, %1\";
215 case 1: return \"mvn%?\\t%0, #%B1\";
216 case 2: return \"ldr%?\\t%0, %1\";
217 case 3: return \"str%?\\t%1, %0\";
218 case 4: return \"tmcr%?\\t%0, %1\";
219 default: return \"tmrc%?\\t%0, %1\";
220 }"
221 [(set_attr "type" "*,*,load_4,store_4,*,*")
222 (set_attr "pool_range" "*,*,4096, *,*,*")
223 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
224 )
226 (define_insn "mov<mode>_internal"
227 [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
228 (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))]
229 "TARGET_REALLY_IWMMXT"
230 "*
231 switch (which_alternative)
232 {
233 case 0: return \"wmov%?\\t%0, %1\";
234 case 1: return \"wstrd%?\\t%1, %0\";
235 case 2: return \"wldrd%?\\t%0, %1\";
236 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
237 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
238 case 5: return \"#\";
239 default: return output_move_double (operands, true, NULL);
240 }"
241 [(set_attr "predicable" "yes")
242 (set_attr "length" "4, 4, 4,4,4,8, 8,8")
243 (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4")
244 (set_attr "pool_range" "*, *, 256,*,*,*, 256,*")
245 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")]
246 )
248 (define_expand "iwmmxt_setwcgr0"
249 [(set (reg:SI WCGR0)
250 (match_operand:SI 0 "register_operand"))]
251 "TARGET_REALLY_IWMMXT"
252 {}
253 )
255 (define_expand "iwmmxt_setwcgr1"
256 [(set (reg:SI WCGR1)
257 (match_operand:SI 0 "register_operand"))]
258 "TARGET_REALLY_IWMMXT"
259 {}
260 )
262 (define_expand "iwmmxt_setwcgr2"
263 [(set (reg:SI WCGR2)
264 (match_operand:SI 0 "register_operand"))]
265 "TARGET_REALLY_IWMMXT"
266 {}
267 )
269 (define_expand "iwmmxt_setwcgr3"
270 [(set (reg:SI WCGR3)
271 (match_operand:SI 0 "register_operand"))]
272 "TARGET_REALLY_IWMMXT"
273 {}
274 )
276 (define_expand "iwmmxt_getwcgr0"
277 [(set (match_operand:SI 0 "register_operand")
278 (reg:SI WCGR0))]
279 "TARGET_REALLY_IWMMXT"
280 {}
281 )
283 (define_expand "iwmmxt_getwcgr1"
284 [(set (match_operand:SI 0 "register_operand")
285 (reg:SI WCGR1))]
286 "TARGET_REALLY_IWMMXT"
287 {}
288 )
290 (define_expand "iwmmxt_getwcgr2"
291 [(set (match_operand:SI 0 "register_operand")
292 (reg:SI WCGR2))]
293 "TARGET_REALLY_IWMMXT"
294 {}
295 )
297 (define_expand "iwmmxt_getwcgr3"
298 [(set (match_operand:SI 0 "register_operand")
299 (reg:SI WCGR3))]
300 "TARGET_REALLY_IWMMXT"
301 {}
302 )
304 (define_insn "*and<mode>3_iwmmxt"
305 [(set (match_operand:VMMX 0 "register_operand" "=y")
306 (and:VMMX (match_operand:VMMX 1 "register_operand" "y")
307 (match_operand:VMMX 2 "register_operand" "y")))]
308 "TARGET_REALLY_IWMMXT"
309 "wand\\t%0, %1, %2"
310 [(set_attr "predicable" "yes")
311 (set_attr "type" "wmmx_wand")]
312 )
314 (define_insn "*ior<mode>3_iwmmxt"
315 [(set (match_operand:VMMX 0 "register_operand" "=y")
316 (ior:VMMX (match_operand:VMMX 1 "register_operand" "y")
317 (match_operand:VMMX 2 "register_operand" "y")))]
318 "TARGET_REALLY_IWMMXT"
319 "wor\\t%0, %1, %2"
320 [(set_attr "predicable" "yes")
321 (set_attr "type" "wmmx_wor")]
322 )
324 (define_insn "*xor<mode>3_iwmmxt"
325 [(set (match_operand:VMMX 0 "register_operand" "=y")
326 (xor:VMMX (match_operand:VMMX 1 "register_operand" "y")
327 (match_operand:VMMX 2 "register_operand" "y")))]
328 "TARGET_REALLY_IWMMXT"
329 "wxor\\t%0, %1, %2"
330 [(set_attr "predicable" "yes")
331 (set_attr "type" "wmmx_wxor")]
332 )
335 ;; Vector add/subtract
337 (define_insn "*add<mode>3_iwmmxt"
338 [(set (match_operand:VMMX 0 "register_operand" "=y")
339 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
340 (match_operand:VMMX 2 "register_operand" "y")))]
341 "TARGET_REALLY_IWMMXT"
342 "wadd<MMX_char>%?\\t%0, %1, %2"
343 [(set_attr "predicable" "yes")
344 (set_attr "type" "wmmx_wadd")]
345 )
347 (define_insn "ssaddv8qi3"
348 [(set (match_operand:V8QI 0 "register_operand" "=y")
349 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
350 (match_operand:V8QI 2 "register_operand" "y")))]
351 "TARGET_REALLY_IWMMXT"
352 "waddbss%?\\t%0, %1, %2"
353 [(set_attr "predicable" "yes")
354 (set_attr "type" "wmmx_wadd")]
355 )
357 (define_insn "ssaddv4hi3"
358 [(set (match_operand:V4HI 0 "register_operand" "=y")
359 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
360 (match_operand:V4HI 2 "register_operand" "y")))]
361 "TARGET_REALLY_IWMMXT"
362 "waddhss%?\\t%0, %1, %2"
363 [(set_attr "predicable" "yes")
364 (set_attr "type" "wmmx_wadd")]
365 )
367 (define_insn "ssaddv2si3"
368 [(set (match_operand:V2SI 0 "register_operand" "=y")
369 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
370 (match_operand:V2SI 2 "register_operand" "y")))]
371 "TARGET_REALLY_IWMMXT"
372 "waddwss%?\\t%0, %1, %2"
373 [(set_attr "predicable" "yes")
374 (set_attr "type" "wmmx_wadd")]
375 )
377 (define_insn "usaddv8qi3"
378 [(set (match_operand:V8QI 0 "register_operand" "=y")
379 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
380 (match_operand:V8QI 2 "register_operand" "y")))]
381 "TARGET_REALLY_IWMMXT"
382 "waddbus%?\\t%0, %1, %2"
383 [(set_attr "predicable" "yes")
384 (set_attr "type" "wmmx_wadd")]
385 )
387 (define_insn "usaddv4hi3"
388 [(set (match_operand:V4HI 0 "register_operand" "=y")
389 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
390 (match_operand:V4HI 2 "register_operand" "y")))]
391 "TARGET_REALLY_IWMMXT"
392 "waddhus%?\\t%0, %1, %2"
393 [(set_attr "predicable" "yes")
394 (set_attr "type" "wmmx_wadd")]
395 )
397 (define_insn "usaddv2si3"
398 [(set (match_operand:V2SI 0 "register_operand" "=y")
399 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
400 (match_operand:V2SI 2 "register_operand" "y")))]
401 "TARGET_REALLY_IWMMXT"
402 "waddwus%?\\t%0, %1, %2"
403 [(set_attr "predicable" "yes")
404 (set_attr "type" "wmmx_wadd")]
405 )
407 (define_insn "*sub<mode>3_iwmmxt"
408 [(set (match_operand:VMMX 0 "register_operand" "=y")
409 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y")
410 (match_operand:VMMX 2 "register_operand" "y")))]
411 "TARGET_REALLY_IWMMXT"
412 "wsub<MMX_char>%?\\t%0, %1, %2"
413 [(set_attr "predicable" "yes")
414 (set_attr "type" "wmmx_wsub")]
415 )
417 (define_insn "sssubv8qi3"
418 [(set (match_operand:V8QI 0 "register_operand" "=y")
419 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
420 (match_operand:V8QI 2 "register_operand" "y")))]
421 "TARGET_REALLY_IWMMXT"
422 "wsubbss%?\\t%0, %1, %2"
423 [(set_attr "predicable" "yes")
424 (set_attr "type" "wmmx_wsub")]
425 )
427 (define_insn "sssubv4hi3"
428 [(set (match_operand:V4HI 0 "register_operand" "=y")
429 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
430 (match_operand:V4HI 2 "register_operand" "y")))]
431 "TARGET_REALLY_IWMMXT"
432 "wsubhss%?\\t%0, %1, %2"
433 [(set_attr "predicable" "yes")
434 (set_attr "type" "wmmx_wsub")]
435 )
437 (define_insn "sssubv2si3"
438 [(set (match_operand:V2SI 0 "register_operand" "=y")
439 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
440 (match_operand:V2SI 2 "register_operand" "y")))]
441 "TARGET_REALLY_IWMMXT"
442 "wsubwss%?\\t%0, %1, %2"
443 [(set_attr "predicable" "yes")
444 (set_attr "type" "wmmx_wsub")]
445 )
447 (define_insn "ussubv8qi3"
448 [(set (match_operand:V8QI 0 "register_operand" "=y")
449 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
450 (match_operand:V8QI 2 "register_operand" "y")))]
451 "TARGET_REALLY_IWMMXT"
452 "wsubbus%?\\t%0, %1, %2"
453 [(set_attr "predicable" "yes")
454 (set_attr "type" "wmmx_wsub")]
455 )
457 (define_insn "ussubv4hi3"
458 [(set (match_operand:V4HI 0 "register_operand" "=y")
459 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
460 (match_operand:V4HI 2 "register_operand" "y")))]
461 "TARGET_REALLY_IWMMXT"
462 "wsubhus%?\\t%0, %1, %2"
463 [(set_attr "predicable" "yes")
464 (set_attr "type" "wmmx_wsub")]
465 )
467 (define_insn "ussubv2si3"
468 [(set (match_operand:V2SI 0 "register_operand" "=y")
469 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
470 (match_operand:V2SI 2 "register_operand" "y")))]
471 "TARGET_REALLY_IWMMXT"
472 "wsubwus%?\\t%0, %1, %2"
473 [(set_attr "predicable" "yes")
474 (set_attr "type" "wmmx_wsub")]
475 )
477 (define_insn "*mulv4hi3_iwmmxt"
478 [(set (match_operand:V4HI 0 "register_operand" "=y")
479 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
480 (match_operand:V4HI 2 "register_operand" "y")))]
481 "TARGET_REALLY_IWMMXT"
482 "wmulul%?\\t%0, %1, %2"
483 [(set_attr "predicable" "yes")
484 (set_attr "type" "wmmx_wmul")]
485 )
487 (define_insn "smulv4hi3_highpart"
488 [(set (match_operand:V4HI 0 "register_operand" "=y")
489 (truncate:V4HI
490 (lshiftrt:V4SI
491 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
492 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
493 (const_int 16))))]
494 "TARGET_REALLY_IWMMXT"
495 "wmulsm%?\\t%0, %1, %2"
496 [(set_attr "predicable" "yes")
497 (set_attr "type" "wmmx_wmul")]
498 )
500 (define_insn "umulv4hi3_highpart"
501 [(set (match_operand:V4HI 0 "register_operand" "=y")
502 (truncate:V4HI
503 (lshiftrt:V4SI
504 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
505 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
506 (const_int 16))))]
507 "TARGET_REALLY_IWMMXT"
508 "wmulum%?\\t%0, %1, %2"
509 [(set_attr "predicable" "yes")
510 (set_attr "type" "wmmx_wmul")]
511 )
513 (define_insn "iwmmxt_wmacs"
514 [(set (match_operand:DI 0 "register_operand" "=y")
515 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
516 (match_operand:V4HI 2 "register_operand" "y")
517 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
518 "TARGET_REALLY_IWMMXT"
519 "wmacs%?\\t%0, %2, %3"
520 [(set_attr "predicable" "yes")
521 (set_attr "type" "wmmx_wmac")]
522 )
524 (define_insn "iwmmxt_wmacsz"
525 [(set (match_operand:DI 0 "register_operand" "=y")
526 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
527 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
528 "TARGET_REALLY_IWMMXT"
529 "wmacsz%?\\t%0, %1, %2"
530 [(set_attr "predicable" "yes")
531 (set_attr "type" "wmmx_wmac")]
532 )
534 (define_insn "iwmmxt_wmacu"
535 [(set (match_operand:DI 0 "register_operand" "=y")
536 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
537 (match_operand:V4HI 2 "register_operand" "y")
538 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
539 "TARGET_REALLY_IWMMXT"
540 "wmacu%?\\t%0, %2, %3"
541 [(set_attr "predicable" "yes")
542 (set_attr "type" "wmmx_wmac")]
543 )
545 (define_insn "iwmmxt_wmacuz"
546 [(set (match_operand:DI 0 "register_operand" "=y")
547 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
548 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
549 "TARGET_REALLY_IWMMXT"
550 "wmacuz%?\\t%0, %1, %2"
551 [(set_attr "predicable" "yes")
552 (set_attr "type" "wmmx_wmac")]
553 )
555 ;; Same as xordi3, but don't show input operands so that we don't think
556 ;; they are live.
557 (define_insn "iwmmxt_clrdi"
558 [(set (match_operand:DI 0 "register_operand" "=y")
559 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
560 "TARGET_REALLY_IWMMXT"
561 "wxor%?\\t%0, %0, %0"
562 [(set_attr "predicable" "yes")
563 (set_attr "type" "wmmx_wxor")]
564 )
566 ;; Seems like cse likes to generate these, so we have to support them.
568 (define_insn "iwmmxt_clrv8qi"
569 [(set (match_operand:V8QI 0 "s_register_operand" "=y")
570 (const_vector:V8QI [(const_int 0) (const_int 0)
571 (const_int 0) (const_int 0)
572 (const_int 0) (const_int 0)
573 (const_int 0) (const_int 0)]))]
574 "TARGET_REALLY_IWMMXT"
575 "wxor%?\\t%0, %0, %0"
576 [(set_attr "predicable" "yes")
577 (set_attr "type" "wmmx_wxor")]
578 )
580 (define_insn "iwmmxt_clrv4hi"
581 [(set (match_operand:V4HI 0 "s_register_operand" "=y")
582 (const_vector:V4HI [(const_int 0) (const_int 0)
583 (const_int 0) (const_int 0)]))]
584 "TARGET_REALLY_IWMMXT"
585 "wxor%?\\t%0, %0, %0"
586 [(set_attr "predicable" "yes")
587 (set_attr "type" "wmmx_wxor")]
588 )
590 (define_insn "iwmmxt_clrv2si"
591 [(set (match_operand:V2SI 0 "register_operand" "=y")
592 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
593 "TARGET_REALLY_IWMMXT"
594 "wxor%?\\t%0, %0, %0"
595 [(set_attr "predicable" "yes")
596 (set_attr "type" "wmmx_wxor")]
597 )
599 ;; Unsigned averages/sum of absolute differences
601 (define_insn "iwmmxt_uavgrndv8qi3"
602 [(set (match_operand:V8QI 0 "register_operand" "=y")
603 (truncate:V8QI
604 (lshiftrt:V8HI
605 (plus:V8HI
606 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
607 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
608 (const_vector:V8HI [(const_int 1)
609 (const_int 1)
610 (const_int 1)
611 (const_int 1)
612 (const_int 1)
613 (const_int 1)
614 (const_int 1)
615 (const_int 1)]))
616 (const_int 1))))]
617 "TARGET_REALLY_IWMMXT"
618 "wavg2br%?\\t%0, %1, %2"
619 [(set_attr "predicable" "yes")
620 (set_attr "type" "wmmx_wavg2")]
621 )
623 (define_insn "iwmmxt_uavgrndv4hi3"
624 [(set (match_operand:V4HI 0 "register_operand" "=y")
625 (truncate:V4HI
626 (lshiftrt:V4SI
627 (plus:V4SI
628 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
629 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
630 (const_vector:V4SI [(const_int 1)
631 (const_int 1)
632 (const_int 1)
633 (const_int 1)]))
634 (const_int 1))))]
635 "TARGET_REALLY_IWMMXT"
636 "wavg2hr%?\\t%0, %1, %2"
637 [(set_attr "predicable" "yes")
638 (set_attr "type" "wmmx_wavg2")]
639 )
641 (define_insn "iwmmxt_uavgv8qi3"
642 [(set (match_operand:V8QI 0 "register_operand" "=y")
643 (truncate:V8QI
644 (lshiftrt:V8HI
645 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
646 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
647 (const_int 1))))]
648 "TARGET_REALLY_IWMMXT"
649 "wavg2b%?\\t%0, %1, %2"
650 [(set_attr "predicable" "yes")
651 (set_attr "type" "wmmx_wavg2")]
652 )
654 (define_insn "iwmmxt_uavgv4hi3"
655 [(set (match_operand:V4HI 0 "register_operand" "=y")
656 (truncate:V4HI
657 (lshiftrt:V4SI
658 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
659 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
660 (const_int 1))))]
661 "TARGET_REALLY_IWMMXT"
662 "wavg2h%?\\t%0, %1, %2"
663 [(set_attr "predicable" "yes")
664 (set_attr "type" "wmmx_wavg2")]
665 )
667 ;; Insert/extract/shuffle
669 (define_insn "iwmmxt_tinsrb"
670 [(set (match_operand:V8QI 0 "register_operand" "=y")
671 (vec_merge:V8QI
672 (vec_duplicate:V8QI
673 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
674 (match_operand:V8QI 1 "register_operand" "0")
675 (match_operand:SI 3 "immediate_operand" "i")))]
676 "TARGET_REALLY_IWMMXT"
677 "*
678 {
679 return arm_output_iwmmxt_tinsr (operands);
680 }
681 "
682 [(set_attr "predicable" "yes")
683 (set_attr "type" "wmmx_tinsr")]
684 )
686 (define_insn "iwmmxt_tinsrh"
687 [(set (match_operand:V4HI 0 "register_operand" "=y")
688 (vec_merge:V4HI
689 (vec_duplicate:V4HI
690 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
691 (match_operand:V4HI 1 "register_operand" "0")
692 (match_operand:SI 3 "immediate_operand" "i")))]
693 "TARGET_REALLY_IWMMXT"
694 "*
695 {
696 return arm_output_iwmmxt_tinsr (operands);
697 }
698 "
699 [(set_attr "predicable" "yes")
700 (set_attr "type" "wmmx_tinsr")]
701 )
703 (define_insn "iwmmxt_tinsrw"
704 [(set (match_operand:V2SI 0 "register_operand" "=y")
705 (vec_merge:V2SI
706 (vec_duplicate:V2SI
707 (match_operand:SI 2 "nonimmediate_operand" "r"))
708 (match_operand:V2SI 1 "register_operand" "0")
709 (match_operand:SI 3 "immediate_operand" "i")))]
710 "TARGET_REALLY_IWMMXT"
711 "*
712 {
713 return arm_output_iwmmxt_tinsr (operands);
714 }
715 "
716 [(set_attr "predicable" "yes")
717 (set_attr "type" "wmmx_tinsr")]
718 )
720 (define_insn "iwmmxt_textrmub"
721 [(set (match_operand:SI 0 "register_operand" "=r")
722 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
723 (parallel
724 [(match_operand:SI 2 "immediate_operand" "i")]))))]
725 "TARGET_REALLY_IWMMXT"
726 "textrmub%?\\t%0, %1, %2"
727 [(set_attr "predicable" "yes")
728 (set_attr "type" "wmmx_textrm")]
729 )
731 (define_insn "iwmmxt_textrmsb"
732 [(set (match_operand:SI 0 "register_operand" "=r")
733 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
734 (parallel
735 [(match_operand:SI 2 "immediate_operand" "i")]))))]
736 "TARGET_REALLY_IWMMXT"
737 "textrmsb%?\\t%0, %1, %2"
738 [(set_attr "predicable" "yes")
739 (set_attr "type" "wmmx_textrm")]
740 )
742 (define_insn "iwmmxt_textrmuh"
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
745 (parallel
746 [(match_operand:SI 2 "immediate_operand" "i")]))))]
747 "TARGET_REALLY_IWMMXT"
748 "textrmuh%?\\t%0, %1, %2"
749 [(set_attr "predicable" "yes")
750 (set_attr "type" "wmmx_textrm")]
751 )
753 (define_insn "iwmmxt_textrmsh"
754 [(set (match_operand:SI 0 "register_operand" "=r")
755 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
756 (parallel
757 [(match_operand:SI 2 "immediate_operand" "i")]))))]
758 "TARGET_REALLY_IWMMXT"
759 "textrmsh%?\\t%0, %1, %2"
760 [(set_attr "predicable" "yes")
761 (set_attr "type" "wmmx_textrm")]
762 )
764 ;; There are signed/unsigned variants of this instruction, but they are
765 ;; pointless.
766 (define_insn "iwmmxt_textrmw"
767 [(set (match_operand:SI 0 "register_operand" "=r")
768 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
769 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
770 "TARGET_REALLY_IWMMXT"
771 "textrmsw%?\\t%0, %1, %2"
772 [(set_attr "predicable" "yes")
773 (set_attr "type" "wmmx_textrm")]
774 )
776 (define_insn "iwmmxt_wshufh"
777 [(set (match_operand:V4HI 0 "register_operand" "=y")
778 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
779 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
780 "TARGET_REALLY_IWMMXT"
781 "wshufh%?\\t%0, %1, %2"
782 [(set_attr "predicable" "yes")
783 (set_attr "type" "wmmx_wshufh")]
784 )
786 ;; Mask-generating comparisons
787 ;;
788 ;; Note - you cannot use patterns like these here:
789 ;;
790 ;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
791 ;;
792 ;; Because GCC will assume that the truth value (1 or 0) is installed
793 ;; into the entire destination vector, (with the '1' going into the least
794 ;; significant element of the vector). This is not how these instructions
795 ;; behave.
797 (define_insn "eqv8qi3"
798 [(set (match_operand:V8QI 0 "register_operand" "=y")
799 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
800 (match_operand:V8QI 2 "register_operand" "y")]
801 VUNSPEC_WCMP_EQ))]
802 "TARGET_REALLY_IWMMXT"
803 "wcmpeqb%?\\t%0, %1, %2"
804 [(set_attr "predicable" "yes")
805 (set_attr "type" "wmmx_wcmpeq")]
806 )
808 (define_insn "eqv4hi3"
809 [(set (match_operand:V4HI 0 "register_operand" "=y")
810 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
811 (match_operand:V4HI 2 "register_operand" "y")]
812 VUNSPEC_WCMP_EQ))]
813 "TARGET_REALLY_IWMMXT"
814 "wcmpeqh%?\\t%0, %1, %2"
815 [(set_attr "predicable" "yes")
816 (set_attr "type" "wmmx_wcmpeq")]
817 )
819 (define_insn "eqv2si3"
820 [(set (match_operand:V2SI 0 "register_operand" "=y")
821 (unspec_volatile:V2SI
822 [(match_operand:V2SI 1 "register_operand" "y")
823 (match_operand:V2SI 2 "register_operand" "y")]
824 VUNSPEC_WCMP_EQ))]
825 "TARGET_REALLY_IWMMXT"
826 "wcmpeqw%?\\t%0, %1, %2"
827 [(set_attr "predicable" "yes")
828 (set_attr "type" "wmmx_wcmpeq")]
829 )
831 (define_insn "gtuv8qi3"
832 [(set (match_operand:V8QI 0 "register_operand" "=y")
833 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
834 (match_operand:V8QI 2 "register_operand" "y")]
835 VUNSPEC_WCMP_GTU))]
836 "TARGET_REALLY_IWMMXT"
837 "wcmpgtub%?\\t%0, %1, %2"
838 [(set_attr "predicable" "yes")
839 (set_attr "type" "wmmx_wcmpgt")]
840 )
842 (define_insn "gtuv4hi3"
843 [(set (match_operand:V4HI 0 "register_operand" "=y")
844 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
845 (match_operand:V4HI 2 "register_operand" "y")]
846 VUNSPEC_WCMP_GTU))]
847 "TARGET_REALLY_IWMMXT"
848 "wcmpgtuh%?\\t%0, %1, %2"
849 [(set_attr "predicable" "yes")
850 (set_attr "type" "wmmx_wcmpgt")]
851 )
853 (define_insn "gtuv2si3"
854 [(set (match_operand:V2SI 0 "register_operand" "=y")
855 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
856 (match_operand:V2SI 2 "register_operand" "y")]
857 VUNSPEC_WCMP_GTU))]
858 "TARGET_REALLY_IWMMXT"
859 "wcmpgtuw%?\\t%0, %1, %2"
860 [(set_attr "predicable" "yes")
861 (set_attr "type" "wmmx_wcmpgt")]
862 )
864 (define_insn "gtv8qi3"
865 [(set (match_operand:V8QI 0 "register_operand" "=y")
866 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
867 (match_operand:V8QI 2 "register_operand" "y")]
868 VUNSPEC_WCMP_GT))]
869 "TARGET_REALLY_IWMMXT"
870 "wcmpgtsb%?\\t%0, %1, %2"
871 [(set_attr "predicable" "yes")
872 (set_attr "type" "wmmx_wcmpgt")]
873 )
875 (define_insn "gtv4hi3"
876 [(set (match_operand:V4HI 0 "register_operand" "=y")
877 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
878 (match_operand:V4HI 2 "register_operand" "y")]
879 VUNSPEC_WCMP_GT))]
880 "TARGET_REALLY_IWMMXT"
881 "wcmpgtsh%?\\t%0, %1, %2"
882 [(set_attr "predicable" "yes")
883 (set_attr "type" "wmmx_wcmpgt")]
884 )
886 (define_insn "gtv2si3"
887 [(set (match_operand:V2SI 0 "register_operand" "=y")
888 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
889 (match_operand:V2SI 2 "register_operand" "y")]
890 VUNSPEC_WCMP_GT))]
891 "TARGET_REALLY_IWMMXT"
892 "wcmpgtsw%?\\t%0, %1, %2"
893 [(set_attr "predicable" "yes")
894 (set_attr "type" "wmmx_wcmpgt")]
895 )
897 ;; Max/min insns
899 (define_insn "*smax<mode>3_iwmmxt"
900 [(set (match_operand:VMMX 0 "register_operand" "=y")
901 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
902 (match_operand:VMMX 2 "register_operand" "y")))]
903 "TARGET_REALLY_IWMMXT"
904 "wmaxs<MMX_char>%?\\t%0, %1, %2"
905 [(set_attr "predicable" "yes")
906 (set_attr "type" "wmmx_wmax")]
907 )
909 (define_insn "*umax<mode>3_iwmmxt"
910 [(set (match_operand:VMMX 0 "register_operand" "=y")
911 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
912 (match_operand:VMMX 2 "register_operand" "y")))]
913 "TARGET_REALLY_IWMMXT"
914 "wmaxu<MMX_char>%?\\t%0, %1, %2"
915 [(set_attr "predicable" "yes")
916 (set_attr "type" "wmmx_wmax")]
917 )
919 (define_insn "*smin<mode>3_iwmmxt"
920 [(set (match_operand:VMMX 0 "register_operand" "=y")
921 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
922 (match_operand:VMMX 2 "register_operand" "y")))]
923 "TARGET_REALLY_IWMMXT"
924 "wmins<MMX_char>%?\\t%0, %1, %2"
925 [(set_attr "predicable" "yes")
926 (set_attr "type" "wmmx_wmin")]
927 )
929 (define_insn "*umin<mode>3_iwmmxt"
930 [(set (match_operand:VMMX 0 "register_operand" "=y")
931 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
932 (match_operand:VMMX 2 "register_operand" "y")))]
933 "TARGET_REALLY_IWMMXT"
934 "wminu<MMX_char>%?\\t%0, %1, %2"
935 [(set_attr "predicable" "yes")
936 (set_attr "type" "wmmx_wmin")]
937 )
939 ;; Pack/unpack insns.
941 (define_insn "iwmmxt_wpackhss"
942 [(set (match_operand:V8QI 0 "register_operand" "=y")
943 (vec_concat:V8QI
944 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
945 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
946 "TARGET_REALLY_IWMMXT"
947 "wpackhss%?\\t%0, %1, %2"
948 [(set_attr "predicable" "yes")
949 (set_attr "type" "wmmx_wpack")]
950 )
952 (define_insn "iwmmxt_wpackwss"
953 [(set (match_operand:V4HI 0 "register_operand" "=y")
954 (vec_concat:V4HI
955 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
956 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
957 "TARGET_REALLY_IWMMXT"
958 "wpackwss%?\\t%0, %1, %2"
959 [(set_attr "predicable" "yes")
960 (set_attr "type" "wmmx_wpack")]
961 )
963 (define_insn "iwmmxt_wpackdss"
964 [(set (match_operand:V2SI 0 "register_operand" "=y")
965 (vec_concat:V2SI
966 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
967 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
968 "TARGET_REALLY_IWMMXT"
969 "wpackdss%?\\t%0, %1, %2"
970 [(set_attr "predicable" "yes")
971 (set_attr "type" "wmmx_wpack")]
972 )
974 (define_insn "iwmmxt_wpackhus"
975 [(set (match_operand:V8QI 0 "register_operand" "=y")
976 (vec_concat:V8QI
977 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
978 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
979 "TARGET_REALLY_IWMMXT"
980 "wpackhus%?\\t%0, %1, %2"
981 [(set_attr "predicable" "yes")
982 (set_attr "type" "wmmx_wpack")]
983 )
985 (define_insn "iwmmxt_wpackwus"
986 [(set (match_operand:V4HI 0 "register_operand" "=y")
987 (vec_concat:V4HI
988 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
989 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
990 "TARGET_REALLY_IWMMXT"
991 "wpackwus%?\\t%0, %1, %2"
992 [(set_attr "predicable" "yes")
993 (set_attr "type" "wmmx_wpack")]
994 )
996 (define_insn "iwmmxt_wpackdus"
997 [(set (match_operand:V2SI 0 "register_operand" "=y")
998 (vec_concat:V2SI
999 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
1000 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
1001 "TARGET_REALLY_IWMMXT"
1002 "wpackdus%?\\t%0, %1, %2"
1003 [(set_attr "predicable" "yes")
1004 (set_attr "type" "wmmx_wpack")]
1005 )
1007 (define_insn "iwmmxt_wunpckihb"
1008 [(set (match_operand:V8QI 0 "register_operand" "=y")
1009 (vec_merge:V8QI
1010 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1011 (parallel [(const_int 4)
1012 (const_int 0)
1013 (const_int 5)
1014 (const_int 1)
1015 (const_int 6)
1016 (const_int 2)
1017 (const_int 7)
1018 (const_int 3)]))
1019 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1020 (parallel [(const_int 0)
1021 (const_int 4)
1022 (const_int 1)
1023 (const_int 5)
1024 (const_int 2)
1025 (const_int 6)
1026 (const_int 3)
1027 (const_int 7)]))
1028 (const_int 85)))]
1029 "TARGET_REALLY_IWMMXT"
1030 "wunpckihb%?\\t%0, %1, %2"
1031 [(set_attr "predicable" "yes")
1032 (set_attr "type" "wmmx_wunpckih")]
1033 )
1035 (define_insn "iwmmxt_wunpckihh"
1036 [(set (match_operand:V4HI 0 "register_operand" "=y")
1037 (vec_merge:V4HI
1038 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1039 (parallel [(const_int 2)
1040 (const_int 0)
1041 (const_int 3)
1042 (const_int 1)]))
1043 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1044 (parallel [(const_int 0)
1045 (const_int 2)
1046 (const_int 1)
1047 (const_int 3)]))
1048 (const_int 5)))]
1049 "TARGET_REALLY_IWMMXT"
1050 "wunpckihh%?\\t%0, %1, %2"
1051 [(set_attr "predicable" "yes")
1052 (set_attr "type" "wmmx_wunpckih")]
1053 )
1055 (define_insn "iwmmxt_wunpckihw"
1056 [(set (match_operand:V2SI 0 "register_operand" "=y")
1057 (vec_merge:V2SI
1058 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1059 (parallel [(const_int 1)
1060 (const_int 0)]))
1061 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1062 (parallel [(const_int 0)
1063 (const_int 1)]))
1064 (const_int 1)))]
1065 "TARGET_REALLY_IWMMXT"
1066 "wunpckihw%?\\t%0, %1, %2"
1067 [(set_attr "predicable" "yes")
1068 (set_attr "type" "wmmx_wunpckih")]
1069 )
1071 (define_insn "iwmmxt_wunpckilb"
1072 [(set (match_operand:V8QI 0 "register_operand" "=y")
1073 (vec_merge:V8QI
1074 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1075 (parallel [(const_int 0)
1076 (const_int 4)
1077 (const_int 1)
1078 (const_int 5)
1079 (const_int 2)
1080 (const_int 6)
1081 (const_int 3)
1082 (const_int 7)]))
1083 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1084 (parallel [(const_int 4)
1085 (const_int 0)
1086 (const_int 5)
1087 (const_int 1)
1088 (const_int 6)
1089 (const_int 2)
1090 (const_int 7)
1091 (const_int 3)]))
1092 (const_int 85)))]
1093 "TARGET_REALLY_IWMMXT"
1094 "wunpckilb%?\\t%0, %1, %2"
1095 [(set_attr "predicable" "yes")
1096 (set_attr "type" "wmmx_wunpckil")]
1097 )
1099 (define_insn "iwmmxt_wunpckilh"
1100 [(set (match_operand:V4HI 0 "register_operand" "=y")
1101 (vec_merge:V4HI
1102 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1103 (parallel [(const_int 0)
1104 (const_int 2)
1105 (const_int 1)
1106 (const_int 3)]))
1107 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1108 (parallel [(const_int 2)
1109 (const_int 0)
1110 (const_int 3)
1111 (const_int 1)]))
1112 (const_int 5)))]
1113 "TARGET_REALLY_IWMMXT"
1114 "wunpckilh%?\\t%0, %1, %2"
1115 [(set_attr "predicable" "yes")
1116 (set_attr "type" "wmmx_wunpckil")]
1117 )
1119 (define_insn "iwmmxt_wunpckilw"
1120 [(set (match_operand:V2SI 0 "register_operand" "=y")
1121 (vec_merge:V2SI
1122 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1123 (parallel [(const_int 0)
1124 (const_int 1)]))
1125 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1126 (parallel [(const_int 1)
1127 (const_int 0)]))
1128 (const_int 1)))]
1129 "TARGET_REALLY_IWMMXT"
1130 "wunpckilw%?\\t%0, %1, %2"
1131 [(set_attr "predicable" "yes")
1132 (set_attr "type" "wmmx_wunpckil")]
1133 )
1135 (define_insn "iwmmxt_wunpckehub"
1136 [(set (match_operand:V4HI 0 "register_operand" "=y")
1137 (vec_select:V4HI
1138 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1139 (parallel [(const_int 4) (const_int 5)
1140 (const_int 6) (const_int 7)])))]
1141 "TARGET_REALLY_IWMMXT"
1142 "wunpckehub%?\\t%0, %1"
1143 [(set_attr "predicable" "yes")
1144 (set_attr "type" "wmmx_wunpckeh")]
1145 )
1147 (define_insn "iwmmxt_wunpckehuh"
1148 [(set (match_operand:V2SI 0 "register_operand" "=y")
1149 (vec_select:V2SI
1150 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1151 (parallel [(const_int 2) (const_int 3)])))]
1152 "TARGET_REALLY_IWMMXT"
1153 "wunpckehuh%?\\t%0, %1"
1154 [(set_attr "predicable" "yes")
1155 (set_attr "type" "wmmx_wunpckeh")]
1156 )
1158 (define_insn "iwmmxt_wunpckehuw"
1159 [(set (match_operand:DI 0 "register_operand" "=y")
1160 (vec_select:DI
1161 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1162 (parallel [(const_int 1)])))]
1163 "TARGET_REALLY_IWMMXT"
1164 "wunpckehuw%?\\t%0, %1"
1165 [(set_attr "predicable" "yes")
1166 (set_attr "type" "wmmx_wunpckeh")]
1167 )
1169 (define_insn "iwmmxt_wunpckehsb"
1170 [(set (match_operand:V4HI 0 "register_operand" "=y")
1171 (vec_select:V4HI
1172 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1173 (parallel [(const_int 4) (const_int 5)
1174 (const_int 6) (const_int 7)])))]
1175 "TARGET_REALLY_IWMMXT"
1176 "wunpckehsb%?\\t%0, %1"
1177 [(set_attr "predicable" "yes")
1178 (set_attr "type" "wmmx_wunpckeh")]
1179 )
1181 (define_insn "iwmmxt_wunpckehsh"
1182 [(set (match_operand:V2SI 0 "register_operand" "=y")
1183 (vec_select:V2SI
1184 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1185 (parallel [(const_int 2) (const_int 3)])))]
1186 "TARGET_REALLY_IWMMXT"
1187 "wunpckehsh%?\\t%0, %1"
1188 [(set_attr "predicable" "yes")
1189 (set_attr "type" "wmmx_wunpckeh")]
1190 )
1192 (define_insn "iwmmxt_wunpckehsw"
1193 [(set (match_operand:DI 0 "register_operand" "=y")
1194 (vec_select:DI
1195 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1196 (parallel [(const_int 1)])))]
1197 "TARGET_REALLY_IWMMXT"
1198 "wunpckehsw%?\\t%0, %1"
1199 [(set_attr "predicable" "yes")
1200 (set_attr "type" "wmmx_wunpckeh")]
1201 )
1203 (define_insn "iwmmxt_wunpckelub"
1204 [(set (match_operand:V4HI 0 "register_operand" "=y")
1205 (vec_select:V4HI
1206 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1207 (parallel [(const_int 0) (const_int 1)
1208 (const_int 2) (const_int 3)])))]
1209 "TARGET_REALLY_IWMMXT"
1210 "wunpckelub%?\\t%0, %1"
1211 [(set_attr "predicable" "yes")
1212 (set_attr "type" "wmmx_wunpckel")]
1213 )
1215 (define_insn "iwmmxt_wunpckeluh"
1216 [(set (match_operand:V2SI 0 "register_operand" "=y")
1217 (vec_select:V2SI
1218 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1219 (parallel [(const_int 0) (const_int 1)])))]
1220 "TARGET_REALLY_IWMMXT"
1221 "wunpckeluh%?\\t%0, %1"
1222 [(set_attr "predicable" "yes")
1223 (set_attr "type" "wmmx_wunpckel")]
1224 )
1226 (define_insn "iwmmxt_wunpckeluw"
1227 [(set (match_operand:DI 0 "register_operand" "=y")
1228 (vec_select:DI
1229 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1230 (parallel [(const_int 0)])))]
1231 "TARGET_REALLY_IWMMXT"
1232 "wunpckeluw%?\\t%0, %1"
1233 [(set_attr "predicable" "yes")
1234 (set_attr "type" "wmmx_wunpckel")]
1235 )
1237 (define_insn "iwmmxt_wunpckelsb"
1238 [(set (match_operand:V4HI 0 "register_operand" "=y")
1239 (vec_select:V4HI
1240 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1241 (parallel [(const_int 0) (const_int 1)
1242 (const_int 2) (const_int 3)])))]
1243 "TARGET_REALLY_IWMMXT"
1244 "wunpckelsb%?\\t%0, %1"
1245 [(set_attr "predicable" "yes")
1246 (set_attr "type" "wmmx_wunpckel")]
1247 )
1249 (define_insn "iwmmxt_wunpckelsh"
1250 [(set (match_operand:V2SI 0 "register_operand" "=y")
1251 (vec_select:V2SI
1252 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1253 (parallel [(const_int 0) (const_int 1)])))]
1254 "TARGET_REALLY_IWMMXT"
1255 "wunpckelsh%?\\t%0, %1"
1256 [(set_attr "predicable" "yes")
1257 (set_attr "type" "wmmx_wunpckel")]
1258 )
1260 (define_insn "iwmmxt_wunpckelsw"
1261 [(set (match_operand:DI 0 "register_operand" "=y")
1262 (vec_select:DI
1263 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1264 (parallel [(const_int 0)])))]
1265 "TARGET_REALLY_IWMMXT"
1266 "wunpckelsw%?\\t%0, %1"
1267 [(set_attr "predicable" "yes")
1268 (set_attr "type" "wmmx_wunpckel")]
1269 )
1271 ;; Shifts
1273 (define_insn "ror<mode>3"
1274 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1275 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1276 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1277 "TARGET_REALLY_IWMMXT"
1278 "*
1279 switch (which_alternative)
1280 {
1281 case 0:
1282 return \"wror<MMX_char>g%?\\t%0, %1, %2\";
1283 case 1:
1284 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1285 default:
1286 gcc_unreachable ();
1287 }
1288 "
1289 [(set_attr "predicable" "yes")
1290 (set_attr "arch" "*, iwmmxt2")
1291 (set_attr "type" "wmmx_wror, wmmx_wror")]
1292 )
1294 (define_insn "ashr<mode>3_iwmmxt"
1295 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1296 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1297 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1298 "TARGET_REALLY_IWMMXT"
1299 "*
1300 switch (which_alternative)
1301 {
1302 case 0:
1303 return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
1304 case 1:
1305 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1306 default:
1307 gcc_unreachable ();
1308 }
1309 "
1310 [(set_attr "predicable" "yes")
1311 (set_attr "arch" "*, iwmmxt2")
1312 (set_attr "type" "wmmx_wsra, wmmx_wsra")]
1313 )
1315 (define_insn "lshr<mode>3_iwmmxt"
1316 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1317 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1318 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1319 "TARGET_REALLY_IWMMXT"
1320 "*
1321 switch (which_alternative)
1322 {
1323 case 0:
1324 return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
1325 case 1:
1326 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1327 default:
1328 gcc_unreachable ();
1329 }
1330 "
1331 [(set_attr "predicable" "yes")
1332 (set_attr "arch" "*, iwmmxt2")
1333 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
1334 )
1336 (define_insn "ashl<mode>3_iwmmxt"
1337 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1338 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1339 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1340 "TARGET_REALLY_IWMMXT"
1341 "*
1342 switch (which_alternative)
1343 {
1344 case 0:
1345 return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
1346 case 1:
1347 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1348 default:
1349 gcc_unreachable ();
1350 }
1351 "
1352 [(set_attr "predicable" "yes")
1353 (set_attr "arch" "*, iwmmxt2")
1354 (set_attr "type" "wmmx_wsll, wmmx_wsll")]
1355 )
1357 (define_insn "ror<mode>3_di"
1358 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1359 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1360 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1361 "TARGET_REALLY_IWMMXT"
1362 "*
1363 switch (which_alternative)
1364 {
1365 case 0:
1366 return \"wror<MMX_char>%?\\t%0, %1, %2\";
1367 case 1:
1368 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1369 default:
1370 gcc_unreachable ();
1371 }
1372 "
1373 [(set_attr "predicable" "yes")
1374 (set_attr "arch" "*, iwmmxt2")
1375 (set_attr "type" "wmmx_wror, wmmx_wror")]
1376 )
1378 (define_insn "ashr<mode>3_di"
1379 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1380 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1381 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1382 "TARGET_REALLY_IWMMXT"
1383 "*
1384 switch (which_alternative)
1385 {
1386 case 0:
1387 return \"wsra<MMX_char>%?\\t%0, %1, %2\";
1388 case 1:
1389 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1390 default:
1391 gcc_unreachable ();
1392 }
1393 "
1394 [(set_attr "predicable" "yes")
1395 (set_attr "arch" "*, iwmmxt2")
1396 (set_attr "type" "wmmx_wsra, wmmx_wsra")]
1397 )
1399 (define_insn "lshr<mode>3_di"
1400 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1401 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1402 (match_operand:DI 2 "register_operand" "y,i")))]
1403 "TARGET_REALLY_IWMMXT"
1404 "*
1405 switch (which_alternative)
1406 {
1407 case 0:
1408 return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
1409 case 1:
1410 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1411 default:
1412 gcc_unreachable ();
1413 }
1414 "
1415 [(set_attr "predicable" "yes")
1416 (set_attr "arch" "*, iwmmxt2")
1417 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
1418 )
1420 (define_insn "ashl<mode>3_di"
1421 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1422 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1423 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1424 "TARGET_REALLY_IWMMXT"
1425 "*
1426 switch (which_alternative)
1427 {
1428 case 0:
1429 return \"wsll<MMX_char>%?\\t%0, %1, %2\";
1430 case 1:
1431 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1432 default:
1433 gcc_unreachable ();
1434 }
1435 "
1436 [(set_attr "predicable" "yes")
1437 (set_attr "arch" "*, iwmmxt2")
1438 (set_attr "type" "wmmx_wsll, wmmx_wsll")]
1439 )
1441 (define_insn "iwmmxt_wmadds"
1442 [(set (match_operand:V2SI 0 "register_operand" "=y")
1443 (plus:V2SI
1444 (mult:V2SI
1445 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1446 (parallel [(const_int 1) (const_int 3)]))
1447 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1448 (parallel [(const_int 1) (const_int 3)])))
1449 (mult:V2SI
1450 (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
1451 (parallel [(const_int 0) (const_int 2)]))
1452 (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
1453 (parallel [(const_int 0) (const_int 2)])))))]
1454 "TARGET_REALLY_IWMMXT"
1455 "wmadds%?\\t%0, %1, %2"
1456 [(set_attr "predicable" "yes")
1457 (set_attr "type" "wmmx_wmadd")]
1458 )
1460 (define_insn "iwmmxt_wmaddu"
1461 [(set (match_operand:V2SI 0 "register_operand" "=y")
1462 (plus:V2SI
1463 (mult:V2SI
1464 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1465 (parallel [(const_int 1) (const_int 3)]))
1466 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1467 (parallel [(const_int 1) (const_int 3)])))
1468 (mult:V2SI
1469 (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
1470 (parallel [(const_int 0) (const_int 2)]))
1471 (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
1472 (parallel [(const_int 0) (const_int 2)])))))]
1473 "TARGET_REALLY_IWMMXT"
1474 "wmaddu%?\\t%0, %1, %2"
1475 [(set_attr "predicable" "yes")
1476 (set_attr "type" "wmmx_wmadd")]
1477 )
1479 (define_insn "iwmmxt_tmia"
1480 [(set (match_operand:DI 0 "register_operand" "=y")
1481 (plus:DI (match_operand:DI 1 "register_operand" "0")
1482 (mult:DI (sign_extend:DI
1483 (match_operand:SI 2 "register_operand" "r"))
1484 (sign_extend:DI
1485 (match_operand:SI 3 "register_operand" "r")))))]
1486 "TARGET_REALLY_IWMMXT"
1487 "tmia%?\\t%0, %2, %3"
1488 [(set_attr "predicable" "yes")
1489 (set_attr "type" "wmmx_tmia")]
1490 )
1492 (define_insn "iwmmxt_tmiaph"
1493 [(set (match_operand:DI 0 "register_operand" "=y")
1494 (plus:DI (match_operand:DI 1 "register_operand" "0")
1495 (plus:DI
1496 (mult:DI (sign_extend:DI
1497 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1498 (sign_extend:DI
1499 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1500 (mult:DI (sign_extend:DI
1501 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1502 (sign_extend:DI
1503 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1504 "TARGET_REALLY_IWMMXT"
1505 "tmiaph%?\\t%0, %2, %3"
1506 [(set_attr "predicable" "yes")
1507 (set_attr "type" "wmmx_tmiaph")]
1508 )
1510 (define_insn "iwmmxt_tmiabb"
1511 [(set (match_operand:DI 0 "register_operand" "=y")
1512 (plus:DI (match_operand:DI 1 "register_operand" "0")
1513 (mult:DI (sign_extend:DI
1514 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1515 (sign_extend:DI
1516 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1517 "TARGET_REALLY_IWMMXT"
1518 "tmiabb%?\\t%0, %2, %3"
1519 [(set_attr "predicable" "yes")
1520 (set_attr "type" "wmmx_tmiaxy")]
1521 )
1523 (define_insn "iwmmxt_tmiatb"
1524 [(set (match_operand:DI 0 "register_operand" "=y")
1525 (plus:DI (match_operand:DI 1 "register_operand" "0")
1526 (mult:DI (sign_extend:DI
1527 (truncate:HI
1528 (ashiftrt:SI
1529 (match_operand:SI 2 "register_operand" "r")
1530 (const_int 16))))
1531 (sign_extend:DI
1532 (truncate:HI
1533 (match_operand:SI 3 "register_operand" "r"))))))]
1534 "TARGET_REALLY_IWMMXT"
1535 "tmiatb%?\\t%0, %2, %3"
1536 [(set_attr "predicable" "yes")
1537 (set_attr "type" "wmmx_tmiaxy")]
1538 )
1540 (define_insn "iwmmxt_tmiabt"
1541 [(set (match_operand:DI 0 "register_operand" "=y")
1542 (plus:DI (match_operand:DI 1 "register_operand" "0")
1543 (mult:DI (sign_extend:DI
1544 (truncate:HI
1545 (match_operand:SI 2 "register_operand" "r")))
1546 (sign_extend:DI
1547 (truncate:HI
1548 (ashiftrt:SI
1549 (match_operand:SI 3 "register_operand" "r")
1550 (const_int 16)))))))]
1551 "TARGET_REALLY_IWMMXT"
1552 "tmiabt%?\\t%0, %2, %3"
1553 [(set_attr "predicable" "yes")
1554 (set_attr "type" "wmmx_tmiaxy")]
1555 )
1557 (define_insn "iwmmxt_tmiatt"
1558 [(set (match_operand:DI 0 "register_operand" "=y")
1559 (plus:DI (match_operand:DI 1 "register_operand" "0")
1560 (mult:DI (sign_extend:DI
1561 (truncate:HI
1562 (ashiftrt:SI
1563 (match_operand:SI 2 "register_operand" "r")
1564 (const_int 16))))
1565 (sign_extend:DI
1566 (truncate:HI
1567 (ashiftrt:SI
1568 (match_operand:SI 3 "register_operand" "r")
1569 (const_int 16)))))))]
1570 "TARGET_REALLY_IWMMXT"
1571 "tmiatt%?\\t%0, %2, %3"
1572 [(set_attr "predicable" "yes")
1573 (set_attr "type" "wmmx_tmiaxy")]
1574 )
1576 (define_insn "iwmmxt_tmovmskb"
1577 [(set (match_operand:SI 0 "register_operand" "=r")
1578 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1579 "TARGET_REALLY_IWMMXT"
1580 "tmovmskb%?\\t%0, %1"
1581 [(set_attr "predicable" "yes")
1582 (set_attr "type" "wmmx_tmovmsk")]
1583 )
1585 (define_insn "iwmmxt_tmovmskh"
1586 [(set (match_operand:SI 0 "register_operand" "=r")
1587 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1588 "TARGET_REALLY_IWMMXT"
1589 "tmovmskh%?\\t%0, %1"
1590 [(set_attr "predicable" "yes")
1591 (set_attr "type" "wmmx_tmovmsk")]
1592 )
1594 (define_insn "iwmmxt_tmovmskw"
1595 [(set (match_operand:SI 0 "register_operand" "=r")
1596 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1597 "TARGET_REALLY_IWMMXT"
1598 "tmovmskw%?\\t%0, %1"
1599 [(set_attr "predicable" "yes")
1600 (set_attr "type" "wmmx_tmovmsk")]
1601 )
1603 (define_insn "iwmmxt_waccb"
1604 [(set (match_operand:DI 0 "register_operand" "=y")
1605 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1606 "TARGET_REALLY_IWMMXT"
1607 "waccb%?\\t%0, %1"
1608 [(set_attr "predicable" "yes")
1609 (set_attr "type" "wmmx_wacc")]
1610 )
1612 (define_insn "iwmmxt_wacch"
1613 [(set (match_operand:DI 0 "register_operand" "=y")
1614 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1615 "TARGET_REALLY_IWMMXT"
1616 "wacch%?\\t%0, %1"
1617 [(set_attr "predicable" "yes")
1618 (set_attr "type" "wmmx_wacc")]
1619 )
1621 (define_insn "iwmmxt_waccw"
1622 [(set (match_operand:DI 0 "register_operand" "=y")
1623 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1624 "TARGET_REALLY_IWMMXT"
1625 "waccw%?\\t%0, %1"
1626 [(set_attr "predicable" "yes")
1627 (set_attr "type" "wmmx_wacc")]
1628 )
1630 ;; use unspec here to prevent 8 * imm to be optimized by cse
1631 (define_insn "iwmmxt_waligni"
1632 [(set (match_operand:V8QI 0 "register_operand" "=y")
1633 (unspec:V8QI [(subreg:V8QI
1634 (ashiftrt:TI
1635 (subreg:TI (vec_concat:V16QI
1636 (match_operand:V8QI 1 "register_operand" "y")
1637 (match_operand:V8QI 2 "register_operand" "y")) 0)
1638 (mult:SI
1639 (match_operand:SI 3 "immediate_operand" "i")
1640 (const_int 8))) 0)] UNSPEC_WALIGNI))]
1641 "TARGET_REALLY_IWMMXT"
1642 "waligni%?\\t%0, %1, %2, %3"
1643 [(set_attr "predicable" "yes")
1644 (set_attr "type" "wmmx_waligni")]
1645 )
1647 (define_insn "iwmmxt_walignr"
1648 [(set (match_operand:V8QI 0 "register_operand" "=y")
1649 (subreg:V8QI (ashiftrt:TI
1650 (subreg:TI (vec_concat:V16QI
1651 (match_operand:V8QI 1 "register_operand" "y")
1652 (match_operand:V8QI 2 "register_operand" "y")) 0)
1653 (mult:SI
1654 (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0))
1655 (const_int 8))) 0))]
1656 "TARGET_REALLY_IWMMXT"
1657 "walignr%U3%?\\t%0, %1, %2"
1658 [(set_attr "predicable" "yes")
1659 (set_attr "type" "wmmx_walignr")]
1660 )
1662 (define_insn "iwmmxt_walignr0"
1663 [(set (match_operand:V8QI 0 "register_operand" "=y")
1664 (subreg:V8QI (ashiftrt:TI
1665 (subreg:TI (vec_concat:V16QI
1666 (match_operand:V8QI 1 "register_operand" "y")
1667 (match_operand:V8QI 2 "register_operand" "y")) 0)
1668 (mult:SI
1669 (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0))
1670 (const_int 8))) 0))]
1671 "TARGET_REALLY_IWMMXT"
1672 "walignr0%?\\t%0, %1, %2"
1673 [(set_attr "predicable" "yes")
1674 (set_attr "type" "wmmx_walignr")]
1675 )
1677 (define_insn "iwmmxt_walignr1"
1678 [(set (match_operand:V8QI 0 "register_operand" "=y")
1679 (subreg:V8QI (ashiftrt:TI
1680 (subreg:TI (vec_concat:V16QI
1681 (match_operand:V8QI 1 "register_operand" "y")
1682 (match_operand:V8QI 2 "register_operand" "y")) 0)
1683 (mult:SI
1684 (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0))
1685 (const_int 8))) 0))]
1686 "TARGET_REALLY_IWMMXT"
1687 "walignr1%?\\t%0, %1, %2"
1688 [(set_attr "predicable" "yes")
1689 (set_attr "type" "wmmx_walignr")]
1690 )
1692 (define_insn "iwmmxt_walignr2"
1693 [(set (match_operand:V8QI 0 "register_operand" "=y")
1694 (subreg:V8QI (ashiftrt:TI
1695 (subreg:TI (vec_concat:V16QI
1696 (match_operand:V8QI 1 "register_operand" "y")
1697 (match_operand:V8QI 2 "register_operand" "y")) 0)
1698 (mult:SI
1699 (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0))
1700 (const_int 8))) 0))]
1701 "TARGET_REALLY_IWMMXT"
1702 "walignr2%?\\t%0, %1, %2"
1703 [(set_attr "predicable" "yes")
1704 (set_attr "type" "wmmx_walignr")]
1705 )
1707 (define_insn "iwmmxt_walignr3"
1708 [(set (match_operand:V8QI 0 "register_operand" "=y")
1709 (subreg:V8QI (ashiftrt:TI
1710 (subreg:TI (vec_concat:V16QI
1711 (match_operand:V8QI 1 "register_operand" "y")
1712 (match_operand:V8QI 2 "register_operand" "y")) 0)
1713 (mult:SI
1714 (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0))
1715 (const_int 8))) 0))]
1716 "TARGET_REALLY_IWMMXT"
1717 "walignr3%?\\t%0, %1, %2"
1718 [(set_attr "predicable" "yes")
1719 (set_attr "type" "wmmx_walignr")]
1720 )
1722 (define_insn "iwmmxt_wsadb"
1723 [(set (match_operand:V2SI 0 "register_operand" "=y")
1724 (unspec:V2SI [
1725 (match_operand:V2SI 1 "register_operand" "0")
1726 (match_operand:V8QI 2 "register_operand" "y")
1727 (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))]
1728 "TARGET_REALLY_IWMMXT"
1729 "wsadb%?\\t%0, %2, %3"
1730 [(set_attr "predicable" "yes")
1731 (set_attr "type" "wmmx_wsad")]
1732 )
1734 (define_insn "iwmmxt_wsadh"
1735 [(set (match_operand:V2SI 0 "register_operand" "=y")
1736 (unspec:V2SI [
1737 (match_operand:V2SI 1 "register_operand" "0")
1738 (match_operand:V4HI 2 "register_operand" "y")
1739 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))]
1740 "TARGET_REALLY_IWMMXT"
1741 "wsadh%?\\t%0, %2, %3"
1742 [(set_attr "predicable" "yes")
1743 (set_attr "type" "wmmx_wsad")]
1744 )
1746 (define_insn "iwmmxt_wsadbz"
1747 [(set (match_operand:V2SI 0 "register_operand" "=y")
1748 (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
1749 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1750 "TARGET_REALLY_IWMMXT"
1751 "wsadbz%?\\t%0, %1, %2"
1752 [(set_attr "predicable" "yes")
1753 (set_attr "type" "wmmx_wsad")]
1754 )
1756 (define_insn "iwmmxt_wsadhz"
1757 [(set (match_operand:V2SI 0 "register_operand" "=y")
1758 (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
1759 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1760 "TARGET_REALLY_IWMMXT"
1761 "wsadhz%?\\t%0, %1, %2"
1762 [(set_attr "predicable" "yes")
1763 (set_attr "type" "wmmx_wsad")]
1764 )
1766 (include "iwmmxt2.md")