RISC-V: Add naked function support.
[official-gcc.git] / gcc / config / riscv / riscv-protos.h
blob0538ede77e48e4bffe8f250fda4b656946b96fc8
1 /* Definition of RISC-V target for GNU compiler.
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #ifndef GCC_RISCV_PROTOS_H
23 #define GCC_RISCV_PROTOS_H
25 /* Symbol types we understand. The order of this list must match that of
26 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
27 enum riscv_symbol_type {
28 SYMBOL_ABSOLUTE,
29 SYMBOL_PCREL,
30 SYMBOL_GOT_DISP,
31 SYMBOL_TLS,
32 SYMBOL_TLS_LE,
33 SYMBOL_TLS_IE,
34 SYMBOL_TLS_GD
36 #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
38 /* Routines implemented in riscv.c. */
39 extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
40 extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
41 extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
42 extern int riscv_address_insns (rtx, machine_mode, bool);
43 extern int riscv_const_insns (rtx);
44 extern int riscv_split_const_insns (rtx);
45 extern int riscv_load_store_insns (rtx, rtx_insn *);
46 extern rtx riscv_emit_move (rtx, rtx);
47 extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
48 extern bool riscv_split_symbol_type (enum riscv_symbol_type);
49 extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
50 extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
51 extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
52 extern rtx riscv_subword (rtx, bool);
53 extern bool riscv_split_64bit_move_p (rtx, rtx);
54 extern void riscv_split_doubleword_move (rtx, rtx);
55 extern const char *riscv_output_move (rtx, rtx);
56 extern const char *riscv_output_gpr_save (unsigned);
57 extern const char *riscv_output_return ();
58 #ifdef RTX_CODE
59 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
60 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
61 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
62 #endif
63 extern rtx riscv_legitimize_call_address (rtx);
64 extern void riscv_set_return_address (rtx, rtx);
65 extern bool riscv_expand_block_move (rtx, rtx, rtx);
66 extern rtx riscv_return_addr (int, rtx);
67 extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
68 extern void riscv_expand_prologue (void);
69 extern void riscv_expand_epilogue (bool);
70 extern bool riscv_can_use_return_insn (void);
71 extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
72 extern bool riscv_expand_block_move (rtx, rtx, rtx);
74 /* Routines implemented in riscv-c.c. */
75 void riscv_cpu_cpp_builtins (cpp_reader *);
77 /* Routines implemented in riscv-builtins.c. */
78 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
79 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
80 extern tree riscv_builtin_decl (unsigned int, bool);
81 extern void riscv_init_builtins (void);
83 #endif /* ! GCC_RISCV_PROTOS_H */