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Initial revision
[official-gcc.git] / gcc / config / arm / arm.h
blobf51b76fe9327062013d250ccb546e01474c18077
1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_prologue ();
28 extern void output_epilogue ();
29 extern char *arm_output_asm_insn ();
30 extern char *arm_output_llc ();
31 extern char *arithmetic_instr ();
32 extern char *output_add_immediate ();
33 extern char *output_call ();
34 extern char *output_call_mem ();
35 extern char *output_move_double ();
36 extern char *output_mov_double_fpu_from_arm ();
37 extern char *output_mov_double_arm_from_fpu ();
38 extern char *output_mov_immediate ();
39 extern char *output_multi_immediate ();
40 extern char *output_shifted_move ();
41 extern char *output_shift_compare ();
42 extern char *output_arithmetic_with_immediate_multiply ();
43 extern char *output_arithmetic_with_shift ();
44 extern char *output_return_instruction ();
45 extern char *output_load_symbol ();
46 extern char *fp_immediate_constant ();
47 extern struct rtx_def *gen_compare_reg ();
48 extern struct rtx_def *arm_gen_store_multiple ();
49 extern struct rtx_def *arm_gen_load_multiple ();
50
51 extern char *arm_condition_codes[];
52
53 /* This is needed by the tail-calling peepholes */
54 extern int frame_pointer_needed;
55
56 \f
57 #ifndef CPP_PREDEFINES
58 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
59 #endif
60
61 #ifndef CPP_SPEC
62 #define CPP_SPEC "%{m6:-D__arm6__}"
63 #endif
64 \f
65 /* Run-time Target Specification. */
66 #ifndef TARGET_VERSION
67 #define TARGET_VERSION \
68 fputs (" (ARM/generic)", stderr);
69 #endif
70
71 /* Run-time compilation parameters selecting different hardware subsets.
72 On the ARM, misuse it in a different way. */
73 extern int target_flags;
74
75 /* Nonzero if the function prologue (and epilogue) should obey
76 the ARM Procedure Call Standard. */
77 #define TARGET_APCS (target_flags & 1)
78
79 /* Nonzero if the function prologue should output the function name to enable
80 the post mortem debugger to print a backtrace (very useful on RISCOS,
81 unused on RISCiX). Specifying this flag also enables -mapcs.
82 XXX Must still be implemented in the prologue. */
83 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
84
85 /* Nonzero if floating point instructions are emulated by the FPE, in which
86 case instruction scheduling becomes very uninteresting. */
87 #define TARGET_FPE (target_flags & 4)
88
89 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
90 of condition flags when returning from a branch & link (ie. a function) */
91 #define TARGET_6 (target_flags & 8)
92
93 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
94 are passed to the preprocessor and the assembler post-processor. They
95 aren't needed in the main pass of the compiler, but if we don't define
96 them in target switches cc1 complains about them. For the sake of
97 argument lets allocate bit 31 of target flags for such options. */
98
99 #ifndef ARM_EXTRA_TARGET_SWITCHES
100 #define ARM_EXTRA_TARGET_SWITCHES
101 #endif
102
103 #define TARGET_SWITCHES \
104 { \
105 {"apcs", 1}, \
106 {"poke-function-name", 2}, \
107 {"fpe", 4}, \
108 {"6", 8}, \
109 {"2", -8}, \
110 {"3", -8}, \
111 ARM_EXTRA_TARGET_SWITCHES \
112 {"", TARGET_DEFAULT } \
113 }
114
115 /* Which processor we are running on. Currently this is only used to
116 get the condition code clobbering attribute right when we are running on
117 an arm 6 */
118
119 enum processor_type
120 {
121 PROCESSOR_ARM2,
122 PROCESSOR_ARM3,
123 PROCESSOR_ARM6
124 };
125
126 /* Recast the cpu class to be the cpu attribute. */
127
128 /* Recast the cpu class to be the cpu attribute. */
129 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
130
131 extern enum processor_type arm_cpu;
132
133 #define TARGET_DEFAULT 0
134
135 #define TARGET_MEM_FUNCTIONS 1
136
137 /* OVERRIDE_OPTIONS takes care of the following:
138 - if -mpoke-function-name, then -mapcs.
139 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
140 - if floating point is done by emulation, forget about instruction
141 scheduling. Note that this only saves compilation time; it doesn't
142 matter for the final code. */
143 #ifndef TARGET_WHEN_DEBUGGING
144 #define TARGET_WHEN_DEBUGGING 1
145 #endif
146
147 #define OVERRIDE_OPTIONS \
148 { \
149 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
150 warning ("-g without a frame pointer may not give sensible debugging");\
151 if (TARGET_POKE_FUNCTION_NAME) \
152 target_flags |= 1; \
153 if (TARGET_FPE) \
154 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
155 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
156 }
157
158 /* Omitting the frame pointer is a very good idea on the ARM, especially if
159 not TARGET_APCS, in which case all that pushing on function entry isn't
160 mandatory anymore.
161 Forcing loads to be explicit also allows cse to work better */
162
163 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
164 { \
165 if (OPTIMIZE) \
166 { \
167 flag_force_mem = 1; \
168 flag_omit_frame_pointer = 1; \
169 } \
170 }
171 \f
172 /* Target machine storage Layout. */
173
174
175 /* Define this macro if it is advisable to hold scalars in registers
176 in a wider mode than that declared by the program. In such cases,
177 the value is constrained to be within the bounds of the declared
178 type, but kept valid in the wider mode. The signedness of the
179 extension may differ from that of the type. */
180
181 /* It is far faster to zero extend chars than to sign extend them */
182
183 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
184 if (GET_MODE_CLASS (MODE) == MODE_INT \
185 && GET_MODE_SIZE (MODE) < 4) \
186 { \
187 if (MODE == QImode) \
188 UNSIGNEDP = 1; \
189 (MODE) = SImode; \
190 }
191
192 /* Define for XFmode extended real floating point support.
193 This will automatically cause REAL_ARITHMETIC to be defined. */
194 /* For the ARM:
195 I think I have added all the code to make this work. Unfortunately,
196 early releases of the floating point emulation code on RISCiX used a
197 different format for extended precision numbers. On my RISCiX box there
198 is a bug somewhere which causes the machine to lock up when running enquire
199 with long doubles. There is the additional aspect that Norcroft C
200 treats long doubles as doubles and we ought to remain compatible.
201 Perhaps someone with an FPA coprocessor and not running RISCiX would like
202 to try this someday. */
203 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
204
205 /* Disable XFmode patterns in md file */
206 #define ENABLE_XF_PATTERNS 0
207
208 /* Define if you don't want extended real, but do want to use the
209 software floating point emulator for REAL_ARITHMETIC and
210 decimal <-> binary conversion. */
211 /* See comment above */
212 #define REAL_ARITHMETIC
213
214 /* Define this if most significant bit is lowest numbered
215 in instructions that operate on numbered bit-fields. */
216 #define BITS_BIG_ENDIAN 0
217
218 /* Define this if most significant byte of a word is the lowest numbered. */
219 #define BYTES_BIG_ENDIAN 0
220
221 /* Define this if most significant word of a multiword number is the lowest
222 numbered. */
223 #define WORDS_BIG_ENDIAN 0
224
225 /* Number of bits in an addressable storage unit */
226 #define BITS_PER_UNIT 8
227
228 #define BITS_PER_WORD 32
229
230 #define UNITS_PER_WORD 4
231
232 #define POINTER_SIZE 32
233
234 #define PARM_BOUNDARY 32
235
236 #define STACK_BOUNDARY 32
237
238 #define FUNCTION_BOUNDARY 32
239
240 #define EMPTY_FIELD_BOUNDARY 32
241
242 #define BIGGEST_ALIGNMENT 32
243
244 /* Make strings word-aligned so strcpy from constants will be faster. */
245 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
246 (TREE_CODE (EXP) == STRING_CST \
247 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
248
249 /* Every structures size must be a multiple of 32 bits. */
250 #define STRUCTURE_SIZE_BOUNDARY 32
251
252 /* Non-zero if move instructions will actually fail to work
253 when given unaligned data. */
254 #define STRICT_ALIGNMENT 1
255
256 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
257
258 /* Define number of bits in most basic integer type.
259 (If undefined, default is BITS_PER_WORD). */
260 /* #define INT_TYPE_SIZE */
261 \f
262 /* Standard register usage. */
263
264 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
265 (S - saved over call).
266
267 r0 * argument word/integer result
268 r1-r3 argument word
269
270 r4-r8 S register variable
271 r9 S (rfp) register variable (real frame pointer)
272
273 r10 F S (sl) stack limit (not currently used)
274 r11 F S (fp) argument pointer
275 r12 (ip) temp workspace
276 r13 F S (sp) lower end of current stack frame
277 r14 (lr) link address/workspace
278 r15 F (pc) program counter
279
280 f0 floating point result
281 f1-f3 floating point scratch
282
283 f4-f7 S floating point variable
284
285 cc This is NOT a real register, but is used internally
286 to represent things that use or set the condition
287 codes.
288 sfp This isn't either. It is used during rtl generation
289 since the offset between the frame pointer and the
290 auto's isn't known until after register allocation.
291 afp Nor this, we only need this because of non-local
292 goto. Without it fp appears to be used and the
293 elimination code won't get rid of sfp. It tracks
294 fp exactly at all times.
295
296 *: See CONDITIONAL_REGISTER_USAGE */
297
298 /* The stack backtrace structure is as follows:
299 fp points to here: | save code pointer | [fp]
300 | return link value | [fp, #-4]
301 | return sp value | [fp, #-8]
302 | return fp value | [fp, #-12]
303 [| saved r10 value |]
304 [| saved r9 value |]
305 [| saved r8 value |]
306 [| saved r7 value |]
307 [| saved r6 value |]
308 [| saved r5 value |]
309 [| saved r4 value |]
310 [| saved r3 value |]
311 [| saved r2 value |]
312 [| saved r1 value |]
313 [| saved r0 value |]
314 [| saved f7 value |] three words
315 [| saved f6 value |] three words
316 [| saved f5 value |] three words
317 [| saved f4 value |] three words
318 r0-r3 are not normally saved in a C function. */
319
320 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
321 #define FIRST_PSEUDO_REGISTER 27
322
323 /* 1 for registers that have pervasive standard uses
324 and are not available for the register allocator. */
325 #define FIXED_REGISTERS \
326 { \
327 0,0,0,0,0,0,0,0, \
328 0,0,1,1,0,1,0,1, \
329 0,0,0,0,0,0,0,0, \
330 1,1,1 \
331 }
332
333 /* 1 for registers not available across function calls.
334 These must include the FIXED_REGISTERS and also any
335 registers that can be used without being saved.
336 The latter must include the registers where values are returned
337 and the register where structure-value addresses are passed.
338 Aside from that, you can include as many other registers as you like.
339 The CC is not preserved over function calls on the ARM 6, so it is
340 easier to assume this for all. SFP is preserved, since FP is. */
341 #define CALL_USED_REGISTERS \
342 { \
343 1,1,1,1,0,0,0,0, \
344 0,0,1,1,1,1,1,1, \
345 1,1,1,1,0,0,0,0, \
346 1,1,1 \
347 }
348
349 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
350 trampled. This effectively reduces the number of available registers by 1.
351 XXX It is a hack, I know.
352 XXX Is this still needed? */
353 #define CONDITIONAL_REGISTER_USAGE \
354 { \
355 if (obey_regdecls) \
356 fixed_regs[0] = 1; \
357 }
358
359 /* Return number of consecutive hard regs needed starting at reg REGNO
360 to hold something of mode MODE.
361 This is ordinarily the length in words of a value of mode MODE
362 but can be less for certain modes in special long registers.
363
364 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
365 mode. */
366 #define HARD_REGNO_NREGS(REGNO, MODE) \
367 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
368 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
369 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
370
371 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
372 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
373 regs holding FP. */
374 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
375 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
376 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
377 || REGNO == ARG_POINTER_REGNUM \
378 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
379
380 /* Value is 1 if it is a good idea to tie two pseudo registers
381 when one has mode MODE1 and one has mode MODE2.
382 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
383 for any hard reg, then this must be 0 for correct output. */
384 #define MODES_TIEABLE_P(MODE1, MODE2) \
385 (((MODE1) == SFmode || (MODE1) == DFmode) \
386 == ((MODE2) == SFmode || (MODE2) == DFmode))
387
388 /* Specify the registers used for certain standard purposes.
389 The values of these macros are register numbers. */
390
391 /* Define this if the program counter is overloaded on a register. */
392 #define PC_REGNUM 15
393
394 /* Register to use for pushing function arguments. */
395 #define STACK_POINTER_REGNUM 13
396
397 /* Base register for access to local variables of the function. */
398 #define FRAME_POINTER_REGNUM 25
399
400 /* Define this to be where the real frame pointer is if it is not possible to
401 work out the offset between the frame pointer and the automatic variables
402 until after register allocation has taken place. FRAME_POINTER_REGNUM
403 should point to a special register that we will make sure is eliminated. */
404 #define HARD_FRAME_POINTER_REGNUM 11
405
406 /* Value should be nonzero if functions must have frame pointers.
407 Zero means the frame pointer need not be set up (and parms may be accessed
408 via the stack pointer) in functions that seem suitable.
409 If we have to have a frame pointer we might as well make use of it.
410 APCS says that the frame pointer does not need to be pushed in leaf
411 functions. */
412 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
413
414 /* Base register for access to arguments of the function. */
415 #define ARG_POINTER_REGNUM 26
416
417 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
418 as an invisible last argument (possible since varargs don't exist in
419 Pascal), so the following is not true. */
420 #define STATIC_CHAIN_REGNUM 8
421
422 /* Register in which address to store a structure value
423 is passed to a function. */
424 #define STRUCT_VALUE_REGNUM 0
425
426 /* Internal, so that we don't need to refer to a raw number */
427 #define CC_REGNUM 24
428
429 /* The order in which register should be allocated. It is good to use ip
430 since no saving is required (though calls clobber it) and it never contains
431 function parameters. It is quite good to use lr since other calls may
432 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
433 least likely to contain a function parameter; in addition results are
434 returned in r0.
435 */
436 #define REG_ALLOC_ORDER \
437 { \
438 3, 2, 1, 0, 12, 14, 4, 5, \
439 6, 7, 8, 10, 9, 11, 13, 15, \
440 16, 17, 18, 19, 20, 21, 22, 23, \
441 24, 25 \
442 }
443 \f
444 /* Register and constant classes. */
445
446 /* Register classes: all ARM regs or all FPU regs---simple! */
447 enum reg_class
448 {
449 NO_REGS,
450 FPU_REGS,
451 GENERAL_REGS,
452 ALL_REGS,
453 LIM_REG_CLASSES
454 };
455
456 #define N_REG_CLASSES (int) LIM_REG_CLASSES
457
458 /* Give names of register classes as strings for dump file. */
459 #define REG_CLASS_NAMES \
460 { \
461 "NO_REGS", \
462 "FPU_REGS", \
463 "GENERAL_REGS", \
464 "ALL_REGS", \
465 }
466
467 /* Define which registers fit in which classes.
468 This is an initializer for a vector of HARD_REG_SET
469 of length N_REG_CLASSES. */
470 #define REG_CLASS_CONTENTS \
471 { \
472 0x0000000, /* NO_REGS */ \
473 0x0FF0000, /* FPU_REGS */ \
474 0x200FFFF, /* GENERAL_REGS */ \
475 0x2FFFFFF /* ALL_REGS */ \
476 }
477
478 /* The same information, inverted:
479 Return the class number of the smallest class containing
480 reg number REGNO. This could be a conditional expression
481 or could index an array. */
482 #define REGNO_REG_CLASS(REGNO) \
483 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
484 || REGNO == ARG_POINTER_REGNUM) \
485 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
486 ? NO_REGS : FPU_REGS)
487
488 /* The class value for index registers, and the one for base regs. */
489 #define INDEX_REG_CLASS GENERAL_REGS
490 #define BASE_REG_CLASS GENERAL_REGS
491
492 /* Get reg_class from a letter such as appears in the machine description.
493 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
494 #define REG_CLASS_FROM_LETTER(C) \
495 ((C)=='f' ? FPU_REGS : NO_REGS)
496
497 /* The letters I, J, K, L and M in a register constraint string
498 can be used to stand for particular ranges of immediate operands.
499 This macro defines what the ranges are.
500 C is the letter, and VALUE is a constant value.
501 Return 1 if VALUE is in the range specified by C.
502 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
503 J: valid indexing constants.
504 K: as I but also (not (value)) ok.
505 L: as I but also (neg (value)) ok.*/
506 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
507 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
508 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
509 (C) == 'K' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (~(VALUE))) : \
510 (C) == 'L' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (-(VALUE))) : 0)
511
512 /* For the ARM, `Q' means that this is a memory operand that is just
513 an offset from a register.
514 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
515 address. This means that the symbol is in the text segment and can be
516 accessed without using a load. */
517
518 #define EXTRA_CONSTRAINT(OP, C) \
519 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
520 : (C) == 'S' ? CONSTANT_ADDRESS_P (OP) : 0)
521
522 /* Constant letter 'G' for the FPU immediate constants.
523 'H' means the same constant negated. */
524 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
525 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
526 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
527
528 /* Given an rtx X being reloaded into a reg required to be
529 in class CLASS, return the class of reg to actually use.
530 In general this is just CLASS; but on some machines
531 in some cases it is preferable to use a more restrictive class. */
532 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
533
534 /* Return the register class of a scratch register needed to copy IN into
535 or out of a register in CLASS in MODE. If it can be done directly,
536 NO_REGS is returned. */
537 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
538 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
539 && true_regnum (X) == -1) ? GENERAL_REGS \
540 : NO_REGS)
541
542 /* Return the maximum number of consecutive registers
543 needed to represent mode MODE in a register of class CLASS.
544 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
545 #define CLASS_MAX_NREGS(CLASS, MODE) \
546 ((CLASS) == FPU_REGS ? 1 \
547 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
548
549 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
550 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
551 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
552 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
553 ? 20 : 2)
554 \f
555 /* Stack layout; function entry, exit and calling. */
556
557 /* Define this if pushing a word on the stack
558 makes the stack pointer a smaller address. */
559 #define STACK_GROWS_DOWNWARD 1
560
561 /* Define this if the nominal address of the stack frame
562 is at the high-address end of the local variables;
563 that is, each additional local variable allocated
564 goes at a more negative offset in the frame. */
565 #define FRAME_GROWS_DOWNWARD 1
566
567 /* Offset within stack frame to start allocating local variables at.
568 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
569 first local allocated. Otherwise, it is the offset to the BEGINNING
570 of the first local allocated. */
571 #define STARTING_FRAME_OFFSET 0
572
573 /* If we generate an insn to push BYTES bytes,
574 this says how many the stack pointer really advances by. */
575 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
576
577 /* Offset of first parameter from the argument pointer register value. */
578 #define FIRST_PARM_OFFSET(FNDECL) 4
579
580 /* Value is the number of byte of arguments automatically
581 popped when returning from a subroutine call.
582 FUNTYPE is the data type of the function (as a tree),
583 or for a library call it is an identifier node for the subroutine name.
584 SIZE is the number of bytes of arguments passed on the stack.
585
586 On the ARM, the caller does not pop any of its arguments that were passed
587 on the stack. */
588 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
589
590 /* Define how to find the value returned by a function.
591 VALTYPE is the data type of the value (as a tree).
592 If the precise function being called is known, FUNC is its FUNCTION_DECL;
593 otherwise, FUNC is 0. */
594 #define FUNCTION_VALUE(VALTYPE, FUNC) \
595 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
596 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
597 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
598
599 /* Define how to find the value returned by a library function
600 assuming the value has mode MODE. */
601 #define LIBCALL_VALUE(MODE) \
602 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
603 ? gen_rtx (REG, MODE, 16) \
604 : gen_rtx (REG, MODE, 0))
605
606 /* 1 if N is a possible register number for a function value.
607 On the ARM, only r0 and f0 can return results. */
608 #define FUNCTION_VALUE_REGNO_P(REGNO) \
609 ((REGNO) == 0 || (REGNO) == 16)
610
611 /* Define where to put the arguments to a function.
612 Value is zero to push the argument on the stack,
613 or a hard register in which to store the argument.
614
615 MODE is the argument's machine mode.
616 TYPE is the data type of the argument (as a tree).
617 This is null for libcalls where that information may
618 not be available.
619 CUM is a variable of type CUMULATIVE_ARGS which gives info about
620 the preceding args and about the function being called.
621 NAMED is nonzero if this argument is a named parameter
622 (otherwise it is an extra parameter matching an ellipsis).
623
624 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
625 other arguments are passed on the stack. If (NAMED == 0) (which happens
626 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
627 passed in the stack (function_prologue will indeed make it pass in the
628 stack if necessary). */
629 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
630 ((NAMED) \
631 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
632 : 0)
633
634 /* For an arg passed partly in registers and partly in memory,
635 this is the number of registers used.
636 For args passed entirely in registers or entirely in memory, zero. */
637 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
638 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
639 ? GET_MODE_SIZE (MODE) \
640 : int_size_in_bytes (TYPE)) \
641 ? 4 - (CUM) / 4 : 0)
642
643 /* A C type for declaring a variable that is used as the first argument of
644 `FUNCTION_ARG' and other related values. For some target machines, the
645 type `int' suffices and can hold the number of bytes of argument so far.
646
647 On the ARM, this is the number of bytes of arguments scanned so far. */
648 #define CUMULATIVE_ARGS int
649
650 /* Initialize a variable CUM of type CUMULATIVE_ARGS
651 for a call to a function whose data type is FNTYPE.
652 For a library call, FNTYPE is 0.
653 On the ARM, the offset starts at 0. */
654 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
655 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
656
657 /* Update the data in CUM to advance over an argument
658 of mode MODE and data type TYPE.
659 (TYPE is null for libcalls where that information may not be available.) */
660 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
661 (CUM) += ((MODE) != BLKmode \
662 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
663 : (int_size_in_bytes (TYPE) + 3) & ~3) \
664
665 /* 1 if N is a possible register number for function argument passing.
666 On the ARM, r0-r3 are used to pass args. */
667 #define FUNCTION_ARG_REGNO_P(REGNO) \
668 ((REGNO) >= 0 && (REGNO) <= 3)
669
670 /* Perform any actions needed for a function that is receiving a variable
671 number of arguments. CUM is as above. MODE and TYPE are the mode and type
672 of the current parameter. PRETEND_SIZE is a variable that should be set to
673 the amount of stack that must be pushed by the prolog to pretend that our
674 caller pushed it.
675
676 Normally, this macro will push all remaining incoming registers on the
677 stack and set PRETEND_SIZE to the length of the registers pushed.
678
679 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
680 named arg and all anonymous args onto the stack.
681 XXX I know the prologue shouldn't be pushing registers, but it is faster
682 that way. */
683 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
684 { \
685 extern int current_function_anonymous_args; \
686 current_function_anonymous_args = 1; \
687 if ((CUM) < 16) \
688 (PRETEND_SIZE) = 16 - (CUM); \
689 }
690
691 /* Generate assembly output for the start of a function. */
692 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
693 output_prologue ((STREAM), (SIZE))
694
695 /* Call the function profiler with a given profile label. The Acorn compiler
696 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
697 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
698 to mind about this! */
699 #define FUNCTION_PROFILER(STREAM,LABELNO) \
700 { \
701 fprintf(STREAM, "\tmov\tip, lr\n"); \
702 fprintf(STREAM, "\tbl\tmcount\n"); \
703 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
704 arm_increase_location (12); \
705 }
706
707 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
708 the stack pointer does not matter. The value is tested only in
709 functions that have frame pointers.
710 No definition is equivalent to always zero.
711
712 On the ARM, the function epilogue recovers the stack pointer from the
713 frame. */
714 #define EXIT_IGNORE_STACK 1
715
716 /* Generate the assembly code for function exit. */
717 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
718 output_epilogue ((STREAM), (SIZE))
719
720 /* Determine if the epilogue should be output as RTL.
721 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
722 #define USE_RETURN_INSN use_return_insn ()
723
724 /* Definitions for register eliminations.
725
726 This is an array of structures. Each structure initializes one pair
727 of eliminable registers. The "from" register number is given first,
728 followed by "to". Eliminations of the same "from" register are listed
729 in order of preference.
730
731 We have two registers that can be eliminated on the ARM. First, the
732 arg pointer register can often be eliminated in favor of the stack
733 pointer register. Secondly, the pseudo frame pointer register can always
734 be eliminated; it is replaced with either the stack or the real frame
735 pointer. */
736
737 #define ELIMINABLE_REGS \
738 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
739 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
740 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
741 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
742
743 /* Given FROM and TO register numbers, say whether this elimination is allowed.
744 Frame pointer elimination is automatically handled.
745
746 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
747 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
748 pointer, we must eliminate FRAME_POINTER_REGNUM into
749 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
750 #define CAN_ELIMINATE(FROM, TO) \
751 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
752
753 /* Define the offset between two registers, one to be eliminated, and the other
754 its replacement, at the start of a routine. */
755 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
756 { \
757 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
758 (OFFSET) = 0; \
759 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
760 (OFFSET) = (get_frame_size () + 3 & ~3); \
761 else \
762 { \
763 int regno; \
764 int offset = 12; \
765 \
766 for (regno = 4; regno <= 10; regno++) \
767 if (regs_ever_live[regno]) \
768 offset += 4; \
769 for (regno = 20; regno <=23; regno++) \
770 if (regs_ever_live[regno]) \
771 offset += 12; \
772 if ((FROM) == FRAME_POINTER_REGNUM) \
773 (OFFSET) = -offset; \
774 else \
775 { \
776 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
777 offset -= 16; \
778 if (regs_ever_live[14]) \
779 offset += 4; \
780 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
781 } \
782 } \
783 }
784
785 #if 0
786 /* Store in the variable DEPTH the initial difference between the frame
787 pointer reg contents and the stack pointer reg contents, as of the start of
788 the function body. This depends on the layout of the fixed parts of the
789 stack frame and on how registers are saved. */
790 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
791 { \
792 int regno; \
793 int offset = 12; \
794 \
795 for (regno = 0; regno < FRAME_POINTER_REGNUM; regno++) \
796 if (regs_ever_live[regno]) \
797 offset += 4; \
798 for (regno = 20; regno < 24; regno++) \
799 if (regs_ever_live[regno]) \
800 offset += 12; \
801 (DEPTH) = offset + (get_frame_size () + 3 & ~3); \
802 }
803
804 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
805 (DEPTH) = (get_frame_size () + 3) & ~3;
806 #endif
807 /* Output assembler code for a block containing the constant parts
808 of a trampoline, leaving space for the variable parts.
809
810 On the ARM, (if r8 is the static chain regnum, and remembering that
811 referencing pc adds an offset of 8) the trampoline looks like:
812 ldr r8, [pc, #0]
813 ldr pc, [pc]
814 .word static chain value
815 .word function's address */
816 #define TRAMPOLINE_TEMPLATE(FILE) \
817 { \
818 fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \
819 fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \
820 fprintf ((FILE), "\t.word\t0\n"); \
821 fprintf ((FILE), "\t.word\t0\n"); \
822 }
823
824 /* Length in units of the trampoline for entering a nested function. */
825 #define TRAMPOLINE_SIZE 16
826
827 /* Alignment required for a trampoline in units. */
828 #define TRAMPOLINE_ALIGN 4
829
830 /* Emit RTL insns to initialize the variable parts of a trampoline.
831 FNADDR is an RTX for the address of the function's pure code.
832 CXT is an RTX for the static chain value for the function. */
833 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
834 { \
835 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
836 (CXT)); \
837 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
838 (FNADDR)); \
839 }
840
841 /* Call the function profiler with a given profile label. The Acorn compiler
842 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
843 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
844 to mind about this! */
845 #define FUNCTION_PROFILER(STREAM,LABELNO) \
846 { \
847 fprintf(STREAM, "\tmov\tip, lr\n"); \
848 fprintf(STREAM, "\tbl\tmcount\n"); \
849 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
850 arm_increase_location (12); \
851 }
852 \f
853 /* Addressing modes, and classification of registers for them. */
854
855 #define HAVE_POST_INCREMENT 1
856 #define HAVE_PRE_INCREMENT 1
857 #define HAVE_POST_DECREMENT 1
858 #define HAVE_PRE_DECREMENT 1
859
860 /* Macros to check register numbers against specific register classes. */
861
862 /* These assume that REGNO is a hard or pseudo reg number.
863 They give nonzero only if REGNO is a hard reg of the suitable class
864 or a pseudo reg currently allocated to a suitable hard reg.
865 Since they use reg_renumber, they are safe only once reg_renumber
866 has been allocated, which happens in local-alloc.c.
867
868 On the ARM, don't allow the pc to be used. */
869 #define REGNO_OK_FOR_BASE_P(REGNO) \
870 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
871 || (REGNO) == ARG_POINTER_REGNUM \
872 || (unsigned) reg_renumber[(REGNO)] < 15 \
873 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
874 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
875 #define REGNO_OK_FOR_INDEX_P(REGNO) \
876 REGNO_OK_FOR_BASE_P(REGNO)
877
878 /* Maximum number of registers that can appear in a valid memory address.
879 Shifts in addresses can't be by a register. */
880
881 #define MAX_REGS_PER_ADDRESS 2
882
883 /* Recognize any constant value that is a valid address. */
884 /* XXX We can address any constant, eventually... */
885 #if 0
886 #define CONSTANT_ADDRESS_P(X) \
887 ( GET_CODE(X) == LABEL_REF \
888 || GET_CODE(X) == SYMBOL_REF \
889 || GET_CODE(X) == CONST_INT \
890 || GET_CODE(X) == CONST )
891 #endif
892
893 #define CONSTANT_ADDRESS_P(X) \
894 (GET_CODE (X) == SYMBOL_REF \
895 && (CONSTANT_POOL_ADDRESS_P (X) || SYMBOL_REF_FLAG (X)))
896
897 /* Nonzero if the constant value X is a legitimate general operand.
898 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
899
900 On the ARM, allow any integer (invalid ones are removed later by insn
901 patterns), nice doubles and symbol_refs which refer to the function's
902 constant pool XXX. */
903 #define LEGITIMATE_CONSTANT_P(X) \
904 (GET_CODE (X) == CONST_INT \
905 || (GET_CODE (X) == CONST_DOUBLE \
906 && (const_double_rtx_ok_for_fpu (X) \
907 || neg_const_double_rtx_ok_for_fpu (X))) \
908 || CONSTANT_ADDRESS_P (X))
909
910 /* Symbols in the text segment can be accessed without indirecting via the
911 constant pool; it may take an extra binary operation, but this is still
912 faster than indirecting via memory. */
913
914 #define ENCODE_SECTION_INFO(decl) \
915 { \
916 if (TREE_CONSTANT (decl) \
917 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
918 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 1; \
919 }
920
921 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
922 and check its validity for a certain class.
923 We have two alternate definitions for each of them.
924 The usual definition accepts all pseudo regs; the other rejects
925 them unless they have been allocated suitable hard regs.
926 The symbol REG_OK_STRICT causes the latter definition to be used. */
927 #ifndef REG_OK_STRICT
928
929 /* Nonzero if X is a hard reg that can be used as a base reg
930 or if it is a pseudo reg. */
931 #define REG_OK_FOR_BASE_P(X) \
932 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
933 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
934
935 /* Nonzero if X is a hard reg that can be used as an index
936 or if it is a pseudo reg. */
937 #define REG_OK_FOR_INDEX_P(X) \
938 REG_OK_FOR_BASE_P(X)
939
940 #define REG_OK_FOR_PRE_POST_P(X) \
941 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
942 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
943
944 #else
945
946 /* Nonzero if X is a hard reg that can be used as a base reg. */
947 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
948
949 /* Nonzero if X is a hard reg that can be used as an index. */
950 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
951
952 #define REG_OK_FOR_PRE_POST_P(X) \
953 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
954 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
955 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
956 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
957
958 #endif
959 \f
960 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
961 that is a valid memory address for an instruction.
962 The MODE argument is the machine mode for the MEM expression
963 that wants to use this address.
964
965 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
966 #define BASE_REGISTER_RTX_P(X) \
967 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
968
969 #define INDEX_REGISTER_RTX_P(X) \
970 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
971
972 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
973 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
974 only be small constants. */
975 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
976 do \
977 { \
978 int range; \
979 int code = GET_CODE (INDEX); \
980 \
981 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
982 { \
983 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
984 && INTVAL (INDEX) > -1024 \
985 && (INTVAL (INDEX) & 3) == 0) \
986 goto LABEL; \
987 } \
988 else \
989 { \
990 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
991 goto LABEL; \
992 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
993 { \
994 rtx xiop0 = XEXP (INDEX, 0); \
995 rtx xiop1 = XEXP (INDEX, 1); \
996 if (INDEX_REGISTER_RTX_P (xiop0) \
997 && power_of_two_operand (xiop1, SImode)) \
998 goto LABEL; \
999 if (INDEX_REGISTER_RTX_P (xiop1) \
1000 && power_of_two_operand (xiop0, SImode)) \
1001 goto LABEL; \
1002 } \
1003 if (GET_MODE_SIZE (MODE) <= 4 \
1004 && (code == LSHIFTRT || code == ASHIFTRT || code == LSHIFT \
1005 || code == ASHIFT || code == ROTATERT)) \
1006 { \
1007 rtx op = XEXP (INDEX, 1); \
1008 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1009 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1010 && INTVAL (op) <= 31) \
1011 goto LABEL; \
1012 } \
1013 range = (MODE) == HImode ? 4095 : 4096; \
1014 if (code == CONST_INT && INTVAL (INDEX) < range \
1015 && INTVAL (INDEX) > -range) \
1016 goto LABEL; \
1017 } \
1018 } while (0)
1019
1020 /* Jump to LABEL if X is a valid address RTX. This must also take
1021 REG_OK_STRICT into account when deciding about valid registers, but it uses
1022 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1023 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1024 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1025 refs must be forced though a static cell to ensure addressability. */
1026 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1027 { \
1028 if (BASE_REGISTER_RTX_P (X)) \
1029 goto LABEL; \
1030 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1031 && GET_CODE (XEXP (X, 0)) == REG \
1032 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1033 goto LABEL; \
1034 else if ((MODE) == TImode) \
1035 ; \
1036 else if (GET_CODE (X) == PLUS) \
1037 { \
1038 rtx xop0 = XEXP(X,0); \
1039 rtx xop1 = XEXP(X,1); \
1040 \
1041 if (BASE_REGISTER_RTX_P (xop0)) \
1042 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1043 else if (BASE_REGISTER_RTX_P (xop1)) \
1044 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1045 } \
1046 else if (GET_CODE (X) == MINUS) \
1047 { \
1048 rtx xop0 = XEXP (X,0); \
1049 rtx xop1 = XEXP (X,1); \
1050 \
1051 if (BASE_REGISTER_RTX_P (xop0)) \
1052 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1053 } \
1054 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1055 && GET_CODE (X) == SYMBOL_REF \
1056 && CONSTANT_POOL_ADDRESS_P (X)) \
1057 goto LABEL; \
1058 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1059 && GET_CODE (XEXP (X, 0)) == REG \
1060 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1061 goto LABEL; \
1062 }
1063 \f
1064 /* Try machine-dependent ways of modifying an illegitimate address
1065 to be legitimate. If we find one, return the new, valid address.
1066 This macro is used in only one place: `memory_address' in explow.c.
1067
1068 OLDX is the address as it was before break_out_memory_refs was called.
1069 In some cases it is useful to look at this to decide what needs to be done.
1070
1071 MODE and WIN are passed so that this macro can use
1072 GO_IF_LEGITIMATE_ADDRESS.
1073
1074 It is always safe for this macro to do nothing. It exists to recognize
1075 opportunities to optimize the output.
1076
1077 On the ARM, try to convert [REG, #BIGCONST]
1078 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1079 where VALIDCONST == 0 in case of TImode. */
1080 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1081 { \
1082 if (GET_CODE (X) == PLUS) \
1083 { \
1084 rtx xop0 = XEXP (X, 0); \
1085 rtx xop1 = XEXP (X, 1); \
1086 \
1087 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1088 { \
1089 int n = INTVAL (xop1); \
1090 int low_n = ((MODE) == TImode ? 0 \
1091 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1092 rtx base_reg = gen_reg_rtx (SImode); \
1093 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1094 gen_rtx (CONST_INT, \
1095 VOIDmode, n - low_n)), \
1096 0); \
1097 emit_move_insn (base_reg, val); \
1098 (X) = (low_n == 0 ? base_reg \
1099 : gen_rtx (PLUS, SImode, base_reg, \
1100 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1101 } \
1102 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1103 { \
1104 int n = INTVAL (xop0); \
1105 int low_n = ((MODE) == TImode ? 0 \
1106 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1107 rtx base_reg = gen_reg_rtx (SImode); \
1108 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1109 gen_rtx (CONST_INT, \
1110 VOIDmode, n - low_n)), \
1111 0); \
1112 emit_move_insn (base_reg, val); \
1113 (X) = (low_n == 0 ? base_reg \
1114 : gen_rtx (PLUS, SImode, base_reg, \
1115 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1116 } \
1117 } \
1118 if (memory_address_p (MODE, X)) \
1119 goto win; \
1120 }
1121
1122 /* Go to LABEL if ADDR (a legitimate address expression)
1123 has an effect that depends on the machine mode it is used for. */
1124 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1125 { \
1126 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1127 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1128 goto LABEL; \
1129 }
1130 \f
1131 /* Specify the machine mode that this machine uses
1132 for the index in the tablejump instruction. */
1133 #define CASE_VECTOR_MODE SImode
1134
1135 /* Define this if the tablejump instruction expects the table
1136 to contain offsets from the address of the table.
1137 Do not define this if the table should contain absolute addresses. */
1138 /* #define CASE_VECTOR_PC_RELATIVE */
1139
1140 /* Specify the tree operation to be used to convert reals to integers. */
1141 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1142
1143 /* This is the kind of divide that is easiest to do in the general case. */
1144 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1145
1146 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1147 unsigned is probably best, but may break some code. */
1148 #ifndef DEFAULT_SIGNED_CHAR
1149 #define DEFAULT_SIGNED_CHAR 1
1150 #endif
1151
1152 /* Don't cse the address of the function being compiled. */
1153 #define NO_RECURSIVE_FUNCTION_CSE 1
1154
1155 /* Max number of bytes we can move from memory to memory
1156 in one reasonably fast instruction. */
1157 #define MOVE_MAX 4
1158
1159 /* Define if operations between registers always perform the operation
1160 on the full register even if a narrower mode is specified. */
1161 #define WORD_REGISTER_OPERATIONS
1162
1163 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1164 will either zero-extend or sign-extend. The value of this macro should
1165 be the code that says which one of the two operations is implicitly
1166 done, NIL if none. */
1167 #define LOAD_EXTEND_OP(MODE) \
1168 ((MODE) == QImode ? ZERO_EXTEND : NIL)
1169
1170 /* Define this if zero-extension is slow (more than one real instruction).
1171 On the ARM, it is more than one instruction only if not fetching from
1172 memory. */
1173 /* #define SLOW_ZERO_EXTEND */
1174
1175 /* Nonzero if access to memory by bytes is slow and undesirable. */
1176 #define SLOW_BYTE_ACCESS 0
1177
1178 /* Immediate shift counts are truncated by the output routines (or was it
1179 the assembler?). Shift counts in a register are truncated by ARM. Note
1180 that the native compiler puts too large (> 32) immediate shift counts
1181 into a register and shifts by the register, letting the ARM decide what
1182 to do instead of doing that itself. */
1183 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1184 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1185 On the arm, Y in a register is used modulo 256 for the shift. Only for
1186 rotates is modulo 32 used. */
1187 /* #define SHIFT_COUNT_TRUNCATED 1 */
1188
1189 /* XX This is not true, is it? */
1190 /* All integers have the same format so truncation is easy. */
1191 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1192
1193 /* Calling from registers is a massive pain. */
1194 #define NO_FUNCTION_CSE 1
1195
1196 /* Chars and shorts should be passed as ints. */
1197 #define PROMOTE_PROTOTYPES 1
1198
1199 /* The machine modes of pointers and functions */
1200 #define Pmode SImode
1201 #define FUNCTION_MODE Pmode
1202
1203 /* The structure type of the machine dependent info field of insns
1204 No uses for this yet. */
1205 /* #define INSN_MACHINE_INFO struct machine_info */
1206
1207 /* The relative costs of various types of constants. Note that cse.c defines
1208 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1209 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1210 case CONST_INT: \
1211 if (const_ok_for_arm (INTVAL (RTX))) \
1212 return (OUTER_CODE) == SET ? 2 : -1; \
1213 else if (OUTER_CODE == AND \
1214 && const_ok_for_arm (~INTVAL (RTX))) \
1215 return -1; \
1216 else if ((OUTER_CODE == COMPARE \
1217 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1218 && const_ok_for_arm (-INTVAL (RTX))) \
1219 return -1; \
1220 else \
1221 return 5; \
1222 case CONST: \
1223 case LABEL_REF: \
1224 case SYMBOL_REF: \
1225 return 6; \
1226 case CONST_DOUBLE: \
1227 if (const_double_rtx_ok_for_fpu (RTX)) \
1228 return (OUTER_CODE) == SET ? 2 : -1; \
1229 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1230 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1231 return -1; \
1232 return(7);
1233
1234 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1235 case MEM: \
1236 { \
1237 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1238 return (COSTS_N_INSNS (10*num_words)); \
1239 } \
1240 case MULT: \
1241 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1242 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1243 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1244 return COSTS_N_INSNS (9); \
1245 case LSHIFT: \
1246 case ASHIFT: \
1247 case LSHIFTRT: \
1248 case ASHIFTRT: \
1249 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1250 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1251 break; \
1252 case MINUS: \
1253 { \
1254 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1255 if (code == MULT) \
1256 { \
1257 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1258 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1259 return COSTS_N_INSNS (1); \
1260 break; \
1261 } \
1262 else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \
1263 || code == LSHIFTRT) \
1264 return COSTS_N_INSNS (1); \
1265 } /* fall through */ \
1266 case PLUS: \
1267 case IOR: \
1268 case XOR: \
1269 case AND: \
1270 { \
1271 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1272 if (code == MULT) \
1273 { \
1274 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1275 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1276 return COSTS_N_INSNS (1); \
1277 if (GET_CODE (X) == PLUS) \
1278 return COSTS_N_INSNS (12); \
1279 break; \
1280 } \
1281 else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \
1282 || code == LSHIFTRT) \
1283 return COSTS_N_INSNS (1); \
1284 break; \
1285 } \
1286 case NOT: \
1287 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1288 case IF_THEN_ELSE: \
1289 { \
1290 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1291 return COSTS_N_INSNS (4); \
1292 return COSTS_N_INSNS (1); \
1293 } \
1294 case SIGN_EXTEND: \
1295 return COSTS_N_INSNS (2); \
1296 case ZERO_EXTEND: \
1297 if (GET_MODE (XEXP (X, 0)) == QImode) \
1298 { \
1299 if (GET_CODE (XEXP (X, 0)) == MEM) \
1300 return COSTS_N_INSNS (10); \
1301 return COSTS_N_INSNS (1); \
1302 } \
1303 break; \
1304 case COMPARE: \
1305 if (GET_CODE (XEXP (X, 1)) == REG) \
1306 return 4; \
1307 case SMIN: \
1308 case SMAX: \
1309 case UMIN: \
1310 case UMAX: \
1311 return COSTS_N_INSNS (3); \
1312 case ABS: \
1313 if (GET_MODE (X) == SImode) \
1314 return COSTS_N_INSNS (2); \
1315 return COSTS_N_INSNS (1);
1316
1317 /* Moves to and from memory are quite expensive */
1318 #define MEMORY_MOVE_COST(MODE) 10
1319
1320 /* All address computations that can be done are free */
1321 #define ADDRESS_COST(x) 2
1322
1323 /* Try to generate sequences that don't involve branches, we can then use
1324 conditional instructions */
1325 #define BRANCH_COST 4
1326 \f
1327 /* Condition code information. */
1328 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1329 return the mode to be used for the comparison.
1330 CCFPEmode should be used with floating inequalites,
1331 CCFPmode should be used with floating equalities.
1332 CC_NOOVmode should be used with SImode integer equalites
1333 CCmode should be used otherwise. */
1334
1335 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1336
1337 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1338
1339 #define SELECT_CC_MODE(OP,X,Y) \
1340 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1341 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1342 : ((GET_MODE (X) == SImode) \
1343 && ((OP) == EQ || (OP) == NE) \
1344 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1345 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1346 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1347 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1348 || GET_CODE (X) == LSHIFT || GET_CODE (X) == LSHIFTRT \
1349 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1350 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1351 ? CC_NOOVmode \
1352 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1353
1354 #define STORE_FLAG_VALUE 1
1355
1356 /* Define the information needed to generate branch insns. This is
1357 stored from the compare operation. Note that we can't use "rtx" here
1358 since it hasn't been defined! */
1359
1360 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1361 extern int arm_compare_fp;
1362
1363 /* Define the codes that are matched by predicates in arm.c */
1364 #define PREDICATE_CODES \
1365 {"s_register_operand", {SUBREG, REG}}, \
1366 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1367 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1368 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1369 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1370 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1371 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1372 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1373 {"shift_operator", {ASHIFT, LSHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
1374 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1375 {"load_multiple_operation", {PARALLEL}}, \
1376 {"store_multiple_operation", {PARALLEL}}, \
1377 {"equality_operator", {EQ, NE}}, \
1378 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1379 {"const_shift_operand", {CONST_INT}}, \
1380 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1381 {"cc_register", {REG}},
1382
1383 \f
1384 /* Assembler output control */
1385
1386 #ifndef ARM_OS_NAME
1387 #define ARM_OS_NAME "(generic)"
1388 #endif
1389
1390 /* The text to go at the start of the assembler file */
1391 #define ASM_FILE_START(STREAM) \
1392 { \
1393 extern char *version_string; \
1394 \
1395 fprintf (STREAM,"@ Generated by gcc %s for ARM/%s\n", version_string, \
1396 ARM_OS_NAME); \
1397 fprintf (STREAM,"rfp\t.req\tr9\n"); \
1398 fprintf (STREAM,"fp\t.req\tr11\n"); \
1399 fprintf (STREAM,"ip\t.req\tr12\n"); \
1400 fprintf (STREAM,"sp\t.req\tr13\n"); \
1401 fprintf (STREAM,"lr\t.req\tr14\n"); \
1402 fprintf (STREAM,"pc\t.req\tr15\n"); \
1403 }
1404
1405 #define ASM_APP_ON ""
1406 #define ASM_APP_OFF ""
1407
1408 /* Switch to the text or data segment. */
1409 #define TEXT_SECTION_ASM_OP ".text"
1410 #define DATA_SECTION_ASM_OP ".data"
1411
1412 /* The assembler's names for the registers. RFP need not always be used as
1413 the Real framepointer; it can also be used as a normal general register.
1414 Note that the name `fp' is horribly misleading since `fp' is in fact only
1415 the argument-and-return-context pointer. */
1416 #define REGISTER_NAMES \
1417 { \
1418 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1419 "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \
1420 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1421 "cc", "sfp", "afp" \
1422 }
1423
1424 /* Arm Assembler barfs on dollars */
1425 #define DOLLARS_IN_IDENTIFIERS 0
1426
1427 #define NO_DOLLAR_IN_LABEL
1428
1429 /* DBX register number for a given compiler register number */
1430 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1431
1432 /* Generate DBX debugging information. riscix.h will undefine this because
1433 the native assembler does not support stabs. */
1434 #define DBX_DEBUGGING_INFO 1
1435
1436 /* Acorn dbx moans about continuation chars, so don't use any. */
1437 #define DBX_CONTIN_LENGTH 0
1438
1439 /* Output a source filename for the debugger. RISCiX dbx insists that the
1440 ``desc'' field is set to compiler version number >= 315 (sic). */
1441 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1442 do { \
1443 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1444 &ltext_label_name[1]); \
1445 text_section (); \
1446 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1447 } while (0)
1448
1449 /* Output a label definition. */
1450 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1451 arm_asm_output_label ((STREAM), (NAME))
1452
1453 /* Output a function label definition. */
1454 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1455 ASM_OUTPUT_LABEL(STREAM, NAME)
1456
1457 /* Output a globalising directive for a label. */
1458 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1459 (fprintf (STREAM, "\t.global\t"), \
1460 assemble_name (STREAM, NAME), \
1461 fputc ('\n',STREAM)) \
1462
1463 /* Output a reference to a label. */
1464 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1465 fprintf (STREAM, "_%s", NAME)
1466
1467 /* Make an internal label into a string. */
1468 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1469 sprintf (STRING, "*%s%d", PREFIX, NUM)
1470
1471 /* Output an internal label definition. */
1472 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1473 do \
1474 { \
1475 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1476 extern int arm_target_label, arm_ccfsm_state; \
1477 \
1478 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1479 && !strcmp (PREFIX, "L")) \
1480 { \
1481 arm_ccfsm_state = 0; \
1482 } \
1483 strcpy (s, "*"); \
1484 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1485 arm_asm_output_label (STREAM, s); \
1486 } while (0)
1487
1488 /* Nothing special is done about jump tables */
1489 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1490 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1491
1492 /* Construct a private name. */
1493 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1494 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1495 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1496
1497 /* Output a push or a pop instruction (only used when profiling). */
1498 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1499 (arm_increase_location (4) \
1500 , fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO]))
1501
1502 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1503 (arm_increase_location (4) \
1504 , fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO]))
1505
1506 /* Output a relative address. Not needed since jump tables are absolute
1507 but we must define it anyway. */
1508 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1509 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1510
1511 /* Output an element of a dispatch table. */
1512 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1513 (arm_increase_location (4) \
1514 , fprintf (STREAM, "\t.word\tL%d\n", VALUE))
1515
1516 /* Output various types of constants. */
1517 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1518 do { long l[3]; \
1519 arm_increase_location (12); \
1520 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1521 if (sizeof (int) == sizeof (long)) \
1522 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\n", l[2], l[1], l[0]); \
1523 else \
1524 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\n", l[2], l[1], l[0]); \
1525 } while (0)
1526
1527
1528 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1529 do { char dstr[30]; \
1530 arm_increase_location (8); \
1531 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1532 fprintf (STREAM, "\t.double %s\n", dstr); \
1533 } while (0)
1534
1535 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1536 do { char dstr[30]; \
1537 arm_increase_location (4); \
1538 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1539 fprintf (STREAM, "\t.float %s\n", dstr); \
1540 } while (0);
1541
1542 #define ASM_OUTPUT_INT(STREAM, EXP) \
1543 (fprintf (STREAM, "\t.word\t"), \
1544 output_addr_const (STREAM, (EXP)), \
1545 arm_increase_location (4), \
1546 fputc ('\n', STREAM))
1547
1548 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1549 (fprintf (STREAM, "\t.short\t"), \
1550 output_addr_const (STREAM, (EXP)), \
1551 arm_increase_location (2), \
1552 fputc ('\n', STREAM))
1553
1554 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1555 (fprintf (STREAM, "\t.byte\t"), \
1556 output_addr_const (STREAM, (EXP)), \
1557 arm_increase_location (1), \
1558 fputc ('\n', STREAM))
1559
1560 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1561 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1562 arm_increase_location (1))
1563
1564 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1565 output_ascii_pseudo_op ((STREAM), (PTR), (LEN))
1566
1567 /* Output a gap. In fact we fill it with nulls. */
1568 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1569 (arm_increase_location (NBYTES), \
1570 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1571
1572 /* Align output to a power of two. Horrible /bin/as. */
1573 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1574 do \
1575 { \
1576 register int amount = 1 << (POWER); \
1577 extern int arm_text_location; \
1578 \
1579 if (amount == 2) \
1580 fprintf (STREAM, "\t.even\n"); \
1581 else \
1582 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1583 \
1584 if (in_text_section ()) \
1585 arm_text_location = ((arm_text_location + amount - 1) \
1586 & ~(amount - 1)); \
1587 } while (0)
1588
1589 /* Output a common block */
1590 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1591 (fprintf (STREAM, "\t.comm\t"), \
1592 assemble_name ((STREAM), (NAME)), \
1593 fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE))
1594
1595 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1596 the bss segment. Note that this is *bad* practice. */
1597 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1598 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1599
1600 /* Output a source filename for the debugger. RISCiX dbx insists that the
1601 ``desc'' field is set to compiler version number >= 315 (sic). */
1602 #if 0
1603 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \
1604 fprintf (STREAM, "\t.stabs\t\"%s\", %d, 0, 315, Ltext\n", (NAME), N_SOL)
1605 #endif
1606
1607 /* Output a source line for the debugger. */
1608 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1609
1610 /* Output a #ident directive. */
1611 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1612 fprintf (STREAM,"- - - ident %s\n",STRING)
1613
1614 /* The assembler's parentheses characters. */
1615 #define ASM_OPEN_PAREN "("
1616 #define ASM_CLOSE_PAREN ")"
1617
1618 /* Target characters. */
1619 #define TARGET_BELL 007
1620 #define TARGET_BS 010
1621 #define TARGET_TAB 011
1622 #define TARGET_NEWLINE 012
1623 #define TARGET_VT 013
1624 #define TARGET_FF 014
1625 #define TARGET_CR 015
1626 \f
1627 /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete
1628 small-distance conditional branches and have ASM_OUTPUT_OPCODE make the
1629 instructions conditional. Suffixes like s (affect flags) and b (bytewise
1630 load/store) need to stay suffixes, so the possible condition code comes
1631 before these suffixes. %d<n> or %D<n> may appear in the opcode if
1632 it can take a condition; a null rtx will cause no condition to be added,
1633 this is what we expect to happen if arm_ccfsm_state is non-zero. */
1634 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1635 { \
1636 extern int arm_ccfsm_state, arm_current_cc; \
1637 extern char *arm_condition_codes[]; \
1638 int i; \
1639 \
1640 fflush (STREAM); /* XXX for debugging only. */ \
1641 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \
1642 { \
1643 for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%' && i < 3;\
1644 i++, (PTR)++) \
1645 putc (*(PTR), STREAM); \
1646 fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \
1647 for (; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%'; (PTR)++) \
1648 putc (*(PTR), STREAM); \
1649 } \
1650 }
1651
1652 /* Only perform branch elimination (by making instructions conditional) if
1653 we're optimising. Otherwise it's of no use anyway. */
1654 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1655 if (optimize) \
1656 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1657
1658 /* Output an operand of an instruction. If X is a REG and CODE is `M', output
1659 a ldm/stm style multi-reg. */
1660 #define PRINT_OPERAND(STREAM, X, CODE) \
1661 { \
1662 if ((CODE) == 'd') \
1663 { \
1664 if (X) \
1665 fputs (arm_condition_codes[get_arm_condition_code (X)], \
1666 (STREAM)); \
1667 } \
1668 else if ((CODE) == 'D') \
1669 { \
1670 if (X) \
1671 fputs (arm_condition_codes[get_arm_condition_code (X) ^ 1], \
1672 (STREAM)); \
1673 } \
1674 else if ((CODE) == 'R') \
1675 fputs (reg_names[REGNO (X) + 1], (STREAM)); \
1676 else if (GET_CODE (X) == REG) \
1677 { \
1678 if ((CODE) != 'M') \
1679 fputs (reg_names[REGNO (X)], (STREAM)); \
1680 else \
1681 fprintf ((STREAM), "{%s-%s}", \
1682 reg_names[REGNO (X)], \
1683 reg_names[REGNO (X) - 1 \
1684 + ((GET_MODE_SIZE (GET_MODE (X)) \
1685 + GET_MODE_SIZE (SImode) - 1) \
1686 / GET_MODE_SIZE (SImode))]); \
1687 } \
1688 else if (GET_CODE (X) == MEM) \
1689 { \
1690 extern int output_memory_reference_mode; \
1691 output_memory_reference_mode = GET_MODE (X); \
1692 output_address (XEXP (X, 0)); \
1693 } \
1694 else if (GET_CODE(X) == CONST_DOUBLE) \
1695 { \
1696 union real_extract u; \
1697 u.i[0] = CONST_DOUBLE_LOW (X); \
1698 u.i[1] = CONST_DOUBLE_HIGH (X); \
1699 fprintf(STREAM,"#%s", fp_immediate_constant(X)); \
1700 } \
1701 else if (GET_CODE (X) == NEG) \
1702 { \
1703 fputc ('-', (STREAM)); \
1704 output_operand ((X), 0); \
1705 } \
1706 else \
1707 { \
1708 fputc('#', STREAM); \
1709 output_addr_const(STREAM, X); \
1710 } \
1711 }
1712
1713 /* Output the address of an operand. */
1714 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1715 { \
1716 int is_minus = GET_CODE (X) == MINUS; \
1717 \
1718 if (GET_CODE (X) == REG) \
1719 fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \
1720 else if (GET_CODE (X) == PLUS || is_minus) \
1721 { \
1722 rtx base = XEXP (X, 0); \
1723 rtx index = XEXP (X, 1); \
1724 char *base_reg_name; \
1725 int offset = 0; \
1726 int shift; \
1727 if (GET_CODE (base) != REG) \
1728 { \
1729 /* Ensure that BASE is a register (one of them must be). */ \
1730 rtx temp = base; \
1731 base = index; \
1732 index = temp; \
1733 } \
1734 base_reg_name = reg_names[REGNO (base)]; \
1735 switch (GET_CODE (index)) \
1736 { \
1737 case CONST_INT: \
1738 offset = INTVAL (index); \
1739 if (is_minus) \
1740 offset = -offset; \
1741 fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \
1742 break; \
1743 \
1744 case REG: \
1745 fprintf (STREAM, "[%s, %s%s]", base_reg_name, \
1746 is_minus ? "-" : "", reg_names[REGNO (index)] ); \
1747 break; \
1748 \
1749 case MULT: \
1750 if (GET_CODE (XEXP (index,0)) == CONST_INT) \
1751 { \
1752 shift = int_log2 (INTVAL (XEXP (index, 0))); \
1753 index = XEXP (index, 1); \
1754 } \
1755 else if (GET_CODE(XEXP(index,1)) == CONST_INT) \
1756 { \
1757 shift = int_log2 (INTVAL (XEXP (index, 1))); \
1758 index = XEXP (index, 0); \
1759 } \
1760 else \
1761 abort(); \
1762 fprintf (STREAM, "[%s, %s%s, asl #%d]", base_reg_name, \
1763 is_minus ? "-" : "", reg_names[REGNO (index)], \
1764 shift); \
1765 break; \
1766 case ASHIFTRT: \
1767 case LSHIFTRT: \
1768 case ASHIFT: \
1769 case LSHIFT: \
1770 case ROTATERT: \
1771 { \
1772 char *shift_type = shift_instr (GET_CODE (index), \
1773 &XEXP (index, 1)); \
1774 shift = INTVAL (XEXP (index, 1)); \
1775 index = XEXP (index, 0); \
1776 fprintf (STREAM, "[%s, %s%s, %s #%d]", base_reg_name, \
1777 is_minus ? "-" : "", reg_names[REGNO (index)], \
1778 shift_type, shift); \
1779 break; \
1780 } \
1781 \
1782 default: \
1783 abort(); \
1784 } \
1785 } \
1786 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1787 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1788 { \
1789 extern int output_memory_reference_mode; \
1790 \
1791 if (GET_CODE (XEXP (X, 0)) != REG) \
1792 abort (); \
1793 \
1794 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1795 fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\
1796 GET_CODE (X) == PRE_DEC ? "-" : "", \
1797 GET_MODE_SIZE (output_memory_reference_mode)); \
1798 else \
1799 fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \
1800 GET_CODE (X) == POST_DEC ? "-" : "", \
1801 GET_MODE_SIZE (output_memory_reference_mode)); \
1802 } \
1803 else output_addr_const(STREAM, X); \
1804 }
1805
1806 /* EOF arm.h */
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