| blob | 8f1ace8f1c453d8ce80381ba25b81c7e41869dde |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
306 rtx *);
367 {
368 rtx match;
369 rtx replacement;
370 rtx insn;
373 /* Nonzero iff INSN is between START and END, inclusive. */
374 #define INSN_IN_RANGE_P(INSN, START, END) \
375 (INSN_UID (INSN) < max_uid_for_loop \
376 && INSN_LUID (INSN) >= INSN_LUID (START) \
377 && INSN_LUID (INSN) <= INSN_LUID (END))
379 /* Indirect_jump_in_function is computed once per function. */
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
412 {
414 rtx insn;
417 {
420 /* Don't assign luids to line-number NOTEs, so that the distance in
421 luids between two insns is not affected by -g. */
425 else
426 /* Give a line number note the same luid as preceding insn. */
428 }
430 }
431 \f
432 /* Entry point of this file. Perform loop optimization
433 on the current function. F is the first insn of the function
434 and DUMPFILE is a stream for output of a trace of actions taken
435 (or 0 if none should be output). */
437 void
439 {
440 rtx insn;
455 /* Count the number of loops. */
459 {
462 max_loop_num++;
463 }
465 /* Don't waste time if no loops. */
471 /* Get size to use for tables indexed by uids.
472 Leave some space for labels allocated by find_and_verify_loops. */
478 /* Allocate storage for array of loops. */
481 /* Find and process each loop.
482 First, find them, and record them in order of their beginnings. */
485 /* Allocate and initialize auxiliary loop information. */
490 /* Now find all register lifetimes. This must be done after
491 find_and_verify_loops, because it might reorder the insns in the
492 function. */
495 /* This must occur after reg_scan so that registers created by gcse
496 will have entries in the register tables.
498 We could have added a call to reg_scan after gcse_main in toplev.c,
499 but moving this call to init_alias_analysis is more efficient. */
502 /* See if we went too far. Note that get_max_uid already returns
503 one more that the maximum uid of all insn. */
506 /* Now reset it to the actual size we need. See above. */
509 /* find_and_verify_loops has already called compute_luids, but it
510 might have rearranged code afterwards, so we need to recompute
511 the luids now. */
514 /* Don't leave gaps in uid_luid for insns that have been
515 deleted. It is possible that the first or last insn
516 using some register has been deleted by cross-jumping.
517 Make sure that uid_luid for that former insn's uid
518 points to the general area where that insn used to be. */
520 {
524 }
529 /* Determine if the function has indirect jump. On some systems
530 this prevents low overhead loop instructions from being used. */
533 /* Now scan the loops, last ones first, since this means inner ones are done
534 before outer ones. */
536 {
540 {
543 }
544 }
548 /* Clean up. */
556 }
557 \f
558 /* Returns the next insn, in execution order, after INSN. START and
559 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
560 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
561 insn-stream; it is used with loops that are entered near the
562 bottom. */
564 static rtx
566 {
570 {
572 /* Go to the top of the loop, and continue there. */
574 else
575 /* We're done. */
577 }
580 /* We're done. */
584 }
586 /* Find any register references hidden inside X and add them to
587 the dependency list DEPS. This is used to look inside CLOBBER (MEM
588 when checking whether a PARALLEL can be pulled out of a loop. */
590 static rtx
592 {
596 else
597 {
601 {
607 }
608 }
610 }
612 /* Optimize one loop described by LOOP. */
614 /* ??? Could also move memory writes out of loops if the destination address
615 is invariant, the source is invariant, the memory write is not volatile,
616 and if we can prove that no read inside the loop can read this address
617 before the write occurs. If there is a read of this address after the
618 write, then we can also mark the memory read as invariant. */
620 static void
622 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
654 /* Determine whether this loop starts with a jump down to a test at
655 the end. This will occur for a small number of loops with a test
656 that is too complex to duplicate in front of the loop.
658 We search for the first insn or label in the loop, skipping NOTEs.
659 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
660 (because we might have a loop executed only once that contains a
661 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
662 (in case we have a degenerate loop).
664 Note that if we mistakenly think that a loop is entered at the top
665 when, in fact, it is entered at the exit test, the only effect will be
666 slightly poorer optimization. Making the opposite error can generate
667 incorrect code. Since very few loops now start with a jump to the
668 exit test, the code here to detect that case is very conservative. */
671 p != loop_end
677 ;
681 /* If loop end is the end of the current function, then emit a
682 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
683 note insn. This is the position we use when sinking insns out of
684 the loop. */
687 else
690 /* Set up variables describing this loop. */
694 /* If loop has a jump before the first label,
695 the true entry is the target of that jump.
696 Start scan from there.
697 But record in LOOP->TOP the place where the end-test jumps
698 back to so we can scan that after the end of the loop. */
700 /* Loop entry must be unconditional jump (and not a RETURN) */
703 /* Check to see whether the jump actually
704 jumps out of the loop (meaning it's no loop).
705 This case can happen for things like
706 do {..} while (0). If this label was generated previously
707 by loop, we can't tell anything about it and have to reject
708 the loop. */
710 {
713 }
715 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
716 as required by loop_reg_used_before_p. So skip such loops. (This
717 test may never be true, but it's best to play it safe.)
719 Also, skip loops where we do not start scanning at a label. This
720 test also rejects loops starting with a JUMP_INSN that failed the
721 test above. */
725 {
730 }
732 /* Allocate extra space for REGs that might be created by load_mems.
733 We allocate a little extra slop as well, in the hopes that we
734 won't have to reallocate the regs array. */
742 /* Scan through the loop finding insns that are safe to move.
743 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
744 this reg will be considered invariant for subsequent insns.
745 We consider whether subsequent insns use the reg
746 in deciding whether it is worth actually moving.
748 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
749 and therefore it is possible that the insns we are scanning
750 would never be executed. At such times, we must make sure
751 that it is safe to execute the insn once instead of zero times.
752 When MAYBE_NEVER is 0, all insns will be executed at least once
753 so that is not a problem. */
758 {
760 in_libcall--;
762 {
765 in_libcall++;
769 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
771 #endif
773 {
781 /* Figure out what to use as a source of this insn. If a
782 REG_EQUIV note is given or if a REG_EQUAL note with a
783 constant operand is specified, use it as the source and
784 mark that we should move this insn by calling
785 emit_move_insn rather that duplicating the insn.
787 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
788 note is present. */
792 else
793 {
798 {
800 /* A libcall block can use regs that don't appear in
801 the equivalent expression. To move the libcall,
802 we must move those regs too. */
804 }
805 }
807 /* For parallels, add any possible uses to the dependencies, as
808 we can't move the insn without resolving them first.
809 MEMs inside CLOBBERs may also reference registers; these
810 count as implicit uses. */
812 {
814 {
817 dependencies
819 dependencies);
824 }
825 }
828 than the one where it is set (meaning that
829 something after this point in the loop might
830 depend on its value before the set). */
832 /* And the set is not guaranteed to be executed once
833 the loop starts, or the value before the set is
834 needed before the set occurs...
836 ??? Note we have quadratic behavior here, mitigated
837 by the fact that the previous test will often fail for
838 large loops. Rather than re-scanning the entire loop
839 each time for register usage, we should build tables
840 of the register usage and use them here instead. */
841 && (maybe_never
843 /* It is unsafe to move the set. However, it may be OK to
844 move the source into a new pseudo, and substitute a
845 reg-to-reg copy for the original insn.
847 This code used to consider it OK to move a set of a variable
848 which was not created by the user and not used in an exit
849 test.
850 That behavior is incorrect and was removed. */
853 /* Don't try to optimize a MODE_CC set with a constant
854 source. It probably will be combined with a conditional
855 jump. */
858 ;
859 /* Don't try to optimize a register that was made
860 by loop-optimization for an inner loop.
861 We don't know its life-span, so we can't compute
862 the benefit. */
864 ;
865 /* Don't move the source and add a reg-to-reg copy:
866 - with -Os (this certainly increases size),
867 - if the mode doesn't support copy operations (obviously),
868 - if the source is already a reg (the motion will gain nothing),
869 - if the source is a legitimate constant (likewise). */
871 && (optimize_size
876 ;
879 || (tem2
882 || (tem1
883 = consec_sets_invariant_p
886 p)))
887 /* If the insn can cause a trap (such as divide by zero),
888 can't move it unless it's guaranteed to be executed
889 once loop is entered. Even a function call might
890 prevent the trap insn from being reached
891 (since it might exit!) */
894 {
898 /* A potential lossage is where we have a case where two insns
899 can be combined as long as they are both in the loop, but
900 we move one of them outside the loop. For large loops,
901 this can lose. The most common case of this is the address
902 of a function being called.
904 Therefore, if this register is marked as being used
905 exactly once if we are in a loop with calls
906 (a "large loop"), see if we can replace the usage of
907 this register with the source of this SET. If we can,
908 delete this insn.
910 Don't do this if P has a REG_RETVAL note or if we have
911 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
923 && (! SMALL_REGISTER_CLASSES
928 /* This test is not redundant; SET_SRC (set) might be
929 a call-clobbered register and the life of REGNO
930 might span a call. */
937 {
938 /* Replace any usage in a REG_EQUAL note. Must copy
939 the new source, so that we don't get rtx sharing
940 between the SET_SOURCE and REG_NOTES of insn p. */
942 = (replace_rtx
948 i++)
951 }
960 m->consec
971 /* Set M->cond if either loop_invariant_p
972 or consec_sets_invariant_p returned 2
973 (only conditionally invariant). */
983 /* Add M to the end of the chain MOVABLES. */
987 {
988 /* It is possible for the first instruction to have a
989 REG_EQUAL note but a non-invariant SET_SRC, so we must
990 remember the status of the first instruction in case
991 the last instruction doesn't have a REG_EQUAL note. */
994 /* Skip this insn, not checking REG_LIBCALL notes. */
996 /* Skip the consecutive insns, if there are any. */
998 /* Back up to the last insn of the consecutive group. */
1001 /* We must now reset m->move_insn, m->is_equiv, and
1002 possibly m->set_src to correspond to the effects of
1003 all the insns. */
1007 else
1008 {
1012 else
1015 }
1016 m->is_equiv
1018 }
1019 }
1020 /* If this register is always set within a STRICT_LOW_PART
1021 or set to zero, then its high bytes are constant.
1022 So clear them outside the loop and within the loop
1023 just load the low bytes.
1024 We must check that the machine has an instruction to do so.
1025 Also, if the value loaded into the register
1026 depends on the same register, this cannot be done. */
1036 {
1039 {
1054 /* If the insn may not be executed on some cycles,
1055 we can't clear the whole reg; clear just high part.
1056 Not even if the reg is used only within this loop.
1057 Consider this:
1058 while (1)
1059 while (s != t) {
1060 if (foo ()) x = *s;
1061 use (x);
1062 }
1063 Clearing x before the inner loop could clobber a value
1064 being saved from the last time around the outer loop.
1065 However, if the reg is not used outside this loop
1066 and all uses of the register are in the same
1067 basic block as the store, there is no problem.
1069 If this insn was made by loop, we don't know its
1070 INSN_LUID and hence must make a conservative
1071 assumption. */
1074 || (labels_in_range_p
1078 else
1087 i++)
1089 /* Add M to the end of the chain MOVABLES. */
1091 }
1092 }
1093 }
1094 }
1095 /* Past a call insn, we get to insns which might not be executed
1096 because the call might exit. This matters for insns that trap.
1097 Constant and pure call insns always return, so they don't count. */
1100 /* Past a label or a jump, we get to insns for which we
1101 can't count on whether or how many times they will be
1102 executed during each iteration. Therefore, we can
1103 only move out sets of trivial variables
1104 (those not used after the loop). */
1105 /* Similar code appears twice in strength_reduce. */
1107 /* If we enter the loop in the middle, and scan around to the
1108 beginning, don't set maybe_never for that. This must be an
1109 unconditional jump, otherwise the code at the top of the
1110 loop might never be executed. Unconditional jumps are
1111 followed by a barrier then the loop_end. */
1116 }
1118 /* If one movable subsumes another, ignore that other. */
1122 /* For each movable insn, see if the reg that it loads
1123 leads when it dies right into another conditionally movable insn.
1124 If so, record that the second insn "forces" the first one,
1125 since the second can be moved only if the first is. */
1129 /* See if there are multiple movable insns that load the same value.
1130 If there are, make all but the first point at the first one
1131 through the `match' field, and add the priorities of them
1132 all together as the priority of the first. */
1136 /* Now consider each movable insn to decide whether it is worth moving.
1137 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1139 For machines with few registers this increases code size, so do not
1140 move moveables when optimizing for code size on such machines.
1141 (The 18 below is the value for i386.) */
1145 {
1148 /* Recalculate regs->array if move_movables has created new
1149 registers. */
1151 {
1157 ;
1162 }
1163 }
1165 /* Now candidates that still are negative are those not moved.
1166 Change regs->array[I].set_in_loop to indicate that those are not actually
1167 invariant. */
1172 /* Now that we've moved some things out of the loop, we might be able to
1173 hoist even more memory references. */
1176 /* Recalculate regs->array if load_mems has created new registers. */
1184 ;
1191 {
1193 /* Ensure our label doesn't go away. */
1204 }
1207 /* The movable information is required for strength reduction. */
1213 }
1214 \f
1215 /* Add elements to *OUTPUT to record all the pseudo-regs
1216 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1218 static void
1220 {
1228 {
1246 }
1250 {
1254 {
1263 }
1264 }
1265 }
1266 \f
1267 /* Check what regs are referred to in the libcall block ending with INSN,
1268 aside from those mentioned in the equivalent value.
1269 If there are none, return 0.
1270 If there are one or more, return an EXPR_LIST containing all of them. */
1272 static rtx
1274 {
1279 /* First, find all the regs used in the libcall block
1280 that are not mentioned as inputs to the result. */
1283 {
1287 }
1290 }
1291 \f
1292 /* Return 1 if all uses of REG
1293 are between INSN and the end of the basic block. */
1295 static int
1297 {
1299 rtx p;
1304 /* Search this basic block for the already recorded last use of the reg. */
1306 {
1308 {
1314 /* Ordinary insn: if this is the last use, we win. */
1320 /* Jump insn: if this is the last use, we win. */
1323 /* Otherwise, it's the end of the basic block, so we lose. */
1328 /* It's the end of the basic block, so we lose. */
1333 }
1334 }
1336 /* The "last use" that was recorded can't be found after the first
1337 use. This can happen when the last use was deleted while
1338 processing an inner loop, this inner loop was then completely
1339 unrolled, and the outer loop is always exited after the inner loop,
1340 so that everything after the first use becomes a single basic block. */
1342 }
1343 \f
1344 /* Compute the benefit of eliminating the insns in the block whose
1345 last insn is LAST. This may be a group of insns used to compute a
1346 value directly or can contain a library call. */
1348 static int
1350 {
1351 rtx insn;
1356 {
1359 routine. */
1363 benefit++;
1364 }
1367 }
1368 \f
1369 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1371 static rtx
1373 {
1375 {
1376 rtx temp;
1378 /* If first insn of libcall sequence, skip to end. */
1379 /* Do this at start of loop, since INSN is guaranteed to
1380 be an insn here. */
1385 do
1388 }
1391 }
1393 /* Ignore any movable whose insn falls within a libcall
1394 which is part of another movable.
1395 We make use of the fact that the movable for the libcall value
1396 was made later and so appears later on the chain. */
1398 static void
1400 {
1404 {
1405 /* Is this a movable for the value of a libcall? */
1408 {
1409 rtx insn;
1410 /* Check for earlier movables inside that range,
1411 and mark them invalid. We cannot use LUIDs here because
1412 insns created by loop.c for prior loops don't have LUIDs.
1413 Rather than reject all such insns from movables, we just
1414 explicitly check each insn in the libcall (since invariant
1415 libcalls aren't that common). */
1420 }
1421 }
1422 }
1424 /* For each movable insn, see if the reg that it loads
1425 leads when it dies right into another conditionally movable insn.
1426 If so, record that the second insn "forces" the first one,
1427 since the second can be moved only if the first is. */
1429 static void
1431 {
1435 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1437 {
1440 /* ??? Could this be a bug? What if CSE caused the
1441 register of M1 to be used after this insn?
1442 Since CSE does not update regno_last_uid,
1443 this insn M->insn might not be where it dies.
1444 But very likely this doesn't matter; what matters is
1445 that M's reg is computed from M1's reg. */
1450 /* If m->consec, m->set_src isn't valid. */
1454 /* Increase the priority of the moving the first insn
1455 since it permits the second to be moved as well.
1456 Likewise for insns already forced by the first insn. */
1458 {
1463 {
1466 }
1467 }
1468 }
1469 }
1470 \f
1471 /* Find invariant expressions that are equal and can be combined into
1472 one register. */
1474 static void
1476 {
1481 /* Regs that are set more than once are not allowed to match
1482 or be matched. I'm no longer sure why not. */
1483 /* Only pseudo registers are allowed to match or be matched,
1484 since move_movables does not validate the change. */
1485 /* Perhaps testing m->consec_sets would be more appropriate here? */
1492 {
1499 /* We want later insns to match the first one. Don't make the first
1500 one match any later ones. So start this loop at m->next. */
1506 /* A reg used outside the loop mustn't be eliminated. */
1508 /* A reg used for zero-extending mustn't be eliminated. */
1511 ||
1512 (
1513 /* Can combine regs with different modes loaded from the
1514 same constant only if the modes are the same or
1515 if both are integer modes with M wider or the same
1516 width as M1. The check for integer is redundant, but
1517 safe, since the only case of differing destination
1518 modes with equal sources is when both sources are
1519 VOIDmode, i.e., CONST_INT. */
1525 /* See if the source of M1 says it matches M. */
1532 {
1538 }
1539 }
1541 /* Now combine the regs used for zero-extension.
1542 This can be done for those not marked `global'
1543 provided their lives don't overlap. */
1547 {
1550 /* Combine all the registers for extension from mode MODE.
1551 Don't combine any that are used outside this loop. */
1555 {
1562 {
1563 /* First one: don't check for overlap, just record it. */
1566 }
1568 /* Make sure they extend to the same mode.
1569 (Almost always true.) */
1573 /* We already have one: check for overlap with those
1574 already combined together. */
1581 /* No overlap: we can combine this with the others. */
1587 overlap:
1588 ;
1589 }
1590 }
1592 /* Clean up. */
1594 }
1596 /* Returns the number of movable instructions in LOOP that were not
1597 moved outside the loop. */
1599 static int
1601 {
1610 }
1612 \f
1613 /* Return 1 if regs X and Y will become the same if moved. */
1615 static int
1617 {
1634 }
1636 /* Return 1 if X and Y are identical-looking rtx's.
1637 This is the Lisp function EQUAL for rtx arguments.
1639 If two registers are matching movables or a movable register and an
1640 equivalent constant, consider them equal. */
1642 static int
1645 {
1659 /* If we have a register and a constant, they may sometimes be
1660 equal. */
1663 {
1668 }
1671 {
1676 }
1678 /* Otherwise, rtx's of different codes cannot be equal. */
1682 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1683 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1688 /* These three types of rtx's can be compared nonrecursively. */
1697 /* Compare the elements. If any pair of corresponding elements
1698 fail to match, return 0 for the whole things. */
1702 {
1704 {
1716 /* Two vectors must have the same length. */
1720 /* And the corresponding elements must match. */
1739 /* These are just backpointers, so they don't matter. */
1745 /* It is believed that rtx's at this level will never
1746 contain anything but integers and other rtx's,
1747 except for within LABEL_REFs and SYMBOL_REFs. */
1750 }
1751 }
1753 }
1754 \f
1755 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1756 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1757 references is incremented once for each added note. */
1759 static void
1761 {
1765 rtx insn;
1768 {
1769 /* This code used to ignore labels that referred to dispatch tables to
1770 avoid flow generating (slightly) worse code.
1772 We no longer ignore such label references (see LABEL_REF handling in
1773 mark_jump_label for additional information). */
1776 {
1781 }
1782 }
1786 {
1792 }
1793 }
1794 \f
1795 /* Scan MOVABLES, and move the insns that deserve to be moved.
1796 If two matching movables are combined, replace one reg with the
1797 other throughout. */
1799 static void
1802 {
1807 rtx p;
1810 /* Map of pseudo-register replacements to handle combining
1811 when we move several insns that load the same value
1812 into different pseudo-registers. */
1817 {
1818 /* Describe this movable insn. */
1821 {
1842 }
1844 /* Ignore the insn if it's already done (it matched something else).
1845 Otherwise, see if it is now safe to move. */
1857 {
1859 rtx p;
1862 /* We have an insn that is safe to move.
1863 Compute its desirability. */
1874 /* An insn MUST be moved if we already moved something else
1875 which is safe only if this one is moved too: that is,
1876 if already_moved[REGNO] is nonzero. */
1878 /* An insn is desirable to move if the new lifetime of the
1879 register is no more than THRESHOLD times the old lifetime.
1880 If it's not desirable, it means the loop is so big
1881 that moving won't speed things up much,
1882 and it is liable to make register usage worse. */
1884 /* It is also desirable to move if it can be moved at no
1885 extra cost because something else was already moved. */
1888 || flag_move_all_movables
1893 {
1902 /* Now move the insns that set the reg. */
1905 {
1908 /* Find the end of this chain of matching regs.
1909 Thus, we load each reg in the chain from that one reg.
1910 And that reg is loaded with 0 directly,
1911 since it has ->match == 0. */
1917 /* Mark the moved, invariant reg as being allowed to
1918 share a hard reg with the other matching invariant. */
1922 regs_may_share
1925 regs_may_share));
1933 }
1934 /* If we are to re-generate the item being moved with a
1935 new move insn, first delete what we have and then emit
1936 the move insn before the loop. */
1938 {
1942 {
1943 /* If this is the first insn of a library call sequence,
1944 something is very wrong. */
1949 /* If this is the last insn of a libcall sequence, then
1950 delete every insn in the sequence except the last.
1951 The last insn is handled in the normal manner. */
1954 {
1958 }
1963 /* simplify_giv_expr expects that it can walk the insns
1964 at m->insn forwards and see this old sequence we are
1965 tossing here. delete_insn does preserve the next
1966 pointers, but when we skip over a NOTE we must fix
1967 it up. Otherwise that code walks into the non-deleted
1968 insn stream. */
1973 {
1974 /* Replace the original insn with a move from
1975 our newly created temp. */
1981 }
1982 }
2001 /* The more regs we move, the less we like moving them. */
2003 }
2004 else
2005 {
2007 {
2010 /* If first insn of libcall sequence, skip to end. */
2011 /* Do this at start of loop, since p is guaranteed to
2012 be an insn here. */
2017 /* If last insn of libcall sequence, move all
2018 insns except the last before the loop. The last
2019 insn is handled in the normal manner. */
2022 {
2030 {
2031 rtx body;
2032 rtx n;
2033 rtx next;
2040 /* Find the next insn after TEMP,
2041 not counting USE or NOTE insns. */
2049 /* If that is the call, this may be the insn
2050 that loads the function address.
2052 Extract the function address from the insn
2053 that loads it into a register.
2054 If this insn was cse'd, we get incorrect code.
2056 So emit a new move insn that copies the
2057 function address into the register that the
2058 call insn will use. flow.c will delete any
2059 redundant stores that we have created. */
2064 NULL_RTX)))
2065 {
2071 }
2072 /* We have the call insn.
2073 If it uses the register we suspect it might,
2074 load it with the correct address directly. */
2079 gen_move_insn
2083 {
2085 /* Because the USAGE information potentially
2086 contains objects other than hard registers
2087 we need to copy it. */
2091 }
2092 else
2101 }
2104 }
2106 {
2107 /* P sets REG to zero; but we should clear only
2108 the bits that are not covered by the mode
2109 m->savemode. */
2111 rtx sequence;
2112 rtx tem;
2115 tem = expand_simple_binop
2128 }
2130 {
2132 /* Because the USAGE information potentially
2133 contains objects other than hard registers
2134 we need to copy it. */
2138 }
2140 {
2141 rtx seq;
2142 /* The SET_SRC might not be invariant, so we must
2143 use the REG_EQUAL note. */
2156 }
2158 {
2166 }
2167 else
2171 {
2175 /* If there is a REG_EQUAL note present whose value
2176 is not loop invariant, then delete it, since it
2177 may cause problems with later optimization passes.
2178 It is possible for cse to create such notes
2179 like this as a result of record_jump_cond. */
2184 }
2193 /* If library call, now fix the REG_NOTES that contain
2194 insn pointers, namely REG_LIBCALL on FIRST
2195 and REG_RETVAL on I1. */
2197 {
2201 }
2207 /* simplify_giv_expr expects that it can walk the insns
2208 at m->insn forwards and see this old sequence we are
2209 tossing here. delete_insn does preserve the next
2210 pointers, but when we skip over a NOTE we must fix
2211 it up. Otherwise that code walks into the non-deleted
2212 insn stream. */
2217 {
2218 rtx seq;
2219 /* Replace the original insn with a move from
2220 our newly created temp. */
2226 }
2227 }
2229 /* The more regs we move, the less we like moving them. */
2231 }
2236 {
2237 /* Any other movable that loads the same register
2238 MUST be moved. */
2241 /* This reg has been moved out of one loop. */
2244 /* The reg set here is now invariant. */
2246 {
2250 }
2252 /* Change the length-of-life info for the register
2253 to say it lives at least the full length of this loop.
2254 This will help guide optimizations in outer loops. */
2257 /* This is the old insn before all the moved insns.
2258 We can't use the moved insn because it is out of range
2259 in uid_luid. Only the old insns have luids. */
2263 }
2265 /* Combine with this moved insn any other matching movables. */
2270 {
2271 rtx temp;
2273 /* Schedule the reg loaded by M1
2274 for replacement so that shares the reg of M.
2275 If the modes differ (only possible in restricted
2276 circumstances, make a SUBREG.
2278 Note this assumes that the target dependent files
2279 treat REG and SUBREG equally, including within
2280 GO_IF_LEGITIMATE_ADDRESS and in all the
2281 predicates since we never verify that replacing the
2282 original register with a SUBREG results in a
2283 recognizable insn. */
2286 else
2291 /* Get rid of the matching insn
2292 and prevent further processing of it. */
2295 /* If library call, delete all insns. */
2297 NULL_RTX)))
2299 else
2302 /* Any other movable that loads the same register
2303 MUST be moved. */
2306 /* The reg merged here is now invariant,
2307 if the reg it matches is invariant. */
2309 {
2313 i++)
2315 }
2316 }
2317 }
2320 }
2326 }
2331 /* Go through all the instructions in the loop, making
2332 all the register substitutions scheduled in REG_MAP. */
2335 {
2339 }
2341 /* Clean up. */
2344 }
2347 static void
2349 {
2352 else
2355 }
2358 static void
2360 {
2365 {
2368 }
2369 }
2370 \f
2371 #if 0
2372 /* Scan X and replace the address of any MEM in it with ADDR.
2373 REG is the address that MEM should have before the replacement. */
2375 static void
2377 {
2386 {
2398 /* Short cut for very common case. */
2403 /* Short cut for very common case. */
2408 /* If this MEM uses a reg other than the one we expected,
2409 something is wrong. */
2417 }
2421 {
2425 {
2429 }
2430 }
2431 }
2432 #endif
2433 \f
2434 /* Return the number of memory refs to addresses that vary
2435 in the rtx X. */
2437 static int
2439 {
2450 {
2467 }
2472 {
2476 {
2480 }
2481 }
2483 }
2484 \f
2485 /* Scan a loop setting the elements `loops_enclosed',
2486 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2487 `unknown_address_altered', `unknown_constant_address_altered', and
2488 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2489 list `store_mems' in LOOP. */
2491 static void
2493 {
2495 rtx insn;
2499 /* The label after END. Jumping here is just like falling off the
2500 end of the loop. We use next_nonnote_insn instead of next_label
2501 as a hedge against the (pathological) case where some actual insn
2502 might end up between the two. */
2521 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2526 {
2528 {
2531 }
2532 }
2536 {
2538 {
2541 {
2543 /* Count number of loops contained in this one. */
2545 }
2552 {
2555 }
2565 {
2569 {
2574 {
2577 }
2578 else
2579 {
2582 }
2584 do
2585 {
2587 {
2589 {
2590 /* Something tricky. */
2593 }
2596 {
2597 /* A jump outside the current loop. */
2600 }
2601 }
2605 }
2607 }
2608 else
2609 {
2610 /* A return, or something tricky. */
2612 }
2613 }
2614 /* Fall through. */
2635 }
2636 }
2638 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2640 anywhere. */
2642 /* We don't want loads for MEMs moved to a location before the
2643 one at which their stack memory becomes allocated. (Note
2644 that this is not a problem for malloc, etc., since those
2645 require actual function calls. */
2646 && ! current_function_calls_alloca
2647 /* There are ways to leave the loop other than falling off the
2648 end. */
2654 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2655 that loop_invariant_p and load_mems can use true_dependence
2656 to determine what is really clobbered. */
2658 {
2661 loop_info->store_mems
2663 }
2665 {
2668 loop_info->store_mems
2670 }
2671 }
2672 \f
2673 /* Invalidate all loops containing LABEL. */
2675 static void
2677 {
2681 }
2683 /* Scan the function looking for loops. Record the start and end of each loop.
2684 Also mark as invalid loops any loops that contain a setjmp or are branched
2685 to from outside the loop. */
2687 static void
2689 {
2690 rtx insn;
2691 rtx label;
2701 /* If there are jumps to undefined labels,
2702 treat them as jumps out of any/all loops.
2703 This also avoids writing past end of tables when there are no loops. */
2706 /* Find boundaries of loops, mark which loops are contained within
2707 loops, and invalidate loops that have setjmp. */
2712 {
2715 {
2719 num_loops++;
2735 }
2739 {
2740 /* In this case, we must invalidate our current loop and any
2741 enclosing loop. */
2743 {
2749 }
2750 }
2752 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2753 enclosing loop, but this doesn't matter. */
2755 }
2757 /* Any loop containing a label used in an initializer must be invalidated,
2758 because it can be jumped into from anywhere. */
2762 /* Any loop containing a label used for an exception handler must be
2763 invalidated, because it can be jumped into from anywhere. */
2766 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2767 loop that it is not contained within, that loop is marked invalid.
2768 If any INSN or CALL_INSN uses a label's address, then the loop containing
2769 that label is marked invalid, because it could be jumped into from
2770 anywhere.
2772 Also look for blocks of code ending in an unconditional branch that
2773 exits the loop. If such a block is surrounded by a conditional
2774 branch around the block, move the block elsewhere (see below) and
2775 invert the jump to point to the code block. This may eliminate a
2776 label in our loop and will simplify processing by both us and a
2777 possible second cse pass. */
2781 {
2785 {
2789 }
2796 /* See if this is an unconditional branch outside the loop. */
2804 {
2805 rtx p;
2811 /* Go backwards until we reach the start of the loop, a label,
2812 or a JUMP_INSN. */
2819 ;
2821 /* Check for the case where we have a jump to an inner nested
2822 loop, and do not perform the optimization in that case. */
2825 {
2828 {
2833 }
2834 }
2836 /* Make sure that the target of P is within the current loop. */
2842 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2843 we have a block of code to try to move.
2845 We look backward and then forward from the target of INSN
2846 to find a BARRIER at the same loop depth as the target.
2847 If we find such a BARRIER, we make a new label for the start
2848 of the block, invert the jump in P and point it to that label,
2849 and move the block of code to the spot we found. */
2854 /* Just ignore jumps to labels that were never emitted.
2855 These always indicate compilation errors. */
2859 /* If it's not safe to move the sequence, then we
2860 mustn't try. */
2863 {
2864 rtx target
2868 rtx tmp;
2870 /* Search for possible garbage past the conditional jumps
2871 and look for the last barrier. */
2879 /* Don't move things inside a tablejump. */
2892 /* Don't move things inside a tablejump. */
2903 {
2907 /* Ensure our label doesn't go away. */
2910 /* Verify that uid_loop is large enough and that
2911 we can invert P. */
2913 {
2916 /* If no suitable BARRIER was found, create a suitable
2917 one before TARGET. Since TARGET is a fall through
2918 path, we'll need to insert a jump around our block
2919 and add a BARRIER before TARGET.
2921 This creates an extra unconditional jump outside
2922 the loop. However, the benefits of removing rarely
2923 executed instructions from inside the loop usually
2924 outweighs the cost of the extra unconditional jump
2925 outside the loop. */
2927 {
2928 rtx temp;
2935 }
2937 /* Include the BARRIER after INSN and copy the
2938 block after LOC. */
2943 /* All those insns are now in TARGET_LOOP. */
2949 /* The label jumped to by INSN is no longer a loop
2950 exit. Unless INSN does not have a label (e.g.,
2951 it is a RETURN insn), search loop->exit_labels
2952 to find its label_ref, and remove it. Also turn
2953 off LABEL_OUTSIDE_LOOP_P bit. */
2955 {
2957 r;
2960 {
2964 else
2967 }
2973 /* If we didn't find it, then something is
2974 wrong. */
2977 }
2979 /* P is now a jump outside the loop, so it must be put
2980 in loop->exit_labels, and marked as such.
2981 The easiest way to do this is to just call
2982 mark_loop_jump again for P. */
2985 /* If INSN now jumps to the insn after it,
2986 delete INSN. */
2991 }
2993 /* Continue the loop after where the conditional
2994 branch used to jump, since the only branch insn
2995 in the block (if it still remains) is an inter-loop
2996 branch and hence needs no processing. */
3002 /* This loop will be continued with NEXT_INSN (insn). */
3004 }
3005 }
3006 }
3007 }
3008 }
3010 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3011 loops it is contained in, mark the target loop invalid.
3013 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3015 static void
3017 {
3023 {
3035 /* There could be a label reference in here. */
3047 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3059 /* Link together all labels that branch outside the loop. This
3060 is used by final_[bg]iv_value and the loop unrolling code. Also
3061 mark this LABEL_REF so we know that this branch should predict
3062 false. */
3064 /* A check to make sure the label is not in an inner nested loop,
3065 since this does not count as a loop exit. */
3067 {
3072 }
3073 else
3077 {
3086 }
3088 /* If this is inside a loop, but not in the current loop or one enclosed
3089 by it, it invalidates at least one loop. */
3094 /* We must invalidate every nested loop containing the target of this
3095 label, except those that also contain the jump insn. */
3098 {
3099 /* Stop when we reach a loop that also contains the jump insn. */
3104 /* If we get here, we know we need to invalidate a loop. */
3111 }
3115 /* If this is not setting pc, ignore. */
3137 /* Strictly speaking this is not a jump into the loop, only a possible
3138 jump out of the loop. However, we have no way to link the destination
3139 of this jump onto the list of exit labels. To be safe we mark this
3140 loop and any containing loops as invalid. */
3142 {
3144 {
3150 }
3151 }
3153 }
3154 }
3155 \f
3156 /* Return nonzero if there is a label in the range from
3157 insn INSN to and including the insn whose luid is END
3158 INSN must have an assigned luid (i.e., it must not have
3159 been previously created by loop.c). */
3161 static int
3163 {
3165 {
3169 }
3172 }
3174 /* Record that a memory reference X is being set. */
3176 static void
3179 {
3185 /* Count number of memory writes.
3186 This affects heuristics in strength_reduce. */
3189 /* BLKmode MEM means all memory is clobbered. */
3191 {
3194 else
3198 }
3202 }
3204 /* X is a value modified by an INSN that references a biv inside a loop
3205 exit test (ie, X is somehow related to the value of the biv). If X
3206 is a pseudo that is used more than once, then the biv is (effectively)
3207 used more than once. DATA is a pointer to a loop_regs structure. */
3209 static void
3211 {
3226 /* If we do not have usage information, or if we know the register
3227 is used more than once, note that fact for check_dbra_loop. */
3232 }
3233 \f
3234 /* Return nonzero if the rtx X is invariant over the current loop.
3236 The value is 2 if we refer to something only conditionally invariant.
3238 A memory ref is invariant if it is not volatile and does not conflict
3239 with anything stored in `loop_info->store_mems'. */
3241 int
3243 {
3250 rtx mem_list_entry;
3256 {
3264 /* A LABEL_REF is normally invariant, however, if we are unrolling
3265 loops, and this label is inside the loop, then it isn't invariant.
3266 This is because each unrolled copy of the loop body will have
3267 a copy of this label. If this was invariant, then an insn loading
3268 the address of this label into a register might get moved outside
3269 the loop, and then each loop body would end up using the same label.
3271 We don't know the loop bounds here though, so just fail for all
3272 labels. */
3275 else
3293 /* Out-of-range regs can occur when we are called from unrolling.
3294 These registers created by the unroller are set in the loop,
3295 hence are never invariant.
3296 Other out-of-range regs can be generated by load_mems; those that
3297 are written to in the loop are not invariant, while those that are
3298 not written to are invariant. It would be easy for load_mems
3299 to set n_times_set correctly for these registers, however, there
3300 is no easy way to distinguish them from registers created by the
3301 unroller. */
3312 /* Volatile memory references must be rejected. Do this before
3313 checking for read-only items, so that volatile read-only items
3314 will be rejected also. */
3318 /* See if there is any dependence between a store and this load. */
3321 {
3327 }
3329 /* It's not invalidated by a store in memory
3330 but we must still verify the address is invariant. */
3334 /* Don't mess with insns declared volatile. */
3341 }
3345 {
3347 {
3353 }
3355 {
3358 {
3364 }
3366 }
3367 }
3370 }
3371 \f
3372 /* Return nonzero if all the insns in the loop that set REG
3373 are INSN and the immediately following insns,
3374 and if each of those insns sets REG in an invariant way
3375 (not counting uses of REG in them).
3377 The value is 2 if some of these insns are only conditionally invariant.
3379 We assume that INSN itself is the first set of REG
3380 and that its source is invariant. */
3382 static int
3384 rtx insn)
3385 {
3389 rtx temp;
3390 /* Number of sets we have to insist on finding after INSN. */
3396 /* If N_SETS hit the limit, we can't rely on its value. */
3403 {
3405 rtx set;
3410 /* If library call, skip to end of it. */
3419 {
3424 {
3425 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3426 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3427 notes are OK. */
3433 }
3434 }
3436 count--;
3438 {
3441 }
3442 }
3445 /* If loop_invariant_p ever returned 2, we return 2. */
3447 }
3448 \f
3449 /* Look at all uses (not sets) of registers in X. For each, if it is
3450 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3451 a different insn, set USAGE[REGNO] to const0_rtx. */
3453 static void
3455 {
3467 {
3468 /* Don't count SET_DEST if it is a REG; otherwise count things
3469 in SET_DEST because if a register is partially modified, it won't
3470 show up as a potential movable so we don't care how USAGE is set
3471 for it. */
3475 }
3476 else
3478 {
3484 }
3485 }
3486 \f
3487 /* Count and record any set in X which is contained in INSN. Update
3488 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3489 in X. */
3491 static void
3493 {
3495 /* Don't move a reg that has an explicit clobber.
3496 It's not worth the pain to try to do it correctly. */
3500 {
3508 {
3512 {
3513 /* If this is the first setting of this reg
3514 in current basic block, and it was set before,
3515 it must be set in two basic blocks, so it cannot
3516 be moved out of the loop. */
3520 /* If this is not first setting in current basic block,
3521 see if reg was used in between previous one and this.
3522 If so, neither one can be moved. */
3529 }
3530 }
3531 }
3532 }
3533 \f
3534 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3535 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3536 contained in insn INSN is used by any insn that precedes INSN in
3537 cyclic order starting from the loop entry point.
3539 We don't want to use INSN_LUID here because if we restrict INSN to those
3540 that have a valid INSN_LUID, it means we cannot move an invariant out
3541 from an inner loop past two loops. */
3543 static int
3545 {
3547 rtx p;
3549 /* Scan forward checking for register usage. If we hit INSN, we
3550 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3552 {
3558 }
3561 }
3562 \f
3564 /* Information we collect about arrays that we might want to prefetch. */
3565 struct prefetch_info
3566 {
3570 index. */
3571 HOST_WIDE_INT index;
3573 iteration. */
3575 prefetch area in one iteration. */
3577 This is set only for loops with known
3578 iteration counts and is 0xffffffff
3579 otherwise. */
3583 };
3585 /* Data used by check_store function. */
3586 struct check_store_data
3587 {
3588 rtx mem_address;
3590 };
3596 /* Set mem_write when mem_address is found. Used as callback to
3597 note_stores. */
3598 static void
3600 {
3605 }
3606 \f
3607 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3608 important to get some addresses combined. Later more sophisticated
3609 transformations can be added when necessary.
3611 ??? Same trick with swapping operand is done at several other places.
3612 It can be nice to develop some common way to handle this. */
3614 static int
3616 {
3628 {
3633 }
3635 /* Compare the elements. If any pair of corresponding elements fails to
3636 match, return 0 for the whole thing. */
3640 {
3642 {
3654 /* Two vectors must have the same length. */
3658 /* And the corresponding elements must match. */
3676 /* These are just backpointers, so they don't matter. */
3682 /* It is believed that rtx's at this level will never
3683 contain anything but integers and other rtx's,
3684 except for within LABEL_REFs and SYMBOL_REFs. */
3687 }
3688 }
3690 }
3691 \f
3692 /* Remove constant addition value from the expression X (when present)
3693 and return it. */
3695 static HOST_WIDE_INT
3697 {
3701 /* Avoid clobbering a shared CONST expression. */
3703 {
3707 {
3710 }
3712 }
3715 {
3718 }
3720 /* For plus expression recurse on ourself. */
3722 {
3726 /* In case our parameter was constant, remove extra zero from the
3727 expression. */
3732 }
3735 }
3737 /* Attempt to identify accesses to arrays that are most likely to cause cache
3738 misses, and emit prefetch instructions a few prefetch blocks forward.
3740 To detect the arrays we use the GIV information that was collected by the
3741 strength reduction pass.
3743 The prefetch instructions are generated after the GIV information is done
3744 and before the strength reduction process. The new GIVs are injected into
3745 the strength reduction tables, so the prefetch addresses are optimized as
3746 well.
3748 GIVs are split into base address, stride, and constant addition values.
3749 GIVs with the same address, stride and close addition values are combined
3750 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3751 for write instructions can be used for the block we write to, on machines
3752 that support write prefetches.
3754 Several heuristics are used to determine when to prefetch. They are
3755 controlled by defined symbols that can be overridden for each target. */
3757 static void
3759 {
3775 /* Consider only loops w/o calls. When a call is done, the loop is probably
3776 slow enough to read the memory. */
3778 {
3783 }
3785 /* Don't prefetch in loops known to have few iterations. */
3789 {
3794 }
3796 /* Search all induction variables and pick those interesting for the prefetch
3797 machinery. */
3799 {
3805 /* Expect all BIVs to be executed in each iteration. This makes our
3806 analysis more conservative. */
3808 {
3809 /* Discard non-constant additions that we can't handle well yet, and
3810 BIVs that are executed multiple times; such BIVs ought to be
3811 handled in the nested loop. We accept not_every_iteration BIVs,
3812 since these only result in larger strides and make our
3813 heuristics more conservative. */
3815 {
3817 {
3823 }
3825 }
3828 {
3830 {
3836 }
3838 }
3842 }
3848 {
3849 rtx address;
3850 rtx temp;
3859 /* See whether an induction variable is interesting to us and if
3860 not, report the reason. */
3864 /* We are interested only in constant stride memory references
3865 in order to be able to compute density easily. */
3869 else
3870 {
3873 {
3876 }
3878 /* On some targets, reversed order prefetches are not
3879 worthwhile. */
3883 /* Prefetch of accesses with an extreme stride might not be
3884 worthwhile, either. */
3889 /* Ignore GIVs with varying add values; we can't predict the
3890 value for the next iteration. */
3894 /* Ignore GIVs in the nested loops; they ought to have been
3895 handled already. */
3898 }
3901 {
3907 }
3909 /* Determine the pointer to the basic array we are examining. It is
3910 the sum of the BIV's initial value and the GIV's add_val. */
3920 /* When the GIV is not always executed, we might be better off by
3921 not dirtying the cache pages. */
3924 else
3925 {
3930 }
3932 /* Attempt to find another prefetch to the same array and see if we
3933 can merge this one. */
3937 {
3938 /* In case both access same array (same location
3939 just with small difference in constant indexes), merge
3940 the prefetches. Just do the later and the earlier will
3941 get prefetched from previous iteration.
3942 The artificial threshold should not be too small,
3943 but also not bigger than small portion of memory usually
3944 traversed by single loop. */
3947 {
3956 }
3960 {
3965 }
3966 }
3968 /* Merging failed. */
3970 {
3978 num_prefetches++;
3980 {
3985 }
3986 }
3987 }
3988 }
3991 {
3994 /* Attempt to calculate the total number of bytes fetched by all
3995 iterations of the loop. Avoid overflow. */
4000 else
4005 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4010 {
4015 }
4016 else
4017 {
4023 }
4024 else
4027 /* Find how many prefetch instructions we'll use within the loop. */
4029 {
4035 }
4036 }
4038 /* Determine how many iterations ahead to prefetch within the loop, based
4039 on how many prefetches we currently expect to do within the loop. */
4041 {
4043 {
4049 }
4050 }
4051 /* We'll also use AHEAD to determine how many prefetch instructions to
4052 emit before a loop, so don't leave it zero. */
4057 {
4058 /* Update if we've decided not to prefetch anything within the loop. */
4062 /* Find how many prefetch instructions we'll use before the loop. */
4064 {
4072 }
4075 {
4095 }
4096 }
4099 {
4100 /* Record that this loop uses prefetch instructions. */
4104 {
4109 }
4110 }
4113 {
4117 {
4119 rtx insn;
4123 rtx seq;
4125 /* We can save some effort by offsetting the address on
4126 architectures with offsettable memory references. */
4129 else
4130 {
4136 }
4139 /* Make sure the address operand is valid for prefetch. */
4149 /* Check all insns emitted and record the new GIV
4150 information. */
4153 {
4158 }
4159 }
4162 {
4163 /* Emit insns before the loop to fetch the first cache lines or,
4164 if we're not prefetching within the loop, everything we expect
4165 to need. */
4167 {
4175 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4176 non-constant INIT_VAL to have the same mode as REG, which
4177 in this case we know to be Pmode. */
4179 {
4180 rtx seq;
4187 }
4193 loop_start);
4194 }
4195 }
4196 }
4199 }
4200 \f
4201 /* Communication with routines called via `note_stores'. */
4205 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4209 /* ??? Unfinished optimizations, and possible future optimizations,
4210 for the strength reduction code. */
4212 /* ??? The interaction of biv elimination, and recognition of 'constant'
4213 bivs, may cause problems. */
4215 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4216 performance problems.
4218 Perhaps don't eliminate things that can be combined with an addressing
4219 mode. Find all givs that have the same biv, mult_val, and add_val;
4220 then for each giv, check to see if its only use dies in a following
4221 memory address. If so, generate a new memory address and check to see
4222 if it is valid. If it is valid, then store the modified memory address,
4223 otherwise, mark the giv as not done so that it will get its own iv. */
4225 /* ??? Could try to optimize branches when it is known that a biv is always
4226 positive. */
4228 /* ??? When replace a biv in a compare insn, we should replace with closest
4229 giv so that an optimized branch can still be recognized by the combiner,
4230 e.g. the VAX acb insn. */
4232 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4233 was rerun in loop_optimize whenever a register was added or moved.
4234 Also, some of the optimizations could be a little less conservative. */
4235 \f
4236 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4237 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4238 callback.
4240 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4241 least once for every loop iteration except for the last one.
4243 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4244 loop iteration.
4245 */
4246 void
4248 {
4252 rtx p;
4254 /* If loop_scan_start points to the loop exit test, we have to be wary of
4255 subversive use of gotos inside expression statements. */
4259 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4263 {
4266 /* Past CODE_LABEL, we get to insns that may be executed multiple
4267 times. The only way we can be sure that they can't is if every
4268 jump insn between here and the end of the loop either
4269 returns, exits the loop, is a jump to a location that is still
4270 behind the label, or is a jump to the loop start. */
4273 {
4279 {
4284 {
4287 else
4291 }
4299 {
4302 }
4303 }
4304 }
4306 /* Past a jump, we get to insns for which we can't count
4307 on whether they will be executed during each iteration. */
4308 /* This code appears twice in strength_reduce. There is also similar
4309 code in scan_loop. */
4311 /* If we enter the loop in the middle, and scan around to the
4312 beginning, don't set not_every_iteration for that.
4313 This can be any kind of jump, since we want to know if insns
4314 will be executed if the loop is executed. */
4319 {
4322 /* If this is a jump outside the loop, then it also doesn't
4323 matter. Check to see if the target of this branch is on the
4324 loop->exits_labels list. */
4332 }
4334 /* Note if we pass a loop latch. If we do, then we can not clear
4335 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4336 a loop since a jump before the last CODE_LABEL may have started
4337 a new loop iteration.
4339 Note that LOOP_TOP is only set for rotated loops and we need
4340 this check for all loops, so compare against the CODE_LABEL
4341 which immediately follows LOOP_START. */
4346 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4347 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4348 or not an insn is known to be executed each iteration of the
4349 loop, whether or not any iterations are known to occur.
4351 Therefore, if we have just passed a label and have no more labels
4352 between here and the test insn of the loop, and we have not passed
4353 a jump to the top of the loop, then we know these insns will be
4354 executed each iteration. */
4357 && !past_loop_latch
4361 }
4362 }
4363 \f
4364 static void
4366 {
4369 /* Temporary list pointers for traversing ivs->list. */
4376 /* Scan ivs->list to remove all regs that proved not to be bivs.
4377 Make a sanity check against regs->n_times_set. */
4379 {
4381 /* Above happens if register modified by subreg, etc. */
4382 /* Make sure it is not recognized as a basic induction var: */
4384 /* If never incremented, it is invariant that we decided not to
4385 move. So leave it alone. */
4387 {
4398 }
4399 else
4400 {
4405 }
4406 }
4407 }
4410 /* Determine how BIVS are initialized by looking through pre-header
4411 extended basic block. */
4412 static void
4414 {
4416 /* Temporary list pointers for traversing ivs->list. */
4419 rtx p;
4421 /* Find initial value for each biv by searching backwards from loop_start,
4422 halting at first label. Also record any test condition. */
4426 {
4427 rtx test;
4437 /* Record any test of a biv that branches around the loop if no store
4438 between it and the start of loop. We only care about tests with
4439 constants and registers and only certain of those. */
4449 {
4450 /* If an NE test, we have an initial value! */
4452 {
4456 }
4457 else
4459 }
4460 }
4461 }
4464 /* Look at the each biv and see if we can say anything better about its
4465 initial value from any initializing insns set up above. (This is done
4466 in two passes to avoid missing SETs in a PARALLEL.) */
4467 static void
4469 {
4471 /* Temporary list pointers for traversing ivs->list. */
4476 {
4477 rtx src;
4478 rtx note;
4483 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4484 is a constant, use the value of that. */
4490 else
4503 {
4507 {
4510 }
4511 }
4512 /* If we can't make it a giv,
4513 let biv keep initial value of "itself". */
4516 }
4517 }
4520 /* Search the loop for general induction variables. */
4522 static void
4524 {
4526 }
4529 /* For each giv for which we still don't know whether or not it is
4530 replaceable, check to see if it is replaceable because its final value
4531 can be calculated. */
4533 static void
4535 {
4540 {
4546 }
4547 }
4550 /* Return nonzero if it is possible to eliminate the biv BL provided
4551 all givs are reduced. This is possible if either the reg is not
4552 used outside the loop, or we can compute what its final value will
4553 be. */
4555 static int
4558 {
4559 /* For architectures with a decrement_and_branch_until_zero insn,
4560 don't do this if we put a REG_NONNEG note on the endtest for this
4561 biv. */
4563 #ifdef HAVE_decrement_and_branch_until_zero
4565 {
4570 }
4571 #endif
4573 /* Check that biv is used outside loop or if it has a final value.
4574 Compare against bl->init_insn rather than loop->start. We aren't
4575 concerned with any uses of the biv between init_insn and
4576 loop->start since these won't be affected by the value of the biv
4577 elsewhere in the function, so long as init_insn doesn't use the
4578 biv itself. */
4589 {
4597 }
4599 }
4602 /* Reduce each giv of BL that we have decided to reduce. */
4604 static void
4606 {
4610 {
4613 {
4616 /* If the code for derived givs immediately below has already
4617 allocated a new_reg, we must keep it. */
4621 #ifdef AUTO_INC_DEC
4622 /* If the target has auto-increment addressing modes, and
4623 this is an address giv, then try to put the increment
4624 immediately after its use, so that flow can create an
4625 auto-increment addressing mode. */
4626 /* Don't do this for loops entered at the bottom, to avoid
4627 this invalid transformation:
4628 jmp L; -> jmp L;
4629 TOP: TOP:
4630 use giv use giv
4631 L: inc giv
4632 inc biv L:
4633 test biv test giv
4634 cbr TOP cbr TOP
4635 */
4638 /* We don't handle reversed biv's because bl->biv->insn
4639 does not have a valid INSN_LUID. */
4644 {
4645 /* If other giv's have been combined with this one, then
4646 this will work only if all uses of the other giv's occur
4647 before this giv's insn. This is difficult to check.
4649 We simplify this by looking for the common case where
4650 there is one DEST_REG giv, and this giv's insn is the
4651 last use of the dest_reg of that DEST_REG giv. If the
4652 increment occurs after the address giv, then we can
4653 perform the optimization. (Otherwise, the increment
4654 would have to go before other_giv, and we would not be
4655 able to combine it with the address giv to get an
4656 auto-inc address.) */
4658 {
4663 {
4666 else
4668 }
4675 }
4676 /* Check for case where increment is before the address
4677 giv. Do this test in "loop order". */
4686 else
4689 #ifdef HAVE_cc0
4690 {
4691 rtx prev;
4693 /* We can't put an insn immediately after one setting
4694 cc0, or immediately before one using cc0. */
4701 }
4702 #endif
4706 }
4707 #endif
4709 /* For each place where the biv is incremented, add an insn
4710 to increment the new, reduced reg for the giv. */
4712 {
4713 rtx insert_before;
4715 /* Skip if location is the same as a previous one. */
4722 else
4730 /* A multiply is acceptable here
4731 since this is presumed to be seldom executed. */
4735 }
4737 /* Add code at loop start to initialize giv's reduced reg. */
4742 }
4743 }
4744 }
4747 /* Check for givs whose first use is their definition and whose
4748 last use is the definition of another giv. If so, it is likely
4749 dead and should not be used to derive another giv nor to
4750 eliminate a biv. */
4752 static void
4754 {
4758 {
4765 {
4771 }
4772 }
4773 }
4776 static void
4778 {
4782 {
4789 /* Update expression if this was combined, in case other giv was
4790 replaced. */
4795 /* See if this register is known to be a pointer to something. If
4796 so, see if we can find the alignment. First see if there is a
4797 destination register that is a pointer. If so, this shares the
4798 alignment too. Next see if we can deduce anything from the
4799 computational information. If not, and this is a DEST_ADDR
4800 giv, at least we know that it's a pointer, though we don't know
4801 the alignment. */
4809 {
4818 }
4822 {
4830 }
4835 /* Store reduced reg as the address in the memref where we found
4836 this giv. */
4839 {
4841 }
4842 else
4843 {
4845 rtx note;
4847 /* Not replaceable; emit an insn to set the original giv reg from
4848 the reduced giv, same as above. */
4853 /* The original insn may have a REG_EQUAL note. This note is
4854 now incorrect and may result in invalid substitutions later.
4855 The original insn is dead, but may be part of a libcall
4856 sequence, which doesn't seem worth the bother of handling. */
4860 }
4862 /* When a loop is reversed, givs which depend on the reversed
4863 biv, and which are live outside the loop, must be set to their
4864 correct final value. This insn is only needed if the giv is
4865 not replaceable. The correct final value is the same as the
4866 value that the giv starts the reversed loop with. */
4877 {
4882 }
4883 }
4884 }
4887 static int
4890 rtx test_reg)
4891 {
4900 /* Reduce benefit if not replaceable, since we will insert a
4901 move-insn to replace the insn that calculates this giv. Don't do
4902 this unless the giv is a user variable, since it will often be
4903 marked non-replaceable because of the duplication of the exit
4904 code outside the loop. In such a case, the copies we insert are
4905 dead and will be deleted. So they don't have a cost. Similar
4906 situations exist. */
4907 /* ??? The new final_[bg]iv_value code does a much better job of
4908 finding replaceable giv's, and hence this code may no longer be
4909 necessary. */
4914 /* Decrease the benefit to count the add-insns that we will insert
4915 to increment the reduced reg for the giv. ??? This can
4916 overestimate the run-time cost of the additional insns, e.g. if
4917 there are multiple basic blocks that increment the biv, but only
4918 one of these blocks is executed during each iteration. There is
4919 no good way to detect cases like this with the current structure
4920 of the loop optimizer. This code is more accurate for
4921 determining code size than run-time benefits. */
4924 /* Decide whether to strength-reduce this giv or to leave the code
4925 unchanged (recompute it from the biv each time it is used). This
4926 decision can be made independently for each giv. */
4928 #ifdef AUTO_INC_DEC
4929 /* Attempt to guess whether autoincrement will handle some of the
4930 new add insns; if so, increase BENEFIT (undo the subtraction of
4931 add_cost that was done above). */
4933 /* Increasing the benefit is risky, since this is only a guess.
4934 Avoid increasing register pressure in cases where there would
4935 be no other benefit from reducing this giv. */
4938 {
4953 }
4954 #endif
4957 }
4960 /* Free IV structures for LOOP. */
4962 static void
4964 {
4971 {
4977 {
4980 }
4982 {
4985 }
4989 }
4990 }
4993 /* Perform strength reduction and induction variable elimination.
4995 Pseudo registers created during this function will be beyond the
4996 last valid index in several tables including
4997 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4998 problem here, because the added registers cannot be givs outside of
4999 their loop, and hence will never be reconsidered. But scan_loop
5000 must check regnos to make sure they are in bounds. */
5002 static void
5004 {
5008 rtx p;
5009 /* Temporary list pointer for traversing ivs->list. */
5011 /* Ratio of extra register life span we can justify
5012 for saving an instruction. More if loop doesn't call subroutines
5013 since in that case saving an insn makes more difference
5014 and more registers are available. */
5015 /* ??? could set this to last value of threshold in move_movables */
5017 /* Map of pseudo-register replacements. */
5029 /* Find all BIVs in loop. */
5032 /* Exit if there are no bivs. */
5034 {
5035 /* Can still unroll the loop anyways, but indicate that there is no
5036 strength reduction info available. */
5042 }
5044 /* Determine how BIVS are initialized by looking through pre-header
5045 extended basic block. */
5048 /* Look at the each biv and see if we can say anything better about its
5049 initial value from any initializing insns set up above. */
5052 /* Search the loop for general induction variables. */
5055 /* Try to calculate and save the number of loop iterations. This is
5056 set to zero if the actual number can not be calculated. This must
5057 be called after all giv's have been identified, since otherwise it may
5058 fail if the iteration variable is a giv. */
5061 #ifdef HAVE_prefetch
5064 #endif
5066 /* Now for each giv for which we still don't know whether or not it is
5067 replaceable, check to see if it is replaceable because its final value
5068 can be calculated. This must be done after loop_iterations is called,
5069 so that final_giv_value will work correctly. */
5072 /* Try to prove that the loop counter variable (if any) is always
5073 nonnegative; if so, record that fact with a REG_NONNEG note
5074 so that "decrement and branch until zero" insn can be used. */
5077 /* Create reg_map to hold substitutions for replaceable giv regs.
5078 Some givs might have been made from biv increments, so look at
5079 ivs->reg_iv_type for a suitable size. */
5083 /* Examine each iv class for feasibility of strength reduction/induction
5084 variable elimination. */
5087 {
5091 /* Test whether it will be possible to eliminate this biv
5092 provided all givs are reduced. */
5095 /* This will be true at the end, if all givs which depend on this
5096 biv have been strength reduced.
5097 We can't (currently) eliminate the biv unless this is so. */
5100 /* Check each extension dependent giv in this class to see if its
5101 root biv is safe from wrapping in the interior mode. */
5104 /* Combine all giv's for this iv_class. */
5108 {
5116 /* If an insn is not to be strength reduced, then set its ignore
5117 flag, and clear bl->all_reduced. */
5119 /* A giv that depends on a reversed biv must be reduced if it is
5120 used after the loop exit, otherwise, it would have the wrong
5121 value after the loop exit. To make it simple, just reduce all
5122 of such giv's whether or not we know they are used after the loop
5123 exit. */
5128 {
5136 }
5137 else
5138 {
5139 /* Check that we can increment the reduced giv without a
5140 multiply insn. If not, reject it. */
5145 {
5153 }
5154 }
5155 }
5157 /* Check for givs whose first use is their definition and whose
5158 last use is the definition of another giv. If so, it is likely
5159 dead and should not be used to derive another giv nor to
5160 eliminate a biv. */
5163 /* Reduce each giv that we decided to reduce. */
5166 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5167 as not reduced.
5169 For each giv register that can be reduced now: if replaceable,
5170 substitute reduced reg wherever the old giv occurs;
5171 else add new move insn "giv_reg = reduced_reg". */
5174 /* All the givs based on the biv bl have been reduced if they
5175 merit it. */
5177 /* For each giv not marked as maybe dead that has been combined with a
5178 second giv, clear any "maybe dead" mark on that second giv.
5179 v->new_reg will either be or refer to the register of the giv it
5180 combined with.
5182 Doing this clearing avoids problems in biv elimination where
5183 a giv's new_reg is a complex value that can't be put in the
5184 insn but the giv combined with (with a reg as new_reg) is
5185 marked maybe_dead. Since the register will be used in either
5186 case, we'd prefer it be used from the simpler giv. */
5192 /* Try to eliminate the biv, if it is a candidate.
5193 This won't work if ! bl->all_reduced,
5194 since the givs we planned to use might not have been reduced.
5196 We have to be careful that we didn't initially think we could
5197 eliminate this biv because of a giv that we now think may be
5198 dead and shouldn't be used as a biv replacement.
5200 Also, there is the possibility that we may have a giv that looks
5201 like it can be used to eliminate a biv, but the resulting insn
5202 isn't valid. This can happen, for example, on the 88k, where a
5203 JUMP_INSN can compare a register only with zero. Attempts to
5204 replace it with a compare with a constant will fail.
5206 Note that in cases where this call fails, we may have replaced some
5207 of the occurrences of the biv with a giv, but no harm was done in
5208 doing so in the rare cases where it can occur. */
5212 {
5213 /* ?? If we created a new test to bypass the loop entirely,
5214 or otherwise drop straight in, based on this test, then
5215 we might want to rewrite it also. This way some later
5216 pass has more hope of removing the initialization of this
5217 biv entirely. */
5219 /* If final_value != 0, then the biv may be used after loop end
5220 and we must emit an insn to set it just in case.
5222 Reversed bivs already have an insn after the loop setting their
5223 value, so we don't need another one. We can't calculate the
5224 proper final value for such a biv here anyways. */
5233 }
5234 /* See above note wrt final_value. But since we couldn't eliminate
5235 the biv, we must set the value after the loop instead of before. */
5239 }
5241 /* Go through all the instructions in the loop, making all the
5242 register substitutions scheduled in REG_MAP. */
5246 {
5250 }
5253 {
5254 /* When we completely unroll a loop we will likely not need the increment
5255 of the loop BIV and we will not need the conditional branch at the
5256 end of the loop. */
5259 #ifdef HAVE_cc0
5260 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5261 need the comparison before the conditional branch at the end of the
5262 loop. */
5264 #endif
5266 /* We'll need one copy for each loop iteration. */
5269 /* A little slop to account for the ability to remove initialization
5270 code, better CSE, and other secondary benefits of completely
5271 unrolling some loops. */
5274 /* Clamp the value. */
5277 }
5279 /* Unroll loops from within strength reduction so that we can use the
5280 induction variable information that strength_reduce has already
5281 collected. Always unroll loops that would be as small or smaller
5282 unrolled than when rolled. */
5295 }
5296 \f
5297 /*Record all basic induction variables calculated in the insn. */
5298 static rtx
5301 {
5303 rtx set;
5304 rtx dest_reg;
5305 rtx inc_val;
5306 rtx mult_val;
5312 {
5317 {
5322 {
5323 /* It is a possible basic induction variable.
5324 Create and initialize an induction structure for it. */
5331 }
5334 }
5335 }
5337 }
5338 \f
5339 /* Record all givs calculated in the insn.
5340 A register is a giv if: it is only set once, it is a function of a
5341 biv and a constant (or invariant), and it is not a biv. */
5342 static rtx
5345 {
5348 rtx set;
5349 /* Look for a general induction variable in a register. */
5354 {
5355 rtx src_reg;
5356 rtx dest_reg;
5357 rtx add_val;
5358 rtx mult_val;
5359 rtx ext_val;
5362 rtx last_consec_insn;
5371 /* Equivalent expression is a giv. */
5376 /* Don't try to handle any regs made by loop optimization.
5377 We have nothing on them in regno_first_uid, etc. */
5379 /* Don't recognize a BASIC_INDUCT_VAR here. */
5381 /* This must be the only place where the register is set. */
5383 /* or all sets must be consecutive and make a giv. */
5388 {
5391 /* If this is a library call, increase benefit. */
5395 /* Skip the consecutive insns, if there are any. */
5403 }
5404 }
5406 /* Look for givs which are memory addresses. */
5409 maybe_multiple);
5411 /* Update the status of whether giv can derive other givs. This can
5412 change when we pass a label or an insn that updates a biv. */
5416 }
5417 \f
5418 /* Return 1 if X is a valid source for an initial value (or as value being
5419 compared against in an initial test).
5421 X must be either a register or constant and must not be clobbered between
5422 the current insn and the start of the loop.
5424 INSN is the insn containing X. */
5426 static int
5428 {
5432 /* Only consider pseudos we know about initialized in insns whose luids
5433 we know. */
5438 /* Don't use call-clobbered registers across a call which clobbers it. On
5439 some machines, don't use any hard registers at all. */
5441 && (SMALL_REGISTER_CLASSES
5445 /* Don't use registers that have been clobbered before the start of the
5446 loop. */
5451 }
5452 \f
5453 /* Scan X for memory refs and check each memory address
5454 as a possible giv. INSN is the insn whose pattern X comes from.
5455 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5456 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5457 more than once in each loop iteration. */
5459 static void
5462 {
5472 {
5488 {
5489 rtx src_reg;
5490 rtx add_val;
5491 rtx mult_val;
5492 rtx ext_val;
5495 /* This code used to disable creating GIVs with mult_val == 1 and
5496 add_val == 0. However, this leads to lost optimizations when
5497 it comes time to combine a set of related DEST_ADDR GIVs, since
5498 this one would not be seen. */
5503 {
5504 /* Found one; record it. */
5512 }
5513 }
5518 }
5520 /* Recursively scan the subexpressions for other mem refs. */
5526 maybe_multiple);
5530 maybe_multiple);
5531 }
5532 \f
5533 /* Fill in the data about one biv update.
5534 V is the `struct induction' in which we record the biv. (It is
5535 allocated by the caller, with alloca.)
5536 INSN is the insn that sets it.
5537 DEST_REG is the biv's reg.
5539 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5540 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5541 being set to INC_VAL.
5543 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5544 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5545 can be executed more than once per iteration. If MAYBE_MULTIPLE
5546 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5547 executed exactly once per iteration. */
5549 static void
5553 {
5570 /* Add this to the reg's iv_class, creating a class
5571 if this is the first incrementation of the reg. */
5575 {
5576 /* Create and initialize new iv_class. */
5586 /* Set initial value to the reg itself. */
5589 /* We haven't seen the initializing insn yet. */
5599 /* Add this class to ivs->list. */
5603 /* Put it in the array of biv register classes. */
5605 }
5606 else
5607 {
5608 /* Check if location is the same as a previous one. */
5612 {
5615 }
5616 }
5618 /* Update IV_CLASS entry for this biv. */
5627 }
5628 \f
5629 /* Fill in the data about one giv.
5630 V is the `struct induction' in which we record the giv. (It is
5631 allocated by the caller, with alloca.)
5632 INSN is the insn that sets it.
5633 BENEFIT estimates the savings from deleting this insn.
5634 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5635 into a register or is used as a memory address.
5637 SRC_REG is the biv reg which the giv is computed from.
5638 DEST_REG is the giv's reg (if the giv is stored in a reg).
5639 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5640 LOCATION points to the place where this giv's value appears in INSN. */
5642 static void
5647 {
5652 rtx temp;
5654 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5655 undo the MULT canonicalization that we performed earlier. */
5685 /* The v->always_computable field is used in update_giv_derive, to
5686 determine whether a giv can be used to derive another giv. For a
5687 DEST_REG giv, INSN computes a new value for the giv, so its value
5688 isn't computable if INSN insn't executed every iteration.
5689 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5690 it does not compute a new value. Hence the value is always computable
5691 regardless of whether INSN is executed each iteration. */
5695 else
5701 {
5704 }
5706 {
5711 /* If the lifetime is zero, it means that this register is
5712 really a dead store. So mark this as a giv that can be
5713 ignored. This will not prevent the biv from being eliminated. */
5719 }
5721 /* Add the giv to the class of givs computed from one biv. */
5725 {
5728 /* Don't count DEST_ADDR. This is supposed to count the number of
5729 insns that calculate givs. */
5733 }
5734 else
5735 /* Fatal error, biv missing for this giv? */
5739 {
5742 }
5743 else
5744 {
5745 /* The giv can be replaced outright by the reduced register only if all
5746 of the following conditions are true:
5747 - the insn that sets the giv is always executed on any iteration
5748 on which the giv is used at all
5749 (there are two ways to deduce this:
5750 either the insn is executed on every iteration,
5751 or all uses follow that insn in the same basic block),
5752 - the giv is not used outside the loop
5753 - no assignments to the biv occur during the giv's lifetime. */
5756 /* Previous line always fails if INSN was moved by loop opt. */
5759 && (! not_every_iteration
5761 {
5762 /* Now check that there are no assignments to the biv within the
5763 giv's lifetime. This requires two separate checks. */
5765 /* Check each biv update, and fail if any are between the first
5766 and last use of the giv.
5768 If this loop contains an inner loop that was unrolled, then
5769 the insn modifying the biv may have been emitted by the loop
5770 unrolling code, and hence does not have a valid luid. Just
5771 mark the biv as not replaceable in this case. It is not very
5772 useful as a biv, because it is used in two different loops.
5773 It is very unlikely that we would be able to optimize the giv
5774 using this biv anyways. */
5779 {
5785 {
5789 }
5790 }
5792 /* If there are any backwards branches that go from after the
5793 biv update to before it, then this giv is not replaceable. */
5797 {
5801 }
5802 }
5803 else
5804 {
5805 /* May still be replaceable, we don't have enough info here to
5806 decide. */
5809 }
5810 }
5812 /* Record whether the add_val contains a const_int, for later use by
5813 combine_givs. */
5814 {
5819 ;
5823 {
5825 {
5830 else
5832 }
5835 }
5836 }
5840 }
5842 /* All this does is determine whether a giv can be made replaceable because
5843 its final value can be calculated. This code can not be part of record_giv
5844 above, because final_giv_value requires that the number of loop iterations
5845 be known, and that can not be accurately calculated until after all givs
5846 have been identified. */
5848 static void
5850 {
5853 /* DEST_ADDR givs will never reach here, because they are always marked
5854 replaceable above in record_giv. */
5856 /* The giv can be replaced outright by the reduced register only if all
5857 of the following conditions are true:
5858 - the insn that sets the giv is always executed on any iteration
5859 on which the giv is used at all
5860 (there are two ways to deduce this:
5861 either the insn is executed on every iteration,
5862 or all uses follow that insn in the same basic block),
5863 - its final value can be calculated (this condition is different
5864 than the one above in record_giv)
5865 - it's not used before the it's set
5866 - no assignments to the biv occur during the giv's lifetime. */
5868 #if 0
5869 /* This is only called now when replaceable is known to be false. */
5870 /* Clear replaceable, so that it won't confuse final_giv_value. */
5872 #endif
5877 {
5880 rtx last_giv_use;
5885 /* When trying to determine whether or not a biv increment occurs
5886 during the lifetime of the giv, we can ignore uses of the variable
5887 outside the loop because final_value is true. Hence we can not
5888 use regno_last_uid and regno_first_uid as above in record_giv. */
5890 /* Search the loop to determine whether any assignments to the
5891 biv occur during the giv's lifetime. Start with the insn
5892 that sets the giv, and search around the loop until we come
5893 back to that insn again.
5895 Also fail if there is a jump within the giv's lifetime that jumps
5896 to somewhere outside the lifetime but still within the loop. This
5897 catches spaghetti code where the execution order is not linear, and
5898 hence the above test fails. Here we assume that the giv lifetime
5899 does not extend from one iteration of the loop to the next, so as
5900 to make the test easier. Since the lifetime isn't known yet,
5901 this requires two loops. See also record_giv above. */
5906 {
5909 {
5912 }
5917 {
5918 /* It is possible for the BIV increment to use the GIV if we
5919 have a cycle. Thus we must be sure to check each insn for
5920 both BIV and GIV uses, and we must check for BIV uses
5921 first. */
5928 {
5930 {
5934 }
5936 }
5937 }
5938 }
5940 /* Now that the lifetime of the giv is known, check for branches
5941 from within the lifetime to outside the lifetime if it is still
5942 replaceable. */
5945 {
5948 {
5961 {
5970 }
5971 }
5972 }
5974 /* If it is replaceable, then save the final value. */
5977 }
5982 }
5983 \f
5984 /* Update the status of whether a giv can derive other givs.
5986 We need to do something special if there is or may be an update to the biv
5987 between the time the giv is defined and the time it is used to derive
5988 another giv.
5990 In addition, a giv that is only conditionally set is not allowed to
5991 derive another giv once a label has been passed.
5993 The cases we look at are when a label or an update to a biv is passed. */
5995 static void
5997 {
6001 rtx tem;
6004 /* Search all IV classes, then all bivs, and finally all givs.
6006 There are three cases we are concerned with. First we have the situation
6007 of a giv that is only updated conditionally. In that case, it may not
6008 derive any givs after a label is passed.
6010 The second case is when a biv update occurs, or may occur, after the
6011 definition of a giv. For certain biv updates (see below) that are
6012 known to occur between the giv definition and use, we can adjust the
6013 giv definition. For others, or when the biv update is conditional,
6014 we must prevent the giv from deriving any other givs. There are two
6015 sub-cases within this case.
6017 If this is a label, we are concerned with any biv update that is done
6018 conditionally, since it may be done after the giv is defined followed by
6019 a branch here (actually, we need to pass both a jump and a label, but
6020 this extra tracking doesn't seem worth it).
6022 If this is a jump, we are concerned about any biv update that may be
6023 executed multiple times. We are actually only concerned about
6024 backward jumps, but it is probably not worth performing the test
6025 on the jump again here.
6027 If this is a biv update, we must adjust the giv status to show that a
6028 subsequent biv update was performed. If this adjustment cannot be done,
6029 the giv cannot derive further givs. */
6035 {
6036 /* Skip if location is the same as a previous one. */
6041 {
6042 /* If cant_derive is already true, there is no point in
6043 checking all of these conditions again. */
6047 /* If this giv is conditionally set and we have passed a label,
6048 it cannot derive anything. */
6052 /* Skip givs that have mult_val == 0, since
6053 they are really invariants. Also skip those that are
6054 replaceable, since we know their lifetime doesn't contain
6055 any biv update. */
6059 /* The only way we can allow this giv to derive another
6060 is if this is a biv increment and we can form the product
6061 of biv->add_val and giv->mult_val. In this case, we will
6062 be able to compute a compensation. */
6064 {
6065 rtx ext_val_dummy;
6076 tem = simplify_giv_expr
6083 else
6085 }
6089 }
6090 }
6091 }
6092 \f
6093 /* Check whether an insn is an increment legitimate for a basic induction var.
6094 X is the source of insn P, or a part of it.
6095 MODE is the mode in which X should be interpreted.
6097 DEST_REG is the putative biv, also the destination of the insn.
6098 We accept patterns of these forms:
6099 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6100 REG = INVARIANT + REG
6102 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6103 store the additive term into *INC_VAL, and store the place where
6104 we found the additive term into *LOCATION.
6106 If X is an assignment of an invariant into DEST_REG, we set
6107 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6109 We also want to detect a BIV when it corresponds to a variable
6110 whose mode was promoted. In that case, an increment
6111 of the variable may be a PLUS that adds a SUBREG of that variable to
6112 an invariant and then sign- or zero-extends the result of the PLUS
6113 into the variable.
6115 Most GIVs in such cases will be in the promoted mode, since that is the
6116 probably the natural computation mode (and almost certainly the mode
6117 used for addresses) on the machine. So we view the pseudo-reg containing
6118 the variable as the BIV, as if it were simply incremented.
6120 Note that treating the entire pseudo as a BIV will result in making
6121 simple increments to any GIVs based on it. However, if the variable
6122 overflows in its declared mode but not its promoted mode, the result will
6123 be incorrect. This is acceptable if the variable is signed, since
6124 overflows in such cases are undefined, but not if it is unsigned, since
6125 those overflows are defined. So we only check for SIGN_EXTEND and
6126 not ZERO_EXTEND.
6128 If we cannot find a biv, we return 0. */
6130 static int
6134 {
6142 {
6148 {
6150 }
6155 {
6157 }
6158 else
6165 /* convert_modes can emit new instructions, e.g. when arg is a loop
6166 invariant MEM and dest_reg has a different mode.
6167 These instructions would be emitted after the end of the function
6168 and then *inc_val would be an uninitialized pseudo.
6169 Detect this and bail in this case.
6170 Other alternatives to solve this can be introducing a convert_modes
6171 variant which is allowed to fail but not allowed to emit new
6172 instructions, emit these instructions before loop start and let
6173 it be garbage collected if *inc_val is never used or saving the
6174 *inc_val initialization sequence generated here and when *inc_val
6175 is going to be actually used, emit it at some suitable place. */
6179 {
6182 }
6190 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6191 handle addition of promoted variables.
6192 ??? The comment at the start of this function is wrong: promoted
6193 variable increments don't look like it says they do. */
6199 /* If this register is assigned in a previous insn, look at its
6200 source, but don't go outside the loop or past a label. */
6202 /* If this sets a register to itself, we would repeat any previous
6203 biv increment if we applied this strategy blindly. */
6209 {
6210 rtx dest;
6211 do
6212 {
6214 }
6243 }
6244 /* Fall through. */
6246 /* Can accept constant setting of biv only when inside inner most loop.
6247 Otherwise, a biv of an inner loop may be incorrectly recognized
6248 as a biv of the outer loop,
6249 causing code to be moved INTO the inner loop. */
6256 /* convert_modes aborts if we try to convert to or from CCmode, so just
6257 exclude that case. It is very unlikely that a condition code value
6258 would be a useful iterator anyways. convert_modes aborts if we try to
6259 convert a float mode to non-float or vice versa too. */
6263 {
6264 /* Possible bug here? Perhaps we don't know the mode of X. */
6268 {
6271 }
6276 }
6277 else
6281 /* Ignore this BIV if signed arithmetic overflow is defined. */
6288 /* Similar, since this can be a sign extension. */
6293 ;
6307 location);
6312 }
6313 }
6314 \f
6315 /* A general induction variable (giv) is any quantity that is a linear
6316 function of a basic induction variable,
6317 i.e. giv = biv * mult_val + add_val.
6318 The coefficients can be any loop invariant quantity.
6319 A giv need not be computed directly from the biv;
6320 it can be computed by way of other givs. */
6322 /* Determine whether X computes a giv.
6323 If it does, return a nonzero value
6324 which is the benefit from eliminating the computation of X;
6325 set *SRC_REG to the register of the biv that it is computed from;
6326 set *ADD_VAL and *MULT_VAL to the coefficients,
6327 such that the value of X is biv * mult + add; */
6329 static int
6334 {
6338 /* If this is an invariant, forget it, it isn't a giv. */
6349 {
6352 /* Since this is now an invariant and wasn't before, it must be a giv
6353 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6354 with. */
6361 /* This is equivalent to a BIV. */
6368 /* Either (plus (biv) (invar)) or
6369 (plus (mult (biv) (invar_1)) (invar_2)). */
6371 {
6374 }
6375 else
6376 {
6379 }
6384 /* ADD_VAL is zero. */
6392 }
6394 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6395 unless they are CONST_INT). */
6403 else
6406 /* Always return true if this is a giv so it will be detected as such,
6407 even if the benefit is zero or negative. This allows elimination
6408 of bivs that might otherwise not be eliminated. */
6410 }
6411 \f
6412 /* Given an expression, X, try to form it as a linear function of a biv.
6413 We will canonicalize it to be of the form
6414 (plus (mult (BIV) (invar_1))
6415 (invar_2))
6416 with possible degeneracies.
6418 The invariant expressions must each be of a form that can be used as a
6419 machine operand. We surround then with a USE rtx (a hack, but localized
6420 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6421 routine; it is the caller's responsibility to strip them.
6423 If no such canonicalization is possible (i.e., two biv's are used or an
6424 expression that is neither invariant nor a biv or giv), this routine
6425 returns 0.
6427 For a nonzero return, the result will have a code of CONST_INT, USE,
6428 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6430 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6435 static rtx
6437 {
6442 rtx tem;
6444 /* If this is not an integer mode, or if we cannot do arithmetic in this
6445 mode, this can't be a giv. */
6452 {
6459 /* Put constant last, CONST_INT last if both constant. */
6467 /* Handle addition of zero, then addition of an invariant. */
6472 {
6475 /* Adding two invariants must result in an invariant, so enclose
6476 addition operation inside a USE and return it. */
6486 else
6495 /* biv + invar or mult + invar. Return sum. */
6499 /* (a + invar_1) + invar_2. Associate. */
6500 return
6506 arg1)),
6511 }
6513 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6514 MULT to reduce cases. */
6520 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6521 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6522 Recurse to associate the second PLUS. */
6527 return
6535 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6551 /* Handle "a - b" as "a + b * (-1)". */
6557 constm1_rtx)),
6566 /* Put constant last, CONST_INT last if both constant. */
6571 /* If second argument is not now constant, not giv. */
6575 /* Handle multiply by 0 or 1. */
6583 {
6585 /* biv * invar. Done. */
6589 /* Product of two constants. */
6593 /* invar * invar is a giv, but attempt to simplify it somehow. */
6599 {
6600 /* (invar_0 * invar_1) * invar_2. Associate. */
6607 arg1)),
6609 }
6610 /* Propagate the MULT expressions to the innermost nodes. */
6612 {
6613 /* (invar_0 + invar_1) * invar_2. Distribute. */
6619 arg1),
6623 arg1)),
6625 }
6629 /* (a * invar_1) * invar_2. Associate. */
6635 arg1)),
6639 /* (a + invar_1) * invar_2. Distribute. */
6644 arg1),
6647 arg1)),
6652 }
6655 /* Shift by constant is multiply by power of two. */
6659 return
6668 /* "-a" is "a * (-1)" */
6674 /* "~a" is "-a - 1". Silly, but easy. */
6678 const1_rtx),
6682 /* Already in proper form for invariant. */
6688 /* Conditionally recognize extensions of simple IVs. After we've
6689 computed loop traversal counts and verified the range of the
6690 source IV, we'll reevaluate this as a GIV. */
6692 {
6695 {
6698 }
6699 }
6703 /* If this is a new register, we can't deal with it. */
6707 /* Check for biv or giv. */
6709 {
6713 {
6716 /* Form expression from giv and add benefit. Ensure this giv
6717 can derive another and subtract any needed adjustment if so. */
6719 /* Increasing the benefit here is risky. The only case in which it
6720 is arguably correct is if this is the only use of V. In other
6721 cases, this will artificially inflate the benefit of the current
6722 giv, and lead to suboptimal code. Thus, it is disabled, since
6723 potentially not reducing an only marginally beneficial giv is
6724 less harmful than reducing many givs that are not really
6725 beneficial. */
6726 {
6730 }
6743 {
6746 }
6747 else
6748 {
6751 }
6753 }
6756 do_default:
6757 /* If it isn't an induction variable, and it is invariant, we
6758 may be able to simplify things further by looking through
6759 the bits we just moved outside the loop. */
6761 {
6767 {
6768 /* Ok, we found a match. Substitute and simplify. */
6770 /* If we match another movable, we must use that, as
6771 this one is going away. */
6776 /* If consec is nonzero, this is a member of a group of
6777 instructions that were moved together. We handle this
6778 case only to the point of seeking to the last insn and
6779 looking for a REG_EQUAL. Fail if we don't find one. */
6781 {
6784 do
6785 {
6787 }
6793 }
6794 else
6795 {
6799 }
6802 {
6803 /* What we are most interested in is pointer
6804 arithmetic on invariants -- only take
6805 patterns we may be able to do something with. */
6811 {
6813 benefit);
6816 }
6821 {
6826 }
6827 }
6829 }
6830 }
6832 }
6834 /* Fall through to general case. */
6836 /* If invariant, return as USE (unless CONST_INT).
6837 Otherwise, not giv. */
6842 {
6851 }
6852 else
6854 }
6855 }
6857 /* This routine folds invariants such that there is only ever one
6858 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6860 static rtx
6862 {
6868 {
6871 }
6874 {
6877 }
6878 else
6879 {
6882 }
6883 }
6885 static rtx
6887 {
6889 {
6893 else
6896 }
6899 else
6902 }
6903 \f
6904 /* Help detect a giv that is calculated by several consecutive insns;
6905 for example,
6906 giv = biv * M
6907 giv = giv + A
6908 The caller has already identified the first insn P as having a giv as dest;
6909 we check that all other insns that set the same register follow
6910 immediately after P, that they alter nothing else,
6911 and that the result of the last is still a giv.
6913 The value is 0 if the reg set in P is not really a giv.
6914 Otherwise, the value is the amount gained by eliminating
6915 all the consecutive insns that compute the value.
6917 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6918 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6920 The coefficients of the ultimate giv value are stored in
6921 *MULT_VAL and *ADD_VAL. */
6923 static int
6927 {
6933 rtx temp;
6934 rtx set;
6936 /* Indicate that this is a giv so that we can update the value produced in
6937 each insn of the multi-insn sequence.
6939 This induction structure will be used only by the call to
6940 general_induction_var below, so we can allocate it on our stack.
6941 If this is a giv, our caller will replace the induct var entry with
6942 a new induction structure. */
6963 {
6967 /* If libcall, skip to end of call sequence. */
6978 /* Giv created by equivalent expression. */
6984 {
6988 count--;
6992 }
6994 {
6995 /* Allow insns that set something other than this giv to a
6996 constant. Such insns are needed on machines which cannot
6997 include long constants and should not disqualify a giv. */
7006 }
7007 }
7012 }
7013 \f
7014 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7015 represented by G1. If no such expression can be found, or it is clear that
7016 it cannot possibly be a valid address, 0 is returned.
7018 To perform the computation, we note that
7019 G1 = x * v + a and
7020 G2 = y * v + b
7021 where `v' is the biv.
7023 So G2 = (y/b) * G1 + (b - a*y/x).
7025 Note that MULT = y/x.
7027 Update: A and B are now allowed to be additive expressions such that
7028 B contains all variables in A. That is, computing B-A will not require
7029 subtracting variables. */
7031 static rtx
7033 {
7034 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7039 /* If MULT is not 1, we cannot handle A with non-constants, since we
7040 would then be required to subtract multiples of the registers in A.
7041 This is theoretically possible, and may even apply to some Fortran
7042 constructs, but it is a lot of work and we do not attempt it here. */
7047 /* In general these structures are sorted top to bottom (down the PLUS
7048 chain), but not left to right across the PLUS. If B is a higher
7049 order giv than A, we can strip one level and recurse. If A is higher
7050 order, we'll eventually bail out, but won't know that until the end.
7051 If they are the same, we'll strip one level around this loop. */
7054 {
7066 /* We matched: remove one reg completely. */
7069 /* An alternate match. */
7072 /* An alternate match. */
7074 else
7075 {
7076 /* Indicates an extra register in B. Strip one level from B and
7077 recurse, hoping B was the higher order expression. */
7082 }
7083 }
7085 /* Here we are at the last level of A, go through the cases hoping to
7086 get rid of everything but a constant. */
7089 {
7102 }
7104 {
7106 }
7108 {
7113 }
7115 {
7120 else
7122 }
7127 }
7129 rtx
7131 {
7134 /* The value that G1 will be multiplied by must be a constant integer. Also,
7135 the only chance we have of getting a valid address is if b*c/a (see above
7136 for notation) is also an integer. */
7139 {
7147 }
7150 else
7151 {
7152 /* ??? Find out if the one is a multiple of the other? */
7154 }
7158 {
7159 /* Failed. If we've got a multiplication factor between G1 and G2,
7160 scale G1's addend and try again. */
7162 {
7166 {
7167 HOST_WIDE_INT m;
7171 }
7172 else
7173 {
7175 mult);
7176 }
7179 }
7180 }
7184 /* Form simplified final result. */
7189 else
7194 else
7195 {
7198 {
7202 }
7205 }
7206 }
7207 \f
7208 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7209 represented by G1. This indicates that G2 should be combined with G1 and
7210 that G2 can use (either directly or via an address expression) a register
7211 used to represent G1. */
7213 static rtx
7215 {
7218 /* With the introduction of ext dependent givs, we must care for modes.
7219 G2 must not use a wider mode than G1. */
7229 /* If these givs are identical, they can be combined. We use the results
7230 of express_from because the addends are not in a canonical form, so
7231 rtx_equal_p is a weaker test. */
7232 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7233 combination to be the other way round. */
7236 {
7238 }
7240 /* If G2 can be expressed as a function of G1 and that function is valid
7241 as an address and no more expensive than using a register for G2,
7242 the expression of G2 in terms of G1 can be used. */
7249 }
7250 \f
7251 /* Check each extension dependent giv in this class to see if its
7252 root biv is safe from wrapping in the interior mode, which would
7253 make the giv illegal. */
7255 static void
7257 {
7261 HOST_WIDE_INT start_val;
7267 /* Make sure the iteration data is available. We must have
7268 constants in order to be certain of no overflow. */
7274 /* Make sure the host can represent the arithmetic. */
7276 {
7278 HOST_WIDE_INT s_end_val;
7290 /* Check for host arithmetic overflow. */
7292 {
7294 HOST_WIDE_INT s_max;
7301 /* Check zero extension of biv ok. */
7303 /* Check for host arithmetic overflow. */
7304 && (neg_incr
7307 /* Check for target arithmetic overflow. */
7308 && (neg_incr
7311 {
7313 }
7315 /* Check sign extension of biv ok. */
7316 /* ??? While it is true that overflow with signed and pointer
7317 arithmetic is undefined, I fear too many programmers don't
7318 keep this fact in mind -- myself included on occasion.
7319 So leave alone with the signed overflow optimizations. */
7321 /* Check for host arithmetic overflow. */
7322 && (neg_incr
7325 /* Check for target arithmetic overflow. */
7326 && (neg_incr
7329 {
7331 }
7332 }
7333 }
7335 /* If we know the BIV is compared at run-time against an
7336 invariant value, and the increment is +/- 1, we may also
7337 be able to prove that the BIV cannot overflow. */
7343 {
7344 /* If the increment is +1, and the exit test is a <,
7345 the BIV cannot overflow. (For <=, we have the
7346 problematic case that the comparison value might
7347 be the maximum value of the range.) */
7349 {
7354 }
7356 /* Likewise for increment -1 and exit test >. */
7358 {
7363 }
7364 }
7366 /* Invalidate givs that fail the tests. */
7369 {
7374 {
7383 /* We don't know whether this value is being used as either
7384 signed or unsigned, so to safely truncate we must satisfy
7385 both. The initial check here verifies the BIV itself;
7386 once that is successful we may check its range wrt the
7387 derived GIV. This works only if we were able to determine
7388 constant start and end values above. */
7390 {
7394 /* We know from the above that both endpoints are nonnegative,
7395 and that there is no wrapping. Verify that both endpoints
7396 are within the (signed) range of the outer mode. */
7399 }
7404 }
7407 {
7409 {
7413 }
7414 }
7415 else
7416 {
7418 {
7423 else
7424 {
7429 else
7431 }
7436 }
7439 }
7440 }
7441 }
7443 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7445 rtx
7447 {
7453 /* Recall that check_ext_dependent_givs verified that the known bounds
7454 of a biv did not overflow or wrap with respect to the extension for
7455 the giv. Therefore, constants need no additional adjustment. */
7459 /* Otherwise, we must adjust the value to compensate for the
7460 differing modes of the biv and the giv. */
7462 }
7463 \f
7464 struct combine_givs_stats
7465 {
7468 };
7470 static int
7472 {
7479 /* Stabilize the sort. */
7483 }
7485 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7486 any other. If so, point SAME to the giv combined with and set NEW_REG to
7487 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7488 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7490 static void
7492 {
7493 /* Additional benefit to add for being combined multiple times. */
7501 /* Count givs, because bl->giv_count is incorrect here. */
7505 giv_count++;
7517 {
7519 rtx single_use;
7524 /* If a DEST_REG GIV is used only once, do not allow it to combine
7525 with anything, for in doing so we will gain nothing that cannot
7526 be had by simply letting the GIV with which we would have combined
7527 to be reduced on its own. The losage shows up in particular with
7528 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7529 be seen elsewhere as well. */
7536 /* Add an additional weight for zero addends. */
7541 {
7542 rtx this_combine;
7547 {
7550 }
7551 }
7553 }
7555 /* Iterate, combining until we can't. */
7556 restart:
7560 {
7563 {
7569 }
7571 }
7574 {
7580 /* If it has already been combined, skip. */
7585 {
7588 /* If it has already been combined, skip. */
7590 {
7595 /* For destination, we now may replace by mem expression instead
7596 of register. This changes the costs considerably, so add the
7597 compensation. */
7607 /* ??? The new final_[bg]iv_value code does a much better job
7608 of finding replaceable giv's, and hence this code may no
7609 longer be necessary. */
7613 /* To help optimize the next set of combinations, remove
7614 this giv from the benefits of other potential mates. */
7616 {
7620 }
7627 }
7628 }
7630 /* To help optimize the next set of combinations, remove
7631 this giv from the benefits of other potential mates. */
7633 {
7635 {
7639 }
7643 /* We've finished with this giv, and everything it touched.
7644 Restart the combination so that proper weights for the
7645 rest of the givs are properly taken into account. */
7646 /* ??? Ideally we would compact the arrays at this point, so
7647 as to not cover old ground. But sanely compacting
7648 can_combine is tricky. */
7650 }
7651 }
7653 /* Clean up. */
7656 }
7657 \f
7658 /* Generate sequence for REG = B * M + A. B is the initial value of
7659 the basic induction variable, M a multiplicative constant, A an
7660 additive constant and REG the destination register. */
7662 static rtx
7664 {
7665 rtx seq;
7666 rtx result;
7669 /* Use unsigned arithmetic. */
7677 }
7680 /* Update registers created in insn sequence SEQ. */
7682 static void
7684 {
7685 rtx insn;
7687 /* Update register info for alias analysis. */
7691 {
7698 }
7699 }
7702 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7703 is the initial value of the basic induction variable, M a
7704 multiplicative constant, A an additive constant and REG the
7705 destination register. */
7707 void
7710 {
7711 rtx seq;
7714 {
7717 }
7719 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7722 /* Increase the lifetime of any invariants moved further in code. */
7727 /* It is possible that the expansion created lots of new registers.
7728 Iterate over the sequence we just created and record them all. We
7729 must do this before inserting the sequence. */
7733 }
7736 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7737 initial value of the basic induction variable, M a multiplicative
7738 constant, A an additive constant and REG the destination
7739 register. */
7741 void
7743 {
7744 rtx seq;
7746 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7749 /* Increase the lifetime of any invariants moved further in code.
7750 ???? Is this really necessary? */
7755 /* It is possible that the expansion created lots of new registers.
7756 Iterate over the sequence we just created and record them all. We
7757 must do this before inserting the sequence. */
7761 }
7764 /* Emit insns after loop to set REG = B * M + A. B is the initial
7765 value of the basic induction variable, M a multiplicative constant,
7766 A an additive constant and REG the destination register. */
7768 void
7770 {
7771 rtx seq;
7773 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7776 /* It is possible that the expansion created lots of new registers.
7777 Iterate over the sequence we just created and record them all. We
7778 must do this before inserting the sequence. */
7782 }
7786 /* Similar to gen_add_mult, but compute cost rather than generating
7787 sequence. */
7789 static int
7791 {
7801 {
7806 }
7809 }
7810 \f
7811 /* Test whether A * B can be computed without
7812 an actual multiply insn. Value is 1 if so.
7814 ??? This function stinks because it generates a ton of wasted RTL
7815 ??? and as a result fragments GC memory to no end. There are other
7816 ??? places in the compiler which are invoked a lot and do the same
7817 ??? thing, generate wasted RTL just to see if something is possible. */
7819 static int
7821 {
7822 rtx tmp;
7825 /* If only one is constant, make it B. */
7829 /* If first constant, both constant, so don't need multiply. */
7833 /* If second not constant, neither is constant, so would need multiply. */
7837 /* One operand is constant, so might not need multiply insn. Generate the
7838 code for the multiply and see if a call or multiply, or long sequence
7839 of insns is generated. */
7848 {
7851 {
7861 {
7864 }
7867 }
7868 }
7878 }
7879 \f
7880 /* Check to see if loop can be terminated by a "decrement and branch until
7881 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7882 Also try reversing an increment loop to a decrement loop
7883 to see if the optimization can be performed.
7884 Value is nonzero if optimization was performed. */
7886 /* This is useful even if the architecture doesn't have such an insn,
7887 because it might change a loops which increments from 0 to n to a loop
7888 which decrements from n to 0. A loop that decrements to zero is usually
7889 faster than one that increments from zero. */
7891 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7892 such as approx_final_value, biv_total_increment, loop_iterations, and
7893 final_[bg]iv_value. */
7895 static int
7897 {
7902 rtx reg;
7904 rtx jump_label;
7905 rtx final_value;
7906 rtx start_value;
7907 rtx new_add_val;
7908 rtx comparison;
7909 rtx before_comparison;
7910 rtx p;
7911 rtx jump;
7912 rtx first_compare;
7917 /* If last insn is a conditional branch, and the insn before tests a
7918 register value, try to optimize it. Otherwise, we can't do anything. */
7927 /* Try to compute whether the compare/branch at the loop end is one or
7928 two instructions. */
7934 else
7937 {
7938 /* If more than one condition is present to control the loop, then
7939 do not proceed, as this function does not know how to rewrite
7940 loop tests with more than one condition.
7942 Look backwards from the first insn in the last comparison
7943 sequence and see if we've got another comparison sequence. */
7945 rtx jump1;
7949 }
7951 /* Check all of the bivs to see if the compare uses one of them.
7952 Skip biv's set more than once because we can't guarantee that
7953 it will be zero on the last iteration. Also skip if the biv is
7954 used between its update and the test insn. */
7957 {
7962 first_compare))
7964 }
7966 /* Try swapping the comparison to identify a suitable biv. */
7973 first_compare))
7974 {
7976 VOIDmode,
7980 }
7985 /* Look for the case where the basic induction variable is always
7986 nonnegative, and equals zero on the last iteration.
7987 In this case, add a reg_note REG_NONNEG, which allows the
7988 m68k DBRA instruction to be used. */
7994 {
7995 /* Initial value must be greater than 0,
7996 init_val % -dec_value == 0 to ensure that it equals zero on
7997 the last iteration */
8003 {
8004 /* Register always nonnegative, add REG_NOTE to branch. */
8012 }
8014 /* If the decrement is 1 and the value was tested as >= 0 before
8015 the loop, then we can safely optimize. */
8017 {
8031 {
8039 }
8040 }
8041 }
8044 {
8045 /* Try to change inc to dec, so can apply above optimization. */
8046 /* Can do this if:
8047 all registers modified are induction variables or invariant,
8048 all memory references have non-overlapping addresses
8049 (obviously true if only one write)
8050 allow 2 insns for the compare/jump at the end of the loop. */
8051 /* Also, we must avoid any instructions which use both the reversed
8052 biv and another biv. Such instructions will fail if the loop is
8053 reversed. We meet this condition by requiring that either
8054 no_use_except_counting is true, or else that there is only
8055 one biv. */
8057 /* 1 if the iteration var is used only to count iterations. */
8059 /* 1 if the loop has no memory store, or it has a single memory store
8060 which is reversible. */
8066 {
8070 /* If there are no givs for this biv, and the only exit is the
8071 fall through at the end of the loop, then
8072 see if perhaps there are no uses except to count. */
8076 {
8081 /* An insn that sets the biv is okay. */
8082 ;
8084 /* An insn that doesn't mention the biv is okay. */
8085 ;
8088 {
8089 /* If either of these insns uses the biv and sets a pseudo
8090 that has more than one usage, then the biv has uses
8091 other than counting since it's used to derive a value
8092 that is used more than one time. */
8094 regs);
8096 {
8099 }
8100 }
8101 else
8102 {
8105 }
8106 }
8108 /* A biv has uses besides counting if it is used to set
8109 another biv. */
8113 {
8116 }
8117 }
8120 /* No need to worry about MEMs. */
8121 ;
8123 {
8128 /* If the loop has a single store, and the destination address is
8129 invariant, then we can't reverse the loop, because this address
8130 might then have the wrong value at loop exit.
8131 This would work if the source was invariant also, however, in that
8132 case, the insn should have been moved out of the loop. */
8135 {
8138 /* If we could prove that each of the memory locations
8139 written to was different, then we could reverse the
8140 store -- but we don't presently have any way of
8141 knowing that. */
8144 /* If the store depends on a register that is set after the
8145 store, it depends on the initial value, and is thus not
8146 reversible. */
8148 {
8155 }
8156 }
8157 }
8158 else
8161 /* This code only acts for innermost loops. Also it simplifies
8162 the memory address check by only reversing loops with
8163 zero or one memory access.
8164 Two memory accesses could involve parts of the same array,
8165 and that can't be reversed.
8166 If the biv is used only for counting, than we don't need to worry
8167 about all these things. */
8173 && reversible_mem_store
8178 {
8179 rtx tem;
8181 /* Loop can be reversed. */
8185 /* Now check other conditions:
8187 The increment must be a constant, as must the initial value,
8188 and the comparison code must be LT.
8190 This test can probably be improved since +/- 1 in the constant
8191 can be obtained by changing LT to LE and vice versa; this is
8192 confusing. */
8195 /* for constants, LE gets turned into LT */
8200 {
8212 comparison_const_width
8214 else
8215 comparison_const_width
8219 comparison_sign_mask
8222 /* If the comparison value is not a loop invariant, then we
8223 can not reverse this loop.
8225 ??? If the insns which initialize the comparison value as
8226 a whole compute an invariant result, then we could move
8227 them out of the loop and proceed with loop reversal. */
8235 /* Normalize the initial value if it is an integer and
8236 has no other use except as a counter. This will allow
8237 a few more loops to be reversed. */
8241 {
8243 /* The code below requires comparison_val to be a multiple
8244 of add_val in order to do the loop reversal, so
8245 round up comparison_val to a multiple of add_val.
8246 Since comparison_value is constant, we know that the
8247 current comparison code is LT. */
8249 comparison_val
8251 /* We postpone overflow checks for COMPARISON_VAL here;
8252 even if there is an overflow, we might still be able to
8253 reverse the loop, if converting the loop exit test to
8254 NE is possible. */
8256 }
8258 /* First check if we can do a vanilla loop reversal. */
8261 /* Now do postponed overflow checks on COMPARISON_VAL. */
8264 {
8265 /* Register will always be nonnegative, with value
8266 0 on last iteration */
8270 }
8271 else
8277 /* If the initial value is not zero, or if the comparison
8278 value is not an exact multiple of the increment, then we
8279 can not reverse this loop. */
8282 {
8285 }
8286 else
8287 {
8290 }
8294 /* Reset these in case we normalized the initial value
8295 and comparison value above. */
8298 {
8300 final_value
8302 }
8305 /* Save some info needed to produce the new insns. */
8311 /* Set start_value; if this is not a CONST_INT, we need
8312 to generate a SUB.
8313 Initialize biv to start_value before loop start.
8314 The old initializing insn will be deleted as a
8315 dead store by flow.c. */
8318 {
8319 start_value
8322 }
8324 {
8331 start_value
8337 }
8339 {
8341 initial_value);
8345 start_value
8348 }
8349 else
8350 /* We could handle the other cases too, but it'll be
8351 better to have a testcase first. */
8354 /* We may not have a single insn which can increment a reg, so
8355 create a sequence to hold all the insns from expand_inc. */
8364 /* Update biv info to reflect its new status. */
8369 /* Update loop info. */
8378 /* Inc LABEL_NUSES so that delete_insn will
8379 not delete the label. */
8382 /* If we have a separate comparison insn that does more
8383 than just set cc0, the result of the comparison might
8384 be used outside the loop. */
8386 #ifdef HAVE_CC0
8388 #endif
8389 );
8391 /* Emit an insn after the end of the loop to set the biv's
8392 proper exit value if it is used anywhere outside the loop. */
8402 /* Delete compare/branch at end of loop. */
8407 /* Add new compare/branch insn at end of loop. */
8419 ;
8425 {
8427 {
8428 /* Increment of LABEL_NUSES done above. */
8429 /* Register is now always nonnegative,
8430 so add REG_NONNEG note to the branch. */
8433 }
8435 }
8437 /* No insn may reference both the reversed and another biv or it
8438 will fail (see comment near the top of the loop reversal
8439 code).
8440 Earlier on, we have verified that the biv has no use except
8441 counting, or it is the only biv in this function.
8442 However, the code that computes no_use_except_counting does
8443 not verify reg notes. It's possible to have an insn that
8444 references another biv, and has a REG_EQUAL note with an
8445 expression based on the reversed biv. To avoid this case,
8446 remove all REG_EQUAL notes based on the reversed biv
8447 here. */
8450 {
8453 /* If this is a set of a GIV based on the reversed biv, any
8454 REG_EQUAL notes should still be correct. */
8461 {
8466 else
8468 }
8469 }
8471 /* Mark that this biv has been reversed. Each giv which depends
8472 on this biv, and which is also live past the end of the loop
8473 will have to be fixed up. */
8478 {
8482 else
8484 }
8487 }
8488 }
8489 }
8492 }
8493 \f
8494 /* Verify whether the biv BL appears to be eliminable,
8495 based on the insns in the loop that refer to it.
8497 If ELIMINATE_P is nonzero, actually do the elimination.
8499 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8500 determine whether invariant insns should be placed inside or at the
8501 start of the loop. */
8503 static int
8506 {
8509 rtx p;
8511 /* Scan all insns in the loop, stopping if we find one that uses the
8512 biv in a way that we cannot eliminate. */
8515 {
8519 rtx note;
8521 /* If this is a libcall that sets a giv, skip ahead to its end. */
8523 {
8527 {
8532 {
8539 }
8540 }
8541 }
8543 /* Closely examine the insn if the biv is mentioned. */
8548 {
8554 }
8556 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8561 }
8564 {
8569 }
8572 }
8573 \f
8574 /* INSN and REFERENCE are instructions in the same insn chain.
8575 Return nonzero if INSN is first. */
8577 int
8579 {
8583 {
8584 /* Start with test for not first so that INSN == REFERENCE yields not
8585 first. */
8591 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8592 previous insn, hence the <= comparison below does not work if
8593 P is a note. */
8604 }
8605 }
8607 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8608 the offset that we have to take into account due to auto-increment /
8609 div derivation is zero. */
8610 static int
8613 {
8614 /* If the giv V had the auto-inc address optimization applied
8615 to it, and INSN occurs between the giv insn and the biv
8616 insn, then we'd have to adjust the value used here.
8617 This is rare, so we don't bother to make this possible. */
8626 }
8628 /* If BL appears in X (part of the pattern of INSN), see if we can
8629 eliminate its use. If so, return 1. If not, return 0.
8631 If BIV does not appear in X, return 1.
8633 If ELIMINATE_P is nonzero, actually do the elimination.
8634 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8635 Depending on how many items have been moved out of the loop, it
8636 will either be before INSN (when WHERE_INSN is nonzero) or at the
8637 start of the loop (when WHERE_INSN is zero). */
8639 static int
8643 {
8649 #ifdef HAVE_cc0
8651 #endif
8657 {
8659 /* If we haven't already been able to do something with this BIV,
8660 we can't eliminate it. */
8666 /* If this sets the BIV, it is not a problem. */
8670 /* If this is an insn that defines a giv, it is also ok because
8671 it will go away when the giv is reduced. */
8676 #ifdef HAVE_cc0
8678 {
8679 /* Can replace with any giv that was reduced and
8680 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8681 Require a constant for MULT_VAL, so we know it's nonzero.
8682 ??? We disable this optimization to avoid potential
8683 overflows. */
8691 {
8698 /* If the giv has the opposite direction of change,
8699 then reverse the comparison. */
8703 else
8706 /* We can probably test that giv's reduced reg. */
8709 }
8711 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8712 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8713 Require a constant for MULT_VAL, so we know it's nonzero.
8714 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8715 overflow problem. */
8727 {
8734 /* If the giv has the opposite direction of change,
8735 then reverse the comparison. */
8739 else
8743 /* Replace biv with the giv's reduced register. */
8748 /* Insn doesn't support that constant or invariant. Copy it
8749 into a register (it will be a loop invariant.) */
8756 /* Substitute the new register for its invariant value in
8757 the compare expression. */
8761 }
8762 }
8763 #endif
8770 /* See if either argument is the biv. */
8775 else
8779 {
8780 /* First try to replace with any giv that has constant positive
8781 mult_val and constant add_val. We might be able to support
8782 negative mult_val, but it seems complex to do it in general. */
8794 {
8798 /* Don't eliminate if the linear combination that makes up
8799 the giv overflows when it is applied to ARG. */
8801 {
8802 rtx add_val;
8806 else
8812 }
8817 /* Replace biv with the giv's reduced reg. */
8820 /* If all constants are actually constant integers and
8821 the derived constant can be directly placed in the COMPARE,
8822 do so. */
8825 {
8828 }
8829 else
8830 {
8831 /* Otherwise, load it into a register. */
8836 }
8842 }
8844 /* Look for giv with positive constant mult_val and nonconst add_val.
8845 Insert insns to calculate new compare value.
8846 ??? Turn this off due to possible overflow. */
8854 {
8855 rtx tem;
8865 /* Replace biv with giv's reduced register. */
8869 /* Compute value to compare against. */
8873 /* Use it in this insn. */
8877 }
8878 }
8880 {
8882 {
8883 /* Look for giv with constant positive mult_val and nonconst
8884 add_val. Insert insns to compute new compare value.
8885 ??? Turn this off due to possible overflow. */
8892 {
8893 rtx tem;
8903 /* Replace biv with giv's reduced register. */
8907 /* Compute value to compare against. */
8914 }
8915 }
8917 /* This code has problems. Basically, you can't know when
8918 seeing if we will eliminate BL, whether a particular giv
8919 of ARG will be reduced. If it isn't going to be reduced,
8920 we can't eliminate BL. We can try forcing it to be reduced,
8921 but that can generate poor code.
8923 The problem is that the benefit of reducing TV, below should
8924 be increased if BL can actually be eliminated, but this means
8925 we might have to do a topological sort of the order in which
8926 we try to process biv. It doesn't seem worthwhile to do
8927 this sort of thing now. */
8929 #if 0
8930 /* Otherwise the reg compared with had better be a biv. */
8935 /* Look for a pair of givs, one for each biv,
8936 with identical coefficients. */
8938 {
8950 {
8957 /* Replace biv with its giv's reduced reg. */
8959 /* Replace other operand with the other giv's
8960 reduced reg. */
8963 }
8964 }
8965 #endif
8966 }
8968 /* If we get here, the biv can't be eliminated. */
8972 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8973 biv is used in it, since it will be replaced. */
8981 }
8983 /* See if any subexpression fails elimination. */
8986 {
8988 {
9001 }
9002 }
9005 }
9006 \f
9007 /* Return nonzero if the last use of REG
9008 is in an insn following INSN in the same basic block. */
9010 static int
9012 {
9013 rtx n;
9017 {
9020 }
9022 }
9023 \f
9024 /* Called via `note_stores' to record the initial value of a biv. Here we
9025 just record the location of the set and process it later. */
9027 static void
9029 {
9040 /* If this is the first set found, record it. */
9042 {
9045 }
9046 }
9047 \f
9048 /* If any of the registers in X are "old" and currently have a last use earlier
9049 than INSN, update them to have a last use of INSN. Their actual last use
9050 will be the previous insn but it will not have a valid uid_luid so we can't
9051 use it. X must be a source expression only. */
9053 static void
9055 {
9056 /* Check for the case where INSN does not have a valid luid. In this case,
9057 there is no need to modify the regno_last_uid, as this can only happen
9058 when code is inserted after the loop_end to set a pseudo's final value,
9059 and hence this insn will never be the last use of x.
9060 ???? This comment is not correct. See for example loop_givs_reduce.
9061 This may insert an insn before another new insn. */
9065 {
9067 }
9068 else
9069 {
9073 {
9079 }
9080 }
9081 }
9082 \f
9083 /* Given an insn INSN and condition COND, return the condition in a
9084 canonical form to simplify testing by callers. Specifically:
9086 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9087 (2) Both operands will be machine operands; (cc0) will have been replaced.
9088 (3) If an operand is a constant, it will be the second operand.
9089 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9090 for GE, GEU, and LEU.
9092 If the condition cannot be understood, or is an inequality floating-point
9093 comparison which needs to be reversed, 0 will be returned.
9095 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9097 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9098 insn used in locating the condition was found. If a replacement test
9099 of the condition is desired, it should be placed in front of that
9100 insn and we will be sure that the inputs are still valid.
9102 If WANT_REG is nonzero, we wish the condition to be relative to that
9103 register, if possible. Therefore, do not canonicalize the condition
9104 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9105 to be a compare to a CC mode register.
9107 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
9108 and at INSN. */
9110 rtx
9113 {
9116 rtx set;
9117 rtx tem;
9135 /* If we are comparing a register with zero, see if the register is set
9136 in the previous insn to a COMPARE or a comparison operation. Perform
9137 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9138 in cse.c */
9144 {
9145 /* Set nonzero when we find something of interest. */
9148 #ifdef HAVE_cc0
9149 /* If comparison with cc0, import actual comparison from compare
9150 insn. */
9152 {
9163 }
9164 #endif
9166 /* If this is a COMPARE, pick up the two things being compared. */
9168 {
9172 }
9176 /* Go back to the previous insn. Stop if it is not an INSN. We also
9177 stop if it isn't a single set or if it has a REG_INC note because
9178 we don't want to bother dealing with it. */
9192 /* If this is setting OP0, get what it sets it to if it looks
9193 relevant. */
9195 {
9197 #ifdef FLOAT_STORE_FLAG_VALUE
9198 REAL_VALUE_TYPE fsfv;
9199 #endif
9201 /* ??? We may not combine comparisons done in a CCmode with
9202 comparisons not done in a CCmode. This is to aid targets
9203 like Alpha that have an IEEE compliant EQ instruction, and
9204 a non-IEEE compliant BEQ instruction. The use of CCmode is
9205 actually artificial, simply to prevent the combination, but
9206 should not affect other platforms.
9208 However, we must allow VOIDmode comparisons to match either
9209 CCmode or non-CCmode comparison, because some ports have
9210 modeless comparisons inside branch patterns.
9212 ??? This mode check should perhaps look more like the mode check
9213 in simplify_comparison in combine. */
9221 && (STORE_FLAG_VALUE
9224 #ifdef FLOAT_STORE_FLAG_VALUE
9229 #endif
9230 ))
9241 && (STORE_FLAG_VALUE
9244 #ifdef FLOAT_STORE_FLAG_VALUE
9249 #endif
9250 ))
9256 {
9259 }
9260 else
9262 }
9265 /* If this sets OP0, but not directly, we have to give up. */
9269 {
9270 /* If the caller is expecting the condition to be valid at INSN,
9271 make sure X doesn't change before INSN. */
9278 {
9283 }
9288 }
9289 }
9291 /* If constant is first, put it last. */
9295 /* If OP0 is the result of a comparison, we weren't able to find what
9296 was really being compared, so fail. */
9301 /* Canonicalize any ordered comparison with integers involving equality
9302 if we can do computations in the relevant mode and we do not
9303 overflow. */
9309 {
9312 unsigned HOST_WIDE_INT max_val
9316 {
9322 /* When cross-compiling, const_val might be sign-extended from
9323 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9343 }
9344 }
9346 /* Never return CC0; return zero instead. */
9351 }
9353 /* Given a jump insn JUMP, return the condition that will cause it to branch
9354 to its JUMP_LABEL. If the condition cannot be understood, or is an
9355 inequality floating-point comparison which needs to be reversed, 0 will
9356 be returned.
9358 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9359 insn used in locating the condition was found. If a replacement test
9360 of the condition is desired, it should be placed in front of that
9361 insn and we will be sure that the inputs are still valid. If EARLIEST
9362 is null, the returned condition will be valid at INSN.
9364 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9365 compare CC mode register.
9367 VALID_AT_INSN_P is the same as for canonicalize_condition. */
9369 rtx
9371 {
9372 rtx cond;
9374 rtx set;
9376 /* If this is not a standard conditional jump, we can't parse it. */
9384 /* If this branches to JUMP_LABEL when the condition is false, reverse
9385 the condition. */
9386 reverse
9392 }
9394 /* Similar to above routine, except that we also put an invariant last
9395 unless both operands are invariants. */
9397 rtx
9399 {
9409 }
9411 /* Scan the function and determine whether it has indirect (computed) jumps.
9413 This is taken mostly from flow.c; similar code exists elsewhere
9414 in the compiler. It may be useful to put this into rtlanal.c. */
9415 static int
9417 {
9418 rtx insn;
9425 }
9427 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9428 documentation for LOOP_MEMS for the definition of `appropriate'.
9429 This function is called from prescan_loop via for_each_rtx. */
9431 static int
9433 {
9442 {
9447 /* We're not interested in MEMs that are only clobbered. */
9451 /* We're not interested in the MEM associated with a
9452 CONST_DOUBLE, so there's no need to traverse into this. */
9456 /* We're not interested in any MEMs that only appear in notes. */
9460 /* This is not a MEM. */
9462 }
9464 /* See if we've already seen this MEM. */
9467 {
9471 /* The modes of the two memory accesses are different. If
9472 this happens, something tricky is going on, and we just
9473 don't optimize accesses to this MEM. */
9477 }
9479 /* Resize the array, if necessary. */
9481 {
9484 else
9489 }
9491 /* Actually insert the MEM. */
9493 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9494 because we can't put it in a register. We still store it in the
9495 table, though, so that if we see the same address later, but in a
9496 non-BLK mode, we'll not think we can optimize it at that point. */
9502 }
9505 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9507 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9508 register that is modified by an insn between FROM and TO. If the
9509 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9510 more, stop incrementing it, to avoid overflow.
9512 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9513 register I is used, if it is only used once. Otherwise, it is set
9514 to 0 (for no uses) or const0_rtx for more than one use. This
9515 parameter may be zero, in which case this processing is not done.
9517 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9518 optimize register I. */
9520 static void
9522 {
9525 /* last_set[n] is nonzero iff reg n has been set in the current
9526 basic block. In that case, it is the insn that last set reg n. */
9528 rtx insn;
9534 /* Grow the regs array if not allocated or too small. */
9536 {
9541 /* Zero the new elements. */
9544 }
9546 /* Clear previously scanned fields but do not clear n_times_set. */
9548 {
9552 }
9556 /* Scan the loop, recording register usage. */
9559 {
9561 {
9562 /* Record registers that have exactly one use. */
9565 /* Include uses in REG_EQUAL notes. */
9573 {
9577 last_set);
9578 }
9579 }
9584 /* Invalidate all registers used for function argument passing.
9585 We check rtx_varies_p for the same reason as below, to allow
9586 optimizing PIC calculations. */
9588 {
9589 rtx link;
9591 link;
9593 {
9600 }
9601 }
9602 }
9604 /* Invalidate all hard registers clobbered by calls. With one exception:
9605 a call-clobbered PIC register is still function-invariant for our
9606 purposes, since we can hoist any PIC calculations out of the loop.
9607 Thus the call to rtx_varies_p. */
9612 {
9615 }
9617 #ifdef AVOID_CCMODE_COPIES
9618 /* Don't try to move insns which set CC registers if we should not
9619 create CCmode register copies. */
9623 #endif
9625 /* Set regs->array[I].n_times_set for the new registers. */
9630 }
9632 /* Returns the number of real INSNs in the LOOP. */
9634 static int
9636 {
9638 rtx insn;
9646 }
9648 /* Move MEMs into registers for the duration of the loop. */
9650 static void
9652 {
9659 rtx end_label;
9660 /* Nonzero if the next instruction may never be executed. */
9667 /* We cannot use next_label here because it skips over normal insns. */
9672 /* Check to see if it's possible that some instructions in the loop are
9673 never executed. Also check if there is a goto out of the loop other
9674 than right after the end of the loop. */
9678 {
9682 /* If we enter the loop in the middle, and scan
9683 around to the beginning, don't set maybe_never
9684 for that. This must be an unconditional jump,
9685 otherwise the code at the top of the loop might
9686 never be executed. Unconditional jumps are
9687 followed a by barrier then loop end. */
9692 {
9693 /* If this is a jump outside of the loop but not right
9694 after the end of the loop, we would have to emit new fixup
9695 sequences for each such label. */
9697 JUMP_INSN is executed, we must be conservative. */
9706 /* Something complicated. */
9708 else
9709 /* If there are any more instructions in the loop, they
9710 might not be reached. */
9712 }
9715 }
9717 /* Find start of the extended basic block that enters the loop. */
9721 ;
9726 /* Build table of mems that get set to constant values before the
9727 loop. */
9731 /* Actually move the MEMs. */
9733 {
9734 regset_head load_copies;
9735 regset_head store_copies;
9737 rtx reg;
9739 rtx mem_list_entry;
9743 /* There's no telling whether or not MEM is modified. */
9746 /* Go through the MEMs written to in the loop to see if this
9747 one is aliased by one of them. */
9750 {
9755 {
9756 /* MEM is indeed aliased by this store. */
9759 }
9761 }
9767 /* If this MEM is written to, we must be sure that there
9768 are no reads from another MEM that aliases this one. */
9770 {
9774 {
9778 VOIDmode,
9780 rtx_varies_p))
9781 {
9782 /* It's not safe to hoist loop_info->mems[i] out of
9783 the loop because writes to it might not be
9784 seen by reads from loop_info->mems[j]. */
9787 }
9788 }
9789 }
9792 /* We can't access the MEM outside the loop; it might
9793 cause a trap that wouldn't have happened otherwise. */
9797 /* We thought we were going to lift this MEM out of the
9798 loop, but later discovered that we could not. */
9804 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9805 order to keep scan_loop from moving stores to this MEM
9806 out of the loop just because this REG is neither a
9807 user-variable nor used in the loop test. */
9812 /* Now, replace all references to the MEM with the
9813 corresponding pseudos. */
9818 {
9820 {
9821 rtx set;
9825 /* See if this copies the mem into a register that isn't
9826 modified afterwards. We'll try to do copy propagation
9827 a little further on. */
9829 /* @@@ This test is _way_ too conservative. */
9830 && ! maybe_never
9838 /* See if this copies the mem from a register that isn't
9839 modified afterwards. We'll try to remove the
9840 redundant copy later on by doing a little register
9841 renaming and copy propagation. This will help
9842 to untangle things for the BIV detection code. */
9844 && ! maybe_never
9852 /* If this is a call which uses / clobbers this memory
9853 location, we must not change the interface here. */
9857 {
9861 }
9862 else
9863 /* Replace the memory reference with the shadow register. */
9866 }
9871 }
9876 /* We couldn't replace all occurrences of the MEM. */
9878 else
9879 {
9880 /* Load the memory immediately before LOOP->START, which is
9881 the NOTE_LOOP_BEG. */
9883 rtx set;
9889 {
9893 {
9897 /* Extending hard register lifetimes causes crash
9898 on SRC targets. Doing so on non-SRC is
9899 probably also not good idea, since we most
9900 probably have pseudoregister equivalence as
9901 well. */
9904 }
9905 /* Use the constant equivalence if that is cheap enough. */
9911 {
9914 }
9916 /* If best_equiv is nonzero, we know that MEM is set to a
9917 constant or register before the loop. We will use this
9918 knowledge to initialize the shadow register with that
9919 constant or reg rather than by loading from MEM. */
9922 }
9927 {
9930 {
9933 }
9934 }
9940 {
9942 {
9945 }
9947 /* Store the memory immediately after END, which is
9948 the NOTE_LOOP_END. */
9951 }
9954 {
9959 }
9961 /* Attempt a bit of copy propagation. This helps untangle the
9962 data flow, and enables {basic,general}_induction_var to find
9963 more bivs/givs. */
9964 EXECUTE_IF_SET_IN_REG_SET
9966 {
9968 });
9971 EXECUTE_IF_SET_IN_REG_SET
9973 {
9975 });
9977 }
9978 }
9980 /* Now, we need to replace all references to the previous exit
9981 label with the new one. */
9988 }
9990 /* For communication between note_reg_stored and its caller. */
9991 struct note_reg_stored_arg
9992 {
9994 rtx reg;
9995 };
9997 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9998 is equal to ARG. */
9999 static void
10001 {
10005 }
10007 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10008 There must be exactly one insn that sets this pseudo; it will be
10009 deleted if all replacements succeed and we can prove that the register
10010 is not used after the loop. */
10012 static void
10014 {
10015 /* This is the reg that we are copying from. */
10018 rtx insn;
10019 /* These help keep track of whether we replaced all uses of the reg. */
10026 {
10027 rtx set;
10029 /* Only substitute within one extended basic block from the initializing
10030 insn. */
10037 /* Is this the initializing insn? */
10042 {
10049 }
10051 /* Only substitute after seeing the initializing insn. */
10053 {
10060 /* Stop replacing when REPLACEMENT is modified. */
10065 {
10068 /* It is possible that we've turned previously valid REG_EQUAL to
10069 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10070 REPLACEMENT is modified, we get different meaning. */
10074 }
10075 }
10076 }
10080 {
10084 {
10085 rtx first;
10086 rtx retval_note;
10088 /* Assume we're just deleting INIT_INSN. */
10090 /* Look for REG_RETVAL note. If we're deleting the end of
10091 the libcall sequence, the whole sequence can go. */
10093 /* If we found a REG_RETVAL note, find the first instruction
10094 in the sequence. */
10098 /* Delete the instructions. */
10100 }
10103 }
10104 }
10106 /* Replace all the instructions from FIRST up to and including LAST
10107 with NOTE_INSN_DELETED notes. */
10109 static void
10111 {
10113 {
10119 /* If this was the LAST instructions we're supposed to delete,
10120 we're done. */
10125 }
10126 }
10128 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10129 loop LOOP if the order of the sets of these registers can be
10130 swapped. There must be exactly one insn within the loop that sets
10131 this pseudo followed immediately by a move insn that sets
10132 REPLACEMENT with REGNO. */
10133 static void
10136 {
10137 rtx insn;
10146 {
10147 /* Search for the insn that copies REGNO to NEW_REGNO? */
10155 }
10158 {
10159 rtx prev_insn;
10160 rtx prev_set;
10162 /* Some DEF-USE info would come in handy here to make this
10163 function more general. For now, just check the previous insn
10164 which is the most likely candidate for setting REGNO. */
10172 {
10173 /* We have:
10174 (set (reg regno) (expr))
10175 (set (reg new_regno) (reg regno))
10177 so try converting this to:
10178 (set (reg new_regno) (expr))
10179 (set (reg regno) (reg new_regno))
10181 The former construct is often generated when a global
10182 variable used for an induction variable is shadowed by a
10183 register (NEW_REGNO). The latter construct improves the
10184 chances of GIV replacement and BIV elimination. */
10194 {
10201 /* Update first use of REGNO. */
10205 /* Now perform copy propagation to hopefully
10206 remove all uses of REGNO within the loop. */
10208 }
10209 }
10210 }
10211 }
10213 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10215 static int
10217 {
10219 {
10223 }
10225 }
10227 /* Returns the first MEM found in NOTE by depth-first search. */
10229 static rtx
10231 {
10235 }
10237 /* Replace MEM with its associated pseudo register. This function is
10238 called from load_mems via for_each_rtx. DATA is actually a pointer
10239 to a structure describing the instruction currently being scanned
10240 and the MEM we are currently replacing. */
10242 static int
10244 {
10252 {
10257 /* We're not interested in the MEM associated with a
10258 CONST_DOUBLE, so there's no need to traverse into one. */
10262 /* This is not a MEM. */
10264 }
10267 /* This is not the MEM we are currently replacing. */
10270 /* Actually replace the MEM. */
10274 }
10276 static void
10278 {
10279 loop_replace_args args;
10287 /* If we hoist a mem write out of the loop, then REG_EQUAL
10288 notes referring to the mem are no longer valid. */
10290 {
10295 {
10299 {
10300 /* Remove the note. */
10303 }
10304 }
10305 }
10306 }
10308 /* Replace one register with another. Called through for_each_rtx; PX points
10309 to the rtx being scanned. DATA is actually a pointer to
10310 a structure of arguments. */
10312 static int
10314 {
10325 }
10327 static void
10329 {
10330 loop_replace_args args;
10337 }
10338 \f
10339 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10340 (ignored in the interim). */
10342 static rtx
10345 rtx pattern)
10346 {
10348 }
10351 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10352 in basic block WHERE_BB (ignored in the interim) within the loop
10353 otherwise hoist PATTERN into the loop pre-header. */
10355 rtx
10357 basic_block where_bb ATTRIBUTE_UNUSED,
10359 {
10363 }
10366 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10367 WHERE_BB (ignored in the interim) within the loop. */
10369 static rtx
10371 basic_block where_bb ATTRIBUTE_UNUSED,
10373 {
10375 }
10378 /* Hoist insn for PATTERN into the loop pre-header. */
10380 rtx
10382 {
10384 }
10387 /* Hoist call insn for PATTERN into the loop pre-header. */
10389 static rtx
10391 {
10393 }
10396 /* Sink insn for PATTERN after the loop end. */
10398 rtx
10400 {
10402 }
10404 /* bl->final_value can be either general_operand or PLUS of general_operand
10405 and constant. Emit sequence of instructions to load it into REG. */
10406 static rtx
10408 {
10409 rtx seq;
10417 }
10419 /* If the loop has multiple exits, emit insn for PATTERN before the
10420 loop to ensure that it will always be executed no matter how the
10421 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10422 since this is slightly more efficient. */
10424 static rtx
10426 {
10429 else
10431 }
10432 \f
10433 static void
10435 {
10443 iv_num++;
10448 {
10451 }
10452 }
10455 static void
10458 {
10460 rtx incr;
10471 {
10474 }
10476 {
10479 }
10483 {
10487 }
10490 {
10494 }
10496 /* List the increments. */
10498 {
10502 }
10504 /* List the givs. */
10506 {
10511 else
10514 }
10515 }
10518 static void
10520 {
10531 {
10535 }
10538 }
10541 static void
10543 {
10550 else
10566 {
10568 {
10580 }
10581 }
10592 {
10596 }
10599 }
10602 void
10604 {
10606 }
10609 void
10611 {
10613 }
10616 void
10618 {
10620 }
10623 void
10625 {
10627 }
10630 #define LOOP_BLOCK_NUM_1(INSN) \
10631 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10633 /* The notes do not have an assigned block, so look at the next insn. */
10634 #define LOOP_BLOCK_NUM(INSN) \
10635 ((INSN) ? (NOTE_P (INSN) \
10636 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10637 : LOOP_BLOCK_NUM_1 (INSN)) \
10638 : -1)
10640 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10642 static void
10645 {
10646 rtx label;
10651 /* Print diagnostics to compare our concept of a loop with
10652 what the loop notes say. */
10667 {
10681 {
10684 {
10687 }
10688 }
10690 }
10691 }
10693 /* Call this function from the debugger to dump LOOP. */
10695 void
10697 {
10699 }
10701 /* Call this function from the debugger to dump LOOPS. */
10703 void
10705 {
10707 }