1 ;; Predicate definitions for S/390 and zSeries.
2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; OP is the current operation.
23 ;; MODE is the current operation mode.
25 ;; operands --------------------------------------------------------------
27 ;; Return true if OP a const 0 operand (int/float/vector).
28 (define_predicate "const0_operand"
29 (and (match_code "const_int,const_wide_int,const_double,const_vector")
30 (match_test "op == CONST0_RTX (mode)")))
32 ;; Return true if OP an all ones operand (int/vector).
33 (define_predicate "all_ones_operand"
34 (and (match_code "const_int, const_wide_int, const_vector")
35 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
36 (match_test "op == CONSTM1_RTX (mode)")))
38 ;; Return true if OP is a 4 bit mask operand
39 (define_predicate "const_mask_operand"
40 (and (match_code "const_int")
41 (match_test "UINTVAL (op) < 16")))
43 ;; Return true if OP is constant.
45 (define_special_predicate "consttable_operand"
46 (and (match_code "symbol_ref, label_ref, const, const_int, const_wide_int, const_double, const_vector")
47 (match_test "CONSTANT_P (op)")))
49 ;; Return true if OP is a valid S-type operand.
51 (define_predicate "s_operand"
52 (and (match_code "subreg, mem")
53 (match_operand 0 "general_operand"))
55 /* Just like memory_operand, allow (subreg (mem ...))
58 && GET_CODE (op) == SUBREG
59 && GET_CODE (SUBREG_REG (op)) == MEM)
62 if (GET_CODE (op) != MEM)
64 if (!s390_legitimate_address_without_index_p (op))
70 ;; Return true if OP is a valid operand for the BRAS instruction.
71 ;; Allow SYMBOL_REFs and @PLT stubs.
73 (define_special_predicate "bras_sym_operand"
74 (ior (and (match_code "symbol_ref")
75 (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
76 (and (match_code "const")
77 (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
78 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
80 ;; Return true if OP is a PLUS that is not a legitimate
81 ;; operand for the LA instruction.
83 (define_predicate "s390_plus_operand"
84 (and (match_code "plus")
85 (and (match_test "mode == Pmode")
86 (match_test "!legitimate_la_operand_p (op)"))))
88 ;; Return true if OP is a valid operand as scalar shift count or setmem.
90 (define_predicate "setmem_operand"
91 (match_code "reg, subreg, plus, const_int")
96 if (GET_MODE (op) != VOIDmode
97 && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
100 /* Extract base register and offset. */
101 if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
104 /* Don't allow any non-base hard registers. Doing so without
105 confusing reload and/or regrename would be tricky, and doesn't
106 buy us much anyway. */
107 if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
110 /* Unfortunately we have to reject constants that are invalid
111 for an address, or else reload will get confused. */
112 if (!DISP_IN_RANGE (offset))
118 ; An integer operand with the lowest order 6 bits all ones.
119 (define_predicate "const_int_6bitset_operand"
120 (and (match_code "const_int")
121 (match_test "(INTVAL (op) & 63) == 63")))
122 (define_predicate "nonzero_shift_count_operand"
123 (and (match_code "const_int")
124 (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
126 ;; Return true if OP a valid operand for the LARL instruction.
128 (define_predicate "larl_operand"
129 (match_code "label_ref, symbol_ref, const")
131 /* Allow labels and local symbols. */
132 if (GET_CODE (op) == LABEL_REF)
134 if (GET_CODE (op) == SYMBOL_REF)
135 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
136 && SYMBOL_REF_TLS_MODEL (op) == 0
137 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
139 /* Everything else must have a CONST, so strip it. */
140 if (GET_CODE (op) != CONST)
144 /* Allow adding *even* in-range constants. */
145 if (GET_CODE (op) == PLUS)
147 if (GET_CODE (XEXP (op, 1)) != CONST_INT
148 || (INTVAL (XEXP (op, 1)) & 1) != 0)
150 if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
151 || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
156 /* Labels and local symbols allowed here as well. */
157 if (GET_CODE (op) == LABEL_REF)
159 if (GET_CODE (op) == SYMBOL_REF)
160 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
161 && SYMBOL_REF_TLS_MODEL (op) == 0
162 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
164 /* Now we must have a @GOTENT offset or @PLT stub
165 or an @INDNTPOFF TLS offset. */
166 if (GET_CODE (op) == UNSPEC
167 && XINT (op, 1) == UNSPEC_GOTENT)
169 if (GET_CODE (op) == UNSPEC
170 && XINT (op, 1) == UNSPEC_PLT)
172 if (GET_CODE (op) == UNSPEC
173 && XINT (op, 1) == UNSPEC_INDNTPOFF)
179 (define_predicate "contiguous_bitmask_operand"
180 (match_code "const_int")
182 return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
185 ;; Return true if OP is ligitimate for any LOC instruction.
187 (define_predicate "loc_operand"
188 (ior (match_operand 0 "nonimmediate_operand")
189 (and (match_code "const_int")
190 (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
192 ;; operators --------------------------------------------------------------
194 ;; Return nonzero if OP is a valid comparison operator
195 ;; for a branch condition.
197 (define_predicate "s390_comparison"
198 (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
199 uneq, unlt, ungt, unle, unge, ltgt,
202 if (GET_CODE (XEXP (op, 0)) != REG
203 || REGNO (XEXP (op, 0)) != CC_REGNUM
204 || (XEXP (op, 1) != const0_rtx
205 && !(CONST_INT_P (XEXP (op, 1))
206 && GET_MODE (XEXP (op, 0)) == CCRAWmode
207 && INTVAL (XEXP (op, 1)) >= 0
208 && INTVAL (XEXP (op, 1)) <= 15)))
211 return (s390_branch_condition_mask (op) >= 0);
214 ;; Return true if op is the cc register.
215 (define_predicate "cc_reg_operand"
216 (and (match_code "reg")
217 (match_test "REGNO (op) == CC_REGNUM")))
219 (define_predicate "s390_signed_integer_comparison"
220 (match_code "eq, ne, lt, gt, le, ge")
222 return (s390_compare_and_branch_condition_mask (op) >= 0);
225 (define_predicate "s390_unsigned_integer_comparison"
226 (match_code "eq, ne, ltu, gtu, leu, geu")
228 return (s390_compare_and_branch_condition_mask (op) >= 0);
231 ;; Return nonzero if OP is a valid comparison operator for the
232 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
233 (define_predicate "s390_eqne_operator"
234 (match_code "eq, ne"))
236 (define_predicate "s390_scond_operator"
237 (match_code "ltu, gtu, leu, geu"))
239 (define_predicate "s390_brx_operator"
240 (match_code "le, gt"))
242 ;; Return nonzero if OP is a valid comparison operator
243 ;; for an ALC condition.
245 (define_predicate "s390_alc_comparison"
246 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
248 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
251 if (!COMPARISON_P (op))
254 if (GET_CODE (XEXP (op, 0)) != REG
255 || REGNO (XEXP (op, 0)) != CC_REGNUM
256 || (XEXP (op, 1) != const0_rtx
257 && !(CONST_INT_P (XEXP (op, 1))
258 && GET_MODE (XEXP (op, 0)) == CCRAWmode
259 && INTVAL (XEXP (op, 1)) >= 0
260 && INTVAL (XEXP (op, 1)) <= 15)))
263 switch (GET_MODE (XEXP (op, 0)))
266 return GET_CODE (op) == LTU;
269 return GET_CODE (op) == LEU;
272 return GET_CODE (op) == GEU;
275 return GET_CODE (op) == GTU;
278 return GET_CODE (op) == LTU;
281 return GET_CODE (op) == UNGT;
284 return GET_CODE (op) == UNLT;
291 ;; Return nonzero if OP is a valid comparison operator
292 ;; for an SLB condition.
294 (define_predicate "s390_slb_comparison"
295 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
297 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
300 if (!COMPARISON_P (op))
303 if (GET_CODE (XEXP (op, 0)) != REG
304 || REGNO (XEXP (op, 0)) != CC_REGNUM
305 || XEXP (op, 1) != const0_rtx)
308 switch (GET_MODE (XEXP (op, 0)))
311 return GET_CODE (op) == GEU;
314 return GET_CODE (op) == GTU;
317 return GET_CODE (op) == LTU;
320 return GET_CODE (op) == LEU;
323 return GET_CODE (op) == GEU;
326 return GET_CODE (op) == LE;
329 return GET_CODE (op) == GE;
336 ;; Return true if OP is a load multiple operation. It is known to be a
337 ;; PARALLEL and the first section will be tested.
339 (define_special_predicate "load_multiple_operation"
340 (match_code "parallel")
342 machine_mode elt_mode;
343 int count = XVECLEN (op, 0);
344 unsigned int dest_regno;
348 /* Perform a quick check so we don't blow up below. */
350 || GET_CODE (XVECEXP (op, 0, 0)) != SET
351 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
352 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
355 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
356 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
357 elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
359 /* Check, is base, or base + displacement. */
361 if (GET_CODE (src_addr) == REG)
363 else if (GET_CODE (src_addr) == PLUS
364 && GET_CODE (XEXP (src_addr, 0)) == REG
365 && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
367 off = INTVAL (XEXP (src_addr, 1));
368 src_addr = XEXP (src_addr, 0);
373 for (i = 1; i < count; i++)
375 rtx elt = XVECEXP (op, 0, i);
377 if (GET_CODE (elt) != SET
378 || GET_CODE (SET_DEST (elt)) != REG
379 || GET_MODE (SET_DEST (elt)) != elt_mode
380 || REGNO (SET_DEST (elt)) != dest_regno + i
381 || GET_CODE (SET_SRC (elt)) != MEM
382 || GET_MODE (SET_SRC (elt)) != elt_mode
383 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
384 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
385 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
386 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
387 != off + i * GET_MODE_SIZE (elt_mode))
394 ;; For an execute pattern the target instruction is embedded into the
395 ;; RTX but will not get checked for validity by recog automatically.
396 ;; The execute_operation predicate extracts the target RTX and invokes
398 (define_special_predicate "execute_operation"
399 (match_code "parallel")
405 /* This is redundant but since this predicate is evaluated
406 first when recognizing the insn we can prevent the more
407 expensive code below from being executed for many cases. */
408 if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
409 || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
412 /* Keep in sync with s390_execute_target. */
413 if (XVECLEN (pattern, 0) == 2)
415 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
419 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
422 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
423 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
425 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
428 /* Since we do not have the wrapping insn here we have to build one. */
429 insn = make_insn_raw (pattern);
430 icode = recog_memoized (insn);
434 extract_constrain_insn (insn);
436 return which_alternative >= 0;
439 ;; Return true if OP is a store multiple operation. It is known to be a
440 ;; PARALLEL and the first section will be tested.
442 (define_special_predicate "store_multiple_operation"
443 (match_code "parallel")
445 machine_mode elt_mode;
446 int count = XVECLEN (op, 0);
447 unsigned int src_regno;
451 /* Perform a quick check so we don't blow up below. */
453 || GET_CODE (XVECEXP (op, 0, 0)) != SET
454 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
455 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
458 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
459 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
460 elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
462 /* Check, is base, or base + displacement. */
464 if (GET_CODE (dest_addr) == REG)
466 else if (GET_CODE (dest_addr) == PLUS
467 && GET_CODE (XEXP (dest_addr, 0)) == REG
468 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
470 off = INTVAL (XEXP (dest_addr, 1));
471 dest_addr = XEXP (dest_addr, 0);
476 for (i = 1; i < count; i++)
478 rtx elt = XVECEXP (op, 0, i);
480 if (GET_CODE (elt) != SET
481 || GET_CODE (SET_SRC (elt)) != REG
482 || GET_MODE (SET_SRC (elt)) != elt_mode
483 || REGNO (SET_SRC (elt)) != src_regno + i
484 || GET_CODE (SET_DEST (elt)) != MEM
485 || GET_MODE (SET_DEST (elt)) != elt_mode
486 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
487 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
488 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
489 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
490 != off + i * GET_MODE_SIZE (elt_mode))