1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2016 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 (define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
41 (define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
45 (define_predicate "imm_for_neon_logic_operand"
46 (match_code "const_vector")
49 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
52 (define_predicate "neon_logic_op2"
53 (ior (match_operand 0 "imm_for_neon_logic_operand")
54 (match_operand 0 "s_register_operand")))
56 ;; Any general register.
57 (define_predicate "arm_hard_general_register_operand"
60 return REGNO (op) <= LAST_ARM_REGNUM;
64 (define_predicate "low_register_operand"
65 (and (match_code "reg")
66 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
68 ;; A low register or const_int.
69 (define_predicate "low_reg_or_int_operand"
70 (ior (match_code "const_int")
71 (match_operand 0 "low_register_operand")))
73 ;; Any core register, or any pseudo. */
74 (define_predicate "arm_general_register_operand"
75 (match_code "reg,subreg")
77 if (GET_CODE (op) == SUBREG)
81 && (REGNO (op) <= LAST_ARM_REGNUM
82 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
85 (define_predicate "vfp_register_operand"
86 (match_code "reg,subreg")
88 if (GET_CODE (op) == SUBREG)
91 /* We don't consider registers whose class is NO_REGS
92 to be a register operand. */
94 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
95 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
96 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
98 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
101 (define_predicate "vfp_hard_register_operand"
104 return (IS_VFP_REGNUM (REGNO (op)));
107 (define_predicate "zero_operand"
108 (and (match_code "const_int,const_double,const_vector")
109 (match_test "op == CONST0_RTX (mode)")))
111 ;; Match a register, or zero in the appropriate mode.
112 (define_predicate "reg_or_zero_operand"
113 (ior (match_operand 0 "s_register_operand")
114 (match_operand 0 "zero_operand")))
116 (define_special_predicate "subreg_lowpart_operator"
117 (and (match_code "subreg")
118 (match_test "subreg_lowpart_p (op)")))
120 ;; Reg, subreg(reg) or const_int.
121 (define_predicate "reg_or_int_operand"
122 (ior (match_code "const_int")
123 (match_operand 0 "s_register_operand")))
125 (define_predicate "arm_immediate_operand"
126 (and (match_code "const_int")
127 (match_test "const_ok_for_arm (INTVAL (op))")))
129 ;; A constant value which fits into two instructions, each taking
130 ;; an arithmetic constant operand for one of the words.
131 (define_predicate "arm_immediate_di_operand"
132 (and (match_code "const_int,const_double")
133 (match_test "arm_const_double_by_immediates (op)")))
135 (define_predicate "arm_neg_immediate_operand"
136 (and (match_code "const_int")
137 (match_test "const_ok_for_arm (-INTVAL (op))")))
139 (define_predicate "arm_not_immediate_operand"
140 (and (match_code "const_int")
141 (match_test "const_ok_for_arm (~INTVAL (op))")))
143 (define_predicate "const0_operand"
144 (match_test "op == CONST0_RTX (mode)"))
146 ;; Something valid on the RHS of an ARM data-processing instruction
147 (define_predicate "arm_rhs_operand"
148 (ior (match_operand 0 "s_register_operand")
149 (match_operand 0 "arm_immediate_operand")))
151 (define_predicate "arm_rhsm_operand"
152 (ior (match_operand 0 "arm_rhs_operand")
153 (match_operand 0 "memory_operand")))
155 (define_predicate "const_int_I_operand"
156 (and (match_operand 0 "const_int_operand")
157 (match_test "satisfies_constraint_I (op)")))
159 (define_predicate "const_int_M_operand"
160 (and (match_operand 0 "const_int_operand")
161 (match_test "satisfies_constraint_M (op)")))
163 ;; This doesn't have to do much because the constant is already checked
164 ;; in the shift_operator predicate.
165 (define_predicate "shift_amount_operand"
166 (ior (and (match_test "TARGET_ARM")
167 (match_operand 0 "s_register_operand"))
168 (match_operand 0 "const_int_operand")))
170 (define_predicate "const_neon_scalar_shift_amount_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
174 (define_predicate "ldrd_strd_offset_operand"
175 (and (match_operand 0 "const_int_operand")
176 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
178 (define_predicate "arm_add_operand"
179 (ior (match_operand 0 "arm_rhs_operand")
180 (match_operand 0 "arm_neg_immediate_operand")))
182 (define_predicate "arm_anddi_operand_neon"
183 (ior (match_operand 0 "s_register_operand")
184 (and (match_code "const_int")
185 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
186 (match_operand 0 "neon_inv_logic_op2")))
188 (define_predicate "arm_iordi_operand_neon"
189 (ior (match_operand 0 "s_register_operand")
190 (and (match_code "const_int")
191 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
192 (match_operand 0 "neon_logic_op2")))
194 (define_predicate "arm_xordi_operand"
195 (ior (match_operand 0 "s_register_operand")
196 (and (match_code "const_int")
197 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
199 (define_predicate "arm_adddi_operand"
200 (ior (match_operand 0 "s_register_operand")
201 (and (match_code "const_int")
202 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
204 (define_predicate "arm_addimm_operand"
205 (ior (match_operand 0 "arm_immediate_operand")
206 (match_operand 0 "arm_neg_immediate_operand")))
208 (define_predicate "arm_not_operand"
209 (ior (match_operand 0 "arm_rhs_operand")
210 (match_operand 0 "arm_not_immediate_operand")))
212 (define_predicate "arm_di_operand"
213 (ior (match_operand 0 "s_register_operand")
214 (match_operand 0 "arm_immediate_di_operand")))
216 ;; True if the operand is a memory reference which contains an
217 ;; offsettable address.
218 (define_predicate "offsettable_memory_operand"
219 (and (match_code "mem")
221 "offsettable_address_p (reload_completed | reload_in_progress,
222 mode, XEXP (op, 0))")))
224 ;; True if the operand is a memory operand that does not have an
225 ;; automodified base register (and thus will not generate output reloads).
226 (define_predicate "call_memory_operand"
227 (and (match_code "mem")
228 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
230 (match_operand 0 "memory_operand"))))
232 (define_predicate "arm_reload_memory_operand"
233 (and (match_code "mem,reg,subreg")
234 (match_test "(!CONSTANT_P (op)
235 && (true_regnum(op) == -1
237 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
239 (define_predicate "vfp_compare_operand"
240 (ior (match_operand 0 "s_register_operand")
241 (and (match_code "const_double")
242 (match_test "arm_const_double_rtx (op)"))))
244 (define_predicate "arm_float_compare_operand"
245 (if_then_else (match_test "TARGET_VFP")
246 (match_operand 0 "vfp_compare_operand")
247 (match_operand 0 "s_register_operand")))
249 ;; True for valid index operands.
250 (define_predicate "index_operand"
251 (ior (match_operand 0 "s_register_operand")
252 (and (match_operand 0 "immediate_operand")
253 (match_test "(!CONST_INT_P (op)
254 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
256 ;; True for operators that can be combined with a shift in ARM state.
257 (define_special_predicate "shiftable_operator"
258 (and (match_code "plus,minus,ior,xor,and")
259 (match_test "mode == GET_MODE (op)")))
261 (define_special_predicate "shiftable_operator_strict_it"
262 (and (match_code "plus,and")
263 (match_test "mode == GET_MODE (op)")))
265 ;; True for logical binary operators.
266 (define_special_predicate "logical_binary_operator"
267 (and (match_code "ior,xor,and")
268 (match_test "mode == GET_MODE (op)")))
270 ;; True for commutative operators
271 (define_special_predicate "commutative_binary_operator"
272 (and (match_code "ior,xor,and,plus")
273 (match_test "mode == GET_MODE (op)")))
275 ;; True for shift operators.
277 ;; * mult is only permitted with a constant shift amount
278 ;; * patterns that permit register shift amounts only in ARM mode use
279 ;; shift_amount_operand, patterns that always allow registers do not,
280 ;; so we don't have to worry about that sort of thing here.
281 (define_special_predicate "shift_operator"
282 (and (ior (ior (and (match_code "mult")
283 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
284 (and (match_code "rotate")
285 (match_test "CONST_INT_P (XEXP (op, 1))
286 && (UINTVAL (XEXP (op, 1))) < 32")))
287 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
288 (match_test "!CONST_INT_P (XEXP (op, 1))
289 || (UINTVAL (XEXP (op, 1))) < 32")))
290 (match_test "mode == GET_MODE (op)")))
292 (define_special_predicate "shift_nomul_operator"
293 (and (ior (and (match_code "rotate")
294 (match_test "CONST_INT_P (XEXP (op, 1))
295 && (UINTVAL (XEXP (op, 1))) < 32"))
296 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
297 (match_test "!CONST_INT_P (XEXP (op, 1))
298 || (UINTVAL (XEXP (op, 1))) < 32")))
299 (match_test "mode == GET_MODE (op)")))
301 ;; True for shift operators which can be used with saturation instructions.
302 (define_special_predicate "sat_shift_operator"
303 (and (ior (and (match_code "mult")
304 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
305 (and (match_code "ashift,ashiftrt")
306 (match_test "CONST_INT_P (XEXP (op, 1))
307 && (UINTVAL (XEXP (op, 1)) < 32)")))
308 (match_test "mode == GET_MODE (op)")))
310 ;; True for MULT, to identify which variant of shift_operator is in use.
311 (define_special_predicate "mult_operator"
314 ;; True for operators that have 16-bit thumb variants. */
315 (define_special_predicate "thumb_16bit_operator"
316 (match_code "plus,minus,and,ior,xor"))
319 (define_special_predicate "equality_operator"
320 (match_code "eq,ne"))
322 ;; True for integer comparisons and, if FP is active, for comparisons
323 ;; other than LTGT or UNEQ.
324 (define_special_predicate "expandable_comparison_operator"
325 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
326 unordered,ordered,unlt,unle,unge,ungt"))
328 ;; Likewise, but only accept comparisons that are directly supported
329 ;; by ARM condition codes.
330 (define_special_predicate "arm_comparison_operator"
331 (and (match_operand 0 "expandable_comparison_operator")
332 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
334 ;; Likewise, but don't ignore the mode.
335 ;; RTL SET operations require their operands source and destination have
336 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
337 (define_predicate "arm_comparison_operator_mode"
338 (and (match_operand 0 "expandable_comparison_operator")
339 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
341 (define_special_predicate "lt_ge_comparison_operator"
342 (match_code "lt,ge"))
344 ;; The vsel instruction only accepts the ARM condition codes listed below.
345 (define_special_predicate "arm_vsel_comparison_operator"
346 (and (match_operand 0 "expandable_comparison_operator")
347 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
348 || maybe_get_arm_condition_code (op) == ARM_GT
349 || maybe_get_arm_condition_code (op) == ARM_EQ
350 || maybe_get_arm_condition_code (op) == ARM_VS
351 || maybe_get_arm_condition_code (op) == ARM_LT
352 || maybe_get_arm_condition_code (op) == ARM_LE
353 || maybe_get_arm_condition_code (op) == ARM_NE
354 || maybe_get_arm_condition_code (op) == ARM_VC")))
356 (define_special_predicate "arm_cond_move_operator"
357 (if_then_else (match_test "arm_restrict_it")
358 (and (match_test "TARGET_FPU_ARMV8")
359 (match_operand 0 "arm_vsel_comparison_operator"))
360 (match_operand 0 "expandable_comparison_operator")))
362 (define_special_predicate "noov_comparison_operator"
363 (match_code "lt,ge,eq,ne"))
365 (define_special_predicate "minmax_operator"
366 (and (match_code "smin,smax,umin,umax")
367 (match_test "mode == GET_MODE (op)")))
369 (define_special_predicate "cc_register"
370 (and (match_code "reg")
371 (and (match_test "REGNO (op) == CC_REGNUM")
372 (ior (match_test "mode == GET_MODE (op)")
373 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
375 (define_special_predicate "dominant_cc_register"
378 if (mode == VOIDmode)
380 mode = GET_MODE (op);
382 if (GET_MODE_CLASS (mode) != MODE_CC)
386 return (cc_register (op, mode)
387 && (mode == CC_DNEmode
388 || mode == CC_DEQmode
389 || mode == CC_DLEmode
390 || mode == CC_DLTmode
391 || mode == CC_DGEmode
392 || mode == CC_DGTmode
393 || mode == CC_DLEUmode
394 || mode == CC_DLTUmode
395 || mode == CC_DGEUmode
396 || mode == CC_DGTUmode));
399 (define_special_predicate "arm_extendqisi_mem_op"
400 (and (match_operand 0 "memory_operand")
401 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
405 : memory_address_p (QImode, XEXP (op, 0))")))
407 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
408 (ior (match_operand 0 "arm_extendqisi_mem_op")
409 (match_operand 0 "s_register_operand")))
411 (define_predicate "power_of_two_operand"
412 (match_code "const_int")
414 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
416 return value != 0 && (value & (value - 1)) == 0;
419 (define_predicate "nonimmediate_di_operand"
420 (match_code "reg,subreg,mem")
422 if (s_register_operand (op, mode))
425 if (GET_CODE (op) == SUBREG)
426 op = SUBREG_REG (op);
428 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
431 (define_predicate "di_operand"
432 (ior (match_code "const_int,const_double")
433 (and (match_code "reg,subreg,mem")
434 (match_operand 0 "nonimmediate_di_operand"))))
436 (define_predicate "nonimmediate_soft_df_operand"
437 (match_code "reg,subreg,mem")
439 if (s_register_operand (op, mode))
442 if (GET_CODE (op) == SUBREG)
443 op = SUBREG_REG (op);
445 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
448 (define_predicate "soft_df_operand"
449 (ior (match_code "const_double")
450 (and (match_code "reg,subreg,mem")
451 (match_operand 0 "nonimmediate_soft_df_operand"))))
453 (define_special_predicate "load_multiple_operation"
454 (match_code "parallel")
456 return ldm_stm_operation_p (op, /*load=*/true, SImode,
457 /*consecutive=*/false,
458 /*return_pc=*/false);
461 (define_special_predicate "store_multiple_operation"
462 (match_code "parallel")
464 return ldm_stm_operation_p (op, /*load=*/false, SImode,
465 /*consecutive=*/false,
466 /*return_pc=*/false);
469 (define_special_predicate "pop_multiple_return"
470 (match_code "parallel")
472 return ldm_stm_operation_p (op, /*load=*/true, SImode,
473 /*consecutive=*/false,
477 (define_special_predicate "pop_multiple_fp"
478 (match_code "parallel")
480 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
481 /*consecutive=*/true,
482 /*return_pc=*/false);
485 (define_special_predicate "multi_register_push"
486 (match_code "parallel")
488 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
489 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
490 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
496 (define_predicate "push_mult_memory_operand"
499 /* ??? Given how PUSH_MULT is generated in the prologues, is there
500 any point in testing for thumb1 specially? All of the variants
501 use the same form. */
504 /* ??? No attempt is made to represent STMIA, or validate that
505 the stack adjustment matches the register count. This is
506 true of the ARM/Thumb2 path as well. */
507 rtx x = XEXP (op, 0);
508 if (GET_CODE (x) != PRE_MODIFY)
510 if (XEXP (x, 0) != stack_pointer_rtx)
513 if (GET_CODE (x) != PLUS)
515 if (XEXP (x, 0) != stack_pointer_rtx)
517 return CONST_INT_P (XEXP (x, 1));
520 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
521 return memory_operand (op, mode);
524 ;;-------------------------------------------------------------------------
529 (define_predicate "thumb1_cmp_operand"
530 (ior (and (match_code "reg,subreg")
531 (match_operand 0 "s_register_operand"))
532 (and (match_code "const_int")
533 (match_test "(UINTVAL (op)) < 256"))))
535 (define_predicate "thumb1_cmpneg_operand"
536 (and (match_code "const_int")
537 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
539 ;; Return TRUE if a result can be stored in OP without clobbering the
540 ;; condition code register. Prior to reload we only accept a
541 ;; register. After reload we have to be able to handle memory as
542 ;; well, since a pseudo may not get a hard reg and reload cannot
543 ;; handle output-reloads on jump insns.
545 ;; We could possibly handle mem before reload as well, but that might
546 ;; complicate things with the need to handle increment
548 (define_predicate "thumb_cbrch_target_operand"
549 (and (match_code "reg,subreg,mem")
550 (ior (match_operand 0 "s_register_operand")
551 (and (match_test "reload_in_progress || reload_completed")
552 (match_operand 0 "memory_operand")))))
554 ;;-------------------------------------------------------------------------
559 (define_predicate "imm_or_reg_operand"
560 (ior (match_operand 0 "immediate_operand")
561 (match_operand 0 "register_operand")))
565 (define_predicate "const_multiple_of_8_operand"
566 (match_code "const_int")
568 unsigned HOST_WIDE_INT val = INTVAL (op);
569 return (val & 7) == 0;
572 (define_predicate "imm_for_neon_mov_operand"
573 (match_code "const_vector,const_int")
575 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
578 (define_predicate "imm_for_neon_lshift_operand"
579 (match_code "const_vector")
581 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
584 (define_predicate "imm_for_neon_rshift_operand"
585 (match_code "const_vector")
587 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
590 (define_predicate "imm_lshift_or_reg_neon"
591 (ior (match_operand 0 "s_register_operand")
592 (match_operand 0 "imm_for_neon_lshift_operand")))
594 (define_predicate "imm_rshift_or_reg_neon"
595 (ior (match_operand 0 "s_register_operand")
596 (match_operand 0 "imm_for_neon_rshift_operand")))
598 ;; Predicates for named expanders that overlap multiple ISAs.
600 (define_predicate "cmpdi_operand"
601 (and (match_test "TARGET_32BIT")
602 (match_operand 0 "arm_di_operand")))
604 ;; True if the operand is memory reference suitable for a ldrex/strex.
605 (define_predicate "arm_sync_memory_operand"
606 (and (match_operand 0 "memory_operand")
607 (match_code "reg" "0")))
609 ;; Predicates for parallel expanders based on mode.
610 (define_special_predicate "vect_par_constant_high"
611 (match_code "parallel")
613 return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
616 (define_special_predicate "vect_par_constant_low"
617 (match_code "parallel")
619 return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
622 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
623 (and (match_code "const_double")
624 (match_test "TARGET_32BIT && TARGET_VFP
625 && vfp3_const_double_for_fract_bits (op)")))
627 (define_predicate "const_double_vcvt_power_of_two"
628 (and (match_code "const_double")
629 (match_test "TARGET_32BIT && TARGET_VFP
630 && vfp3_const_double_for_bits (op) > 0")))
632 (define_predicate "neon_struct_operand"
633 (and (match_code "mem")
634 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
636 (define_predicate "neon_permissive_struct_operand"
637 (and (match_code "mem")
638 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
640 (define_predicate "neon_perm_struct_or_reg_operand"
641 (ior (match_operand 0 "neon_permissive_struct_operand")
642 (match_operand 0 "s_register_operand")))
644 (define_special_predicate "add_operator"
647 (define_predicate "mem_noofs_operand"
648 (and (match_code "mem")
649 (match_code "reg" "0")))
651 (define_predicate "call_insn_operand"
652 (ior (and (match_code "symbol_ref")
653 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
654 (match_operand 0 "s_register_operand")))