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Merged with mainline at revision 126347.
[official-gcc.git] / gcc / longlong.h
blobb96e8bbb640d983bb22c492f8c301deb36f48fc3
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004,
3 2005 Free Software Foundation, Inc.
4
5 This definition file is free software; you can redistribute it
6 and/or modify it under the terms of the GNU General Public
7 License as published by the Free Software Foundation; either
8 version 2, or (at your option) any later version.
9
10 This definition file is distributed in the hope that it will be
11 useful, but WITHOUT ANY WARRANTY; without even the implied
12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 See the GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin Street, Fifth Floor,
18 Boston, MA 02110-1301, USA. */
19
20 /* You have to define the following before including this file:
21
22 UWtype -- An unsigned type, default type for operations (typically a "word")
23 UHWtype -- An unsigned type, at least half the size of UWtype.
24 UDWtype -- An unsigned type, at least twice as large a UWtype
25 W_TYPE_SIZE -- size in bits of UWtype
26
27 UQItype -- Unsigned 8 bit type.
28 SItype, USItype -- Signed and unsigned 32 bit types.
29 DItype, UDItype -- Signed and unsigned 64 bit types.
30
31 On a 32 bit machine UWtype should typically be USItype;
32 on a 64 bit machine, UWtype should typically be UDItype. */
33
34 #define __BITS4 (W_TYPE_SIZE / 4)
35 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
36 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
37 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
38
39 #ifndef W_TYPE_SIZE
40 #define W_TYPE_SIZE 32
41 #define UWtype USItype
42 #define UHWtype USItype
43 #define UDWtype UDItype
44 #endif
45
46 extern const UQItype __clz_tab[256];
47
48 /* Define auxiliary asm macros.
49
50 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
51 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
52 word product in HIGH_PROD and LOW_PROD.
53
54 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
55 UDWtype product. This is just a variant of umul_ppmm.
56
57 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
58 denominator) divides a UDWtype, composed by the UWtype integers
59 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
60 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
61 than DENOMINATOR for correct operation. If, in addition, the most
62 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
63 UDIV_NEEDS_NORMALIZATION is defined to 1.
64
65 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
66 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
67 is rounded towards 0.
68
69 5) count_leading_zeros(count, x) counts the number of zero-bits from the
70 msb to the first nonzero bit in the UWtype X. This is the number of
71 steps X needs to be shifted left to set the msb. Undefined for X == 0,
72 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
73
74 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
75 from the least significant end.
76
77 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
78 high_addend_2, low_addend_2) adds two UWtype integers, composed by
79 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
80 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
81 (i.e. carry out) is not stored anywhere, and is lost.
82
83 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
84 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
85 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
86 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
87 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
88 and is lost.
89
90 If any of these macros are left undefined for a particular CPU,
91 C macros are used. */
92
93 /* The CPUs come in alphabetical order below.
94
95 Please add support for more CPUs here, or improve the current support
96 for the CPUs below!
97 (E.g. WE32100, IBM360.) */
98
99 #if defined (__GNUC__) && !defined (NO_ASM)
100
101 /* We sometimes need to clobber "cc" with gcc2, but that would not be
102 understood by gcc1. Use cpp to avoid major code duplication. */
103 #if __GNUC__ < 2
104 #define __CLOBBER_CC
105 #define __AND_CLOBBER_CC
106 #else /* __GNUC__ >= 2 */
107 #define __CLOBBER_CC : "cc"
108 #define __AND_CLOBBER_CC , "cc"
109 #endif /* __GNUC__ < 2 */
110
111 #if defined (__alpha) && W_TYPE_SIZE == 64
112 #define umul_ppmm(ph, pl, m0, m1) \
113 do { \
114 UDItype __m0 = (m0), __m1 = (m1); \
115 (ph) = __builtin_alpha_umulh (__m0, __m1); \
116 (pl) = __m0 * __m1; \
117 } while (0)
118 #define UMUL_TIME 46
119 #ifndef LONGLONG_STANDALONE
120 #define udiv_qrnnd(q, r, n1, n0, d) \
121 do { UDItype __r; \
122 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
123 (r) = __r; \
124 } while (0)
125 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
126 #define UDIV_TIME 220
127 #endif /* LONGLONG_STANDALONE */
128 #ifdef __alpha_cix__
129 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
130 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
131 #define COUNT_LEADING_ZEROS_0 64
132 #else
133 #define count_leading_zeros(COUNT,X) \
134 do { \
135 UDItype __xr = (X), __t, __a; \
136 __t = __builtin_alpha_cmpbge (0, __xr); \
137 __a = __clz_tab[__t ^ 0xff] - 1; \
138 __t = __builtin_alpha_extbl (__xr, __a); \
139 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
140 } while (0)
141 #define count_trailing_zeros(COUNT,X) \
142 do { \
143 UDItype __xr = (X), __t, __a; \
144 __t = __builtin_alpha_cmpbge (0, __xr); \
145 __t = ~__t & -~__t; \
146 __a = ((__t & 0xCC) != 0) * 2; \
147 __a += ((__t & 0xF0) != 0) * 4; \
148 __a += ((__t & 0xAA) != 0); \
149 __t = __builtin_alpha_extbl (__xr, __a); \
150 __a <<= 3; \
151 __t &= -__t; \
152 __a += ((__t & 0xCC) != 0) * 2; \
153 __a += ((__t & 0xF0) != 0) * 4; \
154 __a += ((__t & 0xAA) != 0); \
155 (COUNT) = __a; \
156 } while (0)
157 #endif /* __alpha_cix__ */
158 #endif /* __alpha */
159
160 #if defined (__arc__) && W_TYPE_SIZE == 32
161 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
162 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
163 : "=r" ((USItype) (sh)), \
164 "=&r" ((USItype) (sl)) \
165 : "%r" ((USItype) (ah)), \
166 "rIJ" ((USItype) (bh)), \
167 "%r" ((USItype) (al)), \
168 "rIJ" ((USItype) (bl)))
169 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
170 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
171 : "=r" ((USItype) (sh)), \
172 "=&r" ((USItype) (sl)) \
173 : "r" ((USItype) (ah)), \
174 "rIJ" ((USItype) (bh)), \
175 "r" ((USItype) (al)), \
176 "rIJ" ((USItype) (bl)))
177 /* Call libgcc routine. */
178 #define umul_ppmm(w1, w0, u, v) \
179 do { \
180 DWunion __w; \
181 __w.ll = __umulsidi3 (u, v); \
182 w1 = __w.s.high; \
183 w0 = __w.s.low; \
184 } while (0)
185 #define __umulsidi3 __umulsidi3
186 UDItype __umulsidi3 (USItype, USItype);
187 #endif
188
189 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
191 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
192 : "=r" ((USItype) (sh)), \
193 "=&r" ((USItype) (sl)) \
194 : "%r" ((USItype) (ah)), \
195 "rI" ((USItype) (bh)), \
196 "%r" ((USItype) (al)), \
197 "rI" ((USItype) (bl)) __CLOBBER_CC)
198 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
199 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
200 : "=r" ((USItype) (sh)), \
201 "=&r" ((USItype) (sl)) \
202 : "r" ((USItype) (ah)), \
203 "rI" ((USItype) (bh)), \
204 "r" ((USItype) (al)), \
205 "rI" ((USItype) (bl)) __CLOBBER_CC)
206 #define umul_ppmm(xh, xl, a, b) \
207 {register USItype __t0, __t1, __t2; \
208 __asm__ ("%@ Inlined umul_ppmm\n" \
209 " mov %2, %5, lsr #16\n" \
210 " mov %0, %6, lsr #16\n" \
211 " bic %3, %5, %2, lsl #16\n" \
212 " bic %4, %6, %0, lsl #16\n" \
213 " mul %1, %3, %4\n" \
214 " mul %4, %2, %4\n" \
215 " mul %3, %0, %3\n" \
216 " mul %0, %2, %0\n" \
217 " adds %3, %4, %3\n" \
218 " addcs %0, %0, #65536\n" \
219 " adds %1, %1, %3, lsl #16\n" \
220 " adc %0, %0, %3, lsr #16" \
221 : "=&r" ((USItype) (xh)), \
222 "=r" ((USItype) (xl)), \
223 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
224 : "r" ((USItype) (a)), \
225 "r" ((USItype) (b)) __CLOBBER_CC );}
226 #define UMUL_TIME 20
227 #define UDIV_TIME 100
228 #endif /* __arm__ */
229
230 #if defined (__hppa) && W_TYPE_SIZE == 32
231 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
232 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
233 : "=r" ((USItype) (sh)), \
234 "=&r" ((USItype) (sl)) \
235 : "%rM" ((USItype) (ah)), \
236 "rM" ((USItype) (bh)), \
237 "%rM" ((USItype) (al)), \
238 "rM" ((USItype) (bl)))
239 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
240 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
241 : "=r" ((USItype) (sh)), \
242 "=&r" ((USItype) (sl)) \
243 : "rM" ((USItype) (ah)), \
244 "rM" ((USItype) (bh)), \
245 "rM" ((USItype) (al)), \
246 "rM" ((USItype) (bl)))
247 #if defined (_PA_RISC1_1)
248 #define umul_ppmm(w1, w0, u, v) \
249 do { \
250 union \
251 { \
252 UDItype __f; \
253 struct {USItype __w1, __w0;} __w1w0; \
254 } __t; \
255 __asm__ ("xmpyu %1,%2,%0" \
256 : "=x" (__t.__f) \
257 : "x" ((USItype) (u)), \
258 "x" ((USItype) (v))); \
259 (w1) = __t.__w1w0.__w1; \
260 (w0) = __t.__w1w0.__w0; \
261 } while (0)
262 #define UMUL_TIME 8
263 #else
264 #define UMUL_TIME 30
265 #endif
266 #define UDIV_TIME 40
267 #define count_leading_zeros(count, x) \
268 do { \
269 USItype __tmp; \
270 __asm__ ( \
271 "ldi 1,%0\n" \
272 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
273 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
274 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
275 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
276 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
277 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
278 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
279 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
280 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
281 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
282 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
283 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
284 " extru %1,30,1,%1 ; Extract bit 1.\n" \
285 " sub %0,%1,%0 ; Subtract it.\n" \
286 : "=r" (count), "=r" (__tmp) : "1" (x)); \
287 } while (0)
288 #endif
289
290 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
291 #define smul_ppmm(xh, xl, m0, m1) \
292 do { \
293 union {DItype __ll; \
294 struct {USItype __h, __l;} __i; \
295 } __x; \
296 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
297 : "=&r" (__x.__ll) \
298 : "r" (m0), "r" (m1)); \
299 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
300 } while (0)
301 #define sdiv_qrnnd(q, r, n1, n0, d) \
302 do { \
303 union {DItype __ll; \
304 struct {USItype __h, __l;} __i; \
305 } __x; \
306 __x.__i.__h = n1; __x.__i.__l = n0; \
307 __asm__ ("dr %0,%2" \
308 : "=r" (__x.__ll) \
309 : "0" (__x.__ll), "r" (d)); \
310 (q) = __x.__i.__l; (r) = __x.__i.__h; \
311 } while (0)
312 #endif
313
314 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
315 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
316 __asm__ ("addl %5,%1\n\tadcl %3,%0" \
317 : "=r" ((USItype) (sh)), \
318 "=&r" ((USItype) (sl)) \
319 : "%0" ((USItype) (ah)), \
320 "g" ((USItype) (bh)), \
321 "%1" ((USItype) (al)), \
322 "g" ((USItype) (bl)))
323 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
324 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
325 : "=r" ((USItype) (sh)), \
326 "=&r" ((USItype) (sl)) \
327 : "0" ((USItype) (ah)), \
328 "g" ((USItype) (bh)), \
329 "1" ((USItype) (al)), \
330 "g" ((USItype) (bl)))
331 #define umul_ppmm(w1, w0, u, v) \
332 __asm__ ("mull %3" \
333 : "=a" ((USItype) (w0)), \
334 "=d" ((USItype) (w1)) \
335 : "%0" ((USItype) (u)), \
336 "rm" ((USItype) (v)))
337 #define udiv_qrnnd(q, r, n1, n0, dv) \
338 __asm__ ("divl %4" \
339 : "=a" ((USItype) (q)), \
340 "=d" ((USItype) (r)) \
341 : "0" ((USItype) (n0)), \
342 "1" ((USItype) (n1)), \
343 "rm" ((USItype) (dv)))
344 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
345 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
346 #define UMUL_TIME 40
347 #define UDIV_TIME 40
348 #endif /* 80x86 */
349
350 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
351 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
352 __asm__ ("addq %5,%1\n\tadcq %3,%0" \
353 : "=r" ((UDItype) (sh)), \
354 "=&r" ((UDItype) (sl)) \
355 : "%0" ((UDItype) (ah)), \
356 "rme" ((UDItype) (bh)), \
357 "%1" ((UDItype) (al)), \
358 "rme" ((UDItype) (bl)))
359 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
360 __asm__ ("subq %5,%1\n\tsbbq %3,%0" \
361 : "=r" ((UDItype) (sh)), \
362 "=&r" ((UDItype) (sl)) \
363 : "0" ((UDItype) (ah)), \
364 "rme" ((UDItype) (bh)), \
365 "1" ((UDItype) (al)), \
366 "rme" ((UDItype) (bl)))
367 #define umul_ppmm(w1, w0, u, v) \
368 __asm__ ("mulq %3" \
369 : "=a" ((UDItype) (w0)), \
370 "=d" ((UDItype) (w1)) \
371 : "%0" ((UDItype) (u)), \
372 "rm" ((UDItype) (v)))
373 #define udiv_qrnnd(q, r, n1, n0, dv) \
374 __asm__ ("divq %4" \
375 : "=a" ((UDItype) (q)), \
376 "=d" ((UDItype) (r)) \
377 : "0" ((UDItype) (n0)), \
378 "1" ((UDItype) (n1)), \
379 "rm" ((UDItype) (dv)))
380 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
381 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
382 #define UMUL_TIME 40
383 #define UDIV_TIME 40
384 #endif /* x86_64 */
385
386 #if defined (__i960__) && W_TYPE_SIZE == 32
387 #define umul_ppmm(w1, w0, u, v) \
388 ({union {UDItype __ll; \
389 struct {USItype __l, __h;} __i; \
390 } __xx; \
391 __asm__ ("emul %2,%1,%0" \
392 : "=d" (__xx.__ll) \
393 : "%dI" ((USItype) (u)), \
394 "dI" ((USItype) (v))); \
395 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
396 #define __umulsidi3(u, v) \
397 ({UDItype __w; \
398 __asm__ ("emul %2,%1,%0" \
399 : "=d" (__w) \
400 : "%dI" ((USItype) (u)), \
401 "dI" ((USItype) (v))); \
402 __w; })
403 #endif /* __i960__ */
404
405 #if defined (__M32R__) && W_TYPE_SIZE == 32
406 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
407 /* The cmp clears the condition bit. */ \
408 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
409 : "=r" ((USItype) (sh)), \
410 "=&r" ((USItype) (sl)) \
411 : "0" ((USItype) (ah)), \
412 "r" ((USItype) (bh)), \
413 "1" ((USItype) (al)), \
414 "r" ((USItype) (bl)) \
415 : "cbit")
416 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
417 /* The cmp clears the condition bit. */ \
418 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
419 : "=r" ((USItype) (sh)), \
420 "=&r" ((USItype) (sl)) \
421 : "0" ((USItype) (ah)), \
422 "r" ((USItype) (bh)), \
423 "1" ((USItype) (al)), \
424 "r" ((USItype) (bl)) \
425 : "cbit")
426 #endif /* __M32R__ */
427
428 #if defined (__mc68000__) && W_TYPE_SIZE == 32
429 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
430 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
431 : "=d" ((USItype) (sh)), \
432 "=&d" ((USItype) (sl)) \
433 : "%0" ((USItype) (ah)), \
434 "d" ((USItype) (bh)), \
435 "%1" ((USItype) (al)), \
436 "g" ((USItype) (bl)))
437 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
438 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
439 : "=d" ((USItype) (sh)), \
440 "=&d" ((USItype) (sl)) \
441 : "0" ((USItype) (ah)), \
442 "d" ((USItype) (bh)), \
443 "1" ((USItype) (al)), \
444 "g" ((USItype) (bl)))
445
446 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
447 #if (defined (__mc68020__) && !defined (__mc68060__))
448 #define umul_ppmm(w1, w0, u, v) \
449 __asm__ ("mulu%.l %3,%1:%0" \
450 : "=d" ((USItype) (w0)), \
451 "=d" ((USItype) (w1)) \
452 : "%0" ((USItype) (u)), \
453 "dmi" ((USItype) (v)))
454 #define UMUL_TIME 45
455 #define udiv_qrnnd(q, r, n1, n0, d) \
456 __asm__ ("divu%.l %4,%1:%0" \
457 : "=d" ((USItype) (q)), \
458 "=d" ((USItype) (r)) \
459 : "0" ((USItype) (n0)), \
460 "1" ((USItype) (n1)), \
461 "dmi" ((USItype) (d)))
462 #define UDIV_TIME 90
463 #define sdiv_qrnnd(q, r, n1, n0, d) \
464 __asm__ ("divs%.l %4,%1:%0" \
465 : "=d" ((USItype) (q)), \
466 "=d" ((USItype) (r)) \
467 : "0" ((USItype) (n0)), \
468 "1" ((USItype) (n1)), \
469 "dmi" ((USItype) (d)))
470
471 #elif defined (__mcoldfire__) /* not mc68020 */
472
473 #define umul_ppmm(xh, xl, a, b) \
474 __asm__ ("| Inlined umul_ppmm\n" \
475 " move%.l %2,%/d0\n" \
476 " move%.l %3,%/d1\n" \
477 " move%.l %/d0,%/d2\n" \
478 " swap %/d0\n" \
479 " move%.l %/d1,%/d3\n" \
480 " swap %/d1\n" \
481 " move%.w %/d2,%/d4\n" \
482 " mulu %/d3,%/d4\n" \
483 " mulu %/d1,%/d2\n" \
484 " mulu %/d0,%/d3\n" \
485 " mulu %/d0,%/d1\n" \
486 " move%.l %/d4,%/d0\n" \
487 " clr%.w %/d0\n" \
488 " swap %/d0\n" \
489 " add%.l %/d0,%/d2\n" \
490 " add%.l %/d3,%/d2\n" \
491 " jcc 1f\n" \
492 " add%.l %#65536,%/d1\n" \
493 "1: swap %/d2\n" \
494 " moveq %#0,%/d0\n" \
495 " move%.w %/d2,%/d0\n" \
496 " move%.w %/d4,%/d2\n" \
497 " move%.l %/d2,%1\n" \
498 " add%.l %/d1,%/d0\n" \
499 " move%.l %/d0,%0" \
500 : "=g" ((USItype) (xh)), \
501 "=g" ((USItype) (xl)) \
502 : "g" ((USItype) (a)), \
503 "g" ((USItype) (b)) \
504 : "d0", "d1", "d2", "d3", "d4")
505 #define UMUL_TIME 100
506 #define UDIV_TIME 400
507 #else /* not ColdFire */
508 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
509 #define umul_ppmm(xh, xl, a, b) \
510 __asm__ ("| Inlined umul_ppmm\n" \
511 " move%.l %2,%/d0\n" \
512 " move%.l %3,%/d1\n" \
513 " move%.l %/d0,%/d2\n" \
514 " swap %/d0\n" \
515 " move%.l %/d1,%/d3\n" \
516 " swap %/d1\n" \
517 " move%.w %/d2,%/d4\n" \
518 " mulu %/d3,%/d4\n" \
519 " mulu %/d1,%/d2\n" \
520 " mulu %/d0,%/d3\n" \
521 " mulu %/d0,%/d1\n" \
522 " move%.l %/d4,%/d0\n" \
523 " eor%.w %/d0,%/d0\n" \
524 " swap %/d0\n" \
525 " add%.l %/d0,%/d2\n" \
526 " add%.l %/d3,%/d2\n" \
527 " jcc 1f\n" \
528 " add%.l %#65536,%/d1\n" \
529 "1: swap %/d2\n" \
530 " moveq %#0,%/d0\n" \
531 " move%.w %/d2,%/d0\n" \
532 " move%.w %/d4,%/d2\n" \
533 " move%.l %/d2,%1\n" \
534 " add%.l %/d1,%/d0\n" \
535 " move%.l %/d0,%0" \
536 : "=g" ((USItype) (xh)), \
537 "=g" ((USItype) (xl)) \
538 : "g" ((USItype) (a)), \
539 "g" ((USItype) (b)) \
540 : "d0", "d1", "d2", "d3", "d4")
541 #define UMUL_TIME 100
542 #define UDIV_TIME 400
543
544 #endif /* not mc68020 */
545
546 /* The '020, '030, '040 and '060 have bitfield insns.
547 cpu32 disguises as a 68020, but lacks them. */
548 #if defined (__mc68020__) && !defined (__mcpu32__)
549 #define count_leading_zeros(count, x) \
550 __asm__ ("bfffo %1{%b2:%b2},%0" \
551 : "=d" ((USItype) (count)) \
552 : "od" ((USItype) (x)), "n" (0))
553 /* Some ColdFire architectures have a ff1 instruction supported via
554 __builtin_clz. */
555 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
556 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
557 #define COUNT_LEADING_ZEROS_0 32
558 #endif
559 #endif /* mc68000 */
560
561 #if defined (__m88000__) && W_TYPE_SIZE == 32
562 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
563 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
564 : "=r" ((USItype) (sh)), \
565 "=&r" ((USItype) (sl)) \
566 : "%rJ" ((USItype) (ah)), \
567 "rJ" ((USItype) (bh)), \
568 "%rJ" ((USItype) (al)), \
569 "rJ" ((USItype) (bl)))
570 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
571 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
572 : "=r" ((USItype) (sh)), \
573 "=&r" ((USItype) (sl)) \
574 : "rJ" ((USItype) (ah)), \
575 "rJ" ((USItype) (bh)), \
576 "rJ" ((USItype) (al)), \
577 "rJ" ((USItype) (bl)))
578 #define count_leading_zeros(count, x) \
579 do { \
580 USItype __cbtmp; \
581 __asm__ ("ff1 %0,%1" \
582 : "=r" (__cbtmp) \
583 : "r" ((USItype) (x))); \
584 (count) = __cbtmp ^ 31; \
585 } while (0)
586 #define COUNT_LEADING_ZEROS_0 63 /* sic */
587 #if defined (__mc88110__)
588 #define umul_ppmm(wh, wl, u, v) \
589 do { \
590 union {UDItype __ll; \
591 struct {USItype __h, __l;} __i; \
592 } __xx; \
593 __asm__ ("mulu.d %0,%1,%2" \
594 : "=r" (__xx.__ll) \
595 : "r" ((USItype) (u)), \
596 "r" ((USItype) (v))); \
597 (wh) = __xx.__i.__h; \
598 (wl) = __xx.__i.__l; \
599 } while (0)
600 #define udiv_qrnnd(q, r, n1, n0, d) \
601 ({union {UDItype __ll; \
602 struct {USItype __h, __l;} __i; \
603 } __xx; \
604 USItype __q; \
605 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
606 __asm__ ("divu.d %0,%1,%2" \
607 : "=r" (__q) \
608 : "r" (__xx.__ll), \
609 "r" ((USItype) (d))); \
610 (r) = (n0) - __q * (d); (q) = __q; })
611 #define UMUL_TIME 5
612 #define UDIV_TIME 25
613 #else
614 #define UMUL_TIME 17
615 #define UDIV_TIME 150
616 #endif /* __mc88110__ */
617 #endif /* __m88000__ */
618
619 #if defined (__mips__) && W_TYPE_SIZE == 32
620 #define umul_ppmm(w1, w0, u, v) \
621 __asm__ ("multu %2,%3" \
622 : "=l" ((USItype) (w0)), \
623 "=h" ((USItype) (w1)) \
624 : "d" ((USItype) (u)), \
625 "d" ((USItype) (v)))
626 #define UMUL_TIME 10
627 #define UDIV_TIME 100
628 #endif /* __mips__ */
629
630 #if defined (__ns32000__) && W_TYPE_SIZE == 32
631 #define umul_ppmm(w1, w0, u, v) \
632 ({union {UDItype __ll; \
633 struct {USItype __l, __h;} __i; \
634 } __xx; \
635 __asm__ ("meid %2,%0" \
636 : "=g" (__xx.__ll) \
637 : "%0" ((USItype) (u)), \
638 "g" ((USItype) (v))); \
639 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
640 #define __umulsidi3(u, v) \
641 ({UDItype __w; \
642 __asm__ ("meid %2,%0" \
643 : "=g" (__w) \
644 : "%0" ((USItype) (u)), \
645 "g" ((USItype) (v))); \
646 __w; })
647 #define udiv_qrnnd(q, r, n1, n0, d) \
648 ({union {UDItype __ll; \
649 struct {USItype __l, __h;} __i; \
650 } __xx; \
651 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
652 __asm__ ("deid %2,%0" \
653 : "=g" (__xx.__ll) \
654 : "0" (__xx.__ll), \
655 "g" ((USItype) (d))); \
656 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
657 #define count_trailing_zeros(count,x) \
658 do { \
659 __asm__ ("ffsd %2,%0" \
660 : "=r" ((USItype) (count)) \
661 : "0" ((USItype) 0), \
662 "r" ((USItype) (x))); \
663 } while (0)
664 #endif /* __ns32000__ */
665
666 /* FIXME: We should test _IBMR2 here when we add assembly support for the
667 system vendor compilers.
668 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
669 enough, since that hits ARM and m68k too. */
670 #if (defined (_ARCH_PPC) /* AIX */ \
671 || defined (_ARCH_PWR) /* AIX */ \
672 || defined (_ARCH_COM) /* AIX */ \
673 || defined (__powerpc__) /* gcc */ \
674 || defined (__POWERPC__) /* BEOS */ \
675 || defined (__ppc__) /* Darwin */ \
676 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
677 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
678 && CPU_FAMILY == PPC) \
679 ) && W_TYPE_SIZE == 32
680 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
681 do { \
682 if (__builtin_constant_p (bh) && (bh) == 0) \
683 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
684 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
685 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
686 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
687 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
688 else \
689 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
690 : "=r" (sh), "=&r" (sl) \
691 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
692 } while (0)
693 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
694 do { \
695 if (__builtin_constant_p (ah) && (ah) == 0) \
696 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
697 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
698 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
699 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
700 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
701 else if (__builtin_constant_p (bh) && (bh) == 0) \
702 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
703 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
704 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
705 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
706 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
707 else \
708 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
709 : "=r" (sh), "=&r" (sl) \
710 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
711 } while (0)
712 #define count_leading_zeros(count, x) \
713 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
714 #define COUNT_LEADING_ZEROS_0 32
715 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
716 || defined (__ppc__) \
717 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
718 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
719 && CPU_FAMILY == PPC)
720 #define umul_ppmm(ph, pl, m0, m1) \
721 do { \
722 USItype __m0 = (m0), __m1 = (m1); \
723 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
724 (pl) = __m0 * __m1; \
725 } while (0)
726 #define UMUL_TIME 15
727 #define smul_ppmm(ph, pl, m0, m1) \
728 do { \
729 SItype __m0 = (m0), __m1 = (m1); \
730 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
731 (pl) = __m0 * __m1; \
732 } while (0)
733 #define SMUL_TIME 14
734 #define UDIV_TIME 120
735 #elif defined (_ARCH_PWR)
736 #define UMUL_TIME 8
737 #define smul_ppmm(xh, xl, m0, m1) \
738 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
739 #define SMUL_TIME 4
740 #define sdiv_qrnnd(q, r, nh, nl, d) \
741 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
742 #define UDIV_TIME 100
743 #endif
744 #endif /* 32-bit POWER architecture variants. */
745
746 /* We should test _IBMR2 here when we add assembly support for the system
747 vendor compilers. */
748 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
749 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
750 do { \
751 if (__builtin_constant_p (bh) && (bh) == 0) \
752 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
753 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
754 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
755 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
756 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
757 else \
758 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
759 : "=r" (sh), "=&r" (sl) \
760 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
761 } while (0)
762 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
763 do { \
764 if (__builtin_constant_p (ah) && (ah) == 0) \
765 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
766 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
767 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
768 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
769 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
770 else if (__builtin_constant_p (bh) && (bh) == 0) \
771 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
772 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
773 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
774 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
775 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
776 else \
777 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
778 : "=r" (sh), "=&r" (sl) \
779 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
780 } while (0)
781 #define count_leading_zeros(count, x) \
782 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
783 #define COUNT_LEADING_ZEROS_0 64
784 #define umul_ppmm(ph, pl, m0, m1) \
785 do { \
786 UDItype __m0 = (m0), __m1 = (m1); \
787 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
788 (pl) = __m0 * __m1; \
789 } while (0)
790 #define UMUL_TIME 15
791 #define smul_ppmm(ph, pl, m0, m1) \
792 do { \
793 DItype __m0 = (m0), __m1 = (m1); \
794 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
795 (pl) = __m0 * __m1; \
796 } while (0)
797 #define SMUL_TIME 14 /* ??? */
798 #define UDIV_TIME 120 /* ??? */
799 #endif /* 64-bit PowerPC. */
800
801 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
802 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
803 __asm__ ("a %1,%5\n\tae %0,%3" \
804 : "=r" ((USItype) (sh)), \
805 "=&r" ((USItype) (sl)) \
806 : "%0" ((USItype) (ah)), \
807 "r" ((USItype) (bh)), \
808 "%1" ((USItype) (al)), \
809 "r" ((USItype) (bl)))
810 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
811 __asm__ ("s %1,%5\n\tse %0,%3" \
812 : "=r" ((USItype) (sh)), \
813 "=&r" ((USItype) (sl)) \
814 : "0" ((USItype) (ah)), \
815 "r" ((USItype) (bh)), \
816 "1" ((USItype) (al)), \
817 "r" ((USItype) (bl)))
818 #define umul_ppmm(ph, pl, m0, m1) \
819 do { \
820 USItype __m0 = (m0), __m1 = (m1); \
821 __asm__ ( \
822 "s r2,r2\n" \
823 " mts r10,%2\n" \
824 " m r2,%3\n" \
825 " m r2,%3\n" \
826 " m r2,%3\n" \
827 " m r2,%3\n" \
828 " m r2,%3\n" \
829 " m r2,%3\n" \
830 " m r2,%3\n" \
831 " m r2,%3\n" \
832 " m r2,%3\n" \
833 " m r2,%3\n" \
834 " m r2,%3\n" \
835 " m r2,%3\n" \
836 " m r2,%3\n" \
837 " m r2,%3\n" \
838 " m r2,%3\n" \
839 " m r2,%3\n" \
840 " cas %0,r2,r0\n" \
841 " mfs r10,%1" \
842 : "=r" ((USItype) (ph)), \
843 "=r" ((USItype) (pl)) \
844 : "%r" (__m0), \
845 "r" (__m1) \
846 : "r2"); \
847 (ph) += ((((SItype) __m0 >> 31) & __m1) \
848 + (((SItype) __m1 >> 31) & __m0)); \
849 } while (0)
850 #define UMUL_TIME 20
851 #define UDIV_TIME 200
852 #define count_leading_zeros(count, x) \
853 do { \
854 if ((x) >= 0x10000) \
855 __asm__ ("clz %0,%1" \
856 : "=r" ((USItype) (count)) \
857 : "r" ((USItype) (x) >> 16)); \
858 else \
859 { \
860 __asm__ ("clz %0,%1" \
861 : "=r" ((USItype) (count)) \
862 : "r" ((USItype) (x))); \
863 (count) += 16; \
864 } \
865 } while (0)
866 #endif
867
868 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
869 #ifndef __sh1__
870 #define umul_ppmm(w1, w0, u, v) \
871 __asm__ ( \
872 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
873 : "=r<" ((USItype)(w1)), \
874 "=r<" ((USItype)(w0)) \
875 : "r" ((USItype)(u)), \
876 "r" ((USItype)(v)) \
877 : "macl", "mach")
878 #define UMUL_TIME 5
879 #endif
880
881 /* This is the same algorithm as __udiv_qrnnd_c. */
882 #define UDIV_NEEDS_NORMALIZATION 1
883
884 #define udiv_qrnnd(q, r, n1, n0, d) \
885 do { \
886 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
887 __attribute__ ((visibility ("hidden"))); \
888 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
889 __asm__ ( \
890 "mov%M4 %4,r5\n" \
891 " swap.w %3,r4\n" \
892 " swap.w r5,r6\n" \
893 " jsr @%5\n" \
894 " shll16 r6\n" \
895 " swap.w r4,r4\n" \
896 " jsr @%5\n" \
897 " swap.w r1,%0\n" \
898 " or r1,%0" \
899 : "=r" (q), "=&z" (r) \
900 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
901 : "r1", "r2", "r4", "r5", "r6", "pr"); \
902 } while (0)
903
904 #define UDIV_TIME 80
905
906 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
907 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
908 : "=r" (sh), "=r" (sl) \
909 : "0" (ah), "1" (al), "r" (bh), "r" (bl))
910
911 #endif /* __sh__ */
912
913 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
914 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
915 #define count_leading_zeros(count, x) \
916 do \
917 { \
918 UDItype x_ = (USItype)(x); \
919 SItype c_; \
920 \
921 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
922 (count) = c_ - 31; \
923 } \
924 while (0)
925 #define COUNT_LEADING_ZEROS_0 32
926 #endif
927
928 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
929 && W_TYPE_SIZE == 32
930 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
931 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
932 : "=r" ((USItype) (sh)), \
933 "=&r" ((USItype) (sl)) \
934 : "%rJ" ((USItype) (ah)), \
935 "rI" ((USItype) (bh)), \
936 "%rJ" ((USItype) (al)), \
937 "rI" ((USItype) (bl)) \
938 __CLOBBER_CC)
939 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
940 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
941 : "=r" ((USItype) (sh)), \
942 "=&r" ((USItype) (sl)) \
943 : "rJ" ((USItype) (ah)), \
944 "rI" ((USItype) (bh)), \
945 "rJ" ((USItype) (al)), \
946 "rI" ((USItype) (bl)) \
947 __CLOBBER_CC)
948 #if defined (__sparc_v8__)
949 #define umul_ppmm(w1, w0, u, v) \
950 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
951 : "=r" ((USItype) (w1)), \
952 "=r" ((USItype) (w0)) \
953 : "r" ((USItype) (u)), \
954 "r" ((USItype) (v)))
955 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
956 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
957 : "=&r" ((USItype) (__q)), \
958 "=&r" ((USItype) (__r)) \
959 : "r" ((USItype) (__n1)), \
960 "r" ((USItype) (__n0)), \
961 "r" ((USItype) (__d)))
962 #else
963 #if defined (__sparclite__)
964 /* This has hardware multiply but not divide. It also has two additional
965 instructions scan (ffs from high bit) and divscc. */
966 #define umul_ppmm(w1, w0, u, v) \
967 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
968 : "=r" ((USItype) (w1)), \
969 "=r" ((USItype) (w0)) \
970 : "r" ((USItype) (u)), \
971 "r" ((USItype) (v)))
972 #define udiv_qrnnd(q, r, n1, n0, d) \
973 __asm__ ("! Inlined udiv_qrnnd\n" \
974 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
975 " tst %%g0\n" \
976 " divscc %3,%4,%%g1\n" \
977 " divscc %%g1,%4,%%g1\n" \
978 " divscc %%g1,%4,%%g1\n" \
979 " divscc %%g1,%4,%%g1\n" \
980 " divscc %%g1,%4,%%g1\n" \
981 " divscc %%g1,%4,%%g1\n" \
982 " divscc %%g1,%4,%%g1\n" \
983 " divscc %%g1,%4,%%g1\n" \
984 " divscc %%g1,%4,%%g1\n" \
985 " divscc %%g1,%4,%%g1\n" \
986 " divscc %%g1,%4,%%g1\n" \
987 " divscc %%g1,%4,%%g1\n" \
988 " divscc %%g1,%4,%%g1\n" \
989 " divscc %%g1,%4,%%g1\n" \
990 " divscc %%g1,%4,%%g1\n" \
991 " divscc %%g1,%4,%%g1\n" \
992 " divscc %%g1,%4,%%g1\n" \
993 " divscc %%g1,%4,%%g1\n" \
994 " divscc %%g1,%4,%%g1\n" \
995 " divscc %%g1,%4,%%g1\n" \
996 " divscc %%g1,%4,%%g1\n" \
997 " divscc %%g1,%4,%%g1\n" \
998 " divscc %%g1,%4,%%g1\n" \
999 " divscc %%g1,%4,%%g1\n" \
1000 " divscc %%g1,%4,%%g1\n" \
1001 " divscc %%g1,%4,%%g1\n" \
1002 " divscc %%g1,%4,%%g1\n" \
1003 " divscc %%g1,%4,%%g1\n" \
1004 " divscc %%g1,%4,%%g1\n" \
1005 " divscc %%g1,%4,%%g1\n" \
1006 " divscc %%g1,%4,%%g1\n" \
1007 " divscc %%g1,%4,%0\n" \
1008 " rd %%y,%1\n" \
1009 " bl,a 1f\n" \
1010 " add %1,%4,%1\n" \
1011 "1: ! End of inline udiv_qrnnd" \
1012 : "=r" ((USItype) (q)), \
1013 "=r" ((USItype) (r)) \
1014 : "r" ((USItype) (n1)), \
1015 "r" ((USItype) (n0)), \
1016 "rI" ((USItype) (d)) \
1017 : "g1" __AND_CLOBBER_CC)
1018 #define UDIV_TIME 37
1019 #define count_leading_zeros(count, x) \
1020 do { \
1021 __asm__ ("scan %1,1,%0" \
1022 : "=r" ((USItype) (count)) \
1023 : "r" ((USItype) (x))); \
1024 } while (0)
1025 /* Early sparclites return 63 for an argument of 0, but they warn that future
1026 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1027 undefined. */
1028 #else
1029 /* SPARC without integer multiplication and divide instructions.
1030 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1031 #define umul_ppmm(w1, w0, u, v) \
1032 __asm__ ("! Inlined umul_ppmm\n" \
1033 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1034 " sra %3,31,%%o5 ! Don't move this insn\n" \
1035 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1036 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1037 " mulscc %%g1,%3,%%g1\n" \
1038 " mulscc %%g1,%3,%%g1\n" \
1039 " mulscc %%g1,%3,%%g1\n" \
1040 " mulscc %%g1,%3,%%g1\n" \
1041 " mulscc %%g1,%3,%%g1\n" \
1042 " mulscc %%g1,%3,%%g1\n" \
1043 " mulscc %%g1,%3,%%g1\n" \
1044 " mulscc %%g1,%3,%%g1\n" \
1045 " mulscc %%g1,%3,%%g1\n" \
1046 " mulscc %%g1,%3,%%g1\n" \
1047 " mulscc %%g1,%3,%%g1\n" \
1048 " mulscc %%g1,%3,%%g1\n" \
1049 " mulscc %%g1,%3,%%g1\n" \
1050 " mulscc %%g1,%3,%%g1\n" \
1051 " mulscc %%g1,%3,%%g1\n" \
1052 " mulscc %%g1,%3,%%g1\n" \
1053 " mulscc %%g1,%3,%%g1\n" \
1054 " mulscc %%g1,%3,%%g1\n" \
1055 " mulscc %%g1,%3,%%g1\n" \
1056 " mulscc %%g1,%3,%%g1\n" \
1057 " mulscc %%g1,%3,%%g1\n" \
1058 " mulscc %%g1,%3,%%g1\n" \
1059 " mulscc %%g1,%3,%%g1\n" \
1060 " mulscc %%g1,%3,%%g1\n" \
1061 " mulscc %%g1,%3,%%g1\n" \
1062 " mulscc %%g1,%3,%%g1\n" \
1063 " mulscc %%g1,%3,%%g1\n" \
1064 " mulscc %%g1,%3,%%g1\n" \
1065 " mulscc %%g1,%3,%%g1\n" \
1066 " mulscc %%g1,%3,%%g1\n" \
1067 " mulscc %%g1,%3,%%g1\n" \
1068 " mulscc %%g1,%3,%%g1\n" \
1069 " mulscc %%g1,0,%%g1\n" \
1070 " add %%g1,%%o5,%0\n" \
1071 " rd %%y,%1" \
1072 : "=r" ((USItype) (w1)), \
1073 "=r" ((USItype) (w0)) \
1074 : "%rI" ((USItype) (u)), \
1075 "r" ((USItype) (v)) \
1076 : "g1", "o5" __AND_CLOBBER_CC)
1077 #define UMUL_TIME 39 /* 39 instructions */
1078 /* It's quite necessary to add this much assembler for the sparc.
1079 The default udiv_qrnnd (in C) is more than 10 times slower! */
1080 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1081 __asm__ ("! Inlined udiv_qrnnd\n" \
1082 " mov 32,%%g1\n" \
1083 " subcc %1,%2,%%g0\n" \
1084 "1: bcs 5f\n" \
1085 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1086 " sub %1,%2,%1 ! this kills msb of n\n" \
1087 " addx %1,%1,%1 ! so this can't give carry\n" \
1088 " subcc %%g1,1,%%g1\n" \
1089 "2: bne 1b\n" \
1090 " subcc %1,%2,%%g0\n" \
1091 " bcs 3f\n" \
1092 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1093 " b 3f\n" \
1094 " sub %1,%2,%1 ! this kills msb of n\n" \
1095 "4: sub %1,%2,%1\n" \
1096 "5: addxcc %1,%1,%1\n" \
1097 " bcc 2b\n" \
1098 " subcc %%g1,1,%%g1\n" \
1099 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1100 " bne 4b\n" \
1101 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1102 " sub %1,%2,%1\n" \
1103 "3: xnor %0,0,%0\n" \
1104 " ! End of inline udiv_qrnnd" \
1105 : "=&r" ((USItype) (__q)), \
1106 "=&r" ((USItype) (__r)) \
1107 : "r" ((USItype) (__d)), \
1108 "1" ((USItype) (__n1)), \
1109 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1110 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1111 #endif /* __sparclite__ */
1112 #endif /* __sparc_v8__ */
1113 #endif /* sparc32 */
1114
1115 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1116 && W_TYPE_SIZE == 64
1117 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1118 __asm__ ("addcc %r4,%5,%1\n\t" \
1119 "add %r2,%3,%0\n\t" \
1120 "bcs,a,pn %%xcc, 1f\n\t" \
1121 "add %0, 1, %0\n" \
1122 "1:" \
1123 : "=r" ((UDItype)(sh)), \
1124 "=&r" ((UDItype)(sl)) \
1125 : "%rJ" ((UDItype)(ah)), \
1126 "rI" ((UDItype)(bh)), \
1127 "%rJ" ((UDItype)(al)), \
1128 "rI" ((UDItype)(bl)) \
1129 __CLOBBER_CC)
1130
1131 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1132 __asm__ ("subcc %r4,%5,%1\n\t" \
1133 "sub %r2,%3,%0\n\t" \
1134 "bcs,a,pn %%xcc, 1f\n\t" \
1135 "sub %0, 1, %0\n\t" \
1136 "1:" \
1137 : "=r" ((UDItype)(sh)), \
1138 "=&r" ((UDItype)(sl)) \
1139 : "rJ" ((UDItype)(ah)), \
1140 "rI" ((UDItype)(bh)), \
1141 "rJ" ((UDItype)(al)), \
1142 "rI" ((UDItype)(bl)) \
1143 __CLOBBER_CC)
1144
1145 #define umul_ppmm(wh, wl, u, v) \
1146 do { \
1147 UDItype tmp1, tmp2, tmp3, tmp4; \
1148 __asm__ __volatile__ ( \
1149 "srl %7,0,%3\n\t" \
1150 "mulx %3,%6,%1\n\t" \
1151 "srlx %6,32,%2\n\t" \
1152 "mulx %2,%3,%4\n\t" \
1153 "sllx %4,32,%5\n\t" \
1154 "srl %6,0,%3\n\t" \
1155 "sub %1,%5,%5\n\t" \
1156 "srlx %5,32,%5\n\t" \
1157 "addcc %4,%5,%4\n\t" \
1158 "srlx %7,32,%5\n\t" \
1159 "mulx %3,%5,%3\n\t" \
1160 "mulx %2,%5,%5\n\t" \
1161 "sethi %%hi(0x80000000),%2\n\t" \
1162 "addcc %4,%3,%4\n\t" \
1163 "srlx %4,32,%4\n\t" \
1164 "add %2,%2,%2\n\t" \
1165 "movcc %%xcc,%%g0,%2\n\t" \
1166 "addcc %5,%4,%5\n\t" \
1167 "sllx %3,32,%3\n\t" \
1168 "add %1,%3,%1\n\t" \
1169 "add %5,%2,%0" \
1170 : "=r" ((UDItype)(wh)), \
1171 "=&r" ((UDItype)(wl)), \
1172 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1173 : "r" ((UDItype)(u)), \
1174 "r" ((UDItype)(v)) \
1175 __CLOBBER_CC); \
1176 } while (0)
1177 #define UMUL_TIME 96
1178 #define UDIV_TIME 230
1179 #endif /* sparc64 */
1180
1181 #if defined (__vax__) && W_TYPE_SIZE == 32
1182 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1183 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1184 : "=g" ((USItype) (sh)), \
1185 "=&g" ((USItype) (sl)) \
1186 : "%0" ((USItype) (ah)), \
1187 "g" ((USItype) (bh)), \
1188 "%1" ((USItype) (al)), \
1189 "g" ((USItype) (bl)))
1190 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1191 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1192 : "=g" ((USItype) (sh)), \
1193 "=&g" ((USItype) (sl)) \
1194 : "0" ((USItype) (ah)), \
1195 "g" ((USItype) (bh)), \
1196 "1" ((USItype) (al)), \
1197 "g" ((USItype) (bl)))
1198 #define umul_ppmm(xh, xl, m0, m1) \
1199 do { \
1200 union { \
1201 UDItype __ll; \
1202 struct {USItype __l, __h;} __i; \
1203 } __xx; \
1204 USItype __m0 = (m0), __m1 = (m1); \
1205 __asm__ ("emul %1,%2,$0,%0" \
1206 : "=r" (__xx.__ll) \
1207 : "g" (__m0), \
1208 "g" (__m1)); \
1209 (xh) = __xx.__i.__h; \
1210 (xl) = __xx.__i.__l; \
1211 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1212 + (((SItype) __m1 >> 31) & __m0)); \
1213 } while (0)
1214 #define sdiv_qrnnd(q, r, n1, n0, d) \
1215 do { \
1216 union {DItype __ll; \
1217 struct {SItype __l, __h;} __i; \
1218 } __xx; \
1219 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1220 __asm__ ("ediv %3,%2,%0,%1" \
1221 : "=g" (q), "=g" (r) \
1222 : "g" (__xx.__ll), "g" (d)); \
1223 } while (0)
1224 #endif /* __vax__ */
1225
1226 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1227 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1228 to expand builtin functions depending on what configuration features
1229 are available. This avoids library calls when the operation can be
1230 performed in-line. */
1231 #define umul_ppmm(w1, w0, u, v) \
1232 do { \
1233 DWunion __w; \
1234 __w.ll = __builtin_umulsidi3 (u, v); \
1235 w1 = __w.s.high; \
1236 w0 = __w.s.low; \
1237 } while (0)
1238 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1239 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1240 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1241 #endif /* __xtensa__ */
1242
1243 #if defined (__z8000__) && W_TYPE_SIZE == 16
1244 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1245 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1246 : "=r" ((unsigned int)(sh)), \
1247 "=&r" ((unsigned int)(sl)) \
1248 : "%0" ((unsigned int)(ah)), \
1249 "r" ((unsigned int)(bh)), \
1250 "%1" ((unsigned int)(al)), \
1251 "rQR" ((unsigned int)(bl)))
1252 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1253 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1254 : "=r" ((unsigned int)(sh)), \
1255 "=&r" ((unsigned int)(sl)) \
1256 : "0" ((unsigned int)(ah)), \
1257 "r" ((unsigned int)(bh)), \
1258 "1" ((unsigned int)(al)), \
1259 "rQR" ((unsigned int)(bl)))
1260 #define umul_ppmm(xh, xl, m0, m1) \
1261 do { \
1262 union {long int __ll; \
1263 struct {unsigned int __h, __l;} __i; \
1264 } __xx; \
1265 unsigned int __m0 = (m0), __m1 = (m1); \
1266 __asm__ ("mult %S0,%H3" \
1267 : "=r" (__xx.__i.__h), \
1268 "=r" (__xx.__i.__l) \
1269 : "%1" (__m0), \
1270 "rQR" (__m1)); \
1271 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1272 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1273 + (((signed int) __m1 >> 15) & __m0)); \
1274 } while (0)
1275 #endif /* __z8000__ */
1276
1277 #endif /* __GNUC__ */
1278
1279 /* If this machine has no inline assembler, use C macros. */
1280
1281 #if !defined (add_ssaaaa)
1282 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1283 do { \
1284 UWtype __x; \
1285 __x = (al) + (bl); \
1286 (sh) = (ah) + (bh) + (__x < (al)); \
1287 (sl) = __x; \
1288 } while (0)
1289 #endif
1290
1291 #if !defined (sub_ddmmss)
1292 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1293 do { \
1294 UWtype __x; \
1295 __x = (al) - (bl); \
1296 (sh) = (ah) - (bh) - (__x > (al)); \
1297 (sl) = __x; \
1298 } while (0)
1299 #endif
1300
1301 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1302 smul_ppmm. */
1303 #if !defined (umul_ppmm) && defined (smul_ppmm)
1304 #define umul_ppmm(w1, w0, u, v) \
1305 do { \
1306 UWtype __w1; \
1307 UWtype __xm0 = (u), __xm1 = (v); \
1308 smul_ppmm (__w1, w0, __xm0, __xm1); \
1309 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1310 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1311 } while (0)
1312 #endif
1313
1314 /* If we still don't have umul_ppmm, define it using plain C. */
1315 #if !defined (umul_ppmm)
1316 #define umul_ppmm(w1, w0, u, v) \
1317 do { \
1318 UWtype __x0, __x1, __x2, __x3; \
1319 UHWtype __ul, __vl, __uh, __vh; \
1320 \
1321 __ul = __ll_lowpart (u); \
1322 __uh = __ll_highpart (u); \
1323 __vl = __ll_lowpart (v); \
1324 __vh = __ll_highpart (v); \
1325 \
1326 __x0 = (UWtype) __ul * __vl; \
1327 __x1 = (UWtype) __ul * __vh; \
1328 __x2 = (UWtype) __uh * __vl; \
1329 __x3 = (UWtype) __uh * __vh; \
1330 \
1331 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1332 __x1 += __x2; /* but this indeed can */ \
1333 if (__x1 < __x2) /* did we get it? */ \
1334 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1335 \
1336 (w1) = __x3 + __ll_highpart (__x1); \
1337 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1338 } while (0)
1339 #endif
1340
1341 #if !defined (__umulsidi3)
1342 #define __umulsidi3(u, v) \
1343 ({DWunion __w; \
1344 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1345 __w.ll; })
1346 #endif
1347
1348 /* Define this unconditionally, so it can be used for debugging. */
1349 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1350 do { \
1351 UWtype __d1, __d0, __q1, __q0; \
1352 UWtype __r1, __r0, __m; \
1353 __d1 = __ll_highpart (d); \
1354 __d0 = __ll_lowpart (d); \
1355 \
1356 __r1 = (n1) % __d1; \
1357 __q1 = (n1) / __d1; \
1358 __m = (UWtype) __q1 * __d0; \
1359 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1360 if (__r1 < __m) \
1361 { \
1362 __q1--, __r1 += (d); \
1363 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1364 if (__r1 < __m) \
1365 __q1--, __r1 += (d); \
1366 } \
1367 __r1 -= __m; \
1368 \
1369 __r0 = __r1 % __d1; \
1370 __q0 = __r1 / __d1; \
1371 __m = (UWtype) __q0 * __d0; \
1372 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1373 if (__r0 < __m) \
1374 { \
1375 __q0--, __r0 += (d); \
1376 if (__r0 >= (d)) \
1377 if (__r0 < __m) \
1378 __q0--, __r0 += (d); \
1379 } \
1380 __r0 -= __m; \
1381 \
1382 (q) = (UWtype) __q1 * __ll_B | __q0; \
1383 (r) = __r0; \
1384 } while (0)
1385
1386 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1387 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1388 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1389 #define udiv_qrnnd(q, r, nh, nl, d) \
1390 do { \
1391 USItype __r; \
1392 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1393 (r) = __r; \
1394 } while (0)
1395 #endif
1396
1397 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1398 #if !defined (udiv_qrnnd)
1399 #define UDIV_NEEDS_NORMALIZATION 1
1400 #define udiv_qrnnd __udiv_qrnnd_c
1401 #endif
1402
1403 #if !defined (count_leading_zeros)
1404 #define count_leading_zeros(count, x) \
1405 do { \
1406 UWtype __xr = (x); \
1407 UWtype __a; \
1408 \
1409 if (W_TYPE_SIZE <= 32) \
1410 { \
1411 __a = __xr < ((UWtype)1<<2*__BITS4) \
1412 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1413 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1414 } \
1415 else \
1416 { \
1417 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1418 if (((__xr >> __a) & 0xff) != 0) \
1419 break; \
1420 } \
1421 \
1422 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1423 } while (0)
1424 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1425 #endif
1426
1427 #if !defined (count_trailing_zeros)
1428 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1429 defined in asm, but if it is not, the C version above is good enough. */
1430 #define count_trailing_zeros(count, x) \
1431 do { \
1432 UWtype __ctz_x = (x); \
1433 UWtype __ctz_c; \
1434 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1435 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1436 } while (0)
1437 #endif
1438
1439 #ifndef UDIV_NEEDS_NORMALIZATION
1440 #define UDIV_NEEDS_NORMALIZATION 0
1441 #endif
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