1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2023 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
119 #include "memmodel.h"
127 #include "addresses.h"
130 #include "rtl-error.h"
133 #include "print-rtl.h"
134 #include "function-abi.h"
135 #include "rtl-iter.h"
137 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
138 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
140 static int bb_reload_num
;
142 /* The current insn being processed and corresponding its single set
143 (NULL otherwise), its data (basic block, the insn data, the insn
144 static data, and the mode of each operand). */
145 static rtx_insn
*curr_insn
;
146 static rtx curr_insn_set
;
147 static basic_block curr_bb
;
148 static lra_insn_recog_data_t curr_id
;
149 static struct lra_static_insn_data
*curr_static_id
;
150 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
151 /* Mode of the register substituted by its equivalence with VOIDmode
152 (e.g. constant) and whose subreg is given operand of the current
153 insn. VOIDmode in all other cases. */
154 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
158 /* Start numbers for new registers and insns at the current constraints
160 static int new_regno_start
;
161 static int new_insn_uid_start
;
163 /* If LOC is nonnull, strip any outer subreg from it. */
165 strip_subreg (rtx
*loc
)
167 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
170 /* Return hard regno of REGNO or if it is was not assigned to a hard
171 register, use a hard register from its allocno class. */
173 get_try_hard_regno (int regno
)
176 enum reg_class rclass
;
178 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
179 hard_regno
= lra_get_regno_hard_regno (regno
);
182 rclass
= lra_get_allocno_class (regno
);
183 if (rclass
== NO_REGS
)
185 return ira_class_hard_regs
[rclass
][0];
188 /* Return the hard regno of X after removing its subreg. If X is not a
189 register or a subreg of a register, return -1. If X is a pseudo, use its
190 assignment. If X is a hard regno, return the final hard regno which will be
191 after elimination. */
193 get_hard_regno (rtx x
)
200 reg
= SUBREG_REG (x
);
203 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
204 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
207 if (HARD_REGISTER_NUM_P (REGNO (reg
)))
208 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
210 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
211 SUBREG_BYTE (x
), GET_MODE (x
));
215 /* If REGNO is a hard register or has been allocated a hard register,
216 return the class of that register. If REGNO is a reload pseudo
217 created by the current constraints pass, return its allocno class.
218 Return NO_REGS otherwise. */
219 static enum reg_class
220 get_reg_class (int regno
)
224 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
225 hard_regno
= lra_get_regno_hard_regno (regno
);
228 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
229 return REGNO_REG_CLASS (hard_regno
);
231 if (regno
>= new_regno_start
)
232 return lra_get_allocno_class (regno
);
236 /* Return true if REG_CLASS has enough allocatable hard regs to keep value of
239 enough_allocatable_hard_regs_p (enum reg_class reg_class
,
240 enum machine_mode reg_mode
)
242 int i
, j
, hard_regno
, class_size
, nregs
;
244 if (hard_reg_set_subset_p (reg_class_contents
[reg_class
], lra_no_alloc_regs
))
246 class_size
= ira_class_hard_regs_num
[reg_class
];
247 for (i
= 0; i
< class_size
; i
++)
249 hard_regno
= ira_class_hard_regs
[reg_class
][i
];
250 nregs
= hard_regno_nregs (hard_regno
, reg_mode
);
253 for (j
= 0; j
< nregs
; j
++)
254 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
255 || ! TEST_HARD_REG_BIT (reg_class_contents
[reg_class
],
264 /* Return true if REG satisfies (or will satisfy) reg class constraint
265 CL. Use elimination first if REG is a hard register. If REG is a
266 reload pseudo created by this constraints pass, assume that it will
267 be allocated a hard register from its allocno class, but allow that
268 class to be narrowed to CL if it is currently a superset of CL and
271 - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
272 - the instruction we're processing is not a reload move.
274 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
275 REGNO (reg), or NO_REGS if no change in its class was needed. */
277 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
,
278 bool allow_all_reload_class_changes_p
= false)
280 enum reg_class rclass
, common_class
;
281 machine_mode reg_mode
;
283 int regno
= REGNO (reg
);
285 if (new_class
!= NULL
)
286 *new_class
= NO_REGS
;
287 if (regno
< FIRST_PSEUDO_REGISTER
)
290 rtx
*final_loc
= &final_reg
;
292 lra_eliminate_reg_if_possible (final_loc
);
293 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
295 reg_mode
= GET_MODE (reg
);
296 rclass
= get_reg_class (regno
);
297 src
= curr_insn_set
!= NULL
? SET_SRC (curr_insn_set
) : NULL
;
298 if (regno
< new_regno_start
299 /* Do not allow the constraints for reload instructions to
300 influence the classes of new pseudos. These reloads are
301 typically moves that have many alternatives, and restricting
302 reload pseudos for one alternative may lead to situations
303 where other reload pseudos are no longer allocatable. */
304 || (!allow_all_reload_class_changes_p
305 && INSN_UID (curr_insn
) >= new_insn_uid_start
307 && ((REG_P (src
) || MEM_P (src
))
308 || (GET_CODE (src
) == SUBREG
309 && (REG_P (SUBREG_REG (src
)) || MEM_P (SUBREG_REG (src
)))))))
310 /* When we don't know what class will be used finally for reload
311 pseudos, we use ALL_REGS. */
312 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
313 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
314 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
315 lra_no_alloc_regs
)));
318 common_class
= ira_reg_class_subset
[rclass
][cl
];
319 if (new_class
!= NULL
)
320 *new_class
= common_class
;
321 return enough_allocatable_hard_regs_p (common_class
, reg_mode
);
325 /* Return true if REGNO satisfies a memory constraint. */
329 return get_reg_class (regno
) == NO_REGS
;
332 /* Return true if ADDR is a valid memory address for mode MODE in address
333 space AS, and check that each pseudo has the proper kind of hard
336 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
337 rtx addr
, addr_space_t as
)
339 #ifdef GO_IF_LEGITIMATE_ADDRESS
340 lra_assert (ADDR_SPACE_GENERIC_P (as
));
341 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
347 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
,
353 /* Temporarily eliminates registers in an address (for the lifetime of
355 class address_eliminator
{
357 address_eliminator (struct address_info
*ad
);
358 ~address_eliminator ();
361 struct address_info
*m_ad
;
369 address_eliminator::address_eliminator (struct address_info
*ad
)
371 m_base_loc (strip_subreg (ad
->base_term
)),
372 m_base_reg (NULL_RTX
),
373 m_index_loc (strip_subreg (ad
->index_term
)),
374 m_index_reg (NULL_RTX
)
376 if (m_base_loc
!= NULL
)
378 m_base_reg
= *m_base_loc
;
379 /* If we have non-legitimate address which is decomposed not in
380 the way we expected, don't do elimination here. In such case
381 the address will be reloaded and elimination will be done in
382 reload insn finally. */
383 if (REG_P (m_base_reg
))
384 lra_eliminate_reg_if_possible (m_base_loc
);
385 if (m_ad
->base_term2
!= NULL
)
386 *m_ad
->base_term2
= *m_ad
->base_term
;
388 if (m_index_loc
!= NULL
)
390 m_index_reg
= *m_index_loc
;
391 if (REG_P (m_index_reg
))
392 lra_eliminate_reg_if_possible (m_index_loc
);
396 address_eliminator::~address_eliminator ()
398 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
400 *m_base_loc
= m_base_reg
;
401 if (m_ad
->base_term2
!= NULL
)
402 *m_ad
->base_term2
= *m_ad
->base_term
;
404 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
405 *m_index_loc
= m_index_reg
;
408 /* Return true if the eliminated form of AD is a legitimate target address.
409 If OP is a MEM, AD is the address within OP, otherwise OP should be
410 ignored. CONSTRAINT is one constraint that the operand may need
413 valid_address_p (rtx op
, struct address_info
*ad
,
414 enum constraint_num constraint
)
416 address_eliminator
eliminator (ad
);
418 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
420 Need to extract memory from op for special memory constraint,
421 i.e. bcst_mem_operand in i386 backend. */
422 if (MEM_P (extract_mem_from_operand (op
))
423 && insn_extra_relaxed_memory_constraint (constraint
)
424 && constraint_satisfied_p (op
, constraint
))
427 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
430 /* For special_memory_operand, it could be false for MEM_P (op),
431 i.e. bcst_mem_operand in i386 backend.
432 Extract and return real memory operand or op. */
434 extract_mem_from_operand (rtx op
)
436 for (rtx x
= op
;; x
= XEXP (x
, 0))
440 if (GET_RTX_LENGTH (GET_CODE (x
)) != 1
441 || GET_RTX_FORMAT (GET_CODE (x
))[0] != 'e')
447 /* Return true if the eliminated form of memory reference OP satisfies
448 extra (special) memory constraint CONSTRAINT. */
450 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
452 struct address_info ad
;
453 rtx mem
= extract_mem_from_operand (op
);
457 decompose_mem_address (&ad
, mem
);
458 address_eliminator
eliminator (&ad
);
459 return constraint_satisfied_p (op
, constraint
);
462 /* Return true if the eliminated form of address AD satisfies extra
463 address constraint CONSTRAINT. */
465 satisfies_address_constraint_p (struct address_info
*ad
,
466 enum constraint_num constraint
)
468 address_eliminator
eliminator (ad
);
469 return constraint_satisfied_p (*ad
->outer
, constraint
);
472 /* Return true if the eliminated form of address OP satisfies extra
473 address constraint CONSTRAINT. */
475 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
477 struct address_info ad
;
479 decompose_lea_address (&ad
, &op
);
480 return satisfies_address_constraint_p (&ad
, constraint
);
483 /* Initiate equivalences for LRA. As we keep original equivalences
484 before any elimination, we need to make copies otherwise any change
485 in insns might change the equivalences. */
487 lra_init_equiv (void)
489 ira_expand_reg_equiv ();
490 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
494 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
495 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
496 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
497 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
501 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
503 /* Update equivalence for REGNO. We need to this as the equivalence
504 might contain other pseudos which are changed by their
507 update_equiv (int regno
)
511 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
512 ira_reg_equiv
[regno
].memory
513 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
515 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
516 ira_reg_equiv
[regno
].invariant
517 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
521 /* If we have decided to substitute X with another value, return that
522 value, otherwise return X. */
529 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
530 || ! ira_reg_equiv
[regno
].defined_p
531 || ! ira_reg_equiv
[regno
].profitable_p
532 || lra_get_regno_hard_regno (regno
) >= 0)
534 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
536 if (targetm
.cannot_substitute_mem_equiv_p (res
))
540 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
542 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
547 /* If we have decided to substitute X with the equivalent value,
548 return that value after elimination for INSN, otherwise return
551 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
553 rtx res
= get_equiv (x
);
555 if (x
== res
|| CONSTANT_P (res
))
557 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
558 false, false, 0, true);
561 /* Set up curr_operand_mode. */
563 init_curr_operand_mode (void)
565 int nop
= curr_static_id
->n_operands
;
566 for (int i
= 0; i
< nop
; i
++)
568 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
569 if (mode
== VOIDmode
)
571 /* The .md mode for address operands is the mode of the
572 addressed value rather than the mode of the address itself. */
573 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
576 mode
= curr_static_id
->operand
[i
].mode
;
578 curr_operand_mode
[i
] = mode
;
584 /* The page contains code to reuse input reloads. */
586 /* Structure describes input reload of the current insns. */
589 /* True for input reload of matched operands. */
591 /* Reloaded value. */
593 /* Reload pseudo used. */
597 /* The number of elements in the following array. */
598 static int curr_insn_input_reloads_num
;
599 /* Array containing info about input reloads. It is used to find the
600 same input reload and reuse the reload pseudo in this case. */
601 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
603 /* Initiate data concerning reuse of input reloads for the current
606 init_curr_insn_input_reloads (void)
608 curr_insn_input_reloads_num
= 0;
611 /* The canonical form of an rtx inside a MEM is not necessarily the same as the
612 canonical form of the rtx outside the MEM. Fix this up in the case that
613 we're reloading an address (and therefore pulling it outside a MEM). */
615 canonicalize_reload_addr (rtx addr
)
617 subrtx_var_iterator::array_type array
;
618 FOR_EACH_SUBRTX_VAR (iter
, array
, addr
, NONCONST
)
621 if (GET_CODE (x
) == MULT
&& CONST_INT_P (XEXP (x
, 1)))
623 const HOST_WIDE_INT ci
= INTVAL (XEXP (x
, 1));
624 const int pwr2
= exact_log2 (ci
);
627 /* Rewrite this to use a shift instead, which is canonical when
629 PUT_CODE (x
, ASHIFT
);
630 XEXP (x
, 1) = GEN_INT (pwr2
);
638 /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or
639 reuse an existing reload pseudo. Don't reuse an existing reload pseudo if
640 IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG.
641 The result pseudo is returned through RESULT_REG. Return TRUE if we created
642 a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to
643 describe new registers for debug purposes. */
645 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
646 enum reg_class rclass
, HARD_REG_SET
*exclude_start_hard_regs
,
647 bool in_subreg_p
, const char *title
, rtx
*result_reg
)
650 enum reg_class new_class
;
651 bool unique_p
= false;
655 /* Output reload registers tend to start out with a conservative
656 choice of register class. Usually this is ALL_REGS, although
657 a target might narrow it (for performance reasons) through
658 targetm.preferred_reload_class. It's therefore quite common
659 for a reload instruction to require a more restrictive class
660 than the class that was originally assigned to the reload register.
662 In these situations, it's more efficient to refine the choice
663 of register class rather than create a second reload register.
664 This also helps to avoid cycling for registers that are only
665 used by reload instructions. */
667 && (int) REGNO (original
) >= new_regno_start
668 && INSN_UID (curr_insn
) >= new_insn_uid_start
669 && in_class_p (original
, rclass
, &new_class
, true))
671 unsigned int regno
= REGNO (original
);
672 if (lra_dump_file
!= NULL
)
674 fprintf (lra_dump_file
, " Reuse r%d for output ", regno
);
675 dump_value_slim (lra_dump_file
, original
, 1);
677 if (new_class
!= lra_get_allocno_class (regno
))
678 lra_change_class (regno
, new_class
, ", change to", false);
679 if (lra_dump_file
!= NULL
)
680 fprintf (lra_dump_file
, "\n");
681 *result_reg
= original
;
685 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
,
686 exclude_start_hard_regs
, title
);
689 /* Prevent reuse value of expression with side effects,
690 e.g. volatile memory. */
691 if (! side_effects_p (original
))
692 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
694 if (! curr_insn_input_reloads
[i
].match_p
695 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
696 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
698 rtx reg
= curr_insn_input_reloads
[i
].reg
;
700 /* If input is equal to original and both are VOIDmode,
701 GET_MODE (reg) might be still different from mode.
702 Ensure we don't return *result_reg with wrong mode. */
703 if (GET_MODE (reg
) != mode
)
707 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg
)),
708 GET_MODE_SIZE (mode
)))
710 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
711 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
715 if (lra_dump_file
!= NULL
)
717 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
718 dump_value_slim (lra_dump_file
, original
, 1);
720 if (new_class
!= lra_get_allocno_class (regno
))
721 lra_change_class (regno
, new_class
, ", change to", false);
722 if (lra_dump_file
!= NULL
)
723 fprintf (lra_dump_file
, "\n");
726 /* If we have an input reload with a different mode, make sure it
727 will get a different hard reg. */
728 else if (REG_P (original
)
729 && REG_P (curr_insn_input_reloads
[i
].input
)
730 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
731 && (GET_MODE (original
)
732 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
735 *result_reg
= (unique_p
736 ? lra_create_new_reg_with_unique_value
737 : lra_create_new_reg
) (mode
, original
, rclass
,
738 exclude_start_hard_regs
, title
);
739 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
740 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
741 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
742 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
747 /* The page contains major code to choose the current insn alternative
748 and generate reloads for it. */
750 /* Return the offset from REGNO of the least significant register
753 This function is used to tell whether two registers satisfy
754 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
756 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
757 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
759 lra_constraint_offset (int regno
, machine_mode mode
)
761 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
763 scalar_int_mode int_mode
;
765 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
766 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
767 return hard_regno_nregs (regno
, mode
) - 1;
771 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
772 if they are the same hard reg, and has special hacks for
773 auto-increment and auto-decrement. This is specifically intended for
774 process_alt_operands to use in determining whether two operands
775 match. X is the operand whose number is the lower of the two.
777 It is supposed that X is the output operand and Y is the input
778 operand. Y_HARD_REGNO is the final hard regno of register Y or
779 register in subreg Y as we know it now. Otherwise, it is a
782 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
785 RTX_CODE code
= GET_CODE (x
);
790 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
791 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
795 i
= get_hard_regno (x
);
799 if ((j
= y_hard_regno
) < 0)
802 i
+= lra_constraint_offset (i
, GET_MODE (x
));
803 j
+= lra_constraint_offset (j
, GET_MODE (y
));
808 /* If two operands must match, because they are really a single
809 operand of an assembler insn, then two post-increments are invalid
810 because the assembler insn would increment only once. On the
811 other hand, a post-increment matches ordinary indexing if the
812 post-increment is the output operand. */
813 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
814 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
816 /* Two pre-increments are invalid because the assembler insn would
817 increment only once. On the other hand, a pre-increment matches
818 ordinary indexing if the pre-increment is the input operand. */
819 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
820 || GET_CODE (y
) == PRE_MODIFY
)
821 return operands_match_p (x
, XEXP (y
, 0), -1);
825 if (code
== REG
&& REG_P (y
))
826 return REGNO (x
) == REGNO (y
);
828 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
829 && x
== SUBREG_REG (y
))
831 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
832 && SUBREG_REG (x
) == y
)
835 /* Now we have disposed of all the cases in which different rtx
837 if (code
!= GET_CODE (y
))
840 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
841 if (GET_MODE (x
) != GET_MODE (y
))
850 if (!same_vector_encodings_p (x
, y
))
855 return label_ref_label (x
) == label_ref_label (y
);
857 return XSTR (x
, 0) == XSTR (y
, 0);
863 /* Compare the elements. If any pair of corresponding elements fail
864 to match, return false for the whole things. */
866 fmt
= GET_RTX_FORMAT (code
);
867 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
873 if (XWINT (x
, i
) != XWINT (y
, i
))
878 if (XINT (x
, i
) != XINT (y
, i
))
883 if (maybe_ne (SUBREG_BYTE (x
), SUBREG_BYTE (y
)))
888 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
897 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
899 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
901 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
907 /* It is believed that rtx's at this level will never
908 contain anything but integers and other rtx's, except for
909 within LABEL_REFs and SYMBOL_REFs. */
917 /* True if X is a constant that can be forced into the constant pool.
918 MODE is the mode of the operand, or VOIDmode if not known. */
919 #define CONST_POOL_OK_P(MODE, X) \
920 ((MODE) != VOIDmode \
922 && GET_CODE (X) != HIGH \
923 && GET_MODE_SIZE (MODE).is_constant () \
924 && !targetm.cannot_force_const_mem (MODE, X))
926 /* True if C is a non-empty register class that has too few registers
927 to be safely used as a reload target class. */
928 #define SMALL_REGISTER_CLASS_P(C) \
929 (ira_class_hard_regs_num [(C)] == 1 \
930 || (ira_class_hard_regs_num [(C)] >= 1 \
931 && targetm.class_likely_spilled_p (C)))
933 /* If REG is a reload pseudo, try to make its class satisfying CL. */
935 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
937 enum reg_class rclass
;
939 /* Do not make more accurate class from reloads generated. They are
940 mostly moves with a lot of constraints. Making more accurate
941 class may results in very narrow class and impossibility of find
942 registers for several reloads of one insn. */
943 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
945 if (GET_CODE (reg
) == SUBREG
)
946 reg
= SUBREG_REG (reg
);
947 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
949 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
950 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
953 /* Searches X for any reference to a reg with the same value as REGNO,
954 returning the rtx of the reference found if any. Otherwise,
957 regno_val_use_in (unsigned int regno
, rtx x
)
963 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
966 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
967 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
971 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
974 else if (fmt
[i
] == 'E')
975 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
976 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
983 /* Return true if all current insn non-output operands except INS (it
984 has a negaitve end marker) do not use pseudos with the same value
987 check_conflict_input_operands (int regno
, signed char *ins
)
990 int n_operands
= curr_static_id
->n_operands
;
992 for (int nop
= 0; nop
< n_operands
; nop
++)
993 if (! curr_static_id
->operand
[nop
].is_operator
994 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
996 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
1000 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
1006 /* Generate reloads for matching OUT and INS (array of input operand numbers
1007 with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS,
1008 considering output operands OUTS (similar array to INS) needing to be in
1009 different registers. Add input and output reloads correspondingly to the
1010 lists *BEFORE and *AFTER. OUT might be negative. In this case we generate
1011 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1012 that the output operand is early clobbered for chosen alternative. */
1014 match_reload (signed char out
, signed char *ins
, signed char *outs
,
1015 enum reg_class goal_class
, HARD_REG_SET
*exclude_start_hard_regs
,
1016 rtx_insn
**before
, rtx_insn
**after
, bool early_clobber_p
)
1020 rtx new_in_reg
, new_out_reg
, reg
;
1021 machine_mode inmode
, outmode
;
1022 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
1023 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
1025 inmode
= curr_operand_mode
[ins
[0]];
1026 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
1027 push_to_sequence (*before
);
1028 if (inmode
!= outmode
)
1030 /* process_alt_operands has already checked that the mode sizes
1032 if (partial_subreg_p (outmode
, inmode
))
1034 bool asm_p
= asm_noperands (PATTERN (curr_insn
)) >= 0;
1036 HARD_REG_SET temp_hard_reg_set
;
1038 if (asm_p
&& (hr
= get_hard_regno (out_rtx
)) >= 0
1039 && hard_regno_nregs (hr
, inmode
) > 1)
1041 /* See gcc.c-torture/execute/20030222-1.c.
1042 Consider the code for 32-bit (e.g. BE) target:
1043 int i, v; long x; x = v; asm ("" : "=r" (i) : "0" (x));
1044 We generate the following RTL with reload insns:
1045 1. subreg:si(x:di, 0) = 0;
1046 2. subreg:si(x:di, 4) = v:si;
1047 3. t:di = x:di, dead x;
1048 4. asm ("" : "=r" (subreg:si(t:di,4)) : "0" (t:di))
1049 5. i:si = subreg:si(t:di,4);
1050 If we assign hard reg of x to t, dead code elimination
1051 will remove insn #2 and we will use unitialized hard reg.
1052 So exclude the hard reg of x for t. We could ignore this
1053 problem for non-empty asm using all x value but it is hard to
1054 check that the asm are expanded into insn realy using x
1056 CLEAR_HARD_REG_SET (temp_hard_reg_set
);
1057 if (exclude_start_hard_regs
!= NULL
)
1058 temp_hard_reg_set
= *exclude_start_hard_regs
;
1059 SET_HARD_REG_BIT (temp_hard_reg_set
, hr
);
1060 exclude_start_hard_regs
= &temp_hard_reg_set
;
1063 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
, goal_class
,
1064 exclude_start_hard_regs
,
1066 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
1067 LRA_SUBREG_P (new_out_reg
) = 1;
1068 /* If the input reg is dying here, we can use the same hard
1069 register for REG and IN_RTX. We do it only for original
1070 pseudos as reload pseudos can die although original
1071 pseudos still live where reload pseudos dies. */
1072 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
1073 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1074 && (!early_clobber_p
1075 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
1076 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
1081 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1083 exclude_start_hard_regs
,
1085 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
1086 /* NEW_IN_REG is non-paradoxical subreg. We don't want
1087 NEW_OUT_REG living above. We add clobber clause for
1088 this. This is just a temporary clobber. We can remove
1089 it at the end of LRA work. */
1090 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
1091 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
1092 LRA_SUBREG_P (new_in_reg
) = 1;
1093 if (GET_CODE (in_rtx
) == SUBREG
)
1095 rtx subreg_reg
= SUBREG_REG (in_rtx
);
1097 /* If SUBREG_REG is dying here and sub-registers IN_RTX
1098 and NEW_IN_REG are similar, we can use the same hard
1099 register for REG and SUBREG_REG. */
1100 if (REG_P (subreg_reg
)
1101 && (int) REGNO (subreg_reg
) < lra_new_regno_start
1102 && GET_MODE (subreg_reg
) == outmode
1103 && known_eq (SUBREG_BYTE (in_rtx
), SUBREG_BYTE (new_in_reg
))
1104 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
1105 && (! early_clobber_p
1106 || check_conflict_input_operands (REGNO (subreg_reg
),
1108 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
1114 /* Pseudos have values -- see comments for lra_reg_info.
1115 Different pseudos with the same value do not conflict even if
1116 they live in the same place. When we create a pseudo we
1117 assign value of original pseudo (if any) from which we
1118 created the new pseudo. If we create the pseudo from the
1119 input pseudo, the new pseudo will have no conflict with the
1120 input pseudo which is wrong when the input pseudo lives after
1121 the insn and as the new pseudo value is changed by the insn
1122 output. Therefore we create the new pseudo from the output
1123 except the case when we have single matched dying input
1126 We cannot reuse the current output register because we might
1127 have a situation like "a <- a op b", where the constraints
1128 force the second input operand ("b") to match the output
1129 operand ("a"). "b" must then be copied into a new register
1130 so that it doesn't clobber the current value of "a".
1132 We cannot use the same value if the output pseudo is
1133 early clobbered or the input pseudo is mentioned in the
1134 output, e.g. as an address part in memory, because
1135 output reload will actually extend the pseudo liveness.
1136 We don't care about eliminable hard regs here as we are
1137 interesting only in pseudos. */
1139 /* Matching input's register value is the same as one of the other
1140 output operand. Output operands in a parallel insn must be in
1141 different registers. */
1142 out_conflict
= false;
1145 for (i
= 0; outs
[i
] >= 0; i
++)
1147 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1148 if (outs
[i
] != out
&& REG_P (other_out_rtx
)
1149 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1152 out_conflict
= true;
1158 new_in_reg
= new_out_reg
1159 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1160 && (int) REGNO (in_rtx
) < lra_new_regno_start
1161 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1162 && (! early_clobber_p
1163 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1165 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1167 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
,
1168 exclude_start_hard_regs
, "")
1169 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
, goal_class
,
1170 exclude_start_hard_regs
,
1173 /* In operand can be got from transformations before processing insn
1174 constraints. One example of such transformations is subreg
1175 reloading (see function simplify_operand_subreg). The new
1176 pseudos created by the transformations might have inaccurate
1177 class (ALL_REGS) and we should make their classes more
1179 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1180 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1181 *before
= get_insns ();
1183 /* Add the new pseudo to consider values of subsequent input reload
1185 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1186 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1187 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1188 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1189 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1190 if (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1191 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]))
1192 *curr_id
->operand_loc
[in
] = new_in_reg
;
1196 (GET_MODE (new_out_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1197 *curr_id
->operand_loc
[in
] = new_out_reg
;
1199 lra_update_dups (curr_id
, ins
);
1202 /* See a comment for the input operand above. */
1203 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1204 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1206 reg
= SUBREG_P (out_rtx
) ? SUBREG_REG (out_rtx
) : out_rtx
;
1208 /* If we had strict_low_part, use it also in reload to keep other
1209 parts unchanged but do it only for regs as strict_low_part
1210 has no sense for memory and probably there is no insn pattern
1211 to match the reload insn in memory case. */
1212 if (out
>= 0 && curr_static_id
->operand
[out
].strict_low
&& REG_P (reg
))
1213 out_rtx
= gen_rtx_STRICT_LOW_PART (VOIDmode
, out_rtx
);
1214 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1216 *after
= get_insns ();
1219 *curr_id
->operand_loc
[out
] = new_out_reg
;
1220 lra_update_dup (curr_id
, out
);
1223 /* Return register class which is union of all reg classes in insn
1224 constraint alternative string starting with P. */
1225 static enum reg_class
1226 reg_class_from_constraints (const char *p
)
1229 enum reg_class op_class
= NO_REGS
;
1232 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1239 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1243 enum constraint_num cn
= lookup_constraint (p
);
1244 enum reg_class cl
= reg_class_for_constraint (cn
);
1247 if (insn_extra_address_constraint (cn
))
1249 = (reg_class_subunion
1250 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1251 ADDRESS
, SCRATCH
)]);
1255 op_class
= reg_class_subunion
[op_class
][cl
];
1258 while ((p
+= len
), c
);
1262 /* If OP is a register, return the class of the register as per
1263 get_reg_class, otherwise return NO_REGS. */
1264 static inline enum reg_class
1265 get_op_class (rtx op
)
1267 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1270 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1271 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1272 SUBREG for VAL to make them equal. */
1274 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1276 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1278 /* Usually size of mem_pseudo is greater than val size but in
1279 rare cases it can be less as it can be defined by target
1280 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1283 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1284 GET_CODE (val
) == SUBREG
1285 ? SUBREG_REG (val
) : val
);
1286 LRA_SUBREG_P (val
) = 1;
1290 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1291 LRA_SUBREG_P (mem_pseudo
) = 1;
1294 return to_p
? gen_move_insn (mem_pseudo
, val
)
1295 : gen_move_insn (val
, mem_pseudo
);
1298 /* Process a special case insn (register move), return true if we
1299 don't need to process it anymore. INSN should be a single set
1300 insn. Set up that RTL was changed through CHANGE_P and that hook
1301 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1304 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1307 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1309 enum reg_class dclass
, sclass
, secondary_class
;
1310 secondary_reload_info sri
;
1312 lra_assert (curr_insn_set
!= NULL_RTX
);
1313 dreg
= dest
= SET_DEST (curr_insn_set
);
1314 sreg
= src
= SET_SRC (curr_insn_set
);
1315 if (GET_CODE (dest
) == SUBREG
)
1316 dreg
= SUBREG_REG (dest
);
1317 if (GET_CODE (src
) == SUBREG
)
1318 sreg
= SUBREG_REG (src
);
1319 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1321 sclass
= dclass
= NO_REGS
;
1323 dclass
= get_reg_class (REGNO (dreg
));
1324 gcc_assert (dclass
< LIM_REG_CLASSES
&& dclass
>= NO_REGS
);
1325 if (dclass
== ALL_REGS
)
1326 /* ALL_REGS is used for new pseudos created by transformations
1327 like reload of SUBREG_REG (see function
1328 simplify_operand_subreg). We don't know their class yet. We
1329 should figure out the class from processing the insn
1330 constraints not in this fast path function. Even if ALL_REGS
1331 were a right class for the pseudo, secondary_... hooks usually
1332 are not define for ALL_REGS. */
1335 sclass
= get_reg_class (REGNO (sreg
));
1336 gcc_assert (sclass
< LIM_REG_CLASSES
&& sclass
>= NO_REGS
);
1337 if (sclass
== ALL_REGS
)
1338 /* See comments above. */
1340 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1342 if (targetm
.secondary_memory_needed (GET_MODE (src
), sclass
, dclass
)
1343 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1345 != targetm
.secondary_memory_needed_mode (GET_MODE (src
)))))
1350 if (! REG_P (dreg
) || ! REG_P (sreg
))
1352 sri
.prev_sri
= NULL
;
1353 sri
.icode
= CODE_FOR_nothing
;
1355 secondary_class
= NO_REGS
;
1356 /* Set up hard register for a reload pseudo for hook
1357 secondary_reload because some targets just ignore unassigned
1358 pseudos in the hook. */
1359 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1361 dregno
= REGNO (dreg
);
1362 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1366 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1368 sregno
= REGNO (sreg
);
1369 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1373 if (sclass
!= NO_REGS
)
1375 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1376 (reg_class_t
) sclass
,
1377 GET_MODE (src
), &sri
);
1378 if (sclass
== NO_REGS
1379 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1380 && dclass
!= NO_REGS
))
1382 enum reg_class old_sclass
= secondary_class
;
1383 secondary_reload_info old_sri
= sri
;
1385 sri
.prev_sri
= NULL
;
1386 sri
.icode
= CODE_FOR_nothing
;
1389 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1390 (reg_class_t
) dclass
,
1391 GET_MODE (src
), &sri
);
1392 /* Check the target hook consistency. */
1394 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1395 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1396 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1399 reg_renumber
[sregno
] = -1;
1401 reg_renumber
[dregno
] = -1;
1402 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1406 if (secondary_class
!= NO_REGS
)
1407 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1408 secondary_class
, NULL
,
1411 if (sri
.icode
== CODE_FOR_nothing
)
1412 lra_emit_move (new_reg
, src
);
1415 enum reg_class scratch_class
;
1417 scratch_class
= (reg_class_from_constraints
1418 (insn_data
[sri
.icode
].operand
[2].constraint
));
1419 scratch_reg
= (lra_create_new_reg_with_unique_value
1420 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1421 scratch_class
, NULL
, "scratch"));
1422 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1425 before
= get_insns ();
1427 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1428 if (new_reg
!= NULL_RTX
)
1429 SET_SRC (curr_insn_set
) = new_reg
;
1432 if (lra_dump_file
!= NULL
)
1434 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1435 dump_insn_slim (lra_dump_file
, curr_insn
);
1437 lra_set_insn_deleted (curr_insn
);
1443 /* The following data describe the result of process_alt_operands.
1444 The data are used in curr_insn_transform to generate reloads. */
1446 /* The chosen reg classes which should be used for the corresponding
1448 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1449 /* Hard registers which cannot be a start hard register for the corresponding
1451 static HARD_REG_SET goal_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
1452 /* True if the operand should be the same as another operand and that
1453 other operand does not need a reload. */
1454 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1455 /* True if the operand does not need a reload. */
1456 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1457 /* True if the operand can be offsetable memory. */
1458 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1459 /* The number of an operand to which given operand can be matched to. */
1460 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1461 /* The number of elements in the following array. */
1462 static int goal_alt_dont_inherit_ops_num
;
1463 /* Numbers of operands whose reload pseudos should not be inherited. */
1464 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1465 /* True if the insn commutative operands should be swapped. */
1466 static bool goal_alt_swapped
;
1467 /* The chosen insn alternative. */
1468 static int goal_alt_number
;
1469 /* True if output reload of the stack pointer should be generated. */
1470 static bool goal_alt_out_sp_reload_p
;
1472 /* True if the corresponding operand is the result of an equivalence
1474 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1476 /* The following five variables are used to choose the best insn
1477 alternative. They reflect final characteristics of the best
1480 /* Number of necessary reloads and overall cost reflecting the
1481 previous value and other unpleasantness of the best alternative. */
1482 static int best_losers
, best_overall
;
1483 /* Overall number hard registers used for reloads. For example, on
1484 some targets we need 2 general registers to reload DFmode and only
1485 one floating point register. */
1486 static int best_reload_nregs
;
1487 /* Overall number reflecting distances of previous reloading the same
1488 value. The distances are counted from the current BB start. It is
1489 used to improve inheritance chances. */
1490 static int best_reload_sum
;
1492 /* True if the current insn should have no correspondingly input or
1494 static bool no_input_reloads_p
, no_output_reloads_p
;
1496 /* True if we swapped the commutative operands in the current
1498 static int curr_swapped
;
1500 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1501 register of class CL. Add any input reloads to list BEFORE. AFTER
1502 is nonnull if *LOC is an automodified value; handle that case by
1503 adding the required output reloads to list AFTER. Return true if
1504 the RTL was changed.
1506 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1507 register. Return false if the address register is correct. */
1509 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1513 enum reg_class rclass
, new_class
;
1517 bool subreg_p
, before_p
= false;
1519 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1522 reg
= SUBREG_REG (*loc
);
1523 mode
= GET_MODE (reg
);
1525 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1526 between two registers with different classes, but there normally will
1527 be "mov" which transfers element of vector register into the general
1528 register, and this normally will be a subreg which should be reloaded
1529 as a whole. This is particularly likely to be triggered when
1530 -fno-split-wide-types specified. */
1532 || in_class_p (reg
, cl
, &new_class
)
1533 || known_le (GET_MODE_SIZE (mode
), GET_MODE_SIZE (ptr_mode
)))
1534 loc
= &SUBREG_REG (*loc
);
1538 mode
= GET_MODE (reg
);
1543 /* Always reload memory in an address even if the target supports
1545 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, NULL
,
1551 regno
= REGNO (reg
);
1552 rclass
= get_reg_class (regno
);
1554 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1556 if (lra_dump_file
!= NULL
)
1558 fprintf (lra_dump_file
,
1559 "Changing pseudo %d in address of insn %u on equiv ",
1560 REGNO (reg
), INSN_UID (curr_insn
));
1561 dump_value_slim (lra_dump_file
, *loc
, 1);
1562 fprintf (lra_dump_file
, "\n");
1564 *loc
= copy_rtx (*loc
);
1566 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1571 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1572 mode
, reg
, cl
, NULL
,
1573 subreg_p
, "address", &new_reg
))
1576 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1580 lra_change_class (regno
, new_class
, " Change to", true);
1588 push_to_sequence (*before
);
1589 lra_emit_move (new_reg
, reg
);
1590 *before
= get_insns ();
1597 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1599 *after
= get_insns ();
1605 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1606 the insn to be inserted before curr insn. AFTER returns the
1607 the insn to be inserted after curr insn. ORIGREG and NEWREG
1608 are the original reg and new reg for reload. */
1610 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1615 push_to_sequence (*before
);
1616 lra_emit_move (newreg
, origreg
);
1617 *before
= get_insns ();
1623 lra_emit_move (origreg
, newreg
);
1625 *after
= get_insns ();
1630 static bool valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1631 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1633 /* Make reloads for subreg in operand NOP with internal subreg mode
1634 REG_MODE, add new reloads for further processing. Return true if
1635 any change was done. */
1637 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1639 int hard_regno
, inner_hard_regno
;
1640 rtx_insn
*before
, *after
;
1641 machine_mode mode
, innermode
;
1643 rtx operand
= *curr_id
->operand_loc
[nop
];
1644 enum reg_class regclass
;
1647 before
= after
= NULL
;
1649 if (GET_CODE (operand
) != SUBREG
)
1652 mode
= GET_MODE (operand
);
1653 reg
= SUBREG_REG (operand
);
1654 innermode
= GET_MODE (reg
);
1655 type
= curr_static_id
->operand
[nop
].type
;
1658 const bool addr_was_valid
1659 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1660 alter_subreg (curr_id
->operand_loc
[nop
], false);
1661 rtx subst
= *curr_id
->operand_loc
[nop
];
1662 lra_assert (MEM_P (subst
));
1663 const bool addr_is_valid
= valid_address_p (GET_MODE (subst
),
1665 MEM_ADDR_SPACE (subst
));
1668 || ((get_constraint_type (lookup_constraint
1669 (curr_static_id
->operand
[nop
].constraint
))
1670 != CT_SPECIAL_MEMORY
)
1671 /* We still can reload address and if the address is
1672 valid, we can remove subreg without reloading its
1674 && valid_address_p (GET_MODE (subst
),
1676 [ira_class_hard_regs
1677 [base_reg_class (GET_MODE (subst
),
1678 MEM_ADDR_SPACE (subst
),
1679 ADDRESS
, SCRATCH
)][0]],
1680 MEM_ADDR_SPACE (subst
))))
1682 /* If we change the address for a paradoxical subreg of memory, the
1683 new address might violate the necessary alignment or the access
1684 might be slow; take this into consideration. We need not worry
1685 about accesses beyond allocated memory for paradoxical memory
1686 subregs as we don't substitute such equiv memory (see processing
1687 equivalences in function lra_constraints) and because for spilled
1688 pseudos we allocate stack memory enough for the biggest
1689 corresponding paradoxical subreg.
1691 However, do not blindly simplify a (subreg (mem ...)) for
1692 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1693 data into a register when the inner is narrower than outer or
1694 missing important data from memory when the inner is wider than
1695 outer. This rule only applies to modes that are no wider than
1698 If valid memory becomes invalid after subreg elimination
1699 and address might be different we still have to reload
1702 if ((! addr_was_valid
1704 || known_eq (GET_MODE_SIZE (mode
), GET_MODE_SIZE (innermode
)))
1705 && !(maybe_ne (GET_MODE_PRECISION (mode
),
1706 GET_MODE_PRECISION (innermode
))
1707 && known_le (GET_MODE_SIZE (mode
), UNITS_PER_WORD
)
1708 && known_le (GET_MODE_SIZE (innermode
), UNITS_PER_WORD
)
1709 && WORD_REGISTER_OPERATIONS
)
1710 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1711 && targetm
.slow_unaligned_access (mode
, MEM_ALIGN (subst
)))
1712 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1713 && targetm
.slow_unaligned_access (innermode
,
1717 *curr_id
->operand_loc
[nop
] = operand
;
1719 /* But if the address was not valid, we cannot reload the MEM without
1720 reloading the address first. */
1721 if (!addr_was_valid
)
1722 process_address (nop
, false, &before
, &after
);
1724 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1725 enum reg_class rclass
1726 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1727 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1729 true, "slow/invalid mem", &new_reg
))
1731 bool insert_before
, insert_after
;
1732 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1734 insert_before
= (type
!= OP_OUT
1735 || partial_subreg_p (mode
, innermode
));
1736 insert_after
= type
!= OP_IN
;
1737 insert_move_for_subreg (insert_before
? &before
: NULL
,
1738 insert_after
? &after
: NULL
,
1741 SUBREG_REG (operand
) = new_reg
;
1743 /* Convert to MODE. */
1746 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1747 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1749 true, "slow/invalid mem", &new_reg
))
1751 bool insert_before
, insert_after
;
1752 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1754 insert_before
= type
!= OP_OUT
;
1755 insert_after
= type
!= OP_IN
;
1756 insert_move_for_subreg (insert_before
? &before
: NULL
,
1757 insert_after
? &after
: NULL
,
1760 *curr_id
->operand_loc
[nop
] = new_reg
;
1761 lra_process_new_insns (curr_insn
, before
, after
,
1762 "Inserting slow/invalid mem reload");
1766 /* If the address was valid and became invalid, prefer to reload
1767 the memory. Typical case is when the index scale should
1768 correspond the memory. */
1769 *curr_id
->operand_loc
[nop
] = operand
;
1770 /* Do not return false here as the MEM_P (reg) will be processed
1771 later in this function. */
1773 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1775 alter_subreg (curr_id
->operand_loc
[nop
], false);
1778 else if (CONSTANT_P (reg
))
1780 /* Try to simplify subreg of constant. It is usually result of
1781 equivalence substitution. */
1782 if (innermode
== VOIDmode
1783 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1784 innermode
= curr_static_id
->operand
[nop
].mode
;
1785 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1786 SUBREG_BYTE (operand
))) != NULL_RTX
)
1788 *curr_id
->operand_loc
[nop
] = new_reg
;
1792 /* Put constant into memory when we have mixed modes. It generates
1793 a better code in most cases as it does not need a secondary
1794 reload memory. It also prevents LRA looping when LRA is using
1795 secondary reload memory again and again. */
1796 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1797 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1799 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1800 alter_subreg (curr_id
->operand_loc
[nop
], false);
1803 auto fp_subreg_can_be_simplified_after_reload_p
= [] (machine_mode innermode
,
1805 machine_mode mode
) {
1806 reload_completed
= 1;
1807 bool res
= simplify_subreg_regno (FRAME_POINTER_REGNUM
,
1810 reload_completed
= 0;
1813 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1814 if there may be a problem accessing OPERAND in the outer
1817 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1818 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1819 /* Don't reload paradoxical subregs because we could be looping
1820 having repeatedly final regno out of hard regs range. */
1821 && (hard_regno_nregs (hard_regno
, innermode
)
1822 >= hard_regno_nregs (hard_regno
, mode
))
1823 && simplify_subreg_regno (hard_regno
, innermode
,
1824 SUBREG_BYTE (operand
), mode
) < 0
1825 /* Exclude reloading of frame pointer in subreg if frame pointer can not
1826 be simplified here only because the reload is not finished yet. */
1827 && (hard_regno
!= FRAME_POINTER_REGNUM
1828 || !fp_subreg_can_be_simplified_after_reload_p (innermode
,
1829 SUBREG_BYTE (operand
),
1831 /* Don't reload subreg for matching reload. It is actually
1832 valid subreg in LRA. */
1833 && ! LRA_SUBREG_P (operand
))
1834 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1836 enum reg_class rclass
;
1839 /* There is a big probability that we will get the same class
1840 for the new pseudo and we will get the same insn which
1841 means infinite looping. So spill the new pseudo. */
1844 /* The class will be defined later in curr_insn_transform. */
1846 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1848 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1850 true, "subreg reg", &new_reg
))
1852 bool insert_before
, insert_after
;
1853 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1855 insert_before
= (type
!= OP_OUT
1856 || read_modify_subreg_p (operand
));
1857 insert_after
= (type
!= OP_IN
);
1858 insert_move_for_subreg (insert_before
? &before
: NULL
,
1859 insert_after
? &after
: NULL
,
1862 SUBREG_REG (operand
) = new_reg
;
1863 lra_process_new_insns (curr_insn
, before
, after
,
1864 "Inserting subreg reload");
1867 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1868 IRA allocates hardreg to the inner pseudo reg according to its mode
1869 instead of the outermode, so the size of the hardreg may not be enough
1870 to contain the outermode operand, in that case we may need to insert
1871 reload for the reg. For the following two types of paradoxical subreg,
1872 we need to insert reload:
1873 1. If the op_type is OP_IN, and the hardreg could not be paired with
1874 other hardreg to contain the outermode operand
1875 (checked by in_hard_reg_set_p), we need to insert the reload.
1876 2. If the op_type is OP_OUT or OP_INOUT.
1878 Here is a paradoxical subreg example showing how the reload is generated:
1880 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1881 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1883 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1884 here, if reg107 is assigned to hardreg R15, because R15 is the last
1885 hardreg, compiler cannot find another hardreg to pair with R15 to
1886 contain TImode data. So we insert a TImode reload reg180 for it.
1887 After reload is inserted:
1889 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1890 (reg:DI 107 [ __comp ])) -1
1891 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1892 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1894 Two reload hard registers will be allocated to reg180 to save TImode data
1897 For LRA pseudos this should normally be handled by the biggest_mode
1898 mechanism. However, it's possible for new uses of an LRA pseudo
1899 to be introduced after we've allocated it, such as when undoing
1900 inheritance, and the allocated register might not then be appropriate
1901 for the new uses. */
1902 else if (REG_P (reg
)
1903 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1904 && paradoxical_subreg_p (operand
)
1905 && (inner_hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1907 = simplify_subreg_regno (inner_hard_regno
, innermode
,
1908 SUBREG_BYTE (operand
), mode
)) < 0
1909 || ((hard_regno_nregs (inner_hard_regno
, innermode
)
1910 < hard_regno_nregs (hard_regno
, mode
))
1911 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1913 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1915 || overlaps_hard_reg_set_p (lra_no_alloc_regs
,
1916 mode
, hard_regno
)))))
1918 /* The class will be defined later in curr_insn_transform. */
1919 enum reg_class rclass
1920 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1922 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1924 true, "paradoxical subreg", &new_reg
))
1927 bool insert_before
, insert_after
;
1929 PUT_MODE (new_reg
, mode
);
1930 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1931 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1933 insert_before
= (type
!= OP_OUT
);
1934 insert_after
= (type
!= OP_IN
);
1935 insert_move_for_subreg (insert_before
? &before
: NULL
,
1936 insert_after
? &after
: NULL
,
1939 SUBREG_REG (operand
) = new_reg
;
1940 lra_process_new_insns (curr_insn
, before
, after
,
1941 "Inserting paradoxical subreg reload");
1947 /* Return TRUE if X refers for a hard register from SET. */
1949 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1951 int i
, j
, x_hard_regno
;
1958 code
= GET_CODE (x
);
1959 mode
= GET_MODE (x
);
1963 /* For all SUBREGs we want to check whether the full multi-register
1964 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1965 the inner register, for paradoxical SUBREGs this means the
1966 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1967 fine. Use the wider mode for all cases. */
1968 rtx subreg
= SUBREG_REG (x
);
1969 mode
= wider_subreg_mode (x
);
1970 if (mode
== GET_MODE (subreg
))
1973 code
= GET_CODE (x
);
1977 if (REG_P (x
) || SUBREG_P (x
))
1979 x_hard_regno
= get_hard_regno (x
);
1980 return (x_hard_regno
>= 0
1981 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1983 fmt
= GET_RTX_FORMAT (code
);
1984 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1988 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1991 else if (fmt
[i
] == 'E')
1993 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1994 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
2001 /* Return true if OP is a spilled pseudo. */
2003 spilled_pseudo_p (rtx op
)
2006 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
2009 /* Return true if X is a general constant. */
2011 general_constant_p (rtx x
)
2013 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
2017 reg_in_class_p (rtx reg
, enum reg_class cl
)
2020 return get_reg_class (REGNO (reg
)) == NO_REGS
;
2021 return in_class_p (reg
, cl
, NULL
);
2024 /* Return true if SET of RCLASS contains no hard regs which can be
2027 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
2033 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
2034 temp
= set
& ~lra_no_alloc_regs
;
2035 return (hard_reg_set_subset_p
2036 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
2040 /* Used to check validity info about small class input operands. It
2041 should be incremented at start of processing an insn
2043 static unsigned int curr_small_class_check
= 0;
2045 /* Update number of used inputs of class OP_CLASS for operand NOP
2046 of alternative NALT. Return true if we have more such class operands
2047 than the number of available regs. */
2049 update_and_check_small_class_inputs (int nop
, int nalt
,
2050 enum reg_class op_class
)
2052 static unsigned int small_class_check
[LIM_REG_CLASSES
];
2053 static int small_class_input_nums
[LIM_REG_CLASSES
];
2055 if (SMALL_REGISTER_CLASS_P (op_class
)
2056 /* We are interesting in classes became small because of fixing
2057 some hard regs, e.g. by an user through GCC options. */
2058 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
2060 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
2061 || TEST_BIT (curr_static_id
->operand
[nop
].early_clobber_alts
, nalt
)))
2063 if (small_class_check
[op_class
] == curr_small_class_check
)
2064 small_class_input_nums
[op_class
]++;
2067 small_class_check
[op_class
] = curr_small_class_check
;
2068 small_class_input_nums
[op_class
] = 1;
2070 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
2076 /* Print operand constraints for alternative ALT_NUMBER of the current
2079 print_curr_insn_alt (int alt_number
)
2081 for (int i
= 0; i
< curr_static_id
->n_operands
; i
++)
2083 const char *p
= (curr_static_id
->operand_alternative
2084 [alt_number
* curr_static_id
->n_operands
+ i
].constraint
);
2087 fprintf (lra_dump_file
, " (%d) ", i
);
2088 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2089 fputc (*p
, lra_dump_file
);
2093 /* Major function to choose the current insn alternative and what
2094 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2095 negative we should consider only this alternative. Return false if
2096 we cannot choose the alternative or find how to reload the
2099 process_alt_operands (int only_alternative
)
2102 int nop
, overall
, nalt
;
2103 int n_alternatives
= curr_static_id
->n_alternatives
;
2104 int n_operands
= curr_static_id
->n_operands
;
2105 /* LOSERS counts the operands that don't fit this alternative and
2106 would require loading. */
2109 /* REJECT is a count of how undesirable this alternative says it is
2110 if any reloading is required. If the alternative matches exactly
2111 then REJECT is ignored, but otherwise it gets this much counted
2112 against it in addition to the reloading needed. */
2114 /* This is defined by '!' or '?' alternative constraint and added to
2115 reject. But in some cases it can be ignored. */
2118 /* The number of elements in the following array. */
2119 int early_clobbered_regs_num
;
2120 /* Numbers of operands which are early clobber registers. */
2121 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
2122 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
2123 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
2124 HARD_REG_SET curr_alt_exclude_start_hard_regs
[MAX_RECOG_OPERANDS
];
2125 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
2126 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
2127 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
2128 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
2129 /* The number of elements in the following array. */
2130 int curr_alt_dont_inherit_ops_num
;
2131 /* Numbers of operands whose reload pseudos should not be inherited. */
2132 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
2133 /* True if output stack pointer reload should be generated for the current
2135 bool curr_alt_out_sp_reload_p
;
2137 /* The register when the operand is a subreg of register, otherwise the
2139 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
2140 /* The register if the operand is a register or subreg of register,
2142 rtx operand_reg
[MAX_RECOG_OPERANDS
];
2143 int hard_regno
[MAX_RECOG_OPERANDS
];
2144 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
2145 int reload_nregs
, reload_sum
;
2149 /* Calculate some data common for all alternatives to speed up the
2151 for (nop
= 0; nop
< n_operands
; nop
++)
2155 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
2156 /* The real hard regno of the operand after the allocation. */
2157 hard_regno
[nop
] = get_hard_regno (op
);
2159 operand_reg
[nop
] = reg
= op
;
2160 biggest_mode
[nop
] = GET_MODE (op
);
2161 if (GET_CODE (op
) == SUBREG
)
2163 biggest_mode
[nop
] = wider_subreg_mode (op
);
2164 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
2167 operand_reg
[nop
] = NULL_RTX
;
2168 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2169 || ((int) REGNO (reg
)
2170 == lra_get_elimination_hard_regno (REGNO (reg
))))
2171 no_subreg_reg_operand
[nop
] = reg
;
2173 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
2174 /* Just use natural mode for elimination result. It should
2175 be enough for extra constraints hooks. */
2176 = regno_reg_rtx
[hard_regno
[nop
]];
2179 /* The constraints are made of several alternatives. Each operand's
2180 constraint looks like foo,bar,... with commas separating the
2181 alternatives. The first alternatives for all operands go
2182 together, the second alternatives go together, etc.
2184 First loop over alternatives. */
2185 alternative_mask preferred
= curr_id
->preferred_alternatives
;
2186 if (only_alternative
>= 0)
2187 preferred
&= ALTERNATIVE_BIT (only_alternative
);
2189 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
2191 /* Loop over operands for one constraint alternative. */
2192 if (!TEST_BIT (preferred
, nalt
))
2195 if (lra_dump_file
!= NULL
)
2197 fprintf (lra_dump_file
, " Considering alt=%d of insn %d: ",
2198 nalt
, INSN_UID (curr_insn
));
2199 print_curr_insn_alt (nalt
);
2200 fprintf (lra_dump_file
, "\n");
2203 bool matching_early_clobber
[MAX_RECOG_OPERANDS
];
2204 curr_small_class_check
++;
2205 overall
= losers
= addr_losers
= 0;
2206 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
2207 for (nop
= 0; nop
< n_operands
; nop
++)
2209 int inc
= (curr_static_id
2210 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2211 if (lra_dump_file
!= NULL
&& inc
!= 0)
2212 fprintf (lra_dump_file
,
2213 " Staticly defined alt reject+=%d\n", inc
);
2214 static_reject
+= inc
;
2215 matching_early_clobber
[nop
] = 0;
2217 reject
+= static_reject
;
2218 early_clobbered_regs_num
= 0;
2219 curr_alt_out_sp_reload_p
= false;
2221 for (nop
= 0; nop
< n_operands
; nop
++)
2225 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2226 bool win
, did_match
, offmemok
, early_clobber_p
;
2227 /* false => this operand can be reloaded somehow for this
2230 /* true => this operand can be reloaded if the alternative
2233 /* True if a constant forced into memory would be OK for
2236 enum reg_class this_alternative
, this_costly_alternative
;
2237 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2238 HARD_REG_SET this_alternative_exclude_start_hard_regs
;
2239 bool this_alternative_match_win
, this_alternative_win
;
2240 bool this_alternative_offmemok
;
2243 enum constraint_num cn
;
2245 opalt_num
= nalt
* n_operands
+ nop
;
2246 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2248 /* Fast track for no constraints at all. */
2249 curr_alt
[nop
] = NO_REGS
;
2250 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2251 curr_alt_win
[nop
] = true;
2252 curr_alt_match_win
[nop
] = false;
2253 curr_alt_offmemok
[nop
] = false;
2254 curr_alt_matches
[nop
] = -1;
2258 op
= no_subreg_reg_operand
[nop
];
2259 mode
= curr_operand_mode
[nop
];
2261 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2264 early_clobber_p
= false;
2265 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2267 this_costly_alternative
= this_alternative
= NO_REGS
;
2268 /* We update set of possible hard regs besides its class
2269 because reg class might be inaccurate. For example,
2270 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2271 is translated in HI_REGS because classes are merged by
2272 pairs and there is no accurate intermediate class. */
2273 CLEAR_HARD_REG_SET (this_alternative_set
);
2274 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2275 CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs
);
2276 this_alternative_win
= false;
2277 this_alternative_match_win
= false;
2278 this_alternative_offmemok
= false;
2279 this_alternative_matches
= -1;
2281 /* An empty constraint should be excluded by the fast
2283 lra_assert (*p
!= 0 && *p
!= ',');
2286 /* Scan this alternative's specs for this operand; set WIN
2287 if the operand fits any letter in this alternative.
2288 Otherwise, clear BADOP if this operand could fit some
2289 letter after reloads, or set WINREG if this operand could
2290 fit after reloads provided the constraint allows some
2295 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2305 early_clobber_p
= true;
2309 op_reject
+= LRA_MAX_REJECT
;
2312 op_reject
+= LRA_LOSER_COST_FACTOR
;
2316 /* Ignore rest of this alternative. */
2320 case '0': case '1': case '2': case '3': case '4':
2321 case '5': case '6': case '7': case '8': case '9':
2326 m
= strtoul (p
, &end
, 10);
2329 lra_assert (nop
> m
);
2331 /* Reject matches if we don't know which operand is
2332 bigger. This situation would arguably be a bug in
2333 an .md pattern, but could also occur in a user asm. */
2334 if (!ordered_p (GET_MODE_SIZE (biggest_mode
[m
]),
2335 GET_MODE_SIZE (biggest_mode
[nop
])))
2338 /* Don't match wrong asm insn operands for proper
2339 diagnostic later. */
2340 if (INSN_CODE (curr_insn
) < 0
2341 && (curr_operand_mode
[m
] == BLKmode
2342 || curr_operand_mode
[nop
] == BLKmode
)
2343 && curr_operand_mode
[m
] != curr_operand_mode
[nop
])
2346 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
2347 /* We are supposed to match a previous operand.
2348 If we do, we win if that one did. If we do
2349 not, count both of the operands as losers.
2350 (This is too conservative, since most of the
2351 time only a single reload insn will be needed
2352 to make the two operands win. As a result,
2353 this alternative may be rejected when it is
2354 actually desirable.) */
2356 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2357 *curr_id
->operand_loc
[m
], m_hregno
))
2359 /* We should reject matching of an early
2360 clobber operand if the matching operand is
2361 not dying in the insn. */
2362 if (!TEST_BIT (curr_static_id
->operand
[m
]
2363 .early_clobber_alts
, nalt
)
2364 || operand_reg
[nop
] == NULL_RTX
2365 || (find_regno_note (curr_insn
, REG_DEAD
,
2367 || REGNO (op
) == REGNO (operand_reg
[m
])))
2372 /* If we are matching a non-offsettable
2373 address where an offsettable address was
2374 expected, then we must reject this
2375 combination, because we can't reload
2377 if (curr_alt_offmemok
[m
]
2378 && MEM_P (*curr_id
->operand_loc
[m
])
2379 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2384 /* If the operands do not match and one
2385 operand is INOUT, we can not match them.
2386 Try other possibilities, e.g. other
2387 alternatives or commutative operand
2389 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
2390 || curr_static_id
->operand
[m
].type
== OP_INOUT
)
2392 /* Operands don't match. If the operands are
2393 different user defined explicit hard
2394 registers, then we cannot make them match
2395 when one is early clobber operand. */
2396 if ((REG_P (*curr_id
->operand_loc
[nop
])
2397 || SUBREG_P (*curr_id
->operand_loc
[nop
]))
2398 && (REG_P (*curr_id
->operand_loc
[m
])
2399 || SUBREG_P (*curr_id
->operand_loc
[m
])))
2401 rtx nop_reg
= *curr_id
->operand_loc
[nop
];
2402 if (SUBREG_P (nop_reg
))
2403 nop_reg
= SUBREG_REG (nop_reg
);
2404 rtx m_reg
= *curr_id
->operand_loc
[m
];
2405 if (SUBREG_P (m_reg
))
2406 m_reg
= SUBREG_REG (m_reg
);
2409 && HARD_REGISTER_P (nop_reg
)
2410 && REG_USERVAR_P (nop_reg
)
2412 && HARD_REGISTER_P (m_reg
)
2413 && REG_USERVAR_P (m_reg
))
2417 for (i
= 0; i
< early_clobbered_regs_num
; i
++)
2418 if (m
== early_clobbered_nops
[i
])
2420 if (i
< early_clobbered_regs_num
2425 /* Both operands must allow a reload register,
2426 otherwise we cannot make them match. */
2427 if (curr_alt
[m
] == NO_REGS
)
2429 /* Retroactively mark the operand we had to
2430 match as a loser, if it wasn't already and
2431 it wasn't matched to a register constraint
2432 (e.g it might be matched by memory). */
2434 && (operand_reg
[m
] == NULL_RTX
2435 || hard_regno
[m
] < 0))
2439 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2440 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2443 /* Prefer matching earlyclobber alternative as
2444 it results in less hard regs required for
2445 the insn than a non-matching earlyclobber
2447 if (TEST_BIT (curr_static_id
->operand
[m
]
2448 .early_clobber_alts
, nalt
))
2450 if (lra_dump_file
!= NULL
)
2453 " %d Matching earlyclobber alt:"
2456 if (!matching_early_clobber
[m
])
2459 matching_early_clobber
[m
] = 1;
2462 /* Otherwise we prefer no matching
2463 alternatives because it gives more freedom
2465 else if (operand_reg
[nop
] == NULL_RTX
2466 || (find_regno_note (curr_insn
, REG_DEAD
,
2467 REGNO (operand_reg
[nop
]))
2470 if (lra_dump_file
!= NULL
)
2473 " %d Matching alt: reject+=2\n",
2478 /* If we have to reload this operand and some
2479 previous operand also had to match the same
2480 thing as this operand, we don't know how to do
2482 if (!match_p
|| !curr_alt_win
[m
])
2484 for (i
= 0; i
< nop
; i
++)
2485 if (curr_alt_matches
[i
] == m
)
2493 this_alternative_matches
= m
;
2494 /* This can be fixed with reloads if the operand
2495 we are supposed to match can be fixed with
2498 this_alternative
= curr_alt
[m
];
2499 this_alternative_set
= curr_alt_set
[m
];
2500 this_alternative_exclude_start_hard_regs
2501 = curr_alt_exclude_start_hard_regs
[m
];
2502 winreg
= this_alternative
!= NO_REGS
;
2508 || general_constant_p (op
)
2509 || spilled_pseudo_p (op
))
2515 cn
= lookup_constraint (p
);
2516 switch (get_constraint_type (cn
))
2519 cl
= reg_class_for_constraint (cn
);
2525 if (CONST_INT_P (op
)
2526 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2531 case CT_RELAXED_MEMORY
:
2533 && satisfies_memory_constraint_p (op
, cn
))
2535 else if (spilled_pseudo_p (op
))
2538 /* If we didn't already win, we can reload constants
2539 via force_const_mem or put the pseudo value into
2540 memory, or make other memory by reloading the
2541 address like for 'o'. */
2542 if (CONST_POOL_OK_P (mode
, op
)
2543 || MEM_P (op
) || REG_P (op
)
2544 /* We can restore the equiv insn by a
2546 || equiv_substition_p
[nop
])
2553 /* An asm operand with an address constraint
2554 that doesn't satisfy address_operand has
2555 is_address cleared, so that we don't try to
2556 make a non-address fit. */
2557 if (!curr_static_id
->operand
[nop
].is_address
)
2559 /* If we didn't already win, we can reload the address
2560 into a base register. */
2561 if (satisfies_address_constraint_p (op
, cn
))
2563 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2569 if (constraint_satisfied_p (op
, cn
))
2573 case CT_SPECIAL_MEMORY
:
2574 if (satisfies_memory_constraint_p (op
, cn
))
2576 else if (spilled_pseudo_p (op
))
2583 if (mode
== BLKmode
)
2585 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2586 if (hard_reg_set_subset_p (this_alternative_set
,
2587 reg_class_contents
[cl
]))
2588 this_alternative_exclude_start_hard_regs
2589 = ira_exclude_class_mode_regs
[cl
][mode
];
2590 else if (!hard_reg_set_subset_p (reg_class_contents
[cl
],
2591 this_alternative_set
))
2592 this_alternative_exclude_start_hard_regs
2593 |= ira_exclude_class_mode_regs
[cl
][mode
];
2594 this_alternative_set
|= reg_class_contents
[cl
];
2597 this_costly_alternative
2598 = reg_class_subunion
[this_costly_alternative
][cl
];
2599 this_costly_alternative_set
|= reg_class_contents
[cl
];
2604 if (hard_regno
[nop
] >= 0
2605 && in_hard_reg_set_p (this_alternative_set
,
2606 mode
, hard_regno
[nop
])
2607 && !TEST_HARD_REG_BIT
2608 (this_alternative_exclude_start_hard_regs
,
2611 else if (hard_regno
[nop
] < 0
2612 && in_class_p (op
, this_alternative
, NULL
))
2617 if (c
!= ' ' && c
!= '\t')
2618 costly_p
= c
== '*';
2620 while ((p
+= len
), c
);
2622 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2623 && ira_former_scratch_p (REGNO (operand_reg
[nop
])));
2624 /* Record which operands fit this alternative. */
2627 this_alternative_win
= true;
2628 if (operand_reg
[nop
] != NULL_RTX
)
2630 if (hard_regno
[nop
] >= 0)
2632 if (in_hard_reg_set_p (this_costly_alternative_set
,
2633 mode
, hard_regno
[nop
]))
2635 if (lra_dump_file
!= NULL
)
2636 fprintf (lra_dump_file
,
2637 " %d Costly set: reject++\n",
2644 /* Prefer won reg to spilled pseudo under other
2645 equal conditions for possibe inheritance. */
2648 if (lra_dump_file
!= NULL
)
2651 " %d Non pseudo reload: reject++\n",
2655 if (in_class_p (operand_reg
[nop
],
2656 this_costly_alternative
, NULL
))
2658 if (lra_dump_file
!= NULL
)
2661 " %d Non pseudo costly reload:"
2667 /* We simulate the behavior of old reload here.
2668 Although scratches need hard registers and it
2669 might result in spilling other pseudos, no reload
2670 insns are generated for the scratches. So it
2671 might cost something but probably less than old
2672 reload pass believes. */
2675 if (lra_dump_file
!= NULL
)
2676 fprintf (lra_dump_file
,
2677 " %d Scratch win: reject+=2\n",
2684 this_alternative_match_win
= true;
2687 int const_to_mem
= 0;
2690 reject
+= op_reject
;
2691 /* Mark output reload of the stack pointer. */
2692 if (op
== stack_pointer_rtx
2693 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2694 curr_alt_out_sp_reload_p
= true;
2696 /* If this alternative asks for a specific reg class, see if there
2697 is at least one allocatable register in that class. */
2699 = (this_alternative
== NO_REGS
2700 || (hard_reg_set_subset_p
2701 (reg_class_contents
[this_alternative
],
2702 lra_no_alloc_regs
)));
2704 /* For asms, verify that the class for this alternative is possible
2705 for the mode that is specified. */
2706 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2709 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2710 if (targetm
.hard_regno_mode_ok (i
, mode
)
2711 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2714 if (i
== FIRST_PSEUDO_REGISTER
)
2718 /* If this operand accepts a register, and if the
2719 register class has at least one allocatable register,
2720 then this operand can be reloaded. */
2721 if (winreg
&& !no_regs_p
)
2726 if (lra_dump_file
!= NULL
)
2727 fprintf (lra_dump_file
,
2728 " Bad operand -- refuse\n");
2732 if (this_alternative
!= NO_REGS
)
2734 HARD_REG_SET available_regs
2735 = (reg_class_contents
[this_alternative
]
2736 & ~((ira_prohibited_class_mode_regs
2737 [this_alternative
][mode
])
2738 | lra_no_alloc_regs
));
2739 if (hard_reg_set_empty_p (available_regs
))
2741 /* There are no hard regs holding a value of given
2745 this_alternative
= NO_REGS
;
2746 if (lra_dump_file
!= NULL
)
2747 fprintf (lra_dump_file
,
2748 " %d Using memory because of"
2749 " a bad mode: reject+=2\n",
2755 if (lra_dump_file
!= NULL
)
2756 fprintf (lra_dump_file
,
2757 " Wrong mode -- refuse\n");
2763 /* If not assigned pseudo has a class which a subset of
2764 required reg class, it is a less costly alternative
2765 as the pseudo still can get a hard reg of necessary
2767 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2768 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2769 && ira_class_subset_p
[this_alternative
][cl
])
2771 if (lra_dump_file
!= NULL
)
2774 " %d Super set class reg: reject-=3\n", nop
);
2778 this_alternative_offmemok
= offmemok
;
2779 if (this_costly_alternative
!= NO_REGS
)
2781 if (lra_dump_file
!= NULL
)
2782 fprintf (lra_dump_file
,
2783 " %d Costly loser: reject++\n", nop
);
2786 /* If the operand is dying, has a matching constraint,
2787 and satisfies constraints of the matched operand
2788 which failed to satisfy the own constraints, most probably
2789 the reload for this operand will be gone. */
2790 if (this_alternative_matches
>= 0
2791 && !curr_alt_win
[this_alternative_matches
]
2793 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2794 && (hard_regno
[nop
] >= 0
2795 ? in_hard_reg_set_p (this_alternative_set
,
2796 mode
, hard_regno
[nop
])
2797 : in_class_p (op
, this_alternative
, NULL
)))
2799 if (lra_dump_file
!= NULL
)
2802 " %d Dying matched operand reload: reject++\n",
2808 /* Strict_low_part requires to reload the register
2809 not the sub-register. In this case we should
2810 check that a final reload hard reg can hold the
2812 if (curr_static_id
->operand
[nop
].strict_low
2814 && hard_regno
[nop
] < 0
2815 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2816 && ira_class_hard_regs_num
[this_alternative
] > 0
2817 && (!targetm
.hard_regno_mode_ok
2818 (ira_class_hard_regs
[this_alternative
][0],
2819 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2821 if (lra_dump_file
!= NULL
)
2824 " Strict low subreg reload -- refuse\n");
2829 if (operand_reg
[nop
] != NULL_RTX
2830 /* Output operands and matched input operands are
2831 not inherited. The following conditions do not
2832 exactly describe the previous statement but they
2833 are pretty close. */
2834 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2835 && (this_alternative_matches
< 0
2836 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2838 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2842 /* The value of reload_sum has sense only if we
2843 process insns in their order. It happens only on
2844 the first constraints sub-pass when we do most of
2846 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2847 reload_sum
+= last_reload
- bb_reload_num
;
2849 /* If this is a constant that is reloaded into the
2850 desired class by copying it to memory first, count
2851 that as another reload. This is consistent with
2852 other code and is required to avoid choosing another
2853 alternative when the constant is moved into memory.
2854 Note that the test here is precisely the same as in
2855 the code below that calls force_const_mem. */
2856 if (CONST_POOL_OK_P (mode
, op
)
2857 && ((targetm
.preferred_reload_class
2858 (op
, this_alternative
) == NO_REGS
)
2859 || no_input_reloads_p
))
2866 /* Alternative loses if it requires a type of reload not
2867 permitted for this insn. We can always reload
2868 objects with a REG_UNUSED note. */
2869 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2870 && no_output_reloads_p
2871 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2872 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2873 && no_input_reloads_p
&& ! const_to_mem
)
2874 || (this_alternative_matches
>= 0
2875 && (no_input_reloads_p
2876 || (no_output_reloads_p
2877 && (curr_static_id
->operand
2878 [this_alternative_matches
].type
!= OP_IN
)
2879 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2880 no_subreg_reg_operand
2881 [this_alternative_matches
])))))
2883 if (lra_dump_file
!= NULL
)
2886 " No input/output reload -- refuse\n");
2890 /* Alternative loses if it required class pseudo cannot
2891 hold value of required mode. Such insns can be
2892 described by insn definitions with mode iterators. */
2893 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2894 && ! hard_reg_set_empty_p (this_alternative_set
)
2895 /* It is common practice for constraints to use a
2896 class which does not have actually enough regs to
2897 hold the value (e.g. x86 AREG for mode requiring
2898 more one general reg). Therefore we have 2
2899 conditions to check that the reload pseudo cannot
2900 hold the mode value. */
2901 && (!targetm
.hard_regno_mode_ok
2902 (ira_class_hard_regs
[this_alternative
][0],
2903 GET_MODE (*curr_id
->operand_loc
[nop
])))
2904 /* The above condition is not enough as the first
2905 reg in ira_class_hard_regs can be not aligned for
2906 multi-words mode values. */
2907 && (prohibited_class_reg_set_mode_p
2908 (this_alternative
, this_alternative_set
,
2909 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2911 if (lra_dump_file
!= NULL
)
2912 fprintf (lra_dump_file
,
2913 " reload pseudo for op %d "
2914 "cannot hold the mode value -- refuse\n",
2919 /* Check strong discouragement of reload of non-constant
2920 into class THIS_ALTERNATIVE. */
2921 if (! CONSTANT_P (op
) && ! no_regs_p
2922 && (targetm
.preferred_reload_class
2923 (op
, this_alternative
) == NO_REGS
2924 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2925 && (targetm
.preferred_output_reload_class
2926 (op
, this_alternative
) == NO_REGS
))))
2928 if (offmemok
&& REG_P (op
))
2930 if (lra_dump_file
!= NULL
)
2933 " %d Spill pseudo into memory: reject+=3\n",
2939 if (lra_dump_file
!= NULL
)
2942 " %d Non-prefered reload: reject+=%d\n",
2943 nop
, LRA_MAX_REJECT
);
2944 reject
+= LRA_MAX_REJECT
;
2948 if (! (MEM_P (op
) && offmemok
)
2949 && ! (const_to_mem
&& constmemok
))
2951 /* We prefer to reload pseudos over reloading other
2952 things, since such reloads may be able to be
2953 eliminated later. So bump REJECT in other cases.
2954 Don't do this in the case where we are forcing a
2955 constant into memory and it will then win since
2956 we don't want to have a different alternative
2958 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2960 if (lra_dump_file
!= NULL
)
2963 " %d Non-pseudo reload: reject+=2\n",
2970 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2972 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2974 if (lra_dump_file
!= NULL
)
2977 " %d Small class reload: reject+=%d\n",
2978 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2979 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2983 /* We are trying to spill pseudo into memory. It is
2984 usually more costly than moving to a hard register
2985 although it might takes the same number of
2988 Non-pseudo spill may happen also. Suppose a target allows both
2989 register and memory in the operand constraint alternatives,
2990 then it's typical that an eliminable register has a substition
2991 of "base + offset" which can either be reloaded by a simple
2992 "new_reg <= base + offset" which will match the register
2993 constraint, or a similar reg addition followed by further spill
2994 to and reload from memory which will match the memory
2995 constraint, but this memory spill will be much more costly
2998 Code below increases the reject for both pseudo and non-pseudo
3001 && !(MEM_P (op
) && offmemok
)
3002 && !(REG_P (op
) && hard_regno
[nop
] < 0))
3004 if (lra_dump_file
!= NULL
)
3007 " %d Spill %spseudo into memory: reject+=3\n",
3008 nop
, REG_P (op
) ? "" : "Non-");
3010 if (VECTOR_MODE_P (mode
))
3012 /* Spilling vectors into memory is usually more
3013 costly as they contain big values. */
3014 if (lra_dump_file
!= NULL
)
3017 " %d Spill vector pseudo: reject+=2\n",
3023 /* When we use an operand requiring memory in given
3024 alternative, the insn should write *and* read the
3025 value to/from memory it is costly in comparison with
3026 an insn alternative which does not use memory
3027 (e.g. register or immediate operand). We exclude
3028 memory operand for such case as we can satisfy the
3029 memory constraints by reloading address. */
3030 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
3032 if (lra_dump_file
!= NULL
)
3035 " Using memory insn operand %d: reject+=3\n",
3040 /* If reload requires moving value through secondary
3041 memory, it will need one more insn at least. */
3042 if (this_alternative
!= NO_REGS
3043 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
3044 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
3045 && targetm
.secondary_memory_needed (GET_MODE (op
), cl
,
3047 || (curr_static_id
->operand
[nop
].type
!= OP_IN
3048 && (targetm
.secondary_memory_needed
3049 (GET_MODE (op
), this_alternative
, cl
)))))
3052 if (MEM_P (op
) && offmemok
)
3056 /* Input reloads can be inherited more often than
3057 output reloads can be removed, so penalize output
3059 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
3061 if (lra_dump_file
!= NULL
)
3064 " %d Non input pseudo reload: reject++\n",
3069 if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
3071 if (lra_dump_file
!= NULL
)
3074 " %d Input/Output reload: reject+=%d\n",
3075 nop
, LRA_LOSER_COST_FACTOR
);
3076 reject
+= LRA_LOSER_COST_FACTOR
;
3081 if (early_clobber_p
&& ! scratch_p
)
3083 if (lra_dump_file
!= NULL
)
3084 fprintf (lra_dump_file
,
3085 " %d Early clobber: reject++\n", nop
);
3088 /* ??? We check early clobbers after processing all operands
3089 (see loop below) and there we update the costs more.
3090 Should we update the cost (may be approximately) here
3091 because of early clobber register reloads or it is a rare
3092 or non-important thing to be worth to do it. */
3093 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
3094 - (addr_losers
== losers
? static_reject
: 0));
3095 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
3097 if (lra_dump_file
!= NULL
)
3098 fprintf (lra_dump_file
,
3099 " overall=%d,losers=%d -- refuse\n",
3104 if (update_and_check_small_class_inputs (nop
, nalt
,
3107 if (lra_dump_file
!= NULL
)
3108 fprintf (lra_dump_file
,
3109 " not enough small class regs -- refuse\n");
3112 curr_alt
[nop
] = this_alternative
;
3113 curr_alt_set
[nop
] = this_alternative_set
;
3114 curr_alt_exclude_start_hard_regs
[nop
]
3115 = this_alternative_exclude_start_hard_regs
;
3116 curr_alt_win
[nop
] = this_alternative_win
;
3117 curr_alt_match_win
[nop
] = this_alternative_match_win
;
3118 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
3119 curr_alt_matches
[nop
] = this_alternative_matches
;
3121 if (this_alternative_matches
>= 0
3122 && !did_match
&& !this_alternative_win
)
3123 curr_alt_win
[this_alternative_matches
] = false;
3125 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
3126 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
3129 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
3130 /* Prevent processing non-move insns. */
3131 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
3132 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
3133 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
3134 && REG_P (no_subreg_reg_operand
[0])
3135 && REG_P (no_subreg_reg_operand
[1])
3136 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3137 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
3138 || (! curr_alt_win
[0] && curr_alt_win
[1]
3139 && REG_P (no_subreg_reg_operand
[1])
3140 /* Check that we reload memory not the memory
3142 && ! (curr_alt_offmemok
[0]
3143 && MEM_P (no_subreg_reg_operand
[0]))
3144 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
3145 || (curr_alt_win
[0] && ! curr_alt_win
[1]
3146 && REG_P (no_subreg_reg_operand
[0])
3147 /* Check that we reload memory not the memory
3149 && ! (curr_alt_offmemok
[1]
3150 && MEM_P (no_subreg_reg_operand
[1]))
3151 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
3152 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
3153 no_subreg_reg_operand
[1])
3154 || (targetm
.preferred_reload_class
3155 (no_subreg_reg_operand
[1],
3156 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
3157 /* If it is a result of recent elimination in move
3158 insn we can transform it into an add still by
3159 using this alternative. */
3160 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
3161 /* Likewise if the source has been replaced with an
3162 equivalent value. This only happens once -- the reload
3163 will use the equivalent value instead of the register it
3164 replaces -- so there should be no danger of cycling. */
3165 && !equiv_substition_p
[1])))
3167 /* We have a move insn and a new reload insn will be similar
3168 to the current insn. We should avoid such situation as
3169 it results in LRA cycling. */
3170 if (lra_dump_file
!= NULL
)
3171 fprintf (lra_dump_file
,
3172 " Cycle danger: overall += LRA_MAX_REJECT\n");
3173 overall
+= LRA_MAX_REJECT
;
3176 curr_alt_dont_inherit_ops_num
= 0;
3177 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
3179 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
3180 HARD_REG_SET temp_set
;
3182 i
= early_clobbered_nops
[nop
];
3183 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
3184 || hard_regno
[i
] < 0)
3186 lra_assert (operand_reg
[i
] != NULL_RTX
);
3187 clobbered_hard_regno
= hard_regno
[i
];
3188 CLEAR_HARD_REG_SET (temp_set
);
3189 add_to_hard_reg_set (&temp_set
, GET_MODE (*curr_id
->operand_loc
[i
]),
3190 clobbered_hard_regno
);
3191 first_conflict_j
= last_conflict_j
= -1;
3192 for (j
= 0; j
< n_operands
; j
++)
3194 /* We don't want process insides of match_operator and
3195 match_parallel because otherwise we would process
3196 their operands once again generating a wrong
3198 || curr_static_id
->operand
[j
].is_operator
)
3200 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
3201 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
3203 /* If we don't reload j-th operand, check conflicts. */
3204 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
3205 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
3207 if (first_conflict_j
< 0)
3208 first_conflict_j
= j
;
3209 last_conflict_j
= j
;
3210 /* Both the earlyclobber operand and conflicting operand
3211 cannot both be user defined hard registers. */
3212 if (HARD_REGISTER_P (operand_reg
[i
])
3213 && REG_USERVAR_P (operand_reg
[i
])
3214 && operand_reg
[j
] != NULL_RTX
3215 && HARD_REGISTER_P (operand_reg
[j
])
3216 && REG_USERVAR_P (operand_reg
[j
]))
3218 /* For asm, let curr_insn_transform diagnose it. */
3219 if (INSN_CODE (curr_insn
) < 0)
3221 fatal_insn ("unable to generate reloads for "
3222 "impossible constraints:", curr_insn
);
3225 if (last_conflict_j
< 0)
3228 /* If an earlyclobber operand conflicts with another non-matching
3229 operand (ie, they have been assigned the same hard register),
3230 then it is better to reload the other operand, as there may
3231 exist yet another operand with a matching constraint associated
3232 with the earlyclobber operand. However, if one of the operands
3233 is an explicit use of a hard register, then we must reload the
3234 other non-hard register operand. */
3235 if (HARD_REGISTER_P (operand_reg
[i
])
3236 || (first_conflict_j
== last_conflict_j
3237 && operand_reg
[last_conflict_j
] != NULL_RTX
3238 && !curr_alt_match_win
[last_conflict_j
]
3239 && !HARD_REGISTER_P (operand_reg
[last_conflict_j
])))
3241 curr_alt_win
[last_conflict_j
] = false;
3242 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
3245 if (lra_dump_file
!= NULL
)
3248 " %d Conflict early clobber reload: reject--\n",
3253 /* We need to reload early clobbered register and the
3254 matched registers. */
3255 for (j
= 0; j
< n_operands
; j
++)
3256 if (curr_alt_matches
[j
] == i
)
3258 curr_alt_match_win
[j
] = false;
3260 overall
+= LRA_LOSER_COST_FACTOR
;
3262 if (! curr_alt_match_win
[i
])
3263 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
3266 /* Remember pseudos used for match reloads are never
3268 lra_assert (curr_alt_matches
[i
] >= 0);
3269 curr_alt_win
[curr_alt_matches
[i
]] = false;
3271 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
3273 if (lra_dump_file
!= NULL
)
3276 " %d Matched conflict early clobber reloads: "
3280 /* Early clobber was already reflected in REJECT. */
3281 if (!matching_early_clobber
[i
])
3283 lra_assert (reject
> 0);
3285 matching_early_clobber
[i
] = 1;
3287 overall
+= LRA_LOSER_COST_FACTOR
- 1;
3289 if (lra_dump_file
!= NULL
)
3290 fprintf (lra_dump_file
, " overall=%d,losers=%d,rld_nregs=%d\n",
3291 overall
, losers
, reload_nregs
);
3293 /* If this alternative can be made to work by reloading, and it
3294 needs less reloading than the others checked so far, record
3295 it as the chosen goal for reloading. */
3296 if ((best_losers
!= 0 && losers
== 0)
3297 || (((best_losers
== 0 && losers
== 0)
3298 || (best_losers
!= 0 && losers
!= 0))
3299 && (best_overall
> overall
3300 || (best_overall
== overall
3301 /* If the cost of the reloads is the same,
3302 prefer alternative which requires minimal
3303 number of reload regs. */
3304 && (reload_nregs
< best_reload_nregs
3305 || (reload_nregs
== best_reload_nregs
3306 && (best_reload_sum
< reload_sum
3307 || (best_reload_sum
== reload_sum
3308 && nalt
< goal_alt_number
))))))))
3310 for (nop
= 0; nop
< n_operands
; nop
++)
3312 goal_alt_win
[nop
] = curr_alt_win
[nop
];
3313 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
3314 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
3315 goal_alt
[nop
] = curr_alt
[nop
];
3316 goal_alt_exclude_start_hard_regs
[nop
]
3317 = curr_alt_exclude_start_hard_regs
[nop
];
3318 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
3320 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
3321 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
3322 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
3323 goal_alt_swapped
= curr_swapped
;
3324 goal_alt_out_sp_reload_p
= curr_alt_out_sp_reload_p
;
3325 best_overall
= overall
;
3326 best_losers
= losers
;
3327 best_reload_nregs
= reload_nregs
;
3328 best_reload_sum
= reload_sum
;
3329 goal_alt_number
= nalt
;
3332 /* Everything is satisfied. Do not process alternatives
3341 /* Make reload base reg from address AD. */
3343 base_to_reg (struct address_info
*ad
)
3347 rtx new_inner
= NULL_RTX
;
3348 rtx new_reg
= NULL_RTX
;
3350 rtx_insn
*last_insn
= get_last_insn();
3352 lra_assert (ad
->disp
== ad
->disp_term
);
3353 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3354 get_index_code (ad
));
3355 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
, cl
, NULL
,
3357 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3358 ad
->disp_term
== NULL
3361 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3363 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3364 code
= recog_memoized (insn
);
3367 delete_insns_since (last_insn
);
3374 /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3376 base_plus_disp_to_reg (struct address_info
*ad
, rtx disp
)
3381 lra_assert (ad
->base
== ad
->base_term
);
3382 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3383 get_index_code (ad
));
3384 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
, cl
, NULL
,
3386 lra_emit_add (new_reg
, *ad
->base_term
, disp
);
3390 /* Make reload of index part of address AD. Return the new
3393 index_part_to_reg (struct address_info
*ad
)
3397 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3398 INDEX_REG_CLASS
, NULL
, "index term");
3399 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3400 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3404 /* Return true if we can add a displacement to address AD, even if that
3405 makes the address invalid. The fix-up code requires any new address
3406 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3408 can_add_disp_p (struct address_info
*ad
)
3410 return (!ad
->autoinc_p
3411 && ad
->segment
== NULL
3412 && ad
->base
== ad
->base_term
3413 && ad
->disp
== ad
->disp_term
);
3416 /* Make equiv substitution in address AD. Return true if a substitution
3419 equiv_address_substitution (struct address_info
*ad
)
3421 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3423 HOST_WIDE_INT scale
;
3426 base_term
= strip_subreg (ad
->base_term
);
3427 if (base_term
== NULL
)
3428 base_reg
= new_base_reg
= NULL_RTX
;
3431 base_reg
= *base_term
;
3432 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3434 index_term
= strip_subreg (ad
->index_term
);
3435 if (index_term
== NULL
)
3436 index_reg
= new_index_reg
= NULL_RTX
;
3439 index_reg
= *index_term
;
3440 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3442 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3446 if (lra_dump_file
!= NULL
)
3448 fprintf (lra_dump_file
, "Changing address in insn %d ",
3449 INSN_UID (curr_insn
));
3450 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3452 if (base_reg
!= new_base_reg
)
3455 if (REG_P (new_base_reg
))
3457 *base_term
= new_base_reg
;
3460 else if (GET_CODE (new_base_reg
) == PLUS
3461 && REG_P (XEXP (new_base_reg
, 0))
3462 && poly_int_rtx_p (XEXP (new_base_reg
, 1), &offset
)
3463 && can_add_disp_p (ad
))
3466 *base_term
= XEXP (new_base_reg
, 0);
3469 if (ad
->base_term2
!= NULL
)
3470 *ad
->base_term2
= *ad
->base_term
;
3472 if (index_reg
!= new_index_reg
)
3475 if (REG_P (new_index_reg
))
3477 *index_term
= new_index_reg
;
3480 else if (GET_CODE (new_index_reg
) == PLUS
3481 && REG_P (XEXP (new_index_reg
, 0))
3482 && poly_int_rtx_p (XEXP (new_index_reg
, 1), &offset
)
3483 && can_add_disp_p (ad
)
3484 && (scale
= get_index_scale (ad
)))
3486 disp
+= offset
* scale
;
3487 *index_term
= XEXP (new_index_reg
, 0);
3491 if (maybe_ne (disp
, 0))
3493 if (ad
->disp
!= NULL
)
3494 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3497 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3498 update_address (ad
);
3502 if (lra_dump_file
!= NULL
)
3505 fprintf (lra_dump_file
, " -- no change\n");
3508 fprintf (lra_dump_file
, " on equiv ");
3509 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3510 fprintf (lra_dump_file
, "\n");
3516 /* Skip all modifiers and whitespaces in constraint STR and return the
3519 skip_constraint_modifiers (const char *str
)
3524 case '+': case '&' : case '=': case '*': case ' ': case '\t':
3525 case '$': case '^' : case '%': case '?': case '!':
3527 default: return str
;
3531 /* Takes a string of 0 or more comma-separated constraints. When more
3532 than one constraint is present, evaluate whether they all correspond
3533 to a single, repeated constraint (e.g. "r,r") or whether we have
3534 more than one distinct constraints (e.g. "r,m"). */
3536 constraint_unique (const char *cstr
)
3538 enum constraint_num ca
, cb
;
3539 ca
= CONSTRAINT__UNKNOWN
;
3542 cstr
= skip_constraint_modifiers (cstr
);
3543 if (*cstr
== '\0' || *cstr
== ',')
3547 cb
= lookup_constraint (cstr
);
3548 if (cb
== CONSTRAINT__UNKNOWN
)
3550 cstr
+= CONSTRAINT_LEN (cstr
[0], cstr
);
3552 /* Handle the first iteration of the loop. */
3553 if (ca
== CONSTRAINT__UNKNOWN
)
3555 /* Handle the general case of comparing ca with subsequent
3566 /* Major function to make reloads for an address in operand NOP or
3567 check its correctness (If CHECK_ONLY_P is true). The supported
3570 1) an address that existed before LRA started, at which point it
3571 must have been valid. These addresses are subject to elimination
3572 and may have become invalid due to the elimination offset being out
3575 2) an address created by forcing a constant to memory
3576 (force_const_to_mem). The initial form of these addresses might
3577 not be valid, and it is this function's job to make them valid.
3579 3) a frame address formed from a register and a (possibly zero)
3580 constant offset. As above, these addresses might not be valid and
3581 this function must make them so.
3583 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3584 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3585 address. Return true for any RTL change.
3587 The function is a helper function which does not produce all
3588 transformations (when CHECK_ONLY_P is false) which can be
3589 necessary. It does just basic steps. To do all necessary
3590 transformations use function process_address. */
3592 process_address_1 (int nop
, bool check_only_p
,
3593 rtx_insn
**before
, rtx_insn
**after
)
3595 struct address_info ad
;
3597 HOST_WIDE_INT scale
;
3598 rtx op
= *curr_id
->operand_loc
[nop
];
3599 rtx mem
= extract_mem_from_operand (op
);
3600 const char *constraint
;
3601 enum constraint_num cn
;
3602 bool change_p
= false;
3605 && GET_MODE (mem
) == BLKmode
3606 && GET_CODE (XEXP (mem
, 0)) == SCRATCH
)
3610 = skip_constraint_modifiers (curr_static_id
->operand
[nop
].constraint
);
3611 if (IN_RANGE (constraint
[0], '0', '9'))
3614 unsigned long dup
= strtoul (constraint
, &end
, 10);
3616 = skip_constraint_modifiers (curr_static_id
->operand
[dup
].constraint
);
3618 cn
= lookup_constraint (*constraint
== '\0' ? "X" : constraint
);
3619 /* If we have several alternatives or/and several constraints in an
3620 alternative and we can not say at this stage what constraint will be used,
3621 use unknown constraint. The exception is an address constraint. If
3622 operand has one address constraint, probably all others constraints are
3624 if (constraint
[0] != '\0' && get_constraint_type (cn
) != CT_ADDRESS
3625 && !constraint_unique (constraint
))
3626 cn
= CONSTRAINT__UNKNOWN
;
3627 if (insn_extra_address_constraint (cn
)
3628 /* When we find an asm operand with an address constraint that
3629 doesn't satisfy address_operand to begin with, we clear
3630 is_address, so that we don't try to make a non-address fit.
3631 If the asm statement got this far, it's because other
3632 constraints are available, and we'll use them, disregarding
3633 the unsatisfiable address ones. */
3634 && curr_static_id
->operand
[nop
].is_address
)
3635 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3636 /* Do not attempt to decompose arbitrary addresses generated by combine
3637 for asm operands with loose constraints, e.g 'X'.
3638 Need to extract memory from op for special memory constraint,
3639 i.e. bcst_mem_operand in i386 backend. */
3640 else if (MEM_P (mem
)
3641 && !(INSN_CODE (curr_insn
) < 0
3642 && get_constraint_type (cn
) == CT_FIXED_FORM
3643 && constraint_satisfied_p (op
, cn
)))
3644 decompose_mem_address (&ad
, mem
);
3645 else if (GET_CODE (op
) == SUBREG
3646 && MEM_P (SUBREG_REG (op
)))
3647 decompose_mem_address (&ad
, SUBREG_REG (op
));
3650 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3651 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3652 when INDEX_REG_CLASS is a single register class. */
3653 if (ad
.base_term
!= NULL
3654 && ad
.index_term
!= NULL
3655 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3656 && REG_P (*ad
.base_term
)
3657 && REG_P (*ad
.index_term
)
3658 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3659 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3661 std::swap (ad
.base
, ad
.index
);
3662 std::swap (ad
.base_term
, ad
.index_term
);
3665 change_p
= equiv_address_substitution (&ad
);
3666 if (ad
.base_term
!= NULL
3667 && (process_addr_reg
3668 (ad
.base_term
, check_only_p
, before
,
3670 && !(REG_P (*ad
.base_term
)
3671 && find_regno_note (curr_insn
, REG_DEAD
,
3672 REGNO (*ad
.base_term
)) != NULL_RTX
)
3674 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3675 get_index_code (&ad
)))))
3678 if (ad
.base_term2
!= NULL
)
3679 *ad
.base_term2
= *ad
.base_term
;
3681 if (ad
.index_term
!= NULL
3682 && process_addr_reg (ad
.index_term
, check_only_p
,
3683 before
, NULL
, INDEX_REG_CLASS
))
3686 /* Target hooks sometimes don't treat extra-constraint addresses as
3687 legitimate address_operands, so handle them specially. */
3688 if (insn_extra_address_constraint (cn
)
3689 && satisfies_address_constraint_p (&ad
, cn
))
3695 /* There are three cases where the shape of *AD.INNER may now be invalid:
3697 1) the original address was valid, but either elimination or
3698 equiv_address_substitution was applied and that made
3699 the address invalid.
3701 2) the address is an invalid symbolic address created by
3704 3) the address is a frame address with an invalid offset.
3706 4) the address is a frame address with an invalid base.
3708 All these cases involve a non-autoinc address, so there is no
3709 point revalidating other types. */
3710 if (ad
.autoinc_p
|| valid_address_p (op
, &ad
, cn
))
3713 /* Any index existed before LRA started, so we can assume that the
3714 presence and shape of the index is valid. */
3715 push_to_sequence (*before
);
3716 lra_assert (ad
.disp
== ad
.disp_term
);
3717 if (ad
.base
== NULL
)
3719 if (ad
.index
== NULL
)
3722 rtx_insn
*last
= get_last_insn ();
3724 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3726 rtx addr
= *ad
.inner
;
3728 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3731 /* addr => lo_sum (new_base, addr), case (2) above. */
3732 insn
= emit_insn (gen_rtx_SET
3734 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3735 code
= recog_memoized (insn
);
3738 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3739 if (!valid_address_p (op
, &ad
, cn
))
3741 /* Try to put lo_sum into register. */
3742 insn
= emit_insn (gen_rtx_SET
3744 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3745 code
= recog_memoized (insn
);
3748 *ad
.inner
= new_reg
;
3749 if (!valid_address_p (op
, &ad
, cn
))
3759 delete_insns_since (last
);
3764 /* addr => new_base, case (2) above. */
3765 lra_emit_move (new_reg
, addr
);
3767 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3769 insn
= NEXT_INSN (insn
))
3770 if (recog_memoized (insn
) < 0)
3772 if (insn
!= NULL_RTX
)
3774 /* Do nothing if we cannot generate right insns.
3775 This is analogous to reload pass behavior. */
3776 delete_insns_since (last
);
3780 *ad
.inner
= new_reg
;
3785 /* index * scale + disp => new base + index * scale,
3787 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3788 GET_CODE (*ad
.index
));
3790 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3791 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "disp");
3792 lra_emit_move (new_reg
, *ad
.disp
);
3793 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3794 new_reg
, *ad
.index
);
3797 else if (ad
.index
== NULL
)
3802 rtx_insn
*insns
, *last_insn
;
3803 /* Try to reload base into register only if the base is invalid
3804 for the address but with valid offset, case (4) above. */
3806 new_reg
= base_to_reg (&ad
);
3808 /* base + disp => new base, cases (1) and (3) above. */
3809 /* Another option would be to reload the displacement into an
3810 index register. However, postreload has code to optimize
3811 address reloads that have the same base and different
3812 displacements, so reloading into an index register would
3813 not necessarily be a win. */
3814 if (new_reg
== NULL_RTX
)
3816 /* See if the target can split the displacement into a
3817 legitimate new displacement from a local anchor. */
3818 gcc_assert (ad
.disp
== ad
.disp_term
);
3819 poly_int64 orig_offset
;
3820 rtx offset1
, offset2
;
3821 if (poly_int_rtx_p (*ad
.disp
, &orig_offset
)
3822 && targetm
.legitimize_address_displacement (&offset1
, &offset2
,
3826 new_reg
= base_plus_disp_to_reg (&ad
, offset1
);
3827 new_reg
= gen_rtx_PLUS (GET_MODE (new_reg
), new_reg
, offset2
);
3830 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3832 insns
= get_insns ();
3833 last_insn
= get_last_insn ();
3834 /* If we generated at least two insns, try last insn source as
3835 an address. If we succeed, we generate one less insn. */
3837 && last_insn
!= insns
3838 && (set
= single_set (last_insn
)) != NULL_RTX
3839 && GET_CODE (SET_SRC (set
)) == PLUS
3840 && REG_P (XEXP (SET_SRC (set
), 0))
3841 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3843 *ad
.inner
= SET_SRC (set
);
3844 if (valid_address_p (op
, &ad
, cn
))
3846 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3847 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3848 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3849 get_index_code (&ad
));
3850 regno
= REGNO (*ad
.base_term
);
3851 if (regno
>= FIRST_PSEUDO_REGISTER
3852 && cl
!= lra_get_allocno_class (regno
))
3853 lra_change_class (regno
, cl
, " Change to", true);
3854 new_reg
= SET_SRC (set
);
3855 delete_insns_since (PREV_INSN (last_insn
));
3860 *ad
.inner
= new_reg
;
3862 else if (ad
.disp_term
!= NULL
)
3864 /* base + scale * index + disp => new base + scale * index,
3866 gcc_assert (ad
.disp
== ad
.disp_term
);
3867 new_reg
= base_plus_disp_to_reg (&ad
, *ad
.disp
);
3868 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3869 new_reg
, *ad
.index
);
3871 else if ((scale
= get_index_scale (&ad
)) == 1)
3873 /* The last transformation to one reg will be made in
3874 curr_insn_transform function. */
3878 else if (scale
!= 0)
3880 /* base + scale * index => base + new_reg,
3882 Index part of address may become invalid. For example, we
3883 changed pseudo on the equivalent memory and a subreg of the
3884 pseudo onto the memory of different mode for which the scale is
3886 new_reg
= index_part_to_reg (&ad
);
3887 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3888 *ad
.base_term
, new_reg
);
3892 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3894 rtx addr
= *ad
.inner
;
3896 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, NULL
, "addr");
3897 /* addr => new_base. */
3898 lra_emit_move (new_reg
, addr
);
3899 *ad
.inner
= new_reg
;
3901 *before
= get_insns ();
3906 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3907 Use process_address_1 as a helper function. Return true for any
3910 If CHECK_ONLY_P is true, just check address correctness. Return
3911 false if the address correct. */
3913 process_address (int nop
, bool check_only_p
,
3914 rtx_insn
**before
, rtx_insn
**after
)
3918 while (process_address_1 (nop
, check_only_p
, before
, after
))
3927 /* Emit insns to reload VALUE into a new register. VALUE is an
3928 auto-increment or auto-decrement RTX whose operand is a register or
3929 memory location; so reloading involves incrementing that location.
3930 IN is either identical to VALUE, or some cheaper place to reload
3931 value being incremented/decremented from.
3933 INC_AMOUNT is the number to increment or decrement by (always
3934 positive and ignored for POST_MODIFY/PRE_MODIFY).
3936 Return pseudo containing the result. */
3938 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, poly_int64 inc_amount
)
3940 /* REG or MEM to be copied and incremented. */
3941 rtx incloc
= XEXP (value
, 0);
3942 /* Nonzero if increment after copying. */
3943 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3944 || GET_CODE (value
) == POST_MODIFY
);
3949 rtx real_in
= in
== value
? incloc
: in
;
3953 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3955 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3956 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3957 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3958 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3959 inc
= XEXP (XEXP (value
, 1), 1);
3963 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3964 inc_amount
= -inc_amount
;
3966 inc
= gen_int_mode (inc_amount
, GET_MODE (value
));
3969 if (! post
&& REG_P (incloc
))
3972 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
, NULL
,
3975 if (real_in
!= result
)
3977 /* First copy the location to the result register. */
3978 lra_assert (REG_P (result
));
3979 emit_insn (gen_move_insn (result
, real_in
));
3982 /* We suppose that there are insns to add/sub with the constant
3983 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3984 old reload worked with this assumption. If the assumption
3985 becomes wrong, we should use approach in function
3986 base_plus_disp_to_reg. */
3989 /* See if we can directly increment INCLOC. */
3990 last
= get_last_insn ();
3991 add_insn
= emit_insn (plus_p
3992 ? gen_add2_insn (incloc
, inc
)
3993 : gen_sub2_insn (incloc
, inc
));
3995 code
= recog_memoized (add_insn
);
3998 if (! post
&& result
!= incloc
)
3999 emit_insn (gen_move_insn (result
, incloc
));
4002 delete_insns_since (last
);
4005 /* If couldn't do the increment directly, must increment in RESULT.
4006 The way we do this depends on whether this is pre- or
4007 post-increment. For pre-increment, copy INCLOC to the reload
4008 register, increment it there, then save back. */
4011 if (real_in
!= result
)
4012 emit_insn (gen_move_insn (result
, real_in
));
4014 emit_insn (gen_add2_insn (result
, inc
));
4016 emit_insn (gen_sub2_insn (result
, inc
));
4017 if (result
!= incloc
)
4018 emit_insn (gen_move_insn (incloc
, result
));
4024 Because this might be a jump insn or a compare, and because
4025 RESULT may not be available after the insn in an input
4026 reload, we must do the incrementing before the insn being
4029 We have already copied IN to RESULT. Increment the copy in
4030 RESULT, save that back, then decrement RESULT so it has
4031 the original value. */
4033 emit_insn (gen_add2_insn (result
, inc
));
4035 emit_insn (gen_sub2_insn (result
, inc
));
4036 emit_insn (gen_move_insn (incloc
, result
));
4037 /* Restore non-modified value for the result. We prefer this
4038 way because it does not require an additional hard
4043 if (poly_int_rtx_p (inc
, &offset
))
4044 emit_insn (gen_add2_insn (result
,
4045 gen_int_mode (-offset
,
4046 GET_MODE (result
))));
4048 emit_insn (gen_sub2_insn (result
, inc
));
4051 emit_insn (gen_add2_insn (result
, inc
));
4056 /* Return true if the current move insn does not need processing as we
4057 already know that it satisfies its constraints. */
4059 simple_move_p (void)
4062 enum reg_class dclass
, sclass
;
4064 lra_assert (curr_insn_set
!= NULL_RTX
);
4065 dest
= SET_DEST (curr_insn_set
);
4066 src
= SET_SRC (curr_insn_set
);
4068 /* If the instruction has multiple sets we need to process it even if it
4069 is single_set. This can happen if one or more of the SETs are dead.
4071 if (multiple_sets (curr_insn
))
4074 return ((dclass
= get_op_class (dest
)) != NO_REGS
4075 && (sclass
= get_op_class (src
)) != NO_REGS
4076 /* The backend guarantees that register moves of cost 2
4077 never need reloads. */
4078 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
4081 /* Swap operands NOP and NOP + 1. */
4083 swap_operands (int nop
)
4085 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
4086 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
4087 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
4088 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
4089 /* Swap the duplicates too. */
4090 lra_update_dup (curr_id
, nop
);
4091 lra_update_dup (curr_id
, nop
+ 1);
4094 /* Main entry point of the constraint code: search the body of the
4095 current insn to choose the best alternative. It is mimicking insn
4096 alternative cost calculation model of former reload pass. That is
4097 because machine descriptions were written to use this model. This
4098 model can be changed in future. Make commutative operand exchange
4101 if CHECK_ONLY_P is false, do RTL changes to satisfy the
4102 constraints. Return true if any change happened during function
4105 If CHECK_ONLY_P is true then don't do any transformation. Just
4106 check that the insn satisfies all constraints. If the insn does
4107 not satisfy any constraint, return true. */
4109 curr_insn_transform (bool check_only_p
)
4116 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
4117 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
4118 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
4119 rtx_insn
*before
, *after
;
4121 /* Flag that the insn has been changed through a transformation. */
4125 int max_regno_before
;
4126 int reused_alternative_num
;
4128 curr_insn_set
= single_set (curr_insn
);
4129 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
4131 /* We assume that the corresponding insn alternative has no
4132 earlier clobbers. If it is not the case, don't define move
4133 cost equal to 2 for the corresponding register classes. */
4134 lra_set_used_insn_alternative (curr_insn
, LRA_NON_CLOBBERED_ALT
);
4138 no_input_reloads_p
= no_output_reloads_p
= false;
4139 goal_alt_number
= -1;
4140 change_p
= sec_mem_p
= false;
4142 /* CALL_INSNs are not allowed to have any output reloads. */
4143 if (CALL_P (curr_insn
))
4144 no_output_reloads_p
= true;
4146 n_operands
= curr_static_id
->n_operands
;
4147 n_alternatives
= curr_static_id
->n_alternatives
;
4149 /* Just return "no reloads" if insn has no operands with
4151 if (n_operands
== 0 || n_alternatives
== 0)
4154 max_regno_before
= max_reg_num ();
4156 for (i
= 0; i
< n_operands
; i
++)
4158 goal_alt_matched
[i
][0] = -1;
4159 goal_alt_matches
[i
] = -1;
4162 commutative
= curr_static_id
->commutative
;
4164 /* Now see what we need for pseudos that didn't get hard regs or got
4165 the wrong kind of hard reg. For this, we must consider all the
4166 operands together against the register constraints. */
4168 best_losers
= best_overall
= INT_MAX
;
4169 best_reload_sum
= 0;
4171 curr_swapped
= false;
4172 goal_alt_swapped
= false;
4175 /* Make equivalence substitution and memory subreg elimination
4176 before address processing because an address legitimacy can
4177 depend on memory mode. */
4178 for (i
= 0; i
< n_operands
; i
++)
4181 bool op_change_p
= false;
4183 if (curr_static_id
->operand
[i
].is_operator
)
4186 old
= op
= *curr_id
->operand_loc
[i
];
4187 if (GET_CODE (old
) == SUBREG
)
4188 old
= SUBREG_REG (old
);
4189 subst
= get_equiv_with_elimination (old
, curr_insn
);
4190 original_subreg_reg_mode
[i
] = VOIDmode
;
4191 equiv_substition_p
[i
] = false;
4194 equiv_substition_p
[i
] = true;
4195 subst
= copy_rtx (subst
);
4196 lra_assert (REG_P (old
));
4197 if (GET_CODE (op
) != SUBREG
)
4198 *curr_id
->operand_loc
[i
] = subst
;
4201 SUBREG_REG (op
) = subst
;
4202 if (GET_MODE (subst
) == VOIDmode
)
4203 original_subreg_reg_mode
[i
] = GET_MODE (old
);
4205 if (lra_dump_file
!= NULL
)
4207 fprintf (lra_dump_file
,
4208 "Changing pseudo %d in operand %i of insn %u on equiv ",
4209 REGNO (old
), i
, INSN_UID (curr_insn
));
4210 dump_value_slim (lra_dump_file
, subst
, 1);
4211 fprintf (lra_dump_file
, "\n");
4213 op_change_p
= change_p
= true;
4215 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
4218 lra_update_dup (curr_id
, i
);
4222 /* Reload address registers and displacements. We do it before
4223 finding an alternative because of memory constraints. */
4224 before
= after
= NULL
;
4225 for (i
= 0; i
< n_operands
; i
++)
4226 if (! curr_static_id
->operand
[i
].is_operator
4227 && process_address (i
, check_only_p
, &before
, &after
))
4232 lra_update_dup (curr_id
, i
);
4236 /* If we've changed the instruction then any alternative that
4237 we chose previously may no longer be valid. */
4238 lra_set_used_insn_alternative (curr_insn
, LRA_UNKNOWN_ALT
);
4240 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
4241 && check_and_process_move (&change_p
, &sec_mem_p
))
4246 reused_alternative_num
= check_only_p
? LRA_UNKNOWN_ALT
: curr_id
->used_insn_alternative
;
4247 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
4248 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
4249 reused_alternative_num
, INSN_UID (curr_insn
));
4251 if (process_alt_operands (reused_alternative_num
))
4255 return ! alt_p
|| best_losers
!= 0;
4257 /* If insn is commutative (it's safe to exchange a certain pair of
4258 operands) then we need to try each alternative twice, the second
4259 time matching those two operands as if we had exchanged them. To
4260 do this, really exchange them in operands.
4262 If we have just tried the alternatives the second time, return
4263 operands to normal and drop through. */
4265 if (reused_alternative_num
< 0 && commutative
>= 0)
4267 curr_swapped
= !curr_swapped
;
4270 swap_operands (commutative
);
4274 swap_operands (commutative
);
4277 if (! alt_p
&& ! sec_mem_p
)
4279 /* No alternative works with reloads?? */
4280 if (INSN_CODE (curr_insn
) >= 0)
4281 fatal_insn ("unable to generate reloads for:", curr_insn
);
4282 error_for_asm (curr_insn
,
4283 "inconsistent operand constraints in an %<asm%>");
4284 lra_asm_error_p
= true;
4285 if (! JUMP_P (curr_insn
))
4287 /* Avoid further trouble with this insn. Don't generate use
4288 pattern here as we could use the insn SP offset. */
4289 lra_set_insn_deleted (curr_insn
);
4293 lra_invalidate_insn_data (curr_insn
);
4294 ira_nullify_asm_goto (curr_insn
);
4295 lra_update_insn_regno_info (curr_insn
);
4300 /* If the best alternative is with operands 1 and 2 swapped, swap
4301 them. Update the operand numbers of any reloads already
4304 if (goal_alt_swapped
)
4306 if (lra_dump_file
!= NULL
)
4307 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
4308 INSN_UID (curr_insn
));
4310 /* Swap the duplicates too. */
4311 swap_operands (commutative
);
4315 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4316 too conservatively. So we use the secondary memory only if there
4317 is no any alternative without reloads. */
4318 use_sec_mem_p
= false;
4320 use_sec_mem_p
= true;
4323 for (i
= 0; i
< n_operands
; i
++)
4324 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
4326 use_sec_mem_p
= i
< n_operands
;
4331 int in
= -1, out
= -1;
4332 rtx new_reg
, src
, dest
, rld
;
4333 machine_mode sec_mode
, rld_mode
;
4335 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
4336 dest
= SET_DEST (curr_insn_set
);
4337 src
= SET_SRC (curr_insn_set
);
4338 for (i
= 0; i
< n_operands
; i
++)
4339 if (*curr_id
->operand_loc
[i
] == dest
)
4341 else if (*curr_id
->operand_loc
[i
] == src
)
4343 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
4344 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
4345 out
= curr_static_id
->dup_num
[i
];
4346 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
4347 in
= curr_static_id
->dup_num
[i
];
4348 lra_assert (out
>= 0 && in
>= 0
4349 && curr_static_id
->operand
[out
].type
== OP_OUT
4350 && curr_static_id
->operand
[in
].type
== OP_IN
);
4351 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
4352 rld_mode
= GET_MODE (rld
);
4353 sec_mode
= targetm
.secondary_memory_needed_mode (rld_mode
);
4354 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
, NO_REGS
, NULL
,
4356 /* If the mode is changed, it should be wider. */
4357 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
4358 if (sec_mode
!= rld_mode
)
4360 /* If the target says specifically to use another mode for
4361 secondary memory moves we cannot reuse the original
4363 after
= emit_spill_move (false, new_reg
, dest
);
4364 lra_process_new_insns (curr_insn
, NULL
, after
,
4365 "Inserting the sec. move");
4366 /* We may have non null BEFORE here (e.g. after address
4368 push_to_sequence (before
);
4369 before
= emit_spill_move (true, new_reg
, src
);
4371 before
= get_insns ();
4373 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
4374 lra_set_insn_deleted (curr_insn
);
4376 else if (dest
== rld
)
4378 *curr_id
->operand_loc
[out
] = new_reg
;
4379 lra_update_dup (curr_id
, out
);
4380 after
= emit_spill_move (false, new_reg
, dest
);
4381 lra_process_new_insns (curr_insn
, NULL
, after
,
4382 "Inserting the sec. move");
4386 *curr_id
->operand_loc
[in
] = new_reg
;
4387 lra_update_dup (curr_id
, in
);
4388 /* See comments above. */
4389 push_to_sequence (before
);
4390 before
= emit_spill_move (true, new_reg
, src
);
4392 before
= get_insns ();
4394 lra_process_new_insns (curr_insn
, before
, NULL
,
4395 "Inserting the sec. move");
4397 lra_update_insn_regno_info (curr_insn
);
4401 lra_assert (goal_alt_number
>= 0);
4402 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
4404 if (lra_dump_file
!= NULL
)
4408 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4409 goal_alt_number
, INSN_UID (curr_insn
));
4410 print_curr_insn_alt (goal_alt_number
);
4411 if (INSN_CODE (curr_insn
) >= 0
4412 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4413 fprintf (lra_dump_file
, " {%s}", p
);
4414 if (maybe_ne (curr_id
->sp_offset
, 0))
4416 fprintf (lra_dump_file
, " (sp_off=");
4417 print_dec (curr_id
->sp_offset
, lra_dump_file
);
4418 fprintf (lra_dump_file
, ")");
4420 fprintf (lra_dump_file
, "\n");
4423 /* Right now, for any pair of operands I and J that are required to
4424 match, with J < I, goal_alt_matches[I] is J. Add I to
4425 goal_alt_matched[J]. */
4427 for (i
= 0; i
< n_operands
; i
++)
4428 if ((j
= goal_alt_matches
[i
]) >= 0)
4430 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4432 /* We allow matching one output operand and several input
4435 || (curr_static_id
->operand
[j
].type
== OP_OUT
4436 && curr_static_id
->operand
[i
].type
== OP_IN
4437 && (curr_static_id
->operand
4438 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4439 goal_alt_matched
[j
][k
] = i
;
4440 goal_alt_matched
[j
][k
+ 1] = -1;
4443 for (i
= 0; i
< n_operands
; i
++)
4444 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4446 /* Any constants that aren't allowed and can't be reloaded into
4447 registers are here changed into memory references. */
4448 for (i
= 0; i
< n_operands
; i
++)
4449 if (goal_alt_win
[i
])
4452 enum reg_class new_class
;
4453 rtx reg
= *curr_id
->operand_loc
[i
];
4455 if (GET_CODE (reg
) == SUBREG
)
4456 reg
= SUBREG_REG (reg
);
4458 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4460 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4462 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4465 lra_change_class (regno
, new_class
, " Change to", true);
4471 const char *constraint
;
4473 rtx op
= *curr_id
->operand_loc
[i
];
4474 rtx subreg
= NULL_RTX
;
4475 machine_mode mode
= curr_operand_mode
[i
];
4477 if (GET_CODE (op
) == SUBREG
)
4480 op
= SUBREG_REG (op
);
4481 mode
= GET_MODE (op
);
4484 if (CONST_POOL_OK_P (mode
, op
)
4485 && ((targetm
.preferred_reload_class
4486 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4487 || no_input_reloads_p
))
4489 rtx tem
= force_const_mem (mode
, op
);
4492 if (subreg
!= NULL_RTX
)
4493 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4495 *curr_id
->operand_loc
[i
] = tem
;
4496 lra_update_dup (curr_id
, i
);
4497 process_address (i
, false, &before
, &after
);
4499 /* If the alternative accepts constant pool refs directly
4500 there will be no reload needed at all. */
4501 if (subreg
!= NULL_RTX
)
4503 /* Skip alternatives before the one requested. */
4504 constraint
= (curr_static_id
->operand_alternative
4505 [goal_alt_number
* n_operands
+ i
].constraint
);
4507 (c
= *constraint
) && c
!= ',' && c
!= '#';
4508 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4510 enum constraint_num cn
= lookup_constraint (constraint
);
4511 if ((insn_extra_memory_constraint (cn
)
4512 || insn_extra_special_memory_constraint (cn
)
4513 || insn_extra_relaxed_memory_constraint (cn
))
4514 && satisfies_memory_constraint_p (tem
, cn
))
4517 if (c
== '\0' || c
== ',' || c
== '#')
4520 goal_alt_win
[i
] = true;
4525 for (i
= 0; i
< n_operands
; i
++)
4526 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4527 outputs
[n_outputs
++] = i
;
4528 outputs
[n_outputs
] = -1;
4529 for (i
= 0; i
< n_operands
; i
++)
4532 bool optional_p
= false;
4534 rtx op
= *curr_id
->operand_loc
[i
];
4536 if (goal_alt_win
[i
])
4538 if (goal_alt
[i
] == NO_REGS
4540 /* When we assign NO_REGS it means that we will not
4541 assign a hard register to the scratch pseudo by
4542 assigment pass and the scratch pseudo will be
4543 spilled. Spilled scratch pseudos are transformed
4544 back to scratches at the LRA end. */
4545 && ira_former_scratch_operand_p (curr_insn
, i
)
4546 && ira_former_scratch_p (REGNO (op
)))
4548 int regno
= REGNO (op
);
4549 lra_change_class (regno
, NO_REGS
, " Change to", true);
4550 if (lra_get_regno_hard_regno (regno
) >= 0)
4551 /* We don't have to mark all insn affected by the
4552 spilled pseudo as there is only one such insn, the
4554 reg_renumber
[regno
] = -1;
4555 lra_assert (bitmap_single_bit_set_p
4556 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4558 /* We can do an optional reload. If the pseudo got a hard
4559 reg, we might improve the code through inheritance. If
4560 it does not get a hard register we coalesce memory/memory
4561 moves later. Ignore move insns to avoid cycling. */
4563 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4564 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4565 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4566 && regno
< new_regno_start
4567 && ! ira_former_scratch_p (regno
)
4568 && reg_renumber
[regno
] < 0
4569 /* Check that the optional reload pseudo will be able to
4570 hold given mode value. */
4571 && ! (prohibited_class_reg_set_mode_p
4572 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4573 PSEUDO_REGNO_MODE (regno
)))
4574 && (curr_insn_set
== NULL_RTX
4575 || !((REG_P (SET_SRC (curr_insn_set
))
4576 || MEM_P (SET_SRC (curr_insn_set
))
4577 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4578 && (REG_P (SET_DEST (curr_insn_set
))
4579 || MEM_P (SET_DEST (curr_insn_set
))
4580 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4582 else if (goal_alt_matched
[i
][0] != -1
4583 && curr_static_id
->operand
[i
].type
== OP_OUT
4584 && (curr_static_id
->operand_alternative
4585 [goal_alt_number
* n_operands
+ i
].earlyclobber
)
4588 for (j
= 0; goal_alt_matched
[i
][j
] != -1; j
++)
4590 rtx op2
= *curr_id
->operand_loc
[goal_alt_matched
[i
][j
]];
4592 if (REG_P (op2
) && REGNO (op
) != REGNO (op2
))
4595 if (goal_alt_matched
[i
][j
] != -1)
4597 /* Generate reloads for different output and matched
4598 input registers. This is the easiest way to avoid
4599 creation of non-existing register conflicts in
4601 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4602 &goal_alt_exclude_start_hard_regs
[i
], &before
,
4609 enum reg_class rclass
, common_class
;
4611 if (REG_P (op
) && goal_alt
[i
] != NO_REGS
4612 && (regno
= REGNO (op
)) >= new_regno_start
4613 && (rclass
= get_reg_class (regno
)) == ALL_REGS
4614 && ((common_class
= ira_reg_class_subset
[rclass
][goal_alt
[i
]])
4616 && common_class
!= ALL_REGS
4617 && enough_allocatable_hard_regs_p (common_class
,
4619 /* Refine reload pseudo class from chosen alternative
4621 lra_change_class (regno
, common_class
, " Change to", true);
4626 /* Operands that match previous ones have already been handled. */
4627 if (goal_alt_matches
[i
] >= 0)
4630 /* We should not have an operand with a non-offsettable address
4631 appearing where an offsettable address will do. It also may
4632 be a case when the address should be special in other words
4633 not a general one (e.g. it needs no index reg). */
4634 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4636 enum reg_class rclass
;
4637 rtx
*loc
= &XEXP (op
, 0);
4638 enum rtx_code code
= GET_CODE (*loc
);
4640 push_to_sequence (before
);
4641 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4643 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4644 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4645 /* This value does not matter for MODIFY. */
4646 GET_MODE_SIZE (GET_MODE (op
)));
4647 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
4649 "offsetable address", &new_reg
))
4652 enum rtx_code code
= GET_CODE (addr
);
4653 bool align_p
= false;
4655 if (code
== AND
&& CONST_INT_P (XEXP (addr
, 1)))
4657 /* (and ... (const_int -X)) is used to align to X bytes. */
4659 addr
= XEXP (*loc
, 0);
4662 addr
= canonicalize_reload_addr (addr
);
4664 lra_emit_move (new_reg
, addr
);
4666 emit_move_insn (new_reg
, gen_rtx_AND (GET_MODE (new_reg
), new_reg
, XEXP (*loc
, 1)));
4668 before
= get_insns ();
4671 lra_update_dup (curr_id
, i
);
4673 else if (goal_alt_matched
[i
][0] == -1)
4678 enum op_type type
= curr_static_id
->operand
[i
].type
;
4680 loc
= curr_id
->operand_loc
[i
];
4681 mode
= curr_operand_mode
[i
];
4682 if (GET_CODE (*loc
) == SUBREG
)
4684 reg
= SUBREG_REG (*loc
);
4685 poly_int64 byte
= SUBREG_BYTE (*loc
);
4687 /* Strict_low_part requires reloading the register and not
4688 just the subreg. Likewise for a strict subreg no wider
4689 than a word for WORD_REGISTER_OPERATIONS targets. */
4690 && (curr_static_id
->operand
[i
].strict_low
4691 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4693 = get_try_hard_regno (REGNO (reg
))) >= 0
4694 && (simplify_subreg_regno
4696 GET_MODE (reg
), byte
, mode
) < 0)
4697 && (goal_alt
[i
] == NO_REGS
4698 || (simplify_subreg_regno
4699 (ira_class_hard_regs
[goal_alt
[i
]][0],
4700 GET_MODE (reg
), byte
, mode
) >= 0)))
4701 || (partial_subreg_p (mode
, GET_MODE (reg
))
4702 && known_le (GET_MODE_SIZE (GET_MODE (reg
)),
4704 && WORD_REGISTER_OPERATIONS
))
4705 /* Avoid the situation when there are no available hard regs
4706 for the pseudo mode but there are ones for the subreg
4708 && !(goal_alt
[i
] != NO_REGS
4709 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
4710 && (prohibited_class_reg_set_mode_p
4711 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4713 && !(prohibited_class_reg_set_mode_p
4714 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4717 /* An OP_INOUT is required when reloading a subreg of a
4718 mode wider than a word to ensure that data beyond the
4719 word being reloaded is preserved. Also automatically
4720 ensure that strict_low_part reloads are made into
4721 OP_INOUT which should already be true from the backend
4724 && (curr_static_id
->operand
[i
].strict_low
4725 || read_modify_subreg_p (*loc
)))
4727 loc
= &SUBREG_REG (*loc
);
4728 mode
= GET_MODE (*loc
);
4732 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4733 &goal_alt_exclude_start_hard_regs
[i
],
4734 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4737 push_to_sequence (before
);
4738 lra_emit_move (new_reg
, old
);
4739 before
= get_insns ();
4744 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4747 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4749 after
= get_insns ();
4753 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4754 if (goal_alt_dont_inherit_ops
[j
] == i
)
4756 lra_set_regno_unique_value (REGNO (new_reg
));
4759 lra_update_dup (curr_id
, i
);
4761 else if (curr_static_id
->operand
[i
].type
== OP_IN
4762 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4764 || (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4766 && (operands_match_p
4767 (*curr_id
->operand_loc
[i
],
4768 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4771 /* generate reloads for input and matched outputs. */
4772 match_inputs
[0] = i
;
4773 match_inputs
[1] = -1;
4774 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4775 goal_alt
[i
], &goal_alt_exclude_start_hard_regs
[i
],
4777 curr_static_id
->operand_alternative
4778 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4781 else if ((curr_static_id
->operand
[i
].type
== OP_OUT
4782 || (curr_static_id
->operand
[i
].type
== OP_INOUT
4783 && (operands_match_p
4784 (*curr_id
->operand_loc
[i
],
4785 *curr_id
->operand_loc
[goal_alt_matched
[i
][0]],
4787 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4789 /* Generate reloads for output and matched inputs. */
4790 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
],
4791 &goal_alt_exclude_start_hard_regs
[i
], &before
, &after
,
4792 curr_static_id
->operand_alternative
4793 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4794 else if (curr_static_id
->operand
[i
].type
== OP_IN
4795 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4798 /* Generate reloads for matched inputs. */
4799 match_inputs
[0] = i
;
4800 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4801 match_inputs
[j
+ 1] = k
;
4802 match_inputs
[j
+ 1] = -1;
4803 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
],
4804 &goal_alt_exclude_start_hard_regs
[i
],
4805 &before
, &after
, false);
4808 /* We must generate code in any case when function
4809 process_alt_operands decides that it is possible. */
4816 lra_assert (REG_P (reg
));
4817 regno
= REGNO (reg
);
4818 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4819 if (GET_CODE (op
) == SUBREG
)
4820 op
= SUBREG_REG (op
);
4821 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4822 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4823 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4824 if (lra_dump_file
!= NULL
)
4825 fprintf (lra_dump_file
,
4826 " Making reload reg %d for reg %d optional\n",
4830 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4831 || max_regno_before
!= max_reg_num ())
4835 lra_update_operator_dups (curr_id
);
4836 /* Something changes -- process the insn. */
4837 lra_update_insn_regno_info (curr_insn
);
4838 if (asm_noperands (PATTERN (curr_insn
)) >= 0
4839 && ++curr_id
->asm_reloads_num
>= FIRST_PSEUDO_REGISTER
)
4840 /* Most probably there are no enough registers to satisfy asm insn: */
4841 lra_asm_insn_error (curr_insn
);
4843 if (goal_alt_out_sp_reload_p
)
4845 /* We have an output stack pointer reload -- update sp offset: */
4847 bool done_p
= false;
4848 poly_int64 sp_offset
= curr_id
->sp_offset
;
4849 for (rtx_insn
*insn
= after
; insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
4850 if ((set
= single_set (insn
)) != NULL_RTX
4851 && SET_DEST (set
) == stack_pointer_rtx
)
4853 lra_assert (!done_p
);
4855 curr_id
->sp_offset
= 0;
4856 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
4857 id
->sp_offset
= sp_offset
;
4858 if (lra_dump_file
!= NULL
)
4859 fprintf (lra_dump_file
,
4860 " Moving sp offset from insn %u to %u\n",
4861 INSN_UID (curr_insn
), INSN_UID (insn
));
4863 lra_assert (done_p
);
4865 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4869 /* Return true if INSN satisfies all constraints. In other words, no
4870 reload insns are needed. */
4872 lra_constrain_insn (rtx_insn
*insn
)
4874 int saved_new_regno_start
= new_regno_start
;
4875 int saved_new_insn_uid_start
= new_insn_uid_start
;
4879 curr_id
= lra_get_insn_recog_data (curr_insn
);
4880 curr_static_id
= curr_id
->insn_static_data
;
4881 new_insn_uid_start
= get_max_uid ();
4882 new_regno_start
= max_reg_num ();
4883 change_p
= curr_insn_transform (true);
4884 new_regno_start
= saved_new_regno_start
;
4885 new_insn_uid_start
= saved_new_insn_uid_start
;
4889 /* Return true if X is in LIST. */
4891 in_list_p (rtx x
, rtx list
)
4893 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4894 if (XEXP (list
, 0) == x
)
4899 /* Return true if X contains an allocatable hard register (if
4900 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4902 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4908 code
= GET_CODE (x
);
4911 int regno
= REGNO (x
);
4912 HARD_REG_SET alloc_regs
;
4916 if (regno
>= FIRST_PSEUDO_REGISTER
)
4917 regno
= lra_get_regno_hard_regno (regno
);
4920 alloc_regs
= ~lra_no_alloc_regs
;
4921 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4925 if (regno
< FIRST_PSEUDO_REGISTER
)
4929 return lra_get_regno_hard_regno (regno
) < 0;
4932 fmt
= GET_RTX_FORMAT (code
);
4933 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4937 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4940 else if (fmt
[i
] == 'E')
4942 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4943 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4950 /* Process all regs in location *LOC and change them on equivalent
4951 substitution. Return true if any change was done. */
4953 loc_equivalence_change_p (rtx
*loc
)
4955 rtx subst
, reg
, x
= *loc
;
4956 bool result
= false;
4957 enum rtx_code code
= GET_CODE (x
);
4963 reg
= SUBREG_REG (x
);
4964 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4965 && GET_MODE (subst
) == VOIDmode
)
4967 /* We cannot reload debug location. Simplify subreg here
4968 while we know the inner mode. */
4969 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4970 GET_MODE (reg
), SUBREG_BYTE (x
));
4974 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4980 /* Scan all the operand sub-expressions. */
4981 fmt
= GET_RTX_FORMAT (code
);
4982 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4985 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4986 else if (fmt
[i
] == 'E')
4987 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4989 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4994 /* Similar to loc_equivalence_change_p, but for use as
4995 simplify_replace_fn_rtx callback. DATA is insn for which the
4996 elimination is done. If it null we don't do the elimination. */
4998 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
5003 rtx subst
= (data
== NULL
5004 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
5011 /* Maximum number of generated reload insns per an insn. It is for
5012 preventing this pass cycling in a bug case. */
5013 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
5015 /* The current iteration number of this LRA pass. */
5016 int lra_constraint_iter
;
5018 /* True if we should during assignment sub-pass check assignment
5019 correctness for all pseudos and spill some of them to correct
5020 conflicts. It can be necessary when we substitute equiv which
5021 needs checking register allocation correctness because the
5022 equivalent value contains allocatable hard registers, or when we
5023 restore multi-register pseudo, or when we change the insn code and
5024 its operand became INOUT operand when it was IN one before. */
5025 bool check_and_force_assignment_correctness_p
;
5027 /* Return true if REGNO is referenced in more than one block. */
5029 multi_block_pseudo_p (int regno
)
5031 basic_block bb
= NULL
;
5035 if (regno
< FIRST_PSEUDO_REGISTER
)
5038 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
5040 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
5041 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
5046 /* Return true if LIST contains a deleted insn. */
5048 contains_deleted_insn_p (rtx_insn_list
*list
)
5050 for (; list
!= NULL_RTX
; list
= list
->next ())
5051 if (NOTE_P (list
->insn ())
5052 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
5057 /* Return true if X contains a pseudo dying in INSN. */
5059 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
5066 return (insn
!= NULL_RTX
5067 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
5068 code
= GET_CODE (x
);
5069 fmt
= GET_RTX_FORMAT (code
);
5070 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5074 if (dead_pseudo_p (XEXP (x
, i
), insn
))
5077 else if (fmt
[i
] == 'E')
5079 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5080 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
5087 /* Return true if INSN contains a dying pseudo in INSN right hand
5090 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
5092 rtx set
= single_set (insn
);
5094 gcc_assert (set
!= NULL
);
5095 return dead_pseudo_p (SET_SRC (set
), insn
);
5098 /* Return true if any init insn of REGNO contains a dying pseudo in
5099 insn right hand side. */
5101 init_insn_rhs_dead_pseudo_p (int regno
)
5103 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5107 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
5108 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
5113 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
5114 reverse only if we have one init insn with given REGNO as a
5117 reverse_equiv_p (int regno
)
5119 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
5124 if (! INSN_P (insns
->insn ())
5125 || insns
->next () != NULL
)
5127 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
5129 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
5132 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
5133 call this function only for non-reverse equivalence. */
5135 contains_reloaded_insn_p (int regno
)
5138 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
5140 for (; list
!= NULL
; list
= list
->next ())
5141 if ((set
= single_set (list
->insn ())) == NULL_RTX
5142 || ! REG_P (SET_DEST (set
))
5143 || (int) REGNO (SET_DEST (set
)) != regno
)
5148 /* Try combine secondary memory reload insn FROM for insn TO into TO insn.
5149 FROM should be a load insn (usually a secondary memory reload insn). Return
5150 TRUE in case of success. */
5152 combine_reload_insn (rtx_insn
*from
, rtx_insn
*to
)
5155 rtx_insn
*saved_insn
;
5156 rtx set
, from_reg
, to_reg
, op
;
5157 enum reg_class to_class
, from_class
;
5159 signed char changed_nops
[MAX_RECOG_OPERANDS
+ 1];
5161 /* Check conditions for second memory reload and original insn: */
5162 if ((targetm
.secondary_memory_needed
5163 == hook_bool_mode_reg_class_t_reg_class_t_false
)
5164 || NEXT_INSN (from
) != to
5165 || !NONDEBUG_INSN_P (to
)
5169 lra_insn_recog_data_t id
= lra_get_insn_recog_data (to
);
5170 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
5172 if (id
->used_insn_alternative
== LRA_UNKNOWN_ALT
5173 || (set
= single_set (from
)) == NULL_RTX
)
5175 from_reg
= SET_DEST (set
);
5176 to_reg
= SET_SRC (set
);
5177 /* Ignore optional reloads: */
5178 if (! REG_P (from_reg
) || ! REG_P (to_reg
)
5179 || bitmap_bit_p (&lra_optional_reload_pseudos
, REGNO (from_reg
)))
5181 to_class
= lra_get_allocno_class (REGNO (to_reg
));
5182 from_class
= lra_get_allocno_class (REGNO (from_reg
));
5183 /* Check that reload insn is a load: */
5184 if (to_class
!= NO_REGS
|| from_class
== NO_REGS
)
5186 for (n
= nop
= 0; nop
< static_id
->n_operands
; nop
++)
5188 if (static_id
->operand
[nop
].type
!= OP_IN
)
5190 op
= *id
->operand_loc
[nop
];
5191 if (!REG_P (op
) || REGNO (op
) != REGNO (from_reg
))
5193 *id
->operand_loc
[nop
] = to_reg
;
5194 changed_nops
[n
++] = nop
;
5196 changed_nops
[n
] = -1;
5197 lra_update_dups (id
, changed_nops
);
5198 lra_update_insn_regno_info (to
);
5199 ok_p
= recog_memoized (to
) >= 0;
5202 /* Check that combined insn does not need any reloads: */
5203 saved_insn
= curr_insn
;
5205 curr_id
= lra_get_insn_recog_data (curr_insn
);
5206 curr_static_id
= curr_id
->insn_static_data
;
5207 for (bool swapped_p
= false;;)
5209 ok_p
= !curr_insn_transform (true);
5210 if (ok_p
|| curr_static_id
->commutative
< 0)
5212 swap_operands (curr_static_id
->commutative
);
5213 if (lra_dump_file
!= NULL
)
5215 fprintf (lra_dump_file
,
5216 " Swapping %scombined insn operands:\n",
5217 swapped_p
? "back " : "");
5218 dump_insn_slim (lra_dump_file
, to
);
5224 curr_insn
= saved_insn
;
5225 curr_id
= lra_get_insn_recog_data (curr_insn
);
5226 curr_static_id
= curr_id
->insn_static_data
;
5230 id
->used_insn_alternative
= -1;
5231 lra_push_insn_and_update_insn_regno_info (to
);
5232 if (lra_dump_file
!= NULL
)
5234 fprintf (lra_dump_file
, " Use combined insn:\n");
5235 dump_insn_slim (lra_dump_file
, to
);
5239 if (lra_dump_file
!= NULL
)
5241 fprintf (lra_dump_file
, " Failed combined insn:\n");
5242 dump_insn_slim (lra_dump_file
, to
);
5244 for (int i
= 0; i
< n
; i
++)
5246 nop
= changed_nops
[i
];
5247 *id
->operand_loc
[nop
] = from_reg
;
5249 lra_update_dups (id
, changed_nops
);
5250 lra_update_insn_regno_info (to
);
5251 if (lra_dump_file
!= NULL
)
5253 fprintf (lra_dump_file
, " Restoring insn after failed combining:\n");
5254 dump_insn_slim (lra_dump_file
, to
);
5259 /* Entry function of LRA constraint pass. Return true if the
5260 constraint pass did change the code. */
5262 lra_constraints (bool first_p
)
5265 int i
, hard_regno
, new_insns_num
;
5266 unsigned int min_len
, new_min_len
, uid
;
5267 rtx set
, x
, reg
, dest_reg
;
5268 rtx_insn
*original_insn
;
5269 basic_block last_bb
;
5272 lra_constraint_iter
++;
5273 if (lra_dump_file
!= NULL
)
5274 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
5275 lra_constraint_iter
);
5277 if (pic_offset_table_rtx
5278 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5279 check_and_force_assignment_correctness_p
= true;
5281 /* On the first iteration we should check IRA assignment
5282 correctness. In rare cases, the assignments can be wrong as
5283 early clobbers operands are ignored in IRA or usages of
5284 paradoxical sub-registers are not taken into account by
5286 check_and_force_assignment_correctness_p
= true;
5287 new_insn_uid_start
= get_max_uid ();
5288 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
5289 /* Mark used hard regs for target stack size calulations. */
5290 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5291 if (lra_reg_info
[i
].nrefs
!= 0
5292 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5296 nregs
= hard_regno_nregs (hard_regno
, lra_reg_info
[i
].biggest_mode
);
5297 for (j
= 0; j
< nregs
; j
++)
5298 df_set_regs_ever_live (hard_regno
+ j
, true);
5300 /* Do elimination before the equivalence processing as we can spill
5301 some pseudos during elimination. */
5302 lra_eliminate (false, first_p
);
5303 auto_bitmap
equiv_insn_bitmap (®_obstack
);
5304 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5305 if (lra_reg_info
[i
].nrefs
!= 0)
5307 ira_reg_equiv
[i
].profitable_p
= true;
5308 reg
= regno_reg_rtx
[i
];
5309 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
5311 bool pseudo_p
= contains_reg_p (x
, false, false);
5313 /* After RTL transformation, we cannot guarantee that
5314 pseudo in the substitution was not reloaded which might
5315 make equivalence invalid. For example, in reverse
5322 the memory address register was reloaded before the 2nd
5324 if ((! first_p
&& pseudo_p
)
5325 /* We don't use DF for compilation speed sake. So it
5326 is problematic to update live info when we use an
5327 equivalence containing pseudos in more than one
5329 || (pseudo_p
&& multi_block_pseudo_p (i
))
5330 /* If an init insn was deleted for some reason, cancel
5331 the equiv. We could update the equiv insns after
5332 transformations including an equiv insn deletion
5333 but it is not worthy as such cases are extremely
5335 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
5336 /* If it is not a reverse equivalence, we check that a
5337 pseudo in rhs of the init insn is not dying in the
5338 insn. Otherwise, the live info at the beginning of
5339 the corresponding BB might be wrong after we
5340 removed the insn. When the equiv can be a
5341 constant, the right hand side of the init insn can
5343 || (! reverse_equiv_p (i
)
5344 && (init_insn_rhs_dead_pseudo_p (i
)
5345 /* If we reloaded the pseudo in an equivalence
5346 init insn, we cannot remove the equiv init
5347 insns and the init insns might write into
5348 const memory in this case. */
5349 || contains_reloaded_insn_p (i
)))
5350 /* Prevent access beyond equivalent memory for
5351 paradoxical subregs. */
5353 && maybe_gt (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
),
5354 GET_MODE_SIZE (GET_MODE (x
))))
5355 || (pic_offset_table_rtx
5356 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
5357 && (targetm
.preferred_reload_class
5358 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
5359 || contains_symbol_ref_p (x
))))
5360 ira_reg_equiv
[i
].defined_p
5361 = ira_reg_equiv
[i
].caller_save_p
= false;
5362 if (contains_reg_p (x
, false, true))
5363 ira_reg_equiv
[i
].profitable_p
= false;
5364 if (get_equiv (reg
) != reg
)
5365 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
5368 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5370 /* We should add all insns containing pseudos which should be
5371 substituted by their equivalences. */
5372 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
5373 lra_push_insn_by_uid (uid
);
5374 min_len
= lra_insn_stack_length ();
5378 original_insn
= NULL
;
5379 while ((new_min_len
= lra_insn_stack_length ()) != 0)
5381 curr_insn
= lra_pop_insn ();
5383 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5384 if (curr_bb
!= last_bb
)
5387 bb_reload_num
= lra_curr_reload_num
;
5389 if (min_len
> new_min_len
)
5391 min_len
= new_min_len
;
5393 original_insn
= curr_insn
;
5395 else if (combine_reload_insn (curr_insn
, original_insn
))
5399 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
5401 ("maximum number of generated reload insns per insn achieved (%d)",
5402 MAX_RELOAD_INSNS_NUMBER
);
5404 if (DEBUG_INSN_P (curr_insn
))
5406 /* We need to check equivalence in debug insn and change
5407 pseudo to the equivalent value if necessary. */
5408 curr_id
= lra_get_insn_recog_data (curr_insn
);
5409 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
5411 rtx old
= *curr_id
->operand_loc
[0];
5412 *curr_id
->operand_loc
[0]
5413 = simplify_replace_fn_rtx (old
, NULL_RTX
,
5414 loc_equivalence_callback
, curr_insn
);
5415 if (old
!= *curr_id
->operand_loc
[0])
5417 lra_update_insn_regno_info (curr_insn
);
5422 else if (INSN_P (curr_insn
))
5424 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
5426 dest_reg
= SET_DEST (set
);
5427 /* The equivalence pseudo could be set up as SUBREG in a
5428 case when it is a call restore insn in a mode
5429 different from the pseudo mode. */
5430 if (GET_CODE (dest_reg
) == SUBREG
)
5431 dest_reg
= SUBREG_REG (dest_reg
);
5432 if ((REG_P (dest_reg
)
5433 && (x
= get_equiv (dest_reg
)) != dest_reg
5434 /* Remove insns which set up a pseudo whose value
5435 cannot be changed. Such insns might be not in
5436 init_insns because we don't update equiv data
5437 during insn transformations.
5439 As an example, let suppose that a pseudo got
5440 hard register and on the 1st pass was not
5441 changed to equivalent constant. We generate an
5442 additional insn setting up the pseudo because of
5443 secondary memory movement. Then the pseudo is
5444 spilled and we use the equiv constant. In this
5445 case we should remove the additional insn and
5446 this insn is not init_insns list. */
5447 && (! MEM_P (x
) || MEM_READONLY_P (x
)
5448 /* Check that this is actually an insn setting
5449 up the equivalence. */
5450 || in_list_p (curr_insn
,
5452 [REGNO (dest_reg
)].init_insns
)))
5453 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
5454 && in_list_p (curr_insn
,
5456 [REGNO (SET_SRC (set
))].init_insns
)))
5458 /* This is equiv init insn of pseudo which did not get a
5459 hard register -- remove the insn. */
5460 if (lra_dump_file
!= NULL
)
5462 fprintf (lra_dump_file
,
5463 " Removing equiv init insn %i (freq=%d)\n",
5464 INSN_UID (curr_insn
),
5465 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
5466 dump_insn_slim (lra_dump_file
, curr_insn
);
5468 if (contains_reg_p (x
, true, false))
5469 check_and_force_assignment_correctness_p
= true;
5470 lra_set_insn_deleted (curr_insn
);
5474 curr_id
= lra_get_insn_recog_data (curr_insn
);
5475 curr_static_id
= curr_id
->insn_static_data
;
5476 init_curr_insn_input_reloads ();
5477 init_curr_operand_mode ();
5478 if (curr_insn_transform (false))
5480 /* Check non-transformed insns too for equiv change as USE
5481 or CLOBBER don't need reloads but can contain pseudos
5482 being changed on their equivalences. */
5483 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
5484 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
5486 lra_update_insn_regno_info (curr_insn
);
5492 /* If we used a new hard regno, changed_p should be true because the
5493 hard reg is assigned to a new pseudo. */
5494 if (flag_checking
&& !changed_p
)
5496 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
5497 if (lra_reg_info
[i
].nrefs
!= 0
5498 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
5500 int j
, nregs
= hard_regno_nregs (hard_regno
,
5501 PSEUDO_REGNO_MODE (i
));
5503 for (j
= 0; j
< nregs
; j
++)
5504 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
5510 static void initiate_invariants (void);
5511 static void finish_invariants (void);
5513 /* Initiate the LRA constraint pass. It is done once per
5516 lra_constraints_init (void)
5518 initiate_invariants ();
5521 /* Finalize the LRA constraint pass. It is done once per
5524 lra_constraints_finish (void)
5526 finish_invariants ();
5531 /* Structure describes invariants for ineheritance. */
5532 struct lra_invariant
5534 /* The order number of the invariant. */
5536 /* The invariant RTX. */
5538 /* The origin insn of the invariant. */
5542 typedef lra_invariant invariant_t
;
5543 typedef invariant_t
*invariant_ptr_t
;
5544 typedef const invariant_t
*const_invariant_ptr_t
;
5546 /* Pointer to the inheritance invariants. */
5547 static vec
<invariant_ptr_t
> invariants
;
5549 /* Allocation pool for the invariants. */
5550 static object_allocator
<lra_invariant
> *invariants_pool
;
5552 /* Hash table for the invariants. */
5553 static htab_t invariant_table
;
5555 /* Hash function for INVARIANT. */
5557 invariant_hash (const void *invariant
)
5559 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
5560 return lra_rtx_hash (inv
);
5563 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5565 invariant_eq_p (const void *invariant1
, const void *invariant2
)
5567 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
5568 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
5570 return rtx_equal_p (inv1
, inv2
);
5573 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5574 invariant which is in the table. */
5575 static invariant_ptr_t
5576 insert_invariant (rtx invariant_rtx
)
5579 invariant_t invariant
;
5580 invariant_ptr_t invariant_ptr
;
5582 invariant
.invariant_rtx
= invariant_rtx
;
5583 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
5584 if (*entry_ptr
== NULL
)
5586 invariant_ptr
= invariants_pool
->allocate ();
5587 invariant_ptr
->invariant_rtx
= invariant_rtx
;
5588 invariant_ptr
->insn
= NULL
;
5589 invariants
.safe_push (invariant_ptr
);
5590 *entry_ptr
= (void *) invariant_ptr
;
5592 return (invariant_ptr_t
) *entry_ptr
;
5595 /* Initiate the invariant table. */
5597 initiate_invariants (void)
5599 invariants
.create (100);
5601 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
5602 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
5605 /* Finish the invariant table. */
5607 finish_invariants (void)
5609 htab_delete (invariant_table
);
5610 delete invariants_pool
;
5611 invariants
.release ();
5614 /* Make the invariant table empty. */
5616 clear_invariants (void)
5618 htab_empty (invariant_table
);
5619 invariants_pool
->release ();
5620 invariants
.truncate (0);
5625 /* This page contains code to do inheritance/split
5628 /* Number of reloads passed so far in current EBB. */
5629 static int reloads_num
;
5631 /* Number of calls passed so far in current EBB. */
5632 static int calls_num
;
5634 /* Index ID is the CALLS_NUM associated the last call we saw with
5635 ABI identifier ID. */
5636 static int last_call_for_abi
[NUM_ABI_IDS
];
5638 /* Which registers have been fully or partially clobbered by a call
5639 since they were last used. */
5640 static HARD_REG_SET full_and_partial_call_clobbers
;
5642 /* Current reload pseudo check for validity of elements in
5644 static int curr_usage_insns_check
;
5646 /* Info about last usage of registers in EBB to do inheritance/split
5647 transformation. Inheritance transformation is done from a spilled
5648 pseudo and split transformations from a hard register or a pseudo
5649 assigned to a hard register. */
5652 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5653 value INSNS is valid. The insns is chain of optional debug insns
5654 and a finishing non-debug insn using the corresponding reg. The
5655 value is also used to mark the registers which are set up in the
5656 current insn. The negated insn uid is used for this. */
5658 /* Value of global reloads_num at the last insn in INSNS. */
5660 /* Value of global reloads_nums at the last insn in INSNS. */
5662 /* It can be true only for splitting. And it means that the restore
5663 insn should be put after insn given by the following member. */
5665 /* Next insns in the current EBB which use the original reg and the
5666 original reg value is not changed between the current insn and
5667 the next insns. In order words, e.g. for inheritance, if we need
5668 to use the original reg value again in the next insns we can try
5669 to use the value in a hard register from a reload insn of the
5674 /* Map: regno -> corresponding pseudo usage insns. */
5675 static struct usage_insns
*usage_insns
;
5678 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5680 usage_insns
[regno
].check
= curr_usage_insns_check
;
5681 usage_insns
[regno
].insns
= insn
;
5682 usage_insns
[regno
].reloads_num
= reloads_num
;
5683 usage_insns
[regno
].calls_num
= calls_num
;
5684 usage_insns
[regno
].after_p
= after_p
;
5685 if (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0)
5686 remove_from_hard_reg_set (&full_and_partial_call_clobbers
,
5687 PSEUDO_REGNO_MODE (regno
),
5688 reg_renumber
[regno
]);
5691 /* The function is used to form list REGNO usages which consists of
5692 optional debug insns finished by a non-debug insn using REGNO.
5693 RELOADS_NUM is current number of reload insns processed so far. */
5695 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5697 rtx next_usage_insns
;
5699 if (usage_insns
[regno
].check
== curr_usage_insns_check
5700 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5701 && DEBUG_INSN_P (insn
))
5703 /* Check that we did not add the debug insn yet. */
5704 if (next_usage_insns
!= insn
5705 && (GET_CODE (next_usage_insns
) != INSN_LIST
5706 || XEXP (next_usage_insns
, 0) != insn
))
5707 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5710 else if (NONDEBUG_INSN_P (insn
))
5711 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5713 usage_insns
[regno
].check
= 0;
5716 /* Return first non-debug insn in list USAGE_INSNS. */
5718 skip_usage_debug_insns (rtx usage_insns
)
5722 /* Skip debug insns. */
5723 for (insn
= usage_insns
;
5724 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5725 insn
= XEXP (insn
, 1))
5727 return safe_as_a
<rtx_insn
*> (insn
);
5730 /* Return true if we need secondary memory moves for insn in
5731 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5734 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5735 rtx usage_insns ATTRIBUTE_UNUSED
)
5741 if (inher_cl
== ALL_REGS
5742 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5744 lra_assert (INSN_P (insn
));
5745 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5747 dest
= SET_DEST (set
);
5750 lra_assert (inher_cl
!= NO_REGS
);
5751 cl
= get_reg_class (REGNO (dest
));
5752 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5753 && targetm
.secondary_memory_needed (GET_MODE (dest
), inher_cl
, cl
));
5756 /* Registers involved in inheritance/split in the current EBB
5757 (inheritance/split pseudos and original registers). */
5758 static bitmap_head check_only_regs
;
5760 /* Reload pseudos cannot be involded in invariant inheritance in the
5762 static bitmap_head invalid_invariant_regs
;
5764 /* Do inheritance transformations for insn INSN, which defines (if
5765 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5766 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5767 form as the "insns" field of usage_insns. Return true if we
5768 succeed in such transformation.
5770 The transformations look like:
5773 ... p <- i (new insn)
5775 <- ... p ... <- ... i ...
5777 ... i <- p (new insn)
5778 <- ... p ... <- ... i ...
5780 <- ... p ... <- ... i ...
5781 where p is a spilled original pseudo and i is a new inheritance pseudo.
5784 The inheritance pseudo has the smallest class of two classes CL and
5785 class of ORIGINAL REGNO. */
5787 inherit_reload_reg (bool def_p
, int original_regno
,
5788 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5790 if (optimize_function_for_size_p (cfun
))
5793 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5794 rtx original_reg
= regno_reg_rtx
[original_regno
];
5795 rtx new_reg
, usage_insn
;
5796 rtx_insn
*new_insns
;
5798 lra_assert (! usage_insns
[original_regno
].after_p
);
5799 if (lra_dump_file
!= NULL
)
5800 fprintf (lra_dump_file
,
5801 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5802 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5804 if (lra_dump_file
!= NULL
)
5806 fprintf (lra_dump_file
,
5807 " Rejecting inheritance for %d "
5808 "because of disjoint classes %s and %s\n",
5809 original_regno
, reg_class_names
[cl
],
5810 reg_class_names
[rclass
]);
5811 fprintf (lra_dump_file
,
5812 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5816 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5817 /* We don't use a subset of two classes because it can be
5818 NO_REGS. This transformation is still profitable in most
5819 cases even if the classes are not intersected as register
5820 move is probably cheaper than a memory load. */
5821 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5823 if (lra_dump_file
!= NULL
)
5824 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5825 reg_class_names
[cl
], reg_class_names
[rclass
]);
5829 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5831 /* Reject inheritance resulting in secondary memory moves.
5832 Otherwise, there is a danger in LRA cycling. Also such
5833 transformation will be unprofitable. */
5834 if (lra_dump_file
!= NULL
)
5836 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5837 rtx set
= single_set (insn
);
5839 lra_assert (set
!= NULL_RTX
);
5841 rtx dest
= SET_DEST (set
);
5843 lra_assert (REG_P (dest
));
5844 fprintf (lra_dump_file
,
5845 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5846 "as secondary mem is needed\n",
5847 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5848 original_regno
, reg_class_names
[rclass
]);
5849 fprintf (lra_dump_file
,
5850 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5854 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5855 rclass
, NULL
, "inheritance");
5858 lra_emit_move (original_reg
, new_reg
);
5860 lra_emit_move (new_reg
, original_reg
);
5861 new_insns
= get_insns ();
5863 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5865 if (lra_dump_file
!= NULL
)
5867 fprintf (lra_dump_file
,
5868 " Rejecting inheritance %d->%d "
5869 "as it results in 2 or more insns:\n",
5870 original_regno
, REGNO (new_reg
));
5871 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5872 fprintf (lra_dump_file
,
5873 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5877 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5878 lra_update_insn_regno_info (insn
);
5880 /* We now have a new usage insn for original regno. */
5881 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5882 if (lra_dump_file
!= NULL
)
5883 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5884 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5885 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5886 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5887 bitmap_set_bit (&check_only_regs
, original_regno
);
5888 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5890 lra_process_new_insns (insn
, NULL
, new_insns
,
5891 "Add original<-inheritance");
5893 lra_process_new_insns (insn
, new_insns
, NULL
,
5894 "Add inheritance<-original");
5895 while (next_usage_insns
!= NULL_RTX
)
5897 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5899 usage_insn
= next_usage_insns
;
5900 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5901 next_usage_insns
= NULL
;
5905 usage_insn
= XEXP (next_usage_insns
, 0);
5906 lra_assert (DEBUG_INSN_P (usage_insn
));
5907 next_usage_insns
= XEXP (next_usage_insns
, 1);
5909 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
5910 DEBUG_INSN_P (usage_insn
));
5911 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5912 if (lra_dump_file
!= NULL
)
5914 basic_block bb
= BLOCK_FOR_INSN (usage_insn
);
5915 fprintf (lra_dump_file
,
5916 " Inheritance reuse change %d->%d (bb%d):\n",
5917 original_regno
, REGNO (new_reg
),
5918 bb
? bb
->index
: -1);
5919 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5922 if (lra_dump_file
!= NULL
)
5923 fprintf (lra_dump_file
,
5924 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5928 /* Return true if we need a caller save/restore for pseudo REGNO which
5929 was assigned to a hard register. */
5931 need_for_call_save_p (int regno
)
5933 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5934 if (usage_insns
[regno
].calls_num
< calls_num
)
5936 unsigned int abis
= 0;
5937 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
5938 if (last_call_for_abi
[i
] > usage_insns
[regno
].calls_num
)
5941 if (call_clobbered_in_region_p (abis
, full_and_partial_call_clobbers
,
5942 PSEUDO_REGNO_MODE (regno
),
5943 reg_renumber
[regno
]))
5949 /* Global registers occurring in the current EBB. */
5950 static bitmap_head ebb_global_regs
;
5952 /* Return true if we need a split for hard register REGNO or pseudo
5953 REGNO which was assigned to a hard register.
5954 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5955 used for reloads since the EBB end. It is an approximation of the
5956 used hard registers in the split range. The exact value would
5957 require expensive calculations. If we were aggressive with
5958 splitting because of the approximation, the split pseudo will save
5959 the same hard register assignment and will be removed in the undo
5960 pass. We still need the approximation because too aggressive
5961 splitting would result in too inaccurate cost calculation in the
5962 assignment pass because of too many generated moves which will be
5963 probably removed in the undo pass. */
5965 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5967 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5969 lra_assert (hard_regno
>= 0);
5970 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5971 /* Don't split eliminable hard registers, otherwise we can
5972 split hard registers like hard frame pointer, which
5973 lives on BB start/end according to DF-infrastructure,
5974 when there is a pseudo assigned to the register and
5975 living in the same BB. */
5976 && (regno
>= FIRST_PSEUDO_REGISTER
5977 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5978 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5979 /* Don't split call clobbered hard regs living through
5980 calls, otherwise we might have a check problem in the
5981 assign sub-pass as in the most cases (exception is a
5982 situation when check_and_force_assignment_correctness_p value is
5983 true) the assign pass assumes that all pseudos living
5984 through calls are assigned to call saved hard regs. */
5985 && (regno
>= FIRST_PSEUDO_REGISTER
5986 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers
, regno
))
5987 /* We need at least 2 reloads to make pseudo splitting
5988 profitable. We should provide hard regno splitting in
5989 any case to solve 1st insn scheduling problem when
5990 moving hard register definition up might result in
5991 impossibility to find hard register for reload pseudo of
5992 small register class. */
5993 && (usage_insns
[regno
].reloads_num
5994 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5995 && (regno
< FIRST_PSEUDO_REGISTER
5996 /* For short living pseudos, spilling + inheritance can
5997 be considered a substitution for splitting.
5998 Therefore we do not splitting for local pseudos. It
5999 decreases also aggressiveness of splitting. The
6000 minimal number of references is chosen taking into
6001 account that for 2 references splitting has no sense
6002 as we can just spill the pseudo. */
6003 || (regno
>= FIRST_PSEUDO_REGISTER
6004 && lra_reg_info
[regno
].nrefs
> 3
6005 && bitmap_bit_p (&ebb_global_regs
, regno
))))
6006 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
6009 /* Return class for the split pseudo created from original pseudo with
6010 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
6011 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
6012 results in no secondary memory movements. */
6013 static enum reg_class
6014 choose_split_class (enum reg_class allocno_class
,
6015 int hard_regno ATTRIBUTE_UNUSED
,
6016 machine_mode mode ATTRIBUTE_UNUSED
)
6019 enum reg_class cl
, best_cl
= NO_REGS
;
6020 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
6021 = REGNO_REG_CLASS (hard_regno
);
6023 if (! targetm
.secondary_memory_needed (mode
, allocno_class
, allocno_class
)
6024 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
6025 return allocno_class
;
6027 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
6029 if (! targetm
.secondary_memory_needed (mode
, cl
, hard_reg_class
)
6030 && ! targetm
.secondary_memory_needed (mode
, hard_reg_class
, cl
)
6031 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
6032 && (best_cl
== NO_REGS
6033 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
6038 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. It only
6039 makes sense to call this function if NEW_REGNO is always equal to
6040 ORIGINAL_REGNO. Set up defined_p flag when caller_save_p flag is set up and
6041 CALL_SAVE_P is true. */
6044 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
,
6047 if (!ira_reg_equiv
[original_regno
].defined_p
6048 && !(call_save_p
&& ira_reg_equiv
[original_regno
].caller_save_p
))
6051 ira_expand_reg_equiv ();
6052 ira_reg_equiv
[new_regno
].defined_p
= true;
6053 if (ira_reg_equiv
[original_regno
].memory
)
6054 ira_reg_equiv
[new_regno
].memory
6055 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
6056 if (ira_reg_equiv
[original_regno
].constant
)
6057 ira_reg_equiv
[new_regno
].constant
6058 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
6059 if (ira_reg_equiv
[original_regno
].invariant
)
6060 ira_reg_equiv
[new_regno
].invariant
6061 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
6064 /* Do split transformations for insn INSN, which defines or uses
6065 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
6066 the EBB next uses ORIGINAL_REGNO; it has the same form as the
6067 "insns" field of usage_insns. If TO is not NULL, we don't use
6068 usage_insns, we put restore insns after TO insn. It is a case when
6069 we call it from lra_split_hard_reg_for, outside the inheritance
6072 The transformations look like:
6075 ... s <- p (new insn -- save)
6077 ... p <- s (new insn -- restore)
6078 <- ... p ... <- ... p ...
6080 <- ... p ... <- ... p ...
6081 ... s <- p (new insn -- save)
6083 ... p <- s (new insn -- restore)
6084 <- ... p ... <- ... p ...
6086 where p is an original pseudo got a hard register or a hard
6087 register and s is a new split pseudo. The save is put before INSN
6088 if BEFORE_P is true. Return true if we succeed in such
6091 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
6092 rtx next_usage_insns
, rtx_insn
*to
)
6094 enum reg_class rclass
;
6096 int hard_regno
, nregs
;
6097 rtx new_reg
, usage_insn
;
6098 rtx_insn
*restore
, *save
;
6103 if (original_regno
< FIRST_PSEUDO_REGISTER
)
6105 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
6106 hard_regno
= original_regno
;
6107 call_save_p
= false;
6109 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
6110 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
6111 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
6112 part of a multi-word register. In that case, just use the reg_rtx
6113 mode. Do the same also if the biggest mode was larger than a register
6114 or we can not compare the modes. Otherwise, limit the size to that of
6115 the biggest access in the function or to the natural mode at least. */
6116 if (mode
== VOIDmode
6117 || !ordered_p (GET_MODE_PRECISION (mode
),
6118 GET_MODE_PRECISION (reg_rtx_mode
))
6119 || paradoxical_subreg_p (mode
, reg_rtx_mode
)
6120 || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode
), GET_MODE_PRECISION (mode
)))
6122 original_reg
= regno_reg_rtx
[hard_regno
];
6123 mode
= reg_rtx_mode
;
6126 original_reg
= gen_rtx_REG (mode
, hard_regno
);
6130 mode
= PSEUDO_REGNO_MODE (original_regno
);
6131 hard_regno
= reg_renumber
[original_regno
];
6132 nregs
= hard_regno_nregs (hard_regno
, mode
);
6133 rclass
= lra_get_allocno_class (original_regno
);
6134 original_reg
= regno_reg_rtx
[original_regno
];
6135 call_save_p
= need_for_call_save_p (original_regno
);
6137 lra_assert (hard_regno
>= 0);
6138 if (lra_dump_file
!= NULL
)
6139 fprintf (lra_dump_file
,
6140 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
6144 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
6145 hard_regno_nregs (hard_regno
, mode
),
6147 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, NULL
, "save");
6151 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
6152 if (rclass
== NO_REGS
)
6154 if (lra_dump_file
!= NULL
)
6156 fprintf (lra_dump_file
,
6157 " Rejecting split of %d(%s): "
6158 "no good reg class for %d(%s)\n",
6160 reg_class_names
[lra_get_allocno_class (original_regno
)],
6162 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
6165 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6169 /* Split_if_necessary can split hard registers used as part of a
6170 multi-register mode but splits each register individually. The
6171 mode used for each independent register may not be supported
6172 so reject the split. Splitting the wider mode should theoretically
6173 be possible but is not implemented. */
6174 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
6176 if (lra_dump_file
!= NULL
)
6178 fprintf (lra_dump_file
,
6179 " Rejecting split of %d(%s): unsuitable mode %s\n",
6181 reg_class_names
[lra_get_allocno_class (original_regno
)],
6182 GET_MODE_NAME (mode
));
6185 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6189 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, NULL
, "split");
6190 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
6192 int new_regno
= REGNO (new_reg
);
6193 save
= emit_spill_move (true, new_reg
, original_reg
);
6194 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
6196 if (lra_dump_file
!= NULL
)
6200 " Rejecting split %d->%d resulting in > 2 save insns:\n",
6201 original_regno
, new_regno
);
6202 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
6203 fprintf (lra_dump_file
,
6204 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6208 restore
= emit_spill_move (false, new_reg
, original_reg
);
6209 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
6211 if (lra_dump_file
!= NULL
)
6213 fprintf (lra_dump_file
,
6214 " Rejecting split %d->%d "
6215 "resulting in > 2 restore insns:\n",
6216 original_regno
, new_regno
);
6217 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
6218 fprintf (lra_dump_file
,
6219 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6223 /* Transfer equivalence information to the spill register, so that
6224 if we fail to allocate the spill register, we have the option of
6225 rematerializing the original value instead of spilling to the stack. */
6226 if (!HARD_REGISTER_NUM_P (original_regno
)
6227 && mode
== PSEUDO_REGNO_MODE (original_regno
))
6228 lra_copy_reg_equiv (new_regno
, original_regno
, call_save_p
);
6229 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
6230 bitmap_set_bit (&lra_split_regs
, new_regno
);
6233 lra_assert (next_usage_insns
== NULL
);
6239 /* We need check_only_regs only inside the inheritance pass. */
6240 bitmap_set_bit (&check_only_regs
, new_regno
);
6241 bitmap_set_bit (&check_only_regs
, original_regno
);
6242 after_p
= usage_insns
[original_regno
].after_p
;
6245 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
6247 usage_insn
= next_usage_insns
;
6250 usage_insn
= XEXP (next_usage_insns
, 0);
6251 lra_assert (DEBUG_INSN_P (usage_insn
));
6252 next_usage_insns
= XEXP (next_usage_insns
, 1);
6253 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false,
6255 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
6256 if (lra_dump_file
!= NULL
)
6258 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
6259 original_regno
, new_regno
);
6260 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
6264 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
6265 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
6266 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
6267 after_p
? NULL
: restore
,
6268 after_p
? restore
: NULL
,
6270 ? "Add reg<-save" : "Add reg<-split");
6271 lra_process_new_insns (insn
, before_p
? save
: NULL
,
6272 before_p
? NULL
: save
,
6274 ? "Add save<-reg" : "Add split<-reg");
6275 if (nregs
> 1 || original_regno
< FIRST_PSEUDO_REGISTER
)
6276 /* If we are trying to split multi-register. We should check
6277 conflicts on the next assignment sub-pass. IRA can allocate on
6278 sub-register levels, LRA do this on pseudos level right now and
6279 this discrepancy may create allocation conflicts after
6282 If we are trying to split hard register we should also check conflicts
6283 as such splitting can create artificial conflict of the hard register
6284 with another pseudo because of simplified conflict calculation in
6286 check_and_force_assignment_correctness_p
= true;
6287 if (lra_dump_file
!= NULL
)
6288 fprintf (lra_dump_file
,
6289 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6293 /* Split a hard reg for reload pseudo REGNO having RCLASS and living
6294 in the range [FROM, TO]. Return true if did a split. Otherwise,
6297 spill_hard_reg_in_range (int regno
, enum reg_class rclass
, rtx_insn
*from
, rtx_insn
*to
)
6304 HARD_REG_SET ignore
;
6306 lra_assert (from
!= NULL
&& to
!= NULL
);
6307 ignore
= lra_no_alloc_regs
;
6308 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
6310 lra_insn_recog_data_t id
= lra_insn_recog_data
[uid
];
6311 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
6312 struct lra_insn_reg
*reg
;
6314 for (reg
= id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6315 if (reg
->regno
< FIRST_PSEUDO_REGISTER
)
6316 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6317 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6318 SET_HARD_REG_BIT (ignore
, reg
->regno
);
6320 rclass_size
= ira_class_hard_regs_num
[rclass
];
6321 for (i
= 0; i
< rclass_size
; i
++)
6323 hard_regno
= ira_class_hard_regs
[rclass
][i
];
6324 if (! TEST_HARD_REG_BIT (lra_reg_info
[regno
].conflict_hard_regs
, hard_regno
)
6325 || TEST_HARD_REG_BIT (ignore
, hard_regno
))
6327 for (insn
= from
; insn
!= NEXT_INSN (to
); insn
= NEXT_INSN (insn
))
6329 struct lra_static_insn_data
*static_id
;
6330 struct lra_insn_reg
*reg
;
6334 if (bitmap_bit_p (&lra_reg_info
[hard_regno
].insn_bitmap
,
6337 static_id
= lra_get_insn_recog_data (insn
)->insn_static_data
;
6338 for (reg
= static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6339 if (reg
->regno
== hard_regno
)
6344 if (insn
!= NEXT_INSN (to
))
6346 if (split_reg (true, hard_regno
, from
, NULL
, to
))
6352 /* Recognize that we need a split transformation for insn INSN, which
6353 defines or uses REGNO in its insn biggest MODE (we use it only if
6354 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
6355 hard registers which might be used for reloads since the EBB end.
6356 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
6357 uid before starting INSN processing. Return true if we succeed in
6358 such transformation. */
6360 split_if_necessary (int regno
, machine_mode mode
,
6361 HARD_REG_SET potential_reload_hard_regs
,
6362 bool before_p
, rtx_insn
*insn
, int max_uid
)
6366 rtx next_usage_insns
;
6368 if (regno
< FIRST_PSEUDO_REGISTER
)
6369 nregs
= hard_regno_nregs (regno
, mode
);
6370 for (i
= 0; i
< nregs
; i
++)
6371 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
6372 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
6373 /* To avoid processing the register twice or more. */
6374 && ((GET_CODE (next_usage_insns
) != INSN_LIST
6375 && INSN_UID (next_usage_insns
) < max_uid
)
6376 || (GET_CODE (next_usage_insns
) == INSN_LIST
6377 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
6378 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
6379 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
, NULL
))
6384 /* Return TRUE if rtx X is considered as an invariant for
6387 invariant_p (const_rtx x
)
6394 if (side_effects_p (x
))
6397 code
= GET_CODE (x
);
6398 mode
= GET_MODE (x
);
6402 code
= GET_CODE (x
);
6403 mode
= wider_subreg_mode (mode
, GET_MODE (x
));
6411 int i
, nregs
, regno
= REGNO (x
);
6413 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
6414 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
6415 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
6417 nregs
= hard_regno_nregs (regno
, mode
);
6418 for (i
= 0; i
< nregs
; i
++)
6419 if (! fixed_regs
[regno
+ i
]
6420 /* A hard register may be clobbered in the current insn
6421 but we can ignore this case because if the hard
6422 register is used it should be set somewhere after the
6424 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
6427 fmt
= GET_RTX_FORMAT (code
);
6428 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6432 if (! invariant_p (XEXP (x
, i
)))
6435 else if (fmt
[i
] == 'E')
6437 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6438 if (! invariant_p (XVECEXP (x
, i
, j
)))
6445 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6446 inheritance transformation (using dest_reg instead invariant in a
6447 subsequent insn). */
6449 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
6451 invariant_ptr_t invariant_ptr
;
6452 rtx_insn
*insn
, *new_insns
;
6453 rtx insn_set
, insn_reg
, new_reg
;
6455 bool succ_p
= false;
6456 int dst_regno
= REGNO (dst_reg
);
6457 machine_mode dst_mode
= GET_MODE (dst_reg
);
6458 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
6460 invariant_ptr
= insert_invariant (invariant_rtx
);
6461 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
6463 /* We have a subsequent insn using the invariant. */
6464 insn_set
= single_set (insn
);
6465 lra_assert (insn_set
!= NULL
);
6466 insn_reg
= SET_DEST (insn_set
);
6467 lra_assert (REG_P (insn_reg
));
6468 insn_regno
= REGNO (insn_reg
);
6469 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
6471 if (dst_mode
== GET_MODE (insn_reg
)
6472 /* We should consider only result move reg insns which are
6474 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
6475 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
6477 if (lra_dump_file
!= NULL
)
6478 fprintf (lra_dump_file
,
6479 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6480 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
, cl
, NULL
,
6481 "invariant inheritance");
6482 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
6483 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
6484 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
6486 lra_emit_move (new_reg
, dst_reg
);
6487 new_insns
= get_insns ();
6489 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6490 "Add invariant inheritance<-original");
6492 lra_emit_move (SET_DEST (insn_set
), new_reg
);
6493 new_insns
= get_insns ();
6495 lra_process_new_insns (insn
, NULL
, new_insns
,
6496 "Changing reload<-inheritance");
6497 lra_set_insn_deleted (insn
);
6499 if (lra_dump_file
!= NULL
)
6501 fprintf (lra_dump_file
,
6502 " Invariant inheritance reuse change %d (bb%d):\n",
6503 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
6504 dump_insn_slim (lra_dump_file
, insn
);
6505 fprintf (lra_dump_file
,
6506 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6510 invariant_ptr
->insn
= curr_insn
;
6514 /* Check only registers living at the current program point in the
6516 static bitmap_head live_regs
;
6518 /* Update live info in EBB given by its HEAD and TAIL insns after
6519 inheritance/split transformation. The function removes dead moves
6522 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
6527 rtx_insn
*prev_insn
;
6530 basic_block last_bb
, prev_bb
, curr_bb
;
6532 struct lra_insn_reg
*reg
;
6536 last_bb
= BLOCK_FOR_INSN (tail
);
6538 for (curr_insn
= tail
;
6539 curr_insn
!= PREV_INSN (head
);
6540 curr_insn
= prev_insn
)
6542 prev_insn
= PREV_INSN (curr_insn
);
6543 /* We need to process empty blocks too. They contain
6544 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6545 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
6547 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6548 if (curr_bb
!= prev_bb
)
6550 if (prev_bb
!= NULL
)
6552 /* Update df_get_live_in (prev_bb): */
6553 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6554 if (bitmap_bit_p (&live_regs
, j
))
6555 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
6557 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
6559 if (curr_bb
!= last_bb
)
6561 /* Update df_get_live_out (curr_bb): */
6562 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
6564 live_p
= bitmap_bit_p (&live_regs
, j
);
6566 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
6567 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
6573 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
6575 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
6579 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
6581 if (! NONDEBUG_INSN_P (curr_insn
))
6583 curr_id
= lra_get_insn_recog_data (curr_insn
);
6584 curr_static_id
= curr_id
->insn_static_data
;
6586 if ((set
= single_set (curr_insn
)) != NULL_RTX
6587 && REG_P (SET_DEST (set
))
6588 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
6589 && SET_DEST (set
) != pic_offset_table_rtx
6590 && bitmap_bit_p (&check_only_regs
, regno
)
6591 && ! bitmap_bit_p (&live_regs
, regno
))
6593 /* See which defined values die here. */
6594 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6595 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6596 bitmap_clear_bit (&live_regs
, reg
->regno
);
6597 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6598 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
6599 bitmap_clear_bit (&live_regs
, reg
->regno
);
6600 if (curr_id
->arg_hard_regs
!= NULL
)
6601 /* Make clobbered argument hard registers die. */
6602 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6603 if (regno
>= FIRST_PSEUDO_REGISTER
)
6604 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
6605 /* Mark each used value as live. */
6606 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6607 if (reg
->type
!= OP_OUT
6608 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6609 bitmap_set_bit (&live_regs
, reg
->regno
);
6610 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6611 if (reg
->type
!= OP_OUT
6612 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
6613 bitmap_set_bit (&live_regs
, reg
->regno
);
6614 if (curr_id
->arg_hard_regs
!= NULL
)
6615 /* Make used argument hard registers live. */
6616 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6617 if (regno
< FIRST_PSEUDO_REGISTER
6618 && bitmap_bit_p (&check_only_regs
, regno
))
6619 bitmap_set_bit (&live_regs
, regno
);
6620 /* It is quite important to remove dead move insns because it
6621 means removing dead store. We don't need to process them for
6625 if (lra_dump_file
!= NULL
)
6627 fprintf (lra_dump_file
, " Removing dead insn:\n ");
6628 dump_insn_slim (lra_dump_file
, curr_insn
);
6630 lra_set_insn_deleted (curr_insn
);
6635 /* The structure describes info to do an inheritance for the current
6636 insn. We need to collect such info first before doing the
6637 transformations because the transformations change the insn
6638 internal representation. */
6641 /* Original regno. */
6643 /* Subsequent insns which can inherit original reg value. */
6647 /* Array containing all info for doing inheritance from the current
6649 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
6651 /* Number elements in the previous array. */
6652 static int to_inherit_num
;
6654 /* Add inheritance info REGNO and INSNS. Their meaning is described in
6655 structure to_inherit. */
6657 add_to_inherit (int regno
, rtx insns
)
6661 for (i
= 0; i
< to_inherit_num
; i
++)
6662 if (to_inherit
[i
].regno
== regno
)
6664 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
6665 to_inherit
[to_inherit_num
].regno
= regno
;
6666 to_inherit
[to_inherit_num
++].insns
= insns
;
6669 /* Return the last non-debug insn in basic block BB, or the block begin
6672 get_last_insertion_point (basic_block bb
)
6676 FOR_BB_INSNS_REVERSE (bb
, insn
)
6677 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
6682 /* Set up RES by registers living on edges FROM except the edge (FROM,
6683 TO) or by registers set up in a jump insn in BB FROM. */
6685 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
6688 struct lra_insn_reg
*reg
;
6692 lra_assert (to
!= NULL
);
6694 FOR_EACH_EDGE (e
, ei
, from
->succs
)
6696 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
6697 last
= get_last_insertion_point (from
);
6698 if (! JUMP_P (last
))
6700 curr_id
= lra_get_insn_recog_data (last
);
6701 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6702 if (reg
->type
!= OP_IN
)
6703 bitmap_set_bit (res
, reg
->regno
);
6706 /* Used as a temporary results of some bitmap calculations. */
6707 static bitmap_head temp_bitmap
;
6709 /* We split for reloads of small class of hard regs. The following
6710 defines how many hard regs the class should have to be qualified as
6711 small. The code is mostly oriented to x86/x86-64 architecture
6712 where some insns need to use only specific register or pair of
6713 registers and these register can live in RTL explicitly, e.g. for
6714 parameter passing. */
6715 static const int max_small_class_regs_num
= 2;
6717 /* Do inheritance/split transformations in EBB starting with HEAD and
6718 finishing on TAIL. We process EBB insns in the reverse order.
6719 Return true if we did any inheritance/split transformation in the
6722 We should avoid excessive splitting which results in worse code
6723 because of inaccurate cost calculations for spilling new split
6724 pseudos in such case. To achieve this we do splitting only if
6725 register pressure is high in given basic block and there are reload
6726 pseudos requiring hard registers. We could do more register
6727 pressure calculations at any given program point to avoid necessary
6728 splitting even more but it is to expensive and the current approach
6729 works well enough. */
6731 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6733 int i
, src_regno
, dst_regno
, nregs
;
6734 bool change_p
, succ_p
, update_reloads_num_p
;
6735 rtx_insn
*prev_insn
, *last_insn
;
6736 rtx next_usage_insns
, curr_set
;
6738 struct lra_insn_reg
*reg
;
6739 basic_block last_processed_bb
, curr_bb
= NULL
;
6740 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6744 bool head_p
, after_p
;
6747 curr_usage_insns_check
++;
6748 clear_invariants ();
6749 reloads_num
= calls_num
= 0;
6750 for (unsigned int i
= 0; i
< NUM_ABI_IDS
; ++i
)
6751 last_call_for_abi
[i
] = 0;
6752 CLEAR_HARD_REG_SET (full_and_partial_call_clobbers
);
6753 bitmap_clear (&check_only_regs
);
6754 bitmap_clear (&invalid_invariant_regs
);
6755 last_processed_bb
= NULL
;
6756 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6757 live_hard_regs
= eliminable_regset
| lra_no_alloc_regs
;
6758 /* We don't process new insns generated in the loop. */
6759 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6761 prev_insn
= PREV_INSN (curr_insn
);
6762 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6763 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6764 if (last_processed_bb
!= curr_bb
)
6766 /* We are at the end of BB. Add qualified living
6767 pseudos for potential splitting. */
6768 to_process
= df_get_live_out (curr_bb
);
6769 if (last_processed_bb
!= NULL
)
6771 /* We are somewhere in the middle of EBB. */
6772 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6774 to_process
= &temp_bitmap
;
6776 last_processed_bb
= curr_bb
;
6777 last_insn
= get_last_insertion_point (curr_bb
);
6778 after_p
= (! JUMP_P (last_insn
)
6779 && (! CALL_P (last_insn
)
6780 || (find_reg_note (last_insn
,
6781 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6782 && ! SIBLING_CALL_P (last_insn
))));
6783 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6784 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6786 if ((int) j
>= lra_constraint_new_regno_start
)
6788 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6790 if (j
< FIRST_PSEUDO_REGISTER
)
6791 SET_HARD_REG_BIT (live_hard_regs
, j
);
6793 add_to_hard_reg_set (&live_hard_regs
,
6794 PSEUDO_REGNO_MODE (j
),
6796 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6800 src_regno
= dst_regno
= -1;
6801 curr_set
= single_set (curr_insn
);
6802 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6803 dst_regno
= REGNO (SET_DEST (curr_set
));
6804 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6805 src_regno
= REGNO (SET_SRC (curr_set
));
6806 update_reloads_num_p
= true;
6807 if (src_regno
< lra_constraint_new_regno_start
6808 && src_regno
>= FIRST_PSEUDO_REGISTER
6809 && reg_renumber
[src_regno
] < 0
6810 && dst_regno
>= lra_constraint_new_regno_start
6811 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6813 /* 'reload_pseudo <- original_pseudo'. */
6814 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6816 update_reloads_num_p
= false;
6818 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6819 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6820 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6821 curr_insn
, next_usage_insns
);
6825 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6826 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6827 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6829 else if (src_regno
< 0
6830 && dst_regno
>= lra_constraint_new_regno_start
6831 && invariant_p (SET_SRC (curr_set
))
6832 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6833 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6834 && ! bitmap_bit_p (&invalid_invariant_regs
,
6835 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6837 /* 'reload_pseudo <- invariant'. */
6838 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6840 update_reloads_num_p
= false;
6841 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6843 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6844 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6846 else if (src_regno
>= lra_constraint_new_regno_start
6847 && dst_regno
< lra_constraint_new_regno_start
6848 && dst_regno
>= FIRST_PSEUDO_REGISTER
6849 && reg_renumber
[dst_regno
] < 0
6850 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6851 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6852 && (next_usage_insns
6853 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6855 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6857 update_reloads_num_p
= false;
6858 /* 'original_pseudo <- reload_pseudo'. */
6859 if (! JUMP_P (curr_insn
)
6860 && inherit_reload_reg (true, dst_regno
, cl
,
6861 curr_insn
, next_usage_insns
))
6864 usage_insns
[dst_regno
].check
= 0;
6865 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6866 potential_reload_hard_regs
|= reg_class_contents
[cl
];
6868 else if (INSN_P (curr_insn
))
6871 int max_uid
= get_max_uid ();
6873 curr_id
= lra_get_insn_recog_data (curr_insn
);
6874 curr_static_id
= curr_id
->insn_static_data
;
6876 /* Process insn definitions. */
6877 for (iter
= 0; iter
< 2; iter
++)
6878 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6881 if (reg
->type
!= OP_IN
6882 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6884 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6885 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6886 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6887 && (next_usage_insns
6888 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6890 struct lra_insn_reg
*r
;
6892 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6893 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6895 /* Don't do inheritance if the pseudo is also
6896 used in the insn. */
6898 /* We cannot do inheritance right now
6899 because the current insn reg info (chain
6900 regs) can change after that. */
6901 add_to_inherit (dst_regno
, next_usage_insns
);
6903 /* We cannot process one reg twice here because of
6904 usage_insns invalidation. */
6905 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6906 || reg_renumber
[dst_regno
] >= 0)
6907 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6911 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6912 potential_reload_hard_regs
,
6913 false, curr_insn
, max_uid
))
6915 CLEAR_HARD_REG_SET (s
);
6916 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6917 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6919 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6920 reg_renumber
[dst_regno
]);
6921 live_hard_regs
&= ~s
;
6922 potential_reload_hard_regs
&= ~s
;
6924 /* We should invalidate potential inheritance or
6925 splitting for the current insn usages to the next
6926 usage insns (see code below) as the output pseudo
6928 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6929 && reg_renumber
[dst_regno
] < 0)
6930 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6931 && (dst_regno
< FIRST_PSEUDO_REGISTER
6932 || reg_renumber
[dst_regno
] >= 0)))
6934 /* Invalidate and mark definitions. */
6935 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6936 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6939 nregs
= hard_regno_nregs (dst_regno
,
6941 for (i
= 0; i
< nregs
; i
++)
6942 usage_insns
[dst_regno
+ i
].check
6943 = -(int) INSN_UID (curr_insn
);
6947 /* Process clobbered call regs. */
6948 if (curr_id
->arg_hard_regs
!= NULL
)
6949 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6950 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6951 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6952 = -(int) INSN_UID (curr_insn
);
6953 if (! JUMP_P (curr_insn
))
6954 for (i
= 0; i
< to_inherit_num
; i
++)
6955 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6956 ALL_REGS
, curr_insn
,
6957 to_inherit
[i
].insns
))
6959 if (CALL_P (curr_insn
))
6961 rtx cheap
, pat
, dest
;
6963 int regno
, hard_regno
;
6966 function_abi callee_abi
= insn_callee_abi (curr_insn
);
6967 last_call_for_abi
[callee_abi
.id ()] = calls_num
;
6968 full_and_partial_call_clobbers
6969 |= callee_abi
.full_and_partial_reg_clobbers ();
6970 if ((cheap
= find_reg_note (curr_insn
,
6971 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6972 && ((cheap
= XEXP (cheap
, 0)), true)
6973 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6974 && (hard_regno
= reg_renumber
[regno
]) >= 0
6975 && usage_insns
[regno
].check
== curr_usage_insns_check
6976 /* If there are pending saves/restores, the
6977 optimization is not worth. */
6978 && usage_insns
[regno
].calls_num
== calls_num
- 1
6979 && callee_abi
.clobbers_reg_p (GET_MODE (cheap
), hard_regno
))
6981 /* Restore the pseudo from the call result as
6982 REG_RETURNED note says that the pseudo value is
6983 in the call result and the pseudo is an argument
6985 pat
= PATTERN (curr_insn
);
6986 if (GET_CODE (pat
) == PARALLEL
)
6987 pat
= XVECEXP (pat
, 0, 0);
6988 dest
= SET_DEST (pat
);
6989 /* For multiple return values dest is PARALLEL.
6990 Currently we handle only single return value case. */
6994 emit_move_insn (cheap
, copy_rtx (dest
));
6995 restore
= get_insns ();
6997 lra_process_new_insns (curr_insn
, NULL
, restore
,
6998 "Inserting call parameter restore");
6999 /* We don't need to save/restore of the pseudo from
7001 usage_insns
[regno
].calls_num
= calls_num
;
7002 remove_from_hard_reg_set
7003 (&full_and_partial_call_clobbers
,
7004 GET_MODE (cheap
), hard_regno
);
7005 bitmap_set_bit (&check_only_regs
, regno
);
7010 /* Process insn usages. */
7011 for (iter
= 0; iter
< 2; iter
++)
7012 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
7015 if ((reg
->type
!= OP_OUT
7016 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
7017 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
7019 if (src_regno
>= FIRST_PSEUDO_REGISTER
7020 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
7022 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
7023 && (next_usage_insns
7024 = usage_insns
[src_regno
].insns
) != NULL_RTX
7025 && NONDEBUG_INSN_P (curr_insn
))
7026 add_to_inherit (src_regno
, next_usage_insns
);
7027 else if (usage_insns
[src_regno
].check
7028 != -(int) INSN_UID (curr_insn
))
7029 /* Add usages but only if the reg is not set up
7030 in the same insn. */
7031 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
7033 else if (src_regno
< FIRST_PSEUDO_REGISTER
7034 || reg_renumber
[src_regno
] >= 0)
7037 rtx_insn
*use_insn
= curr_insn
;
7039 before_p
= (JUMP_P (curr_insn
)
7040 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
7041 if (NONDEBUG_INSN_P (curr_insn
)
7042 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
7043 && split_if_necessary (src_regno
, reg
->biggest_mode
,
7044 potential_reload_hard_regs
,
7045 before_p
, curr_insn
, max_uid
))
7048 check_and_force_assignment_correctness_p
= true;
7051 usage_insns
[src_regno
].check
= 0;
7053 use_insn
= PREV_INSN (curr_insn
);
7055 if (NONDEBUG_INSN_P (curr_insn
))
7057 if (src_regno
< FIRST_PSEUDO_REGISTER
)
7058 add_to_hard_reg_set (&live_hard_regs
,
7059 reg
->biggest_mode
, src_regno
);
7061 add_to_hard_reg_set (&live_hard_regs
,
7062 PSEUDO_REGNO_MODE (src_regno
),
7063 reg_renumber
[src_regno
]);
7065 if (src_regno
>= FIRST_PSEUDO_REGISTER
)
7066 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
7069 for (i
= 0; i
< hard_regno_nregs (src_regno
, reg
->biggest_mode
); i
++)
7070 add_next_usage_insn (src_regno
+ i
, use_insn
, reloads_num
);
7074 /* Process used call regs. */
7075 if (curr_id
->arg_hard_regs
!= NULL
)
7076 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7077 if (src_regno
< FIRST_PSEUDO_REGISTER
)
7079 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
7080 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
7082 for (i
= 0; i
< to_inherit_num
; i
++)
7084 src_regno
= to_inherit
[i
].regno
;
7085 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
7086 curr_insn
, to_inherit
[i
].insns
))
7089 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
7092 if (update_reloads_num_p
7093 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
7096 if ((REG_P (SET_DEST (curr_set
))
7097 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
7098 && reg_renumber
[regno
] < 0
7099 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
7100 || (REG_P (SET_SRC (curr_set
))
7101 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
7102 && reg_renumber
[regno
] < 0
7103 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
7105 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
7107 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
7108 potential_reload_hard_regs
|= reg_class_contents
[cl
];
7111 if (NONDEBUG_INSN_P (curr_insn
))
7115 /* Invalidate invariants with changed regs. */
7116 curr_id
= lra_get_insn_recog_data (curr_insn
);
7117 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7118 if (reg
->type
!= OP_IN
)
7120 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7121 bitmap_set_bit (&invalid_invariant_regs
,
7122 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
7124 curr_static_id
= curr_id
->insn_static_data
;
7125 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
7126 if (reg
->type
!= OP_IN
)
7127 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
7128 if (curr_id
->arg_hard_regs
!= NULL
)
7129 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
7130 if (regno
>= FIRST_PSEUDO_REGISTER
)
7131 bitmap_set_bit (&invalid_invariant_regs
,
7132 regno
- FIRST_PSEUDO_REGISTER
);
7134 /* We reached the start of the current basic block. */
7135 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
7136 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
7138 /* We reached the beginning of the current block -- do
7139 rest of spliting in the current BB. */
7140 to_process
= df_get_live_in (curr_bb
);
7141 if (BLOCK_FOR_INSN (head
) != curr_bb
)
7143 /* We are somewhere in the middle of EBB. */
7144 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
7145 curr_bb
, &temp_bitmap
);
7146 to_process
= &temp_bitmap
;
7149 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
7151 if ((int) j
>= lra_constraint_new_regno_start
)
7153 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
7154 && usage_insns
[j
].check
== curr_usage_insns_check
7155 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
7157 if (need_for_split_p (potential_reload_hard_regs
, j
))
7159 if (lra_dump_file
!= NULL
&& head_p
)
7161 fprintf (lra_dump_file
,
7162 " ----------------------------------\n");
7165 if (split_reg (false, j
, bb_note (curr_bb
),
7166 next_usage_insns
, NULL
))
7169 usage_insns
[j
].check
= 0;
7177 /* This value affects EBB forming. If probability of edge from EBB to
7178 a BB is not greater than the following value, we don't add the BB
7180 #define EBB_PROBABILITY_CUTOFF \
7181 ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
7183 /* Current number of inheritance/split iteration. */
7184 int lra_inheritance_iter
;
7186 /* Entry function for inheritance/split pass. */
7188 lra_inheritance (void)
7191 basic_block bb
, start_bb
;
7194 lra_inheritance_iter
++;
7195 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7197 timevar_push (TV_LRA_INHERITANCE
);
7198 if (lra_dump_file
!= NULL
)
7199 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
7200 lra_inheritance_iter
);
7201 curr_usage_insns_check
= 0;
7202 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
7203 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
7204 usage_insns
[i
].check
= 0;
7205 bitmap_initialize (&check_only_regs
, ®_obstack
);
7206 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
7207 bitmap_initialize (&live_regs
, ®_obstack
);
7208 bitmap_initialize (&temp_bitmap
, ®_obstack
);
7209 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
7210 FOR_EACH_BB_FN (bb
, cfun
)
7213 if (lra_dump_file
!= NULL
)
7214 fprintf (lra_dump_file
, "EBB");
7215 /* Form a EBB starting with BB. */
7216 bitmap_clear (&ebb_global_regs
);
7217 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
7220 if (lra_dump_file
!= NULL
)
7221 fprintf (lra_dump_file
, " %d", bb
->index
);
7222 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
7223 || LABEL_P (BB_HEAD (bb
->next_bb
)))
7225 e
= find_fallthru_edge (bb
->succs
);
7228 if (e
->probability
.initialized_p ()
7229 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
7233 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
7234 if (lra_dump_file
!= NULL
)
7235 fprintf (lra_dump_file
, "\n");
7236 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
7237 /* Remember that the EBB head and tail can change in
7239 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
7241 bitmap_release (&ebb_global_regs
);
7242 bitmap_release (&temp_bitmap
);
7243 bitmap_release (&live_regs
);
7244 bitmap_release (&invalid_invariant_regs
);
7245 bitmap_release (&check_only_regs
);
7248 timevar_pop (TV_LRA_INHERITANCE
);
7253 /* This page contains code to undo failed inheritance/split
7256 /* Current number of iteration undoing inheritance/split. */
7257 int lra_undo_inheritance_iter
;
7259 /* Fix BB live info LIVE after removing pseudos created on pass doing
7260 inheritance/split which are REMOVED_PSEUDOS. */
7262 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
7267 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
7268 if (bitmap_clear_bit (live
, regno
)
7269 && REG_P (lra_reg_info
[regno
].restore_rtx
))
7270 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
7273 /* Return regno of the (subreg of) REG. Otherwise, return a negative
7278 if (GET_CODE (reg
) == SUBREG
)
7279 reg
= SUBREG_REG (reg
);
7285 /* Delete a move INSN with destination reg DREGNO and a previous
7286 clobber insn with the same regno. The inheritance/split code can
7287 generate moves with preceding clobber and when we delete such moves
7288 we should delete the clobber insn too to keep the correct life
7291 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
7293 rtx_insn
*prev_insn
= PREV_INSN (insn
);
7295 lra_set_insn_deleted (insn
);
7296 lra_assert (dregno
>= 0);
7297 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
7298 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
7299 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
7300 lra_set_insn_deleted (prev_insn
);
7303 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
7304 return true if we did any change. The undo transformations for
7305 inheritance looks like
7309 p <- i, i <- p, and i <- i3
7310 where p is original pseudo from which inheritance pseudo i was
7311 created, i and i3 are removed inheritance pseudos, i2 is another
7312 not removed inheritance pseudo. All split pseudos or other
7313 occurrences of removed inheritance pseudos are changed on the
7314 corresponding original pseudos.
7316 The function also schedules insns changed and created during
7317 inheritance/split pass for processing by the subsequent constraint
7320 remove_inheritance_pseudos (bitmap remove_pseudos
)
7323 int regno
, sregno
, prev_sregno
, dregno
;
7326 rtx_insn
*prev_insn
;
7327 bool change_p
, done_p
;
7329 change_p
= ! bitmap_empty_p (remove_pseudos
);
7330 /* We cannot finish the function right away if CHANGE_P is true
7331 because we need to marks insns affected by previous
7332 inheritance/split pass for processing by the subsequent
7334 FOR_EACH_BB_FN (bb
, cfun
)
7336 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
7337 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
7338 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
7340 if (! INSN_P (curr_insn
))
7343 sregno
= dregno
= -1;
7344 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
7345 && (set
= single_set (curr_insn
)) != NULL_RTX
)
7347 dregno
= get_regno (SET_DEST (set
));
7348 sregno
= get_regno (SET_SRC (set
));
7351 if (sregno
>= 0 && dregno
>= 0)
7353 if (bitmap_bit_p (remove_pseudos
, dregno
)
7354 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
7356 /* invariant inheritance pseudo <- original pseudo */
7357 if (lra_dump_file
!= NULL
)
7359 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
7360 dump_insn_slim (lra_dump_file
, curr_insn
);
7361 fprintf (lra_dump_file
, "\n");
7363 delete_move_and_clobber (curr_insn
, dregno
);
7366 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7367 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
7369 /* reload pseudo <- invariant inheritance pseudo */
7371 /* We cannot just change the source. It might be
7372 an insn different from the move. */
7373 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
7374 rtx_insn
*new_insns
= get_insns ();
7376 lra_assert (single_set (new_insns
) != NULL
7377 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
7378 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
7379 "Changing reload<-invariant inheritance");
7380 delete_move_and_clobber (curr_insn
, dregno
);
7383 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
7384 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
7385 || (bitmap_bit_p (remove_pseudos
, dregno
)
7386 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7387 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7388 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
7389 || (bitmap_bit_p (remove_pseudos
, dregno
)
7390 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
7391 /* One of the following cases:
7392 original <- removed inheritance pseudo
7393 removed inherit pseudo <- another removed inherit pseudo
7394 removed inherit pseudo <- original pseudo
7396 removed_split_pseudo <- original_reg
7397 original_reg <- removed_split_pseudo */
7399 if (lra_dump_file
!= NULL
)
7401 fprintf (lra_dump_file
, " Removing %s:\n",
7402 bitmap_bit_p (&lra_split_regs
, sregno
)
7403 || bitmap_bit_p (&lra_split_regs
, dregno
)
7404 ? "split" : "inheritance");
7405 dump_insn_slim (lra_dump_file
, curr_insn
);
7407 delete_move_and_clobber (curr_insn
, dregno
);
7410 else if (bitmap_bit_p (remove_pseudos
, sregno
)
7411 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
7413 /* Search the following pattern:
7414 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
7415 original_pseudo <- inherit_or_split_pseudo1
7416 where the 2nd insn is the current insn and
7417 inherit_or_split_pseudo2 is not removed. If it is found,
7418 change the current insn onto:
7419 original_pseudo <- inherit_or_split_pseudo2. */
7420 for (prev_insn
= PREV_INSN (curr_insn
);
7421 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
7422 prev_insn
= PREV_INSN (prev_insn
))
7424 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
7425 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
7426 /* There should be no subregs in insn we are
7427 searching because only the original reg might
7428 be in subreg when we changed the mode of
7429 load/store for splitting. */
7430 && REG_P (SET_DEST (prev_set
))
7431 && REG_P (SET_SRC (prev_set
))
7432 && (int) REGNO (SET_DEST (prev_set
)) == sregno
7433 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
7434 >= FIRST_PSEUDO_REGISTER
)
7435 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
7437 /* As we consider chain of inheritance or
7438 splitting described in above comment we should
7439 check that sregno and prev_sregno were
7440 inheritance/split pseudos created from the
7441 same original regno. */
7442 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
7443 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
7444 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
7445 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
7447 lra_assert (GET_MODE (SET_SRC (prev_set
))
7448 == GET_MODE (regno_reg_rtx
[sregno
]));
7449 /* Although we have a single set, the insn can
7450 contain more one sregno register occurrence
7451 as a source. Change all occurrences. */
7452 lra_substitute_pseudo_within_insn (curr_insn
, sregno
,
7455 /* As we are finishing with processing the insn
7456 here, check the destination too as it might
7457 inheritance pseudo for another pseudo. */
7458 if (bitmap_bit_p (remove_pseudos
, dregno
)
7459 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
7461 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
7463 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
7464 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
7466 SET_DEST (set
) = restore_rtx
;
7468 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7469 lra_set_used_insn_alternative_by_uid
7470 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7472 if (lra_dump_file
!= NULL
)
7474 fprintf (lra_dump_file
, " Change reload insn:\n");
7475 dump_insn_slim (lra_dump_file
, curr_insn
);
7482 struct lra_insn_reg
*reg
;
7483 bool restored_regs_p
= false;
7484 bool kept_regs_p
= false;
7486 curr_id
= lra_get_insn_recog_data (curr_insn
);
7487 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
7490 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
7491 if (restore_rtx
!= NULL_RTX
)
7493 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
7495 lra_substitute_pseudo_within_insn
7496 (curr_insn
, regno
, restore_rtx
, false);
7497 restored_regs_p
= true;
7503 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
7505 /* The instruction has changed since the previous
7506 constraints pass. */
7507 lra_push_insn_and_update_insn_regno_info (curr_insn
);
7508 lra_set_used_insn_alternative_by_uid
7509 (INSN_UID (curr_insn
), LRA_UNKNOWN_ALT
);
7511 else if (restored_regs_p
)
7512 /* The instruction has been restored to the form that
7513 it had during the previous constraints pass. */
7514 lra_update_insn_regno_info (curr_insn
);
7515 if (restored_regs_p
&& lra_dump_file
!= NULL
)
7517 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
7518 dump_insn_slim (lra_dump_file
, curr_insn
);
7526 /* If optional reload pseudos failed to get a hard register or was not
7527 inherited, it is better to remove optional reloads. We do this
7528 transformation after undoing inheritance to figure out necessity to
7529 remove optional reloads easier. Return true if we do any
7532 undo_optional_reloads (void)
7534 bool change_p
, keep_p
;
7535 unsigned int regno
, uid
;
7536 bitmap_iterator bi
, bi2
;
7539 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
7541 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
7542 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7545 /* Keep optional reloads from previous subpasses. */
7546 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
7547 /* If the original pseudo changed its allocation, just
7548 removing the optional pseudo is dangerous as the original
7549 pseudo will have longer live range. */
7550 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
7552 else if (reg_renumber
[regno
] >= 0)
7553 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
7555 insn
= lra_insn_recog_data
[uid
]->insn
;
7556 if ((set
= single_set (insn
)) == NULL_RTX
)
7558 src
= SET_SRC (set
);
7559 dest
= SET_DEST (set
);
7560 if ((! REG_P (src
) && ! SUBREG_P (src
))
7561 || (! REG_P (dest
) && ! SUBREG_P (dest
)))
7563 if (get_regno (dest
) == (int) regno
7564 /* Ignore insn for optional reloads itself. */
7565 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7567 /* Check only inheritance on last inheritance pass. */
7568 && get_regno (src
) >= new_regno_start
7569 /* Check that the optional reload was inherited. */
7570 && bitmap_bit_p (&lra_inheritance_pseudos
, get_regno (src
)))
7578 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
7579 if (lra_dump_file
!= NULL
)
7580 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
7583 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
7584 auto_bitmap
insn_bitmap (®_obstack
);
7585 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
7587 if (lra_dump_file
!= NULL
)
7588 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
7589 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
7590 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
7592 /* We may have already removed a clobber. */
7593 if (!lra_insn_recog_data
[uid
])
7595 insn
= lra_insn_recog_data
[uid
]->insn
;
7596 if ((set
= single_set (insn
)) != NULL_RTX
)
7598 src
= SET_SRC (set
);
7599 dest
= SET_DEST (set
);
7600 if ((REG_P (src
) || SUBREG_P (src
))
7601 && (REG_P (dest
) || SUBREG_P (dest
))
7602 && ((get_regno (src
) == (int) regno
7603 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7604 == get_regno (dest
)))
7605 || (get_regno (dest
) == (int) regno
7606 && (get_regno (lra_reg_info
[regno
].restore_rtx
)
7607 == get_regno (src
)))))
7609 if (lra_dump_file
!= NULL
)
7611 fprintf (lra_dump_file
, " Deleting move %u\n",
7613 dump_insn_slim (lra_dump_file
, insn
);
7615 delete_move_and_clobber (insn
, get_regno (dest
));
7618 /* We should not worry about generation memory-memory
7619 moves here as if the corresponding inheritance did
7620 not work (inheritance pseudo did not get a hard reg),
7621 we remove the inheritance pseudo and the optional
7624 if (GET_CODE (PATTERN (insn
)) == CLOBBER
7625 && REG_P (SET_DEST (insn
))
7626 && get_regno (SET_DEST (insn
)) == (int) regno
)
7627 /* Refuse to remap clobbers to preexisting pseudos. */
7629 lra_substitute_pseudo_within_insn
7630 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
7631 lra_update_insn_regno_info (insn
);
7632 if (lra_dump_file
!= NULL
)
7634 fprintf (lra_dump_file
,
7635 " Restoring original insn:\n");
7636 dump_insn_slim (lra_dump_file
, insn
);
7640 /* Clear restore_regnos. */
7641 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
7642 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7646 /* Entry function for undoing inheritance/split transformation. Return true
7647 if we did any RTL change in this pass. */
7649 lra_undo_inheritance (void)
7653 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
7658 lra_undo_inheritance_iter
++;
7659 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
7661 if (lra_dump_file
!= NULL
)
7662 fprintf (lra_dump_file
,
7663 "\n********** Undoing inheritance #%d: **********\n\n",
7664 lra_undo_inheritance_iter
);
7665 auto_bitmap
remove_pseudos (®_obstack
);
7666 n_inherit
= n_all_inherit
= 0;
7667 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7668 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
7671 if (reg_renumber
[regno
] < 0
7672 /* If the original pseudo changed its allocation, just
7673 removing inheritance is dangerous as for changing
7674 allocation we used shorter live-ranges. */
7675 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
7676 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
7677 bitmap_set_bit (remove_pseudos
, regno
);
7681 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
7682 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
7683 n_inherit
, n_all_inherit
,
7684 (double) n_inherit
/ n_all_inherit
* 100);
7685 n_split
= n_all_split
= 0;
7686 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7687 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
7689 int restore_regno
= REGNO (restore_rtx
);
7692 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
7693 ? reg_renumber
[restore_regno
] : restore_regno
);
7694 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
7695 bitmap_set_bit (remove_pseudos
, regno
);
7699 if (lra_dump_file
!= NULL
)
7700 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
7701 regno
, restore_regno
);
7704 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
7705 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
7706 n_split
, n_all_split
,
7707 (double) n_split
/ n_all_split
* 100);
7708 change_p
= remove_inheritance_pseudos (remove_pseudos
);
7709 /* Clear restore_regnos. */
7710 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
7711 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7712 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
7713 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
7714 change_p
= undo_optional_reloads () || change_p
;