| blob | 55f52bf6c51ecd32955a7eacc8291f541c8ef790 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
53 /* Vector mapping INSN_UIDs to luids.
54 The luids are like uids but increase monotonically always.
55 We use them to see whether a jump comes from outside a given loop. */
59 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
60 number the insn is contained in. */
64 /* 1 + largest uid of any insn. */
68 /* 1 + luid of last insn. */
72 /* Number of loops detected in current function. Used as index to the
73 next few tables. */
77 /* Indexed by loop number, contains the first and last insn of each loop. */
81 /* Likewise for the continue insn */
84 /* The first code_label that is reached in every loop iteration.
85 0 when not computed yet, initially const0_rtx if a jump couldn't be
86 followed.
87 Also set to 0 when there is no such label before the NOTE_INSN_LOOP_CONT
88 of this loop, or in verify_dominator, if a jump couldn't be followed. */
91 /* For each loop, gives the containing loop number, -1 if none. */
95 #ifdef HAVE_decrement_and_branch_on_count
96 /* Records whether resource in use by inner loop. */
101 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
102 really a loop (an insn outside the loop branches into it). */
106 /* Indexed by loop number, links together all LABEL_REFs which refer to
107 code labels outside the loop. Used by routines that need to know all
108 loop exits, such as final_biv_value and final_giv_value.
110 This does not include loop exits due to return instructions. This is
111 because all bivs and givs are pseudos, and hence must be dead after a
112 return, so the presense of a return does not affect any of the
113 optimizations that use this info. It is simpler to just not include return
114 instructions on this list. */
118 /* Indexed by loop number, counts the number of LABEL_REFs on
119 loop_number_exit_labels for this loop and all loops nested inside it. */
123 /* Nonzero if there is a subroutine call in the current loop. */
127 /* Nonzero if there is a volatile memory reference in the current
128 loop. */
132 /* Nonzero if there is a tablejump in the current loop. */
136 /* Added loop_continue which is the NOTE_INSN_LOOP_CONT of the
137 current loop. A continue statement will generate a branch to
138 NEXT_INSN (loop_continue). */
142 /* Indexed by register number, contains the number of times the reg
143 is set during the loop being scanned.
144 During code motion, a negative value indicates a reg that has been
145 made a candidate; in particular -2 means that it is an candidate that
146 we know is equal to a constant and -1 means that it is an candidate
147 not known equal to a constant.
148 After code motion, regs moved have 0 (which is accurate now)
149 while the failed candidates have the original number of times set.
151 Therefore, at all times, == 0 indicates an invariant register;
152 < 0 a conditionally invariant one. */
156 /* Original value of set_in_loop; same except that this value
157 is not set negative for a reg whose sets have been made candidates
158 and not set to 0 for a reg that is moved. */
162 /* Index by register number, 1 indicates that the register
163 cannot be moved or strength reduced. */
167 /* Contains the insn in which a register was used if it was used
168 exactly once; contains const0_rtx if it was used more than once. */
172 /* Nonzero means reg N has already been moved out of one loop.
173 This reduces the desire to move it out of another. */
177 /* List of MEMs that are stored in this loop. */
181 /* The insn where the first of these was found. */
190 /* Array of MEMs that are used (read or written) in this loop, but
191 cannot be aliased by anything in this loop, except perhaps
192 themselves. In other words, if loop_mems[i] is altered during the
193 loop, it is altered by an expression that is rtx_equal_p to it. */
197 /* The index of the next available slot in LOOP_MEMS. */
201 /* The number of elements allocated in LOOP_MEMs. */
205 /* Nonzero if we don't know what MEMs were changed in the current loop.
206 This happens if the loop contains a call (in which case `loop_has_call'
207 will also be set) or if we store into more than NUM_STORES MEMs. */
211 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
214 /* Count of memory write instructions discovered in the loop. */
217 /* Number of loops contained within the current one, including itself. */
220 /* Bound on pseudo register number before loop optimization.
221 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
224 /* This obstack is used in product_cheap_p to allocate its rtl. It
225 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
226 If we used the same obstack that it did, we would be deallocating
227 that array. */
231 /* This is where the pointer to the obstack being used for RTL is stored. */
235 #define obstack_chunk_alloc xmalloc
236 #define obstack_chunk_free free
237 \f
238 /* During the analysis of a loop, a chain of `struct movable's
239 is made to record all the movable insns found.
240 Then the entire chain can be scanned to decide which to move. */
242 struct movable
243 {
248 of any registers used within the LIBCALL. */
250 that must be moved with this one. */
253 may be adjusted when matching movables
254 that load the same value are found. */
256 including other movables that force this
257 or match this one. */
261 /* If PARTIAL is 1, GLOBAL means something different:
262 that the reg is live outside the range from where it is set
263 to the following label. */
267 In particular, moving it does not make it
268 invariant. */
270 load SRC, rather than copying INSN. */
272 first insn of a consecutive sets group. */
275 that we should avoid changing when clearing
276 the rest of the reg. */
280 };
286 /* Forward declarations. */
302 #if 0
304 #endif
322 static void record_giv PROTO((struct induction *, rtx, rtx, rtx, rtx, rtx, int, enum g_types, int, rtx *, rtx, rtx));
350 rtx r;
355 rtx r1;
356 rtx r2;
359 /* Nonzero iff INSN is between START and END, inclusive. */
360 #define INSN_IN_RANGE_P(INSN, START, END) \
361 (INSN_UID (INSN) < max_uid_for_loop \
362 && INSN_LUID (INSN) >= INSN_LUID (START) \
363 && INSN_LUID (INSN) <= INSN_LUID (END))
365 #ifdef HAVE_decrement_and_branch_on_count
366 /* Test whether BCT applicable and safe. */
369 /* Auxiliary function that inserts the BCT pattern into the loop. */
373 /* Indirect_jump_in_function is computed once per function. */
381 \f
382 /* Relative gain of eliminating various kinds of operations. */
384 #if 0
387 #endif
389 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
390 copy the value of the strength reduced giv to its original register. */
393 /* Cost of using a register, to normalize the benefits of a giv. */
397 void
399 {
405 #ifdef ADDRESS_COST
407 #else
409 #endif
411 /* We multiply by 2 to reconcile the difference in scale between
412 these two ways of computing costs. Otherwise the cost of a copy
413 will be far less than the cost of an add. */
417 /* Free the objects we just allocated. */
420 /* Initialize the obstack used for rtl in product_cheap_p. */
422 }
423 \f
424 /* Compute the mapping from uids to luids.
425 LUIDs are numbers assigned to insns, like uids,
426 except that luids increase monotonically through the code.
427 Start at insn START and stop just before END. Assign LUIDs
428 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
429 static int
433 {
435 rtx insn;
438 {
441 /* Don't assign luids to line-number NOTEs, so that the distance in
442 luids between two insns is not affected by -g. */
446 else
447 /* Give a line number note the same luid as preceding insn. */
449 }
451 }
452 \f
453 /* Entry point of this file. Perform loop optimization
454 on the current function. F is the first insn of the function
455 and DUMPFILE is a stream for output of a trace of actions taken
456 (or 0 if none should be output). */
458 void
460 /* f is the first instruction of a chain of insns for one function */
461 rtx f;
464 {
479 /* Count the number of loops. */
483 {
486 max_loop_num++;
487 }
489 /* Don't waste time if no loops. */
493 /* Get size to use for tables indexed by uids.
494 Leave some space for labels allocated by find_and_verify_loops. */
503 /* Allocate tables for recording each loop. We set each entry, so they need
504 not be zeroed. */
514 #ifdef HAVE_decrement_and_branch_on_count
515 /* Allocate for BCT optimization */
520 /* Find and process each loop.
521 First, find them, and record them in order of their beginnings. */
524 /* Now find all register lifetimes. This must be done after
525 find_and_verify_loops, because it might reorder the insns in the
526 function. */
529 /* This must occur after reg_scan so that registers created by gcse
530 will have entries in the register tables.
532 We could have added a call to reg_scan after gcse_main in toplev.c,
533 but moving this call to init_alias_analysis is more efficient. */
536 /* See if we went too far. Note that get_max_uid already returns
537 one more that the maximum uid of all insn. */
540 /* Now reset it to the actual size we need. See above. */
543 /* find_and_verify_loops has already called compute_luids, but it might
544 have rearranged code afterwards, so we need to recompute the luids now. */
547 /* Don't leave gaps in uid_luid for insns that have been
548 deleted. It is possible that the first or last insn
549 using some register has been deleted by cross-jumping.
550 Make sure that uid_luid for that former insn's uid
551 points to the general area where that insn used to be. */
553 {
557 }
562 /* Create a mapping from loops to BLOCK tree nodes. */
566 /* Determine if the function has indirect jump. On some systems
567 this prevents low overhead loop instructions from being used. */
570 /* Now scan the loops, last ones first, since this means inner ones are done
571 before outer ones. */
577 /* If debugging and unrolling loops, we must replicate the tree nodes
578 corresponding to the blocks inside the loop, so that the original one
579 to one mapping will remain. */
584 }
585 \f
586 /* Returns the next insn, in execution order, after INSN. START and
587 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
588 respectively. LOOP_TOP, if non-NULL, is the top of the loop in the
589 insn-stream; it is used with loops that are entered near the
590 bottom. */
592 static rtx
594 rtx insn;
595 rtx start;
596 rtx end;
597 rtx loop_top;
598 {
602 {
604 /* Go to the top of the loop, and continue there. */
606 else
607 /* We're done. */
609 }
612 /* We're done. */
616 }
618 /* Optimize one loop whose start is LOOP_START and end is END.
619 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
620 NOTE_INSN_LOOP_END.
621 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
623 /* ??? Could also move memory writes out of loops if the destination address
624 is invariant, the source is invariant, the memory write is not volatile,
625 and if we can prove that no read inside the loop can read this address
626 before the write occurs. If there is a read of this address after the
627 write, then we can also mark the memory read as invariant. */
629 static void
633 {
635 rtx p;
636 /* 1 if we are scanning insns that could be executed zero times. */
638 /* 1 if we are scanning insns that might never be executed
639 due to a subroutine call which might exit before they are reached. */
641 /* For a rotated loop that is entered near the bottom,
642 this is the label at the top. Otherwise it is zero. */
644 /* Jump insn that enters the loop, or 0 if control drops in. */
646 /* Place in the loop where control enters. */
647 rtx scan_start;
648 /* Number of insns in the loop. */
652 rtx temp;
653 /* The SET from an insn, if it is the only SET in the insn. */
655 /* Chain describing insns movable in current loop. */
657 /* Last element in `movables' -- so we can add elements at the end. */
659 /* Ratio of extra register life span we can justify
660 for saving an instruction. More if loop doesn't call subroutines
661 since in that case saving an insn makes more difference
662 and more registers are available. */
664 /* Nonzero if we are scanning instructions in a sub-loop. */
668 /* Determine whether this loop starts with a jump down to a test at
669 the end. This will occur for a small number of loops with a test
670 that is too complex to duplicate in front of the loop.
672 We search for the first insn or label in the loop, skipping NOTEs.
673 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
674 (because we might have a loop executed only once that contains a
675 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
676 (in case we have a degenerate loop).
678 Note that if we mistakenly think that a loop is entered at the top
679 when, in fact, it is entered at the exit test, the only effect will be
680 slightly poorer optimization. Making the opposite error can generate
681 incorrect code. Since very few loops now start with a jump to the
682 exit test, the code here to detect that case is very conservative. */
685 p != end
691 ;
695 /* Set up variables describing this loop. */
699 /* If loop has a jump before the first label,
700 the true entry is the target of that jump.
701 Start scan from there.
702 But record in LOOP_TOP the place where the end-test jumps
703 back to so we can scan that after the end of the loop. */
705 {
708 /* Loop entry must be unconditional jump (and not a RETURN) */
711 /* Check to see whether the jump actually
712 jumps out of the loop (meaning it's no loop).
713 This case can happen for things like
714 do {..} while (0). If this label was generated previously
715 by loop, we can't tell anything about it and have to reject
716 the loop. */
718 {
721 }
722 }
724 /* If SCAN_START was an insn created by loop, we don't know its luid
725 as required by loop_reg_used_before_p. So skip such loops. (This
726 test may never be true, but it's best to play it safe.)
728 Also, skip loops where we do not start scanning at a label. This
729 test also rejects loops starting with a JUMP_INSN that failed the
730 test above. */
734 {
739 }
741 /* Count number of times each reg is set during this loop.
742 Set VARRAY_CHAR (may_not_optimize, I) if it is not safe to move out
743 the setting of register I. Set VARRAY_RTX (reg_single_usage, I). */
745 /* Allocate extra space for REGS that might be created by
746 load_mems. We allocate a little extra slop as well, in the hopes
747 that even after the moving of movables creates some new registers
748 we won't have to reallocate these arrays. However, we do grow
749 the arrays, if necessary, in load_mems_recount_loop_regs_set. */
760 {
763 }
765 #ifdef AVOID_CCMODE_COPIES
766 /* Don't try to move insns which set CC registers if we should not
767 create CCmode register copies. */
771 #endif
777 {
783 }
785 /* Scan through the loop finding insns that are safe to move.
786 Set set_in_loop negative for the reg being set, so that
787 this reg will be considered invariant for subsequent insns.
788 We consider whether subsequent insns use the reg
789 in deciding whether it is worth actually moving.
791 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
792 and therefore it is possible that the insns we are scanning
793 would never be executed. At such times, we must make sure
794 that it is safe to execute the insn once instead of zero times.
795 When MAYBE_NEVER is 0, all insns will be executed at least once
796 so that is not a problem. */
801 {
813 {
820 /* Figure out what to use as a source of this insn. If a REG_EQUIV
821 note is given or if a REG_EQUAL note with a constant operand is
822 specified, use it as the source and mark that we should move
823 this insn by calling emit_move_insn rather that duplicating the
824 insn.
826 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
827 is present. */
831 else
832 {
837 {
839 /* A libcall block can use regs that don't appear in
840 the equivalent expression. To move the libcall,
841 we must move those regs too. */
843 }
844 }
846 /* Don't try to optimize a register that was made
847 by loop-optimization for an inner loop.
848 We don't know its life-span, so we can't compute the benefit. */
850 ;
852 than the one where it is set (meaning that
853 something after this point in the loop might
854 depend on its value before the set). */
856 /* And the set is not guaranteed to be executed one
857 the loop starts, or the value before the set is
858 needed before the set occurs...
860 ??? Note we have quadratic behaviour here, mitigated
861 by the fact that the previous test will often fail for
862 large loops. Rather than re-scanning the entire loop
863 each time for register usage, we should build tables
864 of the register usage and use them here instead. */
865 && (maybe_never
868 /* It is unsafe to move the set.
870 This code used to consider it OK to move a set of a variable
871 which was not created by the user and not used in an exit test.
872 That behavior is incorrect and was removed. */
873 ;
879 || (tem1
880 = consec_sets_invariant_p
883 p)))
884 /* If the insn can cause a trap (such as divide by zero),
885 can't move it unless it's guaranteed to be executed
886 once loop is entered. Even a function call might
887 prevent the trap insn from being reached
888 (since it might exit!) */
891 {
895 /* A potential lossage is where we have a case where two insns
896 can be combined as long as they are both in the loop, but
897 we move one of them outside the loop. For large loops,
898 this can lose. The most common case of this is the address
899 of a function being called.
901 Therefore, if this register is marked as being used exactly
902 once if we are in a loop with calls (a "large loop"), see if
903 we can replace the usage of this register with the source
904 of this SET. If we can, delete this insn.
906 Don't do this if P has a REG_RETVAL note or if we have
907 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
918 && (! SMALL_REGISTER_CLASSES
921 /* This test is not redundant; SET_SRC (set) might be
922 a call-clobbered register and the life of REGNO
923 might span a call. */
925 VARRAY_RTX
929 VARRAY_RTX
931 {
932 /* Replace any usage in a REG_EQUAL note. Must copy the
933 new source, so that we don't get rtx sharing between the
934 SET_SOURCE and REG_NOTES of insn p. */
945 }
964 /* Set M->cond if either invariant_p or consec_sets_invariant_p
965 returned 2 (only conditionally invariant). */
976 /* Add M to the end of the chain MOVABLES. */
979 else
984 {
985 /* It is possible for the first instruction to have a
986 REG_EQUAL note but a non-invariant SET_SRC, so we must
987 remember the status of the first instruction in case
988 the last instruction doesn't have a REG_EQUAL note. */
991 /* Skip this insn, not checking REG_LIBCALL notes. */
993 /* Skip the consecutive insns, if there are any. */
995 /* Back up to the last insn of the consecutive group. */
998 /* We must now reset m->move_insn, m->is_equiv, and possibly
999 m->set_src to correspond to the effects of all the
1000 insns. */
1004 else
1005 {
1009 else
1012 }
1014 }
1015 }
1016 /* If this register is always set within a STRICT_LOW_PART
1017 or set to zero, then its high bytes are constant.
1018 So clear them outside the loop and within the loop
1019 just load the low bytes.
1020 We must check that the machine has an instruction to do so.
1021 Also, if the value loaded into the register
1022 depends on the same register, this cannot be done. */
1032 {
1035 {
1049 /* If the insn may not be executed on some cycles,
1050 we can't clear the whole reg; clear just high part.
1051 Not even if the reg is used only within this loop.
1052 Consider this:
1053 while (1)
1054 while (s != t) {
1055 if (foo ()) x = *s;
1056 use (x);
1057 }
1058 Clearing x before the inner loop could clobber a value
1059 being saved from the last time around the outer loop.
1060 However, if the reg is not used outside this loop
1061 and all uses of the register are in the same
1062 basic block as the store, there is no problem.
1064 If this insn was made by loop, we don't know its
1065 INSN_LUID and hence must make a conservative
1066 assumption. */
1072 || (labels_in_range_p
1076 else
1085 /* Add M to the end of the chain MOVABLES. */
1088 else
1091 }
1092 }
1093 }
1094 /* Past a call insn, we get to insns which might not be executed
1095 because the call might exit. This matters for insns that trap.
1096 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
1097 so they don't count. */
1100 /* Past a label or a jump, we get to insns for which we
1101 can't count on whether or how many times they will be
1102 executed during each iteration. Therefore, we can
1103 only move out sets of trivial variables
1104 (those not used after the loop). */
1105 /* Similar code appears twice in strength_reduce. */
1107 /* If we enter the loop in the middle, and scan around to the
1108 beginning, don't set maybe_never for that. This must be an
1109 unconditional jump, otherwise the code at the top of the
1110 loop might never be executed. Unconditional jumps are
1111 followed a by barrier then loop end. */
1117 {
1118 /* At the virtual top of a converted loop, insns are again known to
1119 be executed: logically, the loop begins here even though the exit
1120 code has been duplicated. */
1124 loop_depth++;
1126 loop_depth--;
1127 }
1128 }
1130 /* If one movable subsumes another, ignore that other. */
1134 /* For each movable insn, see if the reg that it loads
1135 leads when it dies right into another conditionally movable insn.
1136 If so, record that the second insn "forces" the first one,
1137 since the second can be moved only if the first is. */
1141 /* See if there are multiple movable insns that load the same value.
1142 If there are, make all but the first point at the first one
1143 through the `match' field, and add the priorities of them
1144 all together as the priority of the first. */
1148 /* Now consider each movable insn to decide whether it is worth moving.
1149 Store 0 in set_in_loop for each reg that is moved.
1151 Generally this increases code size, so do not move moveables when
1152 optimizing for code size. */
1158 /* Now candidates that still are negative are those not moved.
1159 Change set_in_loop to indicate that those are not actually invariant. */
1164 /* Now that we've moved some things out of the loop, we might be able to
1165 hoist even more memory references. */
1170 {
1174 }
1180 }
1181 \f
1182 /* Add elements to *OUTPUT to record all the pseudo-regs
1183 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1185 void
1189 {
1197 {
1215 }
1219 {
1223 {
1232 }
1233 }
1234 }
1235 \f
1236 /* Check what regs are referred to in the libcall block ending with INSN,
1237 aside from those mentioned in the equivalent value.
1238 If there are none, return 0.
1239 If there are one or more, return an EXPR_LIST containing all of them. */
1241 rtx
1244 {
1249 /* First, find all the regs used in the libcall block
1250 that are not mentioned as inputs to the result. */
1253 {
1258 }
1261 }
1262 \f
1263 /* Return 1 if all uses of REG
1264 are between INSN and the end of the basic block. */
1266 static int
1269 {
1271 rtx p;
1276 /* Search this basic block for the already recorded last use of the reg. */
1278 {
1280 {
1286 /* Ordinary insn: if this is the last use, we win. */
1292 /* Jump insn: if this is the last use, we win. */
1295 /* Otherwise, it's the end of the basic block, so we lose. */
1300 /* It's the end of the basic block, so we lose. */
1305 }
1306 }
1308 /* The "last use" doesn't follow the "first use"?? */
1310 }
1311 \f
1312 /* Compute the benefit of eliminating the insns in the block whose
1313 last insn is LAST. This may be a group of insns used to compute a
1314 value directly or can contain a library call. */
1316 static int
1318 rtx last;
1319 {
1320 rtx insn;
1325 {
1328 routine. */
1332 benefit++;
1333 }
1336 }
1337 \f
1338 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1340 static rtx
1342 rtx insn;
1344 {
1346 {
1347 rtx temp;
1349 /* If first insn of libcall sequence, skip to end. */
1350 /* Do this at start of loop, since INSN is guaranteed to
1351 be an insn here. */
1358 }
1361 }
1363 /* Ignore any movable whose insn falls within a libcall
1364 which is part of another movable.
1365 We make use of the fact that the movable for the libcall value
1366 was made later and so appears later on the chain. */
1368 static void
1371 {
1375 {
1376 /* Is this a movable for the value of a libcall? */
1379 {
1380 rtx insn;
1381 /* Check for earlier movables inside that range,
1382 and mark them invalid. We cannot use LUIDs here because
1383 insns created by loop.c for prior loops don't have LUIDs.
1384 Rather than reject all such insns from movables, we just
1385 explicitly check each insn in the libcall (since invariant
1386 libcalls aren't that common). */
1391 }
1392 }
1393 }
1395 /* For each movable insn, see if the reg that it loads
1396 leads when it dies right into another conditionally movable insn.
1397 If so, record that the second insn "forces" the first one,
1398 since the second can be moved only if the first is. */
1400 static void
1403 {
1406 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1408 {
1411 /* ??? Could this be a bug? What if CSE caused the
1412 register of M1 to be used after this insn?
1413 Since CSE does not update regno_last_uid,
1414 this insn M->insn might not be where it dies.
1415 But very likely this doesn't matter; what matters is
1416 that M's reg is computed from M1's reg. */
1421 /* If m->consec, m->set_src isn't valid. */
1425 /* Increase the priority of the moving the first insn
1426 since it permits the second to be moved as well. */
1428 {
1432 }
1433 }
1434 }
1435 \f
1436 /* Find invariant expressions that are equal and can be combined into
1437 one register. */
1439 static void
1443 {
1448 /* Regs that are set more than once are not allowed to match
1449 or be matched. I'm no longer sure why not. */
1450 /* Perhaps testing m->consec_sets would be more appropriate here? */
1454 {
1461 /* We want later insns to match the first one. Don't make the first
1462 one match any later ones. So start this loop at m->next. */
1465 /* A reg used outside the loop mustn't be eliminated. */
1467 /* A reg used for zero-extending mustn't be eliminated. */
1470 ||
1471 (
1472 /* Can combine regs with different modes loaded from the
1473 same constant only if the modes are the same or
1474 if both are integer modes with M wider or the same
1475 width as M1. The check for integer is redundant, but
1476 safe, since the only case of differing destination
1477 modes with equal sources is when both sources are
1478 VOIDmode, i.e., CONST_INT. */
1484 /* See if the source of M1 says it matches M. */
1488 movables))))
1491 {
1497 }
1498 }
1500 /* Now combine the regs used for zero-extension.
1501 This can be done for those not marked `global'
1502 provided their lives don't overlap. */
1506 {
1509 /* Combine all the registers for extension from mode MODE.
1510 Don't combine any that are used outside this loop. */
1514 {
1520 {
1521 /* First one: don't check for overlap, just record it. */
1524 }
1526 /* Make sure they extend to the same mode.
1527 (Almost always true.) */
1531 /* We already have one: check for overlap with those
1532 already combined together. */
1539 /* No overlap: we can combine this with the others. */
1545 overlap: ;
1546 }
1547 }
1548 }
1549 \f
1550 /* Return 1 if regs X and Y will become the same if moved. */
1552 static int
1556 {
1573 }
1575 /* Return 1 if X and Y are identical-looking rtx's.
1576 This is the Lisp function EQUAL for rtx arguments.
1578 If two registers are matching movables or a movable register and an
1579 equivalent constant, consider them equal. */
1581 static int
1585 {
1599 /* If we have a register and a constant, they may sometimes be
1600 equal. */
1603 {
1608 }
1611 {
1616 }
1618 /* Otherwise, rtx's of different codes cannot be equal. */
1622 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1623 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1628 /* These three types of rtx's can be compared nonrecursively. */
1637 /* Compare the elements. If any pair of corresponding elements
1638 fail to match, return 0 for the whole things. */
1642 {
1644 {
1656 /* Two vectors must have the same length. */
1660 /* And the corresponding elements must match. */
1677 /* These are just backpointers, so they don't matter. */
1683 /* It is believed that rtx's at this level will never
1684 contain anything but integers and other rtx's,
1685 except for within LABEL_REFs and SYMBOL_REFs. */
1688 }
1689 }
1691 }
1692 \f
1693 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1694 insns in INSNS which use thet reference. */
1696 static void
1698 rtx x;
1699 rtx insns;
1700 {
1704 rtx insn;
1707 {
1708 /* This code used to ignore labels that referred to dispatch tables to
1709 avoid flow generating (slighly) worse code.
1711 We no longer ignore such label references (see LABEL_REF handling in
1712 mark_jump_label for additional information). */
1717 }
1721 {
1727 }
1728 }
1729 \f
1730 /* Scan MOVABLES, and move the insns that deserve to be moved.
1731 If two matching movables are combined, replace one reg with the
1732 other throughout. */
1734 static void
1739 rtx loop_start;
1740 rtx end;
1742 {
1746 /* Map of pseudo-register replacements to handle combining
1747 when we move several insns that load the same value
1748 into different pseudo-registers. */
1758 {
1759 /* Describe this movable insn. */
1762 {
1783 }
1785 /* Count movables. Value used in heuristics in strength_reduce. */
1786 num_movables++;
1788 /* Ignore the insn if it's already done (it matched something else).
1789 Otherwise, see if it is now safe to move. */
1801 {
1806 /* We have an insn that is safe to move.
1807 Compute its desirability. */
1818 /* An insn MUST be moved if we already moved something else
1819 which is safe only if this one is moved too: that is,
1820 if already_moved[REGNO] is nonzero. */
1822 /* An insn is desirable to move if the new lifetime of the
1823 register is no more than THRESHOLD times the old lifetime.
1824 If it's not desirable, it means the loop is so big
1825 that moving won't speed things up much,
1826 and it is liable to make register usage worse. */
1828 /* It is also desirable to move if it can be moved at no
1829 extra cost because something else was already moved. */
1832 || flag_move_all_movables
1837 {
1840 rtx first;
1842 /* Now move the insns that set the reg. */
1845 {
1848 /* Find the end of this chain of matching regs.
1849 Thus, we load each reg in the chain from that one reg.
1850 And that reg is loaded with 0 directly,
1851 since it has ->match == 0. */
1857 /* Mark the moved, invariant reg as being allowed to
1858 share a hard reg with the other matching invariant. */
1862 regs_may_share
1865 regs_may_share));
1873 }
1874 /* If we are to re-generate the item being moved with a
1875 new move insn, first delete what we have and then emit
1876 the move insn before the loop. */
1878 {
1882 {
1883 /* If this is the first insn of a library call sequence,
1884 skip to the end. */
1889 /* If this is the last insn of a libcall sequence, then
1890 delete every insn in the sequence except the last.
1891 The last insn is handled in the normal manner. */
1894 {
1898 }
1903 /* simplify_giv_expr expects that it can walk the insns
1904 at m->insn forwards and see this old sequence we are
1905 tossing here. delete_insn does preserve the next
1906 pointers, but when we skip over a NOTE we must fix
1907 it up. Otherwise that code walks into the non-deleted
1908 insn stream. */
1911 }
1929 /* The more regs we move, the less we like moving them. */
1931 }
1932 else
1933 {
1935 {
1938 /* If first insn of libcall sequence, skip to end. */
1939 /* Do this at start of loop, since p is guaranteed to
1940 be an insn here. */
1945 /* If last insn of libcall sequence, move all
1946 insns except the last before the loop. The last
1947 insn is handled in the normal manner. */
1950 {
1958 {
1959 rtx body;
1960 rtx n;
1961 rtx next;
1968 /* Find the next insn after TEMP,
1969 not counting USE or NOTE insns. */
1977 /* If that is the call, this may be the insn
1978 that loads the function address.
1980 Extract the function address from the insn
1981 that loads it into a register.
1982 If this insn was cse'd, we get incorrect code.
1984 So emit a new move insn that copies the
1985 function address into the register that the
1986 call insn will use. flow.c will delete any
1987 redundant stores that we have created. */
1992 NULL_RTX)))
1993 {
1999 }
2000 /* We have the call insn.
2001 If it uses the register we suspect it might,
2002 load it with the correct address directly. */
2007 fn_address),
2008 fn_address_insn);
2011 {
2013 /* Because the USAGE information potentially
2014 contains objects other than hard registers
2015 we need to copy it. */
2019 }
2020 else
2028 }
2031 }
2033 {
2034 /* P sets REG to zero; but we should clear only
2035 the bits that are not covered by the mode
2036 m->savemode. */
2038 rtx sequence;
2039 rtx tem;
2042 tem = expand_binop
2055 }
2057 {
2059 /* Because the USAGE information potentially
2060 contains objects other than hard registers
2061 we need to copy it. */
2065 }
2067 {
2068 /* The SET_SRC might not be invariant, so we must
2069 use the REG_EQUAL note. */
2083 }
2084 else
2088 {
2091 /* If there is a REG_EQUAL note present whose value
2092 is not loop invariant, then delete it, since it
2093 may cause problems with later optimization passes.
2094 It is possible for cse to create such notes
2095 like this as a result of record_jump_cond. */
2100 }
2109 /* If library call, now fix the REG_NOTES that contain
2110 insn pointers, namely REG_LIBCALL on FIRST
2111 and REG_RETVAL on I1. */
2113 {
2117 }
2123 /* simplify_giv_expr expects that it can walk the insns
2124 at m->insn forwards and see this old sequence we are
2125 tossing here. delete_insn does preserve the next
2126 pointers, but when we skip over a NOTE we must fix
2127 it up. Otherwise that code walks into the non-deleted
2128 insn stream. */
2131 }
2133 /* The more regs we move, the less we like moving them. */
2135 }
2137 /* Any other movable that loads the same register
2138 MUST be moved. */
2141 /* This reg has been moved out of one loop. */
2144 /* The reg set here is now invariant. */
2150 /* Change the length-of-life info for the register
2151 to say it lives at least the full length of this loop.
2152 This will help guide optimizations in outer loops. */
2155 /* This is the old insn before all the moved insns.
2156 We can't use the moved insn because it is out of range
2157 in uid_luid. Only the old insns have luids. */
2162 /* Combine with this moved insn any other matching movables. */
2167 {
2168 rtx temp;
2170 /* Schedule the reg loaded by M1
2171 for replacement so that shares the reg of M.
2172 If the modes differ (only possible in restricted
2173 circumstances, make a SUBREG. */
2176 else
2181 /* Get rid of the matching insn
2182 and prevent further processing of it. */
2185 /* if library call, delete all insn except last, which
2186 is deleted below */
2188 NULL_RTX)))
2189 {
2193 }
2196 /* Any other movable that loads the same register
2197 MUST be moved. */
2200 /* The reg merged here is now invariant,
2201 if the reg it matches is invariant. */
2204 }
2205 }
2208 }
2214 }
2219 /* Go through all the instructions in the loop, making
2220 all the register substitutions scheduled in REG_MAP. */
2224 {
2228 }
2229 }
2230 \f
2231 #if 0
2232 /* Scan X and replace the address of any MEM in it with ADDR.
2233 REG is the address that MEM should have before the replacement. */
2235 static void
2238 {
2247 {
2259 /* Short cut for very common case. */
2264 /* Short cut for very common case. */
2269 /* If this MEM uses a reg other than the one we expected,
2270 something is wrong. */
2278 }
2282 {
2286 {
2290 }
2291 }
2292 }
2293 #endif
2294 \f
2295 /* Return the number of memory refs to addresses that vary
2296 in the rtx X. */
2298 static int
2300 rtx x;
2301 {
2312 {
2329 }
2334 {
2338 {
2342 }
2343 }
2345 }
2347 \f
2348 #if 0
2349 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2350 Replace it with an instruction to load just the low bytes
2351 if the machine supports such an instruction,
2352 and insert above LOOP_START an instruction to clear the register. */
2354 static void
2357 {
2361 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2362 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2373 {
2376 /* Clear destination register before the loop. */
2378 const0_rtx),
2379 loop_start);
2381 /* Inside the loop, just load the low part. */
2383 }
2384 }
2385 #endif
2386 \f
2387 /* Scan a loop setting the variables `unknown_address_altered',
2388 `num_mem_sets', `loop_continue', `loops_enclosed', `loop_has_call',
2389 `loop_has_volatile', and `loop_has_tablejump'.
2390 Also, fill in the array `loop_mems' and the list `loop_store_mems'. */
2392 static void
2395 {
2397 rtx insn;
2399 /* The label after END. Jumping here is just like falling off the
2400 end of the loop. We use next_nonnote_insn instead of next_label
2401 as a hedge against the (pathological) case where some actual insn
2402 might end up between the two. */
2421 {
2423 {
2425 {
2427 /* Count number of loops contained in this one. */
2428 loops_enclosed++;
2429 }
2431 {
2434 {
2437 }
2438 }
2440 {
2443 }
2444 }
2446 {
2450 }
2452 {
2472 {
2474 {
2477 }
2478 else
2479 {
2481 }
2485 {
2487 {
2488 /* Something tricky. */
2491 }
2494 {
2495 /* A jump outside the current loop. */
2498 }
2499 }
2504 }
2505 }
2508 }
2510 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2512 !unknown_address_altered
2513 /* An exception thrown by a called function might land us
2514 anywhere. */
2515 && !loop_has_call
2516 /* We don't want loads for MEMs moved to a location before the
2517 one at which their stack memory becomes allocated. (Note
2518 that this is not a problem for malloc, etc., since those
2519 require actual function calls. */
2520 && !current_function_calls_alloca
2521 /* There are ways to leave the loop other than falling off the
2522 end. */
2527 }
2528 \f
2529 /* LOOP_NUMBER_CONT_DOMINATOR is now the last label between the loop start
2530 and the continue note that is a the destination of a (cond)jump after
2531 the continue note. If there is any (cond)jump between the loop start
2532 and what we have so far as LOOP_NUMBER_CONT_DOMINATOR that has a
2533 target between LOOP_DOMINATOR and the continue note, move
2534 LOOP_NUMBER_CONT_DOMINATOR forward to that label; if a jump's
2535 destination cannot be determined, clear LOOP_NUMBER_CONT_DOMINATOR. */
2537 static void
2540 {
2541 rtx insn;
2544 /* This can happen for an empty loop, e.g. in
2545 gcc.c-torture/compile/920410-2.c */
2548 {
2551 }
2555 {
2558 {
2564 {
2567 }
2569 && (label_luid
2572 }
2573 }
2574 }
2576 /* Scan the function looking for loops. Record the start and end of each loop.
2577 Also mark as invalid loops any loops that contain a setjmp or are branched
2578 to from outside the loop. */
2580 static void
2582 rtx f;
2583 {
2591 /* If there are jumps to undefined labels,
2592 treat them as jumps out of any/all loops.
2593 This also avoids writing past end of tables when there are no loops. */
2596 /* Find boundaries of loops, mark which loops are contained within
2597 loops, and invalidate loops that have setjmp. */
2600 {
2603 {
2617 /* In this case, we must invalidate our current loop and any
2618 enclosing loop. */
2620 {
2626 }
2643 }
2644 /* If for any loop, this is a jump insn between the NOTE_INSN_LOOP_CONT
2645 and NOTE_INSN_LOOP_END notes, update loop_number_loop_dominator. */
2649 {
2657 do
2658 {
2659 /* First see if we care about this loop. */
2662 {
2663 /* If the jump destination is not known, invalidate
2664 loop_number_const_dominator. */
2667 else
2668 /* Check if the destination is between loop start and
2669 cont. */
2674 /* And if there is no later destination already
2675 recorded. */
2681 }
2683 }
2685 }
2687 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2688 enclosing loop, but this doesn't matter. */
2690 }
2692 /* Any loop containing a label used in an initializer must be invalidated,
2693 because it can be jumped into from anywhere. */
2696 {
2703 }
2705 /* Any loop containing a label used for an exception handler must be
2706 invalidated, because it can be jumped into from anywhere. */
2709 {
2716 }
2718 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2719 loop that it is not contained within, that loop is marked invalid.
2720 If any INSN or CALL_INSN uses a label's address, then the loop containing
2721 that label is marked invalid, because it could be jumped into from
2722 anywhere.
2724 Also look for blocks of code ending in an unconditional branch that
2725 exits the loop. If such a block is surrounded by a conditional
2726 branch around the block, move the block elsewhere (see below) and
2727 invert the jump to point to the code block. This may eliminate a
2728 label in our loop and will simplify processing by both us and a
2729 possible second cse pass. */
2733 {
2737 {
2740 {
2747 }
2748 }
2755 /* See if this is an unconditional branch outside the loop. */
2762 {
2763 rtx p;
2768 /* Go backwards until we reach the start of the loop, a label,
2769 or a JUMP_INSN. */
2776 ;
2778 /* Check for the case where we have a jump to an inner nested
2779 loop, and do not perform the optimization in that case. */
2782 {
2785 {
2790 }
2791 }
2793 /* Make sure that the target of P is within the current loop. */
2799 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2800 we have a block of code to try to move.
2802 We look backward and then forward from the target of INSN
2803 to find a BARRIER at the same loop depth as the target.
2804 If we find such a BARRIER, we make a new label for the start
2805 of the block, invert the jump in P and point it to that label,
2806 and move the block of code to the spot we found. */
2811 /* Just ignore jumps to labels that were never emitted.
2812 These always indicate compilation errors. */
2817 {
2818 rtx target
2821 rtx loc;
2835 {
2839 /* Ensure our label doesn't go away. */
2842 /* Verify that uid_loop_num is large enough and that
2843 we can invert P. */
2845 {
2848 /* If no suitable BARRIER was found, create a suitable
2849 one before TARGET. Since TARGET is a fall through
2850 path, we'll need to insert an jump around our block
2851 and a add a BARRIER before TARGET.
2853 This creates an extra unconditional jump outside
2854 the loop. However, the benefits of removing rarely
2855 executed instructions from inside the loop usually
2856 outweighs the cost of the extra unconditional jump
2857 outside the loop. */
2859 {
2860 rtx temp;
2867 }
2869 /* Include the BARRIER after INSN and copy the
2870 block after LOC. */
2874 /* All those insns are now in TARGET_LOOP_NUM. */
2879 /* The label jumped to by INSN is no longer a loop exit.
2880 Unless INSN does not have a label (e.g., it is a
2881 RETURN insn), search loop_number_exit_labels to find
2882 its label_ref, and remove it. Also turn off
2883 LABEL_OUTSIDE_LOOP_P bit. */
2885 {
2892 {
2896 else
2900 }
2907 /* If we didn't find it, then something is wrong. */
2910 }
2912 /* P is now a jump outside the loop, so it must be put
2913 in loop_number_exit_labels, and marked as such.
2914 The easiest way to do this is to just call
2915 mark_loop_jump again for P. */
2918 /* If INSN now jumps to the insn after it,
2919 delete INSN. */
2924 }
2926 /* Continue the loop after where the conditional
2927 branch used to jump, since the only branch insn
2928 in the block (if it still remains) is an inter-loop
2929 branch and hence needs no processing. */
2935 /* This loop will be continued with NEXT_INSN (insn). */
2937 }
2938 }
2939 }
2940 }
2941 }
2943 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2944 loops it is contained in, mark the target loop invalid.
2946 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2948 static void
2950 rtx x;
2952 {
2958 {
2970 /* There could be a label reference in here. */
2982 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2994 /* Link together all labels that branch outside the loop. This
2995 is used by final_[bg]iv_value and the loop unrolling code. Also
2996 mark this LABEL_REF so we know that this branch should predict
2997 false. */
2999 /* A check to make sure the label is not in an inner nested loop,
3000 since this does not count as a loop exit. */
3002 {
3007 }
3008 else
3012 {
3021 }
3023 /* If this is inside a loop, but not in the current loop or one enclosed
3024 by it, it invalidates at least one loop. */
3029 /* We must invalidate every nested loop containing the target of this
3030 label, except those that also contain the jump insn. */
3033 {
3034 /* Stop when we reach a loop that also contains the jump insn. */
3040 /* If we get here, we know we need to invalidate a loop. */
3047 }
3051 /* If this is not setting pc, ignore. */
3073 /* Strictly speaking this is not a jump into the loop, only a possible
3074 jump out of the loop. However, we have no way to link the destination
3075 of this jump onto the list of exit labels. To be safe we mark this
3076 loop and any containing loops as invalid. */
3078 {
3081 {
3087 }
3088 }
3090 }
3091 }
3092 \f
3093 /* Return nonzero if there is a label in the range from
3094 insn INSN to and including the insn whose luid is END
3095 INSN must have an assigned luid (i.e., it must not have
3096 been previously created by loop.c). */
3098 static int
3100 rtx insn;
3102 {
3104 {
3108 }
3111 }
3113 /* Record that a memory reference X is being set. */
3115 static void
3117 rtx x;
3118 rtx y ATTRIBUTE_UNUSED;
3119 {
3123 /* Count number of memory writes.
3124 This affects heuristics in strength_reduce. */
3125 num_mem_sets++;
3127 /* BLKmode MEM means all memory is clobbered. */
3135 }
3136 \f
3137 /* Return nonzero if the rtx X is invariant over the current loop.
3139 The value is 2 if we refer to something only conditionally invariant.
3141 If `unknown_address_altered' is nonzero, no memory ref is invariant.
3142 Otherwise, a memory ref is invariant if it does not conflict with
3143 anything stored in `loop_store_mems'. */
3145 int
3148 {
3153 rtx mem_list_entry;
3159 {
3167 /* A LABEL_REF is normally invariant, however, if we are unrolling
3168 loops, and this label is inside the loop, then it isn't invariant.
3169 This is because each unrolled copy of the loop body will have
3170 a copy of this label. If this was invariant, then an insn loading
3171 the address of this label into a register might get moved outside
3172 the loop, and then each loop body would end up using the same label.
3174 We don't know the loop bounds here though, so just fail for all
3175 labels. */
3178 else
3187 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3188 since the reg might be set by initialization within the loop. */
3205 /* Volatile memory references must be rejected. Do this before
3206 checking for read-only items, so that volatile read-only items
3207 will be rejected also. */
3211 /* Read-only items (such as constants in a constant pool) are
3212 invariant if their address is. */
3216 /* If we had a subroutine call, any location in memory could have been
3217 clobbered. */
3221 /* See if there is any dependence between a store and this load. */
3224 {
3229 }
3231 /* It's not invalidated by a store in memory
3232 but we must still verify the address is invariant. */
3236 /* Don't mess with insns declared volatile. */
3243 }
3247 {
3249 {
3255 }
3257 {
3260 {
3266 }
3268 }
3269 }
3272 }
3274 \f
3275 /* Return nonzero if all the insns in the loop that set REG
3276 are INSN and the immediately following insns,
3277 and if each of those insns sets REG in an invariant way
3278 (not counting uses of REG in them).
3280 The value is 2 if some of these insns are only conditionally invariant.
3282 We assume that INSN itself is the first set of REG
3283 and that its source is invariant. */
3285 static int
3289 {
3292 rtx temp;
3293 /* Number of sets we have to insist on finding after INSN. */
3299 /* If N_SETS hit the limit, we can't rely on its value. */
3306 {
3308 rtx set;
3313 /* If library call, skip to end of it. */
3322 {
3327 {
3328 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3329 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3330 notes are OK. */
3336 }
3337 }
3339 count--;
3341 {
3344 }
3345 }
3348 /* If invariant_p ever returned 2, we return 2. */
3350 }
3352 #if 0
3353 /* I don't think this condition is sufficient to allow INSN
3354 to be moved, so we no longer test it. */
3356 /* Return 1 if all insns in the basic block of INSN and following INSN
3357 that set REG are invariant according to TABLE. */
3359 static int
3363 {
3368 {
3377 {
3380 }
3381 }
3382 }
3384 \f
3385 /* Look at all uses (not sets) of registers in X. For each, if it is
3386 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3387 a different insn, set USAGE[REGNO] to const0_rtx. */
3389 static void
3391 rtx insn;
3392 rtx x;
3393 varray_type usage;
3394 {
3406 {
3407 /* Don't count SET_DEST if it is a REG; otherwise count things
3408 in SET_DEST because if a register is partially modified, it won't
3409 show up as a potential movable so we don't care how USAGE is set
3410 for it. */
3414 }
3415 else
3417 {
3423 }
3424 }
3425 \f
3426 /* Count and record any set in X which is contained in INSN. Update
3427 MAY_NOT_MOVE and LAST_SET for any register set in X. */
3429 static void
3432 varray_type may_not_move;
3434 {
3436 /* Don't move a reg that has an explicit clobber.
3437 It's not worth the pain to try to do it correctly. */
3441 {
3449 {
3451 /* If this is the first setting of this reg
3452 in current basic block, and it was set before,
3453 it must be set in two basic blocks, so it cannot
3454 be moved out of the loop. */
3458 /* If this is not first setting in current basic block,
3459 see if reg was used in between previous one and this.
3460 If so, neither one can be moved. */
3467 }
3468 }
3469 }
3471 /* Increment SET_IN_LOOP at the index of each register
3472 that is modified by an insn between FROM and TO.
3473 If the value of an element of SET_IN_LOOP becomes 127 or more,
3474 stop incrementing it, to avoid overflow.
3476 Store in SINGLE_USAGE[I] the single insn in which register I is
3477 used, if it is only used once. Otherwise, it is set to 0 (for no
3478 uses) or const0_rtx for more than one use. This parameter may be zero,
3479 in which case this processing is not done.
3481 Store in *COUNT_PTR the number of actual instruction
3482 in the loop. We use this to decide what is worth moving out. */
3484 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
3485 In that case, it is the insn that last set reg n. */
3487 static void
3490 varray_type may_not_move;
3491 varray_type single_usage;
3494 {
3501 {
3503 {
3506 /* Record registers that have exactly one use. */
3509 /* Include uses in REG_EQUAL notes. */
3517 {
3522 }
3523 }
3527 }
3529 }
3530 \f
3531 /* Given a loop that is bounded by LOOP_START and LOOP_END
3532 and that is entered at SCAN_START,
3533 return 1 if the register set in SET contained in insn INSN is used by
3534 any insn that precedes INSN in cyclic order starting
3535 from the loop entry point.
3537 We don't want to use INSN_LUID here because if we restrict INSN to those
3538 that have a valid INSN_LUID, it means we cannot move an invariant out
3539 from an inner loop past two loops. */
3541 static int
3544 {
3546 rtx p;
3548 /* Scan forward checking for register usage. If we hit INSN, we
3549 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3551 {
3558 }
3561 }
3562 \f
3563 /* A "basic induction variable" or biv is a pseudo reg that is set
3564 (within this loop) only by incrementing or decrementing it. */
3565 /* A "general induction variable" or giv is a pseudo reg whose
3566 value is a linear function of a biv. */
3568 /* Bivs are recognized by `basic_induction_var';
3569 Givs by `general_induction_var'. */
3571 /* Indexed by register number, indicates whether or not register is an
3572 induction variable, and if so what type. */
3574 varray_type reg_iv_type;
3576 /* Indexed by register number, contains pointer to `struct induction'
3577 if register is an induction variable. This holds general info for
3578 all induction variables. */
3580 varray_type reg_iv_info;
3582 /* Indexed by register number, contains pointer to `struct iv_class'
3583 if register is a basic induction variable. This holds info describing
3584 the class (a related group) of induction variables that the biv belongs
3585 to. */
3589 /* The head of a list which links together (via the next field)
3590 every iv class for the current loop. */
3594 /* Givs made from biv increments are always splittable for loop unrolling.
3595 Since there is no regscan info for them, we have to keep track of them
3596 separately. */
3599 /* Communication with routines called via `note_stores'. */
3603 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3607 /* ??? Unfinished optimizations, and possible future optimizations,
3608 for the strength reduction code. */
3610 /* ??? The interaction of biv elimination, and recognition of 'constant'
3611 bivs, may cause problems. */
3613 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3614 performance problems.
3616 Perhaps don't eliminate things that can be combined with an addressing
3617 mode. Find all givs that have the same biv, mult_val, and add_val;
3618 then for each giv, check to see if its only use dies in a following
3619 memory address. If so, generate a new memory address and check to see
3620 if it is valid. If it is valid, then store the modified memory address,
3621 otherwise, mark the giv as not done so that it will get its own iv. */
3623 /* ??? Could try to optimize branches when it is known that a biv is always
3624 positive. */
3626 /* ??? When replace a biv in a compare insn, we should replace with closest
3627 giv so that an optimized branch can still be recognized by the combiner,
3628 e.g. the VAX acb insn. */
3630 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3631 was rerun in loop_optimize whenever a register was added or moved.
3632 Also, some of the optimizations could be a little less conservative. */
3633 \f
3634 /* Perform strength reduction and induction variable elimination.
3636 Pseudo registers created during this function will be beyond the last
3637 valid index in several tables including n_times_set and regno_last_uid.
3638 This does not cause a problem here, because the added registers cannot be
3639 givs outside of their loop, and hence will never be reconsidered.
3640 But scan_loop must check regnos to make sure they are in bounds.
3642 SCAN_START is the first instruction in the loop, as the loop would
3643 actually be executed. END is the NOTE_INSN_LOOP_END. LOOP_TOP is
3644 the first instruction in the loop, as it is layed out in the
3645 instruction stream. LOOP_START is the NOTE_INSN_LOOP_BEG.
3646 LOOP_CONT is the NOTE_INSN_LOOP_CONT. */
3648 static void
3651 rtx scan_start;
3652 rtx end;
3653 rtx loop_top;
3655 rtx loop_start;
3656 rtx loop_end;
3657 rtx loop_cont;
3659 {
3660 rtx p;
3661 rtx set;
3662 rtx inc_val;
3663 rtx mult_val;
3664 rtx dest_reg;
3666 /* This is 1 if current insn is not executed at least once for every loop
3667 iteration. */
3669 /* This is 1 if current insn may be executed more than once for every
3670 loop iteration. */
3672 /* Temporary list pointers for traversing loop_iv_list. */
3674 /* Ratio of extra register life span we can justify
3675 for saving an instruction. More if loop doesn't call subroutines
3676 since in that case saving an insn makes more difference
3677 and more registers are available. */
3678 /* ??? could set this to last value of threshold in move_movables */
3680 /* Map of pseudo-register replacements. */
3684 rtx test;
3685 rtx end_insert_before;
3691 /* If scan_start points to the loop exit test, we have to be wary of
3692 subversive use of gotos inside expression statements. */
3706 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3707 must be put before this insn, so that they will appear in the right
3708 order (i.e. loop order).
3710 If loop_end is the end of the current function, then emit a
3711 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3712 dummy note insn. */
3715 else
3718 /* Scan through loop to find all possible bivs. */
3723 {
3727 {
3732 {
3736 {
3737 /* It is a possible basic induction variable.
3738 Create and initialize an induction structure for it. */
3746 }
3749 }
3750 }
3752 /* Past CODE_LABEL, we get to insns that may be executed multiple
3753 times. The only way we can be sure that they can't is if every
3754 jump insn between here and the end of the loop either
3755 returns, exits the loop, is a jump to a location that is still
3756 behind the label, or is a jump to the loop start. */
3759 {
3765 {
3770 {
3773 else
3777 }
3785 {
3788 }
3789 }
3790 }
3792 /* Past a jump, we get to insns for which we can't count
3793 on whether they will be executed during each iteration. */
3794 /* This code appears twice in strength_reduce. There is also similar
3795 code in scan_loop. */
3797 /* If we enter the loop in the middle, and scan around to the
3798 beginning, don't set not_every_iteration for that.
3799 This can be any kind of jump, since we want to know if insns
3800 will be executed if the loop is executed. */
3804 {
3807 /* If this is a jump outside the loop, then it also doesn't
3808 matter. Check to see if the target of this branch is on the
3809 loop_number_exits_labels list. */
3812 label;
3819 }
3822 {
3823 /* At the virtual top of a converted loop, insns are again known to
3824 be executed each iteration: logically, the loop begins here
3825 even though the exit code has been duplicated.
3827 Insns are also again known to be executed each iteration at
3828 the LOOP_CONT note. */
3834 loop_depth++;
3836 loop_depth--;
3837 }
3839 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3840 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3841 or not an insn is known to be executed each iteration of the
3842 loop, whether or not any iterations are known to occur.
3844 Therefore, if we have just passed a label and have no more labels
3845 between here and the test insn of the loop, we know these insns
3846 will be executed each iteration. */
3852 }
3854 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3855 Make a sanity check against n_times_set. */
3857 {
3859 /* Above happens if register modified by subreg, etc. */
3860 /* Make sure it is not recognized as a basic induction var: */
3862 /* If never incremented, it is invariant that we decided not to
3863 move. So leave it alone. */
3865 {
3876 }
3877 else
3878 {
3883 }
3884 }
3886 /* Exit if there are no bivs. */
3888 {
3889 /* Can still unroll the loop anyways, but indicate that there is no
3890 strength reduction info available. */
3896 }
3898 /* Find initial value for each biv by searching backwards from loop_start,
3899 halting at first label. Also record any test condition. */
3903 {
3913 /* Record any test of a biv that branches around the loop if no store
3914 between it and the start of loop. We only care about tests with
3915 constants and registers and only certain of those. */
3925 {
3926 /* If an NE test, we have an initial value! */
3928 {
3932 }
3933 else
3935 }
3936 }
3938 /* Look at the each biv and see if we can say anything better about its
3939 initial value from any initializing insns set up above. (This is done
3940 in two passes to avoid missing SETs in a PARALLEL.) */
3942 {
3943 rtx src;
3944 rtx note;
3949 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3950 is a constant, use the value of that. */
3956 else
3967 {
3971 {
3973 {
3976 }
3977 else
3978 {
3981 }
3982 }
3983 }
3984 else
3985 {
3987 rtx increment;
3989 /* Biv initial value is not a simple move. If it is the sum of
3990 another biv and a constant, check if both bivs are incremented
3991 in lockstep. Then we are actually looking at a giv.
3992 For simplicity, we only handle the case where there is but a
3993 single increment, and the register is not used elsewhere. */
4002 {
4008 }
4010 /* Now, can we transform this biv into a giv? */
4015 /* init_insn is only set to insns that are before loop_start
4016 without any intervening labels. */
4019 /* The register from BL2 must be set before the register from
4020 BL is set, or we must be able to move the latter set after
4021 the former set. Currently there can't be any labels
4022 in-between when biv_toal_increment returns nonzero both times
4023 but we test it here in case some day some real cfg analysis
4024 gets used to set always_computable. */
4033 {
4042 /* Let this giv be discovered by the generic code. */
4044 /* We can get better optimization if we can move the giv setting
4045 before the first giv use. */
4049 dominator)
4052 {
4053 rtx p;
4054 rtx next;
4057 {
4063 #ifdef HAVE_cc0
4066 #endif
4068 }
4072 /* Avoid problems with luids by actually moving the insn
4073 and adjusting all luids in the range. */
4078 /* If the only purpose of the init insn is to initialize
4079 this giv, delete it. */
4083 }
4085 {
4092 }
4093 /* Remove this biv from the chain. */
4096 else
4097 {
4100 }
4101 }
4103 /* If we can't make it a giv,
4104 let biv keep initial value of "itself". */
4107 }
4108 }
4110 /* If a biv is unconditionally incremented several times in a row, convert
4111 all but the last increment into a giv. */
4113 /* Get an upper bound for the number of registers
4114 we might have after all bivs have been processed. */
4119 /* If the loop contains volatile memory references do not allow any
4120 replacements to take place, since this could loose the volatile markers. */
4122 {
4125 /* Reallocate reg_iv_type and reg_iv_info. */
4130 {
4134 /* The biv increments lists are in reverse order. Fix this first. */
4136 {
4140 }
4142 /* We must guard against the case that an early exit between v->insn
4143 and next->insn leaves the biv live after the loop, since that
4144 would mean that we'd be missing an increment for the final
4145 value. The following test to set biv_dead_after_loop is like
4146 the first part of the test to set bl->eliminable.
4147 We don't check here if we can calculate the final value, since
4148 this can't succeed if we already know that there is a jump
4149 between v->insn and next->insn, yet next->always_executed is
4150 set and next->maybe_multiple is cleared. Such a combination
4151 implies that the jump destination is outside the loop.
4152 If we want to make this check more sophisticated, we should
4153 check each branch between v->insn and next->insn individually
4154 to see if the biv is dead at its destination. */
4161 #ifdef HAVE_decrement_and_branch_until_zero
4163 #endif
4168 {
4169 HOST_WIDE_INT offset;
4179 || ! (biv_dead_after_loop
4181 {
4184 }
4191 /* Unlike reg_iv_type / reg_iv_info, the other three arrays
4192 have been allocated with some slop space, so we may not
4193 actually need to reallocate them. If we do, the following
4194 if statement will be executed just once in this loop. */
4196 {
4197 /* Grow all the remaining arrays. */
4201 }
4204 {
4207 }
4209 /* Here we can try to eliminate the increment by combining
4210 it into the uses. */
4212 /* Set last_use_insn so that we can check against it. */
4217 {
4221 {
4223 }
4224 }
4226 /* If we can't get the LUIDs for the insns, we can't
4227 calculate the lifetime. This is likely from unrolling
4228 of an inner loop, so there is little point in making this
4229 a DEST_REG giv anyways. */
4233 {
4234 /* Change the increment at NEXT back to what it was. */
4240 }
4274 /* Remove the increment from the list of biv increments,
4275 and record it as a giv. */
4284 /* Now replace the biv with DEST_REG in all insns between
4285 the replaced increment and the next increment, and
4286 remember the last insn that needed a replacement. */
4290 {
4291 rtx note;
4296 {
4300 }
4302 {
4306 }
4307 }
4311 /* If the lifetime is zero, it means that this register is really
4312 a dead store. So mark this as a giv that can be ignored.
4313 This will not prevent the biv from being eliminated. */
4321 }
4322 }
4323 }
4326 /* Search the loop for general induction variables. */
4328 /* A register is a giv if: it is only set once, it is a function of a
4329 biv and a constant (or invariant), and it is not a biv. */
4335 {
4337 /* At end of a straight-in loop, we are done.
4338 At end of a loop entered at the bottom, scan the top. */
4342 {
4345 else
4349 }
4351 /* Look for a general induction variable in a register. */
4356 {
4357 rtx src_reg;
4358 rtx add_val;
4359 rtx mult_val;
4362 rtx last_consec_insn;
4371 /* Equivalent expression is a giv. */
4376 /* Don't try to handle any regs made by loop optimization.
4377 We have nothing on them in regno_first_uid, etc. */
4379 /* Don't recognize a BASIC_INDUCT_VAR here. */
4381 /* This must be the only place where the register is set. */
4383 /* or all sets must be consecutive and make a giv. */
4388 {
4392 /* If this is a library call, increase benefit. */
4396 /* Skip the consecutive insns, if there are any. */
4402 loop_end);
4404 }
4405 }
4407 #ifndef DONT_REDUCE_ADDR
4408 /* Look for givs which are memory addresses. */
4409 /* This resulted in worse code on a VAX 8600. I wonder if it
4410 still does. */
4413 loop_end);
4414 #endif
4416 /* Update the status of whether giv can derive other givs. This can
4417 change when we pass a label or an insn that updates a biv. */
4422 /* Past a jump, we get to insns for which we can't count
4423 on whether they will be executed during each iteration. */
4424 /* This code appears twice in strength_reduce. There is also similar
4425 code in scan_loop. */
4427 /* If we enter the loop in the middle, and scan around to the
4428 beginning, don't set not_every_iteration for that.
4429 This can be any kind of jump, since we want to know if insns
4430 will be executed if the loop is executed. */
4434 {
4437 /* If this is a jump outside the loop, then it also doesn't
4438 matter. Check to see if the target of this branch is on the
4439 loop_number_exits_labels list. */
4442 label;
4449 }
4452 {
4453 /* At the virtual top of a converted loop, insns are again known to
4454 be executed each iteration: logically, the loop begins here
4455 even though the exit code has been duplicated.
4457 Insns are also again known to be executed each iteration at
4458 the LOOP_CONT note. */
4464 loop_depth++;
4466 loop_depth--;
4467 }
4469 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4470 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4471 or not an insn is known to be executed each iteration of the
4472 loop, whether or not any iterations are known to occur.
4474 Therefore, if we have just passed a label and have no more labels
4475 between here and the test insn of the loop, we know these insns
4476 will be executed each iteration. */
4482 }
4484 /* Try to calculate and save the number of loop iterations. This is
4485 set to zero if the actual number can not be calculated. This must
4486 be called after all giv's have been identified, since otherwise it may
4487 fail if the iteration variable is a giv. */
4491 /* Now for each giv for which we still don't know whether or not it is
4492 replaceable, check to see if it is replaceable because its final value
4493 can be calculated. This must be done after loop_iterations is called,
4494 so that final_giv_value will work correctly. */
4497 {
4503 }
4505 /* Try to prove that the loop counter variable (if any) is always
4506 nonnegative; if so, record that fact with a REG_NONNEG note
4507 so that "decrement and branch until zero" insn can be used. */
4510 /* Create reg_map to hold substitutions for replaceable giv regs.
4511 Some givs might have been made from biv increments, so look at
4512 reg_iv_type for a suitable size. */
4517 /* Examine each iv class for feasibility of strength reduction/induction
4518 variable elimination. */
4521 {
4528 /* Test whether it will be possible to eliminate this biv
4529 provided all givs are reduced. This is possible if either
4530 the reg is not used outside the loop, or we can compute
4531 what its final value will be.
4533 For architectures with a decrement_and_branch_until_zero insn,
4534 don't do this if we put a REG_NONNEG note on the endtest for
4535 this biv. */
4537 /* Compare against bl->init_insn rather than loop_start.
4538 We aren't concerned with any uses of the biv between
4539 init_insn and loop_start since these won't be affected
4540 by the value of the biv elsewhere in the function, so
4541 long as init_insn doesn't use the biv itself.
4542 March 14, 1989 -- self@bayes.arc.nasa.gov */
4548 #ifdef HAVE_decrement_and_branch_until_zero
4550 #endif
4554 #ifdef HAVE_decrement_and_branch_until_zero
4556 #endif
4557 ))
4560 else
4561 {
4563 {
4571 }
4572 }
4574 /* Combine all giv's for this iv_class. */
4577 /* This will be true at the end, if all givs which depend on this
4578 biv have been strength reduced.
4579 We can't (currently) eliminate the biv unless this is so. */
4582 /* Check each giv in this class to see if we will benefit by reducing
4583 it. Skip giv's combined with others. */
4585 {
4593 /* Reduce benefit if not replaceable, since we will insert
4594 a move-insn to replace the insn that calculates this giv.
4595 Don't do this unless the giv is a user variable, since it
4596 will often be marked non-replaceable because of the duplication
4597 of the exit code outside the loop. In such a case, the copies
4598 we insert are dead and will be deleted. So they don't have
4599 a cost. Similar situations exist. */
4600 /* ??? The new final_[bg]iv_value code does a much better job
4601 of finding replaceable giv's, and hence this code may no longer
4602 be necessary. */
4607 /* Decrease the benefit to count the add-insns that we will
4608 insert to increment the reduced reg for the giv. */
4611 /* Decide whether to strength-reduce this giv or to leave the code
4612 unchanged (recompute it from the biv each time it is used).
4613 This decision can be made independently for each giv. */
4615 #ifdef AUTO_INC_DEC
4616 /* Attempt to guess whether autoincrement will handle some of the
4617 new add insns; if so, increase BENEFIT (undo the subtraction of
4618 add_cost that was done above). */
4621 {
4634 }
4635 #endif
4637 /* If an insn is not to be strength reduced, then set its ignore
4638 flag, and clear all_reduced. */
4640 /* A giv that depends on a reversed biv must be reduced if it is
4641 used after the loop exit, otherwise, it would have the wrong
4642 value after the loop exit. To make it simple, just reduce all
4643 of such giv's whether or not we know they are used after the loop
4644 exit. */
4648 {
4656 }
4657 else
4658 {
4659 /* Check that we can increment the reduced giv without a
4660 multiply insn. If not, reject it. */
4665 {
4673 }
4674 }
4675 }
4677 /* Check for givs whose first use is their definition and whose
4678 last use is the definition of another giv. If so, it is likely
4679 dead and should not be used to derive another giv nor to
4680 eliminate a biv. */
4682 {
4688 {
4694 }
4697 {
4703 }
4704 }
4706 /* Now that we know which givs will be reduced, try to rearrange the
4707 combinations to reduce register pressure.
4708 recombine_givs calls find_life_end, which needs reg_iv_type and
4709 reg_iv_info to be valid for all pseudos. We do the necessary
4710 reallocation here since it allows to check if there are still
4711 more bivs to process. */
4714 {
4715 /* If there are still more bivs to process, allocate some slack
4716 space so that we're not constantly reallocating these arrays. */
4719 /* Reallocate reg_iv_type and reg_iv_info. */
4722 }
4725 /* Reduce each giv that we decided to reduce. */
4728 {
4731 {
4734 /* If the code for derived givs immediately below has already
4735 allocated a new_reg, we must keep it. */
4740 {
4743 /* In case d->dest_reg is not replaceable, we have
4744 to replace it in v->insn now. */
4752 {
4753 /* For each place where the biv is incremented, add an
4754 insn to set the new, reduced reg for the giv. */
4756 {
4757 /* We always emit reduced giv increments before the
4758 biv increment when bl->biv_count != 1. So by
4759 emitting the add insns for derived givs after the
4760 biv increment, they pick up the updated value of
4761 the reduced giv. */
4765 }
4766 }
4768 }
4770 #ifdef AUTO_INC_DEC
4771 /* If the target has auto-increment addressing modes, and
4772 this is an address giv, then try to put the increment
4773 immediately after its use, so that flow can create an
4774 auto-increment addressing mode. */
4777 /* We don't handle reversed biv's because bl->biv->insn
4778 does not have a valid INSN_LUID. */
4782 {
4783 /* If other giv's have been combined with this one, then
4784 this will work only if all uses of the other giv's occur
4785 before this giv's insn. This is difficult to check.
4787 We simplify this by looking for the common case where
4788 there is one DEST_REG giv, and this giv's insn is the
4789 last use of the dest_reg of that DEST_REG giv. If the
4790 increment occurs after the address giv, then we can
4791 perform the optimization. (Otherwise, the increment
4792 would have to go before other_giv, and we would not be
4793 able to combine it with the address giv to get an
4794 auto-inc address.) */
4796 {
4801 {
4804 else
4806 }
4813 }
4814 /* Check for case where increment is before the address
4815 giv. Do this test in "loop order". */
4824 else
4827 #ifdef HAVE_cc0
4828 {
4829 rtx prev;
4831 /* We can't put an insn immediately after one setting
4832 cc0, or immediately before one using cc0. */
4839 }
4840 #endif
4844 }
4845 #endif
4847 /* For each place where the biv is incremented, add an insn
4848 to increment the new, reduced reg for the giv. */
4850 {
4851 rtx insert_before;
4857 else
4864 /* A multiply is acceptable here
4865 since this is presumed to be seldom executed. */
4868 }
4870 /* Add code at loop start to initialize giv's reduced reg. */
4874 }
4875 }
4877 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4878 as not reduced.
4880 For each giv register that can be reduced now: if replaceable,
4881 substitute reduced reg wherever the old giv occurs;
4882 else add new move insn "giv_reg = reduced_reg". */
4885 {
4892 /* Update expression if this was combined, in case other giv was
4893 replaced. */
4899 /* Store reduced reg as the address in the memref where we found
4900 this giv. */
4903 {
4906 #if 0
4907 /* I can no longer duplicate the original problem. Perhaps
4908 this is unnecessary now? */
4910 /* Replaceable; it isn't strictly necessary to delete the old
4911 insn and emit a new one, because v->dest_reg is now dead.
4913 However, especially when unrolling loops, the special
4914 handling for (set REG0 REG1) in the second cse pass may
4915 make v->dest_reg live again. To avoid this problem, emit
4916 an insn to set the original giv reg from the reduced giv.
4917 We can not delete the original insn, since it may be part
4918 of a LIBCALL, and the code in flow that eliminates dead
4919 libcalls will fail if it is deleted. */
4922 #endif
4923 }
4924 else
4925 {
4926 /* Not replaceable; emit an insn to set the original giv reg from
4927 the reduced giv, same as above. */
4930 }
4932 /* When a loop is reversed, givs which depend on the reversed
4933 biv, and which are live outside the loop, must be set to their
4934 correct final value. This insn is only needed if the giv is
4935 not replaceable. The correct final value is the same as the
4936 value that the giv starts the reversed loop with. */
4941 {
4942 rtx insert_before;
4944 /* If the loop has multiple exits, emit the insn before the
4945 loop to ensure that it will always be executed no matter
4946 how the loop exits. Otherwise, emit the insn after the loop,
4947 since this is slightly more efficient. */
4950 else
4953 insert_before);
4955 #if 0
4956 /* If the insn to set the final value of the giv was emitted
4957 before the loop, then we must delete the insn inside the loop
4958 that sets it. If this is a LIBCALL, then we must delete
4959 every insn in the libcall. Note, however, that
4960 final_giv_value will only succeed when there are multiple
4961 exits if the giv is dead at each exit, hence it does not
4962 matter that the original insn remains because it is dead
4963 anyways. */
4964 /* Delete the insn inside the loop that sets the giv since
4965 the giv is now set before (or after) the loop. */
4967 #endif
4968 }
4971 {
4976 }
4977 }
4979 /* All the givs based on the biv bl have been reduced if they
4980 merit it. */
4982 /* For each giv not marked as maybe dead that has been combined with a
4983 second giv, clear any "maybe dead" mark on that second giv.
4984 v->new_reg will either be or refer to the register of the giv it
4985 combined with.
4987 Doing this clearing avoids problems in biv elimination where a
4988 giv's new_reg is a complex value that can't be put in the insn but
4989 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4990 Since the register will be used in either case, we'd prefer it be
4991 used from the simpler giv. */
4997 /* Try to eliminate the biv, if it is a candidate.
4998 This won't work if ! all_reduced,
4999 since the givs we planned to use might not have been reduced.
5001 We have to be careful that we didn't initially think we could eliminate
5002 this biv because of a giv that we now think may be dead and shouldn't
5003 be used as a biv replacement.
5005 Also, there is the possibility that we may have a giv that looks
5006 like it can be used to eliminate a biv, but the resulting insn
5007 isn't valid. This can happen, for example, on the 88k, where a
5008 JUMP_INSN can compare a register only with zero. Attempts to
5009 replace it with a compare with a constant will fail.
5011 Note that in cases where this call fails, we may have replaced some
5012 of the occurrences of the biv with a giv, but no harm was done in
5013 doing so in the rare cases where it can occur. */
5019 {
5020 /* ?? If we created a new test to bypass the loop entirely,
5021 or otherwise drop straight in, based on this test, then
5022 we might want to rewrite it also. This way some later
5023 pass has more hope of removing the initialization of this
5024 biv entirely. */
5026 /* If final_value != 0, then the biv may be used after loop end
5027 and we must emit an insn to set it just in case.
5029 Reversed bivs already have an insn after the loop setting their
5030 value, so we don't need another one. We can't calculate the
5031 proper final value for such a biv here anyways. */
5033 {
5034 rtx insert_before;
5036 /* If the loop has multiple exits, emit the insn before the
5037 loop to ensure that it will always be executed no matter
5038 how the loop exits. Otherwise, emit the insn after the
5039 loop, since this is slightly more efficient. */
5042 else
5046 end_insert_before);
5047 }
5049 #if 0
5050 /* Delete all of the instructions inside the loop which set
5051 the biv, as they are all dead. If is safe to delete them,
5052 because an insn setting a biv will never be part of a libcall. */
5053 /* However, deleting them will invalidate the regno_last_uid info,
5054 so keeping them around is more convenient. Final_biv_value
5055 will only succeed when there are multiple exits if the biv
5056 is dead at each exit, hence it does not matter that the original
5057 insn remains, because it is dead anyways. */
5060 #endif
5065 }
5066 }
5068 /* Go through all the instructions in the loop, making all the
5069 register substitutions scheduled in REG_MAP. */
5074 {
5078 }
5080 /* Unroll loops from within strength reduction so that we can use the
5081 induction variable information that strength_reduce has already
5082 collected. */
5088 #ifdef HAVE_decrement_and_branch_on_count
5089 /* Instrument the loop with BCT insn. */
5099 }
5100 \f
5101 /* Return 1 if X is a valid source for an initial value (or as value being
5102 compared against in an initial test).
5104 X must be either a register or constant and must not be clobbered between
5105 the current insn and the start of the loop.
5107 INSN is the insn containing X. */
5109 static int
5111 rtx x;
5112 rtx insn;
5114 rtx loop_start;
5115 {
5119 /* Only consider pseudos we know about initialized in insns whose luids
5120 we know. */
5125 /* Don't use call-clobbered registers across a call which clobbers it. On
5126 some machines, don't use any hard registers at all. */
5128 && (SMALL_REGISTER_CLASSES
5132 /* Don't use registers that have been clobbered before the start of the
5133 loop. */
5138 }
5139 \f
5140 /* Scan X for memory refs and check each memory address
5141 as a possible giv. INSN is the insn whose pattern X comes from.
5142 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5143 every loop iteration. */
5145 static void
5147 rtx x;
5148 rtx insn;
5151 {
5161 {
5177 {
5178 rtx src_reg;
5179 rtx add_val;
5180 rtx mult_val;
5183 /* This code used to disable creating GIVs with mult_val == 1 and
5184 add_val == 0. However, this leads to lost optimizations when
5185 it comes time to combine a set of related DEST_ADDR GIVs, since
5186 this one would not be seen. */
5190 {
5191 /* Found one; record it. */
5200 }
5201 }
5206 }
5208 /* Recursively scan the subexpressions for other mem refs. */
5214 loop_end);
5219 }
5220 \f
5221 /* Fill in the data about one biv update.
5222 V is the `struct induction' in which we record the biv. (It is
5223 allocated by the caller, with alloca.)
5224 INSN is the insn that sets it.
5225 DEST_REG is the biv's reg.
5227 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5228 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5229 being set to INC_VAL.
5231 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5232 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5233 can be executed more than once per iteration. If MAYBE_MULTIPLE
5234 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5235 executed exactly once per iteration. */
5237 static void
5241 rtx insn;
5242 rtx dest_reg;
5243 rtx inc_val;
5244 rtx mult_val;
5248 {
5262 /* Add this to the reg's iv_class, creating a class
5263 if this is the first incrementation of the reg. */
5267 {
5268 /* Create and initialize new iv_class. */
5278 /* Set initial value to the reg itself. */
5280 /* We haven't seen the initializing insn yet */
5290 /* Add this class to loop_iv_list. */
5294 /* Put it in the array of biv register classes. */
5296 }
5298 /* Update IV_CLASS entry for this biv. */
5306 {
5311 {
5315 }
5316 else
5317 {
5321 }
5322 }
5323 }
5324 \f
5325 /* Fill in the data about one giv.
5326 V is the `struct induction' in which we record the giv. (It is
5327 allocated by the caller, with alloca.)
5328 INSN is the insn that sets it.
5329 BENEFIT estimates the savings from deleting this insn.
5330 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5331 into a register or is used as a memory address.
5333 SRC_REG is the biv reg which the giv is computed from.
5334 DEST_REG is the giv's reg (if the giv is stored in a reg).
5335 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5336 LOCATION points to the place where this giv's value appears in INSN. */
5338 static void
5342 rtx insn;
5343 rtx src_reg;
5344 rtx dest_reg;
5351 {
5380 /* The v->always_computable field is used in update_giv_derive, to
5381 determine whether a giv can be used to derive another giv. For a
5382 DEST_REG giv, INSN computes a new value for the giv, so its value
5383 isn't computable if INSN insn't executed every iteration.
5384 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5385 it does not compute a new value. Hence the value is always computable
5386 regardless of whether INSN is executed each iteration. */
5390 else
5396 {
5399 }
5401 {
5407 /* If the lifetime is zero, it means that this register is
5408 really a dead store. So mark this as a giv that can be
5409 ignored. This will not prevent the biv from being eliminated. */
5415 }
5417 /* Add the giv to the class of givs computed from one biv. */
5421 {
5424 /* Don't count DEST_ADDR. This is supposed to count the number of
5425 insns that calculate givs. */
5429 }
5430 else
5431 /* Fatal error, biv missing for this giv? */
5436 else
5437 {
5438 /* The giv can be replaced outright by the reduced register only if all
5439 of the following conditions are true:
5440 - the insn that sets the giv is always executed on any iteration
5441 on which the giv is used at all
5442 (there are two ways to deduce this:
5443 either the insn is executed on every iteration,
5444 or all uses follow that insn in the same basic block),
5445 - the giv is not used outside the loop
5446 - no assignments to the biv occur during the giv's lifetime. */
5449 /* Previous line always fails if INSN was moved by loop opt. */
5451 && (! not_every_iteration
5453 {
5454 /* Now check that there are no assignments to the biv within the
5455 giv's lifetime. This requires two separate checks. */
5457 /* Check each biv update, and fail if any are between the first
5458 and last use of the giv.
5460 If this loop contains an inner loop that was unrolled, then
5461 the insn modifying the biv may have been emitted by the loop
5462 unrolling code, and hence does not have a valid luid. Just
5463 mark the biv as not replaceable in this case. It is not very
5464 useful as a biv, because it is used in two different loops.
5465 It is very unlikely that we would be able to optimize the giv
5466 using this biv anyways. */
5470 {
5476 {
5480 }
5481 }
5483 /* If there are any backwards branches that go from after the
5484 biv update to before it, then this giv is not replaceable. */
5488 {
5492 }
5493 }
5494 else
5495 {
5496 /* May still be replaceable, we don't have enough info here to
5497 decide. */
5500 }
5501 }
5503 /* Record whether the add_val contains a const_int, for later use by
5504 combine_givs. */
5505 {
5510 ;
5514 {
5516 {
5521 else
5523 }
5526 }
5527 }
5530 {
5534 else
5550 {
5553 }
5554 else
5555 {
5558 }
5561 {
5564 }
5565 else
5566 {
5569 }
5570 }
5575 }
5578 /* All this does is determine whether a giv can be made replaceable because
5579 its final value can be calculated. This code can not be part of record_giv
5580 above, because final_giv_value requires that the number of loop iterations
5581 be known, and that can not be accurately calculated until after all givs
5582 have been identified. */
5584 static void
5589 {
5595 /* DEST_ADDR givs will never reach here, because they are always marked
5596 replaceable above in record_giv. */
5598 /* The giv can be replaced outright by the reduced register only if all
5599 of the following conditions are true:
5600 - the insn that sets the giv is always executed on any iteration
5601 on which the giv is used at all
5602 (there are two ways to deduce this:
5603 either the insn is executed on every iteration,
5604 or all uses follow that insn in the same basic block),
5605 - its final value can be calculated (this condition is different
5606 than the one above in record_giv)
5607 - no assignments to the biv occur during the giv's lifetime. */
5609 #if 0
5610 /* This is only called now when replaceable is known to be false. */
5611 /* Clear replaceable, so that it won't confuse final_giv_value. */
5613 #endif
5617 {
5620 rtx last_giv_use;
5624 /* When trying to determine whether or not a biv increment occurs
5625 during the lifetime of the giv, we can ignore uses of the variable
5626 outside the loop because final_value is true. Hence we can not
5627 use regno_last_uid and regno_first_uid as above in record_giv. */
5629 /* Search the loop to determine whether any assignments to the
5630 biv occur during the giv's lifetime. Start with the insn
5631 that sets the giv, and search around the loop until we come
5632 back to that insn again.
5634 Also fail if there is a jump within the giv's lifetime that jumps
5635 to somewhere outside the lifetime but still within the loop. This
5636 catches spaghetti code where the execution order is not linear, and
5637 hence the above test fails. Here we assume that the giv lifetime
5638 does not extend from one iteration of the loop to the next, so as
5639 to make the test easier. Since the lifetime isn't known yet,
5640 this requires two loops. See also record_giv above. */
5645 {
5654 {
5656 {
5658 {
5662 }
5663 }
5668 }
5669 }
5671 /* Now that the lifetime of the giv is known, check for branches
5672 from within the lifetime to outside the lifetime if it is still
5673 replaceable. */
5676 {
5679 {
5692 {
5701 }
5702 }
5703 }
5705 /* If it is replaceable, then save the final value. */
5708 }
5713 }
5714 \f
5715 /* Update the status of whether a giv can derive other givs.
5717 We need to do something special if there is or may be an update to the biv
5718 between the time the giv is defined and the time it is used to derive
5719 another giv.
5721 In addition, a giv that is only conditionally set is not allowed to
5722 derive another giv once a label has been passed.
5724 The cases we look at are when a label or an update to a biv is passed. */
5726 static void
5728 rtx p;
5729 {
5732 rtx tem;
5735 /* Search all IV classes, then all bivs, and finally all givs.
5737 There are three cases we are concerned with. First we have the situation
5738 of a giv that is only updated conditionally. In that case, it may not
5739 derive any givs after a label is passed.
5741 The second case is when a biv update occurs, or may occur, after the
5742 definition of a giv. For certain biv updates (see below) that are
5743 known to occur between the giv definition and use, we can adjust the
5744 giv definition. For others, or when the biv update is conditional,
5745 we must prevent the giv from deriving any other givs. There are two
5746 sub-cases within this case.
5748 If this is a label, we are concerned with any biv update that is done
5749 conditionally, since it may be done after the giv is defined followed by
5750 a branch here (actually, we need to pass both a jump and a label, but
5751 this extra tracking doesn't seem worth it).
5753 If this is a jump, we are concerned about any biv update that may be
5754 executed multiple times. We are actually only concerned about
5755 backward jumps, but it is probably not worth performing the test
5756 on the jump again here.
5758 If this is a biv update, we must adjust the giv status to show that a
5759 subsequent biv update was performed. If this adjustment cannot be done,
5760 the giv cannot derive further givs. */
5766 {
5768 {
5769 /* If cant_derive is already true, there is no point in
5770 checking all of these conditions again. */
5774 /* If this giv is conditionally set and we have passed a label,
5775 it cannot derive anything. */
5779 /* Skip givs that have mult_val == 0, since
5780 they are really invariants. Also skip those that are
5781 replaceable, since we know their lifetime doesn't contain
5782 any biv update. */
5786 /* The only way we can allow this giv to derive another
5787 is if this is a biv increment and we can form the product
5788 of biv->add_val and giv->mult_val. In this case, we will
5789 be able to compute a compensation. */
5791 {
5806 else
5808 }
5812 }
5813 }
5814 }
5815 \f
5816 /* Check whether an insn is an increment legitimate for a basic induction var.
5817 X is the source of insn P, or a part of it.
5818 MODE is the mode in which X should be interpreted.
5820 DEST_REG is the putative biv, also the destination of the insn.
5821 We accept patterns of these forms:
5822 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5823 REG = INVARIANT + REG
5825 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5826 store the additive term into *INC_VAL, and store the place where
5827 we found the additive term into *LOCATION.
5829 If X is an assignment of an invariant into DEST_REG, we set
5830 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5832 We also want to detect a BIV when it corresponds to a variable
5833 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5834 of the variable may be a PLUS that adds a SUBREG of that variable to
5835 an invariant and then sign- or zero-extends the result of the PLUS
5836 into the variable.
5838 Most GIVs in such cases will be in the promoted mode, since that is the
5839 probably the natural computation mode (and almost certainly the mode
5840 used for addresses) on the machine. So we view the pseudo-reg containing
5841 the variable as the BIV, as if it were simply incremented.
5843 Note that treating the entire pseudo as a BIV will result in making
5844 simple increments to any GIVs based on it. However, if the variable
5845 overflows in its declared mode but not its promoted mode, the result will
5846 be incorrect. This is acceptable if the variable is signed, since
5847 overflows in such cases are undefined, but not if it is unsigned, since
5848 those overflows are defined. So we only check for SIGN_EXTEND and
5849 not ZERO_EXTEND.
5851 If we cannot find a biv, we return 0. */
5853 static int
5857 rtx p;
5858 rtx dest_reg;
5862 {
5869 {
5875 {
5877 }
5882 {
5884 }
5885 else
5898 /* If this is a SUBREG for a promoted variable, check the inner
5899 value. */
5906 /* If this register is assigned in a previous insn, look at its
5907 source, but don't go outside the loop or past a label. */
5911 {
5935 }
5936 /* ... fall through ... */
5938 /* Can accept constant setting of biv only when inside inner most loop.
5939 Otherwise, a biv of an inner loop may be incorrectly recognized
5940 as a biv of the outer loop,
5941 causing code to be moved INTO the inner loop. */
5948 /* convert_modes aborts if we try to convert to or from CCmode, so just
5949 exclude that case. It is very unlikely that a condition code value
5950 would be a useful iterator anyways. */
5954 {
5955 /* Possible bug here? Perhaps we don't know the mode of X. */
5959 }
5960 else
5968 /* Similar, since this can be a sign extension. */
5973 ;
5986 location);
5991 }
5992 }
5993 \f
5994 /* A general induction variable (giv) is any quantity that is a linear
5995 function of a basic induction variable,
5996 i.e. giv = biv * mult_val + add_val.
5997 The coefficients can be any loop invariant quantity.
5998 A giv need not be computed directly from the biv;
5999 it can be computed by way of other givs. */
6001 /* Determine whether X computes a giv.
6002 If it does, return a nonzero value
6003 which is the benefit from eliminating the computation of X;
6004 set *SRC_REG to the register of the biv that it is computed from;
6005 set *ADD_VAL and *MULT_VAL to the coefficients,
6006 such that the value of X is biv * mult + add; */
6008 static int
6010 rtx x;
6016 {
6020 /* If this is an invariant, forget it, it isn't a giv. */
6024 /* See if the expression could be a giv and get its form.
6025 Mark our place on the obstack in case we don't find a giv. */
6030 {
6033 }
6036 {
6039 /* Since this is now an invariant and wasn't before, it must be a giv
6040 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6041 with. */
6048 /* This is equivalent to a BIV. */
6055 /* Either (plus (biv) (invar)) or
6056 (plus (mult (biv) (invar_1)) (invar_2)). */
6058 {
6061 }
6062 else
6063 {
6066 }
6071 /* ADD_VAL is zero. */
6079 }
6081 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6082 unless they are CONST_INT). */
6089 {
6090 #ifdef ADDRESS_COST
6092 #else
6094 #endif
6095 }
6096 else
6099 /* Always return true if this is a giv so it will be detected as such,
6100 even if the benefit is zero or negative. This allows elimination
6101 of bivs that might otherwise not be eliminated. */
6103 }
6104 \f
6105 /* Given an expression, X, try to form it as a linear function of a biv.
6106 We will canonicalize it to be of the form
6107 (plus (mult (BIV) (invar_1))
6108 (invar_2))
6109 with possible degeneracies.
6111 The invariant expressions must each be of a form that can be used as a
6112 machine operand. We surround then with a USE rtx (a hack, but localized
6113 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6114 routine; it is the caller's responsibility to strip them.
6116 If no such canonicalization is possible (i.e., two biv's are used or an
6117 expression that is neither invariant nor a biv or giv), this routine
6118 returns 0.
6120 For a non-zero return, the result will have a code of CONST_INT, USE,
6121 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6123 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6128 static rtx
6130 rtx x;
6132 {
6135 rtx tem;
6137 /* If this is not an integer mode, or if we cannot do arithmetic in this
6138 mode, this can't be a giv. */
6145 {
6152 /* Put constant last, CONST_INT last if both constant. */
6160 /* Handle addition of zero, then addition of an invariant. */
6165 {
6168 /* Adding two invariants must result in an invariant, so enclose
6169 addition operation inside a USE and return it. */
6179 else
6188 /* biv + invar or mult + invar. Return sum. */
6192 /* (a + invar_1) + invar_2. Associate. */
6196 benefit);
6200 }
6202 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6203 MULT to reduce cases. */
6209 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6210 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6211 Recurse to associate the second PLUS. */
6220 benefit);
6222 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6234 benefit);
6237 /* Handle "a - b" as "a + b * (-1)". */
6241 constm1_rtx)),
6242 benefit);
6250 /* Put constant last, CONST_INT last if both constant. */
6255 /* If second argument is not now constant, not giv. */
6259 /* Handle multiply by 0 or 1. */
6267 {
6269 /* biv * invar. Done. */
6273 /* Product of two constants. */
6277 /* invar * invar. It is a giv, but very few of these will
6278 actually pay off, so limit to simple registers. */
6288 {
6292 }
6293 else
6298 /* (a * invar_1) * invar_2. Associate. */
6302 arg1)),
6303 benefit);
6306 /* (a + invar_1) * invar_2. Distribute. */
6310 arg1),
6313 arg1)),
6314 benefit);
6318 }
6321 /* Shift by constant is multiply by power of two. */
6329 benefit);
6332 /* "-a" is "a * (-1)" */
6334 benefit);
6337 /* "~a" is "-a - 1". Silly, but easy. */
6340 const1_rtx),
6341 benefit);
6344 /* Already in proper form for invariant. */
6348 /* If this is a new register, we can't deal with it. */
6352 /* Check for biv or giv. */
6354 {
6358 {
6361 /* Form expression from giv and add benefit. Ensure this giv
6362 can derive another and subtract any needed adjustment if so. */
6373 }
6376 /* If it isn't an induction variable, and it is invariant, we
6377 may be able to simplify things further by looking through
6378 the bits we just moved outside the loop. */
6380 {
6385 {
6386 /* Ok, we found a match. Substitute and simplify. */
6388 /* If we match another movable, we must use that, as
6389 this one is going away. */
6393 /* If consec is non-zero, this is a member of a group of
6394 instructions that were moved together. We handle this
6395 case only to the point of seeking to the last insn and
6396 looking for a REG_EQUAL. Fail if we don't find one. */
6398 {
6406 }
6407 else
6408 {
6412 }
6415 {
6416 /* What we are most interested in is pointer
6417 arithmetic on invariants -- only take
6418 patterns we may be able to do something with. */
6424 {
6428 }
6433 {
6437 }
6438 }
6440 }
6441 }
6443 }
6445 /* Fall through to general case. */
6447 /* If invariant, return as USE (unless CONST_INT).
6448 Otherwise, not giv. */
6453 {
6462 }
6463 else
6465 }
6466 }
6468 /* This routine folds invariants such that there is only ever one
6469 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6471 static rtx
6474 {
6480 {
6483 }
6486 {
6489 }
6490 else
6491 {
6494 }
6495 }
6497 static rtx
6501 {
6503 {
6507 else
6510 }
6513 else
6516 }
6517 \f
6518 /* Help detect a giv that is calculated by several consecutive insns;
6519 for example,
6520 giv = biv * M
6521 giv = giv + A
6522 The caller has already identified the first insn P as having a giv as dest;
6523 we check that all other insns that set the same register follow
6524 immediately after P, that they alter nothing else,
6525 and that the result of the last is still a giv.
6527 The value is 0 if the reg set in P is not really a giv.
6528 Otherwise, the value is the amount gained by eliminating
6529 all the consecutive insns that compute the value.
6531 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6532 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6534 The coefficients of the ultimate giv value are stored in
6535 *MULT_VAL and *ADD_VAL. */
6537 static int
6541 rtx p;
6542 rtx src_reg;
6543 rtx dest_reg;
6547 {
6551 rtx temp;
6552 rtx set;
6554 /* Indicate that this is a giv so that we can update the value produced in
6555 each insn of the multi-insn sequence.
6557 This induction structure will be used only by the call to
6558 general_induction_var below, so we can allocate it on our stack.
6559 If this is a giv, our caller will replace the induct var entry with
6560 a new induction structure. */
6576 {
6580 /* If libcall, skip to end of call sequence. */
6590 /* Giv created by equivalent expression. */
6595 {
6599 count--;
6603 }
6605 {
6606 /* Allow insns that set something other than this giv to a
6607 constant. Such insns are needed on machines which cannot
6608 include long constants and should not disqualify a giv. */
6617 }
6618 }
6622 }
6623 \f
6624 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6625 represented by G1. If no such expression can be found, or it is clear that
6626 it cannot possibly be a valid address, 0 is returned.
6628 To perform the computation, we note that
6629 G1 = x * v + a and
6630 G2 = y * v + b
6631 where `v' is the biv.
6633 So G2 = (y/b) * G1 + (b - a*y/x).
6635 Note that MULT = y/x.
6637 Update: A and B are now allowed to be additive expressions such that
6638 B contains all variables in A. That is, computing B-A will not require
6639 subtracting variables. */
6641 static rtx
6644 {
6645 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6650 /* If MULT is not 1, we cannot handle A with non-constants, since we
6651 would then be required to subtract multiples of the registers in A.
6652 This is theoretically possible, and may even apply to some Fortran
6653 constructs, but it is a lot of work and we do not attempt it here. */
6658 /* In general these structures are sorted top to bottom (down the PLUS
6659 chain), but not left to right across the PLUS. If B is a higher
6660 order giv than A, we can strip one level and recurse. If A is higher
6661 order, we'll eventually bail out, but won't know that until the end.
6662 If they are the same, we'll strip one level around this loop. */
6665 {
6677 /* We matched: remove one reg completely. */
6680 /* An alternate match. */
6683 /* An alternate match. */
6685 else
6686 {
6687 /* Indicates an extra register in B. Strip one level from B and
6688 recurse, hoping B was the higher order expression. */
6693 }
6694 }
6696 /* Here we are at the last level of A, go through the cases hoping to
6697 get rid of everything but a constant. */
6700 {
6713 }
6715 {
6717 }
6719 {
6724 else
6726 }
6731 }
6733 rtx
6736 {
6739 /* The value that G1 will be multiplied by must be a constant integer. Also,
6740 the only chance we have of getting a valid address is if b*c/a (see above
6741 for notation) is also an integer. */
6744 {
6749 }
6752 else
6753 {
6754 /* ??? Find out if the one is a multiple of the other? */
6756 }
6762 /* Form simplified final result. */
6767 else
6772 else
6773 {
6776 {
6780 }
6783 }
6785 }
6786 \f
6787 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6788 represented by G1. This indicates that G2 should be combined with G1 and
6789 that G2 can use (either directly or via an address expression) a register
6790 used to represent G1. */
6792 static rtx
6795 {
6798 /* If these givs are identical, they can be combined. We use the results
6799 of express_from because the addends are not in a canonical form, so
6800 rtx_equal_p is a weaker test. */
6801 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6802 combination to be the other way round. */
6805 {
6807 }
6809 /* If G2 can be expressed as a function of G1 and that function is valid
6810 as an address and no more expensive than using a register for G2,
6811 the expression of G2 in terms of G1 can be used. */
6815 /* ??? Looses, especially with -fforce-addr, where *g2->location
6816 will always be a register, and so anything more complicated
6817 gets discarded. */
6818 #if 0
6819 #ifdef ADDRESS_COST
6821 #else
6823 #endif
6824 #endif
6825 )
6826 {
6828 }
6831 }
6832 \f
6833 struct combine_givs_stats
6834 {
6837 };
6839 static int
6842 {
6845 /* Stabilize the sort. */
6849 }
6851 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6852 any other. If so, point SAME to the giv combined with and set NEW_REG to
6853 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6854 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6856 static void
6859 {
6860 /* Additional benefit to add for being combined multiple times. */
6868 /* Count givs, because bl->giv_count is incorrect here. */
6872 giv_count++;
6874 giv_array
6888 {
6890 rtx single_use;
6895 /* If a DEST_REG GIV is used only once, do not allow it to combine
6896 with anything, for in doing so we will gain nothing that cannot
6897 be had by simply letting the GIV with which we would have combined
6898 to be reduced on its own. The losage shows up in particular with
6899 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6900 be seen elsewhere as well. */
6907 /* Add an additional weight for zero addends. */
6912 {
6913 rtx this_combine;
6918 {
6921 }
6922 }
6924 }
6926 /* Iterate, combining until we can't. */
6927 restart:
6931 {
6934 {
6940 }
6942 }
6945 {
6951 /* If it has already been combined, skip. */
6956 {
6959 /* If it has already been combined, skip. */
6961 {
6971 /* ??? The new final_[bg]iv_value code does a much better job
6972 of finding replaceable giv's, and hence this code may no
6973 longer be necessary. */
6977 /* To help optimize the next set of combinations, remove
6978 this giv from the benefits of other potential mates. */
6980 {
6984 }
6990 }
6991 }
6993 /* To help optimize the next set of combinations, remove
6994 this giv from the benefits of other potential mates. */
6996 {
6998 {
7002 }
7006 /* We've finished with this giv, and everything it touched.
7007 Restart the combination so that proper weights for the
7008 rest of the givs are properly taken into account. */
7009 /* ??? Ideally we would compact the arrays at this point, so
7010 as to not cover old ground. But sanely compacting
7011 can_combine is tricky. */
7013 }
7014 }
7015 }
7016 \f
7017 struct recombine_givs_stats
7018 {
7021 };
7023 /* Used below as comparison function for qsort. We want a ascending luid
7024 when scanning the array starting at the end, thus the arguments are
7025 used in reverse. */
7026 static int
7029 {
7032 /* Stabilize the sort. */
7036 }
7038 /* Scan X, which is a part of INSN, for the end of life of a giv. Also
7039 look for the start of life of a giv where the start has not been seen
7040 yet to unlock the search for the end of its life.
7041 Only consider givs that belong to BIV.
7042 Return the total number of lifetime ends that have been found. */
7043 static int
7047 {
7055 {
7057 {
7060 {
7068 {
7069 /* If we see a 0 here for end_luid, it means that we have
7070 scanned the entire loop without finding any use at all.
7071 We must not predicate this code on a start_luid match
7072 since that would make the test fail for givs that have
7073 been hoisted out of inner loops. */
7075 {
7078 }
7081 }
7083 }
7085 }
7087 {
7095 {
7100 }
7102 }
7110 }
7114 {
7121 }
7123 }
7125 /* For each giv that has been combined with another, look if
7126 we can combine it with the most recently used one instead.
7127 This tends to shorten giv lifetimes, and helps the next step:
7128 try to derive givs from other givs. */
7129 static void
7134 {
7142 {
7144 giv_count++;
7145 }
7146 giv_array
7150 /* Initialize stats and set up the ix field for each giv in stats to name
7151 the corresponding index into stats. */
7153 {
7154 rtx p;
7160 /* If this giv has been hoisted out of an inner loop, use the luid of
7161 the previous insn. */
7166 i++;
7167 }
7171 /* Do the actual most-recently-used recombination. */
7173 {
7176 {
7178 rtx new_combine;
7180 /* combine_givs_p actually says if we can make this transformation.
7181 The other tests are here only to avoid keeping a giv alive
7182 that could otherwise be eliminated. */
7188 {
7193 /* No need to update lifetimes / benefits here since we have
7194 already decided what to reduce. */
7197 {
7203 }
7205 }
7207 }
7215 }
7218 /* For each DEST_REG giv, compute lifetime starts, and try to compute
7219 lifetime ends from regscan info. */
7221 {
7225 {
7226 /* Loop unrolling of an inner loop can even create new DEST_REG
7227 givs. */
7228 rtx p;
7234 }
7236 {
7238 {
7241 }
7243 {
7244 rtx p;
7245 /* This insn has been created by loop optimization on an inner
7246 loop. We don't have a proper start_luid that will match
7247 when we see the first set. But we do know that there will
7248 be no use before the set, so we can set end_luid to 0 so that
7249 we'll start looking for the last use right away. */
7254 ends_need_computing++;
7255 }
7256 else
7257 {
7262 /* Find the first insn that sets the giv, so that we can verify
7263 if this giv's lifetime wraps around the loop. We also need
7264 the luid of the first setting insn in order to detect the
7265 last use properly. */
7267 {
7270 count--;
7271 }
7275 {
7277 ends_need_computing++;
7278 }
7279 else
7280 {
7283 {
7285 ends_need_computing++;
7286 }
7287 }
7288 }
7289 }
7290 i++;
7291 }
7293 /* If the regscan information was unconclusive for one or more DEST_REG
7294 givs, scan the all insn in the loop to find out lifetime ends. */
7296 {
7300 do
7301 {
7308 }
7310 }
7312 /* Set start_luid back to the last insn that sets the giv. This allows
7313 more combinations. */
7315 {
7320 i++;
7321 }
7323 /* Now adjust lifetime ends by taking combined givs into account. */
7325 {
7332 {
7335 /* Use unsigned arithmetic to model loop wrap-around. */
7339 }
7340 i++;
7341 }
7345 /* Try to derive DEST_REG givs from previous DEST_REG givs with the
7346 same mult_val and non-overlapping lifetime. This reduces register
7347 pressure.
7348 Once we find a DEST_REG giv that is suitable to derive others from,
7349 we set last_giv to this giv, and try to derive as many other DEST_REG
7350 givs from it without joining overlapping lifetimes. If we then
7351 encounter a DEST_REG giv that we can't derive, we set rescan to the
7352 index for this giv (unless rescan is already set).
7353 When we are finished with the current LAST_GIV (i.e. the inner loop
7354 terminates), we start again with rescan, which then becomes the new
7355 LAST_GIV. */
7357 {
7361 {
7362 rtx sum;
7368 {
7369 /* Don't use a giv that's likely to be dead to derive
7370 others - that would be likely to keep that giv alive. */
7372 {
7376 }
7378 }
7379 /* Use unsigned arithmetic to model loop wrap around. */
7384 /* Check that the giv insn we're about to use for deriving
7385 precedes all uses of that giv. Note that initializing the
7386 derived giv would defeat the purpose of reducing register
7387 pressure.
7388 ??? We could arrange to move the insn. */
7392 /* ??? Could handle libcalls, but would need more logic. */
7394 /* We would really like to know if for any giv that v
7395 is combined with, v->insn or any intervening biv increment
7396 dominates that combined giv. However, we
7397 don't have this detailed control flow information.
7398 N.B. since last_giv will be reduced, it is valid
7399 anywhere in the loop, so we don't need to check the
7400 validity of last_giv.
7401 We rely here on the fact that v->always_executed implies that
7402 there is no jump to someplace else in the loop before the
7403 giv insn, and hence any insn that is executed before the
7404 giv insn in the loop will have a lower luid. */
7407 /* Make sure we don't make the add more expensive. ADD_COST
7408 doesn't take different costs of registers and constants into
7409 account, so compare the cost of the actual SET_SRCs. */
7412 /* ??? unroll can't understand anything but reg + const_int
7413 sums. It would be cleaner to fix unroll. */
7420 {
7425 {
7431 }
7432 }
7435 }
7436 }
7437 }
7438 \f
7439 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
7441 void
7447 rtx insert_before;
7448 {
7449 rtx seq;
7450 rtx result;
7452 /* Prevent unexpected sharing of these rtx. */
7456 /* Increase the lifetime of any invariants moved further in code. */
7470 /* It is entirely possible that the expansion created lots of new
7471 registers. Iterate over the sequence we just created and
7472 record them all. */
7475 {
7478 {
7482 }
7483 }
7487 }
7488 \f
7489 /* Test whether A * B can be computed without
7490 an actual multiply insn. Value is 1 if so. */
7492 static int
7494 rtx a;
7495 rtx b;
7496 {
7498 rtx tmp;
7503 /* If only one is constant, make it B. */
7507 /* If first constant, both constant, so don't need multiply. */
7511 /* If second not constant, neither is constant, so would need multiply. */
7515 /* One operand is constant, so might not need multiply insn. Generate the
7516 code for the multiply and see if a call or multiply, or long sequence
7517 of insns is generated. */
7526 {
7531 else
7533 {
7542 {
7545 }
7546 }
7547 }
7556 /* Free any storage we obtained in generating this multiply and restore rtl
7557 allocation to its normal obstack. */
7562 }
7563 \f
7564 /* Check to see if loop can be terminated by a "decrement and branch until
7565 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7566 Also try reversing an increment loop to a decrement loop
7567 to see if the optimization can be performed.
7568 Value is nonzero if optimization was performed. */
7570 /* This is useful even if the architecture doesn't have such an insn,
7571 because it might change a loops which increments from 0 to n to a loop
7572 which decrements from n to 0. A loop that decrements to zero is usually
7573 faster than one that increments from zero. */
7575 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7576 such as approx_final_value, biv_total_increment, loop_iterations, and
7577 final_[bg]iv_value. */
7579 static int
7581 rtx loop_end;
7583 rtx loop_start;
7585 {
7587 rtx reg;
7588 rtx jump_label;
7589 rtx final_value;
7590 rtx start_value;
7591 rtx new_add_val;
7592 rtx comparison;
7593 rtx before_comparison;
7594 rtx p;
7595 rtx jump;
7596 rtx first_compare;
7599 /* If last insn is a conditional branch, and the insn before tests a
7600 register value, try to optimize it. Otherwise, we can't do anything. */
7607 /* Try to compute whether the compare/branch at the loop end is one or
7608 two instructions. */
7614 else
7617 /* Check all of the bivs to see if the compare uses one of them.
7618 Skip biv's set more than once because we can't guarantee that
7619 it will be zero on the last iteration. Also skip if the biv is
7620 used between its update and the test insn. */
7623 {
7627 first_compare))
7629 }
7634 /* Look for the case where the basic induction variable is always
7635 nonnegative, and equals zero on the last iteration.
7636 In this case, add a reg_note REG_NONNEG, which allows the
7637 m68k DBRA instruction to be used. */
7645 {
7646 /* Initial value must be greater than 0,
7647 init_val % -dec_value == 0 to ensure that it equals zero on
7648 the last iteration */
7654 {
7655 /* register always nonnegative, add REG_NOTE to branch */
7662 }
7664 /* If the decrement is 1 and the value was tested as >= 0 before
7665 the loop, then we can safely optimize. */
7667 {
7680 {
7687 }
7688 }
7689 }
7691 {
7692 /* Try to change inc to dec, so can apply above optimization. */
7693 /* Can do this if:
7694 all registers modified are induction variables or invariant,
7695 all memory references have non-overlapping addresses
7696 (obviously true if only one write)
7697 allow 2 insns for the compare/jump at the end of the loop. */
7698 /* Also, we must avoid any instructions which use both the reversed
7699 biv and another biv. Such instructions will fail if the loop is
7700 reversed. We meet this condition by requiring that either
7701 no_use_except_counting is true, or else that there is only
7702 one biv. */
7704 /* 1 if the iteration var is used only to count iterations. */
7706 /* 1 if the loop has no memory store, or it has a single memory store
7707 which is reversible. */
7712 {
7715 /* If there are no givs for this biv, and the only exit is the
7716 fall through at the end of the loop, then
7717 see if perhaps there are no uses except to count. */
7721 {
7726 /* An insn that sets the biv is okay. */
7727 ;
7730 /* Don't bother about the end test. */
7731 ;
7733 {
7736 }
7737 }
7738 }
7743 {
7748 /* If the loop has a single store, and the destination address is
7749 invariant, then we can't reverse the loop, because this address
7750 might then have the wrong value at loop exit.
7751 This would work if the source was invariant also, however, in that
7752 case, the insn should have been moved out of the loop. */
7755 {
7758 reversible_mem_store
7759 = (! unknown_address_altered
7762 /* If the store depends on a register that is set after the
7763 store, it depends on the initial value, and is thus not
7764 reversible. */
7766 {
7772 }
7773 }
7774 }
7775 else
7778 /* This code only acts for innermost loops. Also it simplifies
7779 the memory address check by only reversing loops with
7780 zero or one memory access.
7781 Two memory accesses could involve parts of the same array,
7782 and that can't be reversed.
7783 If the biv is used only for counting, than we don't need to worry
7784 about all these things. */
7787 && !loop_has_call
7788 && !loop_has_volatile
7789 && reversible_mem_store
7794 {
7795 rtx tem;
7797 /* Loop can be reversed. */
7801 /* Now check other conditions:
7803 The increment must be a constant, as must the initial value,
7804 and the comparison code must be LT.
7806 This test can probably be improved since +/- 1 in the constant
7807 can be obtained by changing LT to LE and vice versa; this is
7808 confusing. */
7811 /* for constants, LE gets turned into LT */
7815 {
7826 comparison_const_width
7828 else
7829 comparison_const_width
7833 comparison_sign_mask
7836 /* If the comparison value is not a loop invariant, then we
7837 can not reverse this loop.
7839 ??? If the insns which initialize the comparison value as
7840 a whole compute an invariant result, then we could move
7841 them out of the loop and proceed with loop reversal. */
7849 /* Normalize the initial value if it is an integer and
7850 has no other use except as a counter. This will allow
7851 a few more loops to be reversed. */
7855 {
7857 /* The code below requires comparison_val to be a multiple
7858 of add_val in order to do the loop reversal, so
7859 round up comparison_val to a multiple of add_val.
7860 Since comparison_value is constant, we know that the
7861 current comparison code is LT. */
7863 comparison_val
7865 /* We postpone overflow checks for COMPARISON_VAL here;
7866 even if there is an overflow, we might still be able to
7867 reverse the loop, if converting the loop exit test to
7868 NE is possible. */
7870 }
7872 /* First check if we can do a vanilla loop reversal. */
7874 /* If we have a decrement_and_branch_on_count, prefer
7875 the NE test, since this will allow that instruction to
7876 be generated. Note that we must use a vanilla loop
7877 reversal if the biv is used to calculate a giv or has
7878 a non-counting use. */
7879 #if ! defined (HAVE_decrement_and_branch_until_zero) && defined (HAVE_decrement_and_branch_on_count)
7883 #endif
7885 /* Now do postponed overflow checks on COMPARISON_VAL. */
7888 {
7889 /* Register will always be nonnegative, with value
7890 0 on last iteration */
7894 }
7898 {
7901 }
7902 else
7908 /* If the initial value is not zero, or if the comparison
7909 value is not an exact multiple of the increment, then we
7910 can not reverse this loop. */
7913 {
7916 }
7917 else
7918 {
7921 }
7925 /* Reset these in case we normalized the initial value
7926 and comparison value above. */
7929 {
7931 final_value
7933 }
7936 /* Save some info needed to produce the new insns. */
7943 /* Set start_value; if this is not a CONST_INT, we need
7944 to generate a SUB.
7945 Initialize biv to start_value before loop start.
7946 The old initializing insn will be deleted as a
7947 dead store by flow.c. */
7950 {
7953 loop_start);
7954 }
7956 {
7959 enum insn_code icode
7966 start_value
7970 loop_start);
7974 }
7976 {
7978 enum insn_code icode
7986 start_value
7990 loop_start);
7991 }
7992 else
7993 /* We could handle the other cases too, but it'll be
7994 better to have a testcase first. */
7997 /* We may not have a single insn which can increment a reg, so
7998 create a sequence to hold all the insns from expand_inc. */
8007 /* Update biv info to reflect its new status. */
8012 /* Update loop info. */
8021 /* Inc LABEL_NUSES so that delete_insn will
8022 not delete the label. */
8025 /* Emit an insn after the end of the loop to set the biv's
8026 proper exit value if it is used anywhere outside the loop. */
8031 loop_end);
8033 /* Delete compare/branch at end of loop. */
8038 /* Add new compare/branch insn at end of loop. */
8050 ;
8056 {
8058 {
8059 /* Increment of LABEL_NUSES done above. */
8060 /* Register is now always nonnegative,
8061 so add REG_NONNEG note to the branch. */
8064 }
8066 }
8068 /* Mark that this biv has been reversed. Each giv which depends
8069 on this biv, and which is also live past the end of the loop
8070 will have to be fixed up. */
8075 {
8079 else
8081 }
8084 }
8085 }
8086 }
8089 }
8090 \f
8091 /* Verify whether the biv BL appears to be eliminable,
8092 based on the insns in the loop that refer to it.
8093 LOOP_START is the first insn of the loop, and END is the end insn.
8095 If ELIMINATE_P is non-zero, actually do the elimination.
8097 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8098 determine whether invariant insns should be placed inside or at the
8099 start of the loop. */
8101 static int
8104 rtx loop_start;
8105 rtx end;
8108 {
8110 rtx p;
8112 /* Scan all insns in the loop, stopping if we find one that uses the
8113 biv in a way that we cannot eliminate. */
8116 {
8120 /* If this is a libcall that sets a giv, skip ahead to its end. */
8122 {
8126 {
8131 {
8137 }
8138 }
8139 }
8143 {
8149 }
8150 }
8153 {
8158 }
8161 }
8162 \f
8163 /* INSN and REFERENCE are instructions in the same insn chain.
8164 Return non-zero if INSN is first. */
8166 int
8169 {
8173 {
8174 /* Start with test for not first so that INSN == REFERENCE yields not
8175 first. */
8189 }
8190 }
8192 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8193 the offset that we have to take into account due to auto-increment /
8194 div derivation is zero. */
8195 static int
8198 rtx insn;
8199 {
8200 /* If the giv V had the auto-inc address optimization applied
8201 to it, and INSN occurs between the giv insn and the biv
8202 insn, then we'd have to adjust the value used here.
8203 This is rare, so we don't bother to make this possible. */
8211 /* If the giv V was derived from another giv, and INSN does
8212 not occur between the giv insn and the biv insn, then we'd
8213 have to adjust the value used here. This is rare, so we don't
8214 bother to make this possible. */
8228 }
8230 /* If BL appears in X (part of the pattern of INSN), see if we can
8231 eliminate its use. If so, return 1. If not, return 0.
8233 If BIV does not appear in X, return 1.
8235 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
8236 where extra insns should be added. Depending on how many items have been
8237 moved out of the loop, it will either be before INSN or at the start of
8238 the loop. */
8240 static int
8245 rtx where;
8246 {
8252 #ifdef HAVE_cc0
8254 #endif
8260 {
8262 /* If we haven't already been able to do something with this BIV,
8263 we can't eliminate it. */
8269 /* If this sets the BIV, it is not a problem. */
8273 /* If this is an insn that defines a giv, it is also ok because
8274 it will go away when the giv is reduced. */
8279 #ifdef HAVE_cc0
8281 {
8282 /* Can replace with any giv that was reduced and
8283 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8284 Require a constant for MULT_VAL, so we know it's nonzero.
8285 ??? We disable this optimization to avoid potential
8286 overflows. */
8294 {
8301 /* If the giv has the opposite direction of change,
8302 then reverse the comparison. */
8306 else
8309 /* We can probably test that giv's reduced reg. */
8312 }
8314 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8315 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8316 Require a constant for MULT_VAL, so we know it's nonzero.
8317 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8318 overflow problem. */
8329 {
8336 /* If the giv has the opposite direction of change,
8337 then reverse the comparison. */
8341 else
8345 /* Replace biv with the giv's reduced register. */
8350 /* Insn doesn't support that constant or invariant. Copy it
8351 into a register (it will be a loop invariant.) */
8355 where);
8357 /* Substitute the new register for its invariant value in
8358 the compare expression. */
8362 }
8363 }
8364 #endif
8371 /* See if either argument is the biv. */
8376 else
8380 {
8381 /* First try to replace with any giv that has constant positive
8382 mult_val and constant add_val. We might be able to support
8383 negative mult_val, but it seems complex to do it in general. */
8394 {
8401 /* Replace biv with the giv's reduced reg. */
8404 /* If all constants are actually constant integers and
8405 the derived constant can be directly placed in the COMPARE,
8406 do so. */
8416 /* Otherwise, load it into a register. */
8422 /* If that failed, put back the change we made above. */
8424 }
8426 /* Look for giv with positive constant mult_val and nonconst add_val.
8427 Insert insns to calculate new compare value.
8428 ??? Turn this off due to possible overflow. */
8435 {
8436 rtx tem;
8446 /* Replace biv with giv's reduced register. */
8450 /* Compute value to compare against. */
8452 /* Use it in this insn. */
8456 }
8457 }
8459 {
8461 {
8462 /* Look for giv with constant positive mult_val and nonconst
8463 add_val. Insert insns to compute new compare value.
8464 ??? Turn this off due to possible overflow. */
8471 {
8472 rtx tem;
8482 /* Replace biv with giv's reduced register. */
8486 /* Compute value to compare against. */
8492 }
8493 }
8495 /* This code has problems. Basically, you can't know when
8496 seeing if we will eliminate BL, whether a particular giv
8497 of ARG will be reduced. If it isn't going to be reduced,
8498 we can't eliminate BL. We can try forcing it to be reduced,
8499 but that can generate poor code.
8501 The problem is that the benefit of reducing TV, below should
8502 be increased if BL can actually be eliminated, but this means
8503 we might have to do a topological sort of the order in which
8504 we try to process biv. It doesn't seem worthwhile to do
8505 this sort of thing now. */
8507 #if 0
8508 /* Otherwise the reg compared with had better be a biv. */
8513 /* Look for a pair of givs, one for each biv,
8514 with identical coefficients. */
8516 {
8527 {
8534 /* Replace biv with its giv's reduced reg. */
8536 /* Replace other operand with the other giv's
8537 reduced reg. */
8540 }
8541 }
8542 #endif
8543 }
8545 /* If we get here, the biv can't be eliminated. */
8549 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8550 biv is used in it, since it will be replaced. */
8558 }
8560 /* See if any subexpression fails elimination. */
8563 {
8565 {
8578 }
8579 }
8582 }
8583 \f
8584 /* Return nonzero if the last use of REG
8585 is in an insn following INSN in the same basic block. */
8587 static int
8589 rtx reg;
8590 rtx insn;
8591 {
8592 rtx n;
8596 {
8599 }
8601 }
8602 \f
8603 /* Called via `note_stores' to record the initial value of a biv. Here we
8604 just record the location of the set and process it later. */
8606 static void
8608 rtx dest;
8609 rtx set;
8610 {
8620 /* If this is the first set found, record it. */
8622 {
8625 }
8626 }
8627 \f
8628 /* If any of the registers in X are "old" and currently have a last use earlier
8629 than INSN, update them to have a last use of INSN. Their actual last use
8630 will be the previous insn but it will not have a valid uid_luid so we can't
8631 use it. */
8633 static void
8635 rtx x;
8636 rtx insn;
8637 {
8638 /* Check for the case where INSN does not have a valid luid. In this case,
8639 there is no need to modify the regno_last_uid, as this can only happen
8640 when code is inserted after the loop_end to set a pseudo's final value,
8641 and hence this insn will never be the last use of x. */
8646 else
8647 {
8651 {
8657 }
8658 }
8659 }
8660 \f
8661 /* Given a jump insn JUMP, return the condition that will cause it to branch
8662 to its JUMP_LABEL. If the condition cannot be understood, or is an
8663 inequality floating-point comparison which needs to be reversed, 0 will
8664 be returned.
8666 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8667 insn used in locating the condition was found. If a replacement test
8668 of the condition is desired, it should be placed in front of that
8669 insn and we will be sure that the inputs are still valid.
8671 The condition will be returned in a canonical form to simplify testing by
8672 callers. Specifically:
8674 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8675 (2) Both operands will be machine operands; (cc0) will have been replaced.
8676 (3) If an operand is a constant, it will be the second operand.
8677 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8678 for GE, GEU, and LEU. */
8680 rtx
8682 rtx jump;
8684 {
8687 rtx set;
8688 rtx tem;
8694 /* If this is not a standard conditional jump, we can't parse it. */
8707 /* If this branches to JUMP_LABEL when the condition is false, reverse
8708 the condition. */
8713 /* If we are comparing a register with zero, see if the register is set
8714 in the previous insn to a COMPARE or a comparison operation. Perform
8715 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8716 in cse.c */
8719 {
8720 /* Set non-zero when we find something of interest. */
8723 #ifdef HAVE_cc0
8724 /* If comparison with cc0, import actual comparison from compare
8725 insn. */
8727 {
8738 }
8739 #endif
8741 /* If this is a COMPARE, pick up the two things being compared. */
8743 {
8747 }
8751 /* Go back to the previous insn. Stop if it is not an INSN. We also
8752 stop if it isn't a single set or if it has a REG_INC note because
8753 we don't want to bother dealing with it. */
8761 /* If this is setting OP0, get what it sets it to if it looks
8762 relevant. */
8764 {
8767 /* ??? We may not combine comparisons done in a CCmode with
8768 comparisons not done in a CCmode. This is to aid targets
8769 like Alpha that have an IEEE compliant EQ instruction, and
8770 a non-IEEE compliant BEQ instruction. The use of CCmode is
8771 actually artificial, simply to prevent the combination, but
8772 should not affect other platforms.
8774 However, we must allow VOIDmode comparisons to match either
8775 CCmode or non-CCmode comparison, because some ports have
8776 modeless comparisons inside branch patterns.
8778 ??? This mode check should perhaps look more like the mode check
8779 in simplify_comparison in combine. */
8787 && (STORE_FLAG_VALUE
8790 #ifdef FLOAT_STORE_FLAG_VALUE
8794 #endif
8795 ))
8806 && (STORE_FLAG_VALUE
8809 #ifdef FLOAT_STORE_FLAG_VALUE
8813 #endif
8814 ))
8820 {
8821 /* We might have reversed a LT to get a GE here. But this wasn't
8822 actually the comparison of data, so we don't flag that we
8823 have had to reverse the condition. */
8827 }
8828 else
8830 }
8833 /* If this sets OP0, but not directly, we have to give up. */
8837 {
8841 {
8845 }
8850 }
8851 }
8853 /* If constant is first, put it last. */
8857 /* If OP0 is the result of a comparison, we weren't able to find what
8858 was really being compared, so fail. */
8862 /* Canonicalize any ordered comparison with integers involving equality
8863 if we can do computations in the relevant mode and we do not
8864 overflow. */
8869 {
8872 unsigned HOST_WIDE_INT max_val
8876 {
8882 /* When cross-compiling, const_val might be sign-extended from
8883 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8903 }
8904 }
8906 /* If this was floating-point and we reversed anything other than an
8907 EQ or NE, return zero. */
8910 && ! flag_fast_math
8914 #ifdef HAVE_cc0
8915 /* Never return CC0; return zero instead. */
8918 #endif
8921 }
8923 /* Similar to above routine, except that we also put an invariant last
8924 unless both operands are invariants. */
8926 rtx
8928 rtx x;
8929 {
8939 }
8941 #ifdef HAVE_decrement_and_branch_on_count
8942 /* Instrument loop for insertion of bct instruction. We distinguish between
8943 loops with compile-time bounds and those with run-time bounds.
8944 Information from loop_iterations() is used to compute compile-time bounds.
8945 Run-time bounds should use loop preconditioning, but currently ignored.
8946 */
8948 static void
8952 {
8958 /* If the loop condition is <= or >=, the number of iteration
8959 is 1 more than the range of the bounds of the loop. */
8966 /* It's impossible to instrument a competely unrolled loop. */
8970 /* Make sure that the count register is not in use. */
8972 {
8976 loop_num);
8978 }
8980 /* Make sure that the function has no indirect jumps. */
8982 {
8986 loop_num);
8988 }
8990 /* Make sure that the last loop insn is a conditional jump. */
8994 {
8998 loop_num);
9000 }
9002 /* Make sure that the loop does not contain a function call
9003 (the count register might be altered by the called function). */
9005 {
9009 loop_num);
9011 }
9013 /* Make sure that the loop does not jump via a table.
9014 (the count register might be used to perform the branch on table). */
9016 {
9020 loop_num);
9022 }
9024 /* Account for loop unrolling in instrumented iteration count. */
9027 else
9031 {
9032 /* Allow an enclosing outer loop to benefit if possible. */
9036 loop_num);
9038 }
9040 /* Try to instrument the loop. */
9042 /* Handle the simpler case, where the bounds are known at compile time. */
9044 {
9045 /* Mark all enclosing loops that they cannot use count register. */
9050 }
9052 /* Handle the more complex case, that the bounds are NOT known
9053 at compile time. In this case we generate run_time calculation
9054 of the number of iterations. */
9057 {
9061 loop_num);
9063 }
9067 {
9071 loop_num);
9073 }
9075 /* With runtime bounds, if the compare is of the form '!=' we give up */
9077 {
9081 loop_num);
9083 }
9084 /* Use common loop preconditioning code instead. */
9085 #if 0
9086 else
9087 {
9088 /* We rely on the existence of run-time guard to ensure that the
9089 loop executes at least once. */
9090 rtx sequence;
9091 rtx iterations_num_reg;
9093 unsigned HOST_WIDE_INT increment_value_abs
9096 /* make sure that the increment is a power of two, otherwise (an
9097 expensive) divide is needed. */
9099 {
9104 }
9106 /* compute the number of iterations */
9108 {
9109 rtx temp_reg;
9111 /* Again, the number of iterations is calculated by:
9112 ;
9113 ; compare-val - initial-val + (increment -1) + additional-iteration
9114 ; num_iterations = -----------------------------------------------------------------
9115 ; increment
9116 */
9117 /* ??? Do we have to call copy_rtx here before passing rtx to
9118 expand_binop? */
9120 {
9121 /* <, <= :the loop variable is increasing */
9125 }
9126 else
9127 {
9131 }
9140 {
9141 /* ??? This will generate an expensive divide instruction for
9142 most targets. The original authors apparently expected this
9143 to be a shift, since they test for power-of-2 divisors above,
9144 but just naively generating a divide instruction will not give
9145 a shift. It happens to work for the PowerPC target because
9146 the rs6000.md file has a divide pattern that emits shifts.
9147 It will probably not work for any other target. */
9149 temp_reg,
9152 }
9153 else
9155 }
9160 }
9164 }
9166 /* Instrument loop by inserting a bct in it as follows:
9167 1. A new counter register is created.
9168 2. In the head of the loop the new variable is initialized to the value
9169 passed in the loop_num_iterations parameter.
9170 3. At the end of the loop, comparison of the register with 0 is generated.
9171 The created comparison follows the pattern defined for the
9172 decrement_and_branch_on_count insn, so this insn will be generated.
9173 4. The branch on the old variable are deleted. The compare must remain
9174 because it might be used elsewhere. If the loop-variable or condition
9175 register are used elsewhere, they will be eliminated by flow. */
9177 static void
9180 rtx loop_num_iterations;
9181 {
9182 rtx counter_reg;
9183 rtx start_label;
9184 rtx sequence;
9187 {
9189 {
9194 else
9197 }
9199 /* Discard original jump to continue loop. Original compare result
9200 may still be live, so it cannot be discarded explicitly. */
9203 /* Insert the label which will delimit the start of the loop. */
9207 /* Insert initialization of the count register into the loop header. */
9215 /* Insert new comparison on the count register instead of the
9216 old one, generating the needed BCT pattern (that will be
9217 later recognized by assembly generation phase). */
9219 start_label),
9220 loop_end);
9222 }
9224 }
9227 /* Scan the function and determine whether it has indirect (computed) jumps.
9229 This is taken mostly from flow.c; similar code exists elsewhere
9230 in the compiler. It may be useful to put this into rtlanal.c. */
9231 static int
9233 rtx start;
9234 {
9235 rtx insn;
9242 }
9244 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9245 documentation for LOOP_MEMS for the definition of `appropriate'.
9246 This function is called from prescan_loop via for_each_rtx. */
9248 static int
9252 {
9260 {
9265 /* We're not interested in the MEM associated with a
9266 CONST_DOUBLE, so there's no need to traverse into this. */
9270 /* This is not a MEM. */
9272 }
9274 /* See if we've already seen this MEM. */
9277 {
9279 /* The modes of the two memory accesses are different. If
9280 this happens, something tricky is going on, and we just
9281 don't optimize accesses to this MEM. */
9285 }
9287 /* Resize the array, if necessary. */
9289 {
9292 else
9298 }
9300 /* Actually insert the MEM. */
9302 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9303 because we can't put it in a register. We still store it in the
9304 table, though, so that if we see the same address later, but in a
9305 non-BLK mode, we'll not think we can optimize it at that point. */
9311 }
9313 /* Like load_mems, but also ensures that SET_IN_LOOP,
9314 MAY_NOT_OPTIMIZE, REG_SINGLE_USAGE, and INSN_COUNT have the correct
9315 values after load_mems. */
9317 static void
9319 insn_count)
9320 rtx scan_start;
9321 rtx end;
9322 rtx loop_top;
9323 rtx start;
9325 {
9330 /* Recalculate set_in_loop and friends since load_mems may have
9331 created new registers. */
9333 {
9341 {
9342 /* Grow all the arrays. */
9347 }
9348 /* Clear the arrays */
9358 {
9361 }
9363 #ifdef AVOID_CCMODE_COPIES
9364 /* Don't try to move insns which set CC registers if we should not
9365 create CCmode register copies. */
9369 #endif
9371 /* Set n_times_set for the new registers. */
9375 }
9376 }
9378 /* Move MEMs into registers for the duration of the loop. SCAN_START
9379 is the first instruction in the loop (as it is executed). The
9380 other parameters are as for next_insn_in_loop. */
9382 static void
9384 rtx scan_start;
9385 rtx end;
9386 rtx loop_top;
9387 rtx start;
9388 {
9391 rtx p;
9393 rtx end_label;
9396 {
9397 /* Nonzero if the next instruction may never be executed. */
9400 /* Check to see if it's possible that some instructions in the
9401 loop are never executed. */
9405 {
9409 /* If we enter the loop in the middle, and scan
9410 around to the beginning, don't set maybe_never
9411 for that. This must be an unconditional jump,
9412 otherwise the code at the top of the loop might
9413 never be executed. Unconditional jumps are
9414 followed a by barrier then loop end. */
9419 {
9421 /* Something complicated. */
9423 else
9424 /* If there are any more instructions in the loop, they
9425 might not be reached. */
9427 }
9430 }
9432 /* Actually move the MEMs. */
9434 {
9436 rtx reg;
9438 rtx mem_list_entry;
9442 /* There's no telling whether or not MEM is modified. */
9445 /* Go through the MEMs written to in the loop to see if this
9446 one is aliased by one of them. */
9449 {
9454 {
9455 /* MEM is indeed aliased by this store. */
9458 }
9460 }
9462 /* If this MEM is written to, we must be sure that there
9463 are no reads from another MEM that aliases this one. */
9465 {
9469 {
9473 VOIDmode,
9475 rtx_varies_p))
9476 {
9477 /* It's not safe to hoist loop_mems[i] out of
9478 the loop because writes to it might not be
9479 seen by reads from loop_mems[j]. */
9482 }
9483 }
9484 }
9487 /* We can't access the MEM outside the loop; it might
9488 cause a trap that wouldn't have happened otherwise. */
9492 /* We thought we were going to lift this MEM out of the
9493 loop, but later discovered that we could not. */
9496 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9497 order to keep scan_loop from moving stores to this MEM
9498 out of the loop just because this REG is neither a
9499 user-variable nor used in the loop test. */
9504 /* Now, replace all references to the MEM with the
9505 corresponding pesudos. */
9509 {
9510 rtx_and_int ri;
9514 }
9517 /* We couldn't replace all occurrences of the MEM. */
9519 else
9520 {
9521 rtx set;
9523 /* Load the memory immediately before START, which is
9524 the NOTE_LOOP_BEG. */
9529 {
9531 {
9532 /* We must compute the former
9533 right-after-the-end label before we insert
9534 the new one. */
9538 }
9540 /* Store the memory immediately after END, which is
9541 the NOTE_LOOP_END. */
9544 }
9547 {
9552 }
9553 }
9554 }
9555 }
9558 {
9559 /* Now, we need to replace all references to the previous exit
9560 label with the new one. */
9561 rtx_pair rr;
9566 {
9569 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9570 field. This is not handled by for_each_rtx because it doesn't
9571 handle unprinted ('0') fields. We need to update JUMP_LABEL
9572 because the immediately following unroll pass will use it.
9573 replace_label would not work anyways, because that only handles
9574 LABEL_REFs. */
9577 }
9578 }
9579 }
9581 /* Replace MEM with its associated pseudo register. This function is
9582 called from load_mems via for_each_rtx. DATA is actually an
9583 rtx_and_int * describing the instruction currently being scanned
9584 and the MEM we are currently replacing. */
9586 static int
9590 {
9592 rtx insn;
9600 {
9605 /* We're not interested in the MEM associated with a
9606 CONST_DOUBLE, so there's no need to traverse into one. */
9610 /* This is not a MEM. */
9612 }
9618 /* This is not the MEM we are currently replacing. */
9623 /* Actually replace the MEM. */
9627 }
9629 /* Replace occurrences of the old exit label for the loop with the new
9630 one. DATA is an rtx_pair containing the old and new labels,
9631 respectively. */
9633 static int
9637 {
9656 }