1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
62 #define STAB_CODE_TYPE enum __stab_debug_code
64 #define STAB_CODE_TYPE int
67 extern tree lookup_name
PARAMS ((tree
));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
89 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
90 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
92 static int m16_check_op
PARAMS ((rtx
, int, int, int));
93 static void block_move_loop
PARAMS ((rtx
, rtx
,
97 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
98 static rtx mips_add_large_offset_to_sp
PARAMS ((HOST_WIDE_INT
,
100 static void mips_annotate_frame_insn
PARAMS ((rtx
, rtx
));
101 static rtx mips_frame_set
PARAMS ((enum machine_mode
,
103 static void mips_emit_frame_related_store
PARAMS ((rtx
, rtx
,
105 static void save_restore_insns
PARAMS ((int, rtx
,
107 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
108 static void mips16_fp_args
PARAMS ((FILE *, int, int));
109 static void build_mips16_function_stub
PARAMS ((FILE *));
110 static void mips16_optimize_gp
PARAMS ((rtx
));
111 static rtx add_constant
PARAMS ((struct constant
**,
114 static void dump_constants
PARAMS ((struct constant
*,
116 static rtx mips_find_symbol
PARAMS ((rtx
));
117 static void abort_with_insn
PARAMS ((rtx
, const char *))
119 static int symbolic_expression_p
PARAMS ((rtx
));
120 static void mips_add_gc_roots
PARAMS ((void));
121 static bool mips_assemble_integer
PARAMS ((rtx
, unsigned int, int));
122 static void mips_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
123 static void mips_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
124 static enum processor_type mips_parse_cpu
PARAMS ((const char *));
125 static void copy_file_data
PARAMS ((FILE *, FILE *));
127 static void iris6_asm_named_section_1
PARAMS ((const char *,
130 static void iris6_asm_named_section
PARAMS ((const char *,
132 static int iris_section_align_entry_eq
PARAMS ((const PTR
, const PTR
));
133 static hashval_t iris_section_align_entry_hash
PARAMS ((const PTR
));
134 static int iris6_section_align_1
PARAMS ((void **, void *));
136 static int mips_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
138 /* Global variables for machine-dependent things. */
140 /* Threshold for data being put into the small data/bss area, instead
141 of the normal data area (references to the small data/bss area take
142 1 instruction, and use the global pointer, references to the normal
143 data area takes 2 instructions). */
144 int mips_section_threshold
= -1;
146 /* Count the number of .file directives, so that .loc is up to date. */
147 int num_source_filenames
= 0;
149 /* Count the number of sdb related labels are generated (to find block
150 start and end boundaries). */
151 int sdb_label_count
= 0;
153 /* Next label # for each statement for Silicon Graphics IRIS systems. */
156 /* Non-zero if inside of a function, because the stupid MIPS asm can't
157 handle .files inside of functions. */
158 int inside_function
= 0;
160 /* Files to separate the text and the data output, so that all of the data
161 can be emitted before the text, which will mean that the assembler will
162 generate smaller code, based on the global pointer. */
163 FILE *asm_out_data_file
;
164 FILE *asm_out_text_file
;
166 /* Linked list of all externals that are to be emitted when optimizing
167 for the global pointer if they haven't been declared by the end of
168 the program with an appropriate .comm or initialization. */
172 struct extern_list
*next
; /* next external */
173 const char *name
; /* name of the external */
174 int size
; /* size in bytes */
177 /* Name of the file containing the current function. */
178 const char *current_function_file
= "";
180 /* Warning given that Mips ECOFF can't support changing files
181 within a function. */
182 int file_in_function_warning
= FALSE
;
184 /* Whether to suppress issuing .loc's because the user attempted
185 to change the filename within a function. */
186 int ignore_line_number
= FALSE
;
188 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
194 /* The next branch instruction is a branch likely, not branch normal. */
195 int mips_branch_likely
;
197 /* Count of delay slots and how many are filled. */
198 int dslots_load_total
;
199 int dslots_load_filled
;
200 int dslots_jump_total
;
201 int dslots_jump_filled
;
203 /* # of nops needed by previous insn */
204 int dslots_number_nops
;
206 /* Number of 1/2/3 word references to data items (ie, not jal's). */
209 /* registers to check for load delay */
210 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
212 /* Cached operands, and operator to compare for use in set/branch/trap
213 on condition codes. */
216 /* what type of branch to use */
217 enum cmp_type branch_type
;
219 /* Number of previously seen half-pic pointers and references. */
220 static int prev_half_pic_ptrs
= 0;
221 static int prev_half_pic_refs
= 0;
223 /* The target cpu for code generation. */
224 enum processor_type mips_arch
;
226 /* The target cpu for optimization and scheduling. */
227 enum processor_type mips_tune
;
229 /* which instruction set architecture to use. */
232 /* which abi to use. */
235 /* Strings to hold which cpu and instruction set architecture to use. */
236 const char *mips_cpu_string
; /* for -mcpu=<xxx> */
237 const char *mips_arch_string
; /* for -march=<xxx> */
238 const char *mips_tune_string
; /* for -mtune=<xxx> */
239 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
240 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
242 /* Whether we are generating mips16 code. This is a synonym for
243 TARGET_MIPS16, and exists for use as an attribute. */
246 /* This variable is set by -mno-mips16. We only care whether
247 -mno-mips16 appears or not, and using a string in this fashion is
248 just a way to avoid using up another bit in target_flags. */
249 const char *mips_no_mips16_string
;
251 /* This is only used to determine if an type size setting option was
252 explicitly specified (-mlong64, -mint64, -mlong32). The specs
253 set this option if such an option is used. */
254 const char *mips_explicit_type_size_string
;
256 /* Whether we are generating mips16 hard float code. In mips16 mode
257 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
258 -msoft-float was not specified by the user, which means that we
259 should arrange to call mips32 hard floating point code. */
260 int mips16_hard_float
;
262 /* This variable is set by -mentry. We only care whether -mentry
263 appears or not, and using a string in this fashion is just a way to
264 avoid using up another bit in target_flags. */
265 const char *mips_entry_string
;
267 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
269 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
272 /* If TRUE, we split addresses into their high and low parts in the RTL. */
273 int mips_split_addresses
;
275 /* Generating calls to position independent functions? */
276 enum mips_abicalls_type mips_abicalls
;
278 /* High and low marks for floating point values which we will accept
279 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
280 initialized in override_options. */
281 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
283 /* Mode used for saving/restoring general purpose registers. */
284 static enum machine_mode gpr_mode
;
286 /* Array giving truth value on whether or not a given hard register
287 can support a given mode. */
288 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
290 /* Current frame information calculated by compute_frame_size. */
291 struct mips_frame_info current_frame_info
;
293 /* Zero structure to initialize current_frame_info. */
294 struct mips_frame_info zero_frame_info
;
296 /* Pseudo-reg holding the address of the current function when
297 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
298 by mips_finalize_pic if it was created. */
299 rtx embedded_pic_fnaddr_rtx
;
301 /* The length of all strings seen when compiling for the mips16. This
302 is used to tell how many strings are in the constant pool, so that
303 we can see if we may have an overflow. This is reset each time the
304 constant pool is output. */
305 int mips_string_length
;
307 /* Pseudo-reg holding the value of $28 in a mips16 function which
308 refers to GP relative global variables. */
309 rtx mips16_gp_pseudo_rtx
;
311 /* In mips16 mode, we build a list of all the string constants we see
312 in a particular function. */
314 struct string_constant
316 struct string_constant
*next
;
320 static struct string_constant
*string_constants
;
322 /* List of all MIPS punctuation characters used by print_operand. */
323 char mips_print_operand_punct
[256];
325 /* Map GCC register number to debugger register number. */
326 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
328 /* Buffer to use to enclose a load/store operation with %{ %} to
329 turn on .set volatile. */
330 static char volatile_buffer
[60];
332 /* Hardware names for the registers. If -mrnames is used, this
333 will be overwritten with mips_sw_reg_names. */
335 char mips_reg_names
[][8] =
337 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
338 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
339 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
340 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
341 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
342 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
343 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
344 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
345 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
346 "$fcc5","$fcc6","$fcc7","$rap"
349 /* Mips software names for the registers, used to overwrite the
350 mips_reg_names array. */
352 static const char mips_sw_reg_names
[][8] =
354 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
355 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
356 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
357 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
358 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
359 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
360 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
361 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
362 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
363 "$fcc5","$fcc6","$fcc7","$rap"
366 /* Map hard register number to register class */
367 const enum reg_class mips_regno_to_class
[] =
369 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
370 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
371 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
372 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
373 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
374 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
375 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
376 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
377 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
378 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
379 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
380 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
381 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
382 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
383 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
384 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
385 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
386 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
387 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
390 /* Map register constraint character to register class. */
391 enum reg_class mips_char_to_class
[256] =
393 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
394 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
395 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
396 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
397 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
398 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
399 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
400 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
401 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
402 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
403 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
404 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
405 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
406 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
407 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
408 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
409 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
410 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
411 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
412 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
413 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
414 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
415 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
416 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
417 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
418 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
419 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
420 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
421 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
422 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
423 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
424 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
425 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
426 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
427 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
428 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
429 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
430 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
431 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
432 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
433 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
434 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
435 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
436 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
437 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
438 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
439 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
440 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
441 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
442 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
443 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
444 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
445 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
446 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
447 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
448 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
449 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
450 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
451 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
452 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
453 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
454 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
455 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
456 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
459 /* Initialize the GCC target structure. */
460 #undef TARGET_ASM_ALIGNED_HI_OP
461 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
462 #undef TARGET_ASM_ALIGNED_SI_OP
463 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
464 #undef TARGET_ASM_INTEGER
465 #define TARGET_ASM_INTEGER mips_assemble_integer
467 #if TARGET_IRIX5 && !TARGET_IRIX6
468 #undef TARGET_ASM_UNALIGNED_HI_OP
469 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
470 #undef TARGET_ASM_UNALIGNED_SI_OP
471 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
474 #undef TARGET_ASM_FUNCTION_PROLOGUE
475 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
476 #undef TARGET_ASM_FUNCTION_EPILOGUE
477 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
479 #undef TARGET_SCHED_ADJUST_COST
480 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
482 struct gcc_target targetm
= TARGET_INITIALIZER
;
484 /* Return truth value of whether OP can be used as an operands
485 where a register or 16 bit unsigned integer is needed. */
488 uns_arith_operand (op
, mode
)
490 enum machine_mode mode
;
492 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
495 return register_operand (op
, mode
);
498 /* Return truth value of whether OP can be used as an operands
499 where a 16 bit integer is needed */
502 arith_operand (op
, mode
)
504 enum machine_mode mode
;
506 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
509 /* On the mips16, a GP relative value is a signed 16 bit offset. */
510 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
513 return register_operand (op
, mode
);
516 /* Return truth value of whether OP can be used as an operand in a two
517 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
520 arith32_operand (op
, mode
)
522 enum machine_mode mode
;
524 if (GET_CODE (op
) == CONST_INT
)
527 return register_operand (op
, mode
);
530 /* Return truth value of whether OP is an integer which fits in 16 bits. */
535 enum machine_mode mode ATTRIBUTE_UNUSED
;
537 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
540 /* Return truth value of whether OP is a 32 bit integer which is too big to
541 be loaded with one instruction. */
546 enum machine_mode mode ATTRIBUTE_UNUSED
;
550 if (GET_CODE (op
) != CONST_INT
)
555 /* ior reg,$r0,value */
556 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
559 /* subu reg,$r0,value */
560 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
563 /* lui reg,value>>16 */
564 if ((value
& 0x0000ffff) == 0)
570 /* Return truth value of whether OP is a register or the constant 0.
571 In mips16 mode, we only accept a register, since the mips16 does
575 reg_or_0_operand (op
, mode
)
577 enum machine_mode mode
;
579 switch (GET_CODE (op
))
584 return INTVAL (op
) == 0;
589 return op
== CONST0_RTX (mode
);
593 return register_operand (op
, mode
);
602 /* Return truth value of whether OP is a register or the constant 0,
603 even in mips16 mode. */
606 true_reg_or_0_operand (op
, mode
)
608 enum machine_mode mode
;
610 switch (GET_CODE (op
))
613 return INTVAL (op
) == 0;
616 return op
== CONST0_RTX (mode
);
620 return register_operand (op
, mode
);
629 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
632 mips_const_double_ok (op
, mode
)
634 enum machine_mode mode
;
638 if (GET_CODE (op
) != CONST_DOUBLE
)
641 if (mode
== VOIDmode
)
644 if (mode
!= SFmode
&& mode
!= DFmode
)
647 if (op
== CONST0_RTX (mode
))
650 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
651 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
654 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
656 if (REAL_VALUE_ISNAN (d
))
659 if (REAL_VALUE_NEGATIVE (d
))
660 d
= REAL_VALUE_NEGATE (d
);
664 if (REAL_VALUES_LESS (d
, dfhigh
)
665 && REAL_VALUES_LESS (dflow
, d
))
670 if (REAL_VALUES_LESS (d
, sfhigh
)
671 && REAL_VALUES_LESS (sflow
, d
))
678 /* Accept the floating point constant 1 in the appropriate mode. */
681 const_float_1_operand (op
, mode
)
683 enum machine_mode mode
;
686 static REAL_VALUE_TYPE onedf
;
687 static REAL_VALUE_TYPE onesf
;
688 static int one_initialized
;
690 if (GET_CODE (op
) != CONST_DOUBLE
691 || mode
!= GET_MODE (op
)
692 || (mode
!= DFmode
&& mode
!= SFmode
))
695 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
697 /* We only initialize these values if we need them, since we will
698 never get called unless mips_isa >= 4. */
699 if (! one_initialized
)
701 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
702 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
707 return REAL_VALUES_EQUAL (d
, onedf
);
709 return REAL_VALUES_EQUAL (d
, onesf
);
712 /* Return true if a memory load or store of REG plus OFFSET in MODE
713 can be represented in a single word on the mips16. */
716 mips16_simple_memory_operand (reg
, offset
, mode
)
719 enum machine_mode mode
;
726 /* We can't tell, because we don't know how the value will
727 eventually be accessed. Returning 0 here does no great
728 harm; it just prevents some possible instruction scheduling. */
732 size
= GET_MODE_SIZE (mode
);
734 if (INTVAL (offset
) % size
!= 0)
736 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
740 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < (HOST_WIDE_INT
)(off
* size
))
745 /* Return truth value if a memory operand fits in a single instruction
746 (ie, register + small offset). */
749 simple_memory_operand (op
, mode
)
751 enum machine_mode mode
;
753 rtx addr
, plus0
, plus1
;
755 /* Eliminate non-memory operations */
756 if (GET_CODE (op
) != MEM
)
759 /* dword operations really put out 2 instructions, so eliminate them. */
760 /* ??? This isn't strictly correct. It is OK to accept multiword modes
761 here, since the length attributes are being set correctly, but only
762 if the address is offsettable. LO_SUM is not offsettable. */
763 if (GET_MODE_SIZE (GET_MODE (op
)) > (unsigned) UNITS_PER_WORD
)
766 /* Decode the address now. */
768 switch (GET_CODE (addr
))
777 return SMALL_INT (addr
);
780 plus0
= XEXP (addr
, 0);
781 plus1
= XEXP (addr
, 1);
782 if (GET_CODE (plus0
) == REG
783 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
785 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
788 else if (GET_CODE (plus1
) == REG
789 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
791 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
798 /* We used to allow small symbol refs here (ie, stuff in .sdata
799 or .sbss), but this causes some bugs in G++. Also, it won't
800 interfere if the MIPS linker rewrites the store instruction
801 because the function is PIC. */
803 case LABEL_REF
: /* never gp relative */
807 /* If -G 0, we can never have a GP relative memory operation.
808 Also, save some time if not optimizing. */
813 rtx offset
= const0_rtx
;
814 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
815 if (GET_CODE (op
) != SYMBOL_REF
)
818 /* let's be paranoid.... */
819 if (! SMALL_INT (offset
))
826 return SYMBOL_REF_FLAG (addr
);
829 /* This SYMBOL_REF case is for the mips16. If the above case is
830 reenabled, this one should be merged in. */
832 /* References to the constant pool on the mips16 use a small
833 offset if the function is small. The only time we care about
834 getting this right is during delayed branch scheduling, so
835 don't need to check until then. The machine_dependent_reorg
836 function will set the total length of the instructions used
837 in the function in current_frame_info. If that is small
838 enough, we know for sure that this is a small offset. It
839 would be better if we could take into account the location of
840 the instruction within the function, but we can't, because we
841 don't know where we are. */
843 && CONSTANT_POOL_ADDRESS_P (addr
)
844 && current_frame_info
.insns_len
> 0)
848 size
= current_frame_info
.insns_len
+ get_pool_size ();
849 if (GET_MODE_SIZE (mode
) == 4)
850 return size
< 4 * 0x100;
851 else if (GET_MODE_SIZE (mode
) == 8)
852 return size
< 8 * 0x20;
866 /* Return nonzero for a memory address that can be used to load or store
870 double_memory_operand (op
, mode
)
872 enum machine_mode mode
;
874 if (GET_CODE (op
) != MEM
875 || ! memory_operand (op
, mode
))
877 /* During reload, we accept a pseudo register if it has an
878 appropriate memory address. If we don't do this, we will
879 wind up reloading into a register, and then reloading that
880 register from memory, when we could just reload directly from
882 if (reload_in_progress
883 && GET_CODE (op
) == REG
884 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
885 && reg_renumber
[REGNO (op
)] < 0
886 && reg_equiv_mem
[REGNO (op
)] != 0
887 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
890 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
891 the same test performed for 'm' in find_reloads. */
893 if (reload_in_progress
895 && (GET_CODE (op
) == MEM
896 || (GET_CODE (op
) == REG
897 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
898 && reg_renumber
[REGNO (op
)] < 0)))
901 if (reload_in_progress
903 && GET_CODE (op
) == MEM
)
909 /* During reload on the mips16, we accept a large offset
910 from the frame pointer or the stack pointer. This large
911 address will get reloaded anyhow. */
912 if (GET_CODE (addr
) == PLUS
913 && GET_CODE (XEXP (addr
, 0)) == REG
914 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
915 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
916 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
917 && ! SMALL_INT (XEXP (addr
, 1)))
918 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
919 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
922 /* Similarly, we accept a case where the memory address is
923 itself on the stack, and will be reloaded. */
924 if (GET_CODE (addr
) == MEM
)
928 maddr
= XEXP (addr
, 0);
929 if (GET_CODE (maddr
) == PLUS
930 && GET_CODE (XEXP (maddr
, 0)) == REG
931 && (REGNO (XEXP (maddr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
932 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
933 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
934 && ! SMALL_INT (XEXP (maddr
, 1)))
935 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
936 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
940 /* We also accept the same case when we have a 16 bit signed
941 offset mixed in as well. The large address will get
942 reloaded, and the 16 bit offset will be OK. */
943 if (GET_CODE (addr
) == PLUS
944 && GET_CODE (XEXP (addr
, 0)) == MEM
945 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
946 && SMALL_INT (XEXP (addr
, 1)))
948 addr
= XEXP (XEXP (addr
, 0), 0);
949 if (GET_CODE (addr
) == PLUS
950 && GET_CODE (XEXP (addr
, 0)) == REG
951 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
952 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
953 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
954 && ! SMALL_INT (XEXP (addr
, 1)))
955 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
956 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
966 /* In this case we can use an instruction like sd. */
970 /* Make sure that 4 added to the address is a valid memory address.
971 This essentially just checks for overflow in an added constant. */
973 if (CONSTANT_ADDRESS_P (XEXP (op
, 0)))
976 op
= adjust_address_nv (op
, GET_MODE_CLASS (mode
) == MODE_INT
977 ? SImode
: SFmode
, 4);
978 return memory_address_p (GET_MODE (op
), XEXP (op
, 0));
981 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
984 equality_op (op
, mode
)
986 enum machine_mode mode
;
988 if (mode
!= GET_MODE (op
))
991 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
994 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
999 enum machine_mode mode
;
1001 if (mode
!= GET_MODE (op
))
1004 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
1007 /* Return nonzero if the code is a relational operation suitable for a
1008 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1009 We need this in the insn that expands `trap_if' in order to prevent
1010 combine from erroneously altering the condition. */
1013 trap_cmp_op (op
, mode
)
1015 enum machine_mode mode
;
1017 if (mode
!= GET_MODE (op
))
1020 switch (GET_CODE (op
))
1035 /* Return nonzero if the operand is either the PC or a label_ref. */
1038 pc_or_label_operand (op
, mode
)
1040 enum machine_mode mode ATTRIBUTE_UNUSED
;
1045 if (GET_CODE (op
) == LABEL_REF
)
1051 /* Test for a valid operand for a call instruction.
1052 Don't allow the arg pointer register or virtual regs
1053 since they may change into reg + const, which the patterns
1054 can't handle yet. */
1057 call_insn_operand (op
, mode
)
1059 enum machine_mode mode ATTRIBUTE_UNUSED
;
1061 return (CONSTANT_ADDRESS_P (op
)
1062 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
1063 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1064 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
1067 /* Return nonzero if OPERAND is valid as a source operand for a move
1071 move_operand (op
, mode
)
1073 enum machine_mode mode
;
1075 /* Accept any general operand after reload has started; doing so
1076 avoids losing if reload does an in-place replacement of a register
1077 with a SYMBOL_REF or CONST. */
1078 return (general_operand (op
, mode
)
1079 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1080 || reload_in_progress
|| reload_completed
)
1082 && GET_CODE (op
) == SYMBOL_REF
1083 && ! mips16_constant (op
, mode
, 1, 0)));
1086 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1087 This accepts not only general_operand, but also sign extended
1088 constants and registers. We need to accept sign extended constants
1089 in case a sign extended register which is used in an expression,
1090 and is equivalent to a constant, is spilled. */
1093 movdi_operand (op
, mode
)
1095 enum machine_mode mode
;
1099 && GET_CODE (op
) == SIGN_EXTEND
1100 && GET_MODE (op
) == DImode
1101 && (GET_MODE (XEXP (op
, 0)) == SImode
1102 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
1103 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
1104 && (register_operand (XEXP (op
, 0), SImode
)
1105 || immediate_operand (XEXP (op
, 0), SImode
)))
1108 return (general_operand (op
, mode
)
1110 && GET_CODE (op
) == SYMBOL_REF
1111 && ! mips16_constant (op
, mode
, 1, 0)));
1114 /* Like register_operand, but when in 64 bit mode also accept a sign
1115 extend of a 32 bit register, since the value is known to be already
1119 se_register_operand (op
, mode
)
1121 enum machine_mode mode
;
1125 && GET_CODE (op
) == SIGN_EXTEND
1126 && GET_MODE (op
) == DImode
1127 && GET_MODE (XEXP (op
, 0)) == SImode
1128 && register_operand (XEXP (op
, 0), SImode
))
1131 return register_operand (op
, mode
);
1134 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1135 extend of a 32 bit register, since the value is known to be already
1139 se_reg_or_0_operand (op
, mode
)
1141 enum machine_mode mode
;
1145 && GET_CODE (op
) == SIGN_EXTEND
1146 && GET_MODE (op
) == DImode
1147 && GET_MODE (XEXP (op
, 0)) == SImode
1148 && register_operand (XEXP (op
, 0), SImode
))
1151 return reg_or_0_operand (op
, mode
);
1154 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1155 extend of a 32 bit register, since the value is known to be already
1159 se_uns_arith_operand (op
, mode
)
1161 enum machine_mode mode
;
1165 && GET_CODE (op
) == SIGN_EXTEND
1166 && GET_MODE (op
) == DImode
1167 && GET_MODE (XEXP (op
, 0)) == SImode
1168 && register_operand (XEXP (op
, 0), SImode
))
1171 return uns_arith_operand (op
, mode
);
1174 /* Like arith_operand, but when in 64 bit mode also accept a sign
1175 extend of a 32 bit register, since the value is known to be already
1179 se_arith_operand (op
, mode
)
1181 enum machine_mode mode
;
1185 && GET_CODE (op
) == SIGN_EXTEND
1186 && GET_MODE (op
) == DImode
1187 && GET_MODE (XEXP (op
, 0)) == SImode
1188 && register_operand (XEXP (op
, 0), SImode
))
1191 return arith_operand (op
, mode
);
1194 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1195 extend of a 32 bit register, since the value is known to be already
1199 se_nonmemory_operand (op
, mode
)
1201 enum machine_mode mode
;
1205 && GET_CODE (op
) == SIGN_EXTEND
1206 && GET_MODE (op
) == DImode
1207 && GET_MODE (XEXP (op
, 0)) == SImode
1208 && register_operand (XEXP (op
, 0), SImode
))
1211 return nonmemory_operand (op
, mode
);
1214 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1215 sign extend of a 32 bit register, since the value is known to be
1216 already sign extended. */
1219 se_nonimmediate_operand (op
, mode
)
1221 enum machine_mode mode
;
1225 && GET_CODE (op
) == SIGN_EXTEND
1226 && GET_MODE (op
) == DImode
1227 && GET_MODE (XEXP (op
, 0)) == SImode
1228 && register_operand (XEXP (op
, 0), SImode
))
1231 return nonimmediate_operand (op
, mode
);
1234 /* Accept any operand that can appear in a mips16 constant table
1235 instruction. We can't use any of the standard operand functions
1236 because for these instructions we accept values that are not
1237 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1240 consttable_operand (op
, mode
)
1242 enum machine_mode mode ATTRIBUTE_UNUSED
;
1244 return CONSTANT_P (op
);
1247 /* Return nonzero if we split the address into high and low parts. */
1249 /* ??? We should also handle reg+array somewhere. We get four
1250 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1251 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1252 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1253 out of the address, then we have 4 instructions to combine. Perhaps
1254 add a 3->2 define_split for combine. */
1256 /* ??? We could also split a CONST_INT here if it is a large_int().
1257 However, it doesn't seem to be very useful to have %hi(constant).
1258 We would be better off by doing the masking ourselves and then putting
1259 the explicit high part of the constant in the RTL. This will give better
1260 optimization. Also, %hi(constant) needs assembler changes to work.
1261 There is already a define_split that does this. */
1264 mips_check_split (address
, mode
)
1266 enum machine_mode mode
;
1268 /* ??? This is the same check used in simple_memory_operand.
1269 We use it here because LO_SUM is not offsettable. */
1270 if (GET_MODE_SIZE (mode
) > (unsigned) UNITS_PER_WORD
)
1273 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1274 || (GET_CODE (address
) == CONST
1275 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1276 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1277 || GET_CODE (address
) == LABEL_REF
)
1283 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1286 mips_reg_mode_ok_for_base_p (reg
, mode
, strict
)
1288 enum machine_mode mode
;
1292 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg
), mode
)
1293 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg
), mode
));
1296 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1297 returns a nonzero value if XINSN is a legitimate address for a
1298 memory operand of the indicated MODE. STRICT is non-zero if this
1299 function is called during reload. */
1302 mips_legitimate_address_p (mode
, xinsn
, strict
)
1303 enum machine_mode mode
;
1307 if (TARGET_DEBUG_B_MODE
)
1309 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1310 strict
? "" : "not ");
1311 GO_DEBUG_RTX (xinsn
);
1314 /* Check for constant before stripping off SUBREG, so that we don't
1315 accept (subreg (const_int)) which will fail to reload. */
1316 if (CONSTANT_ADDRESS_P (xinsn
)
1317 && ! (mips_split_addresses
&& mips_check_split (xinsn
, mode
))
1318 && (! TARGET_MIPS16
|| mips16_constant (xinsn
, mode
, 1, 0)))
1321 while (GET_CODE (xinsn
) == SUBREG
)
1322 xinsn
= SUBREG_REG (xinsn
);
1324 /* The mips16 can only use the stack pointer as a base register when
1325 loading SImode or DImode values. */
1326 if (GET_CODE (xinsn
) == REG
1327 && mips_reg_mode_ok_for_base_p (xinsn
, mode
, strict
))
1330 if (GET_CODE (xinsn
) == LO_SUM
&& mips_split_addresses
)
1332 register rtx xlow0
= XEXP (xinsn
, 0);
1333 register rtx xlow1
= XEXP (xinsn
, 1);
1335 while (GET_CODE (xlow0
) == SUBREG
)
1336 xlow0
= SUBREG_REG (xlow0
);
1337 if (GET_CODE (xlow0
) == REG
1338 && mips_reg_mode_ok_for_base_p (xlow0
, mode
, strict
)
1339 && mips_check_split (xlow1
, mode
))
1343 if (GET_CODE (xinsn
) == PLUS
)
1345 register rtx xplus0
= XEXP (xinsn
, 0);
1346 register rtx xplus1
= XEXP (xinsn
, 1);
1347 register enum rtx_code code0
;
1348 register enum rtx_code code1
;
1350 while (GET_CODE (xplus0
) == SUBREG
)
1351 xplus0
= SUBREG_REG (xplus0
);
1352 code0
= GET_CODE (xplus0
);
1354 while (GET_CODE (xplus1
) == SUBREG
)
1355 xplus1
= SUBREG_REG (xplus1
);
1356 code1
= GET_CODE (xplus1
);
1358 /* The mips16 can only use the stack pointer as a base register
1359 when loading SImode or DImode values. */
1361 && mips_reg_mode_ok_for_base_p (xplus0
, mode
, strict
))
1363 if (code1
== CONST_INT
&& SMALL_INT (xplus1
))
1366 /* On the mips16, we represent GP relative offsets in RTL.
1367 These are 16 bit signed values, and can serve as register
1370 && mips16_gp_offset_p (xplus1
))
1373 /* For some code sequences, you actually get better code by
1374 pretending that the MIPS supports an address mode of a
1375 constant address + a register, even though the real
1376 machine doesn't support it. This is because the
1377 assembler can use $r1 to load just the high 16 bits, add
1378 in the register, and fold the low 16 bits into the memory
1379 reference, whereas the compiler generates a 4 instruction
1380 sequence. On the other hand, CSE is not as effective.
1381 It would be a win to generate the lui directly, but the
1382 MIPS assembler does not have syntax to generate the
1383 appropriate relocation. */
1385 /* Also accept CONST_INT addresses here, so no else. */
1386 /* Reject combining an embedded PIC text segment reference
1387 with a register. That requires an additional
1389 /* ??? Reject combining an address with a register for the MIPS
1390 64 bit ABI, because the SGI assembler can not handle this. */
1391 if (!TARGET_DEBUG_A_MODE
1392 && (mips_abi
== ABI_32
1393 || mips_abi
== ABI_O64
1394 || mips_abi
== ABI_EABI
)
1395 && CONSTANT_ADDRESS_P (xplus1
)
1396 && ! mips_split_addresses
1397 && (!TARGET_EMBEDDED_PIC
1399 || GET_CODE (XEXP (xplus1
, 0)) != MINUS
)
1400 /* When assembling for machines with 64 bit registers,
1401 the assembler will sign-extend the constant "foo"
1402 in "la x, foo(x)" yielding the wrong result for:
1403 (set (blah:DI) (plus x y)). */
1405 || (code1
== CONST_INT
1406 && trunc_int_for_mode (INTVAL (xplus1
),
1407 SImode
) == INTVAL (xplus1
)))
1413 if (TARGET_DEBUG_B_MODE
)
1414 GO_PRINTF ("Not a legitimate address\n");
1416 /* The address was not legitimate. */
1421 /* We need a lot of little routines to check constant values on the
1422 mips16. These are used to figure out how long the instruction will
1423 be. It would be much better to do this using constraints, but
1424 there aren't nearly enough letters available. */
1427 m16_check_op (op
, low
, high
, mask
)
1433 return (GET_CODE (op
) == CONST_INT
1434 && INTVAL (op
) >= low
1435 && INTVAL (op
) <= high
1436 && (INTVAL (op
) & mask
) == 0);
1440 m16_uimm3_b (op
, mode
)
1442 enum machine_mode mode ATTRIBUTE_UNUSED
;
1444 return m16_check_op (op
, 0x1, 0x8, 0);
1448 m16_simm4_1 (op
, mode
)
1450 enum machine_mode mode ATTRIBUTE_UNUSED
;
1452 return m16_check_op (op
, - 0x8, 0x7, 0);
1456 m16_nsimm4_1 (op
, mode
)
1458 enum machine_mode mode ATTRIBUTE_UNUSED
;
1460 return m16_check_op (op
, - 0x7, 0x8, 0);
1464 m16_simm5_1 (op
, mode
)
1466 enum machine_mode mode ATTRIBUTE_UNUSED
;
1468 return m16_check_op (op
, - 0x10, 0xf, 0);
1472 m16_nsimm5_1 (op
, mode
)
1474 enum machine_mode mode ATTRIBUTE_UNUSED
;
1476 return m16_check_op (op
, - 0xf, 0x10, 0);
1480 m16_uimm5_4 (op
, mode
)
1482 enum machine_mode mode ATTRIBUTE_UNUSED
;
1484 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1488 m16_nuimm5_4 (op
, mode
)
1490 enum machine_mode mode ATTRIBUTE_UNUSED
;
1492 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1496 m16_simm8_1 (op
, mode
)
1498 enum machine_mode mode ATTRIBUTE_UNUSED
;
1500 return m16_check_op (op
, - 0x80, 0x7f, 0);
1504 m16_nsimm8_1 (op
, mode
)
1506 enum machine_mode mode ATTRIBUTE_UNUSED
;
1508 return m16_check_op (op
, - 0x7f, 0x80, 0);
1512 m16_uimm8_1 (op
, mode
)
1514 enum machine_mode mode ATTRIBUTE_UNUSED
;
1516 return m16_check_op (op
, 0x0, 0xff, 0);
1520 m16_nuimm8_1 (op
, mode
)
1522 enum machine_mode mode ATTRIBUTE_UNUSED
;
1524 return m16_check_op (op
, - 0xff, 0x0, 0);
1528 m16_uimm8_m1_1 (op
, mode
)
1530 enum machine_mode mode ATTRIBUTE_UNUSED
;
1532 return m16_check_op (op
, - 0x1, 0xfe, 0);
1536 m16_uimm8_4 (op
, mode
)
1538 enum machine_mode mode ATTRIBUTE_UNUSED
;
1540 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1544 m16_nuimm8_4 (op
, mode
)
1546 enum machine_mode mode ATTRIBUTE_UNUSED
;
1548 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1552 m16_simm8_8 (op
, mode
)
1554 enum machine_mode mode ATTRIBUTE_UNUSED
;
1556 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1560 m16_nsimm8_8 (op
, mode
)
1562 enum machine_mode mode ATTRIBUTE_UNUSED
;
1564 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1567 /* References to the string table on the mips16 only use a small
1568 offset if the function is small. See the comment in the SYMBOL_REF
1569 case in simple_memory_operand. We can't check for LABEL_REF here,
1570 because the offset is always large if the label is before the
1571 referencing instruction. */
1574 m16_usym8_4 (op
, mode
)
1576 enum machine_mode mode ATTRIBUTE_UNUSED
;
1578 if (GET_CODE (op
) == SYMBOL_REF
1579 && SYMBOL_REF_FLAG (op
)
1580 && current_frame_info
.insns_len
> 0
1581 && XSTR (op
, 0)[0] == '*'
1582 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1583 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1584 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1587 struct string_constant
*l
;
1589 /* Make sure this symbol is on thelist of string constants to be
1590 output for this function. It is possible that it has already
1591 been output, in which case this requires a large offset. */
1592 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1593 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1601 m16_usym5_4 (op
, mode
)
1603 enum machine_mode mode ATTRIBUTE_UNUSED
;
1605 if (GET_CODE (op
) == SYMBOL_REF
1606 && SYMBOL_REF_FLAG (op
)
1607 && current_frame_info
.insns_len
> 0
1608 && XSTR (op
, 0)[0] == '*'
1609 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1610 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1611 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1614 struct string_constant
*l
;
1616 /* Make sure this symbol is on thelist of string constants to be
1617 output for this function. It is possible that it has already
1618 been output, in which case this requires a large offset. */
1619 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1620 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1627 /* Returns an operand string for the given instruction's delay slot,
1628 after updating filled delay slot statistics.
1630 We assume that operands[0] is the target register that is set.
1632 In order to check the next insn, most of this functionality is moved
1633 to FINAL_PRESCAN_INSN, and we just set the global variables that
1636 /* ??? This function no longer does anything useful, because final_prescan_insn
1637 now will never emit a nop. */
1640 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1641 const char *ret
; /* normal string to return */
1642 enum delay_type type
; /* type of delay */
1643 rtx operands
[]; /* operands to use */
1644 rtx cur_insn
; /* current insn */
1646 register rtx set_reg
;
1647 register enum machine_mode mode
;
1648 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1649 register int num_nops
;
1651 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1654 else if (type
== DELAY_HILO
)
1660 /* Make sure that we don't put nop's after labels. */
1661 next_insn
= NEXT_INSN (cur_insn
);
1662 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1663 next_insn
= NEXT_INSN (next_insn
);
1665 dslots_load_total
+= num_nops
;
1666 if (TARGET_DEBUG_F_MODE
1668 || type
== DELAY_NONE
1672 || GET_CODE (next_insn
) == CODE_LABEL
1673 || (set_reg
= operands
[0]) == 0)
1675 dslots_number_nops
= 0;
1683 set_reg
= operands
[0];
1687 while (GET_CODE (set_reg
) == SUBREG
)
1688 set_reg
= SUBREG_REG (set_reg
);
1690 mode
= GET_MODE (set_reg
);
1691 dslots_number_nops
= num_nops
;
1692 mips_load_reg
= set_reg
;
1693 if (GET_MODE_SIZE (mode
)
1694 > (unsigned) (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1695 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1699 if (type
== DELAY_HILO
)
1701 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1702 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1714 /* Determine whether a memory reference takes one (based off of the GP
1715 pointer), two (normal), or three (label + reg) instructions, and bump the
1716 appropriate counter for -mstats. */
1719 mips_count_memory_refs (op
, num
)
1725 rtx addr
, plus0
, plus1
;
1726 enum rtx_code code0
, code1
;
1729 if (TARGET_DEBUG_B_MODE
)
1731 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1735 /* Skip MEM if passed, otherwise handle movsi of address. */
1736 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1738 /* Loop, going through the address RTL. */
1742 switch (GET_CODE (addr
))
1750 plus0
= XEXP (addr
, 0);
1751 plus1
= XEXP (addr
, 1);
1752 code0
= GET_CODE (plus0
);
1753 code1
= GET_CODE (plus1
);
1763 if (code0
== CONST_INT
)
1778 if (code1
== CONST_INT
)
1785 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1792 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1802 n_words
= 2; /* always 2 words */
1806 addr
= XEXP (addr
, 0);
1811 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1823 n_words
+= additional
;
1827 num_refs
[n_words
-1] += num
;
1831 /* Return RTL for the offset from the current function to the argument.
1833 ??? Which argument is this? */
1836 embedded_pic_offset (x
)
1839 if (embedded_pic_fnaddr_rtx
== NULL
)
1843 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1845 /* Output code at function start to initialize the pseudo-reg. */
1846 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1847 inline functions, because it is called after RTL for the function
1848 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1849 does not get copied, and ends up not matching the rest of the RTL.
1850 This solution works, but means that we get unnecessary code to
1851 initialize this value every time a function is inlined into another
1854 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1855 XEXP (DECL_RTL (current_function_decl
), 0)));
1856 seq
= gen_sequence ();
1858 push_topmost_sequence ();
1859 emit_insn_after (seq
, get_insns ());
1860 pop_topmost_sequence ();
1864 gen_rtx_CONST (Pmode
,
1865 gen_rtx_MINUS (Pmode
, x
,
1866 XEXP (DECL_RTL (current_function_decl
), 0)));
1869 /* Return the appropriate instructions to move one operand to another. */
1872 mips_move_1word (operands
, insn
, unsignedp
)
1877 const char *ret
= 0;
1878 rtx op0
= operands
[0];
1879 rtx op1
= operands
[1];
1880 enum rtx_code code0
= GET_CODE (op0
);
1881 enum rtx_code code1
= GET_CODE (op1
);
1882 enum machine_mode mode
= GET_MODE (op0
);
1883 int subreg_offset0
= 0;
1884 int subreg_offset1
= 0;
1885 enum delay_type delay
= DELAY_NONE
;
1887 while (code0
== SUBREG
)
1889 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
1890 GET_MODE (SUBREG_REG (op0
)),
1893 op0
= SUBREG_REG (op0
);
1894 code0
= GET_CODE (op0
);
1897 while (code1
== SUBREG
)
1899 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
1900 GET_MODE (SUBREG_REG (op1
)),
1903 op1
= SUBREG_REG (op1
);
1904 code1
= GET_CODE (op1
);
1907 /* For our purposes, a condition code mode is the same as SImode. */
1913 int regno0
= REGNO (op0
) + subreg_offset0
;
1917 int regno1
= REGNO (op1
) + subreg_offset1
;
1919 /* Just in case, don't do anything for assigning a register
1920 to itself, unless we are filling a delay slot. */
1921 if (regno0
== regno1
&& set_nomacro
== 0)
1924 else if (GP_REG_P (regno0
))
1926 if (GP_REG_P (regno1
))
1927 ret
= "move\t%0,%1";
1929 else if (MD_REG_P (regno1
))
1932 if (regno1
!= HILO_REGNUM
)
1938 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
1939 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1944 if (FP_REG_P (regno1
))
1945 ret
= "mfc1\t%0,%1";
1947 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
1948 ret
= "cfc1\t%0,$31";
1952 else if (FP_REG_P (regno0
))
1954 if (GP_REG_P (regno1
))
1957 ret
= "mtc1\t%1,%0";
1960 if (FP_REG_P (regno1
))
1961 ret
= "mov.s\t%0,%1";
1964 else if (MD_REG_P (regno0
))
1966 if (GP_REG_P (regno1
))
1969 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
1974 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
1976 if (GP_REG_P (regno1
))
1979 ret
= "ctc1\t%0,$31";
1984 else if (code1
== MEM
)
1989 mips_count_memory_refs (op1
, 1);
1991 if (GP_REG_P (regno0
))
1993 /* For loads, use the mode of the memory item, instead of the
1994 target, so zero/sign extend can use this code as well. */
1995 switch (GET_MODE (op1
))
2004 ret
= ((unsignedp
&& TARGET_64BIT
)
2009 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
2012 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
2017 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
2020 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
2022 size_t i
= strlen (ret
);
2023 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2026 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2027 ret
= volatile_buffer
;
2031 else if (code1
== CONST_INT
2032 || (code1
== CONST_DOUBLE
2033 && GET_MODE (op1
) == VOIDmode
))
2035 if (code1
== CONST_DOUBLE
)
2037 /* This can happen when storing constants into long long
2038 bitfields. Just store the least significant word of
2040 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2043 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2045 if (GP_REG_P (regno0
))
2046 ret
= "move\t%0,%z1";
2048 else if (FP_REG_P (regno0
))
2051 ret
= "mtc1\t%z1,%0";
2054 else if (MD_REG_P (regno0
))
2061 else if (GP_REG_P (regno0
))
2063 /* Don't use X format, because that will give out of
2064 range numbers for 64 bit host and 32 bit target. */
2065 if (! TARGET_MIPS16
)
2066 ret
= "li\t%0,%1\t\t\t# %X1";
2069 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2071 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2072 ret
= "li\t%0,%n1\n\tneg\t%0";
2077 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
2079 if (op1
== CONST0_RTX (SFmode
))
2081 if (GP_REG_P (regno0
))
2082 ret
= "move\t%0,%.";
2084 else if (FP_REG_P (regno0
))
2087 ret
= "mtc1\t%.,%0";
2094 ret
= "li.s\t%0,%1";
2098 else if (code1
== LABEL_REF
)
2101 mips_count_memory_refs (op1
, 1);
2106 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2108 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
2110 rtx offset
= const0_rtx
;
2112 if (GET_CODE (op1
) == CONST
)
2113 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
2115 if (GET_CODE (op1
) == SYMBOL_REF
)
2117 operands
[2] = HALF_PIC_PTR (op1
);
2120 mips_count_memory_refs (operands
[2], 1);
2122 if (INTVAL (offset
) == 0)
2125 ret
= (unsignedp
&& TARGET_64BIT
2131 dslots_load_total
++;
2132 operands
[3] = offset
;
2133 if (unsignedp
&& TARGET_64BIT
)
2134 ret
= (SMALL_INT (offset
)
2135 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2136 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2138 ret
= (SMALL_INT (offset
)
2139 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2140 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2144 else if (TARGET_MIPS16
2146 && GET_CODE (XEXP (op1
, 0)) == REG
2147 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2149 /* This case arises on the mips16; see
2150 mips16_gp_pseudo_reg. */
2151 ret
= "move\t%0,%+";
2153 else if (TARGET_MIPS16
2154 && code1
== SYMBOL_REF
2155 && SYMBOL_REF_FLAG (op1
)
2156 && (XSTR (op1
, 0)[0] != '*'
2157 || strncmp (XSTR (op1
, 0) + 1,
2159 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2161 /* This can occur when reloading the address of a GP
2162 relative symbol on the mips16. */
2163 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2168 mips_count_memory_refs (op1
, 1);
2174 else if (code1
== PLUS
)
2176 rtx add_op0
= XEXP (op1
, 0);
2177 rtx add_op1
= XEXP (op1
, 1);
2179 if (GET_CODE (XEXP (op1
, 1)) == REG
2180 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
2181 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
2183 operands
[2] = add_op0
;
2184 operands
[3] = add_op1
;
2185 ret
= "add%:\t%0,%2,%3";
2188 else if (code1
== HIGH
)
2190 operands
[1] = XEXP (op1
, 0);
2191 ret
= "lui\t%0,%%hi(%1)";
2195 else if (code0
== MEM
)
2198 mips_count_memory_refs (op0
, 1);
2202 int regno1
= REGNO (op1
) + subreg_offset1
;
2204 if (GP_REG_P (regno1
))
2208 case SFmode
: ret
= "sw\t%1,%0"; break;
2209 case SImode
: ret
= "sw\t%1,%0"; break;
2210 case HImode
: ret
= "sh\t%1,%0"; break;
2211 case QImode
: ret
= "sb\t%1,%0"; break;
2216 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2220 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2224 case SFmode
: ret
= "sw\t%z1,%0"; break;
2225 case SImode
: ret
= "sw\t%z1,%0"; break;
2226 case HImode
: ret
= "sh\t%z1,%0"; break;
2227 case QImode
: ret
= "sb\t%z1,%0"; break;
2232 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2236 case SFmode
: ret
= "sw\t%.,%0"; break;
2237 case SImode
: ret
= "sw\t%.,%0"; break;
2238 case HImode
: ret
= "sh\t%.,%0"; break;
2239 case QImode
: ret
= "sb\t%.,%0"; break;
2244 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2246 size_t i
= strlen (ret
);
2248 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2251 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2252 ret
= volatile_buffer
;
2258 abort_with_insn (insn
, "bad move");
2262 if (delay
!= DELAY_NONE
)
2263 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2269 /* Return the appropriate instructions to move 2 words */
2272 mips_move_2words (operands
, insn
)
2276 const char *ret
= 0;
2277 rtx op0
= operands
[0];
2278 rtx op1
= operands
[1];
2279 enum rtx_code code0
= GET_CODE (operands
[0]);
2280 enum rtx_code code1
= GET_CODE (operands
[1]);
2281 int subreg_offset0
= 0;
2282 int subreg_offset1
= 0;
2283 enum delay_type delay
= DELAY_NONE
;
2285 while (code0
== SUBREG
)
2287 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2288 GET_MODE (SUBREG_REG (op0
)),
2291 op0
= SUBREG_REG (op0
);
2292 code0
= GET_CODE (op0
);
2295 if (code1
== SIGN_EXTEND
)
2297 op1
= XEXP (op1
, 0);
2298 code1
= GET_CODE (op1
);
2301 while (code1
== SUBREG
)
2303 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2304 GET_MODE (SUBREG_REG (op1
)),
2307 op1
= SUBREG_REG (op1
);
2308 code1
= GET_CODE (op1
);
2312 if (GET_CODE (operands
[1]) == SIGN_EXTEND
2314 && code1
!= CONST_INT
2315 /* The following three can happen as the result of a questionable
2317 && code1
!= LABEL_REF
2318 && code1
!= SYMBOL_REF
2324 int regno0
= REGNO (op0
) + subreg_offset0
;
2328 int regno1
= REGNO (op1
) + subreg_offset1
;
2330 /* Just in case, don't do anything for assigning a register
2331 to itself, unless we are filling a delay slot. */
2332 if (regno0
== regno1
&& set_nomacro
== 0)
2335 else if (FP_REG_P (regno0
))
2337 if (FP_REG_P (regno1
))
2338 ret
= "mov.d\t%0,%1";
2346 abort_with_insn (insn
, "bad move");
2348 #ifdef TARGET_FP_CALL_32
2349 if (FP_CALL_GP_REG_P (regno1
))
2350 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2353 ret
= "dmtc1\t%1,%0";
2356 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2360 else if (FP_REG_P (regno1
))
2366 abort_with_insn (insn
, "bad move");
2368 #ifdef TARGET_FP_CALL_32
2369 if (FP_CALL_GP_REG_P (regno0
))
2370 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2373 ret
= "dmfc1\t%0,%1";
2376 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2379 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2384 if (regno0
!= HILO_REGNUM
)
2386 else if (regno1
== 0)
2387 ret
= "mtlo\t%.\n\tmthi\t%.";
2390 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2393 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2398 if (regno1
!= HILO_REGNUM
)
2402 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2405 else if (TARGET_64BIT
)
2406 ret
= "move\t%0,%1";
2408 else if (regno0
!= (regno1
+1))
2409 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2412 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2415 else if (code1
== CONST_DOUBLE
)
2417 /* Move zero from $0 unless !TARGET_64BIT and recipient
2418 is 64-bit fp reg, in which case generate a constant. */
2419 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2420 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2422 if (GET_MODE (op1
) == DFmode
)
2426 #ifdef TARGET_FP_CALL_32
2427 if (FP_CALL_GP_REG_P (regno0
))
2429 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2431 split_double (op1
, operands
+ 2, operands
+ 3);
2432 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2435 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2439 /* GNU as emits 64-bit code for li.d if the ISA is 3
2440 or higher. For !TARGET_64BIT && gp registers we
2441 need to avoid this by using two li instructions
2443 if (ISA_HAS_64BIT_REGS
2445 && ! FP_REG_P (regno0
))
2447 split_double (op1
, operands
+ 2, operands
+ 3);
2448 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2451 ret
= "li.d\t%0,%1";
2454 else if (TARGET_64BIT
)
2456 if (! TARGET_MIPS16
)
2462 split_double (op1
, operands
+ 2, operands
+ 3);
2463 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2469 if (GP_REG_P (regno0
))
2471 #ifdef TARGET_FP_CALL_32
2472 && ! FP_CALL_GP_REG_P (regno0
)
2475 : "move\t%0,%.\n\tmove\t%D0,%.");
2477 else if (FP_REG_P (regno0
))
2482 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2487 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2489 if (GP_REG_P (regno0
))
2492 : "move\t%0,%.\n\tmove\t%D0,%.");
2494 else if (FP_REG_P (regno0
))
2501 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2503 else if (MD_REG_P (regno0
))
2506 ret
= (regno0
== HILO_REGNUM
2507 ? "mtlo\t%.\n\tmthi\t%."
2512 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2513 && GP_REG_P (regno0
))
2519 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2521 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2522 ret
= "li\t%0,%n1\n\tneg\t%0";
2524 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2525 ret
= "li\t%0,%1\t\t# %X1";
2526 else if (HOST_BITS_PER_WIDE_INT
< 64)
2527 /* We can't use 'X' for negative numbers, because then we won't
2528 get the right value for the upper 32 bits. */
2529 ret
= (INTVAL (op1
) < 0
2530 ? "dli\t%0,%1\t\t\t# %X1"
2531 : "dli\t%0,%X1\t\t# %1");
2533 /* We must use 'X', because otherwise LONG_MIN will print as
2534 a number that the assembler won't accept. */
2535 ret
= "dli\t%0,%X1\t\t# %1";
2537 else if (HOST_BITS_PER_WIDE_INT
< 64)
2539 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2542 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2543 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2544 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2546 operands
[2] = GEN_INT (1);
2547 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2551 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2555 /* We use multiple shifts here, to avoid warnings about out
2556 of range shifts on 32 bit hosts. */
2557 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2559 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2560 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2564 else if (code1
== MEM
)
2569 mips_count_memory_refs (op1
, 2);
2571 if (FP_REG_P (regno0
))
2574 else if (TARGET_64BIT
)
2577 #ifdef TARGET_FP_CALL_32
2578 if (FP_CALL_GP_REG_P (regno0
))
2579 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2580 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2581 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2587 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2588 ret
= (reg_mentioned_p (op0
, op1
)
2589 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2590 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2592 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2594 size_t i
= strlen (ret
);
2596 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2599 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2600 ret
= volatile_buffer
;
2604 else if (code1
== LABEL_REF
)
2607 mips_count_memory_refs (op1
, 2);
2609 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2610 /* We deliberately remove the 'a' from '%1', so that we don't
2611 have to add SIGN_EXTEND support to print_operand_address.
2612 print_operand will just call print_operand_address in this
2613 case, so there is no problem. */
2616 ret
= "dla\t%0,%a1";
2618 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2622 && GET_CODE (XEXP (op1
, 0)) == REG
2623 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2625 /* This case arises on the mips16; see
2626 mips16_gp_pseudo_reg. */
2627 ret
= "move\t%0,%+";
2629 else if (TARGET_MIPS16
2630 && code1
== SYMBOL_REF
2631 && SYMBOL_REF_FLAG (op1
)
2632 && (XSTR (op1
, 0)[0] != '*'
2633 || strncmp (XSTR (op1
, 0) + 1,
2635 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2637 /* This can occur when reloading the address of a GP
2638 relative symbol on the mips16. */
2639 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2644 mips_count_memory_refs (op1
, 2);
2646 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2647 /* We deliberately remove the 'a' from '%1', so that we don't
2648 have to add SIGN_EXTEND support to print_operand_address.
2649 print_operand will just call print_operand_address in this
2650 case, so there is no problem. */
2653 ret
= "dla\t%0,%a1";
2658 else if (code0
== MEM
)
2662 int regno1
= REGNO (op1
) + subreg_offset1
;
2664 if (FP_REG_P (regno1
))
2667 else if (TARGET_64BIT
)
2670 #ifdef TARGET_FP_CALL_32
2671 if (FP_CALL_GP_REG_P (regno1
))
2672 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2678 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2679 ret
= "sw\t%1,%0\n\tsw\t%D1,%D0";
2682 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2683 || (code1
== CONST_DOUBLE
2684 && op1
== CONST0_RTX (GET_MODE (op1
))))
2686 || double_memory_operand (op0
, GET_MODE (op0
))))
2691 ret
= "sw\t%.,%0\n\tsw\t%.,%D0";
2695 mips_count_memory_refs (op0
, 2);
2697 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2699 size_t i
= strlen (ret
);
2701 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2704 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2705 ret
= volatile_buffer
;
2711 abort_with_insn (insn
, "bad move");
2715 if (delay
!= DELAY_NONE
)
2716 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2721 /* Provide the costs of an addressing mode that contains ADDR.
2722 If ADDR is not a valid address, its cost is irrelevant. */
2725 mips_address_cost (addr
)
2728 switch (GET_CODE (addr
))
2738 rtx offset
= const0_rtx
;
2739 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
2740 if (GET_CODE (addr
) == LABEL_REF
)
2743 if (GET_CODE (addr
) != SYMBOL_REF
)
2746 if (! SMALL_INT (offset
))
2750 /* ... fall through ... */
2753 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
2757 register rtx plus0
= XEXP (addr
, 0);
2758 register rtx plus1
= XEXP (addr
, 1);
2760 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
2761 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
2763 if (GET_CODE (plus0
) != REG
)
2766 switch (GET_CODE (plus1
))
2769 return SMALL_INT (plus1
) ? 1 : 2;
2776 return mips_address_cost (plus1
) + 1;
2790 /* Return nonzero if X is an address which needs a temporary register when
2791 reloaded while generating PIC code. */
2794 pic_address_needs_scratch (x
)
2797 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2798 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2799 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2800 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2801 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2807 /* Make normal rtx_code into something we can index from an array */
2809 static enum internal_test
2810 map_test_to_internal_test (test_code
)
2811 enum rtx_code test_code
;
2813 enum internal_test test
= ITEST_MAX
;
2817 case EQ
: test
= ITEST_EQ
; break;
2818 case NE
: test
= ITEST_NE
; break;
2819 case GT
: test
= ITEST_GT
; break;
2820 case GE
: test
= ITEST_GE
; break;
2821 case LT
: test
= ITEST_LT
; break;
2822 case LE
: test
= ITEST_LE
; break;
2823 case GTU
: test
= ITEST_GTU
; break;
2824 case GEU
: test
= ITEST_GEU
; break;
2825 case LTU
: test
= ITEST_LTU
; break;
2826 case LEU
: test
= ITEST_LEU
; break;
2834 /* Generate the code to compare two integer values. The return value is:
2835 (reg:SI xx) The pseudo register the comparison is in
2836 0 No register, generate a simple branch.
2838 ??? This is called with result nonzero by the Scond patterns in
2839 mips.md. These patterns are called with a target in the mode of
2840 the Scond instruction pattern. Since this must be a constant, we
2841 must use SImode. This means that if RESULT is non-zero, it will
2842 always be an SImode register, even if TARGET_64BIT is true. We
2843 cope with this by calling convert_move rather than emit_move_insn.
2844 This will sometimes lead to an unnecessary extension of the result;
2856 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2857 enum rtx_code test_code
; /* relational test (EQ, etc) */
2858 rtx result
; /* result to store comp. or 0 if branch */
2859 rtx cmp0
; /* first operand to compare */
2860 rtx cmp1
; /* second operand to compare */
2861 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2862 /* to reverse its test */
2866 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2867 int const_low
; /* low bound of constant we can accept */
2868 int const_high
; /* high bound of constant we can accept */
2869 int const_add
; /* constant to add (convert LE -> LT) */
2870 int reverse_regs
; /* reverse registers in test */
2871 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2872 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2873 int unsignedp
; /* != 0 for unsigned comparisons. */
2876 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2878 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2879 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2880 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2881 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2882 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2883 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2884 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2885 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2886 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2887 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2890 enum internal_test test
;
2891 enum machine_mode mode
;
2892 struct cmp_info
*p_info
;
2899 test
= map_test_to_internal_test (test_code
);
2900 if (test
== ITEST_MAX
)
2903 p_info
= &info
[(int) test
];
2904 eqne_p
= (p_info
->test_code
== XOR
);
2906 mode
= GET_MODE (cmp0
);
2907 if (mode
== VOIDmode
)
2908 mode
= GET_MODE (cmp1
);
2910 /* Eliminate simple branches */
2911 branch_p
= (result
== 0);
2914 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2916 /* Comparisons against zero are simple branches */
2917 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
2918 && (! TARGET_MIPS16
|| eqne_p
))
2921 /* Test for beq/bne. */
2922 if (eqne_p
&& ! TARGET_MIPS16
)
2926 /* allocate a pseudo to calculate the value in. */
2927 result
= gen_reg_rtx (mode
);
2930 /* Make sure we can handle any constants given to us. */
2931 if (GET_CODE (cmp0
) == CONST_INT
)
2932 cmp0
= force_reg (mode
, cmp0
);
2934 if (GET_CODE (cmp1
) == CONST_INT
)
2936 HOST_WIDE_INT value
= INTVAL (cmp1
);
2938 if (value
< p_info
->const_low
2939 || value
> p_info
->const_high
2940 /* ??? Why? And why wasn't the similar code below modified too? */
2942 && HOST_BITS_PER_WIDE_INT
< 64
2943 && p_info
->const_add
!= 0
2944 && ((p_info
->unsignedp
2945 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2946 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
2947 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2948 != (p_info
->const_add
> 0))))
2949 cmp1
= force_reg (mode
, cmp1
);
2952 /* See if we need to invert the result. */
2953 invert
= (GET_CODE (cmp1
) == CONST_INT
2954 ? p_info
->invert_const
: p_info
->invert_reg
);
2956 if (p_invert
!= (int *)0)
2962 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2963 Comparison between two registers, may involve switching operands. */
2964 if (GET_CODE (cmp1
) == CONST_INT
)
2966 if (p_info
->const_add
!= 0)
2968 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2970 /* If modification of cmp1 caused overflow,
2971 we would get the wrong answer if we follow the usual path;
2972 thus, x > 0xffffffffU would turn into x > 0U. */
2973 if ((p_info
->unsignedp
2974 ? (unsigned HOST_WIDE_INT
) new >
2975 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
2976 : new > INTVAL (cmp1
))
2977 != (p_info
->const_add
> 0))
2979 /* This test is always true, but if INVERT is true then
2980 the result of the test needs to be inverted so 0 should
2981 be returned instead. */
2982 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2986 cmp1
= GEN_INT (new);
2990 else if (p_info
->reverse_regs
)
2997 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
3001 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
3002 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
3005 if (test
== ITEST_NE
)
3007 if (! TARGET_MIPS16
)
3009 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
3010 if (p_invert
!= NULL
)
3016 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3017 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
3022 else if (test
== ITEST_EQ
)
3024 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3025 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
3033 if (! TARGET_MIPS16
)
3037 /* The value is in $24. Copy it to another register, so
3038 that reload doesn't think it needs to store the $24 and
3039 the input to the XOR in the same location. */
3040 reg2
= gen_reg_rtx (mode
);
3041 emit_move_insn (reg2
, reg
);
3043 one
= force_reg (mode
, const1_rtx
);
3045 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
3051 /* Emit the common code for doing conditional branches.
3052 operand[0] is the label to jump to.
3053 The comparison operands are saved away by cmp{si,di,sf,df}. */
3056 gen_conditional_branch (operands
, test_code
)
3058 enum rtx_code test_code
;
3060 enum cmp_type type
= branch_type
;
3061 rtx cmp0
= branch_cmp
[0];
3062 rtx cmp1
= branch_cmp
[1];
3063 enum machine_mode mode
;
3072 mode
= type
== CMP_SI
? SImode
: DImode
;
3074 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
3082 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
3083 /* We don't want to build a comparison against a non-zero
3085 cmp1
= force_reg (mode
, cmp1
);
3092 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
3094 reg
= gen_reg_rtx (CCmode
);
3096 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3097 0 in the instruction built below. The MIPS FPU handles
3098 inequality testing by testing for equality and looking for a
3100 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3101 gen_rtx (test_code
== NE
? EQ
: test_code
,
3102 CCmode
, cmp0
, cmp1
)));
3104 test_code
= test_code
== NE
? EQ
: NE
;
3112 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
3115 /* Generate the branch. */
3117 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
3126 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3127 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3128 gen_rtx (test_code
, mode
,
3133 /* Emit the common code for conditional moves. OPERANDS is the array
3134 of operands passed to the conditional move defined_expand. */
3137 gen_conditional_move (operands
)
3140 rtx op0
= branch_cmp
[0];
3141 rtx op1
= branch_cmp
[1];
3142 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3143 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
3144 enum rtx_code move_code
= NE
;
3145 enum machine_mode op_mode
= GET_MODE (operands
[0]);
3146 enum machine_mode cmp_mode
;
3149 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3168 op0
= force_reg (mode
, branch_cmp
[1]);
3169 op1
= branch_cmp
[0];
3173 op0
= force_reg (mode
, branch_cmp
[1]);
3174 op1
= branch_cmp
[0];
3185 op0
= force_reg (mode
, branch_cmp
[1]);
3186 op1
= branch_cmp
[0];
3190 op0
= force_reg (mode
, branch_cmp
[1]);
3191 op1
= branch_cmp
[0];
3198 else if (cmp_code
== NE
)
3199 cmp_code
= EQ
, move_code
= EQ
;
3201 if (mode
== SImode
|| mode
== DImode
)
3203 else if (mode
== SFmode
|| mode
== DFmode
)
3208 cmp_reg
= gen_reg_rtx (cmp_mode
);
3209 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
3210 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
3212 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
3213 gen_rtx_IF_THEN_ELSE (op_mode
,
3214 gen_rtx (move_code
, VOIDmode
,
3216 CONST0_RTX (SImode
)),
3217 operands
[2], operands
[3])));
3220 /* Emit the common code for conditional moves. OPERANDS is the array
3221 of operands passed to the conditional move defined_expand. */
3224 mips_gen_conditional_trap (operands
)
3228 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3229 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3231 /* MIPS conditional trap machine instructions don't have GT or LE
3232 flavors, so we must invert the comparison and convert to LT and
3233 GE, respectively. */
3236 case GT
: cmp_code
= LT
; break;
3237 case LE
: cmp_code
= GE
; break;
3238 case GTU
: cmp_code
= LTU
; break;
3239 case LEU
: cmp_code
= GEU
; break;
3242 if (cmp_code
== GET_CODE (operands
[0]))
3244 op0
= force_reg (mode
, branch_cmp
[0]);
3245 op1
= branch_cmp
[1];
3249 op0
= force_reg (mode
, branch_cmp
[1]);
3250 op1
= branch_cmp
[0];
3252 if (GET_CODE (op1
) == CONST_INT
&& ! SMALL_INT (op1
))
3253 op1
= force_reg (mode
, op1
);
3255 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3256 gen_rtx (cmp_code
, GET_MODE (operands
[0]), op0
, op1
),
3260 /* Write a loop to move a constant number of bytes.
3261 Generate load/stores as follows:
3267 temp<last> = src[MAX_MOVE_REGS-1];
3271 dest[MAX_MOVE_REGS-1] = temp<last>;
3272 src += MAX_MOVE_REGS;
3273 dest += MAX_MOVE_REGS;
3274 } while (src != final);
3276 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3277 registers are needed.
3279 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3280 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3281 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3283 #define MAX_MOVE_REGS 4
3284 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3287 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3288 rtx dest_reg
; /* register holding destination address */
3289 rtx src_reg
; /* register holding source address */
3290 unsigned int bytes
; /* # bytes to move */
3291 int align
; /* alignment */
3292 rtx orig_dest
; /* original dest */
3293 rtx orig_src
; /* original source for making a reg note */
3295 rtx dest_mem
= replace_equiv_address (orig_dest
, dest_reg
);
3296 rtx src_mem
= replace_equiv_address (orig_src
, src_reg
);
3297 rtx align_rtx
= GEN_INT (align
);
3303 if (bytes
< (unsigned)2 * MAX_MOVE_BYTES
)
3306 leftover
= bytes
% MAX_MOVE_BYTES
;
3309 label
= gen_label_rtx ();
3310 final_src
= gen_reg_rtx (Pmode
);
3311 bytes_rtx
= GEN_INT (bytes
);
3315 if (Pmode
== DImode
)
3317 emit_insn (gen_movdi (final_src
, bytes_rtx
));
3318 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
3322 emit_insn (gen_movsi (final_src
, bytes_rtx
));
3323 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
3328 if (Pmode
== DImode
)
3329 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
3331 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
3336 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
3337 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
3339 if (Pmode
== DImode
)
3341 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
3342 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
3343 emit_insn (gen_cmpdi (src_reg
, final_src
));
3347 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
3348 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
3349 emit_insn (gen_cmpsi (src_reg
, final_src
));
3352 emit_jump_insn (gen_bne (label
));
3355 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
3359 /* Use a library function to move some bytes. */
3362 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
3367 /* We want to pass the size as Pmode, which will normally be SImode
3368 but will be DImode if we are using 64 bit longs and pointers. */
3369 if (GET_MODE (bytes_rtx
) != VOIDmode
3370 && GET_MODE (bytes_rtx
) != (unsigned) Pmode
)
3371 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
3373 #ifdef TARGET_MEM_FUNCTIONS
3374 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
3375 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
3376 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
3377 TREE_UNSIGNED (sizetype
)),
3378 TYPE_MODE (sizetype
));
3380 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
3381 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
3382 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
3383 TREE_UNSIGNED (integer_type_node
)),
3384 TYPE_MODE (integer_type_node
));
3388 /* Expand string/block move operations.
3390 operands[0] is the pointer to the destination.
3391 operands[1] is the pointer to the source.
3392 operands[2] is the number of bytes to move.
3393 operands[3] is the alignment. */
3396 expand_block_move (operands
)
3399 rtx bytes_rtx
= operands
[2];
3400 rtx align_rtx
= operands
[3];
3401 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
3402 unsigned HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
3403 unsigned int align
= INTVAL (align_rtx
);
3404 rtx orig_src
= operands
[1];
3405 rtx orig_dest
= operands
[0];
3409 if (constp
&& bytes
== 0)
3412 if (align
> (unsigned) UNITS_PER_WORD
)
3413 align
= UNITS_PER_WORD
;
3415 /* Move the address into scratch registers. */
3416 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
3417 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
3420 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3422 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
3423 && align
== (unsigned) UNITS_PER_WORD
)
3424 move_by_pieces (orig_dest
, orig_src
, bytes
, align
* BITS_PER_WORD
);
3426 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
)
3427 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3429 replace_equiv_address (orig_src
,
3431 bytes_rtx
, align_rtx
));
3433 else if (constp
&& align
>= (unsigned) UNITS_PER_WORD
&& optimize
)
3434 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
3436 else if (constp
&& optimize
)
3438 /* If the alignment is not word aligned, generate a test at
3439 runtime, to see whether things wound up aligned, and we
3440 can use the faster lw/sw instead ulw/usw. */
3442 rtx temp
= gen_reg_rtx (Pmode
);
3443 rtx aligned_label
= gen_label_rtx ();
3444 rtx join_label
= gen_label_rtx ();
3445 int leftover
= bytes
% MAX_MOVE_BYTES
;
3449 if (Pmode
== DImode
)
3451 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
3452 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3453 emit_insn (gen_cmpdi (temp
, const0_rtx
));
3457 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
3458 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3459 emit_insn (gen_cmpsi (temp
, const0_rtx
));
3462 emit_jump_insn (gen_beq (aligned_label
));
3464 /* Unaligned loop. */
3465 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
3466 emit_jump_insn (gen_jump (join_label
));
3470 emit_label (aligned_label
);
3471 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
3473 emit_label (join_label
);
3475 /* Bytes at the end of the loop. */
3477 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3479 replace_equiv_address (orig_src
,
3486 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3489 /* Emit load/stores for a small constant block_move.
3491 operands[0] is the memory address of the destination.
3492 operands[1] is the memory address of the source.
3493 operands[2] is the number of bytes to move.
3494 operands[3] is the alignment.
3495 operands[4] is a temp register.
3496 operands[5] is a temp register.
3498 operands[3+num_regs] is the last temp register.
3500 The block move type can be one of the following:
3501 BLOCK_MOVE_NORMAL Do all of the block move.
3502 BLOCK_MOVE_NOT_LAST Do all but the last store.
3503 BLOCK_MOVE_LAST Do just the last store. */
3506 output_block_move (insn
, operands
, num_regs
, move_type
)
3510 enum block_move_type move_type
;
3512 rtx dest_reg
= XEXP (operands
[0], 0);
3513 rtx src_reg
= XEXP (operands
[1], 0);
3514 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
3515 int align
= INTVAL (operands
[3]);
3518 int use_lwl_lwr
= 0;
3519 int last_operand
= num_regs
+ 4;
3525 const char *load
; /* load insn without nop */
3526 const char *load_nop
; /* load insn with trailing nop */
3527 const char *store
; /* store insn */
3528 const char *final
; /* if last_store used: NULL or swr */
3529 const char *last_store
; /* last store instruction */
3530 int offset
; /* current offset */
3531 enum machine_mode mode
; /* mode to use on (MEM) */
3534 /* ??? Detect a bug in GCC, where it can give us a register
3535 the same as one of the addressing registers and reduce
3536 the number of registers available. */
3537 for (i
= 4; i
< last_operand
&& safe_regs
< (int) ARRAY_SIZE (xoperands
); i
++)
3538 if (! reg_mentioned_p (operands
[i
], operands
[0])
3539 && ! reg_mentioned_p (operands
[i
], operands
[1]))
3540 xoperands
[safe_regs
++] = operands
[i
];
3542 if (safe_regs
< last_operand
)
3544 xoperands
[0] = operands
[0];
3545 xoperands
[1] = operands
[1];
3546 xoperands
[2] = operands
[2];
3547 xoperands
[3] = operands
[3];
3548 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
3551 /* If we are given global or static addresses, and we would be
3552 emitting a few instructions, try to save time by using a
3553 temporary register for the pointer. */
3554 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3555 an ldl/ldr instruction pair. We play it safe, and always move
3556 constant addresses into registers when generating N32/N64 code, just
3557 in case we might emit an unaligned load instruction. */
3558 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
3559 || mips_abi
== ABI_MEABI
3560 || mips_abi
== ABI_N32
3561 || mips_abi
== ABI_64
))
3563 if (CONSTANT_P (src_reg
))
3566 mips_count_memory_refs (operands
[1], 1);
3568 src_reg
= operands
[3 + num_regs
--];
3569 if (move_type
!= BLOCK_MOVE_LAST
)
3571 xoperands
[1] = operands
[1];
3572 xoperands
[0] = src_reg
;
3573 if (Pmode
== DImode
)
3574 output_asm_insn ("dla\t%0,%1", xoperands
);
3576 output_asm_insn ("la\t%0,%1", xoperands
);
3580 if (CONSTANT_P (dest_reg
))
3583 mips_count_memory_refs (operands
[0], 1);
3585 dest_reg
= operands
[3 + num_regs
--];
3586 if (move_type
!= BLOCK_MOVE_LAST
)
3588 xoperands
[1] = operands
[0];
3589 xoperands
[0] = dest_reg
;
3590 if (Pmode
== DImode
)
3591 output_asm_insn ("dla\t%0,%1", xoperands
);
3593 output_asm_insn ("la\t%0,%1", xoperands
);
3598 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3599 are not offsettable, however, offsettable_address_p says they are
3600 offsettable. I think this is a bug in offsettable_address_p.
3601 For expediency, we fix this by just loading the address into a register
3602 if we happen to get one. */
3604 if (GET_CODE (src_reg
) == LO_SUM
)
3606 src_reg
= operands
[3 + num_regs
--];
3607 if (move_type
!= BLOCK_MOVE_LAST
)
3609 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
3610 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3611 xoperands
[0] = src_reg
;
3612 if (Pmode
== DImode
)
3613 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3615 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3619 if (GET_CODE (dest_reg
) == LO_SUM
)
3621 dest_reg
= operands
[3 + num_regs
--];
3622 if (move_type
!= BLOCK_MOVE_LAST
)
3624 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
3625 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
3626 xoperands
[0] = dest_reg
;
3627 if (Pmode
== DImode
)
3628 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3630 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3634 if (num_regs
> (int) ARRAY_SIZE (load_store
))
3635 num_regs
= ARRAY_SIZE (load_store
);
3637 else if (num_regs
< 1)
3638 abort_with_insn (insn
,
3639 "cannot do block move, not enough scratch registers");
3643 load_store
[num
].offset
= offset
;
3645 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
3647 load_store
[num
].load
= "ld\t%0,%1";
3648 load_store
[num
].load_nop
= "ld\t%0,%1%#";
3649 load_store
[num
].store
= "sd\t%0,%1";
3650 load_store
[num
].last_store
= "sd\t%0,%1";
3651 load_store
[num
].final
= 0;
3652 load_store
[num
].mode
= DImode
;
3657 /* ??? Fails because of a MIPS assembler bug? */
3658 else if (TARGET_64BIT
&& bytes
>= 8 && ! TARGET_MIPS16
)
3660 if (BYTES_BIG_ENDIAN
)
3662 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
3663 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
3664 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
3665 load_store
[num
].last_store
= "sdr\t%0,%2";
3666 load_store
[num
].final
= "sdl\t%0,%1";
3670 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
3671 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
3672 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
3673 load_store
[num
].last_store
= "sdr\t%0,%1";
3674 load_store
[num
].final
= "sdl\t%0,%2";
3677 load_store
[num
].mode
= DImode
;
3683 else if (bytes
>= 4 && align
>= 4)
3685 load_store
[num
].load
= "lw\t%0,%1";
3686 load_store
[num
].load_nop
= "lw\t%0,%1%#";
3687 load_store
[num
].store
= "sw\t%0,%1";
3688 load_store
[num
].last_store
= "sw\t%0,%1";
3689 load_store
[num
].final
= 0;
3690 load_store
[num
].mode
= SImode
;
3695 else if (bytes
>= 4 && ! TARGET_MIPS16
)
3697 if (BYTES_BIG_ENDIAN
)
3699 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
3700 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3701 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
3702 load_store
[num
].last_store
= "swr\t%0,%2";
3703 load_store
[num
].final
= "swl\t%0,%1";
3707 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
3708 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3709 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
3710 load_store
[num
].last_store
= "swr\t%0,%1";
3711 load_store
[num
].final
= "swl\t%0,%2";
3714 load_store
[num
].mode
= SImode
;
3720 else if (bytes
>= 2 && align
>= 2)
3722 load_store
[num
].load
= "lh\t%0,%1";
3723 load_store
[num
].load_nop
= "lh\t%0,%1%#";
3724 load_store
[num
].store
= "sh\t%0,%1";
3725 load_store
[num
].last_store
= "sh\t%0,%1";
3726 load_store
[num
].final
= 0;
3727 load_store
[num
].mode
= HImode
;
3733 load_store
[num
].load
= "lb\t%0,%1";
3734 load_store
[num
].load_nop
= "lb\t%0,%1%#";
3735 load_store
[num
].store
= "sb\t%0,%1";
3736 load_store
[num
].last_store
= "sb\t%0,%1";
3737 load_store
[num
].final
= 0;
3738 load_store
[num
].mode
= QImode
;
3743 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3745 dslots_load_total
++;
3746 dslots_load_filled
++;
3748 if (CONSTANT_P (src_reg
))
3749 mips_count_memory_refs (src_reg
, 1);
3751 if (CONSTANT_P (dest_reg
))
3752 mips_count_memory_refs (dest_reg
, 1);
3755 /* Emit load/stores now if we have run out of registers or are
3756 at the end of the move. */
3758 if (++num
== num_regs
|| bytes
== 0)
3760 /* If only load/store, we need a NOP after the load. */
3763 load_store
[0].load
= load_store
[0].load_nop
;
3764 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3765 dslots_load_filled
--;
3768 if (move_type
!= BLOCK_MOVE_LAST
)
3770 for (i
= 0; i
< num
; i
++)
3774 if (!operands
[i
+ 4])
3777 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
3778 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
3779 REGNO (operands
[i
+ 4]));
3781 offset
= load_store
[i
].offset
;
3782 xoperands
[0] = operands
[i
+ 4];
3783 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
3784 plus_constant (src_reg
, offset
));
3789 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
3791 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
3792 plus_constant (src_reg
,
3797 output_asm_insn (load_store
[i
].load
, xoperands
);
3801 for (i
= 0; i
< num
; i
++)
3803 int last_p
= (i
== num
-1 && bytes
== 0);
3804 int offset
= load_store
[i
].offset
;
3806 xoperands
[0] = operands
[i
+ 4];
3807 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
3808 plus_constant (dest_reg
, offset
));
3813 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
3814 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
3815 plus_constant (dest_reg
,
3820 if (move_type
== BLOCK_MOVE_NORMAL
)
3821 output_asm_insn (load_store
[i
].store
, xoperands
);
3823 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
3826 output_asm_insn (load_store
[i
].store
, xoperands
);
3828 else if (load_store
[i
].final
!= 0)
3829 output_asm_insn (load_store
[i
].final
, xoperands
);
3833 output_asm_insn (load_store
[i
].last_store
, xoperands
);
3836 num
= 0; /* reset load_store */
3844 /* Argument support functions. */
3846 /* Initialize CUMULATIVE_ARGS for a function. */
3849 init_cumulative_args (cum
, fntype
, libname
)
3850 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
3851 tree fntype
; /* tree ptr for function decl */
3852 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
3854 static CUMULATIVE_ARGS zero_cum
;
3855 tree param
, next_param
;
3857 if (TARGET_DEBUG_E_MODE
)
3860 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
3863 fputc ('\n', stderr
);
3867 tree ret_type
= TREE_TYPE (fntype
);
3868 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
3869 tree_code_name
[(int)TREE_CODE (fntype
)],
3870 tree_code_name
[(int)TREE_CODE (ret_type
)]);
3875 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
3877 /* Determine if this function has variable arguments. This is
3878 indicated by the last argument being 'void_type_mode' if there
3879 are no variable arguments. The standard MIPS calling sequence
3880 passes all arguments in the general purpose registers in this case. */
3882 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
3883 param
!= 0; param
= next_param
)
3885 next_param
= TREE_CHAIN (param
);
3886 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
3887 cum
->gp_reg_found
= 1;
3891 /* Advance the argument to the next argument position. */
3894 function_arg_advance (cum
, mode
, type
, named
)
3895 CUMULATIVE_ARGS
*cum
; /* current arg information */
3896 enum machine_mode mode
; /* current arg mode */
3897 tree type
; /* type of the argument or 0 if lib support */
3898 int named
; /* whether or not the argument was named */
3900 if (TARGET_DEBUG_E_MODE
)
3903 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3904 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
3905 GET_MODE_NAME (mode
));
3906 fprintf (stderr
, HOST_PTR_PRINTF
, (const PTR
) type
);
3907 fprintf (stderr
, ", %d )\n\n", named
);
3917 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3918 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3921 cum
->gp_reg_found
= 1;
3922 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3927 cum
->gp_reg_found
= 1;
3928 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3933 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3934 cum
->fp_arg_words
++;
3937 if (! cum
->gp_reg_found
&& cum
->arg_number
<= 2)
3938 cum
->fp_code
+= 1 << ((cum
->arg_number
- 1) * 2);
3942 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3943 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3945 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3946 if (! cum
->gp_reg_found
&& ! TARGET_SINGLE_FLOAT
&& cum
->arg_number
<= 2)
3947 cum
->fp_code
+= 2 << ((cum
->arg_number
- 1) * 2);
3951 cum
->gp_reg_found
= 1;
3952 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3958 cum
->gp_reg_found
= 1;
3964 /* Return an RTL expression containing the register for the given mode,
3965 or 0 if the argument is to be passed on the stack. */
3968 function_arg (cum
, mode
, type
, named
)
3969 CUMULATIVE_ARGS
*cum
; /* current arg information */
3970 enum machine_mode mode
; /* current arg mode */
3971 tree type
; /* type of the argument or 0 if lib support */
3972 int named
; /* != 0 for normal args, == 0 for ... args */
3977 unsigned int *arg_words
= &cum
->arg_words
;
3978 int struct_p
= (type
!= 0
3979 && (TREE_CODE (type
) == RECORD_TYPE
3980 || TREE_CODE (type
) == UNION_TYPE
3981 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
3983 if (TARGET_DEBUG_E_MODE
)
3986 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3987 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
3988 GET_MODE_NAME (mode
));
3989 fprintf (stderr
, HOST_PTR_PRINTF
, (const PTR
) type
);
3990 fprintf (stderr
, ", %d ) = ", named
);
3994 cum
->last_arg_fp
= 0;
3998 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4000 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
4001 regbase
= GP_ARG_FIRST
;
4004 regbase
= FP_ARG_FIRST
;
4006 /* If the first arg was a float in a floating point register,
4007 then set bias to align this float arg properly. */
4008 if (cum
->arg_words
== 1)
4012 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
4015 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
4016 cum
->last_arg_fp
= 1;
4017 arg_words
= &cum
->fp_arg_words
;
4018 regbase
= FP_ARG_FIRST
;
4020 /* The MIPS eabi says only structures containing doubles get passed in a
4021 fp register, so force a structure containing a float to be passed in
4022 the integer registers. */
4023 else if (mips_abi
== ABI_MEABI
&& struct_p
)
4024 regbase
= GP_ARG_FIRST
;
4026 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
4032 if (mips_abi
== ABI_EABI
4033 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
4034 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
4036 cum
->arg_words
+= cum
->arg_words
& 1;
4039 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4040 regbase
= ((cum
->gp_reg_found
4041 || TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
4042 || cum
->arg_number
>= 2)
4043 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
4044 else if (mips_abi
== ABI_EABI
4045 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
4047 cum
->last_arg_fp
= 1;
4048 arg_words
= &cum
->fp_arg_words
;
4049 regbase
= FP_ARG_FIRST
;
4052 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
4053 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
4057 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
4058 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4061 /* Drops through. */
4063 if (type
!= NULL_TREE
&& TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
4064 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
4065 cum
->arg_words
+= (cum
->arg_words
& 1);
4066 regbase
= GP_ARG_FIRST
;
4073 regbase
= GP_ARG_FIRST
;
4078 cum
->arg_words
+= (cum
->arg_words
& 1);
4079 regbase
= GP_ARG_FIRST
;
4082 if (*arg_words
>= (unsigned) MAX_ARGS_IN_REGISTERS
)
4084 if (TARGET_DEBUG_E_MODE
)
4085 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
4094 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
4095 || mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
4096 || mips_abi
== ABI_O64
|| mips_abi
== ABI_MEABI
4098 || ! TYPE_SIZE_UNIT (type
)
4099 || ! host_integerp (TYPE_SIZE_UNIT (type
), 1))
4102 unsigned int arg_reg
= (regbase
+ *arg_words
+ bias
);
4103 ret
= gen_rtx_REG (mode
, arg_reg
);
4104 if (mips_abi
== ABI_MEABI
4105 && regbase
== FP_ARG_FIRST
4106 && ! cum
->prototype
)
4108 /* To make K&R varargs work we need to pass floating
4109 point arguments in both integer and FP registers. */
4110 ret
= gen_rtx_PARALLEL (mode
,
4112 gen_rtx_EXPR_LIST (VOIDmode
,
4114 arg_reg
+ GP_ARG_FIRST
- FP_ARG_FIRST
),
4115 const0_rtx
), gen_rtx_EXPR_LIST (VOIDmode
, ret
, const0_rtx
)));
4120 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4121 structure contains a double in its entirety, then that 64 bit
4122 chunk is passed in a floating point register. */
4125 /* First check to see if there is any such field. */
4126 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4127 if (TREE_CODE (field
) == FIELD_DECL
4128 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4129 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4130 && host_integerp (bit_position (field
), 0)
4131 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4134 /* If the whole struct fits a DFmode register,
4135 we don't need the PARALLEL. */
4136 if (! field
|| mode
== DFmode
)
4137 ret
= gen_rtx_REG (mode
, regbase
+ *arg_words
+ bias
);
4140 /* Now handle the special case by returning a PARALLEL
4141 indicating where each 64 bit chunk goes. */
4142 unsigned int chunks
;
4143 HOST_WIDE_INT bitpos
;
4147 /* ??? If this is a packed structure, then the last hunk won't
4151 = tree_low_cst (TYPE_SIZE_UNIT (type
), 1) / UNITS_PER_WORD
;
4152 if (chunks
+ *arg_words
+ bias
> (unsigned) MAX_ARGS_IN_REGISTERS
)
4153 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
4155 /* assign_parms checks the mode of ENTRY_PARM, so we must
4156 use the actual mode here. */
4157 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (chunks
));
4160 regno
= regbase
+ *arg_words
+ bias
;
4161 field
= TYPE_FIELDS (type
);
4162 for (i
= 0; i
< chunks
; i
++)
4166 for (; field
; field
= TREE_CHAIN (field
))
4167 if (TREE_CODE (field
) == FIELD_DECL
4168 && int_bit_position (field
) >= bitpos
)
4172 && int_bit_position (field
) == bitpos
4173 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4174 && !TARGET_SOFT_FLOAT
4175 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4176 reg
= gen_rtx_REG (DFmode
,
4177 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
4179 reg
= gen_rtx_REG (word_mode
, regno
);
4182 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4183 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4191 if (TARGET_DEBUG_E_MODE
)
4192 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
4193 struct_p
? ", [struct]" : "");
4195 /* The following is a hack in order to pass 1 byte structures
4196 the same way that the MIPS compiler does (namely by passing
4197 the structure in the high byte or half word of the register).
4198 This also makes varargs work. If we have such a structure,
4199 we save the adjustment RTL, and the call define expands will
4200 emit them. For the VOIDmode argument (argument after the
4201 last real argument), pass back a parallel vector holding each
4202 of the adjustments. */
4204 /* ??? function_arg can be called more than once for each argument.
4205 As a result, we compute more adjustments than we need here.
4206 See the CUMULATIVE_ARGS definition in mips.h. */
4208 /* ??? This scheme requires everything smaller than the word size to
4209 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4210 that would mean every int needs to be shifted left, which is very
4211 inefficient. Let's not carry this compatibility to the 64 bit
4212 calling convention for now. */
4214 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
4216 && mips_abi
!= ABI_EABI
4217 && mips_abi
!= ABI_MEABI
)
4219 rtx amount
= GEN_INT (BITS_PER_WORD
4220 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
4221 rtx reg
= gen_rtx_REG (word_mode
, regbase
+ *arg_words
+ bias
);
4224 cum
->adjust
[cum
->num_adjusts
++] = gen_ashldi3 (reg
, reg
, amount
);
4226 cum
->adjust
[cum
->num_adjusts
++] = gen_ashlsi3 (reg
, reg
, amount
);
4230 /* We will be called with a mode of VOIDmode after the last argument
4231 has been seen. Whatever we return will be passed to the call
4232 insn. If we need any shifts for small structures, return them in
4233 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4234 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4235 with the code stored as the mode. */
4236 if (mode
== VOIDmode
)
4238 if (cum
->num_adjusts
> 0)
4239 ret
= gen_rtx (PARALLEL
, (enum machine_mode
) cum
->fp_code
,
4240 gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
4241 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4242 ret
= gen_rtx (REG
, (enum machine_mode
) cum
->fp_code
, 0);
4249 function_arg_partial_nregs (cum
, mode
, type
, named
)
4250 CUMULATIVE_ARGS
*cum
; /* current arg information */
4251 enum machine_mode mode
; /* current arg mode */
4252 tree type
; /* type of the argument or 0 if lib support */
4253 int named ATTRIBUTE_UNUSED
;/* != 0 for normal args, == 0 for ... args */
4255 if ((mode
== BLKmode
4256 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
4257 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
4258 && cum
->arg_words
< (unsigned) MAX_ARGS_IN_REGISTERS
4259 && mips_abi
!= ABI_EABI
)
4262 if (mode
== BLKmode
)
4263 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
4266 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4268 if (words
+ cum
->arg_words
<= (unsigned) MAX_ARGS_IN_REGISTERS
)
4269 return 0; /* structure fits in registers */
4271 if (TARGET_DEBUG_E_MODE
)
4272 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
4273 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
4275 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
4278 else if (mode
== DImode
4279 && cum
->arg_words
== MAX_ARGS_IN_REGISTERS
- (unsigned)1
4280 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
4282 if (TARGET_DEBUG_E_MODE
)
4283 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
4291 /* Create the va_list data type.
4292 We keep 3 pointers, and two offsets.
4293 Two pointers are to the overflow area, which starts at the CFA.
4294 One of these is constant, for addressing into the GPR save area below it.
4295 The other is advanced up the stack through the overflow region.
4296 The third pointer is to the GPR save area. Since the FPR save area
4297 is just below it, we can address FPR slots off this pointer.
4298 We also keep two one-byte offsets, which are to be subtracted from the
4299 constant pointers to yield addresses in the GPR and FPR save areas.
4300 These are downcounted as float or non-float arguments are used,
4301 and when they get to zero, the argument must be obtained from the
4303 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4304 and a single pointer is enough. It's started at the GPR save area,
4305 and is advanced, period.
4306 Note that the GPR save area is not constant size, due to optimization
4307 in the prologue. Hence, we can't use a design with two pointers
4308 and two offsets, although we could have designed this with two pointers
4309 and three offsets. */
4313 mips_build_va_list ()
4315 if (mips_abi
== ABI_EABI
&& !TARGET_SOFT_FLOAT
&& !TARGET_SINGLE_FLOAT
)
4317 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, record
;
4319 record
= make_node (RECORD_TYPE
);
4321 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4323 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4325 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4327 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4328 unsigned_char_type_node
);
4329 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4330 unsigned_char_type_node
);
4333 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4334 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4335 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4336 DECL_FIELD_CONTEXT (f_goff
) = record
;
4337 DECL_FIELD_CONTEXT (f_foff
) = record
;
4339 TYPE_FIELDS (record
) = f_ovfl
;
4340 TREE_CHAIN (f_ovfl
) = f_gtop
;
4341 TREE_CHAIN (f_gtop
) = f_ftop
;
4342 TREE_CHAIN (f_ftop
) = f_goff
;
4343 TREE_CHAIN (f_goff
) = f_foff
;
4345 layout_type (record
);
4349 return ptr_type_node
;
4352 /* Implement va_start. stdarg_p is 0 if implementing
4353 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4354 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4355 (It doesn't have "...", so it inherits the pointers of its caller.) */
4358 mips_va_start (stdarg_p
, valist
, nextarg
)
4366 /* Find out how many non-float named formals */
4367 int_arg_words
= current_function_args_info
.arg_words
;
4369 if (mips_abi
== ABI_EABI
)
4371 int gpr_save_area_size
;
4372 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4373 if (int_arg_words
< 8 )
4374 /* Adjust for the prologue's economy measure */
4375 gpr_save_area_size
= (8 - int_arg_words
) * UNITS_PER_WORD
;
4377 gpr_save_area_size
= 0;
4379 if (!TARGET_SOFT_FLOAT
&& !TARGET_SINGLE_FLOAT
)
4381 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4382 tree ovfl
, gtop
, ftop
, goff
, foff
;
4384 int float_formals
, fpr_offset
, size_excess
, floats_passed_in_regs
;
4385 int fpr_save_offset
;
4387 float_formals
= current_function_args_info
.fp_arg_words
;
4388 /* If mips2, the number of formals is half the reported # of words */
4391 floats_passed_in_regs
= (TARGET_64BIT
? 8 : 4);
4393 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4394 f_gtop
= TREE_CHAIN (f_ovfl
);
4395 f_ftop
= TREE_CHAIN (f_gtop
);
4396 f_goff
= TREE_CHAIN (f_ftop
);
4397 f_foff
= TREE_CHAIN (f_goff
);
4399 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4400 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4401 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4402 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4403 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4405 /* Emit code setting a pointer into the overflow (shared-stack) area.
4406 If there were more than 8 non-float formals, or more than 8
4407 float formals, then this pointer isn't to the base of the area.
4408 In that case, it must point to where the first vararg is. */
4410 if (float_formals
> floats_passed_in_regs
)
4411 size_excess
+= (float_formals
-floats_passed_in_regs
) * 8;
4412 if (int_arg_words
> 8)
4413 size_excess
+= (int_arg_words
-8) * UNITS_PER_WORD
;
4415 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4416 overflow stack holds mixed size items, there can be alignments,
4417 so that an 8 byte double following a 4 byte int will be on an
4418 8 byte boundary. This means that the above calculation should
4419 take into account the exact sequence of floats and non-floats
4420 which make up the excess. That calculation should be rolled
4421 into the code which sets the current_function_args_info struct.
4422 The above then reduces to a fetch from that struct. */
4425 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4427 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4428 build_int_2 (size_excess
, 0));
4429 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4430 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4432 /* Emit code setting a ptr to the base of the overflow area. */
4433 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4434 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
4435 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4437 /* Emit code setting a pointer to the GPR save area.
4438 More precisely, a pointer to off-the-end of the FPR save area.
4439 If mips4, this is gpr_save_area_size below the overflow area.
4440 If mips2, also round down to an 8-byte boundary, since the FPR
4441 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4442 Therefore there can be a 4-byte gap between the save areas. */
4443 gprv
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4444 fpr_save_offset
= gpr_save_area_size
;
4447 if (fpr_save_offset
& 7)
4448 fpr_save_offset
+= 4;
4450 if (fpr_save_offset
)
4451 gprv
= build (PLUS_EXPR
, TREE_TYPE (ftop
), gprv
,
4452 build_int_2 (-fpr_save_offset
,-1));
4453 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, gprv
);
4454 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4456 /* Emit code initting an offset to the size of the GPR save area */
4457 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
4458 build_int_2 (gpr_save_area_size
,0));
4459 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4461 /* Emit code initting an offset from ftop to the first float
4462 vararg. This varies in size, since any float
4463 varargs are put in the FPR save area after the formals.
4464 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4465 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4466 If there are 8 or more float formals, init to zero.
4467 (In fact, the formals aren't stored in the bottom of the
4468 FPR save area: they are elsewhere, and the size of the FPR
4469 save area is economized by the prologue. But this code doesn't
4470 care. This design is unaffected by that fact.) */
4471 if (float_formals
>= floats_passed_in_regs
)
4474 fpr_offset
= (floats_passed_in_regs
- float_formals
) * 8;
4475 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
4476 build_int_2 (fpr_offset
,0));
4477 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4481 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4483 /* Everything is in the GPR save area, or in the overflow
4484 area which is contiguous with it. */
4486 int offset
= -gpr_save_area_size
;
4487 if (gpr_save_area_size
== 0)
4488 offset
= (stdarg_p
? 0 : -UNITS_PER_WORD
);
4489 nextarg
= plus_constant (nextarg
, offset
);
4490 std_expand_builtin_va_start (1, valist
, nextarg
);
4502 /* ??? This had been conditional on
4503 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4504 and both iris5.h and iris6.h define _MIPS_SIM. */
4505 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4506 ofs
= (int_arg_words
>= 8 ? -UNITS_PER_WORD
: 0);
4507 else if (mips_abi
== ABI_MEABI
)
4508 ofs
= (int_arg_words
>= 8 ? -UNITS_PER_WORD
: 0);
4510 ofs
= -UNITS_PER_WORD
;
4513 nextarg
= plus_constant (nextarg
, ofs
);
4514 std_expand_builtin_va_start (1, valist
, nextarg
);
4518 /* Implement va_arg. */
4521 mips_va_arg (valist
, type
)
4524 HOST_WIDE_INT size
, rsize
;
4528 size
= int_size_in_bytes (type
);
4529 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4531 if (mips_abi
== ABI_EABI
)
4534 rtx r
, lab_over
= NULL_RTX
, lab_false
;
4535 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4536 tree ovfl
, gtop
, ftop
, goff
, foff
;
4539 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4542 size
= POINTER_SIZE
/ BITS_PER_UNIT
;
4543 rsize
= UNITS_PER_WORD
;
4546 addr_rtx
= gen_reg_rtx (Pmode
);
4548 if (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
)
4550 /* Case of all args in a merged stack. No need to check bounds,
4551 just advance valist along the stack. */
4556 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
4558 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
4559 build_int_2 (2*UNITS_PER_WORD
- 1, 0));
4560 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4561 build_int_2 (-2*UNITS_PER_WORD
, -1));
4562 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
4563 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4566 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
,
4568 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4570 emit_move_insn (addr_rtx
, r
);
4572 /* flush the POSTINCREMENT */
4577 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4578 set_mem_alias_set (r
, get_varargs_alias_set ());
4579 emit_move_insn (addr_rtx
, r
);
4583 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4584 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4589 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4591 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4592 f_gtop
= TREE_CHAIN (f_ovfl
);
4593 f_ftop
= TREE_CHAIN (f_gtop
);
4594 f_goff
= TREE_CHAIN (f_ftop
);
4595 f_foff
= TREE_CHAIN (f_goff
);
4597 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4598 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4599 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4600 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4601 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4603 lab_false
= gen_label_rtx ();
4604 lab_over
= gen_label_rtx ();
4606 if (TREE_CODE (type
) == REAL_TYPE
)
4609 /* Emit code to branch if foff == 0. */
4610 r
= expand_expr (foff
, NULL_RTX
, TYPE_MODE (TREE_TYPE (foff
)),
4612 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
4615 /* Emit code for addr_rtx = ftop - foff */
4616 t
= build (MINUS_EXPR
, TREE_TYPE (ftop
), ftop
, foff
);
4617 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4619 emit_move_insn (addr_rtx
, r
);
4621 /* Emit code for foff-=8.
4622 Advances the offset up FPR save area by one double */
4623 t
= build (MINUS_EXPR
, TREE_TYPE (foff
), foff
, build_int_2 (8, 0));
4624 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
, t
);
4625 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4628 emit_jump (lab_over
);
4630 emit_label (lab_false
);
4634 /* For mips2, the overflow area contains mixed size items.
4635 If a 4-byte int is followed by an 8-byte float, then
4636 natural alignment causes a 4 byte gap.
4637 So, dynamically adjust ovfl up to a multiple of 8. */
4638 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4639 build_int_2 (7, 0));
4640 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4641 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4642 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4645 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4646 Regardless of mips2, postincrement the ovfl pointer by 8. */
4647 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE(ovfl
), ovfl
,
4649 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4651 emit_move_insn (addr_rtx
, r
);
4654 emit_label (lab_over
);
4663 && TREE_CODE (type
) == INTEGER_TYPE
4664 && TYPE_PRECISION (type
) == 64)
4666 /* In mips2, int takes 32 bits of the GPR save area, but
4667 longlong takes an aligned 64 bits. So, emit code
4668 to zero the low order bits of goff, thus aligning
4669 the later calculation of (gtop-goff) upwards. */
4670 t
= build (BIT_AND_EXPR
, TREE_TYPE (goff
), goff
,
4671 build_int_2 (-8, -1));
4672 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
, t
);
4673 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4676 /* Emit code to branch if goff == 0. */
4677 r
= expand_expr (goff
, NULL_RTX
, TYPE_MODE (TREE_TYPE (goff
)),
4679 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
4682 /* Emit code for addr_rtx = gtop - goff. */
4683 t
= build (MINUS_EXPR
, TREE_TYPE (gtop
), gtop
, goff
);
4684 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4686 emit_move_insn (addr_rtx
, r
);
4688 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4689 if (! TARGET_64BIT
&& TYPE_PRECISION (type
) == 64)
4692 step_size
= UNITS_PER_WORD
;
4694 /* Emit code for goff = goff - step_size.
4695 Advances the offset up GPR save area over the item. */
4696 t
= build (MINUS_EXPR
, TREE_TYPE (goff
), goff
,
4697 build_int_2 (step_size
, 0));
4698 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
, t
);
4699 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4702 emit_jump (lab_over
);
4704 emit_label (lab_false
);
4706 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4707 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE(ovfl
), ovfl
,
4708 size_int (step_size
));
4709 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4711 emit_move_insn (addr_rtx
, r
);
4714 emit_label (lab_over
);
4718 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4719 set_mem_alias_set (r
, get_varargs_alias_set ());
4720 emit_move_insn (addr_rtx
, r
);
4724 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4725 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4735 /* ??? The original va-mips.h did always align, despite the fact
4736 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4737 increment mechanism. */
4741 else if (TYPE_ALIGN (type
) > 32)
4746 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4747 build_int_2 (align
- 1, 0));
4748 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
4749 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4750 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4752 /* Everything past the alignment is standard. */
4753 return std_expand_builtin_va_arg (valist
, type
);
4757 /* Abort after printing out a specific insn. */
4760 abort_with_insn (insn
, reason
)
4769 /* Set up the threshold for data to go into the small data area, instead
4770 of the normal data area, and detect any conflicts in the switches. */
4775 register int i
, start
;
4777 register enum machine_mode mode
;
4778 register enum processor_type mips_cpu
;
4780 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4782 if (mips_section_threshold
<= 0)
4783 target_flags
&= ~MASK_GPOPT
;
4785 target_flags
|= MASK_GPOPT
;
4787 /* If both single-float and soft-float are set, then clear the one that
4788 was set by TARGET_DEFAULT, leaving the one that was set by the
4789 user. We assume here that the specs prevent both being set by the
4791 #ifdef TARGET_DEFAULT
4792 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
4793 target_flags
&= ~((TARGET_DEFAULT
) & (MASK_SOFT_FLOAT
| MASK_SINGLE_FLOAT
));
4796 /* Get the architectural level. */
4797 if (mips_isa_string
== 0)
4798 mips_isa
= MIPS_ISA_DEFAULT
;
4800 else if (ISDIGIT (*mips_isa_string
))
4802 mips_isa
= atoi (mips_isa_string
);
4805 /* -mno-mips16 overrides -mips16. */
4806 if (mips_no_mips16_string
== NULL
)
4808 target_flags
|= MASK_MIPS16
;
4812 mips_isa
= MIPS_ISA_DEFAULT
;
4816 mips_isa
= MIPS_ISA_DEFAULT
;
4819 else if (mips_isa
< 1
4824 error ("-mips%d not supported", mips_isa
);
4831 error ("bad value (%s) for -mips switch", mips_isa_string
);
4835 #ifdef MIPS_ABI_DEFAULT
4836 /* Get the ABI to use. */
4837 if (mips_abi_string
== (char *) 0)
4838 mips_abi
= MIPS_ABI_DEFAULT
;
4839 else if (! strcmp (mips_abi_string
, "32"))
4841 else if (! strcmp (mips_abi_string
, "o64"))
4843 else if (! strcmp (mips_abi_string
, "n32"))
4845 else if (! strcmp (mips_abi_string
, "64"))
4847 else if (! strcmp (mips_abi_string
, "eabi"))
4848 mips_abi
= ABI_EABI
;
4849 else if (! strcmp (mips_abi_string
, "meabi"))
4850 mips_abi
= ABI_MEABI
;
4852 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
4854 /* A specified ISA defaults the ABI if it was not specified. */
4855 if (mips_abi_string
== 0 && mips_isa_string
4856 && mips_abi
!= ABI_EABI
4857 && mips_abi
!= ABI_O64
4858 && mips_abi
!= ABI_MEABI
)
4864 if (! ISA_HAS_64BIT_REGS
)
4871 #ifdef MIPS_CPU_STRING_DEFAULT
4872 /* A specified ABI defaults the ISA if it was not specified. */
4873 else if (mips_isa_string
== 0 && mips_abi_string
4874 && mips_abi
!= ABI_EABI
&& mips_abi
!= ABI_O64
)
4876 if (mips_abi
== ABI_32
)
4878 else if (mips_abi
== ABI_N32
)
4885 /* If both ABI and ISA were specified, check for conflicts. */
4886 else if (mips_isa_string
&& mips_abi_string
)
4888 if (! ISA_HAS_64BIT_REGS
&& (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
4889 || mips_abi
== ABI_O64
))
4890 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
4893 /* Override TARGET_DEFAULT if necessary. */
4894 if (mips_abi
== ABI_32
)
4895 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
4897 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4898 then set the type sizes. In the EABI in 64 bit mode, longs and
4899 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4900 if (mips_explicit_type_size_string
== NULL
4901 && ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
4902 || mips_abi
== ABI_64
))
4903 target_flags
|= MASK_LONG64
;
4906 if (mips_abi_string
)
4907 error ("this target does not support the -mabi switch");
4910 #ifdef MIPS_CPU_STRING_DEFAULT
4911 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4912 greater than that supported by the default processor, then the user gets
4913 an error. Normally, the compiler will just default to the base level cpu
4914 for the indicated isa. */
4915 if (mips_arch_string
== 0)
4916 mips_arch_string
= MIPS_CPU_STRING_DEFAULT
;
4917 if (mips_tune_string
== 0)
4918 mips_tune_string
= MIPS_CPU_STRING_DEFAULT
;
4921 /* Identify the processor type. */
4923 if (mips_cpu_string
!= 0)
4925 mips_cpu
= mips_parse_cpu (mips_cpu_string
);
4926 if (mips_cpu
== PROCESSOR_DEFAULT
)
4928 error ("bad value (%s) for -mcpu= switch", mips_arch_string
);
4929 mips_cpu_string
= "default";
4931 mips_arch
= mips_cpu
;
4932 mips_tune
= mips_cpu
;
4935 if (mips_arch_string
== 0
4936 || ! strcmp (mips_arch_string
, "default")
4937 || ! strcmp (mips_arch_string
, "DEFAULT"))
4942 mips_arch_string
= "3000";
4943 mips_arch
= PROCESSOR_R3000
;
4946 mips_arch_string
= "6000";
4947 mips_arch
= PROCESSOR_R6000
;
4950 mips_arch_string
= "4000";
4951 mips_arch
= PROCESSOR_R4000
;
4954 mips_arch_string
= "8000";
4955 mips_arch
= PROCESSOR_R8000
;
4958 mips_arch_string
= "4kc";
4959 mips_arch
= PROCESSOR_R4KC
;
4962 mips_arch_string
= "5kc";
4963 mips_arch
= PROCESSOR_R5KC
;
4969 mips_arch
= mips_parse_cpu (mips_arch_string
);
4970 if (mips_arch
== PROCESSOR_DEFAULT
)
4972 error ("bad value (%s) for -march= switch", mips_arch_string
);
4973 mips_arch_string
= "default";
4976 if (mips_tune_string
== 0
4977 || ! strcmp (mips_tune_string
, "default")
4978 || ! strcmp (mips_tune_string
, "DEFAULT"))
4980 if (mips_arch
!= PROCESSOR_DEFAULT
)
4981 mips_tune
= mips_arch
;
4986 mips_tune_string
= "3000";
4987 mips_tune
= PROCESSOR_R3000
;
4990 mips_tune_string
= "6000";
4991 mips_tune
= PROCESSOR_R6000
;
4994 mips_tune_string
= "4000";
4995 mips_tune
= PROCESSOR_R4000
;
4998 mips_tune_string
= "8000";
4999 mips_tune
= PROCESSOR_R8000
;
5002 mips_tune_string
= "4kc";
5003 mips_tune
= PROCESSOR_R4KC
;
5006 mips_tune_string
= "5kc";
5007 mips_tune
= PROCESSOR_R5KC
;
5014 mips_tune
= mips_parse_cpu (mips_tune_string
);
5015 if (mips_tune
== PROCESSOR_DEFAULT
)
5017 error ("bad value (%s) for -mtune= switch", mips_tune_string
);
5018 mips_tune_string
= "default";
5022 if ((mips_arch
== PROCESSOR_R3000
&& (mips_isa
!= 1))
5023 || (mips_arch
== PROCESSOR_R4KC
&& mips_isa
!= 32)
5024 || ((mips_arch
== PROCESSOR_R5KC
5025 || mips_arch
== PROCESSOR_R20KC
) && mips_isa
!= 64)
5026 || (mips_arch
== PROCESSOR_R6000
&& mips_isa
!= 1 && mips_isa
!= 2)
5027 || ((mips_arch
== PROCESSOR_R4000
5028 || mips_arch
== PROCESSOR_R4100
5029 || mips_arch
== PROCESSOR_R4300
5030 || mips_arch
== PROCESSOR_R4600
5031 || mips_arch
== PROCESSOR_R4650
)
5032 && mips_isa
!= 1 && mips_isa
!= 2 && mips_isa
!= 3))
5033 error ("-march=%s does not support -mips%d", mips_arch_string
, mips_isa
);
5035 /* make sure sizes of ints/longs/etc. are ok */
5036 if (! ISA_HAS_64BIT_REGS
)
5040 error ("-mips%d does not support 64 bit fp registers", mips_isa
);
5041 target_flags
&= ~ MASK_FLOAT64
;
5044 else if (TARGET_64BIT
)
5046 error ("-mips%d does not support 64 bit gp registers", mips_isa
);
5047 target_flags
&= ~MASK_64BIT
;
5051 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5052 flag_pcc_struct_return
= 0;
5054 /* Tell halfpic.c that we have half-pic code if we do. */
5055 if (TARGET_HALF_PIC
)
5058 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5059 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5060 /* ??? -non_shared turns off pic code generation, but this is not
5062 if (TARGET_ABICALLS
)
5064 mips_abicalls
= MIPS_ABICALLS_YES
;
5066 if (mips_section_threshold
> 0)
5067 warning ("-G is incompatible with PIC code which is the default");
5070 mips_abicalls
= MIPS_ABICALLS_NO
;
5072 /* -membedded-pic is a form of PIC code suitable for embedded
5073 systems. All calls are made using PC relative addressing, and
5074 all data is addressed using the $gp register. This requires gas,
5075 which does most of the work, and GNU ld, which automatically
5076 expands PC relative calls which are out of range into a longer
5077 instruction sequence. All gcc really does differently is
5078 generate a different sequence for a switch. */
5079 if (TARGET_EMBEDDED_PIC
)
5082 if (TARGET_ABICALLS
)
5083 warning ("-membedded-pic and -mabicalls are incompatible");
5086 warning ("-G and -membedded-pic are incompatible");
5088 /* Setting mips_section_threshold is not required, because gas
5089 will force everything to be GP addressable anyhow, but
5090 setting it will cause gcc to make better estimates of the
5091 number of instructions required to access a particular data
5093 mips_section_threshold
= 0x7fffffff;
5096 /* This optimization requires a linker that can support a R_MIPS_LO16
5097 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5098 GNU ld has this support, but not all other MIPS linkers do, so we enable
5099 this optimization only if the user requests it, or if GNU ld is the
5100 standard linker for this configuration. */
5101 /* ??? This does not work when target addresses are DImode.
5102 This is because we are missing DImode high/lo_sum patterns. */
5103 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
5105 mips_split_addresses
= 1;
5107 mips_split_addresses
= 0;
5109 /* -mrnames says to use the MIPS software convention for register
5110 names instead of the hardware names (ie, $a0 instead of $4).
5111 We do this by switching the names in mips_reg_names, which the
5112 reg_names points into via the REGISTER_NAMES macro. */
5114 if (TARGET_NAME_REGS
)
5115 memcpy (mips_reg_names
, mips_sw_reg_names
, sizeof (mips_reg_names
));
5117 /* When compiling for the mips16, we can not use floating point. We
5118 record the original hard float value in mips16_hard_float. */
5121 if (TARGET_SOFT_FLOAT
)
5122 mips16_hard_float
= 0;
5124 mips16_hard_float
= 1;
5125 target_flags
|= MASK_SOFT_FLOAT
;
5127 /* Don't run the scheduler before reload, since it tends to
5128 increase register pressure. */
5129 flag_schedule_insns
= 0;
5132 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5133 to avoid using up another bit in target_flags. */
5134 if (mips_entry_string
!= NULL
)
5136 if (*mips_entry_string
!= '\0')
5137 error ("invalid option `entry%s'", mips_entry_string
);
5139 if (! TARGET_MIPS16
)
5140 warning ("-mentry is only meaningful with -mips-16");
5145 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5146 attributes can access it. */
5152 /* Initialize the high and low values for legitimate floating point
5153 constants. Rather than trying to get the accuracy down to the
5154 last bit, just use approximate ranges. */
5155 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
5156 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
5157 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
5158 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
5160 mips_print_operand_punct
['?'] = 1;
5161 mips_print_operand_punct
['#'] = 1;
5162 mips_print_operand_punct
['&'] = 1;
5163 mips_print_operand_punct
['!'] = 1;
5164 mips_print_operand_punct
['*'] = 1;
5165 mips_print_operand_punct
['@'] = 1;
5166 mips_print_operand_punct
['.'] = 1;
5167 mips_print_operand_punct
['('] = 1;
5168 mips_print_operand_punct
[')'] = 1;
5169 mips_print_operand_punct
['['] = 1;
5170 mips_print_operand_punct
[']'] = 1;
5171 mips_print_operand_punct
['<'] = 1;
5172 mips_print_operand_punct
['>'] = 1;
5173 mips_print_operand_punct
['{'] = 1;
5174 mips_print_operand_punct
['}'] = 1;
5175 mips_print_operand_punct
['^'] = 1;
5176 mips_print_operand_punct
['$'] = 1;
5177 mips_print_operand_punct
['+'] = 1;
5178 mips_print_operand_punct
['~'] = 1;
5180 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
5181 mips_char_to_class
['e'] = M16_NA_REGS
;
5182 mips_char_to_class
['t'] = T_REG
;
5183 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
5184 mips_char_to_class
['h'] = HI_REG
;
5185 mips_char_to_class
['l'] = LO_REG
;
5186 mips_char_to_class
['a'] = HILO_REG
;
5187 mips_char_to_class
['x'] = MD_REGS
;
5188 mips_char_to_class
['b'] = ALL_REGS
;
5189 mips_char_to_class
['y'] = GR_REGS
;
5190 mips_char_to_class
['z'] = ST_REGS
;
5192 /* Set up array to map GCC register number to debug register number.
5193 Ignore the special purpose register numbers. */
5195 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5196 mips_dbx_regno
[i
] = -1;
5198 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
5199 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
5200 mips_dbx_regno
[i
] = i
+ start
;
5202 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
5203 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
5204 mips_dbx_regno
[i
] = i
+ start
;
5206 /* Set up array giving whether a given register can hold a given mode.
5207 At present, restrict ints from being in FP registers, because reload
5208 is a little enthusiastic about storing extra values in FP registers,
5209 and this is not good for things like OS kernels. Also, due to the
5210 mandatory delay, it is as fast to load from cached memory as to move
5211 from the FP register. */
5213 for (mode
= VOIDmode
;
5214 mode
!= MAX_MACHINE_MODE
;
5215 mode
= (enum machine_mode
) ((int)mode
+ 1))
5217 register int size
= GET_MODE_SIZE (mode
);
5218 register enum mode_class
class = GET_MODE_CLASS (mode
);
5220 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5227 temp
= (regno
== FPSW_REGNUM
);
5229 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5230 || FP_REG_P (regno
));
5233 else if (GP_REG_P (regno
))
5234 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5236 else if (FP_REG_P (regno
))
5237 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0)
5238 /* I think this change is OK regardless of abi, but
5239 I'm being cautions untill I can test this more.
5240 HARD_REGNO_MODE_OK is about whether or not you
5241 can move to and from a register without changing
5242 the value, not about whether math works on the
5244 || (mips_abi
== ABI_MEABI
&& size
<= 4))
5245 && (class == MODE_FLOAT
5246 || class == MODE_COMPLEX_FLOAT
5247 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
5248 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
5250 else if (MD_REG_P (regno
))
5251 temp
= (class == MODE_INT
5252 && (size
<= UNITS_PER_WORD
5253 || (regno
== MD_REG_FIRST
5254 && size
== 2 * UNITS_PER_WORD
)));
5259 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5263 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5264 initialized yet, so we can't use that here. */
5265 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5267 /* Provide default values for align_* for 64-bit targets. */
5268 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5270 if (align_loops
== 0)
5272 if (align_jumps
== 0)
5274 if (align_functions
== 0)
5275 align_functions
= 8;
5278 /* Register global variables with the garbage collector. */
5279 mips_add_gc_roots ();
5282 /* On the mips16, we want to allocate $24 (T_REG) before other
5283 registers for instructions for which it is possible. This helps
5284 avoid shuffling registers around in order to set up for an xor,
5285 encouraging the compiler to use a cmp instead. */
5288 mips_order_regs_for_local_alloc ()
5292 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5293 reg_alloc_order
[i
] = i
;
5297 /* It really doesn't matter where we put register 0, since it is
5298 a fixed register anyhow. */
5299 reg_alloc_order
[0] = 24;
5300 reg_alloc_order
[24] = 0;
5305 /* The MIPS debug format wants all automatic variables and arguments
5306 to be in terms of the virtual frame pointer (stack pointer before
5307 any adjustment in the function), while the MIPS 3.0 linker wants
5308 the frame pointer to be the stack pointer after the initial
5309 adjustment. So, we do the adjustment here. The arg pointer (which
5310 is eliminated) points to the virtual frame pointer, while the frame
5311 pointer (which may be eliminated) points to the stack pointer after
5312 the initial adjustments. */
5315 mips_debugger_offset (addr
, offset
)
5317 HOST_WIDE_INT offset
;
5319 rtx offset2
= const0_rtx
;
5320 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5323 offset
= INTVAL (offset2
);
5325 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5326 || reg
== hard_frame_pointer_rtx
)
5328 HOST_WIDE_INT frame_size
= (!current_frame_info
.initialized
)
5329 ? compute_frame_size (get_frame_size ())
5330 : current_frame_info
.total_size
;
5332 /* MIPS16 frame is smaller */
5333 if (frame_pointer_needed
&& TARGET_MIPS16
)
5334 frame_size
-= current_function_outgoing_args_size
;
5336 offset
= offset
- frame_size
;
5339 /* sdbout_parms does not want this to crash for unrecognized cases. */
5341 else if (reg
!= arg_pointer_rtx
)
5342 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer");
5348 /* A C compound statement to output to stdio stream STREAM the
5349 assembler syntax for an instruction operand X. X is an RTL
5352 CODE is a value that can be used to specify one of several ways
5353 of printing the operand. It is used when identical operands
5354 must be printed differently depending on the context. CODE
5355 comes from the `%' specification that was used to request
5356 printing of the operand. If the specification was just `%DIGIT'
5357 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5358 is the ASCII code for LTR.
5360 If X is a register, this macro should print the register's name.
5361 The names can be found in an array `reg_names' whose type is
5362 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5364 When the machine description has a specification `%PUNCT' (a `%'
5365 followed by a punctuation character), this macro is called with
5366 a null pointer for X and the punctuation character for CODE.
5368 The MIPS specific codes are:
5370 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5371 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5372 'd' output integer constant in decimal,
5373 'z' if the operand is 0, use $0 instead of normal operand.
5374 'D' print second part of double-word register or memory operand.
5375 'L' print low-order register of double-word register operand.
5376 'M' print high-order register of double-word register operand.
5377 'C' print part of opcode for a branch condition.
5378 'F' print part of opcode for a floating-point branch condition.
5379 'N' print part of opcode for a branch condition, inverted.
5380 'W' print part of opcode for a floating-point branch condition, inverted.
5381 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5382 'B' print 'z' for EQ, 'n' for NE
5383 'b' print 'n' for EQ, 'z' for NE
5384 'T' print 'f' for EQ, 't' for NE
5385 't' print 't' for EQ, 'f' for NE
5386 'Z' print register and a comma, but print nothing for $fcc0
5387 '(' Turn on .set noreorder
5388 ')' Turn on .set reorder
5389 '[' Turn on .set noat
5391 '<' Turn on .set nomacro
5392 '>' Turn on .set macro
5393 '{' Turn on .set volatile (not GAS)
5394 '}' Turn on .set novolatile (not GAS)
5395 '&' Turn on .set noreorder if filling delay slots
5396 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5397 '!' Turn on .set nomacro if filling delay slots
5398 '#' Print nop if in a .set noreorder section.
5399 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5400 '@' Print the name of the assembler temporary register (at or $1).
5401 '.' Print the name of the register with a hard-wired zero (zero or $0).
5402 '^' Print the name of the pic call-through register (t9 or $25).
5403 '$' Print the name of the stack pointer register (sp or $29).
5404 '+' Print the name of the gp register (gp or $28).
5405 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5408 print_operand (file
, op
, letter
)
5409 FILE *file
; /* file to write to */
5410 rtx op
; /* operand to print */
5411 int letter
; /* %<letter> or 0 */
5413 register enum rtx_code code
;
5415 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5420 if (mips_branch_likely
)
5425 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5429 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5433 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5437 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5441 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
5445 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5446 fputs (".set\tnoreorder\n\t", file
);
5450 if (final_sequence
!= 0)
5452 if (set_noreorder
++ == 0)
5453 fputs (".set\tnoreorder\n\t", file
);
5455 if (set_nomacro
++ == 0)
5456 fputs (".set\tnomacro\n\t", file
);
5461 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5462 fputs ("\n\t.set\tnomacro", file
);
5466 if (set_noreorder
!= 0)
5467 fputs ("\n\tnop", file
);
5468 else if (TARGET_STATS
)
5469 fputs ("\n\t#nop", file
);
5474 if (set_noreorder
++ == 0)
5475 fputs (".set\tnoreorder\n\t", file
);
5479 if (set_noreorder
== 0)
5480 error ("internal error: %%) found without a %%( in assembler pattern");
5482 else if (--set_noreorder
== 0)
5483 fputs ("\n\t.set\treorder", file
);
5488 if (set_noat
++ == 0)
5489 fputs (".set\tnoat\n\t", file
);
5494 error ("internal error: %%] found without a %%[ in assembler pattern");
5495 else if (--set_noat
== 0)
5496 fputs ("\n\t.set\tat", file
);
5501 if (set_nomacro
++ == 0)
5502 fputs (".set\tnomacro\n\t", file
);
5506 if (set_nomacro
== 0)
5507 error ("internal error: %%> found without a %%< in assembler pattern");
5508 else if (--set_nomacro
== 0)
5509 fputs ("\n\t.set\tmacro", file
);
5514 if (set_volatile
++ == 0)
5515 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
5519 if (set_volatile
== 0)
5520 error ("internal error: %%} found without a %%{ in assembler pattern");
5521 else if (--set_volatile
== 0)
5522 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
5528 if (align_labels_log
> 0)
5529 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5534 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5543 error ("PRINT_OPERAND null pointer");
5547 code
= GET_CODE (op
);
5549 if (code
== SIGN_EXTEND
)
5550 op
= XEXP (op
, 0), code
= GET_CODE (op
);
5555 case EQ
: fputs ("eq", file
); break;
5556 case NE
: fputs ("ne", file
); break;
5557 case GT
: fputs ("gt", file
); break;
5558 case GE
: fputs ("ge", file
); break;
5559 case LT
: fputs ("lt", file
); break;
5560 case LE
: fputs ("le", file
); break;
5561 case GTU
: fputs ("gtu", file
); break;
5562 case GEU
: fputs ("geu", file
); break;
5563 case LTU
: fputs ("ltu", file
); break;
5564 case LEU
: fputs ("leu", file
); break;
5566 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
5569 else if (letter
== 'N')
5572 case EQ
: fputs ("ne", file
); break;
5573 case NE
: fputs ("eq", file
); break;
5574 case GT
: fputs ("le", file
); break;
5575 case GE
: fputs ("lt", file
); break;
5576 case LT
: fputs ("ge", file
); break;
5577 case LE
: fputs ("gt", file
); break;
5578 case GTU
: fputs ("leu", file
); break;
5579 case GEU
: fputs ("ltu", file
); break;
5580 case LTU
: fputs ("geu", file
); break;
5581 case LEU
: fputs ("gtu", file
); break;
5583 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
5586 else if (letter
== 'F')
5589 case EQ
: fputs ("c1f", file
); break;
5590 case NE
: fputs ("c1t", file
); break;
5592 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
5595 else if (letter
== 'W')
5598 case EQ
: fputs ("c1t", file
); break;
5599 case NE
: fputs ("c1f", file
); break;
5601 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
5604 else if (letter
== 'S')
5608 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
5609 assemble_name (file
, buffer
);
5612 else if (letter
== 'Z')
5614 register int regnum
;
5619 regnum
= REGNO (op
);
5620 if (! ST_REG_P (regnum
))
5623 if (regnum
!= ST_REG_FIRST
)
5624 fprintf (file
, "%s,", reg_names
[regnum
]);
5627 else if (code
== REG
|| code
== SUBREG
)
5629 register int regnum
;
5632 regnum
= REGNO (op
);
5634 regnum
= true_regnum (op
);
5636 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5637 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5641 fprintf (file
, "%s", reg_names
[regnum
]);
5644 else if (code
== MEM
)
5647 output_address (plus_constant (XEXP (op
, 0), 4));
5649 output_address (XEXP (op
, 0));
5652 else if (code
== CONST_DOUBLE
5653 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
5658 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
5659 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
5663 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5664 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5666 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5667 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5669 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5670 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5672 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
5673 fputs (reg_names
[GP_REG_FIRST
], file
);
5675 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5676 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5678 else if (letter
== 'B')
5679 fputs (code
== EQ
? "z" : "n", file
);
5680 else if (letter
== 'b')
5681 fputs (code
== EQ
? "n" : "z", file
);
5682 else if (letter
== 'T')
5683 fputs (code
== EQ
? "f" : "t", file
);
5684 else if (letter
== 't')
5685 fputs (code
== EQ
? "t" : "f", file
);
5687 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
5689 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5690 print_operand (file
, XEXP (op
, 0), letter
);
5693 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
5695 fputs ("%gprel(", file
);
5696 mips16_output_gp_offset (file
, op
);
5701 output_addr_const (file
, op
);
5704 /* A C compound statement to output to stdio stream STREAM the
5705 assembler syntax for an instruction operand that is a memory
5706 reference whose address is ADDR. ADDR is an RTL expression.
5708 On some machines, the syntax for a symbolic address depends on
5709 the section that the address refers to. On these machines,
5710 define the macro `ENCODE_SECTION_INFO' to store the information
5711 into the `symbol_ref', and then check for it here. */
5714 print_operand_address (file
, addr
)
5719 error ("PRINT_OPERAND_ADDRESS, null pointer");
5722 switch (GET_CODE (addr
))
5725 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
5726 abort_with_insn (addr
, "arg pointer not eliminated");
5728 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
5733 register rtx arg0
= XEXP (addr
, 0);
5734 register rtx arg1
= XEXP (addr
, 1);
5736 if (! mips_split_addresses
)
5737 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5739 if (GET_CODE (arg0
) != REG
)
5740 abort_with_insn (addr
,
5741 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5743 fprintf (file
, "%%lo(");
5744 print_operand_address (file
, arg1
);
5745 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
5751 register rtx reg
= 0;
5752 register rtx offset
= 0;
5753 register rtx arg0
= XEXP (addr
, 0);
5754 register rtx arg1
= XEXP (addr
, 1);
5756 if (GET_CODE (arg0
) == REG
)
5760 if (GET_CODE (offset
) == REG
)
5761 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
5764 else if (GET_CODE (arg1
) == REG
)
5765 reg
= arg1
, offset
= arg0
;
5766 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
5768 output_addr_const (file
, addr
);
5772 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
5774 if (! CONSTANT_P (offset
))
5775 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5777 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
5778 abort_with_insn (addr
, "arg pointer not eliminated");
5781 && GET_CODE (offset
) == CONST
5782 && mips16_gp_offset_p (offset
))
5784 fputs ("%gprel(", file
);
5785 mips16_output_gp_offset (file
, offset
);
5789 output_addr_const (file
, offset
);
5790 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
5798 output_addr_const (file
, addr
);
5802 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5807 /* Target hook for assembling integer objects. It appears that the Irix
5808 6 assembler can't handle 64-bit decimal integers, so avoid printing
5809 such an integer here. */
5812 mips_assemble_integer (x
, size
, aligned_p
)
5817 if ((TARGET_64BIT
|| TARGET_GAS
) && size
== 8 && aligned_p
)
5819 fputs ("\t.dword\t", asm_out_file
);
5820 if (HOST_BITS_PER_WIDE_INT
< 64 || GET_CODE (x
) != CONST_INT
)
5821 output_addr_const (asm_out_file
, x
);
5823 print_operand (asm_out_file
, x
, 'X');
5824 fputc ('\n', asm_out_file
);
5827 return default_assemble_integer (x
, size
, aligned_p
);
5830 /* If optimizing for the global pointer, keep track of all of the externs, so
5831 that at the end of the file, we can emit the appropriate .extern
5832 declaration for them, before writing out the text section. We assume all
5833 names passed to us are in the permanent obstack, so they will be valid at
5834 the end of the compilation.
5836 If we have -G 0, or the extern size is unknown, or the object is in a user
5837 specified section that is not .sbss/.sdata, don't bother emitting the
5838 .externs. In the case of user specified sections this behaviour is
5839 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5842 mips_output_external (file
, decl
, name
)
5843 FILE *file ATTRIBUTE_UNUSED
;
5847 register struct extern_list
*p
;
5852 && TREE_CODE (decl
) != FUNCTION_DECL
5853 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
5854 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
5855 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
5856 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
5858 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5859 p
->next
= extern_head
;
5865 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5866 if (TREE_CODE (decl
) == FUNCTION_DECL
5867 /* ??? Don't include alloca, since gcc will always expand it
5868 inline. If we don't do this, the C++ library fails to build. */
5869 && strcmp (name
, "alloca")
5870 /* ??? Don't include __builtin_next_arg, because then gcc will not
5871 bootstrap under Irix 5.1. */
5872 && strcmp (name
, "__builtin_next_arg"))
5874 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5875 p
->next
= extern_head
;
5885 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5887 mips_output_external_libcall (file
, name
)
5888 FILE *file ATTRIBUTE_UNUSED
;
5891 register struct extern_list
*p
;
5893 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5894 p
->next
= extern_head
;
5903 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5904 for .file's that start within a function. If we are smuggling stabs, try to
5905 put out a MIPS ECOFF file and a stab. */
5908 mips_output_filename (stream
, name
)
5912 static int first_time
= 1;
5913 char ltext_label_name
[100];
5919 current_function_file
= name
;
5920 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5921 /* This tells mips-tfile that stabs will follow. */
5922 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
5923 fprintf (stream
, "\t#@stabs\n");
5926 else if (write_symbols
== DBX_DEBUG
)
5928 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
5929 fprintf (stream
, "%s", ASM_STABS_OP
);
5930 output_quoted_string (stream
, name
);
5931 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
5934 else if (name
!= current_function_file
5935 && strcmp (name
, current_function_file
) != 0)
5937 if (inside_function
&& !TARGET_GAS
)
5939 if (!file_in_function_warning
)
5941 file_in_function_warning
= 1;
5942 ignore_line_number
= 1;
5943 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5949 current_function_file
= name
;
5950 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5955 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5956 as well as a .loc, since it is possible that MIPS ECOFF might not be
5957 able to represent the location for inlines that come from a different
5961 mips_output_lineno (stream
, line
)
5965 if (write_symbols
== DBX_DEBUG
)
5968 fprintf (stream
, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5969 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
5970 LOCAL_LABEL_PREFIX
, sym_lineno
);
5974 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
5975 (ignore_line_number
) ? "#" : "",
5976 num_source_filenames
, line
);
5978 LABEL_AFTER_LOC (stream
);
5982 /* Output an ASCII string, in a space-saving way. */
5985 mips_output_ascii (stream
, string_param
, len
)
5987 const char *string_param
;
5992 register const unsigned char *string
=
5993 (const unsigned char *)string_param
;
5995 fprintf (stream
, "\t.ascii\t\"");
5996 for (i
= 0; i
< len
; i
++)
5998 register int c
= string
[i
];
6004 putc ('\\', stream
);
6009 case TARGET_NEWLINE
:
6010 fputs ("\\n", stream
);
6012 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
6013 || c
== TARGET_TAB
))
6014 cur_pos
= 32767; /* break right here */
6020 fputs ("\\t", stream
);
6025 fputs ("\\f", stream
);
6030 fputs ("\\b", stream
);
6035 fputs ("\\r", stream
);
6040 if (c
>= ' ' && c
< 0177)
6047 fprintf (stream
, "\\%03o", c
);
6052 if (cur_pos
> 72 && i
+1 < len
)
6055 fprintf (stream
, "\"\n\t.ascii\t\"");
6058 fprintf (stream
, "\"\n");
6061 /* If defined, a C statement to be executed just prior to the output of
6062 assembler code for INSN, to modify the extracted operands so they will be
6065 Here the argument OPVEC is the vector containing the operands extracted
6066 from INSN, and NOPERANDS is the number of elements of the vector which
6067 contain meaningful data for this insn. The contents of this vector are
6068 what will be used to convert the insn template into assembler code, so you
6069 can change the assembler output by changing the contents of the vector.
6071 We use it to check if the current insn needs a nop in front of it because
6072 of load delays, and also to update the delay slot statistics. */
6074 /* ??? There is no real need for this function, because it never actually
6075 emits a NOP anymore. */
6078 final_prescan_insn (insn
, opvec
, noperands
)
6080 rtx opvec
[] ATTRIBUTE_UNUSED
;
6081 int noperands ATTRIBUTE_UNUSED
;
6083 if (dslots_number_nops
> 0)
6085 rtx pattern
= PATTERN (insn
);
6086 int length
= get_attr_length (insn
);
6088 /* Do we need to emit a NOP? */
6090 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
6091 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
6092 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
6093 || (mips_load_reg4
!= 0
6094 && reg_mentioned_p (mips_load_reg4
, pattern
)))
6095 fputs ("\t#nop\n", asm_out_file
);
6098 dslots_load_filled
++;
6100 while (--dslots_number_nops
> 0)
6101 fputs ("\t#nop\n", asm_out_file
);
6110 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
6111 dslots_jump_total
++;
6114 /* Output at beginning of assembler file.
6116 If we are optimizing to use the global pointer, create a temporary file to
6117 hold all of the text stuff, and write it out to the end. This is needed
6118 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6119 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6120 processed, it generates a two instruction sequence. */
6123 mips_asm_file_start (stream
)
6126 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
6128 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6129 inside of a .set noreorder section jumps to a label outside of the .set
6130 noreorder section. Revision 2.20 just set nobopt silently rather than
6133 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
6134 fprintf (stream
, "\t.set\tnobopt\n");
6138 #if defined(OBJECT_FORMAT_ELF)
6139 /* Generate a special section to describe the ABI switches used to
6140 produce the resultant binary. This used to be done by the assembler
6141 setting bits in the ELF header's flags field, but we have run out of
6142 bits. GDB needs this information in order to be able to correctly
6143 debug these binaries. See the function mips_gdbarch_init() in
6145 const char * abi_string
= NULL
;
6149 case ABI_32
: abi_string
= "abi32"; break;
6150 case ABI_N32
: abi_string
= "abiN32"; break;
6151 case ABI_64
: abi_string
= "abi64"; break;
6152 case ABI_O64
: abi_string
= "abiO64"; break;
6153 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
6154 case ABI_MEABI
:abi_string
= TARGET_64BIT
? "meabi64" : "meabi32"; break;
6158 /* Note - we use fprintf directly rather than called named_section()
6159 because in this way we can avoid creating an allocated section. We
6160 do not want this section to take up any space in the running
6162 fprintf (stream
, "\t.section .mdebug.%s\n", abi_string
);
6164 /* Restore the default section. */
6165 fprintf (stream
, "\t.previous\n");
6171 /* Generate the pseudo ops that System V.4 wants. */
6172 #ifndef ABICALLS_ASM_OP
6173 #define ABICALLS_ASM_OP "\t.abicalls"
6175 if (TARGET_ABICALLS
)
6176 /* ??? but do not want this (or want pic0) if -non-shared? */
6177 fprintf (stream
, "%s\n", ABICALLS_ASM_OP
);
6180 fprintf (stream
, "\t.set\tmips16\n");
6182 /* This code exists so that we can put all externs before all symbol
6183 references. This is necessary for the MIPS assembler's global pointer
6184 optimizations to work. */
6185 if (TARGET_FILE_SWITCHING
)
6187 asm_out_data_file
= stream
;
6188 asm_out_text_file
= tmpfile ();
6191 asm_out_data_file
= asm_out_text_file
= stream
;
6193 if (flag_verbose_asm
)
6194 fprintf (stream
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6196 mips_section_threshold
, mips_arch_string
, mips_isa
);
6199 /* If we are optimizing the global pointer, emit the text section now and any
6200 small externs which did not have .comm, etc that are needed. Also, give a
6201 warning if the data area is more than 32K and -pic because 3 instructions
6202 are needed to reference the data pointers. */
6205 mips_asm_file_end (file
)
6209 struct extern_list
*p
;
6213 HALF_PIC_FINISH (file
);
6220 for (p
= extern_head
; p
!= 0; p
= p
->next
)
6222 name_tree
= get_identifier (p
->name
);
6224 /* Positively ensure only one .extern for any given symbol. */
6225 if (! TREE_ASM_WRITTEN (name_tree
))
6227 TREE_ASM_WRITTEN (name_tree
) = 1;
6228 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6230 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
6234 fputs ("\t.extern\t", file
);
6235 assemble_name (file
, p
->name
);
6236 fprintf (file
, ", %d\n", p
->size
);
6242 if (TARGET_FILE_SWITCHING
)
6244 fprintf (file
, "\n\t.text\n");
6245 copy_file_data (file
, asm_out_text_file
);
6250 copy_file_data (to
, from
)
6257 fatal_io_error ("can't rewind temp file");
6259 while ((len
= fread (buffer
, 1, sizeof (buffer
), from
)) > 0)
6260 if (fwrite (buffer
, 1, len
, to
) != len
)
6261 fatal_io_error ("can't write to output file");
6264 fatal_io_error ("can't read from temp file");
6267 fatal_io_error ("can't close temp file");
6270 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6271 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6274 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
6277 const char *init_string
;
6278 const char *final_string
;
6281 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
6282 assemble_name (stream
, name
);
6283 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
6287 tree name_tree
= get_identifier (name
);
6288 TREE_ASM_WRITTEN (name_tree
) = 1;
6292 /* Return the bytes needed to compute the frame pointer from the current
6295 Mips stack frames look like:
6297 Before call After call
6298 +-----------------------+ +-----------------------+
6301 | caller's temps. | | caller's temps. |
6303 +-----------------------+ +-----------------------+
6305 | arguments on stack. | | arguments on stack. |
6307 +-----------------------+ +-----------------------+
6308 | 4 words to save | | 4 words to save |
6309 | arguments passed | | arguments passed |
6310 | in registers, even | | in registers, even |
6311 SP->| if not passed. | VFP->| if not passed. |
6312 +-----------------------+ +-----------------------+
6314 | fp register save |
6316 +-----------------------+
6318 | gp register save |
6320 +-----------------------+
6324 +-----------------------+
6326 | alloca allocations |
6328 +-----------------------+
6330 | GP save for V.4 abi |
6332 +-----------------------+
6334 | arguments on stack |
6336 +-----------------------+
6338 | arguments passed |
6339 | in registers, even |
6340 low SP->| if not passed. |
6341 memory +-----------------------+
6346 compute_frame_size (size
)
6347 HOST_WIDE_INT size
; /* # of var. bytes allocated */
6350 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6351 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6352 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6353 HOST_WIDE_INT extra_size
; /* # extra bytes */
6354 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6355 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6356 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6357 long mask
; /* mask of saved gp registers */
6358 long fmask
; /* mask of saved fp registers */
6359 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
6360 long fp_bits
; /* bitmask to use for each fp register */
6366 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
6367 var_size
= MIPS_STACK_ALIGN (size
);
6368 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
6370 /* The MIPS 3.0 linker does not like functions that dynamically
6371 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6372 looks like we are trying to create a second frame pointer to the
6373 function, so allocate some stack space to make it happy. */
6375 if (args_size
== 0 && current_function_calls_alloca
)
6376 args_size
= 4 * UNITS_PER_WORD
;
6378 total_size
= var_size
+ args_size
+ extra_size
;
6380 /* Calculate space needed for gp registers. */
6381 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6383 /* $18 is a special case on the mips16. It may be used to call
6384 a function which returns a floating point value, but it is
6385 marked in call_used_regs. $31 is also a special case. When
6386 not using -mentry, it will be used to copy a return value
6387 into the floating point registers if the return value is
6389 if (MUST_SAVE_REGISTER (regno
)
6391 && regno
== GP_REG_FIRST
+ 18
6392 && regs_ever_live
[regno
])
6394 && regno
== GP_REG_FIRST
+ 31
6395 && mips16_hard_float
6397 && ! aggregate_value_p (DECL_RESULT (current_function_decl
))
6398 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl
)))
6400 && (! TARGET_SINGLE_FLOAT
6401 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl
)))
6404 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6405 mask
|= 1L << (regno
- GP_REG_FIRST
);
6407 /* The entry and exit pseudo instructions can not save $17
6408 without also saving $16. */
6410 && regno
== GP_REG_FIRST
+ 17
6411 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
6413 gp_reg_size
+= UNITS_PER_WORD
;
6419 /* We need to restore these for the handler. */
6420 if (current_function_calls_eh_return
)
6425 regno
= EH_RETURN_DATA_REGNO (i
);
6426 if (regno
== INVALID_REGNUM
)
6428 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6429 mask
|= 1L << (regno
- GP_REG_FIRST
);
6433 /* Calculate space needed for fp registers. */
6434 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
6445 /* This loop must iterate over the same space as its companion in
6446 save_restore_regs. */
6447 for (regno
= (FP_REG_LAST
- fp_inc
+ 1);
6448 regno
>= FP_REG_FIRST
;
6451 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6453 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
6454 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
6458 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6459 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6461 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6462 for leaf routines (total_size == extra_size) to save the gp reg.
6463 The gp reg is callee saved in the 64 bit ABI, so all routines must
6464 save the gp reg. This is not a leaf routine if -p, because of the
6466 if (total_size
== extra_size
6467 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
6469 total_size
= extra_size
= 0;
6470 else if (TARGET_ABICALLS
)
6472 /* Add the context-pointer to the saved registers. */
6473 gp_reg_size
+= UNITS_PER_WORD
;
6474 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
6475 total_size
-= gp_reg_rounded
;
6476 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6477 total_size
+= gp_reg_rounded
;
6480 /* Add in space reserved on the stack by the callee for storing arguments
6481 passed in registers. */
6482 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6483 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
6485 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6486 if (mips_entry
&& total_size
> 0 && total_size
< 32)
6489 /* Save other computed information. */
6490 current_frame_info
.total_size
= total_size
;
6491 current_frame_info
.var_size
= var_size
;
6492 current_frame_info
.args_size
= args_size
;
6493 current_frame_info
.extra_size
= extra_size
;
6494 current_frame_info
.gp_reg_size
= gp_reg_size
;
6495 current_frame_info
.fp_reg_size
= fp_reg_size
;
6496 current_frame_info
.mask
= mask
;
6497 current_frame_info
.fmask
= fmask
;
6498 current_frame_info
.initialized
= reload_completed
;
6499 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6500 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
6504 unsigned long offset
;
6506 /* When using mips_entry, the registers are always saved at the
6507 top of the stack. */
6509 offset
= (args_size
+ extra_size
+ var_size
6510 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6512 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
6514 current_frame_info
.gp_sp_offset
= offset
;
6515 current_frame_info
.gp_save_offset
= offset
- total_size
;
6519 current_frame_info
.gp_sp_offset
= 0;
6520 current_frame_info
.gp_save_offset
= 0;
6525 unsigned long offset
= (args_size
+ extra_size
+ var_size
6526 + gp_reg_rounded
+ fp_reg_size
6527 - fp_inc
* UNITS_PER_FPREG
);
6528 current_frame_info
.fp_sp_offset
= offset
;
6529 current_frame_info
.fp_save_offset
= offset
- total_size
;
6533 current_frame_info
.fp_sp_offset
= 0;
6534 current_frame_info
.fp_save_offset
= 0;
6537 /* Ok, we're done. */
6541 /* Common code to emit the insns (or to write the instructions to a file)
6542 to save/restore registers.
6544 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6545 is not modified within save_restore_insns. */
6547 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6549 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6550 and return an rtl expression for the register. Write the assembly
6551 instructions directly to FILE if it is not null, otherwise emit them as
6554 This function is a subroutine of save_restore_insns. It is used when
6555 OFFSET is too large to add in a single instruction. */
6558 mips_add_large_offset_to_sp (offset
, file
)
6559 HOST_WIDE_INT offset
;
6562 rtx reg
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6565 rtx offset_rtx
= GEN_INT (offset
);
6567 emit_move_insn (reg
, offset_rtx
);
6568 if (Pmode
== DImode
)
6569 emit_insn (gen_adddi3 (reg
, reg
, stack_pointer_rtx
));
6571 emit_insn (gen_addsi3 (reg
, reg
, stack_pointer_rtx
));
6575 fprintf (file
, "\tli\t%s,0x%.08lx\t# ",
6576 reg_names
[MIPS_TEMP2_REGNUM
], (long) offset
);
6577 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6578 fprintf (file
, "\n\t%s\t%s,%s,%s\n",
6579 Pmode
== DImode
? "daddu" : "addu",
6580 reg_names
[MIPS_TEMP2_REGNUM
],
6581 reg_names
[MIPS_TEMP2_REGNUM
],
6582 reg_names
[STACK_POINTER_REGNUM
]);
6587 /* Make INSN frame related and note that it performs the frame-related
6588 operation DWARF_PATTERN. */
6591 mips_annotate_frame_insn (insn
, dwarf_pattern
)
6592 rtx insn
, dwarf_pattern
;
6594 RTX_FRAME_RELATED_P (insn
) = 1;
6595 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6600 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6601 The expression should only be used to store single registers. */
6604 mips_frame_set (mode
, regno
, offset
)
6605 enum machine_mode mode
;
6609 rtx address
= plus_constant (stack_pointer_rtx
, offset
);
6610 rtx set
= gen_rtx_SET (mode
,
6611 gen_rtx_MEM (mode
, address
),
6612 gen_rtx_REG (mode
, regno
));
6613 RTX_FRAME_RELATED_P (set
) = 1;
6618 /* Emit a move instruction that stores REG in MEM. Make the instruction
6619 frame related and note that it stores REG at (SP + OFFSET). This
6620 function may be asked to store an FPR pair. */
6623 mips_emit_frame_related_store (mem
, reg
, offset
)
6626 HOST_WIDE_INT offset
;
6630 if (GET_MODE (reg
) == DFmode
&& ! TARGET_FLOAT64
)
6632 /* Two registers are being stored, so the frame-related expression
6633 must be a PARALLEL rtx with one SET for each register. The
6634 higher numbered register is stored in the lower address on
6635 big-endian targets. */
6636 int regno1
= TARGET_BIG_ENDIAN
? REGNO (reg
) + 1 : REGNO (reg
);
6637 int regno2
= TARGET_BIG_ENDIAN
? REGNO (reg
) : REGNO (reg
) + 1;
6638 rtx set1
= mips_frame_set (SFmode
, regno1
, offset
);
6639 rtx set2
= mips_frame_set (SFmode
, regno2
, offset
+ UNITS_PER_FPREG
);
6640 dwarf_expr
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set1
, set2
));
6643 dwarf_expr
= mips_frame_set (GET_MODE (reg
), REGNO (reg
), offset
);
6645 mips_annotate_frame_insn (emit_move_insn (mem
, reg
), dwarf_expr
);
6649 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
6650 int store_p
; /* true if this is prologue */
6651 rtx large_reg
; /* register holding large offset constant or NULL */
6652 long large_offset
; /* large constant offset value */
6653 FILE *file
; /* file to write instructions instead of making RTL */
6655 long mask
= current_frame_info
.mask
;
6656 long fmask
= current_frame_info
.fmask
;
6657 long real_mask
= mask
;
6660 HOST_WIDE_INT base_offset
;
6661 HOST_WIDE_INT gp_offset
;
6662 HOST_WIDE_INT fp_offset
;
6663 HOST_WIDE_INT end_offset
;
6666 if (frame_pointer_needed
6667 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
6670 /* Do not restore GP under certain conditions. */
6673 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
6674 mask
&= ~(1 << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
));
6676 if (mask
== 0 && fmask
== 0)
6679 /* Save registers starting from high to low. The debuggers prefer at least
6680 the return register be stored at func+4, and also it allows us not to
6681 need a nop in the epilog if at least one register is reloaded in
6682 addition to return address. */
6684 /* Save GP registers if needed. */
6687 /* Pick which pointer to use as a base register. For small frames, just
6688 use the stack pointer. Otherwise, use a temporary register. Save 2
6689 cycles if the save area is near the end of a large frame, by reusing
6690 the constant created in the prologue/epilogue to adjust the stack
6693 gp_offset
= current_frame_info
.gp_sp_offset
;
6695 = gp_offset
- (current_frame_info
.gp_reg_size
6696 - GET_MODE_SIZE (gpr_mode
));
6698 if (gp_offset
< 0 || end_offset
< 0)
6700 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6701 (long) gp_offset
, (long) end_offset
);
6703 /* If we see a large frame in mips16 mode, we save the registers
6704 before adjusting the stack pointer, and load them afterward. */
6705 else if (TARGET_MIPS16
&& large_offset
> 32767)
6706 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
6708 else if (gp_offset
< 32768)
6709 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6711 else if (large_reg
!= 0
6712 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
6713 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6715 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6716 base_offset
= large_offset
;
6719 if (Pmode
== DImode
)
6720 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6721 stack_pointer_rtx
));
6723 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6724 stack_pointer_rtx
));
6727 fprintf (file
, "\t%s\t%s,%s,%s\n",
6728 Pmode
== DImode
? "daddu" : "addu",
6729 reg_names
[MIPS_TEMP2_REGNUM
],
6730 reg_names
[REGNO (large_reg
)],
6731 reg_names
[STACK_POINTER_REGNUM
]);
6735 base_offset
= gp_offset
;
6736 base_reg_rtx
= mips_add_large_offset_to_sp (base_offset
, file
);
6739 /* When we restore the registers in MIPS16 mode, then if we are
6740 using a frame pointer, and this is not a large frame, the
6741 current stack pointer will be offset by
6742 current_function_outgoing_args_size. Doing it this way lets
6743 us avoid offsetting the frame pointer before copying it into
6744 the stack pointer; there is no instruction to set the stack
6745 pointer to the sum of a register and a constant. */
6748 && frame_pointer_needed
6749 && large_offset
<= 32767)
6750 base_offset
+= current_function_outgoing_args_size
;
6752 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6753 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
6759 = gen_rtx (MEM
, gpr_mode
,
6760 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6761 GEN_INT (gp_offset
- base_offset
)));
6763 if (! current_function_calls_eh_return
)
6764 RTX_UNCHANGING_P (mem_rtx
) = 1;
6766 /* The mips16 does not have an instruction to load
6767 $31, so we load $7 instead, and work things out
6769 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
6770 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
6771 /* The mips16 sometimes needs to save $18. */
6772 else if (TARGET_MIPS16
6773 && regno
!= GP_REG_FIRST
+ 31
6774 && ! M16_REG_P (regno
))
6777 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
6780 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
6781 emit_move_insn (reg_rtx
,
6782 gen_rtx (REG
, gpr_mode
, regno
));
6786 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
6789 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, gp_offset
);
6792 emit_move_insn (reg_rtx
, mem_rtx
);
6794 && regno
!= GP_REG_FIRST
+ 31
6795 && ! M16_REG_P (regno
))
6796 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
6804 /* The mips16 does not have an instruction to
6805 load $31, so we load $7 instead, and work
6806 things out in the caller. */
6807 if (TARGET_MIPS16
&& ! store_p
&& r
== GP_REG_FIRST
+ 31)
6808 r
= GP_REG_FIRST
+ 7;
6809 /* The mips16 sometimes needs to save $18. */
6811 && regno
!= GP_REG_FIRST
+ 31
6812 && ! M16_REG_P (regno
))
6815 r
= GP_REG_FIRST
+ 6;
6818 r
= GP_REG_FIRST
+ 3;
6819 fprintf (file
, "\tmove\t%s,%s\n",
6820 reg_names
[r
], reg_names
[regno
]);
6823 fprintf (file
, "\t%s\t%s,",
6825 ? (store_p
) ? "sd" : "ld"
6826 : (store_p
) ? "sw" : "lw"),
6828 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6829 gp_offset
- base_offset
);
6830 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
6833 && regno
!= GP_REG_FIRST
+ 31
6834 && ! M16_REG_P (regno
))
6835 fprintf (file
, "\tmove\t%s,%s\n",
6836 reg_names
[regno
], reg_names
[r
]);
6838 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
6840 /* If the restore is being supressed, still take into account
6841 the offset at which it is stored. */
6842 else if (BITSET_P (real_mask
, regno
- GP_REG_FIRST
))
6844 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
6848 base_reg_rtx
= 0, base_offset
= 0;
6850 /* Save floating point registers if needed. */
6853 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
6854 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
6856 /* Pick which pointer to use as a base register. */
6857 fp_offset
= current_frame_info
.fp_sp_offset
;
6858 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
6860 if (fp_offset
< 0 || end_offset
< 0)
6862 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
6863 (long) fp_offset
, (long) end_offset
);
6865 else if (fp_offset
< 32768)
6866 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6868 else if (base_reg_rtx
!= 0
6869 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
6870 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
6871 ; /* already set up for gp registers above */
6873 else if (large_reg
!= 0
6874 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
6875 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6877 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6878 base_offset
= large_offset
;
6881 if (Pmode
== DImode
)
6882 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6883 stack_pointer_rtx
));
6885 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6886 stack_pointer_rtx
));
6890 fprintf (file
, "\t%s\t%s,%s,%s\n",
6891 Pmode
== DImode
? "daddu" : "addu",
6892 reg_names
[MIPS_TEMP2_REGNUM
],
6893 reg_names
[REGNO (large_reg
)],
6894 reg_names
[STACK_POINTER_REGNUM
]);
6898 base_offset
= fp_offset
;
6899 base_reg_rtx
= mips_add_large_offset_to_sp (fp_offset
, file
);
6902 /* This loop must iterate over the same space as its companion in
6903 compute_frame_size. */
6904 for (regno
= (FP_REG_LAST
- fp_inc
+ 1);
6905 regno
>= FP_REG_FIRST
;
6907 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
6911 enum machine_mode sz
6912 = TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6913 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
6914 rtx mem_rtx
= gen_rtx (MEM
, sz
,
6915 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6918 if (! current_function_calls_eh_return
)
6919 RTX_UNCHANGING_P (mem_rtx
) = 1;
6922 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, fp_offset
);
6924 emit_move_insn (reg_rtx
, mem_rtx
);
6928 fprintf (file
, "\t%s\t%s,",
6929 (TARGET_SINGLE_FLOAT
6930 ? (store_p
? "s.s" : "l.s")
6931 : (store_p
? "s.d" : "l.d")),
6933 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6934 fp_offset
- base_offset
);
6935 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
6938 fp_offset
-= fp_size
;
6943 /* Set up the stack and frame (if desired) for the function. */
6946 mips_output_function_prologue (file
, size
)
6948 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
6950 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6953 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
6955 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
6957 #ifdef SDB_DEBUGGING_INFO
6958 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
6959 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
6962 /* In mips16 mode, we may need to generate a 32 bit to handle
6963 floating point arguments. The linker will arrange for any 32 bit
6964 functions to call this stub, which will then jump to the 16 bit
6966 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
6967 && current_function_args_info
.fp_code
!= 0)
6968 build_mips16_function_stub (file
);
6970 inside_function
= 1;
6972 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6973 /* Get the function name the same way that toplev.c does before calling
6974 assemble_start_function. This is needed so that the name used here
6975 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6976 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6978 if (!flag_inhibit_size_directive
)
6980 fputs ("\t.ent\t", file
);
6981 assemble_name (file
, fnname
);
6985 assemble_name (file
, fnname
);
6986 fputs (":\n", file
);
6989 if (!flag_inhibit_size_directive
)
6991 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6993 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6994 (reg_names
[(frame_pointer_needed
)
6995 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
6996 ((frame_pointer_needed
&& TARGET_MIPS16
)
6997 ? ((long) tsize
- current_function_outgoing_args_size
)
6999 reg_names
[GP_REG_FIRST
+ 31],
7000 current_frame_info
.var_size
,
7001 current_frame_info
.num_gp
,
7002 current_frame_info
.num_fp
,
7003 current_function_outgoing_args_size
,
7004 current_frame_info
.extra_size
);
7006 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7007 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7008 current_frame_info
.mask
,
7009 current_frame_info
.gp_save_offset
,
7010 current_frame_info
.fmask
,
7011 current_frame_info
.fp_save_offset
);
7014 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7015 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7018 if (mips_entry
&& ! mips_can_use_return_insn ())
7020 int save16
= BITSET_P (current_frame_info
.mask
, 16);
7021 int save17
= BITSET_P (current_frame_info
.mask
, 17);
7022 int save31
= BITSET_P (current_frame_info
.mask
, 31);
7026 /* Look through the initial insns to see if any of them store
7027 the function parameters into the incoming parameter storage
7028 area. If they do, we delete the insn, and save the register
7029 using the entry pseudo-instruction instead. We don't try to
7030 look past a label, jump, or call. */
7031 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
7033 rtx note
, set
, src
, dest
, base
, offset
;
7036 if (GET_CODE (insn
) == CODE_LABEL
7037 || GET_CODE (insn
) == JUMP_INSN
7038 || GET_CODE (insn
) == CALL_INSN
)
7040 if (GET_CODE (insn
) != INSN
)
7042 set
= PATTERN (insn
);
7043 if (GET_CODE (set
) != SET
)
7046 /* An insn storing a function parameter will still have a
7047 REG_EQUIV note on it mentioning the argument pointer. */
7048 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
7049 if (note
== NULL_RTX
)
7051 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
7054 src
= SET_SRC (set
);
7055 if (GET_CODE (src
) != REG
7056 || REGNO (src
) < GP_REG_FIRST
+ 4
7057 || REGNO (src
) > GP_REG_FIRST
+ 7)
7060 dest
= SET_DEST (set
);
7061 if (GET_CODE (dest
) != MEM
)
7063 if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned) UNITS_PER_WORD
)
7065 else if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned)2 * UNITS_PER_WORD
7066 && REGNO (src
) < GP_REG_FIRST
+ 7)
7070 offset
= const0_rtx
;
7071 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
7072 if (GET_CODE (base
) != REG
7073 || GET_CODE (offset
) != CONST_INT
)
7075 if (REGNO (base
) == (unsigned) STACK_POINTER_REGNUM
7076 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
7078 else if (REGNO (base
) == (unsigned) HARD_FRAME_POINTER_REGNUM
7081 + (REGNO (src
) - 4) * UNITS_PER_WORD
7082 - current_function_outgoing_args_size
)))
7087 /* This insn stores a parameter onto the stack, in the same
7088 location where the entry pseudo-instruction will put it.
7089 Delete the insn, and arrange to tell the entry
7090 instruction to save the register. */
7091 PUT_CODE (insn
, NOTE
);
7092 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7093 NOTE_SOURCE_FILE (insn
) = 0;
7095 hireg
= (REGNO (src
)
7096 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
7098 if (hireg
> savearg
)
7102 /* If this is a varargs function, we need to save all the
7103 registers onto the stack anyhow. */
7104 if (current_function_stdarg
|| current_function_varargs
)
7105 savearg
= GP_REG_FIRST
+ 7;
7107 fprintf (file
, "\tentry\t");
7110 if (savearg
== GP_REG_FIRST
+ 4)
7111 fprintf (file
, "%s", reg_names
[savearg
]);
7113 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
7114 reg_names
[savearg
]);
7116 if (save16
|| save17
)
7119 fprintf (file
, ",");
7120 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
7122 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
7126 if (savearg
> 0 || save16
|| save17
)
7127 fprintf (file
, ",");
7128 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
7130 fprintf (file
, "\n");
7133 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7135 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7137 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7138 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
7141 fprintf (file
, "\t%s\t%s,%s,%ld\n",
7142 (Pmode
== DImode
? "dsubu" : "subu"),
7143 sp_str
, sp_str
, (long) tsize
);
7144 fprintf (file
, "\t.cprestore %ld\n", current_frame_info
.args_size
);
7147 if (dwarf2out_do_frame ())
7148 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
7152 /* Expand the prologue into a bunch of separate insns. */
7155 mips_expand_prologue ()
7158 HOST_WIDE_INT tsize
;
7160 int last_arg_is_vararg_marker
= 0;
7161 tree fndecl
= current_function_decl
;
7162 tree fntype
= TREE_TYPE (fndecl
);
7163 tree fnargs
= DECL_ARGUMENTS (fndecl
);
7168 CUMULATIVE_ARGS args_so_far
;
7169 rtx reg_18_save
= NULL_RTX
;
7170 int store_args_on_stack
= (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
7171 && (! mips_entry
|| mips_can_use_return_insn ());
7173 /* If struct value address is treated as the first argument, make it so. */
7174 if (aggregate_value_p (DECL_RESULT (fndecl
))
7175 && ! current_function_returns_pcc_struct
7176 && struct_value_incoming_rtx
== 0)
7178 tree type
= build_pointer_type (fntype
);
7179 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
7181 DECL_ARG_TYPE (function_result_decl
) = type
;
7182 TREE_CHAIN (function_result_decl
) = fnargs
;
7183 fnargs
= function_result_decl
;
7186 /* For arguments passed in registers, find the register number
7187 of the first argument in the variable part of the argument list,
7188 otherwise GP_ARG_LAST+1. Note also if the last argument is
7189 the varargs special argument, and treat it as part of the
7192 This is only needed if store_args_on_stack is true. */
7194 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
7195 regno
= GP_ARG_FIRST
;
7197 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
7199 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
7200 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
7203 if (TREE_ADDRESSABLE (passed_type
))
7205 passed_type
= build_pointer_type (passed_type
);
7206 passed_mode
= Pmode
;
7209 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
7211 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
7212 next_arg
= TREE_CHAIN (cur_arg
);
7214 if (entry_parm
&& store_args_on_stack
)
7217 && DECL_NAME (cur_arg
)
7218 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7219 "__builtin_va_alist"))
7220 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7223 last_arg_is_vararg_marker
= 1;
7230 if (GET_CODE (entry_parm
) != REG
)
7233 /* passed in a register, so will get homed automatically */
7234 if (GET_MODE (entry_parm
) == BLKmode
)
7235 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
7237 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
7239 regno
= REGNO (entry_parm
) + words
- 1;
7244 regno
= GP_ARG_LAST
+1;
7249 /* In order to pass small structures by value in registers compatibly with
7250 the MIPS compiler, we need to shift the value into the high part of the
7251 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7252 adjustments to be made as the next_arg_reg variable, so we split up the
7253 insns, and emit them separately. */
7255 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
7256 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
7258 rtvec adjust
= XVEC (next_arg_reg
, 0);
7259 int num
= GET_NUM_ELEM (adjust
);
7261 for (i
= 0; i
< num
; i
++)
7265 pattern
= RTVEC_ELT (adjust
, i
);
7266 if (GET_CODE (pattern
) != SET
7267 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
7268 abort_with_insn (pattern
, "insn is not a shift");
7269 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
7271 insn
= emit_insn (pattern
);
7273 /* Global life information isn't valid at this point, so we
7274 can't check whether these shifts are actually used. Mark
7275 them MAYBE_DEAD so that flow2 will remove them, and not
7276 complain about dead code in the prologue. */
7277 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, NULL_RTX
,
7282 tsize
= compute_frame_size (get_frame_size ());
7284 /* If this function is a varargs function, store any registers that
7285 would normally hold arguments ($4 - $7) on the stack. */
7286 if (store_args_on_stack
7287 && ((TYPE_ARG_TYPES (fntype
) != 0
7288 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
7290 || last_arg_is_vararg_marker
))
7292 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
7293 rtx ptr
= stack_pointer_rtx
;
7295 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7296 if (TARGET_ABICALLS
)
7299 for (; regno
<= GP_ARG_LAST
; regno
++)
7302 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
7303 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
7304 gen_rtx (REG
, gpr_mode
, regno
));
7306 offset
+= GET_MODE_SIZE (gpr_mode
);
7310 /* If we are using the entry pseudo instruction, it will
7311 automatically subtract 32 from the stack pointer, so we don't
7312 need to. The entry pseudo instruction is emitted by
7313 function_prologue. */
7314 if (mips_entry
&& ! mips_can_use_return_insn ())
7316 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
7320 /* If we are using a frame pointer with a small stack frame,
7321 we need to initialize it here since it won't be done
7323 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7325 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7326 if (Pmode
== DImode
)
7327 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7331 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7335 else if (Pmode
== DImode
)
7336 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7337 stack_pointer_rtx
));
7339 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7340 stack_pointer_rtx
));
7342 RTX_FRAME_RELATED_P (insn
) = 1;
7345 /* We may need to save $18, if it is used to call a function
7346 which may return a floating point value. Set up a sequence
7347 of instructions to do so. Later on we emit them at the right
7349 if (TARGET_MIPS16
&& BITSET_P (current_frame_info
.mask
, 18))
7351 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
7352 long gp_offset
, base_offset
;
7354 gp_offset
= current_frame_info
.gp_sp_offset
;
7355 if (BITSET_P (current_frame_info
.mask
, 16))
7356 gp_offset
-= UNITS_PER_WORD
;
7357 if (BITSET_P (current_frame_info
.mask
, 17))
7358 gp_offset
-= UNITS_PER_WORD
;
7359 if (BITSET_P (current_frame_info
.mask
, 31))
7360 gp_offset
-= UNITS_PER_WORD
;
7362 base_offset
= tsize
;
7366 emit_move_insn (reg_rtx
,
7367 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
7368 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
7369 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
7373 reg_18_save
= gen_sequence ();
7382 if (reg_18_save
!= NULL_RTX
)
7383 emit_insn (reg_18_save
);
7389 rtx tsize_rtx
= GEN_INT (tsize
);
7391 /* If we are doing svr4-abi, sp move is done by
7392 function_prologue. In mips16 mode with a large frame, we
7393 save the registers before adjusting the stack. */
7394 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7395 && (!TARGET_MIPS16
|| tsize
<= 32767))
7397 rtx adjustment_rtx
, insn
, dwarf_pattern
;
7401 adjustment_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
7402 emit_move_insn (adjustment_rtx
, tsize_rtx
);
7405 adjustment_rtx
= tsize_rtx
;
7407 if (Pmode
== DImode
)
7408 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7411 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7414 dwarf_pattern
= gen_rtx_SET (Pmode
, stack_pointer_rtx
,
7415 plus_constant (stack_pointer_rtx
,
7418 mips_annotate_frame_insn (insn
, dwarf_pattern
);
7422 save_restore_insns (1, tmp_rtx
, tsize
, (FILE *)0);
7423 else if (reg_18_save
!= NULL_RTX
)
7424 emit_insn (reg_18_save
);
7426 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7432 if (!frame_pointer_needed
)
7435 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
7436 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7437 emit_move_insn (reg_rtx
, tsize_rtx
);
7438 if (Pmode
== DImode
)
7439 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
7440 hard_frame_pointer_rtx
,
7443 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
7444 hard_frame_pointer_rtx
,
7446 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
7449 if (frame_pointer_needed
)
7453 /* On the mips16, we encourage the use of unextended
7454 instructions when using the frame pointer by pointing the
7455 frame pointer ahead of the argument space allocated on
7457 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7461 /* In this case, we have already copied the stack
7462 pointer into the frame pointer, above. We need only
7463 adjust for the outgoing argument size. */
7464 if (current_function_outgoing_args_size
!= 0)
7466 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7467 if (Pmode
== DImode
)
7468 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7469 hard_frame_pointer_rtx
,
7472 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7473 hard_frame_pointer_rtx
,
7477 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7479 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7480 if (Pmode
== DImode
)
7481 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7485 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7489 else if (Pmode
== DImode
)
7490 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7491 stack_pointer_rtx
));
7493 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7494 stack_pointer_rtx
));
7497 RTX_FRAME_RELATED_P (insn
) = 1;
7500 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7501 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
7502 gen_rtx_REG (DImode
, 25)));
7505 /* If we are profiling, make sure no instructions are scheduled before
7506 the call to mcount. */
7509 emit_insn (gen_blockage ());
7512 /* Do any necessary cleanup after a function to restore stack, frame,
7515 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7516 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7519 mips_output_function_epilogue (file
, size
)
7520 FILE *file ATTRIBUTE_UNUSED
;
7521 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7523 const char *fnname
= ""; /* FIXME: Correct initialisation? */
7525 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7526 /* Get the function name the same way that toplev.c does before calling
7527 assemble_start_function. This is needed so that the name used here
7528 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7529 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7531 if (!flag_inhibit_size_directive
)
7533 fputs ("\t.end\t", file
);
7534 assemble_name (file
, fnname
);
7541 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
7542 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
7543 int num_regs
= num_gp_regs
+ num_fp_regs
;
7544 const char *name
= fnname
;
7549 dslots_load_total
+= num_regs
;
7552 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7553 name
, frame_pointer_needed
? 'y' : 'n',
7554 (current_frame_info
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
7555 current_function_calls_alloca
? 'y' : 'n',
7556 current_function_calls_setjmp
? 'y' : 'n',
7557 current_frame_info
.total_size
,
7558 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
7559 dslots_load_total
, dslots_load_filled
,
7560 dslots_jump_total
, dslots_jump_filled
,
7561 num_refs
[0], num_refs
[1], num_refs
[2]);
7563 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
7566 " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
7567 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
7570 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
7573 " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
7574 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
7577 fputc ('\n', stderr
);
7580 /* Reset state info for each function. */
7581 inside_function
= 0;
7582 ignore_line_number
= 0;
7583 dslots_load_total
= 0;
7584 dslots_jump_total
= 0;
7585 dslots_load_filled
= 0;
7586 dslots_jump_filled
= 0;
7592 current_frame_info
= zero_frame_info
;
7594 while (string_constants
!= NULL
)
7596 struct string_constant
*next
;
7598 next
= string_constants
->next
;
7599 free (string_constants
);
7600 string_constants
= next
;
7603 /* Restore the output file if optimizing the GP (optimizing the GP causes
7604 the text to be diverted to a tempfile, so that data decls come before
7605 references to the data). */
7606 if (TARGET_FILE_SWITCHING
)
7608 asm_out_file
= asm_out_data_file
;
7613 /* Expand the epilogue into a bunch of separate insns. */
7616 mips_expand_epilogue ()
7618 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7619 rtx tsize_rtx
= GEN_INT (tsize
);
7620 rtx tmp_rtx
= (rtx
)0;
7622 if (mips_can_use_return_insn ())
7624 emit_insn (gen_return ());
7628 if (mips_entry
&& ! mips_can_use_return_insn ())
7631 if (tsize
> 32767 && ! TARGET_MIPS16
)
7633 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
7634 emit_move_insn (tmp_rtx
, tsize_rtx
);
7635 tsize_rtx
= tmp_rtx
;
7640 long orig_tsize
= tsize
;
7642 if (frame_pointer_needed
)
7644 emit_insn (gen_blockage ());
7646 /* On the mips16, the frame pointer is offset from the stack
7647 pointer by current_function_outgoing_args_size. We
7648 account for that by changing tsize. Note that this can
7649 actually make tsize negative. */
7652 tsize
-= current_function_outgoing_args_size
;
7654 /* If we have a large frame, it's easier to add to $17
7655 than to $sp, since the mips16 has no instruction to
7656 add a register to $sp. */
7657 if (orig_tsize
> 32767)
7659 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7661 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
7662 if (Pmode
== DImode
)
7663 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7664 hard_frame_pointer_rtx
,
7667 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7668 hard_frame_pointer_rtx
,
7673 if (tsize
&& tsize
!= orig_tsize
)
7674 tsize_rtx
= GEN_INT (tsize
);
7677 if (Pmode
== DImode
)
7678 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7680 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7683 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7684 are going to restore it, then we must emit a blockage insn to
7685 prevent the scheduler from moving the restore out of the epilogue. */
7686 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
7687 && (current_frame_info
.mask
7688 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
7689 emit_insn (gen_blockage ());
7691 save_restore_insns (0, tmp_rtx
, orig_tsize
, (FILE *)0);
7693 /* In mips16 mode with a large frame, we adjust the stack
7694 pointer before restoring the registers. In this case, we
7695 should always be using a frame pointer, so everything should
7696 have been handled above. */
7697 if (tsize
> 32767 && TARGET_MIPS16
)
7700 if (current_function_calls_eh_return
)
7702 rtx eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7703 if (Pmode
== DImode
)
7704 emit_insn (gen_adddi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7706 emit_insn (gen_addsi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7710 emit_insn (gen_blockage ());
7712 if (tsize
!= 0 || current_function_calls_eh_return
)
7714 if (Pmode
== DImode
)
7715 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7718 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7723 /* The mips16 loads the return address into $7, not $31. */
7724 if (TARGET_MIPS16
&& (current_frame_info
.mask
& RA_MASK
) != 0)
7725 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7726 GP_REG_FIRST
+ 7)));
7728 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7729 GP_REG_FIRST
+ 31)));
7732 /* Return nonzero if this function is known to have a null epilogue.
7733 This allows the optimizer to omit jumps to jumps if no stack
7737 mips_can_use_return_insn ()
7739 if (! reload_completed
)
7742 if (regs_ever_live
[31] || profile_flag
)
7745 /* In mips16 mode, a function which returns a floating point value
7746 needs to arrange to copy the return value into the floating point
7749 && mips16_hard_float
7750 && ! aggregate_value_p (DECL_RESULT (current_function_decl
))
7751 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl
)))
7753 && (! TARGET_SINGLE_FLOAT
7754 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl
)))
7758 if (current_frame_info
.initialized
)
7759 return current_frame_info
.total_size
== 0;
7761 return compute_frame_size (get_frame_size ()) == 0;
7764 /* Returns non-zero if X contains a SYMBOL_REF. */
7767 symbolic_expression_p (x
)
7770 if (GET_CODE (x
) == SYMBOL_REF
)
7773 if (GET_CODE (x
) == CONST
)
7774 return symbolic_expression_p (XEXP (x
, 0));
7776 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
7777 return symbolic_expression_p (XEXP (x
, 0));
7779 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
7780 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
7781 return (symbolic_expression_p (XEXP (x
, 0))
7782 || symbolic_expression_p (XEXP (x
, 1)));
7787 /* Choose the section to use for the constant rtx expression X that has
7791 mips_select_rtx_section (mode
, x
)
7792 enum machine_mode mode
;
7793 rtx x ATTRIBUTE_UNUSED
;
7797 /* In mips16 mode, the constant table always goes in the same section
7798 as the function, so that constants can be loaded using PC relative
7800 function_section (current_function_decl
);
7802 else if (TARGET_EMBEDDED_DATA
)
7804 /* For embedded applications, always put constants in read-only data,
7805 in order to reduce RAM usage. */
7806 READONLY_DATA_SECTION ();
7810 /* For hosted applications, always put constants in small data if
7811 possible, as this gives the best performance. */
7813 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
7814 && mips_section_threshold
> 0)
7815 SMALL_DATA_SECTION ();
7816 else if (flag_pic
&& symbolic_expression_p (x
))
7817 /* Any expression involving a SYMBOL_REF might need a run-time
7818 relocation. (The symbol might be defined in a shared
7819 library loaded at an unexpected base address.) So, we must
7820 put such expressions in the data segment (which is
7821 writable), rather than the text segment (which is
7825 READONLY_DATA_SECTION ();
7829 /* Choose the section to use for DECL. RELOC is true if its value contains
7830 any relocatable expression.
7832 Some of the logic used here needs to be replicated in
7833 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7834 are done correctly. Specifically, at least all symbols assigned
7835 here to rom (.text and/or .rodata) must not be referenced via
7836 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7838 If you need to make a change here, you probably should check
7839 ENCODE_SECTION_INFO to see if it needs a similar change. */
7842 mips_select_section (decl
, reloc
)
7846 int size
= int_size_in_bytes (TREE_TYPE (decl
));
7848 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
7849 && TREE_CODE (decl
) == STRING_CST
7850 && !flag_writable_strings
)
7851 /* For embedded position independent code, put constant strings in the
7852 text section, because the data section is limited to 64K in size.
7853 For mips16 code, put strings in the text section so that a PC
7854 relative load instruction can be used to get their address. */
7856 else if (TARGET_EMBEDDED_DATA
)
7858 /* For embedded applications, always put an object in read-only data
7859 if possible, in order to reduce RAM usage. */
7861 if (((TREE_CODE (decl
) == VAR_DECL
7862 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7863 && DECL_INITIAL (decl
)
7864 && (DECL_INITIAL (decl
) == error_mark_node
7865 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7866 /* Deal with calls from output_constant_def_contents. */
7867 || (TREE_CODE (decl
) != VAR_DECL
7868 && (TREE_CODE (decl
) != STRING_CST
7869 || !flag_writable_strings
)))
7870 && ! (flag_pic
&& reloc
))
7871 READONLY_DATA_SECTION ();
7872 else if (size
> 0 && size
<= mips_section_threshold
)
7873 SMALL_DATA_SECTION ();
7879 /* For hosted applications, always put an object in small data if
7880 possible, as this gives the best performance. */
7882 if (size
> 0 && size
<= mips_section_threshold
)
7883 SMALL_DATA_SECTION ();
7884 else if (((TREE_CODE (decl
) == VAR_DECL
7885 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7886 && DECL_INITIAL (decl
)
7887 && (DECL_INITIAL (decl
) == error_mark_node
7888 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7889 /* Deal with calls from output_constant_def_contents. */
7890 || (TREE_CODE (decl
) != VAR_DECL
7891 && (TREE_CODE (decl
) != STRING_CST
7892 || !flag_writable_strings
)))
7893 && ! (flag_pic
&& reloc
))
7894 READONLY_DATA_SECTION ();
7900 #ifdef MIPS_ABI_DEFAULT
7902 /* Support functions for the 64 bit ABI. */
7904 /* Return register to use for a function return value with VALTYPE for function
7908 mips_function_value (valtype
, func
)
7910 tree func ATTRIBUTE_UNUSED
;
7912 int reg
= GP_RETURN
;
7913 enum machine_mode mode
= TYPE_MODE (valtype
);
7914 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7915 int unsignedp
= TREE_UNSIGNED (valtype
);
7917 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7918 just as PROMOTE_MODE does. */
7919 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
7921 if (mclass
== MODE_FLOAT
)
7923 if (TARGET_SINGLE_FLOAT
7924 && (mclass
== MODE_FLOAT
7925 ? GET_MODE_SIZE (mode
) > 4 : GET_MODE_SIZE (mode
) / 2 > 4))
7931 else if (mclass
== MODE_COMPLEX_FLOAT
)
7935 else if (mode
== SCmode
)
7937 /* When FP registers are 32 bits, we can't directly reference
7938 the odd numbered ones, so let's make a pair of evens. */
7940 enum machine_mode cmode
= TYPE_MODE (TREE_TYPE (valtype
));
7942 return gen_rtx_PARALLEL
7945 gen_rtx_EXPR_LIST (VOIDmode
,
7949 gen_rtx_EXPR_LIST (VOIDmode
,
7958 else if (TREE_CODE (valtype
) == RECORD_TYPE
7959 && mips_abi
!= ABI_32
7960 && mips_abi
!= ABI_O64
7961 && mips_abi
!= ABI_EABI
)
7963 /* A struct with only one or two floating point fields is returned in
7964 the floating point registers. */
7965 tree field
, fields
[2];
7968 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
7969 field
= TREE_CHAIN (field
))
7971 if (TREE_CODE (field
) != FIELD_DECL
)
7974 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
7977 fields
[i
++] = field
;
7980 /* Must check i, so that we reject structures with no elements. */
7985 /* The structure has DImode, but we don't allow DImode values
7986 in FP registers, so we use a PARALLEL even though it isn't
7987 strictly necessary. */
7988 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
7990 return gen_rtx_PARALLEL
7993 gen_rtx_EXPR_LIST (VOIDmode
,
7994 gen_rtx_REG (field_mode
,
8001 enum machine_mode first_mode
8002 = TYPE_MODE (TREE_TYPE (fields
[0]));
8003 enum machine_mode second_mode
8004 = TYPE_MODE (TREE_TYPE (fields
[1]));
8005 HOST_WIDE_INT first_offset
= int_byte_position (fields
[0]);
8006 HOST_WIDE_INT second_offset
= int_byte_position (fields
[1]);
8008 return gen_rtx_PARALLEL
8011 gen_rtx_EXPR_LIST (VOIDmode
,
8012 gen_rtx_REG (first_mode
,
8014 GEN_INT (first_offset
)),
8015 gen_rtx_EXPR_LIST (VOIDmode
,
8016 gen_rtx_REG (second_mode
,
8018 GEN_INT (second_offset
))));
8023 return gen_rtx_REG (mode
, reg
);
8027 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8028 nonzero when an argument must be passed by reference. */
8031 function_arg_pass_by_reference (cum
, mode
, type
, named
)
8032 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
8033 enum machine_mode mode
;
8035 int named ATTRIBUTE_UNUSED
;
8039 /* We must pass by reference if we would be both passing in registers
8040 and the stack. This is because any subsequent partial arg would be
8041 handled incorrectly in this case.
8043 ??? This is really a kludge. We should either fix GCC so that such
8044 a situation causes an abort and then do something in the MIPS port
8045 to prevent it, or add code to function.c to properly handle the case. */
8046 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8047 here hopefully is not relevant to mips_va_arg. */
8048 if (cum
&& MUST_PASS_IN_STACK (mode
, type
)
8049 && mips_abi
!= ABI_MEABI
)
8051 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
8052 get double copies of any offsets generated for small structs
8053 passed in registers. */
8054 CUMULATIVE_ARGS temp
;
8056 if (FUNCTION_ARG (temp
, mode
, type
, named
) != 0)
8060 /* Otherwise, we only do this if EABI is selected. */
8061 if (mips_abi
!= ABI_EABI
)
8064 /* ??? How should SCmode be handled? */
8065 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
8068 size
= int_size_in_bytes (type
);
8069 return size
== -1 || size
> UNITS_PER_WORD
;
8072 /* This function returns the register class required for a secondary
8073 register when copying between one of the registers in CLASS, and X,
8074 using MODE. If IN_P is nonzero, the copy is going from X to the
8075 register, otherwise the register is the source. A return value of
8076 NO_REGS means that no secondary register is required. */
8079 mips_secondary_reload_class (class, mode
, x
, in_p
)
8080 enum reg_class
class;
8081 enum machine_mode mode
;
8085 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
8089 if (GET_CODE (x
) == SIGN_EXTEND
)
8095 /* We may be called with reg_renumber NULL from regclass.
8096 ??? This is probably a bug. */
8098 regno
= true_regnum (x
);
8101 while (GET_CODE (x
) == SUBREG
)
8103 off
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
8104 GET_MODE (SUBREG_REG (x
)),
8110 if (GET_CODE (x
) == REG
)
8111 regno
= REGNO (x
) + off
;
8115 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
8116 regno
= true_regnum (x
);
8118 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
8120 /* We always require a general register when copying anything to
8121 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8122 to a general register, or when copying from register 0. */
8123 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
8126 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8127 ? NO_REGS
: gr_regs
);
8128 else if (regno
== HILO_REGNUM
)
8131 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8132 ? NO_REGS
: gr_regs
);
8134 /* Copying from HI or LO to anywhere other than a general register
8135 requires a general register. */
8136 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
8138 if (TARGET_MIPS16
&& in_p
)
8140 /* We can't really copy to HI or LO at all in mips16 mode. */
8143 return gp_reg_p
? NO_REGS
: gr_regs
;
8145 if (MD_REG_P (regno
))
8147 if (TARGET_MIPS16
&& ! in_p
)
8149 /* We can't really copy to HI or LO at all in mips16 mode. */
8152 return class == gr_regs
? NO_REGS
: gr_regs
;
8155 /* We can only copy a value to a condition code register from a
8156 floating point register, and even then we require a scratch
8157 floating point register. We can only copy a value out of a
8158 condition code register into a general register. */
8159 if (class == ST_REGS
)
8163 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8165 if (ST_REG_P (regno
))
8169 return class == GR_REGS
? NO_REGS
: GR_REGS
;
8172 /* In mips16 mode, going between memory and anything but M16_REGS
8173 requires an M16_REG. */
8176 if (class != M16_REGS
&& class != M16_NA_REGS
)
8184 /* The stack pointer isn't a valid operand to an add instruction,
8185 so we need to load it into M16_REGS first. This can happen as
8186 a result of register elimination and form_sum converting
8187 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8188 need an extra register if the dest is the same as the other
8189 register. In that case, we can't fix the problem by loading SP
8190 into the dest first. */
8191 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
8192 && GET_CODE (XEXP (x
, 1)) == REG
8193 && (XEXP (x
, 0) == stack_pointer_rtx
8194 || XEXP (x
, 1) == stack_pointer_rtx
))
8195 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
8197 if (class == M16_REGS
|| class == M16_NA_REGS
)
8206 /* For each mips16 function which refers to GP relative symbols, we
8207 use a pseudo register, initialized at the start of the function, to
8208 hold the $gp value. */
8211 mips16_gp_pseudo_reg ()
8213 if (mips16_gp_pseudo_rtx
== NULL_RTX
)
8218 mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
8219 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx
) = 1;
8221 /* We want to initialize this to a value which gcc will believe
8223 const_gp
= gen_rtx (CONST
, Pmode
,
8224 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
8227 emit_move_insn (mips16_gp_pseudo_rtx
, const_gp
);
8228 insn
= gen_sequence ();
8231 push_topmost_sequence ();
8232 /* We need to emit the initialization after the FUNCTION_BEG
8233 note, so that it will be integrated. */
8234 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
8235 if (GET_CODE (scan
) == NOTE
8236 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
8238 if (scan
== NULL_RTX
)
8239 scan
= get_insns ();
8240 insn
= emit_insn_after (insn
, scan
);
8241 pop_topmost_sequence ();
8244 return mips16_gp_pseudo_rtx
;
8247 /* Return an RTX which represents the signed 16 bit offset from the
8248 $gp register for the given symbol. This is only used on the
8252 mips16_gp_offset (sym
)
8257 if (GET_CODE (sym
) != SYMBOL_REF
8258 || ! SYMBOL_REF_FLAG (sym
))
8261 /* We use a special identifier to represent the value of the gp
8263 gp
= get_identifier ("__mips16_gp_value");
8265 return gen_rtx (CONST
, Pmode
,
8266 gen_rtx (MINUS
, Pmode
, sym
,
8267 gen_rtx (SYMBOL_REF
, Pmode
,
8268 IDENTIFIER_POINTER (gp
))));
8271 /* Return nonzero if the given RTX represents a signed 16 bit offset
8272 from the $gp register. */
8275 mips16_gp_offset_p (x
)
8278 if (GET_CODE (x
) == CONST
)
8281 /* It's OK to add a small integer value to a gp offset. */
8282 if (GET_CODE (x
) == PLUS
)
8284 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8285 && SMALL_INT (XEXP (x
, 1)))
8286 return mips16_gp_offset_p (XEXP (x
, 0));
8287 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
8288 && SMALL_INT (XEXP (x
, 0)))
8289 return mips16_gp_offset_p (XEXP (x
, 1));
8293 /* Make sure it is in the form SYM - __mips16_gp_value. */
8294 return (GET_CODE (x
) == MINUS
8295 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
8296 && SYMBOL_REF_FLAG (XEXP (x
, 0))
8297 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8298 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
8301 /* Output a GP offset. We don't want to print the subtraction of
8302 __mips16_gp_value; it is implicitly represented by the %gprel which
8303 should have been printed by the caller. */
8306 mips16_output_gp_offset (file
, x
)
8310 if (GET_CODE (x
) == CONST
)
8313 if (GET_CODE (x
) == PLUS
)
8315 mips16_output_gp_offset (file
, XEXP (x
, 0));
8317 mips16_output_gp_offset (file
, XEXP (x
, 1));
8321 if (GET_CODE (x
) == MINUS
8322 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8323 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
8325 mips16_output_gp_offset (file
, XEXP (x
, 0));
8329 output_addr_const (file
, x
);
8332 /* Return nonzero if a constant should not be output until after the
8333 function. This is true of most string constants, so that we can
8334 use a more efficient PC relative reference. However, a static
8335 inline function may never call assemble_function_end to write out
8336 the constant pool, so don't try to postpone the constant in that
8339 ??? It's really a bug that a static inline function can put stuff
8340 in the constant pool even if the function itself is not output.
8342 We record which string constants we've seen, so that we know which
8343 ones might use the more efficient reference. */
8346 mips16_constant_after_function_p (x
)
8349 if (TREE_CODE (x
) == STRING_CST
8350 && ! flag_writable_strings
8351 && current_function_decl
!= 0
8352 && ! DECL_DEFER_OUTPUT (current_function_decl
)
8353 && ! (DECL_INLINE (current_function_decl
)
8354 && ((! TREE_PUBLIC (current_function_decl
)
8355 && ! TREE_ADDRESSABLE (current_function_decl
)
8356 && ! flag_keep_inline_functions
)
8357 || DECL_EXTERNAL (current_function_decl
))))
8359 struct string_constant
*n
;
8361 n
= (struct string_constant
*) xmalloc (sizeof *n
);
8362 n
->label
= XSTR (XEXP (TREE_CST_RTL (x
), 0), 0);
8363 n
->next
= string_constants
;
8364 string_constants
= n
;
8372 /* Validate a constant for the mips16. This rejects general symbolic
8373 addresses, which must be loaded from memory. If ADDR is nonzero,
8374 this should reject anything which is not a legal address. If
8375 ADDEND is nonzero, this is being added to something else. */
8378 mips16_constant (x
, mode
, addr
, addend
)
8380 enum machine_mode mode
;
8384 while (GET_CODE (x
) == CONST
)
8387 switch (GET_CODE (x
))
8393 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
8394 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
8397 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8399 if (CONSTANT_POOL_ADDRESS_P (x
))
8402 /* If we aren't looking for a memory address, we can accept a GP
8403 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8404 knows how to handle this. We can always accept a string
8405 constant, which is the other case in which SYMBOL_REF_FLAG
8409 && SYMBOL_REF_FLAG (x
)
8410 && mode
== (enum machine_mode
) Pmode
)
8413 /* We can accept a string constant, which will have
8414 SYMBOL_REF_FLAG set but must be recognized by name to
8415 distinguish from a GP accessible symbol. The name of a
8416 string constant will have been generated by
8417 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8418 if (SYMBOL_REF_FLAG (x
))
8420 const char *name
= XSTR (x
, 0);
8422 return (name
[0] == '*'
8423 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
8424 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
8430 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8435 if (addr
&& ! addend
)
8437 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
8440 /* We need to treat $gp as a legitimate constant, because
8441 mips16_gp_pseudo_reg assumes that. */
8442 return REGNO (x
) == GP_REG_FIRST
+ 28;
8446 /* Write out code to move floating point arguments in or out of
8447 general registers. Output the instructions to FILE. FP_CODE is
8448 the code describing which arguments are present (see the comment at
8449 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8450 we are copying from the floating point registers. */
8453 mips16_fp_args (file
, fp_code
, from_fp_p
)
8462 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8463 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8470 gparg
= GP_ARG_FIRST
;
8471 fparg
= FP_ARG_FIRST
;
8472 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8476 if ((fparg
& 1) != 0)
8478 fprintf (file
, "\t%s\t%s,%s\n", s
,
8479 reg_names
[gparg
], reg_names
[fparg
]);
8481 else if ((f
& 3) == 2)
8484 fprintf (file
, "\td%s\t%s,%s\n", s
,
8485 reg_names
[gparg
], reg_names
[fparg
]);
8488 if ((fparg
& 1) != 0)
8490 if (TARGET_BIG_ENDIAN
)
8491 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8492 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
8493 reg_names
[gparg
+ 1], reg_names
[fparg
]);
8495 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8496 reg_names
[gparg
], reg_names
[fparg
], s
,
8497 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
8510 /* Build a mips16 function stub. This is used for functions which
8511 take aruments in the floating point registers. It is 32 bit code
8512 that moves the floating point args into the general registers, and
8513 then jumps to the 16 bit code. */
8516 build_mips16_function_stub (file
)
8520 char *secname
, *stubname
;
8521 tree stubid
, stubdecl
;
8525 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8526 secname
= (char *) alloca (strlen (fnname
) + 20);
8527 sprintf (secname
, ".mips16.fn.%s", fnname
);
8528 stubname
= (char *) alloca (strlen (fnname
) + 20);
8529 sprintf (stubname
, "__fn_stub_%s", fnname
);
8530 stubid
= get_identifier (stubname
);
8531 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8532 build_function_type (void_type_node
, NULL_TREE
));
8533 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8535 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
8537 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
8539 fprintf (file
, "%s%s",
8540 need_comma
? ", " : "",
8541 (f
& 3) == 1 ? "float" : "double");
8544 fprintf (file
, ")\n");
8546 fprintf (file
, "\t.set\tnomips16\n");
8547 function_section (stubdecl
);
8548 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
8550 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8551 within a .ent, and we can not emit another .ent. */
8552 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8553 fputs ("\t.ent\t", file
);
8554 assemble_name (file
, stubname
);
8558 assemble_name (file
, stubname
);
8559 fputs (":\n", file
);
8561 /* We don't want the assembler to insert any nops here. */
8562 fprintf (file
, "\t.set\tnoreorder\n");
8564 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
8566 fprintf (asm_out_file
, "\t.set\tnoat\n");
8567 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
8568 assemble_name (file
, fnname
);
8569 fprintf (file
, "\n");
8570 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8571 fprintf (asm_out_file
, "\t.set\tat\n");
8573 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8574 with one of the mfc1 instructions, because the result is not
8575 available for one instruction, so if the very first instruction
8576 in the function refers to the register, it will see the wrong
8578 fprintf (file
, "\tnop\n");
8580 fprintf (file
, "\t.set\treorder\n");
8582 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8583 fputs ("\t.end\t", file
);
8584 assemble_name (file
, stubname
);
8588 fprintf (file
, "\t.set\tmips16\n");
8590 function_section (current_function_decl
);
8593 /* We keep a list of functions for which we have already built stubs
8594 in build_mips16_call_stub. */
8598 struct mips16_stub
*next
;
8603 static struct mips16_stub
*mips16_stubs
;
8605 /* Build a call stub for a mips16 call. A stub is needed if we are
8606 passing any floating point values which should go into the floating
8607 point registers. If we are, and the call turns out to be to a 32
8608 bit function, the stub will be used to move the values into the
8609 floating point registers before calling the 32 bit function. The
8610 linker will magically adjust the function call to either the 16 bit
8611 function or the 32 bit stub, depending upon where the function call
8612 is actually defined.
8614 Similarly, we need a stub if the return value might come back in a
8615 floating point register.
8617 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8618 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8619 is the code built by function_arg. This function returns a nonzero
8620 value if it builds the call instruction itself. */
8623 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
8632 char *secname
, *stubname
;
8633 struct mips16_stub
*l
;
8634 tree stubid
, stubdecl
;
8638 /* We don't need to do anything if we aren't in mips16 mode, or if
8639 we were invoked with the -msoft-float option. */
8640 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8643 /* Figure out whether the value might come back in a floating point
8645 fpret
= (retval
!= 0
8646 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8647 && (! TARGET_SINGLE_FLOAT
8648 || GET_MODE_SIZE (GET_MODE (retval
)) <= 4));
8650 /* We don't need to do anything if there were no floating point
8651 arguments and the value will not be returned in a floating point
8653 if (fp_code
== 0 && ! fpret
)
8656 if (GET_CODE (fnmem
) != MEM
)
8658 fn
= XEXP (fnmem
, 0);
8660 /* We don't need to do anything if this is a call to a special
8661 mips16 support function. */
8662 if (GET_CODE (fn
) == SYMBOL_REF
8663 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8666 /* This code will only work for o32 and o64 abis. The other ABI's
8667 require more sophisticated support. */
8668 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8671 /* We can only handle SFmode and DFmode floating point return
8673 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
8676 /* If we're calling via a function pointer, then we must always call
8677 via a stub. There are magic stubs provided in libgcc.a for each
8678 of the required cases. Each of them expects the function address
8679 to arrive in register $2. */
8681 if (GET_CODE (fn
) != SYMBOL_REF
)
8685 rtx stub_fn
, stub_mem
, insn
;
8687 /* ??? If this code is modified to support other ABI's, we need
8688 to handle PARALLEL return values here. */
8690 sprintf (buf
, "__mips16_call_stub_%s%d",
8692 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
8695 id
= get_identifier (buf
);
8696 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
8697 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
8699 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
8701 if (retval
== NULL_RTX
)
8702 insn
= gen_call_internal0 (stub_mem
, arg_size
,
8703 gen_rtx (REG
, SImode
,
8704 GP_REG_FIRST
+ 31));
8706 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
8707 gen_rtx (REG
, SImode
,
8708 GP_REG_FIRST
+ 31));
8709 insn
= emit_call_insn (insn
);
8711 /* Put the register usage information on the CALL. */
8712 if (GET_CODE (insn
) != CALL_INSN
)
8714 CALL_INSN_FUNCTION_USAGE (insn
) =
8715 gen_rtx (EXPR_LIST
, VOIDmode
,
8716 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
8717 CALL_INSN_FUNCTION_USAGE (insn
));
8719 /* If we are handling a floating point return value, we need to
8720 save $18 in the function prologue. Putting a note on the
8721 call will mean that regs_ever_live[$18] will be true if the
8722 call is not eliminated, and we can check that in the prologue
8725 CALL_INSN_FUNCTION_USAGE (insn
) =
8726 gen_rtx (EXPR_LIST
, VOIDmode
,
8727 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8728 CALL_INSN_FUNCTION_USAGE (insn
));
8730 /* Return 1 to tell the caller that we've generated the call
8735 /* We know the function we are going to call. If we have already
8736 built a stub, we don't need to do anything further. */
8738 fnname
= XSTR (fn
, 0);
8739 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8740 if (strcmp (l
->name
, fnname
) == 0)
8745 /* Build a special purpose stub. When the linker sees a
8746 function call in mips16 code, it will check where the target
8747 is defined. If the target is a 32 bit call, the linker will
8748 search for the section defined here. It can tell which
8749 symbol this section is associated with by looking at the
8750 relocation information (the name is unreliable, since this
8751 might be a static function). If such a section is found, the
8752 linker will redirect the call to the start of the magic
8755 If the function does not return a floating point value, the
8756 special stub section is named
8759 If the function does return a floating point value, the stub
8761 .mips16.call.fp.FNNAME
8764 secname
= (char *) alloca (strlen (fnname
) + 40);
8765 sprintf (secname
, ".mips16.call.%s%s",
8768 stubname
= (char *) alloca (strlen (fnname
) + 20);
8769 sprintf (stubname
, "__call_stub_%s%s",
8772 stubid
= get_identifier (stubname
);
8773 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8774 build_function_type (void_type_node
, NULL_TREE
));
8775 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8777 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8779 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8783 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8785 fprintf (asm_out_file
, "%s%s",
8786 need_comma
? ", " : "",
8787 (f
& 3) == 1 ? "float" : "double");
8790 fprintf (asm_out_file
, ")\n");
8792 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8793 assemble_start_function (stubdecl
, stubname
);
8795 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8796 fputs ("\t.ent\t", asm_out_file
);
8797 assemble_name (asm_out_file
, stubname
);
8798 fputs ("\n", asm_out_file
);
8800 assemble_name (asm_out_file
, stubname
);
8801 fputs (":\n", asm_out_file
);
8804 /* We build the stub code by hand. That's the only way we can
8805 do it, since we can't generate 32 bit code during a 16 bit
8808 /* We don't want the assembler to insert any nops here. */
8809 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
8811 mips16_fp_args (asm_out_file
, fp_code
, 0);
8815 fprintf (asm_out_file
, "\t.set\tnoat\n");
8816 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
8818 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8819 fprintf (asm_out_file
, "\t.set\tat\n");
8820 /* Unfortunately, we can't fill the jump delay slot. We
8821 can't fill with one of the mtc1 instructions, because the
8822 result is not available for one instruction, so if the
8823 very first instruction in the function refers to the
8824 register, it will see the wrong value. */
8825 fprintf (asm_out_file
, "\tnop\n");
8829 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
8830 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
8831 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
8832 /* As above, we can't fill the delay slot. */
8833 fprintf (asm_out_file
, "\tnop\n");
8834 if (GET_MODE (retval
) == SFmode
)
8835 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8836 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
8839 if (TARGET_BIG_ENDIAN
)
8841 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8842 reg_names
[GP_REG_FIRST
+ 2],
8843 reg_names
[FP_REG_FIRST
+ 1]);
8844 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8845 reg_names
[GP_REG_FIRST
+ 3],
8846 reg_names
[FP_REG_FIRST
+ 0]);
8850 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8851 reg_names
[GP_REG_FIRST
+ 2],
8852 reg_names
[FP_REG_FIRST
+ 0]);
8853 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8854 reg_names
[GP_REG_FIRST
+ 3],
8855 reg_names
[FP_REG_FIRST
+ 1]);
8858 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
8859 /* As above, we can't fill the delay slot. */
8860 fprintf (asm_out_file
, "\tnop\n");
8863 fprintf (asm_out_file
, "\t.set\treorder\n");
8865 #ifdef ASM_DECLARE_FUNCTION_SIZE
8866 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
8869 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8870 fputs ("\t.end\t", asm_out_file
);
8871 assemble_name (asm_out_file
, stubname
);
8872 fputs ("\n", asm_out_file
);
8875 fprintf (asm_out_file
, "\t.set\tmips16\n");
8877 /* Record this stub. */
8878 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
8879 l
->name
= xstrdup (fnname
);
8881 l
->next
= mips16_stubs
;
8885 /* If we expect a floating point return value, but we've built a
8886 stub which does not expect one, then we're in trouble. We can't
8887 use the existing stub, because it won't handle the floating point
8888 value. We can't build a new stub, because the linker won't know
8889 which stub to use for the various calls in this object file.
8890 Fortunately, this case is illegal, since it means that a function
8891 was declared in two different ways in a single compilation. */
8892 if (fpret
&& ! l
->fpret
)
8893 error ("can not handle inconsistent calls to `%s'", fnname
);
8895 /* If we are calling a stub which handles a floating point return
8896 value, we need to arrange to save $18 in the prologue. We do
8897 this by marking the function call as using the register. The
8898 prologue will later see that it is used, and emit code to save
8905 if (retval
== NULL_RTX
)
8906 insn
= gen_call_internal0 (fnmem
, arg_size
,
8907 gen_rtx (REG
, SImode
,
8908 GP_REG_FIRST
+ 31));
8910 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
8911 gen_rtx (REG
, SImode
,
8912 GP_REG_FIRST
+ 31));
8913 insn
= emit_call_insn (insn
);
8915 if (GET_CODE (insn
) != CALL_INSN
)
8918 CALL_INSN_FUNCTION_USAGE (insn
) =
8919 gen_rtx (EXPR_LIST
, VOIDmode
,
8920 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8921 CALL_INSN_FUNCTION_USAGE (insn
));
8923 /* Return 1 to tell the caller that we've generated the call
8928 /* Return 0 to let the caller generate the call insn. */
8932 /* This function looks through the code for a function, and tries to
8933 optimize the usage of the $gp register. We arrange to copy $gp
8934 into a pseudo-register, and then let gcc's normal reload handling
8935 deal with the pseudo-register. Unfortunately, if reload choose to
8936 put the pseudo-register into a call-clobbered register, it will
8937 emit saves and restores for that register around any function
8938 calls. We don't need the saves, and it's faster to copy $gp than
8939 to do an actual restore. ??? This still means that we waste a
8942 This is an optimization, and the code which gcc has actually
8943 generated is correct, so we do not need to catch all cases. */
8946 mips16_optimize_gp (first
)
8949 rtx gpcopy
, slot
, insn
;
8951 /* Look through the instructions. Set GPCOPY to the register which
8952 holds a copy of $gp. Set SLOT to the stack slot where it is
8953 saved. If we find an instruction which sets GPCOPY to anything
8954 other than $gp or SLOT, then we can't use it. If we find an
8955 instruction which sets SLOT to anything other than GPCOPY, we
8960 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
8964 if (! INSN_P (insn
))
8967 set
= PATTERN (insn
);
8969 /* We know that all references to memory will be inside a SET,
8970 because there is no other way to access memory on the mips16.
8971 We don't have to worry about a PARALLEL here, because the
8972 mips.md file will never generate them for memory references. */
8973 if (GET_CODE (set
) != SET
)
8976 if (gpcopy
== NULL_RTX
8977 && GET_CODE (SET_SRC (set
)) == CONST
8978 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
8979 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
8980 && GET_CODE (SET_DEST (set
)) == REG
8981 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
8982 gpcopy
= SET_DEST (set
);
8983 else if (slot
== NULL_RTX
8984 && gpcopy
!= NULL_RTX
8985 && GET_CODE (SET_DEST (set
)) == MEM
8986 && GET_CODE (SET_SRC (set
)) == REG
8987 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
8988 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
8992 offset
= const0_rtx
;
8993 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
8994 if (GET_CODE (base
) == REG
8995 && (REGNO (base
) == STACK_POINTER_REGNUM
8996 || REGNO (base
) == FRAME_POINTER_REGNUM
))
8997 slot
= SET_DEST (set
);
8999 else if (gpcopy
!= NULL_RTX
9000 && (GET_CODE (SET_DEST (set
)) == REG
9001 || GET_CODE (SET_DEST (set
)) == SUBREG
)
9002 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
9003 && (GET_CODE (SET_DEST (set
)) != REG
9004 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
9005 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
9006 || ((GET_CODE (SET_SRC (set
)) != CONST
9007 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
9008 || (REGNO (XEXP (SET_SRC (set
), 0))
9009 != GP_REG_FIRST
+ 28))
9010 && ! rtx_equal_p (SET_SRC (set
), slot
))))
9012 else if (slot
!= NULL_RTX
9013 && GET_CODE (SET_DEST (set
)) == MEM
9014 && rtx_equal_p (SET_DEST (set
), slot
)
9015 && (GET_CODE (SET_SRC (set
)) != REG
9016 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
9020 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9021 different optimization. Any time we find a copy of $28 into a
9022 register, followed by an add of a symbol_ref to that register, we
9023 convert it to load the value from the constant table instead.
9024 The copy and add will take six bytes, just as the load and
9025 constant table entry will take six bytes. However, it is
9026 possible that the constant table entry will be shared.
9028 This could be a peephole optimization, but I don't know if the
9029 peephole code can call force_const_mem.
9031 Using the same register for the copy of $28 and the add of the
9032 symbol_ref is actually pretty likely, since the add instruction
9033 requires the destination and the first addend to be the same
9036 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
9040 /* This optimization is only reasonable if the constant table
9041 entries are only 4 bytes. */
9042 if (Pmode
!= SImode
)
9045 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
9052 next
= NEXT_INSN (next
);
9054 while (next
!= NULL_RTX
9055 && (GET_CODE (next
) == NOTE
9056 || (GET_CODE (next
) == INSN
9057 && (GET_CODE (PATTERN (next
)) == USE
9058 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
9060 if (next
== NULL_RTX
)
9063 if (! INSN_P (insn
))
9066 if (! INSN_P (next
))
9069 set1
= PATTERN (insn
);
9070 if (GET_CODE (set1
) != SET
)
9072 set2
= PATTERN (next
);
9073 if (GET_CODE (set2
) != SET
)
9076 if (GET_CODE (SET_DEST (set1
)) == REG
9077 && GET_CODE (SET_SRC (set1
)) == CONST
9078 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
9079 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
9080 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
9081 && GET_CODE (SET_SRC (set2
)) == PLUS
9082 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
9083 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
9084 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
9088 /* We've found a case we can change to load from the
9091 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
9092 if (GET_CODE (sym
) != SYMBOL_REF
)
9094 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
9095 force_const_mem (Pmode
, sym
)),
9098 PUT_CODE (insn
, NOTE
);
9099 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9100 NOTE_SOURCE_FILE (insn
) = 0;
9102 PUT_CODE (next
, NOTE
);
9103 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
9104 NOTE_SOURCE_FILE (next
) = 0;
9111 /* We can safely remove all assignments to SLOT from GPCOPY, and
9112 replace all assignments from SLOT to GPCOPY with assignments from
9115 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9119 if (! INSN_P (insn
))
9122 set
= PATTERN (insn
);
9123 if (GET_CODE (set
) != SET
9124 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
)
9127 if (GET_CODE (SET_DEST (set
)) == MEM
9128 && rtx_equal_p (SET_DEST (set
), slot
)
9129 && GET_CODE (SET_SRC (set
)) == REG
9130 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
9132 PUT_CODE (insn
, NOTE
);
9133 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9134 NOTE_SOURCE_FILE (insn
) = 0;
9136 else if (GET_CODE (SET_DEST (set
)) == REG
9137 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
9138 && GET_CODE (SET_SRC (set
)) == MEM
9139 && rtx_equal_p (SET_SRC (set
), slot
))
9141 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
9142 gen_rtx (CONST
, Pmode
,
9143 gen_rtx (REG
, Pmode
,
9144 GP_REG_FIRST
+ 28))),
9146 PUT_CODE (insn
, NOTE
);
9147 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9148 NOTE_SOURCE_FILE (insn
) = 0;
9153 /* We keep a list of constants we which we have to add to internal
9154 constant tables in the middle of large functions. */
9158 struct constant
*next
;
9161 enum machine_mode mode
;
9164 /* Add a constant to the list in *PCONSTANTS. */
9167 add_constant (pconstants
, val
, mode
)
9168 struct constant
**pconstants
;
9170 enum machine_mode mode
;
9174 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
9175 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
9178 c
= (struct constant
*) xmalloc (sizeof *c
);
9181 c
->label
= gen_label_rtx ();
9182 c
->next
= *pconstants
;
9187 /* Dump out the constants in CONSTANTS after INSN. */
9190 dump_constants (constants
, insn
)
9191 struct constant
*constants
;
9202 struct constant
*next
;
9204 switch (GET_MODE_SIZE (c
->mode
))
9211 insn
= emit_insn_after (gen_align_2 (), insn
);
9216 insn
= emit_insn_after (gen_align_4 (), insn
);
9221 insn
= emit_insn_after (gen_align_8 (), insn
);
9226 insn
= emit_label_after (c
->label
, insn
);
9231 r
= gen_consttable_qi (c
->value
);
9234 r
= gen_consttable_hi (c
->value
);
9237 r
= gen_consttable_si (c
->value
);
9240 r
= gen_consttable_sf (c
->value
);
9243 r
= gen_consttable_di (c
->value
);
9246 r
= gen_consttable_df (c
->value
);
9252 insn
= emit_insn_after (r
, insn
);
9259 emit_barrier_after (insn
);
9262 /* Find the symbol in an address expression. */
9265 mips_find_symbol (addr
)
9268 if (GET_CODE (addr
) == MEM
)
9269 addr
= XEXP (addr
, 0);
9270 while (GET_CODE (addr
) == CONST
)
9271 addr
= XEXP (addr
, 0);
9272 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
9274 if (GET_CODE (addr
) == PLUS
)
9278 l1
= mips_find_symbol (XEXP (addr
, 0));
9279 l2
= mips_find_symbol (XEXP (addr
, 1));
9280 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
9282 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
9288 /* Exported to toplev.c.
9290 Do a final pass over the function, just before delayed branch
9294 machine_dependent_reorg (first
)
9297 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
9299 struct constant
*constants
;
9301 if (! TARGET_MIPS16
)
9304 /* If $gp is used, try to remove stores, and replace loads with
9307 mips16_optimize_gp (first
);
9309 /* Scan the function looking for PC relative loads which may be out
9310 of range. All such loads will either be from the constant table,
9311 or be getting the address of a constant string. If the size of
9312 the function plus the size of the constant table is less than
9313 0x8000, then all loads are in range. */
9316 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9318 insns_len
+= get_attr_length (insn
);
9320 /* ??? We put switch tables in .text, but we don't define
9321 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9322 compute their lengths correctly. */
9323 if (GET_CODE (insn
) == JUMP_INSN
)
9327 body
= PATTERN (insn
);
9328 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9329 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9330 * GET_MODE_SIZE (GET_MODE (body
)));
9331 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9335 /* Store the original value of insns_len in current_frame_info, so
9336 that simple_memory_operand can look at it. */
9337 current_frame_info
.insns_len
= insns_len
;
9339 pool_size
= get_pool_size ();
9340 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
9343 /* Loop over the insns and figure out what the maximum internal pool
9345 max_internal_pool_size
= 0;
9346 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9348 if (GET_CODE (insn
) == INSN
9349 && GET_CODE (PATTERN (insn
)) == SET
)
9353 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9354 if (src
== NULL_RTX
)
9356 if (CONSTANT_POOL_ADDRESS_P (src
))
9357 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
9358 else if (SYMBOL_REF_FLAG (src
))
9359 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
9365 first_constant_ref
= -1;
9367 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9369 if (GET_CODE (insn
) == INSN
9370 && GET_CODE (PATTERN (insn
)) == SET
)
9373 enum machine_mode mode
= VOIDmode
;
9376 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9377 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
9379 /* ??? This is very conservative, which means that we
9380 will generate too many copies of the constant table.
9381 The only solution would seem to be some form of
9383 if (((insns_len
- addr
)
9384 + max_internal_pool_size
9385 + get_pool_offset (src
))
9388 val
= get_pool_constant (src
);
9389 mode
= get_pool_mode (src
);
9391 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
9393 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
9395 /* Including all of mips_string_length is conservative,
9396 and so is including all of max_internal_pool_size. */
9397 if (((insns_len
- addr
)
9398 + max_internal_pool_size
9400 + mips_string_length
)
9406 max_internal_pool_size
-= Pmode
;
9409 if (val
!= NULL_RTX
)
9413 /* This PC relative load is out of range. ??? In the
9414 case of a string constant, we are only guessing that
9415 it is range, since we don't know the offset of a
9416 particular string constant. */
9418 lab
= add_constant (&constants
, val
, mode
);
9419 newsrc
= gen_rtx (MEM
, mode
,
9420 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
9421 RTX_UNCHANGING_P (newsrc
) = 1;
9422 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
9423 SET_DEST (PATTERN (insn
)),
9425 INSN_CODE (insn
) = -1;
9427 if (first_constant_ref
< 0)
9428 first_constant_ref
= addr
;
9432 addr
+= get_attr_length (insn
);
9434 /* ??? We put switch tables in .text, but we don't define
9435 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9436 compute their lengths correctly. */
9437 if (GET_CODE (insn
) == JUMP_INSN
)
9441 body
= PATTERN (insn
);
9442 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9443 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9444 * GET_MODE_SIZE (GET_MODE (body
)));
9445 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9448 if (GET_CODE (insn
) == BARRIER
)
9450 /* Output any constants we have accumulated. Note that we
9451 don't need to change ADDR, since its only use is
9452 subtraction from INSNS_LEN, and both would be changed by
9454 ??? If the instructions up to the next barrier reuse a
9455 constant, it would often be better to continue
9457 if (constants
!= NULL
)
9458 dump_constants (constants
, insn
);
9460 first_constant_ref
= -1;
9463 if (constants
!= NULL
9464 && (NEXT_INSN (insn
) == NULL
9465 || (first_constant_ref
>= 0
9466 && (((addr
- first_constant_ref
)
9467 + 2 /* for alignment */
9468 + 2 /* for a short jump insn */
9472 /* If we haven't had a barrier within 0x8000 bytes of a
9473 constant reference or we are at the end of the function,
9474 emit a barrier now. */
9476 rtx label
, jump
, barrier
;
9478 label
= gen_label_rtx ();
9479 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
9480 JUMP_LABEL (jump
) = label
;
9481 LABEL_NUSES (label
) = 1;
9482 barrier
= emit_barrier_after (jump
);
9483 emit_label_after (label
, barrier
);
9484 first_constant_ref
= -1;
9488 /* ??? If we output all references to a constant in internal
9489 constants table, we don't need to output the constant in the real
9490 constant table, but we have no way to prevent that. */
9493 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9495 extend_operator (x
, mode
)
9497 enum machine_mode mode ATTRIBUTE_UNUSED
;
9499 enum rtx_code code
= GET_CODE (x
);
9500 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
9503 /* Accept any operator that can be used to shift the high half of the
9504 input value to the lower half, suitable for truncation. The
9505 remainder (the lower half of the input, and the upper half of the
9506 output) will be discarded. */
9508 highpart_shift_operator (x
, mode
)
9510 enum machine_mode mode ATTRIBUTE_UNUSED
;
9512 enum rtx_code code
= GET_CODE (x
);
9513 return (code
== LSHIFTRT
9519 /* Return the length of INSN. LENGTH is the initial length computed by
9520 attributes in the machine-description file. */
9523 mips_adjust_insn_length (insn
, length
)
9527 /* A unconditional jump has an unfilled delay slot if it is not part
9528 of a sequence. A conditional jump normally has a delay slot, but
9529 does not on MIPS16. */
9530 if (simplejump_p (insn
)
9531 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
9532 || GET_CODE (insn
) == CALL_INSN
)))
9535 /* All MIPS16 instructions are a measly two bytes. */
9542 /* Output assembly instructions to peform a conditional branch.
9544 INSN is the branch instruction. OPERANDS[0] is the condition.
9545 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9546 of the first operand to the condition. If TWO_OPERANDS_P is
9547 non-zero the comparison takes two operands; OPERANDS[3] will be the
9550 If INVERTED_P is non-zero we are to branch if the condition does
9551 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9553 LENGTH is the length (in bytes) of the sequence we are to generate.
9554 That tells us whether to generate a simple conditional branch, or a
9555 reversed conditional branch around a `jr' instruction. */
9557 mips_output_conditional_branch (insn
,
9570 static char buffer
[200];
9571 /* The kind of comparison we are doing. */
9572 enum rtx_code code
= GET_CODE (operands
[0]);
9573 /* Non-zero if the opcode for the comparison needs a `z' indicating
9574 that it is a comparision against zero. */
9576 /* A string to use in the assembly output to represent the first
9578 const char *op1
= "%z2";
9579 /* A string to use in the assembly output to represent the second
9580 operand. Use the hard-wired zero register if there's no second
9582 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
9583 /* The operand-printing string for the comparison. */
9584 const char *const comp
= (float_p
? "%F0" : "%C0");
9585 /* The operand-printing string for the inverted comparison. */
9586 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
9588 /* The MIPS processors (for levels of the ISA at least two), have
9589 "likely" variants of each branch instruction. These instructions
9590 annul the instruction in the delay slot if the branch is not
9592 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9594 if (!two_operands_p
)
9596 /* To compute whether than A > B, for example, we normally
9597 subtract B from A and then look at the sign bit. But, if we
9598 are doing an unsigned comparison, and B is zero, we don't
9599 have to do the subtraction. Instead, we can just check to
9600 see if A is non-zero. Thus, we change the CODE here to
9601 reflect the simpler comparison operation. */
9613 /* A condition which will always be true. */
9619 /* A condition which will always be false. */
9625 /* Not a special case. */
9630 /* Relative comparisons are always done against zero. But
9631 equality comparisons are done between two operands, and therefore
9632 do not require a `z' in the assembly language output. */
9633 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
9634 /* For comparisons against zero, the zero is not provided
9639 /* Begin by terminating the buffer. That way we can always use
9640 strcat to add to it. */
9647 /* Just a simple conditional branch. */
9649 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
9650 inverted_p
? inverted_comp
: comp
);
9652 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
9653 inverted_p
? inverted_comp
: comp
,
9654 need_z_p
? "z" : "",
9662 /* Generate a reversed conditional branch around ` j'
9677 rtx target
= gen_label_rtx ();
9679 output_asm_insn ("%(%<", 0);
9680 orig_target
= operands
[1];
9681 operands
[1] = target
;
9682 /* Generate the reversed comparison. This takes four
9685 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
9686 inverted_p
? comp
: inverted_comp
);
9688 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
9689 inverted_p
? comp
: inverted_comp
,
9690 need_z_p
? "z" : "",
9693 output_asm_insn (buffer
, operands
);
9694 operands
[1] = orig_target
;
9696 output_asm_insn ("nop\n\tj\t%1", operands
);
9699 output_asm_insn ("nop", 0);
9702 /* Output delay slot instruction. */
9703 rtx insn
= final_sequence
;
9704 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
9706 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
9708 output_asm_insn ("%>%)", 0);
9709 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
9710 CODE_LABEL_NUMBER (target
));
9714 /* We do not currently use this code. It handles jumps to
9715 arbitrary locations, using `jr', even across a 256MB boundary.
9716 We could add a -mhuge switch, and then use this code instead of
9717 the `j' alternative above when -mhuge was used. */
9722 /* Generate a reversed conditional branch around a `jr'
9736 Not pretty, but allows a conditional branch anywhere in the
9737 32-bit address space. If the original branch is annulled,
9738 then the instruction in the delay slot should be executed
9739 only if the branch is taken. The la instruction is really
9740 a macro which will usually take eight bytes, but sometimes
9741 takes only four, if the instruction to which we're jumping
9742 gets its own entry in the global pointer table, which will
9743 happen if its a case label. The assembler will then
9744 generate only a four-byte sequence, rather than eight, and
9745 there seems to be no way to tell it not to. Thus, we can't
9746 just use a `.+x' addressing form; we don't know what value
9749 So, we resort to using the explicit relocation syntax
9750 available in the assembler and do:
9752 lw $at,%got_page(target)($gp)
9753 daddiu $at,$at,%got_ofst(target)
9755 That way, this always takes up eight bytes, and we can use
9756 the `.+x' form. Of course, these explicit machinations
9757 with relocation will not work with old assemblers. Then
9758 again, neither do out-of-range branches, so we haven't lost
9761 /* The target of the reversed branch. */
9762 const char *const target
9763 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
9764 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
9765 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
9768 strcpy (buffer
, "%(%<%[");
9769 c
= strchr (buffer
, '\0');
9770 /* Generate the reversed comparision. This takes four
9773 sprintf (c
, "%%*b%s\t%%Z2%s",
9774 inverted_p
? comp
: inverted_comp
,
9777 sprintf (c
, "%%*b%s%s\t%s%s,%s",
9778 inverted_p
? comp
: inverted_comp
,
9779 need_z_p
? "z" : "",
9783 c
= strchr (buffer
, '\0');
9784 /* Generate the load-address, and jump. This takes twelve
9785 bytes, for a total of 16. */
9787 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9794 /* The delay slot was unfilled. Since we're inside
9795 .noreorder, the assembler will not fill in the NOP for
9796 us, so we must do it ourselves. */
9797 strcat (buffer
, "\n\tnop");
9798 strcat (buffer
, "%]%>%)");
9811 /* Called to register all of our global variables with the garbage
9815 mips_add_gc_roots ()
9817 ggc_add_rtx_root (&mips_load_reg
, 1);
9818 ggc_add_rtx_root (&mips_load_reg2
, 1);
9819 ggc_add_rtx_root (&mips_load_reg3
, 1);
9820 ggc_add_rtx_root (&mips_load_reg4
, 1);
9821 ggc_add_rtx_root (branch_cmp
, sizeof (branch_cmp
) / sizeof (rtx
));
9822 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx
, 1);
9823 ggc_add_rtx_root (&mips16_gp_pseudo_rtx
, 1);
9826 static enum processor_type
9827 mips_parse_cpu (cpu_string
)
9828 const char *cpu_string
;
9830 const char *p
= cpu_string
;
9832 enum processor_type cpu
;
9834 /* We need to cope with the various "vr" prefixes for the NEC 4300
9835 and 4100 processors. */
9836 if (*p
== 'v' || *p
== 'V')
9839 if (*p
== 'r' || *p
== 'R')
9842 /* Since there is no difference between a R2000 and R3000 in
9843 terms of the scheduler, we collapse them into just an R3000. */
9845 cpu
= PROCESSOR_DEFAULT
;
9849 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
9850 cpu
= PROCESSOR_R3000
;
9851 else if (!strcmp (p
, "20kc") || !strcmp (p
, "20Kc") )
9852 cpu
= PROCESSOR_R20KC
;
9856 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
9857 cpu
= PROCESSOR_R3000
;
9858 else if (!strcmp (p
, "3900"))
9859 cpu
= PROCESSOR_R3900
;
9863 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
9864 cpu
= PROCESSOR_R4000
;
9865 /* The vr4100 is a non-FP ISA III processor with some extra
9867 else if (!strcmp (p
, "4100"))
9868 cpu
= PROCESSOR_R4100
;
9869 /* The vr4300 is a standard ISA III processor, but with a different
9871 else if (!strcmp (p
, "4300"))
9872 cpu
= PROCESSOR_R4300
;
9873 /* The r4400 is exactly the same as the r4000 from the compiler's
9875 else if (!strcmp (p
, "4400"))
9876 cpu
= PROCESSOR_R4000
;
9877 else if (!strcmp (p
, "4600"))
9878 cpu
= PROCESSOR_R4600
;
9879 else if (!strcmp (p
, "4650"))
9880 cpu
= PROCESSOR_R4650
;
9881 /* The 4kc and 4kp processor cores are the same for
9882 scheduling purposes; they both implement the MIPS32
9883 ISA and only differ in their memory management
9885 else if (!strcmp (p
, "4kc") || !strcmp (p
, "4Kc")
9886 || !strcmp (p
, "4kp") || !strcmp (p
, "4Kp") )
9887 cpu
= PROCESSOR_R4KC
;
9891 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
9892 cpu
= PROCESSOR_R5000
;
9893 else if (!strcmp (p
, "5kc") || !strcmp (p
, "5Kc") )
9894 cpu
= PROCESSOR_R5KC
;
9898 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
9899 cpu
= PROCESSOR_R6000
;
9903 if (!strcmp (p
, "8000"))
9904 cpu
= PROCESSOR_R8000
;
9908 if (!strcmp (p
, "orion"))
9909 cpu
= PROCESSOR_R4600
;
9914 && cpu
!= PROCESSOR_R4300
9915 && cpu
!= PROCESSOR_R4100
9916 && cpu
!= PROCESSOR_R5000
)
9917 cpu
= PROCESSOR_DEFAULT
;
9922 /* Adjust the cost of INSN based on the relationship between INSN that
9923 is dependent on DEP_INSN through the dependence LINK. The default
9924 is to make no adjustment to COST.
9926 On the MIPS, ignore the cost of anti- and output-dependencies. */
9928 mips_adjust_cost (insn
, link
, dep
, cost
)
9929 rtx insn ATTRIBUTE_UNUSED
;
9931 rtx dep ATTRIBUTE_UNUSED
;
9934 if (REG_NOTE_KIND (link
) != 0)
9935 return 0; /* Anti or output dependence. */
9939 /* Cover function for UNIQUE_SECTION. */
9942 mips_unique_section (decl
, reloc
)
9947 const char *name
, *prefix
;
9949 static const char *const prefixes
[4][2] = {
9950 { ".text.", ".gnu.linkonce.t." },
9951 { ".rodata.", ".gnu.linkonce.r." },
9952 { ".data.", ".gnu.linkonce.d." },
9953 { ".sdata.", ".gnu.linkonce.s." }
9956 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9957 size
= int_size_in_bytes (TREE_TYPE (decl
));
9959 /* Determine the base section we are interested in:
9960 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
9961 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9963 else if (DECL_INITIAL (decl
) == 0
9964 || DECL_INITIAL (decl
) == error_mark_node
)
9966 else if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
9967 && TREE_CODE (decl
) == STRING_CST
9968 && !flag_writable_strings
)
9970 /* For embedded position independent code, put constant
9971 strings in the text section, because the data section
9972 is limited to 64K in size. For mips16 code, put
9973 strings in the text section so that a PC relative load
9974 instruction can be used to get their address. */
9977 else if (TARGET_EMBEDDED_DATA
)
9979 /* For embedded applications, always put an object in
9980 read-only data if possible, in order to reduce RAM
9983 if (DECL_READONLY_SECTION (decl
, reloc
))
9985 else if (size
> 0 && size
<= mips_section_threshold
)
9992 /* For hosted applications, always put an object in
9993 small data if possible, as this gives the best
9996 if (size
> 0 && size
<= mips_section_threshold
)
9998 else if (DECL_READONLY_SECTION (decl
, reloc
))
10004 prefix
= prefixes
[sec
][DECL_ONE_ONLY (decl
)];
10005 len
= strlen (name
) + strlen (prefix
);
10006 string
= alloca (len
+ 1);
10007 sprintf (string
, "%s%s", prefix
, name
);
10009 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
10013 mips_hard_regno_nregs (regno
, mode
)
10015 enum machine_mode mode
;
10017 if (! FP_REG_P (regno
))
10018 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
10020 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
10024 #ifdef TARGET_IRIX6
10025 /* Output assembly to switch to section NAME with attribute FLAGS. */
10028 iris6_asm_named_section_1 (name
, flags
, align
)
10030 unsigned int flags
;
10031 unsigned int align
;
10033 unsigned int sh_type
, sh_flags
, sh_entsize
;
10036 if (!(flags
& SECTION_DEBUG
))
10037 sh_flags
|= 2; /* SHF_ALLOC */
10038 if (flags
& SECTION_WRITE
)
10039 sh_flags
|= 1; /* SHF_WRITE */
10040 if (flags
& SECTION_CODE
)
10041 sh_flags
|= 4; /* SHF_EXECINSTR */
10042 if (flags
& SECTION_SMALL
)
10043 sh_flags
|= 0x10000000; /* SHF_MIPS_GPREL */
10044 if (strcmp (name
, ".debug_frame") == 0)
10045 sh_flags
|= 0x08000000; /* SHF_MIPS_NOSTRIP */
10046 if (flags
& SECTION_DEBUG
)
10047 sh_type
= 0x7000001e; /* SHT_MIPS_DWARF */
10048 else if (flags
& SECTION_BSS
)
10049 sh_type
= 8; /* SHT_NOBITS */
10051 sh_type
= 1; /* SHT_PROGBITS */
10053 if (flags
& SECTION_CODE
)
10058 fprintf (asm_out_file
, "\t.section %s,%#x,%#x,%u,%u\n",
10059 name
, sh_type
, sh_flags
, sh_entsize
, align
);
10063 iris6_asm_named_section (name
, flags
)
10065 unsigned int flags
;
10067 if (TARGET_FILE_SWITCHING
&& (flags
& SECTION_CODE
))
10068 asm_out_file
= asm_out_text_file
;
10069 iris6_asm_named_section_1 (name
, flags
, 0);
10072 /* In addition to emitting a .align directive, record the maximum
10073 alignment requested for the current section. */
10075 struct iris_section_align_entry
10079 unsigned int flags
;
10082 static htab_t iris_section_align_htab
;
10083 static FILE *iris_orig_asm_out_file
;
10086 iris_section_align_entry_eq (p1
, p2
)
10090 const struct iris_section_align_entry
*old
= p1
;
10091 const char *new = p2
;
10093 return strcmp (old
->name
, new) == 0;
10097 iris_section_align_entry_hash (p
)
10100 const struct iris_section_align_entry
*old
= p
;
10101 return htab_hash_string (old
->name
);
10105 iris6_asm_output_align (file
, log
)
10109 const char *section
= current_section_name ();
10110 struct iris_section_align_entry
**slot
, *entry
;
10115 slot
= (struct iris_section_align_entry
**)
10116 htab_find_slot_with_hash (iris_section_align_htab
, section
,
10117 htab_hash_string (section
), INSERT
);
10121 entry
= (struct iris_section_align_entry
*)
10122 xmalloc (sizeof (struct iris_section_align_entry
));
10124 entry
->name
= section
;
10126 entry
->flags
= current_section_flags ();
10128 else if (entry
->log
< log
)
10131 fprintf (file
, "\t.align\t%u\n", log
);
10134 /* The Iris assembler does not record alignment from .align directives,
10135 but takes it from the first .section directive seen. Play yet more
10136 file switching games so that we can emit a .section directive at the
10137 beginning of the file with the proper alignment attached. */
10140 iris6_asm_file_start (stream
)
10143 mips_asm_file_start (stream
);
10145 iris_orig_asm_out_file
= asm_out_file
;
10146 stream
= tmpfile ();
10147 asm_out_file
= stream
;
10148 asm_out_data_file
= stream
;
10149 if (! TARGET_FILE_SWITCHING
)
10150 asm_out_text_file
= stream
;
10152 iris_section_align_htab
= htab_create (31, iris_section_align_entry_hash
,
10153 iris_section_align_entry_eq
, NULL
);
10157 iris6_section_align_1 (slot
, data
)
10159 void *data ATTRIBUTE_UNUSED
;
10161 const struct iris_section_align_entry
*entry
10162 = *(const struct iris_section_align_entry
**) slot
;
10164 iris6_asm_named_section_1 (entry
->name
, entry
->flags
, 1 << entry
->log
);
10169 iris6_asm_file_end (stream
)
10172 /* Emit section directives with the proper alignment at the top of the
10173 real output file. */
10174 asm_out_file
= iris_orig_asm_out_file
;
10175 htab_traverse (iris_section_align_htab
, iris6_section_align_1
, NULL
);
10177 /* Copy the data emitted to the temp file to the real output file. */
10178 copy_file_data (asm_out_file
, stream
);
10180 mips_asm_file_end (stream
);
10182 #endif /* TARGET_IRIX6 */