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* varasm.c (assemble_real): Use REAL_VALUE_TO_x and assemble_integer
[official-gcc.git] / gcc / config / i386 / i386.h
blob7297f84d1d359c678d4367110dfb402e41731875
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern int x86_prefetch_sse;
226
227 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
228 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
229 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
230 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
231 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
232 /* For sane SSE instruction set generation we need fcomi instruction. It is
233 safe to enable all CMOVE instructions. */
234 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
235 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
236 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
237 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
238 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
239 #define TARGET_MOVX (x86_movx & CPUMASK)
240 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
241 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
242 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
243 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
244 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
245 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
246 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
247 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
248 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
249 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
250 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
251 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
252 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
253 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
254 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
255 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
256 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
257 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
258 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
259 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
260 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
261 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
262 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
263 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
264 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
265
266 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
267
268 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
269 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
270
271 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
272
273 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
274 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
275 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
276 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
277 && (ix86_fpmath & FPMATH_387))
278 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
279 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
280 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
281
282 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
283
284 #define TARGET_SWITCHES \
285 { { "80387", MASK_80387, N_("Use hardware fp") }, \
286 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
287 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
288 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
289 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
290 { "386", 0, N_("") /*Deprecated.*/}, \
291 { "486", 0, N_("") /*Deprecated.*/}, \
292 { "pentium", 0, N_("") /*Deprecated.*/}, \
293 { "pentiumpro", 0, N_("") /*Deprecated.*/}, \
294 { "intel-syntax", 0, N_("") /*Deprecated.*/}, \
295 { "no-intel-syntax", 0, N_("") /*Deprecated.*/}, \
296 { "rtd", MASK_RTD, \
297 N_("Alternate calling convention") }, \
298 { "no-rtd", -MASK_RTD, \
299 N_("Use normal calling convention") }, \
300 { "align-double", MASK_ALIGN_DOUBLE, \
301 N_("Align some doubles on dword boundary") }, \
302 { "no-align-double", -MASK_ALIGN_DOUBLE, \
303 N_("Align doubles on word boundary") }, \
304 { "svr3-shlib", MASK_SVR3_SHLIB, \
305 N_("Uninitialized locals in .bss") }, \
306 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
307 N_("Uninitialized locals in .data") }, \
308 { "ieee-fp", MASK_IEEE_FP, \
309 N_("Use IEEE math for fp comparisons") }, \
310 { "no-ieee-fp", -MASK_IEEE_FP, \
311 N_("Do not use IEEE math for fp comparisons") }, \
312 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
313 N_("Return values of functions in FPU registers") }, \
314 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
315 N_("Do not return values of functions in FPU registers")}, \
316 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
317 N_("Do not generate sin, cos, sqrt for FPU") }, \
318 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
319 N_("Generate sin, cos, sqrt for FPU")}, \
320 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
321 N_("Omit the frame pointer in leaf functions") }, \
322 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
323 { "stack-arg-probe", MASK_STACK_PROBE, \
324 N_("Enable stack probing") }, \
325 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
326 { "windows", 0, 0 /* undocumented */ }, \
327 { "dll", 0, 0 /* undocumented */ }, \
328 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
329 N_("Align destination of the string operations") }, \
330 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
331 N_("Do not align destination of the string operations") }, \
332 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
333 N_("Inline all known string operations") }, \
334 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
335 N_("Do not inline all known string operations") }, \
336 { "push-args", -MASK_NO_PUSH_ARGS, \
337 N_("Use push instructions to save outgoing arguments") }, \
338 { "no-push-args", MASK_NO_PUSH_ARGS, \
339 N_("Do not use push instructions to save outgoing arguments") }, \
340 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
341 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
342 N_("Use push instructions to save outgoing arguments") }, \
343 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
344 N_("Do not use push instructions to save outgoing arguments") }, \
345 { "mmx", MASK_MMX | MASK_MMX_SET, \
346 N_("Support MMX built-in functions") }, \
347 { "no-mmx", -MASK_MMX, \
348 N_("Do not support MMX built-in functions") }, \
349 { "no-mmx", MASK_MMX_SET, N_("") }, \
350 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
351 N_("Support 3DNow! built-in functions") }, \
352 { "no-3dnow", -MASK_3DNOW, N_("") }, \
353 { "no-3dnow", MASK_3DNOW_SET, \
354 N_("Do not support 3DNow! built-in functions") }, \
355 { "sse", MASK_SSE | MASK_SSE_SET, \
356 N_("Support MMX and SSE built-in functions and code generation") }, \
357 { "no-sse", -MASK_SSE, N_("") }, \
358 { "no-sse", MASK_SSE_SET, \
359 N_("Do not support MMX and SSE built-in functions and code generation") },\
360 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
361 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
362 { "no-sse2", -MASK_SSE2, N_("") }, \
363 { "no-sse2", MASK_SSE2_SET, \
364 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
365 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
366 N_("sizeof(long double) is 16") }, \
367 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
368 N_("sizeof(long double) is 12") }, \
369 { "64", MASK_64BIT, \
370 N_("Generate 64bit x86-64 code") }, \
371 { "32", -MASK_64BIT, \
372 N_("Generate 32bit i386 code") }, \
373 { "red-zone", -MASK_NO_RED_ZONE, \
374 N_("Use red-zone in the x86-64 code") }, \
375 { "no-red-zone", MASK_NO_RED_ZONE, \
376 N_("Do not use red-zone in the x86-64 code") }, \
377 SUBTARGET_SWITCHES \
378 { "", TARGET_DEFAULT, 0 }}
379
380 #ifdef TARGET_64BIT_DEFAULT
381 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
382 #else
383 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
384 #endif
385
386 /* Which processor to schedule for. The cpu attribute defines a list that
387 mirrors this list, so changes to i386.md must be made at the same time. */
388
389 enum processor_type
390 {
391 PROCESSOR_I386, /* 80386 */
392 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
393 PROCESSOR_PENTIUM,
394 PROCESSOR_PENTIUMPRO,
395 PROCESSOR_K6,
396 PROCESSOR_ATHLON,
397 PROCESSOR_PENTIUM4,
398 PROCESSOR_max
399 };
400 enum fpmath_unit
401 {
402 FPMATH_387 = 1,
403 FPMATH_SSE = 2
404 };
405
406 extern enum processor_type ix86_cpu;
407 extern enum fpmath_unit ix86_fpmath;
408
409 extern int ix86_arch;
410
411 /* This macro is similar to `TARGET_SWITCHES' but defines names of
412 command options that have values. Its definition is an
413 initializer with a subgrouping for each command option.
414
415 Each subgrouping contains a string constant, that defines the
416 fixed part of the option name, and the address of a variable. The
417 variable, type `char *', is set to the variable part of the given
418 option if the fixed part matches. The actual option name is made
419 by appending `-m' to the specified name. */
420 #define TARGET_OPTIONS \
421 { { "cpu=", &ix86_cpu_string, \
422 N_("Schedule code for given CPU")}, \
423 { "fpmath=", &ix86_fpmath_string, \
424 N_("Generate floating point mathematics using given instruction set")},\
425 { "arch=", &ix86_arch_string, \
426 N_("Generate code for given CPU")}, \
427 { "regparm=", &ix86_regparm_string, \
428 N_("Number of registers used to pass integer arguments") }, \
429 { "align-loops=", &ix86_align_loops_string, \
430 N_("Loop code aligned to this power of 2") }, \
431 { "align-jumps=", &ix86_align_jumps_string, \
432 N_("Jump targets are aligned to this power of 2") }, \
433 { "align-functions=", &ix86_align_funcs_string, \
434 N_("Function starts are aligned to this power of 2") }, \
435 { "preferred-stack-boundary=", \
436 &ix86_preferred_stack_boundary_string, \
437 N_("Attempt to keep stack aligned to this power of 2") }, \
438 { "branch-cost=", &ix86_branch_cost_string, \
439 N_("Branches are this expensive (1-5, arbitrary units)") }, \
440 { "cmodel=", &ix86_cmodel_string, \
441 N_("Use given x86-64 code model") }, \
442 { "debug-arg", &ix86_debug_arg_string, \
443 N_("" /* Undocumented. */) }, \
444 { "debug-addr", &ix86_debug_addr_string, \
445 N_("" /* Undocumented. */) }, \
446 { "asm=", &ix86_asm_string, \
447 N_("Use given assembler dialect") }, \
448 SUBTARGET_OPTIONS \
449 }
450
451 /* Sometimes certain combinations of command options do not make
452 sense on a particular target machine. You can define a macro
453 `OVERRIDE_OPTIONS' to take account of this. This macro, if
454 defined, is executed once just after all the command options have
455 been parsed.
456
457 Don't use this macro to turn on various extra optimizations for
458 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
459
460 #define OVERRIDE_OPTIONS override_options ()
461
462 /* These are meant to be redefined in the host dependent files */
463 #define SUBTARGET_SWITCHES
464 #define SUBTARGET_OPTIONS
465
466 /* Define this to change the optimizations performed by default. */
467 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
468
469 /* Specs for the compiler proper */
470
471 #ifndef CC1_CPU_SPEC
472 #define CC1_CPU_SPEC "\
473 %{!mcpu*: \
474 %{m386:-mcpu=i386 \
475 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
476 %{m486:-mcpu=i486 \
477 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
478 %{mpentium:-mcpu=pentium \
479 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
480 %{mpentiumpro:-mcpu=pentiumpro \
481 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
482 %{mintel-syntax:-masm=intel \
483 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
484 %{mno-intel-syntax:-masm=att \
485 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
486 #endif
487 \f
488 #define TARGET_CPU_DEFAULT_i386 0
489 #define TARGET_CPU_DEFAULT_i486 1
490 #define TARGET_CPU_DEFAULT_pentium 2
491 #define TARGET_CPU_DEFAULT_pentiumpro 3
492 #define TARGET_CPU_DEFAULT_pentium2 4
493 #define TARGET_CPU_DEFAULT_pentium3 5
494 #define TARGET_CPU_DEFAULT_pentium4 6
495 #define TARGET_CPU_DEFAULT_k6 7
496 #define TARGET_CPU_DEFAULT_k6_2 8
497 #define TARGET_CPU_DEFAULT_k6_3 9
498 #define TARGET_CPU_DEFAULT_athlon 10
499 #define TARGET_CPU_DEFAULT_athlon_sse 11
500
501 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
502 "pentiumpro", "pentium2", "pentium3", \
503 "pentium4", "k6", "k6-2", "k6-3",\
504 "athlon", "athlon-4"}
505 #ifndef CPP_CPU_DEFAULT_SPEC
506 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
507 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
508 #endif
509 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
510 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
511 #endif
512 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
513 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
514 #endif
515 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
516 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
517 #endif
518 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
519 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
520 -D__tune_pentium2__"
521 #endif
522 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
523 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
524 -D__tune_pentium2__ -D__tune_pentium3__"
525 #endif
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
528 #endif
529 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
530 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
531 #endif
532 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
533 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
534 #endif
535 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
536 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
537 #endif
538 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
539 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
540 #endif
541 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
542 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
543 #endif
544 #ifndef CPP_CPU_DEFAULT_SPEC
545 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
546 #endif
547 #endif /* CPP_CPU_DEFAULT_SPEC */
548
549 #ifdef TARGET_BI_ARCH
550 #define NO_BUILTIN_SIZE_TYPE
551 #define NO_BUILTIN_PTRDIFF_TYPE
552 #endif
553
554 #ifdef NO_BUILTIN_SIZE_TYPE
555 #define CPP_CPU32_SIZE_TYPE_SPEC \
556 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
557 #define CPP_CPU64_SIZE_TYPE_SPEC \
558 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
559 #else
560 #define CPP_CPU32_SIZE_TYPE_SPEC ""
561 #define CPP_CPU64_SIZE_TYPE_SPEC ""
562 #endif
563
564 #define CPP_CPU32_SPEC \
565 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
566 -D__i386__ %(cpp_cpu32sizet)"
567
568 #define CPP_CPU64_SPEC \
569 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
570
571 #define CPP_CPUCOMMON_SPEC "\
572 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
573 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
574 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
575 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
576 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
577 -D__pentium__mmx__ \
578 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
579 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
580 -D__pentiumpro -D__pentiumpro__ \
581 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
582 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
583 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
584 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
585 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
586 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
587 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
588 %{!mcpu*:-D__tune_athlon__ }}\
589 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
590 -D__athlon_sse__ \
591 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
592 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
593 %{m386|mcpu=i386:-D__tune_i386__ }\
594 %{m486|mcpu=i486:-D__tune_i486__ }\
595 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
596 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
597 -D__tune_pentiumpro__ }\
598 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
599 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
600 -D__tune_athlon__ }\
601 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
602 -D__tune_athlon_sse__ }\
603 %{mcpu=pentium4:-D__tune_pentium4__ }\
604 %{march=march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
605 -D__SSE__ }\
606 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
607 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
608 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
609 %{march=k6-2|march=k6-3\
610 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
611 |march=athlon-mp: -D__3dNOW__ }\
612 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
613 |march=athlon-mp: -D__3dNOW_A__ }\
614 %{march=mcpu=pentium4: -D__SSE2__ }\
615 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
616
617 #ifndef CPP_CPU_SPEC
618 #ifdef TARGET_BI_ARCH
619 #ifdef TARGET_64BIT_DEFAULT
620 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
621 #else
622 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
623 #endif
624 #else
625 #ifdef TARGET_64BIT_DEFAULT
626 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
627 #else
628 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
629 #endif
630 #endif
631 #endif
632
633 #ifndef CC1_SPEC
634 #define CC1_SPEC "%(cc1_cpu) "
635 #endif
636
637 /* This macro defines names of additional specifications to put in the
638 specs that can be used in various specifications like CC1_SPEC. Its
639 definition is an initializer with a subgrouping for each command option.
640
641 Each subgrouping contains a string constant, that defines the
642 specification name, and a string constant that used by the GNU CC driver
643 program.
644
645 Do not define this macro if it does not need to do anything. */
646
647 #ifndef SUBTARGET_EXTRA_SPECS
648 #define SUBTARGET_EXTRA_SPECS
649 #endif
650
651 #define EXTRA_SPECS \
652 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
653 { "cpp_cpu", CPP_CPU_SPEC }, \
654 { "cpp_cpu32", CPP_CPU32_SPEC }, \
655 { "cpp_cpu64", CPP_CPU64_SPEC }, \
656 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
657 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
658 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
659 { "cc1_cpu", CC1_CPU_SPEC }, \
660 SUBTARGET_EXTRA_SPECS
661 \f
662 /* target machine storage layout */
663
664 /* Define for XFmode or TFmode extended real floating point support.
665 This will automatically cause REAL_ARITHMETIC to be defined.
666
667 The XFmode is specified by i386 ABI, while TFmode may be faster
668 due to alignment and simplifications in the address calculations.
669 */
670 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
671 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
672 #ifdef __x86_64__
673 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
674 #else
675 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
676 #endif
677 /* Tell real.c that this is the 80-bit Intel extended float format
678 packaged in a 128-bit or 96bit entity. */
679 #define INTEL_EXTENDED_IEEE_FORMAT 1
680
681
682 #define SHORT_TYPE_SIZE 16
683 #define INT_TYPE_SIZE 32
684 #define FLOAT_TYPE_SIZE 32
685 #define LONG_TYPE_SIZE BITS_PER_WORD
686 #define MAX_WCHAR_TYPE_SIZE 32
687 #define DOUBLE_TYPE_SIZE 64
688 #define LONG_LONG_TYPE_SIZE 64
689
690 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
691 #define MAX_BITS_PER_WORD 64
692 #define MAX_LONG_TYPE_SIZE 64
693 #else
694 #define MAX_BITS_PER_WORD 32
695 #define MAX_LONG_TYPE_SIZE 32
696 #endif
697
698 /* Define if you don't want extended real, but do want to use the
699 software floating point emulator for REAL_ARITHMETIC and
700 decimal <-> binary conversion. */
701 /* #define REAL_ARITHMETIC */
702
703 /* Define this if most significant byte of a word is the lowest numbered. */
704 /* That is true on the 80386. */
705
706 #define BITS_BIG_ENDIAN 0
707
708 /* Define this if most significant byte of a word is the lowest numbered. */
709 /* That is not true on the 80386. */
710 #define BYTES_BIG_ENDIAN 0
711
712 /* Define this if most significant word of a multiword number is the lowest
713 numbered. */
714 /* Not true for 80386 */
715 #define WORDS_BIG_ENDIAN 0
716
717 /* number of bits in an addressable storage unit */
718 #define BITS_PER_UNIT 8
719
720 /* Width in bits of a "word", which is the contents of a machine register.
721 Note that this is not necessarily the width of data type `int';
722 if using 16-bit ints on a 80386, this would still be 32.
723 But on a machine with 16-bit registers, this would be 16. */
724 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
725
726 /* Width of a word, in units (bytes). */
727 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
728 #define MIN_UNITS_PER_WORD 4
729
730 /* Width in bits of a pointer.
731 See also the macro `Pmode' defined below. */
732 #define POINTER_SIZE BITS_PER_WORD
733
734 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
735 #define PARM_BOUNDARY BITS_PER_WORD
736
737 /* Boundary (in *bits*) on which stack pointer should be aligned. */
738 #define STACK_BOUNDARY BITS_PER_WORD
739
740 /* Boundary (in *bits*) on which the stack pointer preferrs to be
741 aligned; the compiler cannot rely on having this alignment. */
742 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
743
744 /* As of July 2001, many runtimes to not align the stack properly when
745 entering main. This causes expand_main_function to forcably align
746 the stack, which results in aligned frames for functions called from
747 main, though it does nothing for the alignment of main itself. */
748 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
749 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
750
751 /* Allocation boundary for the code of a function. */
752 #define FUNCTION_BOUNDARY 16
753
754 /* Alignment of field after `int : 0' in a structure. */
755
756 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
757
758 /* Minimum size in bits of the largest boundary to which any
759 and all fundamental data types supported by the hardware
760 might need to be aligned. No data type wants to be aligned
761 rounder than this.
762
763 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
764 and Pentium Pro XFmode values at 128 bit boundaries. */
765
766 #define BIGGEST_ALIGNMENT 128
767
768 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
769 #define ALIGN_MODE_128(MODE) \
770 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
771 || (MODE) == V4SFmode || (MODE) == V4SImode)
772
773 /* The published ABIs say that doubles should be aligned on word
774 boundaries, so lower the aligment for structure fields unless
775 -malign-double is set. */
776 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
777 constant. Use the smaller value in that context. */
778 #ifndef IN_TARGET_LIBS
779 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
780 #else
781 #define BIGGEST_FIELD_ALIGNMENT 32
782 #endif
783
784 /* If defined, a C expression to compute the alignment given to a
785 constant that is being placed in memory. EXP is the constant
786 and ALIGN is the alignment that the object would ordinarily have.
787 The value of this macro is used instead of that alignment to align
788 the object.
789
790 If this macro is not defined, then ALIGN is used.
791
792 The typical use of this macro is to increase alignment for string
793 constants to be word aligned so that `strcpy' calls that copy
794 constants can be done inline. */
795
796 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
797
798 /* If defined, a C expression to compute the alignment for a static
799 variable. TYPE is the data type, and ALIGN is the alignment that
800 the object would ordinarily have. The value of this macro is used
801 instead of that alignment to align the object.
802
803 If this macro is not defined, then ALIGN is used.
804
805 One use of this macro is to increase alignment of medium-size
806 data to make it all fit in fewer cache lines. Another is to
807 cause character arrays to be word-aligned so that `strcpy' calls
808 that copy constants to character arrays can be done inline. */
809
810 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
811
812 /* If defined, a C expression to compute the alignment for a local
813 variable. TYPE is the data type, and ALIGN is the alignment that
814 the object would ordinarily have. The value of this macro is used
815 instead of that alignment to align the object.
816
817 If this macro is not defined, then ALIGN is used.
818
819 One use of this macro is to increase alignment of medium-size
820 data to make it all fit in fewer cache lines. */
821
822 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
823
824 /* If defined, a C expression that gives the alignment boundary, in
825 bits, of an argument with the specified mode and type. If it is
826 not defined, `PARM_BOUNDARY' is used for all arguments. */
827
828 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) ix86_function_arg_boundary (MODE, TYPE)
829
830 /* Set this non-zero if move instructions will actually fail to work
831 when given unaligned data. */
832 #define STRICT_ALIGNMENT 0
833
834 /* If bit field type is int, don't let it cross an int,
835 and give entire struct the alignment of an int. */
836 /* Required on the 386 since it doesn't have bitfield insns. */
837 #define PCC_BITFIELD_TYPE_MATTERS 1
838 \f
839 /* Standard register usage. */
840
841 /* This processor has special stack-like registers. See reg-stack.c
842 for details. */
843
844 #define STACK_REGS
845 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
846 || mode==XFmode || mode==TFmode)
847
848 /* Number of actual hardware registers.
849 The hardware registers are assigned numbers for the compiler
850 from 0 to just below FIRST_PSEUDO_REGISTER.
851 All registers that the compiler knows about must be given numbers,
852 even those that are not normally considered general registers.
853
854 In the 80386 we give the 8 general purpose registers the numbers 0-7.
855 We number the floating point registers 8-15.
856 Note that registers 0-7 can be accessed as a short or int,
857 while only 0-3 may be used with byte `mov' instructions.
858
859 Reg 16 does not correspond to any hardware register, but instead
860 appears in the RTL as an argument pointer prior to reload, and is
861 eliminated during reloading in favor of either the stack or frame
862 pointer. */
863
864 #define FIRST_PSEUDO_REGISTER 53
865
866 /* Number of hardware registers that go into the DWARF-2 unwind info.
867 If not defined, equals FIRST_PSEUDO_REGISTER. */
868
869 #define DWARF_FRAME_REGISTERS 17
870
871 /* 1 for registers that have pervasive standard uses
872 and are not available for the register allocator.
873 On the 80386, the stack pointer is such, as is the arg pointer.
874
875 The value is an mask - bit 1 is set for fixed registers
876 for 32bit target, while 2 is set for fixed registers for 64bit.
877 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
878 */
879 #define FIXED_REGISTERS \
880 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
881 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
882 /*arg,flags,fpsr,dir,frame*/ \
883 3, 3, 3, 3, 3, \
884 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
885 0, 0, 0, 0, 0, 0, 0, 0, \
886 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
887 0, 0, 0, 0, 0, 0, 0, 0, \
888 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
889 1, 1, 1, 1, 1, 1, 1, 1, \
890 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
891 1, 1, 1, 1, 1, 1, 1, 1}
892
893
894 /* 1 for registers not available across function calls.
895 These must include the FIXED_REGISTERS and also any
896 registers that can be used without being saved.
897 The latter must include the registers where values are returned
898 and the register where structure-value addresses are passed.
899 Aside from that, you can include as many other registers as you like.
900
901 The value is an mask - bit 1 is set for call used
902 for 32bit target, while 2 is set for call used for 64bit.
903 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
904 */
905 #define CALL_USED_REGISTERS \
906 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
907 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
908 /*arg,flags,fpsr,dir,frame*/ \
909 3, 3, 3, 3, 3, \
910 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
911 3, 3, 3, 3, 3, 3, 3, 3, \
912 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
913 3, 3, 3, 3, 3, 3, 3, 3, \
914 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
915 3, 3, 3, 3, 1, 1, 1, 1, \
916 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
917 3, 3, 3, 3, 3, 3, 3, 3} \
918
919 /* Order in which to allocate registers. Each register must be
920 listed once, even those in FIXED_REGISTERS. List frame pointer
921 late and fixed registers last. Note that, in general, we prefer
922 registers listed in CALL_USED_REGISTERS, keeping the others
923 available for storage of persistent values.
924
925 Three different versions of REG_ALLOC_ORDER have been tried:
926
927 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
928 but slower code on simple functions returning values in eax.
929
930 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
931 perl 4.036 due to not being able to create a DImode register (to hold a 2
932 word union).
933
934 If the order is eax, edx, ecx, ... it produces better code for simple
935 functions, and a slightly slower compiler. Users complained about the code
936 generated by allocating edx first, so restore the 'natural' order of things. */
937
938 #define REG_ALLOC_ORDER \
939 /*ax,dx,cx,*/ \
940 { 0, 1, 2, \
941 /* bx,si,di,bp,sp,*/ \
942 3, 4, 5, 6, 7, \
943 /*r8,r9,r10,r11,*/ \
944 37,38, 39, 40, \
945 /*r12,r15,r14,r13*/ \
946 41, 44, 43, 42, \
947 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
948 21, 22, 23, 24, 25, 26, 27, 28, \
949 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
950 45, 46, 47, 48, 49, 50, 51, 52, \
951 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
952 8, 9, 10, 11, 12, 13, 14, 15, \
953 /*,arg,cc,fpsr,dir,frame*/ \
954 16,17, 18, 19, 20, \
955 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
956 29, 30, 31, 32, 33, 34, 35, 36 }
957
958 /* Macro to conditionally modify fixed_regs/call_used_regs. */
959 #define CONDITIONAL_REGISTER_USAGE \
960 { \
961 int i; \
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
963 { \
964 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
965 call_used_regs[i] = (call_used_regs[i] \
966 & (TARGET_64BIT ? 2 : 1)) != 0; \
967 } \
968 if (flag_pic) \
969 { \
970 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
971 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
972 } \
973 if (! TARGET_MMX) \
974 { \
975 int i; \
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
977 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
978 fixed_regs[i] = call_used_regs[i] = 1; \
979 } \
980 if (! TARGET_SSE) \
981 { \
982 int i; \
983 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
984 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
985 fixed_regs[i] = call_used_regs[i] = 1; \
986 } \
987 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
988 { \
989 int i; \
990 HARD_REG_SET x; \
991 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
993 if (TEST_HARD_REG_BIT (x, i)) \
994 fixed_regs[i] = call_used_regs[i] = 1; \
995 } \
996 }
997
998 /* Return number of consecutive hard regs needed starting at reg REGNO
999 to hold something of mode MODE.
1000 This is ordinarily the length in words of a value of mode MODE
1001 but can be less for certain modes in special long registers.
1002
1003 Actually there are no two word move instructions for consecutive
1004 registers. And only registers 0-3 may have mov byte instructions
1005 applied to them.
1006 */
1007
1008 #define HARD_REGNO_NREGS(REGNO, MODE) \
1009 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1010 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1011 : (MODE == TFmode \
1012 ? (TARGET_64BIT ? 2 : 3) \
1013 : MODE == TCmode \
1014 ? (TARGET_64BIT ? 4 : 6) \
1015 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1016
1017 #define VALID_SSE_REG_MODE(MODE) \
1018 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1019 || (MODE) == SFmode \
1020 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1021
1022 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1023 ((MODE) == V2SFmode || (MODE) == SFmode)
1024
1025 #define VALID_MMX_REG_MODE(MODE) \
1026 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1027 || (MODE) == V2SImode || (MODE) == SImode)
1028
1029 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1030 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1031 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1032 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1033
1034 #define VALID_FP_MODE_P(mode) \
1035 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
1036 || (!TARGET_64BIT && (mode) == XFmode) \
1037 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
1038 || (!TARGET_64BIT && (mode) == XCmode))
1039
1040 #define VALID_INT_MODE_P(mode) \
1041 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
1042 || (mode) == DImode \
1043 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
1044 || (mode) == CDImode \
1045 || (TARGET_64BIT && ((mode) == TImode || (mode) == CTImode)))
1046
1047 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1048
1049 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1050 ix86_hard_regno_mode_ok (REGNO, MODE)
1051
1052 /* Value is 1 if it is a good idea to tie two pseudo registers
1053 when one has mode MODE1 and one has mode MODE2.
1054 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1055 for any hard reg, then this must be 0 for correct output. */
1056
1057 #define MODES_TIEABLE_P(MODE1, MODE2) \
1058 ((MODE1) == (MODE2) \
1059 || (((MODE1) == HImode || (MODE1) == SImode \
1060 || ((MODE1) == QImode \
1061 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1062 || ((MODE1) == DImode && TARGET_64BIT)) \
1063 && ((MODE2) == HImode || (MODE2) == SImode \
1064 || ((MODE1) == QImode \
1065 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1066 || ((MODE2) == DImode && TARGET_64BIT))))
1067
1068
1069 /* Specify the modes required to caller save a given hard regno.
1070 We do this on i386 to prevent flags from being saved at all.
1071
1072 Kill any attempts to combine saving of modes. */
1073
1074 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1075 (CC_REGNO_P (REGNO) ? VOIDmode \
1076 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1077 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1078 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1079 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1080 : (MODE))
1081 /* Specify the registers used for certain standard purposes.
1082 The values of these macros are register numbers. */
1083
1084 /* on the 386 the pc register is %eip, and is not usable as a general
1085 register. The ordinary mov instructions won't work */
1086 /* #define PC_REGNUM */
1087
1088 /* Register to use for pushing function arguments. */
1089 #define STACK_POINTER_REGNUM 7
1090
1091 /* Base register for access to local variables of the function. */
1092 #define HARD_FRAME_POINTER_REGNUM 6
1093
1094 /* Base register for access to local variables of the function. */
1095 #define FRAME_POINTER_REGNUM 20
1096
1097 /* First floating point reg */
1098 #define FIRST_FLOAT_REG 8
1099
1100 /* First & last stack-like regs */
1101 #define FIRST_STACK_REG FIRST_FLOAT_REG
1102 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1103
1104 #define FLAGS_REG 17
1105 #define FPSR_REG 18
1106 #define DIRFLAG_REG 19
1107
1108 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1109 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1110
1111 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1112 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1113
1114 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1115 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1116
1117 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1118 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1119
1120 /* Value should be nonzero if functions must have frame pointers.
1121 Zero means the frame pointer need not be set up (and parms
1122 may be accessed via the stack pointer) in functions that seem suitable.
1123 This is computed in `reload', in reload1.c. */
1124 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1125
1126 /* Override this in other tm.h files to cope with various OS losage
1127 requiring a frame pointer. */
1128 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1129 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1130 #endif
1131
1132 /* Make sure we can access arbitrary call frames. */
1133 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1134
1135 /* Base register for access to arguments of the function. */
1136 #define ARG_POINTER_REGNUM 16
1137
1138 /* Register in which static-chain is passed to a function.
1139 We do use ECX as static chain register for 32 bit ABI. On the
1140 64bit ABI, ECX is an argument register, so we use R10 instead. */
1141 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1142
1143 /* Register to hold the addressing base for position independent
1144 code access to data items.
1145 We don't use PIC pointer for 64bit mode. Define the regnum to
1146 dummy value to prevent gcc from pessimizing code dealing with EBX.
1147 */
1148 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1149
1150 /* Register in which address to store a structure value
1151 arrives in the function. On the 386, the prologue
1152 copies this from the stack to register %eax. */
1153 #define STRUCT_VALUE_INCOMING 0
1154
1155 /* Place in which caller passes the structure value address.
1156 0 means push the value on the stack like an argument. */
1157 #define STRUCT_VALUE 0
1158
1159 /* A C expression which can inhibit the returning of certain function
1160 values in registers, based on the type of value. A nonzero value
1161 says to return the function value in memory, just as large
1162 structures are always returned. Here TYPE will be a C expression
1163 of type `tree', representing the data type of the value.
1164
1165 Note that values of mode `BLKmode' must be explicitly handled by
1166 this macro. Also, the option `-fpcc-struct-return' takes effect
1167 regardless of this macro. On most systems, it is possible to
1168 leave the macro undefined; this causes a default definition to be
1169 used, whose value is the constant 1 for `BLKmode' values, and 0
1170 otherwise.
1171
1172 Do not use this macro to indicate that structures and unions
1173 should always be returned in memory. You should instead use
1174 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1175
1176 #define RETURN_IN_MEMORY(TYPE) \
1177 ix86_return_in_memory (TYPE)
1178
1179 \f
1180 /* Define the classes of registers for register constraints in the
1181 machine description. Also define ranges of constants.
1182
1183 One of the classes must always be named ALL_REGS and include all hard regs.
1184 If there is more than one class, another class must be named NO_REGS
1185 and contain no registers.
1186
1187 The name GENERAL_REGS must be the name of a class (or an alias for
1188 another name such as ALL_REGS). This is the class of registers
1189 that is allowed by "g" or "r" in a register constraint.
1190 Also, registers outside this class are allocated only when
1191 instructions express preferences for them.
1192
1193 The classes must be numbered in nondecreasing order; that is,
1194 a larger-numbered class must never be contained completely
1195 in a smaller-numbered class.
1196
1197 For any two classes, it is very desirable that there be another
1198 class that represents their union.
1199
1200 It might seem that class BREG is unnecessary, since no useful 386
1201 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1202 and the "b" register constraint is useful in asms for syscalls.
1203
1204 The flags and fpsr registers are in no class. */
1205
1206 enum reg_class
1207 {
1208 NO_REGS,
1209 AREG, DREG, CREG, BREG, SIREG, DIREG,
1210 AD_REGS, /* %eax/%edx for DImode */
1211 Q_REGS, /* %eax %ebx %ecx %edx */
1212 NON_Q_REGS, /* %esi %edi %ebp %esp */
1213 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1214 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1215 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1216 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1217 FLOAT_REGS,
1218 SSE_REGS,
1219 MMX_REGS,
1220 FP_TOP_SSE_REGS,
1221 FP_SECOND_SSE_REGS,
1222 FLOAT_SSE_REGS,
1223 FLOAT_INT_REGS,
1224 INT_SSE_REGS,
1225 FLOAT_INT_SSE_REGS,
1226 ALL_REGS, LIM_REG_CLASSES
1227 };
1228
1229 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1230
1231 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1232 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1233 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1234 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1235 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1236 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1237 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1238 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1239
1240 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1241
1242 /* Give names of register classes as strings for dump file. */
1243
1244 #define REG_CLASS_NAMES \
1245 { "NO_REGS", \
1246 "AREG", "DREG", "CREG", "BREG", \
1247 "SIREG", "DIREG", \
1248 "AD_REGS", \
1249 "Q_REGS", "NON_Q_REGS", \
1250 "INDEX_REGS", \
1251 "LEGACY_REGS", \
1252 "GENERAL_REGS", \
1253 "FP_TOP_REG", "FP_SECOND_REG", \
1254 "FLOAT_REGS", \
1255 "SSE_REGS", \
1256 "MMX_REGS", \
1257 "FP_TOP_SSE_REGS", \
1258 "FP_SECOND_SSE_REGS", \
1259 "FLOAT_SSE_REGS", \
1260 "FLOAT_INT_REGS", \
1261 "INT_SSE_REGS", \
1262 "FLOAT_INT_SSE_REGS", \
1263 "ALL_REGS" }
1264
1265 /* Define which registers fit in which classes.
1266 This is an initializer for a vector of HARD_REG_SET
1267 of length N_REG_CLASSES. */
1268
1269 #define REG_CLASS_CONTENTS \
1270 { { 0x00, 0x0 }, \
1271 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1272 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1273 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1274 { 0x03, 0x0 }, /* AD_REGS */ \
1275 { 0x0f, 0x0 }, /* Q_REGS */ \
1276 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1277 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1278 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1279 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1280 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1281 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1282 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1283 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1284 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1285 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1286 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1287 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1288 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1289 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1290 { 0xffffffff,0x1fffff } \
1291 }
1292
1293 /* The same information, inverted:
1294 Return the class number of the smallest class containing
1295 reg number REGNO. This could be a conditional expression
1296 or could index an array. */
1297
1298 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1299
1300 /* When defined, the compiler allows registers explicitly used in the
1301 rtl to be used as spill registers but prevents the compiler from
1302 extending the lifetime of these registers. */
1303
1304 #define SMALL_REGISTER_CLASSES 1
1305
1306 #define QI_REG_P(X) \
1307 (REG_P (X) && REGNO (X) < 4)
1308
1309 #define GENERAL_REGNO_P(n) \
1310 ((n) < 8 || REX_INT_REGNO_P (n))
1311
1312 #define GENERAL_REG_P(X) \
1313 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1314
1315 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1316
1317 #define NON_QI_REG_P(X) \
1318 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1319
1320 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1321 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1322
1323 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1324 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1325 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1326 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1327
1328 #define SSE_REGNO_P(n) \
1329 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1330 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1331
1332 #define SSE_REGNO(n) \
1333 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1334 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1335
1336 #define SSE_FLOAT_MODE_P(m) \
1337 ((TARGET_SSE_MATH && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1338
1339 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1340 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1341
1342 #define STACK_REG_P(xop) (REG_P (xop) && \
1343 REGNO (xop) >= FIRST_STACK_REG && \
1344 REGNO (xop) <= LAST_STACK_REG)
1345
1346 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1347
1348 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1349
1350 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1351 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1352
1353 /* Indicate whether hard register numbered REG_NO should be converted
1354 to SSA form. */
1355 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1356 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1357
1358 /* The class value for index registers, and the one for base regs. */
1359
1360 #define INDEX_REG_CLASS INDEX_REGS
1361 #define BASE_REG_CLASS GENERAL_REGS
1362
1363 /* Get reg_class from a letter such as appears in the machine description. */
1364
1365 #define REG_CLASS_FROM_LETTER(C) \
1366 ((C) == 'r' ? GENERAL_REGS : \
1367 (C) == 'R' ? LEGACY_REGS : \
1368 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1369 (C) == 'Q' ? Q_REGS : \
1370 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1371 ? FLOAT_REGS \
1372 : NO_REGS) : \
1373 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1374 ? FP_TOP_REG \
1375 : NO_REGS) : \
1376 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1377 ? FP_SECOND_REG \
1378 : NO_REGS) : \
1379 (C) == 'a' ? AREG : \
1380 (C) == 'b' ? BREG : \
1381 (C) == 'c' ? CREG : \
1382 (C) == 'd' ? DREG : \
1383 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1384 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1385 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1386 (C) == 'A' ? AD_REGS : \
1387 (C) == 'D' ? DIREG : \
1388 (C) == 'S' ? SIREG : NO_REGS)
1389
1390 /* The letters I, J, K, L and M in a register constraint string
1391 can be used to stand for particular ranges of immediate operands.
1392 This macro defines what the ranges are.
1393 C is the letter, and VALUE is a constant value.
1394 Return 1 if VALUE is in the range specified by C.
1395
1396 I is for non-DImode shifts.
1397 J is for DImode shifts.
1398 K is for signed imm8 operands.
1399 L is for andsi as zero-extending move.
1400 M is for shifts that can be executed by the "lea" opcode.
1401 N is for immedaite operands for out/in instructions (0-255)
1402 */
1403
1404 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1405 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1406 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1407 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1408 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1409 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1410 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1411 : 0)
1412
1413 /* Similar, but for floating constants, and defining letters G and H.
1414 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1415 TARGET_387 isn't set, because the stack register converter may need to
1416 load 0.0 into the function value register. */
1417
1418 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1419 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1420 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1421
1422 /* A C expression that defines the optional machine-dependent
1423 constraint letters that can be used to segregate specific types of
1424 operands, usually memory references, for the target machine. Any
1425 letter that is not elsewhere defined and not matched by
1426 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1427 be defined.
1428
1429 If it is required for a particular target machine, it should
1430 return 1 if VALUE corresponds to the operand type represented by
1431 the constraint letter C. If C is not defined as an extra
1432 constraint, the value returned should be 0 regardless of VALUE. */
1433
1434 #define EXTRA_CONSTRAINT(VALUE, C) \
1435 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1436 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1437 : 0)
1438
1439 /* Place additional restrictions on the register class to use when it
1440 is necessary to be able to hold a value of mode MODE in a reload
1441 register for which class CLASS would ordinarily be used. */
1442
1443 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1444 ((MODE) == QImode && !TARGET_64BIT \
1445 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1446 ? Q_REGS : (CLASS))
1447
1448 /* Given an rtx X being reloaded into a reg required to be
1449 in class CLASS, return the class of reg to actually use.
1450 In general this is just CLASS; but on some machines
1451 in some cases it is preferable to use a more restrictive class.
1452 On the 80386 series, we prevent floating constants from being
1453 reloaded into floating registers (since no move-insn can do that)
1454 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1455
1456 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1457 QImode must go into class Q_REGS.
1458 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1459 movdf to do mem-to-mem moves through integer regs. */
1460
1461 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1462 ix86_preferred_reload_class (X, CLASS)
1463
1464 /* If we are copying between general and FP registers, we need a memory
1465 location. The same is true for SSE and MMX registers. */
1466 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1467 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1468
1469 /* QImode spills from non-QI registers need a scratch. This does not
1470 happen often -- the only example so far requires an uninitialized
1471 pseudo. */
1472
1473 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1474 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1475 ? Q_REGS : NO_REGS)
1476
1477 /* Return the maximum number of consecutive registers
1478 needed to represent mode MODE in a register of class CLASS. */
1479 /* On the 80386, this is the size of MODE in words,
1480 except in the FP regs, where a single reg is always enough.
1481 The TFmodes are really just 80bit values, so we use only 3 registers
1482 to hold them, instead of 4, as the size would suggest.
1483 */
1484 #define CLASS_MAX_NREGS(CLASS, MODE) \
1485 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1486 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1487 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1488 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1489
1490 /* A C expression whose value is nonzero if pseudos that have been
1491 assigned to registers of class CLASS would likely be spilled
1492 because registers of CLASS are needed for spill registers.
1493
1494 The default value of this macro returns 1 if CLASS has exactly one
1495 register and zero otherwise. On most machines, this default
1496 should be used. Only define this macro to some other expression
1497 if pseudo allocated by `local-alloc.c' end up in memory because
1498 their hard registers were needed for spill registers. If this
1499 macro returns nonzero for those classes, those pseudos will only
1500 be allocated by `global.c', which knows how to reallocate the
1501 pseudo to another register. If there would not be another
1502 register available for reallocation, you should not change the
1503 definition of this macro since the only effect of such a
1504 definition would be to slow down register allocation. */
1505
1506 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1507 (((CLASS) == AREG) \
1508 || ((CLASS) == DREG) \
1509 || ((CLASS) == CREG) \
1510 || ((CLASS) == BREG) \
1511 || ((CLASS) == AD_REGS) \
1512 || ((CLASS) == SIREG) \
1513 || ((CLASS) == DIREG))
1514
1515 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1516 to automatically clobber for all asms.
1517
1518 We do this in the new i386 backend to maintain source compatibility
1519 with the old cc0-based compiler. */
1520
1521 #define MD_ASM_CLOBBERS(CLOBBERS) \
1522 do { \
1523 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1524 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1525 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1526 } while (0)
1527 \f
1528 /* Stack layout; function entry, exit and calling. */
1529
1530 /* Define this if pushing a word on the stack
1531 makes the stack pointer a smaller address. */
1532 #define STACK_GROWS_DOWNWARD
1533
1534 /* Define this if the nominal address of the stack frame
1535 is at the high-address end of the local variables;
1536 that is, each additional local variable allocated
1537 goes at a more negative offset in the frame. */
1538 #define FRAME_GROWS_DOWNWARD
1539
1540 /* Offset within stack frame to start allocating local variables at.
1541 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1542 first local allocated. Otherwise, it is the offset to the BEGINNING
1543 of the first local allocated. */
1544 #define STARTING_FRAME_OFFSET 0
1545
1546 /* If we generate an insn to push BYTES bytes,
1547 this says how many the stack pointer really advances by.
1548 On 386 pushw decrements by exactly 2 no matter what the position was.
1549 On the 386 there is no pushb; we use pushw instead, and this
1550 has the effect of rounding up to 2.
1551
1552 For 64bit ABI we round up to 8 bytes.
1553 */
1554
1555 #define PUSH_ROUNDING(BYTES) \
1556 (TARGET_64BIT \
1557 ? (((BYTES) + 7) & (-8)) \
1558 : (((BYTES) + 1) & (-2)))
1559
1560 /* If defined, the maximum amount of space required for outgoing arguments will
1561 be computed and placed into the variable
1562 `current_function_outgoing_args_size'. No space will be pushed onto the
1563 stack for each call; instead, the function prologue should increase the stack
1564 frame size by this amount. */
1565
1566 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1567
1568 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1569 instructions to pass outgoing arguments. */
1570
1571 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1572
1573 /* Offset of first parameter from the argument pointer register value. */
1574 #define FIRST_PARM_OFFSET(FNDECL) 0
1575
1576 /* Define this macro if functions should assume that stack space has been
1577 allocated for arguments even when their values are passed in registers.
1578
1579 The value of this macro is the size, in bytes, of the area reserved for
1580 arguments passed in registers for the function represented by FNDECL.
1581
1582 This space can be allocated by the caller, or be a part of the
1583 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1584 which. */
1585 #define REG_PARM_STACK_SPACE(FNDECL) 0
1586
1587 /* Define as a C expression that evaluates to nonzero if we do not know how
1588 to pass TYPE solely in registers. The file expr.h defines a
1589 definition that is usually appropriate, refer to expr.h for additional
1590 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1591 computed in the stack and then loaded into a register. */
1592 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1593 ((TYPE) != 0 \
1594 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1595 || TREE_ADDRESSABLE (TYPE) \
1596 || ((MODE) == TImode) \
1597 || ((MODE) == BLKmode \
1598 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1599 && 0 == (int_size_in_bytes (TYPE) \
1600 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1601 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1602 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1603
1604 /* Value is the number of bytes of arguments automatically
1605 popped when returning from a subroutine call.
1606 FUNDECL is the declaration node of the function (as a tree),
1607 FUNTYPE is the data type of the function (as a tree),
1608 or for a library call it is an identifier node for the subroutine name.
1609 SIZE is the number of bytes of arguments passed on the stack.
1610
1611 On the 80386, the RTD insn may be used to pop them if the number
1612 of args is fixed, but if the number is variable then the caller
1613 must pop them all. RTD can't be used for library calls now
1614 because the library is compiled with the Unix compiler.
1615 Use of RTD is a selectable option, since it is incompatible with
1616 standard Unix calling sequences. If the option is not selected,
1617 the caller must always pop the args.
1618
1619 The attribute stdcall is equivalent to RTD on a per module basis. */
1620
1621 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1622 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1623
1624 /* Define how to find the value returned by a function.
1625 VALTYPE is the data type of the value (as a tree).
1626 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1627 otherwise, FUNC is 0. */
1628 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1629 ix86_function_value (VALTYPE)
1630
1631 #define FUNCTION_VALUE_REGNO_P(N) \
1632 ix86_function_value_regno_p (N)
1633
1634 /* Define how to find the value returned by a library function
1635 assuming the value has mode MODE. */
1636
1637 #define LIBCALL_VALUE(MODE) \
1638 ix86_libcall_value (MODE)
1639
1640 /* Define the size of the result block used for communication between
1641 untyped_call and untyped_return. The block contains a DImode value
1642 followed by the block used by fnsave and frstor. */
1643
1644 #define APPLY_RESULT_SIZE (8+108)
1645
1646 /* 1 if N is a possible register number for function argument passing. */
1647 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1648
1649 /* Define a data type for recording info about an argument list
1650 during the scan of that argument list. This data type should
1651 hold all necessary information about the function itself
1652 and about the args processed so far, enough to enable macros
1653 such as FUNCTION_ARG to determine where the next arg should go. */
1654
1655 typedef struct ix86_args {
1656 int words; /* # words passed so far */
1657 int nregs; /* # registers available for passing */
1658 int regno; /* next available register number */
1659 int sse_words; /* # sse words passed so far */
1660 int sse_nregs; /* # sse registers available for passing */
1661 int sse_regno; /* next available sse register number */
1662 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1663 } CUMULATIVE_ARGS;
1664
1665 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1666 for a call to a function whose data type is FNTYPE.
1667 For a library call, FNTYPE is 0. */
1668
1669 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1670 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1671
1672 /* Update the data in CUM to advance over an argument
1673 of mode MODE and data type TYPE.
1674 (TYPE is null for libcalls where that information may not be available.) */
1675
1676 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1677 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1678
1679 /* Define where to put the arguments to a function.
1680 Value is zero to push the argument on the stack,
1681 or a hard register in which to store the argument.
1682
1683 MODE is the argument's machine mode.
1684 TYPE is the data type of the argument (as a tree).
1685 This is null for libcalls where that information may
1686 not be available.
1687 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1688 the preceding args and about the function being called.
1689 NAMED is nonzero if this argument is a named parameter
1690 (otherwise it is an extra parameter matching an ellipsis). */
1691
1692 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1693 (function_arg (&CUM, MODE, TYPE, NAMED))
1694
1695 /* For an arg passed partly in registers and partly in memory,
1696 this is the number of registers used.
1697 For args passed entirely in registers or entirely in memory, zero. */
1698
1699 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1700
1701 /* If PIC, we cannot make sibling calls to global functions
1702 because the PLT requires %ebx live.
1703 If we are returning floats on the register stack, we cannot make
1704 sibling calls to functions that return floats. (The stack adjust
1705 instruction will wind up after the sibcall jump, and not be executed.) */
1706 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1707 (DECL \
1708 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1709 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1710 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1711 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1712
1713 /* Perform any needed actions needed for a function that is receiving a
1714 variable number of arguments.
1715
1716 CUM is as above.
1717
1718 MODE and TYPE are the mode and type of the current parameter.
1719
1720 PRETEND_SIZE is a variable that should be set to the amount of stack
1721 that must be pushed by the prolog to pretend that our caller pushed
1722 it.
1723
1724 Normally, this macro will push all remaining incoming registers on the
1725 stack and set PRETEND_SIZE to the length of the registers pushed. */
1726
1727 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1728 ix86_setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1729
1730 /* Define the `__builtin_va_list' type for the ABI. */
1731 #define BUILD_VA_LIST_TYPE(VALIST) \
1732 (VALIST) = ix86_build_va_list ()
1733
1734 /* Implement `va_start' for varargs and stdarg. */
1735 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1736 ix86_va_start (stdarg, valist, nextarg)
1737
1738 /* Implement `va_arg'. */
1739 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1740 ix86_va_arg (valist, type)
1741
1742 /* This macro is invoked at the end of compilation. It is used here to
1743 output code for -fpic that will load the return address into %ebx. */
1744
1745 #undef ASM_FILE_END
1746 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1747
1748 /* Output assembler code to FILE to increment profiler label # LABELNO
1749 for profiling a function entry. */
1750
1751 #define FUNCTION_PROFILER(FILE, LABELNO) \
1752 { \
1753 if (flag_pic) \
1754 { \
1755 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1756 LPREFIX, (LABELNO)); \
1757 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1758 } \
1759 else \
1760 { \
1761 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1762 fprintf (FILE, "\tcall\t_mcount\n"); \
1763 } \
1764 }
1765
1766 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1767 the stack pointer does not matter. The value is tested only in
1768 functions that have frame pointers.
1769 No definition is equivalent to always zero. */
1770 /* Note on the 386 it might be more efficient not to define this since
1771 we have to restore it ourselves from the frame pointer, in order to
1772 use pop */
1773
1774 #define EXIT_IGNORE_STACK 1
1775
1776 /* Output assembler code for a block containing the constant parts
1777 of a trampoline, leaving space for the variable parts. */
1778
1779 /* On the 386, the trampoline contains two instructions:
1780 mov #STATIC,ecx
1781 jmp FUNCTION
1782 The trampoline is generated entirely at runtime. The operand of JMP
1783 is the address of FUNCTION relative to the instruction following the
1784 JMP (which is 5 bytes long). */
1785
1786 /* Length in units of the trampoline for entering a nested function. */
1787
1788 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1789
1790 /* Emit RTL insns to initialize the variable parts of a trampoline.
1791 FNADDR is an RTX for the address of the function's pure code.
1792 CXT is an RTX for the static chain value for the function. */
1793
1794 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1795 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1796 \f
1797 /* Definitions for register eliminations.
1798
1799 This is an array of structures. Each structure initializes one pair
1800 of eliminable registers. The "from" register number is given first,
1801 followed by "to". Eliminations of the same "from" register are listed
1802 in order of preference.
1803
1804 There are two registers that can always be eliminated on the i386.
1805 The frame pointer and the arg pointer can be replaced by either the
1806 hard frame pointer or to the stack pointer, depending upon the
1807 circumstances. The hard frame pointer is not used before reload and
1808 so it is not eligible for elimination. */
1809
1810 #define ELIMINABLE_REGS \
1811 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1812 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1813 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1814 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1815
1816 /* Given FROM and TO register numbers, say whether this elimination is
1817 allowed. Frame pointer elimination is automatically handled.
1818
1819 All other eliminations are valid. */
1820
1821 #define CAN_ELIMINATE(FROM, TO) \
1822 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1823
1824 /* Define the offset between two registers, one to be eliminated, and the other
1825 its replacement, at the start of a routine. */
1826
1827 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1828 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1829 \f
1830 /* Addressing modes, and classification of registers for them. */
1831
1832 /* #define HAVE_POST_INCREMENT 0 */
1833 /* #define HAVE_POST_DECREMENT 0 */
1834
1835 /* #define HAVE_PRE_DECREMENT 0 */
1836 /* #define HAVE_PRE_INCREMENT 0 */
1837
1838 /* Macros to check register numbers against specific register classes. */
1839
1840 /* These assume that REGNO is a hard or pseudo reg number.
1841 They give nonzero only if REGNO is a hard reg of the suitable class
1842 or a pseudo reg currently allocated to a suitable hard reg.
1843 Since they use reg_renumber, they are safe only once reg_renumber
1844 has been allocated, which happens in local-alloc.c. */
1845
1846 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1847 ((REGNO) < STACK_POINTER_REGNUM \
1848 || (REGNO >= FIRST_REX_INT_REG \
1849 && (REGNO) <= LAST_REX_INT_REG) \
1850 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1851 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1852 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1853
1854 #define REGNO_OK_FOR_BASE_P(REGNO) \
1855 ((REGNO) <= STACK_POINTER_REGNUM \
1856 || (REGNO) == ARG_POINTER_REGNUM \
1857 || (REGNO) == FRAME_POINTER_REGNUM \
1858 || (REGNO >= FIRST_REX_INT_REG \
1859 && (REGNO) <= LAST_REX_INT_REG) \
1860 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1861 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1862 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1863
1864 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1865 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1866
1867 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1868 and check its validity for a certain class.
1869 We have two alternate definitions for each of them.
1870 The usual definition accepts all pseudo regs; the other rejects
1871 them unless they have been allocated suitable hard regs.
1872 The symbol REG_OK_STRICT causes the latter definition to be used.
1873
1874 Most source files want to accept pseudo regs in the hope that
1875 they will get allocated to the class that the insn wants them to be in.
1876 Source files for reload pass need to be strict.
1877 After reload, it makes no difference, since pseudo regs have
1878 been eliminated by then. */
1879
1880
1881 /* Non strict versions, pseudos are ok */
1882 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1883 (REGNO (X) < STACK_POINTER_REGNUM \
1884 || (REGNO (X) >= FIRST_REX_INT_REG \
1885 && REGNO (X) <= LAST_REX_INT_REG) \
1886 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1887
1888 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1889 (REGNO (X) <= STACK_POINTER_REGNUM \
1890 || REGNO (X) == ARG_POINTER_REGNUM \
1891 || REGNO (X) == FRAME_POINTER_REGNUM \
1892 || (REGNO (X) >= FIRST_REX_INT_REG \
1893 && REGNO (X) <= LAST_REX_INT_REG) \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1895
1896 /* Strict versions, hard registers only */
1897 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1898 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1899
1900 #ifndef REG_OK_STRICT
1901 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1902 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1903
1904 #else
1905 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1906 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1907 #endif
1908
1909 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1910 that is a valid memory address for an instruction.
1911 The MODE argument is the machine mode for the MEM expression
1912 that wants to use this address.
1913
1914 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1915 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1916
1917 See legitimize_pic_address in i386.c for details as to what
1918 constitutes a legitimate address when -fpic is used. */
1919
1920 #define MAX_REGS_PER_ADDRESS 2
1921
1922 #define CONSTANT_ADDRESS_P(X) \
1923 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1924 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1925 || GET_CODE (X) == CONST_DOUBLE)
1926
1927 /* Nonzero if the constant value X is a legitimate general operand.
1928 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1929
1930 #define LEGITIMATE_CONSTANT_P(X) 1
1931
1932 #ifdef REG_OK_STRICT
1933 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1934 { \
1935 if (legitimate_address_p (MODE, X, 1)) \
1936 goto ADDR; \
1937 }
1938
1939 #else
1940 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1941 { \
1942 if (legitimate_address_p (MODE, X, 0)) \
1943 goto ADDR; \
1944 }
1945
1946 #endif
1947
1948 /* If defined, a C expression to determine the base term of address X.
1949 This macro is used in only one place: `find_base_term' in alias.c.
1950
1951 It is always safe for this macro to not be defined. It exists so
1952 that alias analysis can understand machine-dependent addresses.
1953
1954 The typical use of this macro is to handle addresses containing
1955 a label_ref or symbol_ref within an UNSPEC. */
1956
1957 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1958
1959 /* Try machine-dependent ways of modifying an illegitimate address
1960 to be legitimate. If we find one, return the new, valid address.
1961 This macro is used in only one place: `memory_address' in explow.c.
1962
1963 OLDX is the address as it was before break_out_memory_refs was called.
1964 In some cases it is useful to look at this to decide what needs to be done.
1965
1966 MODE and WIN are passed so that this macro can use
1967 GO_IF_LEGITIMATE_ADDRESS.
1968
1969 It is always safe for this macro to do nothing. It exists to recognize
1970 opportunities to optimize the output.
1971
1972 For the 80386, we handle X+REG by loading X into a register R and
1973 using R+REG. R will go in a general reg and indexing will be used.
1974 However, if REG is a broken-out memory address or multiplication,
1975 nothing needs to be done because REG can certainly go in a general reg.
1976
1977 When -fpic is used, special handling is needed for symbolic references.
1978 See comments by legitimize_pic_address in i386.c for details. */
1979
1980 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1981 { \
1982 (X) = legitimize_address (X, OLDX, MODE); \
1983 if (memory_address_p (MODE, X)) \
1984 goto WIN; \
1985 }
1986
1987 #define REWRITE_ADDRESS(x) rewrite_address(x)
1988
1989 /* Nonzero if the constant value X is a legitimate general operand
1990 when generating PIC code. It is given that flag_pic is on and
1991 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1992
1993 #define LEGITIMATE_PIC_OPERAND_P(X) \
1994 (! SYMBOLIC_CONST (X) \
1995 || legitimate_pic_address_disp_p (X))
1996
1997 #define SYMBOLIC_CONST(X) \
1998 (GET_CODE (X) == SYMBOL_REF \
1999 || GET_CODE (X) == LABEL_REF \
2000 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2001
2002 /* Go to LABEL if ADDR (a legitimate address expression)
2003 has an effect that depends on the machine mode it is used for.
2004 On the 80386, only postdecrement and postincrement address depend thus
2005 (the amount of decrement or increment being the length of the operand). */
2006 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2007 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
2008 \f
2009 /* Codes for all the SSE/MMX builtins. */
2010 enum ix86_builtins
2011 {
2012 IX86_BUILTIN_ADDPS,
2013 IX86_BUILTIN_ADDSS,
2014 IX86_BUILTIN_DIVPS,
2015 IX86_BUILTIN_DIVSS,
2016 IX86_BUILTIN_MULPS,
2017 IX86_BUILTIN_MULSS,
2018 IX86_BUILTIN_SUBPS,
2019 IX86_BUILTIN_SUBSS,
2020
2021 IX86_BUILTIN_CMPEQPS,
2022 IX86_BUILTIN_CMPLTPS,
2023 IX86_BUILTIN_CMPLEPS,
2024 IX86_BUILTIN_CMPGTPS,
2025 IX86_BUILTIN_CMPGEPS,
2026 IX86_BUILTIN_CMPNEQPS,
2027 IX86_BUILTIN_CMPNLTPS,
2028 IX86_BUILTIN_CMPNLEPS,
2029 IX86_BUILTIN_CMPNGTPS,
2030 IX86_BUILTIN_CMPNGEPS,
2031 IX86_BUILTIN_CMPORDPS,
2032 IX86_BUILTIN_CMPUNORDPS,
2033 IX86_BUILTIN_CMPNEPS,
2034 IX86_BUILTIN_CMPEQSS,
2035 IX86_BUILTIN_CMPLTSS,
2036 IX86_BUILTIN_CMPLESS,
2037 IX86_BUILTIN_CMPGTSS,
2038 IX86_BUILTIN_CMPGESS,
2039 IX86_BUILTIN_CMPNEQSS,
2040 IX86_BUILTIN_CMPNLTSS,
2041 IX86_BUILTIN_CMPNLESS,
2042 IX86_BUILTIN_CMPNGTSS,
2043 IX86_BUILTIN_CMPNGESS,
2044 IX86_BUILTIN_CMPORDSS,
2045 IX86_BUILTIN_CMPUNORDSS,
2046 IX86_BUILTIN_CMPNESS,
2047
2048 IX86_BUILTIN_COMIEQSS,
2049 IX86_BUILTIN_COMILTSS,
2050 IX86_BUILTIN_COMILESS,
2051 IX86_BUILTIN_COMIGTSS,
2052 IX86_BUILTIN_COMIGESS,
2053 IX86_BUILTIN_COMINEQSS,
2054 IX86_BUILTIN_UCOMIEQSS,
2055 IX86_BUILTIN_UCOMILTSS,
2056 IX86_BUILTIN_UCOMILESS,
2057 IX86_BUILTIN_UCOMIGTSS,
2058 IX86_BUILTIN_UCOMIGESS,
2059 IX86_BUILTIN_UCOMINEQSS,
2060
2061 IX86_BUILTIN_CVTPI2PS,
2062 IX86_BUILTIN_CVTPS2PI,
2063 IX86_BUILTIN_CVTSI2SS,
2064 IX86_BUILTIN_CVTSS2SI,
2065 IX86_BUILTIN_CVTTPS2PI,
2066 IX86_BUILTIN_CVTTSS2SI,
2067 IX86_BUILTIN_M_FROM_INT,
2068 IX86_BUILTIN_M_TO_INT,
2069
2070 IX86_BUILTIN_MAXPS,
2071 IX86_BUILTIN_MAXSS,
2072 IX86_BUILTIN_MINPS,
2073 IX86_BUILTIN_MINSS,
2074
2075 IX86_BUILTIN_LOADAPS,
2076 IX86_BUILTIN_LOADUPS,
2077 IX86_BUILTIN_STOREAPS,
2078 IX86_BUILTIN_STOREUPS,
2079 IX86_BUILTIN_LOADSS,
2080 IX86_BUILTIN_STORESS,
2081 IX86_BUILTIN_MOVSS,
2082
2083 IX86_BUILTIN_MOVHLPS,
2084 IX86_BUILTIN_MOVLHPS,
2085 IX86_BUILTIN_LOADHPS,
2086 IX86_BUILTIN_LOADLPS,
2087 IX86_BUILTIN_STOREHPS,
2088 IX86_BUILTIN_STORELPS,
2089
2090 IX86_BUILTIN_MASKMOVQ,
2091 IX86_BUILTIN_MOVMSKPS,
2092 IX86_BUILTIN_PMOVMSKB,
2093
2094 IX86_BUILTIN_MOVNTPS,
2095 IX86_BUILTIN_MOVNTQ,
2096
2097 IX86_BUILTIN_PACKSSWB,
2098 IX86_BUILTIN_PACKSSDW,
2099 IX86_BUILTIN_PACKUSWB,
2100
2101 IX86_BUILTIN_PADDB,
2102 IX86_BUILTIN_PADDW,
2103 IX86_BUILTIN_PADDD,
2104 IX86_BUILTIN_PADDSB,
2105 IX86_BUILTIN_PADDSW,
2106 IX86_BUILTIN_PADDUSB,
2107 IX86_BUILTIN_PADDUSW,
2108 IX86_BUILTIN_PSUBB,
2109 IX86_BUILTIN_PSUBW,
2110 IX86_BUILTIN_PSUBD,
2111 IX86_BUILTIN_PSUBSB,
2112 IX86_BUILTIN_PSUBSW,
2113 IX86_BUILTIN_PSUBUSB,
2114 IX86_BUILTIN_PSUBUSW,
2115
2116 IX86_BUILTIN_PAND,
2117 IX86_BUILTIN_PANDN,
2118 IX86_BUILTIN_POR,
2119 IX86_BUILTIN_PXOR,
2120
2121 IX86_BUILTIN_PAVGB,
2122 IX86_BUILTIN_PAVGW,
2123
2124 IX86_BUILTIN_PCMPEQB,
2125 IX86_BUILTIN_PCMPEQW,
2126 IX86_BUILTIN_PCMPEQD,
2127 IX86_BUILTIN_PCMPGTB,
2128 IX86_BUILTIN_PCMPGTW,
2129 IX86_BUILTIN_PCMPGTD,
2130
2131 IX86_BUILTIN_PEXTRW,
2132 IX86_BUILTIN_PINSRW,
2133
2134 IX86_BUILTIN_PMADDWD,
2135
2136 IX86_BUILTIN_PMAXSW,
2137 IX86_BUILTIN_PMAXUB,
2138 IX86_BUILTIN_PMINSW,
2139 IX86_BUILTIN_PMINUB,
2140
2141 IX86_BUILTIN_PMULHUW,
2142 IX86_BUILTIN_PMULHW,
2143 IX86_BUILTIN_PMULLW,
2144
2145 IX86_BUILTIN_PSADBW,
2146 IX86_BUILTIN_PSHUFW,
2147
2148 IX86_BUILTIN_PSLLW,
2149 IX86_BUILTIN_PSLLD,
2150 IX86_BUILTIN_PSLLQ,
2151 IX86_BUILTIN_PSRAW,
2152 IX86_BUILTIN_PSRAD,
2153 IX86_BUILTIN_PSRLW,
2154 IX86_BUILTIN_PSRLD,
2155 IX86_BUILTIN_PSRLQ,
2156 IX86_BUILTIN_PSLLWI,
2157 IX86_BUILTIN_PSLLDI,
2158 IX86_BUILTIN_PSLLQI,
2159 IX86_BUILTIN_PSRAWI,
2160 IX86_BUILTIN_PSRADI,
2161 IX86_BUILTIN_PSRLWI,
2162 IX86_BUILTIN_PSRLDI,
2163 IX86_BUILTIN_PSRLQI,
2164
2165 IX86_BUILTIN_PUNPCKHBW,
2166 IX86_BUILTIN_PUNPCKHWD,
2167 IX86_BUILTIN_PUNPCKHDQ,
2168 IX86_BUILTIN_PUNPCKLBW,
2169 IX86_BUILTIN_PUNPCKLWD,
2170 IX86_BUILTIN_PUNPCKLDQ,
2171
2172 IX86_BUILTIN_SHUFPS,
2173
2174 IX86_BUILTIN_RCPPS,
2175 IX86_BUILTIN_RCPSS,
2176 IX86_BUILTIN_RSQRTPS,
2177 IX86_BUILTIN_RSQRTSS,
2178 IX86_BUILTIN_SQRTPS,
2179 IX86_BUILTIN_SQRTSS,
2180
2181 IX86_BUILTIN_UNPCKHPS,
2182 IX86_BUILTIN_UNPCKLPS,
2183
2184 IX86_BUILTIN_ANDPS,
2185 IX86_BUILTIN_ANDNPS,
2186 IX86_BUILTIN_ORPS,
2187 IX86_BUILTIN_XORPS,
2188
2189 IX86_BUILTIN_EMMS,
2190 IX86_BUILTIN_LDMXCSR,
2191 IX86_BUILTIN_STMXCSR,
2192 IX86_BUILTIN_SFENCE,
2193 IX86_BUILTIN_PREFETCH,
2194
2195 /* 3DNow! Original */
2196 IX86_BUILTIN_FEMMS,
2197 IX86_BUILTIN_PAVGUSB,
2198 IX86_BUILTIN_PF2ID,
2199 IX86_BUILTIN_PFACC,
2200 IX86_BUILTIN_PFADD,
2201 IX86_BUILTIN_PFCMPEQ,
2202 IX86_BUILTIN_PFCMPGE,
2203 IX86_BUILTIN_PFCMPGT,
2204 IX86_BUILTIN_PFMAX,
2205 IX86_BUILTIN_PFMIN,
2206 IX86_BUILTIN_PFMUL,
2207 IX86_BUILTIN_PFRCP,
2208 IX86_BUILTIN_PFRCPIT1,
2209 IX86_BUILTIN_PFRCPIT2,
2210 IX86_BUILTIN_PFRSQIT1,
2211 IX86_BUILTIN_PFRSQRT,
2212 IX86_BUILTIN_PFSUB,
2213 IX86_BUILTIN_PFSUBR,
2214 IX86_BUILTIN_PI2FD,
2215 IX86_BUILTIN_PMULHRW,
2216 IX86_BUILTIN_PREFETCH_3DNOW, /* PREFETCH already used */
2217 IX86_BUILTIN_PREFETCHW,
2218
2219 /* 3DNow! Athlon Extensions */
2220 IX86_BUILTIN_PF2IW,
2221 IX86_BUILTIN_PFNACC,
2222 IX86_BUILTIN_PFPNACC,
2223 IX86_BUILTIN_PI2FW,
2224 IX86_BUILTIN_PSWAPDSI,
2225 IX86_BUILTIN_PSWAPDSF,
2226
2227 /* Composite builtins, expand to more than one insn. */
2228 IX86_BUILTIN_SETPS1,
2229 IX86_BUILTIN_SETPS,
2230 IX86_BUILTIN_CLRPS,
2231 IX86_BUILTIN_SETRPS,
2232 IX86_BUILTIN_LOADPS1,
2233 IX86_BUILTIN_LOADRPS,
2234 IX86_BUILTIN_STOREPS1,
2235 IX86_BUILTIN_STORERPS,
2236
2237 IX86_BUILTIN_MMX_ZERO,
2238
2239 IX86_BUILTIN_MAX
2240 };
2241 \f
2242 /* Define this macro if references to a symbol must be treated
2243 differently depending on something about the variable or
2244 function named by the symbol (such as what section it is in).
2245
2246 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2247 so that we may access it directly in the GOT. */
2248
2249 #define ENCODE_SECTION_INFO(DECL) \
2250 do \
2251 { \
2252 if (flag_pic) \
2253 { \
2254 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2255 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2256 \
2257 if (GET_CODE (rtl) == MEM) \
2258 { \
2259 if (TARGET_DEBUG_ADDR \
2260 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2261 { \
2262 fprintf (stderr, "Encode %s, public = %d\n", \
2263 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2264 TREE_PUBLIC (DECL)); \
2265 } \
2266 \
2267 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2268 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2269 || ! TREE_PUBLIC (DECL)); \
2270 } \
2271 } \
2272 } \
2273 while (0)
2274
2275 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2276 codes once the function is being compiled into assembly code, but
2277 not before. (It is not done before, because in the case of
2278 compiling an inline function, it would lead to multiple PIC
2279 prologues being included in functions which used inline functions
2280 and were compiled to assembly language.) */
2281
2282 #define FINALIZE_PIC \
2283 do \
2284 { \
2285 current_function_uses_pic_offset_table |= profile_flag; \
2286 } \
2287 while (0)
2288
2289 \f
2290 /* Max number of args passed in registers. If this is more than 3, we will
2291 have problems with ebx (register #4), since it is a caller save register and
2292 is also used as the pic register in ELF. So for now, don't allow more than
2293 3 registers to be passed in registers. */
2294
2295 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2296
2297 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2298
2299 \f
2300 /* Specify the machine mode that this machine uses
2301 for the index in the tablejump instruction. */
2302 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2303
2304 /* Define as C expression which evaluates to nonzero if the tablejump
2305 instruction expects the table to contain offsets from the address of the
2306 table.
2307 Do not define this if the table should contain absolute addresses. */
2308 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2309
2310 /* Specify the tree operation to be used to convert reals to integers.
2311 This should be changed to take advantage of fist --wfs ??
2312 */
2313 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2314
2315 /* This is the kind of divide that is easiest to do in the general case. */
2316 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2317
2318 /* Define this as 1 if `char' should by default be signed; else as 0. */
2319 #define DEFAULT_SIGNED_CHAR 1
2320
2321 /* Number of bytes moved into a data cache for a single prefetch operation. */
2322 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2323
2324 /* Number of prefetch operations that can be done in parallel. */
2325 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2326
2327 /* Max number of bytes we can move from memory to memory
2328 in one reasonably fast instruction. */
2329 #define MOVE_MAX 16
2330
2331 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2332 move efficiently, as opposed to MOVE_MAX which is the maximum
2333 number of bytes we can move with a single instruction. */
2334 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2335
2336 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2337 move-instruction pairs, we will do a movstr or libcall instead.
2338 Increasing the value will always make code faster, but eventually
2339 incurs high cost in increased code size.
2340
2341 If you don't define this, a reasonable default is used. */
2342
2343 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2344
2345 /* Define if shifts truncate the shift count
2346 which implies one can omit a sign-extension or zero-extension
2347 of a shift count. */
2348 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2349
2350 /* #define SHIFT_COUNT_TRUNCATED */
2351
2352 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2353 is done just by pretending it is already truncated. */
2354 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2355
2356 /* We assume that the store-condition-codes instructions store 0 for false
2357 and some other value for true. This is the value stored for true. */
2358
2359 #define STORE_FLAG_VALUE 1
2360
2361 /* When a prototype says `char' or `short', really pass an `int'.
2362 (The 386 can't easily push less than an int.) */
2363
2364 #define PROMOTE_PROTOTYPES 1
2365
2366 /* A macro to update M and UNSIGNEDP when an object whose type is
2367 TYPE and which has the specified mode and signedness is to be
2368 stored in a register. This macro is only called when TYPE is a
2369 scalar type.
2370
2371 On i386 it is sometimes useful to promote HImode and QImode
2372 quantities to SImode. The choice depends on target type. */
2373
2374 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2375 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2376 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2377 (MODE) = SImode;
2378
2379 /* Specify the machine mode that pointers have.
2380 After generation of rtl, the compiler makes no further distinction
2381 between pointers and any other objects of this machine mode. */
2382 #define Pmode (TARGET_64BIT ? DImode : SImode)
2383
2384 /* A function address in a call instruction
2385 is a byte address (for indexing purposes)
2386 so give the MEM rtx a byte's mode. */
2387 #define FUNCTION_MODE QImode
2388 \f
2389 /* A part of a C `switch' statement that describes the relative costs
2390 of constant RTL expressions. It must contain `case' labels for
2391 expression codes `const_int', `const', `symbol_ref', `label_ref'
2392 and `const_double'. Each case must ultimately reach a `return'
2393 statement to return the relative cost of the use of that kind of
2394 constant value in an expression. The cost may depend on the
2395 precise value of the constant, which is available for examination
2396 in X, and the rtx code of the expression in which it is contained,
2397 found in OUTER_CODE.
2398
2399 CODE is the expression code--redundant, since it can be obtained
2400 with `GET_CODE (X)'. */
2401
2402 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2403 case CONST_INT: \
2404 case CONST: \
2405 case LABEL_REF: \
2406 case SYMBOL_REF: \
2407 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2408 return 3; \
2409 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2410 return 2; \
2411 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2412 \
2413 case CONST_DOUBLE: \
2414 { \
2415 int code; \
2416 if (GET_MODE (RTX) == VOIDmode) \
2417 return 0; \
2418 \
2419 code = standard_80387_constant_p (RTX); \
2420 return code == 1 ? 1 : \
2421 code == 2 ? 2 : \
2422 3; \
2423 }
2424
2425 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2426 #define TOPLEVEL_COSTS_N_INSNS(N) \
2427 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2428
2429 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2430 This can be used, for example, to indicate how costly a multiply
2431 instruction is. In writing this macro, you can use the construct
2432 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2433 instructions. OUTER_CODE is the code of the expression in which X
2434 is contained.
2435
2436 This macro is optional; do not define it if the default cost
2437 assumptions are adequate for the target machine. */
2438
2439 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2440 case ZERO_EXTEND: \
2441 /* The zero extensions is often completely free on x86_64, so make \
2442 it as cheap as possible. */ \
2443 if (TARGET_64BIT && GET_MODE (X) == DImode \
2444 && GET_MODE (XEXP (X, 0)) == SImode) \
2445 { \
2446 total = 1; goto egress_rtx_costs; \
2447 } \
2448 else \
2449 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2450 ix86_cost->add : ix86_cost->movzx); \
2451 break; \
2452 case SIGN_EXTEND: \
2453 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2454 break; \
2455 case ASHIFT: \
2456 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2457 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2458 { \
2459 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2460 if (value == 1) \
2461 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2462 if ((value == 2 || value == 3) \
2463 && !TARGET_DECOMPOSE_LEA \
2464 && ix86_cost->lea <= ix86_cost->shift_const) \
2465 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2466 } \
2467 /* fall through */ \
2468 \
2469 case ROTATE: \
2470 case ASHIFTRT: \
2471 case LSHIFTRT: \
2472 case ROTATERT: \
2473 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2474 { \
2475 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2476 { \
2477 if (INTVAL (XEXP (X, 1)) > 32) \
2478 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2479 else \
2480 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2481 } \
2482 else \
2483 { \
2484 if (GET_CODE (XEXP (X, 1)) == AND) \
2485 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2486 else \
2487 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2488 } \
2489 } \
2490 else \
2491 { \
2492 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2493 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2494 else \
2495 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2496 } \
2497 break; \
2498 \
2499 case MULT: \
2500 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2501 { \
2502 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2503 int nbits = 0; \
2504 \
2505 while (value != 0) \
2506 { \
2507 nbits++; \
2508 value >>= 1; \
2509 } \
2510 \
2511 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2512 + nbits * ix86_cost->mult_bit); \
2513 } \
2514 else /* This is arbitrary */ \
2515 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2516 + 7 * ix86_cost->mult_bit); \
2517 \
2518 case DIV: \
2519 case UDIV: \
2520 case MOD: \
2521 case UMOD: \
2522 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2523 \
2524 case PLUS: \
2525 if (!TARGET_DECOMPOSE_LEA \
2526 && INTEGRAL_MODE_P (GET_MODE (X)) \
2527 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2528 { \
2529 if (GET_CODE (XEXP (X, 0)) == PLUS \
2530 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2531 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2532 && CONSTANT_P (XEXP (X, 1))) \
2533 { \
2534 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2535 if (val == 2 || val == 4 || val == 8) \
2536 { \
2537 return (COSTS_N_INSNS (ix86_cost->lea) \
2538 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2539 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2540 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2541 } \
2542 } \
2543 else if (GET_CODE (XEXP (X, 0)) == MULT \
2544 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2545 { \
2546 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2547 if (val == 2 || val == 4 || val == 8) \
2548 { \
2549 return (COSTS_N_INSNS (ix86_cost->lea) \
2550 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2551 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2552 } \
2553 } \
2554 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2555 { \
2556 return (COSTS_N_INSNS (ix86_cost->lea) \
2557 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2558 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2559 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2560 } \
2561 } \
2562 \
2563 /* fall through */ \
2564 case AND: \
2565 case IOR: \
2566 case XOR: \
2567 case MINUS: \
2568 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2569 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2570 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2571 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2572 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2573 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2574 \
2575 /* fall through */ \
2576 case NEG: \
2577 case NOT: \
2578 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2579 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2580 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2581 \
2582 egress_rtx_costs: \
2583 break;
2584
2585
2586 /* An expression giving the cost of an addressing mode that contains
2587 ADDRESS. If not defined, the cost is computed from the ADDRESS
2588 expression and the `CONST_COSTS' values.
2589
2590 For most CISC machines, the default cost is a good approximation
2591 of the true cost of the addressing mode. However, on RISC
2592 machines, all instructions normally have the same length and
2593 execution time. Hence all addresses will have equal costs.
2594
2595 In cases where more than one form of an address is known, the form
2596 with the lowest cost will be used. If multiple forms have the
2597 same, lowest, cost, the one that is the most complex will be used.
2598
2599 For example, suppose an address that is equal to the sum of a
2600 register and a constant is used twice in the same basic block.
2601 When this macro is not defined, the address will be computed in a
2602 register and memory references will be indirect through that
2603 register. On machines where the cost of the addressing mode
2604 containing the sum is no higher than that of a simple indirect
2605 reference, this will produce an additional instruction and
2606 possibly require an additional register. Proper specification of
2607 this macro eliminates this overhead for such machines.
2608
2609 Similar use of this macro is made in strength reduction of loops.
2610
2611 ADDRESS need not be valid as an address. In such a case, the cost
2612 is not relevant and can be any value; invalid addresses need not be
2613 assigned a different cost.
2614
2615 On machines where an address involving more than one register is as
2616 cheap as an address computation involving only one register,
2617 defining `ADDRESS_COST' to reflect this can cause two registers to
2618 be live over a region of code where only one would have been if
2619 `ADDRESS_COST' were not defined in that manner. This effect should
2620 be considered in the definition of this macro. Equivalent costs
2621 should probably only be given to addresses with different numbers
2622 of registers on machines with lots of registers.
2623
2624 This macro will normally either not be defined or be defined as a
2625 constant.
2626
2627 For i386, it is better to use a complex address than let gcc copy
2628 the address into a reg and make a new pseudo. But not if the address
2629 requires to two regs - that would mean more pseudos with longer
2630 lifetimes. */
2631
2632 #define ADDRESS_COST(RTX) \
2633 ix86_address_cost (RTX)
2634
2635 /* A C expression for the cost of moving data from a register in class FROM to
2636 one in class TO. The classes are expressed using the enumeration values
2637 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2638 interpreted relative to that.
2639
2640 It is not required that the cost always equal 2 when FROM is the same as TO;
2641 on some machines it is expensive to move between registers if they are not
2642 general registers. */
2643
2644 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2645 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2646
2647 /* A C expression for the cost of moving data of mode M between a
2648 register and memory. A value of 2 is the default; this cost is
2649 relative to those in `REGISTER_MOVE_COST'.
2650
2651 If moving between registers and memory is more expensive than
2652 between two registers, you should define this macro to express the
2653 relative cost. */
2654
2655 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2656 ix86_memory_move_cost (MODE, CLASS, IN)
2657
2658 /* A C expression for the cost of a branch instruction. A value of 1
2659 is the default; other values are interpreted relative to that. */
2660
2661 #define BRANCH_COST ix86_branch_cost
2662
2663 /* Define this macro as a C expression which is nonzero if accessing
2664 less than a word of memory (i.e. a `char' or a `short') is no
2665 faster than accessing a word of memory, i.e., if such access
2666 require more than one instruction or if there is no difference in
2667 cost between byte and (aligned) word loads.
2668
2669 When this macro is not defined, the compiler will access a field by
2670 finding the smallest containing object; when it is defined, a
2671 fullword load will be used if alignment permits. Unless bytes
2672 accesses are faster than word accesses, using word accesses is
2673 preferable since it may eliminate subsequent memory access if
2674 subsequent accesses occur to other fields in the same word of the
2675 structure, but to different bytes. */
2676
2677 #define SLOW_BYTE_ACCESS 0
2678
2679 /* Nonzero if access to memory by shorts is slow and undesirable. */
2680 #define SLOW_SHORT_ACCESS 0
2681
2682 /* Define this macro if zero-extension (of a `char' or `short' to an
2683 `int') can be done faster if the destination is a register that is
2684 known to be zero.
2685
2686 If you define this macro, you must have instruction patterns that
2687 recognize RTL structures like this:
2688
2689 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2690
2691 and likewise for `HImode'. */
2692
2693 /* #define SLOW_ZERO_EXTEND */
2694
2695 /* Define this macro to be the value 1 if unaligned accesses have a
2696 cost many times greater than aligned accesses, for example if they
2697 are emulated in a trap handler.
2698
2699 When this macro is non-zero, the compiler will act as if
2700 `STRICT_ALIGNMENT' were non-zero when generating code for block
2701 moves. This can cause significantly more instructions to be
2702 produced. Therefore, do not set this macro non-zero if unaligned
2703 accesses only add a cycle or two to the time for a memory access.
2704
2705 If the value of this macro is always zero, it need not be defined. */
2706
2707 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2708
2709 /* Define this macro to inhibit strength reduction of memory
2710 addresses. (On some machines, such strength reduction seems to do
2711 harm rather than good.) */
2712
2713 /* #define DONT_REDUCE_ADDR */
2714
2715 /* Define this macro if it is as good or better to call a constant
2716 function address than to call an address kept in a register.
2717
2718 Desirable on the 386 because a CALL with a constant address is
2719 faster than one with a register address. */
2720
2721 #define NO_FUNCTION_CSE
2722
2723 /* Define this macro if it is as good or better for a function to call
2724 itself with an explicit address than to call an address kept in a
2725 register. */
2726
2727 #define NO_RECURSIVE_FUNCTION_CSE
2728 \f
2729 /* Add any extra modes needed to represent the condition code.
2730
2731 For the i386, we need separate modes when floating-point
2732 equality comparisons are being done.
2733
2734 Add CCNO to indicate comparisons against zero that requires
2735 Overflow flag to be unset. Sign bit test is used instead and
2736 thus can be used to form "a&b>0" type of tests.
2737
2738 Add CCGC to indicate comparisons agains zero that allows
2739 unspecified garbage in the Carry flag. This mode is used
2740 by inc/dec instructions.
2741
2742 Add CCGOC to indicate comparisons agains zero that allows
2743 unspecified garbage in the Carry and Overflow flag. This
2744 mode is used to simulate comparisons of (a-b) and (a+b)
2745 against zero using sub/cmp/add operations.
2746
2747 Add CCZ to indicate that only the Zero flag is valid. */
2748
2749 #define EXTRA_CC_MODES \
2750 CC(CCGCmode, "CCGC") \
2751 CC(CCGOCmode, "CCGOC") \
2752 CC(CCNOmode, "CCNO") \
2753 CC(CCZmode, "CCZ") \
2754 CC(CCFPmode, "CCFP") \
2755 CC(CCFPUmode, "CCFPU")
2756
2757 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2758 return the mode to be used for the comparison.
2759
2760 For floating-point equality comparisons, CCFPEQmode should be used.
2761 VOIDmode should be used in all other cases.
2762
2763 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2764 possible, to allow for more combinations. */
2765
2766 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2767
2768 /* Return non-zero if MODE implies a floating point inequality can be
2769 reversed. */
2770
2771 #define REVERSIBLE_CC_MODE(MODE) 1
2772
2773 /* A C expression whose value is reversed condition code of the CODE for
2774 comparison done in CC_MODE mode. */
2775 #define REVERSE_CONDITION(CODE, MODE) \
2776 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2777 : reverse_condition_maybe_unordered (CODE))
2778
2779 \f
2780 /* Control the assembler format that we output, to the extent
2781 this does not vary between assemblers. */
2782
2783 /* How to refer to registers in assembler output.
2784 This sequence is indexed by compiler's hard-register-number (see above). */
2785
2786 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2787 For non floating point regs, the following are the HImode names.
2788
2789 For float regs, the stack top is sometimes referred to as "%st(0)"
2790 instead of just "%st". PRINT_REG handles this with the "y" code. */
2791
2792 #undef HI_REGISTER_NAMES
2793 #define HI_REGISTER_NAMES \
2794 {"ax","dx","cx","bx","si","di","bp","sp", \
2795 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2796 "flags","fpsr", "dirflag", "frame", \
2797 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2798 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2799 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2800 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2801
2802 #define REGISTER_NAMES HI_REGISTER_NAMES
2803
2804 /* Table of additional register names to use in user input. */
2805
2806 #define ADDITIONAL_REGISTER_NAMES \
2807 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2808 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2809 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2810 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2811 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2812 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2813 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2814 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2815
2816 /* Note we are omitting these since currently I don't know how
2817 to get gcc to use these, since they want the same but different
2818 number as al, and ax.
2819 */
2820
2821 #define QI_REGISTER_NAMES \
2822 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2823
2824 /* These parallel the array above, and can be used to access bits 8:15
2825 of regs 0 through 3. */
2826
2827 #define QI_HIGH_REGISTER_NAMES \
2828 {"ah", "dh", "ch", "bh", }
2829
2830 /* How to renumber registers for dbx and gdb. */
2831
2832 #define DBX_REGISTER_NUMBER(n) \
2833 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2834
2835 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2836 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2837 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2838
2839 /* Before the prologue, RA is at 0(%esp). */
2840 #define INCOMING_RETURN_ADDR_RTX \
2841 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2842
2843 /* After the prologue, RA is at -4(AP) in the current frame. */
2844 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2845 ((COUNT) == 0 \
2846 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2847 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2848
2849 /* PC is dbx register 8; let's use that column for RA. */
2850 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2851
2852 /* Before the prologue, the top of the frame is at 4(%esp). */
2853 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2854
2855 /* Describe how we implement __builtin_eh_return. */
2856 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2857 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2858
2859
2860 /* Select a format to encode pointers in exception handling data. CODE
2861 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2862 true if the symbol may be affected by dynamic relocations.
2863
2864 ??? All x86 object file formats are capable of representing this.
2865 After all, the relocation needed is the same as for the call insn.
2866 Whether or not a particular assembler allows us to enter such, I
2867 guess we'll have to see. */
2868 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2869 (flag_pic \
2870 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2871 : DW_EH_PE_absptr)
2872
2873 /* This is how to output the definition of a user-level label named NAME,
2874 such as the label on a static function or variable NAME. */
2875
2876 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2877 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2878
2879 /* Store in OUTPUT a string (made with alloca) containing
2880 an assembler-name for a local static variable named NAME.
2881 LABELNO is an integer which is different for each call. */
2882
2883 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2884 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2885 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2886
2887 /* This is how to output an insn to push a register on the stack.
2888 It need not be very fast code. */
2889
2890 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2891 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2892
2893 /* This is how to output an insn to pop a register from the stack.
2894 It need not be very fast code. */
2895
2896 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2897 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2898
2899 /* This is how to output an element of a case-vector that is absolute. */
2900
2901 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2902 ix86_output_addr_vec_elt (FILE, VALUE)
2903
2904 /* This is how to output an element of a case-vector that is relative. */
2905
2906 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2907 ix86_output_addr_diff_elt (FILE, VALUE, REL)
2908
2909 /* Under some conditions we need jump tables in the text section, because
2910 the assembler cannot handle label differences between sections. */
2911
2912 #define JUMP_TABLES_IN_TEXT_SECTION \
2913 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2914
2915 /* A C statement that outputs an address constant appropriate to
2916 for DWARF debugging. */
2917
2918 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2919 i386_dwarf_output_addr_const((FILE),(X))
2920
2921 /* Either simplify a location expression, or return the original. */
2922
2923 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2924 i386_simplify_dwarf_addr(X)
2925 \f
2926 /* Print operand X (an rtx) in assembler syntax to file FILE.
2927 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2928 Effect of various CODE letters is described in i386.c near
2929 print_operand function. */
2930
2931 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2932 ((CODE) == '*' || (CODE) == '+')
2933
2934 /* Print the name of a register based on its machine mode and number.
2935 If CODE is 'w', pretend the mode is HImode.
2936 If CODE is 'b', pretend the mode is QImode.
2937 If CODE is 'k', pretend the mode is SImode.
2938 If CODE is 'q', pretend the mode is DImode.
2939 If CODE is 'h', pretend the reg is the `high' byte register.
2940 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2941
2942 #define PRINT_REG(X, CODE, FILE) \
2943 print_reg (X, CODE, FILE)
2944
2945 #define PRINT_OPERAND(FILE, X, CODE) \
2946 print_operand (FILE, X, CODE)
2947
2948 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2949 print_operand_address (FILE, ADDR)
2950
2951 /* Print the name of a register for based on its machine mode and number.
2952 This macro is used to print debugging output.
2953 This macro is different from PRINT_REG in that it may be used in
2954 programs that are not linked with aux-output.o. */
2955
2956 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2957 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2958 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2959 fprintf (FILE, "%d ", REGNO (X)); \
2960 if (REGNO (X) == FLAGS_REG) \
2961 { fputs ("flags", FILE); break; } \
2962 if (REGNO (X) == DIRFLAG_REG) \
2963 { fputs ("dirflag", FILE); break; } \
2964 if (REGNO (X) == FPSR_REG) \
2965 { fputs ("fpsr", FILE); break; } \
2966 if (REGNO (X) == ARG_POINTER_REGNUM) \
2967 { fputs ("argp", FILE); break; } \
2968 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2969 { fputs ("frame", FILE); break; } \
2970 if (STACK_TOP_P (X)) \
2971 { fputs ("st(0)", FILE); break; } \
2972 if (FP_REG_P (X)) \
2973 { fputs (hi_name[REGNO(X)], FILE); break; } \
2974 if (REX_INT_REG_P (X)) \
2975 { \
2976 switch (GET_MODE_SIZE (GET_MODE (X))) \
2977 { \
2978 default: \
2979 case 8: \
2980 fprintf (FILE, "r%i", REGNO (X) \
2981 - FIRST_REX_INT_REG + 8); \
2982 break; \
2983 case 4: \
2984 fprintf (FILE, "r%id", REGNO (X) \
2985 - FIRST_REX_INT_REG + 8); \
2986 break; \
2987 case 2: \
2988 fprintf (FILE, "r%iw", REGNO (X) \
2989 - FIRST_REX_INT_REG + 8); \
2990 break; \
2991 case 1: \
2992 fprintf (FILE, "r%ib", REGNO (X) \
2993 - FIRST_REX_INT_REG + 8); \
2994 break; \
2995 } \
2996 break; \
2997 } \
2998 switch (GET_MODE_SIZE (GET_MODE (X))) \
2999 { \
3000 case 8: \
3001 fputs ("r", FILE); \
3002 fputs (hi_name[REGNO (X)], FILE); \
3003 break; \
3004 default: \
3005 fputs ("e", FILE); \
3006 case 2: \
3007 fputs (hi_name[REGNO (X)], FILE); \
3008 break; \
3009 case 1: \
3010 fputs (qi_name[REGNO (X)], FILE); \
3011 break; \
3012 } \
3013 } while (0)
3014
3015 /* a letter which is not needed by the normal asm syntax, which
3016 we can use for operand syntax in the extended asm */
3017
3018 #define ASM_OPERAND_LETTER '#'
3019 #define RET return ""
3020 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3021 \f
3022 /* Define the codes that are matched by predicates in i386.c. */
3023
3024 #define PREDICATE_CODES \
3025 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3026 SYMBOL_REF, LABEL_REF, CONST}}, \
3027 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3028 SYMBOL_REF, LABEL_REF, CONST}}, \
3029 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3030 SYMBOL_REF, LABEL_REF, CONST}}, \
3031 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3032 SYMBOL_REF, LABEL_REF, CONST}}, \
3033 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3034 SYMBOL_REF, LABEL_REF, CONST}}, \
3035 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3036 SYMBOL_REF, LABEL_REF, CONST}}, \
3037 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3038 SYMBOL_REF, LABEL_REF}}, \
3039 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3040 {"const_int_1_operand", {CONST_INT}}, \
3041 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3042 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3043 LABEL_REF, SUBREG, REG, MEM}}, \
3044 {"pic_symbolic_operand", {CONST}}, \
3045 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3046 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3047 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3048 {"const1_operand", {CONST_INT}}, \
3049 {"const248_operand", {CONST_INT}}, \
3050 {"incdec_operand", {CONST_INT}}, \
3051 {"mmx_reg_operand", {REG}}, \
3052 {"reg_no_sp_operand", {SUBREG, REG}}, \
3053 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3054 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3055 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3056 {"q_regs_operand", {SUBREG, REG}}, \
3057 {"non_q_regs_operand", {SUBREG, REG}}, \
3058 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3059 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3060 GE, UNGE, LTGT, UNEQ}}, \
3061 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3062 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3063 }}, \
3064 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3065 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3066 UNGE, UNGT, LTGT, UNEQ }}, \
3067 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3068 {"ext_register_operand", {SUBREG, REG}}, \
3069 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3070 {"mult_operator", {MULT}}, \
3071 {"div_operator", {DIV}}, \
3072 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3073 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3074 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3075 LSHIFTRT, ROTATERT}}, \
3076 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3077 {"memory_displacement_operand", {MEM}}, \
3078 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3079 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3080 {"long_memory_operand", {MEM}},
3081
3082 /* A list of predicates that do special things with modes, and so
3083 should not elicit warnings for VOIDmode match_operand. */
3084
3085 #define SPECIAL_MODE_PREDICATES \
3086 "ext_register_operand",
3087 \f
3088 /* CM_32 is used by 32bit ABI
3089 CM_SMALL is small model assuming that all code and data fits in the first
3090 31bits of address space.
3091 CM_KERNEL is model assuming that all code and data fits in the negative
3092 31bits of address space.
3093 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3094 space. Size of data is unlimited.
3095 CM_LARGE is model making no assumptions about size of particular sections.
3096
3097 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3098 tables first in 31bits of address space.
3099 */
3100 enum cmodel {
3101 CM_32,
3102 CM_SMALL,
3103 CM_KERNEL,
3104 CM_MEDIUM,
3105 CM_LARGE,
3106 CM_SMALL_PIC
3107 };
3108
3109 /* Size of the RED_ZONE area. */
3110 #define RED_ZONE_SIZE 128
3111 /* Reserved area of the red zone for temporaries. */
3112 #define RED_ZONE_RESERVE 8
3113 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3114
3115 enum asm_dialect {
3116 ASM_ATT,
3117 ASM_INTEL
3118 };
3119 extern const char *ix86_asm_string;
3120 extern enum cmodel ix86_asm_dialect;
3121 /* Valud of -mcmodel specified by user. */
3122 extern const char *ix86_cmodel_string;
3123 extern enum cmodel ix86_cmodel;
3124 \f
3125 /* Variables in i386.c */
3126 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3127 extern const char *ix86_arch_string; /* for -march=<xxx> */
3128 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3129 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3130 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3131 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3132 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3133 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3134 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3135 extern int ix86_regparm; /* ix86_regparm_string as a number */
3136 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3137 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3138 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3139 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3140 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
3141 \f
3142 /* To properly truncate FP values into integers, we need to set i387 control
3143 word. We can't emit proper mode switching code before reload, as spills
3144 generated by reload may truncate values incorrectly, but we still can avoid
3145 redundant computation of new control word by the mode switching pass.
3146 The fldcw instructions are still emitted redundantly, but this is probably
3147 not going to be noticeable problem, as most CPUs do have fast path for
3148 the sequence.
3149
3150 The machinery is to emit simple truncation instructions and split them
3151 before reload to instructions having USEs of two memory locations that
3152 are filled by this code to old and new control word.
3153
3154 Post-reload pass may be later used to eliminate the redundant fildcw if
3155 needed. */
3156
3157 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3158
3159 /* Define this macro if the port needs extra instructions inserted
3160 for mode switching in an optimizing compilation. */
3161
3162 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3163
3164 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3165 initializer for an array of integers. Each initializer element N
3166 refers to an entity that needs mode switching, and specifies the
3167 number of different modes that might need to be set for this
3168 entity. The position of the initializer in the initializer -
3169 starting counting at zero - determines the integer that is used to
3170 refer to the mode-switched entity in question. */
3171
3172 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3173
3174 /* ENTITY is an integer specifying a mode-switched entity. If
3175 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3176 return an integer value not larger than the corresponding element
3177 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3178 must be switched into prior to the execution of INSN. */
3179
3180 #define MODE_NEEDED(ENTITY, I) \
3181 (GET_CODE (I) == CALL_INSN \
3182 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3183 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3184 ? FP_CW_UNINITIALIZED \
3185 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3186 ? FP_CW_ANY \
3187 : FP_CW_STORED)
3188
3189 /* This macro specifies the order in which modes for ENTITY are
3190 processed. 0 is the highest priority. */
3191
3192 #define MODE_PRIORITY_TO_MODE(ENTITY, N) N
3193
3194 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3195 is the set of hard registers live at the point where the insn(s)
3196 are to be inserted. */
3197
3198 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3199 (MODE == FP_CW_STORED \
3200 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3201 assign_386_stack_local (HImode, 2)), 0\
3202 : 0)
3203 \f
3204 /* Avoid renaming of stack registers, as doing so in combination with
3205 scheduling just increases amount of live registers at time and in
3206 the turn amount of fxch instructions needed.
3207
3208 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3209
3210 #define HARD_REGNO_RENAME_OK(src,target) \
3211 ((src) < FIRST_STACK_REG || (src) > LAST_STACK_REG)
3212
3213 \f
3214 /*
3215 Local variables:
3216 version-control: t
3217 End:
3218 */
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