gcc/testsuite/gcc.target/aarch64/vect-vcvt.c

   1 /* { dg-do run } */
   2 /* { dg-options "-O3 --save-temps -ffast-math" } */
   3
   4 #include <arm_neon.h>
   5
   6 extern void abort (void);
   7 extern double fabs (double);
   8
   9 #define NUM_TESTS 8
  10 #define DELTA 0.000001
  11
  12 float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f,
  13                      200.0f, -800.0f, -13.0f, -0.5f};
  14 double input_f64[] = {0.1, -0.1, 0.4, 10.3,
  15                       200.0, -800.0, -13.0, -0.5};
  16
  17 #define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D)                          \
  18 int                                                                     \
  19 test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t (void)          \
  20 {                                                                       \
  21   int ret = 1;                                                          \
  22   int i = 0;                                                            \
  23   int nlanes = LANES;                                                   \
  24   U##int##WIDTH##_t expected_out[NUM_TESTS];                            \
  25   U##int##WIDTH##_t actual_out[NUM_TESTS];                              \
  26                                                                         \
  27   for (i = 0; i < NUM_TESTS; i++)                                       \
  28     {                                                                   \
  29       expected_out[i]                                                   \
  30         = vcvt##SUFFIX##D##_##S##WIDTH##_f##WIDTH (input_f##WIDTH[i]);  \
  31       /* Don't vectorize this.  */                                      \
  32       asm volatile ("" : : : "memory");                                 \
  33     }                                                                   \
  34                                                                         \
  35   for (i = 0; i < NUM_TESTS; i+=nlanes)                                 \
  36     {                                                                   \
  37       U##int##WIDTH##x##LANES##_t out =                                 \
  38         vcvt##SUFFIX##Q##_##S##WIDTH##_f##WIDTH                         \
  39                 (vld1##Q##_f##WIDTH (input_f##WIDTH + i));              \
  40       vst1##Q##_##S##WIDTH (actual_out + i, out);                       \
  41     }                                                                   \
  42                                                                         \
  43   for (i = 0; i < NUM_TESTS; i++)                                       \
  44     ret &= fabs (expected_out[i] - actual_out[i]) < DELTA;              \
  45                                                                         \
  46   return ret;                                                           \
  47 }                                                                       \
  48
  49
  50 #define BUILD_VARIANTS(SUFFIX)                  \
  51 TEST (SUFFIX,  , 32, 2, s, ,s)                  \
  52 TEST (SUFFIX, q, 32, 4, s, ,s)                  \
  53 TEST (SUFFIX, q, 64, 2, s, ,d)                  \
  54 TEST (SUFFIX,  , 32, 2, u,u,s)                  \
  55 TEST (SUFFIX, q, 32, 4, u,u,s)                  \
  56 TEST (SUFFIX, q, 64, 2, u,u,d)                  \
  57
  58 BUILD_VARIANTS ( )
  59 /* { dg-final { scan-assembler "fcvtzs\\t(w|s)\[0-9\]+, s\[0-9\]+" } } */
  60 /* { dg-final { scan-assembler "fcvtzs\\t(x|d)\[0-9\]+, d\[0-9\]+" } } */
  61 /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  62 /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  63 /* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  64 /* { dg-final { scan-assembler "fcvtzu\\t(w|s)\[0-9\]+, s\[0-9\]+" } } */
  65 /* { dg-final { scan-assembler "fcvtzu\\t(x|d)\[0-9\]+, d\[0-9\]+" } } */
  66 /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  67 /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  68 /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  69 BUILD_VARIANTS (a)
  70 /* { dg-final { scan-assembler "fcvtas\\tw\[0-9\]+, s\[0-9\]+" } } */
  71 /* { dg-final { scan-assembler "fcvtas\\tx\[0-9\]+, d\[0-9\]+" } } */
  72 /* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  73 /* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  74 /* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  75 /* { dg-final { scan-assembler "fcvtau\\tw\[0-9\]+, s\[0-9\]+" } } */
  76 /* { dg-final { scan-assembler "fcvtau\\tx\[0-9\]+, d\[0-9\]+" } } */
  77 /* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  78 /* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  79 /* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  80 BUILD_VARIANTS (m)
  81 /* { dg-final { scan-assembler "fcvtms\\tw\[0-9\]+, s\[0-9\]+" } } */
  82 /* { dg-final { scan-assembler "fcvtms\\tx\[0-9\]+, d\[0-9\]+" } } */
  83 /* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  84 /* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  85 /* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  86 /* { dg-final { scan-assembler "fcvtmu\\tw\[0-9\]+, s\[0-9\]+" } } */
  87 /* { dg-final { scan-assembler "fcvtmu\\tx\[0-9\]+, d\[0-9\]+" } } */
  88 /* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  89 /* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  90 /* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  91 BUILD_VARIANTS (n)
  92 /* { dg-final { scan-assembler "fcvtns\\tw\[0-9\]+, s\[0-9\]+" } } */
  93 /* { dg-final { scan-assembler "fcvtns\\tx\[0-9\]+, d\[0-9\]+" } } */
  94 /* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
  95 /* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
  96 /* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
  97 /* { dg-final { scan-assembler "fcvtnu\\tw\[0-9\]+, s\[0-9\]+" } } */
  98 /* { dg-final { scan-assembler "fcvtnu\\tx\[0-9\]+, d\[0-9\]+" } } */
  99 /* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
 100 /* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
 101 /* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
 102 BUILD_VARIANTS (p)
 103 /* { dg-final { scan-assembler "fcvtps\\tw\[0-9\]+, s\[0-9\]+" } } */
 104 /* { dg-final { scan-assembler "fcvtps\\tx\[0-9\]+, d\[0-9\]+" } } */
 105 /* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
 106 /* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
 107 /* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
 108 /* { dg-final { scan-assembler "fcvtpu\\tw\[0-9\]+, s\[0-9\]+" } } */
 109 /* { dg-final { scan-assembler "fcvtpu\\tx\[0-9\]+, d\[0-9\]+" } } */
 110 /* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
 111 /* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
 112 /* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
 113
 114 #undef TEST
 115 #define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D)                          \
 116 {                                                                       \
 117   if (!test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t ())      \
 118     abort ();                                                           \
 119 }
 120
 121 int
 122 main (int argc, char **argv)
 123 {
 124   BUILD_VARIANTS ( )
 125   BUILD_VARIANTS (a)
 126   BUILD_VARIANTS (m)
 127   BUILD_VARIANTS (n)
 128   BUILD_VARIANTS (p)
 129   return 0;
 130 }
 131