[AArch64/arm] PR testsuite/85326 Avoid C++ tests when C++ compiler not present
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / vect-fp.c
blobaf0c524b466caf2f1c82580bd50ac92da78a28ce
2 /* { dg-do run } */
3 /* { dg-options "-O3" } */
5 extern void abort (void);
7 #include "vect-fp.x"
10 #define DEFN_SETV(type) \
11 void set_vector_##type (pR##type a, type n) \
12 { \
13 int i; \
14 for (i=0; i<16; i++) \
15 a[i] = n; \
18 #define DEFN_CHECKV(type) \
19 void check_vector_##type (pR##type a, pR##type vec) \
20 { \
21 int i; \
22 for (i=0; i<16; i++) \
23 if (a[i] != vec[i]) \
24 abort (); \
27 #define TEST2(fname, type) \
28 set_vector_##type (a##type, 0.0); \
29 fname##_##type (a##type, b##type); \
30 check_vector_##type (a##type, fname##_##type##_vector);
32 #define TEST3(fname, type) \
33 set_vector_##type (a##type, 0.0); \
34 fname##_##type (a##type, b##type, c##type); \
35 check_vector_##type (a##type, fname##_##type##_vector);
37 #define TEST(fname, N) \
38 TEST##N(fname, F32); \
39 TEST##N(fname, F64);
41 DEFN_SETV (F32)
42 DEFN_SETV (F64)
44 DEFN_CHECKV (F32)
45 DEFN_CHECKV (F64)
47 int main (void)
49 F32 aF32[16];
50 F32 bF32[16];
51 F32 cF32[16];
53 F64 aF64[16];
54 F64 bF64[16];
55 F64 cF64[16];
56 int i;
58 F32 add_F32_vector[] = { 3.0f, 5.0f, 7.0f, 9.0f, 11.0f,
59 13.0f, 15.0f, 17.0f, 19.0f,
60 21.0f, 23.0f, 25.0f, 27.0f,
61 29.0f, 31.0f, 33.0f };
63 F64 add_F64_vector[] = { 3.0, 5.0, 7.0, 9.0, 11.0,
64 13.0, 15.0, 17.0, 19.0,
65 21.0, 23.0, 25.0, 27.0,
66 29.0, 31.0, 33.0 };
68 F32 sub_F32_vector[] = { -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
69 -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
70 -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
71 -1.0f };
73 F64 sub_F64_vector[] = { -1.0, -1.0, -1.0, -1.0, -1.0,
74 -1.0, -1.0, -1.0, -1.0, -1.0,
75 -1.0, -1.0, -1.0, -1.0, -1.0,
76 -1.0 };
78 F32 mul_F32_vector[] = { 2.0f, 6.0f, 12.0f, 20.0f, 30.0f,
79 42.0f, 56.0f, 72.0f, 90.0f,
80 110.0f, 132.0f, 156.0f, 182.0f,
81 210.0f, 240.0f, 272.0f };
83 F64 mul_F64_vector[] = { 2.0, 6.0, 12.0, 20.0, 30.0,
84 42.0, 56.0, 72.0, 90.0,
85 110.0, 132.0, 156.0, 182.0,
86 210.0, 240.0, 272.0 };
88 F32 div_F32_vector[] = { 0.5f, (float)(2.0/3.0), 0.75f, 0.8f,
89 (float)(5.0/6.0), (float)(6.0/7.0), 0.875000f,
90 (float)(8.0/9.0), 0.900000f, (float)(10.0/11.0),
91 (float)(11.0/12.0), (float)(12.0/13.0),
92 (float)(13.0/14.0), (float)(14.0/15.0), 0.937500f,
93 (float)(16.0/17.0) };
95 F64 div_F64_vector[] = { 0.5, (2.0/3.0), 0.75, 0.8, (5.0/6.0),
96 (6.0/7.0), 0.875000, (8.0/9.0), 0.900000,
97 (10.0/11.0), (11.0/12.0), (12.0/13.0), (13.0/14.0),
98 (14.0/15.0), 0.937500, (16.0/17.0) };
100 F32 neg_F32_vector[] = { -1.0f, -2.0f, -3.0f, -4.0f,
101 -5.0f, -6.0f, -7.0f, -8.0f,
102 -9.0f, -10.0f, -11.0f, -12.0f,
103 -13.0f, -14.0f, -15.0f, -16.0f };
105 F64 neg_F64_vector[] = { -1.0, -2.0, -3.0, -4.0,
106 -5.0, -6.0, -7.0, -8.0,
107 -9.0, -10.0, -11.0, -12.0,
108 -13.0, -14.0, -15.0, -16.0 };
110 F32 abs_F32_vector[] = { 1.0f, 2.0f, 3.0f, 4.0f,
111 5.0f, 6.0f, 7.0f, 8.0f,
112 9.0f, 10.0f, 11.0f, 12.0f,
113 13.0f, 14.0f, 15.0f, 16.0f };
115 F64 abs_F64_vector[] = { 1.0, 2.0, 3.0, 4.0,
116 5.0, 6.0, 7.0, 8.0,
117 9.0, 10.0, 11.0, 12.0,
118 13.0, 14.0, 15.0, 16.0 };
120 F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
121 1.0f, 1.0f, 1.0f, 1.0f,
122 1.0f, 1.0f, 1.0f, 1.0f,
123 1.0f, 1.0f, 1.0f, 1.0f };
125 F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
126 1.0, 1.0, 1.0, 1.0,
127 1.0, 1.0, 1.0, 1.0,
128 1.0, 1.0, 1.0, 1.0 };
130 /* Setup input vectors. */
131 for (i=1; i<=16; i++)
133 bF32[i-1] = (float)i;
134 cF32[i-1] = (float)(i+1);
135 bF64[i-1] = (double)i;
136 cF64[i-1] = (double)(i+1);
139 TEST (add, 3);
140 TEST (sub, 3);
141 TEST (mul, 3);
142 TEST (div, 3);
143 TEST (neg, 2);
144 TEST (abs, 2);
145 TEST (fabd, 3);
147 return 0;