2 /* { dg-options "-O2 -fno-inline -save-temps" } */
6 #define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
7 #define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
9 typedef unsigned long long int UInt64x1
;
10 typedef long long int Int64x1
;
11 typedef unsigned int UInt32x1
;
15 test_lshift_left_sisd_di (UInt64x1 b
, UInt64x1 c
)
26 /* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
27 /* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
30 test_lshift_left_sisd_si (UInt32x1 b
, UInt32x1 c
)
41 /* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
42 /* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */
45 test_lshift_right_sisd_di (UInt64x1 b
, UInt64x1 c
)
56 /* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
57 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
58 /* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
61 test_lshift_right_sisd_si (UInt32x1 b
, UInt32x1 c
)
72 /* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
73 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
74 /* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
77 test_ashift_right_sisd_di (Int64x1 b
, Int64x1 c
)
88 /* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
89 /* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
90 /* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
93 test_ashift_right_sisd_si (Int32x1 b
, Int32x1 c
)
104 /* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
105 /* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */
106 /* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
109 /* The following are to make sure if the integer instructions lsl/lsr/asr are
110 generated in non-vector scenarios */
113 test_lshift_left_int_di (UInt64x1 b
, UInt64x1 c
)
121 /* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
122 /* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
125 test_lshift_left_int_si (UInt32x1 b
, UInt32x1 c
)
133 /* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
134 /* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
137 test_lshift_right_int_di (UInt64x1 b
, UInt64x1 c
)
145 /* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
146 /* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
149 test_lshift_right_int_si (UInt32x1 b
, UInt32x1 c
)
157 /* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
158 /* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
161 test_ashift_right_int_di (Int64x1 b
, Int64x1 c
)
169 /* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
170 /* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
173 test_ashift_right_int_si (Int32x1 b
, Int32x1 c
)
181 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
182 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
184 #define CHECK(var,val) \
192 UInt64x1 x
= 0xC01dDeadBeefFaceull
;
193 UInt32x1 y
= 0xDeadBeef;
198 x
= test_lshift_left_sisd_di (x
, 8);
199 CHECK (x
, 0xdeadbeefface0000ull
);
200 x
= test_lshift_right_int_di (x
, 8);
201 CHECK (x
, 0x0000deadbeeffaceull
);
202 x
= test_lshift_right_sisd_di (x
, 8);
203 CHECK (x
, 0x00000000deadbeefull
);
204 x
= test_lshift_left_int_di (x
, 8);
205 CHECK (x
, 0x0000deadbeef0000ull
);
207 x
= test_ashift_right_int_di (x
, 8);
208 CHECK (x
, 0xffffffff21524110ull
);
209 x
= test_ashift_right_sisd_di (x
, 8);
210 CHECK (x
, 0xffffffffffff2152ull
);
212 y
= test_lshift_left_sisd_si (y
, 4);
213 CHECK (y
, 0xadbeef00);
214 y
= test_lshift_right_int_si (y
, 4);
215 CHECK (y
, 0x00adbeef);
216 y
= test_lshift_right_sisd_si (y
, 4);
217 CHECK (y
, 0x0000adbe);
218 y
= test_lshift_left_int_si (y
, 4);
219 CHECK (y
, 0x00adbe00);
221 y
= test_ashift_right_int_si (y
, 4);
222 CHECK (y
, 0xffff5241);
223 y
= test_ashift_right_sisd_si (y
, 4);
224 CHECK (y
, 0xffffff52);