1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* External variables defined in xtensa.c. */
27 extern unsigned xtensa_current_frame_size
;
29 /* Macros used in the machine description to select various Xtensa
30 configuration options. */
31 #ifndef XCHAL_HAVE_MUL32_HIGH
32 #define XCHAL_HAVE_MUL32_HIGH 0
34 #ifndef XCHAL_HAVE_RELEASE_SYNC
35 #define XCHAL_HAVE_RELEASE_SYNC 0
37 #ifndef XCHAL_HAVE_S32C1I
38 #define XCHAL_HAVE_S32C1I 0
40 #ifndef XCHAL_HAVE_THREADPTR
41 #define XCHAL_HAVE_THREADPTR 0
43 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
44 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
45 #define TARGET_MAC16 XCHAL_HAVE_MAC16
46 #define TARGET_MUL16 XCHAL_HAVE_MUL16
47 #define TARGET_MUL32 XCHAL_HAVE_MUL32
48 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
49 #define TARGET_DIV32 XCHAL_HAVE_DIV32
50 #define TARGET_NSA XCHAL_HAVE_NSA
51 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
52 #define TARGET_SEXT XCHAL_HAVE_SEXT
53 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
54 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
55 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
56 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
57 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
58 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
59 #define TARGET_ABS XCHAL_HAVE_ABS
60 #define TARGET_ADDX XCHAL_HAVE_ADDX
61 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
62 #define TARGET_S32C1I XCHAL_HAVE_S32C1I
63 #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS
64 #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR
66 #define TARGET_DEFAULT \
67 ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \
68 MASK_SERIALIZE_VOLATILE)
75 /* Target CPU builtins. */
76 #define TARGET_CPU_CPP_BUILTINS() \
78 builtin_assert ("cpu=xtensa"); \
79 builtin_assert ("machine=xtensa"); \
80 builtin_define ("__xtensa__"); \
81 builtin_define ("__XTENSA__"); \
82 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
83 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
84 if (!TARGET_HARD_FLOAT) \
85 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
88 #define CPP_SPEC " %(subtarget_cpp_spec) "
90 #ifndef SUBTARGET_CPP_SPEC
91 #define SUBTARGET_CPP_SPEC ""
95 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
97 /* Target machine storage layout */
99 /* Define this if most significant bit is lowest numbered
100 in instructions that operate on numbered bit-fields. */
101 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
103 /* Define this if most significant byte of a word is the lowest numbered. */
104 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
106 /* Define this if most significant word of a multiword number is the lowest. */
107 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
109 #define MAX_BITS_PER_WORD 32
111 /* Width of a word, in units (bytes). */
112 #define UNITS_PER_WORD 4
113 #define MIN_UNITS_PER_WORD 4
115 /* Width of a floating point register. */
116 #define UNITS_PER_FPREG 4
118 /* Size in bits of various types on the target machine. */
119 #define INT_TYPE_SIZE 32
120 #define SHORT_TYPE_SIZE 16
121 #define LONG_TYPE_SIZE 32
122 #define LONG_LONG_TYPE_SIZE 64
123 #define FLOAT_TYPE_SIZE 32
124 #define DOUBLE_TYPE_SIZE 64
125 #define LONG_DOUBLE_TYPE_SIZE 64
127 /* Allocation boundary (in *bits*) for storing pointers in memory. */
128 #define POINTER_BOUNDARY 32
130 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
131 #define PARM_BOUNDARY 32
133 /* Allocation boundary (in *bits*) for the code of a function. */
134 #define FUNCTION_BOUNDARY 32
136 /* Alignment of field after 'int : 0' in a structure. */
137 #define EMPTY_FIELD_BOUNDARY 32
139 /* Every structure's size must be a multiple of this. */
140 #define STRUCTURE_SIZE_BOUNDARY 8
142 /* There is no point aligning anything to a rounder boundary than this. */
143 #define BIGGEST_ALIGNMENT 128
145 /* Set this nonzero if move instructions will actually fail to work
146 when given unaligned data. */
147 #define STRICT_ALIGNMENT 1
149 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
150 for QImode, because there is no 8-bit load from memory with sign
151 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
152 loads both with and without sign extension. */
153 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
155 if (GET_MODE_CLASS (MODE) == MODE_INT \
156 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
158 if ((MODE) == QImode) \
164 /* Imitate the way many other C compilers handle alignment of
165 bitfields and the structures that contain them. */
166 #define PCC_BITFIELD_TYPE_MATTERS 1
168 /* Disable the use of word-sized or smaller complex modes for structures,
169 and for function arguments in particular, where they cause problems with
170 register a7. The xtensa_copy_incoming_a7 function assumes that there is
171 a single reference to an argument in a7, but with small complex modes the
172 real and imaginary components may be extracted separately, leading to two
173 uses of the register, only one of which would be replaced. */
174 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
175 ((MODE) == CQImode || (MODE) == CHImode)
177 /* Align string constants and constructors to at least a word boundary.
178 The typical use of this macro is to increase alignment for string
179 constants to be word aligned so that 'strcpy' calls that copy
180 constants can be done inline. */
181 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
182 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
183 && (ALIGN) < BITS_PER_WORD \
187 /* Align arrays, unions and records to at least a word boundary.
188 One use of this macro is to increase alignment of medium-size
189 data to make it all fit in fewer cache lines. Another is to
190 cause character arrays to be word-aligned so that 'strcpy' calls
191 that copy constants to character arrays can be done inline. */
192 #undef DATA_ALIGNMENT
193 #define DATA_ALIGNMENT(TYPE, ALIGN) \
194 ((((ALIGN) < BITS_PER_WORD) \
195 && (TREE_CODE (TYPE) == ARRAY_TYPE \
196 || TREE_CODE (TYPE) == UNION_TYPE \
197 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
199 /* Operations between registers always perform the operation
200 on the full register even if a narrower mode is specified. */
201 #define WORD_REGISTER_OPERATIONS
203 /* Xtensa loads are zero-extended by default. */
204 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
206 /* Standard register usage. */
208 /* Number of actual hardware registers.
209 The hardware registers are assigned numbers for the compiler
210 from 0 to just below FIRST_PSEUDO_REGISTER.
211 All registers that the compiler knows about must be given numbers,
212 even those that are not normally considered general registers.
214 The fake frame pointer and argument pointer will never appear in
215 the generated code, since they will always be eliminated and replaced
216 by either the stack pointer or the hard frame pointer.
218 0 - 15 AR[0] - AR[15]
219 16 FRAME_POINTER (fake = initial sp)
220 17 ARG_POINTER (fake = initial sp + framesize)
221 18 BR[0] for floating-point CC
222 19 - 34 FR[0] - FR[15]
223 35 MAC16 accumulator */
225 #define FIRST_PSEUDO_REGISTER 36
227 /* Return the stabs register number to use for REGNO. */
228 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
230 /* 1 for registers that have pervasive standard uses
231 and are not available for the register allocator. */
232 #define FIXED_REGISTERS \
234 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
240 /* 1 for registers not available across function calls.
241 These must include the FIXED_REGISTERS and also any
242 registers that can be used without being saved.
243 The latter must include the registers where values are returned
244 and the register where structure-value addresses are passed.
245 Aside from that, you can include as many other registers as you like. */
246 #define CALL_USED_REGISTERS \
248 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
250 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
254 /* For non-leaf procedures on Xtensa processors, the allocation order
255 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
256 want to use the lowest numbered registers first to minimize
257 register window overflows. However, local-alloc is not smart
258 enough to consider conflicts with incoming arguments. If an
259 incoming argument in a2 is live throughout the function and
260 local-alloc decides to use a2, then the incoming argument must
261 either be spilled or copied to another register. To get around
262 this, we define ADJUST_REG_ALLOC_ORDER to redefine
263 reg_alloc_order for leaf functions such that lowest numbered
264 registers are used first with the exception that the incoming
265 argument registers are not used until after other register choices
266 have been exhausted. */
268 #define REG_ALLOC_ORDER \
269 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
271 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
276 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
278 /* For Xtensa, the only point of this is to prevent GCC from otherwise
279 giving preference to call-used registers. To minimize window
280 overflows for the AR registers, we want to give preference to the
281 lower-numbered AR registers. For other register files, which are
282 not windowed, we still prefer call-used registers, if there are any. */
283 extern const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
];
284 #define LEAF_REGISTERS xtensa_leaf_regs
286 /* For Xtensa, no remapping is necessary, but this macro must be
287 defined if LEAF_REGISTERS is defined. */
288 #define LEAF_REG_REMAP(REGNO) (REGNO)
290 /* This must be declared if LEAF_REGISTERS is set. */
291 extern int leaf_function
;
293 /* Internal macros to classify a register number. */
295 /* 16 address registers + fake registers */
296 #define GP_REG_FIRST 0
297 #define GP_REG_LAST 17
298 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
300 /* Coprocessor registers */
301 #define BR_REG_FIRST 18
302 #define BR_REG_LAST 18
303 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
305 /* 16 floating-point registers */
306 #define FP_REG_FIRST 19
307 #define FP_REG_LAST 34
308 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
310 /* MAC16 accumulator */
311 #define ACC_REG_FIRST 35
312 #define ACC_REG_LAST 35
313 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
315 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
316 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
317 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
318 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
320 /* Return number of consecutive hard regs needed starting at reg REGNO
321 to hold something of mode MODE. */
322 #define HARD_REGNO_NREGS(REGNO, MODE) \
323 (FP_REG_P (REGNO) ? \
324 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
325 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
327 /* Value is 1 if hard register REGNO can hold a value of machine-mode
329 extern char xtensa_hard_regno_mode_ok
[][FIRST_PSEUDO_REGISTER
];
331 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
332 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
334 /* Value is 1 if it is a good idea to tie two pseudo registers
335 when one has mode MODE1 and one has mode MODE2.
336 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
337 for any hard reg, then this must be 0 for correct output. */
338 #define MODES_TIEABLE_P(MODE1, MODE2) \
339 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
340 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
341 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
342 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
344 /* Register to use for pushing function arguments. */
345 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
347 /* Base register for access to local variables of the function. */
348 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
350 /* The register number of the frame pointer register, which is used to
351 access automatic variables in the stack frame. For Xtensa, this
352 register never appears in the output. It is always eliminated to
353 either the stack pointer or the hard frame pointer. */
354 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
356 /* Base register for access to arguments of the function. */
357 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
359 /* For now we don't try to use the full set of boolean registers. Without
360 software pipelining of FP operations, there's not much to gain and it's
361 a real pain to get them reloaded. */
362 #define FPCC_REGNUM (BR_REG_FIRST + 0)
364 /* It is as good or better to call a constant function address than to
365 call an address kept in a register. */
366 #define NO_FUNCTION_CSE 1
368 /* Xtensa processors have "register windows". GCC does not currently
369 take advantage of the possibility for variable-sized windows; instead,
370 we use a fixed window size of 8. */
372 #define INCOMING_REGNO(OUT) \
373 ((GP_REG_P (OUT) && \
374 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
375 (OUT) - WINDOW_SIZE : (OUT))
377 #define OUTGOING_REGNO(IN) \
379 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
380 (IN) + WINDOW_SIZE : (IN))
383 /* Define the classes of registers for register constraints in the
384 machine description. */
387 NO_REGS
, /* no registers in set */
388 BR_REGS
, /* coprocessor boolean registers */
389 FP_REGS
, /* floating point registers */
390 ACC_REG
, /* MAC16 accumulator */
391 SP_REG
, /* sp register (aka a1) */
392 RL_REGS
, /* preferred reload regs (not sp or fp) */
393 GR_REGS
, /* integer registers except sp */
394 AR_REGS
, /* all integer registers */
395 ALL_REGS
, /* all registers */
396 LIM_REG_CLASSES
/* max value + 1 */
399 #define N_REG_CLASSES (int) LIM_REG_CLASSES
401 #define GENERAL_REGS AR_REGS
403 /* An initializer containing the names of the register classes as C
404 string constants. These names are used in writing some of the
406 #define REG_CLASS_NAMES \
419 /* Contents of the register classes. The Nth integer specifies the
420 contents of class N. The way the integer MASK is interpreted is
421 that register R is in the class if 'MASK & (1 << R)' is 1. */
422 #define REG_CLASS_CONTENTS \
424 { 0x00000000, 0x00000000 }, /* no registers */ \
425 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
426 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
427 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
428 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
429 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
430 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
431 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
432 { 0xffffffff, 0x0000000f } /* all registers */ \
435 #define IRA_COVER_CLASSES \
437 BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \
440 /* A C expression whose value is a register class containing hard
441 register REGNO. In general there is more that one such class;
442 choose a class which is "minimal", meaning that no smaller class
443 also contains the register. */
444 extern const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
];
446 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
448 /* Use the Xtensa AR register file for base registers.
449 No index registers. */
450 #define BASE_REG_CLASS AR_REGS
451 #define INDEX_REG_CLASS NO_REGS
453 /* The small_register_classes_for_mode_p hook must always return true for
454 Xtrnase, because all of the 16 AR registers may be explicitly used in
455 the RTL, as either incoming or outgoing arguments. */
456 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
458 /* Return the maximum number of consecutive registers
459 needed to represent mode MODE in a register of class CLASS. */
460 #define CLASS_UNITS(mode, size) \
461 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
463 #define CLASS_MAX_NREGS(CLASS, MODE) \
464 (CLASS_UNITS (MODE, UNITS_PER_WORD))
467 /* Stack layout; function entry, exit and calling. */
469 #define STACK_GROWS_DOWNWARD
471 /* Offset within stack frame to start allocating local variables at. */
472 #define STARTING_FRAME_OFFSET \
473 crtl->outgoing_args_size
475 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
476 they are eliminated to either the stack pointer or hard frame pointer. */
477 #define ELIMINABLE_REGS \
478 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
479 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
480 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
481 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
483 /* Specify the initial difference between the specified pair of registers. */
484 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
486 compute_frame_size (get_frame_size ()); \
489 case FRAME_POINTER_REGNUM: \
492 case ARG_POINTER_REGNUM: \
493 (OFFSET) = xtensa_current_frame_size; \
496 gcc_unreachable (); \
500 /* If defined, the maximum amount of space required for outgoing
501 arguments will be computed and placed into the variable
502 'crtl->outgoing_args_size'. No space will be pushed
503 onto the stack for each call; instead, the function prologue
504 should increase the stack frame size by this amount. */
505 #define ACCUMULATE_OUTGOING_ARGS 1
507 /* Offset from the argument pointer register to the first argument's
508 address. On some machines it may depend on the data type of the
509 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
510 location above the first argument's address. */
511 #define FIRST_PARM_OFFSET(FNDECL) 0
513 /* Align stack frames on 128 bits for Xtensa. This is necessary for
514 128-bit datatypes defined in TIE (e.g., for Vectra). */
515 #define STACK_BOUNDARY 128
517 /* Use a fixed register window size of 8. */
518 #define WINDOW_SIZE 8
520 /* Symbolic macros for the registers used to return integer, floating
521 point, and values of coprocessor and user-defined modes. */
522 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
523 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
525 /* Symbolic macros for the first/last argument registers. */
526 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
527 #define GP_ARG_LAST (GP_REG_FIRST + 7)
528 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
529 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
531 #define MAX_ARGS_IN_REGISTERS 6
533 /* Don't worry about compatibility with PCC. */
534 #define DEFAULT_PCC_STRUCT_RETURN 0
536 /* A C expression that is nonzero if REGNO is the number of a hard
537 register in which function arguments are sometimes passed. This
538 does *not* include implicit arguments such as the static chain and
539 the structure-value address. On many machines, no registers can be
540 used for this purpose since all function arguments are pushed on
542 #define FUNCTION_ARG_REGNO_P(N) \
543 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
545 /* Record the number of argument words seen so far, along with a flag to
546 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
547 is used for both incoming and outgoing args, so a separate flag is
549 typedef struct xtensa_args
555 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
556 init_cumulative_args (&CUM, 0)
558 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
559 init_cumulative_args (&CUM, 1)
561 /* Profiling Xtensa code is typically done with the built-in profiling
562 feature of Tensilica's instruction set simulator, which does not
563 require any compiler support. Profiling code on a real (i.e.,
564 non-simulated) Xtensa processor is currently only supported by
565 GNU/Linux with glibc. The glibc version of _mcount doesn't require
566 counter variables. The _mcount function needs the current PC and
567 the current return address to identify an arc in the call graph.
568 Pass the current return address as the first argument; the current
569 PC is available as a0 in _mcount's register window. Both of these
570 values contain window size information in the two most significant
571 bits; we assume that _mcount will mask off those bits. The call to
572 _mcount uses a window size of 8 to make sure that it doesn't clobber
573 any incoming argument values. */
575 #define NO_PROFILE_COUNTERS 1
577 #define FUNCTION_PROFILER(FILE, LABELNO) \
579 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
582 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
583 fprintf (FILE, "\tcallx8\ta8\n"); \
586 fprintf (FILE, "\tcall8\t_mcount\n"); \
589 /* Stack pointer value doesn't matter at exit. */
590 #define EXIT_IGNORE_STACK 1
592 /* Size in bytes of the trampoline, as an integer. Make sure this is
593 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
594 #define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52)
596 /* Alignment required for trampolines, in bits. */
597 #define TRAMPOLINE_ALIGNMENT 32
599 /* If defined, a C expression that produces the machine-specific code
600 to setup the stack so that arbitrary frames can be accessed.
602 On Xtensa, a stack back-trace must always begin from the stack pointer,
603 so that the register overflow save area can be located. However, the
604 stack-walking code in GCC always begins from the hard_frame_pointer
605 register, not the stack pointer. The frame pointer is usually equal
606 to the stack pointer, but the __builtin_return_address and
607 __builtin_frame_address functions will not work if count > 0 and
608 they are called from a routine that uses alloca. These functions
609 are not guaranteed to work at all if count > 0 so maybe that is OK.
611 A nicer solution would be to allow the architecture-specific files to
612 specify whether to start from the stack pointer or frame pointer. That
613 would also allow us to skip the machine->accesses_prev_frame stuff that
614 we currently need to ensure that there is a frame pointer when these
615 builtin functions are used. */
617 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
619 /* A C expression whose value is RTL representing the address in a
620 stack frame where the pointer to the caller's frame is stored.
621 Assume that FRAMEADDR is an RTL expression for the address of the
624 For Xtensa, there is no easy way to get the frame pointer if it is
625 not equivalent to the stack pointer. Moreover, the result of this
626 macro is used for continuing to walk back up the stack, so it must
627 return the stack pointer address. Thus, there is some inconsistency
628 here in that __builtin_frame_address will return the frame pointer
629 when count == 0 and the stack pointer when count > 0. */
631 #define DYNAMIC_CHAIN_ADDRESS(frame) \
632 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
634 /* Define this if the return address of a particular stack frame is
635 accessed from the frame pointer of the previous stack frame. */
636 #define RETURN_ADDR_IN_PREVIOUS_FRAME
638 /* A C expression whose value is RTL representing the value of the
639 return address for the frame COUNT steps up from the current
640 frame, after the prologue. */
641 #define RETURN_ADDR_RTX xtensa_return_addr
643 /* Addressing modes, and classification of registers for them. */
645 /* C expressions which are nonzero if register number NUM is suitable
646 for use as a base or index register in operand addresses. */
648 #define REGNO_OK_FOR_INDEX_P(NUM) 0
649 #define REGNO_OK_FOR_BASE_P(NUM) \
650 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
652 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
653 valid for use as a base or index register. */
656 #define REG_OK_STRICT_FLAG 1
658 #define REG_OK_STRICT_FLAG 0
661 #define BASE_REG_P(X, STRICT) \
662 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
663 || REGNO_OK_FOR_BASE_P (REGNO (X)))
665 #define REG_OK_FOR_INDEX_P(X) 0
666 #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG)
668 /* Maximum number of registers that can appear in a valid memory address. */
669 #define MAX_REGS_PER_ADDRESS 1
671 /* A C expression that is 1 if the RTX X is a constant which is a
672 valid address. This is defined to be the same as 'CONSTANT_P (X)',
673 but rejecting CONST_DOUBLE. */
674 #define CONSTANT_ADDRESS_P(X) \
675 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
676 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
677 || (GET_CODE (X) == CONST)))
679 /* Nonzero if the constant value X is a legitimate general operand.
680 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
681 #define LEGITIMATE_CONSTANT_P(X) (! xtensa_tls_referenced_p (X))
683 /* A C expression that is nonzero if X is a legitimate immediate
684 operand on the target machine when generating position independent
686 #define LEGITIMATE_PIC_OPERAND_P(X) \
687 ((GET_CODE (X) != SYMBOL_REF \
688 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
689 && GET_CODE (X) != LABEL_REF \
690 && GET_CODE (X) != CONST)
692 /* Specify the machine mode that this machine uses
693 for the index in the tablejump instruction. */
694 #define CASE_VECTOR_MODE (SImode)
696 /* Define this as 1 if 'char' should by default be signed; else as 0. */
697 #define DEFAULT_SIGNED_CHAR 0
699 /* Max number of bytes we can move from memory to memory
700 in one reasonably fast instruction. */
702 #define MAX_MOVE_MAX 4
704 /* Prefer word-sized loads. */
705 #define SLOW_BYTE_ACCESS 1
707 /* Shift instructions ignore all but the low-order few bits. */
708 #define SHIFT_COUNT_TRUNCATED 1
710 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
711 is done just by pretending it is already truncated. */
712 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
714 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
715 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
717 /* Specify the machine mode that pointers have.
718 After generation of rtl, the compiler makes no further distinction
719 between pointers and any other objects of this machine mode. */
722 /* A function address in a call instruction is a word address (for
723 indexing purposes) so give the MEM rtx a words's mode. */
724 #define FUNCTION_MODE SImode
726 #define BRANCH_COST(speed_p, predictable_p) 3
728 /* How to refer to registers in assembler output.
729 This sequence is indexed by compiler's hard-register-number (see above). */
730 #define REGISTER_NAMES \
732 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
733 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
734 "fp", "argp", "b0", \
735 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
736 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
740 /* If defined, a C initializer for an array of structures containing a
741 name and a register number. This macro defines additional names
742 for hard registers, thus allowing the 'asm' option in declarations
743 to refer to registers using alternate names. */
744 #define ADDITIONAL_REGISTER_NAMES \
746 { "a1", 1 + GP_REG_FIRST } \
749 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
750 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
752 /* Globalizing directive for a label. */
753 #define GLOBAL_ASM_OP "\t.global\t"
755 /* Declare an uninitialized external linkage data object. */
756 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
757 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
759 /* This is how to output an element of a case-vector that is absolute. */
760 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
761 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
762 LOCAL_LABEL_PREFIX, VALUE)
764 /* This is how to output an element of a case-vector that is relative.
765 This is used for pc-relative code. */
766 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
768 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
769 LOCAL_LABEL_PREFIX, (VALUE), \
770 LOCAL_LABEL_PREFIX, (REL)); \
773 /* This is how to output an assembler line that says to advance the
774 location counter to a multiple of 2**LOG bytes. */
775 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
778 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
781 /* Indicate that jump tables go in the text section. This is
782 necessary when compiling PIC code. */
783 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
786 /* Define the strings to put out for each section in the object file. */
787 #define TEXT_SECTION_ASM_OP "\t.text"
788 #define DATA_SECTION_ASM_OP "\t.data"
789 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
792 /* Define output to appear before the constant pool. */
793 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
797 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
798 switch_to_section (function_section (FUNDECL)); \
799 fprintf (FILE, "\t.literal_position\n"); \
804 /* A C statement (with or without semicolon) to output a constant in
805 the constant pool, if it needs special treatment. */
806 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
808 xtensa_output_literal (FILE, X, MODE, LABELNO); \
812 /* How to start an assembler comment. */
813 #define ASM_COMMENT_START "#"
815 /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding
816 machinery, but the variable size register window save areas are too
817 complicated to efficiently describe with CFI entries. The CFA must
818 still be specified in DWARF so that DW_AT_frame_base is set correctly
820 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0)
821 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0)
822 #define DWARF_FRAME_REGISTERS 16
823 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM)
824 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
826 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \
827 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
830 /* Emit a PC-relative relocation. */
831 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
833 fputs (integer_asm_op (SIZE, FALSE), FILE); \
834 assemble_name (FILE, LABEL); \
835 fputs ("@pcrel", FILE); \
838 /* Xtensa constant pool breaks the devices in crtstuff.c to control
839 section in where code resides. We have to write it as asm code. Use
840 a MOVI and let the assembler relax it -- for the .init and .fini
841 sections, the assembler knows to put the literal in the right
843 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
845 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
847 TEXT_SECTION_ASM_OP);