1 /* Xstormy16 cpu description.
2 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Driver configuration. */
29 #define LINK_SPEC "%{h*} %{v:-V} \
30 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
33 - If -msim is specified, everything is built and linked as for the sim.
34 - If -T is specified, that linker script is used, and it should provide
35 appropriate libraries.
36 - If neither is specified, everything is built as for the sim, but no
37 I/O support is assumed. */
39 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)"
42 #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
45 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
48 /* Run-time target specifications. */
50 #define TARGET_CPU_CPP_BUILTINS() \
53 builtin_define_std ("xstormy16"); \
54 builtin_assert ("machine=xstormy16"); \
55 builtin_assert ("cpu=xstormy16"); \
59 #define TARGET_VERSION fprintf (stderr, " (xstormy16 cpu core)");
63 #define BITS_BIG_ENDIAN 1
65 #define BYTES_BIG_ENDIAN 0
67 #define WORDS_BIG_ENDIAN 0
69 #define UNITS_PER_WORD 2
71 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
74 if (GET_MODE_CLASS (MODE) == MODE_INT \
75 && GET_MODE_SIZE (MODE) < 2) \
80 #define PARM_BOUNDARY 16
82 #define STACK_BOUNDARY 16
84 #define FUNCTION_BOUNDARY 16
86 #define BIGGEST_ALIGNMENT 16
88 #define DATA_ALIGNMENT(TYPE, ALIGN) \
89 (TREE_CODE (TYPE) == ARRAY_TYPE \
90 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
91 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
93 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
94 (TREE_CODE (EXP) == STRING_CST \
95 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
97 #define STRICT_ALIGNMENT 1
99 #define PCC_BITFIELD_TYPE_MATTERS 1
101 /* Layout of Source Language Data Types. */
103 #define INT_TYPE_SIZE 16
105 #define SHORT_TYPE_SIZE 16
107 #define LONG_TYPE_SIZE 32
109 #define LONG_LONG_TYPE_SIZE 64
111 #define FLOAT_TYPE_SIZE 32
113 #define DOUBLE_TYPE_SIZE 64
115 #define LONG_DOUBLE_TYPE_SIZE 64
117 #define DEFAULT_SIGNED_CHAR 0
119 #define SIZE_TYPE "unsigned int"
121 #define PTRDIFF_TYPE "int"
124 #define WCHAR_TYPE "long int"
126 #undef WCHAR_TYPE_SIZE
127 #define WCHAR_TYPE_SIZE 32
130 /* Register Basics. */
132 #define FIRST_PSEUDO_REGISTER 19
134 #define FIXED_REGISTERS \
135 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 }
137 #define CALL_USED_REGISTERS \
138 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 }
141 /* Order of allocation of registers. */
143 #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 }
146 /* How Values Fit in Registers. */
148 #define HARD_REGNO_NREGS(REGNO, MODE) \
149 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
151 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode)
153 /* A C expression that is nonzero if it is desirable to choose register
154 allocation so as to avoid move instructions between a value of mode MODE1
155 and a value of mode MODE2.
157 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
158 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
160 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode)
163 /* Register Classes. */
180 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
182 #define IRA_COVER_CLASSES \
184 GENERAL_REGS, LIM_REG_CLASSES \
187 #define REG_CLASS_NAMES \
201 #define REG_CLASS_CONTENTS \
212 { (1 << FIRST_PSEUDO_REGISTER) - 1 } \
215 #define REGNO_REG_CLASS(REGNO) \
216 ( (REGNO) == 0 ? R0_REGS \
217 : (REGNO) == 1 ? R1_REGS \
218 : (REGNO) == 2 ? R2_REGS \
219 : (REGNO) < 8 ? EIGHT_REGS \
220 : (REGNO) == 8 ? R8_REGS \
221 : (REGNO) <= 18 ? GENERAL_REGS \
224 #define BASE_REG_CLASS GENERAL_REGS
226 #define INDEX_REG_CLASS GENERAL_REGS
228 #define REGNO_OK_FOR_BASE_P(NUM) 1
230 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
232 /* This chip has the interesting property that only the first eight
233 registers can be moved to/from memory. */
234 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
235 xstormy16_secondary_reload_class (CLASS, MODE, X)
237 #define CLASS_MAX_NREGS(CLASS, MODE) \
238 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
241 /* Basic Stack Layout. */
243 /* We want to use post-increment instructions to push things on the stack,
244 because we don't have any pre-increment ones. */
245 #define STACK_PUSH_CODE POST_INC
247 #define FRAME_GROWS_DOWNWARD 0
249 #define ARGS_GROW_DOWNWARD 1
251 #define STARTING_FRAME_OFFSET 0
253 #define FIRST_PARM_OFFSET(FUNDECL) 0
255 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
257 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
260 #define INCOMING_RETURN_ADDR_RTX \
261 gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4)))
263 #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4)
266 /* Register That Address the Stack Frame. */
268 #define STATIC_CHAIN_REGNUM 1
269 #define HARD_FRAME_POINTER_REGNUM 13
270 #define STACK_POINTER_REGNUM 15
271 #define CARRY_REGNUM 16
272 #define FRAME_POINTER_REGNUM 17
273 #define ARG_POINTER_REGNUM 18
276 /* Eliminating the Frame Pointer and the Arg Pointer. */
278 #define ELIMINABLE_REGS \
280 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
281 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
282 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
283 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
286 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
287 (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO)
290 /* Passing Function Arguments on the Stack. */
292 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
295 /* Function Arguments in Registers. */
297 #define NUM_ARGUMENT_REGISTERS 6
298 #define FIRST_ARGUMENT_REGISTER 2
300 #define XSTORMY16_WORD_SIZE(TYPE, MODE) \
301 ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
305 /* For this platform, the value of CUMULATIVE_ARGS is the number of words
306 of arguments that have been passed in registers so far. */
307 #define CUMULATIVE_ARGS int
309 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
312 #define FUNCTION_ARG_REGNO_P(REGNO) \
313 ((REGNO) >= FIRST_ARGUMENT_REGISTER \
314 && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS)
317 /* How Scalar Function Values are Returned. */
319 /* The number of the hard register that is used to return a scalar value from a
321 #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER
324 /* Function Entry and Exit. */
326 #define EPILOGUE_USES(REGNO) \
327 xstormy16_epilogue_uses (REGNO)
330 /* Generating Code for Profiling. */
332 /* This declaration must be present, but it can be an abort if profiling is
335 #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler ()
338 /* Trampolines for Nested Functions. */
340 #define TRAMPOLINE_SIZE 8
341 #define TRAMPOLINE_ALIGNMENT 16
344 /* Addressing Modes. */
346 #define HAVE_POST_INCREMENT 1
348 #define HAVE_PRE_DECREMENT 1
350 #define MAX_REGS_PER_ADDRESS 1
352 #define LEGITIMATE_CONSTANT_P(X) 1
355 /* Describing Relative Costs of Operations. */
357 #define BRANCH_COST(speed_p, predictable_p) 5
359 #define SLOW_BYTE_ACCESS 0
361 #define NO_FUNCTION_CSE
364 /* Dividing the output into sections. */
366 #define TEXT_SECTION_ASM_OP ".text"
368 #define DATA_SECTION_ASM_OP ".data"
370 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
372 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
373 There are no shared libraries on this target so these sections need
376 Defined in elfos.h. */
378 #undef CTORS_SECTION_ASM_OP
379 #undef DTORS_SECTION_ASM_OP
380 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
381 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
383 #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections
385 #define JUMP_TABLES_IN_TEXT_SECTION 1
387 /* The Overall Framework of an Assembler File. */
389 #define ASM_COMMENT_START ";"
391 #define ASM_APP_ON "#APP\n"
393 #define ASM_APP_OFF "#NO_APP\n"
395 /* Output of Data. */
397 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|')
399 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
400 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
401 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
402 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
405 /* Output and Generation of Labels. */
406 #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0)
408 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
411 const char *rn = XSTR (SYMBOL, 0); \
413 if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
414 ASM_OUTPUT_LABEL_REF ((STREAM), rn); \
416 assemble_name (STREAM, rn); \
420 #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \
423 fputs ("@fptr(", STREAM); \
424 assemble_name (STREAM, NAME); \
425 fputc (')', STREAM); \
429 /* Globalizing directive for a label. */
430 #define GLOBAL_ASM_OP "\t.globl "
433 /* Output of Assembler Instructions. */
435 #define REGISTER_NAMES \
436 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
437 "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" }
439 #define ADDITIONAL_REGISTER_NAMES \
443 #define REGISTER_PREFIX ""
444 #define LOCAL_LABEL_PREFIX "."
445 #define USER_LABEL_PREFIX ""
446 #define IMMEDIATE_PREFIX "#"
448 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
449 fprintf (STREAM, "\tpush %d\n", REGNO)
451 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
452 fprintf (STREAM, "\tpop %d\n", REGNO)
455 /* Output of dispatch tables. */
457 /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because
458 this could cause label alignment to appear between the 'br' and the table,
459 which would be bad. Instead, it controls the output of the table
461 #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
462 xstormy16_output_addr_vec (file, LABEL, BODY)
464 /* Alignment for ADDR_VECs is the same as for code. */
465 #define ADDR_VEC_ALIGN(ADDR_VEC) 1
468 /* Assembler Commands for Exception Regions. */
470 #define DWARF2_UNWIND_INFO 0
471 #define DWARF_CIE_DATA_ALIGNMENT 1
473 #undef DONT_USE_BUILTIN_SETJMP
474 #define JMP_BUF_SIZE 8
476 /* Assembler Commands for Alignment. */
478 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
479 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
482 /* Macros Affecting all Debug Formats. */
484 #undef PREFERRED_DEBUGGING_TYPE
485 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
488 /* Macros for SDB and Dwarf Output. */
490 /* Define this macro if addresses in Dwarf 2 debugging info should not
491 be the same size as pointers on the target architecture. The
492 macro's value should be the size, in bytes, to use for addresses in
495 Some architectures use word addresses to refer to code locations,
496 but Dwarf 2 info always uses byte addresses. On such machines,
497 Dwarf 2 addresses need to be larger than the architecture's
499 #define DWARF2_ADDR_SIZE 4
502 /* Miscellaneous Parameters. */
504 #define CASE_VECTOR_MODE SImode
506 #define WORD_REGISTER_OPERATIONS
508 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
512 #define SHIFT_COUNT_TRUNCATED 1
514 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
518 #define FUNCTION_MODE HImode
520 #define NO_IMPLICIT_EXTERN_C