1 ;; Machine description for PowerPC synchronization instructions.
2 ;; Copyright (C) 2005, 2007, 2008, 2009, 2011
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Geoffrey Keating.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
23 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
25 (define_code_iterator FETCHOP [plus minus ior xor and])
26 (define_code_attr fetchop_name
27 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
28 (define_code_attr fetchop_pred
29 [(plus "add_operand") (minus "gpc_reg_operand")
30 (ior "logical_operand") (xor "logical_operand") (and "and_operand")])
31 (define_code_attr fetchopsi_constr
32 [(plus "rIL") (minus "r") (ior "rKL") (xor "rKL") (and "rTKL")])
33 (define_code_attr fetchopdi_constr
34 [(plus "rIL") (minus "r") (ior "rKJF") (xor "rKJF") (and "rSTKJ")])
36 (define_expand "memory_barrier"
38 (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
41 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
42 MEM_VOLATILE_P (operands[0]) = 1;
45 (define_insn "*sync_internal"
46 [(set (match_operand:BLK 0 "" "")
47 (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
50 [(set_attr "type" "sync")])
52 (define_insn "load_locked_<mode>"
53 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
55 [(match_operand:GPR 1 "memory_operand" "Z")] UNSPECV_LL))]
58 [(set_attr "type" "load_l")])
60 (define_insn "store_conditional_<mode>"
61 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
62 (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
63 (set (match_operand:GPR 1 "memory_operand" "=Z")
64 (match_operand:GPR 2 "gpc_reg_operand" "r"))]
67 [(set_attr "type" "store_c")])
69 (define_insn_and_split "sync_compare_and_swap<mode>"
70 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
71 (match_operand:GPR 1 "memory_operand" "+Z"))
74 [(match_operand:GPR 2 "reg_or_short_operand" "rI")
75 (match_operand:GPR 3 "gpc_reg_operand" "r")]
77 (clobber (match_scratch:GPR 4 "=&r"))
78 (clobber (match_scratch:CC 5 "=&x"))]
84 rs6000_split_compare_and_swap (operands[0], operands[1], operands[2],
85 operands[3], operands[4]);
89 (define_expand "sync_compare_and_swaphi"
90 [(match_operand:HI 0 "gpc_reg_operand" "")
91 (match_operand:HI 1 "memory_operand" "")
92 (match_operand:HI 2 "gpc_reg_operand" "")
93 (match_operand:HI 3 "gpc_reg_operand" "")]
96 rs6000_expand_compare_and_swapqhi (operands[0], operands[1],
97 operands[2], operands[3]);
101 (define_expand "sync_compare_and_swapqi"
102 [(match_operand:QI 0 "gpc_reg_operand" "")
103 (match_operand:QI 1 "memory_operand" "")
104 (match_operand:QI 2 "gpc_reg_operand" "")
105 (match_operand:QI 3 "gpc_reg_operand" "")]
108 rs6000_expand_compare_and_swapqhi (operands[0], operands[1],
109 operands[2], operands[3]);
113 (define_insn_and_split "sync_compare_and_swapqhi_internal"
114 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
115 (match_operand:SI 4 "memory_operand" "+Z"))
118 [(match_operand:SI 1 "gpc_reg_operand" "r")
119 (match_operand:SI 2 "gpc_reg_operand" "r")
120 (match_operand:SI 3 "gpc_reg_operand" "r")]
122 (clobber (match_scratch:SI 5 "=&r"))
123 (clobber (match_scratch:CC 6 "=&x"))]
126 "&& reload_completed"
129 rs6000_split_compare_and_swapqhi (operands[0], operands[1],
130 operands[2], operands[3], operands[4],
135 (define_insn_and_split "sync_lock_test_and_set<mode>"
136 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
137 (match_operand:GPR 1 "memory_operand" "+Z"))
140 [(match_operand:GPR 2 "reg_or_short_operand" "rL")]
142 (clobber (match_scratch:GPR 3 "=&r"))
143 (clobber (match_scratch:CC 4 "=&x"))]
146 "&& reload_completed"
149 rs6000_split_lock_test_and_set (operands[0], operands[1], operands[2],
154 (define_expand "sync_<fetchop_name><mode>"
155 [(parallel [(set (match_operand:INT1 0 "memory_operand" "")
157 [(FETCHOP:INT1 (match_dup 0)
158 (match_operand:INT1 1 "<fetchop_pred>" ""))]
160 (clobber (scratch:INT1))
161 (clobber (scratch:CC))])]
165 if (<MODE>mode != SImode && <MODE>mode != DImode)
167 if (PPC405_ERRATUM77)
169 rs6000_emit_sync (<CODE>, <MODE>mode, operands[0], operands[1],
170 NULL_RTX, NULL_RTX, true);
175 (define_insn_and_split "*sync_<fetchop_name>si_internal"
176 [(set (match_operand:SI 0 "memory_operand" "+Z")
178 [(FETCHOP:SI (match_dup 0)
179 (match_operand:SI 1 "<fetchop_pred>" "<fetchopsi_constr>"))]
181 (clobber (match_scratch:SI 2 "=&b"))
182 (clobber (match_scratch:CC 3 "=&x"))]
185 "&& reload_completed"
188 rs6000_split_atomic_op (<CODE>, operands[0], operands[1],
189 NULL_RTX, NULL_RTX, operands[2]);
193 (define_insn_and_split "*sync_<fetchop_name>di_internal"
194 [(set (match_operand:DI 0 "memory_operand" "+Z")
196 [(FETCHOP:DI (match_dup 0)
197 (match_operand:DI 1 "<fetchop_pred>" "<fetchopdi_constr>"))]
199 (clobber (match_scratch:DI 2 "=&b"))
200 (clobber (match_scratch:CC 3 "=&x"))]
203 "&& reload_completed"
206 rs6000_split_atomic_op (<CODE>, operands[0], operands[1],
207 NULL_RTX, NULL_RTX, operands[2]);
211 (define_expand "sync_nand<mode>"
212 [(parallel [(set (match_operand:INT1 0 "memory_operand" "")
214 [(ior:INT1 (not:INT1 (match_dup 0))
215 (not:INT1 (match_operand:INT1 1 "gpc_reg_operand" "")))]
217 (clobber (scratch:INT1))
218 (clobber (scratch:CC))])]
222 if (<MODE>mode != SImode && <MODE>mode != DImode)
225 if (PPC405_ERRATUM77)
227 rs6000_emit_sync (NOT, <MODE>mode, operands[0], operands[1],
228 NULL_RTX, NULL_RTX, true);
233 (define_insn_and_split "*sync_nand<mode>_internal"
234 [(set (match_operand:GPR 0 "memory_operand" "+Z")
236 [(ior:GPR (not:GPR (match_dup 0))
237 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
239 (clobber (match_scratch:GPR 2 "=&r"))
240 (clobber (match_scratch:CC 3 "=&x"))]
243 "&& reload_completed"
246 rs6000_split_atomic_op (NOT, operands[0], operands[1],
247 NULL_RTX, NULL_RTX, operands[2]);
251 (define_expand "sync_old_<fetchop_name><mode>"
252 [(parallel [(set (match_operand:INT1 0 "gpc_reg_operand" "")
253 (match_operand:INT1 1 "memory_operand" ""))
256 [(FETCHOP:INT1 (match_dup 1)
257 (match_operand:INT1 2 "<fetchop_pred>" ""))]
259 (clobber (scratch:INT1))
260 (clobber (scratch:CC))])]
264 if (<MODE>mode != SImode && <MODE>mode != DImode)
266 if (PPC405_ERRATUM77)
268 rs6000_emit_sync (<CODE>, <MODE>mode, operands[1], operands[2],
269 operands[0], NULL_RTX, true);
274 (define_insn_and_split "*sync_old_<fetchop_name>si_internal"
275 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
276 (match_operand:SI 1 "memory_operand" "+Z"))
279 [(FETCHOP:SI (match_dup 1)
280 (match_operand:SI 2 "<fetchop_pred>" "<fetchopsi_constr>"))]
282 (clobber (match_scratch:SI 3 "=&b"))
283 (clobber (match_scratch:CC 4 "=&x"))]
286 "&& reload_completed"
289 rs6000_split_atomic_op (<CODE>, operands[1], operands[2],
290 operands[0], NULL_RTX, operands[3]);
294 (define_insn_and_split "*sync_old_<fetchop_name>di_internal"
295 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
296 (match_operand:DI 1 "memory_operand" "+Z"))
299 [(FETCHOP:DI (match_dup 1)
300 (match_operand:DI 2 "<fetchop_pred>" "<fetchopdi_constr>"))]
302 (clobber (match_scratch:DI 3 "=&b"))
303 (clobber (match_scratch:CC 4 "=&x"))]
306 "&& reload_completed"
309 rs6000_split_atomic_op (<CODE>, operands[1], operands[2],
310 operands[0], NULL_RTX, operands[3]);
314 (define_expand "sync_old_nand<mode>"
315 [(parallel [(set (match_operand:INT1 0 "gpc_reg_operand" "")
316 (match_operand:INT1 1 "memory_operand" ""))
319 [(ior:INT1 (not:INT1 (match_dup 1))
320 (not:INT1 (match_operand:INT1 2 "gpc_reg_operand" "")))]
322 (clobber (scratch:INT1))
323 (clobber (scratch:CC))])]
327 if (<MODE>mode != SImode && <MODE>mode != DImode)
330 if (PPC405_ERRATUM77)
332 rs6000_emit_sync (NOT, <MODE>mode, operands[1], operands[2],
333 operands[0], NULL_RTX, true);
338 (define_insn_and_split "*sync_old_nand<mode>_internal"
339 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
340 (match_operand:GPR 1 "memory_operand" "+Z"))
343 [(ior:GPR (not:GPR (match_dup 1))
344 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")))]
346 (clobber (match_scratch:GPR 3 "=&r"))
347 (clobber (match_scratch:CC 4 "=&x"))]
350 "&& reload_completed"
353 rs6000_split_atomic_op (NOT, operands[1], operands[2],
354 operands[0], NULL_RTX, operands[3]);
358 (define_expand "sync_new_<fetchop_name><mode>"
359 [(parallel [(set (match_operand:INT1 0 "gpc_reg_operand" "")
361 (match_operand:INT1 1 "memory_operand" "")
362 (match_operand:INT1 2 "<fetchop_pred>" "")))
365 [(FETCHOP:INT1 (match_dup 1) (match_dup 2))]
367 (clobber (scratch:INT1))
368 (clobber (scratch:CC))])]
372 if (<MODE>mode != SImode && <MODE>mode != DImode)
374 if (PPC405_ERRATUM77)
376 rs6000_emit_sync (<CODE>, <MODE>mode, operands[1], operands[2],
377 NULL_RTX, operands[0], true);
382 (define_insn_and_split "*sync_new_<fetchop_name>si_internal"
383 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
385 (match_operand:SI 1 "memory_operand" "+Z")
386 (match_operand:SI 2 "<fetchop_pred>" "<fetchopsi_constr>")))
389 [(FETCHOP:SI (match_dup 1) (match_dup 2))]
391 (clobber (match_scratch:SI 3 "=&b"))
392 (clobber (match_scratch:CC 4 "=&x"))]
395 "&& reload_completed"
398 rs6000_split_atomic_op (<CODE>, operands[1], operands[2],
399 NULL_RTX, operands[0], operands[3]);
403 (define_insn_and_split "*sync_new_<fetchop_name>di_internal"
404 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
406 (match_operand:DI 1 "memory_operand" "+Z")
407 (match_operand:DI 2 "<fetchop_pred>" "<fetchopdi_constr>")))
410 [(FETCHOP:DI (match_dup 1) (match_dup 2))]
412 (clobber (match_scratch:DI 3 "=&b"))
413 (clobber (match_scratch:CC 4 "=&x"))]
416 "&& reload_completed"
419 rs6000_split_atomic_op (<CODE>, operands[1], operands[2],
420 NULL_RTX, operands[0], operands[3]);
424 (define_expand "sync_new_nand<mode>"
425 [(parallel [(set (match_operand:INT1 0 "gpc_reg_operand" "")
427 (not:INT1 (match_operand:INT1 1 "memory_operand" ""))
428 (not:INT1 (match_operand:INT1 2 "gpc_reg_operand" ""))))
431 [(ior:INT1 (not:INT1 (match_dup 1))
432 (not:INT1 (match_dup 2)))]
434 (clobber (scratch:INT1))
435 (clobber (scratch:CC))])]
439 if (<MODE>mode != SImode && <MODE>mode != DImode)
442 if (PPC405_ERRATUM77)
444 rs6000_emit_sync (NOT, <MODE>mode, operands[1], operands[2],
445 NULL_RTX, operands[0], true);
450 (define_insn_and_split "*sync_new_nand<mode>_internal"
451 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
453 (not:GPR (match_operand:GPR 1 "memory_operand" "+Z"))
454 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))))
457 [(ior:GPR (not:GPR (match_dup 1)) (not:GPR (match_dup 2)))]
459 (clobber (match_scratch:GPR 3 "=&r"))
460 (clobber (match_scratch:CC 4 "=&x"))]
463 "&& reload_completed"
466 rs6000_split_atomic_op (NOT, operands[1], operands[2],
467 NULL_RTX, operands[0], operands[3]);
471 ; and<mode> without cr0 clobber to avoid generation of additional clobber
472 ; in atomic splitters causing internal consistency failure.
473 ; cr0 already clobbered by larx/stcx.
474 (define_insn "*atomic_andsi"
475 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
476 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
477 (match_operand:SI 2 "and_operand" "?r,T,K,L")]
482 {rlinm|rlwinm} %0,%1,0,%m2,%M2
483 {andil.|andi.} %0,%1,%b2
484 {andiu.|andis.} %0,%1,%u2"
485 [(set_attr "type" "*,*,compare,compare")])
487 (define_insn "*atomic_anddi"
488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
489 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
490 (match_operand:DI 2 "and_operand" "?r,S,T,K,J")]
496 rlwinm %0,%1,0,%m2,%M2
499 [(set_attr "type" "*,*,*,compare,compare")
500 (set_attr "length" "4,4,4,4,4")])
502 ; the sync_*_internal patterns all have these operands:
503 ; 0 - memory location
505 ; 2 - value in memory after operation
506 ; 3 - value in memory immediately before operation
508 (define_insn "*sync_addshort_internal"
509 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
510 (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
511 (match_operand:SI 1 "add_operand" "rI"))
512 (match_operand:SI 4 "gpc_reg_operand" "r"))
513 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
514 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
516 (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
518 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
520 (clobber (match_scratch:CC 5 "=&x"))
521 (clobber (match_scratch:SI 6 "=&r"))]
522 "TARGET_POWERPC && !PPC405_ERRATUM77"
523 "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
524 [(set_attr "length" "28")])
526 (define_insn "*sync_subshort_internal"
527 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
528 (ior:SI (and:SI (minus:SI (match_operand:SI 0 "memory_operand" "+Z")
529 (match_operand:SI 1 "add_operand" "rI"))
530 (match_operand:SI 4 "gpc_reg_operand" "r"))
531 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
532 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
534 (unspec:SI [(ior:SI (and:SI (minus:SI (match_dup 0) (match_dup 1))
536 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
538 (clobber (match_scratch:CC 5 "=&x"))
539 (clobber (match_scratch:SI 6 "=&r"))]
540 "TARGET_POWERPC && !PPC405_ERRATUM77"
541 "lwarx %3,%y0\n\tsubf %2,%1,%3\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
542 [(set_attr "length" "28")])
544 (define_insn "*sync_andsi_internal"
545 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
546 (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
547 (match_operand:SI 1 "and_operand" "r,T,K,L")))
548 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
550 (unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
552 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
553 "TARGET_POWERPC && !PPC405_ERRATUM77"
555 lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
556 lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12
557 lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
558 lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
559 [(set_attr "length" "16,16,16,16")])
561 (define_insn "*sync_boolsi_internal"
562 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
563 (match_operator:SI 4 "boolean_or_operator"
564 [(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
565 (match_operand:SI 1 "logical_operand" "r,K,L")]))
566 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
567 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
568 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
569 "TARGET_POWERPC && !PPC405_ERRATUM77"
571 lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
572 lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
573 lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
574 [(set_attr "length" "16,16,16")])
576 ; This pattern could also take immediate values of operand 1,
577 ; since the non-NOT version of the operator is used; but this is not
578 ; very useful, since in practice operand 1 is a full 32-bit value.
579 ; Likewise, operand 5 is in practice either <= 2^16 or it is a register.
580 (define_insn "*sync_boolcshort_internal"
581 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
582 (match_operator:SI 4 "boolean_or_operator"
583 [(xor:SI (not:SI (match_operand:SI 0 "memory_operand" "+Z"))
584 (not:SI (match_operand:SI 5 "logical_operand" "rK")))
585 (match_operand:SI 1 "gpc_reg_operand" "r")]))
586 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
587 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
588 (clobber (match_scratch:CC 6 "=&x"))]
589 "TARGET_POWERPC && !PPC405_ERRATUM77"
590 "lwarx %3,%y0\n\txor%I2 %2,%3,%5\n\t%q4 %2,%2,%1\n\tstwcx. %2,%y0\n\tbne- $-16"
591 [(set_attr "length" "20")])
594 [(set (mem:BLK (match_scratch 0 "X"))
595 (unspec_volatile:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPECV_ISYNC))]
598 [(set_attr "type" "isync")])
600 (define_expand "sync_lock_release<mode>"
601 [(set (match_operand:INT 0 "memory_operand")
602 (match_operand:INT 1 "any_operand"))]
606 emit_insn (gen_lwsync ());
607 emit_move_insn (operands[0], operands[1]);
611 ; Some AIX assemblers don't accept lwsync, so we use a .long.
612 (define_insn "lwsync"
613 [(set (mem:BLK (match_scratch 0 "X"))
614 (unspec_volatile:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPECV_LWSYNC))]
617 if (TARGET_NO_LWSYNC)
620 return (TARGET_LWSYNC_INSTRUCTION) ? "lwsync" : ".long 0x7c2004ac";
622 [(set_attr "type" "sync")])