1 ; Options for the rs6000 port of the compiler
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software
5 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
7 ; This file is part of GCC.
9 ; GCC is free software; you can redistribute it and/or modify it under
10 ; the terms of the GNU General Public License as published by the Free
11 ; Software Foundation; either version 3, or (at your option) any later
14 ; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ; License for more details.
19 ; You should have received a copy of the GNU General Public License
20 ; along with GCC; see the file COPYING3. If not see
21 ; <http://www.gnu.org/licenses/>.
24 config/rs6000/rs6000-opts.h
28 enum processor_type rs6000_cpu = PROCESSOR_RIOS1
30 ;; Always emit branch hint bits.
32 unsigned char rs6000_always_hint
34 ;; Schedule instructions for group formation.
36 unsigned char rs6000_sched_groups
38 ;; Align branch targets.
40 unsigned char rs6000_align_branch_targets
42 ;; Support for -msched-costly-dep option.
44 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
46 ;; Support for -minsert-sched-nops option.
48 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
50 ;; Size of long double.
52 unsigned char rs6000_long_double_type_size
54 ;; IEEE quad extended precision long double.
56 unsigned char rs6000_ieeequad
58 ;; Nonzero to use AltiVec ABI.
60 unsigned char rs6000_altivec_abi
62 ;; Nonzero if we want SPE SIMD instructions.
66 ;; Nonzero if we want SPE ABI extensions.
68 unsigned char rs6000_spe_abi
70 ;; Nonzero if floating point operations are done in the GPRs.
72 unsigned char rs6000_float_gprs
74 ;; Nonzero if we want Darwin's struct-by-value-in-regs ABI.
76 unsigned char rs6000_darwin64_abi
78 ;; Non-zero to allow overriding loop alignment.
80 unsigned char can_override_loop_align
82 ;; Which small data model to use (for System V targets only)
84 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
86 ;; Bit size of immediate TLS offsets and string from which it is decoded.
88 int rs6000_tls_size = 32
90 ;; ABI enumeration available for subtarget to use.
92 enum rs6000_abi rs6000_current_abi = ABI_NONE
94 ;; Type of traceback to use.
96 enum rs6000_traceback_type rs6000_traceback = traceback_default
98 ;; Control alignment for fields within structures.
100 unsigned char rs6000_alignment_flags
102 ;; Code model for 64-bit linux.
104 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
106 ;; What type of reciprocal estimation instructions to generate
108 unsigned int rs6000_recip_control
110 ;; -mcpu=<xxx> as an index into the processor_target_table or -1
112 int rs6000_cpu_index = -1
114 ;; -mtune=<xxx> as an index into the processor_target_table or -1
116 int rs6000_tune_index = -1
120 unsigned int rs6000_debug
122 ;; Save for target_flags_explicit
124 int rs6000_target_flags_explicit
127 Target Report RejectNegative Mask(POWER)
128 Use POWER instruction set
131 Target Report RejectNegative
132 Do not use POWER instruction set
135 Target Report Mask(POWER2)
136 Use POWER2 instruction set
139 Target Report RejectNegative Mask(POWERPC)
140 Use PowerPC instruction set
143 Target Report RejectNegative
144 Do not use PowerPC instruction set
147 Target Report Mask(POWERPC64)
148 Use PowerPC-64 instruction set
151 Target Report Mask(PPC_GPOPT) Save
152 Use PowerPC General Purpose group optional instructions
155 Target Report Mask(PPC_GFXOPT) Save
156 Use PowerPC Graphics group optional instructions
159 Target Report Mask(MFCRF) Save
160 Use PowerPC V2.01 single field mfcr instruction
163 Target Report Mask(POPCNTB) Save
164 Use PowerPC V2.02 popcntb instruction
167 Target Report Mask(FPRND) Save
168 Use PowerPC V2.02 floating point rounding instructions
171 Target Report Mask(CMPB) Save
172 Use PowerPC V2.05 compare bytes instruction
175 Target Report Mask(MFPGPR) Save
176 Use extended PowerPC V2.05 move floating point to/from GPR instructions
179 Target Report Mask(ALTIVEC) Save
180 Use AltiVec instructions
183 Target Report Mask(DFP) Save
184 Use decimal floating point instructions
187 Target Report Mask(MULHW) Save
188 Use 4xx half-word multiply instructions
191 Target Report Mask(DLMZB) Save
192 Use 4xx string-search dlmzb instruction
195 Target Report Mask(MULTIPLE) Save
196 Generate load/store multiple instructions
199 Target Report Mask(STRING) Save
200 Generate string instructions for block moves
203 Target Report RejectNegative Mask(NEW_MNEMONICS)
204 Use new mnemonics for PowerPC architecture
207 Target Report RejectNegative InverseMask(NEW_MNEMONICS)
208 Use old mnemonics for PowerPC architecture
211 Target Report RejectNegative Mask(SOFT_FLOAT)
212 Do not use hardware floating point
215 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
216 Use hardware floating point
219 Target Report Mask(POPCNTD) Save
220 Use PowerPC V2.06 popcntd instruction
223 Target Report Var(TARGET_FRIZ) Init(-1) Save
224 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions
227 Target RejectNegative Joined Var(rs6000_veclibabi_name)
228 Vector library ABI to use
231 Target Report Mask(VSX) Save
232 Use vector/scalar (VSX) instructions
235 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1)
236 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default)
239 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY)
240 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default)
243 Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
244 ; If -mvsx, set alignment to 128 bits instead of 32/64
247 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
248 ; Allow/disallow the movmisalign in DF/DI vectors
251 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
252 ; Allow/disallow permutation of DF/DI vectors
255 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
256 ; Explicitly set/unset whether rs6000_sched_groups is set
259 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
260 ; Explicitly set/unset whether rs6000_always_hint is set
262 malign-branch-targets
263 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
264 ; Explicitly set/unset whether rs6000_align_branch_targets is set
267 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
268 ; Explicitly control whether we vectorize the builtins or not.
271 Target Report RejectNegative Mask(NO_UPDATE) Save
272 Do not generate load/store with update instructions
275 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
276 Generate load/store with update instructions
279 Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
280 Do not load the PIC register in function prologues
282 mavoid-indexed-addresses
283 Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
284 Avoid generation of indexed load/store instructions when possible
287 Target Report Var(tls_markers) Init(1) Save
288 Mark __tls_get_addr calls with argument info
291 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
294 Target Report Var(TARGET_SCHED_PROLOG) Save
295 Schedule the start and end of the procedure
298 Target Report RejectNegative Var(aix_struct_return) Save
299 Return all structures in memory (AIX default)
302 Target Report RejectNegative Var(aix_struct_return,0) Save
303 Return small structures in registers (SVR4 default)
306 Target Report Var(TARGET_XL_COMPAT) Save
307 Conform more closely to IBM XLC semantics
311 Generate software reciprocal divide and square root for better throughput.
314 Target Report RejectNegative Joined
315 Generate software reciprocal divide and square root for better throughput.
318 Target Report Mask(RECIP_PRECISION) Save
319 Assume that the reciprocal estimate instructions provide more accuracy.
322 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
323 Do not place floating point constants in TOC
326 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
327 Place floating point constants in TOC
330 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
331 Do not place symbol+offset constants in TOC
334 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
335 Place symbol+offset constants in TOC
337 ; Output only one TOC entry per module. Normally linking fails if
338 ; there are more than 16K unique variables/constants in an executable. With
339 ; this option, linking fails only if there are more than 16K modules, or
340 ; if there are more than 16K unique variables/constant in a single module.
342 ; This is at the cost of having 2 extra loads and one extra store per
343 ; function, and one less allocable register.
345 Target Report Mask(MINIMAL_TOC)
346 Use only one TOC entry per procedure
350 Put everything in the regular TOC
353 Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
354 Generate VRSAVE instructions when generating AltiVec code
357 Target RejectNegative Joined
358 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead
360 mblock-move-inline-limit=
361 Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
362 Specify how many bytes should be moved inline before calling out to memcpy/memmove
365 Target Report Mask(ISEL) Save
366 Generate isel instructions
369 Target RejectNegative Joined
370 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead
374 Generate SPE SIMD instructions on E500
377 Target Var(rs6000_paired_float) Save
378 Generate PPC750CL paired-single instructions
381 Target RejectNegative Joined
382 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead
385 Target RejectNegative Joined
386 -mdebug= Enable debug output
389 Target RejectNegative Joined
390 -mabi= Specify ABI to use
393 Target RejectNegative Joined
394 -mcpu= Use features of and schedule code for given CPU
397 Target RejectNegative Joined
398 -mtune= Schedule code for given CPU
401 Target RejectNegative Joined
402 -mtraceback= Select full, part, or no traceback table
405 Target Report Var(rs6000_default_long_calls) Save
406 Avoid all range limits on call instructions
409 Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
410 Generate Cell microcode
413 Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
414 Warn when a Cell microcoded instruction is emitted
417 Target Var(rs6000_warn_altivec_long) Init(1) Save
418 Warn about deprecated 'vector long ...' AltiVec type usage
421 Target RejectNegative Joined
422 -mfloat-gprs= Select GPR floating point method
425 Target RejectNegative Joined UInteger
426 -mlong-double-<n> Specify size of long double (64 or 128 bits)
429 Target RejectNegative Joined
430 Determine which dependences between insns are considered costly
433 Target RejectNegative Joined
434 Specify which post scheduling nop insertion scheme to apply
437 Target RejectNegative Joined
438 Specify alignment of structure fields default/natural
440 mprioritize-restricted-insns=
441 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
442 Specify scheduling priority for dispatch slot restricted insns
445 Target RejectNegative Var(rs6000_single_float) Save
446 Single-precision floating point unit
449 Target RejectNegative Var(rs6000_double_float) Save
450 Double-precision floating point unit
453 Target RejectNegative Var(rs6000_simple_fpu) Save
454 Floating point unit does not support divide & sqrt
457 Target RejectNegative Joined
458 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)
461 Target Var(rs6000_xilinx_fpu) Save