1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return 1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return 1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return 1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == CTR_REGNO
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return 1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand 0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return 1 if op is a VSX register.
43 (define_predicate "vsx_register_operand"
44 (and (match_operand 0 "register_operand")
45 (match_test "GET_CODE (op) != REG
46 || VSX_REGNO_P (REGNO (op))
47 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
49 ;; Return 1 if op is a vector register that operates on floating point vectors
50 ;; (either altivec or VSX).
51 (define_predicate "vfloat_operand"
52 (and (match_operand 0 "register_operand")
53 (match_test "GET_CODE (op) != REG
54 || VFLOAT_REGNO_P (REGNO (op))
55 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
57 ;; Return 1 if op is a vector register that operates on integer vectors
58 ;; (only altivec, VSX doesn't support integer vectors)
59 (define_predicate "vint_operand"
60 (and (match_operand 0 "register_operand")
61 (match_test "GET_CODE (op) != REG
62 || VINT_REGNO_P (REGNO (op))
63 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
65 ;; Return 1 if op is a vector register to do logical operations on (and, or,
67 (define_predicate "vlogical_operand"
68 (and (match_operand 0 "register_operand")
69 (match_test "GET_CODE (op) != REG
70 || VLOGICAL_REGNO_P (REGNO (op))
71 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
73 ;; Return 1 if op is the carry register.
74 (define_predicate "ca_operand"
75 (and (match_code "reg")
76 (match_test "CA_REGNO_P (REGNO (op))")))
78 ;; Return 1 if op is a signed 5-bit constant integer.
79 (define_predicate "s5bit_cint_operand"
80 (and (match_code "const_int")
81 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
83 ;; Return 1 if op is a unsigned 5-bit constant integer.
84 (define_predicate "u5bit_cint_operand"
85 (and (match_code "const_int")
86 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
88 ;; Return 1 if op is a signed 8-bit constant integer.
89 ;; Integer multiplication complete more quickly
90 (define_predicate "s8bit_cint_operand"
91 (and (match_code "const_int")
92 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
94 ;; Return 1 if op is a constant integer that can fit in a D field.
95 (define_predicate "short_cint_operand"
96 (and (match_code "const_int")
97 (match_test "satisfies_constraint_I (op)")))
99 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
100 (define_predicate "u_short_cint_operand"
101 (and (match_code "const_int")
102 (match_test "satisfies_constraint_K (op)")))
104 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
105 (define_predicate "non_short_cint_operand"
106 (and (match_code "const_int")
107 (match_test "(unsigned HOST_WIDE_INT)
108 (INTVAL (op) + 0x8000) >= 0x10000")))
110 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
111 (define_predicate "exact_log2_cint_operand"
112 (and (match_code "const_int")
113 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
115 ;; Return 1 if op is a register that is not special.
116 (define_predicate "gpc_reg_operand"
117 (and (match_operand 0 "register_operand")
118 (match_test "(GET_CODE (op) != REG
119 || (REGNO (op) >= ARG_POINTER_REGNUM
120 && !CA_REGNO_P (REGNO (op)))
121 || REGNO (op) < MQ_REGNO)
122 && !((TARGET_E500_DOUBLE || TARGET_SPE)
123 && invalid_e500_subreg (op, mode))")))
125 ;; Return 1 if op is a register that is a condition register field.
126 (define_predicate "cc_reg_operand"
127 (and (match_operand 0 "register_operand")
128 (match_test "GET_CODE (op) != REG
129 || REGNO (op) > LAST_VIRTUAL_REGISTER
130 || CR_REGNO_P (REGNO (op))")))
132 ;; Return 1 if op is a register that is a condition register field not cr0.
133 (define_predicate "cc_reg_not_cr0_operand"
134 (and (match_operand 0 "register_operand")
135 (match_test "GET_CODE (op) != REG
136 || REGNO (op) > LAST_VIRTUAL_REGISTER
137 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
139 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
140 (define_predicate "cc_reg_not_micro_cr0_operand"
141 (and (match_operand 0 "register_operand")
142 (match_test "GET_CODE (op) != REG
143 || REGNO (op) > LAST_VIRTUAL_REGISTER
144 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
145 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
147 ;; Return 1 if op is a constant integer valid for D field
148 ;; or non-special register register.
149 (define_predicate "reg_or_short_operand"
150 (if_then_else (match_code "const_int")
151 (match_operand 0 "short_cint_operand")
152 (match_operand 0 "gpc_reg_operand")))
154 ;; Return 1 if op is a constant integer valid whose negation is valid for
155 ;; D field or non-special register register.
156 ;; Do not allow a constant zero because all patterns that call this
157 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
158 ;; or equal to const, which does not work for zero.
159 (define_predicate "reg_or_neg_short_operand"
160 (if_then_else (match_code "const_int")
161 (match_test "satisfies_constraint_P (op)
162 && INTVAL (op) != 0")
163 (match_operand 0 "gpc_reg_operand")))
165 ;; Return 1 if op is a constant integer valid for DS field
166 ;; or non-special register.
167 (define_predicate "reg_or_aligned_short_operand"
168 (if_then_else (match_code "const_int")
169 (and (match_operand 0 "short_cint_operand")
170 (match_test "!(INTVAL (op) & 3)"))
171 (match_operand 0 "gpc_reg_operand")))
173 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
174 ;; or non-special register.
175 (define_predicate "reg_or_u_short_operand"
176 (if_then_else (match_code "const_int")
177 (match_operand 0 "u_short_cint_operand")
178 (match_operand 0 "gpc_reg_operand")))
180 ;; Return 1 if op is any constant integer
181 ;; or non-special register.
182 (define_predicate "reg_or_cint_operand"
183 (ior (match_code "const_int")
184 (match_operand 0 "gpc_reg_operand")))
186 ;; Return 1 if op is a constant integer valid for addition
187 ;; or non-special register.
188 (define_predicate "reg_or_add_cint_operand"
189 (if_then_else (match_code "const_int")
190 (match_test "(HOST_BITS_PER_WIDE_INT == 32
191 && (mode == SImode || INTVAL (op) < 0x7fff8000))
192 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
193 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
194 (match_operand 0 "gpc_reg_operand")))
196 ;; Return 1 if op is a constant integer valid for subtraction
197 ;; or non-special register.
198 (define_predicate "reg_or_sub_cint_operand"
199 (if_then_else (match_code "const_int")
200 (match_test "(HOST_BITS_PER_WIDE_INT == 32
201 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
202 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
204 ? 0x80000000 : 0x80008000))
205 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
206 (match_operand 0 "gpc_reg_operand")))
208 ;; Return 1 if op is any 32-bit unsigned constant integer
209 ;; or non-special register.
210 (define_predicate "reg_or_logical_cint_operand"
211 (if_then_else (match_code "const_int")
212 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
214 || ((INTVAL (op) & GET_MODE_MASK (mode)
215 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
216 (if_then_else (match_code "const_double")
217 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
219 && CONST_DOUBLE_HIGH (op) == 0")
220 (match_operand 0 "gpc_reg_operand"))))
222 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
223 ;; with no more than one instruction per word.
224 (define_predicate "easy_fp_constant"
225 (match_code "const_double")
230 if (GET_MODE (op) != mode
231 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
234 /* Consider all constants with -msoft-float to be easy. */
235 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
236 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
240 if (DECIMAL_FLOAT_MODE_P (mode))
243 /* If we are using V.4 style PIC, consider all constants to be hard. */
244 if (flag_pic && DEFAULT_ABI == ABI_V4)
247 #ifdef TARGET_RELOCATABLE
248 /* Similarly if we are using -mrelocatable, consider all constants
250 if (TARGET_RELOCATABLE)
257 if (TARGET_E500_DOUBLE)
260 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
261 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
263 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
264 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
265 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
266 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
269 /* The constant 0.f is easy under VSX. */
270 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
273 /* Force constants to memory before reload to utilize
274 compress_float_constant.
275 Avoid this when flag_unsafe_math_optimizations is enabled
276 because RDIV division to reciprocal optimization is not able
277 to regenerate the division. */
278 if (TARGET_E500_DOUBLE
279 || (!reload_in_progress && !reload_completed
280 && !flag_unsafe_math_optimizations))
283 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
284 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
286 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
287 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
290 /* The constant 0.f is easy. */
291 if (op == CONST0_RTX (SFmode))
294 /* Force constants to memory before reload to utilize
295 compress_float_constant.
296 Avoid this when flag_unsafe_math_optimizations is enabled
297 because RDIV division to reciprocal optimization is not able
298 to regenerate the division. */
299 if (!reload_in_progress && !reload_completed
300 && !flag_unsafe_math_optimizations)
303 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
304 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
306 return num_insns_constant_wide (k[0]) == 1;
309 return ((TARGET_POWERPC64
310 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
311 || (num_insns_constant (op, DImode) <= 2));
321 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
322 ;; vector register without using memory.
323 (define_predicate "easy_vector_constant"
324 (match_code "const_vector")
326 /* As the paired vectors are actually FPRs it seems that there is
327 no easy way to load a CONST_VECTOR without using memory. */
328 if (TARGET_PAIRED_FLOAT)
331 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
333 if (zero_constant (op, mode))
336 return easy_altivec_constant (op, mode);
339 if (SPE_VECTOR_MODE (mode))
342 if (zero_constant (op, mode))
344 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
347 /* Limit SPE vectors to 15 bits signed. These we can generate with:
352 I don't know how efficient it would be to allow bigger constants,
353 considering we'll have an extra 'ori' for every 'li'. I doubt 5
354 instructions is better than a 64-bit memory load, but I don't
355 have the e500 timing specs. */
356 if (mode == V2SImode)
358 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
359 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
360 return cst >= -0x7fff && cst <= 0x7fff
361 && cst2 >= -0x7fff && cst2 <= 0x7fff;
368 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
369 (define_predicate "easy_vector_constant_add_self"
370 (and (match_code "const_vector")
371 (and (match_test "TARGET_ALTIVEC")
372 (match_test "easy_altivec_constant (op, mode)")))
375 if (mode == V2DImode || mode == V2DFmode)
377 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
378 val = ((val & 0xff) ^ 0x80) - 0x80;
379 return EASY_VECTOR_15_ADD_SELF (val);
382 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
383 (define_predicate "easy_vector_constant_msb"
384 (and (match_code "const_vector")
385 (and (match_test "TARGET_ALTIVEC")
386 (match_test "easy_altivec_constant (op, mode)")))
389 if (mode == V2DImode || mode == V2DFmode)
391 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
392 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
395 ;; Return 1 if operand is constant zero (scalars and vectors).
396 (define_predicate "zero_constant"
397 (and (match_code "const_int,const_double,const_vector")
398 (match_test "op == CONST0_RTX (mode)")))
400 ;; Return 1 if operand is 0.0.
401 ;; or non-special register register field no cr0
402 (define_predicate "zero_fp_constant"
403 (and (match_code "const_double")
404 (match_test "SCALAR_FLOAT_MODE_P (mode)
405 && op == CONST0_RTX (mode)")))
407 ;; Return 1 if the operand is in volatile memory. Note that during the
408 ;; RTL generation phase, memory_operand does not return TRUE for volatile
409 ;; memory references. So this function allows us to recognize volatile
410 ;; references where it's safe.
411 (define_predicate "volatile_mem_operand"
412 (and (and (match_code "mem")
413 (match_test "MEM_VOLATILE_P (op)"))
414 (if_then_else (match_test "reload_completed")
415 (match_operand 0 "memory_operand")
416 (if_then_else (match_test "reload_in_progress")
417 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
418 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
420 ;; Return 1 if the operand is an offsettable memory operand.
421 (define_predicate "offsettable_mem_operand"
422 (and (match_operand 0 "memory_operand")
423 (match_test "offsettable_nonstrict_memref_p (op)")))
425 ;; Return 1 if the operand is a memory operand with an address divisible by 4
426 (define_predicate "word_offset_memref_operand"
427 (match_operand 0 "memory_operand")
429 /* Address inside MEM. */
432 /* Extract address from auto-inc/dec. */
433 if (GET_CODE (op) == PRE_INC
434 || GET_CODE (op) == PRE_DEC)
436 else if (GET_CODE (op) == PRE_MODIFY)
439 return (GET_CODE (op) != PLUS
440 || ! REG_P (XEXP (op, 0))
441 || GET_CODE (XEXP (op, 1)) != CONST_INT
442 || INTVAL (XEXP (op, 1)) % 4 == 0);
445 ;; Return 1 if the operand is an indexed or indirect memory operand.
446 (define_predicate "indexed_or_indirect_operand"
450 if (VECTOR_MEM_ALTIVEC_P (mode)
451 && GET_CODE (op) == AND
452 && GET_CODE (XEXP (op, 1)) == CONST_INT
453 && INTVAL (XEXP (op, 1)) == -16)
456 return indexed_or_indirect_address (op, mode);
459 ;; Return 1 if the operand is an indexed or indirect memory operand with an
460 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
461 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
462 ;; while VSX uses the full address and traps)
463 (define_predicate "altivec_indexed_or_indirect_operand"
467 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
468 && GET_CODE (op) == AND
469 && GET_CODE (XEXP (op, 1)) == CONST_INT
470 && INTVAL (XEXP (op, 1)) == -16)
471 return indexed_or_indirect_address (XEXP (op, 0), mode);
476 ;; Return 1 if the operand is an indexed or indirect address.
477 (define_special_predicate "indexed_or_indirect_address"
478 (and (match_test "REG_P (op)
479 || (GET_CODE (op) == PLUS
480 /* Omit testing REG_P (XEXP (op, 0)). */
481 && REG_P (XEXP (op, 1)))")
482 (match_operand 0 "address_operand")))
484 ;; Used for the destination of the fix_truncdfsi2 expander.
485 ;; If stfiwx will be used, the result goes to memory; otherwise,
486 ;; we're going to emit a store and a load of a subreg, so the dest is a
488 (define_predicate "fix_trunc_dest_operand"
489 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
490 (match_operand 0 "memory_operand")
491 (match_operand 0 "gpc_reg_operand")))
493 ;; Return 1 if the operand is either a non-special register or can be used
494 ;; as the operand of a `mode' add insn.
495 (define_predicate "add_operand"
496 (if_then_else (match_code "const_int")
497 (match_test "satisfies_constraint_I (op)
498 || satisfies_constraint_L (op)")
499 (match_operand 0 "gpc_reg_operand")))
501 ;; Return 1 if OP is a constant but not a valid add_operand.
502 (define_predicate "non_add_cint_operand"
503 (and (match_code "const_int")
504 (match_test "!satisfies_constraint_I (op)
505 && !satisfies_constraint_L (op)")))
507 ;; Return 1 if the operand is a constant that can be used as the operand
509 (define_predicate "logical_const_operand"
510 (match_code "const_int,const_double")
512 HOST_WIDE_INT opl, oph;
514 if (GET_CODE (op) == CONST_INT)
516 opl = INTVAL (op) & GET_MODE_MASK (mode);
518 if (HOST_BITS_PER_WIDE_INT <= 32
519 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
522 else if (GET_CODE (op) == CONST_DOUBLE)
524 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
526 opl = CONST_DOUBLE_LOW (op);
527 oph = CONST_DOUBLE_HIGH (op);
534 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
535 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
538 ;; Return 1 if the operand is a non-special register or a constant that
539 ;; can be used as the operand of an OR or XOR.
540 (define_predicate "logical_operand"
541 (ior (match_operand 0 "gpc_reg_operand")
542 (match_operand 0 "logical_const_operand")))
544 ;; Return 1 if op is a constant that is not a logical operand, but could
545 ;; be split into one.
546 (define_predicate "non_logical_cint_operand"
547 (and (match_code "const_int,const_double")
548 (and (not (match_operand 0 "logical_operand"))
549 (match_operand 0 "reg_or_logical_cint_operand"))))
551 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
552 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
553 ;; transitions). Reject all ones and all zeros, since these should have
554 ;; been optimized away and confuse the making of MB and ME.
555 (define_predicate "mask_operand"
556 (match_code "const_int")
558 HOST_WIDE_INT c, lsb;
562 if (TARGET_POWERPC64)
564 /* Fail if the mask is not 32-bit. */
565 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
568 /* Fail if the mask wraps around because the upper 32-bits of the
569 mask will all be 1s, contrary to GCC's internal view. */
570 if ((c & 0x80000001) == 0x80000001)
574 /* We don't change the number of transitions by inverting,
575 so make sure we start with the LS bit zero. */
579 /* Reject all zeros or all ones. */
583 /* Find the first transition. */
586 /* Invert to look for a second transition. */
589 /* Erase first transition. */
592 /* Find the second transition (if any). */
595 /* Match if all the bits above are 1's (or c is zero). */
599 ;; Return 1 for the PowerPC64 rlwinm corner case.
600 (define_predicate "mask_operand_wrap"
601 (match_code "const_int")
603 HOST_WIDE_INT c, lsb;
607 if ((c & 0x80000001) != 0x80000001)
621 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
622 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
623 ;; transition). Reject all zeros, since zero should have been
624 ;; optimized away and confuses the making of MB and ME.
625 (define_predicate "mask64_operand"
626 (match_code "const_int")
628 HOST_WIDE_INT c, lsb;
632 /* Reject all zeros. */
636 /* We don't change the number of transitions by inverting,
637 so make sure we start with the LS bit zero. */
641 /* Find the first transition. */
644 /* Match if all the bits above are 1's (or c is zero). */
648 ;; Like mask64_operand, but allow up to three transitions. This
649 ;; predicate is used by insn patterns that generate two rldicl or
650 ;; rldicr machine insns.
651 (define_predicate "mask64_2_operand"
652 (match_code "const_int")
654 HOST_WIDE_INT c, lsb;
658 /* Disallow all zeros. */
662 /* We don't change the number of transitions by inverting,
663 so make sure we start with the LS bit zero. */
667 /* Find the first transition. */
670 /* Invert to look for a second transition. */
673 /* Erase first transition. */
676 /* Find the second transition. */
679 /* Invert to look for a third transition. */
682 /* Erase second transition. */
685 /* Find the third transition (if any). */
688 /* Match if all the bits above are 1's (or c is zero). */
692 ;; Like and_operand, but also match constants that can be implemented
693 ;; with two rldicl or rldicr insns.
694 (define_predicate "and64_2_operand"
695 (ior (match_operand 0 "mask64_2_operand")
696 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
697 (match_operand 0 "gpc_reg_operand")
698 (match_operand 0 "logical_operand"))))
700 ;; Return 1 if the operand is either a non-special register or a
701 ;; constant that can be used as the operand of a logical AND.
702 (define_predicate "and_operand"
703 (ior (match_operand 0 "mask_operand")
704 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
705 (match_operand 0 "mask64_operand"))
706 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
707 (match_operand 0 "gpc_reg_operand")
708 (match_operand 0 "logical_operand")))))
710 ;; Return 1 if the operand is either a logical operand or a short cint operand.
711 (define_predicate "scc_eq_operand"
712 (ior (match_operand 0 "logical_operand")
713 (match_operand 0 "short_cint_operand")))
715 ;; Return 1 if the operand is a general non-special register or memory operand.
716 (define_predicate "reg_or_mem_operand"
717 (ior (match_operand 0 "memory_operand")
718 (ior (and (match_code "mem")
719 (match_test "macho_lo_sum_memory_operand (op, mode)"))
720 (ior (match_operand 0 "volatile_mem_operand")
721 (match_operand 0 "gpc_reg_operand")))))
723 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
724 (define_predicate "reg_or_none500mem_operand"
725 (if_then_else (match_code "mem")
726 (and (match_test "!TARGET_E500_DOUBLE")
727 (ior (match_operand 0 "memory_operand")
728 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
729 (match_operand 0 "volatile_mem_operand"))))
730 (match_operand 0 "gpc_reg_operand")))
732 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
733 (define_predicate "zero_reg_mem_operand"
734 (ior (match_operand 0 "zero_fp_constant")
735 (match_operand 0 "reg_or_mem_operand")))
737 ;; Return 1 if the operand is a general register or memory operand without
738 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
740 (define_predicate "lwa_operand"
741 (match_code "reg,subreg,mem")
743 rtx inner, addr, offset;
746 if (reload_completed && GET_CODE (inner) == SUBREG)
747 inner = SUBREG_REG (inner);
749 if (gpc_reg_operand (inner, mode))
751 if (!memory_operand (inner, mode))
753 addr = XEXP (inner, 0);
754 if (GET_CODE (addr) == PRE_INC
755 || GET_CODE (addr) == PRE_DEC
756 || (GET_CODE (addr) == PRE_MODIFY
757 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
759 if (GET_CODE (addr) == LO_SUM
760 && GET_CODE (XEXP (addr, 0)) == REG
761 && GET_CODE (XEXP (addr, 1)) == CONST)
762 addr = XEXP (XEXP (addr, 1), 0);
763 if (GET_CODE (addr) != PLUS)
765 offset = XEXP (addr, 1);
766 if (GET_CODE (offset) != CONST_INT)
768 return INTVAL (offset) % 4 == 0;
771 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
772 (define_predicate "symbol_ref_operand"
773 (and (match_code "symbol_ref")
774 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
775 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
777 ;; Return 1 if op is an operand that can be loaded via the GOT.
778 ;; or non-special register register field no cr0
779 (define_predicate "got_operand"
780 (match_code "symbol_ref,const,label_ref"))
782 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
783 ;; excluding labels involving addition.
784 (define_predicate "got_no_const_operand"
785 (match_code "symbol_ref,label_ref"))
787 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
788 (define_predicate "rs6000_tls_symbol_ref"
789 (and (match_code "symbol_ref")
790 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
792 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
793 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
794 (define_predicate "call_operand"
795 (if_then_else (match_code "reg")
796 (match_test "REGNO (op) == LR_REGNO
797 || REGNO (op) == CTR_REGNO
798 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
799 (match_code "symbol_ref")))
801 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
803 (define_predicate "current_file_function_operand"
804 (and (match_code "symbol_ref")
805 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
806 && ((SYMBOL_REF_LOCAL_P (op)
807 && (DEFAULT_ABI != ABI_AIX
808 || !SYMBOL_REF_EXTERNAL_P (op)))
809 || (op == XEXP (DECL_RTL (current_function_decl),
812 ;; Return 1 if this operand is a valid input for a move insn.
813 (define_predicate "input_operand"
814 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
815 const_double,const_vector,const_int,plus")
817 /* Memory is always valid. */
818 if (memory_operand (op, mode))
821 /* For floating-point, easy constants are valid. */
822 if (SCALAR_FLOAT_MODE_P (mode)
824 && easy_fp_constant (op, mode))
827 /* Allow any integer constant. */
828 if (GET_MODE_CLASS (mode) == MODE_INT
829 && (GET_CODE (op) == CONST_INT
830 || GET_CODE (op) == CONST_DOUBLE))
833 /* Allow easy vector constants. */
834 if (GET_CODE (op) == CONST_VECTOR
835 && easy_vector_constant (op, mode))
838 /* Do not allow invalid E500 subregs. */
839 if ((TARGET_E500_DOUBLE || TARGET_SPE)
840 && GET_CODE (op) == SUBREG
841 && invalid_e500_subreg (op, mode))
844 /* For floating-point or multi-word mode, the only remaining valid type
846 if (SCALAR_FLOAT_MODE_P (mode)
847 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
848 return register_operand (op, mode);
850 /* The only cases left are integral modes one word or smaller (we
851 do not get called for MODE_CC values). These can be in any
853 if (register_operand (op, mode))
856 /* A SYMBOL_REF referring to the TOC is valid. */
857 if (legitimate_constant_pool_address_p (op, mode, false))
860 /* A constant pool expression (relative to the TOC) is valid */
861 if (toc_relative_expr_p (op))
864 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
866 if (DEFAULT_ABI == ABI_V4
867 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
868 && small_data_operand (op, Pmode))
874 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
875 (define_predicate "splat_input_operand"
876 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
877 const_double,const_vector,const_int,plus")
883 else if (mode == DImode)
888 return input_operand (op, mode);
891 ;; Return true if OP is an invalid SUBREG operation on the e500.
892 (define_predicate "rs6000_nonimmediate_operand"
893 (match_code "reg,subreg,mem")
895 if ((TARGET_E500_DOUBLE || TARGET_SPE)
896 && GET_CODE (op) == SUBREG
897 && invalid_e500_subreg (op, mode))
900 return nonimmediate_operand (op, mode);
903 ;; Return true if operand is boolean operator.
904 (define_predicate "boolean_operator"
905 (match_code "and,ior,xor"))
907 ;; Return true if operand is OR-form of boolean operator.
908 (define_predicate "boolean_or_operator"
909 (match_code "ior,xor"))
911 ;; Return true if operand is an equality operator.
912 (define_special_predicate "equality_operator"
913 (match_code "eq,ne"))
915 ;; Return true if operand is MIN or MAX operator.
916 (define_predicate "min_max_operator"
917 (match_code "smin,smax,umin,umax"))
919 ;; Return 1 if OP is a comparison operation that is valid for a branch
920 ;; instruction. We check the opcode against the mode of the CC value.
921 ;; validate_condition_mode is an assertion.
922 (define_predicate "branch_comparison_operator"
923 (and (match_operand 0 "comparison_operator")
924 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
925 (match_test "validate_condition_mode (GET_CODE (op),
926 GET_MODE (XEXP (op, 0))),
929 (define_predicate "rs6000_cbranch_operator"
930 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
931 (match_operand 0 "ordered_comparison_operator")
932 (match_operand 0 "comparison_operator")))
934 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
935 ;; it must be a positive comparison.
936 (define_predicate "scc_comparison_operator"
937 (and (match_operand 0 "branch_comparison_operator")
938 (match_code "eq,lt,gt,ltu,gtu,unordered")))
940 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
942 (define_predicate "scc_rev_comparison_operator"
943 (and (match_operand 0 "branch_comparison_operator")
944 (match_code "ne,le,ge,leu,geu,ordered")))
946 ;; Return 1 if OP is a comparison operation that is valid for a branch
947 ;; insn, which is true if the corresponding bit in the CC register is set.
948 (define_predicate "branch_positive_comparison_operator"
949 (and (match_operand 0 "branch_comparison_operator")
950 (match_code "eq,lt,gt,ltu,gtu,unordered")))
952 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
953 (define_predicate "load_multiple_operation"
954 (match_code "parallel")
956 int count = XVECLEN (op, 0);
957 unsigned int dest_regno;
961 /* Perform a quick check so we don't blow up below. */
963 || GET_CODE (XVECEXP (op, 0, 0)) != SET
964 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
965 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
968 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
969 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
971 for (i = 1; i < count; i++)
973 rtx elt = XVECEXP (op, 0, i);
975 if (GET_CODE (elt) != SET
976 || GET_CODE (SET_DEST (elt)) != REG
977 || GET_MODE (SET_DEST (elt)) != SImode
978 || REGNO (SET_DEST (elt)) != dest_regno + i
979 || GET_CODE (SET_SRC (elt)) != MEM
980 || GET_MODE (SET_SRC (elt)) != SImode
981 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
982 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
983 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
984 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
991 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
992 ;; The second vector element is a CLOBBER.
993 (define_predicate "store_multiple_operation"
994 (match_code "parallel")
996 int count = XVECLEN (op, 0) - 1;
997 unsigned int src_regno;
1001 /* Perform a quick check so we don't blow up below. */
1003 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1004 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1005 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1008 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1009 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1011 for (i = 1; i < count; i++)
1013 rtx elt = XVECEXP (op, 0, i + 1);
1015 if (GET_CODE (elt) != SET
1016 || GET_CODE (SET_SRC (elt)) != REG
1017 || GET_MODE (SET_SRC (elt)) != SImode
1018 || REGNO (SET_SRC (elt)) != src_regno + i
1019 || GET_CODE (SET_DEST (elt)) != MEM
1020 || GET_MODE (SET_DEST (elt)) != SImode
1021 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1022 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1023 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1024 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1031 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1033 (define_predicate "save_world_operation"
1034 (match_code "parallel")
1039 int count = XVECLEN (op, 0);
1045 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1046 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1049 for (i=1; i <= 18; i++)
1051 elt = XVECEXP (op, 0, index++);
1052 if (GET_CODE (elt) != SET
1053 || GET_CODE (SET_DEST (elt)) != MEM
1054 || ! memory_operand (SET_DEST (elt), DFmode)
1055 || GET_CODE (SET_SRC (elt)) != REG
1056 || GET_MODE (SET_SRC (elt)) != DFmode)
1060 for (i=1; i <= 12; i++)
1062 elt = XVECEXP (op, 0, index++);
1063 if (GET_CODE (elt) != SET
1064 || GET_CODE (SET_DEST (elt)) != MEM
1065 || GET_CODE (SET_SRC (elt)) != REG
1066 || GET_MODE (SET_SRC (elt)) != V4SImode)
1070 for (i=1; i <= 19; i++)
1072 elt = XVECEXP (op, 0, index++);
1073 if (GET_CODE (elt) != SET
1074 || GET_CODE (SET_DEST (elt)) != MEM
1075 || ! memory_operand (SET_DEST (elt), Pmode)
1076 || GET_CODE (SET_SRC (elt)) != REG
1077 || GET_MODE (SET_SRC (elt)) != Pmode)
1081 elt = XVECEXP (op, 0, index++);
1082 if (GET_CODE (elt) != SET
1083 || GET_CODE (SET_DEST (elt)) != MEM
1084 || ! memory_operand (SET_DEST (elt), Pmode)
1085 || GET_CODE (SET_SRC (elt)) != REG
1086 || REGNO (SET_SRC (elt)) != CR2_REGNO
1087 || GET_MODE (SET_SRC (elt)) != Pmode)
1090 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1091 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1096 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1098 (define_predicate "restore_world_operation"
1099 (match_code "parallel")
1104 int count = XVECLEN (op, 0);
1110 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1111 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1112 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1113 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1116 elt = XVECEXP (op, 0, index++);
1117 if (GET_CODE (elt) != SET
1118 || GET_CODE (SET_SRC (elt)) != MEM
1119 || ! memory_operand (SET_SRC (elt), Pmode)
1120 || GET_CODE (SET_DEST (elt)) != REG
1121 || REGNO (SET_DEST (elt)) != CR2_REGNO
1122 || GET_MODE (SET_DEST (elt)) != Pmode)
1125 for (i=1; i <= 19; i++)
1127 elt = XVECEXP (op, 0, index++);
1128 if (GET_CODE (elt) != SET
1129 || GET_CODE (SET_SRC (elt)) != MEM
1130 || ! memory_operand (SET_SRC (elt), Pmode)
1131 || GET_CODE (SET_DEST (elt)) != REG
1132 || GET_MODE (SET_DEST (elt)) != Pmode)
1136 for (i=1; i <= 12; i++)
1138 elt = XVECEXP (op, 0, index++);
1139 if (GET_CODE (elt) != SET
1140 || GET_CODE (SET_SRC (elt)) != MEM
1141 || GET_CODE (SET_DEST (elt)) != REG
1142 || GET_MODE (SET_DEST (elt)) != V4SImode)
1146 for (i=1; i <= 18; i++)
1148 elt = XVECEXP (op, 0, index++);
1149 if (GET_CODE (elt) != SET
1150 || GET_CODE (SET_SRC (elt)) != MEM
1151 || ! memory_operand (SET_SRC (elt), DFmode)
1152 || GET_CODE (SET_DEST (elt)) != REG
1153 || GET_MODE (SET_DEST (elt)) != DFmode)
1157 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1158 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1159 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1160 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1161 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1166 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1167 (define_predicate "vrsave_operation"
1168 (match_code "parallel")
1170 int count = XVECLEN (op, 0);
1171 unsigned int dest_regno, src_regno;
1175 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1176 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1177 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1178 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1181 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1182 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1184 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1187 for (i = 1; i < count; i++)
1189 rtx elt = XVECEXP (op, 0, i);
1191 if (GET_CODE (elt) != CLOBBER
1192 && GET_CODE (elt) != SET)
1199 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1200 (define_predicate "mfcr_operation"
1201 (match_code "parallel")
1203 int count = XVECLEN (op, 0);
1206 /* Perform a quick check so we don't blow up below. */
1208 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1209 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1210 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1213 for (i = 0; i < count; i++)
1215 rtx exp = XVECEXP (op, 0, i);
1220 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1222 if (GET_CODE (src_reg) != REG
1223 || GET_MODE (src_reg) != CCmode
1224 || ! CR_REGNO_P (REGNO (src_reg)))
1227 if (GET_CODE (exp) != SET
1228 || GET_CODE (SET_DEST (exp)) != REG
1229 || GET_MODE (SET_DEST (exp)) != SImode
1230 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1232 unspec = SET_SRC (exp);
1233 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1235 if (GET_CODE (unspec) != UNSPEC
1236 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1237 || XVECLEN (unspec, 0) != 2
1238 || XVECEXP (unspec, 0, 0) != src_reg
1239 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1240 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1246 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1247 (define_predicate "mtcrf_operation"
1248 (match_code "parallel")
1250 int count = XVECLEN (op, 0);
1254 /* Perform a quick check so we don't blow up below. */
1256 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1257 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1258 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1260 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1262 if (GET_CODE (src_reg) != REG
1263 || GET_MODE (src_reg) != SImode
1264 || ! INT_REGNO_P (REGNO (src_reg)))
1267 for (i = 0; i < count; i++)
1269 rtx exp = XVECEXP (op, 0, i);
1273 if (GET_CODE (exp) != SET
1274 || GET_CODE (SET_DEST (exp)) != REG
1275 || GET_MODE (SET_DEST (exp)) != CCmode
1276 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1278 unspec = SET_SRC (exp);
1279 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1281 if (GET_CODE (unspec) != UNSPEC
1282 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1283 || XVECLEN (unspec, 0) != 2
1284 || XVECEXP (unspec, 0, 0) != src_reg
1285 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1286 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1292 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1293 (define_predicate "lmw_operation"
1294 (match_code "parallel")
1296 int count = XVECLEN (op, 0);
1297 unsigned int dest_regno;
1299 unsigned int base_regno;
1300 HOST_WIDE_INT offset;
1303 /* Perform a quick check so we don't blow up below. */
1305 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1306 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1307 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1310 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1311 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1314 || count != 32 - (int) dest_regno)
1317 if (legitimate_indirect_address_p (src_addr, 0))
1320 base_regno = REGNO (src_addr);
1321 if (base_regno == 0)
1324 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1326 offset = INTVAL (XEXP (src_addr, 1));
1327 base_regno = REGNO (XEXP (src_addr, 0));
1332 for (i = 0; i < count; i++)
1334 rtx elt = XVECEXP (op, 0, i);
1337 HOST_WIDE_INT newoffset;
1339 if (GET_CODE (elt) != SET
1340 || GET_CODE (SET_DEST (elt)) != REG
1341 || GET_MODE (SET_DEST (elt)) != SImode
1342 || REGNO (SET_DEST (elt)) != dest_regno + i
1343 || GET_CODE (SET_SRC (elt)) != MEM
1344 || GET_MODE (SET_SRC (elt)) != SImode)
1346 newaddr = XEXP (SET_SRC (elt), 0);
1347 if (legitimate_indirect_address_p (newaddr, 0))
1352 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1354 addr_reg = XEXP (newaddr, 0);
1355 newoffset = INTVAL (XEXP (newaddr, 1));
1359 if (REGNO (addr_reg) != base_regno
1360 || newoffset != offset + 4 * i)
1367 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1368 (define_predicate "stmw_operation"
1369 (match_code "parallel")
1371 int count = XVECLEN (op, 0);
1372 unsigned int src_regno;
1374 unsigned int base_regno;
1375 HOST_WIDE_INT offset;
1378 /* Perform a quick check so we don't blow up below. */
1380 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1381 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1382 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1385 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1386 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1389 || count != 32 - (int) src_regno)
1392 if (legitimate_indirect_address_p (dest_addr, 0))
1395 base_regno = REGNO (dest_addr);
1396 if (base_regno == 0)
1399 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1401 offset = INTVAL (XEXP (dest_addr, 1));
1402 base_regno = REGNO (XEXP (dest_addr, 0));
1407 for (i = 0; i < count; i++)
1409 rtx elt = XVECEXP (op, 0, i);
1412 HOST_WIDE_INT newoffset;
1414 if (GET_CODE (elt) != SET
1415 || GET_CODE (SET_SRC (elt)) != REG
1416 || GET_MODE (SET_SRC (elt)) != SImode
1417 || REGNO (SET_SRC (elt)) != src_regno + i
1418 || GET_CODE (SET_DEST (elt)) != MEM
1419 || GET_MODE (SET_DEST (elt)) != SImode)
1421 newaddr = XEXP (SET_DEST (elt), 0);
1422 if (legitimate_indirect_address_p (newaddr, 0))
1427 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1429 addr_reg = XEXP (newaddr, 0);
1430 newoffset = INTVAL (XEXP (newaddr, 1));
1434 if (REGNO (addr_reg) != base_regno
1435 || newoffset != offset + 4 * i)