1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by the Center for Software Science at the University
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
43 (UNSPEC_TLSLDM_PIC 11)
50 [(UNSPECV_BLOCKAGE 0) ; blockage
51 (UNSPECV_DCACHE 1) ; dcacheflush
52 (UNSPECV_ICACHE 2) ; icacheflush
53 (UNSPECV_OPC 3) ; outline_prologue_call
54 (UNSPECV_OEC 4) ; outline_epilogue_call
55 (UNSPECV_LONGJMP 5) ; builtin_longjmp
58 ;; Maximum pc-relative branch offsets.
60 ;; These numbers are a bit smaller than the maximum allowable offsets
61 ;; so that a few instructions may be inserted before the actual branch.
64 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
65 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
68 ;; Mode and code iterators
70 ;; This mode iterator allows :P to be used for patterns that operate on
71 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
72 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
74 ;; This attribute defines the condition prefix for word and double word
75 ;; add, compare, subtract and logical instructions.
76 (define_mode_attr dwc [(SI "") (DI "*")])
78 ;; Insn type. Used to default other attribute values.
80 ;; type "unary" insns have one input operand (1) and one output operand (0)
81 ;; type "binary" insns have two input operands (1,2) and one output (0)
84 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
85 (const_string "binary"))
87 (define_attr "pa_combine_type"
88 "fmpy,faddsub,uncond_branch,addmove,none"
89 (const_string "none"))
91 ;; Processor type (for scheduling, not code generation) -- this attribute
92 ;; must exactly match the processor_type enumeration in pa.h.
94 ;; FIXME: Add 800 scheduling for completeness?
96 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
98 ;; Length (in # of bytes).
99 (define_attr "length" ""
100 (cond [(eq_attr "type" "load,fpload")
101 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
102 (const_int 8) (const_int 4))
104 (eq_attr "type" "store,fpstore")
105 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
106 (const_int 8) (const_int 4))
108 (eq_attr "type" "binary,shift,nullshift")
109 (if_then_else (match_operand 2 "arith_operand" "")
110 (const_int 4) (const_int 12))
112 (eq_attr "type" "move,unary,shift,nullshift")
113 (if_then_else (match_operand 1 "arith_operand" "")
114 (const_int 4) (const_int 8))]
118 (define_asm_attributes
119 [(set_attr "length" "4")
120 (set_attr "type" "multi")])
122 ;; Attributes for instruction and branch scheduling
124 ;; For conditional branches.
125 (define_attr "in_branch_delay" "false,true"
126 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
127 (eq_attr "length" "4"))
128 (const_string "true")
129 (const_string "false")))
131 ;; Disallow instructions which use the FPU since they will tie up the FPU
132 ;; even if the instruction is nullified.
133 (define_attr "in_nullified_branch_delay" "false,true"
134 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
135 (eq_attr "length" "4"))
136 (const_string "true")
137 (const_string "false")))
139 ;; For calls and millicode calls. Allow unconditional branches in the
141 (define_attr "in_call_delay" "false,true"
142 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
143 (eq_attr "length" "4"))
144 (const_string "true")
145 (eq_attr "type" "uncond_branch")
146 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
148 (const_string "true")
149 (const_string "false"))]
150 (const_string "false")))
153 ;; Call delay slot description.
154 (define_delay (eq_attr "type" "call")
155 [(eq_attr "in_call_delay" "true") (nil) (nil)])
157 ;; Millicode call delay slot description.
158 (define_delay (eq_attr "type" "milli")
159 [(eq_attr "in_call_delay" "true") (nil) (nil)])
161 ;; Return and other similar instructions.
162 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
163 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
165 ;; Floating point conditional branch delay slot description.
166 (define_delay (eq_attr "type" "fbranch")
167 [(eq_attr "in_branch_delay" "true")
168 (eq_attr "in_nullified_branch_delay" "true")
171 ;; Integer conditional branch delay slot description.
172 ;; Nullification of conditional branches on the PA is dependent on the
173 ;; direction of the branch. Forward branches nullify true and
174 ;; backward branches nullify false. If the direction is unknown
175 ;; then nullification is not allowed.
176 (define_delay (eq_attr "type" "cbranch")
177 [(eq_attr "in_branch_delay" "true")
178 (and (eq_attr "in_nullified_branch_delay" "true")
179 (attr_flag "forward"))
180 (and (eq_attr "in_nullified_branch_delay" "true")
181 (attr_flag "backward"))])
183 (define_delay (and (eq_attr "type" "uncond_branch")
184 (eq (symbol_ref "following_call (insn)")
186 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
188 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
189 ;; load: 2, fpload: 3
190 ;; store, fpstore: 3, no D-cache operations should be scheduled.
192 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
194 ;; Instruction Time Unit Minimum Distance (unit contention)
201 ;; fmpyadd 3 ALU,MPY 2
202 ;; fmpysub 3 ALU,MPY 2
203 ;; fmpycfxt 3 ALU,MPY 2
206 ;; fdiv,sgl 10 MPY 10
207 ;; fdiv,dbl 12 MPY 12
208 ;; fsqrt,sgl 14 MPY 14
209 ;; fsqrt,dbl 18 MPY 18
211 ;; We don't model fmpyadd/fmpysub properly as those instructions
212 ;; keep both the FP ALU and MPY units busy. Given that these
213 ;; processors are obsolete, I'm not going to spend the time to
214 ;; model those instructions correctly.
216 (define_automaton "pa700")
217 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
219 (define_insn_reservation "W0" 4
220 (and (eq_attr "type" "fpcc")
221 (eq_attr "cpu" "700"))
224 (define_insn_reservation "W1" 3
225 (and (eq_attr "type" "fpalu")
226 (eq_attr "cpu" "700"))
229 (define_insn_reservation "W2" 3
230 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
231 (eq_attr "cpu" "700"))
234 (define_insn_reservation "W3" 10
235 (and (eq_attr "type" "fpdivsgl")
236 (eq_attr "cpu" "700"))
239 (define_insn_reservation "W4" 12
240 (and (eq_attr "type" "fpdivdbl")
241 (eq_attr "cpu" "700"))
244 (define_insn_reservation "W5" 14
245 (and (eq_attr "type" "fpsqrtsgl")
246 (eq_attr "cpu" "700"))
249 (define_insn_reservation "W6" 18
250 (and (eq_attr "type" "fpsqrtdbl")
251 (eq_attr "cpu" "700"))
254 (define_insn_reservation "W7" 2
255 (and (eq_attr "type" "load")
256 (eq_attr "cpu" "700"))
259 (define_insn_reservation "W8" 2
260 (and (eq_attr "type" "fpload")
261 (eq_attr "cpu" "700"))
264 (define_insn_reservation "W9" 3
265 (and (eq_attr "type" "store")
266 (eq_attr "cpu" "700"))
269 (define_insn_reservation "W10" 3
270 (and (eq_attr "type" "fpstore")
271 (eq_attr "cpu" "700"))
274 (define_insn_reservation "W11" 5
275 (and (eq_attr "type" "fpstore_load")
276 (eq_attr "cpu" "700"))
279 (define_insn_reservation "W12" 6
280 (and (eq_attr "type" "store_fpload")
281 (eq_attr "cpu" "700"))
284 (define_insn_reservation "W13" 1
285 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
286 (eq_attr "cpu" "700"))
289 ;; We have a bypass for all computations in the FP unit which feed an
290 ;; FP store as long as the sizes are the same.
291 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
292 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
293 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
294 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
295 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
297 ;; We have an "anti-bypass" for FP loads which feed an FP store.
298 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
300 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
301 ;; floating point computations with non-floating point computations (fp loads
302 ;; and stores are not fp computations).
304 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
305 ;; take two cycles, during which no Dcache operations should be scheduled.
306 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
307 ;; all have the same memory characteristics if one disregards cache misses.
309 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
310 ;; There's no value in modeling the ALU and MUL separately though
311 ;; since there can never be a functional unit conflict given the
312 ;; latency and issue rates for those units.
315 ;; Instruction Time Unit Minimum Distance (unit contention)
322 ;; fmpyadd 2 ALU,MPY 1
323 ;; fmpysub 2 ALU,MPY 1
324 ;; fmpycfxt 2 ALU,MPY 1
328 ;; fdiv,dbl 15 DIV 15
330 ;; fsqrt,dbl 15 DIV 15
332 (define_automaton "pa7100")
333 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
335 (define_insn_reservation "X0" 2
336 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
337 (eq_attr "cpu" "7100"))
340 (define_insn_reservation "X1" 8
341 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
342 (eq_attr "cpu" "7100"))
343 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
345 (define_insn_reservation "X2" 15
346 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
347 (eq_attr "cpu" "7100"))
348 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
350 (define_insn_reservation "X3" 2
351 (and (eq_attr "type" "load")
352 (eq_attr "cpu" "7100"))
355 (define_insn_reservation "X4" 2
356 (and (eq_attr "type" "fpload")
357 (eq_attr "cpu" "7100"))
360 (define_insn_reservation "X5" 2
361 (and (eq_attr "type" "store")
362 (eq_attr "cpu" "7100"))
363 "i_7100+mem_7100,mem_7100")
365 (define_insn_reservation "X6" 2
366 (and (eq_attr "type" "fpstore")
367 (eq_attr "cpu" "7100"))
368 "i_7100+mem_7100,mem_7100")
370 (define_insn_reservation "X7" 4
371 (and (eq_attr "type" "fpstore_load")
372 (eq_attr "cpu" "7100"))
373 "i_7100+mem_7100,mem_7100*3")
375 (define_insn_reservation "X8" 4
376 (and (eq_attr "type" "store_fpload")
377 (eq_attr "cpu" "7100"))
378 "i_7100+mem_7100,mem_7100*3")
380 (define_insn_reservation "X9" 1
381 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
382 (eq_attr "cpu" "7100"))
385 ;; We have a bypass for all computations in the FP unit which feed an
386 ;; FP store as long as the sizes are the same.
387 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
388 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
389 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
391 ;; We have an "anti-bypass" for FP loads which feed an FP store.
392 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
394 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
395 ;; There's no value in modeling the ALU and MUL separately though
396 ;; since there can never be a functional unit conflict that
397 ;; can be avoided given the latency, issue rates and mandatory
398 ;; one cycle cpu-wide lock for a double precision fp multiply.
401 ;; Instruction Time Unit Minimum Distance (unit contention)
408 ;; fmpyadd,sgl 2 ALU,MPY 1
409 ;; fmpyadd,dbl 3 ALU,MPY 2
410 ;; fmpysub,sgl 2 ALU,MPY 1
411 ;; fmpysub,dbl 3 ALU,MPY 2
412 ;; fmpycfxt,sgl 2 ALU,MPY 1
413 ;; fmpycfxt,dbl 3 ALU,MPY 2
418 ;; fdiv,dbl 15 DIV 15
420 ;; fsqrt,dbl 15 DIV 15
422 ;; The PA7200 is just like the PA7100LC except that there is
423 ;; no store-store penalty.
425 ;; The PA7300 is just like the PA7200 except that there is
426 ;; no store-load penalty.
428 ;; Note there are some aspects of the 7100LC we are not modeling
429 ;; at the moment. I'll be reviewing the 7100LC scheduling info
430 ;; shortly and updating this description.
434 ;; other issue modeling
436 (define_automaton "pa7100lc")
437 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
438 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
439 (define_cpu_unit "mem_7100lc" "pa7100lc")
441 ;; Double precision multiplies lock the entire CPU for one
442 ;; cycle. There is no way to avoid this lock and trying to
443 ;; schedule around the lock is pointless and thus there is no
444 ;; value in trying to model this lock.
446 ;; Not modeling the lock allows us to treat fp multiplies just
447 ;; like any other FP alu instruction. It allows for a smaller
448 ;; DFA and may reduce register pressure.
449 (define_insn_reservation "Y0" 2
450 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
451 (eq_attr "cpu" "7100LC,7200,7300"))
452 "f_7100lc,fpmac_7100lc")
454 ;; fp division and sqrt instructions lock the entire CPU for
455 ;; 7 cycles (single precision) or 14 cycles (double precision).
456 ;; There is no way to avoid this lock and trying to schedule
457 ;; around the lock is pointless and thus there is no value in
458 ;; trying to model this lock. Not modeling the lock allows
459 ;; for a smaller DFA and may reduce register pressure.
460 (define_insn_reservation "Y1" 1
461 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
462 (eq_attr "cpu" "7100LC,7200,7300"))
465 (define_insn_reservation "Y2" 2
466 (and (eq_attr "type" "load")
467 (eq_attr "cpu" "7100LC,7200,7300"))
468 "i1_7100lc+mem_7100lc")
470 (define_insn_reservation "Y3" 2
471 (and (eq_attr "type" "fpload")
472 (eq_attr "cpu" "7100LC,7200,7300"))
473 "i1_7100lc+mem_7100lc")
475 (define_insn_reservation "Y4" 2
476 (and (eq_attr "type" "store")
477 (eq_attr "cpu" "7100LC"))
478 "i1_7100lc+mem_7100lc,mem_7100lc")
480 (define_insn_reservation "Y5" 2
481 (and (eq_attr "type" "fpstore")
482 (eq_attr "cpu" "7100LC"))
483 "i1_7100lc+mem_7100lc,mem_7100lc")
485 (define_insn_reservation "Y6" 4
486 (and (eq_attr "type" "fpstore_load")
487 (eq_attr "cpu" "7100LC"))
488 "i1_7100lc+mem_7100lc,mem_7100lc*3")
490 (define_insn_reservation "Y7" 4
491 (and (eq_attr "type" "store_fpload")
492 (eq_attr "cpu" "7100LC"))
493 "i1_7100lc+mem_7100lc,mem_7100lc*3")
495 (define_insn_reservation "Y8" 1
496 (and (eq_attr "type" "shift,nullshift")
497 (eq_attr "cpu" "7100LC,7200,7300"))
500 (define_insn_reservation "Y9" 1
501 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
502 (eq_attr "cpu" "7100LC,7200,7300"))
503 "(i0_7100lc|i1_7100lc)")
505 ;; The 7200 has a store-load penalty
506 (define_insn_reservation "Y10" 2
507 (and (eq_attr "type" "store")
508 (eq_attr "cpu" "7200"))
509 "i1_7100lc,mem_7100lc")
511 (define_insn_reservation "Y11" 2
512 (and (eq_attr "type" "fpstore")
513 (eq_attr "cpu" "7200"))
514 "i1_7100lc,mem_7100lc")
516 (define_insn_reservation "Y12" 4
517 (and (eq_attr "type" "fpstore_load")
518 (eq_attr "cpu" "7200"))
519 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
521 (define_insn_reservation "Y13" 4
522 (and (eq_attr "type" "store_fpload")
523 (eq_attr "cpu" "7200"))
524 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
526 ;; The 7300 has no penalty for store-store or store-load
527 (define_insn_reservation "Y14" 2
528 (and (eq_attr "type" "store")
529 (eq_attr "cpu" "7300"))
532 (define_insn_reservation "Y15" 2
533 (and (eq_attr "type" "fpstore")
534 (eq_attr "cpu" "7300"))
537 (define_insn_reservation "Y16" 4
538 (and (eq_attr "type" "fpstore_load")
539 (eq_attr "cpu" "7300"))
540 "i1_7100lc,i1_7100lc+mem_7100lc")
542 (define_insn_reservation "Y17" 4
543 (and (eq_attr "type" "store_fpload")
544 (eq_attr "cpu" "7300"))
545 "i1_7100lc,i1_7100lc+mem_7100lc")
547 ;; We have an "anti-bypass" for FP loads which feed an FP store.
548 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
550 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
551 ;; traditional architecture.
553 ;; The PA8000 has a large (56) entry reorder buffer that is split between
554 ;; memory and non-memory operations.
556 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
557 ;; the function units, with the exception of branches and multi-output
558 ;; instructions. The PA8000 can retire two non-memory operations per cycle
559 ;; and two memory operations per cycle, only one of which may be a store.
561 ;; Given the large reorder buffer, the processor can hide most latencies.
562 ;; According to HP, they've got the best results by scheduling for retirement
563 ;; bandwidth with limited latency scheduling for floating point operations.
564 ;; Latency for integer operations and memory references is ignored.
567 ;; We claim floating point operations have a 2 cycle latency and are
568 ;; fully pipelined, except for div and sqrt which are not pipelined and
569 ;; take from 17 to 31 cycles to complete.
571 ;; It's worth noting that there is no way to saturate all the functional
572 ;; units on the PA8000 as there is not enough issue bandwidth.
574 (define_automaton "pa8000")
575 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
576 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
577 (define_cpu_unit "store_8000" "pa8000")
578 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
579 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
580 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
581 (define_reservation "im_8000" "im0_8000 | im1_8000")
582 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
583 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
584 (define_reservation "f_8000" "f0_8000 | f1_8000")
585 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
587 ;; We can issue any two memops per cycle, but we can only retire
588 ;; one memory store per cycle. We assume that the reorder buffer
589 ;; will hide any memory latencies per HP's recommendation.
590 (define_insn_reservation "Z0" 0
592 (eq_attr "type" "load,fpload")
593 (eq_attr "cpu" "8000"))
596 (define_insn_reservation "Z1" 0
598 (eq_attr "type" "store,fpstore")
599 (eq_attr "cpu" "8000"))
600 "im_8000,rm_8000+store_8000")
602 (define_insn_reservation "Z2" 0
603 (and (eq_attr "type" "fpstore_load,store_fpload")
604 (eq_attr "cpu" "8000"))
605 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
607 ;; We can issue and retire two non-memory operations per cycle with
608 ;; a few exceptions (branches). This group catches those we want
609 ;; to assume have zero latency.
610 (define_insn_reservation "Z3" 0
612 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
613 (eq_attr "cpu" "8000"))
616 ;; Branches use both slots in the non-memory issue and
618 (define_insn_reservation "Z4" 0
620 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
621 (eq_attr "cpu" "8000"))
622 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
624 ;; We partial latency schedule the floating point units.
625 ;; They can issue/retire two at a time in the non-memory
626 ;; units. We fix their latency at 2 cycles and they
627 ;; are fully pipelined.
628 (define_insn_reservation "Z5" 1
630 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
631 (eq_attr "cpu" "8000"))
632 "inm_8000,f_8000,rnm_8000")
634 ;; The fdivsqrt units are not pipelined and have a very long latency.
635 ;; To keep the DFA from exploding, we do not show all the
636 ;; reservations for the divsqrt unit.
637 (define_insn_reservation "Z6" 17
639 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
640 (eq_attr "cpu" "8000"))
641 "inm_8000,fdivsqrt_8000*6,rnm_8000")
643 (define_insn_reservation "Z7" 31
645 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
646 (eq_attr "cpu" "8000"))
647 "inm_8000,fdivsqrt_8000*6,rnm_8000")
649 ;; Operand and operator predicates and constraints
651 (include "predicates.md")
652 (include "constraints.md")
654 ;; Compare instructions.
655 ;; This controls RTL generation and register allocation.
659 (match_operator:CCFP 2 "comparison_operator"
660 [(match_operand:SF 0 "reg_or_0_operand" "fG")
661 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
662 "! TARGET_SOFT_FLOAT"
663 "fcmp,sgl,%Y2 %f0,%f1"
664 [(set_attr "length" "4")
665 (set_attr "type" "fpcc")])
669 (match_operator:CCFP 2 "comparison_operator"
670 [(match_operand:DF 0 "reg_or_0_operand" "fG")
671 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
672 "! TARGET_SOFT_FLOAT"
673 "fcmp,dbl,%Y2 %f0,%f1"
674 [(set_attr "length" "4")
675 (set_attr "type" "fpcc")])
677 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
678 ;; placeholders. This is necessary in rare situations when a
679 ;; placeholder is re-emitted (see PR 8705).
681 (define_expand "movccfp"
683 (match_operand 0 "const_int_operand" ""))]
684 "! TARGET_SOFT_FLOAT"
687 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
691 ;; The following patterns are optimization placeholders. In almost
692 ;; all cases, the user of the condition code will be simplified and the
693 ;; original condition code setting insn should be eliminated.
695 (define_insn "*movccfp0"
698 "! TARGET_SOFT_FLOAT"
699 "fcmp,dbl,= %%fr0,%%fr0"
700 [(set_attr "length" "4")
701 (set_attr "type" "fpcc")])
703 (define_insn "*movccfp1"
706 "! TARGET_SOFT_FLOAT"
707 "fcmp,dbl,!= %%fr0,%%fr0"
708 [(set_attr "length" "4")
709 (set_attr "type" "fpcc")])
713 (define_expand "cstoresi4"
714 [(set (match_operand:SI 0 "register_operand")
715 (match_operator:SI 1 "ordered_comparison_operator"
716 [(match_operand:SI 2 "reg_or_0_operand" "")
717 (match_operand:SI 3 "arith5_operand" "")]))]
721 ;; Instruction canonicalization puts immediate operands second, which
722 ;; is the reverse of what we want.
725 [(set (match_operand:SI 0 "register_operand" "=r")
726 (match_operator:SI 3 "comparison_operator"
727 [(match_operand:SI 1 "register_operand" "r")
728 (match_operand:SI 2 "arith11_operand" "rI")]))]
730 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
731 [(set_attr "type" "binary")
732 (set_attr "length" "8")])
735 [(set (match_operand:DI 0 "register_operand" "=r")
736 (match_operator:DI 3 "comparison_operator"
737 [(match_operand:DI 1 "register_operand" "r")
738 (match_operand:DI 2 "arith11_operand" "rI")]))]
740 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
741 [(set_attr "type" "binary")
742 (set_attr "length" "8")])
744 (define_insn "iorscc"
745 [(set (match_operand:SI 0 "register_operand" "=r")
746 (ior:SI (match_operator:SI 3 "comparison_operator"
747 [(match_operand:SI 1 "register_operand" "r")
748 (match_operand:SI 2 "arith11_operand" "rI")])
749 (match_operator:SI 6 "comparison_operator"
750 [(match_operand:SI 4 "register_operand" "r")
751 (match_operand:SI 5 "arith11_operand" "rI")])))]
753 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
754 [(set_attr "type" "binary")
755 (set_attr "length" "12")])
758 [(set (match_operand:DI 0 "register_operand" "=r")
759 (ior:DI (match_operator:DI 3 "comparison_operator"
760 [(match_operand:DI 1 "register_operand" "r")
761 (match_operand:DI 2 "arith11_operand" "rI")])
762 (match_operator:DI 6 "comparison_operator"
763 [(match_operand:DI 4 "register_operand" "r")
764 (match_operand:DI 5 "arith11_operand" "rI")])))]
766 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
767 [(set_attr "type" "binary")
768 (set_attr "length" "12")])
770 ;; Combiner patterns for common operations performed with the output
771 ;; from an scc insn (negscc and incscc).
772 (define_insn "negscc"
773 [(set (match_operand:SI 0 "register_operand" "=r")
774 (neg:SI (match_operator:SI 3 "comparison_operator"
775 [(match_operand:SI 1 "register_operand" "r")
776 (match_operand:SI 2 "arith11_operand" "rI")])))]
778 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
779 [(set_attr "type" "binary")
780 (set_attr "length" "8")])
783 [(set (match_operand:DI 0 "register_operand" "=r")
784 (neg:DI (match_operator:DI 3 "comparison_operator"
785 [(match_operand:DI 1 "register_operand" "r")
786 (match_operand:DI 2 "arith11_operand" "rI")])))]
788 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
789 [(set_attr "type" "binary")
790 (set_attr "length" "8")])
792 ;; Patterns for adding/subtracting the result of a boolean expression from
793 ;; a register. First we have special patterns that make use of the carry
794 ;; bit, and output only two instructions. For the cases we can't in
795 ;; general do in two instructions, the incscc pattern at the end outputs
796 ;; two or three instructions.
799 [(set (match_operand:SI 0 "register_operand" "=r")
800 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
801 (match_operand:SI 3 "arith11_operand" "rI"))
802 (match_operand:SI 1 "register_operand" "r")))]
804 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
805 [(set_attr "type" "binary")
806 (set_attr "length" "8")])
809 [(set (match_operand:DI 0 "register_operand" "=r")
810 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
811 (match_operand:DI 3 "arith11_operand" "rI"))
812 (match_operand:DI 1 "register_operand" "r")))]
814 "sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0"
815 [(set_attr "type" "binary")
816 (set_attr "length" "8")])
818 ; This need only accept registers for op3, since canonicalization
819 ; replaces geu with gtu when op3 is an integer.
821 [(set (match_operand:SI 0 "register_operand" "=r")
822 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
823 (match_operand:SI 3 "register_operand" "r"))
824 (match_operand:SI 1 "register_operand" "r")))]
826 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
827 [(set_attr "type" "binary")
828 (set_attr "length" "8")])
831 [(set (match_operand:DI 0 "register_operand" "=r")
832 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
833 (match_operand:DI 3 "register_operand" "r"))
834 (match_operand:DI 1 "register_operand" "r")))]
836 "sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0"
837 [(set_attr "type" "binary")
838 (set_attr "length" "8")])
840 ; Match only integers for op3 here. This is used as canonical form of the
841 ; geu pattern when op3 is an integer. Don't match registers since we can't
842 ; make better code than the general incscc pattern.
844 [(set (match_operand:SI 0 "register_operand" "=r")
845 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
846 (match_operand:SI 3 "int11_operand" "I"))
847 (match_operand:SI 1 "register_operand" "r")))]
849 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
850 [(set_attr "type" "binary")
851 (set_attr "length" "8")])
854 [(set (match_operand:DI 0 "register_operand" "=r")
855 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
856 (match_operand:DI 3 "int11_operand" "I"))
857 (match_operand:DI 1 "register_operand" "r")))]
859 "addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
863 (define_insn "incscc"
864 [(set (match_operand:SI 0 "register_operand" "=r,r")
865 (plus:SI (match_operator:SI 4 "comparison_operator"
866 [(match_operand:SI 2 "register_operand" "r,r")
867 (match_operand:SI 3 "arith11_operand" "rI,rI")])
868 (match_operand:SI 1 "register_operand" "0,?r")))]
871 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
872 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
873 [(set_attr "type" "binary,binary")
874 (set_attr "length" "8,12")])
877 [(set (match_operand:DI 0 "register_operand" "=r,r")
878 (plus:DI (match_operator:DI 4 "comparison_operator"
879 [(match_operand:DI 2 "register_operand" "r,r")
880 (match_operand:DI 3 "arith11_operand" "rI,rI")])
881 (match_operand:DI 1 "register_operand" "0,?r")))]
884 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
885 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
886 [(set_attr "type" "binary,binary")
887 (set_attr "length" "8,12")])
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (minus:SI (match_operand:SI 1 "register_operand" "r")
892 (gtu:SI (match_operand:SI 2 "register_operand" "r")
893 (match_operand:SI 3 "arith11_operand" "rI"))))]
895 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
900 [(set (match_operand:DI 0 "register_operand" "=r")
901 (minus:DI (match_operand:DI 1 "register_operand" "r")
902 (gtu:DI (match_operand:DI 2 "register_operand" "r")
903 (match_operand:DI 3 "arith11_operand" "rI"))))]
905 "sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0"
906 [(set_attr "type" "binary")
907 (set_attr "length" "8")])
910 [(set (match_operand:SI 0 "register_operand" "=r")
911 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
912 (gtu:SI (match_operand:SI 2 "register_operand" "r")
913 (match_operand:SI 3 "arith11_operand" "rI")))
914 (match_operand:SI 4 "register_operand" "r")))]
916 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
917 [(set_attr "type" "binary")
918 (set_attr "length" "8")])
921 [(set (match_operand:DI 0 "register_operand" "=r")
922 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
923 (gtu:DI (match_operand:DI 2 "register_operand" "r")
924 (match_operand:DI 3 "arith11_operand" "rI")))
925 (match_operand:DI 4 "register_operand" "r")))]
927 "sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0"
928 [(set_attr "type" "binary")
929 (set_attr "length" "8")])
931 ; This need only accept registers for op3, since canonicalization
932 ; replaces ltu with leu when op3 is an integer.
934 [(set (match_operand:SI 0 "register_operand" "=r")
935 (minus:SI (match_operand:SI 1 "register_operand" "r")
936 (ltu:SI (match_operand:SI 2 "register_operand" "r")
937 (match_operand:SI 3 "register_operand" "r"))))]
939 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
940 [(set_attr "type" "binary")
941 (set_attr "length" "8")])
944 [(set (match_operand:DI 0 "register_operand" "=r")
945 (minus:DI (match_operand:DI 1 "register_operand" "r")
946 (ltu:DI (match_operand:DI 2 "register_operand" "r")
947 (match_operand:DI 3 "register_operand" "r"))))]
949 "sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0"
950 [(set_attr "type" "binary")
951 (set_attr "length" "8")])
954 [(set (match_operand:SI 0 "register_operand" "=r")
955 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
956 (ltu:SI (match_operand:SI 2 "register_operand" "r")
957 (match_operand:SI 3 "register_operand" "r")))
958 (match_operand:SI 4 "register_operand" "r")))]
960 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
961 [(set_attr "type" "binary")
962 (set_attr "length" "8")])
965 [(set (match_operand:DI 0 "register_operand" "=r")
966 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
967 (ltu:DI (match_operand:DI 2 "register_operand" "r")
968 (match_operand:DI 3 "register_operand" "r")))
969 (match_operand:DI 4 "register_operand" "r")))]
971 "sub,* %2,%3,%%r0\;sub,db %1,%4,%0"
972 [(set_attr "type" "binary")
973 (set_attr "length" "8")])
975 ; Match only integers for op3 here. This is used as canonical form of the
976 ; ltu pattern when op3 is an integer. Don't match registers since we can't
977 ; make better code than the general incscc pattern.
979 [(set (match_operand:SI 0 "register_operand" "=r")
980 (minus:SI (match_operand:SI 1 "register_operand" "r")
981 (leu:SI (match_operand:SI 2 "register_operand" "r")
982 (match_operand:SI 3 "int11_operand" "I"))))]
984 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
985 [(set_attr "type" "binary")
986 (set_attr "length" "8")])
989 [(set (match_operand:DI 0 "register_operand" "=r")
990 (minus:DI (match_operand:DI 1 "register_operand" "r")
991 (leu:DI (match_operand:DI 2 "register_operand" "r")
992 (match_operand:DI 3 "int11_operand" "I"))))]
994 "addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0"
995 [(set_attr "type" "binary")
996 (set_attr "length" "8")])
999 [(set (match_operand:SI 0 "register_operand" "=r")
1000 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1001 (leu:SI (match_operand:SI 2 "register_operand" "r")
1002 (match_operand:SI 3 "int11_operand" "I")))
1003 (match_operand:SI 4 "register_operand" "r")))]
1005 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1006 [(set_attr "type" "binary")
1007 (set_attr "length" "8")])
1010 [(set (match_operand:DI 0 "register_operand" "=r")
1011 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1012 (leu:DI (match_operand:DI 2 "register_operand" "r")
1013 (match_operand:DI 3 "int11_operand" "I")))
1014 (match_operand:DI 4 "register_operand" "r")))]
1016 "addi,* %k3,%2,%%r0\;sub,db %1,%4,%0"
1017 [(set_attr "type" "binary")
1018 (set_attr "length" "8")])
1020 (define_insn "decscc"
1021 [(set (match_operand:SI 0 "register_operand" "=r,r")
1022 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1023 (match_operator:SI 4 "comparison_operator"
1024 [(match_operand:SI 2 "register_operand" "r,r")
1025 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1028 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1029 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1030 [(set_attr "type" "binary,binary")
1031 (set_attr "length" "8,12")])
1034 [(set (match_operand:DI 0 "register_operand" "=r,r")
1035 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1036 (match_operator:DI 4 "comparison_operator"
1037 [(match_operand:DI 2 "register_operand" "r,r")
1038 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1041 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1042 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1043 [(set_attr "type" "binary,binary")
1044 (set_attr "length" "8,12")])
1046 ; Patterns for max and min. (There is no need for an earlyclobber in the
1047 ; last alternative since the middle alternative will match if op0 == op1.)
1049 (define_insn "sminsi3"
1050 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1051 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1052 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1055 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1056 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1057 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1058 [(set_attr "type" "multi,multi,multi")
1059 (set_attr "length" "8,8,8")])
1061 (define_insn "smindi3"
1062 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1063 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1064 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1067 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1068 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1069 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1070 [(set_attr "type" "multi,multi,multi")
1071 (set_attr "length" "8,8,8")])
1073 (define_insn "uminsi3"
1074 [(set (match_operand:SI 0 "register_operand" "=r,r")
1075 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1076 (match_operand:SI 2 "arith11_operand" "r,I")))]
1079 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1080 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1081 [(set_attr "type" "multi,multi")
1082 (set_attr "length" "8,8")])
1084 (define_insn "umindi3"
1085 [(set (match_operand:DI 0 "register_operand" "=r,r")
1086 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1087 (match_operand:DI 2 "arith11_operand" "r,I")))]
1090 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1091 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1092 [(set_attr "type" "multi,multi")
1093 (set_attr "length" "8,8")])
1095 (define_insn "smaxsi3"
1096 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1097 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1098 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1101 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1102 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1103 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1104 [(set_attr "type" "multi,multi,multi")
1105 (set_attr "length" "8,8,8")])
1107 (define_insn "smaxdi3"
1108 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1109 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1110 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1113 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1114 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1115 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1116 [(set_attr "type" "multi,multi,multi")
1117 (set_attr "length" "8,8,8")])
1119 (define_insn "umaxsi3"
1120 [(set (match_operand:SI 0 "register_operand" "=r,r")
1121 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1122 (match_operand:SI 2 "arith11_operand" "r,I")))]
1125 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1126 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1127 [(set_attr "type" "multi,multi")
1128 (set_attr "length" "8,8")])
1130 (define_insn "umaxdi3"
1131 [(set (match_operand:DI 0 "register_operand" "=r,r")
1132 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1133 (match_operand:DI 2 "arith11_operand" "r,I")))]
1136 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1137 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1138 [(set_attr "type" "multi,multi")
1139 (set_attr "length" "8,8")])
1141 (define_insn "abssi2"
1142 [(set (match_operand:SI 0 "register_operand" "=r")
1143 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1145 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1146 [(set_attr "type" "multi")
1147 (set_attr "length" "8")])
1149 (define_insn "absdi2"
1150 [(set (match_operand:DI 0 "register_operand" "=r")
1151 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1153 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1154 [(set_attr "type" "multi")
1155 (set_attr "length" "8")])
1157 ;;; Experimental conditional move patterns
1159 (define_expand "movsicc"
1160 [(set (match_operand:SI 0 "register_operand" "")
1162 (match_operand 1 "comparison_operator" "")
1163 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1164 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1168 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1169 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1173 ;; We used to accept any register for op1.
1175 ;; However, it loses sometimes because the compiler will end up using
1176 ;; different registers for op0 and op1 in some critical cases. local-alloc
1177 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1179 ;; If/when global register allocation supports tying we should allow any
1180 ;; register for op1 again.
1182 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1184 (match_operator 2 "comparison_operator"
1185 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1186 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1187 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1191 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1192 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1193 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1194 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1195 [(set_attr "type" "multi,multi,multi,nullshift")
1196 (set_attr "length" "8,8,8,8")])
1199 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1201 (match_operator 5 "comparison_operator"
1202 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1203 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1204 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1205 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1208 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1209 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1210 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1211 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1212 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1213 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1214 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1215 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1216 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1217 (set_attr "length" "8,8,8,8,8,8,8,8")])
1219 (define_expand "movdicc"
1220 [(set (match_operand:DI 0 "register_operand" "")
1222 (match_operand 1 "comparison_operator" "")
1223 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1224 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1228 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1229 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1233 ; We need the first constraint alternative in order to avoid
1234 ; earlyclobbers on all other alternatives.
1236 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1238 (match_operator 2 "comparison_operator"
1239 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1240 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1241 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1245 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1246 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1247 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1248 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1249 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1250 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1251 (set_attr "length" "8,8,8,8,8")])
1254 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1256 (match_operator 5 "comparison_operator"
1257 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1258 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1259 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1260 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1263 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1264 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1265 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1266 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1267 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1268 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1269 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1270 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1271 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1272 (set_attr "length" "8,8,8,8,8,8,8,8")])
1274 ;; Conditional Branches
1276 (define_expand "cbranchdi4"
1278 (if_then_else (match_operator 0 "ordered_comparison_operator"
1279 [(match_operand:DI 1 "reg_or_0_operand" "")
1280 (match_operand:DI 2 "register_operand" "")])
1281 (label_ref (match_operand 3 "" ""))
1286 (define_expand "cbranchsi4"
1288 (if_then_else (match_operator 0 "ordered_comparison_operator"
1289 [(match_operand:SI 1 "reg_or_0_operand" "")
1290 (match_operand:SI 2 "arith5_operand" "")])
1291 (label_ref (match_operand 3 "" ""))
1296 (define_expand "cbranchsf4"
1298 (if_then_else (match_operator 0 "comparison_operator"
1299 [(match_operand:SF 1 "reg_or_0_operand" "")
1300 (match_operand:SF 2 "reg_or_0_operand" "")])
1301 (label_ref (match_operand 3 "" ""))
1306 emit_bcond_fp (operands);
1311 (define_expand "cbranchdf4"
1313 (if_then_else (match_operator 0 "comparison_operator"
1314 [(match_operand:DF 1 "reg_or_0_operand" "")
1315 (match_operand:DF 2 "reg_or_0_operand" "")])
1316 (label_ref (match_operand 3 "" ""))
1321 emit_bcond_fp (operands);
1325 ;; Match the branch patterns.
1328 ;; Note a long backward conditional branch with an annulled delay slot
1329 ;; has a length of 12.
1333 (match_operator 3 "comparison_operator"
1334 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1335 (match_operand:SI 2 "arith5_operand" "rL")])
1336 (label_ref (match_operand 0 "" ""))
1341 return output_cbranch (operands, 0, insn);
1343 [(set_attr "type" "cbranch")
1344 (set (attr "length")
1345 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1346 (const_int MAX_12BIT_OFFSET))
1348 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1349 (const_int MAX_17BIT_OFFSET))
1351 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1353 (eq (symbol_ref "flag_pic") (const_int 0))
1357 ;; Match the negated branch.
1362 (match_operator 3 "comparison_operator"
1363 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1364 (match_operand:SI 2 "arith5_operand" "rL")])
1366 (label_ref (match_operand 0 "" ""))))]
1370 return output_cbranch (operands, 1, insn);
1372 [(set_attr "type" "cbranch")
1373 (set (attr "length")
1374 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1375 (const_int MAX_12BIT_OFFSET))
1377 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1378 (const_int MAX_17BIT_OFFSET))
1380 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1382 (eq (symbol_ref "flag_pic") (const_int 0))
1389 (match_operator 3 "comparison_operator"
1390 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1391 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1392 (label_ref (match_operand 0 "" ""))
1397 return output_cbranch (operands, 0, insn);
1399 [(set_attr "type" "cbranch")
1400 (set (attr "length")
1401 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1402 (const_int MAX_12BIT_OFFSET))
1404 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1405 (const_int MAX_17BIT_OFFSET))
1407 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1409 (eq (symbol_ref "flag_pic") (const_int 0))
1413 ;; Match the negated branch.
1418 (match_operator 3 "comparison_operator"
1419 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1420 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1422 (label_ref (match_operand 0 "" ""))))]
1426 return output_cbranch (operands, 1, insn);
1428 [(set_attr "type" "cbranch")
1429 (set (attr "length")
1430 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1431 (const_int MAX_12BIT_OFFSET))
1433 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1434 (const_int MAX_17BIT_OFFSET))
1436 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1438 (eq (symbol_ref "flag_pic") (const_int 0))
1444 (match_operator 3 "cmpib_comparison_operator"
1445 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1446 (match_operand:DI 2 "arith5_operand" "rL")])
1447 (label_ref (match_operand 0 "" ""))
1452 return output_cbranch (operands, 0, insn);
1454 [(set_attr "type" "cbranch")
1455 (set (attr "length")
1456 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1457 (const_int MAX_12BIT_OFFSET))
1459 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1460 (const_int MAX_17BIT_OFFSET))
1462 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1464 (eq (symbol_ref "flag_pic") (const_int 0))
1468 ;; Match the negated branch.
1473 (match_operator 3 "cmpib_comparison_operator"
1474 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1475 (match_operand:DI 2 "arith5_operand" "rL")])
1477 (label_ref (match_operand 0 "" ""))))]
1481 return output_cbranch (operands, 1, insn);
1483 [(set_attr "type" "cbranch")
1484 (set (attr "length")
1485 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1486 (const_int MAX_12BIT_OFFSET))
1488 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1489 (const_int MAX_17BIT_OFFSET))
1491 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1493 (eq (symbol_ref "flag_pic") (const_int 0))
1497 ;; Branch on Bit patterns.
1501 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1503 (match_operand:SI 1 "uint5_operand" ""))
1505 (label_ref (match_operand 2 "" ""))
1510 return output_bb (operands, 0, insn, 0);
1512 [(set_attr "type" "cbranch")
1513 (set (attr "length")
1514 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1515 (const_int MAX_12BIT_OFFSET))
1517 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1518 (const_int MAX_17BIT_OFFSET))
1520 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1522 (eq (symbol_ref "flag_pic") (const_int 0))
1529 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1531 (match_operand:DI 1 "uint32_operand" ""))
1533 (label_ref (match_operand 2 "" ""))
1538 return output_bb (operands, 0, insn, 0);
1540 [(set_attr "type" "cbranch")
1541 (set (attr "length")
1542 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1543 (const_int MAX_12BIT_OFFSET))
1545 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1546 (const_int MAX_17BIT_OFFSET))
1548 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1550 (eq (symbol_ref "flag_pic") (const_int 0))
1557 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1559 (match_operand:SI 1 "uint5_operand" ""))
1562 (label_ref (match_operand 2 "" ""))))]
1566 return output_bb (operands, 1, insn, 0);
1568 [(set_attr "type" "cbranch")
1569 (set (attr "length")
1570 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1571 (const_int MAX_12BIT_OFFSET))
1573 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1574 (const_int MAX_17BIT_OFFSET))
1576 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1578 (eq (symbol_ref "flag_pic") (const_int 0))
1585 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1587 (match_operand:DI 1 "uint32_operand" ""))
1590 (label_ref (match_operand 2 "" ""))))]
1594 return output_bb (operands, 1, insn, 0);
1596 [(set_attr "type" "cbranch")
1597 (set (attr "length")
1598 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1599 (const_int MAX_12BIT_OFFSET))
1601 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1602 (const_int MAX_17BIT_OFFSET))
1604 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1606 (eq (symbol_ref "flag_pic") (const_int 0))
1613 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1615 (match_operand:SI 1 "uint5_operand" ""))
1617 (label_ref (match_operand 2 "" ""))
1622 return output_bb (operands, 0, insn, 1);
1624 [(set_attr "type" "cbranch")
1625 (set (attr "length")
1626 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1627 (const_int MAX_12BIT_OFFSET))
1629 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1630 (const_int MAX_17BIT_OFFSET))
1632 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1634 (eq (symbol_ref "flag_pic") (const_int 0))
1641 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1643 (match_operand:DI 1 "uint32_operand" ""))
1645 (label_ref (match_operand 2 "" ""))
1650 return output_bb (operands, 0, insn, 1);
1652 [(set_attr "type" "cbranch")
1653 (set (attr "length")
1654 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1655 (const_int MAX_12BIT_OFFSET))
1657 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1658 (const_int MAX_17BIT_OFFSET))
1660 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1662 (eq (symbol_ref "flag_pic") (const_int 0))
1669 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1671 (match_operand:SI 1 "uint5_operand" ""))
1674 (label_ref (match_operand 2 "" ""))))]
1678 return output_bb (operands, 1, insn, 1);
1680 [(set_attr "type" "cbranch")
1681 (set (attr "length")
1682 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1683 (const_int MAX_12BIT_OFFSET))
1685 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1686 (const_int MAX_17BIT_OFFSET))
1688 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1690 (eq (symbol_ref "flag_pic") (const_int 0))
1697 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1699 (match_operand:DI 1 "uint32_operand" ""))
1702 (label_ref (match_operand 2 "" ""))))]
1706 return output_bb (operands, 1, insn, 1);
1708 [(set_attr "type" "cbranch")
1709 (set (attr "length")
1710 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1711 (const_int MAX_12BIT_OFFSET))
1713 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1714 (const_int MAX_17BIT_OFFSET))
1716 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1718 (eq (symbol_ref "flag_pic") (const_int 0))
1722 ;; Branch on Variable Bit patterns.
1726 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1728 (match_operand:SI 1 "register_operand" "q"))
1730 (label_ref (match_operand 2 "" ""))
1735 return output_bvb (operands, 0, insn, 0);
1737 [(set_attr "type" "cbranch")
1738 (set (attr "length")
1739 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1740 (const_int MAX_12BIT_OFFSET))
1742 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1743 (const_int MAX_17BIT_OFFSET))
1745 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1747 (eq (symbol_ref "flag_pic") (const_int 0))
1754 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1756 (match_operand:DI 1 "register_operand" "q"))
1758 (label_ref (match_operand 2 "" ""))
1763 return output_bvb (operands, 0, insn, 0);
1765 [(set_attr "type" "cbranch")
1766 (set (attr "length")
1767 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1768 (const_int MAX_12BIT_OFFSET))
1770 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1771 (const_int MAX_17BIT_OFFSET))
1773 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1775 (eq (symbol_ref "flag_pic") (const_int 0))
1782 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1784 (match_operand:SI 1 "register_operand" "q"))
1787 (label_ref (match_operand 2 "" ""))))]
1791 return output_bvb (operands, 1, insn, 0);
1793 [(set_attr "type" "cbranch")
1794 (set (attr "length")
1795 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1796 (const_int MAX_12BIT_OFFSET))
1798 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1799 (const_int MAX_17BIT_OFFSET))
1801 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1810 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1812 (match_operand:DI 1 "register_operand" "q"))
1815 (label_ref (match_operand 2 "" ""))))]
1819 return output_bvb (operands, 1, insn, 0);
1821 [(set_attr "type" "cbranch")
1822 (set (attr "length")
1823 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1824 (const_int MAX_12BIT_OFFSET))
1826 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1827 (const_int MAX_17BIT_OFFSET))
1829 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1838 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1840 (match_operand:SI 1 "register_operand" "q"))
1842 (label_ref (match_operand 2 "" ""))
1847 return output_bvb (operands, 0, insn, 1);
1849 [(set_attr "type" "cbranch")
1850 (set (attr "length")
1851 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1852 (const_int MAX_12BIT_OFFSET))
1854 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1855 (const_int MAX_17BIT_OFFSET))
1857 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1859 (eq (symbol_ref "flag_pic") (const_int 0))
1866 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1868 (match_operand:DI 1 "register_operand" "q"))
1870 (label_ref (match_operand 2 "" ""))
1875 return output_bvb (operands, 0, insn, 1);
1877 [(set_attr "type" "cbranch")
1878 (set (attr "length")
1879 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1880 (const_int MAX_12BIT_OFFSET))
1882 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (const_int MAX_17BIT_OFFSET))
1885 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1887 (eq (symbol_ref "flag_pic") (const_int 0))
1894 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1896 (match_operand:SI 1 "register_operand" "q"))
1899 (label_ref (match_operand 2 "" ""))))]
1903 return output_bvb (operands, 1, insn, 1);
1905 [(set_attr "type" "cbranch")
1906 (set (attr "length")
1907 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1908 (const_int MAX_12BIT_OFFSET))
1910 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1911 (const_int MAX_17BIT_OFFSET))
1913 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1915 (eq (symbol_ref "flag_pic") (const_int 0))
1922 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1924 (match_operand:DI 1 "register_operand" "q"))
1927 (label_ref (match_operand 2 "" ""))))]
1931 return output_bvb (operands, 1, insn, 1);
1933 [(set_attr "type" "cbranch")
1934 (set (attr "length")
1935 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1936 (const_int MAX_12BIT_OFFSET))
1938 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1939 (const_int MAX_17BIT_OFFSET))
1941 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1943 (eq (symbol_ref "flag_pic") (const_int 0))
1947 ;; Floating point branches
1949 ;; ??? Nullification is handled differently from other branches.
1950 ;; If nullification is specified, the delay slot is nullified on any
1951 ;; taken branch regardless of branch direction.
1953 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1954 (label_ref (match_operand 0 "" ""))
1956 "!TARGET_SOFT_FLOAT"
1959 int length = get_attr_length (insn);
1961 int nullify, xdelay;
1964 return \"ftest\;b%* %l0\";
1966 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
1970 xoperands[0] = GEN_INT (length - 8);
1976 xoperands[0] = GEN_INT (length - 4);
1980 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
1982 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
1983 return output_lbranch (operands[0], insn, xdelay);
1985 [(set_attr "type" "fbranch")
1986 (set (attr "length")
1987 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1988 (const_int MAX_17BIT_OFFSET))
1990 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1992 (eq (symbol_ref "flag_pic") (const_int 0))
1997 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1999 (label_ref (match_operand 0 "" ""))))]
2000 "!TARGET_SOFT_FLOAT"
2003 int length = get_attr_length (insn);
2005 int nullify, xdelay;
2008 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2010 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2014 xoperands[0] = GEN_INT (length - 4);
2020 xoperands[0] = GEN_INT (length);
2024 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2026 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2027 return output_lbranch (operands[0], insn, xdelay);
2029 [(set_attr "type" "fbranch")
2030 (set (attr "length")
2031 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2032 (const_int MAX_17BIT_OFFSET))
2034 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2036 (eq (symbol_ref "flag_pic") (const_int 0))
2040 ;; Move instructions
2042 (define_expand "movsi"
2043 [(set (match_operand:SI 0 "general_operand" "")
2044 (match_operand:SI 1 "general_operand" ""))]
2048 if (emit_move_sequence (operands, SImode, 0))
2052 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2053 (define_expand "reload_insi_r1"
2054 [(set (match_operand:SI 0 "register_operand" "=Z")
2055 (match_operand:SI 1 "non_hard_reg_operand" ""))
2056 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2060 if (emit_move_sequence (operands, SImode, operands[2]))
2063 /* We don't want the clobber emitted, so handle this ourselves. */
2064 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2068 ;; Handle SImode input reloads requiring a general register as a
2069 ;; scratch register.
2070 (define_expand "reload_insi"
2071 [(set (match_operand:SI 0 "register_operand" "=Z")
2072 (match_operand:SI 1 "non_hard_reg_operand" ""))
2073 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2077 if (emit_move_sequence (operands, SImode, operands[2]))
2080 /* We don't want the clobber emitted, so handle this ourselves. */
2081 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2085 ;; Handle SImode output reloads requiring a general register as a
2086 ;; scratch register.
2087 (define_expand "reload_outsi"
2088 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2089 (match_operand:SI 1 "register_operand" "Z"))
2090 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2094 if (emit_move_sequence (operands, SImode, operands[2]))
2097 /* We don't want the clobber emitted, so handle this ourselves. */
2098 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2103 [(set (match_operand:SI 0 "move_dest_operand"
2104 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2105 (match_operand:SI 1 "move_src_operand"
2106 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2107 "(register_operand (operands[0], SImode)
2108 || reg_or_0_operand (operands[1], SImode))
2109 && !TARGET_SOFT_FLOAT
2116 {zdepi|depwi,z} %Z1,%0
2120 {mfctl|mfctl,w} %%sar,%0
2124 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2125 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2126 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2127 (set_attr "pa_combine_type" "addmove")
2128 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2131 [(set (match_operand:SI 0 "move_dest_operand"
2132 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2133 (match_operand:SI 1 "move_src_operand"
2134 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2135 "(register_operand (operands[0], SImode)
2136 || reg_or_0_operand (operands[1], SImode))
2137 && !TARGET_SOFT_FLOAT
2144 {zdepi|depwi,z} %Z1,%0
2148 {mfctl|mfctl,w} %%sar,%0
2152 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2153 (set_attr "pa_combine_type" "addmove")
2154 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2157 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2158 (match_operand:SI 1 "register_operand" "f"))]
2160 && !TARGET_DISABLE_INDEXING
2161 && reload_completed"
2163 [(set_attr "type" "fpstore")
2164 (set_attr "pa_combine_type" "addmove")
2165 (set_attr "length" "4")])
2167 ; Rewrite RTL using an indexed store. This will allow the insn that
2168 ; computes the address to be deleted if the register it sets is dead.
2170 [(set (match_operand:SI 0 "register_operand" "")
2171 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2173 (match_operand:SI 2 "register_operand" "")))
2174 (set (mem:SI (match_dup 0))
2175 (match_operand:SI 3 "register_operand" ""))]
2177 && !TARGET_DISABLE_INDEXING
2178 && REG_OK_FOR_BASE_P (operands[2])
2179 && FP_REGNO_P (REGNO (operands[3]))"
2180 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2182 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2187 [(set (match_operand:SI 0 "register_operand" "")
2188 (plus:SI (match_operand:SI 2 "register_operand" "")
2189 (mult:SI (match_operand:SI 1 "register_operand" "")
2191 (set (mem:SI (match_dup 0))
2192 (match_operand:SI 3 "register_operand" ""))]
2194 && !TARGET_DISABLE_INDEXING
2195 && REG_OK_FOR_BASE_P (operands[2])
2196 && FP_REGNO_P (REGNO (operands[3]))"
2197 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2199 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2204 [(set (match_operand:DI 0 "register_operand" "")
2205 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2207 (match_operand:DI 2 "register_operand" "")))
2208 (set (mem:SI (match_dup 0))
2209 (match_operand:SI 3 "register_operand" ""))]
2211 && !TARGET_DISABLE_INDEXING
2213 && REG_OK_FOR_BASE_P (operands[2])
2214 && FP_REGNO_P (REGNO (operands[3]))"
2215 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2217 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2222 [(set (match_operand:DI 0 "register_operand" "")
2223 (plus:DI (match_operand:DI 2 "register_operand" "")
2224 (mult:DI (match_operand:DI 1 "register_operand" "")
2226 (set (mem:SI (match_dup 0))
2227 (match_operand:SI 3 "register_operand" ""))]
2229 && !TARGET_DISABLE_INDEXING
2231 && REG_OK_FOR_BASE_P (operands[2])
2232 && FP_REGNO_P (REGNO (operands[3]))"
2233 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2235 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2240 [(set (match_operand:SI 0 "register_operand" "")
2241 (plus:SI (match_operand:SI 1 "register_operand" "")
2242 (match_operand:SI 2 "register_operand" "")))
2243 (set (mem:SI (match_dup 0))
2244 (match_operand:SI 3 "register_operand" ""))]
2246 && !TARGET_DISABLE_INDEXING
2247 && TARGET_NO_SPACE_REGS
2248 && REG_OK_FOR_INDEX_P (operands[1])
2249 && REG_OK_FOR_BASE_P (operands[2])
2250 && FP_REGNO_P (REGNO (operands[3]))"
2251 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2253 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2257 [(set (match_operand:SI 0 "register_operand" "")
2258 (plus:SI (match_operand:SI 1 "register_operand" "")
2259 (match_operand:SI 2 "register_operand" "")))
2260 (set (mem:SI (match_dup 0))
2261 (match_operand:SI 3 "register_operand" ""))]
2263 && !TARGET_DISABLE_INDEXING
2264 && TARGET_NO_SPACE_REGS
2265 && REG_OK_FOR_BASE_P (operands[1])
2266 && REG_OK_FOR_INDEX_P (operands[2])
2267 && FP_REGNO_P (REGNO (operands[3]))"
2268 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2270 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2274 [(set (match_operand:DI 0 "register_operand" "")
2275 (plus:DI (match_operand:DI 1 "register_operand" "")
2276 (match_operand:DI 2 "register_operand" "")))
2277 (set (mem:SI (match_dup 0))
2278 (match_operand:SI 3 "register_operand" ""))]
2280 && !TARGET_DISABLE_INDEXING
2282 && TARGET_NO_SPACE_REGS
2283 && REG_OK_FOR_INDEX_P (operands[1])
2284 && REG_OK_FOR_BASE_P (operands[2])
2285 && FP_REGNO_P (REGNO (operands[3]))"
2286 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2288 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2292 [(set (match_operand:DI 0 "register_operand" "")
2293 (plus:DI (match_operand:DI 1 "register_operand" "")
2294 (match_operand:DI 2 "register_operand" "")))
2295 (set (mem:SI (match_dup 0))
2296 (match_operand:SI 3 "register_operand" ""))]
2298 && !TARGET_DISABLE_INDEXING
2300 && TARGET_NO_SPACE_REGS
2301 && REG_OK_FOR_BASE_P (operands[1])
2302 && REG_OK_FOR_INDEX_P (operands[2])
2303 && FP_REGNO_P (REGNO (operands[3]))"
2304 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2306 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2310 [(set (match_operand:SI 0 "move_dest_operand"
2311 "=r,r,r,r,r,r,Q,!*q,!r")
2312 (match_operand:SI 1 "move_src_operand"
2313 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2314 "(register_operand (operands[0], SImode)
2315 || reg_or_0_operand (operands[1], SImode))
2316 && TARGET_SOFT_FLOAT"
2322 {zdepi|depwi,z} %Z1,%0
2326 {mfctl|mfctl,w} %%sar,%0"
2327 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2328 (set_attr "pa_combine_type" "addmove")
2329 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2331 ;; Load or store with base-register modification.
2333 [(set (match_operand:SI 0 "register_operand" "=r")
2334 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2335 (match_operand:DI 2 "int5_operand" "L"))))
2337 (plus:DI (match_dup 1) (match_dup 2)))]
2340 [(set_attr "type" "load")
2341 (set_attr "length" "4")])
2343 ; And a zero extended variant.
2345 [(set (match_operand:DI 0 "register_operand" "=r")
2346 (zero_extend:DI (mem:SI
2348 (match_operand:DI 1 "register_operand" "+r")
2349 (match_operand:DI 2 "int5_operand" "L")))))
2351 (plus:DI (match_dup 1) (match_dup 2)))]
2354 [(set_attr "type" "load")
2355 (set_attr "length" "4")])
2357 (define_expand "pre_load"
2358 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2359 (mem (plus (match_operand 1 "register_operand" "")
2360 (match_operand 2 "pre_cint_operand" ""))))
2362 (plus (match_dup 1) (match_dup 2)))])]
2368 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2371 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2375 (define_insn "pre_ldw"
2376 [(set (match_operand:SI 0 "register_operand" "=r")
2377 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2378 (match_operand:SI 2 "pre_cint_operand" ""))))
2380 (plus:SI (match_dup 1) (match_dup 2)))]
2384 if (INTVAL (operands[2]) < 0)
2385 return \"{ldwm|ldw,mb} %2(%1),%0\";
2386 return \"{ldws|ldw},mb %2(%1),%0\";
2388 [(set_attr "type" "load")
2389 (set_attr "length" "4")])
2391 (define_insn "pre_ldd"
2392 [(set (match_operand:DI 0 "register_operand" "=r")
2393 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2394 (match_operand:DI 2 "pre_cint_operand" ""))))
2396 (plus:DI (match_dup 1) (match_dup 2)))]
2399 [(set_attr "type" "load")
2400 (set_attr "length" "4")])
2403 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2404 (match_operand:SI 1 "pre_cint_operand" "")))
2405 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2407 (plus:SI (match_dup 0) (match_dup 1)))]
2411 if (INTVAL (operands[1]) < 0)
2412 return \"{stwm|stw,mb} %r2,%1(%0)\";
2413 return \"{stws|stw},mb %r2,%1(%0)\";
2415 [(set_attr "type" "store")
2416 (set_attr "length" "4")])
2419 [(set (match_operand:SI 0 "register_operand" "=r")
2420 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2422 (plus:SI (match_dup 1)
2423 (match_operand:SI 2 "post_cint_operand" "")))]
2427 if (INTVAL (operands[2]) > 0)
2428 return \"{ldwm|ldw,ma} %2(%1),%0\";
2429 return \"{ldws|ldw},ma %2(%1),%0\";
2431 [(set_attr "type" "load")
2432 (set_attr "length" "4")])
2434 (define_expand "post_store"
2435 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2436 (match_operand 1 "reg_or_0_operand" ""))
2439 (match_operand 2 "post_cint_operand" "")))])]
2445 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2448 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2452 (define_insn "post_stw"
2453 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2454 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2456 (plus:SI (match_dup 0)
2457 (match_operand:SI 2 "post_cint_operand" "")))]
2461 if (INTVAL (operands[2]) > 0)
2462 return \"{stwm|stw,ma} %r1,%2(%0)\";
2463 return \"{stws|stw},ma %r1,%2(%0)\";
2465 [(set_attr "type" "store")
2466 (set_attr "length" "4")])
2468 (define_insn "post_std"
2469 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2470 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2472 (plus:DI (match_dup 0)
2473 (match_operand:DI 2 "post_cint_operand" "")))]
2476 [(set_attr "type" "store")
2477 (set_attr "length" "4")])
2479 ;; For loading the address of a label while generating PIC code.
2480 ;; Note since this pattern can be created at reload time (via movsi), all
2481 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2483 [(set (match_operand 0 "pmode_register_operand" "=a")
2484 (match_operand 1 "pic_label_operand" ""))]
2490 xoperands[0] = operands[0];
2491 xoperands[1] = operands[1];
2492 xoperands[2] = gen_label_rtx ();
2494 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2495 CODE_LABEL_NUMBER (xoperands[2]));
2496 output_asm_insn (\"mfia %0\", xoperands);
2498 /* If we're trying to load the address of a label that happens to be
2499 close, then we can use a shorter sequence. */
2500 if (GET_CODE (operands[1]) == LABEL_REF
2501 && !LABEL_REF_NONLOCAL_P (operands[1])
2502 && INSN_ADDRESSES_SET_P ()
2503 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2504 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2505 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2508 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2509 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2513 [(set_attr "type" "multi")
2514 (set_attr "length" "12")]) ; 8 or 12
2517 [(set (match_operand 0 "pmode_register_operand" "=a")
2518 (match_operand 1 "pic_label_operand" ""))]
2524 xoperands[0] = operands[0];
2525 xoperands[1] = operands[1];
2526 xoperands[2] = gen_label_rtx ();
2528 output_asm_insn (\"bl .+8,%0\", xoperands);
2529 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2530 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2531 CODE_LABEL_NUMBER (xoperands[2]));
2533 /* If we're trying to load the address of a label that happens to be
2534 close, then we can use a shorter sequence. */
2535 if (GET_CODE (operands[1]) == LABEL_REF
2536 && !LABEL_REF_NONLOCAL_P (operands[1])
2537 && INSN_ADDRESSES_SET_P ()
2538 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2539 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2540 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2543 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2544 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2548 [(set_attr "type" "multi")
2549 (set_attr "length" "16")]) ; 12 or 16
2552 [(set (match_operand:SI 0 "register_operand" "=a")
2553 (plus:SI (match_operand:SI 1 "register_operand" "r")
2554 (high:SI (match_operand 2 "" ""))))]
2555 "symbolic_operand (operands[2], Pmode)
2556 && ! function_label_operand (operands[2], Pmode)
2559 [(set_attr "type" "binary")
2560 (set_attr "length" "4")])
2563 [(set (match_operand:DI 0 "register_operand" "=a")
2564 (plus:DI (match_operand:DI 1 "register_operand" "r")
2565 (high:DI (match_operand 2 "" ""))))]
2566 "symbolic_operand (operands[2], Pmode)
2567 && ! function_label_operand (operands[2], Pmode)
2571 [(set_attr "type" "binary")
2572 (set_attr "length" "4")])
2574 ;; Always use addil rather than ldil;add sequences. This allows the
2575 ;; HP linker to eliminate the dp relocation if the symbolic operand
2576 ;; lives in the TEXT space.
2578 [(set (match_operand:SI 0 "register_operand" "=a")
2579 (high:SI (match_operand 1 "" "")))]
2580 "symbolic_operand (operands[1], Pmode)
2581 && ! function_label_operand (operands[1], Pmode)
2582 && ! read_only_operand (operands[1], Pmode)
2586 if (TARGET_LONG_LOAD_STORE)
2587 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2589 return \"addil LR'%H1,%%r27\";
2591 [(set_attr "type" "binary")
2592 (set (attr "length")
2593 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2598 ;; This is for use in the prologue/epilogue code. We need it
2599 ;; to add large constants to a stack pointer or frame pointer.
2600 ;; Because of the additional %r1 pressure, we probably do not
2601 ;; want to use this in general code, so make it available
2602 ;; only after reload.
2604 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2605 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2606 (high:SI (match_operand 2 "const_int_operand" ""))))]
2610 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2611 [(set_attr "type" "binary,binary")
2612 (set_attr "length" "4,8")])
2615 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2616 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2617 (high:DI (match_operand 2 "const_int_operand" ""))))]
2618 "reload_completed && TARGET_64BIT"
2621 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2622 [(set_attr "type" "binary,binary")
2623 (set_attr "length" "4,8")])
2626 [(set (match_operand:SI 0 "register_operand" "=r")
2627 (high:SI (match_operand 1 "" "")))]
2628 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2629 && !is_function_label_plus_const (operands[1])"
2632 if (symbolic_operand (operands[1], Pmode))
2633 return \"ldil LR'%H1,%0\";
2635 return \"ldil L'%G1,%0\";
2637 [(set_attr "type" "move")
2638 (set_attr "length" "4")])
2641 [(set (match_operand:DI 0 "register_operand" "=r")
2642 (high:DI (match_operand 1 "const_int_operand" "")))]
2645 [(set_attr "type" "move")
2646 (set_attr "length" "4")])
2649 [(set (match_operand:DI 0 "register_operand" "=r")
2650 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2651 (match_operand:DI 2 "const_int_operand" "i")))]
2654 [(set_attr "type" "move")
2655 (set_attr "length" "4")])
2658 [(set (match_operand:SI 0 "register_operand" "=r")
2659 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2660 (match_operand:SI 2 "immediate_operand" "i")))]
2661 "!is_function_label_plus_const (operands[2])"
2664 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2666 if (symbolic_operand (operands[2], Pmode))
2667 return \"ldo RR'%G2(%1),%0\";
2669 return \"ldo R'%G2(%1),%0\";
2671 [(set_attr "type" "move")
2672 (set_attr "length" "4")])
2674 ;; Now that a symbolic_address plus a constant is broken up early
2675 ;; in the compilation phase (for better CSE) we need a special
2676 ;; combiner pattern to load the symbolic address plus the constant
2677 ;; in only 2 instructions. (For cases where the symbolic address
2678 ;; was not a common subexpression.)
2680 [(set (match_operand:SI 0 "register_operand" "")
2681 (match_operand:SI 1 "symbolic_operand" ""))
2682 (clobber (match_operand:SI 2 "register_operand" ""))]
2683 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2684 [(set (match_dup 2) (high:SI (match_dup 1)))
2685 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2688 ;; hppa_legitimize_address goes to a great deal of trouble to
2689 ;; create addresses which use indexing. In some cases, this
2690 ;; is a lose because there isn't any store instructions which
2691 ;; allow indexed addresses (with integer register source).
2693 ;; These define_splits try to turn a 3 insn store into
2694 ;; a 2 insn store with some creative RTL rewriting.
2696 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2697 (match_operand:SI 1 "shadd_operand" ""))
2698 (plus:SI (match_operand:SI 2 "register_operand" "")
2699 (match_operand:SI 3 "const_int_operand" ""))))
2700 (match_operand:SI 4 "register_operand" ""))
2701 (clobber (match_operand:SI 5 "register_operand" ""))]
2703 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2705 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2709 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2710 (match_operand:SI 1 "shadd_operand" ""))
2711 (plus:SI (match_operand:SI 2 "register_operand" "")
2712 (match_operand:SI 3 "const_int_operand" ""))))
2713 (match_operand:HI 4 "register_operand" ""))
2714 (clobber (match_operand:SI 5 "register_operand" ""))]
2716 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2718 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2722 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2723 (match_operand:SI 1 "shadd_operand" ""))
2724 (plus:SI (match_operand:SI 2 "register_operand" "")
2725 (match_operand:SI 3 "const_int_operand" ""))))
2726 (match_operand:QI 4 "register_operand" ""))
2727 (clobber (match_operand:SI 5 "register_operand" ""))]
2729 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2731 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2734 (define_expand "movhi"
2735 [(set (match_operand:HI 0 "general_operand" "")
2736 (match_operand:HI 1 "general_operand" ""))]
2740 if (emit_move_sequence (operands, HImode, 0))
2744 ;; Handle HImode input reloads requiring a general register as a
2745 ;; scratch register.
2746 (define_expand "reload_inhi"
2747 [(set (match_operand:HI 0 "register_operand" "=Z")
2748 (match_operand:HI 1 "non_hard_reg_operand" ""))
2749 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2753 if (emit_move_sequence (operands, HImode, operands[2]))
2756 /* We don't want the clobber emitted, so handle this ourselves. */
2757 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2761 ;; Handle HImode output reloads requiring a general register as a
2762 ;; scratch register.
2763 (define_expand "reload_outhi"
2764 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2765 (match_operand:HI 1 "register_operand" "Z"))
2766 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2770 if (emit_move_sequence (operands, HImode, operands[2]))
2773 /* We don't want the clobber emitted, so handle this ourselves. */
2774 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2779 [(set (match_operand:HI 0 "move_dest_operand"
2780 "=r,r,r,r,r,Q,!*q,!r")
2781 (match_operand:HI 1 "move_src_operand"
2782 "r,J,N,K,RQ,rM,!rM,!*q"))]
2783 "(register_operand (operands[0], HImode)
2784 || reg_or_0_operand (operands[1], HImode))"
2789 {zdepi|depwi,z} %Z1,%0
2793 {mfctl|mfctl,w} %sar,%0"
2794 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2795 (set_attr "pa_combine_type" "addmove")
2796 (set_attr "length" "4,4,4,4,4,4,4,4")])
2799 [(set (match_operand:HI 0 "register_operand" "=r")
2800 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2801 (match_operand:SI 2 "int5_operand" "L"))))
2803 (plus:SI (match_dup 1) (match_dup 2)))]
2805 "{ldhs|ldh},mb %2(%1),%0"
2806 [(set_attr "type" "load")
2807 (set_attr "length" "4")])
2810 [(set (match_operand:HI 0 "register_operand" "=r")
2811 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2812 (match_operand:DI 2 "int5_operand" "L"))))
2814 (plus:DI (match_dup 1) (match_dup 2)))]
2817 [(set_attr "type" "load")
2818 (set_attr "length" "4")])
2820 ; And a zero extended variant.
2822 [(set (match_operand:DI 0 "register_operand" "=r")
2823 (zero_extend:DI (mem:HI
2825 (match_operand:DI 1 "register_operand" "+r")
2826 (match_operand:DI 2 "int5_operand" "L")))))
2828 (plus:DI (match_dup 1) (match_dup 2)))]
2831 [(set_attr "type" "load")
2832 (set_attr "length" "4")])
2835 [(set (match_operand:SI 0 "register_operand" "=r")
2836 (zero_extend:SI (mem:HI
2838 (match_operand:SI 1 "register_operand" "+r")
2839 (match_operand:SI 2 "int5_operand" "L")))))
2841 (plus:SI (match_dup 1) (match_dup 2)))]
2843 "{ldhs|ldh},mb %2(%1),%0"
2844 [(set_attr "type" "load")
2845 (set_attr "length" "4")])
2848 [(set (match_operand:SI 0 "register_operand" "=r")
2849 (zero_extend:SI (mem:HI
2851 (match_operand:DI 1 "register_operand" "+r")
2852 (match_operand:DI 2 "int5_operand" "L")))))
2854 (plus:DI (match_dup 1) (match_dup 2)))]
2857 [(set_attr "type" "load")
2858 (set_attr "length" "4")])
2861 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2862 (match_operand:SI 1 "int5_operand" "L")))
2863 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2865 (plus:SI (match_dup 0) (match_dup 1)))]
2867 "{sths|sth},mb %r2,%1(%0)"
2868 [(set_attr "type" "store")
2869 (set_attr "length" "4")])
2872 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2873 (match_operand:DI 1 "int5_operand" "L")))
2874 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2876 (plus:DI (match_dup 0) (match_dup 1)))]
2879 [(set_attr "type" "store")
2880 (set_attr "length" "4")])
2883 [(set (match_operand:HI 0 "register_operand" "=r")
2884 (plus:HI (match_operand:HI 1 "register_operand" "r")
2885 (match_operand 2 "const_int_operand" "J")))]
2888 [(set_attr "type" "binary")
2889 (set_attr "pa_combine_type" "addmove")
2890 (set_attr "length" "4")])
2892 (define_expand "movqi"
2893 [(set (match_operand:QI 0 "general_operand" "")
2894 (match_operand:QI 1 "general_operand" ""))]
2898 if (emit_move_sequence (operands, QImode, 0))
2902 ;; Handle QImode input reloads requiring a general register as a
2903 ;; scratch register.
2904 (define_expand "reload_inqi"
2905 [(set (match_operand:QI 0 "register_operand" "=Z")
2906 (match_operand:QI 1 "non_hard_reg_operand" ""))
2907 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2911 if (emit_move_sequence (operands, QImode, operands[2]))
2914 /* We don't want the clobber emitted, so handle this ourselves. */
2915 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2919 ;; Handle QImode output reloads requiring a general register as a
2920 ;; scratch register.
2921 (define_expand "reload_outqi"
2922 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
2923 (match_operand:QI 1 "register_operand" "Z"))
2924 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2928 if (emit_move_sequence (operands, QImode, operands[2]))
2931 /* We don't want the clobber emitted, so handle this ourselves. */
2932 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2937 [(set (match_operand:QI 0 "move_dest_operand"
2938 "=r,r,r,r,r,Q,!*q,!r")
2939 (match_operand:QI 1 "move_src_operand"
2940 "r,J,N,K,RQ,rM,!rM,!*q"))]
2941 "(register_operand (operands[0], QImode)
2942 || reg_or_0_operand (operands[1], QImode))"
2947 {zdepi|depwi,z} %Z1,%0
2951 {mfctl|mfctl,w} %%sar,%0"
2952 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2953 (set_attr "pa_combine_type" "addmove")
2954 (set_attr "length" "4,4,4,4,4,4,4,4")])
2957 [(set (match_operand:QI 0 "register_operand" "=r")
2958 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2959 (match_operand:SI 2 "int5_operand" "L"))))
2960 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2962 "{ldbs|ldb},mb %2(%1),%0"
2963 [(set_attr "type" "load")
2964 (set_attr "length" "4")])
2967 [(set (match_operand:QI 0 "register_operand" "=r")
2968 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2969 (match_operand:DI 2 "int5_operand" "L"))))
2970 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2973 [(set_attr "type" "load")
2974 (set_attr "length" "4")])
2976 ; Now the same thing with zero extensions.
2978 [(set (match_operand:DI 0 "register_operand" "=r")
2979 (zero_extend:DI (mem:QI (plus:DI
2980 (match_operand:DI 1 "register_operand" "+r")
2981 (match_operand:DI 2 "int5_operand" "L")))))
2982 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2985 [(set_attr "type" "load")
2986 (set_attr "length" "4")])
2989 [(set (match_operand:SI 0 "register_operand" "=r")
2990 (zero_extend:SI (mem:QI (plus:SI
2991 (match_operand:SI 1 "register_operand" "+r")
2992 (match_operand:SI 2 "int5_operand" "L")))))
2993 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2995 "{ldbs|ldb},mb %2(%1),%0"
2996 [(set_attr "type" "load")
2997 (set_attr "length" "4")])
3000 [(set (match_operand:SI 0 "register_operand" "=r")
3001 (zero_extend:SI (mem:QI (plus:DI
3002 (match_operand:DI 1 "register_operand" "+r")
3003 (match_operand:DI 2 "int5_operand" "L")))))
3004 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3007 [(set_attr "type" "load")
3008 (set_attr "length" "4")])
3011 [(set (match_operand:HI 0 "register_operand" "=r")
3012 (zero_extend:HI (mem:QI (plus:SI
3013 (match_operand:SI 1 "register_operand" "+r")
3014 (match_operand:SI 2 "int5_operand" "L")))))
3015 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3017 "{ldbs|ldb},mb %2(%1),%0"
3018 [(set_attr "type" "load")
3019 (set_attr "length" "4")])
3022 [(set (match_operand:HI 0 "register_operand" "=r")
3023 (zero_extend:HI (mem:QI (plus:DI
3024 (match_operand:DI 1 "register_operand" "+r")
3025 (match_operand:DI 2 "int5_operand" "L")))))
3026 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3033 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3034 (match_operand:SI 1 "int5_operand" "L")))
3035 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3037 (plus:SI (match_dup 0) (match_dup 1)))]
3039 "{stbs|stb},mb %r2,%1(%0)"
3040 [(set_attr "type" "store")
3041 (set_attr "length" "4")])
3044 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3045 (match_operand:DI 1 "int5_operand" "L")))
3046 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3048 (plus:DI (match_dup 0) (match_dup 1)))]
3051 [(set_attr "type" "store")
3052 (set_attr "length" "4")])
3054 ;; The definition of this insn does not really explain what it does,
3055 ;; but it should suffice that anything generated as this insn will be
3056 ;; recognized as a movmemsi operation, and that it will not successfully
3057 ;; combine with anything.
3058 (define_expand "movmemsi"
3059 [(parallel [(set (match_operand:BLK 0 "" "")
3060 (match_operand:BLK 1 "" ""))
3061 (clobber (match_dup 4))
3062 (clobber (match_dup 5))
3063 (clobber (match_dup 6))
3064 (clobber (match_dup 7))
3065 (clobber (match_dup 8))
3066 (use (match_operand:SI 2 "arith_operand" ""))
3067 (use (match_operand:SI 3 "const_int_operand" ""))])]
3068 "!TARGET_64BIT && optimize > 0"
3073 /* HP provides very fast block move library routine for the PA;
3074 this routine includes:
3076 4x4 byte at a time block moves,
3077 1x4 byte at a time with alignment checked at runtime with
3078 attempts to align the source and destination as needed
3081 With that in mind, here's the heuristics to try and guess when
3082 the inlined block move will be better than the library block
3085 If the size isn't constant, then always use the library routines.
3087 If the size is large in respect to the known alignment, then use
3088 the library routines.
3090 If the size is small in respect to the known alignment, then open
3091 code the copy (since that will lead to better scheduling).
3093 Else use the block move pattern. */
3095 /* Undetermined size, use the library routine. */
3096 if (GET_CODE (operands[2]) != CONST_INT)
3099 size = INTVAL (operands[2]);
3100 align = INTVAL (operands[3]);
3101 align = align > 4 ? 4 : (align ? align : 1);
3103 /* If size/alignment is large, then use the library routines. */
3104 if (size / align > 16)
3107 /* This does happen, but not often enough to worry much about. */
3108 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3111 /* Fall through means we're going to use our block move pattern. */
3113 = replace_equiv_address (operands[0],
3114 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3116 = replace_equiv_address (operands[1],
3117 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3118 operands[4] = gen_reg_rtx (SImode);
3119 operands[5] = gen_reg_rtx (SImode);
3120 operands[6] = gen_reg_rtx (SImode);
3121 operands[7] = gen_reg_rtx (SImode);
3122 operands[8] = gen_reg_rtx (SImode);
3125 ;; The operand constraints are written like this to support both compile-time
3126 ;; and run-time determined byte counts. The expander and output_block_move
3127 ;; only support compile-time determined counts at this time.
3129 ;; If the count is run-time determined, the register with the byte count
3130 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3132 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3133 ;; broke this semantic for pseudo registers. We can't use match_scratch
3134 ;; as this requires two registers in the class R1_REGS when the MEMs for
3135 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3136 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3137 ;; respectively. We then split or peephole optimize after reload.
3138 (define_insn "movmemsi_prereload"
3139 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3140 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3141 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3142 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3143 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3144 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3145 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3146 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3147 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3150 [(set_attr "type" "multi,multi")])
3153 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3154 (match_operand:BLK 1 "memory_operand" ""))
3155 (clobber (match_operand:SI 2 "register_operand" ""))
3156 (clobber (match_operand:SI 3 "register_operand" ""))
3157 (clobber (match_operand:SI 6 "register_operand" ""))
3158 (clobber (match_operand:SI 7 "register_operand" ""))
3159 (clobber (match_operand:SI 8 "register_operand" ""))
3160 (use (match_operand:SI 4 "arith_operand" ""))
3161 (use (match_operand:SI 5 "const_int_operand" ""))])]
3162 "!TARGET_64BIT && reload_completed && !flag_peephole2
3163 && GET_CODE (operands[0]) == MEM
3164 && register_operand (XEXP (operands[0], 0), SImode)
3165 && GET_CODE (operands[1]) == MEM
3166 && register_operand (XEXP (operands[1], 0), SImode)"
3167 [(set (match_dup 7) (match_dup 9))
3168 (set (match_dup 8) (match_dup 10))
3169 (parallel [(set (match_dup 0) (match_dup 1))
3170 (clobber (match_dup 2))
3171 (clobber (match_dup 3))
3172 (clobber (match_dup 6))
3173 (clobber (match_dup 7))
3174 (clobber (match_dup 8))
3180 operands[9] = XEXP (operands[0], 0);
3181 operands[10] = XEXP (operands[1], 0);
3182 operands[0] = replace_equiv_address (operands[0], operands[7]);
3183 operands[1] = replace_equiv_address (operands[1], operands[8]);
3187 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3188 (match_operand:BLK 1 "memory_operand" ""))
3189 (clobber (match_operand:SI 2 "register_operand" ""))
3190 (clobber (match_operand:SI 3 "register_operand" ""))
3191 (clobber (match_operand:SI 6 "register_operand" ""))
3192 (clobber (match_operand:SI 7 "register_operand" ""))
3193 (clobber (match_operand:SI 8 "register_operand" ""))
3194 (use (match_operand:SI 4 "arith_operand" ""))
3195 (use (match_operand:SI 5 "const_int_operand" ""))])]
3197 && GET_CODE (operands[0]) == MEM
3198 && register_operand (XEXP (operands[0], 0), SImode)
3199 && GET_CODE (operands[1]) == MEM
3200 && register_operand (XEXP (operands[1], 0), SImode)"
3201 [(parallel [(set (match_dup 0) (match_dup 1))
3202 (clobber (match_dup 2))
3203 (clobber (match_dup 3))
3204 (clobber (match_dup 6))
3205 (clobber (match_dup 7))
3206 (clobber (match_dup 8))
3212 rtx addr = XEXP (operands[0], 0);
3213 if (dead_or_set_p (curr_insn, addr))
3217 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3218 operands[0] = replace_equiv_address (operands[0], operands[7]);
3221 addr = XEXP (operands[1], 0);
3222 if (dead_or_set_p (curr_insn, addr))
3226 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3227 operands[1] = replace_equiv_address (operands[1], operands[8]);
3231 (define_insn "movmemsi_postreload"
3232 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3233 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3234 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3235 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3236 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3237 (clobber (match_dup 0))
3238 (clobber (match_dup 1))
3239 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3240 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3242 "!TARGET_64BIT && reload_completed"
3243 "* return output_block_move (operands, !which_alternative);"
3244 [(set_attr "type" "multi,multi")])
3246 (define_expand "movmemdi"
3247 [(parallel [(set (match_operand:BLK 0 "" "")
3248 (match_operand:BLK 1 "" ""))
3249 (clobber (match_dup 4))
3250 (clobber (match_dup 5))
3251 (clobber (match_dup 6))
3252 (clobber (match_dup 7))
3253 (clobber (match_dup 8))
3254 (use (match_operand:DI 2 "arith_operand" ""))
3255 (use (match_operand:DI 3 "const_int_operand" ""))])]
3256 "TARGET_64BIT && optimize > 0"
3261 /* HP provides very fast block move library routine for the PA;
3262 this routine includes:
3264 4x4 byte at a time block moves,
3265 1x4 byte at a time with alignment checked at runtime with
3266 attempts to align the source and destination as needed
3269 With that in mind, here's the heuristics to try and guess when
3270 the inlined block move will be better than the library block
3273 If the size isn't constant, then always use the library routines.
3275 If the size is large in respect to the known alignment, then use
3276 the library routines.
3278 If the size is small in respect to the known alignment, then open
3279 code the copy (since that will lead to better scheduling).
3281 Else use the block move pattern. */
3283 /* Undetermined size, use the library routine. */
3284 if (GET_CODE (operands[2]) != CONST_INT)
3287 size = INTVAL (operands[2]);
3288 align = INTVAL (operands[3]);
3289 align = align > 8 ? 8 : (align ? align : 1);
3291 /* If size/alignment is large, then use the library routines. */
3292 if (size / align > 16)
3295 /* This does happen, but not often enough to worry much about. */
3296 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3299 /* Fall through means we're going to use our block move pattern. */
3301 = replace_equiv_address (operands[0],
3302 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3304 = replace_equiv_address (operands[1],
3305 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3306 operands[4] = gen_reg_rtx (DImode);
3307 operands[5] = gen_reg_rtx (DImode);
3308 operands[6] = gen_reg_rtx (DImode);
3309 operands[7] = gen_reg_rtx (DImode);
3310 operands[8] = gen_reg_rtx (DImode);
3313 ;; The operand constraints are written like this to support both compile-time
3314 ;; and run-time determined byte counts. The expander and output_block_move
3315 ;; only support compile-time determined counts at this time.
3317 ;; If the count is run-time determined, the register with the byte count
3318 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3320 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3321 ;; broke this semantic for pseudo registers. We can't use match_scratch
3322 ;; as this requires two registers in the class R1_REGS when the MEMs for
3323 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3324 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3325 ;; respectively. We then split or peephole optimize after reload.
3326 (define_insn "movmemdi_prereload"
3327 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3328 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3329 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3330 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3331 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3332 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3333 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3334 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3335 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3338 [(set_attr "type" "multi,multi")])
3341 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3342 (match_operand:BLK 1 "memory_operand" ""))
3343 (clobber (match_operand:DI 2 "register_operand" ""))
3344 (clobber (match_operand:DI 3 "register_operand" ""))
3345 (clobber (match_operand:DI 6 "register_operand" ""))
3346 (clobber (match_operand:DI 7 "register_operand" ""))
3347 (clobber (match_operand:DI 8 "register_operand" ""))
3348 (use (match_operand:DI 4 "arith_operand" ""))
3349 (use (match_operand:DI 5 "const_int_operand" ""))])]
3350 "TARGET_64BIT && reload_completed && !flag_peephole2
3351 && GET_CODE (operands[0]) == MEM
3352 && register_operand (XEXP (operands[0], 0), DImode)
3353 && GET_CODE (operands[1]) == MEM
3354 && register_operand (XEXP (operands[1], 0), DImode)"
3355 [(set (match_dup 7) (match_dup 9))
3356 (set (match_dup 8) (match_dup 10))
3357 (parallel [(set (match_dup 0) (match_dup 1))
3358 (clobber (match_dup 2))
3359 (clobber (match_dup 3))
3360 (clobber (match_dup 6))
3361 (clobber (match_dup 7))
3362 (clobber (match_dup 8))
3368 operands[9] = XEXP (operands[0], 0);
3369 operands[10] = XEXP (operands[1], 0);
3370 operands[0] = replace_equiv_address (operands[0], operands[7]);
3371 operands[1] = replace_equiv_address (operands[1], operands[8]);
3375 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3376 (match_operand:BLK 1 "memory_operand" ""))
3377 (clobber (match_operand:DI 2 "register_operand" ""))
3378 (clobber (match_operand:DI 3 "register_operand" ""))
3379 (clobber (match_operand:DI 6 "register_operand" ""))
3380 (clobber (match_operand:DI 7 "register_operand" ""))
3381 (clobber (match_operand:DI 8 "register_operand" ""))
3382 (use (match_operand:DI 4 "arith_operand" ""))
3383 (use (match_operand:DI 5 "const_int_operand" ""))])]
3385 && GET_CODE (operands[0]) == MEM
3386 && register_operand (XEXP (operands[0], 0), DImode)
3387 && GET_CODE (operands[1]) == MEM
3388 && register_operand (XEXP (operands[1], 0), DImode)"
3389 [(parallel [(set (match_dup 0) (match_dup 1))
3390 (clobber (match_dup 2))
3391 (clobber (match_dup 3))
3392 (clobber (match_dup 6))
3393 (clobber (match_dup 7))
3394 (clobber (match_dup 8))
3400 rtx addr = XEXP (operands[0], 0);
3401 if (dead_or_set_p (curr_insn, addr))
3405 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3406 operands[0] = replace_equiv_address (operands[0], operands[7]);
3409 addr = XEXP (operands[1], 0);
3410 if (dead_or_set_p (curr_insn, addr))
3414 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3415 operands[1] = replace_equiv_address (operands[1], operands[8]);
3419 (define_insn "movmemdi_postreload"
3420 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3421 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3422 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3423 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3424 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3425 (clobber (match_dup 0))
3426 (clobber (match_dup 1))
3427 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3428 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3430 "TARGET_64BIT && reload_completed"
3431 "* return output_block_move (operands, !which_alternative);"
3432 [(set_attr "type" "multi,multi")])
3434 (define_expand "setmemsi"
3435 [(parallel [(set (match_operand:BLK 0 "" "")
3436 (match_operand 2 "const_int_operand" ""))
3437 (clobber (match_dup 4))
3438 (clobber (match_dup 5))
3439 (use (match_operand:SI 1 "arith_operand" ""))
3440 (use (match_operand:SI 3 "const_int_operand" ""))])]
3441 "!TARGET_64BIT && optimize > 0"
3446 /* If value to set is not zero, use the library routine. */
3447 if (operands[2] != const0_rtx)
3450 /* Undetermined size, use the library routine. */
3451 if (GET_CODE (operands[1]) != CONST_INT)
3454 size = INTVAL (operands[1]);
3455 align = INTVAL (operands[3]);
3456 align = align > 4 ? 4 : align;
3458 /* If size/alignment is large, then use the library routines. */
3459 if (size / align > 16)
3462 /* This does happen, but not often enough to worry much about. */
3463 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3466 /* Fall through means we're going to use our block clear pattern. */
3468 = replace_equiv_address (operands[0],
3469 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3470 operands[4] = gen_reg_rtx (SImode);
3471 operands[5] = gen_reg_rtx (SImode);
3474 (define_insn "clrmemsi_prereload"
3475 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3477 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3478 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3479 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3480 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3483 [(set_attr "type" "multi,multi")])
3486 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3488 (clobber (match_operand:SI 1 "register_operand" ""))
3489 (clobber (match_operand:SI 4 "register_operand" ""))
3490 (use (match_operand:SI 2 "arith_operand" ""))
3491 (use (match_operand:SI 3 "const_int_operand" ""))])]
3492 "!TARGET_64BIT && reload_completed && !flag_peephole2
3493 && GET_CODE (operands[0]) == MEM
3494 && register_operand (XEXP (operands[0], 0), SImode)"
3495 [(set (match_dup 4) (match_dup 5))
3496 (parallel [(set (match_dup 0) (const_int 0))
3497 (clobber (match_dup 1))
3498 (clobber (match_dup 4))
3504 operands[5] = XEXP (operands[0], 0);
3505 operands[0] = replace_equiv_address (operands[0], operands[4]);
3509 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3511 (clobber (match_operand:SI 1 "register_operand" ""))
3512 (clobber (match_operand:SI 4 "register_operand" ""))
3513 (use (match_operand:SI 2 "arith_operand" ""))
3514 (use (match_operand:SI 3 "const_int_operand" ""))])]
3516 && GET_CODE (operands[0]) == MEM
3517 && register_operand (XEXP (operands[0], 0), SImode)"
3518 [(parallel [(set (match_dup 0) (const_int 0))
3519 (clobber (match_dup 1))
3520 (clobber (match_dup 4))
3526 rtx addr = XEXP (operands[0], 0);
3527 if (dead_or_set_p (curr_insn, addr))
3531 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3532 operands[0] = replace_equiv_address (operands[0], operands[4]);
3536 (define_insn "clrmemsi_postreload"
3537 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3539 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3540 (clobber (match_dup 0))
3541 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3542 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3544 "!TARGET_64BIT && reload_completed"
3545 "* return output_block_clear (operands, !which_alternative);"
3546 [(set_attr "type" "multi,multi")])
3548 (define_expand "setmemdi"
3549 [(parallel [(set (match_operand:BLK 0 "" "")
3550 (match_operand 2 "const_int_operand" ""))
3551 (clobber (match_dup 4))
3552 (clobber (match_dup 5))
3553 (use (match_operand:DI 1 "arith_operand" ""))
3554 (use (match_operand:DI 3 "const_int_operand" ""))])]
3555 "TARGET_64BIT && optimize > 0"
3560 /* If value to set is not zero, use the library routine. */
3561 if (operands[2] != const0_rtx)
3564 /* Undetermined size, use the library routine. */
3565 if (GET_CODE (operands[1]) != CONST_INT)
3568 size = INTVAL (operands[1]);
3569 align = INTVAL (operands[3]);
3570 align = align > 8 ? 8 : align;
3572 /* If size/alignment is large, then use the library routines. */
3573 if (size / align > 16)
3576 /* This does happen, but not often enough to worry much about. */
3577 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3580 /* Fall through means we're going to use our block clear pattern. */
3582 = replace_equiv_address (operands[0],
3583 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3584 operands[4] = gen_reg_rtx (DImode);
3585 operands[5] = gen_reg_rtx (DImode);
3588 (define_insn "clrmemdi_prereload"
3589 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3591 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3592 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3593 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3594 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3597 [(set_attr "type" "multi,multi")])
3600 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3602 (clobber (match_operand:DI 1 "register_operand" ""))
3603 (clobber (match_operand:DI 4 "register_operand" ""))
3604 (use (match_operand:DI 2 "arith_operand" ""))
3605 (use (match_operand:DI 3 "const_int_operand" ""))])]
3606 "TARGET_64BIT && reload_completed && !flag_peephole2
3607 && GET_CODE (operands[0]) == MEM
3608 && register_operand (XEXP (operands[0], 0), DImode)"
3609 [(set (match_dup 4) (match_dup 5))
3610 (parallel [(set (match_dup 0) (const_int 0))
3611 (clobber (match_dup 1))
3612 (clobber (match_dup 4))
3618 operands[5] = XEXP (operands[0], 0);
3619 operands[0] = replace_equiv_address (operands[0], operands[4]);
3623 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3625 (clobber (match_operand:DI 1 "register_operand" ""))
3626 (clobber (match_operand:DI 4 "register_operand" ""))
3627 (use (match_operand:DI 2 "arith_operand" ""))
3628 (use (match_operand:DI 3 "const_int_operand" ""))])]
3630 && GET_CODE (operands[0]) == MEM
3631 && register_operand (XEXP (operands[0], 0), DImode)"
3632 [(parallel [(set (match_dup 0) (const_int 0))
3633 (clobber (match_dup 1))
3634 (clobber (match_dup 4))
3640 rtx addr = XEXP (operands[0], 0);
3641 if (dead_or_set_p (curr_insn, addr))
3645 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3646 operands[0] = replace_equiv_address (operands[0], operands[4]);
3650 (define_insn "clrmemdi_postreload"
3651 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3653 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3654 (clobber (match_dup 0))
3655 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3656 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3658 "TARGET_64BIT && reload_completed"
3659 "* return output_block_clear (operands, !which_alternative);"
3660 [(set_attr "type" "multi,multi")])
3662 ;; Floating point move insns
3664 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3665 ;; to be reloaded by putting the constant into memory when
3666 ;; reg is a floating point register.
3668 ;; For integer registers we use ldil;ldo to set the appropriate
3671 ;; This must come before the movdf pattern, and it must be present
3672 ;; to handle obscure reloading cases.
3674 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3675 (match_operand:DF 1 "" "?F,m"))]
3676 "GET_CODE (operands[1]) == CONST_DOUBLE
3677 && operands[1] != CONST0_RTX (DFmode)
3679 && !TARGET_SOFT_FLOAT"
3680 "* return (which_alternative == 0 ? output_move_double (operands)
3681 : \"fldd%F1 %1,%0\");"
3682 [(set_attr "type" "move,fpload")
3683 (set_attr "length" "16,4")])
3685 (define_expand "movdf"
3686 [(set (match_operand:DF 0 "general_operand" "")
3687 (match_operand:DF 1 "general_operand" ""))]
3691 if (GET_CODE (operands[1]) == CONST_DOUBLE
3692 && operands[1] != CONST0_RTX (DFmode))
3694 /* Reject CONST_DOUBLE loads to all hard registers when
3695 generating 64-bit code and to floating point registers
3696 when generating 32-bit code. */
3697 if (REG_P (operands[0])
3698 && HARD_REGISTER_P (operands[0])
3699 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
3703 operands[1] = force_const_mem (DFmode, operands[1]);
3706 if (emit_move_sequence (operands, DFmode, 0))
3710 ;; Handle DFmode input reloads requiring a general register as a
3711 ;; scratch register.
3712 (define_expand "reload_indf"
3713 [(set (match_operand:DF 0 "register_operand" "=Z")
3714 (match_operand:DF 1 "non_hard_reg_operand" ""))
3715 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3719 if (emit_move_sequence (operands, DFmode, operands[2]))
3722 /* We don't want the clobber emitted, so handle this ourselves. */
3723 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3727 ;; Handle DFmode output reloads requiring a general register as a
3728 ;; scratch register.
3729 (define_expand "reload_outdf"
3730 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3731 (match_operand:DF 1 "register_operand" "Z"))
3732 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3736 if (emit_move_sequence (operands, DFmode, operands[2]))
3739 /* We don't want the clobber emitted, so handle this ourselves. */
3740 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3745 [(set (match_operand:DF 0 "move_dest_operand"
3746 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
3747 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3748 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
3749 "(register_operand (operands[0], DFmode)
3750 || reg_or_0_operand (operands[1], DFmode))
3751 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3752 && GET_CODE (operands[0]) == MEM)
3754 && !TARGET_SOFT_FLOAT"
3757 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3758 || operands[1] == CONST0_RTX (DFmode))
3759 && !(REG_P (operands[0]) && REG_P (operands[1])
3760 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3761 return output_fp_move_double (operands);
3762 return output_move_double (operands);
3764 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3765 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3768 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3769 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3771 && !TARGET_DISABLE_INDEXING
3772 && reload_completed"
3774 [(set_attr "type" "fpstore")
3775 (set_attr "pa_combine_type" "addmove")
3776 (set_attr "length" "4")])
3779 [(set (match_operand:SI 0 "register_operand" "")
3780 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3782 (match_operand:SI 2 "register_operand" "")))
3783 (set (mem:DF (match_dup 0))
3784 (match_operand:DF 3 "register_operand" ""))]
3786 && !TARGET_DISABLE_INDEXING
3787 && REG_OK_FOR_BASE_P (operands[2])
3788 && FP_REGNO_P (REGNO (operands[3]))"
3789 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3791 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3796 [(set (match_operand:SI 0 "register_operand" "")
3797 (plus:SI (match_operand:SI 2 "register_operand" "")
3798 (mult:SI (match_operand:SI 1 "register_operand" "")
3800 (set (mem:DF (match_dup 0))
3801 (match_operand:DF 3 "register_operand" ""))]
3803 && !TARGET_DISABLE_INDEXING
3804 && REG_OK_FOR_BASE_P (operands[2])
3805 && FP_REGNO_P (REGNO (operands[3]))"
3806 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3808 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3813 [(set (match_operand:DI 0 "register_operand" "")
3814 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3816 (match_operand:DI 2 "register_operand" "")))
3817 (set (mem:DF (match_dup 0))
3818 (match_operand:DF 3 "register_operand" ""))]
3820 && !TARGET_DISABLE_INDEXING
3822 && REG_OK_FOR_BASE_P (operands[2])
3823 && FP_REGNO_P (REGNO (operands[3]))"
3824 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3826 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3831 [(set (match_operand:DI 0 "register_operand" "")
3832 (plus:DI (match_operand:DI 2 "register_operand" "")
3833 (mult:DI (match_operand:DI 1 "register_operand" "")
3835 (set (mem:DF (match_dup 0))
3836 (match_operand:DF 3 "register_operand" ""))]
3838 && !TARGET_DISABLE_INDEXING
3840 && REG_OK_FOR_BASE_P (operands[2])
3841 && FP_REGNO_P (REGNO (operands[3]))"
3842 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3844 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3849 [(set (match_operand:SI 0 "register_operand" "")
3850 (plus:SI (match_operand:SI 1 "register_operand" "")
3851 (match_operand:SI 2 "register_operand" "")))
3852 (set (mem:DF (match_dup 0))
3853 (match_operand:DF 3 "register_operand" ""))]
3855 && !TARGET_DISABLE_INDEXING
3856 && TARGET_NO_SPACE_REGS
3857 && REG_OK_FOR_INDEX_P (operands[1])
3858 && REG_OK_FOR_BASE_P (operands[2])
3859 && FP_REGNO_P (REGNO (operands[3]))"
3860 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3862 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3866 [(set (match_operand:SI 0 "register_operand" "")
3867 (plus:SI (match_operand:SI 1 "register_operand" "")
3868 (match_operand:SI 2 "register_operand" "")))
3869 (set (mem:DF (match_dup 0))
3870 (match_operand:DF 3 "register_operand" ""))]
3872 && !TARGET_DISABLE_INDEXING
3873 && TARGET_NO_SPACE_REGS
3874 && REG_OK_FOR_BASE_P (operands[1])
3875 && REG_OK_FOR_INDEX_P (operands[2])
3876 && FP_REGNO_P (REGNO (operands[3]))"
3877 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3879 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3883 [(set (match_operand:DI 0 "register_operand" "")
3884 (plus:DI (match_operand:DI 1 "register_operand" "")
3885 (match_operand:DI 2 "register_operand" "")))
3886 (set (mem:DF (match_dup 0))
3887 (match_operand:DF 3 "register_operand" ""))]
3889 && !TARGET_DISABLE_INDEXING
3891 && TARGET_NO_SPACE_REGS
3892 && REG_OK_FOR_INDEX_P (operands[1])
3893 && REG_OK_FOR_BASE_P (operands[2])
3894 && FP_REGNO_P (REGNO (operands[3]))"
3895 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3897 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3901 [(set (match_operand:DI 0 "register_operand" "")
3902 (plus:DI (match_operand:DI 1 "register_operand" "")
3903 (match_operand:DI 2 "register_operand" "")))
3904 (set (mem:DF (match_dup 0))
3905 (match_operand:DF 3 "register_operand" ""))]
3907 && !TARGET_DISABLE_INDEXING
3909 && TARGET_NO_SPACE_REGS
3910 && REG_OK_FOR_BASE_P (operands[1])
3911 && REG_OK_FOR_INDEX_P (operands[2])
3912 && FP_REGNO_P (REGNO (operands[3]))"
3913 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3915 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3919 [(set (match_operand:DF 0 "move_dest_operand"
3921 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3923 "(register_operand (operands[0], DFmode)
3924 || reg_or_0_operand (operands[1], DFmode))
3926 && TARGET_SOFT_FLOAT"
3929 return output_move_double (operands);
3931 [(set_attr "type" "move,store,store,load,load")
3932 (set_attr "length" "8,8,16,8,16")])
3935 [(set (match_operand:DF 0 "move_dest_operand"
3936 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3937 (match_operand:DF 1 "move_src_operand"
3938 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
3939 "(register_operand (operands[0], DFmode)
3940 || reg_or_0_operand (operands[1], DFmode))
3941 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3952 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3953 (set_attr "pa_combine_type" "addmove")
3954 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3957 (define_expand "movdi"
3958 [(set (match_operand:DI 0 "general_operand" "")
3959 (match_operand:DI 1 "general_operand" ""))]
3963 /* Except for zero, we don't support loading a CONST_INT directly
3964 to a hard floating-point register since a scratch register is
3965 needed for the operation. While the operation could be handled
3966 before register allocation, the simplest solution is to fail. */
3968 && GET_CODE (operands[1]) == CONST_INT
3969 && operands[1] != CONST0_RTX (DImode)
3970 && REG_P (operands[0])
3971 && HARD_REGISTER_P (operands[0])
3972 && REGNO (operands[0]) >= 32)
3975 if (emit_move_sequence (operands, DImode, 0))
3979 ;; Handle DImode input reloads requiring %r1 as a scratch register.
3980 (define_expand "reload_indi_r1"
3981 [(set (match_operand:DI 0 "register_operand" "=Z")
3982 (match_operand:DI 1 "non_hard_reg_operand" ""))
3983 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3987 if (emit_move_sequence (operands, DImode, operands[2]))
3990 /* We don't want the clobber emitted, so handle this ourselves. */
3991 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3995 ;; Handle DImode input reloads requiring a general register as a
3996 ;; scratch register.
3997 (define_expand "reload_indi"
3998 [(set (match_operand:DI 0 "register_operand" "=Z")
3999 (match_operand:DI 1 "non_hard_reg_operand" ""))
4000 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4004 if (emit_move_sequence (operands, DImode, operands[2]))
4007 /* We don't want the clobber emitted, so handle this ourselves. */
4008 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4012 ;; Handle DImode output reloads requiring a general register as a
4013 ;; scratch register.
4014 (define_expand "reload_outdi"
4015 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4016 (match_operand:DI 1 "register_operand" "Z"))
4017 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4021 if (emit_move_sequence (operands, DImode, operands[2]))
4024 /* We don't want the clobber emitted, so handle this ourselves. */
4025 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4030 [(set (match_operand:DI 0 "register_operand" "=r")
4031 (high:DI (match_operand 1 "" "")))]
4035 rtx op0 = operands[0];
4036 rtx op1 = operands[1];
4038 switch (GET_CODE (op1))
4041 #if HOST_BITS_PER_WIDE_INT <= 32
4042 operands[0] = operand_subword (op0, 1, 0, DImode);
4043 output_asm_insn (\"ldil L'%1,%0\", operands);
4045 operands[0] = operand_subword (op0, 0, 0, DImode);
4046 if (INTVAL (op1) < 0)
4047 output_asm_insn (\"ldi -1,%0\", operands);
4049 output_asm_insn (\"ldi 0,%0\", operands);
4051 operands[0] = operand_subword (op0, 1, 0, DImode);
4052 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4053 output_asm_insn (\"ldil L'%1,%0\", operands);
4055 operands[0] = operand_subword (op0, 0, 0, DImode);
4056 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4057 output_asm_insn (singlemove_string (operands), operands);
4062 operands[0] = operand_subword (op0, 1, 0, DImode);
4063 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4064 output_asm_insn (\"ldil L'%1,%0\", operands);
4066 operands[0] = operand_subword (op0, 0, 0, DImode);
4067 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4068 output_asm_insn (singlemove_string (operands), operands);
4076 [(set_attr "type" "move")
4077 (set_attr "length" "12")])
4080 [(set (match_operand:DI 0 "move_dest_operand"
4081 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4082 (match_operand:DI 1 "general_operand"
4083 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4084 "(register_operand (operands[0], DImode)
4085 || reg_or_0_operand (operands[1], DImode))
4087 && !TARGET_SOFT_FLOAT"
4090 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4091 || operands[1] == CONST0_RTX (DFmode))
4092 && !(REG_P (operands[0]) && REG_P (operands[1])
4093 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4094 return output_fp_move_double (operands);
4095 return output_move_double (operands);
4098 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4099 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4102 [(set (match_operand:DI 0 "move_dest_operand"
4103 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4104 (match_operand:DI 1 "move_src_operand"
4105 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4106 "(register_operand (operands[0], DImode)
4107 || reg_or_0_operand (operands[1], DImode))
4108 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4118 {mfctl|mfctl,w} %%sar,%0
4122 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4123 (set_attr "pa_combine_type" "addmove")
4124 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4127 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4128 (match_operand:DI 1 "register_operand" "f"))]
4131 && !TARGET_DISABLE_INDEXING
4132 && reload_completed"
4134 [(set_attr "type" "fpstore")
4135 (set_attr "pa_combine_type" "addmove")
4136 (set_attr "length" "4")])
4139 [(set (match_operand:DI 0 "register_operand" "")
4140 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4142 (match_operand:DI 2 "register_operand" "")))
4143 (set (mem:DI (match_dup 0))
4144 (match_operand:DI 3 "register_operand" ""))]
4146 && !TARGET_DISABLE_INDEXING
4148 && REG_OK_FOR_BASE_P (operands[2])
4149 && FP_REGNO_P (REGNO (operands[3]))"
4150 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4152 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4157 [(set (match_operand:DI 0 "register_operand" "")
4158 (plus:DI (match_operand:DI 2 "register_operand" "")
4159 (mult:DI (match_operand:DI 1 "register_operand" "")
4161 (set (mem:DI (match_dup 0))
4162 (match_operand:DI 3 "register_operand" ""))]
4164 && !TARGET_DISABLE_INDEXING
4166 && REG_OK_FOR_BASE_P (operands[2])
4167 && FP_REGNO_P (REGNO (operands[3]))"
4168 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4170 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4175 [(set (match_operand:DI 0 "register_operand" "")
4176 (plus:DI (match_operand:DI 1 "register_operand" "")
4177 (match_operand:DI 2 "register_operand" "")))
4178 (set (mem:DI (match_dup 0))
4179 (match_operand:DI 3 "register_operand" ""))]
4181 && !TARGET_DISABLE_INDEXING
4183 && TARGET_NO_SPACE_REGS
4184 && REG_OK_FOR_INDEX_P (operands[1])
4185 && REG_OK_FOR_BASE_P (operands[2])
4186 && FP_REGNO_P (REGNO (operands[3]))"
4187 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4189 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4193 [(set (match_operand:DI 0 "register_operand" "")
4194 (plus:DI (match_operand:DI 1 "register_operand" "")
4195 (match_operand:DI 2 "register_operand" "")))
4196 (set (mem:DI (match_dup 0))
4197 (match_operand:DI 3 "register_operand" ""))]
4199 && !TARGET_DISABLE_INDEXING
4201 && TARGET_NO_SPACE_REGS
4202 && REG_OK_FOR_BASE_P (operands[1])
4203 && REG_OK_FOR_INDEX_P (operands[2])
4204 && FP_REGNO_P (REGNO (operands[3]))"
4205 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4207 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4211 [(set (match_operand:DI 0 "move_dest_operand"
4213 (match_operand:DI 1 "general_operand"
4215 "(register_operand (operands[0], DImode)
4216 || reg_or_0_operand (operands[1], DImode))
4218 && TARGET_SOFT_FLOAT"
4221 return output_move_double (operands);
4223 [(set_attr "type" "move,store,store,load,load,multi")
4224 (set_attr "length" "8,8,16,8,16,16")])
4227 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4228 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4229 (match_operand:DI 2 "immediate_operand" "i,i")))]
4233 /* Don't output a 64-bit constant, since we can't trust the assembler to
4234 handle it correctly. */
4235 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4236 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4237 else if (HOST_BITS_PER_WIDE_INT > 32
4238 && GET_CODE (operands[2]) == CONST_INT)
4239 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4240 if (which_alternative == 1)
4241 output_asm_insn (\"copy %1,%0\", operands);
4242 return \"ldo R'%G2(%R1),%R0\";
4244 [(set_attr "type" "move,move")
4245 (set_attr "length" "4,8")])
4247 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4248 ;; to be reloaded by putting the constant into memory when
4249 ;; reg is a floating point register.
4251 ;; For integer registers we use ldil;ldo to set the appropriate
4254 ;; This must come before the movsf pattern, and it must be present
4255 ;; to handle obscure reloading cases.
4257 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4258 (match_operand:SF 1 "" "?F,m"))]
4259 "GET_CODE (operands[1]) == CONST_DOUBLE
4260 && operands[1] != CONST0_RTX (SFmode)
4261 && ! TARGET_SOFT_FLOAT"
4262 "* return (which_alternative == 0 ? singlemove_string (operands)
4263 : \" fldw%F1 %1,%0\");"
4264 [(set_attr "type" "move,fpload")
4265 (set_attr "length" "8,4")])
4267 (define_expand "movsf"
4268 [(set (match_operand:SF 0 "general_operand" "")
4269 (match_operand:SF 1 "general_operand" ""))]
4273 /* Reject CONST_DOUBLE loads to floating point registers. */
4274 if (GET_CODE (operands[1]) == CONST_DOUBLE
4275 && operands[1] != CONST0_RTX (SFmode)
4276 && REG_P (operands[0])
4277 && HARD_REGISTER_P (operands[0])
4278 && REGNO (operands[0]) >= 32)
4281 if (emit_move_sequence (operands, SFmode, 0))
4285 ;; Handle SFmode input reloads requiring a general register as a
4286 ;; scratch register.
4287 (define_expand "reload_insf"
4288 [(set (match_operand:SF 0 "register_operand" "=Z")
4289 (match_operand:SF 1 "non_hard_reg_operand" ""))
4290 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4294 if (emit_move_sequence (operands, SFmode, operands[2]))
4297 /* We don't want the clobber emitted, so handle this ourselves. */
4298 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4302 ;; Handle SFmode output reloads requiring a general register as a
4303 ;; scratch register.
4304 (define_expand "reload_outsf"
4305 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4306 (match_operand:SF 1 "register_operand" "Z"))
4307 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4311 if (emit_move_sequence (operands, SFmode, operands[2]))
4314 /* We don't want the clobber emitted, so handle this ourselves. */
4315 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4320 [(set (match_operand:SF 0 "move_dest_operand"
4321 "=f,!*r,f,*r,Q,Q,?*r,?f")
4322 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4323 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4324 "(register_operand (operands[0], SFmode)
4325 || reg_or_0_operand (operands[1], SFmode))
4326 && !TARGET_SOFT_FLOAT
4335 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4336 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4337 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4338 (set_attr "pa_combine_type" "addmove")
4339 (set_attr "length" "4,4,4,4,4,4,8,8")])
4342 [(set (match_operand:SF 0 "move_dest_operand"
4344 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4345 "fG,!*rG,RQ,RQ,f,*rG"))]
4346 "(register_operand (operands[0], SFmode)
4347 || reg_or_0_operand (operands[1], SFmode))
4348 && !TARGET_SOFT_FLOAT
4357 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4358 (set_attr "pa_combine_type" "addmove")
4359 (set_attr "length" "4,4,4,4,4,4")])
4362 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4363 (match_operand:SF 1 "register_operand" "f"))]
4365 && !TARGET_DISABLE_INDEXING
4366 && reload_completed"
4368 [(set_attr "type" "fpstore")
4369 (set_attr "pa_combine_type" "addmove")
4370 (set_attr "length" "4")])
4373 [(set (match_operand:SI 0 "register_operand" "")
4374 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4376 (match_operand:SI 2 "register_operand" "")))
4377 (set (mem:SF (match_dup 0))
4378 (match_operand:SF 3 "register_operand" ""))]
4380 && !TARGET_DISABLE_INDEXING
4381 && REG_OK_FOR_BASE_P (operands[2])
4382 && FP_REGNO_P (REGNO (operands[3]))"
4383 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4385 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4390 [(set (match_operand:SI 0 "register_operand" "")
4391 (plus:SI (match_operand:SI 2 "register_operand" "")
4392 (mult:SI (match_operand:SI 1 "register_operand" "")
4394 (set (mem:SF (match_dup 0))
4395 (match_operand:SF 3 "register_operand" ""))]
4397 && !TARGET_DISABLE_INDEXING
4398 && REG_OK_FOR_BASE_P (operands[2])
4399 && FP_REGNO_P (REGNO (operands[3]))"
4400 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4402 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4407 [(set (match_operand:DI 0 "register_operand" "")
4408 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4410 (match_operand:DI 2 "register_operand" "")))
4411 (set (mem:SF (match_dup 0))
4412 (match_operand:SF 3 "register_operand" ""))]
4414 && !TARGET_DISABLE_INDEXING
4416 && REG_OK_FOR_BASE_P (operands[2])
4417 && FP_REGNO_P (REGNO (operands[3]))"
4418 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4420 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4425 [(set (match_operand:DI 0 "register_operand" "")
4426 (plus:DI (match_operand:DI 2 "register_operand" "")
4427 (mult:DI (match_operand:DI 1 "register_operand" "")
4429 (set (mem:SF (match_dup 0))
4430 (match_operand:SF 3 "register_operand" ""))]
4432 && !TARGET_DISABLE_INDEXING
4434 && REG_OK_FOR_BASE_P (operands[2])
4435 && FP_REGNO_P (REGNO (operands[3]))"
4436 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4438 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4443 [(set (match_operand:SI 0 "register_operand" "")
4444 (plus:SI (match_operand:SI 1 "register_operand" "")
4445 (match_operand:SI 2 "register_operand" "")))
4446 (set (mem:SF (match_dup 0))
4447 (match_operand:SF 3 "register_operand" ""))]
4449 && !TARGET_DISABLE_INDEXING
4450 && TARGET_NO_SPACE_REGS
4451 && REG_OK_FOR_INDEX_P (operands[1])
4452 && REG_OK_FOR_BASE_P (operands[2])
4453 && FP_REGNO_P (REGNO (operands[3]))"
4454 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4456 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4460 [(set (match_operand:SI 0 "register_operand" "")
4461 (plus:SI (match_operand:SI 1 "register_operand" "")
4462 (match_operand:SI 2 "register_operand" "")))
4463 (set (mem:SF (match_dup 0))
4464 (match_operand:SF 3 "register_operand" ""))]
4466 && !TARGET_DISABLE_INDEXING
4467 && TARGET_NO_SPACE_REGS
4468 && REG_OK_FOR_BASE_P (operands[1])
4469 && REG_OK_FOR_INDEX_P (operands[2])
4470 && FP_REGNO_P (REGNO (operands[3]))"
4471 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4473 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4477 [(set (match_operand:DI 0 "register_operand" "")
4478 (plus:DI (match_operand:DI 1 "register_operand" "")
4479 (match_operand:DI 2 "register_operand" "")))
4480 (set (mem:SF (match_dup 0))
4481 (match_operand:SF 3 "register_operand" ""))]
4483 && !TARGET_DISABLE_INDEXING
4485 && TARGET_NO_SPACE_REGS
4486 && REG_OK_FOR_INDEX_P (operands[1])
4487 && REG_OK_FOR_BASE_P (operands[2])
4488 && FP_REGNO_P (REGNO (operands[3]))"
4489 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4491 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4495 [(set (match_operand:DI 0 "register_operand" "")
4496 (plus:DI (match_operand:DI 1 "register_operand" "")
4497 (match_operand:DI 2 "register_operand" "")))
4498 (set (mem:SF (match_dup 0))
4499 (match_operand:SF 3 "register_operand" ""))]
4501 && !TARGET_DISABLE_INDEXING
4503 && TARGET_NO_SPACE_REGS
4504 && REG_OK_FOR_BASE_P (operands[1])
4505 && REG_OK_FOR_INDEX_P (operands[2])
4506 && FP_REGNO_P (REGNO (operands[3]))"
4507 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4509 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4513 [(set (match_operand:SF 0 "move_dest_operand"
4515 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4517 "(register_operand (operands[0], SFmode)
4518 || reg_or_0_operand (operands[1], SFmode))
4519 && TARGET_SOFT_FLOAT"
4524 [(set_attr "type" "move,load,store")
4525 (set_attr "pa_combine_type" "addmove")
4526 (set_attr "length" "4,4,4")])
4530 ;;- zero extension instructions
4531 ;; We have define_expand for zero extension patterns to make sure the
4532 ;; operands get loaded into registers. The define_insns accept
4533 ;; memory operands. This gives us better overall code than just
4534 ;; having a pattern that does or does not accept memory operands.
4536 (define_expand "zero_extendqihi2"
4537 [(set (match_operand:HI 0 "register_operand" "")
4539 (match_operand:QI 1 "register_operand" "")))]
4544 [(set (match_operand:HI 0 "register_operand" "=r,r")
4546 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4547 "GET_CODE (operands[1]) != CONST_INT"
4549 {extru|extrw,u} %1,31,8,%0
4551 [(set_attr "type" "shift,load")
4552 (set_attr "length" "4,4")])
4554 (define_expand "zero_extendqisi2"
4555 [(set (match_operand:SI 0 "register_operand" "")
4557 (match_operand:QI 1 "register_operand" "")))]
4562 [(set (match_operand:SI 0 "register_operand" "=r,r")
4564 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4565 "GET_CODE (operands[1]) != CONST_INT"
4567 {extru|extrw,u} %1,31,8,%0
4569 [(set_attr "type" "shift,load")
4570 (set_attr "length" "4,4")])
4572 (define_expand "zero_extendhisi2"
4573 [(set (match_operand:SI 0 "register_operand" "")
4575 (match_operand:HI 1 "register_operand" "")))]
4580 [(set (match_operand:SI 0 "register_operand" "=r,r")
4582 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4583 "GET_CODE (operands[1]) != CONST_INT"
4585 {extru|extrw,u} %1,31,16,%0
4587 [(set_attr "type" "shift,load")
4588 (set_attr "length" "4,4")])
4590 (define_expand "zero_extendqidi2"
4591 [(set (match_operand:DI 0 "register_operand" "")
4593 (match_operand:QI 1 "register_operand" "")))]
4598 [(set (match_operand:DI 0 "register_operand" "=r,r")
4600 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4601 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4605 [(set_attr "type" "shift,load")
4606 (set_attr "length" "4,4")])
4608 (define_expand "zero_extendhidi2"
4609 [(set (match_operand:DI 0 "register_operand" "")
4611 (match_operand:HI 1 "register_operand" "")))]
4616 [(set (match_operand:DI 0 "register_operand" "=r,r")
4618 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4619 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4623 [(set_attr "type" "shift,load")
4624 (set_attr "length" "4,4")])
4626 (define_expand "zero_extendsidi2"
4627 [(set (match_operand:DI 0 "register_operand" "")
4629 (match_operand:SI 1 "register_operand" "")))]
4634 [(set (match_operand:DI 0 "register_operand" "=r,r")
4636 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4637 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4641 [(set_attr "type" "shift,load")
4642 (set_attr "length" "4,4")])
4644 ;;- sign extension instructions
4646 (define_insn "extendhisi2"
4647 [(set (match_operand:SI 0 "register_operand" "=r")
4648 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4650 "{extrs|extrw,s} %1,31,16,%0"
4651 [(set_attr "type" "shift")
4652 (set_attr "length" "4")])
4654 (define_insn "extendqihi2"
4655 [(set (match_operand:HI 0 "register_operand" "=r")
4656 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4658 "{extrs|extrw,s} %1,31,8,%0"
4659 [(set_attr "type" "shift")
4660 (set_attr "length" "4")])
4662 (define_insn "extendqisi2"
4663 [(set (match_operand:SI 0 "register_operand" "=r")
4664 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4666 "{extrs|extrw,s} %1,31,8,%0"
4667 [(set_attr "type" "shift")
4668 (set_attr "length" "4")])
4670 (define_insn "extendqidi2"
4671 [(set (match_operand:DI 0 "register_operand" "=r")
4672 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4674 "extrd,s %1,63,8,%0"
4675 [(set_attr "type" "shift")
4676 (set_attr "length" "4")])
4678 (define_insn "extendhidi2"
4679 [(set (match_operand:DI 0 "register_operand" "=r")
4680 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4682 "extrd,s %1,63,16,%0"
4683 [(set_attr "type" "shift")
4684 (set_attr "length" "4")])
4686 (define_insn "extendsidi2"
4687 [(set (match_operand:DI 0 "register_operand" "=r")
4688 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4690 "extrd,s %1,63,32,%0"
4691 [(set_attr "type" "shift")
4692 (set_attr "length" "4")])
4695 ;; Conversions between float and double.
4697 (define_insn "extendsfdf2"
4698 [(set (match_operand:DF 0 "register_operand" "=f")
4700 (match_operand:SF 1 "register_operand" "f")))]
4701 "! TARGET_SOFT_FLOAT"
4702 "{fcnvff|fcnv},sgl,dbl %1,%0"
4703 [(set_attr "type" "fpalu")
4704 (set_attr "length" "4")])
4706 (define_insn "truncdfsf2"
4707 [(set (match_operand:SF 0 "register_operand" "=f")
4709 (match_operand:DF 1 "register_operand" "f")))]
4710 "! TARGET_SOFT_FLOAT"
4711 "{fcnvff|fcnv},dbl,sgl %1,%0"
4712 [(set_attr "type" "fpalu")
4713 (set_attr "length" "4")])
4715 ;; Conversion between fixed point and floating point.
4716 ;; Note that among the fix-to-float insns
4717 ;; the ones that start with SImode come first.
4718 ;; That is so that an operand that is a CONST_INT
4719 ;; (and therefore lacks a specific machine mode).
4720 ;; will be recognized as SImode (which is always valid)
4721 ;; rather than as QImode or HImode.
4723 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4724 ;; to be reloaded by putting the constant into memory.
4725 ;; It must come before the more general floatsisf2 pattern.
4727 [(set (match_operand:SF 0 "register_operand" "=f")
4728 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4729 "! TARGET_SOFT_FLOAT"
4730 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4731 [(set_attr "type" "fpalu")
4732 (set_attr "length" "8")])
4734 (define_insn "floatsisf2"
4735 [(set (match_operand:SF 0 "register_operand" "=f")
4736 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4737 "! TARGET_SOFT_FLOAT"
4738 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4739 [(set_attr "type" "fpalu")
4740 (set_attr "length" "4")])
4742 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4743 ;; to be reloaded by putting the constant into memory.
4744 ;; It must come before the more general floatsidf2 pattern.
4746 [(set (match_operand:DF 0 "register_operand" "=f")
4747 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4748 "! TARGET_SOFT_FLOAT"
4749 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4750 [(set_attr "type" "fpalu")
4751 (set_attr "length" "8")])
4753 (define_insn "floatsidf2"
4754 [(set (match_operand:DF 0 "register_operand" "=f")
4755 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4756 "! TARGET_SOFT_FLOAT"
4757 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4758 [(set_attr "type" "fpalu")
4759 (set_attr "length" "4")])
4761 (define_expand "floatunssisf2"
4762 [(set (subreg:SI (match_dup 2) 4)
4763 (match_operand:SI 1 "register_operand" ""))
4764 (set (subreg:SI (match_dup 2) 0)
4766 (set (match_operand:SF 0 "register_operand" "")
4767 (float:SF (match_dup 2)))]
4768 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4773 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4776 operands[2] = gen_reg_rtx (DImode);
4779 (define_expand "floatunssidf2"
4780 [(set (subreg:SI (match_dup 2) 4)
4781 (match_operand:SI 1 "register_operand" ""))
4782 (set (subreg:SI (match_dup 2) 0)
4784 (set (match_operand:DF 0 "register_operand" "")
4785 (float:DF (match_dup 2)))]
4786 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4791 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4794 operands[2] = gen_reg_rtx (DImode);
4797 (define_insn "floatdisf2"
4798 [(set (match_operand:SF 0 "register_operand" "=f")
4799 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4800 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4801 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4802 [(set_attr "type" "fpalu")
4803 (set_attr "length" "4")])
4805 (define_insn "floatdidf2"
4806 [(set (match_operand:DF 0 "register_operand" "=f")
4807 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4808 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4809 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4810 [(set_attr "type" "fpalu")
4811 (set_attr "length" "4")])
4813 ;; Convert a float to an actual integer.
4814 ;; Truncation is performed as part of the conversion.
4816 (define_insn "fix_truncsfsi2"
4817 [(set (match_operand:SI 0 "register_operand" "=f")
4818 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4819 "! TARGET_SOFT_FLOAT"
4820 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4821 [(set_attr "type" "fpalu")
4822 (set_attr "length" "4")])
4824 (define_insn "fix_truncdfsi2"
4825 [(set (match_operand:SI 0 "register_operand" "=f")
4826 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4827 "! TARGET_SOFT_FLOAT"
4828 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4829 [(set_attr "type" "fpalu")
4830 (set_attr "length" "4")])
4832 (define_insn "fix_truncsfdi2"
4833 [(set (match_operand:DI 0 "register_operand" "=f")
4834 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4835 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4836 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4837 [(set_attr "type" "fpalu")
4838 (set_attr "length" "4")])
4840 (define_insn "fix_truncdfdi2"
4841 [(set (match_operand:DI 0 "register_operand" "=f")
4842 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4843 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4844 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4845 [(set_attr "type" "fpalu")
4846 (set_attr "length" "4")])
4848 (define_insn "floatunssidf2_pa20"
4849 [(set (match_operand:DF 0 "register_operand" "=f")
4850 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4851 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4853 [(set_attr "type" "fpalu")
4854 (set_attr "length" "4")])
4856 (define_insn "floatunssisf2_pa20"
4857 [(set (match_operand:SF 0 "register_operand" "=f")
4858 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4859 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4861 [(set_attr "type" "fpalu")
4862 (set_attr "length" "4")])
4864 (define_insn "floatunsdisf2"
4865 [(set (match_operand:SF 0 "register_operand" "=f")
4866 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4867 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4868 "fcnv,udw,sgl %1,%0"
4869 [(set_attr "type" "fpalu")
4870 (set_attr "length" "4")])
4872 (define_insn "floatunsdidf2"
4873 [(set (match_operand:DF 0 "register_operand" "=f")
4874 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4875 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4876 "fcnv,udw,dbl %1,%0"
4877 [(set_attr "type" "fpalu")
4878 (set_attr "length" "4")])
4880 (define_insn "fixuns_truncsfsi2"
4881 [(set (match_operand:SI 0 "register_operand" "=f")
4882 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4883 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4884 "fcnv,t,sgl,uw %1,%0"
4885 [(set_attr "type" "fpalu")
4886 (set_attr "length" "4")])
4888 (define_insn "fixuns_truncdfsi2"
4889 [(set (match_operand:SI 0 "register_operand" "=f")
4890 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4891 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4892 "fcnv,t,dbl,uw %1,%0"
4893 [(set_attr "type" "fpalu")
4894 (set_attr "length" "4")])
4896 (define_insn "fixuns_truncsfdi2"
4897 [(set (match_operand:DI 0 "register_operand" "=f")
4898 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4899 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4900 "fcnv,t,sgl,udw %1,%0"
4901 [(set_attr "type" "fpalu")
4902 (set_attr "length" "4")])
4904 (define_insn "fixuns_truncdfdi2"
4905 [(set (match_operand:DI 0 "register_operand" "=f")
4906 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4907 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4908 "fcnv,t,dbl,udw %1,%0"
4909 [(set_attr "type" "fpalu")
4910 (set_attr "length" "4")])
4912 ;;- arithmetic instructions
4914 (define_expand "adddi3"
4915 [(set (match_operand:DI 0 "register_operand" "")
4916 (plus:DI (match_operand:DI 1 "register_operand" "")
4917 (match_operand:DI 2 "adddi3_operand" "")))]
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4924 (match_operand:DI 2 "arith11_operand" "rI")))]
4928 if (GET_CODE (operands[2]) == CONST_INT)
4930 if (INTVAL (operands[2]) >= 0)
4931 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4933 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4936 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4938 [(set_attr "type" "binary")
4939 (set_attr "length" "8")])
4942 [(set (match_operand:DI 0 "register_operand" "=r,r")
4943 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4944 (match_operand:DI 2 "arith_operand" "r,J")))]
4949 [(set_attr "type" "binary,binary")
4950 (set_attr "pa_combine_type" "addmove")
4951 (set_attr "length" "4,4")])
4954 [(set (match_operand:DI 0 "register_operand" "=r")
4955 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4956 (match_operand:DI 2 "register_operand" "r")))]
4959 [(set_attr "type" "binary")
4960 (set_attr "length" "4")])
4963 [(set (match_operand:SI 0 "register_operand" "=r")
4964 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4965 (match_operand:SI 2 "register_operand" "r")))]
4968 [(set_attr "type" "binary")
4969 (set_attr "length" "4")])
4971 (define_expand "addvdi3"
4972 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4973 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4974 (match_operand:DI 2 "arith11_operand" "")))
4975 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4976 (sign_extend:TI (match_dup 2)))
4977 (sign_extend:TI (plus:DI (match_dup 1)
4984 [(set (match_operand:DI 0 "register_operand" "=r,r")
4985 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4986 (match_operand:DI 2 "arith11_operand" "r,I")))
4987 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4988 (sign_extend:TI (match_dup 2)))
4989 (sign_extend:TI (plus:DI (match_dup 1)
4995 addi,tsv,* %2,%1,%0"
4996 [(set_attr "type" "binary,binary")
4997 (set_attr "length" "4,4")])
5000 [(set (match_operand:DI 0 "register_operand" "=r")
5001 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5002 (match_operand:DI 2 "arith11_operand" "rI")))
5003 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5004 (sign_extend:TI (match_dup 2)))
5005 (sign_extend:TI (plus:DI (match_dup 1)
5011 if (GET_CODE (operands[2]) == CONST_INT)
5013 if (INTVAL (operands[2]) >= 0)
5014 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5016 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5019 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5021 [(set_attr "type" "binary")
5022 (set_attr "length" "8")])
5024 ;; define_splits to optimize cases of adding a constant integer
5025 ;; to a register when the constant does not fit in 14 bits. */
5027 [(set (match_operand:SI 0 "register_operand" "")
5028 (plus:SI (match_operand:SI 1 "register_operand" "")
5029 (match_operand:SI 2 "const_int_operand" "")))
5030 (clobber (match_operand:SI 4 "register_operand" ""))]
5031 "! cint_ok_for_move (INTVAL (operands[2]))
5032 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5033 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5034 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5037 int val = INTVAL (operands[2]);
5038 int low = (val < 0) ? -0x2000 : 0x1fff;
5039 int rest = val - low;
5041 operands[2] = GEN_INT (rest);
5042 operands[3] = GEN_INT (low);
5046 [(set (match_operand:SI 0 "register_operand" "")
5047 (plus:SI (match_operand:SI 1 "register_operand" "")
5048 (match_operand:SI 2 "const_int_operand" "")))
5049 (clobber (match_operand:SI 4 "register_operand" ""))]
5050 "! cint_ok_for_move (INTVAL (operands[2]))"
5051 [(set (match_dup 4) (match_dup 2))
5052 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5056 HOST_WIDE_INT intval = INTVAL (operands[2]);
5058 /* Try dividing the constant by 2, then 4, and finally 8 to see
5059 if we can get a constant which can be loaded into a register
5060 in a single instruction (cint_ok_for_move).
5062 If that fails, try to negate the constant and subtract it
5063 from our input operand. */
5064 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5066 operands[2] = GEN_INT (intval / 2);
5067 operands[3] = const2_rtx;
5069 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5071 operands[2] = GEN_INT (intval / 4);
5072 operands[3] = GEN_INT (4);
5074 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5076 operands[2] = GEN_INT (intval / 8);
5077 operands[3] = GEN_INT (8);
5079 else if (cint_ok_for_move (-intval))
5081 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5082 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5089 (define_insn "addsi3"
5090 [(set (match_operand:SI 0 "register_operand" "=r,r")
5091 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5092 (match_operand:SI 2 "arith_operand" "r,J")))]
5095 {addl|add,l} %1,%2,%0
5097 [(set_attr "type" "binary,binary")
5098 (set_attr "pa_combine_type" "addmove")
5099 (set_attr "length" "4,4")])
5101 (define_insn "addvsi3"
5102 [(set (match_operand:SI 0 "register_operand" "=r,r")
5103 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5104 (match_operand:SI 2 "arith11_operand" "r,I")))
5105 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5106 (sign_extend:DI (match_dup 2)))
5107 (sign_extend:DI (plus:SI (match_dup 1)
5112 {addo|add,tsv} %2,%1,%0
5113 {addio|addi,tsv} %2,%1,%0"
5114 [(set_attr "type" "binary,binary")
5115 (set_attr "length" "4,4")])
5117 (define_expand "subdi3"
5118 [(set (match_operand:DI 0 "register_operand" "")
5119 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5120 (match_operand:DI 2 "reg_or_0_operand" "")))]
5125 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5126 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5127 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5133 [(set_attr "type" "binary,binary,move")
5134 (set_attr "length" "4,4,4")])
5137 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5138 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5139 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5143 if (GET_CODE (operands[1]) == CONST_INT)
5145 if (INTVAL (operands[1]) >= 0)
5146 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5148 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5151 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5153 [(set_attr "type" "binary")
5154 (set (attr "length")
5155 (if_then_else (eq_attr "alternative" "0")
5157 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5162 (define_expand "subvdi3"
5163 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5164 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5165 (match_operand:DI 2 "reg_or_0_operand" "")))
5166 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5167 (sign_extend:TI (match_dup 2)))
5168 (sign_extend:TI (minus:DI (match_dup 1)
5175 [(set (match_operand:DI 0 "register_operand" "=r,r")
5176 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5177 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5178 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5179 (sign_extend:TI (match_dup 2)))
5180 (sign_extend:TI (minus:DI (match_dup 1)
5185 {subo|sub,tsv} %1,%2,%0
5186 {subio|subi,tsv} %1,%2,%0"
5187 [(set_attr "type" "binary,binary")
5188 (set_attr "length" "4,4")])
5191 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5192 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5193 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5194 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5195 (sign_extend:TI (match_dup 2)))
5196 (sign_extend:TI (minus:DI (match_dup 1)
5202 if (GET_CODE (operands[1]) == CONST_INT)
5204 if (INTVAL (operands[1]) >= 0)
5205 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5207 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5210 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5212 [(set_attr "type" "binary,binary")
5213 (set (attr "length")
5214 (if_then_else (eq_attr "alternative" "0")
5216 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5221 (define_expand "subsi3"
5222 [(set (match_operand:SI 0 "register_operand" "")
5223 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5224 (match_operand:SI 2 "register_operand" "")))]
5229 [(set (match_operand:SI 0 "register_operand" "=r,r")
5230 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5231 (match_operand:SI 2 "register_operand" "r,r")))]
5236 [(set_attr "type" "binary,binary")
5237 (set_attr "length" "4,4")])
5240 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5241 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5242 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5248 [(set_attr "type" "binary,binary,move")
5249 (set_attr "length" "4,4,4")])
5251 (define_insn "subvsi3"
5252 [(set (match_operand:SI 0 "register_operand" "=r,r")
5253 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5254 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5255 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5256 (sign_extend:DI (match_dup 2)))
5257 (sign_extend:DI (minus:SI (match_dup 1)
5262 {subo|sub,tsv} %1,%2,%0
5263 {subio|subi,tsv} %1,%2,%0"
5264 [(set_attr "type" "binary,binary")
5265 (set_attr "length" "4,4")])
5267 ;; Clobbering a "register_operand" instead of a match_scratch
5268 ;; in operand3 of millicode calls avoids spilling %r1 and
5269 ;; produces better code.
5271 ;; The mulsi3 insns set up registers for the millicode call.
5272 (define_expand "mulsi3"
5273 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5274 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5275 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5276 (clobber (match_dup 3))
5277 (clobber (reg:SI 26))
5278 (clobber (reg:SI 25))
5279 (clobber (match_dup 4))])
5280 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5284 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5285 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5287 rtx scratch = gen_reg_rtx (DImode);
5288 operands[1] = force_reg (SImode, operands[1]);
5289 operands[2] = force_reg (SImode, operands[2]);
5290 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5291 emit_insn (gen_movsi (operands[0],
5292 gen_rtx_SUBREG (SImode, scratch,
5293 GET_MODE_SIZE (SImode))));
5296 operands[3] = gen_reg_rtx (SImode);
5299 (define_insn "umulsidi3"
5300 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5301 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5302 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5303 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5305 [(set_attr "type" "fpmuldbl")
5306 (set_attr "length" "4")])
5309 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5310 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5311 (match_operand:DI 2 "uint32_operand" "f")))]
5312 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5314 [(set_attr "type" "fpmuldbl")
5315 (set_attr "length" "4")])
5318 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5319 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5320 (match_operand:DI 2 "uint32_operand" "f")))]
5321 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5323 [(set_attr "type" "fpmuldbl")
5324 (set_attr "length" "4")])
5327 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5328 (clobber (match_operand:SI 0 "register_operand" "=a"))
5329 (clobber (reg:SI 26))
5330 (clobber (reg:SI 25))
5331 (clobber (reg:SI 31))]
5333 "* return output_mul_insn (0, insn);"
5334 [(set_attr "type" "milli")
5335 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5338 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5339 (clobber (match_operand:SI 0 "register_operand" "=a"))
5340 (clobber (reg:SI 26))
5341 (clobber (reg:SI 25))
5342 (clobber (reg:SI 2))]
5344 "* return output_mul_insn (0, insn);"
5345 [(set_attr "type" "milli")
5346 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5348 (define_expand "muldi3"
5349 [(set (match_operand:DI 0 "register_operand" "")
5350 (mult:DI (match_operand:DI 1 "register_operand" "")
5351 (match_operand:DI 2 "register_operand" "")))]
5352 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5355 rtx low_product = gen_reg_rtx (DImode);
5356 rtx cross_product1 = gen_reg_rtx (DImode);
5357 rtx cross_product2 = gen_reg_rtx (DImode);
5358 rtx cross_scratch = gen_reg_rtx (DImode);
5359 rtx cross_product = gen_reg_rtx (DImode);
5360 rtx op1l, op1r, op2l, op2r;
5361 rtx op1shifted, op2shifted;
5363 op1shifted = gen_reg_rtx (DImode);
5364 op2shifted = gen_reg_rtx (DImode);
5365 op1l = gen_reg_rtx (SImode);
5366 op1r = gen_reg_rtx (SImode);
5367 op2l = gen_reg_rtx (SImode);
5368 op2r = gen_reg_rtx (SImode);
5370 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5372 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5374 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5375 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5376 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5377 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5379 /* Emit multiplies for the cross products. */
5380 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5381 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5383 /* Emit a multiply for the low sub-word. */
5384 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5386 /* Sum the cross products and shift them into proper position. */
5387 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5388 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5390 /* Add the cross product to the low product and store the result
5391 into the output operand . */
5392 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5396 ;;; Division and mod.
5397 (define_expand "divsi3"
5398 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5399 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5400 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5401 (clobber (match_dup 3))
5402 (clobber (match_dup 4))
5403 (clobber (reg:SI 26))
5404 (clobber (reg:SI 25))
5405 (clobber (match_dup 5))])
5406 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5410 operands[3] = gen_reg_rtx (SImode);
5413 operands[5] = gen_rtx_REG (SImode, 2);
5414 operands[4] = operands[5];
5418 operands[5] = gen_rtx_REG (SImode, 31);
5419 operands[4] = gen_reg_rtx (SImode);
5421 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5427 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5428 (clobber (match_operand:SI 1 "register_operand" "=a"))
5429 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5430 (clobber (reg:SI 26))
5431 (clobber (reg:SI 25))
5432 (clobber (reg:SI 31))]
5435 return output_div_insn (operands, 0, insn);"
5436 [(set_attr "type" "milli")
5437 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5441 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5442 (clobber (match_operand:SI 1 "register_operand" "=a"))
5443 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5444 (clobber (reg:SI 26))
5445 (clobber (reg:SI 25))
5446 (clobber (reg:SI 2))]
5449 return output_div_insn (operands, 0, insn);"
5450 [(set_attr "type" "milli")
5451 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5453 (define_expand "udivsi3"
5454 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5455 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5456 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5457 (clobber (match_dup 3))
5458 (clobber (match_dup 4))
5459 (clobber (reg:SI 26))
5460 (clobber (reg:SI 25))
5461 (clobber (match_dup 5))])
5462 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5466 operands[3] = gen_reg_rtx (SImode);
5470 operands[5] = gen_rtx_REG (SImode, 2);
5471 operands[4] = operands[5];
5475 operands[5] = gen_rtx_REG (SImode, 31);
5476 operands[4] = gen_reg_rtx (SImode);
5478 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5484 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5485 (clobber (match_operand:SI 1 "register_operand" "=a"))
5486 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5487 (clobber (reg:SI 26))
5488 (clobber (reg:SI 25))
5489 (clobber (reg:SI 31))]
5492 return output_div_insn (operands, 1, insn);"
5493 [(set_attr "type" "milli")
5494 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5498 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5499 (clobber (match_operand:SI 1 "register_operand" "=a"))
5500 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5501 (clobber (reg:SI 26))
5502 (clobber (reg:SI 25))
5503 (clobber (reg:SI 2))]
5506 return output_div_insn (operands, 1, insn);"
5507 [(set_attr "type" "milli")
5508 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5510 (define_expand "modsi3"
5511 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5512 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5513 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5514 (clobber (match_dup 3))
5515 (clobber (match_dup 4))
5516 (clobber (reg:SI 26))
5517 (clobber (reg:SI 25))
5518 (clobber (match_dup 5))])
5519 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5525 operands[5] = gen_rtx_REG (SImode, 2);
5526 operands[4] = operands[5];
5530 operands[5] = gen_rtx_REG (SImode, 31);
5531 operands[4] = gen_reg_rtx (SImode);
5533 operands[3] = gen_reg_rtx (SImode);
5537 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5538 (clobber (match_operand:SI 0 "register_operand" "=a"))
5539 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5540 (clobber (reg:SI 26))
5541 (clobber (reg:SI 25))
5542 (clobber (reg:SI 31))]
5545 return output_mod_insn (0, insn);"
5546 [(set_attr "type" "milli")
5547 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5550 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5551 (clobber (match_operand:SI 0 "register_operand" "=a"))
5552 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5553 (clobber (reg:SI 26))
5554 (clobber (reg:SI 25))
5555 (clobber (reg:SI 2))]
5558 return output_mod_insn (0, insn);"
5559 [(set_attr "type" "milli")
5560 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5562 (define_expand "umodsi3"
5563 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5564 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5565 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5566 (clobber (match_dup 3))
5567 (clobber (match_dup 4))
5568 (clobber (reg:SI 26))
5569 (clobber (reg:SI 25))
5570 (clobber (match_dup 5))])
5571 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5577 operands[5] = gen_rtx_REG (SImode, 2);
5578 operands[4] = operands[5];
5582 operands[5] = gen_rtx_REG (SImode, 31);
5583 operands[4] = gen_reg_rtx (SImode);
5585 operands[3] = gen_reg_rtx (SImode);
5589 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5590 (clobber (match_operand:SI 0 "register_operand" "=a"))
5591 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5592 (clobber (reg:SI 26))
5593 (clobber (reg:SI 25))
5594 (clobber (reg:SI 31))]
5597 return output_mod_insn (1, insn);"
5598 [(set_attr "type" "milli")
5599 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5602 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5603 (clobber (match_operand:SI 0 "register_operand" "=a"))
5604 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5605 (clobber (reg:SI 26))
5606 (clobber (reg:SI 25))
5607 (clobber (reg:SI 2))]
5610 return output_mod_insn (1, insn);"
5611 [(set_attr "type" "milli")
5612 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5614 ;;- and instructions
5615 ;; We define DImode `and` so with DImode `not` we can get
5616 ;; DImode `andn`. Other combinations are possible.
5618 (define_expand "anddi3"
5619 [(set (match_operand:DI 0 "register_operand" "")
5620 (and:DI (match_operand:DI 1 "register_operand" "")
5621 (match_operand:DI 2 "and_operand" "")))]
5625 /* Both operands must be register operands. */
5626 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5631 [(set (match_operand:DI 0 "register_operand" "=r")
5632 (and:DI (match_operand:DI 1 "register_operand" "%r")
5633 (match_operand:DI 2 "register_operand" "r")))]
5635 "and %1,%2,%0\;and %R1,%R2,%R0"
5636 [(set_attr "type" "binary")
5637 (set_attr "length" "8")])
5640 [(set (match_operand:DI 0 "register_operand" "=r,r")
5641 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5642 (match_operand:DI 2 "and_operand" "rO,P")))]
5644 "* return output_64bit_and (operands); "
5645 [(set_attr "type" "binary")
5646 (set_attr "length" "4")])
5648 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5649 ; constant with ldil;ldo.
5650 (define_insn "andsi3"
5651 [(set (match_operand:SI 0 "register_operand" "=r,r")
5652 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5653 (match_operand:SI 2 "and_operand" "rO,P")))]
5655 "* return output_and (operands); "
5656 [(set_attr "type" "binary,shift")
5657 (set_attr "length" "4,4")])
5660 [(set (match_operand:DI 0 "register_operand" "=r")
5661 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5662 (match_operand:DI 2 "register_operand" "r")))]
5664 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5665 [(set_attr "type" "binary")
5666 (set_attr "length" "8")])
5669 [(set (match_operand:DI 0 "register_operand" "=r")
5670 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5671 (match_operand:DI 2 "register_operand" "r")))]
5674 [(set_attr "type" "binary")
5675 (set_attr "length" "4")])
5678 [(set (match_operand:SI 0 "register_operand" "=r")
5679 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5680 (match_operand:SI 2 "register_operand" "r")))]
5683 [(set_attr "type" "binary")
5684 (set_attr "length" "4")])
5686 (define_expand "iordi3"
5687 [(set (match_operand:DI 0 "register_operand" "")
5688 (ior:DI (match_operand:DI 1 "register_operand" "")
5689 (match_operand:DI 2 "ior_operand" "")))]
5693 /* Both operands must be register operands. */
5694 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5699 [(set (match_operand:DI 0 "register_operand" "=r")
5700 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5701 (match_operand:DI 2 "register_operand" "r")))]
5703 "or %1,%2,%0\;or %R1,%R2,%R0"
5704 [(set_attr "type" "binary")
5705 (set_attr "length" "8")])
5708 [(set (match_operand:DI 0 "register_operand" "=r,r")
5709 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5710 (match_operand:DI 2 "ior_operand" "M,i")))]
5712 "* return output_64bit_ior (operands); "
5713 [(set_attr "type" "binary,shift")
5714 (set_attr "length" "4,4")])
5717 [(set (match_operand:DI 0 "register_operand" "=r")
5718 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5719 (match_operand:DI 2 "register_operand" "r")))]
5722 [(set_attr "type" "binary")
5723 (set_attr "length" "4")])
5725 ;; Need a define_expand because we've run out of CONST_OK... characters.
5726 (define_expand "iorsi3"
5727 [(set (match_operand:SI 0 "register_operand" "")
5728 (ior:SI (match_operand:SI 1 "register_operand" "")
5729 (match_operand:SI 2 "arith32_operand" "")))]
5733 if (! (ior_operand (operands[2], SImode)
5734 || register_operand (operands[2], SImode)))
5735 operands[2] = force_reg (SImode, operands[2]);
5739 [(set (match_operand:SI 0 "register_operand" "=r,r")
5740 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5741 (match_operand:SI 2 "ior_operand" "M,i")))]
5743 "* return output_ior (operands); "
5744 [(set_attr "type" "binary,shift")
5745 (set_attr "length" "4,4")])
5748 [(set (match_operand:SI 0 "register_operand" "=r")
5749 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5750 (match_operand:SI 2 "register_operand" "r")))]
5753 [(set_attr "type" "binary")
5754 (set_attr "length" "4")])
5756 (define_expand "xordi3"
5757 [(set (match_operand:DI 0 "register_operand" "")
5758 (xor:DI (match_operand:DI 1 "register_operand" "")
5759 (match_operand:DI 2 "register_operand" "")))]
5766 [(set (match_operand:DI 0 "register_operand" "=r")
5767 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5768 (match_operand:DI 2 "register_operand" "r")))]
5770 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5771 [(set_attr "type" "binary")
5772 (set_attr "length" "8")])
5775 [(set (match_operand:DI 0 "register_operand" "=r")
5776 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5777 (match_operand:DI 2 "register_operand" "r")))]
5780 [(set_attr "type" "binary")
5781 (set_attr "length" "4")])
5783 (define_insn "xorsi3"
5784 [(set (match_operand:SI 0 "register_operand" "=r")
5785 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5786 (match_operand:SI 2 "register_operand" "r")))]
5789 [(set_attr "type" "binary")
5790 (set_attr "length" "4")])
5792 (define_expand "negdi2"
5793 [(set (match_operand:DI 0 "register_operand" "")
5794 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5799 [(set (match_operand:DI 0 "register_operand" "=r")
5800 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5802 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5803 [(set_attr "type" "unary")
5804 (set_attr "length" "8")])
5807 [(set (match_operand:DI 0 "register_operand" "=r")
5808 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5811 [(set_attr "type" "unary")
5812 (set_attr "length" "4")])
5814 (define_expand "negvdi2"
5815 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5816 (neg:DI (match_operand:DI 1 "register_operand" "")))
5817 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5818 (sign_extend:TI (neg:DI (match_dup 1))))
5824 [(set (match_operand:DI 0 "register_operand" "=r")
5825 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5826 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5827 (sign_extend:TI (neg:DI (match_dup 1))))
5830 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5831 [(set_attr "type" "unary")
5832 (set_attr "length" "8")])
5835 [(set (match_operand:DI 0 "register_operand" "=r")
5836 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5837 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5838 (sign_extend:TI (neg:DI (match_dup 1))))
5841 "sub,tsv %%r0,%1,%0"
5842 [(set_attr "type" "unary")
5843 (set_attr "length" "4")])
5845 (define_insn "negsi2"
5846 [(set (match_operand:SI 0 "register_operand" "=r")
5847 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5850 [(set_attr "type" "unary")
5851 (set_attr "length" "4")])
5853 (define_insn "negvsi2"
5854 [(set (match_operand:SI 0 "register_operand" "=r")
5855 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5856 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5857 (sign_extend:DI (neg:SI (match_dup 1))))
5860 "{subo|sub,tsv} %%r0,%1,%0"
5861 [(set_attr "type" "unary")
5862 (set_attr "length" "4")])
5864 (define_expand "one_cmpldi2"
5865 [(set (match_operand:DI 0 "register_operand" "")
5866 (not:DI (match_operand:DI 1 "register_operand" "")))]
5873 [(set (match_operand:DI 0 "register_operand" "=r")
5874 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5876 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5877 [(set_attr "type" "unary")
5878 (set_attr "length" "8")])
5881 [(set (match_operand:DI 0 "register_operand" "=r")
5882 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5885 [(set_attr "type" "unary")
5886 (set_attr "length" "4")])
5888 (define_insn "one_cmplsi2"
5889 [(set (match_operand:SI 0 "register_operand" "=r")
5890 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5893 [(set_attr "type" "unary")
5894 (set_attr "length" "4")])
5896 ;; Floating point arithmetic instructions.
5898 (define_insn "adddf3"
5899 [(set (match_operand:DF 0 "register_operand" "=f")
5900 (plus:DF (match_operand:DF 1 "register_operand" "f")
5901 (match_operand:DF 2 "register_operand" "f")))]
5902 "! TARGET_SOFT_FLOAT"
5904 [(set_attr "type" "fpalu")
5905 (set_attr "pa_combine_type" "faddsub")
5906 (set_attr "length" "4")])
5908 (define_insn "addsf3"
5909 [(set (match_operand:SF 0 "register_operand" "=f")
5910 (plus:SF (match_operand:SF 1 "register_operand" "f")
5911 (match_operand:SF 2 "register_operand" "f")))]
5912 "! TARGET_SOFT_FLOAT"
5914 [(set_attr "type" "fpalu")
5915 (set_attr "pa_combine_type" "faddsub")
5916 (set_attr "length" "4")])
5918 (define_insn "subdf3"
5919 [(set (match_operand:DF 0 "register_operand" "=f")
5920 (minus:DF (match_operand:DF 1 "register_operand" "f")
5921 (match_operand:DF 2 "register_operand" "f")))]
5922 "! TARGET_SOFT_FLOAT"
5924 [(set_attr "type" "fpalu")
5925 (set_attr "pa_combine_type" "faddsub")
5926 (set_attr "length" "4")])
5928 (define_insn "subsf3"
5929 [(set (match_operand:SF 0 "register_operand" "=f")
5930 (minus:SF (match_operand:SF 1 "register_operand" "f")
5931 (match_operand:SF 2 "register_operand" "f")))]
5932 "! TARGET_SOFT_FLOAT"
5934 [(set_attr "type" "fpalu")
5935 (set_attr "pa_combine_type" "faddsub")
5936 (set_attr "length" "4")])
5938 (define_insn "muldf3"
5939 [(set (match_operand:DF 0 "register_operand" "=f")
5940 (mult:DF (match_operand:DF 1 "register_operand" "f")
5941 (match_operand:DF 2 "register_operand" "f")))]
5942 "! TARGET_SOFT_FLOAT"
5944 [(set_attr "type" "fpmuldbl")
5945 (set_attr "pa_combine_type" "fmpy")
5946 (set_attr "length" "4")])
5948 (define_insn "mulsf3"
5949 [(set (match_operand:SF 0 "register_operand" "=f")
5950 (mult:SF (match_operand:SF 1 "register_operand" "f")
5951 (match_operand:SF 2 "register_operand" "f")))]
5952 "! TARGET_SOFT_FLOAT"
5954 [(set_attr "type" "fpmulsgl")
5955 (set_attr "pa_combine_type" "fmpy")
5956 (set_attr "length" "4")])
5958 (define_insn "divdf3"
5959 [(set (match_operand:DF 0 "register_operand" "=f")
5960 (div:DF (match_operand:DF 1 "register_operand" "f")
5961 (match_operand:DF 2 "register_operand" "f")))]
5962 "! TARGET_SOFT_FLOAT"
5964 [(set_attr "type" "fpdivdbl")
5965 (set_attr "length" "4")])
5967 (define_insn "divsf3"
5968 [(set (match_operand:SF 0 "register_operand" "=f")
5969 (div:SF (match_operand:SF 1 "register_operand" "f")
5970 (match_operand:SF 2 "register_operand" "f")))]
5971 "! TARGET_SOFT_FLOAT"
5973 [(set_attr "type" "fpdivsgl")
5974 (set_attr "length" "4")])
5976 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5977 ;; negation can be done by subtracting from plus zero. However, this
5978 ;; violates the IEEE standard when negating plus and minus zero.
5979 ;; The slow path toggles the sign bit in the general registers.
5980 (define_expand "negdf2"
5981 [(set (match_operand:DF 0 "register_operand" "")
5982 (neg:DF (match_operand:DF 1 "register_operand" "")))]
5983 "!TARGET_SOFT_FLOAT"
5985 if (TARGET_PA_20 || !flag_signed_zeros)
5986 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5988 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
5992 (define_insn "negdf2_slow"
5993 [(set (match_operand:DF 0 "register_operand" "=r")
5994 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
5995 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5998 if (rtx_equal_p (operands[0], operands[1]))
5999 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
6001 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
6003 [(set_attr "type" "multi")
6004 (set (attr "length")
6005 (if_then_else (ne (symbol_ref "rtx_equal_p (operands[0], operands[1])")
6010 (define_insn "negdf2_fast"
6011 [(set (match_operand:DF 0 "register_operand" "=f")
6012 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6013 "!TARGET_SOFT_FLOAT"
6017 return \"fneg,dbl %1,%0\";
6019 return \"fsub,dbl %%fr0,%1,%0\";
6021 [(set_attr "type" "fpalu")
6022 (set_attr "length" "4")])
6024 (define_expand "negsf2"
6025 [(set (match_operand:SF 0 "register_operand" "")
6026 (neg:SF (match_operand:SF 1 "register_operand" "")))]
6027 "!TARGET_SOFT_FLOAT"
6029 if (TARGET_PA_20 || !flag_signed_zeros)
6030 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6032 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
6036 (define_insn "negsf2_slow"
6037 [(set (match_operand:SF 0 "register_operand" "=r")
6038 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
6039 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6040 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
6041 [(set_attr "type" "multi")
6042 (set_attr "length" "12")])
6044 (define_insn "negsf2_fast"
6045 [(set (match_operand:SF 0 "register_operand" "=f")
6046 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6047 "!TARGET_SOFT_FLOAT"
6051 return \"fneg,sgl %1,%0\";
6053 return \"fsub,sgl %%fr0,%1,%0\";
6055 [(set_attr "type" "fpalu")
6056 (set_attr "length" "4")])
6058 (define_insn "absdf2"
6059 [(set (match_operand:DF 0 "register_operand" "=f")
6060 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6061 "! TARGET_SOFT_FLOAT"
6063 [(set_attr "type" "fpalu")
6064 (set_attr "length" "4")])
6066 (define_insn "abssf2"
6067 [(set (match_operand:SF 0 "register_operand" "=f")
6068 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6069 "! TARGET_SOFT_FLOAT"
6071 [(set_attr "type" "fpalu")
6072 (set_attr "length" "4")])
6074 (define_insn "sqrtdf2"
6075 [(set (match_operand:DF 0 "register_operand" "=f")
6076 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6077 "! TARGET_SOFT_FLOAT"
6079 [(set_attr "type" "fpsqrtdbl")
6080 (set_attr "length" "4")])
6082 (define_insn "sqrtsf2"
6083 [(set (match_operand:SF 0 "register_operand" "=f")
6084 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6085 "! TARGET_SOFT_FLOAT"
6087 [(set_attr "type" "fpsqrtsgl")
6088 (set_attr "length" "4")])
6090 ;; PA 2.0 floating point instructions
6093 (define_insn "fmadf4"
6094 [(set (match_operand:DF 0 "register_operand" "=f")
6095 (fma:DF (match_operand:DF 1 "register_operand" "f")
6096 (match_operand:DF 2 "register_operand" "f")
6097 (match_operand:DF 3 "register_operand" "f")))]
6098 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6099 "fmpyfadd,dbl %1,%2,%3,%0"
6100 [(set_attr "type" "fpmuldbl")
6101 (set_attr "length" "4")])
6103 (define_insn "fmasf4"
6104 [(set (match_operand:SF 0 "register_operand" "=f")
6105 (fma:SF (match_operand:SF 1 "register_operand" "f")
6106 (match_operand:SF 2 "register_operand" "f")
6107 (match_operand:SF 3 "register_operand" "f")))]
6108 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6109 "fmpyfadd,sgl %1,%2,%3,%0"
6110 [(set_attr "type" "fpmulsgl")
6111 (set_attr "length" "4")])
6113 ; fmpynfadd patterns
6114 (define_insn "fnmadf4"
6115 [(set (match_operand:DF 0 "register_operand" "=f")
6116 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6117 (match_operand:DF 2 "register_operand" "f")
6118 (match_operand:DF 3 "register_operand" "f")))]
6119 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6120 "fmpynfadd,dbl %1,%2,%3,%0"
6121 [(set_attr "type" "fpmuldbl")
6122 (set_attr "length" "4")])
6124 (define_insn "fnmasf4"
6125 [(set (match_operand:SF 0 "register_operand" "=f")
6126 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6127 (match_operand:SF 2 "register_operand" "f")
6128 (match_operand:SF 3 "register_operand" "f")))]
6129 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6130 "fmpynfadd,sgl %1,%2,%3,%0"
6131 [(set_attr "type" "fpmulsgl")
6132 (set_attr "length" "4")])
6136 [(set (match_operand:DF 0 "register_operand" "=f")
6137 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6138 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6140 [(set_attr "type" "fpalu")
6141 (set_attr "length" "4")])
6144 [(set (match_operand:SF 0 "register_operand" "=f")
6145 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6146 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6148 [(set_attr "type" "fpalu")
6149 (set_attr "length" "4")])
6152 [(set (match_operand:DF 0 "register_operand" "=f")
6153 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6154 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6155 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6156 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6158 [(set_attr "type" "fpalu")
6159 (set_attr "length" "8")])
6162 [(set (match_operand:DF 0 "register_operand" "")
6163 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6164 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6165 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6166 [(set (match_dup 2) (abs:DF (match_dup 1)))
6167 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6171 [(set (match_operand:SF 0 "register_operand" "=f")
6172 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6173 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6174 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6175 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6177 [(set_attr "type" "fpalu")
6178 (set_attr "length" "8")])
6181 [(set (match_operand:SF 0 "register_operand" "")
6182 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6183 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6184 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6185 [(set (match_dup 2) (abs:SF (match_dup 1)))
6186 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6189 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6190 ;; instruction if we can ignore the sign of zero.
6192 [(set (match_operand:DF 0 "register_operand" "=f")
6193 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6194 (match_operand:DF 2 "register_operand" "f"))))]
6195 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6196 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6197 [(set_attr "type" "fpmuldbl")
6198 (set_attr "length" "4")])
6201 [(set (match_operand:SF 0 "register_operand" "=f")
6202 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6203 (match_operand:SF 2 "register_operand" "f"))))]
6204 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6205 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6206 [(set_attr "type" "fpmuldbl")
6207 (set_attr "length" "4")])
6210 [(set (match_operand:DF 0 "register_operand" "=f")
6211 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6212 (match_operand:DF 2 "register_operand" "f"))))
6213 (set (match_operand:DF 3 "register_operand" "=&f")
6214 (mult:DF (match_dup 1) (match_dup 2)))]
6215 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6216 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6217 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6219 [(set_attr "type" "fpmuldbl")
6220 (set_attr "length" "8")])
6223 [(set (match_operand:DF 0 "register_operand" "")
6224 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6225 (match_operand:DF 2 "register_operand" ""))))
6226 (set (match_operand:DF 3 "register_operand" "")
6227 (mult:DF (match_dup 1) (match_dup 2)))]
6228 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6229 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6230 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6234 [(set (match_operand:SF 0 "register_operand" "=f")
6235 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6236 (match_operand:SF 2 "register_operand" "f"))))
6237 (set (match_operand:SF 3 "register_operand" "=&f")
6238 (mult:SF (match_dup 1) (match_dup 2)))]
6239 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6240 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6241 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6243 [(set_attr "type" "fpmuldbl")
6244 (set_attr "length" "8")])
6247 [(set (match_operand:SF 0 "register_operand" "")
6248 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6249 (match_operand:SF 2 "register_operand" ""))))
6250 (set (match_operand:SF 3 "register_operand" "")
6251 (mult:SF (match_dup 1) (match_dup 2)))]
6252 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6253 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6254 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6257 ;;- Shift instructions
6259 ;; Optimized special case of shifting.
6262 [(set (match_operand:SI 0 "register_operand" "=r")
6263 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6267 [(set_attr "type" "load")
6268 (set_attr "length" "4")])
6271 [(set (match_operand:SI 0 "register_operand" "=r")
6272 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6276 [(set_attr "type" "load")
6277 (set_attr "length" "4")])
6280 [(set (match_operand:SI 0 "register_operand" "=r")
6281 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6282 (match_operand:SI 3 "shadd_operand" ""))
6283 (match_operand:SI 1 "register_operand" "r")))]
6285 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6286 [(set_attr "type" "binary")
6287 (set_attr "length" "4")])
6290 [(set (match_operand:DI 0 "register_operand" "=r")
6291 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6292 (match_operand:DI 3 "shadd_operand" ""))
6293 (match_operand:DI 1 "register_operand" "r")))]
6295 "shladd,l %2,%O3,%1,%0"
6296 [(set_attr "type" "binary")
6297 (set_attr "length" "4")])
6299 (define_expand "ashlsi3"
6300 [(set (match_operand:SI 0 "register_operand" "")
6301 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6302 (match_operand:SI 2 "arith32_operand" "")))]
6306 if (GET_CODE (operands[2]) != CONST_INT)
6308 rtx temp = gen_reg_rtx (SImode);
6309 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6310 if (GET_CODE (operands[1]) == CONST_INT)
6311 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6313 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6316 /* Make sure both inputs are not constants,
6317 there are no patterns for that. */
6318 operands[1] = force_reg (SImode, operands[1]);
6322 [(set (match_operand:SI 0 "register_operand" "=r")
6323 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6324 (match_operand:SI 2 "const_int_operand" "n")))]
6326 "{zdep|depw,z} %1,%P2,%L2,%0"
6327 [(set_attr "type" "shift")
6328 (set_attr "length" "4")])
6330 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6331 ; Doing it like this makes slightly better code since reload can
6332 ; replace a register with a known value in range -16..15 with a
6333 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6334 ; but since we have no more CONST_OK... characters, that is not
6336 (define_insn "zvdep32"
6337 [(set (match_operand:SI 0 "register_operand" "=r,r")
6338 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6339 (minus:SI (const_int 31)
6340 (match_operand:SI 2 "register_operand" "q,q"))))]
6343 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6344 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6345 [(set_attr "type" "shift,shift")
6346 (set_attr "length" "4,4")])
6348 (define_insn "zvdep_imm32"
6349 [(set (match_operand:SI 0 "register_operand" "=r")
6350 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6351 (minus:SI (const_int 31)
6352 (match_operand:SI 2 "register_operand" "q"))))]
6356 int x = INTVAL (operands[1]);
6357 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6358 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6359 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6361 [(set_attr "type" "shift")
6362 (set_attr "length" "4")])
6364 (define_insn "vdepi_ior"
6365 [(set (match_operand:SI 0 "register_operand" "=r")
6366 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6367 (minus:SI (const_int 31)
6368 (match_operand:SI 2 "register_operand" "q")))
6369 (match_operand:SI 3 "register_operand" "0")))]
6370 ; accept ...0001...1, can this be generalized?
6371 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6374 int x = INTVAL (operands[1]);
6375 operands[2] = GEN_INT (exact_log2 (x + 1));
6376 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6378 [(set_attr "type" "shift")
6379 (set_attr "length" "4")])
6381 (define_insn "vdepi_and"
6382 [(set (match_operand:SI 0 "register_operand" "=r")
6383 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6384 (minus:SI (const_int 31)
6385 (match_operand:SI 2 "register_operand" "q")))
6386 (match_operand:SI 3 "register_operand" "0")))]
6387 ; this can be generalized...!
6388 "INTVAL (operands[1]) == -2"
6391 int x = INTVAL (operands[1]);
6392 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6393 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6395 [(set_attr "type" "shift")
6396 (set_attr "length" "4")])
6398 (define_expand "ashldi3"
6399 [(set (match_operand:DI 0 "register_operand" "")
6400 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6401 (match_operand:DI 2 "arith32_operand" "")))]
6405 if (GET_CODE (operands[2]) != CONST_INT)
6407 rtx temp = gen_reg_rtx (DImode);
6408 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6409 if (GET_CODE (operands[1]) == CONST_INT)
6410 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6412 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6415 /* Make sure both inputs are not constants,
6416 there are no patterns for that. */
6417 operands[1] = force_reg (DImode, operands[1]);
6421 [(set (match_operand:DI 0 "register_operand" "=r")
6422 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6423 (match_operand:DI 2 "const_int_operand" "n")))]
6425 "depd,z %1,%p2,%Q2,%0"
6426 [(set_attr "type" "shift")
6427 (set_attr "length" "4")])
6429 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6430 ; Doing it like this makes slightly better code since reload can
6431 ; replace a register with a known value in range -16..15 with a
6432 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6433 ; but since we have no more CONST_OK... characters, that is not
6435 (define_insn "zvdep64"
6436 [(set (match_operand:DI 0 "register_operand" "=r,r")
6437 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6438 (minus:DI (const_int 63)
6439 (match_operand:DI 2 "register_operand" "q,q"))))]
6442 depd,z %1,%%sar,64,%0
6443 depdi,z %1,%%sar,64,%0"
6444 [(set_attr "type" "shift,shift")
6445 (set_attr "length" "4,4")])
6447 (define_insn "zvdep_imm64"
6448 [(set (match_operand:DI 0 "register_operand" "=r")
6449 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6450 (minus:DI (const_int 63)
6451 (match_operand:DI 2 "register_operand" "q"))))]
6455 int x = INTVAL (operands[1]);
6456 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6457 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6458 return \"depdi,z %1,%%sar,%2,%0\";
6460 [(set_attr "type" "shift")
6461 (set_attr "length" "4")])
6464 [(set (match_operand:DI 0 "register_operand" "=r")
6465 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6466 (minus:DI (const_int 63)
6467 (match_operand:DI 2 "register_operand" "q")))
6468 (match_operand:DI 3 "register_operand" "0")))]
6469 ; accept ...0001...1, can this be generalized?
6470 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6473 int x = INTVAL (operands[1]);
6474 operands[2] = GEN_INT (exact_log2 (x + 1));
6475 return \"depdi -1,%%sar,%2,%0\";
6477 [(set_attr "type" "shift")
6478 (set_attr "length" "4")])
6481 [(set (match_operand:DI 0 "register_operand" "=r")
6482 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6483 (minus:DI (const_int 63)
6484 (match_operand:DI 2 "register_operand" "q")))
6485 (match_operand:DI 3 "register_operand" "0")))]
6486 ; this can be generalized...!
6487 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6490 int x = INTVAL (operands[1]);
6491 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6492 return \"depdi 0,%%sar,%2,%0\";
6494 [(set_attr "type" "shift")
6495 (set_attr "length" "4")])
6497 (define_expand "ashrsi3"
6498 [(set (match_operand:SI 0 "register_operand" "")
6499 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6500 (match_operand:SI 2 "arith32_operand" "")))]
6504 if (GET_CODE (operands[2]) != CONST_INT)
6506 rtx temp = gen_reg_rtx (SImode);
6507 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6508 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6514 [(set (match_operand:SI 0 "register_operand" "=r")
6515 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6516 (match_operand:SI 2 "const_int_operand" "n")))]
6518 "{extrs|extrw,s} %1,%P2,%L2,%0"
6519 [(set_attr "type" "shift")
6520 (set_attr "length" "4")])
6522 (define_insn "vextrs32"
6523 [(set (match_operand:SI 0 "register_operand" "=r")
6524 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6525 (minus:SI (const_int 31)
6526 (match_operand:SI 2 "register_operand" "q"))))]
6528 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6529 [(set_attr "type" "shift")
6530 (set_attr "length" "4")])
6532 (define_expand "ashrdi3"
6533 [(set (match_operand:DI 0 "register_operand" "")
6534 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6535 (match_operand:DI 2 "arith32_operand" "")))]
6539 if (GET_CODE (operands[2]) != CONST_INT)
6541 rtx temp = gen_reg_rtx (DImode);
6542 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6543 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6549 [(set (match_operand:DI 0 "register_operand" "=r")
6550 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6551 (match_operand:DI 2 "const_int_operand" "n")))]
6553 "extrd,s %1,%p2,%Q2,%0"
6554 [(set_attr "type" "shift")
6555 (set_attr "length" "4")])
6557 (define_insn "vextrs64"
6558 [(set (match_operand:DI 0 "register_operand" "=r")
6559 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6560 (minus:DI (const_int 63)
6561 (match_operand:DI 2 "register_operand" "q"))))]
6563 "extrd,s %1,%%sar,64,%0"
6564 [(set_attr "type" "shift")
6565 (set_attr "length" "4")])
6567 (define_insn "lshrsi3"
6568 [(set (match_operand:SI 0 "register_operand" "=r,r")
6569 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6570 (match_operand:SI 2 "arith32_operand" "q,n")))]
6573 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6574 {extru|extrw,u} %1,%P2,%L2,%0"
6575 [(set_attr "type" "shift")
6576 (set_attr "length" "4")])
6578 (define_insn "lshrdi3"
6579 [(set (match_operand:DI 0 "register_operand" "=r,r")
6580 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6581 (match_operand:DI 2 "arith32_operand" "q,n")))]
6584 shrpd %%r0,%1,%%sar,%0
6585 extrd,u %1,%p2,%Q2,%0"
6586 [(set_attr "type" "shift")
6587 (set_attr "length" "4")])
6589 (define_insn "rotrsi3"
6590 [(set (match_operand:SI 0 "register_operand" "=r,r")
6591 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6592 (match_operand:SI 2 "arith32_operand" "q,n")))]
6596 if (GET_CODE (operands[2]) == CONST_INT)
6598 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6599 return \"{shd|shrpw} %1,%1,%2,%0\";
6602 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6604 [(set_attr "type" "shift")
6605 (set_attr "length" "4")])
6607 (define_expand "rotlsi3"
6608 [(set (match_operand:SI 0 "register_operand" "")
6609 (rotate:SI (match_operand:SI 1 "register_operand" "")
6610 (match_operand:SI 2 "arith32_operand" "")))]
6614 if (GET_CODE (operands[2]) != CONST_INT)
6616 rtx temp = gen_reg_rtx (SImode);
6617 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6618 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6621 /* Else expand normally. */
6625 [(set (match_operand:SI 0 "register_operand" "=r")
6626 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6627 (match_operand:SI 2 "const_int_operand" "n")))]
6631 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6632 return \"{shd|shrpw} %1,%1,%2,%0\";
6634 [(set_attr "type" "shift")
6635 (set_attr "length" "4")])
6638 [(set (match_operand:SI 0 "register_operand" "=r")
6639 (match_operator:SI 5 "plus_xor_ior_operator"
6640 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6641 (match_operand:SI 3 "const_int_operand" "n"))
6642 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6643 (match_operand:SI 4 "const_int_operand" "n"))]))]
6644 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6645 "{shd|shrpw} %1,%2,%4,%0"
6646 [(set_attr "type" "shift")
6647 (set_attr "length" "4")])
6650 [(set (match_operand:SI 0 "register_operand" "=r")
6651 (match_operator:SI 5 "plus_xor_ior_operator"
6652 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6653 (match_operand:SI 4 "const_int_operand" "n"))
6654 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6655 (match_operand:SI 3 "const_int_operand" "n"))]))]
6656 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6657 "{shd|shrpw} %1,%2,%4,%0"
6658 [(set_attr "type" "shift")
6659 (set_attr "length" "4")])
6662 [(set (match_operand:SI 0 "register_operand" "=r")
6663 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6664 (match_operand:SI 2 "const_int_operand" ""))
6665 (match_operand:SI 3 "const_int_operand" "")))]
6666 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6669 int cnt = INTVAL (operands[2]) & 31;
6670 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6671 operands[2] = GEN_INT (31 - cnt);
6672 return \"{zdep|depw,z} %1,%2,%3,%0\";
6674 [(set_attr "type" "shift")
6675 (set_attr "length" "4")])
6677 ;; Unconditional and other jump instructions.
6679 ;; This is used for most returns.
6680 (define_insn "return_internal"
6687 return \"bve%* (%%r2)\";
6688 return \"bv%* %%r0(%%r2)\";
6690 [(set_attr "type" "branch")
6691 (set_attr "length" "4")])
6693 ;; This is used for eh returns which bypass the return stub.
6694 (define_insn "return_external_pic"
6696 (clobber (reg:SI 1))
6698 "!TARGET_NO_SPACE_REGS
6700 && flag_pic && crtl->calls_eh_return"
6701 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6702 [(set_attr "type" "branch")
6703 (set_attr "length" "12")])
6705 (define_expand "prologue"
6708 "hppa_expand_prologue ();DONE;")
6710 (define_expand "sibcall_epilogue"
6715 hppa_expand_epilogue ();
6719 (define_expand "epilogue"
6726 /* Try to use the trivial return first. Else use the full epilogue. */
6727 if (reload_completed
6728 && !frame_pointer_needed
6729 && !df_regs_ever_live_p (2)
6730 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1))
6731 x = gen_return_internal ();
6734 hppa_expand_epilogue ();
6736 /* EH returns bypass the normal return stub. Thus, we must do an
6737 interspace branch to return from functions that call eh_return.
6738 This is only a problem for returns from shared code on ports
6739 using space registers. */
6740 if (!TARGET_NO_SPACE_REGS
6742 && flag_pic && crtl->calls_eh_return)
6743 x = gen_return_external_pic ();
6745 x = gen_return_internal ();
6751 ; Used by hppa_profile_hook to load the starting address of the current
6752 ; function; operand 1 contains the address of the label in operand 3
6753 (define_insn "load_offset_label_address"
6754 [(set (match_operand:SI 0 "register_operand" "=r")
6755 (plus:SI (match_operand:SI 1 "register_operand" "r")
6756 (minus:SI (match_operand:SI 2 "" "")
6757 (label_ref:SI (match_operand 3 "" "")))))]
6760 [(set_attr "type" "multi")
6761 (set_attr "length" "4")])
6763 ; Output a code label and load its address.
6764 (define_insn "lcla1"
6765 [(set (match_operand:SI 0 "register_operand" "=r")
6766 (label_ref:SI (match_operand 1 "" "")))
6771 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6772 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6773 CODE_LABEL_NUMBER (operands[1]));
6776 [(set_attr "type" "multi")
6777 (set_attr "length" "8")])
6779 (define_insn "lcla2"
6780 [(set (match_operand:SI 0 "register_operand" "=r")
6781 (label_ref:SI (match_operand 1 "" "")))
6786 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6787 CODE_LABEL_NUMBER (operands[1]));
6790 [(set_attr "type" "move")
6791 (set_attr "length" "4")])
6793 (define_insn "blockage"
6794 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6797 [(set_attr "length" "0")])
6800 [(set (pc) (label_ref (match_operand 0 "" "")))]
6804 /* An unconditional branch which can reach its target. */
6805 if (get_attr_length (insn) < 16)
6808 return output_lbranch (operands[0], insn, 1);
6810 [(set_attr "type" "uncond_branch")
6811 (set_attr "pa_combine_type" "uncond_branch")
6812 (set (attr "length")
6813 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6814 (if_then_else (lt (abs (minus (match_dup 0)
6815 (plus (pc) (const_int 8))))
6816 (const_int MAX_12BIT_OFFSET))
6819 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6820 (const_int MAX_17BIT_OFFSET))
6822 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
6824 (eq (symbol_ref "flag_pic") (const_int 0))
6828 ;;; Hope this is only within a function...
6829 (define_insn "indirect_jump"
6830 [(set (pc) (match_operand 0 "register_operand" "r"))]
6831 "GET_MODE (operands[0]) == word_mode"
6833 [(set_attr "type" "branch")
6834 (set_attr "length" "4")])
6836 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6837 ;;; SOM target doesn't allow branching to a label inside a function.
6838 ;;; We also don't correctly compute branch distances for labels
6839 ;;; outside the current function. Thus, we use an indirect jump can't
6840 ;;; be optimized to a direct jump for all targets. We assume that
6841 ;;; the branch target is in the same space (i.e., nested function
6842 ;;; jumping to a label in an outer function in the same translation
6844 (define_expand "nonlocal_goto"
6845 [(use (match_operand 0 "general_operand" ""))
6846 (use (match_operand 1 "general_operand" ""))
6847 (use (match_operand 2 "general_operand" ""))
6848 (use (match_operand 3 "general_operand" ""))]
6851 rtx lab = operands[1];
6852 rtx stack = operands[2];
6853 rtx fp = operands[3];
6855 lab = copy_to_reg (lab);
6857 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6858 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6860 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6861 instead of the hard_frame_pointer_rtx in the save area. As a
6862 result, an extra instruction is needed to adjust for the offset
6863 of the virtual stack variables and the hard frame pointer. */
6864 if (GET_CODE (fp) != REG)
6865 fp = force_reg (Pmode, fp);
6866 emit_move_insn (hard_frame_pointer_rtx, plus_constant (fp, -8));
6868 emit_stack_restore (SAVE_NONLOCAL, stack);
6870 emit_use (hard_frame_pointer_rtx);
6871 emit_use (stack_pointer_rtx);
6873 /* Nonlocal goto jumps are only used between functions in the same
6874 translation unit. Thus, we can avoid the extra overhead of an
6876 emit_jump_insn (gen_indirect_goto (lab));
6881 (define_insn "indirect_goto"
6882 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6883 "GET_MODE (operands[0]) == word_mode"
6885 [(set_attr "type" "branch")
6886 (set_attr "length" "4")])
6888 ;;; This jump is used in branch tables where the insn length is fixed.
6889 ;;; The length of this insn is adjusted if the delay slot is not filled.
6890 (define_insn "short_jump"
6891 [(set (pc) (label_ref (match_operand 0 "" "")))
6895 [(set_attr "type" "btable_branch")
6896 (set_attr "length" "4")])
6898 ;; Subroutines of "casesi".
6899 ;; operand 0 is index
6900 ;; operand 1 is the minimum bound
6901 ;; operand 2 is the maximum bound - minimum bound + 1
6902 ;; operand 3 is CODE_LABEL for the table;
6903 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6905 (define_expand "casesi"
6906 [(match_operand:SI 0 "general_operand" "")
6907 (match_operand:SI 1 "const_int_operand" "")
6908 (match_operand:SI 2 "const_int_operand" "")
6909 (match_operand 3 "" "")
6910 (match_operand 4 "" "")]
6914 if (GET_CODE (operands[0]) != REG)
6915 operands[0] = force_reg (SImode, operands[0]);
6917 if (operands[1] != const0_rtx)
6919 rtx index = gen_reg_rtx (SImode);
6921 operands[1] = GEN_INT (-INTVAL (operands[1]));
6922 if (!INT_14_BITS (operands[1]))
6923 operands[1] = force_reg (SImode, operands[1]);
6924 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6925 operands[0] = index;
6928 if (!INT_5_BITS (operands[2]))
6929 operands[2] = force_reg (SImode, operands[2]);
6931 /* This branch prevents us finding an insn for the delay slot of the
6932 following vectored branch. It might be possible to use the delay
6933 slot if an index value of -1 was used to transfer to the out-of-range
6934 label. In order to do this, we would have to output the -1 vector
6935 element after the delay insn. The casesi output code would have to
6936 check if the casesi insn is in a delay branch sequence and output
6937 the delay insn if one is found. If this was done, then it might
6938 then be worthwhile to split the casesi patterns to improve scheduling.
6939 However, it's not clear that all this extra complexity is worth
6942 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
6943 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
6946 /* In 64bit mode we must make sure to wipe the upper bits of the register
6947 just in case the addition overflowed or we had random bits in the
6948 high part of the register. */
6951 rtx index = gen_reg_rtx (DImode);
6953 emit_insn (gen_extendsidi2 (index, operands[0]));
6954 operands[0] = index;
6957 if (TARGET_BIG_SWITCH)
6960 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
6962 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
6964 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
6967 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6971 ;;; The rtl for this pattern doesn't accurately describe what the insn
6972 ;;; actually does, particularly when case-vector elements are exploded
6973 ;;; in pa_reorg. However, the initial SET in these patterns must show
6974 ;;; the connection of the insn to the following jump table.
6975 (define_insn "casesi0"
6976 [(set (pc) (mem:SI (plus:SI
6977 (mult:SI (match_operand:SI 0 "register_operand" "r")
6979 (label_ref (match_operand 1 "" "")))))]
6981 "blr,n %0,%%r0\;nop"
6982 [(set_attr "type" "multi")
6983 (set_attr "length" "8")])
6985 ;;; 32-bit code, absolute branch table.
6986 (define_insn "casesi32"
6987 [(set (pc) (mem:SI (plus:SI
6988 (mult:SI (match_operand:SI 0 "register_operand" "r")
6990 (label_ref (match_operand 1 "" "")))))
6991 (clobber (match_scratch:SI 2 "=&r"))]
6993 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6994 [(set_attr "type" "multi")
6995 (set_attr "length" "16")])
6997 ;;; 32-bit code, relative branch table.
6998 (define_insn "casesi32p"
6999 [(set (pc) (mem:SI (plus:SI
7000 (mult:SI (match_operand:SI 0 "register_operand" "r")
7002 (label_ref (match_operand 1 "" "")))))
7003 (clobber (match_scratch:SI 2 "=&r"))
7004 (clobber (match_scratch:SI 3 "=&r"))]
7006 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7007 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7008 [(set_attr "type" "multi")
7009 (set (attr "length")
7010 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7014 ;;; 64-bit code, 32-bit relative branch table.
7015 (define_insn "casesi64p"
7016 [(set (pc) (mem:DI (plus:DI
7017 (mult:DI (match_operand:DI 0 "register_operand" "r")
7019 (label_ref (match_operand 1 "" "")))))
7020 (clobber (match_scratch:DI 2 "=&r"))
7021 (clobber (match_scratch:DI 3 "=&r"))]
7023 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7024 add,l %2,%3,%3\;bv,n %%r0(%3)"
7025 [(set_attr "type" "multi")
7026 (set_attr "length" "24")])
7030 ;;- jump to subroutine
7032 (define_expand "call"
7033 [(parallel [(call (match_operand:SI 0 "" "")
7034 (match_operand 1 "" ""))
7035 (clobber (reg:SI 2))])]
7040 rtx nb = operands[1];
7042 if (TARGET_PORTABLE_RUNTIME)
7043 op = force_reg (SImode, XEXP (operands[0], 0));
7045 op = XEXP (operands[0], 0);
7049 if (!virtuals_instantiated)
7050 emit_move_insn (arg_pointer_rtx,
7051 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7055 /* The loop pass can generate new libcalls after the virtual
7056 registers are instantiated when fpregs are disabled because
7057 the only method that we have for doing DImode multiplication
7058 is with a libcall. This could be trouble if we haven't
7059 allocated enough space for the outgoing arguments. */
7060 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7062 emit_move_insn (arg_pointer_rtx,
7063 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7064 GEN_INT (STACK_POINTER_OFFSET + 64)));
7068 /* Use two different patterns for calls to explicitly named functions
7069 and calls through function pointers. This is necessary as these two
7070 types of calls use different calling conventions, and CSE might try
7071 to change the named call into an indirect call in some cases (using
7072 two patterns keeps CSE from performing this optimization).
7074 We now use even more call patterns as there was a subtle bug in
7075 attempting to restore the pic register after a call using a simple
7076 move insn. During reload, a instruction involving a pseudo register
7077 with no explicit dependence on the PIC register can be converted
7078 to an equivalent load from memory using the PIC register. If we
7079 emit a simple move to restore the PIC register in the initial rtl
7080 generation, then it can potentially be repositioned during scheduling.
7081 and an instruction that eventually uses the PIC register may end up
7082 between the call and the PIC register restore.
7084 This only worked because there is a post call group of instructions
7085 that are scheduled with the call. These instructions are included
7086 in the same basic block as the call. However, calls can throw in
7087 C++ code and a basic block has to terminate at the call if the call
7088 can throw. This results in the PIC register restore being scheduled
7089 independently from the call. So, we now hide the save and restore
7090 of the PIC register in the call pattern until after reload. Then,
7091 we split the moves out. A small side benefit is that we now don't
7092 need to have a use of the PIC register in the return pattern and
7093 the final save/restore operation is not needed.
7095 I elected to just use register %r4 in the PIC patterns instead
7096 of trying to force hppa_pic_save_rtx () to a callee saved register.
7097 This might have required a new register class and constraint. It
7098 was also simpler to just handle the restore from a register than a
7102 rtx r4 = gen_rtx_REG (word_mode, 4);
7103 if (GET_CODE (op) == SYMBOL_REF)
7104 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7107 op = force_reg (word_mode, op);
7108 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7113 if (GET_CODE (op) == SYMBOL_REF)
7117 rtx r4 = gen_rtx_REG (word_mode, 4);
7118 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7121 emit_call_insn (gen_call_symref (op, nb));
7125 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7126 emit_move_insn (tmpreg, force_reg (word_mode, op));
7129 rtx r4 = gen_rtx_REG (word_mode, 4);
7130 emit_call_insn (gen_call_reg_pic (nb, r4));
7133 emit_call_insn (gen_call_reg (nb));
7140 ;; We use function calls to set the attribute length of calls and millicode
7141 ;; calls. This is necessary because of the large variety of call sequences.
7142 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7143 ;; we need the same calculation in several places, maintenance becomes a
7146 ;; However, this has a subtle impact on branch shortening. When the
7147 ;; expression used to set the length attribute of an instruction depends
7148 ;; on a relative address (e.g., pc or a branch address), genattrtab
7149 ;; notes that the insn's length is variable, and attempts to determine a
7150 ;; worst-case default length and code to compute an insn's current length.
7152 ;; The use of a function call hides the variable dependence of our calls
7153 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7154 ;; as variable and it only generates code for the default case using our
7155 ;; function call. Because of this, calls and millicode calls have a fixed
7156 ;; length in the branch shortening pass, and some branches will use a longer
7157 ;; code sequence than necessary. However, the length of any given call
7158 ;; will still reflect its final code location and it may be shorter than
7159 ;; the initial length estimate.
7161 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7162 ;; in the set. However, when genattrtab hits a function call in its attempt
7163 ;; to compute the default length, it marks the result as unknown and sets
7164 ;; the default result to MAX_INT ;-( One possible fix that would allow
7165 ;; calls to participate in branch shortening would be to make the call to
7166 ;; insn_default_length a target option. Then, we could massage unknown
7167 ;; results. Another fix might be to change genattrtab so that it just does
7168 ;; the call in the variable case as it already does for the fixed case.
7170 (define_insn "call_symref"
7171 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7172 (match_operand 1 "" "i"))
7173 (clobber (reg:SI 1))
7174 (clobber (reg:SI 2))
7175 (use (const_int 0))]
7176 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7179 output_arg_descriptor (insn);
7180 return output_call (insn, operands[0], 0);
7182 [(set_attr "type" "call")
7183 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7185 (define_insn "call_symref_pic"
7186 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7187 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7188 (match_operand 1 "" "i"))
7189 (clobber (reg:SI 1))
7190 (clobber (reg:SI 2))
7193 (use (const_int 0))]
7194 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7197 ;; Split out the PIC register save and restore after reload. As the
7198 ;; split is done after reload, there are some situations in which we
7199 ;; unnecessarily save and restore %r4. This happens when there is a
7200 ;; single call and the PIC register is not used after the call.
7202 ;; The split has to be done since call_from_call_insn () can't handle
7203 ;; the pattern as is. Noreturn calls are special because they have to
7204 ;; terminate the basic block. The split has to contain more than one
7207 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7208 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7209 (match_operand 1 "" ""))
7210 (clobber (reg:SI 1))
7211 (clobber (reg:SI 2))
7214 (use (const_int 0))])]
7215 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7216 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7217 [(set (match_dup 2) (reg:SI 19))
7218 (parallel [(call (mem:SI (match_dup 0))
7220 (clobber (reg:SI 1))
7221 (clobber (reg:SI 2))
7223 (use (const_int 0))])]
7227 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7228 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7229 (match_operand 1 "" ""))
7230 (clobber (reg:SI 1))
7231 (clobber (reg:SI 2))
7234 (use (const_int 0))])]
7235 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7236 [(set (match_dup 2) (reg:SI 19))
7237 (parallel [(call (mem:SI (match_dup 0))
7239 (clobber (reg:SI 1))
7240 (clobber (reg:SI 2))
7242 (use (const_int 0))])
7243 (set (reg:SI 19) (match_dup 2))]
7246 (define_insn "*call_symref_pic_post_reload"
7247 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7248 (match_operand 1 "" "i"))
7249 (clobber (reg:SI 1))
7250 (clobber (reg:SI 2))
7252 (use (const_int 0))]
7253 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7256 output_arg_descriptor (insn);
7257 return output_call (insn, operands[0], 0);
7259 [(set_attr "type" "call")
7260 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7262 ;; This pattern is split if it is necessary to save and restore the
7264 (define_insn "call_symref_64bit"
7265 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7266 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7267 (match_operand 1 "" "i"))
7268 (clobber (reg:DI 1))
7269 (clobber (reg:DI 2))
7273 (use (const_int 0))]
7277 ;; Split out the PIC register save and restore after reload. As the
7278 ;; split is done after reload, there are some situations in which we
7279 ;; unnecessarily save and restore %r4. This happens when there is a
7280 ;; single call and the PIC register is not used after the call.
7282 ;; The split has to be done since call_from_call_insn () can't handle
7283 ;; the pattern as is. Noreturn calls are special because they have to
7284 ;; terminate the basic block. The split has to contain more than one
7287 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7288 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7289 (match_operand 1 "" ""))
7290 (clobber (reg:DI 1))
7291 (clobber (reg:DI 2))
7295 (use (const_int 0))])]
7296 "TARGET_64BIT && reload_completed
7297 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7298 [(set (match_dup 2) (reg:DI 27))
7299 (parallel [(call (mem:SI (match_dup 0))
7301 (clobber (reg:DI 1))
7302 (clobber (reg:DI 2))
7305 (use (const_int 0))])]
7309 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7310 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7311 (match_operand 1 "" ""))
7312 (clobber (reg:DI 1))
7313 (clobber (reg:DI 2))
7317 (use (const_int 0))])]
7318 "TARGET_64BIT && reload_completed"
7319 [(set (match_dup 2) (reg:DI 27))
7320 (parallel [(call (mem:SI (match_dup 0))
7322 (clobber (reg:DI 1))
7323 (clobber (reg:DI 2))
7326 (use (const_int 0))])
7327 (set (reg:DI 27) (match_dup 2))]
7330 (define_insn "*call_symref_64bit_post_reload"
7331 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7332 (match_operand 1 "" "i"))
7333 (clobber (reg:DI 1))
7334 (clobber (reg:DI 2))
7337 (use (const_int 0))]
7341 output_arg_descriptor (insn);
7342 return output_call (insn, operands[0], 0);
7344 [(set_attr "type" "call")
7345 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7347 (define_insn "call_reg"
7348 [(call (mem:SI (reg:SI 22))
7349 (match_operand 0 "" "i"))
7350 (clobber (reg:SI 1))
7351 (clobber (reg:SI 2))
7352 (use (const_int 1))]
7356 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7358 [(set_attr "type" "dyncall")
7359 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7361 ;; This pattern is split if it is necessary to save and restore the
7363 (define_insn "call_reg_pic"
7364 [(set (match_operand:SI 1 "register_operand" "=&r") (reg:SI 19))
7365 (call (mem:SI (reg:SI 22))
7366 (match_operand 0 "" "i"))
7367 (clobber (reg:SI 1))
7368 (clobber (reg:SI 2))
7371 (use (const_int 1))]
7375 ;; Split out the PIC register save and restore after reload. As the
7376 ;; split is done after reload, there are some situations in which we
7377 ;; unnecessarily save and restore %r4. This happens when there is a
7378 ;; single call and the PIC register is not used after the call.
7380 ;; The split has to be done since call_from_call_insn () can't handle
7381 ;; the pattern as is. Noreturn calls are special because they have to
7382 ;; terminate the basic block. The split has to contain more than one
7385 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7386 (call (mem:SI (reg:SI 22))
7387 (match_operand 0 "" ""))
7388 (clobber (reg:SI 1))
7389 (clobber (reg:SI 2))
7392 (use (const_int 1))])]
7393 "!TARGET_64BIT && reload_completed
7394 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7395 [(set (match_dup 1) (reg:SI 19))
7396 (parallel [(call (mem:SI (reg:SI 22))
7398 (clobber (reg:SI 1))
7399 (clobber (reg:SI 2))
7401 (use (const_int 1))])]
7405 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7406 (call (mem:SI (reg:SI 22))
7407 (match_operand 0 "" ""))
7408 (clobber (reg:SI 1))
7409 (clobber (reg:SI 2))
7412 (use (const_int 1))])]
7413 "!TARGET_64BIT && reload_completed"
7414 [(set (match_dup 1) (reg:SI 19))
7415 (parallel [(call (mem:SI (reg:SI 22))
7417 (clobber (reg:SI 1))
7418 (clobber (reg:SI 2))
7420 (use (const_int 1))])
7421 (set (reg:SI 19) (match_dup 1))]
7424 (define_insn "*call_reg_pic_post_reload"
7425 [(call (mem:SI (reg:SI 22))
7426 (match_operand 0 "" "i"))
7427 (clobber (reg:SI 1))
7428 (clobber (reg:SI 2))
7430 (use (const_int 1))]
7434 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7436 [(set_attr "type" "dyncall")
7437 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7439 ;; This pattern is split if it is necessary to save and restore the
7441 (define_insn "call_reg_64bit"
7442 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7443 (call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7444 (match_operand 1 "" "i"))
7445 (clobber (reg:DI 1))
7446 (clobber (reg:DI 2))
7450 (use (const_int 1))]
7454 ;; Split out the PIC register save and restore after reload. As the
7455 ;; split is done after reload, there are some situations in which we
7456 ;; unnecessarily save and restore %r4. This happens when there is a
7457 ;; single call and the PIC register is not used after the call.
7459 ;; The split has to be done since call_from_call_insn () can't handle
7460 ;; the pattern as is. Noreturn calls are special because they have to
7461 ;; terminate the basic block. The split has to contain more than one
7464 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7465 (call (mem:SI (match_operand 0 "register_operand" ""))
7466 (match_operand 1 "" ""))
7467 (clobber (reg:DI 1))
7468 (clobber (reg:DI 2))
7472 (use (const_int 1))])]
7473 "TARGET_64BIT && reload_completed
7474 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7475 [(set (match_dup 2) (reg:DI 27))
7476 (parallel [(call (mem:SI (match_dup 0))
7478 (clobber (reg:DI 1))
7479 (clobber (reg:DI 2))
7482 (use (const_int 1))])]
7486 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7487 (call (mem:SI (match_operand 0 "register_operand" ""))
7488 (match_operand 1 "" ""))
7489 (clobber (reg:DI 1))
7490 (clobber (reg:DI 2))
7494 (use (const_int 1))])]
7495 "TARGET_64BIT && reload_completed"
7496 [(set (match_dup 2) (reg:DI 27))
7497 (parallel [(call (mem:SI (match_dup 0))
7499 (clobber (reg:DI 1))
7500 (clobber (reg:DI 2))
7503 (use (const_int 1))])
7504 (set (reg:DI 27) (match_dup 2))]
7507 (define_insn "*call_reg_64bit_post_reload"
7508 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7509 (match_operand 1 "" "i"))
7510 (clobber (reg:DI 1))
7511 (clobber (reg:DI 2))
7514 (use (const_int 1))]
7518 return output_indirect_call (insn, operands[0]);
7520 [(set_attr "type" "dyncall")
7521 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7523 (define_expand "call_value"
7524 [(parallel [(set (match_operand 0 "" "")
7525 (call (match_operand:SI 1 "" "")
7526 (match_operand 2 "" "")))
7527 (clobber (reg:SI 2))])]
7532 rtx dst = operands[0];
7533 rtx nb = operands[2];
7535 if (TARGET_PORTABLE_RUNTIME)
7536 op = force_reg (SImode, XEXP (operands[1], 0));
7538 op = XEXP (operands[1], 0);
7542 if (!virtuals_instantiated)
7543 emit_move_insn (arg_pointer_rtx,
7544 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7548 /* The loop pass can generate new libcalls after the virtual
7549 registers are instantiated when fpregs are disabled because
7550 the only method that we have for doing DImode multiplication
7551 is with a libcall. This could be trouble if we haven't
7552 allocated enough space for the outgoing arguments. */
7553 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7555 emit_move_insn (arg_pointer_rtx,
7556 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7557 GEN_INT (STACK_POINTER_OFFSET + 64)));
7561 /* Use two different patterns for calls to explicitly named functions
7562 and calls through function pointers. This is necessary as these two
7563 types of calls use different calling conventions, and CSE might try
7564 to change the named call into an indirect call in some cases (using
7565 two patterns keeps CSE from performing this optimization).
7567 We now use even more call patterns as there was a subtle bug in
7568 attempting to restore the pic register after a call using a simple
7569 move insn. During reload, a instruction involving a pseudo register
7570 with no explicit dependence on the PIC register can be converted
7571 to an equivalent load from memory using the PIC register. If we
7572 emit a simple move to restore the PIC register in the initial rtl
7573 generation, then it can potentially be repositioned during scheduling.
7574 and an instruction that eventually uses the PIC register may end up
7575 between the call and the PIC register restore.
7577 This only worked because there is a post call group of instructions
7578 that are scheduled with the call. These instructions are included
7579 in the same basic block as the call. However, calls can throw in
7580 C++ code and a basic block has to terminate at the call if the call
7581 can throw. This results in the PIC register restore being scheduled
7582 independently from the call. So, we now hide the save and restore
7583 of the PIC register in the call pattern until after reload. Then,
7584 we split the moves out. A small side benefit is that we now don't
7585 need to have a use of the PIC register in the return pattern and
7586 the final save/restore operation is not needed.
7588 I elected to just use register %r4 in the PIC patterns instead
7589 of trying to force hppa_pic_save_rtx () to a callee saved register.
7590 This might have required a new register class and constraint. It
7591 was also simpler to just handle the restore from a register than a
7595 rtx r4 = gen_rtx_REG (word_mode, 4);
7596 if (GET_CODE (op) == SYMBOL_REF)
7597 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7600 op = force_reg (word_mode, op);
7601 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7606 if (GET_CODE (op) == SYMBOL_REF)
7610 rtx r4 = gen_rtx_REG (word_mode, 4);
7611 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7614 emit_call_insn (gen_call_val_symref (dst, op, nb));
7618 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7619 emit_move_insn (tmpreg, force_reg (word_mode, op));
7622 rtx r4 = gen_rtx_REG (word_mode, 4);
7623 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7626 emit_call_insn (gen_call_val_reg (dst, nb));
7633 (define_insn "call_val_symref"
7634 [(set (match_operand 0 "" "")
7635 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7636 (match_operand 2 "" "i")))
7637 (clobber (reg:SI 1))
7638 (clobber (reg:SI 2))
7639 (use (const_int 0))]
7640 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7643 output_arg_descriptor (insn);
7644 return output_call (insn, operands[1], 0);
7646 [(set_attr "type" "call")
7647 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7649 (define_insn "call_val_symref_pic"
7650 [(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
7651 (set (match_operand 0 "" "")
7652 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7653 (match_operand 2 "" "i")))
7654 (clobber (reg:SI 1))
7655 (clobber (reg:SI 2))
7658 (use (const_int 0))]
7659 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7662 ;; Split out the PIC register save and restore after reload. As the
7663 ;; split is done after reload, there are some situations in which we
7664 ;; unnecessarily save and restore %r4. This happens when there is a
7665 ;; single call and the PIC register is not used after the call.
7667 ;; The split has to be done since call_from_call_insn () can't handle
7668 ;; the pattern as is. Noreturn calls are special because they have to
7669 ;; terminate the basic block. The split has to contain more than one
7672 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7673 (set (match_operand 0 "" "")
7674 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7675 (match_operand 2 "" "")))
7676 (clobber (reg:SI 1))
7677 (clobber (reg:SI 2))
7680 (use (const_int 0))])]
7681 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7682 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7683 [(set (match_dup 3) (reg:SI 19))
7684 (parallel [(set (match_dup 0)
7685 (call (mem:SI (match_dup 1))
7687 (clobber (reg:SI 1))
7688 (clobber (reg:SI 2))
7690 (use (const_int 0))])]
7694 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7695 (set (match_operand 0 "" "")
7696 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7697 (match_operand 2 "" "")))
7698 (clobber (reg:SI 1))
7699 (clobber (reg:SI 2))
7702 (use (const_int 0))])]
7703 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7704 [(set (match_dup 3) (reg:SI 19))
7705 (parallel [(set (match_dup 0)
7706 (call (mem:SI (match_dup 1))
7708 (clobber (reg:SI 1))
7709 (clobber (reg:SI 2))
7711 (use (const_int 0))])
7712 (set (reg:SI 19) (match_dup 3))]
7715 (define_insn "*call_val_symref_pic_post_reload"
7716 [(set (match_operand 0 "" "")
7717 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7718 (match_operand 2 "" "i")))
7719 (clobber (reg:SI 1))
7720 (clobber (reg:SI 2))
7722 (use (const_int 0))]
7723 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7726 output_arg_descriptor (insn);
7727 return output_call (insn, operands[1], 0);
7729 [(set_attr "type" "call")
7730 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7732 ;; This pattern is split if it is necessary to save and restore the
7734 (define_insn "call_val_symref_64bit"
7735 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7736 (set (match_operand 0 "" "")
7737 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7738 (match_operand 2 "" "i")))
7739 (clobber (reg:DI 1))
7740 (clobber (reg:DI 2))
7744 (use (const_int 0))]
7748 ;; Split out the PIC register save and restore after reload. As the
7749 ;; split is done after reload, there are some situations in which we
7750 ;; unnecessarily save and restore %r4. This happens when there is a
7751 ;; single call and the PIC register is not used after the call.
7753 ;; The split has to be done since call_from_call_insn () can't handle
7754 ;; the pattern as is. Noreturn calls are special because they have to
7755 ;; terminate the basic block. The split has to contain more than one
7758 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7759 (set (match_operand 0 "" "")
7760 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7761 (match_operand 2 "" "")))
7762 (clobber (reg:DI 1))
7763 (clobber (reg:DI 2))
7767 (use (const_int 0))])]
7768 "TARGET_64BIT && reload_completed
7769 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7770 [(set (match_dup 3) (reg:DI 27))
7771 (parallel [(set (match_dup 0)
7772 (call (mem:SI (match_dup 1))
7774 (clobber (reg:DI 1))
7775 (clobber (reg:DI 2))
7778 (use (const_int 0))])]
7782 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7783 (set (match_operand 0 "" "")
7784 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7785 (match_operand 2 "" "")))
7786 (clobber (reg:DI 1))
7787 (clobber (reg:DI 2))
7791 (use (const_int 0))])]
7792 "TARGET_64BIT && reload_completed"
7793 [(set (match_dup 3) (reg:DI 27))
7794 (parallel [(set (match_dup 0)
7795 (call (mem:SI (match_dup 1))
7797 (clobber (reg:DI 1))
7798 (clobber (reg:DI 2))
7801 (use (const_int 0))])
7802 (set (reg:DI 27) (match_dup 3))]
7805 (define_insn "*call_val_symref_64bit_post_reload"
7806 [(set (match_operand 0 "" "")
7807 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7808 (match_operand 2 "" "i")))
7809 (clobber (reg:DI 1))
7810 (clobber (reg:DI 2))
7813 (use (const_int 0))]
7817 output_arg_descriptor (insn);
7818 return output_call (insn, operands[1], 0);
7820 [(set_attr "type" "call")
7821 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7823 (define_insn "call_val_reg"
7824 [(set (match_operand 0 "" "")
7825 (call (mem:SI (reg:SI 22))
7826 (match_operand 1 "" "i")))
7827 (clobber (reg:SI 1))
7828 (clobber (reg:SI 2))
7829 (use (const_int 1))]
7833 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7835 [(set_attr "type" "dyncall")
7836 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7838 ;; This pattern is split if it is necessary to save and restore the
7840 (define_insn "call_val_reg_pic"
7841 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7842 (set (match_operand 0 "" "")
7843 (call (mem:SI (reg:SI 22))
7844 (match_operand 1 "" "i")))
7845 (clobber (reg:SI 1))
7846 (clobber (reg:SI 2))
7849 (use (const_int 1))]
7853 ;; Split out the PIC register save and restore after reload. As the
7854 ;; split is done after reload, there are some situations in which we
7855 ;; unnecessarily save and restore %r4. This happens when there is a
7856 ;; single call and the PIC register is not used after the call.
7858 ;; The split has to be done since call_from_call_insn () can't handle
7859 ;; the pattern as is. Noreturn calls are special because they have to
7860 ;; terminate the basic block. The split has to contain more than one
7863 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7864 (set (match_operand 0 "" "")
7865 (call (mem:SI (reg:SI 22))
7866 (match_operand 1 "" "")))
7867 (clobber (reg:SI 1))
7868 (clobber (reg:SI 2))
7871 (use (const_int 1))])]
7872 "!TARGET_64BIT && reload_completed
7873 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7874 [(set (match_dup 2) (reg:SI 19))
7875 (parallel [(set (match_dup 0)
7876 (call (mem:SI (reg:SI 22))
7878 (clobber (reg:SI 1))
7879 (clobber (reg:SI 2))
7881 (use (const_int 1))])]
7885 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7886 (set (match_operand 0 "" "")
7887 (call (mem:SI (reg:SI 22))
7888 (match_operand 1 "" "")))
7889 (clobber (reg:SI 1))
7890 (clobber (reg:SI 2))
7893 (use (const_int 1))])]
7894 "!TARGET_64BIT && reload_completed"
7895 [(set (match_dup 2) (reg:SI 19))
7896 (parallel [(set (match_dup 0)
7897 (call (mem:SI (reg:SI 22))
7899 (clobber (reg:SI 1))
7900 (clobber (reg:SI 2))
7902 (use (const_int 1))])
7903 (set (reg:SI 19) (match_dup 2))]
7906 (define_insn "*call_val_reg_pic_post_reload"
7907 [(set (match_operand 0 "" "")
7908 (call (mem:SI (reg:SI 22))
7909 (match_operand 1 "" "i")))
7910 (clobber (reg:SI 1))
7911 (clobber (reg:SI 2))
7913 (use (const_int 1))]
7917 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7919 [(set_attr "type" "dyncall")
7920 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7922 ;; This pattern is split if it is necessary to save and restore the
7924 (define_insn "call_val_reg_64bit"
7925 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7926 (set (match_operand 0 "" "")
7927 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7928 (match_operand 2 "" "i")))
7929 (clobber (reg:DI 1))
7930 (clobber (reg:DI 2))
7934 (use (const_int 1))]
7938 ;; Split out the PIC register save and restore after reload. As the
7939 ;; split is done after reload, there are some situations in which we
7940 ;; unnecessarily save and restore %r4. This happens when there is a
7941 ;; single call and the PIC register is not used after the call.
7943 ;; The split has to be done since call_from_call_insn () can't handle
7944 ;; the pattern as is. Noreturn calls are special because they have to
7945 ;; terminate the basic block. The split has to contain more than one
7948 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7949 (set (match_operand 0 "" "")
7950 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7951 (match_operand 2 "" "")))
7952 (clobber (reg:DI 1))
7953 (clobber (reg:DI 2))
7957 (use (const_int 1))])]
7958 "TARGET_64BIT && reload_completed
7959 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7960 [(set (match_dup 3) (reg:DI 27))
7961 (parallel [(set (match_dup 0)
7962 (call (mem:SI (match_dup 1))
7964 (clobber (reg:DI 1))
7965 (clobber (reg:DI 2))
7968 (use (const_int 1))])]
7972 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7973 (set (match_operand 0 "" "")
7974 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7975 (match_operand 2 "" "")))
7976 (clobber (reg:DI 1))
7977 (clobber (reg:DI 2))
7981 (use (const_int 1))])]
7982 "TARGET_64BIT && reload_completed"
7983 [(set (match_dup 3) (reg:DI 27))
7984 (parallel [(set (match_dup 0)
7985 (call (mem:SI (match_dup 1))
7987 (clobber (reg:DI 1))
7988 (clobber (reg:DI 2))
7991 (use (const_int 1))])
7992 (set (reg:DI 27) (match_dup 3))]
7995 (define_insn "*call_val_reg_64bit_post_reload"
7996 [(set (match_operand 0 "" "")
7997 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7998 (match_operand 2 "" "i")))
7999 (clobber (reg:DI 1))
8000 (clobber (reg:DI 2))
8003 (use (const_int 1))]
8007 return output_indirect_call (insn, operands[1]);
8009 [(set_attr "type" "dyncall")
8010 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8012 ;; Call subroutine returning any type.
8014 (define_expand "untyped_call"
8015 [(parallel [(call (match_operand 0 "" "")
8017 (match_operand 1 "" "")
8018 (match_operand 2 "" "")])]
8024 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8026 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8028 rtx set = XVECEXP (operands[2], 0, i);
8029 emit_move_insn (SET_DEST (set), SET_SRC (set));
8032 /* The optimizer does not know that the call sets the function value
8033 registers we stored in the result block. We avoid problems by
8034 claiming that all hard registers are used and clobbered at this
8036 emit_insn (gen_blockage ());
8041 (define_expand "sibcall"
8042 [(call (match_operand:SI 0 "" "")
8043 (match_operand 1 "" ""))]
8044 "!TARGET_PORTABLE_RUNTIME"
8048 rtx nb = operands[1];
8050 op = XEXP (operands[0], 0);
8054 if (!virtuals_instantiated)
8055 emit_move_insn (arg_pointer_rtx,
8056 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8060 /* The loop pass can generate new libcalls after the virtual
8061 registers are instantiated when fpregs are disabled because
8062 the only method that we have for doing DImode multiplication
8063 is with a libcall. This could be trouble if we haven't
8064 allocated enough space for the outgoing arguments. */
8065 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8067 emit_move_insn (arg_pointer_rtx,
8068 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8069 GEN_INT (STACK_POINTER_OFFSET + 64)));
8073 /* Indirect sibling calls are not allowed. */
8075 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8077 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8079 call_insn = emit_call_insn (call_insn);
8082 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8084 /* We don't have to restore the PIC register. */
8086 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8091 (define_insn "sibcall_internal_symref"
8092 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8093 (match_operand 1 "" "i"))
8094 (clobber (reg:SI 1))
8096 (use (const_int 0))]
8097 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8100 output_arg_descriptor (insn);
8101 return output_call (insn, operands[0], 1);
8103 [(set_attr "type" "call")
8104 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8106 (define_insn "sibcall_internal_symref_64bit"
8107 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8108 (match_operand 1 "" "i"))
8109 (clobber (reg:DI 1))
8111 (use (const_int 0))]
8115 output_arg_descriptor (insn);
8116 return output_call (insn, operands[0], 1);
8118 [(set_attr "type" "call")
8119 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8121 (define_expand "sibcall_value"
8122 [(set (match_operand 0 "" "")
8123 (call (match_operand:SI 1 "" "")
8124 (match_operand 2 "" "")))]
8125 "!TARGET_PORTABLE_RUNTIME"
8129 rtx nb = operands[1];
8131 op = XEXP (operands[1], 0);
8135 if (!virtuals_instantiated)
8136 emit_move_insn (arg_pointer_rtx,
8137 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8141 /* The loop pass can generate new libcalls after the virtual
8142 registers are instantiated when fpregs are disabled because
8143 the only method that we have for doing DImode multiplication
8144 is with a libcall. This could be trouble if we haven't
8145 allocated enough space for the outgoing arguments. */
8146 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8148 emit_move_insn (arg_pointer_rtx,
8149 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8150 GEN_INT (STACK_POINTER_OFFSET + 64)));
8154 /* Indirect sibling calls are not allowed. */
8157 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8160 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8162 call_insn = emit_call_insn (call_insn);
8165 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8167 /* We don't have to restore the PIC register. */
8169 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8174 (define_insn "sibcall_value_internal_symref"
8175 [(set (match_operand 0 "" "")
8176 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8177 (match_operand 2 "" "i")))
8178 (clobber (reg:SI 1))
8180 (use (const_int 0))]
8181 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8184 output_arg_descriptor (insn);
8185 return output_call (insn, operands[1], 1);
8187 [(set_attr "type" "call")
8188 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8190 (define_insn "sibcall_value_internal_symref_64bit"
8191 [(set (match_operand 0 "" "")
8192 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8193 (match_operand 2 "" "i")))
8194 (clobber (reg:DI 1))
8196 (use (const_int 0))]
8200 output_arg_descriptor (insn);
8201 return output_call (insn, operands[1], 1);
8203 [(set_attr "type" "call")
8204 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8210 [(set_attr "type" "move")
8211 (set_attr "length" "4")])
8213 ;; These are just placeholders so we know where branch tables
8215 (define_insn "begin_brtab"
8220 /* Only GAS actually supports this pseudo-op. */
8222 return \".begin_brtab\";
8226 [(set_attr "type" "move")
8227 (set_attr "length" "0")])
8229 (define_insn "end_brtab"
8234 /* Only GAS actually supports this pseudo-op. */
8236 return \".end_brtab\";
8240 [(set_attr "type" "move")
8241 (set_attr "length" "0")])
8243 ;;; EH does longjmp's from and within the data section. Thus,
8244 ;;; an interspace branch is required for the longjmp implementation.
8245 ;;; Registers r1 and r2 are used as scratch registers for the jump
8247 (define_expand "interspace_jump"
8249 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8250 (clobber (match_dup 1))])]
8254 operands[1] = gen_rtx_REG (word_mode, 2);
8258 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8259 (clobber (reg:SI 2))]
8260 "TARGET_PA_20 && !TARGET_64BIT"
8262 [(set_attr "type" "branch")
8263 (set_attr "length" "4")])
8266 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8267 (clobber (reg:SI 2))]
8268 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8270 [(set_attr "type" "branch")
8271 (set_attr "length" "4")])
8274 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8275 (clobber (reg:SI 2))]
8277 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8278 [(set_attr "type" "branch")
8279 (set_attr "length" "12")])
8282 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8283 (clobber (reg:DI 2))]
8286 [(set_attr "type" "branch")
8287 (set_attr "length" "4")])
8289 (define_expand "builtin_longjmp"
8290 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8294 /* The elements of the buffer are, in order: */
8295 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8296 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8297 POINTER_SIZE / BITS_PER_UNIT));
8298 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8299 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8300 rtx pv = gen_rtx_REG (Pmode, 1);
8302 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8303 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8305 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8306 instead of the hard_frame_pointer_rtx in the save area. We need
8307 to adjust for the offset between these two values. */
8308 if (GET_CODE (fp) != REG)
8309 fp = force_reg (Pmode, fp);
8310 emit_move_insn (hard_frame_pointer_rtx, plus_constant (fp, -8));
8312 /* This bit is the same as expand_builtin_longjmp. */
8313 emit_stack_restore (SAVE_NONLOCAL, stack);
8314 emit_use (hard_frame_pointer_rtx);
8315 emit_use (stack_pointer_rtx);
8317 /* Load the label we are jumping through into r1 so that we know
8318 where to look for it when we get back to setjmp's function for
8319 restoring the gp. */
8320 emit_move_insn (pv, lab);
8322 /* Prevent the insns above from being scheduled into the delay slot
8323 of the interspace jump because the space register could change. */
8324 emit_insn (gen_blockage ());
8326 emit_jump_insn (gen_interspace_jump (pv));
8331 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8332 (define_expand "extzv"
8333 [(set (match_operand 0 "register_operand" "")
8334 (zero_extract (match_operand 1 "register_operand" "")
8335 (match_operand 2 "uint32_operand" "")
8336 (match_operand 3 "uint32_operand" "")))]
8340 HOST_WIDE_INT len = INTVAL (operands[2]);
8341 HOST_WIDE_INT pos = INTVAL (operands[3]);
8343 /* PA extraction insns don't support zero length bitfields or fields
8344 extending beyond the left or right-most bits. Also, we reject lengths
8345 equal to a word as they are better handled by the move patterns. */
8346 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8349 /* From mips.md: extract_bit_field doesn't verify that our source
8350 matches the predicate, so check it again here. */
8351 if (!register_operand (operands[1], VOIDmode))
8355 emit_insn (gen_extzv_64 (operands[0], operands[1],
8356 operands[2], operands[3]));
8358 emit_insn (gen_extzv_32 (operands[0], operands[1],
8359 operands[2], operands[3]));
8363 (define_insn "extzv_32"
8364 [(set (match_operand:SI 0 "register_operand" "=r")
8365 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8366 (match_operand:SI 2 "uint5_operand" "")
8367 (match_operand:SI 3 "uint5_operand" "")))]
8369 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8370 [(set_attr "type" "shift")
8371 (set_attr "length" "4")])
8374 [(set (match_operand:SI 0 "register_operand" "=r")
8375 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8377 (match_operand:SI 2 "register_operand" "q")))]
8379 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8380 [(set_attr "type" "shift")
8381 (set_attr "length" "4")])
8383 (define_insn "extzv_64"
8384 [(set (match_operand:DI 0 "register_operand" "=r")
8385 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8386 (match_operand:DI 2 "uint32_operand" "")
8387 (match_operand:DI 3 "uint32_operand" "")))]
8389 "extrd,u %1,%3+%2-1,%2,%0"
8390 [(set_attr "type" "shift")
8391 (set_attr "length" "4")])
8394 [(set (match_operand:DI 0 "register_operand" "=r")
8395 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8397 (match_operand:DI 2 "register_operand" "q")))]
8399 "extrd,u %1,%%sar,1,%0"
8400 [(set_attr "type" "shift")
8401 (set_attr "length" "4")])
8403 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8404 (define_expand "extv"
8405 [(set (match_operand 0 "register_operand" "")
8406 (sign_extract (match_operand 1 "register_operand" "")
8407 (match_operand 2 "uint32_operand" "")
8408 (match_operand 3 "uint32_operand" "")))]
8412 HOST_WIDE_INT len = INTVAL (operands[2]);
8413 HOST_WIDE_INT pos = INTVAL (operands[3]);
8415 /* PA extraction insns don't support zero length bitfields or fields
8416 extending beyond the left or right-most bits. Also, we reject lengths
8417 equal to a word as they are better handled by the move patterns. */
8418 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8421 /* From mips.md: extract_bit_field doesn't verify that our source
8422 matches the predicate, so check it again here. */
8423 if (!register_operand (operands[1], VOIDmode))
8427 emit_insn (gen_extv_64 (operands[0], operands[1],
8428 operands[2], operands[3]));
8430 emit_insn (gen_extv_32 (operands[0], operands[1],
8431 operands[2], operands[3]));
8435 (define_insn "extv_32"
8436 [(set (match_operand:SI 0 "register_operand" "=r")
8437 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8438 (match_operand:SI 2 "uint5_operand" "")
8439 (match_operand:SI 3 "uint5_operand" "")))]
8441 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8442 [(set_attr "type" "shift")
8443 (set_attr "length" "4")])
8446 [(set (match_operand:SI 0 "register_operand" "=r")
8447 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8449 (match_operand:SI 2 "register_operand" "q")))]
8451 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8452 [(set_attr "type" "shift")
8453 (set_attr "length" "4")])
8455 (define_insn "extv_64"
8456 [(set (match_operand:DI 0 "register_operand" "=r")
8457 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8458 (match_operand:DI 2 "uint32_operand" "")
8459 (match_operand:DI 3 "uint32_operand" "")))]
8461 "extrd,s %1,%3+%2-1,%2,%0"
8462 [(set_attr "type" "shift")
8463 (set_attr "length" "4")])
8466 [(set (match_operand:DI 0 "register_operand" "=r")
8467 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8469 (match_operand:DI 2 "register_operand" "q")))]
8471 "extrd,s %1,%%sar,1,%0"
8472 [(set_attr "type" "shift")
8473 (set_attr "length" "4")])
8475 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8476 (define_expand "insv"
8477 [(set (zero_extract (match_operand 0 "register_operand" "")
8478 (match_operand 1 "uint32_operand" "")
8479 (match_operand 2 "uint32_operand" ""))
8480 (match_operand 3 "arith5_operand" ""))]
8484 HOST_WIDE_INT len = INTVAL (operands[1]);
8485 HOST_WIDE_INT pos = INTVAL (operands[2]);
8487 /* PA insertion insns don't support zero length bitfields or fields
8488 extending beyond the left or right-most bits. Also, we reject lengths
8489 equal to a word as they are better handled by the move patterns. */
8490 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8493 /* From mips.md: insert_bit_field doesn't verify that our destination
8494 matches the predicate, so check it again here. */
8495 if (!register_operand (operands[0], VOIDmode))
8499 emit_insn (gen_insv_64 (operands[0], operands[1],
8500 operands[2], operands[3]));
8502 emit_insn (gen_insv_32 (operands[0], operands[1],
8503 operands[2], operands[3]));
8507 (define_insn "insv_32"
8508 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8509 (match_operand:SI 1 "uint5_operand" "")
8510 (match_operand:SI 2 "uint5_operand" ""))
8511 (match_operand:SI 3 "arith5_operand" "r,L"))]
8514 {dep|depw} %3,%2+%1-1,%1,%0
8515 {depi|depwi} %3,%2+%1-1,%1,%0"
8516 [(set_attr "type" "shift,shift")
8517 (set_attr "length" "4,4")])
8519 ;; Optimize insertion of const_int values of type 1...1xxxx.
8521 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8522 (match_operand:SI 1 "uint5_operand" "")
8523 (match_operand:SI 2 "uint5_operand" ""))
8524 (match_operand:SI 3 "const_int_operand" ""))]
8525 "(INTVAL (operands[3]) & 0x10) != 0 &&
8526 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8529 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8530 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8532 [(set_attr "type" "shift")
8533 (set_attr "length" "4")])
8535 (define_insn "insv_64"
8536 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8537 (match_operand:DI 1 "uint32_operand" "")
8538 (match_operand:DI 2 "uint32_operand" ""))
8539 (match_operand:DI 3 "arith32_operand" "r,L"))]
8542 depd %3,%2+%1-1,%1,%0
8543 depdi %3,%2+%1-1,%1,%0"
8544 [(set_attr "type" "shift,shift")
8545 (set_attr "length" "4,4")])
8547 ;; Optimize insertion of const_int values of type 1...1xxxx.
8549 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8550 (match_operand:DI 1 "uint32_operand" "")
8551 (match_operand:DI 2 "uint32_operand" ""))
8552 (match_operand:DI 3 "const_int_operand" ""))]
8553 "(INTVAL (operands[3]) & 0x10) != 0
8555 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8558 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8559 return \"depdi %3,%2+%1-1,%1,%0\";
8561 [(set_attr "type" "shift")
8562 (set_attr "length" "4")])
8565 [(set (match_operand:DI 0 "register_operand" "=r")
8566 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8569 "depd,z %1,31,32,%0"
8570 [(set_attr "type" "shift")
8571 (set_attr "length" "4")])
8573 ;; This insn is used for some loop tests, typically loops reversed when
8574 ;; strength reduction is used. It is actually created when the instruction
8575 ;; combination phase combines the special loop test. Since this insn
8576 ;; is both a jump insn and has an output, it must deal with its own
8577 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8578 ;; to not choose the register alternatives in the event a reload is needed.
8579 (define_insn "decrement_and_branch_until_zero"
8582 (match_operator 2 "comparison_operator"
8584 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8585 (match_operand:SI 1 "int5_operand" "L,L,L"))
8587 (label_ref (match_operand 3 "" ""))
8590 (plus:SI (match_dup 0) (match_dup 1)))
8591 (clobber (match_scratch:SI 4 "=X,r,r"))]
8593 "* return output_dbra (operands, insn, which_alternative); "
8594 ;; Do not expect to understand this the first time through.
8595 [(set_attr "type" "cbranch,multi,multi")
8596 (set (attr "length")
8597 (if_then_else (eq_attr "alternative" "0")
8598 ;; Loop counter in register case
8599 ;; Short branch has length of 4
8600 ;; Long branch has length of 8, 20, 24 or 28
8601 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8602 (const_int MAX_12BIT_OFFSET))
8604 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8605 (const_int MAX_17BIT_OFFSET))
8607 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8609 (eq (symbol_ref "flag_pic") (const_int 0))
8613 ;; Loop counter in FP reg case.
8614 ;; Extra goo to deal with additional reload insns.
8615 (if_then_else (eq_attr "alternative" "1")
8616 (if_then_else (lt (match_dup 3) (pc))
8617 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8618 (const_int MAX_12BIT_OFFSET))
8620 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8621 (const_int MAX_17BIT_OFFSET))
8623 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8625 (eq (symbol_ref "flag_pic") (const_int 0))
8628 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8629 (const_int MAX_12BIT_OFFSET))
8631 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8632 (const_int MAX_17BIT_OFFSET))
8634 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8636 (eq (symbol_ref "flag_pic") (const_int 0))
8640 ;; Loop counter in memory case.
8641 ;; Extra goo to deal with additional reload insns.
8642 (if_then_else (lt (match_dup 3) (pc))
8643 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8644 (const_int MAX_12BIT_OFFSET))
8646 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8647 (const_int MAX_17BIT_OFFSET))
8649 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8651 (eq (symbol_ref "flag_pic") (const_int 0))
8654 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8655 (const_int MAX_12BIT_OFFSET))
8657 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8658 (const_int MAX_17BIT_OFFSET))
8660 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8662 (eq (symbol_ref "flag_pic") (const_int 0))
8664 (const_int 36))))))])
8669 (match_operator 2 "movb_comparison_operator"
8670 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8671 (label_ref (match_operand 3 "" ""))
8673 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8676 "* return output_movb (operands, insn, which_alternative, 0); "
8677 ;; Do not expect to understand this the first time through.
8678 [(set_attr "type" "cbranch,multi,multi,multi")
8679 (set (attr "length")
8680 (if_then_else (eq_attr "alternative" "0")
8681 ;; Loop counter in register case
8682 ;; Short branch has length of 4
8683 ;; Long branch has length of 8, 20, 24 or 28
8684 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8685 (const_int MAX_12BIT_OFFSET))
8687 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8688 (const_int MAX_17BIT_OFFSET))
8690 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8692 (eq (symbol_ref "flag_pic") (const_int 0))
8696 ;; Loop counter in FP reg case.
8697 ;; Extra goo to deal with additional reload insns.
8698 (if_then_else (eq_attr "alternative" "1")
8699 (if_then_else (lt (match_dup 3) (pc))
8700 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8701 (const_int MAX_12BIT_OFFSET))
8703 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8704 (const_int MAX_17BIT_OFFSET))
8706 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8708 (eq (symbol_ref "flag_pic") (const_int 0))
8711 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8712 (const_int MAX_12BIT_OFFSET))
8714 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8715 (const_int MAX_17BIT_OFFSET))
8717 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8719 (eq (symbol_ref "flag_pic") (const_int 0))
8723 ;; Loop counter in memory or sar case.
8724 ;; Extra goo to deal with additional reload insns.
8725 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8726 (const_int MAX_12BIT_OFFSET))
8728 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8729 (const_int MAX_17BIT_OFFSET))
8731 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8733 (eq (symbol_ref "flag_pic") (const_int 0))
8735 (const_int 32)))))])
8737 ;; Handle negated branch.
8741 (match_operator 2 "movb_comparison_operator"
8742 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8744 (label_ref (match_operand 3 "" ""))))
8745 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8748 "* return output_movb (operands, insn, which_alternative, 1); "
8749 ;; Do not expect to understand this the first time through.
8750 [(set_attr "type" "cbranch,multi,multi,multi")
8751 (set (attr "length")
8752 (if_then_else (eq_attr "alternative" "0")
8753 ;; Loop counter in register case
8754 ;; Short branch has length of 4
8755 ;; Long branch has length of 8
8756 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8757 (const_int MAX_12BIT_OFFSET))
8759 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8760 (const_int MAX_17BIT_OFFSET))
8762 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8764 (eq (symbol_ref "flag_pic") (const_int 0))
8768 ;; Loop counter in FP reg case.
8769 ;; Extra goo to deal with additional reload insns.
8770 (if_then_else (eq_attr "alternative" "1")
8771 (if_then_else (lt (match_dup 3) (pc))
8772 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8773 (const_int MAX_12BIT_OFFSET))
8775 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8776 (const_int MAX_17BIT_OFFSET))
8778 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8780 (eq (symbol_ref "flag_pic") (const_int 0))
8783 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8784 (const_int MAX_12BIT_OFFSET))
8786 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8787 (const_int MAX_17BIT_OFFSET))
8789 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8791 (eq (symbol_ref "flag_pic") (const_int 0))
8795 ;; Loop counter in memory or SAR case.
8796 ;; Extra goo to deal with additional reload insns.
8797 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8798 (const_int MAX_12BIT_OFFSET))
8800 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8801 (const_int MAX_17BIT_OFFSET))
8803 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8805 (eq (symbol_ref "flag_pic") (const_int 0))
8807 (const_int 32)))))])
8810 [(set (pc) (label_ref (match_operand 3 "" "" )))
8811 (set (match_operand:SI 0 "ireg_operand" "=r")
8812 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8813 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8814 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8817 return output_parallel_addb (operands, insn);
8819 [(set_attr "type" "parallel_branch")
8820 (set (attr "length")
8821 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8822 (const_int MAX_12BIT_OFFSET))
8824 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8825 (const_int MAX_17BIT_OFFSET))
8827 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8829 (eq (symbol_ref "flag_pic") (const_int 0))
8834 [(set (pc) (label_ref (match_operand 2 "" "" )))
8835 (set (match_operand:SF 0 "ireg_operand" "=r")
8836 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8840 return output_parallel_movb (operands, insn);
8842 [(set_attr "type" "parallel_branch")
8843 (set (attr "length")
8844 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8845 (const_int MAX_12BIT_OFFSET))
8847 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8848 (const_int MAX_17BIT_OFFSET))
8850 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8852 (eq (symbol_ref "flag_pic") (const_int 0))
8857 [(set (pc) (label_ref (match_operand 2 "" "" )))
8858 (set (match_operand:SI 0 "ireg_operand" "=r")
8859 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8863 return output_parallel_movb (operands, insn);
8865 [(set_attr "type" "parallel_branch")
8866 (set (attr "length")
8867 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8868 (const_int MAX_12BIT_OFFSET))
8870 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8871 (const_int MAX_17BIT_OFFSET))
8873 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8875 (eq (symbol_ref "flag_pic") (const_int 0))
8880 [(set (pc) (label_ref (match_operand 2 "" "" )))
8881 (set (match_operand:HI 0 "ireg_operand" "=r")
8882 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8886 return output_parallel_movb (operands, insn);
8888 [(set_attr "type" "parallel_branch")
8889 (set (attr "length")
8890 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8891 (const_int MAX_12BIT_OFFSET))
8893 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8894 (const_int MAX_17BIT_OFFSET))
8896 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8898 (eq (symbol_ref "flag_pic") (const_int 0))
8903 [(set (pc) (label_ref (match_operand 2 "" "" )))
8904 (set (match_operand:QI 0 "ireg_operand" "=r")
8905 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8909 return output_parallel_movb (operands, insn);
8911 [(set_attr "type" "parallel_branch")
8912 (set (attr "length")
8913 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8914 (const_int MAX_12BIT_OFFSET))
8916 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8917 (const_int MAX_17BIT_OFFSET))
8919 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
8921 (eq (symbol_ref "flag_pic") (const_int 0))
8926 [(set (match_operand 0 "register_operand" "=f")
8927 (mult (match_operand 1 "register_operand" "f")
8928 (match_operand 2 "register_operand" "f")))
8929 (set (match_operand 3 "register_operand" "+f")
8930 (plus (match_operand 4 "register_operand" "f")
8931 (match_operand 5 "register_operand" "f")))]
8932 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8933 && reload_completed && fmpyaddoperands (operands)"
8936 if (GET_MODE (operands[0]) == DFmode)
8938 if (rtx_equal_p (operands[3], operands[5]))
8939 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8941 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8945 if (rtx_equal_p (operands[3], operands[5]))
8946 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8948 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8951 [(set_attr "type" "fpalu")
8952 (set_attr "length" "4")])
8955 [(set (match_operand 3 "register_operand" "+f")
8956 (plus (match_operand 4 "register_operand" "f")
8957 (match_operand 5 "register_operand" "f")))
8958 (set (match_operand 0 "register_operand" "=f")
8959 (mult (match_operand 1 "register_operand" "f")
8960 (match_operand 2 "register_operand" "f")))]
8961 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8962 && reload_completed && fmpyaddoperands (operands)"
8965 if (GET_MODE (operands[0]) == DFmode)
8967 if (rtx_equal_p (operands[3], operands[5]))
8968 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8970 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8974 if (rtx_equal_p (operands[3], operands[5]))
8975 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8977 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8980 [(set_attr "type" "fpalu")
8981 (set_attr "length" "4")])
8984 [(set (match_operand 0 "register_operand" "=f")
8985 (mult (match_operand 1 "register_operand" "f")
8986 (match_operand 2 "register_operand" "f")))
8987 (set (match_operand 3 "register_operand" "+f")
8988 (minus (match_operand 4 "register_operand" "f")
8989 (match_operand 5 "register_operand" "f")))]
8990 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8991 && reload_completed && fmpysuboperands (operands)"
8994 if (GET_MODE (operands[0]) == DFmode)
8995 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8997 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8999 [(set_attr "type" "fpalu")
9000 (set_attr "length" "4")])
9003 [(set (match_operand 3 "register_operand" "+f")
9004 (minus (match_operand 4 "register_operand" "f")
9005 (match_operand 5 "register_operand" "f")))
9006 (set (match_operand 0 "register_operand" "=f")
9007 (mult (match_operand 1 "register_operand" "f")
9008 (match_operand 2 "register_operand" "f")))]
9009 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9010 && reload_completed && fmpysuboperands (operands)"
9013 if (GET_MODE (operands[0]) == DFmode)
9014 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9016 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9018 [(set_attr "type" "fpalu")
9019 (set_attr "length" "4")])
9021 ;; The following two patterns are used by the trampoline code for nested
9022 ;; functions. They flush the I and D cache lines from the start address
9023 ;; (operand0) to the end address (operand1). No lines are flushed if the
9024 ;; end address is less than the start address (unsigned).
9026 ;; Because the range of memory flushed is variable and the size of a MEM
9027 ;; can only be a CONST_INT, the patterns specify that they perform an
9028 ;; unspecified volatile operation on all memory.
9030 ;; The address range for an icache flush must lie within a single
9031 ;; space on targets with non-equivalent space registers.
9033 ;; Operand 0 contains the start address.
9034 ;; Operand 1 contains the end address.
9035 ;; Operand 2 contains the line length to use.
9036 (define_insn "dcacheflush<P:mode>"
9038 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9039 (use (match_operand 0 "pmode_register_operand" "r"))
9040 (use (match_operand 1 "pmode_register_operand" "r"))
9041 (use (match_operand 2 "pmode_register_operand" "r"))
9042 (clobber (match_scratch:P 3 "=&0"))]
9044 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9045 [(set_attr "type" "multi")
9046 (set_attr "length" "12")])
9048 (define_insn "icacheflush<P:mode>"
9050 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9051 (use (match_operand 0 "pmode_register_operand" "r"))
9052 (use (match_operand 1 "pmode_register_operand" "r"))
9053 (use (match_operand 2 "pmode_register_operand" "r"))
9054 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9055 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9056 (clobber (match_scratch:P 5 "=&0"))]
9058 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9059 [(set_attr "type" "multi")
9060 (set_attr "length" "52")])
9062 ;; An out-of-line prologue.
9063 (define_insn "outline_prologue_call"
9064 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9065 (clobber (reg:SI 31))
9066 (clobber (reg:SI 22))
9067 (clobber (reg:SI 21))
9068 (clobber (reg:SI 20))
9069 (clobber (reg:SI 19))
9070 (clobber (reg:SI 1))]
9075 /* We need two different versions depending on whether or not we
9076 need a frame pointer. Also note that we return to the instruction
9077 immediately after the branch rather than two instructions after the
9078 break as normally is the case. */
9079 if (frame_pointer_needed)
9081 /* Must import the magic millicode routine(s). */
9082 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9084 if (TARGET_PORTABLE_RUNTIME)
9086 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9087 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9091 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9095 /* Must import the magic millicode routine(s). */
9096 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9098 if (TARGET_PORTABLE_RUNTIME)
9100 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9101 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9104 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9108 [(set_attr "type" "multi")
9109 (set_attr "length" "8")])
9111 ;; An out-of-line epilogue.
9112 (define_insn "outline_epilogue_call"
9113 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9116 (clobber (reg:SI 31))
9117 (clobber (reg:SI 22))
9118 (clobber (reg:SI 21))
9119 (clobber (reg:SI 20))
9120 (clobber (reg:SI 19))
9121 (clobber (reg:SI 2))
9122 (clobber (reg:SI 1))]
9127 /* We need two different versions depending on whether or not we
9128 need a frame pointer. Also note that we return to the instruction
9129 immediately after the branch rather than two instructions after the
9130 break as normally is the case. */
9131 if (frame_pointer_needed)
9133 /* Must import the magic millicode routine. */
9134 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9136 /* The out-of-line prologue will make sure we return to the right
9138 if (TARGET_PORTABLE_RUNTIME)
9140 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9141 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9145 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9149 /* Must import the magic millicode routine. */
9150 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9152 /* The out-of-line prologue will make sure we return to the right
9154 if (TARGET_PORTABLE_RUNTIME)
9156 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9157 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9160 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9164 [(set_attr "type" "multi")
9165 (set_attr "length" "8")])
9167 ;; Given a function pointer, canonicalize it so it can be
9168 ;; reliably compared to another function pointer. */
9169 (define_expand "canonicalize_funcptr_for_compare"
9170 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9171 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9172 (clobber (match_dup 2))
9173 (clobber (reg:SI 26))
9174 (clobber (reg:SI 22))
9175 (clobber (reg:SI 31))])
9176 (set (match_operand:SI 0 "register_operand" "")
9178 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9183 rtx canonicalize_funcptr_for_compare_libfunc
9184 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9186 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9187 operands[0], LCT_NORMAL, Pmode,
9188 1, operands[1], Pmode);
9192 operands[2] = gen_reg_rtx (SImode);
9193 if (GET_CODE (operands[1]) != REG)
9195 rtx tmp = gen_reg_rtx (Pmode);
9196 emit_move_insn (tmp, operands[1]);
9201 (define_insn "*$$sh_func_adrs"
9202 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9203 (clobber (match_operand:SI 0 "register_operand" "=a"))
9204 (clobber (reg:SI 26))
9205 (clobber (reg:SI 22))
9206 (clobber (reg:SI 31))]
9210 int length = get_attr_length (insn);
9213 xoperands[0] = GEN_INT (length - 8);
9214 xoperands[1] = GEN_INT (length - 16);
9216 /* Must import the magic millicode routine. */
9217 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9219 /* This is absolutely amazing.
9221 First, copy our input parameter into %r29 just in case we don't
9222 need to call $$sh_func_adrs. */
9223 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9224 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9226 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9227 we use %r26 unchanged. */
9228 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9229 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9231 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9232 4096, then again we use %r26 unchanged. */
9233 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9235 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9236 return output_millicode_call (insn,
9237 gen_rtx_SYMBOL_REF (SImode,
9238 \"$$sh_func_adrs\"));
9240 [(set_attr "type" "multi")
9241 (set (attr "length")
9242 (plus (symbol_ref "attr_length_millicode_call (insn)")
9245 ;; On the PA, the PIC register is call clobbered, so it must
9246 ;; be saved & restored around calls by the caller. If the call
9247 ;; doesn't return normally (nonlocal goto, or an exception is
9248 ;; thrown), then the code at the exception handler label must
9249 ;; restore the PIC register.
9250 (define_expand "exception_receiver"
9255 /* On the 64-bit port, we need a blockage because there is
9256 confusion regarding the dependence of the restore on the
9257 frame pointer. As a result, the frame pointer and pic
9258 register restores sometimes are interchanged erroneously. */
9260 emit_insn (gen_blockage ());
9261 /* Restore the PIC register using hppa_pic_save_rtx (). The
9262 PIC register is not saved in the frame in 64-bit ABI. */
9263 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9264 emit_insn (gen_blockage ());
9268 (define_expand "builtin_setjmp_receiver"
9269 [(label_ref (match_operand 0 "" ""))]
9274 emit_insn (gen_blockage ());
9275 /* Restore the PIC register. Hopefully, this will always be from
9276 a stack slot. The only registers that are valid after a
9277 builtin_longjmp are the stack and frame pointers. */
9278 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9279 emit_insn (gen_blockage ());
9283 ;; Allocate new stack space and update the saved stack pointer in the
9284 ;; frame marker. The HP C compilers also copy additional words in the
9285 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9286 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9287 ;; currently don't copy these values.
9289 ;; Since the copy of the frame marker can't be done atomically, I
9290 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9291 ;; The HP compilers appear to raise the stack and copy the frame
9292 ;; marker in a strict instruction sequence. This suggests that the
9293 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9294 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9295 ;; as GAS doesn't support it, or try to keep the instructions emitted
9296 ;; here in strict sequence.
9297 (define_expand "allocate_stack"
9298 [(match_operand 0 "" "")
9299 (match_operand 1 "" "")]
9305 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9306 in operand 0 before adjusting the stack. */
9307 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9308 anti_adjust_stack (operands[1]);
9309 if (TARGET_HPUX_UNWIND_LIBRARY)
9311 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9312 GEN_INT (TARGET_64BIT ? -8 : -4));
9313 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9315 if (!TARGET_64BIT && flag_pic)
9317 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9318 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9323 (define_expand "prefetch"
9324 [(match_operand 0 "address_operand" "")
9325 (match_operand 1 "const_int_operand" "")
9326 (match_operand 2 "const_int_operand" "")]
9329 operands[0] = copy_addr_to_reg (operands[0]);
9330 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9334 (define_insn "prefetch_20"
9335 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9336 (match_operand:SI 1 "const_int_operand" "n")
9337 (match_operand:SI 2 "const_int_operand" "n"))]
9340 /* The SL cache-control completer indicates good spatial locality but
9341 poor temporal locality. The ldw instruction with a target of general
9342 register 0 prefetches a cache line for a read. The ldd instruction
9343 prefetches a cache line for a write. */
9344 static const char * const instr[2][2] = {
9346 "ldw,sl 0(%0),%%r0",
9354 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9355 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9357 return instr [locality][read_or_write];
9359 [(set_attr "type" "load")
9360 (set_attr "length" "4")])
9363 (define_insn "tgd_load"
9364 [(set (match_operand:SI 0 "register_operand" "=r")
9365 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9366 (clobber (reg:SI 1))
9371 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9373 [(set_attr "type" "multi")
9374 (set_attr "length" "8")])
9376 (define_insn "tgd_load_pic"
9377 [(set (match_operand:SI 0 "register_operand" "=r")
9378 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9379 (clobber (reg:SI 1))
9384 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9386 [(set_attr "type" "multi")
9387 (set_attr "length" "8")])
9389 (define_insn "tld_load"
9390 [(set (match_operand:SI 0 "register_operand" "=r")
9391 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9392 (clobber (reg:SI 1))
9397 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9399 [(set_attr "type" "multi")
9400 (set_attr "length" "8")])
9402 (define_insn "tld_load_pic"
9403 [(set (match_operand:SI 0 "register_operand" "=r")
9404 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9405 (clobber (reg:SI 1))
9410 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9412 [(set_attr "type" "multi")
9413 (set_attr "length" "8")])
9415 (define_insn "tld_offset_load"
9416 [(set (match_operand:SI 0 "register_operand" "=r")
9417 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9419 (match_operand:SI 2 "register_operand" "r")))
9420 (clobber (reg:SI 1))]
9424 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9426 [(set_attr "type" "multi")
9427 (set_attr "length" "8")])
9429 (define_insn "tp_load"
9430 [(set (match_operand:SI 0 "register_operand" "=r")
9431 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9434 [(set_attr "type" "multi")
9435 (set_attr "length" "4")])
9437 (define_insn "tie_load"
9438 [(set (match_operand:SI 0 "register_operand" "=r")
9439 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9440 (clobber (reg:SI 1))
9445 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9447 [(set_attr "type" "multi")
9448 (set_attr "length" "8")])
9450 (define_insn "tie_load_pic"
9451 [(set (match_operand:SI 0 "register_operand" "=r")
9452 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9453 (clobber (reg:SI 1))
9458 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9460 [(set_attr "type" "multi")
9461 (set_attr "length" "8")])
9463 (define_insn "tle_load"
9464 [(set (match_operand:SI 0 "register_operand" "=r")
9465 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9467 (match_operand:SI 2 "register_operand" "r")))
9468 (clobber (reg:SI 1))]
9470 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9471 [(set_attr "type" "multi")
9472 (set_attr "length" "8")])