| blob | 83b7044d92580eea1d6b006d1b7b55577f647027 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
66 /* This file should be included last. */
69 /* Defined for convenience. */
70 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
72 /* Classifies an address.
74 ADDRESS_REG_IMM
75 A simple base register plus immediate offset.
77 ADDRESS_REG_WB
78 A base register indexed by immediate offset with writeback.
80 ADDRESS_REG_REG
81 A base register indexed by (optionally scaled) register.
83 ADDRESS_REG_UXTW
84 A base register indexed by (optionally scaled) zero-extended register.
86 ADDRESS_REG_SXTW
87 A base register indexed by (optionally scaled) sign-extended register.
89 ADDRESS_LO_SUM
90 A LO_SUM rtx with a base register and "LO12" symbol relocation.
92 ADDRESS_SYMBOLIC:
93 A constant symbolic address, in pc-relative literal pool. */
96 ADDRESS_REG_IMM,
97 ADDRESS_REG_WB,
98 ADDRESS_REG_REG,
99 ADDRESS_REG_UXTW,
100 ADDRESS_REG_SXTW,
101 ADDRESS_LO_SUM,
102 ADDRESS_SYMBOLIC
103 };
107 rtx base;
108 rtx offset;
111 };
113 struct simd_immediate_info
114 {
115 rtx value;
120 };
122 /* The current code model. */
125 #ifdef HAVE_AS_TLS
126 #undef TARGET_HAVE_TLS
127 #define TARGET_HAVE_TLS 1
128 #endif
132 const_tree,
143 /* Major revision number of the ARM Architecture implemented by the target. */
146 /* The processor for which instructions should be scheduled. */
149 /* Mask to specify which instruction scheduling options should be used. */
152 /* Global flag for PC relative loads. */
155 /* Support for command line parsing of boolean flags in the tuning
156 structures. */
157 struct aarch64_flag_desc
158 {
161 };
163 #define AARCH64_FUSION_PAIR(name, internal_name) \
164 { name, AARCH64_FUSE_##internal_name },
166 {
171 };
172 #undef AARCH64_FUION_PAIR
174 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
175 { name, AARCH64_EXTRA_TUNE_##internal_name },
177 {
182 };
183 #undef AARCH64_EXTRA_TUNING_OPTION
185 /* Tuning parameters. */
188 {
189 {
194 },
201 };
204 {
205 {
210 },
217 };
220 {
221 {
226 },
233 };
236 {
238 /* Avoid the use of slow int<->fp moves for spilling by setting
239 their cost higher than memmov_cost. */
243 };
246 {
248 /* Avoid the use of slow int<->fp moves for spilling by setting
249 their cost higher than memmov_cost. */
253 };
256 {
258 /* Avoid the use of slow int<->fp moves for spilling by setting
259 their cost higher than memmov_cost. */
263 };
266 {
271 };
274 {
276 /* Avoid the use of slow int<->fp moves for spilling by setting
277 their cost higher than memmov_cost. */
281 };
283 /* Generic costs for vector insn classes. */
285 {
298 };
300 /* Generic costs for vector insn classes. */
302 {
315 };
317 /* Generic costs for vector insn classes. */
319 {
332 };
334 /* Generic costs for branch instructions. */
336 {
339 };
342 {
361 };
364 {
384 };
387 {
406 (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS
408 };
411 {
431 };
434 {
453 };
456 {
475 };
477 /* Support for fine-grained override of the tuning structures. */
478 struct aarch64_tuning_override_function
479 {
482 };
487 static const struct aarch64_tuning_override_function
488 aarch64_tuning_override_functions[] =
489 {
493 };
495 /* A processor implementing AArch64. */
496 struct processor
497 {
505 };
507 /* Architectures implementing AArch64. */
509 {
510 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
511 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, ARCH_REV, FLAGS, NULL},
513 #undef AARCH64_ARCH
515 };
517 /* Processor cores implementing AArch64. */
519 {
520 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \
521 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
522 all_architectures[AARCH64_ARCH_##ARCH].architecture_version, \
523 FLAGS, &COSTS##_tunings},
525 #undef AARCH64_CORE
529 };
532 /* Target specification. These are populated by the -march, -mtune, -mcpu
533 handling code or by target attributes. */
538 /* The current tuning set. */
541 #define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
543 /* An ISA extension in the co-processor and main instruction set space. */
544 struct aarch64_option_extension
545 {
549 };
551 /* ISA extensions in AArch64. */
553 {
554 #define AARCH64_OPT_EXTENSION(NAME, FLAGS_ON, FLAGS_OFF, FEATURE_STRING) \
555 {NAME, FLAGS_ON, FLAGS_OFF},
557 #undef AARCH64_OPT_EXTENSION
559 };
562 {
566 }
567 aarch64_cc;
569 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
571 /* The condition codes of the processor, and the inverse function. */
573 {
576 };
578 /* Generate code to enable conditional branches in functions over 1 MiB. */
582 {
599 }
601 void
603 {
607 else
609 }
611 static unsigned int
613 {
617 }
619 static int
622 {
630 }
632 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
633 unsigned
635 {
643 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
644 equivalent DWARF register. */
646 }
648 /* Return TRUE if MODE is any of the large INT modes. */
649 static bool
651 {
653 }
655 /* Return TRUE if MODE is any of the vector modes. */
656 static bool
658 {
661 }
663 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
664 static bool
667 {
675 }
677 /* Implement HARD_REGNO_NREGS. */
679 int
681 {
683 {
689 }
691 }
693 /* Implement HARD_REGNO_MODE_OK. */
695 int
697 {
702 /* The purpose of comparing with ptr_mode is to support the
703 global register variable associated with the stack pointer
704 register via the syntax of asm ("wsp") in ILP32. */
714 {
716 return
718 else
720 }
723 }
725 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
726 machine_mode
728 machine_mode mode)
729 {
730 /* Handle modes that fit within single registers. */
732 {
735 else
737 }
738 /* Fall back to generic for multi-reg and very large modes. */
739 else
741 }
743 /* Return true if calls to DECL should be treated as
744 long-calls (ie called via a register). */
745 static bool
747 {
749 }
751 /* Return true if calls to symbol-ref SYM should be treated as
752 long-calls (ie called via a register). */
753 bool
755 {
757 }
759 /* Return true if calls to symbol-ref SYM should not go through
760 plt stubs. */
762 bool
764 {
768 && decl
769 && (!flag_plt
775 }
777 /* Return true if the offsets to a zero/sign-extract operation
778 represent an expression that matches an extend operation. The
779 operands represent the paramters from
781 (extract:MODE (mult (reg) (MULT_IMM)) (EXTRACT_IMM) (const_int 0)). */
782 bool
784 rtx extract_imm)
785 {
802 }
804 /* Emit an insn that's a simple single-set. Both the operands must be
805 known to be valid. */
808 {
810 }
812 /* X and Y are two things to compare using CODE. Emit the compare insn and
813 return the rtx for register 0 in the proper mode. */
814 rtx
816 {
822 }
824 /* Build the SYMBOL_REF for __tls_get_addr. */
828 rtx
830 {
834 }
836 /* Return the TLS model to use for ADDR. */
838 static enum tls_model
840 {
845 {
849 }
854 }
856 /* We'll allow lo_sum's in addresses in our legitimate addresses
857 so that combine would take care of combining addresses where
858 necessary, but for generation purposes, we'll generate the address
859 as :
860 RTL Absolute
861 tmp = hi (symbol_ref); adrp x1, foo
862 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
863 nop
865 PIC TLS
866 adrp x1, :got:foo adrp tmp, :tlsgd:foo
867 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
868 bl __tls_get_addr
869 nop
871 Load TLS symbol, depending on TLS mechanism and TLS access model.
873 Global Dynamic - Traditional TLS:
874 adrp tmp, :tlsgd:imm
875 add dest, tmp, #:tlsgd_lo12:imm
876 bl __tls_get_addr
878 Global Dynamic - TLS Descriptors:
879 adrp dest, :tlsdesc:imm
880 ldr tmp, [dest, #:tlsdesc_lo12:imm]
881 add dest, dest, #:tlsdesc_lo12:imm
882 blr tmp
883 mrs tp, tpidr_el0
884 add dest, dest, tp
886 Initial Exec:
887 mrs tp, tpidr_el0
888 adrp tmp, :gottprel:imm
889 ldr dest, [tmp, #:gottprel_lo12:imm]
890 add dest, dest, tp
892 Local Exec:
893 mrs tp, tpidr_el0
894 add t0, tp, #:tprel_hi12:imm, lsl #12
895 add t0, t0, #:tprel_lo12_nc:imm
896 */
898 static void
901 {
903 {
905 {
906 /* In ILP32, the mode of dest can be either SImode or DImode. */
918 }
925 {
928 rtx insn;
929 rtx mem;
931 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
932 here before rtl expand. Tree IVOPT will generate rtl pattern to
933 decide rtx costs, in which case pic_offset_table_rtx is not
934 initialized. For that case no need to generate the first adrp
935 instruction as the final cost for global variable access is
936 one instruction. */
938 {
939 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
940 using the page base as GOT base, the first page may be wasted,
941 in the worst scenario, there is only 28K space for GOT).
943 The generate instruction sequence for accessing global variable
944 is:
946 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
948 Only one instruction needed. But we must initialize
949 pic_offset_table_rtx properly. We generate initialize insn for
950 every global access, and allow CSE to remove all redundant.
952 The final instruction sequences will look like the following
953 for multiply global variables access.
955 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
957 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
958 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
959 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
960 ... */
968 }
971 {
974 else
978 }
979 else
980 {
985 }
987 /* The operand is expected to be MEM. Whenever the related insn
988 pattern changed, above code which calculate mem should be
989 updated. */
995 }
998 {
999 /* In ILP32, the mode of dest can be either SImode or DImode,
1000 while the got entry is always of SImode size. The mode of
1001 dest depends on how dest is used: if dest is assigned to a
1002 pointer (e.g. in the memory), it has SImode; it may have
1003 DImode if dest is dereferenced to access the memeory.
1004 This is why we have to handle three different ldr_got_small
1005 patterns here (two patterns for ILP32). */
1007 rtx insn;
1008 rtx mem;
1017 {
1020 else
1024 }
1025 else
1026 {
1031 }
1038 }
1041 {
1053 }
1056 {
1059 rtx tp;
1063 /* In ILP32, the got entry is always of SImode size. Unlike
1064 small GOT, the dest is fixed at reg 0. */
1067 else
1077 }
1080 {
1081 /* In ILP32, the mode of dest can be either SImode or DImode,
1082 while the got entry is always of SImode size. The mode of
1083 dest depends on how dest is used: if dest is assigned to a
1084 pointer (e.g. in the memory), it has SImode; it may have
1085 DImode if dest is dereferenced to access the memeory.
1086 This is why we have to handle three different tlsie_small
1087 patterns here (two patterns for ILP32). */
1093 {
1096 else
1097 {
1100 }
1101 }
1102 else
1103 {
1106 }
1111 }
1117 {
1125 {
1148 }
1152 }
1159 {
1164 {
1167 else
1168 {
1171 }
1172 }
1173 else
1174 {
1177 }
1181 }
1185 }
1186 }
1188 /* Emit a move from SRC to DEST. Assume that the move expanders can
1189 handle all moves if !can_create_pseudo_p (). The distinction is
1190 important because, unlike emit_move_insn, the move expanders know
1191 how to force Pmode objects into the constant pool even when the
1192 constant pool address is not itself legitimate. */
1193 static rtx
1195 {
1199 }
1201 /* Split a 128-bit move operation into two 64-bit move operations,
1202 taking care to handle partial overlap of register to register
1203 copies. Special cases are needed when moving between GP regs and
1204 FP regs. SRC can be a register, constant or memory; DST a register
1205 or memory. If either operand is memory it must not have any side
1206 effects. */
1207 void
1209 {
1220 {
1224 /* Handle FP <-> GP regs. */
1226 {
1231 {
1234 }
1235 else
1236 {
1239 }
1241 }
1243 {
1248 {
1251 }
1252 else
1253 {
1256 }
1258 }
1259 }
1266 /* At most one pairing may overlap. */
1268 {
1271 }
1272 else
1273 {
1276 }
1277 }
1279 bool
1281 {
1284 }
1286 /* Split a complex SIMD combine. */
1288 void
1290 {
1297 {
1301 {
1325 }
1329 }
1330 }
1332 /* Split a complex SIMD move. */
1334 void
1336 {
1343 {
1349 {
1373 }
1377 }
1378 }
1380 static rtx
1382 {
1385 else
1386 {
1389 }
1390 }
1393 static rtx
1395 {
1397 {
1398 rtx high;
1399 /* Load the full offset into a register. This
1400 might be improvable in the future. */
1406 }
1408 }
1410 static int
1412 machine_mode mode)
1413 {
1422 {
1426 }
1429 {
1431 {
1436 else
1439 }
1441 }
1443 /* Remaining cases are all for DImode. */
1452 {
1453 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
1454 For a 64-bit bitmask try whether changing 16 bits to all ones or
1455 zeroes creates a valid bitmask. To check any repeated bitmask,
1456 try using 16 bits from the other 32-bit half of val. */
1459 {
1470 }
1472 {
1474 {
1478 }
1479 }
1480 }
1482 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
1483 are emitted by the initial mov. If one_match > zero_match, skip set bits,
1484 otherwise skip zero bits. */
1496 {
1502 num_insns ++;
1503 }
1506 }
1509 void
1511 {
1516 /* Check on what type of symbol it is. */
1520 {
1524 /* If we have (const (plus symbol offset)), separate out the offset
1525 before we start classifying the symbol. */
1530 {
1534 {
1540 }
1545 /* If we aren't generating PC relative literals, then
1546 we need to expand the literal pool access carefully.
1547 This is something that needs to be done in a number
1548 of places, so could well live as a separate function. */
1550 {
1555 }
1572 {
1578 }
1579 /* FALLTHRU */
1592 }
1593 }
1596 {
1599 else
1600 {
1604 }
1607 }
1610 }
1612 static bool
1614 tree exp ATTRIBUTE_UNUSED)
1615 {
1616 /* Currently, always true. */
1618 }
1620 /* Implement TARGET_PASS_BY_REFERENCE. */
1622 static bool
1624 machine_mode mode,
1625 const_tree type,
1627 {
1628 HOST_WIDE_INT size;
1629 machine_mode dummymode;
1632 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
1636 /* Aggregates are passed by reference based on their size. */
1638 {
1640 }
1642 /* Variable sized arguments are always returned by reference. */
1646 /* Can this be a candidate to be passed in fp/simd register(s)? */
1649 NULL))
1652 /* Arguments which are variable sized or larger than 2 registers are
1653 passed by reference unless they are a homogenous floating point
1654 aggregate. */
1656 }
1658 /* Return TRUE if VALTYPE is padded to its least significant bits. */
1659 static bool
1661 {
1662 machine_mode dummy_mode;
1665 /* Never happens in little-endian mode. */
1669 /* Only composite types smaller than or equal to 16 bytes can
1670 be potentially returned in registers. */
1676 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
1677 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
1678 is always passed/returned in the least significant bits of fp/simd
1679 register(s). */
1685 }
1687 /* Implement TARGET_FUNCTION_VALUE.
1688 Define how to find the value returned by a function. */
1690 static rtx
1693 {
1694 machine_mode mode;
1697 machine_mode ag_mode;
1704 {
1708 {
1711 }
1712 }
1716 {
1718 {
1721 }
1722 else
1723 {
1725 rtx par;
1729 {
1734 }
1736 }
1737 }
1738 else
1740 }
1742 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
1743 Return true if REGNO is the number of a hard register in which the values
1744 of called function may come back. */
1746 static bool
1748 {
1749 /* Maximum of 16 bytes can be returned in the general registers. Examples
1750 of 16-byte return values are: 128-bit integers and 16-byte small
1751 structures (excluding homogeneous floating-point aggregates). */
1755 /* Up to four fp/simd registers can return a function value, e.g. a
1756 homogeneous floating-point aggregate having four members. */
1761 }
1763 /* Implement TARGET_RETURN_IN_MEMORY.
1765 If the type T of the result of a function is such that
1766 void func (T arg)
1767 would require that arg be passed as a value in a register (or set of
1768 registers) according to the parameter passing rules, then the result
1769 is returned in the same registers as would be used for such an
1770 argument. */
1772 static bool
1774 {
1775 HOST_WIDE_INT size;
1776 machine_mode ag_mode;
1782 /* Simple scalar types always returned in registers. */
1786 type,
1789 NULL))
1792 /* Types larger than 2 registers returned in memory. */
1795 }
1797 static bool
1800 {
1803 type,
1805 nregs,
1806 NULL);
1807 }
1809 /* Given MODE and TYPE of a function argument, return the alignment in
1810 bits. The idea is to suppress any stronger alignment requested by
1811 the user and opt for the natural alignment (specified in AAPCS64 \S 4.1).
1812 This is a helper function for local use only. */
1814 static unsigned int
1816 {
1820 {
1822 {
1825 else
1827 }
1828 else
1830 }
1831 else
1835 }
1837 /* Layout a function argument according to the AAPCS64 rules. The rule
1838 numbers refer to the rule numbers in the AAPCS64. */
1840 static void
1842 const_tree type,
1844 {
1848 HOST_WIDE_INT size;
1850 /* We need to do this once per argument. */
1856 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
1857 size
1859 UNITS_PER_WORD);
1863 mode,
1864 type,
1867 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
1868 The following code thus handles passing by SIMD/FP registers first. */
1872 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
1873 and homogenous short-vector aggregates (HVA). */
1875 {
1880 {
1883 {
1886 }
1887 else
1888 {
1889 rtx par;
1893 {
1896 tmp = gen_rtx_EXPR_LIST
1900 }
1902 }
1904 }
1905 else
1906 {
1907 /* C.3 NSRN is set to 8. */
1910 }
1911 }
1916 /* C6 - C9. though the sign and zero extension semantics are
1917 handled elsewhere. This is the case where the argument fits
1918 entirely general registers. */
1920 {
1925 /* C.8 if the argument has an alignment of 16 then the NGRN is
1926 rounded up to the next even number. */
1928 {
1931 }
1932 /* NREGS can be 0 when e.g. an empty structure is to be passed.
1933 A reg is still generated for it, but the caller should be smart
1934 enough not to use it. */
1936 {
1938 }
1939 else
1940 {
1941 rtx par;
1946 {
1951 }
1953 }
1957 }
1959 /* C.11 */
1962 /* The argument is passed on stack; record the needed number of words for
1963 this argument and align the total size if necessary. */
1964 on_stack:
1970 }
1972 /* Implement TARGET_FUNCTION_ARG. */
1974 static rtx
1977 {
1986 }
1988 void
1990 const_tree fntype ATTRIBUTE_UNUSED,
1991 rtx libname ATTRIBUTE_UNUSED,
1992 const_tree fndecl ATTRIBUTE_UNUSED,
1994 {
2008 {
2015 }
2017 }
2019 static void
2021 machine_mode mode,
2022 const_tree type,
2024 {
2027 {
2037 }
2038 }
2040 bool
2042 {
2045 }
2047 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
2048 PARM_BOUNDARY bits of alignment, but will be given anything up
2049 to STACK_BOUNDARY bits if the type requires it. This makes sure
2050 that both before and after the layout of each argument, the Next
2051 Stacked Argument Address (NSAA) will have a minimum alignment of
2052 8 bytes. */
2054 static unsigned int
2056 {
2064 }
2066 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
2068 Return true if an argument passed on the stack should be padded upwards,
2069 i.e. if the least-significant byte of the stack slot has useful data.
2071 Small aggregate types are placed in the lowest memory address.
2073 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
2075 bool
2077 {
2078 /* On little-endian targets, the least significant byte of every stack
2079 argument is passed at the lowest byte address of the stack slot. */
2083 /* Otherwise, integral, floating-point and pointer types are padded downward:
2084 the least significant byte of a stack argument is passed at the highest
2085 byte address of the stack slot. */
2092 /* Everything else padded upward, i.e. data in first byte of stack slot. */
2094 }
2096 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
2098 It specifies padding for the last (may also be the only)
2099 element of a block move between registers and memory. If
2100 assuming the block is in the memory, padding upward means that
2101 the last element is padded after its highest significant byte,
2102 while in downward padding, the last element is padded at the
2103 its least significant byte side.
2105 Small aggregates and small complex types are always padded
2106 upwards.
2108 We don't need to worry about homogeneous floating-point or
2109 short-vector aggregates; their move is not affected by the
2110 padding direction determined here. Regardless of endianness,
2111 each element of such an aggregate is put in the least
2112 significant bits of a fp/simd register.
2114 Return !BYTES_BIG_ENDIAN if the least significant byte of the
2115 register has useful data, and return the opposite if the most
2116 significant byte does. */
2118 bool
2121 {
2123 /* Small composite types are always padded upward. */
2125 {
2130 }
2132 /* Otherwise, use the default padding. */
2134 }
2136 static machine_mode
2138 {
2140 }
2142 static bool
2144 {
2145 /* In aarch64_override_options_after_change
2146 flag_omit_leaf_frame_pointer turns off the frame pointer by
2147 default. Turn it back on now if we've not got a leaf
2148 function. */
2154 }
2156 /* Mark the registers that need to be saved by the callee and calculate
2157 the size of the callee-saved registers area and frame record (both FP
2158 and LR may be omitted). */
2159 static void
2161 {
2168 #define SLOT_NOT_REQUIRED (-2)
2169 #define SLOT_REQUIRED (-1)
2174 /* First mark all the registers that really need to be saved... */
2181 /* ... that includes the eh data registers (if needed)... */
2187 /* ... and any callee saved register that dataflow says is live. */
2200 {
2201 /* FP and LR are placed in the linkage record. */
2208 }
2210 /* Now assign stack slots for them. */
2213 {
2220 }
2224 {
2232 }
2252 }
2254 static bool
2256 {
2258 }
2260 static unsigned
2262 {
2264 regno ++;
2266 }
2268 static void
2270 HOST_WIDE_INT adjustment)
2271 {
2282 }
2284 static rtx
2286 HOST_WIDE_INT adjustment)
2287 {
2289 {
2300 }
2301 }
2303 static void
2306 {
2316 }
2318 static rtx
2320 HOST_WIDE_INT adjustment)
2321 {
2323 {
2332 }
2333 }
2335 static rtx
2337 rtx reg2)
2338 {
2340 {
2349 }
2350 }
2352 static rtx
2354 rtx mem2)
2355 {
2357 {
2366 }
2367 }
2370 static void
2373 {
2383 {
2385 HOST_WIDE_INT offset;
2395 offset));
2403 {
2405 rtx mem2;
2409 offset));
2411 reg2));
2413 /* The first part of a frame-related parallel insn is
2414 always assumed to be relevant to the frame
2415 calculations; subsequent parts, are only
2416 frame-related if explicitly marked. */
2419 }
2420 else
2424 }
2425 }
2427 static void
2431 {
2437 HOST_WIDE_INT offset;
2442 {
2459 {
2461 rtx mem2;
2469 }
2470 else
2473 }
2474 }
2476 /* AArch64 stack frames generated by this compiler look like:
2478 +-------------------------------+
2479 | |
2480 | incoming stack arguments |
2481 | |
2482 +-------------------------------+
2483 | | <-- incoming stack pointer (aligned)
2484 | callee-allocated save area |
2485 | for register varargs |
2486 | |
2487 +-------------------------------+
2488 | local variables | <-- frame_pointer_rtx
2489 | |
2490 +-------------------------------+
2491 | padding0 | \
2492 +-------------------------------+ |
2493 | callee-saved registers | | frame.saved_regs_size
2494 +-------------------------------+ |
2495 | LR' | |
2496 +-------------------------------+ |
2497 | FP' | / <- hard_frame_pointer_rtx (aligned)
2498 +-------------------------------+
2499 | dynamic allocation |
2500 +-------------------------------+
2501 | padding |
2502 +-------------------------------+
2503 | outgoing stack arguments | <-- arg_pointer
2504 | |
2505 +-------------------------------+
2506 | | <-- stack_pointer_rtx (aligned)
2508 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
2509 but leave frame_pointer_rtx and hard_frame_pointer_rtx
2510 unchanged. */
2512 /* Generate the prologue instructions for entry into a function.
2513 Establish the stack frame by decreasing the stack pointer with a
2514 properly calculated size and, if necessary, create a frame record
2515 filled with the values of LR and previous frame pointer. The
2516 current FP is also set up if it is in use. */
2518 void
2520 {
2521 /* sub sp, sp, #<frame_size>
2522 stp {fp, lr}, [sp, #<frame_size> - 16]
2523 add fp, sp, #<frame_size> - hardfp_offset
2524 stp {cs_reg}, [fp, #-16] etc.
2526 sub sp, sp, <final_adjustment_if_any>
2527 */
2530 HOST_WIDE_INT hard_fp_offset;
2542 /* Store pairs and load pairs have a range only -512 to 504. */
2544 {
2545 /* When the frame has a large size, an initial decrease is done on
2546 the stack pointer to jump over the callee-allocated save area for
2547 register varargs, the local variable area and/or the callee-saved
2548 register area. This will allow the pre-index write-back
2549 store pair instructions to be used for setting up the stack frame
2550 efficiently. */
2559 {
2569 }
2571 {
2576 {
2580 }
2582 {
2586 }
2587 }
2588 }
2589 else
2593 {
2597 {
2601 {
2608 }
2609 else
2612 /* Set up frame pointer to point to the location of the
2613 previous frame pointer on the stack. */
2615 stack_pointer_rtx,
2619 }
2620 else
2621 {
2629 {
2633 }
2634 else
2635 {
2642 else
2644 }
2645 }
2648 skip_wb);
2650 skip_wb);
2651 }
2653 /* when offset >= 512,
2654 sub sp, sp, #<outgoing_args_size> */
2656 {
2658 {
2663 }
2664 }
2665 }
2667 /* Return TRUE if we can use a simple_return insn.
2669 This function checks whether the callee saved stack is empty, which
2670 means no restore actions are need. The pro_and_epilogue will use
2671 this to check whether shrink-wrapping opt is feasible. */
2673 bool
2675 {
2685 }
2687 /* Generate the epilogue instructions for returning from a function. */
2688 void
2690 {
2692 HOST_WIDE_INT fp_offset;
2693 HOST_WIDE_INT hard_fp_offset;
2695 /* We need to add memory barrier to prevent read from deallocated stack. */
2705 /* Store pairs and load pairs have a range only -512 to 504. */
2707 {
2715 {
2720 }
2721 }
2722 else
2725 /* If there were outgoing arguments or we've done dynamic stack
2726 allocation, then restore the stack pointer from the frame
2727 pointer. This is at most one insn and more efficient than using
2728 GCC's internal mechanism. */
2731 {
2736 hard_frame_pointer_rtx,
2739 }
2742 {
2765 {
2771 {
2776 }
2777 else
2778 {
2785 }
2786 }
2787 else
2788 {
2791 }
2793 /* Reset the CFA to be SP + FRAME_SIZE. */
2800 }
2803 {
2808 {
2812 }
2813 else
2814 {
2819 {
2824 }
2827 }
2829 /* Reset the CFA to be SP + 0. */
2832 }
2834 /* Stack adjustment for exception handler. */
2836 {
2837 /* We need to unwind the stack by the offset computed by
2838 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
2839 to be SP; letting the CFA move during this adjustment
2840 is just as correct as retaining the CFA from the body
2841 of the function. Therefore, do nothing special. */
2843 }
2848 }
2850 /* Return the place to copy the exception unwinding return address to.
2851 This will probably be a stack slot, but could (in theory be the
2852 return register). */
2853 rtx
2855 {
2856 HOST_WIDE_INT fp_offset;
2866 /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2. This can
2867 result in a store to save LR introduced by builtin_eh_return () being
2868 incorrectly deleted because the alias is not detected.
2869 So in the calculation of the address to copy the exception unwinding
2870 return address to, we note 2 cases.
2871 If FP is needed and the fp_offset is 0, it means that SP = FP and hence
2872 we return a SP-relative location since all the addresses are SP-relative
2873 in this case. This prevents the store from being optimized away.
2874 If the fp_offset is not 0, then the addresses will be FP-relative and
2875 therefore we return a FP-relative location. */
2878 {
2882 else
2885 }
2887 /* If FP is not needed, we calculate the location of LR, which would be
2888 at the top of the saved registers block. */
2892 stack_pointer_rtx,
2893 fp_offset
2896 }
2898 /* Possibly output code to build up a constant in a register. For
2899 the benefit of the costs infrastructure, returns the number of
2900 instructions which would be emitted. GENERATE inhibits or
2901 enables code generation. */
2903 static int
2905 {
2909 {
2913 }
2914 else
2915 {
2920 HOST_WIDE_INT valm;
2921 HOST_WIDE_INT tval;
2924 {
2934 }
2936 /* zcount contains the number of additional MOVK instructions
2937 required if the constant is built up with an initial MOVZ instruction,
2938 while ncount is the number of MOVK instructions required if starting
2939 with a MOVN instruction. Choose the sequence that yields the fewest
2940 number of instructions, preferring MOVZ instructions when they are both
2941 the same. */
2943 {
2948 insns++;
2949 }
2950 else
2951 {
2956 insns++;
2957 }
2962 {
2964 {
2969 insns++;
2970 }
2972 }
2973 }
2975 }
2977 static void
2979 {
2988 {
2991 }
2993 {
2995 {
3001 else
3004 }
3006 {
3010 }
3011 }
3012 }
3014 /* Output code to add DELTA to the first argument, and then jump
3015 to FUNCTION. Used for C++ multiple inheritance. */
3016 static void
3018 HOST_WIDE_INT delta,
3019 HOST_WIDE_INT vcall_offset,
3020 tree function)
3021 {
3022 /* The this pointer is always in x0. Note that this differs from
3023 Arm where the this pointer maybe bumped to r1 if r0 is required
3024 to return a pointer to an aggregate. On AArch64 a result value
3025 pointer will be in x8. */
3035 else
3036 {
3045 {
3049 else
3051 }
3055 else
3062 else
3063 {
3066 }
3070 else
3076 }
3078 /* Generate a tail call to the target function. */
3080 {
3083 }
3095 /* Stop pretending to be a post-reload pass. */
3097 }
3099 static bool
3101 {
3106 {
3110 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
3111 TLS offsets, not real symbol references. */
3114 }
3116 }
3119 /* Return true if val can be encoded as a 12-bit unsigned immediate with
3120 a left shift of 0 or 12 bits. */
3121 bool
3123 {
3126 );
3127 }
3130 /* Return true if val is an immediate that can be loaded into a
3131 register by a MOVZ instruction. */
3132 static bool
3134 {
3136 {
3140 }
3141 else
3142 {
3143 /* Ignore sign extension. */
3145 }
3148 }
3150 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
3153 {
3159 };
3162 /* Return true if val is a valid bitmask immediate. */
3164 bool
3166 {
3170 /* Check for a single sequence of one bits and return quickly if so.
3171 The special cases of all ones and all zeroes returns false. */
3178 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
3182 /* Invert if the immediate doesn't start with a zero bit - this means we
3183 only need to search for sequences of one bits. */
3187 /* Find the first set bit and set tmp to val with the first sequence of one
3188 bits removed. Return success if there is a single sequence of ones. */
3195 /* Find the next set bit and compute the difference in bit position. */
3200 /* Check the bit position difference is a power of 2, and that the first
3201 sequence of one bits fits within 'bits' bits. */
3205 /* Check the sequence of one bits is repeated 64/bits times. */
3207 }
3210 /* Return true if val is an immediate that can be loaded into a
3211 register in a single instruction. */
3212 bool
3214 {
3218 }
3220 static bool
3222 {
3230 {
3234 else
3235 /* Avoid generating a 64-bit relocation in ILP32; leave
3236 to aarch64_expand_mov_immediate to handle it properly. */
3238 }
3241 }
3243 /* Return true if register REGNO is a valid index register.
3244 STRICT_P is true if REG_OK_STRICT is in effect. */
3246 bool
3248 {
3250 {
3258 }
3260 }
3262 /* Return true if register REGNO is a valid base register for mode MODE.
3263 STRICT_P is true if REG_OK_STRICT is in effect. */
3265 bool
3267 {
3269 {
3277 }
3279 /* The fake registers will be eliminated to either the stack or
3280 hard frame pointer, both of which are usually valid base registers.
3281 Reload deals with the cases where the eliminated form isn't valid. */
3286 }
3288 /* Return true if X is a valid base register for mode MODE.
3289 STRICT_P is true if REG_OK_STRICT is in effect. */
3291 static bool
3293 {
3298 }
3300 /* Return true if address offset is a valid index. If it is, fill in INFO
3301 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
3303 static bool
3306 {
3308 rtx index;
3311 /* (reg:P) */
3314 {
3318 }
3319 /* (sign_extend:DI (reg:SI)) */
3324 {
3329 }
3330 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
3337 {
3342 }
3343 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
3350 {
3355 }
3356 /* (sign_extract:DI (mult:DI (reg:DI) (const_int scale)) 32+shift 0) */
3363 {
3371 }
3372 /* (and:DI (mult:DI (reg:DI) (const_int scale))
3373 (const_int 0xffffffff<<shift)) */
3380 {
3386 }
3387 /* (sign_extract:DI (ashift:DI (reg:DI) (const_int shift)) 32+shift 0) */
3394 {
3402 }
3403 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
3404 (const_int 0xffffffff<<shift)) */
3411 {
3417 }
3418 /* (mult:P (reg:P) (const_int scale)) */
3423 {
3427 }
3428 /* (ashift:P (reg:P) (const_int shift)) */
3433 {
3437 }
3438 else
3449 {
3454 }
3457 }
3459 bool
3461 {
3465 }
3469 HOST_WIDE_INT offset)
3470 {
3472 }
3476 {
3480 }
3482 /* Return true if MODE is one of the modes for which we
3483 support LDP/STP operations. */
3485 static bool
3487 {
3492 }
3494 /* Return true if X is a valid address for machine mode MODE. If it is,
3495 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
3496 effect. OUTER_CODE is PARALLEL for a load/store pair. */
3498 static bool
3502 {
3506 /* On BE, we use load/store pair for all large int mode load/stores. */
3508 || (BYTES_BIG_ENDIAN
3512 !load_store_pair_p
3516 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
3517 REG addressing. */
3523 {
3541 {
3547 }
3552 {
3559 /* TImode and TFmode values are allowed in both pairs of X
3560 registers and individual Q registers. The available
3561 address modes are:
3562 X,X: 7-bit signed scaled offset
3563 Q: 9-bit signed offset
3564 We conservatively require an offset representable in either mode.
3565 */
3570 /* A 7bit offset check because OImode will emit a ldp/stp
3571 instruction (only big endian will get here).
3572 For ldp/stp instructions, the offset is scaled for the size of a
3573 single element of the pair. */
3577 /* Three 9/12 bit offsets checks because CImode will emit three
3578 ldr/str instructions (only big endian will get here). */
3585 /* Two 7bit offsets checks because XImode will emit two ldp/stp
3586 instructions (only big endian will get here). */
3595 else
3598 }
3601 {
3602 /* Look for base + (scaled/extended) index register. */
3605 {
3608 }
3611 {
3614 }
3615 }
3636 {
3637 HOST_WIDE_INT offset;
3641 /* TImode and TFmode values are allowed in both pairs of X
3642 registers and individual Q registers. The available
3643 address modes are:
3644 X,X: 7-bit signed scaled offset
3645 Q: 9-bit signed offset
3646 We conservatively require an offset representable in either mode.
3647 */
3655 else
3657 }
3663 /* load literal: pc-relative constant pool entry. Only supported
3664 for SI mode or larger. */
3668 {
3676 }
3685 {
3690 {
3691 /* The symbol and offset must be aligned to the access size. */
3698 {
3702 }
3708 else
3717 }
3718 }
3723 }
3724 }
3726 bool
3728 {
3729 rtx offset;
3733 }
3735 /* Classify the base of symbolic expression X. */
3737 enum aarch64_symbol_type
3739 {
3740 rtx offset;
3744 }
3747 /* Return TRUE if X is a legitimate address for accessing memory in
3748 mode MODE. */
3749 static bool
3751 {
3755 }
3757 /* Return TRUE if X is a legitimate address for accessing memory in
3758 mode MODE. OUTER_CODE will be PARALLEL if this is a load/store
3759 pair operation. */
3760 bool
3763 {
3767 }
3769 /* Return TRUE if rtx X is immediate constant 0.0 */
3770 bool
3772 {
3779 }
3781 /* Return the fixed registers used for condition codes. */
3783 static bool
3785 {
3789 }
3791 /* Emit call insn with PAT and do aarch64-specific handling. */
3793 void
3795 {
3801 }
3803 machine_mode
3805 {
3806 /* All floating point compares return CCFP if it is an equality
3807 comparison, and CCFPE otherwise. */
3809 {
3811 {
3832 }
3833 }
3842 /* A compare with a shifted operand. Because of canonicalization,
3843 the comparison will have to be swapped when we emit the assembly
3844 code. */
3852 /* Similarly for a negated operand, but we can only do this for
3853 equalities. */
3860 /* A compare of a mode narrower than SI mode against zero can be done
3861 by extending the value in the comparison. */
3864 /* Only use sign-extension if we really need it. */
3868 /* For everything else, return CCmode. */
3870 }
3872 static int
3875 int
3877 {
3884 }
3886 static int
3888 {
3891 {
3895 {
3909 }
3964 {
3976 }
3983 {
3995 }
4000 {
4006 }
4011 {
4015 }
4021 }
4030 }
4032 bool
4034 HOST_WIDE_INT minval,
4035 HOST_WIDE_INT maxval)
4036 {
4037 HOST_WIDE_INT firstval;
4054 }
4056 bool
4058 {
4060 }
4063 /* N Z C V. */
4064 #define AARCH64_CC_V 1
4065 #define AARCH64_CC_C (1 << 1)
4066 #define AARCH64_CC_Z (1 << 2)
4067 #define AARCH64_CC_N (1 << 3)
4069 /* N Z C V flags for ccmp. The first code is for AND op and the other
4070 is for IOR op. Indexed by AARCH64_COND_CODE. */
4072 {
4089 };
4091 int
4093 {
4095 {
4128 }
4129 }
4132 static void
4134 {
4136 {
4137 /* An integer or symbol address without a preceding # sign. */
4140 {
4152 {
4155 }
4156 /* Fall through. */
4160 }
4164 /* Print the sign/zero-extend size as a character 8->b, 16->h, 32->w. */
4165 {
4170 {
4173 }
4176 {
4189 }
4190 }
4194 {
4197 /* Print N such that 2^N == X. */
4199 {
4202 }
4205 }
4209 /* Print the number of non-zero bits in X (a const_int). */
4211 {
4214 }
4220 /* Print the higher numbered register of a pair (TImode) of regs. */
4222 {
4225 }
4231 {
4233 /* Print a condition (eq, ne, etc). */
4235 /* CONST_TRUE_RTX means always -- that's the default. */
4240 {
4243 }
4248 }
4252 {
4254 /* Print the inverse of a condition (eq <-> ne, etc). */
4256 /* CONST_TRUE_RTX means never -- that's the default. */
4258 {
4261 }
4264 {
4267 }
4272 }
4280 /* Print a scalar FP/SIMD register name. */
4282 {
4283 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4285 }
4293 /* Print the first FP/SIMD register name in a list. */
4295 {
4296 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4298 }
4303 /* Print a scalar FP/SIMD register name + 1. */
4305 {
4306 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
4308 }
4313 /* Print bottom 16 bits of integer constant in hex. */
4315 {
4318 }
4324 /* Print a general register name or the zero register (32-bit or
4325 64-bit). */
4328 {
4331 }
4334 {
4337 }
4340 {
4343 }
4345 /* Fall through */
4348 /* Print a normal operand, if it's a general register, then we
4349 assume DImode. */
4351 {
4354 }
4357 {
4378 {
4381 HOST_WIDE_INT_MIN,
4382 HOST_WIDE_INT_MAX));
4384 }
4386 {
4388 }
4389 else
4394 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
4395 be getting CONST_DOUBLEs holding integers. */
4398 {
4401 }
4403 {
4404 #define buf_size 20
4412 #undef buf_size
4413 }
4419 }
4427 {
4454 }
4460 {
4495 }
4502 {
4508 }
4513 {
4515 /* Print nzcv. */
4518 {
4521 }
4526 }
4530 {
4532 /* Print nzcv. */
4535 {
4538 }
4543 }
4549 }
4550 }
4552 static void
4554 {
4559 {
4563 else
4572 else
4581 else
4590 else
4597 {
4624 }
4635 }
4638 }
4640 bool
4642 {
4649 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
4650 referencing instruction, but they are constant offsets, not
4651 symbols. */
4657 {
4659 {
4665 }
4668 }
4671 }
4673 /* Implement REGNO_REG_CLASS. */
4675 enum reg_class
4677 {
4692 }
4694 static rtx
4696 {
4697 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
4698 where mask is selected by alignment and size of the offset.
4699 We try to pick as large a range for the offset as possible to
4700 maximize the chance of a CSE. However, for aligned addresses
4701 we limit the range to 4k so that structures with different sized
4702 elements are likely to use the same base. */
4705 {
4707 HOST_WIDE_INT base_offset;
4709 /* Does it look like we'll need a load/store-pair operation? */
4714 /* For offsets aren't a multiple of the access size, the limit is
4715 -256...255. */
4718 else
4727 NULL_RTX);
4730 }
4733 }
4735 /* Try a machine-dependent way of reloading an illegitimate address
4736 operand. If we find one, push the reload and return the new rtx. */
4738 rtx
4740 machine_mode mode,
4743 {
4746 /* Do not allow mem (plus (reg, const)) if vector struct mode. */
4751 {
4758 }
4760 /* We must recognize output that we have already generated ourselves. */
4766 {
4771 }
4773 /* We wish to handle large displacements off a base register by splitting
4774 the addend across an add and the mem insn. This can cut the number of
4775 extra insns needed from 3 to 1. It is only useful for load/store of a
4776 single register with 12 bit offset field. */
4784 {
4788 HOST_WIDE_INT offs;
4789 rtx cst;
4792 /* In ILP32, xmode can be either DImode or SImode. */
4795 /* Reload non-zero BLKmode offsets. This is because we cannot ascertain
4796 BLKmode alignment. */
4802 /* Align misaligned offset by adjusting high part to compensate. */
4804 {
4806 {
4807 /* Align down. */
4810 }
4811 else
4812 {
4813 /* Align up. */
4818 }
4819 }
4821 /* Check for overflow. */
4829 /* Reload high part into base reg, leaving the low part
4830 in the mem instruction.
4831 Note that replacing this gen_rtx_PLUS with plus_constant is
4832 wrong in this case because we rely on the
4833 (plus (plus reg c1) c2) structure being preserved so that
4834 XEXP (*p, 0) in push_reload below uses the correct term. */
4843 }
4846 }
4849 /* Return the reload icode required for a constant pool in mode. */
4850 static enum insn_code
4852 {
4854 {
4890 }
4893 }
4894 static reg_class_t
4896 reg_class_t rclass,
4897 machine_mode mode,
4899 {
4901 /* If we have to disable direct literal pool loads and stores because the
4902 function is too big, then we need a scratch register. */
4907 {
4910 }
4912 /* Without the TARGET_SIMD instructions we cannot move a Q register
4913 to a Q register directly. We need a scratch. */
4917 {
4923 }
4925 /* A TFmode or TImode memory access should be handled via an FP_REGS
4926 because AArch64 has richer addressing modes for LDR/STR instructions
4927 than LDP/STP instructions. */
4936 }
4938 static bool
4940 {
4941 /* If we need a frame pointer, we must eliminate FRAME_POINTER_REGNUM into
4942 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
4945 {
4957 }
4958 else
4959 {
4960 /* If we decided that we didn't need a leaf frame pointer but then used
4961 LR in the function, then we'll want a frame pointer after all, so
4962 prevent this elimination to ensure a frame pointer is used. */
4964 && flag_omit_leaf_frame_pointer
4967 }
4970 }
4972 HOST_WIDE_INT
4974 {
4978 {
4985 }
4988 {
4992 }
4995 }
4997 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
4998 previous frame. */
5000 rtx
5002 {
5006 }
5009 static void
5011 {
5013 {
5016 }
5017 else
5018 {
5021 }
5026 }
5028 static void
5030 {
5034 /* Don't need to copy the trailing D-words, we fill those in below. */
5046 /* XXX We should really define a "clear_cache" pattern and use
5047 gen_clear_cache(). */
5052 ptr_mode);
5053 }
5055 static unsigned char
5057 {
5059 {
5066 return
5078 }
5080 }
5082 static reg_class_t
5084 {
5089 {
5095 }
5097 /* If it's an integer immediate that MOVI can't handle, then
5098 FP_REGS is not an option, so we return NO_REGS instead. */
5103 /* Register eliminiation can result in a request for
5104 SP+constant->FP_REGS. We cannot support such operations which
5105 use SP as source and an FP_REG as destination, so reject out
5106 right now. */
5108 {
5111 /* Look through a possible SUBREG introduced by ILP32. */
5117 POINTER_REGS));
5119 }
5122 }
5124 void
5126 {
5128 }
5130 static void
5132 {
5135 else
5136 {
5144 }
5145 }
5147 static void
5149 {
5152 else
5153 {
5161 }
5162 }
5166 {
5172 {
5173 {
5176 },
5177 {
5180 },
5181 {
5184 },
5185 /* We assume that DImode is only generated when not optimizing and
5186 that we don't really need 64-bit address offsets. That would
5187 imply an object file with 8GB of code in a single function! */
5188 {
5191 }
5192 };
5200 /* Need to implement table size reduction, by chaning the code below. */
5210 }
5213 /* Return size in bits of an arithmetic operand which is shifted/scaled and
5214 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
5215 operator. */
5217 int
5219 {
5221 {
5224 {
5228 }
5229 }
5231 }
5233 /* Constant pools are per function only when PC relative
5234 literal loads are true or we are in the large memory
5235 model. */
5239 {
5242 }
5244 static bool
5246 {
5247 /* We can't use blocks for constants when we're using a per-function
5248 constant pool. */
5250 }
5252 /* Select appropriate section for constants depending
5253 on where we place literal pools. */
5257 rtx x,
5259 {
5264 }
5266 /* Costs. */
5268 /* Helper function for rtx cost calculation. Strip a shift expression
5269 from X. Returns the inner operand if successful, or the original
5270 expression on failure. */
5271 static rtx
5273 {
5276 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
5277 we can convert both to ROR during final output. */
5292 }
5294 /* Helper function for rtx cost calculation. Strip an extend
5295 expression from X. Returns the inner operand if successful, or the
5296 original expression on failure. We deal with a number of possible
5297 canonicalization variations here. */
5298 static rtx
5300 {
5303 /* Zero and sign extraction of a widened value. */
5311 /* It can also be represented (for zero-extend) as an AND with an
5312 immediate. */
5321 /* Now handle extended register, as this may also have an optional
5322 left shift by 1..4. */
5336 }
5338 /* Return true iff CODE is a shift supported in combination
5339 with arithmetic instructions. */
5341 static bool
5343 {
5345 }
5347 /* Helper function for rtx cost calculation. Calculate the cost of
5348 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
5349 Return the calculated cost of the expression, recursing manually in to
5350 operands where needed. */
5352 static int
5354 {
5370 /* Integer multiply/fma. */
5372 {
5373 /* The multiply will be canonicalized as a shift, cost it as such. */
5377 {
5381 {
5383 {
5385 /* ARITH + shift-by-register. */
5388 /* ARITH + extended register. We don't have a cost field
5389 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
5391 else
5392 /* ARITH + shift-by-immediate. */
5394 }
5395 else
5396 /* LSL (immediate). */
5399 }
5400 /* Strip extends as we will have costed them in the case above. */
5407 }
5409 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
5410 compound and let the below cases handle it. After all, MNEG is a
5411 special-case alias of MSUB. */
5413 {
5416 }
5418 /* Integer multiplies or FMAs have zero/sign extending variants. */
5423 {
5428 {
5430 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
5432 else
5433 /* MUL/SMULL/UMULL. */
5435 }
5438 }
5440 /* This is either an integer multiply or a MADD. In both cases
5441 we want to recurse and cost the operands. */
5446 {
5448 /* MADD/MSUB. */
5450 else
5451 /* MUL. */
5453 }
5456 }
5457 else
5458 {
5460 {
5461 /* Floating-point FMA/FMUL can also support negations of the
5462 operands, unless the rounding mode is upward or downward in
5463 which case FNMUL is different than FMUL with operand negation. */
5467 {
5472 }
5475 /* FMADD/FNMADD/FNMSUB/FMSUB. */
5477 else
5478 /* FMUL/FNMUL. */
5480 }
5485 }
5486 }
5488 static int
5490 machine_mode mode,
5491 addr_space_t as ATTRIBUTE_UNUSED,
5493 {
5501 {
5503 {
5504 /* This is a CONST or SYMBOL ref which will be split
5505 in a different way depending on the code model in use.
5506 Cost it through the generic infrastructure. */
5508 /* Divide through by the cost of one instruction to
5509 bring it to the same units as the address costs. */
5511 /* The cost is then the cost of preparing the address,
5512 followed by an immediate (possibly 0) offset. */
5514 }
5515 else
5516 {
5517 /* This is most likely a jump table from a case
5518 statement. */
5520 }
5521 }
5524 {
5536 else
5555 }
5559 {
5560 /* For the sake of calculating the cost of the shifted register
5561 component, we can treat same sized modes in the same way. */
5563 {
5576 /* We can't tell, or this is a 128-bit vector. */
5580 }
5581 }
5584 }
5586 /* Return the cost of a branch. If SPEED_P is true then the compiler is
5587 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
5588 to be taken. */
5590 int
5592 {
5593 /* When optimizing for speed, use the cost of unpredictable branches. */
5599 else
5601 }
5603 /* Return true if the RTX X in mode MODE is a zero or sign extract
5604 usable in an ADD or SUB (extended register) instruction. */
5605 static bool
5607 {
5608 /* Catch add with a sign extract.
5609 This is add_<optab><mode>_multp2. */
5612 {
5623 op1))
5624 {
5626 }
5627 }
5628 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
5629 No shift. */
5635 }
5637 static bool
5639 {
5641 {
5653 }
5654 }
5656 /* Return true iff X is an rtx that will match an extr instruction
5657 i.e. as described in the *extr<mode>5_insn family of patterns.
5658 OP0 and OP1 will be set to the operands of the shifts involved
5659 on success and will be NULL_RTX otherwise. */
5661 static bool
5663 {
5678 {
5679 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
5691 {
5695 }
5696 }
5699 }
5701 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
5702 storing it in *COST. Result is true if the total cost of the operation
5703 has now been calculated. */
5704 static bool
5706 {
5707 rtx inner;
5708 rtx comparator;
5712 {
5716 }
5717 else
5718 {
5722 }
5725 {
5726 /* Conditional branch. */
5729 else
5730 {
5732 {
5734 {
5735 /* TBZ/TBNZ/CBZ/CBNZ. */
5737 /* TBZ/TBNZ. */
5740 else
5741 /* CBZ/CBNZ. */
5745 }
5746 }
5748 {
5749 /* TBZ/TBNZ. */
5752 }
5753 }
5754 }
5756 {
5757 /* It's a conditional operation based on the status flags,
5758 so it must be some flavor of CSEL. */
5760 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
5769 }
5771 /* We don't know what this is, cost all operands. */
5773 }
5775 /* Calculate the cost of calculating X, storing it in *COST. Result
5776 is true if the total cost of the operation has now been calculated. */
5777 static bool
5780 {
5786 /* By default, assume that everything has equivalent cost to the
5787 cheapest instruction. Any additional costs are applied as a delta
5788 above this default. */
5792 {
5794 /* The cost depends entirely on the operands to SET. */
5800 {
5803 {
5817 }
5826 /* Fall through. */
5828 /* The cost is one per vector-register copied. */
5830 {
5834 }
5835 /* const0_rtx is in general free, but we will use an
5836 instruction to set a register to 0. */
5838 {
5839 /* The cost is 1 per register copied. */
5843 }
5844 else
5845 /* Cost is just the cost of the RHS of the set. */
5851 /* Bit-field insertion. Strip any redundant widening of
5852 the RHS to meet the width of the target. */
5863 {
5864 /* MOV immediate is assumed to always be cheap. */
5866 }
5867 else
5868 {
5869 /* BFM. */
5873 }
5878 /* We can't make sense of this, assume default cost. */
5881 }
5885 /* If an instruction can incorporate a constant within the
5886 instruction, the instruction's expression avoids calling
5887 rtx_cost() on the constant. If rtx_cost() is called on a
5888 constant, then it is usually because the constant must be
5889 moved into a register by one or more instructions.
5891 The exception is constant 0, which can be expressed
5892 as XZR/WZR and is therefore free. The exception to this is
5893 if we have (set (reg) (const0_rtx)) in which case we must cost
5894 the move. However, we can catch that when we cost the SET, so
5895 we don't need to consider that here. */
5898 else
5899 {
5900 /* To an approximation, building any other constant is
5901 proportionally expensive to the number of instructions
5902 required to build that constant. This is true whether we
5903 are compiling for SPEED or otherwise. */
5906 }
5911 {
5912 /* mov[df,sf]_aarch64. */
5914 /* FMOV (scalar immediate). */
5917 {
5918 /* This will be a load from memory. */
5921 else
5923 }
5924 else
5925 /* Otherwise this is +0.0. We get this using MOVI d0, #0
5926 or MOV v0.s[0], wzr - neither of which are modeled by the
5927 cost tables. Just use the default cost. */
5928 {
5929 }
5930 }
5936 {
5937 /* For loads we want the base cost of a load, plus an
5938 approximation for the additional cost of the addressing
5939 mode. */
5953 }
5961 {
5963 {
5964 /* FNEG. */
5966 }
5968 }
5971 {
5974 {
5975 /* CSETM. */
5978 }
5980 /* Cost this as SUB wzr, X. */
5984 }
5987 {
5988 /* Support (neg(fma...)) as a single instruction only if
5989 sign of zeros is unimportant. This matches the decision
5990 making in aarch64.md. */
5992 {
5993 /* FNMADD. */
5996 }
5998 {
5999 /* FNMUL. */
6002 }
6004 /* FNEG. */
6007 }
6014 {
6017 else
6019 }
6029 {
6033 }
6036 {
6037 /* TODO: A write to the CC flags possibly costs extra, this
6038 needs encoding in the cost tables. */
6040 /* CC_ZESWPmode supports zero extend for free. */
6045 /* ANDS. */
6047 {
6050 }
6053 {
6054 /* ADDS (and CMN alias). */
6057 }
6060 {
6061 /* SUBS. */
6064 }
6067 {
6068 /* CMN. */
6075 }
6077 /* CMP.
6079 Compare can freely swap the order of operands, and
6080 canonicalization puts the more complex operation first.
6081 But the integer MINUS logic expects the shift/extend
6082 operation in op1. */
6085 {
6088 }
6090 }
6093 {
6094 /* FCMP. */
6099 {
6101 /* FCMP supports constant 0.0 for no extra cost. */
6103 }
6105 }
6108 {
6109 /* Vector compare. */
6114 {
6115 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
6116 cost. */
6118 }
6120 }
6124 {
6128 cost_minus:
6131 /* Detect valid immediates. */
6137 {
6139 /* SUB(S) (immediate). */
6142 }
6144 /* Look for SUB (extended register). */
6146 {
6154 }
6158 /* Cost this as an FMA-alike operation. */
6162 {
6165 speed);
6167 }
6172 {
6174 {
6175 /* Vector SUB. */
6177 }
6179 {
6180 /* SUB(S). */
6182 }
6184 {
6185 /* FSUB. */
6187 }
6188 }
6190 }
6193 {
6194 rtx new_op0;
6199 cost_plus:
6202 {
6203 /* CSINC. */
6207 }
6212 {
6216 /* ADD (immediate). */
6219 }
6223 /* Look for ADD (extended register). */
6225 {
6233 }
6235 /* Strip any extend, leave shifts behind as we will
6236 cost them through mult_cost. */
6241 {
6243 speed);
6245 }
6250 {
6252 {
6253 /* Vector ADD. */
6255 }
6257 {
6258 /* ADD. */
6260 }
6262 {
6263 /* FADD. */
6265 }
6266 }
6268 }
6274 {
6277 else
6279 }
6284 {
6288 {
6291 else
6293 }
6295 }
6298 {
6305 }
6306 /* Fall through. */
6309 cost_logic:
6314 {
6318 }
6326 {
6327 /* This is a UBFM/SBFM. */
6332 }
6335 {
6336 /* We possibly get the immediate for free, this is not
6337 modelled. */
6340 {
6347 }
6348 else
6349 {
6352 /* Handle ORN, EON, or BIC. */
6358 /* If we had a shift on op0 then this is a logical-shift-
6359 by-register/immediate operation. Otherwise, this is just
6360 a logical operation. */
6362 {
6364 {
6365 /* Shift by immediate. */
6368 else
6370 }
6371 else
6373 }
6375 /* In both cases we want to cost both operands. */
6380 }
6381 }
6389 {
6390 /* Vector NOT. */
6393 }
6395 /* MVN-shifted-reg. */
6397 {
6404 }
6405 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
6406 Handle the second form here taking care that 'a' in the above can
6407 be a shift. */
6409 {
6418 {
6421 else
6423 }
6426 }
6427 /* MVN. */
6436 /* If a value is written in SI mode, then zero extended to DI
6437 mode, the operation will in general be free as a write to
6438 a 'w' register implicitly zeroes the upper bits of an 'x'
6439 register. However, if this is
6441 (set (reg) (zero_extend (reg)))
6443 we must cost the explicit register move. */
6447 {
6451 /* MOV. */
6453 else
6454 /* Free, the cost is that of the SI mode operation. */
6458 }
6460 {
6461 /* All loads can zero extend to any size for free. */
6464 }
6467 {
6469 {
6470 /* UMOV. */
6472 }
6473 else
6474 {
6475 /* UXTB/UXTH. */
6477 }
6478 }
6483 {
6484 /* LDRSH. */
6486 {
6493 }
6495 }
6498 {
6501 else
6503 }
6511 {
6513 {
6515 {
6516 /* Vector shift (immediate). */
6518 }
6519 else
6520 {
6521 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
6522 aliases. */
6524 }
6525 }
6527 /* We can incorporate zero/sign extend for free. */
6534 }
6535 else
6536 {
6538 {
6540 {
6541 /* Vector shift (register). */
6543 }
6544 else
6545 {
6546 /* LSLV. */
6548 }
6549 }
6551 }
6561 {
6562 /* ASR (immediate) and friends. */
6564 {
6567 else
6569 }
6573 }
6574 else
6575 {
6577 /* ASR (register) and friends. */
6579 {
6582 else
6584 }
6586 }
6592 {
6593 /* LDR. */
6596 }
6599 {
6600 /* ADRP, followed by ADD. */
6604 }
6607 {
6608 /* ADR. */
6611 }
6614 {
6615 /* One extra load instruction, after accessing the GOT. */
6619 }
6624 /* ADRP/ADD (immediate). */
6631 /* UBFX/SBFX. */
6633 {
6636 else
6638 }
6640 /* We can trust that the immediates used will be correct (there
6641 are no by-register forms), so we need only cost op0. */
6647 /* aarch64_rtx_mult_cost always handles recursion to its
6648 operands. */
6652 /* We can expand signed mod by power of 2 using a NEGS, two parallel
6653 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
6654 an unconditional negate. This case should only ever be reached through
6655 the set_smod_pow2_cheap check in expmed.c. */
6659 {
6660 /* We expand to 4 instructions. Reset the baseline. */
6668 }
6670 /* Fall-through. */
6673 {
6685 }
6692 {
6696 /* There is no integer SQRT, so only DIV and UDIV can get
6697 here. */
6699 else
6701 }
6727 {
6730 else
6732 }
6734 /* FMSUB, FNMADD, and FNMSUB are free. */
6741 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
6742 and the by-element operand as operand 0. */
6746 /* Catch vector-by-element operations. The by-element operand can
6747 either be (vec_duplicate (vec_select (x))) or just
6748 (vec_select (x)), depending on whether we are multiplying by
6749 a vector or a scalar.
6751 Canonicalization is not very good in these cases, FMA4 will put the
6752 by-element operand as operand 0, FNMA4 will have it as operand 1. */
6763 /* If the remaining parameters are not registers,
6764 get the cost to put them into registers. */
6778 {
6780 {
6781 /*Vector truncate. */
6783 }
6784 else
6786 }
6791 {
6793 {
6794 /*Vector conversion. */
6796 }
6797 else
6799 }
6805 /* Strip the rounding part. They will all be implemented
6806 by the fcvt* family of instructions anyway. */
6808 {
6817 }
6820 {
6823 else
6825 }
6827 /* We can combine fmul by a power of 2 followed by a fcvt into a single
6828 fixed-point fcvt. */
6833 {
6837 }
6844 {
6845 /* ABS (vector). */
6848 }
6850 {
6853 /* FABD, which is analogous to FADD. */
6855 {
6862 }
6863 /* Simple FABS is analogous to FNEG. */
6866 }
6867 else
6868 {
6869 /* Integer ABS will either be split to
6870 two arithmetic instructions, or will be an ABS
6871 (scalar), which we don't model. */
6875 }
6881 {
6884 else
6885 {
6886 /* FMAXNM/FMINNM/FMAX/FMIN.
6887 TODO: This may not be accurate for all implementations, but
6888 we do not model this in the cost tables. */
6890 }
6891 }
6895 /* The floating point round to integer frint* instructions. */
6897 {
6902 }
6905 {
6910 }
6915 /* Decompose <su>muldi3_highpart. */
6917 mode == DImode
6918 /* (lshiftrt:TI */
6921 /* (mult:TI */
6923 /* (ANY_EXTEND:TI (reg:DI))
6924 (ANY_EXTEND:TI (reg:DI))) */
6931 /* (const_int 64) */
6934 {
6935 /* UMULH/SMULH. */
6943 }
6945 /* Fall through. */
6948 }
6955 }
6957 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
6958 calculated for X. This cost is stored in *COST. Returns true
6959 if the total cost of X was calculated. */
6960 static bool
6963 {
6967 {
6972 }
6975 }
6977 static int
6980 {
6986 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
6993 /* Moving between GPR and stack cost is the same as GP2GP. */
6998 /* To/From the stack register, we move via the gprs. */
7004 {
7005 /* 128-bit operations on general registers require 2 instructions. */
7013 /* When AdvSIMD instructions are disabled it is not possible to move
7014 a 128-bit value directly between Q registers. This is handled in
7015 secondary reload. A general register is used as a scratch to move
7016 the upper DI value and the lower DI value is moved directly,
7017 hence the cost is the sum of three moves. */
7022 }
7032 }
7034 static int
7036 reg_class_t rclass ATTRIBUTE_UNUSED,
7038 {
7040 }
7042 /* Function to decide when to use
7043 reciprocal square root builtins. */
7045 static tree
7049 {
7051 || !flag_unsafe_math_optimizations
7052 || optimize_size
7055 {
7057 }
7060 }
7064 /* Select reciprocal square root initial estimate
7065 insn depending on machine mode. */
7067 rsqrte_type
7069 {
7071 {
7078 }
7079 }
7083 /* Select reciprocal square root Newton-Raphson step
7084 insn depending on machine mode. */
7086 rsqrts_type
7088 {
7090 {
7097 }
7098 }
7100 /* Emit instruction sequence to compute
7101 reciprocal square root. Use two Newton-Raphson steps
7102 for single precision and three for double precision. */
7104 void
7106 {
7123 iterations--;
7126 {
7136 }
7139 }
7141 /* Return the number of instructions that can be issued per cycle. */
7142 static int
7144 {
7146 }
7148 static int
7150 {
7154 }
7157 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
7158 autopref_multipass_dfa_lookahead_guard from haifa-sched.c. It only
7159 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
7161 static int
7164 {
7166 }
7169 /* Vectorizer cost model target hooks. */
7171 /* Implement targetm.vectorize.builtin_vectorization_cost. */
7172 static int
7174 tree vectype,
7176 {
7180 {
7227 }
7228 }
7230 /* Implement targetm.vectorize.add_stmt_cost. */
7231 static unsigned
7235 {
7240 {
7245 /* Statements in an inner loop relative to the loop being
7246 vectorized are weighted more heavily. The value here is
7247 arbitrary and could potentially be improved with analysis. */
7253 }
7256 }
7260 /* Enum describing the various ways that the
7261 aarch64_parse_{arch,tune,cpu,extension} functions can fail.
7262 This way their callers can choose what kind of error to give. */
7264 enum aarch64_parse_opt_result
7265 {
7269 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
7270 };
7272 /* Parse the architecture extension string STR and update ISA_FLAGS
7273 with the architecture features turned on or off. Return a
7274 aarch64_parse_opt_result describing the result. */
7276 static enum aarch64_parse_opt_result
7278 {
7279 /* The extension string is parsed left to right. */
7282 /* Flag to say whether we are adding or removing an extension. */
7286 {
7290 str++;
7295 else
7299 {
7303 }
7311 /* Scan over the extensions table trying to find an exact match. */
7313 {
7315 {
7316 /* Add or remove the extension. */
7319 else
7322 }
7323 }
7326 {
7327 /* Extension not found in list. */
7329 }
7332 };
7335 }
7337 /* Parse the TO_PARSE string and put the architecture struct that it
7338 selects into RES and the architectural features into ISA_FLAGS.
7339 Return an aarch64_parse_opt_result describing the parse result.
7340 If there is an error parsing, RES and ISA_FLAGS are left unchanged. */
7342 static enum aarch64_parse_opt_result
7345 {
7357 else
7364 /* Loop through the list of supported ARCHes to find a match. */
7366 {
7368 {
7372 {
7373 /* TO_PARSE string contains at least one extension. */
7374 enum aarch64_parse_opt_result ext_res
7379 }
7380 /* Extension parsing was successful. Confirm the result
7381 arch and ISA flags. */
7385 }
7386 }
7388 /* ARCH name not found in list. */
7390 }
7392 /* Parse the TO_PARSE string and put the result tuning in RES and the
7393 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
7394 describing the parse result. If there is an error parsing, RES and
7395 ISA_FLAGS are left unchanged. */
7397 static enum aarch64_parse_opt_result
7400 {
7412 else
7419 /* Loop through the list of supported CPUs to find a match. */
7421 {
7423 {
7428 {
7429 /* TO_PARSE string contains at least one extension. */
7430 enum aarch64_parse_opt_result ext_res
7435 }
7436 /* Extension parsing was successfull. Confirm the result
7437 cpu and ISA flags. */
7441 }
7442 }
7444 /* CPU name not found in list. */
7446 }
7448 /* Parse the TO_PARSE string and put the cpu it selects into RES.
7449 Return an aarch64_parse_opt_result describing the parse result.
7450 If the parsing fails the RES does not change. */
7452 static enum aarch64_parse_opt_result
7454 {
7460 /* Loop through the list of supported CPUs to find a match. */
7462 {
7464 {
7467 }
7468 }
7470 /* CPU name not found in list. */
7472 }
7474 /* Parse TOKEN, which has length LENGTH to see if it is an option
7475 described in FLAG. If it is, return the index bit for that fusion type.
7476 If not, error (printing OPTION_NAME) and return zero. */
7478 static unsigned int
7483 {
7485 {
7489 }
7493 }
7495 /* Parse OPTION which is a comma-separated list of flags to enable.
7496 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
7497 default state we inherit from the CPU tuning structures. OPTION_NAME
7498 gives the top-level option we are parsing in the -moverride string,
7499 for use in error messages. */
7501 static unsigned int
7506 {
7513 {
7516 token_length,
7517 flags,
7518 option_name);
7519 /* If we find "none" (or, for simplicity's sake, an error) anywhere
7520 in the token stream, reset the supported operations. So:
7522 adrp+add.cmp+branch.none.adrp+add
7524 would have the result of turning on only adrp+add fusion. */
7530 }
7532 /* We ended with a comma, print something. */
7534 {
7537 }
7539 /* We still have one more token to parse. */
7542 token_length,
7543 flags,
7544 option_name);
7550 }
7552 /* Support for overriding instruction fusion. */
7554 static void
7557 {
7559 aarch64_fusible_pairs,
7562 }
7564 /* Support for overriding other tuning flags. */
7566 static void
7569 {
7570 tune->extra_tuning_flags
7572 aarch64_tuning_flags,
7575 }
7577 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
7578 we understand. If it is, extract the option string and handoff to
7579 the appropriate function. */
7581 void
7585 {
7591 {
7594 }
7596 /* Get the length of the option name. */
7598 /* Skip the '=' to get to the option string. */
7599 option_part++;
7602 {
7604 {
7607 }
7608 }
7612 }
7614 /* A checking mechanism for the implementation of the tls size. */
7616 static void
7618 {
7623 {
7625 /* Both the default and maximum TLS size allowed under tiny is 1M which
7626 needs two instructions to address, so we clamp the size to 24. */
7631 /* The maximum TLS size allowed under small is 4G. */
7636 /* The maximum TLS size allowed under large is 16E.
7637 FIXME: 16E should be 64bit, we only support 48bit offset now. */
7643 }
7646 }
7648 /* Parse STRING looking for options in the format:
7649 string :: option:string
7650 option :: name=substring
7651 name :: {a-z}
7652 substring :: defined by option. */
7654 static void
7657 {
7668 {
7670 /* Make this substring look like a string. */
7674 }
7676 /* One last option to parse. */
7679 }
7682 static void
7684 {
7690 /* If not optimizing for size, set the default
7691 alignment to what the target wants. */
7693 {
7700 }
7702 /* If nopcrelative_literal_loads is set on the command line, this
7703 implies that the user asked for PC relative literal loads. */
7707 /* If it is not set on the command line, we default to no
7708 pc relative literal loads. */
7712 /* In the tiny memory model it makes no sense
7713 to disallow non PC relative literal pool loads
7714 as many other things will break anyway. */
7719 }
7721 /* 'Unpack' up the internal tuning structs and update the options
7722 in OPTS. The caller must have set up selected_tune and selected_arch
7723 as all the other target-specific codegen decisions are
7724 derived from them. */
7726 void
7728 {
7731 /* Make a copy of the tuning parameters attached to the core, which
7732 we may later overwrite. */
7740 /* This target defaults to strict volatile bitfields. */
7744 /* -mgeneral-regs-only sets a mask in target_flags, make sure that
7745 aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags
7746 in case some code tries reading aarch64_isa_flags directly to check if
7747 FP is available. Reuse the aarch64_parse_extension machinery since it
7748 knows how to disable any other flags that fp implies. */
7750 {
7751 /* aarch64_parse_extension takes char* rather than const char* because
7752 it is usually called from within other parsing functions. */
7755 }
7762 {
7774 }
7776 /* We don't mind passing in global_options_set here as we don't use
7777 the *options_set structs anyway. */
7779 queue_depth,
7784 }
7786 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
7787 specified in STR and throw errors if appropriate. Put the results if
7788 they are valid in RES and ISA_FLAGS. Return whether the option is
7789 valid. */
7791 static bool
7794 {
7795 enum aarch64_parse_opt_result parse_res
7802 {
7814 }
7817 }
7819 /* Validate a command-line -march option. Parse the arch and extensions
7820 (if any) specified in STR and throw errors if appropriate. Put the
7821 results, if they are valid, in RES and ISA_FLAGS. Return whether the
7822 option is valid. */
7824 static bool
7827 {
7828 enum aarch64_parse_opt_result parse_res
7835 {
7847 }
7850 }
7852 /* Validate a command-line -mtune option. Parse the cpu
7853 specified in STR and throw errors if appropriate. Put the
7854 result, if it is valid, in RES. Return whether the option is
7855 valid. */
7857 static bool
7859 {
7860 enum aarch64_parse_opt_result parse_res
7867 {
7876 }
7878 }
7880 /* Return the CPU corresponding to the enum CPU.
7881 If it doesn't specify a cpu, return the default. */
7885 {
7889 /* The & 0x3f is to extract the bottom 6 bits that encode the
7890 default cpu as selected by the --with-cpu GCC configure option
7891 in config.gcc.
7892 ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS
7893 flags mechanism should be reworked to make it more sane. */
7895 }
7897 /* Return the architecture corresponding to the enum ARCH.
7898 If it doesn't specify a valid architecture, return the default. */
7902 {
7909 }
7911 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
7912 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
7913 tuning structs. In particular it must set selected_tune and
7914 aarch64_isa_flags that define the available ISA features and tuning
7915 decisions. It must also set selected_arch as this will be used to
7916 output the .arch asm tags for each function. */
7918 static void
7920 {
7933 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
7934 If either of -march or -mtune is given, they override their
7935 respective component of -mcpu. */
7947 /* If the user did not specify a processor, choose the default
7948 one for them. This will be the CPU set during configuration using
7949 --with-cpu, otherwise it is "generic". */
7951 {
7953 {
7957 }
7958 else
7959 {
7960 /* Get default configure-time CPU. */
7963 }
7967 }
7968 /* If both -mcpu and -march are specified check that they are architecturally
7969 compatible, warn if they're not and prefer the -march ISA flags. */
7971 {
7973 {
7977 }
7982 }
7983 else
7984 {
7985 /* -mcpu but no -march. */
7992 }
7994 /* Set the arch as well as we will need it when outputing
7995 the .arch directive in assembly. */
7997 {
8000 }
8005 #ifndef HAVE_AS_MABI_OPTION
8006 /* The compiler may have been configured with 2.23.* binutils, which does
8007 not have support for ILP32. */
8010 #endif
8012 /* Make sure we properly set up the explicit options. */
8023 /* Save these options as the default ones in case we push and pop them later
8024 while processing functions with potential target attributes. */
8025 target_option_default_node = target_option_current_node
8030 }
8032 /* Implement targetm.override_options_after_change. */
8034 static void
8036 {
8038 }
8042 {
8046 }
8048 void
8050 {
8052 }
8054 /* A checking mechanism for the implementation of the various code models. */
8055 static void
8057 {
8059 {
8061 {
8066 #ifdef HAVE_AS_SMALL_PIC_RELOCS
8068 ? AARCH64_CMODEL_SMALL_PIC
8070 #else
8072 #endif
8080 }
8081 }
8082 else
8084 }
8086 /* Implement TARGET_OPTION_SAVE. */
8088 static void
8090 {
8092 }
8094 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
8095 using the information saved in PTR. */
8097 static void
8099 {
8107 }
8109 /* Implement TARGET_OPTION_PRINT. */
8111 static void
8113 {
8124 }
8128 void
8130 {
8132 }
8134 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
8135 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
8136 of the function, if such exists. This function may be called multiple
8137 times on a single function so use aarch64_previous_fndecl to avoid
8138 setting up identical state. */
8140 static void
8142 {
8143 tree old_tree = (aarch64_previous_fndecl
8147 tree new_tree = (fndecl
8153 {
8156 ;
8159 {
8164 else
8167 }
8170 {
8178 else
8181 }
8182 }
8187 /* If we turned on SIMD make sure that any vector parameters are re-laid out
8188 so that they use proper vector modes. */
8190 {
8193 {
8198 }
8199 }
8200 }
8202 /* Enum describing the various ways we can handle attributes.
8203 In many cases we can reuse the generic option handling machinery. */
8205 enum aarch64_attr_opt_type
8206 {
8210 aarch64_attr_custom /* Attribute requires a custom handling function. */
8211 };
8213 /* All the information needed to handle a target attribute.
8214 NAME is the name of the attribute.
8215 ATTR_TYPE specifies the type of behaviour of the attribute as described
8216 in the definition of enum aarch64_attr_opt_type.
8217 ALLOW_NEG is true if the attribute supports a "no-" form.
8218 HANDLER is the function that takes the attribute string and whether
8219 it is a pragma or attribute and handles the option. It is needed only
8220 when the ATTR_TYPE is aarch64_attr_custom.
8221 OPT_NUM is the enum specifying the option that the attribute modifies.
8222 This is needed for attributes that mirror the behaviour of a command-line
8223 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
8224 aarch64_attr_enum. */
8226 struct aarch64_attribute_info
8227 {
8233 };
8235 /* Handle the ARCH_STR argument to the arch= target attribute.
8236 PRAGMA_OR_ATTR is used in potential error messages. */
8238 static bool
8240 {
8242 enum aarch64_parse_opt_result parse_res
8246 {
8251 }
8254 {
8267 }
8270 }
8272 /* Handle the argument CPU_STR to the cpu= target attribute.
8273 PRAGMA_OR_ATTR is used in potential error messages. */
8275 static bool
8277 {
8279 enum aarch64_parse_opt_result parse_res
8283 {
8291 }
8294 {
8307 }
8310 }
8312 /* Handle the argument STR to the tune= target attribute.
8313 PRAGMA_OR_ATTR is used in potential error messages. */
8315 static bool
8317 {
8319 enum aarch64_parse_opt_result parse_res
8323 {
8328 }
8331 {
8337 }
8340 }
8342 /* Parse an architecture extensions target attribute string specified in STR.
8343 For example "+fp+nosimd". Show any errors if needed. Return TRUE
8344 if successful. Update aarch64_isa_flags to reflect the ISA features
8345 modified.
8346 PRAGMA_OR_ATTR is used in potential error messages. */
8348 static bool
8350 {
8354 /* We allow "+nothing" in the beginning to clear out all architectural
8355 features if the user wants to handpick specific features. */
8357 {
8360 }
8365 {
8368 }
8371 {
8384 }
8387 }
8389 /* The target attributes that we support. On top of these we also support just
8390 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
8391 handled explicitly in aarch64_process_one_target_attr. */
8394 {
8396 OPT_mgeneral_regs_only },
8398 OPT_mfix_cortex_a53_835769 },
8402 OPT_momit_leaf_frame_pointer },
8405 OPT_march_ },
8408 OPT_mtune_ },
8410 };
8412 /* Parse ARG_STR which contains the definition of one target attribute.
8413 Show appropriate errors if any or return true if the attribute is valid.
8414 PRAGMA_OR_ATTR holds the string to use in error messages about whether
8415 we're processing a target attribute or pragma. */
8417 static bool
8419 {
8425 {
8428 }
8433 /* Skip leading whitespace. */
8435 str_to_check++;
8437 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
8438 It is easier to detect and handle it explicitly here rather than going
8439 through the machinery for the rest of the target attributes in this
8440 function. */
8445 {
8448 }
8451 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
8452 and point ARG to "foo". */
8454 {
8456 arg++;
8457 }
8460 {
8461 /* If the names don't match up, or the user has given an argument
8462 to an attribute that doesn't accept one, or didn't give an argument
8463 to an attribute that expects one, fail to match. */
8471 {
8475 }
8477 /* If the name matches but the attribute does not allow "no-" versions
8478 then we can't match. */
8480 {
8484 }
8487 {
8488 /* Has a custom handler registered.
8489 For example, cpu=, arch=, tune=. */
8496 /* Either set or unset a boolean option. */
8498 {
8506 }
8507 /* Set or unset a bit in the target_flags. aarch64_handle_option
8508 should know what mask to apply given the option number. */
8510 {
8512 /* We only need to specify the option number.
8513 aarch64_handle_option will know which mask to apply. */
8519 }
8520 /* Use the option setting machinery to set an option to an enum. */
8522 {
8529 {
8532 global_dc);
8533 }
8534 else
8535 {
8538 }
8540 }
8543 }
8544 }
8547 }
8549 /* Count how many times the character C appears in
8550 NULL-terminated string STR. */
8552 static unsigned int
8554 {
8557 {
8559 res++;
8561 str++;
8562 }
8565 }
8567 /* Parse the tree in ARGS that contains the target attribute information
8568 and update the global target options space. PRAGMA_OR_ATTR is a string
8569 to be used in error messages, specifying whether this is processing
8570 a target attribute or a target pragma. */
8572 bool
8574 {
8576 {
8577 do
8578 {
8581 {
8584 }
8589 }
8590 /* We expect to find a string to parse. */
8598 {
8601 }
8603 /* Used to catch empty spaces between commas i.e.
8604 attribute ((target ("attr1,,attr2"))). */
8607 /* Handle multiple target attributes separated by ','. */
8612 {
8613 num_attrs++;
8615 {
8618 }
8621 }
8624 {
8628 }
8631 }
8633 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
8634 process attribute ((target ("..."))). */
8636 static bool
8638 {
8641 tree old_optimize;
8645 /* If what we're processing is the current pragma string then the
8646 target option node is already stored in target_option_current_node
8647 by aarch64_pragma_target_parse in aarch64-c.c. Use that to avoid
8648 having to re-parse the string. This is especially useful to keep
8649 arm_neon.h compile times down since that header contains a lot
8650 of intrinsics enclosed in pragmas. */
8652 {
8655 }
8661 /* If the function changed the optimization levels as well as setting
8662 target options, start with the optimizations specified. */
8667 /* Save the current target options to restore at the end. */
8670 /* If fndecl already has some target attributes applied to it, unpack
8671 them so that we add this attribute on top of them, rather than
8672 overwriting them. */
8674 {
8680 }
8681 else
8688 /* Set up any additional state. */
8690 {
8692 /* Initialize SIMD builtins if we haven't already.
8693 Set current_target_pragma to NULL for the duration so that
8694 the builtin initialization code doesn't try to tag the functions
8695 being built with the attributes specified by any current pragma, thus
8696 going into an infinite recursion. */
8698 {
8703 }
8705 }
8706 else
8712 {
8717 }
8725 }
8727 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
8728 tri-bool options (yes, no, don't care) and the default value is
8729 DEF, determine whether to reject inlining. */
8731 static bool
8734 {
8735 /* If the callee doesn't care, always allow inlining. */
8739 /* If the caller doesn't care, always allow inlining. */
8743 /* Otherwise, allow inlining if either the callee and caller values
8744 agree, or if the callee is using the default value. */
8746 }
8748 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
8749 to inline CALLEE into CALLER based on target-specific info.
8750 Make sure that the caller and callee have compatible architectural
8751 features. Then go through the other possible target attributes
8752 and see if they can block inlining. Try not to reject always_inline
8753 callees unless they are incompatible architecturally. */
8755 static bool
8757 {
8761 /* If callee has no option attributes, then it is ok to inline. */
8772 /* Callee's ISA flags should be a subset of the caller's. */
8777 /* Allow non-strict aligned functions inlining into strict
8778 aligned ones. */
8788 /* If the architectural features match up and the callee is always_inline
8789 then the other attributes don't matter. */
8801 /* Honour explicit requests to workaround errata. */
8808 /* If the user explicitly specified -momit-leaf-frame-pointer for the
8809 caller and calle and they don't match up, reject inlining. */
8816 /* If the callee has specific tuning overrides, respect them. */
8821 /* If the user specified tuning override strings for the
8822 caller and callee and they don't match up, reject inlining.
8823 We just do a string compare here, we don't analyze the meaning
8824 of the string, as it would be too costly for little gain. */
8832 }
8834 /* Return true if SYMBOL_REF X binds locally. */
8836 static bool
8838 {
8842 }
8844 /* Return true if SYMBOL_REF X is thread local */
8845 static bool
8847 {
8855 }
8857 /* Classify a TLS symbol into one of the TLS kinds. */
8858 enum aarch64_symbol_type
8860 {
8864 {
8871 {
8877 }
8888 else
8897 }
8898 }
8900 /* Return the method that should be used to access SYMBOL_REF or
8901 LABEL_REF X. */
8903 enum aarch64_symbol_type
8905 {
8907 {
8909 {
8924 }
8925 }
8928 {
8930 {
8931 /* This is alright even in PIC code as the constant
8932 pool reference is always PC relative and within
8933 the same translation unit. */
8937 else
8939 }
8945 {
8947 /* When we retreive symbol + offset address, we have to make sure
8948 the offset does not cause overflow of the final address. But
8949 we have no way of knowing the address of symbol at compile time
8950 so we can't accurately say if the distance between the PC and
8951 symbol + offset is outside the addressible range of +/-1M in the
8952 TINY code model. So we rely on images not being greater than
8953 1M and cap the offset at 1M and anything beyond 1M will have to
8954 be loaded using an alternative mechanism. */
8961 /* Same reasoning as the tiny code model, but the offset cap here is
8962 4G. */
8983 }
8984 }
8986 /* By default push everything into the constant pool. */
8988 }
8990 bool
8992 {
8994 }
8996 bool
8998 {
9006 }
9008 /* Return true if X holds either a quarter-precision or
9009 floating-point +0.0 constant. */
9010 static bool
9012 {
9019 /* We only handle moving 0.0 to a TFmode register. */
9024 }
9026 static bool
9028 {
9029 /* Do not allow vector struct mode constants. We could support
9030 0 and -1 easily, but they need support in aarch64-simd.md. */
9034 /* This could probably go away because
9035 we now decompose CONST_INTs according to expand_mov_immediate. */
9046 }
9048 rtx
9050 {
9056 /* Can return in any reg. */
9059 }
9061 /* On AAPCS systems, this is the "struct __va_list". */
9064 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
9065 Return the type to use as __builtin_va_list.
9067 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
9069 struct __va_list
9070 {
9071 void *__stack;
9072 void *__gr_top;
9073 void *__vr_top;
9074 int __gr_offs;
9075 int __vr_offs;
9076 }; */
9078 static tree
9080 {
9081 tree va_list_name;
9084 /* Create the type. */
9086 /* Give it the required name. */
9088 TYPE_DECL,
9090 va_list_type);
9095 /* Create the fields. */
9098 ptr_type_node);
9101 ptr_type_node);
9104 ptr_type_node);
9107 integer_type_node);
9110 integer_type_node);
9130 /* Compute its layout. */
9134 }
9136 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
9137 static void
9139 {
9143 tree t;
9149 gr_save_area_size
9151 vr_save_area_size
9155 {
9158 }
9167 NULL_TREE);
9169 NULL_TREE);
9171 NULL_TREE);
9173 NULL_TREE);
9175 NULL_TREE);
9177 /* Emit code to initialize STACK, which points to the next varargs stack
9178 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
9179 by named arguments. STACK is 8-byte aligned. */
9186 /* Emit code to initialize GRTOP, the top of the GR save area.
9187 virtual_incoming_args_rtx should have been 16 byte aligned. */
9192 /* Emit code to initialize VRTOP, the top of the VR save area.
9193 This address is gr_save_area_bytes below GRTOP, rounded
9194 down to the next 16-byte boundary. */
9204 /* Emit code to initialize GROFF, the offset from GRTOP of the
9205 next GPR argument. */
9210 /* Likewise emit code to initialize VROFF, the offset from FTOP
9211 of the next VR argument. */
9215 }
9217 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
9219 static tree
9222 {
9223 tree addr;
9229 machine_mode mode;
9256 type,
9260 {
9261 /* TYPE passed in fp/simd registers. */
9273 {
9276 }
9279 {
9281 }
9282 }
9283 else
9284 {
9285 /* TYPE passed in general registers. */
9298 {
9300 }
9301 }
9303 /* Get a local temporary for the field value. */
9306 /* Emit code to branch if off >= 0. */
9312 {
9313 /* Emit: offs = (offs + 15) & -16. */
9319 }
9320 else
9323 /* Update ap.__[g|v]r_offs */
9328 /* String up. */
9332 /* [cond2] if (ap.__[g|v]r_offs > 0) */
9337 /* String up: make sure the assignment happens before the use. */
9341 /* Prepare the trees handling the argument that is passed on the stack;
9342 the top level node will store in ON_STACK. */
9345 {
9346 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
9354 }
9355 else
9357 /* Advance ap.__stack */
9365 /* String up roundup and advance. */
9368 /* String up with arg */
9370 /* Big-endianness related address adjustment. */
9373 {
9377 }
9382 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
9392 {
9393 /* type ha; // treat as "struct {ftype field[n];}"
9394 ... [computing offs]
9395 for (i = 0; i <nregs; ++i, offs += 16)
9396 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
9397 return ha; */
9401 /* Declare a local variable. */
9405 /* Establish the base type. */
9407 {
9420 /* The half precision and quad precision are not fully supported yet. Enable
9421 the following code after the support is complete. Need to find the correct
9422 type node for __fp16 *. */
9423 #if 0
9428 #endif
9431 {
9435 }
9439 }
9441 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
9449 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
9451 {
9461 }
9465 }
9475 }
9477 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
9479 static void
9483 {
9485 CUMULATIVE_ARGS local_cum;
9488 /* The caller has advanced CUM up to, but not beyond, the last named
9489 argument. Advance a local copy of CUM past the last "real" named
9490 argument, to find out how many registers are left over. */
9494 /* Found out how many registers we need to save. */
9499 {
9502 }
9505 {
9507 {
9510 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
9518 }
9520 {
9521 /* We can't use move_block_from_reg, because it will use
9522 the wrong mode, storing D regs only. */
9526 /* Set OFF to the offset from virtual_incoming_args_rtx of
9527 the first vector register. The VR save area lies below
9528 the GR one, and is aligned to 16 bytes. */
9534 {
9542 }
9543 }
9544 }
9546 /* We don't save the size into *PRETEND_SIZE because we want to avoid
9547 any complication of having crtl->args.pretend_args_size changed. */
9552 }
9554 static void
9556 {
9559 {
9561 {
9564 }
9565 }
9566 }
9568 /* Walk down the type tree of TYPE counting consecutive base elements.
9569 If *MODEP is VOIDmode, then set it to the first valid floating point
9570 type. If a non-floating point type is found, or if a floating point
9571 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
9572 otherwise return the count in the sub-tree. */
9573 static int
9575 {
9576 machine_mode mode;
9577 HOST_WIDE_INT size;
9580 {
9608 /* Use V2SImode and V4SImode as representatives of all 64-bit
9609 and 128-bit vector types. */
9612 {
9621 }
9626 /* Vector modes are considered to be opaque: two vectors are
9627 equivalent for the purposes of being homogeneous aggregates
9628 if they are the same size. */
9635 {
9639 /* Can't handle incomplete types nor sizes that are not
9640 fixed. */
9647 || !index
9658 /* There must be no padding. */
9663 }
9666 {
9669 tree field;
9671 /* Can't handle incomplete types nor sizes that are not
9672 fixed. */
9678 {
9686 }
9688 /* There must be no padding. */
9693 }
9697 {
9698 /* These aren't very interesting except in a degenerate case. */
9701 tree field;
9703 /* Can't handle incomplete types nor sizes that are not
9704 fixed. */
9710 {
9718 }
9720 /* There must be no padding. */
9725 }
9729 }
9732 }
9734 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
9735 type as described in AAPCS64 \S 4.1.2.
9737 See the comment above aarch64_composite_type_p for the notes on MODE. */
9739 static bool
9741 machine_mode mode)
9742 {
9752 }
9754 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
9755 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
9756 array types. The C99 floating-point complex types are also considered
9757 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
9758 types, which are GCC extensions and out of the scope of AAPCS64, are
9759 treated as composite types here as well.
9761 Note that MODE itself is not sufficient in determining whether a type
9762 is such a composite type or not. This is because
9763 stor-layout.c:compute_record_mode may have already changed the MODE
9764 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
9765 structure with only one field may have its MODE set to the mode of the
9766 field. Also an integer mode whose size matches the size of the
9767 RECORD_TYPE type may be used to substitute the original mode
9768 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
9769 solely relied on. */
9771 static bool
9773 machine_mode mode)
9774 {
9787 }
9789 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
9790 shall be passed or returned in simd/fp register(s) (providing these
9791 parameter passing registers are available).
9793 Upon successful return, *COUNT returns the number of needed registers,
9794 *BASE_MODE returns the mode of the individual register and when IS_HAF
9795 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
9796 floating-point aggregate or a homogeneous short-vector aggregate. */
9798 static bool
9800 const_tree type,
9804 {
9812 {
9815 }
9817 {
9821 }
9823 {
9827 {
9830 }
9831 else
9833 }
9834 else
9839 }
9841 /* Implement TARGET_STRUCT_VALUE_RTX. */
9843 static rtx
9846 {
9848 }
9850 /* Implements target hook vector_mode_supported_p. */
9851 static bool
9853 {
9865 }
9867 /* Return appropriate SIMD container
9868 for MODE within a vector of WIDTH bits. */
9869 static machine_mode
9871 {
9874 {
9877 {
9892 }
9893 else
9895 {
9906 }
9907 }
9909 }
9911 /* Return 128-bit container as the preferred SIMD mode for MODE. */
9912 static machine_mode
9914 {
9916 }
9918 /* Return the bitmask of possible vector sizes for the vectorizer
9919 to iterate over. */
9920 static unsigned int
9922 {
9924 }
9926 /* Implement TARGET_MANGLE_TYPE. */
9930 {
9931 /* The AArch64 ABI documents say that "__va_list" has to be
9932 managled as if it is in the "std" namespace. */
9936 /* Half-precision float. */
9940 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
9941 builtin types. */
9945 /* Use the default mangling. */
9947 }
9950 /* Return true if the rtx_insn contains a MEM RTX somewhere
9951 in it. */
9953 static bool
9955 {
9962 }
9964 /* Find the first rtx_insn before insn that will generate an assembly
9965 instruction. */
9969 {
9973 do
9974 {
9976 }
9980 }
9982 static bool
9984 {
9986 /* A number of these may be AArch32 only. */
9991 };
9994 {
9997 }
10000 }
10002 /* Check if there is a register dependency between a load and the insn
10003 for which we hold recog_data. */
10005 static bool
10007 {
10008 rtx load_reg;
10018 {
10024 }
10026 }
10029 /* When working around the Cortex-A53 erratum 835769,
10030 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
10031 instruction and has a preceding memory instruction such that a NOP
10032 should be inserted between them. */
10034 bool
10036 {
10039 rtx body;
10052 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
10053 Restore recog state to INSN to avoid state corruption. */
10061 /* If the previous insn is a memory op and there is no dependency between
10062 it and the DImode madd, emit a NOP between them. If body is NULL then we
10063 have a complex memory operation, probably a load/store pair.
10064 Be conservative for now and emit a NOP. */
10071 }
10074 /* Implement FINAL_PRESCAN_INSN. */
10076 void
10078 {
10081 }
10084 /* Return the equivalent letter for size. */
10085 static char
10087 {
10089 {
10095 }
10096 }
10098 /* Return true iff x is a uniform vector of floating-point
10099 constants, and the constant can be represented in
10100 quarter-precision form. Note, as aarch64_float_const_representable
10101 rejects both +0.0 and -0.0, we will also reject +0.0 and -0.0. */
10102 static bool
10104 {
10105 rtx elt;
10109 }
10111 /* Return true for valid and false for invalid. */
10112 bool
10115 {
10116 #define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
10117 matches = 1; \
10118 for (i = 0; i < idx; i += (STRIDE)) \
10119 if (!(TEST)) \
10120 matches = 0; \
10121 if (matches) \
10122 { \
10123 immtype = (CLASS); \
10124 elsize = (ELSIZE); \
10125 eshift = (SHIFT); \
10126 emvn = (NEG); \
10127 break; \
10128 }
10138 {
10144 {
10149 }
10152 }
10154 /* Splat vector constant out into a byte vector. */
10156 {
10157 /* The vector is provided in gcc endian-neutral fashion. For aarch64_be,
10158 it must be laid out in the vector register in reverse order. */
10164 {
10167 }
10169 {
10172 }
10173 else
10177 {
10180 {
10183 }
10186 }
10187 }
10189 /* Sanity check. */
10192 do
10193 {
10242 }
10249 {
10259 /* Un-invert bytes of recognized vector, if necessary. */
10265 {
10266 /* FIXME: Broken on 32-bit H_W_I hosts. */
10275 }
10276 else
10277 {
10281 /* Construct 'abcdefgh' because the assembler cannot handle
10282 generic constants. */
10287 }
10288 }
10291 #undef CHECK
10292 }
10294 /* Check of immediate shift constants are within range. */
10295 bool
10297 {
10301 else
10303 }
10305 /* Return true if X is a uniform vector where all elements
10306 are either the floating-point constant 0.0 or the
10307 integer constant 0. */
10308 bool
10310 {
10312 }
10314 bool
10316 {
10321 {
10326 }
10329 }
10331 bool
10333 {
10346 }
10348 /* Return a const_int vector of VAL. */
10349 rtx
10351 {
10360 }
10362 /* Check OP is a legal scalar immediate for the MOVI instruction. */
10364 bool
10366 {
10367 machine_mode vmode;
10373 }
10375 /* Construct and return a PARALLEL RTX vector with elements numbering the
10376 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
10377 the vector - from the perspective of the architecture. This does not
10378 line up with GCC's perspective on lane numbers, so we end up with
10379 different masks depending on our target endian-ness. The diagram
10380 below may help. We must draw the distinction when building masks
10381 which select one half of the vector. An instruction selecting
10382 architectural low-lanes for a big-endian target, must be described using
10383 a mask selecting GCC high-lanes.
10385 Big-Endian Little-Endian
10387 GCC 0 1 2 3 3 2 1 0
10388 | x | x | x | x | | x | x | x | x |
10389 Architecture 3 2 1 0 3 2 1 0
10391 Low Mask: { 2, 3 } { 0, 1 }
10392 High Mask: { 0, 1 } { 2, 3 }
10393 */
10395 rtx
10397 {
10403 rtx t1;
10408 else
10416 }
10418 /* Check OP for validity as a PARALLEL RTX vector with elements
10419 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
10420 from the perspective of the architecture. See the diagram above
10421 aarch64_simd_vect_par_cnst_half for more details. */
10423 bool
10426 {
10439 {
10446 }
10448 }
10450 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
10451 HIGH (exclusive). */
10452 void
10454 const_tree exp)
10455 {
10456 HOST_WIDE_INT lane;
10461 {
10464 else
10466 }
10467 }
10469 /* Return TRUE if OP is a valid vector addressing mode. */
10470 bool
10472 {
10475 }
10477 /* Emit a register copy from operand to operand, taking care not to
10478 early-clobber source registers in the process.
10480 COUNT is the number of components into which the copy needs to be
10481 decomposed. */
10482 void
10485 {
10495 else
10499 }
10501 /* Compute and return the length of aarch64_simd_mov<mode>, where <mode> is
10502 one of VSTRUCT modes: OI, CI or XI. */
10503 int
10505 {
10506 machine_mode mode;
10511 {
10514 {
10523 }
10524 }
10526 }
10528 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
10529 one of VSTRUCT modes: OI, CI, or XI. */
10530 int
10532 {
10534 }
10536 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
10537 alignment of a vector to 128 bits. */
10538 static HOST_WIDE_INT
10540 {
10543 }
10545 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
10546 static bool
10548 {
10552 /* We guarantee alignment for vectors up to 128-bits. */
10557 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
10559 }
10561 /* If VALS is a vector constant that can be loaded into a register
10562 using DUP, generate instructions to do so and return an RTX to
10563 assign to the register. Otherwise return NULL_RTX. */
10564 static rtx
10566 {
10569 rtx x;
10574 /* We can load this constant by using DUP and a constant in a
10575 single ARM register. This will be cheaper than a vector
10576 load. */
10579 }
10582 /* Generate code to load VALS, which is a PARALLEL containing only
10583 constants (for vec_init) or CONST_VECTOR, efficiently into a
10584 register. Returns an RTX to copy into the register, or NULL_RTX
10585 for a PARALLEL that can not be converted into a CONST_VECTOR. */
10586 static rtx
10588 {
10590 rtx const_dup;
10599 {
10600 /* A CONST_VECTOR must contain only CONST_INTs and
10601 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
10602 Only store valid constants in a CONST_VECTOR. */
10604 {
10607 n_const++;
10608 }
10611 }
10612 else
10617 /* Load using MOVI/MVNI. */
10620 /* Loaded using DUP. */
10623 /* Load from constant pool. We can not take advantage of single-cycle
10624 LD1 because we need a PC-relative addressing mode. */
10626 else
10627 /* A PARALLEL containing something not valid inside CONST_VECTOR.
10628 We can not construct an initializer. */
10630 }
10632 void
10634 {
10643 {
10647 else
10652 }
10655 {
10658 {
10661 }
10662 }
10664 /* Splat a single non-constant element if we can. */
10666 {
10670 }
10672 /* Half the fields (or less) are non-constant. Load constant then overwrite
10673 varying fields. Hope that this is more efficient than using the stack. */
10675 {
10678 /* Load constant part of vector. We really don't care what goes into the
10679 parts we will overwrite, but we're more likely to be able to load the
10680 constant efficiently if it has fewer, larger, repeating parts
10681 (see aarch64_simd_valid_immediate). */
10683 {
10689 {
10690 /* Look in the copied vector, as more elements are const. */
10693 {
10696 }
10697 }
10699 }
10702 /* Insert variables. */
10707 {
10713 }
10715 }
10717 /* Construct the vector in memory one field at a time
10718 and load the whole vector. */
10726 }
10728 static unsigned HOST_WIDE_INT
10730 {
10731 return
10734 }
10736 /* Select a format to encode pointers in exception handling data. */
10737 int
10739 {
10742 {
10748 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
10749 for everything. */
10753 /* No assumptions here. 8-byte relocs required. */
10756 }
10758 }
10760 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
10761 by the function fndecl. */
10763 void
10765 tree fndecl)
10766 {
10772 else
10785 /* Print the cpu name we're tuning for in the comments, might be
10786 useful to readers of the generated asm. */
10794 /* Don't forget the type directive for ELF. */
10797 }
10799 /* Emit load exclusive. */
10801 static void
10804 {
10808 {
10815 }
10818 }
10820 /* Emit store exclusive. */
10822 static void
10825 {
10829 {
10836 }
10839 }
10841 /* Mark the previous jump instruction as unlikely. */
10843 static void
10845 {
10850 }
10852 /* Expand a compare and swap pattern. */
10854 void
10856 {
10861 gen_cas_fn gen;
10863 {
10864 gen_aarch64_compare_and_swapqi,
10865 gen_aarch64_compare_and_swaphi,
10866 gen_aarch64_compare_and_swapsi,
10867 gen_aarch64_compare_and_swapdi
10868 };
10870 {
10871 gen_aarch64_compare_and_swapqi_lse,
10872 gen_aarch64_compare_and_swaphi_lse,
10873 gen_aarch64_compare_and_swapsi_lse,
10874 gen_aarch64_compare_and_swapdi_lse
10875 };
10888 /* Normally the succ memory model must be stronger than fail, but in the
10889 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
10890 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
10897 {
10900 /* For short modes, we're going to perform the comparison in SImode,
10901 so do the zero-extension now. */
10905 /* Fall through. */
10909 /* Force the value into a register if needed. */
10916 }
10919 {
10926 }
10929 else
10940 }
10942 /* Test whether the target supports using a atomic load-operate instruction.
10943 CODE is the operation and AFTER is TRUE if the data in memory after the
10944 operation should be returned and FALSE if the data before the operation
10945 should be returned. Returns FALSE if the operation isn't supported by the
10946 architecture. */
10948 bool
10950 {
10955 {
10965 }
10966 }
10968 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
10969 sequence implementing an atomic operation. */
10971 static void
10973 {
10980 {
10982 }
10983 }
10985 /* Emit an atomic compare-and-swap operation. RVAL is the destination register
10986 for the data in memory. EXPECTED is the value expected to be in memory.
10987 DESIRED is the value to store to memory. MEM is the memory location. MODEL
10988 is the memory ordering to use. */
10990 void
10993 rtx model)
10994 {
10996 machine_mode mode;
11001 {
11008 }
11010 /* Move the expected value into the CAS destination register. */
11013 /* Emit the CAS. */
11016 /* Compare the expected value with the value loaded by the CAS, to establish
11017 whether the swap was made. */
11019 }
11021 /* Split a compare and swap pattern. */
11023 void
11025 {
11027 machine_mode mode;
11032 rtx model_rtx;
11046 {
11049 }
11052 /* The initial load can be relaxed for a __sync operation since a final
11053 barrier will be emitted to stop code hoisting. */
11057 else
11069 {
11074 }
11075 else
11076 {
11080 }
11084 /* Emit any final barrier needed for a __sync operation. */
11087 }
11089 /* Emit a BIC instruction. */
11091 static void
11093 {
11098 {
11103 }
11106 }
11108 /* Emit an atomic swap. */
11110 static void
11113 {
11117 {
11124 }
11127 }
11129 /* Operations supported by aarch64_emit_atomic_load_op. */
11131 enum aarch64_atomic_load_op_code
11132 {
11136 AARCH64_LDOP_BIC /* A & ~B */
11137 };
11139 /* Emit an atomic load-operate. */
11141 static void
11145 {
11148 {
11149 gen_aarch64_atomic_loadaddqi,
11150 gen_aarch64_atomic_loadaddhi,
11151 gen_aarch64_atomic_loadaddsi,
11152 gen_aarch64_atomic_loadadddi
11153 };
11155 {
11156 gen_aarch64_atomic_loadeorqi,
11157 gen_aarch64_atomic_loadeorhi,
11158 gen_aarch64_atomic_loadeorsi,
11159 gen_aarch64_atomic_loadeordi
11160 };
11162 {
11163 gen_aarch64_atomic_loadsetqi,
11164 gen_aarch64_atomic_loadsethi,
11165 gen_aarch64_atomic_loadsetsi,
11166 gen_aarch64_atomic_loadsetdi
11167 };
11169 {
11170 gen_aarch64_atomic_loadclrqi,
11171 gen_aarch64_atomic_loadclrhi,
11172 gen_aarch64_atomic_loadclrsi,
11173 gen_aarch64_atomic_loadclrdi
11174 };
11175 aarch64_atomic_load_op_fn gen;
11179 {
11186 }
11189 {
11196 }
11199 }
11201 /* Emit an atomic load+operate. CODE is the operation. OUT_DATA is the
11202 location to store the data read from memory. OUT_RESULT is the location to
11203 store the result of the operation. MEM is the memory location to read and
11204 modify. MODEL_RTX is the memory ordering to use. VALUE is the second
11205 operand for the operation. Either OUT_DATA or OUT_RESULT, but not both, can
11206 be NULL. */
11208 void
11211 {
11215 aarch64_atomic_load_op_code ldop_code;
11216 rtx src;
11217 rtx x;
11225 /* Make sure the value is in a register, putting it into a destination
11226 register if it needs to be manipulated. */
11229 {
11232 }
11233 else
11237 /* Preprocess the data for the operation as necessary. If the operation is
11238 a SET then emit a swap instruction and finish. */
11240 {
11246 /* Negate the value and treat it as a PLUS. */
11247 {
11248 rtx neg_src;
11250 /* Resize the value if necessary. */
11259 }
11260 /* Fall-through. */
11274 {
11275 rtx not_src;
11277 /* Resize the value if necessary. */
11286 }
11291 /* The operation can't be done with atomic instructions. */
11293 }
11297 /* If necessary, calculate the data in memory after the update by redoing the
11298 operation from values in registers. */
11303 {
11307 }
11312 {
11328 }
11333 }
11335 /* Split an atomic operation. */
11337 void
11340 {
11346 rtx x;
11348 /* Split the atomic operation into a sequence. */
11356 else
11360 /* The initial load can be relaxed for a __sync operation since a final
11361 barrier will be emitted to stop code hoisting. */
11365 else
11369 {
11383 {
11386 }
11387 /* Fall through. */
11393 }
11403 /* Emit any final barrier needed for a __sync operation. */
11406 }
11408 static void
11410 {
11411 /* Half-precision float operations. The compiler handles all operations
11412 with NULL libfuncs by converting to SFmode. */
11414 /* Conversions. */
11418 /* Arithmetic. */
11425 /* Comparisons. */
11433 }
11435 /* Target hook for c_mode_for_suffix. */
11436 static machine_mode
11438 {
11443 }
11445 /* We can only represent floating point constants which will fit in
11446 "quarter-precision" values. These values are characterised by
11447 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
11448 by:
11450 (-1)^s * (n/16) * 2^r
11452 Where:
11453 's' is the sign bit.
11454 'n' is an integer in the range 16 <= n <= 31.
11455 'r' is an integer in the range -3 <= r <= 4. */
11457 /* Return true iff X can be represented by a quarter-precision
11458 floating point immediate operand X. Note, we cannot represent 0.0. */
11459 bool
11461 {
11462 /* This represents our current view of how many bits
11463 make up the mantissa. */
11473 /* We don't support HFmode constants yet. */
11479 /* We cannot represent infinities, NaNs or +/-zero. We won't
11480 know if we have +zero until we analyse the mantissa, but we
11481 can reject the other invalid values. */
11486 /* Extract exponent. */
11490 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
11491 highest (sign) bit, with a fixed binary point at bit point_pos.
11492 m1 holds the low part of the mantissa, m2 the high part.
11493 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
11494 bits for the mantissa, this can fail (low bits will be lost). */
11498 /* If the low part of the mantissa has bits set we cannot represent
11499 the value. */
11502 /* We have rejected the lower HOST_WIDE_INT, so update our
11503 understanding of how many bits lie in the mantissa and
11504 look only at the high HOST_WIDE_INT. */
11508 /* We can only represent values with a mantissa of the form 1.xxxx. */
11513 /* Having filtered unrepresentable values, we may now remove all
11514 but the highest 5 bits. */
11517 /* We cannot represent the value 0.0, so reject it. This is handled
11518 elsewhere. */
11522 /* Then, as bit 4 is always set, we can mask it off, leaving
11523 the mantissa in the range [0, 15]. */
11527 /* GCC internally does not use IEEE754-like encoding (where normalized
11528 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.c).
11529 Our mantissa values are shifted 4 places to the left relative to
11530 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
11531 by 5 places to correct for GCC's representation. */
11535 }
11539 machine_mode mode,
11541 {
11551 /* This will return true to show const_vector is legal for use as either
11552 a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
11553 also update INFO to show how the immediate should be generated. */
11562 {
11564 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
11565 move immediate path. */
11568 else
11569 {
11570 #define buf_size 20
11575 #undef buf_size
11579 else
11583 }
11584 }
11597 else
11601 }
11605 machine_mode mode)
11606 {
11607 machine_mode vmode;
11613 }
11615 /* Split operands into moves from op[1] + op[2] into op[0]. */
11617 void
11619 {
11630 {
11631 /* No-op move. Can't split to nothing; emit something. */
11634 }
11636 /* Preserve register attributes for variable tracking. */
11641 /* Special case of reversed high/low parts. */
11644 {
11648 }
11650 {
11651 /* Try to avoid unnecessary moves if part of the result
11652 is in the right place already. */
11657 }
11658 else
11659 {
11664 }
11665 }
11667 /* vec_perm support. */
11669 #define MAX_VECT_LEN 16
11671 struct expand_vec_perm_d
11672 {
11675 machine_mode vmode;
11679 };
11681 /* Generate a variable permutation. */
11683 static void
11685 {
11696 {
11698 {
11699 /* Expand the argument to a V16QI mode by duplicating it. */
11703 }
11704 else
11705 {
11707 }
11708 }
11709 else
11710 {
11711 rtx pair;
11714 {
11718 }
11719 else
11720 {
11724 }
11725 }
11726 }
11728 void
11730 {
11734 rtx mask;
11736 /* The TBL instruction does not use a modulo index, so we must take care
11737 of that ourselves. */
11742 /* For big-endian, we also need to reverse the index within the vector
11743 (but not which vector). */
11745 {
11746 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
11751 }
11753 }
11755 /* Recognize patterns suitable for the TRN instructions. */
11756 static bool
11758 {
11767 /* Note that these are little-endian tests.
11768 We correct for big-endian later. */
11773 else
11778 {
11783 }
11785 /* Success! */
11792 {
11795 }
11799 {
11801 {
11814 }
11815 }
11816 else
11817 {
11819 {
11832 }
11833 }
11837 }
11839 /* Recognize patterns suitable for the UZP instructions. */
11840 static bool
11842 {
11851 /* Note that these are little-endian tests.
11852 We correct for big-endian later. */
11857 else
11862 {
11866 }
11868 /* Success! */
11875 {
11878 }
11882 {
11884 {
11897 }
11898 }
11899 else
11900 {
11902 {
11915 }
11916 }
11920 }
11922 /* Recognize patterns suitable for the ZIP instructions. */
11923 static bool
11925 {
11934 /* Note that these are little-endian tests.
11935 We correct for big-endian later. */
11938 /* Do Nothing. */
11939 ;
11942 else
11947 {
11954 }
11956 /* Success! */
11963 {
11966 }
11970 {
11972 {
11985 }
11986 }
11987 else
11988 {
11990 {
12003 }
12004 }
12008 }
12010 /* Recognize patterns for the EXT insn. */
12012 static bool
12014 {
12017 rtx offset;
12021 /* Check if the extracted indices are increasing by one. */
12023 {
12026 {
12027 /* We'll pass the same vector in twice, so allow indices to wrap. */
12029 }
12032 }
12035 {
12048 }
12050 /* Success! */
12054 /* The case where (location == 0) is a no-op for both big- and little-endian,
12055 and is removed by the mid-end at optimization levels -O1 and higher. */
12058 {
12059 /* After setup, we want the high elements of the first vector (stored
12060 at the LSB end of the register), and the low elements of the second
12061 vector (stored at the MSB end of the register). So swap. */
12063 /* location != 0 (above), so safe to assume (nelt - location) < nelt. */
12065 }
12070 }
12072 /* Recognize patterns for the REV insns. */
12074 static bool
12076 {
12085 {
12088 {
12093 }
12097 {
12104 }
12108 {
12119 }
12123 }
12127 {
12128 /* This is guaranteed to be true as the value of diff
12129 is 7, 3, 1 and we should have enough elements in the
12130 queue to generate this. Getting a vector mask with a
12131 value of diff other than these values implies that
12132 something is wrong by the time we get here. */
12136 }
12138 /* Success! */
12144 }
12146 static bool
12148 {
12151 rtx in0;
12154 rtx lane;
12158 {
12161 }
12163 /* The generic preparation in aarch64_expand_vec_perm_const_1
12164 swaps the operand order and the permute indices if it finds
12165 d->perm[0] to be in the second operand. Thus, we can always
12166 use d->op0 and need not do any extra arithmetic to get the
12167 correct lane number. */
12172 {
12187 }
12191 }
12193 static bool
12195 {
12203 /* Generic code will try constant permutation twice. Once with the
12204 original mode and again with the elements lowered to QImode.
12205 So wait and don't do the selector expansion ourselves. */
12210 {
12213 /* If big-endian and two vectors we end up with a weird mixed-endian
12214 mode on NEON. Reverse the index within each word but not the word
12215 itself. */
12218 }
12224 }
12226 static bool
12228 {
12229 /* The pattern matching functions above are written to look for a small
12230 number to begin the sequence (0, 1, N/2). If we begin with an index
12231 from the second operand, we can swap the operands. */
12233 {
12241 }
12244 {
12258 }
12260 }
12262 /* Expand a vec_perm_const pattern. */
12264 bool
12266 {
12280 {
12285 }
12288 {
12297 /* The elements of PERM do not suggest that only the first operand
12298 is used, but both operands are identical. Allow easier matching
12299 of the permutation by folding the permutation into the single
12300 input vector. */
12301 /* Fall Through. */
12313 }
12316 }
12318 static bool
12321 {
12331 /* Calculate whether all elements are in one vector. */
12333 {
12337 }
12339 /* If all elements are from the second vector, reindex as if from the
12340 first vector. */
12345 /* Check whether the mask can be applied to a single vector. */
12358 }
12360 rtx
12362 {
12363 /* We have to reverse each vector because we dont have
12364 a permuted load that can reverse-load according to ABI rules. */
12365 rtx mask;
12379 }
12381 /* Implement MODES_TIEABLE_P. */
12383 bool
12385 {
12389 /* We specifically want to allow elements of "structure" modes to
12390 be tieable to the structure. This more general condition allows
12391 other rarer situations too. */
12398 }
12400 /* Return a new RTX holding the result of moving POINTER forward by
12401 AMOUNT bytes. */
12403 static rtx
12405 {
12410 }
12412 /* Return a new RTX holding the result of moving POINTER forward by the
12413 size of the mode it points to. */
12415 static rtx
12417 {
12421 }
12423 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
12424 MODE bytes. */
12426 static void
12428 machine_mode mode)
12429 {
12432 /* "Cast" the pointers to the correct mode. */
12435 /* Emit the memcpy. */
12438 /* Move the pointers forward. */
12441 }
12443 /* Expand movmem, as if from a __builtin_memcpy. Return true if
12444 we succeed, otherwise return false. */
12446 bool
12448 {
12452 rtx base;
12455 /* When optimizing for size, give a better estimate of the length of a
12456 memcpy call, but use the default otherwise. */
12459 /* We can't do anything smart if the amount to copy is not constant. */
12465 /* Try to keep the number of instructions low. For cases below 16 bytes we
12466 need to make at most two moves. For cases above 16 bytes it will be one
12467 move for each 16 byte chunk, then at most two additional moves. */
12477 /* Simple cases. Copy 0-3 bytes, as (if applicable) a 2-byte, then a
12478 1-byte chunk. */
12480 {
12482 {
12485 }
12491 }
12493 /* Copy 4-8 bytes. First a 4-byte chunk, then (if applicable) a second
12494 4-byte chunk, partially overlapping with the previously copied chunk. */
12496 {
12500 {
12506 }
12508 }
12510 /* Copy more than 8 bytes. Copy chunks of 16 bytes until we run out of
12511 them, then (if applicable) an 8-byte chunk. */
12513 {
12515 {
12518 }
12519 else
12520 {
12523 }
12524 }
12526 /* Finish the final bytes of the copy. We can always do this in one
12527 instruction. We either copy the exact amount we need, or partially
12528 overlap with the previous chunk we copied and copy 8-bytes. */
12537 else
12538 {
12540 {
12544 }
12545 else
12546 {
12552 }
12553 }
12556 }
12558 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12560 static unsigned HOST_WIDE_INT
12562 {
12564 }
12566 static bool
12571 {
12572 /* STORE_BY_PIECES can be used when copying a constant string, but
12573 in that case each 64-bit chunk takes 5 insns instead of 2 (LDR/STR).
12574 For now we always fail this and let the move_by_pieces code copy
12575 the string from read-only memory. */
12580 }
12582 static enum machine_mode
12584 {
12586 {
12619 }
12620 }
12622 static rtx
12625 {
12644 {
12660 }
12665 {
12668 }
12682 {
12685 }
12690 }
12692 static rtx
12695 {
12714 {
12732 }
12737 {
12740 }
12757 {
12760 }
12766 }
12768 #undef TARGET_GEN_CCMP_FIRST
12769 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
12771 #undef TARGET_GEN_CCMP_NEXT
12772 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
12774 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
12775 instruction fusion of some sort. */
12777 static bool
12779 {
12781 }
12784 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
12785 should be kept together during scheduling. */
12787 static bool
12789 {
12790 rtx set_dest;
12793 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
12801 {
12802 /* We are trying to match:
12803 prev (mov) == (set (reg r0) (const_int imm16))
12804 curr (movk) == (set (zero_extract (reg r0)
12805 (const_int 16)
12806 (const_int 16))
12807 (const_int imm16_1)) */
12819 {
12821 }
12822 }
12826 {
12828 /* We're trying to match:
12829 prev (adrp) == (set (reg r1)
12830 (high (symbol_ref ("SYM"))))
12831 curr (add) == (set (reg r0)
12832 (lo_sum (reg r1)
12833 (symbol_ref ("SYM"))))
12834 Note that r0 need not necessarily be the same as r1, especially
12835 during pre-regalloc scheduling. */
12839 {
12847 }
12848 }
12852 {
12854 /* We're trying to match:
12855 prev (movk) == (set (zero_extract (reg r0)
12856 (const_int 16)
12857 (const_int 32))
12858 (const_int imm16_1))
12859 curr (movk) == (set (zero_extract (reg r0)
12860 (const_int 16)
12861 (const_int 48))
12862 (const_int imm16_2)) */
12878 }
12881 {
12882 /* We're trying to match:
12883 prev (adrp) == (set (reg r0)
12884 (high (symbol_ref ("SYM"))))
12885 curr (ldr) == (set (reg r1)
12886 (mem (lo_sum (reg r0)
12887 (symbol_ref ("SYM")))))
12888 or
12889 curr (ldr) == (set (reg r1)
12890 (zero_extend (mem
12891 (lo_sum (reg r0)
12892 (symbol_ref ("SYM")))))) */
12895 {
12908 }
12909 }
12913 {
12916 /* FIXME: this misses some which is considered simple arthematic
12917 instructions for ThunderX. Simple shifts are missed here. */
12923 }
12926 }
12928 /* If MEM is in the form of [base+offset], extract the two parts
12929 of address and set to BASE and OFFSET, otherwise return false
12930 after clearing BASE and OFFSET. */
12932 bool
12934 {
12935 rtx addr;
12942 {
12946 }
12950 {
12954 }
12960 }
12962 /* Types for scheduling fusion. */
12963 enum sched_fusion_type
12964 {
12966 SCHED_FUSION_LD_SIGN_EXTEND,
12967 SCHED_FUSION_LD_ZERO_EXTEND,
12968 SCHED_FUSION_LD,
12969 SCHED_FUSION_ST,
12970 SCHED_FUSION_NUM
12971 };
12973 /* If INSN is a load or store of address in the form of [base+offset],
12974 extract the two parts and set to BASE and OFFSET. Return scheduling
12975 fusion type this INSN is. */
12977 static enum sched_fusion_type
12979 {
12997 {
13002 }
13004 {
13009 }
13014 {
13017 }
13018 else
13025 }
13027 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
13029 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
13030 and PRI are only calculated for these instructions. For other instruction,
13031 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
13032 type instruction fusion can be added by returning different priorities.
13034 It's important that irrelevant instructions get the largest FUSION_PRI. */
13036 static void
13039 {
13049 {
13053 }
13055 /* Set FUSION_PRI according to fusion type and base register. */
13058 /* Calculate PRI. */
13061 /* INSN with smaller offset goes first. */
13065 else
13070 }
13072 /* Given OPERANDS of consecutive load/store, check if we can merge
13073 them into ldp/stp. LOAD is true if they are load instructions.
13074 MODE is the mode of memory operands. */
13076 bool
13079 {
13085 {
13093 }
13094 else
13095 {
13100 }
13102 /* The mems cannot be volatile. */
13106 /* Check if the addresses are in the form of [base+offset]. */
13114 /* Check if the bases are same. */
13121 /* Check if the offsets are consecutive. */
13125 /* Check if the addresses are clobbered by load. */
13127 {
13131 /* In increasing order, the last load can clobber the address. */
13134 }
13138 else
13143 else
13146 /* Check if the registers are of same class. */
13151 }
13153 /* Given OPERANDS of consecutive load/store, check if we can merge
13154 them into ldp/stp by adjusting the offset. LOAD is true if they
13155 are load instructions. MODE is the mode of memory operands.
13157 Given below consecutive stores:
13159 str w1, [xb, 0x100]
13160 str w1, [xb, 0x104]
13161 str w1, [xb, 0x108]
13162 str w1, [xb, 0x10c]
13164 Though the offsets are out of the range supported by stp, we can
13165 still pair them after adjusting the offset, like:
13167 add scratch, xb, 0x100
13168 stp w1, w1, [scratch]
13169 stp w1, w1, [scratch, 0x8]
13171 The peephole patterns detecting this opportunity should guarantee
13172 the scratch register is avaliable. */
13174 bool
13177 {
13184 {
13197 }
13198 else
13199 {
13208 }
13209 /* Skip if memory operand is by itslef valid for ldp/stp. */
13213 /* The mems cannot be volatile. */
13218 /* Check if the addresses are in the form of [base+offset]. */
13232 /* Check if the bases are same. */
13243 /* Check if the offsets are consecutive. */
13252 /* Check if the addresses are clobbered by load. */
13254 {
13260 /* In increasing order, the last load can clobber the address. */
13263 }
13267 else
13272 else
13277 else
13282 else
13285 /* Check if the registers are of same class. */
13290 }
13292 /* Given OPERANDS of consecutive load/store, this function pairs them
13293 into ldp/stp after adjusting the offset. It depends on the fact
13294 that addresses of load/store instructions are in increasing order.
13295 MODE is the mode of memory operands. CODE is the rtl operator
13296 which should be applied to all memory operands, it's SIGN_EXTEND,
13297 ZERO_EXTEND or UNKNOWN. */
13299 bool
13302 {
13308 {
13313 }
13314 else
13315 {
13321 }
13326 /* Adjust offset thus it can fit in ldp/stp instruction. */
13334 /* Further adjust to make sure all offsets are OK. */
13336 {
13339 }
13341 /* Make sure the adjustment can be done with ADD/SUB instructions. */
13346 {
13349 }
13351 /* Create new memory references. */
13355 /* Check if the adjusted address is OK for ldp/stp. */
13374 {
13379 }
13381 {
13386 }
13389 {
13394 }
13395 else
13396 {
13401 }
13403 /* Emit adjusting instruction. */
13405 /* Emit ldp/stp instructions. */
13413 }
13415 /* Return 1 if pseudo register should be created and used to hold
13416 GOT address for PIC code. */
13418 bool
13420 {
13422 }
13424 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
13426 static int
13428 {
13430 {
13437 }
13440 }
13443 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
13444 return the log2 of that value. Otherwise return -1. */
13446 int
13448 {
13463 }
13465 /* If X is a vector of equal CONST_DOUBLE values and that value is
13466 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
13468 int
13470 {
13486 }
13488 /* Implement TARGET_PROMOTED_TYPE to promote __fp16 to float. */
13489 static tree
13491 {
13495 }
13496 #undef TARGET_ADDRESS_COST
13497 #define TARGET_ADDRESS_COST aarch64_address_cost
13499 /* This hook will determines whether unnamed bitfields affect the alignment
13500 of the containing structure. The hook returns true if the structure
13501 should inherit the alignment requirements of an unnamed bitfield's
13502 type. */
13503 #undef TARGET_ALIGN_ANON_BITFIELD
13504 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
13506 #undef TARGET_ASM_ALIGNED_DI_OP
13509 #undef TARGET_ASM_ALIGNED_HI_OP
13512 #undef TARGET_ASM_ALIGNED_SI_OP
13515 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
13516 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
13517 hook_bool_const_tree_hwi_hwi_const_tree_true
13519 #undef TARGET_ASM_OUTPUT_MI_THUNK
13520 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
13522 #undef TARGET_ASM_SELECT_RTX_SECTION
13523 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
13525 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
13526 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
13528 #undef TARGET_BUILD_BUILTIN_VA_LIST
13529 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
13531 #undef TARGET_CALLEE_COPIES
13532 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
13534 #undef TARGET_CAN_ELIMINATE
13535 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
13537 #undef TARGET_CAN_INLINE_P
13538 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
13540 #undef TARGET_CANNOT_FORCE_CONST_MEM
13541 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
13543 #undef TARGET_CONDITIONAL_REGISTER_USAGE
13544 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
13546 /* Only the least significant bit is used for initialization guard
13547 variables. */
13548 #undef TARGET_CXX_GUARD_MASK_BIT
13549 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
13551 #undef TARGET_C_MODE_FOR_SUFFIX
13552 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
13554 #ifdef TARGET_BIG_ENDIAN_DEFAULT
13555 #undef TARGET_DEFAULT_TARGET_FLAGS
13556 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
13557 #endif
13559 #undef TARGET_CLASS_MAX_NREGS
13560 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
13562 #undef TARGET_BUILTIN_DECL
13563 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
13565 #undef TARGET_BUILTIN_RECIPROCAL
13566 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
13568 #undef TARGET_EXPAND_BUILTIN
13569 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
13571 #undef TARGET_EXPAND_BUILTIN_VA_START
13572 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
13574 #undef TARGET_FOLD_BUILTIN
13575 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
13577 #undef TARGET_FUNCTION_ARG
13578 #define TARGET_FUNCTION_ARG aarch64_function_arg
13580 #undef TARGET_FUNCTION_ARG_ADVANCE
13581 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
13583 #undef TARGET_FUNCTION_ARG_BOUNDARY
13584 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
13586 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13587 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
13589 #undef TARGET_FUNCTION_VALUE
13590 #define TARGET_FUNCTION_VALUE aarch64_function_value
13592 #undef TARGET_FUNCTION_VALUE_REGNO_P
13593 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
13595 #undef TARGET_FRAME_POINTER_REQUIRED
13596 #define TARGET_FRAME_POINTER_REQUIRED aarch64_frame_pointer_required
13598 #undef TARGET_GIMPLE_FOLD_BUILTIN
13599 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
13601 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
13602 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
13604 #undef TARGET_INIT_BUILTINS
13605 #define TARGET_INIT_BUILTINS aarch64_init_builtins
13607 #undef TARGET_LEGITIMATE_ADDRESS_P
13608 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
13610 #undef TARGET_LEGITIMATE_CONSTANT_P
13611 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
13613 #undef TARGET_LIBGCC_CMP_RETURN_MODE
13614 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
13616 #undef TARGET_LRA_P
13617 #define TARGET_LRA_P hook_bool_void_true
13619 #undef TARGET_MANGLE_TYPE
13620 #define TARGET_MANGLE_TYPE aarch64_mangle_type
13622 #undef TARGET_MEMORY_MOVE_COST
13623 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
13625 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
13626 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
13628 #undef TARGET_MUST_PASS_IN_STACK
13629 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
13631 /* This target hook should return true if accesses to volatile bitfields
13632 should use the narrowest mode possible. It should return false if these
13633 accesses should use the bitfield container type. */
13634 #undef TARGET_NARROW_VOLATILE_BITFIELD
13635 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
13637 #undef TARGET_OPTION_OVERRIDE
13638 #define TARGET_OPTION_OVERRIDE aarch64_override_options
13640 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
13641 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
13642 aarch64_override_options_after_change
13644 #undef TARGET_OPTION_SAVE
13645 #define TARGET_OPTION_SAVE aarch64_option_save
13647 #undef TARGET_OPTION_RESTORE
13648 #define TARGET_OPTION_RESTORE aarch64_option_restore
13650 #undef TARGET_OPTION_PRINT
13651 #define TARGET_OPTION_PRINT aarch64_option_print
13653 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
13654 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
13656 #undef TARGET_SET_CURRENT_FUNCTION
13657 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
13659 #undef TARGET_PASS_BY_REFERENCE
13660 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
13662 #undef TARGET_PREFERRED_RELOAD_CLASS
13663 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
13665 #undef TARGET_SCHED_REASSOCIATION_WIDTH
13666 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
13668 #undef TARGET_PROMOTED_TYPE
13669 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
13671 #undef TARGET_SECONDARY_RELOAD
13672 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
13674 #undef TARGET_SHIFT_TRUNCATION_MASK
13675 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
13677 #undef TARGET_SETUP_INCOMING_VARARGS
13678 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
13680 #undef TARGET_STRUCT_VALUE_RTX
13681 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
13683 #undef TARGET_REGISTER_MOVE_COST
13684 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
13686 #undef TARGET_RETURN_IN_MEMORY
13687 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
13689 #undef TARGET_RETURN_IN_MSB
13690 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
13692 #undef TARGET_RTX_COSTS
13693 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
13695 #undef TARGET_SCHED_ISSUE_RATE
13696 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
13698 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
13699 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
13700 aarch64_sched_first_cycle_multipass_dfa_lookahead
13702 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
13703 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
13704 aarch64_first_cycle_multipass_dfa_lookahead_guard
13706 #undef TARGET_TRAMPOLINE_INIT
13707 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
13709 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
13710 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
13712 #undef TARGET_VECTOR_MODE_SUPPORTED_P
13713 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
13715 #undef TARGET_ARRAY_MODE_SUPPORTED_P
13716 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
13718 #undef TARGET_VECTORIZE_ADD_STMT_COST
13719 #define TARGET_VECTORIZE_ADD_STMT_COST aarch64_add_stmt_cost
13721 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
13722 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
13723 aarch64_builtin_vectorization_cost
13725 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
13726 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
13728 #undef TARGET_VECTORIZE_BUILTINS
13729 #define TARGET_VECTORIZE_BUILTINS
13731 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
13732 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
13733 aarch64_builtin_vectorized_function
13735 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
13736 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
13737 aarch64_autovectorize_vector_sizes
13739 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
13740 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
13741 aarch64_atomic_assign_expand_fenv
13743 /* Section anchor support. */
13745 #undef TARGET_MIN_ANCHOR_OFFSET
13746 #define TARGET_MIN_ANCHOR_OFFSET -256
13748 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
13749 byte offset; we can do much more for larger data types, but have no way
13750 to determine the size of the access. We assume accesses are aligned. */
13751 #undef TARGET_MAX_ANCHOR_OFFSET
13752 #define TARGET_MAX_ANCHOR_OFFSET 4095
13754 #undef TARGET_VECTOR_ALIGNMENT
13755 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
13757 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
13758 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
13759 aarch64_simd_vector_alignment_reachable
13761 /* vec_perm support. */
13763 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
13764 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
13765 aarch64_vectorize_vec_perm_const_ok
13767 #undef TARGET_INIT_LIBFUNCS
13768 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
13770 #undef TARGET_FIXED_CONDITION_CODE_REGS
13771 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
13773 #undef TARGET_FLAGS_REGNUM
13774 #define TARGET_FLAGS_REGNUM CC_REGNUM
13776 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
13777 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
13779 #undef TARGET_ASAN_SHADOW_OFFSET
13780 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
13782 #undef TARGET_LEGITIMIZE_ADDRESS
13783 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
13785 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
13786 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
13787 aarch64_use_by_pieces_infrastructure_p
13789 #undef TARGET_CAN_USE_DOLOOP_P
13790 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
13792 #undef TARGET_SCHED_MACRO_FUSION_P
13793 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
13795 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
13796 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
13798 #undef TARGET_SCHED_FUSION_PRIORITY
13799 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
13801 #undef TARGET_UNSPEC_MAY_TRAP_P
13802 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
13804 #undef TARGET_USE_PSEUDO_PIC_REG
13805 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
13807 #undef TARGET_PRINT_OPERAND
13808 #define TARGET_PRINT_OPERAND aarch64_print_operand
13810 #undef TARGET_PRINT_OPERAND_ADDRESS
13811 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address