1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
118 #include "memmodel.h"
126 #include "addresses.h"
129 #include "rtl-error.h"
133 #include "print-rtl.h"
135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 static int bb_reload_num
;
140 /* The current insn being processed and corresponding its single set
141 (NULL otherwise), its data (basic block, the insn data, the insn
142 static data, and the mode of each operand). */
143 static rtx_insn
*curr_insn
;
144 static rtx curr_insn_set
;
145 static basic_block curr_bb
;
146 static lra_insn_recog_data_t curr_id
;
147 static struct lra_static_insn_data
*curr_static_id
;
148 static machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
149 /* Mode of the register substituted by its equivalence with VOIDmode
150 (e.g. constant) and whose subreg is given operand of the current
151 insn. VOIDmode in all other cases. */
152 static machine_mode original_subreg_reg_mode
[MAX_RECOG_OPERANDS
];
156 /* Start numbers for new registers and insns at the current constraints
158 static int new_regno_start
;
159 static int new_insn_uid_start
;
161 /* If LOC is nonnull, strip any outer subreg from it. */
163 strip_subreg (rtx
*loc
)
165 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
168 /* Return hard regno of REGNO or if it is was not assigned to a hard
169 register, use a hard register from its allocno class. */
171 get_try_hard_regno (int regno
)
174 enum reg_class rclass
;
176 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
177 hard_regno
= lra_get_regno_hard_regno (regno
);
180 rclass
= lra_get_allocno_class (regno
);
181 if (rclass
== NO_REGS
)
183 return ira_class_hard_regs
[rclass
][0];
186 /* Return the hard regno of X after removing its subreg. If X is not
187 a register or a subreg of a register, return -1. If X is a pseudo,
188 use its assignment. If FINAL_P return the final hard regno which will
189 be after elimination. */
191 get_hard_regno (rtx x
, bool final_p
)
198 reg
= SUBREG_REG (x
);
201 if (! HARD_REGISTER_NUM_P (hard_regno
= REGNO (reg
)))
202 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
206 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
208 hard_regno
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
209 SUBREG_BYTE (x
), GET_MODE (x
));
213 /* If REGNO is a hard register or has been allocated a hard register,
214 return the class of that register. If REGNO is a reload pseudo
215 created by the current constraints pass, return its allocno class.
216 Return NO_REGS otherwise. */
217 static enum reg_class
218 get_reg_class (int regno
)
222 if (! HARD_REGISTER_NUM_P (hard_regno
= regno
))
223 hard_regno
= lra_get_regno_hard_regno (regno
);
226 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
227 return REGNO_REG_CLASS (hard_regno
);
229 if (regno
>= new_regno_start
)
230 return lra_get_allocno_class (regno
);
234 /* Return true if REG satisfies (or will satisfy) reg class constraint
235 CL. Use elimination first if REG is a hard register. If REG is a
236 reload pseudo created by this constraints pass, assume that it will
237 be allocated a hard register from its allocno class, but allow that
238 class to be narrowed to CL if it is currently a superset of CL.
240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
241 REGNO (reg), or NO_REGS if no change in its class was needed. */
243 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
245 enum reg_class rclass
, common_class
;
246 machine_mode reg_mode
;
247 int class_size
, hard_regno
, nregs
, i
, j
;
248 int regno
= REGNO (reg
);
250 if (new_class
!= NULL
)
251 *new_class
= NO_REGS
;
252 if (regno
< FIRST_PSEUDO_REGISTER
)
255 rtx
*final_loc
= &final_reg
;
257 lra_eliminate_reg_if_possible (final_loc
);
258 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
260 reg_mode
= GET_MODE (reg
);
261 rclass
= get_reg_class (regno
);
262 if (regno
< new_regno_start
263 /* Do not allow the constraints for reload instructions to
264 influence the classes of new pseudos. These reloads are
265 typically moves that have many alternatives, and restricting
266 reload pseudos for one alternative may lead to situations
267 where other reload pseudos are no longer allocatable. */
268 || (INSN_UID (curr_insn
) >= new_insn_uid_start
269 && curr_insn_set
!= NULL
270 && ((OBJECT_P (SET_SRC (curr_insn_set
))
271 && ! CONSTANT_P (SET_SRC (curr_insn_set
)))
272 || (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))
274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set
)))))))
275 /* When we don't know what class will be used finally for reload
276 pseudos, we use ALL_REGS. */
277 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
278 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
279 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
280 lra_no_alloc_regs
)));
283 common_class
= ira_reg_class_subset
[rclass
][cl
];
284 if (new_class
!= NULL
)
285 *new_class
= common_class
;
286 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
289 /* Check that there are enough allocatable regs. */
290 class_size
= ira_class_hard_regs_num
[common_class
];
291 for (i
= 0; i
< class_size
; i
++)
293 hard_regno
= ira_class_hard_regs
[common_class
][i
];
294 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
297 for (j
= 0; j
< nregs
; j
++)
298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
299 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
309 /* Return true if REGNO satisfies a memory constraint. */
313 return get_reg_class (regno
) == NO_REGS
;
316 /* Return 1 if ADDR is a valid memory address for mode MODE in address
317 space AS, and check that each pseudo has the proper kind of hard
320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED
,
321 rtx addr
, addr_space_t as
)
323 #ifdef GO_IF_LEGITIMATE_ADDRESS
324 lra_assert (ADDR_SPACE_GENERIC_P (as
));
325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
331 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
336 /* Temporarily eliminates registers in an address (for the lifetime of
338 class address_eliminator
{
340 address_eliminator (struct address_info
*ad
);
341 ~address_eliminator ();
344 struct address_info
*m_ad
;
352 address_eliminator::address_eliminator (struct address_info
*ad
)
354 m_base_loc (strip_subreg (ad
->base_term
)),
355 m_base_reg (NULL_RTX
),
356 m_index_loc (strip_subreg (ad
->index_term
)),
357 m_index_reg (NULL_RTX
)
359 if (m_base_loc
!= NULL
)
361 m_base_reg
= *m_base_loc
;
362 lra_eliminate_reg_if_possible (m_base_loc
);
363 if (m_ad
->base_term2
!= NULL
)
364 *m_ad
->base_term2
= *m_ad
->base_term
;
366 if (m_index_loc
!= NULL
)
368 m_index_reg
= *m_index_loc
;
369 lra_eliminate_reg_if_possible (m_index_loc
);
373 address_eliminator::~address_eliminator ()
375 if (m_base_loc
&& *m_base_loc
!= m_base_reg
)
377 *m_base_loc
= m_base_reg
;
378 if (m_ad
->base_term2
!= NULL
)
379 *m_ad
->base_term2
= *m_ad
->base_term
;
381 if (m_index_loc
&& *m_index_loc
!= m_index_reg
)
382 *m_index_loc
= m_index_reg
;
385 /* Return true if the eliminated form of AD is a legitimate target address. */
387 valid_address_p (struct address_info
*ad
)
389 address_eliminator
eliminator (ad
);
390 return valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
393 /* Return true if the eliminated form of memory reference OP satisfies
394 extra (special) memory constraint CONSTRAINT. */
396 satisfies_memory_constraint_p (rtx op
, enum constraint_num constraint
)
398 struct address_info ad
;
400 decompose_mem_address (&ad
, op
);
401 address_eliminator
eliminator (&ad
);
402 return constraint_satisfied_p (op
, constraint
);
405 /* Return true if the eliminated form of address AD satisfies extra
406 address constraint CONSTRAINT. */
408 satisfies_address_constraint_p (struct address_info
*ad
,
409 enum constraint_num constraint
)
411 address_eliminator
eliminator (ad
);
412 return constraint_satisfied_p (*ad
->outer
, constraint
);
415 /* Return true if the eliminated form of address OP satisfies extra
416 address constraint CONSTRAINT. */
418 satisfies_address_constraint_p (rtx op
, enum constraint_num constraint
)
420 struct address_info ad
;
422 decompose_lea_address (&ad
, &op
);
423 return satisfies_address_constraint_p (&ad
, constraint
);
426 /* Initiate equivalences for LRA. As we keep original equivalences
427 before any elimination, we need to make copies otherwise any change
428 in insns might change the equivalences. */
430 lra_init_equiv (void)
432 ira_expand_reg_equiv ();
433 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_reg_num (); i
++)
437 if ((res
= ira_reg_equiv
[i
].memory
) != NULL_RTX
)
438 ira_reg_equiv
[i
].memory
= copy_rtx (res
);
439 if ((res
= ira_reg_equiv
[i
].invariant
) != NULL_RTX
)
440 ira_reg_equiv
[i
].invariant
= copy_rtx (res
);
444 static rtx
loc_equivalence_callback (rtx
, const_rtx
, void *);
446 /* Update equivalence for REGNO. We need to this as the equivalence
447 might contain other pseudos which are changed by their
450 update_equiv (int regno
)
454 if ((x
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
455 ira_reg_equiv
[regno
].memory
456 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
458 if ((x
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
459 ira_reg_equiv
[regno
].invariant
460 = simplify_replace_fn_rtx (x
, NULL_RTX
, loc_equivalence_callback
,
464 /* If we have decided to substitute X with another value, return that
465 value, otherwise return X. */
472 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
473 || ! ira_reg_equiv
[regno
].defined_p
474 || ! ira_reg_equiv
[regno
].profitable_p
475 || lra_get_regno_hard_regno (regno
) >= 0)
477 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
479 if (targetm
.cannot_substitute_mem_equiv_p (res
))
483 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
485 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
490 /* If we have decided to substitute X with the equivalent value,
491 return that value after elimination for INSN, otherwise return
494 get_equiv_with_elimination (rtx x
, rtx_insn
*insn
)
496 rtx res
= get_equiv (x
);
498 if (x
== res
|| CONSTANT_P (res
))
500 return lra_eliminate_regs_1 (insn
, res
, GET_MODE (res
),
501 false, false, 0, true);
504 /* Set up curr_operand_mode. */
506 init_curr_operand_mode (void)
508 int nop
= curr_static_id
->n_operands
;
509 for (int i
= 0; i
< nop
; i
++)
511 machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
512 if (mode
== VOIDmode
)
514 /* The .md mode for address operands is the mode of the
515 addressed value rather than the mode of the address itself. */
516 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
519 mode
= curr_static_id
->operand
[i
].mode
;
521 curr_operand_mode
[i
] = mode
;
527 /* The page contains code to reuse input reloads. */
529 /* Structure describes input reload of the current insns. */
532 /* True for input reload of matched operands. */
534 /* Reloaded value. */
536 /* Reload pseudo used. */
540 /* The number of elements in the following array. */
541 static int curr_insn_input_reloads_num
;
542 /* Array containing info about input reloads. It is used to find the
543 same input reload and reuse the reload pseudo in this case. */
544 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
546 /* Initiate data concerning reuse of input reloads for the current
549 init_curr_insn_input_reloads (void)
551 curr_insn_input_reloads_num
= 0;
554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
555 created input reload pseudo (only if TYPE is not OP_OUT). Don't
556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be
557 wrapped up in SUBREG. The result pseudo is returned through
558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we
559 reused the already created input reload pseudo. Use TITLE to
560 describe new registers for debug purposes. */
562 get_reload_reg (enum op_type type
, machine_mode mode
, rtx original
,
563 enum reg_class rclass
, bool in_subreg_p
,
564 const char *title
, rtx
*result_reg
)
567 enum reg_class new_class
;
568 bool unique_p
= false;
573 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
576 /* Prevent reuse value of expression with side effects,
577 e.g. volatile memory. */
578 if (! side_effects_p (original
))
579 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
581 if (! curr_insn_input_reloads
[i
].match_p
582 && rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
583 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
585 rtx reg
= curr_insn_input_reloads
[i
].reg
;
587 /* If input is equal to original and both are VOIDmode,
588 GET_MODE (reg) might be still different from mode.
589 Ensure we don't return *result_reg with wrong mode. */
590 if (GET_MODE (reg
) != mode
)
594 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
596 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
597 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
601 if (lra_dump_file
!= NULL
)
603 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
604 dump_value_slim (lra_dump_file
, original
, 1);
606 if (new_class
!= lra_get_allocno_class (regno
))
607 lra_change_class (regno
, new_class
, ", change to", false);
608 if (lra_dump_file
!= NULL
)
609 fprintf (lra_dump_file
, "\n");
612 /* If we have an input reload with a different mode, make sure it
613 will get a different hard reg. */
614 else if (REG_P (original
)
615 && REG_P (curr_insn_input_reloads
[i
].input
)
616 && REGNO (original
) == REGNO (curr_insn_input_reloads
[i
].input
)
617 && (GET_MODE (original
)
618 != GET_MODE (curr_insn_input_reloads
[i
].input
)))
621 *result_reg
= (unique_p
622 ? lra_create_new_reg_with_unique_value
623 : lra_create_new_reg
) (mode
, original
, rclass
, title
);
624 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
625 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
626 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= false;
627 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
633 /* The page contains code to extract memory address parts. */
635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
637 ok_for_index_p_nonstrict (rtx reg
)
639 unsigned regno
= REGNO (reg
);
641 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
644 /* A version of regno_ok_for_base_p for use here, when all pseudos
645 should count as OK. Arguments as for regno_ok_for_base_p. */
647 ok_for_base_p_nonstrict (rtx reg
, machine_mode mode
, addr_space_t as
,
648 enum rtx_code outer_code
, enum rtx_code index_code
)
650 unsigned regno
= REGNO (reg
);
652 if (regno
>= FIRST_PSEUDO_REGISTER
)
654 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
659 /* The page contains major code to choose the current insn alternative
660 and generate reloads for it. */
662 /* Return the offset from REGNO of the least significant register
665 This function is used to tell whether two registers satisfy
666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
668 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
671 lra_constraint_offset (int regno
, machine_mode mode
)
673 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
675 scalar_int_mode int_mode
;
677 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
678 && GET_MODE_SIZE (int_mode
) > UNITS_PER_WORD
)
679 return hard_regno_nregs
[regno
][mode
] - 1;
683 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
684 if they are the same hard reg, and has special hacks for
685 auto-increment and auto-decrement. This is specifically intended for
686 process_alt_operands to use in determining whether two operands
687 match. X is the operand whose number is the lower of the two.
689 It is supposed that X is the output operand and Y is the input
690 operand. Y_HARD_REGNO is the final hard regno of register Y or
691 register in subreg Y as we know it now. Otherwise, it is a
694 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
697 RTX_CODE code
= GET_CODE (x
);
702 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
703 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
707 i
= get_hard_regno (x
, false);
711 if ((j
= y_hard_regno
) < 0)
714 i
+= lra_constraint_offset (i
, GET_MODE (x
));
715 j
+= lra_constraint_offset (j
, GET_MODE (y
));
720 /* If two operands must match, because they are really a single
721 operand of an assembler insn, then two post-increments are invalid
722 because the assembler insn would increment only once. On the
723 other hand, a post-increment matches ordinary indexing if the
724 post-increment is the output operand. */
725 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
726 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
728 /* Two pre-increments are invalid because the assembler insn would
729 increment only once. On the other hand, a pre-increment matches
730 ordinary indexing if the pre-increment is the input operand. */
731 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
732 || GET_CODE (y
) == PRE_MODIFY
)
733 return operands_match_p (x
, XEXP (y
, 0), -1);
737 if (code
== REG
&& REG_P (y
))
738 return REGNO (x
) == REGNO (y
);
740 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
741 && x
== SUBREG_REG (y
))
743 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
744 && SUBREG_REG (x
) == y
)
747 /* Now we have disposed of all the cases in which different rtx
749 if (code
!= GET_CODE (y
))
752 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
753 if (GET_MODE (x
) != GET_MODE (y
))
762 return label_ref_label (x
) == label_ref_label (y
);
764 return XSTR (x
, 0) == XSTR (y
, 0);
770 /* Compare the elements. If any pair of corresponding elements fail
771 to match, return false for the whole things. */
773 fmt
= GET_RTX_FORMAT (code
);
774 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
780 if (XWINT (x
, i
) != XWINT (y
, i
))
785 if (XINT (x
, i
) != XINT (y
, i
))
790 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
799 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
801 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
803 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
809 /* It is believed that rtx's at this level will never
810 contain anything but integers and other rtx's, except for
811 within LABEL_REFs and SYMBOL_REFs. */
819 /* True if X is a constant that can be forced into the constant pool.
820 MODE is the mode of the operand, or VOIDmode if not known. */
821 #define CONST_POOL_OK_P(MODE, X) \
822 ((MODE) != VOIDmode \
824 && GET_CODE (X) != HIGH \
825 && !targetm.cannot_force_const_mem (MODE, X))
827 /* True if C is a non-empty register class that has too few registers
828 to be safely used as a reload target class. */
829 #define SMALL_REGISTER_CLASS_P(C) \
830 (ira_class_hard_regs_num [(C)] == 1 \
831 || (ira_class_hard_regs_num [(C)] >= 1 \
832 && targetm.class_likely_spilled_p (C)))
834 /* If REG is a reload pseudo, try to make its class satisfying CL. */
836 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
838 enum reg_class rclass
;
840 /* Do not make more accurate class from reloads generated. They are
841 mostly moves with a lot of constraints. Making more accurate
842 class may results in very narrow class and impossibility of find
843 registers for several reloads of one insn. */
844 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
846 if (GET_CODE (reg
) == SUBREG
)
847 reg
= SUBREG_REG (reg
);
848 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
850 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
851 lra_change_class (REGNO (reg
), rclass
, " Change to", true);
854 /* Searches X for any reference to a reg with the same value as REGNO,
855 returning the rtx of the reference found if any. Otherwise,
858 regno_val_use_in (unsigned int regno
, rtx x
)
864 if (REG_P (x
) && lra_reg_info
[REGNO (x
)].val
== lra_reg_info
[regno
].val
)
867 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
868 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
872 if ((tem
= regno_val_use_in (regno
, XEXP (x
, i
))))
875 else if (fmt
[i
] == 'E')
876 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
877 if ((tem
= regno_val_use_in (regno
, XVECEXP (x
, i
, j
))))
884 /* Return true if all current insn non-output operands except INS (it
885 has a negaitve end marker) do not use pseudos with the same value
888 check_conflict_input_operands (int regno
, signed char *ins
)
891 int n_operands
= curr_static_id
->n_operands
;
893 for (int nop
= 0; nop
< n_operands
; nop
++)
894 if (! curr_static_id
->operand
[nop
].is_operator
895 && curr_static_id
->operand
[nop
].type
!= OP_OUT
)
897 for (int i
= 0; (in
= ins
[i
]) >= 0; i
++)
901 && regno_val_use_in (regno
, *curr_id
->operand_loc
[nop
]) != NULL_RTX
)
907 /* Generate reloads for matching OUT and INS (array of input operand
908 numbers with end marker -1) with reg class GOAL_CLASS, considering
909 output operands OUTS (similar array to INS) needing to be in different
910 registers. Add input and output reloads correspondingly to the lists
911 *BEFORE and *AFTER. OUT might be negative. In this case we generate
912 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
913 that the output operand is early clobbered for chosen alternative. */
915 match_reload (signed char out
, signed char *ins
, signed char *outs
,
916 enum reg_class goal_class
, rtx_insn
**before
,
917 rtx_insn
**after
, bool early_clobber_p
)
921 rtx new_in_reg
, new_out_reg
, reg
;
922 machine_mode inmode
, outmode
;
923 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
924 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
926 inmode
= curr_operand_mode
[ins
[0]];
927 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
928 push_to_sequence (*before
);
929 if (inmode
!= outmode
)
931 if (partial_subreg_p (outmode
, inmode
))
934 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
936 if (SCALAR_INT_MODE_P (inmode
))
937 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
939 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
940 LRA_SUBREG_P (new_out_reg
) = 1;
941 /* If the input reg is dying here, we can use the same hard
942 register for REG and IN_RTX. We do it only for original
943 pseudos as reload pseudos can die although original
944 pseudos still live where reload pseudos dies. */
945 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
946 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
948 || check_conflict_input_operands(REGNO (in_rtx
), ins
)))
949 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
954 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
956 if (SCALAR_INT_MODE_P (outmode
))
957 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
959 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
960 /* NEW_IN_REG is non-paradoxical subreg. We don't want
961 NEW_OUT_REG living above. We add clobber clause for
962 this. This is just a temporary clobber. We can remove
963 it at the end of LRA work. */
964 rtx_insn
*clobber
= emit_clobber (new_out_reg
);
965 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
966 LRA_SUBREG_P (new_in_reg
) = 1;
967 if (GET_CODE (in_rtx
) == SUBREG
)
969 rtx subreg_reg
= SUBREG_REG (in_rtx
);
971 /* If SUBREG_REG is dying here and sub-registers IN_RTX
972 and NEW_IN_REG are similar, we can use the same hard
973 register for REG and SUBREG_REG. */
974 if (REG_P (subreg_reg
)
975 && (int) REGNO (subreg_reg
) < lra_new_regno_start
976 && GET_MODE (subreg_reg
) == outmode
977 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
978 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
))
979 && (! early_clobber_p
980 || check_conflict_input_operands (REGNO (subreg_reg
),
982 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
988 /* Pseudos have values -- see comments for lra_reg_info.
989 Different pseudos with the same value do not conflict even if
990 they live in the same place. When we create a pseudo we
991 assign value of original pseudo (if any) from which we
992 created the new pseudo. If we create the pseudo from the
993 input pseudo, the new pseudo will have no conflict with the
994 input pseudo which is wrong when the input pseudo lives after
995 the insn and as the new pseudo value is changed by the insn
996 output. Therefore we create the new pseudo from the output
997 except the case when we have single matched dying input
1000 We cannot reuse the current output register because we might
1001 have a situation like "a <- a op b", where the constraints
1002 force the second input operand ("b") to match the output
1003 operand ("a"). "b" must then be copied into a new register
1004 so that it doesn't clobber the current value of "a".
1006 We can not use the same value if the output pseudo is
1007 early clobbered or the input pseudo is mentioned in the
1008 output, e.g. as an address part in memory, because
1009 output reload will actually extend the pseudo liveness.
1010 We don't care about eliminable hard regs here as we are
1011 interesting only in pseudos. */
1013 /* Matching input's register value is the same as one of the other
1014 output operand. Output operands in a parallel insn must be in
1015 different registers. */
1016 out_conflict
= false;
1019 for (i
= 0; outs
[i
] >= 0; i
++)
1021 rtx other_out_rtx
= *curr_id
->operand_loc
[outs
[i
]];
1022 if (REG_P (other_out_rtx
)
1023 && (regno_val_use_in (REGNO (in_rtx
), other_out_rtx
)
1026 out_conflict
= true;
1032 new_in_reg
= new_out_reg
1033 = (! early_clobber_p
&& ins
[1] < 0 && REG_P (in_rtx
)
1034 && (int) REGNO (in_rtx
) < lra_new_regno_start
1035 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
))
1036 && (! early_clobber_p
1037 || check_conflict_input_operands (REGNO (in_rtx
), ins
))
1039 || regno_val_use_in (REGNO (in_rtx
), out_rtx
) == NULL_RTX
)
1041 ? lra_create_new_reg (inmode
, in_rtx
, goal_class
, "")
1042 : lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1045 /* In operand can be got from transformations before processing insn
1046 constraints. One example of such transformations is subreg
1047 reloading (see function simplify_operand_subreg). The new
1048 pseudos created by the transformations might have inaccurate
1049 class (ALL_REGS) and we should make their classes more
1051 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1052 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1053 *before
= get_insns ();
1055 /* Add the new pseudo to consider values of subsequent input reload
1057 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
1058 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= in_rtx
;
1059 curr_insn_input_reloads
[curr_insn_input_reloads_num
].match_p
= true;
1060 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= new_in_reg
;
1061 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1064 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1065 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1066 *curr_id
->operand_loc
[in
] = new_in_reg
;
1068 lra_update_dups (curr_id
, ins
);
1071 /* See a comment for the input operand above. */
1072 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1073 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1076 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1078 *after
= get_insns ();
1081 *curr_id
->operand_loc
[out
] = new_out_reg
;
1082 lra_update_dup (curr_id
, out
);
1085 /* Return register class which is union of all reg classes in insn
1086 constraint alternative string starting with P. */
1087 static enum reg_class
1088 reg_class_from_constraints (const char *p
)
1091 enum reg_class op_class
= NO_REGS
;
1094 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1101 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1105 enum constraint_num cn
= lookup_constraint (p
);
1106 enum reg_class cl
= reg_class_for_constraint (cn
);
1109 if (insn_extra_address_constraint (cn
))
1111 = (reg_class_subunion
1112 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1113 ADDRESS
, SCRATCH
)]);
1117 op_class
= reg_class_subunion
[op_class
][cl
];
1120 while ((p
+= len
), c
);
1124 /* If OP is a register, return the class of the register as per
1125 get_reg_class, otherwise return NO_REGS. */
1126 static inline enum reg_class
1127 get_op_class (rtx op
)
1129 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1132 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1133 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1134 SUBREG for VAL to make them equal. */
1136 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1138 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1140 /* Usually size of mem_pseudo is greater than val size but in
1141 rare cases it can be less as it can be defined by target
1142 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1145 val
= gen_lowpart_SUBREG (GET_MODE (mem_pseudo
),
1146 GET_CODE (val
) == SUBREG
1147 ? SUBREG_REG (val
) : val
);
1148 LRA_SUBREG_P (val
) = 1;
1152 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
1153 LRA_SUBREG_P (mem_pseudo
) = 1;
1156 return to_p
? gen_move_insn (mem_pseudo
, val
)
1157 : gen_move_insn (val
, mem_pseudo
);
1160 /* Process a special case insn (register move), return true if we
1161 don't need to process it anymore. INSN should be a single set
1162 insn. Set up that RTL was changed through CHANGE_P and macro
1163 SECONDARY_MEMORY_NEEDED says to use secondary memory through
1166 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
1169 rtx dest
, src
, dreg
, sreg
, new_reg
, scratch_reg
;
1171 enum reg_class dclass
, sclass
, secondary_class
;
1172 secondary_reload_info sri
;
1174 lra_assert (curr_insn_set
!= NULL_RTX
);
1175 dreg
= dest
= SET_DEST (curr_insn_set
);
1176 sreg
= src
= SET_SRC (curr_insn_set
);
1177 if (GET_CODE (dest
) == SUBREG
)
1178 dreg
= SUBREG_REG (dest
);
1179 if (GET_CODE (src
) == SUBREG
)
1180 sreg
= SUBREG_REG (src
);
1181 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
1183 sclass
= dclass
= NO_REGS
;
1185 dclass
= get_reg_class (REGNO (dreg
));
1186 gcc_assert (dclass
< LIM_REG_CLASSES
);
1187 if (dclass
== ALL_REGS
)
1188 /* ALL_REGS is used for new pseudos created by transformations
1189 like reload of SUBREG_REG (see function
1190 simplify_operand_subreg). We don't know their class yet. We
1191 should figure out the class from processing the insn
1192 constraints not in this fast path function. Even if ALL_REGS
1193 were a right class for the pseudo, secondary_... hooks usually
1194 are not define for ALL_REGS. */
1197 sclass
= get_reg_class (REGNO (sreg
));
1198 gcc_assert (sclass
< LIM_REG_CLASSES
);
1199 if (sclass
== ALL_REGS
)
1200 /* See comments above. */
1202 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
1204 #ifdef SECONDARY_MEMORY_NEEDED
1205 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
1206 #ifdef SECONDARY_MEMORY_NEEDED_MODE
1207 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
1208 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
1216 if (! REG_P (dreg
) || ! REG_P (sreg
))
1218 sri
.prev_sri
= NULL
;
1219 sri
.icode
= CODE_FOR_nothing
;
1221 secondary_class
= NO_REGS
;
1222 /* Set up hard register for a reload pseudo for hook
1223 secondary_reload because some targets just ignore unassigned
1224 pseudos in the hook. */
1225 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1227 dregno
= REGNO (dreg
);
1228 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1232 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1234 sregno
= REGNO (sreg
);
1235 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1239 if (sclass
!= NO_REGS
)
1241 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1242 (reg_class_t
) sclass
,
1243 GET_MODE (src
), &sri
);
1244 if (sclass
== NO_REGS
1245 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1246 && dclass
!= NO_REGS
))
1248 enum reg_class old_sclass
= secondary_class
;
1249 secondary_reload_info old_sri
= sri
;
1251 sri
.prev_sri
= NULL
;
1252 sri
.icode
= CODE_FOR_nothing
;
1255 = (enum reg_class
) targetm
.secondary_reload (true, src
,
1256 (reg_class_t
) dclass
,
1257 GET_MODE (src
), &sri
);
1258 /* Check the target hook consistency. */
1260 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1261 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1262 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1265 reg_renumber
[sregno
] = -1;
1267 reg_renumber
[dregno
] = -1;
1268 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1272 if (secondary_class
!= NO_REGS
)
1273 new_reg
= lra_create_new_reg_with_unique_value (GET_MODE (src
), NULL_RTX
,
1277 if (sri
.icode
== CODE_FOR_nothing
)
1278 lra_emit_move (new_reg
, src
);
1281 enum reg_class scratch_class
;
1283 scratch_class
= (reg_class_from_constraints
1284 (insn_data
[sri
.icode
].operand
[2].constraint
));
1285 scratch_reg
= (lra_create_new_reg_with_unique_value
1286 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1287 scratch_class
, "scratch"));
1288 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1291 before
= get_insns ();
1293 lra_process_new_insns (curr_insn
, before
, NULL
, "Inserting the move");
1294 if (new_reg
!= NULL_RTX
)
1295 SET_SRC (curr_insn_set
) = new_reg
;
1298 if (lra_dump_file
!= NULL
)
1300 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1301 dump_insn_slim (lra_dump_file
, curr_insn
);
1303 lra_set_insn_deleted (curr_insn
);
1309 /* The following data describe the result of process_alt_operands.
1310 The data are used in curr_insn_transform to generate reloads. */
1312 /* The chosen reg classes which should be used for the corresponding
1314 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1315 /* True if the operand should be the same as another operand and that
1316 other operand does not need a reload. */
1317 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1318 /* True if the operand does not need a reload. */
1319 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1320 /* True if the operand can be offsetable memory. */
1321 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1322 /* The number of an operand to which given operand can be matched to. */
1323 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1324 /* The number of elements in the following array. */
1325 static int goal_alt_dont_inherit_ops_num
;
1326 /* Numbers of operands whose reload pseudos should not be inherited. */
1327 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1328 /* True if the insn commutative operands should be swapped. */
1329 static bool goal_alt_swapped
;
1330 /* The chosen insn alternative. */
1331 static int goal_alt_number
;
1333 /* True if the corresponding operand is the result of an equivalence
1335 static bool equiv_substition_p
[MAX_RECOG_OPERANDS
];
1337 /* The following five variables are used to choose the best insn
1338 alternative. They reflect final characteristics of the best
1341 /* Number of necessary reloads and overall cost reflecting the
1342 previous value and other unpleasantness of the best alternative. */
1343 static int best_losers
, best_overall
;
1344 /* Overall number hard registers used for reloads. For example, on
1345 some targets we need 2 general registers to reload DFmode and only
1346 one floating point register. */
1347 static int best_reload_nregs
;
1348 /* Overall number reflecting distances of previous reloading the same
1349 value. The distances are counted from the current BB start. It is
1350 used to improve inheritance chances. */
1351 static int best_reload_sum
;
1353 /* True if the current insn should have no correspondingly input or
1355 static bool no_input_reloads_p
, no_output_reloads_p
;
1357 /* True if we swapped the commutative operands in the current
1359 static int curr_swapped
;
1361 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1362 register of class CL. Add any input reloads to list BEFORE. AFTER
1363 is nonnull if *LOC is an automodified value; handle that case by
1364 adding the required output reloads to list AFTER. Return true if
1365 the RTL was changed.
1367 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1368 register. Return false if the address register is correct. */
1370 process_addr_reg (rtx
*loc
, bool check_only_p
, rtx_insn
**before
, rtx_insn
**after
,
1374 enum reg_class rclass
, new_class
;
1378 bool subreg_p
, before_p
= false;
1380 subreg_p
= GET_CODE (*loc
) == SUBREG
;
1383 reg
= SUBREG_REG (*loc
);
1384 mode
= GET_MODE (reg
);
1386 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1387 between two registers with different classes, but there normally will
1388 be "mov" which transfers element of vector register into the general
1389 register, and this normally will be a subreg which should be reloaded
1390 as a whole. This is particularly likely to be triggered when
1391 -fno-split-wide-types specified. */
1393 || in_class_p (reg
, cl
, &new_class
)
1394 || GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (ptr_mode
))
1395 loc
= &SUBREG_REG (*loc
);
1399 mode
= GET_MODE (reg
);
1404 /* Always reload memory in an address even if the target supports
1406 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1411 regno
= REGNO (reg
);
1412 rclass
= get_reg_class (regno
);
1414 && (*loc
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
)
1416 if (lra_dump_file
!= NULL
)
1418 fprintf (lra_dump_file
,
1419 "Changing pseudo %d in address of insn %u on equiv ",
1420 REGNO (reg
), INSN_UID (curr_insn
));
1421 dump_value_slim (lra_dump_file
, *loc
, 1);
1422 fprintf (lra_dump_file
, "\n");
1424 *loc
= copy_rtx (*loc
);
1426 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1431 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1432 mode
, reg
, cl
, subreg_p
, "address", &new_reg
))
1435 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1439 lra_change_class (regno
, new_class
, " Change to", true);
1447 push_to_sequence (*before
);
1448 lra_emit_move (new_reg
, reg
);
1449 *before
= get_insns ();
1456 lra_emit_move (before_p
? copy_rtx (reg
) : reg
, new_reg
);
1458 *after
= get_insns ();
1464 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1465 the insn to be inserted before curr insn. AFTER returns the
1466 the insn to be inserted after curr insn. ORIGREG and NEWREG
1467 are the original reg and new reg for reload. */
1469 insert_move_for_subreg (rtx_insn
**before
, rtx_insn
**after
, rtx origreg
,
1474 push_to_sequence (*before
);
1475 lra_emit_move (newreg
, origreg
);
1476 *before
= get_insns ();
1482 lra_emit_move (origreg
, newreg
);
1484 *after
= get_insns ();
1489 static int valid_address_p (machine_mode mode
, rtx addr
, addr_space_t as
);
1490 static bool process_address (int, bool, rtx_insn
**, rtx_insn
**);
1492 /* Make reloads for subreg in operand NOP with internal subreg mode
1493 REG_MODE, add new reloads for further processing. Return true if
1494 any change was done. */
1496 simplify_operand_subreg (int nop
, machine_mode reg_mode
)
1499 rtx_insn
*before
, *after
;
1500 machine_mode mode
, innermode
;
1502 rtx operand
= *curr_id
->operand_loc
[nop
];
1503 enum reg_class regclass
;
1506 before
= after
= NULL
;
1508 if (GET_CODE (operand
) != SUBREG
)
1511 mode
= GET_MODE (operand
);
1512 reg
= SUBREG_REG (operand
);
1513 innermode
= GET_MODE (reg
);
1514 type
= curr_static_id
->operand
[nop
].type
;
1517 const bool addr_was_valid
1518 = valid_address_p (innermode
, XEXP (reg
, 0), MEM_ADDR_SPACE (reg
));
1519 alter_subreg (curr_id
->operand_loc
[nop
], false);
1520 rtx subst
= *curr_id
->operand_loc
[nop
];
1521 lra_assert (MEM_P (subst
));
1524 || valid_address_p (GET_MODE (subst
), XEXP (subst
, 0),
1525 MEM_ADDR_SPACE (subst
))
1526 || ((get_constraint_type (lookup_constraint
1527 (curr_static_id
->operand
[nop
].constraint
))
1528 != CT_SPECIAL_MEMORY
)
1529 /* We still can reload address and if the address is
1530 valid, we can remove subreg without reloading its
1532 && valid_address_p (GET_MODE (subst
),
1534 [ira_class_hard_regs
1535 [base_reg_class (GET_MODE (subst
),
1536 MEM_ADDR_SPACE (subst
),
1537 ADDRESS
, SCRATCH
)][0]],
1538 MEM_ADDR_SPACE (subst
))))
1540 /* If we change the address for a paradoxical subreg of memory, the
1541 new address might violate the necessary alignment or the access
1542 might be slow; take this into consideration. We need not worry
1543 about accesses beyond allocated memory for paradoxical memory
1544 subregs as we don't substitute such equiv memory (see processing
1545 equivalences in function lra_constraints) and because for spilled
1546 pseudos we allocate stack memory enough for the biggest
1547 corresponding paradoxical subreg.
1549 However, do not blindly simplify a (subreg (mem ...)) for
1550 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1551 data into a register when the inner is narrower than outer or
1552 missing important data from memory when the inner is wider than
1553 outer. This rule only applies to modes that are no wider than
1555 if (!(GET_MODE_PRECISION (mode
) != GET_MODE_PRECISION (innermode
)
1556 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1557 && GET_MODE_SIZE (innermode
) <= UNITS_PER_WORD
1558 && WORD_REGISTER_OPERATIONS
)
1559 && (!(MEM_ALIGN (subst
) < GET_MODE_ALIGNMENT (mode
)
1560 && SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (subst
)))
1561 || (MEM_ALIGN (reg
) < GET_MODE_ALIGNMENT (innermode
)
1562 && SLOW_UNALIGNED_ACCESS (innermode
, MEM_ALIGN (reg
)))))
1565 *curr_id
->operand_loc
[nop
] = operand
;
1567 /* But if the address was not valid, we cannot reload the MEM without
1568 reloading the address first. */
1569 if (!addr_was_valid
)
1570 process_address (nop
, false, &before
, &after
);
1572 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1573 enum reg_class rclass
1574 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1575 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, innermode
,
1576 reg
, rclass
, TRUE
, "slow mem", &new_reg
))
1578 bool insert_before
, insert_after
;
1579 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1581 insert_before
= (type
!= OP_OUT
1582 || partial_subreg_p (mode
, innermode
));
1583 insert_after
= type
!= OP_IN
;
1584 insert_move_for_subreg (insert_before
? &before
: NULL
,
1585 insert_after
? &after
: NULL
,
1588 SUBREG_REG (operand
) = new_reg
;
1590 /* Convert to MODE. */
1593 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1594 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1595 rclass
, TRUE
, "slow mem", &new_reg
))
1597 bool insert_before
, insert_after
;
1598 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1600 insert_before
= type
!= OP_OUT
;
1601 insert_after
= type
!= OP_IN
;
1602 insert_move_for_subreg (insert_before
? &before
: NULL
,
1603 insert_after
? &after
: NULL
,
1606 *curr_id
->operand_loc
[nop
] = new_reg
;
1607 lra_process_new_insns (curr_insn
, before
, after
,
1608 "Inserting slow mem reload");
1612 /* If the address was valid and became invalid, prefer to reload
1613 the memory. Typical case is when the index scale should
1614 correspond the memory. */
1615 *curr_id
->operand_loc
[nop
] = operand
;
1616 /* Do not return false here as the MEM_P (reg) will be processed
1617 later in this function. */
1619 else if (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
1621 alter_subreg (curr_id
->operand_loc
[nop
], false);
1624 else if (CONSTANT_P (reg
))
1626 /* Try to simplify subreg of constant. It is usually result of
1627 equivalence substitution. */
1628 if (innermode
== VOIDmode
1629 && (innermode
= original_subreg_reg_mode
[nop
]) == VOIDmode
)
1630 innermode
= curr_static_id
->operand
[nop
].mode
;
1631 if ((new_reg
= simplify_subreg (mode
, reg
, innermode
,
1632 SUBREG_BYTE (operand
))) != NULL_RTX
)
1634 *curr_id
->operand_loc
[nop
] = new_reg
;
1638 /* Put constant into memory when we have mixed modes. It generates
1639 a better code in most cases as it does not need a secondary
1640 reload memory. It also prevents LRA looping when LRA is using
1641 secondary reload memory again and again. */
1642 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1643 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1645 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1646 alter_subreg (curr_id
->operand_loc
[nop
], false);
1649 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1650 if there may be a problem accessing OPERAND in the outer
1653 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1654 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1655 /* Don't reload paradoxical subregs because we could be looping
1656 having repeatedly final regno out of hard regs range. */
1657 && (hard_regno_nregs
[hard_regno
][innermode
]
1658 >= hard_regno_nregs
[hard_regno
][mode
])
1659 && simplify_subreg_regno (hard_regno
, innermode
,
1660 SUBREG_BYTE (operand
), mode
) < 0
1661 /* Don't reload subreg for matching reload. It is actually
1662 valid subreg in LRA. */
1663 && ! LRA_SUBREG_P (operand
))
1664 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1666 enum reg_class rclass
;
1669 /* There is a big probability that we will get the same class
1670 for the new pseudo and we will get the same insn which
1671 means infinite looping. So spill the new pseudo. */
1674 /* The class will be defined later in curr_insn_transform. */
1676 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1678 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1679 rclass
, TRUE
, "subreg reg", &new_reg
))
1681 bool insert_before
, insert_after
;
1682 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1684 insert_before
= (type
!= OP_OUT
1685 || GET_MODE_SIZE (innermode
) > GET_MODE_SIZE (mode
));
1686 insert_after
= (type
!= OP_IN
);
1687 insert_move_for_subreg (insert_before
? &before
: NULL
,
1688 insert_after
? &after
: NULL
,
1691 SUBREG_REG (operand
) = new_reg
;
1692 lra_process_new_insns (curr_insn
, before
, after
,
1693 "Inserting subreg reload");
1696 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1697 IRA allocates hardreg to the inner pseudo reg according to its mode
1698 instead of the outermode, so the size of the hardreg may not be enough
1699 to contain the outermode operand, in that case we may need to insert
1700 reload for the reg. For the following two types of paradoxical subreg,
1701 we need to insert reload:
1702 1. If the op_type is OP_IN, and the hardreg could not be paired with
1703 other hardreg to contain the outermode operand
1704 (checked by in_hard_reg_set_p), we need to insert the reload.
1705 2. If the op_type is OP_OUT or OP_INOUT.
1707 Here is a paradoxical subreg example showing how the reload is generated:
1709 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1710 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1712 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1713 here, if reg107 is assigned to hardreg R15, because R15 is the last
1714 hardreg, compiler cannot find another hardreg to pair with R15 to
1715 contain TImode data. So we insert a TImode reload reg180 for it.
1716 After reload is inserted:
1718 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1719 (reg:DI 107 [ __comp ])) -1
1720 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1721 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1723 Two reload hard registers will be allocated to reg180 to save TImode data
1725 else if (REG_P (reg
)
1726 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1727 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1728 && (hard_regno_nregs
[hard_regno
][innermode
]
1729 < hard_regno_nregs
[hard_regno
][mode
])
1730 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1732 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1735 /* The class will be defined later in curr_insn_transform. */
1736 enum reg_class rclass
1737 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1739 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1740 rclass
, TRUE
, "paradoxical subreg", &new_reg
))
1743 bool insert_before
, insert_after
;
1745 PUT_MODE (new_reg
, mode
);
1746 subreg
= gen_lowpart_SUBREG (innermode
, new_reg
);
1747 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1749 insert_before
= (type
!= OP_OUT
);
1750 insert_after
= (type
!= OP_IN
);
1751 insert_move_for_subreg (insert_before
? &before
: NULL
,
1752 insert_after
? &after
: NULL
,
1755 SUBREG_REG (operand
) = new_reg
;
1756 lra_process_new_insns (curr_insn
, before
, after
,
1757 "Inserting paradoxical subreg reload");
1763 /* Return TRUE if X refers for a hard register from SET. */
1765 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1767 int i
, j
, x_hard_regno
;
1774 code
= GET_CODE (x
);
1775 mode
= GET_MODE (x
);
1779 code
= GET_CODE (x
);
1780 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1781 mode
= GET_MODE (x
);
1786 x_hard_regno
= get_hard_regno (x
, true);
1787 return (x_hard_regno
>= 0
1788 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1792 struct address_info ad
;
1794 decompose_mem_address (&ad
, x
);
1795 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1797 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1800 fmt
= GET_RTX_FORMAT (code
);
1801 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1805 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1808 else if (fmt
[i
] == 'E')
1810 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1811 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1818 /* Return true if OP is a spilled pseudo. */
1820 spilled_pseudo_p (rtx op
)
1823 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1826 /* Return true if X is a general constant. */
1828 general_constant_p (rtx x
)
1830 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1834 reg_in_class_p (rtx reg
, enum reg_class cl
)
1837 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1838 return in_class_p (reg
, cl
, NULL
);
1841 /* Return true if SET of RCLASS contains no hard regs which can be
1844 prohibited_class_reg_set_mode_p (enum reg_class rclass
,
1850 lra_assert (hard_reg_set_subset_p (reg_class_contents
[rclass
], set
));
1851 COPY_HARD_REG_SET (temp
, set
);
1852 AND_COMPL_HARD_REG_SET (temp
, lra_no_alloc_regs
);
1853 return (hard_reg_set_subset_p
1854 (temp
, ira_prohibited_class_mode_regs
[rclass
][mode
]));
1858 /* Used to check validity info about small class input operands. It
1859 should be incremented at start of processing an insn
1861 static unsigned int curr_small_class_check
= 0;
1863 /* Update number of used inputs of class OP_CLASS for operand NOP.
1864 Return true if we have more such class operands than the number of
1867 update_and_check_small_class_inputs (int nop
, enum reg_class op_class
)
1869 static unsigned int small_class_check
[LIM_REG_CLASSES
];
1870 static int small_class_input_nums
[LIM_REG_CLASSES
];
1872 if (SMALL_REGISTER_CLASS_P (op_class
)
1873 /* We are interesting in classes became small because of fixing
1874 some hard regs, e.g. by an user through GCC options. */
1875 && hard_reg_set_intersect_p (reg_class_contents
[op_class
],
1877 && (curr_static_id
->operand
[nop
].type
!= OP_OUT
1878 || curr_static_id
->operand
[nop
].early_clobber
))
1880 if (small_class_check
[op_class
] == curr_small_class_check
)
1881 small_class_input_nums
[op_class
]++;
1884 small_class_check
[op_class
] = curr_small_class_check
;
1885 small_class_input_nums
[op_class
] = 1;
1887 if (small_class_input_nums
[op_class
] > ira_class_hard_regs_num
[op_class
])
1893 /* Major function to choose the current insn alternative and what
1894 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1895 negative we should consider only this alternative. Return false if
1896 we can not choose the alternative or find how to reload the
1899 process_alt_operands (int only_alternative
)
1902 int nop
, overall
, nalt
;
1903 int n_alternatives
= curr_static_id
->n_alternatives
;
1904 int n_operands
= curr_static_id
->n_operands
;
1905 /* LOSERS counts the operands that don't fit this alternative and
1906 would require loading. */
1909 /* REJECT is a count of how undesirable this alternative says it is
1910 if any reloading is required. If the alternative matches exactly
1911 then REJECT is ignored, but otherwise it gets this much counted
1912 against it in addition to the reloading needed. */
1914 /* This is defined by '!' or '?' alternative constraint and added to
1915 reject. But in some cases it can be ignored. */
1918 /* The number of elements in the following array. */
1919 int early_clobbered_regs_num
;
1920 /* Numbers of operands which are early clobber registers. */
1921 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1922 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1923 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1924 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1925 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1926 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1927 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1928 /* The number of elements in the following array. */
1929 int curr_alt_dont_inherit_ops_num
;
1930 /* Numbers of operands whose reload pseudos should not be inherited. */
1931 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1933 /* The register when the operand is a subreg of register, otherwise the
1935 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1936 /* The register if the operand is a register or subreg of register,
1938 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1939 int hard_regno
[MAX_RECOG_OPERANDS
];
1940 machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1941 int reload_nregs
, reload_sum
;
1945 /* Calculate some data common for all alternatives to speed up the
1947 for (nop
= 0; nop
< n_operands
; nop
++)
1951 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1952 /* The real hard regno of the operand after the allocation. */
1953 hard_regno
[nop
] = get_hard_regno (op
, true);
1955 operand_reg
[nop
] = reg
= op
;
1956 biggest_mode
[nop
] = GET_MODE (op
);
1957 if (GET_CODE (op
) == SUBREG
)
1959 operand_reg
[nop
] = reg
= SUBREG_REG (op
);
1960 if (GET_MODE_SIZE (biggest_mode
[nop
])
1961 < GET_MODE_SIZE (GET_MODE (reg
)))
1962 biggest_mode
[nop
] = GET_MODE (reg
);
1965 operand_reg
[nop
] = NULL_RTX
;
1966 else if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1967 || ((int) REGNO (reg
)
1968 == lra_get_elimination_hard_regno (REGNO (reg
))))
1969 no_subreg_reg_operand
[nop
] = reg
;
1971 operand_reg
[nop
] = no_subreg_reg_operand
[nop
]
1972 /* Just use natural mode for elimination result. It should
1973 be enough for extra constraints hooks. */
1974 = regno_reg_rtx
[hard_regno
[nop
]];
1977 /* The constraints are made of several alternatives. Each operand's
1978 constraint looks like foo,bar,... with commas separating the
1979 alternatives. The first alternatives for all operands go
1980 together, the second alternatives go together, etc.
1982 First loop over alternatives. */
1983 alternative_mask preferred
= curr_id
->preferred_alternatives
;
1984 if (only_alternative
>= 0)
1985 preferred
&= ALTERNATIVE_BIT (only_alternative
);
1987 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1989 /* Loop over operands for one constraint alternative. */
1990 if (!TEST_BIT (preferred
, nalt
))
1993 curr_small_class_check
++;
1994 overall
= losers
= addr_losers
= 0;
1995 static_reject
= reject
= reload_nregs
= reload_sum
= 0;
1996 for (nop
= 0; nop
< n_operands
; nop
++)
1998 int inc
= (curr_static_id
1999 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
2000 if (lra_dump_file
!= NULL
&& inc
!= 0)
2001 fprintf (lra_dump_file
,
2002 " Staticly defined alt reject+=%d\n", inc
);
2003 static_reject
+= inc
;
2005 reject
+= static_reject
;
2006 early_clobbered_regs_num
= 0;
2008 for (nop
= 0; nop
< n_operands
; nop
++)
2012 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
2013 bool win
, did_match
, offmemok
, early_clobber_p
;
2014 /* false => this operand can be reloaded somehow for this
2017 /* true => this operand can be reloaded if the alternative
2020 /* True if a constant forced into memory would be OK for
2023 enum reg_class this_alternative
, this_costly_alternative
;
2024 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
2025 bool this_alternative_match_win
, this_alternative_win
;
2026 bool this_alternative_offmemok
;
2029 enum constraint_num cn
;
2031 opalt_num
= nalt
* n_operands
+ nop
;
2032 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
2034 /* Fast track for no constraints at all. */
2035 curr_alt
[nop
] = NO_REGS
;
2036 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
2037 curr_alt_win
[nop
] = true;
2038 curr_alt_match_win
[nop
] = false;
2039 curr_alt_offmemok
[nop
] = false;
2040 curr_alt_matches
[nop
] = -1;
2044 op
= no_subreg_reg_operand
[nop
];
2045 mode
= curr_operand_mode
[nop
];
2047 win
= did_match
= winreg
= offmemok
= constmemok
= false;
2050 early_clobber_p
= false;
2051 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
2053 this_costly_alternative
= this_alternative
= NO_REGS
;
2054 /* We update set of possible hard regs besides its class
2055 because reg class might be inaccurate. For example,
2056 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2057 is translated in HI_REGS because classes are merged by
2058 pairs and there is no accurate intermediate class. */
2059 CLEAR_HARD_REG_SET (this_alternative_set
);
2060 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
2061 this_alternative_win
= false;
2062 this_alternative_match_win
= false;
2063 this_alternative_offmemok
= false;
2064 this_alternative_matches
= -1;
2066 /* An empty constraint should be excluded by the fast
2068 lra_assert (*p
!= 0 && *p
!= ',');
2071 /* Scan this alternative's specs for this operand; set WIN
2072 if the operand fits any letter in this alternative.
2073 Otherwise, clear BADOP if this operand could fit some
2074 letter after reloads, or set WINREG if this operand could
2075 fit after reloads provided the constraint allows some
2080 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
2090 early_clobber_p
= true;
2094 op_reject
+= LRA_MAX_REJECT
;
2097 op_reject
+= LRA_LOSER_COST_FACTOR
;
2101 /* Ignore rest of this alternative. */
2105 case '0': case '1': case '2': case '3': case '4':
2106 case '5': case '6': case '7': case '8': case '9':
2111 m
= strtoul (p
, &end
, 10);
2114 lra_assert (nop
> m
);
2116 this_alternative_matches
= m
;
2117 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
], false);
2118 /* We are supposed to match a previous operand.
2119 If we do, we win if that one did. If we do
2120 not, count both of the operands as losers.
2121 (This is too conservative, since most of the
2122 time only a single reload insn will be needed
2123 to make the two operands win. As a result,
2124 this alternative may be rejected when it is
2125 actually desirable.) */
2127 if (operands_match_p (*curr_id
->operand_loc
[nop
],
2128 *curr_id
->operand_loc
[m
], m_hregno
))
2130 /* We should reject matching of an early
2131 clobber operand if the matching operand is
2132 not dying in the insn. */
2133 if (! curr_static_id
->operand
[m
].early_clobber
2134 || operand_reg
[nop
] == NULL_RTX
2135 || (find_regno_note (curr_insn
, REG_DEAD
,
2137 || REGNO (op
) == REGNO (operand_reg
[m
])))
2142 /* If we are matching a non-offsettable
2143 address where an offsettable address was
2144 expected, then we must reject this
2145 combination, because we can't reload
2147 if (curr_alt_offmemok
[m
]
2148 && MEM_P (*curr_id
->operand_loc
[m
])
2149 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
2154 /* Operands don't match. Both operands must
2155 allow a reload register, otherwise we
2156 cannot make them match. */
2157 if (curr_alt
[m
] == NO_REGS
)
2159 /* Retroactively mark the operand we had to
2160 match as a loser, if it wasn't already and
2161 it wasn't matched to a register constraint
2162 (e.g it might be matched by memory). */
2164 && (operand_reg
[m
] == NULL_RTX
2165 || hard_regno
[m
] < 0))
2169 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
2170 [GET_MODE (*curr_id
->operand_loc
[m
])]);
2173 /* Prefer matching earlyclobber alternative as
2174 it results in less hard regs required for
2175 the insn than a non-matching earlyclobber
2177 if (curr_static_id
->operand
[m
].early_clobber
)
2179 if (lra_dump_file
!= NULL
)
2182 " %d Matching earlyclobber alt:"
2187 /* Otherwise we prefer no matching
2188 alternatives because it gives more freedom
2190 else if (operand_reg
[nop
] == NULL_RTX
2191 || (find_regno_note (curr_insn
, REG_DEAD
,
2192 REGNO (operand_reg
[nop
]))
2195 if (lra_dump_file
!= NULL
)
2198 " %d Matching alt: reject+=2\n",
2203 /* If we have to reload this operand and some
2204 previous operand also had to match the same
2205 thing as this operand, we don't know how to do
2207 if (!match_p
|| !curr_alt_win
[m
])
2209 for (i
= 0; i
< nop
; i
++)
2210 if (curr_alt_matches
[i
] == m
)
2218 /* This can be fixed with reloads if the operand
2219 we are supposed to match can be fixed with
2222 this_alternative
= curr_alt
[m
];
2223 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
2224 winreg
= this_alternative
!= NO_REGS
;
2230 || general_constant_p (op
)
2231 || spilled_pseudo_p (op
))
2237 cn
= lookup_constraint (p
);
2238 switch (get_constraint_type (cn
))
2241 cl
= reg_class_for_constraint (cn
);
2247 if (CONST_INT_P (op
)
2248 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
2254 && satisfies_memory_constraint_p (op
, cn
))
2256 else if (spilled_pseudo_p (op
))
2259 /* If we didn't already win, we can reload constants
2260 via force_const_mem or put the pseudo value into
2261 memory, or make other memory by reloading the
2262 address like for 'o'. */
2263 if (CONST_POOL_OK_P (mode
, op
)
2264 || MEM_P (op
) || REG_P (op
)
2265 /* We can restore the equiv insn by a
2267 || equiv_substition_p
[nop
])
2274 /* If we didn't already win, we can reload the address
2275 into a base register. */
2276 if (satisfies_address_constraint_p (op
, cn
))
2278 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2284 if (constraint_satisfied_p (op
, cn
))
2288 case CT_SPECIAL_MEMORY
:
2290 && satisfies_memory_constraint_p (op
, cn
))
2292 else if (spilled_pseudo_p (op
))
2299 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2300 IOR_HARD_REG_SET (this_alternative_set
,
2301 reg_class_contents
[cl
]);
2304 this_costly_alternative
2305 = reg_class_subunion
[this_costly_alternative
][cl
];
2306 IOR_HARD_REG_SET (this_costly_alternative_set
,
2307 reg_class_contents
[cl
]);
2309 if (mode
== BLKmode
)
2314 if (hard_regno
[nop
] >= 0
2315 && in_hard_reg_set_p (this_alternative_set
,
2316 mode
, hard_regno
[nop
]))
2318 else if (hard_regno
[nop
] < 0
2319 && in_class_p (op
, this_alternative
, NULL
))
2324 if (c
!= ' ' && c
!= '\t')
2325 costly_p
= c
== '*';
2327 while ((p
+= len
), c
);
2329 scratch_p
= (operand_reg
[nop
] != NULL_RTX
2330 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
2331 /* Record which operands fit this alternative. */
2334 this_alternative_win
= true;
2335 if (operand_reg
[nop
] != NULL_RTX
)
2337 if (hard_regno
[nop
] >= 0)
2339 if (in_hard_reg_set_p (this_costly_alternative_set
,
2340 mode
, hard_regno
[nop
]))
2342 if (lra_dump_file
!= NULL
)
2343 fprintf (lra_dump_file
,
2344 " %d Costly set: reject++\n",
2351 /* Prefer won reg to spilled pseudo under other
2352 equal conditions for possibe inheritance. */
2355 if (lra_dump_file
!= NULL
)
2358 " %d Non pseudo reload: reject++\n",
2362 if (in_class_p (operand_reg
[nop
],
2363 this_costly_alternative
, NULL
))
2365 if (lra_dump_file
!= NULL
)
2368 " %d Non pseudo costly reload:"
2374 /* We simulate the behavior of old reload here.
2375 Although scratches need hard registers and it
2376 might result in spilling other pseudos, no reload
2377 insns are generated for the scratches. So it
2378 might cost something but probably less than old
2379 reload pass believes. */
2382 if (lra_dump_file
!= NULL
)
2383 fprintf (lra_dump_file
,
2384 " %d Scratch win: reject+=2\n",
2391 this_alternative_match_win
= true;
2394 int const_to_mem
= 0;
2397 reject
+= op_reject
;
2398 /* Never do output reload of stack pointer. It makes
2399 impossible to do elimination when SP is changed in
2401 if (op
== stack_pointer_rtx
&& ! frame_pointer_needed
2402 && curr_static_id
->operand
[nop
].type
!= OP_IN
)
2405 /* If this alternative asks for a specific reg class, see if there
2406 is at least one allocatable register in that class. */
2408 = (this_alternative
== NO_REGS
2409 || (hard_reg_set_subset_p
2410 (reg_class_contents
[this_alternative
],
2411 lra_no_alloc_regs
)));
2413 /* For asms, verify that the class for this alternative is possible
2414 for the mode that is specified. */
2415 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2418 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2419 if (targetm
.hard_regno_mode_ok (i
, mode
)
2420 && in_hard_reg_set_p (reg_class_contents
[this_alternative
],
2423 if (i
== FIRST_PSEUDO_REGISTER
)
2427 /* If this operand accepts a register, and if the
2428 register class has at least one allocatable register,
2429 then this operand can be reloaded. */
2430 if (winreg
&& !no_regs_p
)
2435 if (lra_dump_file
!= NULL
)
2436 fprintf (lra_dump_file
,
2437 " alt=%d: Bad operand -- refuse\n",
2442 if (this_alternative
!= NO_REGS
)
2444 HARD_REG_SET available_regs
;
2446 COPY_HARD_REG_SET (available_regs
,
2447 reg_class_contents
[this_alternative
]);
2448 AND_COMPL_HARD_REG_SET
2450 ira_prohibited_class_mode_regs
[this_alternative
][mode
]);
2451 AND_COMPL_HARD_REG_SET (available_regs
, lra_no_alloc_regs
);
2452 if (hard_reg_set_empty_p (available_regs
))
2454 /* There are no hard regs holding a value of given
2458 this_alternative
= NO_REGS
;
2459 if (lra_dump_file
!= NULL
)
2460 fprintf (lra_dump_file
,
2461 " %d Using memory because of"
2462 " a bad mode: reject+=2\n",
2468 if (lra_dump_file
!= NULL
)
2469 fprintf (lra_dump_file
,
2470 " alt=%d: Wrong mode -- refuse\n",
2477 /* If not assigned pseudo has a class which a subset of
2478 required reg class, it is a less costly alternative
2479 as the pseudo still can get a hard reg of necessary
2481 if (! no_regs_p
&& REG_P (op
) && hard_regno
[nop
] < 0
2482 && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2483 && ira_class_subset_p
[this_alternative
][cl
])
2485 if (lra_dump_file
!= NULL
)
2488 " %d Super set class reg: reject-=3\n", nop
);
2492 this_alternative_offmemok
= offmemok
;
2493 if (this_costly_alternative
!= NO_REGS
)
2495 if (lra_dump_file
!= NULL
)
2496 fprintf (lra_dump_file
,
2497 " %d Costly loser: reject++\n", nop
);
2500 /* If the operand is dying, has a matching constraint,
2501 and satisfies constraints of the matched operand
2502 which failed to satisfy the own constraints, most probably
2503 the reload for this operand will be gone. */
2504 if (this_alternative_matches
>= 0
2505 && !curr_alt_win
[this_alternative_matches
]
2507 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2508 && (hard_regno
[nop
] >= 0
2509 ? in_hard_reg_set_p (this_alternative_set
,
2510 mode
, hard_regno
[nop
])
2511 : in_class_p (op
, this_alternative
, NULL
)))
2513 if (lra_dump_file
!= NULL
)
2516 " %d Dying matched operand reload: reject++\n",
2522 /* Strict_low_part requires to reload the register
2523 not the sub-register. In this case we should
2524 check that a final reload hard reg can hold the
2526 if (curr_static_id
->operand
[nop
].strict_low
2528 && hard_regno
[nop
] < 0
2529 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2530 && ira_class_hard_regs_num
[this_alternative
] > 0
2531 && (!targetm
.hard_regno_mode_ok
2532 (ira_class_hard_regs
[this_alternative
][0],
2533 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2535 if (lra_dump_file
!= NULL
)
2538 " alt=%d: Strict low subreg reload -- refuse\n",
2544 if (operand_reg
[nop
] != NULL_RTX
2545 /* Output operands and matched input operands are
2546 not inherited. The following conditions do not
2547 exactly describe the previous statement but they
2548 are pretty close. */
2549 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2550 && (this_alternative_matches
< 0
2551 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2553 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2557 /* The value of reload_sum has sense only if we
2558 process insns in their order. It happens only on
2559 the first constraints sub-pass when we do most of
2561 if (lra_constraint_iter
== 1 && last_reload
> bb_reload_num
)
2562 reload_sum
+= last_reload
- bb_reload_num
;
2564 /* If this is a constant that is reloaded into the
2565 desired class by copying it to memory first, count
2566 that as another reload. This is consistent with
2567 other code and is required to avoid choosing another
2568 alternative when the constant is moved into memory.
2569 Note that the test here is precisely the same as in
2570 the code below that calls force_const_mem. */
2571 if (CONST_POOL_OK_P (mode
, op
)
2572 && ((targetm
.preferred_reload_class
2573 (op
, this_alternative
) == NO_REGS
)
2574 || no_input_reloads_p
))
2581 /* Alternative loses if it requires a type of reload not
2582 permitted for this insn. We can always reload
2583 objects with a REG_UNUSED note. */
2584 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2585 && no_output_reloads_p
2586 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2587 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2588 && no_input_reloads_p
&& ! const_to_mem
)
2589 || (this_alternative_matches
>= 0
2590 && (no_input_reloads_p
2591 || (no_output_reloads_p
2592 && (curr_static_id
->operand
2593 [this_alternative_matches
].type
!= OP_IN
)
2594 && ! find_reg_note (curr_insn
, REG_UNUSED
,
2595 no_subreg_reg_operand
2596 [this_alternative_matches
])))))
2598 if (lra_dump_file
!= NULL
)
2601 " alt=%d: No input/otput reload -- refuse\n",
2606 /* Alternative loses if it required class pseudo can not
2607 hold value of required mode. Such insns can be
2608 described by insn definitions with mode iterators. */
2609 if (GET_MODE (*curr_id
->operand_loc
[nop
]) != VOIDmode
2610 && ! hard_reg_set_empty_p (this_alternative_set
)
2611 /* It is common practice for constraints to use a
2612 class which does not have actually enough regs to
2613 hold the value (e.g. x86 AREG for mode requiring
2614 more one general reg). Therefore we have 2
2615 conditions to check that the reload pseudo can
2616 not hold the mode value. */
2617 && (!targetm
.hard_regno_mode_ok
2618 (ira_class_hard_regs
[this_alternative
][0],
2619 GET_MODE (*curr_id
->operand_loc
[nop
])))
2620 /* The above condition is not enough as the first
2621 reg in ira_class_hard_regs can be not aligned for
2622 multi-words mode values. */
2623 && (prohibited_class_reg_set_mode_p
2624 (this_alternative
, this_alternative_set
,
2625 GET_MODE (*curr_id
->operand_loc
[nop
]))))
2627 if (lra_dump_file
!= NULL
)
2628 fprintf (lra_dump_file
,
2629 " alt=%d: reload pseudo for op %d "
2630 " can not hold the mode value -- refuse\n",
2635 /* Check strong discouragement of reload of non-constant
2636 into class THIS_ALTERNATIVE. */
2637 if (! CONSTANT_P (op
) && ! no_regs_p
2638 && (targetm
.preferred_reload_class
2639 (op
, this_alternative
) == NO_REGS
2640 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2641 && (targetm
.preferred_output_reload_class
2642 (op
, this_alternative
) == NO_REGS
))))
2644 if (lra_dump_file
!= NULL
)
2645 fprintf (lra_dump_file
,
2646 " %d Non-prefered reload: reject+=%d\n",
2647 nop
, LRA_MAX_REJECT
);
2648 reject
+= LRA_MAX_REJECT
;
2651 if (! (MEM_P (op
) && offmemok
)
2652 && ! (const_to_mem
&& constmemok
))
2654 /* We prefer to reload pseudos over reloading other
2655 things, since such reloads may be able to be
2656 eliminated later. So bump REJECT in other cases.
2657 Don't do this in the case where we are forcing a
2658 constant into memory and it will then win since
2659 we don't want to have a different alternative
2661 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2663 if (lra_dump_file
!= NULL
)
2666 " %d Non-pseudo reload: reject+=2\n",
2673 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2675 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2677 if (lra_dump_file
!= NULL
)
2680 " %d Small class reload: reject+=%d\n",
2681 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2682 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2686 /* We are trying to spill pseudo into memory. It is
2687 usually more costly than moving to a hard register
2688 although it might takes the same number of
2691 Non-pseudo spill may happen also. Suppose a target allows both
2692 register and memory in the operand constraint alternatives,
2693 then it's typical that an eliminable register has a substition
2694 of "base + offset" which can either be reloaded by a simple
2695 "new_reg <= base + offset" which will match the register
2696 constraint, or a similar reg addition followed by further spill
2697 to and reload from memory which will match the memory
2698 constraint, but this memory spill will be much more costly
2701 Code below increases the reject for both pseudo and non-pseudo
2704 && !(MEM_P (op
) && offmemok
)
2705 && !(REG_P (op
) && hard_regno
[nop
] < 0))
2707 if (lra_dump_file
!= NULL
)
2710 " %d Spill %spseudo into memory: reject+=3\n",
2711 nop
, REG_P (op
) ? "" : "Non-");
2713 if (VECTOR_MODE_P (mode
))
2715 /* Spilling vectors into memory is usually more
2716 costly as they contain big values. */
2717 if (lra_dump_file
!= NULL
)
2720 " %d Spill vector pseudo: reject+=2\n",
2726 /* When we use an operand requiring memory in given
2727 alternative, the insn should write *and* read the
2728 value to/from memory it is costly in comparison with
2729 an insn alternative which does not use memory
2730 (e.g. register or immediate operand). We exclude
2731 memory operand for such case as we can satisfy the
2732 memory constraints by reloading address. */
2733 if (no_regs_p
&& offmemok
&& !MEM_P (op
))
2735 if (lra_dump_file
!= NULL
)
2738 " Using memory insn operand %d: reject+=3\n",
2743 #ifdef SECONDARY_MEMORY_NEEDED
2744 /* If reload requires moving value through secondary
2745 memory, it will need one more insn at least. */
2746 if (this_alternative
!= NO_REGS
2747 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2748 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2749 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2751 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2752 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2756 /* Input reloads can be inherited more often than output
2757 reloads can be removed, so penalize output
2759 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2761 if (lra_dump_file
!= NULL
)
2764 " %d Non input pseudo reload: reject++\n",
2769 if (MEM_P (op
) && offmemok
)
2771 else if (curr_static_id
->operand
[nop
].type
== OP_INOUT
)
2773 if (lra_dump_file
!= NULL
)
2776 " %d Input/Output reload: reject+=%d\n",
2777 nop
, LRA_LOSER_COST_FACTOR
);
2778 reject
+= LRA_LOSER_COST_FACTOR
;
2782 if (early_clobber_p
&& ! scratch_p
)
2784 if (lra_dump_file
!= NULL
)
2785 fprintf (lra_dump_file
,
2786 " %d Early clobber: reject++\n", nop
);
2789 /* ??? We check early clobbers after processing all operands
2790 (see loop below) and there we update the costs more.
2791 Should we update the cost (may be approximately) here
2792 because of early clobber register reloads or it is a rare
2793 or non-important thing to be worth to do it. */
2794 overall
= (losers
* LRA_LOSER_COST_FACTOR
+ reject
2795 - (addr_losers
== losers
? static_reject
: 0));
2796 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2798 if (lra_dump_file
!= NULL
)
2799 fprintf (lra_dump_file
,
2800 " alt=%d,overall=%d,losers=%d -- refuse\n",
2801 nalt
, overall
, losers
);
2805 if (update_and_check_small_class_inputs (nop
, this_alternative
))
2807 if (lra_dump_file
!= NULL
)
2808 fprintf (lra_dump_file
,
2809 " alt=%d, not enough small class regs -- refuse\n",
2813 curr_alt
[nop
] = this_alternative
;
2814 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2815 curr_alt_win
[nop
] = this_alternative_win
;
2816 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2817 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2818 curr_alt_matches
[nop
] = this_alternative_matches
;
2820 if (this_alternative_matches
>= 0
2821 && !did_match
&& !this_alternative_win
)
2822 curr_alt_win
[this_alternative_matches
] = false;
2824 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2825 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2828 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2829 /* Prevent processing non-move insns. */
2830 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2831 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2832 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2833 && REG_P (no_subreg_reg_operand
[0])
2834 && REG_P (no_subreg_reg_operand
[1])
2835 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2836 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2837 || (! curr_alt_win
[0] && curr_alt_win
[1]
2838 && REG_P (no_subreg_reg_operand
[1])
2839 /* Check that we reload memory not the memory
2841 && ! (curr_alt_offmemok
[0]
2842 && MEM_P (no_subreg_reg_operand
[0]))
2843 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2844 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2845 && REG_P (no_subreg_reg_operand
[0])
2846 /* Check that we reload memory not the memory
2848 && ! (curr_alt_offmemok
[1]
2849 && MEM_P (no_subreg_reg_operand
[1]))
2850 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2851 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2852 no_subreg_reg_operand
[1])
2853 || (targetm
.preferred_reload_class
2854 (no_subreg_reg_operand
[1],
2855 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2856 /* If it is a result of recent elimination in move
2857 insn we can transform it into an add still by
2858 using this alternative. */
2859 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2861 /* We have a move insn and a new reload insn will be similar
2862 to the current insn. We should avoid such situation as
2863 it results in LRA cycling. */
2864 if (lra_dump_file
!= NULL
)
2865 fprintf (lra_dump_file
,
2866 " Cycle danger: overall += LRA_MAX_REJECT\n");
2867 overall
+= LRA_MAX_REJECT
;
2870 curr_alt_dont_inherit_ops_num
= 0;
2871 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2873 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2874 HARD_REG_SET temp_set
;
2876 i
= early_clobbered_nops
[nop
];
2877 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2878 || hard_regno
[i
] < 0)
2880 lra_assert (operand_reg
[i
] != NULL_RTX
);
2881 clobbered_hard_regno
= hard_regno
[i
];
2882 CLEAR_HARD_REG_SET (temp_set
);
2883 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2884 first_conflict_j
= last_conflict_j
= -1;
2885 for (j
= 0; j
< n_operands
; j
++)
2887 /* We don't want process insides of match_operator and
2888 match_parallel because otherwise we would process
2889 their operands once again generating a wrong
2891 || curr_static_id
->operand
[j
].is_operator
)
2893 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2894 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2896 /* If we don't reload j-th operand, check conflicts. */
2897 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2898 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2900 if (first_conflict_j
< 0)
2901 first_conflict_j
= j
;
2902 last_conflict_j
= j
;
2904 if (last_conflict_j
< 0)
2906 /* If earlyclobber operand conflicts with another
2907 non-matching operand which is actually the same register
2908 as the earlyclobber operand, it is better to reload the
2909 another operand as an operand matching the earlyclobber
2910 operand can be also the same. */
2911 if (first_conflict_j
== last_conflict_j
2912 && operand_reg
[last_conflict_j
] != NULL_RTX
2913 && ! curr_alt_match_win
[last_conflict_j
]
2914 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2916 curr_alt_win
[last_conflict_j
] = false;
2917 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2920 /* Early clobber was already reflected in REJECT. */
2921 lra_assert (reject
> 0);
2922 if (lra_dump_file
!= NULL
)
2925 " %d Conflict early clobber reload: reject--\n",
2928 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2932 /* We need to reload early clobbered register and the
2933 matched registers. */
2934 for (j
= 0; j
< n_operands
; j
++)
2935 if (curr_alt_matches
[j
] == i
)
2937 curr_alt_match_win
[j
] = false;
2939 overall
+= LRA_LOSER_COST_FACTOR
;
2941 if (! curr_alt_match_win
[i
])
2942 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2945 /* Remember pseudos used for match reloads are never
2947 lra_assert (curr_alt_matches
[i
] >= 0);
2948 curr_alt_win
[curr_alt_matches
[i
]] = false;
2950 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2952 /* Early clobber was already reflected in REJECT. */
2953 lra_assert (reject
> 0);
2954 if (lra_dump_file
!= NULL
)
2957 " %d Matched conflict early clobber reloads: "
2961 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2964 if (lra_dump_file
!= NULL
)
2965 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2966 nalt
, overall
, losers
, reload_nregs
);
2968 /* If this alternative can be made to work by reloading, and it
2969 needs less reloading than the others checked so far, record
2970 it as the chosen goal for reloading. */
2971 if ((best_losers
!= 0 && losers
== 0)
2972 || (((best_losers
== 0 && losers
== 0)
2973 || (best_losers
!= 0 && losers
!= 0))
2974 && (best_overall
> overall
2975 || (best_overall
== overall
2976 /* If the cost of the reloads is the same,
2977 prefer alternative which requires minimal
2978 number of reload regs. */
2979 && (reload_nregs
< best_reload_nregs
2980 || (reload_nregs
== best_reload_nregs
2981 && (best_reload_sum
< reload_sum
2982 || (best_reload_sum
== reload_sum
2983 && nalt
< goal_alt_number
))))))))
2985 for (nop
= 0; nop
< n_operands
; nop
++)
2987 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2988 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2989 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2990 goal_alt
[nop
] = curr_alt
[nop
];
2991 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2993 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2994 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2995 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2996 goal_alt_swapped
= curr_swapped
;
2997 best_overall
= overall
;
2998 best_losers
= losers
;
2999 best_reload_nregs
= reload_nregs
;
3000 best_reload_sum
= reload_sum
;
3001 goal_alt_number
= nalt
;
3004 /* Everything is satisfied. Do not process alternatives
3013 /* Make reload base reg from address AD. */
3015 base_to_reg (struct address_info
*ad
)
3019 rtx new_inner
= NULL_RTX
;
3020 rtx new_reg
= NULL_RTX
;
3022 rtx_insn
*last_insn
= get_last_insn();
3024 lra_assert (ad
->disp
== ad
->disp_term
);
3025 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3026 get_index_code (ad
));
3027 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base
), NULL_RTX
,
3029 new_inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
), new_reg
,
3030 ad
->disp_term
== NULL
3033 if (!valid_address_p (ad
->mode
, new_inner
, ad
->as
))
3035 insn
= emit_insn (gen_rtx_SET (new_reg
, *ad
->base
));
3036 code
= recog_memoized (insn
);
3039 delete_insns_since (last_insn
);
3046 /* Make reload base reg + disp from address AD. Return the new pseudo. */
3048 base_plus_disp_to_reg (struct address_info
*ad
)
3053 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
3054 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
3055 get_index_code (ad
));
3056 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
3058 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
3062 /* Make reload of index part of address AD. Return the new
3065 index_part_to_reg (struct address_info
*ad
)
3069 new_reg
= lra_create_new_reg (GET_MODE (*ad
->index
), NULL_RTX
,
3070 INDEX_REG_CLASS
, "index term");
3071 expand_mult (GET_MODE (*ad
->index
), *ad
->index_term
,
3072 GEN_INT (get_index_scale (ad
)), new_reg
, 1);
3076 /* Return true if we can add a displacement to address AD, even if that
3077 makes the address invalid. The fix-up code requires any new address
3078 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3080 can_add_disp_p (struct address_info
*ad
)
3082 return (!ad
->autoinc_p
3083 && ad
->segment
== NULL
3084 && ad
->base
== ad
->base_term
3085 && ad
->disp
== ad
->disp_term
);
3088 /* Make equiv substitution in address AD. Return true if a substitution
3091 equiv_address_substitution (struct address_info
*ad
)
3093 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
3094 HOST_WIDE_INT disp
, scale
;
3097 base_term
= strip_subreg (ad
->base_term
);
3098 if (base_term
== NULL
)
3099 base_reg
= new_base_reg
= NULL_RTX
;
3102 base_reg
= *base_term
;
3103 new_base_reg
= get_equiv_with_elimination (base_reg
, curr_insn
);
3105 index_term
= strip_subreg (ad
->index_term
);
3106 if (index_term
== NULL
)
3107 index_reg
= new_index_reg
= NULL_RTX
;
3110 index_reg
= *index_term
;
3111 new_index_reg
= get_equiv_with_elimination (index_reg
, curr_insn
);
3113 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
3117 if (lra_dump_file
!= NULL
)
3119 fprintf (lra_dump_file
, "Changing address in insn %d ",
3120 INSN_UID (curr_insn
));
3121 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3123 if (base_reg
!= new_base_reg
)
3125 if (REG_P (new_base_reg
))
3127 *base_term
= new_base_reg
;
3130 else if (GET_CODE (new_base_reg
) == PLUS
3131 && REG_P (XEXP (new_base_reg
, 0))
3132 && CONST_INT_P (XEXP (new_base_reg
, 1))
3133 && can_add_disp_p (ad
))
3135 disp
+= INTVAL (XEXP (new_base_reg
, 1));
3136 *base_term
= XEXP (new_base_reg
, 0);
3139 if (ad
->base_term2
!= NULL
)
3140 *ad
->base_term2
= *ad
->base_term
;
3142 if (index_reg
!= new_index_reg
)
3144 if (REG_P (new_index_reg
))
3146 *index_term
= new_index_reg
;
3149 else if (GET_CODE (new_index_reg
) == PLUS
3150 && REG_P (XEXP (new_index_reg
, 0))
3151 && CONST_INT_P (XEXP (new_index_reg
, 1))
3152 && can_add_disp_p (ad
)
3153 && (scale
= get_index_scale (ad
)))
3155 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
3156 *index_term
= XEXP (new_index_reg
, 0);
3162 if (ad
->disp
!= NULL
)
3163 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
3166 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
3167 update_address (ad
);
3171 if (lra_dump_file
!= NULL
)
3174 fprintf (lra_dump_file
, " -- no change\n");
3177 fprintf (lra_dump_file
, " on equiv ");
3178 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
3179 fprintf (lra_dump_file
, "\n");
3185 /* Major function to make reloads for an address in operand NOP or
3186 check its correctness (If CHECK_ONLY_P is true). The supported
3189 1) an address that existed before LRA started, at which point it
3190 must have been valid. These addresses are subject to elimination
3191 and may have become invalid due to the elimination offset being out
3194 2) an address created by forcing a constant to memory
3195 (force_const_to_mem). The initial form of these addresses might
3196 not be valid, and it is this function's job to make them valid.
3198 3) a frame address formed from a register and a (possibly zero)
3199 constant offset. As above, these addresses might not be valid and
3200 this function must make them so.
3202 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3203 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3204 address. Return true for any RTL change.
3206 The function is a helper function which does not produce all
3207 transformations (when CHECK_ONLY_P is false) which can be
3208 necessary. It does just basic steps. To do all necessary
3209 transformations use function process_address. */
3211 process_address_1 (int nop
, bool check_only_p
,
3212 rtx_insn
**before
, rtx_insn
**after
)
3214 struct address_info ad
;
3216 HOST_WIDE_INT scale
;
3217 rtx op
= *curr_id
->operand_loc
[nop
];
3218 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
3219 enum constraint_num cn
= lookup_constraint (constraint
);
3220 bool change_p
= false;
3223 && GET_MODE (op
) == BLKmode
3224 && GET_CODE (XEXP (op
, 0)) == SCRATCH
)
3227 if (insn_extra_address_constraint (cn
))
3228 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
3229 /* Do not attempt to decompose arbitrary addresses generated by combine
3230 for asm operands with loose constraints, e.g 'X'. */
3232 && !(get_constraint_type (cn
) == CT_FIXED_FORM
3233 && constraint_satisfied_p (op
, cn
)))
3234 decompose_mem_address (&ad
, op
);
3235 else if (GET_CODE (op
) == SUBREG
3236 && MEM_P (SUBREG_REG (op
)))
3237 decompose_mem_address (&ad
, SUBREG_REG (op
));
3240 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3241 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3242 when INDEX_REG_CLASS is a single register class. */
3243 if (ad
.base_term
!= NULL
3244 && ad
.index_term
!= NULL
3245 && ira_class_hard_regs_num
[INDEX_REG_CLASS
] == 1
3246 && REG_P (*ad
.base_term
)
3247 && REG_P (*ad
.index_term
)
3248 && in_class_p (*ad
.base_term
, INDEX_REG_CLASS
, NULL
)
3249 && ! in_class_p (*ad
.index_term
, INDEX_REG_CLASS
, NULL
))
3251 std::swap (ad
.base
, ad
.index
);
3252 std::swap (ad
.base_term
, ad
.index_term
);
3255 change_p
= equiv_address_substitution (&ad
);
3256 if (ad
.base_term
!= NULL
3257 && (process_addr_reg
3258 (ad
.base_term
, check_only_p
, before
,
3260 && !(REG_P (*ad
.base_term
)
3261 && find_regno_note (curr_insn
, REG_DEAD
,
3262 REGNO (*ad
.base_term
)) != NULL_RTX
)
3264 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3265 get_index_code (&ad
)))))
3268 if (ad
.base_term2
!= NULL
)
3269 *ad
.base_term2
= *ad
.base_term
;
3271 if (ad
.index_term
!= NULL
3272 && process_addr_reg (ad
.index_term
, check_only_p
,
3273 before
, NULL
, INDEX_REG_CLASS
))
3276 /* Target hooks sometimes don't treat extra-constraint addresses as
3277 legitimate address_operands, so handle them specially. */
3278 if (insn_extra_address_constraint (cn
)
3279 && satisfies_address_constraint_p (&ad
, cn
))
3285 /* There are three cases where the shape of *AD.INNER may now be invalid:
3287 1) the original address was valid, but either elimination or
3288 equiv_address_substitution was applied and that made
3289 the address invalid.
3291 2) the address is an invalid symbolic address created by
3294 3) the address is a frame address with an invalid offset.
3296 4) the address is a frame address with an invalid base.
3298 All these cases involve a non-autoinc address, so there is no
3299 point revalidating other types. */
3300 if (ad
.autoinc_p
|| valid_address_p (&ad
))
3303 /* Any index existed before LRA started, so we can assume that the
3304 presence and shape of the index is valid. */
3305 push_to_sequence (*before
);
3306 lra_assert (ad
.disp
== ad
.disp_term
);
3307 if (ad
.base
== NULL
)
3309 if (ad
.index
== NULL
)
3312 rtx_insn
*last
= get_last_insn ();
3314 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3316 rtx addr
= *ad
.inner
;
3318 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3321 /* addr => lo_sum (new_base, addr), case (2) above. */
3322 insn
= emit_insn (gen_rtx_SET
3324 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
3325 code
= recog_memoized (insn
);
3328 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
3329 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3331 /* Try to put lo_sum into register. */
3332 insn
= emit_insn (gen_rtx_SET
3334 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
3335 code
= recog_memoized (insn
);
3338 *ad
.inner
= new_reg
;
3339 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3349 delete_insns_since (last
);
3354 /* addr => new_base, case (2) above. */
3355 lra_emit_move (new_reg
, addr
);
3357 for (insn
= last
== NULL_RTX
? get_insns () : NEXT_INSN (last
);
3359 insn
= NEXT_INSN (insn
))
3360 if (recog_memoized (insn
) < 0)
3362 if (insn
!= NULL_RTX
)
3364 /* Do nothing if we cannot generate right insns.
3365 This is analogous to reload pass behavior. */
3366 delete_insns_since (last
);
3370 *ad
.inner
= new_reg
;
3375 /* index * scale + disp => new base + index * scale,
3377 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
3378 GET_CODE (*ad
.index
));
3380 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
3381 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
3382 lra_emit_move (new_reg
, *ad
.disp
);
3383 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3384 new_reg
, *ad
.index
);
3387 else if (ad
.index
== NULL
)
3392 rtx_insn
*insns
, *last_insn
;
3393 /* Try to reload base into register only if the base is invalid
3394 for the address but with valid offset, case (4) above. */
3396 new_reg
= base_to_reg (&ad
);
3398 /* base + disp => new base, cases (1) and (3) above. */
3399 /* Another option would be to reload the displacement into an
3400 index register. However, postreload has code to optimize
3401 address reloads that have the same base and different
3402 displacements, so reloading into an index register would
3403 not necessarily be a win. */
3404 if (new_reg
== NULL_RTX
)
3405 new_reg
= base_plus_disp_to_reg (&ad
);
3406 insns
= get_insns ();
3407 last_insn
= get_last_insn ();
3408 /* If we generated at least two insns, try last insn source as
3409 an address. If we succeed, we generate one less insn. */
3410 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
3411 && GET_CODE (SET_SRC (set
)) == PLUS
3412 && REG_P (XEXP (SET_SRC (set
), 0))
3413 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
3415 *ad
.inner
= SET_SRC (set
);
3416 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
3418 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
3419 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
3420 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
3421 get_index_code (&ad
));
3422 regno
= REGNO (*ad
.base_term
);
3423 if (regno
>= FIRST_PSEUDO_REGISTER
3424 && cl
!= lra_get_allocno_class (regno
))
3425 lra_change_class (regno
, cl
, " Change to", true);
3426 new_reg
= SET_SRC (set
);
3427 delete_insns_since (PREV_INSN (last_insn
));
3430 /* Try if target can split displacement into legitimite new disp
3431 and offset. If it's the case, we replace the last insn with
3432 insns for base + offset => new_reg and set new_reg + new disp
3434 last_insn
= get_last_insn ();
3435 if ((set
= single_set (last_insn
)) != NULL_RTX
3436 && GET_CODE (SET_SRC (set
)) == PLUS
3437 && REG_P (XEXP (SET_SRC (set
), 0))
3438 && REGNO (XEXP (SET_SRC (set
), 0)) < FIRST_PSEUDO_REGISTER
3439 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
3441 rtx addend
, disp
= XEXP (SET_SRC (set
), 1);
3442 if (targetm
.legitimize_address_displacement (&disp
, &addend
,
3445 rtx_insn
*new_insns
;
3447 lra_emit_add (new_reg
, XEXP (SET_SRC (set
), 0), addend
);
3448 new_insns
= get_insns ();
3450 new_reg
= gen_rtx_PLUS (Pmode
, new_reg
, disp
);
3451 delete_insns_since (PREV_INSN (last_insn
));
3452 add_insn (new_insns
);
3453 insns
= get_insns ();
3458 *ad
.inner
= new_reg
;
3460 else if (ad
.disp_term
!= NULL
)
3462 /* base + scale * index + disp => new base + scale * index,
3464 new_reg
= base_plus_disp_to_reg (&ad
);
3465 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3466 new_reg
, *ad
.index
);
3468 else if ((scale
= get_index_scale (&ad
)) == 1)
3470 /* The last transformation to one reg will be made in
3471 curr_insn_transform function. */
3475 else if (scale
!= 0)
3477 /* base + scale * index => base + new_reg,
3479 Index part of address may become invalid. For example, we
3480 changed pseudo on the equivalent memory and a subreg of the
3481 pseudo onto the memory of different mode for which the scale is
3483 new_reg
= index_part_to_reg (&ad
);
3484 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
3485 *ad
.base_term
, new_reg
);
3489 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
3491 rtx addr
= *ad
.inner
;
3493 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
3494 /* addr => new_base. */
3495 lra_emit_move (new_reg
, addr
);
3496 *ad
.inner
= new_reg
;
3498 *before
= get_insns ();
3503 /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3504 Use process_address_1 as a helper function. Return true for any
3507 If CHECK_ONLY_P is true, just check address correctness. Return
3508 false if the address correct. */
3510 process_address (int nop
, bool check_only_p
,
3511 rtx_insn
**before
, rtx_insn
**after
)
3515 while (process_address_1 (nop
, check_only_p
, before
, after
))
3524 /* Emit insns to reload VALUE into a new register. VALUE is an
3525 auto-increment or auto-decrement RTX whose operand is a register or
3526 memory location; so reloading involves incrementing that location.
3527 IN is either identical to VALUE, or some cheaper place to reload
3528 value being incremented/decremented from.
3530 INC_AMOUNT is the number to increment or decrement by (always
3531 positive and ignored for POST_MODIFY/PRE_MODIFY).
3533 Return pseudo containing the result. */
3535 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
3537 /* REG or MEM to be copied and incremented. */
3538 rtx incloc
= XEXP (value
, 0);
3539 /* Nonzero if increment after copying. */
3540 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
3541 || GET_CODE (value
) == POST_MODIFY
);
3546 rtx real_in
= in
== value
? incloc
: in
;
3550 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
3552 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
3553 || GET_CODE (XEXP (value
, 1)) == MINUS
);
3554 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
3555 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
3556 inc
= XEXP (XEXP (value
, 1), 1);
3560 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
3561 inc_amount
= -inc_amount
;
3563 inc
= GEN_INT (inc_amount
);
3566 if (! post
&& REG_P (incloc
))
3569 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
3572 if (real_in
!= result
)
3574 /* First copy the location to the result register. */
3575 lra_assert (REG_P (result
));
3576 emit_insn (gen_move_insn (result
, real_in
));
3579 /* We suppose that there are insns to add/sub with the constant
3580 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3581 old reload worked with this assumption. If the assumption
3582 becomes wrong, we should use approach in function
3583 base_plus_disp_to_reg. */
3586 /* See if we can directly increment INCLOC. */
3587 last
= get_last_insn ();
3588 add_insn
= emit_insn (plus_p
3589 ? gen_add2_insn (incloc
, inc
)
3590 : gen_sub2_insn (incloc
, inc
));
3592 code
= recog_memoized (add_insn
);
3595 if (! post
&& result
!= incloc
)
3596 emit_insn (gen_move_insn (result
, incloc
));
3599 delete_insns_since (last
);
3602 /* If couldn't do the increment directly, must increment in RESULT.
3603 The way we do this depends on whether this is pre- or
3604 post-increment. For pre-increment, copy INCLOC to the reload
3605 register, increment it there, then save back. */
3608 if (real_in
!= result
)
3609 emit_insn (gen_move_insn (result
, real_in
));
3611 emit_insn (gen_add2_insn (result
, inc
));
3613 emit_insn (gen_sub2_insn (result
, inc
));
3614 if (result
!= incloc
)
3615 emit_insn (gen_move_insn (incloc
, result
));
3621 Because this might be a jump insn or a compare, and because
3622 RESULT may not be available after the insn in an input
3623 reload, we must do the incrementing before the insn being
3626 We have already copied IN to RESULT. Increment the copy in
3627 RESULT, save that back, then decrement RESULT so it has
3628 the original value. */
3630 emit_insn (gen_add2_insn (result
, inc
));
3632 emit_insn (gen_sub2_insn (result
, inc
));
3633 emit_insn (gen_move_insn (incloc
, result
));
3634 /* Restore non-modified value for the result. We prefer this
3635 way because it does not require an additional hard
3639 if (CONST_INT_P (inc
))
3640 emit_insn (gen_add2_insn (result
,
3641 gen_int_mode (-INTVAL (inc
),
3642 GET_MODE (result
))));
3644 emit_insn (gen_sub2_insn (result
, inc
));
3647 emit_insn (gen_add2_insn (result
, inc
));
3652 /* Return true if the current move insn does not need processing as we
3653 already know that it satisfies its constraints. */
3655 simple_move_p (void)
3658 enum reg_class dclass
, sclass
;
3660 lra_assert (curr_insn_set
!= NULL_RTX
);
3661 dest
= SET_DEST (curr_insn_set
);
3662 src
= SET_SRC (curr_insn_set
);
3664 /* If the instruction has multiple sets we need to process it even if it
3665 is single_set. This can happen if one or more of the SETs are dead.
3667 if (multiple_sets (curr_insn
))
3670 return ((dclass
= get_op_class (dest
)) != NO_REGS
3671 && (sclass
= get_op_class (src
)) != NO_REGS
3672 /* The backend guarantees that register moves of cost 2
3673 never need reloads. */
3674 && targetm
.register_move_cost (GET_MODE (src
), sclass
, dclass
) == 2);
3677 /* Swap operands NOP and NOP + 1. */
3679 swap_operands (int nop
)
3681 std::swap (curr_operand_mode
[nop
], curr_operand_mode
[nop
+ 1]);
3682 std::swap (original_subreg_reg_mode
[nop
], original_subreg_reg_mode
[nop
+ 1]);
3683 std::swap (*curr_id
->operand_loc
[nop
], *curr_id
->operand_loc
[nop
+ 1]);
3684 std::swap (equiv_substition_p
[nop
], equiv_substition_p
[nop
+ 1]);
3685 /* Swap the duplicates too. */
3686 lra_update_dup (curr_id
, nop
);
3687 lra_update_dup (curr_id
, nop
+ 1);
3690 /* Main entry point of the constraint code: search the body of the
3691 current insn to choose the best alternative. It is mimicking insn
3692 alternative cost calculation model of former reload pass. That is
3693 because machine descriptions were written to use this model. This
3694 model can be changed in future. Make commutative operand exchange
3697 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3698 constraints. Return true if any change happened during function
3701 If CHECK_ONLY_P is true then don't do any transformation. Just
3702 check that the insn satisfies all constraints. If the insn does
3703 not satisfy any constraint, return true. */
3705 curr_insn_transform (bool check_only_p
)
3712 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
3713 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
3714 signed char outputs
[MAX_RECOG_OPERANDS
+ 1];
3715 rtx_insn
*before
, *after
;
3717 /* Flag that the insn has been changed through a transformation. */
3720 #ifdef SECONDARY_MEMORY_NEEDED
3723 int max_regno_before
;
3724 int reused_alternative_num
;
3726 curr_insn_set
= single_set (curr_insn
);
3727 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3730 no_input_reloads_p
= no_output_reloads_p
= false;
3731 goal_alt_number
= -1;
3732 change_p
= sec_mem_p
= false;
3733 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3734 reloads; neither are insns that SET cc0. Insns that use CC0 are
3735 not allowed to have any input reloads. */
3736 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3737 no_output_reloads_p
= true;
3739 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3740 no_input_reloads_p
= true;
3741 if (HAVE_cc0
&& reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3742 no_output_reloads_p
= true;
3744 n_operands
= curr_static_id
->n_operands
;
3745 n_alternatives
= curr_static_id
->n_alternatives
;
3747 /* Just return "no reloads" if insn has no operands with
3749 if (n_operands
== 0 || n_alternatives
== 0)
3752 max_regno_before
= max_reg_num ();
3754 for (i
= 0; i
< n_operands
; i
++)
3756 goal_alt_matched
[i
][0] = -1;
3757 goal_alt_matches
[i
] = -1;
3760 commutative
= curr_static_id
->commutative
;
3762 /* Now see what we need for pseudos that didn't get hard regs or got
3763 the wrong kind of hard reg. For this, we must consider all the
3764 operands together against the register constraints. */
3766 best_losers
= best_overall
= INT_MAX
;
3767 best_reload_sum
= 0;
3769 curr_swapped
= false;
3770 goal_alt_swapped
= false;
3773 /* Make equivalence substitution and memory subreg elimination
3774 before address processing because an address legitimacy can
3775 depend on memory mode. */
3776 for (i
= 0; i
< n_operands
; i
++)
3779 bool op_change_p
= false;
3781 if (curr_static_id
->operand
[i
].is_operator
)
3784 old
= op
= *curr_id
->operand_loc
[i
];
3785 if (GET_CODE (old
) == SUBREG
)
3786 old
= SUBREG_REG (old
);
3787 subst
= get_equiv_with_elimination (old
, curr_insn
);
3788 original_subreg_reg_mode
[i
] = VOIDmode
;
3789 equiv_substition_p
[i
] = false;
3792 equiv_substition_p
[i
] = true;
3793 subst
= copy_rtx (subst
);
3794 lra_assert (REG_P (old
));
3795 if (GET_CODE (op
) != SUBREG
)
3796 *curr_id
->operand_loc
[i
] = subst
;
3799 SUBREG_REG (op
) = subst
;
3800 if (GET_MODE (subst
) == VOIDmode
)
3801 original_subreg_reg_mode
[i
] = GET_MODE (old
);
3803 if (lra_dump_file
!= NULL
)
3805 fprintf (lra_dump_file
,
3806 "Changing pseudo %d in operand %i of insn %u on equiv ",
3807 REGNO (old
), i
, INSN_UID (curr_insn
));
3808 dump_value_slim (lra_dump_file
, subst
, 1);
3809 fprintf (lra_dump_file
, "\n");
3811 op_change_p
= change_p
= true;
3813 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3816 lra_update_dup (curr_id
, i
);
3820 /* Reload address registers and displacements. We do it before
3821 finding an alternative because of memory constraints. */
3822 before
= after
= NULL
;
3823 for (i
= 0; i
< n_operands
; i
++)
3824 if (! curr_static_id
->operand
[i
].is_operator
3825 && process_address (i
, check_only_p
, &before
, &after
))
3830 lra_update_dup (curr_id
, i
);
3834 /* If we've changed the instruction then any alternative that
3835 we chose previously may no longer be valid. */
3836 lra_set_used_insn_alternative (curr_insn
, -1);
3838 if (! check_only_p
&& curr_insn_set
!= NULL_RTX
3839 && check_and_process_move (&change_p
, &sec_mem_p
))
3844 reused_alternative_num
= check_only_p
? -1 : curr_id
->used_insn_alternative
;
3845 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3846 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3847 reused_alternative_num
, INSN_UID (curr_insn
));
3849 if (process_alt_operands (reused_alternative_num
))
3853 return ! alt_p
|| best_losers
!= 0;
3855 /* If insn is commutative (it's safe to exchange a certain pair of
3856 operands) then we need to try each alternative twice, the second
3857 time matching those two operands as if we had exchanged them. To
3858 do this, really exchange them in operands.
3860 If we have just tried the alternatives the second time, return
3861 operands to normal and drop through. */
3863 if (reused_alternative_num
< 0 && commutative
>= 0)
3865 curr_swapped
= !curr_swapped
;
3868 swap_operands (commutative
);
3872 swap_operands (commutative
);
3875 if (! alt_p
&& ! sec_mem_p
)
3877 /* No alternative works with reloads?? */
3878 if (INSN_CODE (curr_insn
) >= 0)
3879 fatal_insn ("unable to generate reloads for:", curr_insn
);
3880 error_for_asm (curr_insn
,
3881 "inconsistent operand constraints in an %<asm%>");
3882 /* Avoid further trouble with this insn. Don't generate use
3883 pattern here as we could use the insn SP offset. */
3884 lra_set_insn_deleted (curr_insn
);
3888 /* If the best alternative is with operands 1 and 2 swapped, swap
3889 them. Update the operand numbers of any reloads already
3892 if (goal_alt_swapped
)
3894 if (lra_dump_file
!= NULL
)
3895 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3896 INSN_UID (curr_insn
));
3898 /* Swap the duplicates too. */
3899 swap_operands (commutative
);
3903 #ifdef SECONDARY_MEMORY_NEEDED
3904 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3905 too conservatively. So we use the secondary memory only if there
3906 is no any alternative without reloads. */
3907 use_sec_mem_p
= false;
3909 use_sec_mem_p
= true;
3912 for (i
= 0; i
< n_operands
; i
++)
3913 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3915 use_sec_mem_p
= i
< n_operands
;
3920 int in
= -1, out
= -1;
3921 rtx new_reg
, src
, dest
, rld
;
3922 machine_mode sec_mode
, rld_mode
;
3924 lra_assert (curr_insn_set
!= NULL_RTX
&& sec_mem_p
);
3925 dest
= SET_DEST (curr_insn_set
);
3926 src
= SET_SRC (curr_insn_set
);
3927 for (i
= 0; i
< n_operands
; i
++)
3928 if (*curr_id
->operand_loc
[i
] == dest
)
3930 else if (*curr_id
->operand_loc
[i
] == src
)
3932 for (i
= 0; i
< curr_static_id
->n_dups
; i
++)
3933 if (out
< 0 && *curr_id
->dup_loc
[i
] == dest
)
3934 out
= curr_static_id
->dup_num
[i
];
3935 else if (in
< 0 && *curr_id
->dup_loc
[i
] == src
)
3936 in
= curr_static_id
->dup_num
[i
];
3937 lra_assert (out
>= 0 && in
>= 0
3938 && curr_static_id
->operand
[out
].type
== OP_OUT
3939 && curr_static_id
->operand
[in
].type
== OP_IN
);
3940 rld
= partial_subreg_p (GET_MODE (src
), GET_MODE (dest
)) ? src
: dest
;
3941 rld_mode
= GET_MODE (rld
);
3942 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3943 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3945 sec_mode
= rld_mode
;
3947 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3948 NO_REGS
, "secondary");
3949 /* If the mode is changed, it should be wider. */
3950 lra_assert (!partial_subreg_p (sec_mode
, rld_mode
));
3951 if (sec_mode
!= rld_mode
)
3953 /* If the target says specifically to use another mode for
3954 secondary memory moves we can not reuse the original
3956 after
= emit_spill_move (false, new_reg
, dest
);
3957 lra_process_new_insns (curr_insn
, NULL
, after
,
3958 "Inserting the sec. move");
3959 /* We may have non null BEFORE here (e.g. after address
3961 push_to_sequence (before
);
3962 before
= emit_spill_move (true, new_reg
, src
);
3964 before
= get_insns ();
3966 lra_process_new_insns (curr_insn
, before
, NULL
, "Changing on");
3967 lra_set_insn_deleted (curr_insn
);
3969 else if (dest
== rld
)
3971 *curr_id
->operand_loc
[out
] = new_reg
;
3972 lra_update_dup (curr_id
, out
);
3973 after
= emit_spill_move (false, new_reg
, dest
);
3974 lra_process_new_insns (curr_insn
, NULL
, after
,
3975 "Inserting the sec. move");
3979 *curr_id
->operand_loc
[in
] = new_reg
;
3980 lra_update_dup (curr_id
, in
);
3981 /* See comments above. */
3982 push_to_sequence (before
);
3983 before
= emit_spill_move (true, new_reg
, src
);
3985 before
= get_insns ();
3987 lra_process_new_insns (curr_insn
, before
, NULL
,
3988 "Inserting the sec. move");
3990 lra_update_insn_regno_info (curr_insn
);
3995 lra_assert (goal_alt_number
>= 0);
3996 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3998 if (lra_dump_file
!= NULL
)
4002 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
4003 goal_alt_number
, INSN_UID (curr_insn
));
4004 for (i
= 0; i
< n_operands
; i
++)
4006 p
= (curr_static_id
->operand_alternative
4007 [goal_alt_number
* n_operands
+ i
].constraint
);
4010 fprintf (lra_dump_file
, " (%d) ", i
);
4011 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
4012 fputc (*p
, lra_dump_file
);
4014 if (INSN_CODE (curr_insn
) >= 0
4015 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
4016 fprintf (lra_dump_file
, " {%s}", p
);
4017 if (curr_id
->sp_offset
!= 0)
4018 fprintf (lra_dump_file
, " (sp_off=%" HOST_WIDE_INT_PRINT
"d)",
4019 curr_id
->sp_offset
);
4020 fprintf (lra_dump_file
, "\n");
4023 /* Right now, for any pair of operands I and J that are required to
4024 match, with J < I, goal_alt_matches[I] is J. Add I to
4025 goal_alt_matched[J]. */
4027 for (i
= 0; i
< n_operands
; i
++)
4028 if ((j
= goal_alt_matches
[i
]) >= 0)
4030 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
4032 /* We allow matching one output operand and several input
4035 || (curr_static_id
->operand
[j
].type
== OP_OUT
4036 && curr_static_id
->operand
[i
].type
== OP_IN
4037 && (curr_static_id
->operand
4038 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
4039 goal_alt_matched
[j
][k
] = i
;
4040 goal_alt_matched
[j
][k
+ 1] = -1;
4043 for (i
= 0; i
< n_operands
; i
++)
4044 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
4046 /* Any constants that aren't allowed and can't be reloaded into
4047 registers are here changed into memory references. */
4048 for (i
= 0; i
< n_operands
; i
++)
4049 if (goal_alt_win
[i
])
4052 enum reg_class new_class
;
4053 rtx reg
= *curr_id
->operand_loc
[i
];
4055 if (GET_CODE (reg
) == SUBREG
)
4056 reg
= SUBREG_REG (reg
);
4058 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
4060 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
4062 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
4065 lra_change_class (regno
, new_class
, " Change to", true);
4071 const char *constraint
;
4073 rtx op
= *curr_id
->operand_loc
[i
];
4074 rtx subreg
= NULL_RTX
;
4075 machine_mode mode
= curr_operand_mode
[i
];
4077 if (GET_CODE (op
) == SUBREG
)
4080 op
= SUBREG_REG (op
);
4081 mode
= GET_MODE (op
);
4084 if (CONST_POOL_OK_P (mode
, op
)
4085 && ((targetm
.preferred_reload_class
4086 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
4087 || no_input_reloads_p
))
4089 rtx tem
= force_const_mem (mode
, op
);
4092 if (subreg
!= NULL_RTX
)
4093 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
4095 *curr_id
->operand_loc
[i
] = tem
;
4096 lra_update_dup (curr_id
, i
);
4097 process_address (i
, false, &before
, &after
);
4099 /* If the alternative accepts constant pool refs directly
4100 there will be no reload needed at all. */
4101 if (subreg
!= NULL_RTX
)
4103 /* Skip alternatives before the one requested. */
4104 constraint
= (curr_static_id
->operand_alternative
4105 [goal_alt_number
* n_operands
+ i
].constraint
);
4107 (c
= *constraint
) && c
!= ',' && c
!= '#';
4108 constraint
+= CONSTRAINT_LEN (c
, constraint
))
4110 enum constraint_num cn
= lookup_constraint (constraint
);
4111 if ((insn_extra_memory_constraint (cn
)
4112 || insn_extra_special_memory_constraint (cn
))
4113 && satisfies_memory_constraint_p (tem
, cn
))
4116 if (c
== '\0' || c
== ',' || c
== '#')
4119 goal_alt_win
[i
] = true;
4125 for (i
= 0; i
< n_operands
; i
++)
4128 bool optional_p
= false;
4130 rtx op
= *curr_id
->operand_loc
[i
];
4132 if (goal_alt_win
[i
])
4134 if (goal_alt
[i
] == NO_REGS
4136 /* When we assign NO_REGS it means that we will not
4137 assign a hard register to the scratch pseudo by
4138 assigment pass and the scratch pseudo will be
4139 spilled. Spilled scratch pseudos are transformed
4140 back to scratches at the LRA end. */
4141 && lra_former_scratch_operand_p (curr_insn
, i
)
4142 && lra_former_scratch_p (REGNO (op
)))
4144 int regno
= REGNO (op
);
4145 lra_change_class (regno
, NO_REGS
, " Change to", true);
4146 if (lra_get_regno_hard_regno (regno
) >= 0)
4147 /* We don't have to mark all insn affected by the
4148 spilled pseudo as there is only one such insn, the
4150 reg_renumber
[regno
] = -1;
4151 lra_assert (bitmap_single_bit_set_p
4152 (&lra_reg_info
[REGNO (op
)].insn_bitmap
));
4154 /* We can do an optional reload. If the pseudo got a hard
4155 reg, we might improve the code through inheritance. If
4156 it does not get a hard register we coalesce memory/memory
4157 moves later. Ignore move insns to avoid cycling. */
4159 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
4160 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
4161 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
4162 && regno
< new_regno_start
4163 && ! lra_former_scratch_p (regno
)
4164 && reg_renumber
[regno
] < 0
4165 /* Check that the optional reload pseudo will be able to
4166 hold given mode value. */
4167 && ! (prohibited_class_reg_set_mode_p
4168 (goal_alt
[i
], reg_class_contents
[goal_alt
[i
]],
4169 PSEUDO_REGNO_MODE (regno
)))
4170 && (curr_insn_set
== NULL_RTX
4171 || !((REG_P (SET_SRC (curr_insn_set
))
4172 || MEM_P (SET_SRC (curr_insn_set
))
4173 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
4174 && (REG_P (SET_DEST (curr_insn_set
))
4175 || MEM_P (SET_DEST (curr_insn_set
))
4176 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
4182 /* Operands that match previous ones have already been handled. */
4183 if (goal_alt_matches
[i
] >= 0)
4186 /* We should not have an operand with a non-offsettable address
4187 appearing where an offsettable address will do. It also may
4188 be a case when the address should be special in other words
4189 not a general one (e.g. it needs no index reg). */
4190 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
4192 enum reg_class rclass
;
4193 rtx
*loc
= &XEXP (op
, 0);
4194 enum rtx_code code
= GET_CODE (*loc
);
4196 push_to_sequence (before
);
4197 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
4199 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
4200 new_reg
= emit_inc (rclass
, *loc
, *loc
,
4201 /* This value does not matter for MODIFY. */
4202 GET_MODE_SIZE (GET_MODE (op
)));
4203 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
, FALSE
,
4204 "offsetable address", &new_reg
))
4205 lra_emit_move (new_reg
, *loc
);
4206 before
= get_insns ();
4209 lra_update_dup (curr_id
, i
);
4211 else if (goal_alt_matched
[i
][0] == -1)
4215 int hard_regno
, byte
;
4216 enum op_type type
= curr_static_id
->operand
[i
].type
;
4218 loc
= curr_id
->operand_loc
[i
];
4219 mode
= curr_operand_mode
[i
];
4220 if (GET_CODE (*loc
) == SUBREG
)
4222 reg
= SUBREG_REG (*loc
);
4223 byte
= SUBREG_BYTE (*loc
);
4225 /* Strict_low_part requires reload the register not
4226 the sub-register. */
4227 && (curr_static_id
->operand
[i
].strict_low
4228 || (!paradoxical_subreg_p (mode
, GET_MODE (reg
))
4230 = get_try_hard_regno (REGNO (reg
))) >= 0
4231 && (simplify_subreg_regno
4233 GET_MODE (reg
), byte
, mode
) < 0)
4234 && (goal_alt
[i
] == NO_REGS
4235 || (simplify_subreg_regno
4236 (ira_class_hard_regs
[goal_alt
[i
]][0],
4237 GET_MODE (reg
), byte
, mode
) >= 0)))))
4239 /* An OP_INOUT is required when reloading a subreg of a
4240 mode wider than a word to ensure that data beyond the
4241 word being reloaded is preserved. Also automatically
4242 ensure that strict_low_part reloads are made into
4243 OP_INOUT which should already be true from the backend
4246 && (curr_static_id
->operand
[i
].strict_low
4247 || (GET_MODE_SIZE (GET_MODE (reg
)) > UNITS_PER_WORD
4248 && (GET_MODE_SIZE (mode
)
4249 < GET_MODE_SIZE (GET_MODE (reg
))))))
4251 loc
= &SUBREG_REG (*loc
);
4252 mode
= GET_MODE (*loc
);
4256 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
],
4257 loc
!= curr_id
->operand_loc
[i
], "", &new_reg
)
4260 push_to_sequence (before
);
4261 lra_emit_move (new_reg
, old
);
4262 before
= get_insns ();
4267 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
4270 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
4272 after
= get_insns ();
4276 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
4277 if (goal_alt_dont_inherit_ops
[j
] == i
)
4279 lra_set_regno_unique_value (REGNO (new_reg
));
4282 lra_update_dup (curr_id
, i
);
4284 else if (curr_static_id
->operand
[i
].type
== OP_IN
4285 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4288 /* generate reloads for input and matched outputs. */
4289 match_inputs
[0] = i
;
4290 match_inputs
[1] = -1;
4291 match_reload (goal_alt_matched
[i
][0], match_inputs
, outputs
,
4292 goal_alt
[i
], &before
, &after
,
4293 curr_static_id
->operand_alternative
4294 [goal_alt_number
* n_operands
+ goal_alt_matched
[i
][0]]
4297 else if (curr_static_id
->operand
[i
].type
== OP_OUT
4298 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4300 /* Generate reloads for output and matched inputs. */
4301 match_reload (i
, goal_alt_matched
[i
], outputs
, goal_alt
[i
], &before
,
4302 &after
, curr_static_id
->operand_alternative
4303 [goal_alt_number
* n_operands
+ i
].earlyclobber
);
4304 else if (curr_static_id
->operand
[i
].type
== OP_IN
4305 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
4308 /* Generate reloads for matched inputs. */
4309 match_inputs
[0] = i
;
4310 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
4311 match_inputs
[j
+ 1] = k
;
4312 match_inputs
[j
+ 1] = -1;
4313 match_reload (-1, match_inputs
, outputs
, goal_alt
[i
], &before
,
4317 /* We must generate code in any case when function
4318 process_alt_operands decides that it is possible. */
4321 /* Memorise processed outputs so that output remaining to be processed
4322 can avoid using the same register value (see match_reload). */
4323 if (curr_static_id
->operand
[i
].type
== OP_OUT
)
4325 outputs
[n_outputs
++] = i
;
4326 outputs
[n_outputs
] = -1;
4333 lra_assert (REG_P (reg
));
4334 regno
= REGNO (reg
);
4335 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
4336 if (GET_CODE (op
) == SUBREG
)
4337 op
= SUBREG_REG (op
);
4338 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
4339 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
4340 lra_reg_info
[REGNO (op
)].restore_rtx
= reg
;
4341 if (lra_dump_file
!= NULL
)
4342 fprintf (lra_dump_file
,
4343 " Making reload reg %d for reg %d optional\n",
4347 if (before
!= NULL_RTX
|| after
!= NULL_RTX
4348 || max_regno_before
!= max_reg_num ())
4352 lra_update_operator_dups (curr_id
);
4353 /* Something changes -- process the insn. */
4354 lra_update_insn_regno_info (curr_insn
);
4356 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
4360 /* Return true if INSN satisfies all constraints. In other words, no
4361 reload insns are needed. */
4363 lra_constrain_insn (rtx_insn
*insn
)
4365 int saved_new_regno_start
= new_regno_start
;
4366 int saved_new_insn_uid_start
= new_insn_uid_start
;
4370 curr_id
= lra_get_insn_recog_data (curr_insn
);
4371 curr_static_id
= curr_id
->insn_static_data
;
4372 new_insn_uid_start
= get_max_uid ();
4373 new_regno_start
= max_reg_num ();
4374 change_p
= curr_insn_transform (true);
4375 new_regno_start
= saved_new_regno_start
;
4376 new_insn_uid_start
= saved_new_insn_uid_start
;
4380 /* Return true if X is in LIST. */
4382 in_list_p (rtx x
, rtx list
)
4384 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
4385 if (XEXP (list
, 0) == x
)
4390 /* Return true if X contains an allocatable hard register (if
4391 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4393 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
4399 code
= GET_CODE (x
);
4402 int regno
= REGNO (x
);
4403 HARD_REG_SET alloc_regs
;
4407 if (regno
>= FIRST_PSEUDO_REGISTER
)
4408 regno
= lra_get_regno_hard_regno (regno
);
4411 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
4412 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
4416 if (regno
< FIRST_PSEUDO_REGISTER
)
4420 return lra_get_regno_hard_regno (regno
) < 0;
4423 fmt
= GET_RTX_FORMAT (code
);
4424 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4428 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
4431 else if (fmt
[i
] == 'E')
4433 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4434 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
4441 /* Process all regs in location *LOC and change them on equivalent
4442 substitution. Return true if any change was done. */
4444 loc_equivalence_change_p (rtx
*loc
)
4446 rtx subst
, reg
, x
= *loc
;
4447 bool result
= false;
4448 enum rtx_code code
= GET_CODE (x
);
4454 reg
= SUBREG_REG (x
);
4455 if ((subst
= get_equiv_with_elimination (reg
, curr_insn
)) != reg
4456 && GET_MODE (subst
) == VOIDmode
)
4458 /* We cannot reload debug location. Simplify subreg here
4459 while we know the inner mode. */
4460 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
4461 GET_MODE (reg
), SUBREG_BYTE (x
));
4465 if (code
== REG
&& (subst
= get_equiv_with_elimination (x
, curr_insn
)) != x
)
4471 /* Scan all the operand sub-expressions. */
4472 fmt
= GET_RTX_FORMAT (code
);
4473 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4476 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
4477 else if (fmt
[i
] == 'E')
4478 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4480 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
4485 /* Similar to loc_equivalence_change_p, but for use as
4486 simplify_replace_fn_rtx callback. DATA is insn for which the
4487 elimination is done. If it null we don't do the elimination. */
4489 loc_equivalence_callback (rtx loc
, const_rtx
, void *data
)
4494 rtx subst
= (data
== NULL
4495 ? get_equiv (loc
) : get_equiv_with_elimination (loc
, (rtx_insn
*) data
));
4502 /* Maximum number of generated reload insns per an insn. It is for
4503 preventing this pass cycling in a bug case. */
4504 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4506 /* The current iteration number of this LRA pass. */
4507 int lra_constraint_iter
;
4509 /* True if we substituted equiv which needs checking register
4510 allocation correctness because the equivalent value contains
4511 allocatable hard registers or when we restore multi-register
4513 bool lra_risky_transformations_p
;
4515 /* Return true if REGNO is referenced in more than one block. */
4517 multi_block_pseudo_p (int regno
)
4519 basic_block bb
= NULL
;
4523 if (regno
< FIRST_PSEUDO_REGISTER
)
4526 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
4528 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
4529 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
4534 /* Return true if LIST contains a deleted insn. */
4536 contains_deleted_insn_p (rtx_insn_list
*list
)
4538 for (; list
!= NULL_RTX
; list
= list
->next ())
4539 if (NOTE_P (list
->insn ())
4540 && NOTE_KIND (list
->insn ()) == NOTE_INSN_DELETED
)
4545 /* Return true if X contains a pseudo dying in INSN. */
4547 dead_pseudo_p (rtx x
, rtx_insn
*insn
)
4554 return (insn
!= NULL_RTX
4555 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
4556 code
= GET_CODE (x
);
4557 fmt
= GET_RTX_FORMAT (code
);
4558 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4562 if (dead_pseudo_p (XEXP (x
, i
), insn
))
4565 else if (fmt
[i
] == 'E')
4567 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4568 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
4575 /* Return true if INSN contains a dying pseudo in INSN right hand
4578 insn_rhs_dead_pseudo_p (rtx_insn
*insn
)
4580 rtx set
= single_set (insn
);
4582 gcc_assert (set
!= NULL
);
4583 return dead_pseudo_p (SET_SRC (set
), insn
);
4586 /* Return true if any init insn of REGNO contains a dying pseudo in
4587 insn right hand side. */
4589 init_insn_rhs_dead_pseudo_p (int regno
)
4591 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4595 for (; insns
!= NULL_RTX
; insns
= insns
->next ())
4596 if (insn_rhs_dead_pseudo_p (insns
->insn ()))
4601 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4602 reverse only if we have one init insn with given REGNO as a
4605 reverse_equiv_p (int regno
)
4607 rtx_insn_list
*insns
= ira_reg_equiv
[regno
].init_insns
;
4612 if (! INSN_P (insns
->insn ())
4613 || insns
->next () != NULL
)
4615 if ((set
= single_set (insns
->insn ())) == NULL_RTX
)
4617 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
4620 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4621 call this function only for non-reverse equivalence. */
4623 contains_reloaded_insn_p (int regno
)
4626 rtx_insn_list
*list
= ira_reg_equiv
[regno
].init_insns
;
4628 for (; list
!= NULL
; list
= list
->next ())
4629 if ((set
= single_set (list
->insn ())) == NULL_RTX
4630 || ! REG_P (SET_DEST (set
))
4631 || (int) REGNO (SET_DEST (set
)) != regno
)
4636 /* Entry function of LRA constraint pass. Return true if the
4637 constraint pass did change the code. */
4639 lra_constraints (bool first_p
)
4642 int i
, hard_regno
, new_insns_num
;
4643 unsigned int min_len
, new_min_len
, uid
;
4644 rtx set
, x
, reg
, dest_reg
;
4645 basic_block last_bb
;
4648 lra_constraint_iter
++;
4649 if (lra_dump_file
!= NULL
)
4650 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
4651 lra_constraint_iter
);
4653 if (pic_offset_table_rtx
4654 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
4655 lra_risky_transformations_p
= true;
4657 /* On the first iteration we should check IRA assignment
4658 correctness. In rare cases, the assignments can be wrong as
4659 early clobbers operands are ignored in IRA. */
4660 lra_risky_transformations_p
= first_p
;
4661 new_insn_uid_start
= get_max_uid ();
4662 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
4663 /* Mark used hard regs for target stack size calulations. */
4664 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4665 if (lra_reg_info
[i
].nrefs
!= 0
4666 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4670 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
4671 for (j
= 0; j
< nregs
; j
++)
4672 df_set_regs_ever_live (hard_regno
+ j
, true);
4674 /* Do elimination before the equivalence processing as we can spill
4675 some pseudos during elimination. */
4676 lra_eliminate (false, first_p
);
4677 auto_bitmap
equiv_insn_bitmap (®_obstack
);
4678 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4679 if (lra_reg_info
[i
].nrefs
!= 0)
4681 ira_reg_equiv
[i
].profitable_p
= true;
4682 reg
= regno_reg_rtx
[i
];
4683 if (lra_get_regno_hard_regno (i
) < 0 && (x
= get_equiv (reg
)) != reg
)
4685 bool pseudo_p
= contains_reg_p (x
, false, false);
4687 /* After RTL transformation, we can not guarantee that
4688 pseudo in the substitution was not reloaded which might
4689 make equivalence invalid. For example, in reverse
4696 the memory address register was reloaded before the 2nd
4698 if ((! first_p
&& pseudo_p
)
4699 /* We don't use DF for compilation speed sake. So it
4700 is problematic to update live info when we use an
4701 equivalence containing pseudos in more than one
4703 || (pseudo_p
&& multi_block_pseudo_p (i
))
4704 /* If an init insn was deleted for some reason, cancel
4705 the equiv. We could update the equiv insns after
4706 transformations including an equiv insn deletion
4707 but it is not worthy as such cases are extremely
4709 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
4710 /* If it is not a reverse equivalence, we check that a
4711 pseudo in rhs of the init insn is not dying in the
4712 insn. Otherwise, the live info at the beginning of
4713 the corresponding BB might be wrong after we
4714 removed the insn. When the equiv can be a
4715 constant, the right hand side of the init insn can
4717 || (! reverse_equiv_p (i
)
4718 && (init_insn_rhs_dead_pseudo_p (i
)
4719 /* If we reloaded the pseudo in an equivalence
4720 init insn, we can not remove the equiv init
4721 insns and the init insns might write into
4722 const memory in this case. */
4723 || contains_reloaded_insn_p (i
)))
4724 /* Prevent access beyond equivalent memory for
4725 paradoxical subregs. */
4727 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
4728 > GET_MODE_SIZE (GET_MODE (x
))))
4729 || (pic_offset_table_rtx
4730 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i
), x
)
4731 && (targetm
.preferred_reload_class
4732 (x
, lra_get_allocno_class (i
)) == NO_REGS
))
4733 || contains_symbol_ref_p (x
))))
4734 ira_reg_equiv
[i
].defined_p
= false;
4735 if (contains_reg_p (x
, false, true))
4736 ira_reg_equiv
[i
].profitable_p
= false;
4737 if (get_equiv (reg
) != reg
)
4738 bitmap_ior_into (equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
4741 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4743 /* We should add all insns containing pseudos which should be
4744 substituted by their equivalences. */
4745 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap
, 0, uid
, bi
)
4746 lra_push_insn_by_uid (uid
);
4747 min_len
= lra_insn_stack_length ();
4751 while ((new_min_len
= lra_insn_stack_length ()) != 0)
4753 curr_insn
= lra_pop_insn ();
4755 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4756 if (curr_bb
!= last_bb
)
4759 bb_reload_num
= lra_curr_reload_num
;
4761 if (min_len
> new_min_len
)
4763 min_len
= new_min_len
;
4766 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
4768 ("Max. number of generated reload insns per insn is achieved (%d)\n",
4769 MAX_RELOAD_INSNS_NUMBER
);
4771 if (DEBUG_INSN_P (curr_insn
))
4773 /* We need to check equivalence in debug insn and change
4774 pseudo to the equivalent value if necessary. */
4775 curr_id
= lra_get_insn_recog_data (curr_insn
);
4776 if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
)))
4778 rtx old
= *curr_id
->operand_loc
[0];
4779 *curr_id
->operand_loc
[0]
4780 = simplify_replace_fn_rtx (old
, NULL_RTX
,
4781 loc_equivalence_callback
, curr_insn
);
4782 if (old
!= *curr_id
->operand_loc
[0])
4784 lra_update_insn_regno_info (curr_insn
);
4789 else if (INSN_P (curr_insn
))
4791 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
4793 dest_reg
= SET_DEST (set
);
4794 /* The equivalence pseudo could be set up as SUBREG in a
4795 case when it is a call restore insn in a mode
4796 different from the pseudo mode. */
4797 if (GET_CODE (dest_reg
) == SUBREG
)
4798 dest_reg
= SUBREG_REG (dest_reg
);
4799 if ((REG_P (dest_reg
)
4800 && (x
= get_equiv (dest_reg
)) != dest_reg
4801 /* Remove insns which set up a pseudo whose value
4802 can not be changed. Such insns might be not in
4803 init_insns because we don't update equiv data
4804 during insn transformations.
4806 As an example, let suppose that a pseudo got
4807 hard register and on the 1st pass was not
4808 changed to equivalent constant. We generate an
4809 additional insn setting up the pseudo because of
4810 secondary memory movement. Then the pseudo is
4811 spilled and we use the equiv constant. In this
4812 case we should remove the additional insn and
4813 this insn is not init_insns list. */
4814 && (! MEM_P (x
) || MEM_READONLY_P (x
)
4815 /* Check that this is actually an insn setting
4816 up the equivalence. */
4817 || in_list_p (curr_insn
,
4819 [REGNO (dest_reg
)].init_insns
)))
4820 || (((x
= get_equiv (SET_SRC (set
))) != SET_SRC (set
))
4821 && in_list_p (curr_insn
,
4823 [REGNO (SET_SRC (set
))].init_insns
)))
4825 /* This is equiv init insn of pseudo which did not get a
4826 hard register -- remove the insn. */
4827 if (lra_dump_file
!= NULL
)
4829 fprintf (lra_dump_file
,
4830 " Removing equiv init insn %i (freq=%d)\n",
4831 INSN_UID (curr_insn
),
4832 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn
)));
4833 dump_insn_slim (lra_dump_file
, curr_insn
);
4835 if (contains_reg_p (x
, true, false))
4836 lra_risky_transformations_p
= true;
4837 lra_set_insn_deleted (curr_insn
);
4841 curr_id
= lra_get_insn_recog_data (curr_insn
);
4842 curr_static_id
= curr_id
->insn_static_data
;
4843 init_curr_insn_input_reloads ();
4844 init_curr_operand_mode ();
4845 if (curr_insn_transform (false))
4847 /* Check non-transformed insns too for equiv change as USE
4848 or CLOBBER don't need reloads but can contain pseudos
4849 being changed on their equivalences. */
4850 else if (bitmap_bit_p (equiv_insn_bitmap
, INSN_UID (curr_insn
))
4851 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4853 lra_update_insn_regno_info (curr_insn
);
4859 /* If we used a new hard regno, changed_p should be true because the
4860 hard reg is assigned to a new pseudo. */
4861 if (flag_checking
&& !changed_p
)
4863 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4864 if (lra_reg_info
[i
].nrefs
!= 0
4865 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4867 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4869 for (j
= 0; j
< nregs
; j
++)
4870 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4876 static void initiate_invariants (void);
4877 static void finish_invariants (void);
4879 /* Initiate the LRA constraint pass. It is done once per
4882 lra_constraints_init (void)
4884 initiate_invariants ();
4887 /* Finalize the LRA constraint pass. It is done once per
4890 lra_constraints_finish (void)
4892 finish_invariants ();
4897 /* Structure describes invariants for ineheritance. */
4898 struct lra_invariant
4900 /* The order number of the invariant. */
4902 /* The invariant RTX. */
4904 /* The origin insn of the invariant. */
4908 typedef lra_invariant invariant_t
;
4909 typedef invariant_t
*invariant_ptr_t
;
4910 typedef const invariant_t
*const_invariant_ptr_t
;
4912 /* Pointer to the inheritance invariants. */
4913 static vec
<invariant_ptr_t
> invariants
;
4915 /* Allocation pool for the invariants. */
4916 static object_allocator
<lra_invariant
> *invariants_pool
;
4918 /* Hash table for the invariants. */
4919 static htab_t invariant_table
;
4921 /* Hash function for INVARIANT. */
4923 invariant_hash (const void *invariant
)
4925 rtx inv
= ((const_invariant_ptr_t
) invariant
)->invariant_rtx
;
4926 return lra_rtx_hash (inv
);
4929 /* Equal function for invariants INVARIANT1 and INVARIANT2. */
4931 invariant_eq_p (const void *invariant1
, const void *invariant2
)
4933 rtx inv1
= ((const_invariant_ptr_t
) invariant1
)->invariant_rtx
;
4934 rtx inv2
= ((const_invariant_ptr_t
) invariant2
)->invariant_rtx
;
4936 return rtx_equal_p (inv1
, inv2
);
4939 /* Insert INVARIANT_RTX into the table if it is not there yet. Return
4940 invariant which is in the table. */
4941 static invariant_ptr_t
4942 insert_invariant (rtx invariant_rtx
)
4945 invariant_t invariant
;
4946 invariant_ptr_t invariant_ptr
;
4948 invariant
.invariant_rtx
= invariant_rtx
;
4949 entry_ptr
= htab_find_slot (invariant_table
, &invariant
, INSERT
);
4950 if (*entry_ptr
== NULL
)
4952 invariant_ptr
= invariants_pool
->allocate ();
4953 invariant_ptr
->invariant_rtx
= invariant_rtx
;
4954 invariant_ptr
->insn
= NULL
;
4955 invariants
.safe_push (invariant_ptr
);
4956 *entry_ptr
= (void *) invariant_ptr
;
4958 return (invariant_ptr_t
) *entry_ptr
;
4961 /* Initiate the invariant table. */
4963 initiate_invariants (void)
4965 invariants
.create (100);
4967 = new object_allocator
<lra_invariant
> ("Inheritance invariants");
4968 invariant_table
= htab_create (100, invariant_hash
, invariant_eq_p
, NULL
);
4971 /* Finish the invariant table. */
4973 finish_invariants (void)
4975 htab_delete (invariant_table
);
4976 delete invariants_pool
;
4977 invariants
.release ();
4980 /* Make the invariant table empty. */
4982 clear_invariants (void)
4984 htab_empty (invariant_table
);
4985 invariants_pool
->release ();
4986 invariants
.truncate (0);
4991 /* This page contains code to do inheritance/split
4994 /* Number of reloads passed so far in current EBB. */
4995 static int reloads_num
;
4997 /* Number of calls passed so far in current EBB. */
4998 static int calls_num
;
5000 /* Current reload pseudo check for validity of elements in
5002 static int curr_usage_insns_check
;
5004 /* Info about last usage of registers in EBB to do inheritance/split
5005 transformation. Inheritance transformation is done from a spilled
5006 pseudo and split transformations from a hard register or a pseudo
5007 assigned to a hard register. */
5010 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5011 value INSNS is valid. The insns is chain of optional debug insns
5012 and a finishing non-debug insn using the corresponding reg. The
5013 value is also used to mark the registers which are set up in the
5014 current insn. The negated insn uid is used for this. */
5016 /* Value of global reloads_num at the last insn in INSNS. */
5018 /* Value of global reloads_nums at the last insn in INSNS. */
5020 /* It can be true only for splitting. And it means that the restore
5021 insn should be put after insn given by the following member. */
5023 /* Next insns in the current EBB which use the original reg and the
5024 original reg value is not changed between the current insn and
5025 the next insns. In order words, e.g. for inheritance, if we need
5026 to use the original reg value again in the next insns we can try
5027 to use the value in a hard register from a reload insn of the
5032 /* Map: regno -> corresponding pseudo usage insns. */
5033 static struct usage_insns
*usage_insns
;
5036 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
5038 usage_insns
[regno
].check
= curr_usage_insns_check
;
5039 usage_insns
[regno
].insns
= insn
;
5040 usage_insns
[regno
].reloads_num
= reloads_num
;
5041 usage_insns
[regno
].calls_num
= calls_num
;
5042 usage_insns
[regno
].after_p
= after_p
;
5045 /* The function is used to form list REGNO usages which consists of
5046 optional debug insns finished by a non-debug insn using REGNO.
5047 RELOADS_NUM is current number of reload insns processed so far. */
5049 add_next_usage_insn (int regno
, rtx_insn
*insn
, int reloads_num
)
5051 rtx next_usage_insns
;
5053 if (usage_insns
[regno
].check
== curr_usage_insns_check
5054 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
5055 && DEBUG_INSN_P (insn
))
5057 /* Check that we did not add the debug insn yet. */
5058 if (next_usage_insns
!= insn
5059 && (GET_CODE (next_usage_insns
) != INSN_LIST
5060 || XEXP (next_usage_insns
, 0) != insn
))
5061 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
5064 else if (NONDEBUG_INSN_P (insn
))
5065 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
5067 usage_insns
[regno
].check
= 0;
5070 /* Return first non-debug insn in list USAGE_INSNS. */
5072 skip_usage_debug_insns (rtx usage_insns
)
5076 /* Skip debug insns. */
5077 for (insn
= usage_insns
;
5078 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
5079 insn
= XEXP (insn
, 1))
5081 return safe_as_a
<rtx_insn
*> (insn
);
5084 /* Return true if we need secondary memory moves for insn in
5085 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5088 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
5089 rtx usage_insns ATTRIBUTE_UNUSED
)
5091 #ifndef SECONDARY_MEMORY_NEEDED
5098 if (inher_cl
== ALL_REGS
5099 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
5101 lra_assert (INSN_P (insn
));
5102 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
5104 dest
= SET_DEST (set
);
5107 lra_assert (inher_cl
!= NO_REGS
);
5108 cl
= get_reg_class (REGNO (dest
));
5109 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
5110 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
5114 /* Registers involved in inheritance/split in the current EBB
5115 (inheritance/split pseudos and original registers). */
5116 static bitmap_head check_only_regs
;
5118 /* Reload pseudos can not be involded in invariant inheritance in the
5120 static bitmap_head invalid_invariant_regs
;
5122 /* Do inheritance transformations for insn INSN, which defines (if
5123 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5124 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5125 form as the "insns" field of usage_insns. Return true if we
5126 succeed in such transformation.
5128 The transformations look like:
5131 ... p <- i (new insn)
5133 <- ... p ... <- ... i ...
5135 ... i <- p (new insn)
5136 <- ... p ... <- ... i ...
5138 <- ... p ... <- ... i ...
5139 where p is a spilled original pseudo and i is a new inheritance pseudo.
5142 The inheritance pseudo has the smallest class of two classes CL and
5143 class of ORIGINAL REGNO. */
5145 inherit_reload_reg (bool def_p
, int original_regno
,
5146 enum reg_class cl
, rtx_insn
*insn
, rtx next_usage_insns
)
5148 if (optimize_function_for_size_p (cfun
))
5151 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
5152 rtx original_reg
= regno_reg_rtx
[original_regno
];
5153 rtx new_reg
, usage_insn
;
5154 rtx_insn
*new_insns
;
5156 lra_assert (! usage_insns
[original_regno
].after_p
);
5157 if (lra_dump_file
!= NULL
)
5158 fprintf (lra_dump_file
,
5159 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5160 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
5162 if (lra_dump_file
!= NULL
)
5164 fprintf (lra_dump_file
,
5165 " Rejecting inheritance for %d "
5166 "because of disjoint classes %s and %s\n",
5167 original_regno
, reg_class_names
[cl
],
5168 reg_class_names
[rclass
]);
5169 fprintf (lra_dump_file
,
5170 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5174 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
5175 /* We don't use a subset of two classes because it can be
5176 NO_REGS. This transformation is still profitable in most
5177 cases even if the classes are not intersected as register
5178 move is probably cheaper than a memory load. */
5179 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
5181 if (lra_dump_file
!= NULL
)
5182 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
5183 reg_class_names
[cl
], reg_class_names
[rclass
]);
5187 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
5189 /* Reject inheritance resulting in secondary memory moves.
5190 Otherwise, there is a danger in LRA cycling. Also such
5191 transformation will be unprofitable. */
5192 if (lra_dump_file
!= NULL
)
5194 rtx_insn
*insn
= skip_usage_debug_insns (next_usage_insns
);
5195 rtx set
= single_set (insn
);
5197 lra_assert (set
!= NULL_RTX
);
5199 rtx dest
= SET_DEST (set
);
5201 lra_assert (REG_P (dest
));
5202 fprintf (lra_dump_file
,
5203 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5204 "as secondary mem is needed\n",
5205 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
5206 original_regno
, reg_class_names
[rclass
]);
5207 fprintf (lra_dump_file
,
5208 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5212 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
5213 rclass
, "inheritance");
5216 lra_emit_move (original_reg
, new_reg
);
5218 lra_emit_move (new_reg
, original_reg
);
5219 new_insns
= get_insns ();
5221 if (NEXT_INSN (new_insns
) != NULL_RTX
)
5223 if (lra_dump_file
!= NULL
)
5225 fprintf (lra_dump_file
,
5226 " Rejecting inheritance %d->%d "
5227 "as it results in 2 or more insns:\n",
5228 original_regno
, REGNO (new_reg
));
5229 dump_rtl_slim (lra_dump_file
, new_insns
, NULL
, -1, 0);
5230 fprintf (lra_dump_file
,
5231 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5235 lra_substitute_pseudo_within_insn (insn
, original_regno
, new_reg
, false);
5236 lra_update_insn_regno_info (insn
);
5238 /* We now have a new usage insn for original regno. */
5239 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
5240 if (lra_dump_file
!= NULL
)
5241 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
5242 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5243 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= regno_reg_rtx
[original_regno
];
5244 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5245 bitmap_set_bit (&check_only_regs
, original_regno
);
5246 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5248 lra_process_new_insns (insn
, NULL
, new_insns
,
5249 "Add original<-inheritance");
5251 lra_process_new_insns (insn
, new_insns
, NULL
,
5252 "Add inheritance<-original");
5253 while (next_usage_insns
!= NULL_RTX
)
5255 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5257 usage_insn
= next_usage_insns
;
5258 lra_assert (NONDEBUG_INSN_P (usage_insn
));
5259 next_usage_insns
= NULL
;
5263 usage_insn
= XEXP (next_usage_insns
, 0);
5264 lra_assert (DEBUG_INSN_P (usage_insn
));
5265 next_usage_insns
= XEXP (next_usage_insns
, 1);
5267 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5268 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5269 if (lra_dump_file
!= NULL
)
5271 fprintf (lra_dump_file
,
5272 " Inheritance reuse change %d->%d (bb%d):\n",
5273 original_regno
, REGNO (new_reg
),
5274 BLOCK_FOR_INSN (usage_insn
)->index
);
5275 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5278 if (lra_dump_file
!= NULL
)
5279 fprintf (lra_dump_file
,
5280 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5284 /* Return true if we need a caller save/restore for pseudo REGNO which
5285 was assigned to a hard register. */
5287 need_for_call_save_p (int regno
)
5289 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
5290 return (usage_insns
[regno
].calls_num
< calls_num
5291 && (overlaps_hard_reg_set_p
5293 ! hard_reg_set_empty_p (lra_reg_info
[regno
].actual_call_used_reg_set
))
5294 ? lra_reg_info
[regno
].actual_call_used_reg_set
5295 : call_used_reg_set
,
5296 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
5297 || (targetm
.hard_regno_call_part_clobbered
5298 (reg_renumber
[regno
], PSEUDO_REGNO_MODE (regno
)))));
5301 /* Global registers occurring in the current EBB. */
5302 static bitmap_head ebb_global_regs
;
5304 /* Return true if we need a split for hard register REGNO or pseudo
5305 REGNO which was assigned to a hard register.
5306 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5307 used for reloads since the EBB end. It is an approximation of the
5308 used hard registers in the split range. The exact value would
5309 require expensive calculations. If we were aggressive with
5310 splitting because of the approximation, the split pseudo will save
5311 the same hard register assignment and will be removed in the undo
5312 pass. We still need the approximation because too aggressive
5313 splitting would result in too inaccurate cost calculation in the
5314 assignment pass because of too many generated moves which will be
5315 probably removed in the undo pass. */
5317 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
5319 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
5321 lra_assert (hard_regno
>= 0);
5322 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
5323 /* Don't split eliminable hard registers, otherwise we can
5324 split hard registers like hard frame pointer, which
5325 lives on BB start/end according to DF-infrastructure,
5326 when there is a pseudo assigned to the register and
5327 living in the same BB. */
5328 && (regno
>= FIRST_PSEUDO_REGISTER
5329 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
5330 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
5331 /* Don't split call clobbered hard regs living through
5332 calls, otherwise we might have a check problem in the
5333 assign sub-pass as in the most cases (exception is a
5334 situation when lra_risky_transformations_p value is
5335 true) the assign pass assumes that all pseudos living
5336 through calls are assigned to call saved hard regs. */
5337 && (regno
>= FIRST_PSEUDO_REGISTER
5338 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
5339 || usage_insns
[regno
].calls_num
== calls_num
)
5340 /* We need at least 2 reloads to make pseudo splitting
5341 profitable. We should provide hard regno splitting in
5342 any case to solve 1st insn scheduling problem when
5343 moving hard register definition up might result in
5344 impossibility to find hard register for reload pseudo of
5345 small register class. */
5346 && (usage_insns
[regno
].reloads_num
5347 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 3) < reloads_num
)
5348 && (regno
< FIRST_PSEUDO_REGISTER
5349 /* For short living pseudos, spilling + inheritance can
5350 be considered a substitution for splitting.
5351 Therefore we do not splitting for local pseudos. It
5352 decreases also aggressiveness of splitting. The
5353 minimal number of references is chosen taking into
5354 account that for 2 references splitting has no sense
5355 as we can just spill the pseudo. */
5356 || (regno
>= FIRST_PSEUDO_REGISTER
5357 && lra_reg_info
[regno
].nrefs
> 3
5358 && bitmap_bit_p (&ebb_global_regs
, regno
))))
5359 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
5362 /* Return class for the split pseudo created from original pseudo with
5363 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5364 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5365 results in no secondary memory movements. */
5366 static enum reg_class
5367 choose_split_class (enum reg_class allocno_class
,
5368 int hard_regno ATTRIBUTE_UNUSED
,
5369 machine_mode mode ATTRIBUTE_UNUSED
)
5371 #ifndef SECONDARY_MEMORY_NEEDED
5372 return allocno_class
;
5375 enum reg_class cl
, best_cl
= NO_REGS
;
5376 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5377 = REGNO_REG_CLASS (hard_regno
);
5379 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
5380 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
5381 return allocno_class
;
5383 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
5385 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
5386 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
5387 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
5388 && (best_cl
== NO_REGS
5389 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
5395 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5396 It only makes sense to call this function if NEW_REGNO is always
5397 equal to ORIGINAL_REGNO. */
5400 lra_copy_reg_equiv (unsigned int new_regno
, unsigned int original_regno
)
5402 if (!ira_reg_equiv
[original_regno
].defined_p
)
5405 ira_expand_reg_equiv ();
5406 ira_reg_equiv
[new_regno
].defined_p
= true;
5407 if (ira_reg_equiv
[original_regno
].memory
)
5408 ira_reg_equiv
[new_regno
].memory
5409 = copy_rtx (ira_reg_equiv
[original_regno
].memory
);
5410 if (ira_reg_equiv
[original_regno
].constant
)
5411 ira_reg_equiv
[new_regno
].constant
5412 = copy_rtx (ira_reg_equiv
[original_regno
].constant
);
5413 if (ira_reg_equiv
[original_regno
].invariant
)
5414 ira_reg_equiv
[new_regno
].invariant
5415 = copy_rtx (ira_reg_equiv
[original_regno
].invariant
);
5418 /* Do split transformations for insn INSN, which defines or uses
5419 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5420 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5421 "insns" field of usage_insns.
5423 The transformations look like:
5426 ... s <- p (new insn -- save)
5428 ... p <- s (new insn -- restore)
5429 <- ... p ... <- ... p ...
5431 <- ... p ... <- ... p ...
5432 ... s <- p (new insn -- save)
5434 ... p <- s (new insn -- restore)
5435 <- ... p ... <- ... p ...
5437 where p is an original pseudo got a hard register or a hard
5438 register and s is a new split pseudo. The save is put before INSN
5439 if BEFORE_P is true. Return true if we succeed in such
5442 split_reg (bool before_p
, int original_regno
, rtx_insn
*insn
,
5443 rtx next_usage_insns
)
5445 enum reg_class rclass
;
5447 int hard_regno
, nregs
;
5448 rtx new_reg
, usage_insn
;
5449 rtx_insn
*restore
, *save
;
5454 if (original_regno
< FIRST_PSEUDO_REGISTER
)
5456 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
5457 hard_regno
= original_regno
;
5458 call_save_p
= false;
5460 mode
= lra_reg_info
[hard_regno
].biggest_mode
;
5461 machine_mode reg_rtx_mode
= GET_MODE (regno_reg_rtx
[hard_regno
]);
5462 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen
5463 as part of a multi-word register. In that case, or if the biggest
5464 mode was larger than a register, just use the reg_rtx. Otherwise,
5465 limit the size to that of the biggest access in the function. */
5466 if (mode
== VOIDmode
5467 || paradoxical_subreg_p (mode
, reg_rtx_mode
))
5469 original_reg
= regno_reg_rtx
[hard_regno
];
5470 mode
= reg_rtx_mode
;
5473 original_reg
= gen_rtx_REG (mode
, hard_regno
);
5477 mode
= PSEUDO_REGNO_MODE (original_regno
);
5478 hard_regno
= reg_renumber
[original_regno
];
5479 nregs
= hard_regno_nregs
[hard_regno
][mode
];
5480 rclass
= lra_get_allocno_class (original_regno
);
5481 original_reg
= regno_reg_rtx
[original_regno
];
5482 call_save_p
= need_for_call_save_p (original_regno
);
5484 lra_assert (hard_regno
>= 0);
5485 if (lra_dump_file
!= NULL
)
5486 fprintf (lra_dump_file
,
5487 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
5491 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
5492 hard_regno_nregs
[hard_regno
][mode
],
5494 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
5498 rclass
= choose_split_class (rclass
, hard_regno
, mode
);
5499 if (rclass
== NO_REGS
)
5501 if (lra_dump_file
!= NULL
)
5503 fprintf (lra_dump_file
,
5504 " Rejecting split of %d(%s): "
5505 "no good reg class for %d(%s)\n",
5507 reg_class_names
[lra_get_allocno_class (original_regno
)],
5509 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
5512 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5516 /* Split_if_necessary can split hard registers used as part of a
5517 multi-register mode but splits each register individually. The
5518 mode used for each independent register may not be supported
5519 so reject the split. Splitting the wider mode should theoretically
5520 be possible but is not implemented. */
5521 if (!targetm
.hard_regno_mode_ok (hard_regno
, mode
))
5523 if (lra_dump_file
!= NULL
)
5525 fprintf (lra_dump_file
,
5526 " Rejecting split of %d(%s): unsuitable mode %s\n",
5528 reg_class_names
[lra_get_allocno_class (original_regno
)],
5529 GET_MODE_NAME (mode
));
5532 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5536 new_reg
= lra_create_new_reg (mode
, original_reg
, rclass
, "split");
5537 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
5539 int new_regno
= REGNO (new_reg
);
5540 save
= emit_spill_move (true, new_reg
, original_reg
);
5541 if (NEXT_INSN (save
) != NULL_RTX
&& !call_save_p
)
5543 if (lra_dump_file
!= NULL
)
5547 " Rejecting split %d->%d resulting in > 2 save insns:\n",
5548 original_regno
, new_regno
);
5549 dump_rtl_slim (lra_dump_file
, save
, NULL
, -1, 0);
5550 fprintf (lra_dump_file
,
5551 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5555 restore
= emit_spill_move (false, new_reg
, original_reg
);
5556 if (NEXT_INSN (restore
) != NULL_RTX
&& !call_save_p
)
5558 if (lra_dump_file
!= NULL
)
5560 fprintf (lra_dump_file
,
5561 " Rejecting split %d->%d "
5562 "resulting in > 2 restore insns:\n",
5563 original_regno
, new_regno
);
5564 dump_rtl_slim (lra_dump_file
, restore
, NULL
, -1, 0);
5565 fprintf (lra_dump_file
,
5566 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5570 /* Transfer equivalence information to the spill register, so that
5571 if we fail to allocate the spill register, we have the option of
5572 rematerializing the original value instead of spilling to the stack. */
5573 if (!HARD_REGISTER_NUM_P (original_regno
)
5574 && mode
== PSEUDO_REGNO_MODE (original_regno
))
5575 lra_copy_reg_equiv (new_regno
, original_regno
);
5576 after_p
= usage_insns
[original_regno
].after_p
;
5577 lra_reg_info
[new_regno
].restore_rtx
= regno_reg_rtx
[original_regno
];
5578 bitmap_set_bit (&check_only_regs
, new_regno
);
5579 bitmap_set_bit (&check_only_regs
, original_regno
);
5580 bitmap_set_bit (&lra_split_regs
, new_regno
);
5583 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
5585 usage_insn
= next_usage_insns
;
5588 usage_insn
= XEXP (next_usage_insns
, 0);
5589 lra_assert (DEBUG_INSN_P (usage_insn
));
5590 next_usage_insns
= XEXP (next_usage_insns
, 1);
5591 lra_substitute_pseudo (&usage_insn
, original_regno
, new_reg
, false);
5592 lra_update_insn_regno_info (as_a
<rtx_insn
*> (usage_insn
));
5593 if (lra_dump_file
!= NULL
)
5595 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
5596 original_regno
, new_regno
);
5597 dump_insn_slim (lra_dump_file
, as_a
<rtx_insn
*> (usage_insn
));
5600 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
5601 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
5602 lra_process_new_insns (as_a
<rtx_insn
*> (usage_insn
),
5603 after_p
? NULL
: restore
,
5604 after_p
? restore
: NULL
,
5606 ? "Add reg<-save" : "Add reg<-split");
5607 lra_process_new_insns (insn
, before_p
? save
: NULL
,
5608 before_p
? NULL
: save
,
5610 ? "Add save<-reg" : "Add split<-reg");
5612 /* If we are trying to split multi-register. We should check
5613 conflicts on the next assignment sub-pass. IRA can allocate on
5614 sub-register levels, LRA do this on pseudos level right now and
5615 this discrepancy may create allocation conflicts after
5617 lra_risky_transformations_p
= true;
5618 if (lra_dump_file
!= NULL
)
5619 fprintf (lra_dump_file
,
5620 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
5624 /* Recognize that we need a split transformation for insn INSN, which
5625 defines or uses REGNO in its insn biggest MODE (we use it only if
5626 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
5627 hard registers which might be used for reloads since the EBB end.
5628 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
5629 uid before starting INSN processing. Return true if we succeed in
5630 such transformation. */
5632 split_if_necessary (int regno
, machine_mode mode
,
5633 HARD_REG_SET potential_reload_hard_regs
,
5634 bool before_p
, rtx_insn
*insn
, int max_uid
)
5638 rtx next_usage_insns
;
5640 if (regno
< FIRST_PSEUDO_REGISTER
)
5641 nregs
= hard_regno_nregs
[regno
][mode
];
5642 for (i
= 0; i
< nregs
; i
++)
5643 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
5644 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
5645 /* To avoid processing the register twice or more. */
5646 && ((GET_CODE (next_usage_insns
) != INSN_LIST
5647 && INSN_UID (next_usage_insns
) < max_uid
)
5648 || (GET_CODE (next_usage_insns
) == INSN_LIST
5649 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
5650 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
5651 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
5656 /* Return TRUE if rtx X is considered as an invariant for
5659 invariant_p (const_rtx x
)
5666 code
= GET_CODE (x
);
5667 mode
= GET_MODE (x
);
5671 code
= GET_CODE (x
);
5672 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
5673 mode
= GET_MODE (x
);
5681 int i
, nregs
, regno
= REGNO (x
);
5683 if (regno
>= FIRST_PSEUDO_REGISTER
|| regno
== STACK_POINTER_REGNUM
5684 || TEST_HARD_REG_BIT (eliminable_regset
, regno
)
5685 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
5687 nregs
= hard_regno_nregs
[regno
][mode
];
5688 for (i
= 0; i
< nregs
; i
++)
5689 if (! fixed_regs
[regno
+ i
]
5690 /* A hard register may be clobbered in the current insn
5691 but we can ignore this case because if the hard
5692 register is used it should be set somewhere after the
5694 || bitmap_bit_p (&invalid_invariant_regs
, regno
+ i
))
5697 fmt
= GET_RTX_FORMAT (code
);
5698 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5702 if (! invariant_p (XEXP (x
, i
)))
5705 else if (fmt
[i
] == 'E')
5707 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5708 if (! invariant_p (XVECEXP (x
, i
, j
)))
5715 /* We have 'dest_reg <- invariant'. Let us try to make an invariant
5716 inheritance transformation (using dest_reg instead invariant in a
5717 subsequent insn). */
5719 process_invariant_for_inheritance (rtx dst_reg
, rtx invariant_rtx
)
5721 invariant_ptr_t invariant_ptr
;
5722 rtx_insn
*insn
, *new_insns
;
5723 rtx insn_set
, insn_reg
, new_reg
;
5725 bool succ_p
= false;
5726 int dst_regno
= REGNO (dst_reg
);
5727 machine_mode dst_mode
= GET_MODE (dst_reg
);
5728 enum reg_class cl
= lra_get_allocno_class (dst_regno
), insn_reg_cl
;
5730 invariant_ptr
= insert_invariant (invariant_rtx
);
5731 if ((insn
= invariant_ptr
->insn
) != NULL_RTX
)
5733 /* We have a subsequent insn using the invariant. */
5734 insn_set
= single_set (insn
);
5735 lra_assert (insn_set
!= NULL
);
5736 insn_reg
= SET_DEST (insn_set
);
5737 lra_assert (REG_P (insn_reg
));
5738 insn_regno
= REGNO (insn_reg
);
5739 insn_reg_cl
= lra_get_allocno_class (insn_regno
);
5741 if (dst_mode
== GET_MODE (insn_reg
)
5742 /* We should consider only result move reg insns which are
5744 && targetm
.register_move_cost (dst_mode
, cl
, insn_reg_cl
) == 2
5745 && targetm
.register_move_cost (dst_mode
, cl
, cl
) == 2)
5747 if (lra_dump_file
!= NULL
)
5748 fprintf (lra_dump_file
,
5749 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
5750 new_reg
= lra_create_new_reg (dst_mode
, dst_reg
,
5751 cl
, "invariant inheritance");
5752 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
5753 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
5754 lra_reg_info
[REGNO (new_reg
)].restore_rtx
= PATTERN (insn
);
5756 lra_emit_move (new_reg
, dst_reg
);
5757 new_insns
= get_insns ();
5759 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
5760 "Add invariant inheritance<-original");
5762 lra_emit_move (SET_DEST (insn_set
), new_reg
);
5763 new_insns
= get_insns ();
5765 lra_process_new_insns (insn
, NULL
, new_insns
,
5766 "Changing reload<-inheritance");
5767 lra_set_insn_deleted (insn
);
5769 if (lra_dump_file
!= NULL
)
5771 fprintf (lra_dump_file
,
5772 " Invariant inheritance reuse change %d (bb%d):\n",
5773 REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
5774 dump_insn_slim (lra_dump_file
, insn
);
5775 fprintf (lra_dump_file
,
5776 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
5780 invariant_ptr
->insn
= curr_insn
;
5784 /* Check only registers living at the current program point in the
5786 static bitmap_head live_regs
;
5788 /* Update live info in EBB given by its HEAD and TAIL insns after
5789 inheritance/split transformation. The function removes dead moves
5792 update_ebb_live_info (rtx_insn
*head
, rtx_insn
*tail
)
5797 rtx_insn
*prev_insn
;
5800 basic_block last_bb
, prev_bb
, curr_bb
;
5802 struct lra_insn_reg
*reg
;
5806 last_bb
= BLOCK_FOR_INSN (tail
);
5808 for (curr_insn
= tail
;
5809 curr_insn
!= PREV_INSN (head
);
5810 curr_insn
= prev_insn
)
5812 prev_insn
= PREV_INSN (curr_insn
);
5813 /* We need to process empty blocks too. They contain
5814 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
5815 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
5817 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
5818 if (curr_bb
!= prev_bb
)
5820 if (prev_bb
!= NULL
)
5822 /* Update df_get_live_in (prev_bb): */
5823 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5824 if (bitmap_bit_p (&live_regs
, j
))
5825 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
5827 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
5829 if (curr_bb
!= last_bb
)
5831 /* Update df_get_live_out (curr_bb): */
5832 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
5834 live_p
= bitmap_bit_p (&live_regs
, j
);
5836 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
5837 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
5843 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
5845 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
5849 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
5851 if (! NONDEBUG_INSN_P (curr_insn
))
5853 curr_id
= lra_get_insn_recog_data (curr_insn
);
5854 curr_static_id
= curr_id
->insn_static_data
;
5856 if ((set
= single_set (curr_insn
)) != NULL_RTX
5857 && REG_P (SET_DEST (set
))
5858 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
5859 && SET_DEST (set
) != pic_offset_table_rtx
5860 && bitmap_bit_p (&check_only_regs
, regno
)
5861 && ! bitmap_bit_p (&live_regs
, regno
))
5863 /* See which defined values die here. */
5864 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5865 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5866 bitmap_clear_bit (&live_regs
, reg
->regno
);
5867 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5868 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
5869 bitmap_clear_bit (&live_regs
, reg
->regno
);
5870 if (curr_id
->arg_hard_regs
!= NULL
)
5871 /* Make clobbered argument hard registers die. */
5872 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5873 if (regno
>= FIRST_PSEUDO_REGISTER
)
5874 bitmap_clear_bit (&live_regs
, regno
- FIRST_PSEUDO_REGISTER
);
5875 /* Mark each used value as live. */
5876 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5877 if (reg
->type
!= OP_OUT
5878 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5879 bitmap_set_bit (&live_regs
, reg
->regno
);
5880 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
5881 if (reg
->type
!= OP_OUT
5882 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
5883 bitmap_set_bit (&live_regs
, reg
->regno
);
5884 if (curr_id
->arg_hard_regs
!= NULL
)
5885 /* Make used argument hard registers live. */
5886 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
5887 if (regno
< FIRST_PSEUDO_REGISTER
5888 && bitmap_bit_p (&check_only_regs
, regno
))
5889 bitmap_set_bit (&live_regs
, regno
);
5890 /* It is quite important to remove dead move insns because it
5891 means removing dead store. We don't need to process them for
5895 if (lra_dump_file
!= NULL
)
5897 fprintf (lra_dump_file
, " Removing dead insn:\n ");
5898 dump_insn_slim (lra_dump_file
, curr_insn
);
5900 lra_set_insn_deleted (curr_insn
);
5905 /* The structure describes info to do an inheritance for the current
5906 insn. We need to collect such info first before doing the
5907 transformations because the transformations change the insn
5908 internal representation. */
5911 /* Original regno. */
5913 /* Subsequent insns which can inherit original reg value. */
5917 /* Array containing all info for doing inheritance from the current
5919 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
5921 /* Number elements in the previous array. */
5922 static int to_inherit_num
;
5924 /* Add inheritance info REGNO and INSNS. Their meaning is described in
5925 structure to_inherit. */
5927 add_to_inherit (int regno
, rtx insns
)
5931 for (i
= 0; i
< to_inherit_num
; i
++)
5932 if (to_inherit
[i
].regno
== regno
)
5934 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
5935 to_inherit
[to_inherit_num
].regno
= regno
;
5936 to_inherit
[to_inherit_num
++].insns
= insns
;
5939 /* Return the last non-debug insn in basic block BB, or the block begin
5942 get_last_insertion_point (basic_block bb
)
5946 FOR_BB_INSNS_REVERSE (bb
, insn
)
5947 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
5952 /* Set up RES by registers living on edges FROM except the edge (FROM,
5953 TO) or by registers set up in a jump insn in BB FROM. */
5955 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
5958 struct lra_insn_reg
*reg
;
5962 lra_assert (to
!= NULL
);
5964 FOR_EACH_EDGE (e
, ei
, from
->succs
)
5966 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
5967 last
= get_last_insertion_point (from
);
5968 if (! JUMP_P (last
))
5970 curr_id
= lra_get_insn_recog_data (last
);
5971 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5972 if (reg
->type
!= OP_IN
)
5973 bitmap_set_bit (res
, reg
->regno
);
5976 /* Used as a temporary results of some bitmap calculations. */
5977 static bitmap_head temp_bitmap
;
5979 /* We split for reloads of small class of hard regs. The following
5980 defines how many hard regs the class should have to be qualified as
5981 small. The code is mostly oriented to x86/x86-64 architecture
5982 where some insns need to use only specific register or pair of
5983 registers and these register can live in RTL explicitly, e.g. for
5984 parameter passing. */
5985 static const int max_small_class_regs_num
= 2;
5987 /* Do inheritance/split transformations in EBB starting with HEAD and
5988 finishing on TAIL. We process EBB insns in the reverse order.
5989 Return true if we did any inheritance/split transformation in the
5992 We should avoid excessive splitting which results in worse code
5993 because of inaccurate cost calculations for spilling new split
5994 pseudos in such case. To achieve this we do splitting only if
5995 register pressure is high in given basic block and there are reload
5996 pseudos requiring hard registers. We could do more register
5997 pressure calculations at any given program point to avoid necessary
5998 splitting even more but it is to expensive and the current approach
5999 works well enough. */
6001 inherit_in_ebb (rtx_insn
*head
, rtx_insn
*tail
)
6003 int i
, src_regno
, dst_regno
, nregs
;
6004 bool change_p
, succ_p
, update_reloads_num_p
;
6005 rtx_insn
*prev_insn
, *last_insn
;
6006 rtx next_usage_insns
, curr_set
;
6008 struct lra_insn_reg
*reg
;
6009 basic_block last_processed_bb
, curr_bb
= NULL
;
6010 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
6014 bool head_p
, after_p
;
6017 curr_usage_insns_check
++;
6018 clear_invariants ();
6019 reloads_num
= calls_num
= 0;
6020 bitmap_clear (&check_only_regs
);
6021 bitmap_clear (&invalid_invariant_regs
);
6022 last_processed_bb
= NULL
;
6023 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6024 COPY_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
6025 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
6026 /* We don't process new insns generated in the loop. */
6027 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
6029 prev_insn
= PREV_INSN (curr_insn
);
6030 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
6031 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
6032 if (last_processed_bb
!= curr_bb
)
6034 /* We are at the end of BB. Add qualified living
6035 pseudos for potential splitting. */
6036 to_process
= df_get_live_out (curr_bb
);
6037 if (last_processed_bb
!= NULL
)
6039 /* We are somewhere in the middle of EBB. */
6040 get_live_on_other_edges (curr_bb
, last_processed_bb
,
6042 to_process
= &temp_bitmap
;
6044 last_processed_bb
= curr_bb
;
6045 last_insn
= get_last_insertion_point (curr_bb
);
6046 after_p
= (! JUMP_P (last_insn
)
6047 && (! CALL_P (last_insn
)
6048 || (find_reg_note (last_insn
,
6049 REG_NORETURN
, NULL_RTX
) == NULL_RTX
6050 && ! SIBLING_CALL_P (last_insn
))));
6051 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
6052 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6054 if ((int) j
>= lra_constraint_new_regno_start
)
6056 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6058 if (j
< FIRST_PSEUDO_REGISTER
)
6059 SET_HARD_REG_BIT (live_hard_regs
, j
);
6061 add_to_hard_reg_set (&live_hard_regs
,
6062 PSEUDO_REGNO_MODE (j
),
6064 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
6068 src_regno
= dst_regno
= -1;
6069 curr_set
= single_set (curr_insn
);
6070 if (curr_set
!= NULL_RTX
&& REG_P (SET_DEST (curr_set
)))
6071 dst_regno
= REGNO (SET_DEST (curr_set
));
6072 if (curr_set
!= NULL_RTX
&& REG_P (SET_SRC (curr_set
)))
6073 src_regno
= REGNO (SET_SRC (curr_set
));
6074 update_reloads_num_p
= true;
6075 if (src_regno
< lra_constraint_new_regno_start
6076 && src_regno
>= FIRST_PSEUDO_REGISTER
6077 && reg_renumber
[src_regno
] < 0
6078 && dst_regno
>= lra_constraint_new_regno_start
6079 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
6081 /* 'reload_pseudo <- original_pseudo'. */
6082 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6084 update_reloads_num_p
= false;
6086 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6087 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
6088 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
6089 curr_insn
, next_usage_insns
);
6093 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6094 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6095 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6096 reg_class_contents
[cl
]);
6098 else if (src_regno
< 0
6099 && dst_regno
>= lra_constraint_new_regno_start
6100 && invariant_p (SET_SRC (curr_set
))
6101 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
6102 && ! bitmap_bit_p (&invalid_invariant_regs
, dst_regno
)
6103 && ! bitmap_bit_p (&invalid_invariant_regs
,
6104 ORIGINAL_REGNO(regno_reg_rtx
[dst_regno
])))
6106 /* 'reload_pseudo <- invariant'. */
6107 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6109 update_reloads_num_p
= false;
6110 if (process_invariant_for_inheritance (SET_DEST (curr_set
), SET_SRC (curr_set
)))
6112 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6113 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6114 reg_class_contents
[cl
]);
6116 else if (src_regno
>= lra_constraint_new_regno_start
6117 && dst_regno
< lra_constraint_new_regno_start
6118 && dst_regno
>= FIRST_PSEUDO_REGISTER
6119 && reg_renumber
[dst_regno
] < 0
6120 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
6121 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6122 && (next_usage_insns
6123 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6125 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6127 update_reloads_num_p
= false;
6128 /* 'original_pseudo <- reload_pseudo'. */
6129 if (! JUMP_P (curr_insn
)
6130 && inherit_reload_reg (true, dst_regno
, cl
,
6131 curr_insn
, next_usage_insns
))
6134 usage_insns
[dst_regno
].check
= 0;
6135 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6136 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6137 reg_class_contents
[cl
]);
6139 else if (INSN_P (curr_insn
))
6142 int max_uid
= get_max_uid ();
6144 curr_id
= lra_get_insn_recog_data (curr_insn
);
6145 curr_static_id
= curr_id
->insn_static_data
;
6147 /* Process insn definitions. */
6148 for (iter
= 0; iter
< 2; iter
++)
6149 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6152 if (reg
->type
!= OP_IN
6153 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6155 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
6156 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
6157 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
6158 && (next_usage_insns
6159 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
6161 struct lra_insn_reg
*r
;
6163 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
6164 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
6166 /* Don't do inheritance if the pseudo is also
6167 used in the insn. */
6169 /* We can not do inheritance right now
6170 because the current insn reg info (chain
6171 regs) can change after that. */
6172 add_to_inherit (dst_regno
, next_usage_insns
);
6174 /* We can not process one reg twice here because of
6175 usage_insns invalidation. */
6176 if ((dst_regno
< FIRST_PSEUDO_REGISTER
6177 || reg_renumber
[dst_regno
] >= 0)
6178 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
6182 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
6183 potential_reload_hard_regs
,
6184 false, curr_insn
, max_uid
))
6186 CLEAR_HARD_REG_SET (s
);
6187 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
6188 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
6190 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
6191 reg_renumber
[dst_regno
]);
6192 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
6194 /* We should invalidate potential inheritance or
6195 splitting for the current insn usages to the next
6196 usage insns (see code below) as the output pseudo
6198 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
6199 && reg_renumber
[dst_regno
] < 0)
6200 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
6201 && (dst_regno
< FIRST_PSEUDO_REGISTER
6202 || reg_renumber
[dst_regno
] >= 0)))
6204 /* Invalidate and mark definitions. */
6205 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6206 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
6209 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
6210 for (i
= 0; i
< nregs
; i
++)
6211 usage_insns
[dst_regno
+ i
].check
6212 = -(int) INSN_UID (curr_insn
);
6216 /* Process clobbered call regs. */
6217 if (curr_id
->arg_hard_regs
!= NULL
)
6218 for (i
= 0; (dst_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6219 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
6220 usage_insns
[dst_regno
- FIRST_PSEUDO_REGISTER
].check
6221 = -(int) INSN_UID (curr_insn
);
6222 if (! JUMP_P (curr_insn
))
6223 for (i
= 0; i
< to_inherit_num
; i
++)
6224 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
6225 ALL_REGS
, curr_insn
,
6226 to_inherit
[i
].insns
))
6228 if (CALL_P (curr_insn
))
6230 rtx cheap
, pat
, dest
;
6232 int regno
, hard_regno
;
6235 if ((cheap
= find_reg_note (curr_insn
,
6236 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
6237 && ((cheap
= XEXP (cheap
, 0)), true)
6238 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
6239 && (hard_regno
= reg_renumber
[regno
]) >= 0
6240 /* If there are pending saves/restores, the
6241 optimization is not worth. */
6242 && usage_insns
[regno
].calls_num
== calls_num
- 1
6243 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
6245 /* Restore the pseudo from the call result as
6246 REG_RETURNED note says that the pseudo value is
6247 in the call result and the pseudo is an argument
6249 pat
= PATTERN (curr_insn
);
6250 if (GET_CODE (pat
) == PARALLEL
)
6251 pat
= XVECEXP (pat
, 0, 0);
6252 dest
= SET_DEST (pat
);
6253 /* For multiple return values dest is PARALLEL.
6254 Currently we handle only single return value case. */
6258 emit_move_insn (cheap
, copy_rtx (dest
));
6259 restore
= get_insns ();
6261 lra_process_new_insns (curr_insn
, NULL
, restore
,
6262 "Inserting call parameter restore");
6263 /* We don't need to save/restore of the pseudo from
6265 usage_insns
[regno
].calls_num
= calls_num
;
6266 bitmap_set_bit (&check_only_regs
, regno
);
6271 /* Process insn usages. */
6272 for (iter
= 0; iter
< 2; iter
++)
6273 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
6276 if ((reg
->type
!= OP_OUT
6277 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
6278 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
6280 if (src_regno
>= FIRST_PSEUDO_REGISTER
6281 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
6283 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
6284 && (next_usage_insns
6285 = usage_insns
[src_regno
].insns
) != NULL_RTX
6286 && NONDEBUG_INSN_P (curr_insn
))
6287 add_to_inherit (src_regno
, next_usage_insns
);
6288 else if (usage_insns
[src_regno
].check
6289 != -(int) INSN_UID (curr_insn
))
6290 /* Add usages but only if the reg is not set up
6291 in the same insn. */
6292 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6294 else if (src_regno
< FIRST_PSEUDO_REGISTER
6295 || reg_renumber
[src_regno
] >= 0)
6298 rtx_insn
*use_insn
= curr_insn
;
6300 before_p
= (JUMP_P (curr_insn
)
6301 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
6302 if (NONDEBUG_INSN_P (curr_insn
)
6303 && (! JUMP_P (curr_insn
) || reg
->type
== OP_IN
)
6304 && split_if_necessary (src_regno
, reg
->biggest_mode
,
6305 potential_reload_hard_regs
,
6306 before_p
, curr_insn
, max_uid
))
6309 lra_risky_transformations_p
= true;
6312 usage_insns
[src_regno
].check
= 0;
6314 use_insn
= PREV_INSN (curr_insn
);
6316 if (NONDEBUG_INSN_P (curr_insn
))
6318 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6319 add_to_hard_reg_set (&live_hard_regs
,
6320 reg
->biggest_mode
, src_regno
);
6322 add_to_hard_reg_set (&live_hard_regs
,
6323 PSEUDO_REGNO_MODE (src_regno
),
6324 reg_renumber
[src_regno
]);
6326 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
6329 /* Process used call regs. */
6330 if (curr_id
->arg_hard_regs
!= NULL
)
6331 for (i
= 0; (src_regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6332 if (src_regno
< FIRST_PSEUDO_REGISTER
)
6334 SET_HARD_REG_BIT (live_hard_regs
, src_regno
);
6335 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
6337 for (i
= 0; i
< to_inherit_num
; i
++)
6339 src_regno
= to_inherit
[i
].regno
;
6340 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
6341 curr_insn
, to_inherit
[i
].insns
))
6344 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
6347 if (update_reloads_num_p
6348 && NONDEBUG_INSN_P (curr_insn
) && curr_set
!= NULL_RTX
)
6351 if ((REG_P (SET_DEST (curr_set
))
6352 && (regno
= REGNO (SET_DEST (curr_set
))) >= lra_constraint_new_regno_start
6353 && reg_renumber
[regno
] < 0
6354 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
)
6355 || (REG_P (SET_SRC (curr_set
))
6356 && (regno
= REGNO (SET_SRC (curr_set
))) >= lra_constraint_new_regno_start
6357 && reg_renumber
[regno
] < 0
6358 && (cl
= lra_get_allocno_class (regno
)) != NO_REGS
))
6360 if (ira_class_hard_regs_num
[cl
] <= max_small_class_regs_num
)
6362 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
6363 IOR_HARD_REG_SET (potential_reload_hard_regs
,
6364 reg_class_contents
[cl
]);
6367 if (NONDEBUG_INSN_P (curr_insn
))
6371 /* Invalidate invariants with changed regs. */
6372 curr_id
= lra_get_insn_recog_data (curr_insn
);
6373 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6374 if (reg
->type
!= OP_IN
)
6376 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6377 bitmap_set_bit (&invalid_invariant_regs
,
6378 ORIGINAL_REGNO (regno_reg_rtx
[reg
->regno
]));
6380 curr_static_id
= curr_id
->insn_static_data
;
6381 for (reg
= curr_static_id
->hard_regs
; reg
!= NULL
; reg
= reg
->next
)
6382 if (reg
->type
!= OP_IN
)
6383 bitmap_set_bit (&invalid_invariant_regs
, reg
->regno
);
6384 if (curr_id
->arg_hard_regs
!= NULL
)
6385 for (i
= 0; (regno
= curr_id
->arg_hard_regs
[i
]) >= 0; i
++)
6386 if (regno
>= FIRST_PSEUDO_REGISTER
)
6387 bitmap_set_bit (&invalid_invariant_regs
,
6388 regno
- FIRST_PSEUDO_REGISTER
);
6390 /* We reached the start of the current basic block. */
6391 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
6392 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
6394 /* We reached the beginning of the current block -- do
6395 rest of spliting in the current BB. */
6396 to_process
= df_get_live_in (curr_bb
);
6397 if (BLOCK_FOR_INSN (head
) != curr_bb
)
6399 /* We are somewhere in the middle of EBB. */
6400 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
6401 curr_bb
, &temp_bitmap
);
6402 to_process
= &temp_bitmap
;
6405 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
6407 if ((int) j
>= lra_constraint_new_regno_start
)
6409 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
6410 && usage_insns
[j
].check
== curr_usage_insns_check
6411 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
6413 if (need_for_split_p (potential_reload_hard_regs
, j
))
6415 if (lra_dump_file
!= NULL
&& head_p
)
6417 fprintf (lra_dump_file
,
6418 " ----------------------------------\n");
6421 if (split_reg (false, j
, bb_note (curr_bb
),
6425 usage_insns
[j
].check
= 0;
6433 /* This value affects EBB forming. If probability of edge from EBB to
6434 a BB is not greater than the following value, we don't add the BB
6436 #define EBB_PROBABILITY_CUTOFF \
6437 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100)
6439 /* Current number of inheritance/split iteration. */
6440 int lra_inheritance_iter
;
6442 /* Entry function for inheritance/split pass. */
6444 lra_inheritance (void)
6447 basic_block bb
, start_bb
;
6450 lra_inheritance_iter
++;
6451 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6453 timevar_push (TV_LRA_INHERITANCE
);
6454 if (lra_dump_file
!= NULL
)
6455 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
6456 lra_inheritance_iter
);
6457 curr_usage_insns_check
= 0;
6458 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
6459 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
6460 usage_insns
[i
].check
= 0;
6461 bitmap_initialize (&check_only_regs
, ®_obstack
);
6462 bitmap_initialize (&invalid_invariant_regs
, ®_obstack
);
6463 bitmap_initialize (&live_regs
, ®_obstack
);
6464 bitmap_initialize (&temp_bitmap
, ®_obstack
);
6465 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
6466 FOR_EACH_BB_FN (bb
, cfun
)
6469 if (lra_dump_file
!= NULL
)
6470 fprintf (lra_dump_file
, "EBB");
6471 /* Form a EBB starting with BB. */
6472 bitmap_clear (&ebb_global_regs
);
6473 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
6476 if (lra_dump_file
!= NULL
)
6477 fprintf (lra_dump_file
, " %d", bb
->index
);
6478 if (bb
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
6479 || LABEL_P (BB_HEAD (bb
->next_bb
)))
6481 e
= find_fallthru_edge (bb
->succs
);
6484 if (e
->probability
.initialized_p ()
6485 && e
->probability
.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF
)
6489 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
6490 if (lra_dump_file
!= NULL
)
6491 fprintf (lra_dump_file
, "\n");
6492 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
6493 /* Remember that the EBB head and tail can change in
6495 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
6497 bitmap_clear (&ebb_global_regs
);
6498 bitmap_clear (&temp_bitmap
);
6499 bitmap_clear (&live_regs
);
6500 bitmap_clear (&invalid_invariant_regs
);
6501 bitmap_clear (&check_only_regs
);
6504 timevar_pop (TV_LRA_INHERITANCE
);
6509 /* This page contains code to undo failed inheritance/split
6512 /* Current number of iteration undoing inheritance/split. */
6513 int lra_undo_inheritance_iter
;
6515 /* Fix BB live info LIVE after removing pseudos created on pass doing
6516 inheritance/split which are REMOVED_PSEUDOS. */
6518 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
6523 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
6524 if (bitmap_clear_bit (live
, regno
)
6525 && REG_P (lra_reg_info
[regno
].restore_rtx
))
6526 bitmap_set_bit (live
, REGNO (lra_reg_info
[regno
].restore_rtx
));
6529 /* Return regno of the (subreg of) REG. Otherwise, return a negative
6534 if (GET_CODE (reg
) == SUBREG
)
6535 reg
= SUBREG_REG (reg
);
6541 /* Delete a move INSN with destination reg DREGNO and a previous
6542 clobber insn with the same regno. The inheritance/split code can
6543 generate moves with preceding clobber and when we delete such moves
6544 we should delete the clobber insn too to keep the correct life
6547 delete_move_and_clobber (rtx_insn
*insn
, int dregno
)
6549 rtx_insn
*prev_insn
= PREV_INSN (insn
);
6551 lra_set_insn_deleted (insn
);
6552 lra_assert (dregno
>= 0);
6553 if (prev_insn
!= NULL
&& NONDEBUG_INSN_P (prev_insn
)
6554 && GET_CODE (PATTERN (prev_insn
)) == CLOBBER
6555 && dregno
== get_regno (XEXP (PATTERN (prev_insn
), 0)))
6556 lra_set_insn_deleted (prev_insn
);
6559 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
6560 return true if we did any change. The undo transformations for
6561 inheritance looks like
6565 p <- i, i <- p, and i <- i3
6566 where p is original pseudo from which inheritance pseudo i was
6567 created, i and i3 are removed inheritance pseudos, i2 is another
6568 not removed inheritance pseudo. All split pseudos or other
6569 occurrences of removed inheritance pseudos are changed on the
6570 corresponding original pseudos.
6572 The function also schedules insns changed and created during
6573 inheritance/split pass for processing by the subsequent constraint
6576 remove_inheritance_pseudos (bitmap remove_pseudos
)
6579 int regno
, sregno
, prev_sregno
, dregno
;
6582 rtx_insn
*prev_insn
;
6583 bool change_p
, done_p
;
6585 change_p
= ! bitmap_empty_p (remove_pseudos
);
6586 /* We can not finish the function right away if CHANGE_P is true
6587 because we need to marks insns affected by previous
6588 inheritance/split pass for processing by the subsequent
6590 FOR_EACH_BB_FN (bb
, cfun
)
6592 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
6593 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
6594 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
6596 if (! INSN_P (curr_insn
))
6599 sregno
= dregno
= -1;
6600 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
6601 && (set
= single_set (curr_insn
)) != NULL_RTX
)
6603 dregno
= get_regno (SET_DEST (set
));
6604 sregno
= get_regno (SET_SRC (set
));
6607 if (sregno
>= 0 && dregno
>= 0)
6609 if (bitmap_bit_p (remove_pseudos
, dregno
)
6610 && ! REG_P (lra_reg_info
[dregno
].restore_rtx
))
6612 /* invariant inheritance pseudo <- original pseudo */
6613 if (lra_dump_file
!= NULL
)
6615 fprintf (lra_dump_file
, " Removing invariant inheritance:\n");
6616 dump_insn_slim (lra_dump_file
, curr_insn
);
6617 fprintf (lra_dump_file
, "\n");
6619 delete_move_and_clobber (curr_insn
, dregno
);
6622 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6623 && ! REG_P (lra_reg_info
[sregno
].restore_rtx
))
6625 /* reload pseudo <- invariant inheritance pseudo */
6627 /* We can not just change the source. It might be
6628 an insn different from the move. */
6629 emit_insn (lra_reg_info
[sregno
].restore_rtx
);
6630 rtx_insn
*new_insns
= get_insns ();
6632 lra_assert (single_set (new_insns
) != NULL
6633 && SET_DEST (set
) == SET_DEST (single_set (new_insns
)));
6634 lra_process_new_insns (curr_insn
, NULL
, new_insns
,
6635 "Changing reload<-invariant inheritance");
6636 delete_move_and_clobber (curr_insn
, dregno
);
6639 else if ((bitmap_bit_p (remove_pseudos
, sregno
)
6640 && (get_regno (lra_reg_info
[sregno
].restore_rtx
) == dregno
6641 || (bitmap_bit_p (remove_pseudos
, dregno
)
6642 && get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6643 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6644 == get_regno (lra_reg_info
[dregno
].restore_rtx
)))))
6645 || (bitmap_bit_p (remove_pseudos
, dregno
)
6646 && get_regno (lra_reg_info
[dregno
].restore_rtx
) == sregno
))
6647 /* One of the following cases:
6648 original <- removed inheritance pseudo
6649 removed inherit pseudo <- another removed inherit pseudo
6650 removed inherit pseudo <- original pseudo
6652 removed_split_pseudo <- original_reg
6653 original_reg <- removed_split_pseudo */
6655 if (lra_dump_file
!= NULL
)
6657 fprintf (lra_dump_file
, " Removing %s:\n",
6658 bitmap_bit_p (&lra_split_regs
, sregno
)
6659 || bitmap_bit_p (&lra_split_regs
, dregno
)
6660 ? "split" : "inheritance");
6661 dump_insn_slim (lra_dump_file
, curr_insn
);
6663 delete_move_and_clobber (curr_insn
, dregno
);
6666 else if (bitmap_bit_p (remove_pseudos
, sregno
)
6667 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
6669 /* Search the following pattern:
6670 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
6671 original_pseudo <- inherit_or_split_pseudo1
6672 where the 2nd insn is the current insn and
6673 inherit_or_split_pseudo2 is not removed. If it is found,
6674 change the current insn onto:
6675 original_pseudo <- inherit_or_split_pseudo2. */
6676 for (prev_insn
= PREV_INSN (curr_insn
);
6677 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
6678 prev_insn
= PREV_INSN (prev_insn
))
6680 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
6681 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
6682 /* There should be no subregs in insn we are
6683 searching because only the original reg might
6684 be in subreg when we changed the mode of
6685 load/store for splitting. */
6686 && REG_P (SET_DEST (prev_set
))
6687 && REG_P (SET_SRC (prev_set
))
6688 && (int) REGNO (SET_DEST (prev_set
)) == sregno
6689 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
6690 >= FIRST_PSEUDO_REGISTER
)
6691 && (lra_reg_info
[prev_sregno
].restore_rtx
== NULL_RTX
6693 /* As we consider chain of inheritance or
6694 splitting described in above comment we should
6695 check that sregno and prev_sregno were
6696 inheritance/split pseudos created from the
6697 same original regno. */
6698 (get_regno (lra_reg_info
[sregno
].restore_rtx
) >= 0
6699 && (get_regno (lra_reg_info
[sregno
].restore_rtx
)
6700 == get_regno (lra_reg_info
[prev_sregno
].restore_rtx
))))
6701 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
6703 lra_assert (GET_MODE (SET_SRC (prev_set
))
6704 == GET_MODE (regno_reg_rtx
[sregno
]));
6705 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
6706 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
6708 SET_SRC (set
) = SET_SRC (prev_set
);
6709 /* As we are finishing with processing the insn
6710 here, check the destination too as it might
6711 inheritance pseudo for another pseudo. */
6712 if (bitmap_bit_p (remove_pseudos
, dregno
)
6713 && bitmap_bit_p (&lra_inheritance_pseudos
, dregno
)
6715 = lra_reg_info
[dregno
].restore_rtx
) != NULL_RTX
)
6717 if (GET_CODE (SET_DEST (set
)) == SUBREG
)
6718 SUBREG_REG (SET_DEST (set
)) = restore_rtx
;
6720 SET_DEST (set
) = restore_rtx
;
6722 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6723 lra_set_used_insn_alternative_by_uid
6724 (INSN_UID (curr_insn
), -1);
6726 if (lra_dump_file
!= NULL
)
6728 fprintf (lra_dump_file
, " Change reload insn:\n");
6729 dump_insn_slim (lra_dump_file
, curr_insn
);
6736 struct lra_insn_reg
*reg
;
6737 bool restored_regs_p
= false;
6738 bool kept_regs_p
= false;
6740 curr_id
= lra_get_insn_recog_data (curr_insn
);
6741 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
6744 restore_rtx
= lra_reg_info
[regno
].restore_rtx
;
6745 if (restore_rtx
!= NULL_RTX
)
6747 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
6749 lra_substitute_pseudo_within_insn
6750 (curr_insn
, regno
, restore_rtx
, false);
6751 restored_regs_p
= true;
6757 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
6759 /* The instruction has changed since the previous
6760 constraints pass. */
6761 lra_push_insn_and_update_insn_regno_info (curr_insn
);
6762 lra_set_used_insn_alternative_by_uid
6763 (INSN_UID (curr_insn
), -1);
6765 else if (restored_regs_p
)
6766 /* The instruction has been restored to the form that
6767 it had during the previous constraints pass. */
6768 lra_update_insn_regno_info (curr_insn
);
6769 if (restored_regs_p
&& lra_dump_file
!= NULL
)
6771 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
6772 dump_insn_slim (lra_dump_file
, curr_insn
);
6780 /* If optional reload pseudos failed to get a hard register or was not
6781 inherited, it is better to remove optional reloads. We do this
6782 transformation after undoing inheritance to figure out necessity to
6783 remove optional reloads easier. Return true if we do any
6786 undo_optional_reloads (void)
6788 bool change_p
, keep_p
;
6789 unsigned int regno
, uid
;
6790 bitmap_iterator bi
, bi2
;
6793 auto_bitmap
removed_optional_reload_pseudos (®_obstack
);
6795 bitmap_copy (removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
6796 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6799 /* Keep optional reloads from previous subpasses. */
6800 if (lra_reg_info
[regno
].restore_rtx
== NULL_RTX
6801 /* If the original pseudo changed its allocation, just
6802 removing the optional pseudo is dangerous as the original
6803 pseudo will have longer live range. */
6804 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] >= 0)
6806 else if (reg_renumber
[regno
] >= 0)
6807 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
6809 insn
= lra_insn_recog_data
[uid
]->insn
;
6810 if ((set
= single_set (insn
)) == NULL_RTX
)
6812 src
= SET_SRC (set
);
6813 dest
= SET_DEST (set
);
6814 if (! REG_P (src
) || ! REG_P (dest
))
6816 if (REGNO (dest
) == regno
6817 /* Ignore insn for optional reloads itself. */
6818 && REGNO (lra_reg_info
[regno
].restore_rtx
) != REGNO (src
)
6819 /* Check only inheritance on last inheritance pass. */
6820 && (int) REGNO (src
) >= new_regno_start
6821 /* Check that the optional reload was inherited. */
6822 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
6830 bitmap_clear_bit (removed_optional_reload_pseudos
, regno
);
6831 if (lra_dump_file
!= NULL
)
6832 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
6835 change_p
= ! bitmap_empty_p (removed_optional_reload_pseudos
);
6836 auto_bitmap
insn_bitmap (®_obstack
);
6837 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos
, 0, regno
, bi
)
6839 if (lra_dump_file
!= NULL
)
6840 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
6841 bitmap_copy (insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
6842 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap
, 0, uid
, bi2
)
6844 insn
= lra_insn_recog_data
[uid
]->insn
;
6845 if ((set
= single_set (insn
)) != NULL_RTX
)
6847 src
= SET_SRC (set
);
6848 dest
= SET_DEST (set
);
6849 if (REG_P (src
) && REG_P (dest
)
6850 && ((REGNO (src
) == regno
6851 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6853 || (REGNO (dest
) == regno
6854 && (REGNO (lra_reg_info
[regno
].restore_rtx
)
6857 if (lra_dump_file
!= NULL
)
6859 fprintf (lra_dump_file
, " Deleting move %u\n",
6861 dump_insn_slim (lra_dump_file
, insn
);
6863 delete_move_and_clobber (insn
, REGNO (dest
));
6866 /* We should not worry about generation memory-memory
6867 moves here as if the corresponding inheritance did
6868 not work (inheritance pseudo did not get a hard reg),
6869 we remove the inheritance pseudo and the optional
6872 lra_substitute_pseudo_within_insn
6873 (insn
, regno
, lra_reg_info
[regno
].restore_rtx
, false);
6874 lra_update_insn_regno_info (insn
);
6875 if (lra_dump_file
!= NULL
)
6877 fprintf (lra_dump_file
,
6878 " Restoring original insn:\n");
6879 dump_insn_slim (lra_dump_file
, insn
);
6883 /* Clear restore_regnos. */
6884 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
6885 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6889 /* Entry function for undoing inheritance/split transformation. Return true
6890 if we did any RTL change in this pass. */
6892 lra_undo_inheritance (void)
6896 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
6901 lra_undo_inheritance_iter
++;
6902 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
6904 if (lra_dump_file
!= NULL
)
6905 fprintf (lra_dump_file
,
6906 "\n********** Undoing inheritance #%d: **********\n\n",
6907 lra_undo_inheritance_iter
);
6908 auto_bitmap
remove_pseudos (®_obstack
);
6909 n_inherit
= n_all_inherit
= 0;
6910 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6911 if (lra_reg_info
[regno
].restore_rtx
!= NULL_RTX
)
6914 if (reg_renumber
[regno
] < 0
6915 /* If the original pseudo changed its allocation, just
6916 removing inheritance is dangerous as for changing
6917 allocation we used shorter live-ranges. */
6918 && (! REG_P (lra_reg_info
[regno
].restore_rtx
)
6919 || reg_renumber
[REGNO (lra_reg_info
[regno
].restore_rtx
)] < 0))
6920 bitmap_set_bit (remove_pseudos
, regno
);
6924 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
6925 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
6926 n_inherit
, n_all_inherit
,
6927 (double) n_inherit
/ n_all_inherit
* 100);
6928 n_split
= n_all_split
= 0;
6929 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6930 if ((restore_rtx
= lra_reg_info
[regno
].restore_rtx
) != NULL_RTX
)
6932 int restore_regno
= REGNO (restore_rtx
);
6935 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
6936 ? reg_renumber
[restore_regno
] : restore_regno
);
6937 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
6938 bitmap_set_bit (remove_pseudos
, regno
);
6942 if (lra_dump_file
!= NULL
)
6943 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
6944 regno
, restore_regno
);
6947 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
6948 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
6949 n_split
, n_all_split
,
6950 (double) n_split
/ n_all_split
* 100);
6951 change_p
= remove_inheritance_pseudos (remove_pseudos
);
6952 /* Clear restore_regnos. */
6953 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
6954 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6955 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
6956 lra_reg_info
[regno
].restore_rtx
= NULL_RTX
;
6957 change_p
= undo_optional_reloads () || change_p
;