1 /* Dwarf2 Call Frame Information helper routines.
2 Copyright (C) 1992-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "tree-pass.h"
31 #include "stor-layout.h"
33 #include "dwarf2out.h"
34 #include "dwarf2asm.h"
35 #include "common/common-target.h"
37 #include "except.h" /* expand_builtin_dwarf_sp_column */
38 #include "profile-count.h" /* For expr.h */
39 #include "expr.h" /* init_return_column_size */
40 #include "output.h" /* asm_out_file */
41 #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */
42 #include "flags.h" /* dwarf_debuginfo_p */
44 /* ??? Poison these here until it can be done generically. They've been
45 totally replaced in this file; make sure it stays that way. */
46 #undef DWARF2_UNWIND_INFO
47 #undef DWARF2_FRAME_INFO
48 #if (GCC_VERSION >= 3000)
49 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO
52 #ifndef INCOMING_RETURN_ADDR_RTX
53 #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX)
56 #ifndef DEFAULT_INCOMING_FRAME_SP_OFFSET
57 #define DEFAULT_INCOMING_FRAME_SP_OFFSET INCOMING_FRAME_SP_OFFSET
60 /* A collected description of an entire row of the abstract CFI table. */
61 struct GTY(()) dw_cfi_row
63 /* The expression that computes the CFA, expressed in two different ways.
64 The CFA member for the simple cases, and the full CFI expression for
65 the complex cases. The later will be a DW_CFA_cfa_expression. */
69 /* The expressions for any register column that is saved. */
72 /* True if the register window is saved. */
75 /* True if the return address is in a mangled state. */
79 /* The caller's ORIG_REG is saved in SAVED_IN_REG. */
80 struct GTY(()) reg_saved_in_data
{
86 /* Since we no longer have a proper CFG, we're going to create a facsimile
87 of one on the fly while processing the frame-related insns.
89 We create dw_trace_info structures for each extended basic block beginning
90 and ending at a "save point". Save points are labels, barriers, certain
91 notes, and of course the beginning and end of the function.
93 As we encounter control transfer insns, we propagate the "current"
94 row state across the edges to the starts of traces. When checking is
95 enabled, we validate that we propagate the same data from all sources.
97 All traces are members of the TRACE_INFO array, in the order in which
98 they appear in the instruction stream.
100 All save points are present in the TRACE_INDEX hash, mapping the insn
101 starting a trace to the dw_trace_info describing the trace. */
105 /* The insn that begins the trace. */
108 /* The row state at the beginning and end of the trace. */
109 dw_cfi_row
*beg_row
, *end_row
;
111 /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find
112 while scanning insns. However, the args_size value is irrelevant at
113 any point except can_throw_internal_p insns. Therefore the "delay"
114 sizes the values that must actually be emitted for this trace. */
115 poly_int64_pod beg_true_args_size
, end_true_args_size
;
116 poly_int64_pod beg_delay_args_size
, end_delay_args_size
;
118 /* The first EH insn in the trace, where beg_delay_args_size must be set. */
121 /* The following variables contain data used in interpreting frame related
122 expressions. These are not part of the "real" row state as defined by
123 Dwarf, but it seems like they need to be propagated into a trace in case
124 frame related expressions have been sunk. */
125 /* ??? This seems fragile. These variables are fragments of a larger
126 expression. If we do not keep the entire expression together, we risk
127 not being able to put it together properly. Consider forcing targets
128 to generate self-contained expressions and dropping all of the magic
129 interpretation code in this file. Or at least refusing to shrink wrap
130 any frame related insn that doesn't contain a complete expression. */
132 /* The register used for saving registers to the stack, and its offset
134 dw_cfa_location cfa_store
;
136 /* A temporary register holding an integral value used in adjusting SP
137 or setting up the store_reg. The "offset" field holds the integer
138 value, not an offset. */
139 dw_cfa_location cfa_temp
;
141 /* A set of registers saved in other registers. This is the inverse of
142 the row->reg_save info, if the entry is a DW_CFA_register. This is
143 implemented as a flat array because it normally contains zero or 1
144 entry, depending on the target. IA-64 is the big spender here, using
145 a maximum of 5 entries. */
146 vec
<reg_saved_in_data
> regs_saved_in_regs
;
148 /* An identifier for this trace. Used only for debugging dumps. */
151 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */
152 bool switch_sections
;
154 /* True if we've seen different values incoming to beg_true_args_size. */
155 bool args_size_undefined
;
157 /* True if we've seen an insn with a REG_ARGS_SIZE note before EH_HEAD. */
158 bool args_size_defined_for_eh
;
162 /* Hashtable helpers. */
164 struct trace_info_hasher
: nofree_ptr_hash
<dw_trace_info
>
166 static inline hashval_t
hash (const dw_trace_info
*);
167 static inline bool equal (const dw_trace_info
*, const dw_trace_info
*);
171 trace_info_hasher::hash (const dw_trace_info
*ti
)
173 return INSN_UID (ti
->head
);
177 trace_info_hasher::equal (const dw_trace_info
*a
, const dw_trace_info
*b
)
179 return a
->head
== b
->head
;
183 /* The variables making up the pseudo-cfg, as described above. */
184 static vec
<dw_trace_info
> trace_info
;
185 static vec
<dw_trace_info
*> trace_work_list
;
186 static hash_table
<trace_info_hasher
> *trace_index
;
188 /* A vector of call frame insns for the CIE. */
191 /* The state of the first row of the FDE table, which includes the
192 state provided by the CIE. */
193 static GTY(()) dw_cfi_row
*cie_cfi_row
;
195 static GTY(()) reg_saved_in_data
*cie_return_save
;
197 static GTY(()) unsigned long dwarf2out_cfi_label_num
;
199 /* The insn after which a new CFI note should be emitted. */
200 static rtx_insn
*add_cfi_insn
;
202 /* When non-null, add_cfi will add the CFI to this vector. */
203 static cfi_vec
*add_cfi_vec
;
205 /* The current instruction trace. */
206 static dw_trace_info
*cur_trace
;
208 /* The current, i.e. most recently generated, row of the CFI table. */
209 static dw_cfi_row
*cur_row
;
211 /* A copy of the current CFA, for use during the processing of a
213 static dw_cfa_location
*cur_cfa
;
215 /* We delay emitting a register save until either (a) we reach the end
216 of the prologue or (b) the register is clobbered. This clusters
217 register saves so that there are fewer pc advances. */
219 struct queued_reg_save
{
222 poly_int64_pod cfa_offset
;
226 static vec
<queued_reg_save
> queued_reg_saves
;
228 /* True if any CFI directives were emitted at the current insn. */
229 static bool any_cfis_emitted
;
231 /* Short-hand for commonly used register numbers. */
232 static struct cfa_reg dw_stack_pointer_regnum
;
233 static struct cfa_reg dw_frame_pointer_regnum
;
235 /* Hook used by __throw. */
238 expand_builtin_dwarf_sp_column (void)
240 unsigned int dwarf_regnum
= DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM
);
241 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum
, 1));
244 /* MEM is a memory reference for the register size table, each element of
245 which has mode MODE. Initialize column C as a return address column. */
248 init_return_column_size (scalar_int_mode mode
, rtx mem
, unsigned int c
)
250 HOST_WIDE_INT offset
= c
* GET_MODE_SIZE (mode
);
251 HOST_WIDE_INT size
= GET_MODE_SIZE (Pmode
);
252 emit_move_insn (adjust_address (mem
, mode
, offset
),
253 gen_int_mode (size
, mode
));
256 /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and
257 init_one_dwarf_reg_size to communicate on what has been done by the
260 struct init_one_dwarf_reg_state
262 /* Whether the dwarf return column was initialized. */
263 bool wrote_return_column
;
265 /* For each hard register REGNO, whether init_one_dwarf_reg_size
266 was given REGNO to process already. */
267 bool processed_regno
[FIRST_PSEUDO_REGISTER
];
271 /* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to
272 initialize the dwarf register size table entry corresponding to register
273 REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to
274 use for the size entry to initialize, and INIT_STATE is the communication
275 datastructure conveying what we're doing to our caller. */
278 void init_one_dwarf_reg_size (int regno
, machine_mode regmode
,
279 rtx table
, machine_mode slotmode
,
280 init_one_dwarf_reg_state
*init_state
)
282 const unsigned int dnum
= DWARF_FRAME_REGNUM (regno
);
283 const unsigned int rnum
= DWARF2_FRAME_REG_OUT (dnum
, 1);
284 const unsigned int dcol
= DWARF_REG_TO_UNWIND_COLUMN (rnum
);
286 poly_int64 slotoffset
= dcol
* GET_MODE_SIZE (slotmode
);
287 poly_int64 regsize
= GET_MODE_SIZE (regmode
);
289 init_state
->processed_regno
[regno
] = true;
291 if (rnum
>= DWARF_FRAME_REGISTERS
)
294 if (dnum
== DWARF_FRAME_RETURN_COLUMN
)
296 if (regmode
== VOIDmode
)
298 init_state
->wrote_return_column
= true;
301 /* ??? When is this true? Should it be a test based on DCOL instead? */
302 if (maybe_lt (slotoffset
, 0))
305 emit_move_insn (adjust_address (table
, slotmode
, slotoffset
),
306 gen_int_mode (regsize
, slotmode
));
309 /* Generate code to initialize the dwarf register size table located
310 at the provided ADDRESS. */
313 expand_builtin_init_dwarf_reg_sizes (tree address
)
316 scalar_int_mode mode
= SCALAR_INT_TYPE_MODE (char_type_node
);
317 rtx addr
= expand_normal (address
);
318 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
320 init_one_dwarf_reg_state init_state
;
322 memset ((char *)&init_state
, 0, sizeof (init_state
));
324 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
326 machine_mode save_mode
;
329 /* No point in processing a register multiple times. This could happen
330 with register spans, e.g. when a reg is first processed as a piece of
331 a span, then as a register on its own later on. */
333 if (init_state
.processed_regno
[i
])
336 save_mode
= targetm
.dwarf_frame_reg_mode (i
);
337 span
= targetm
.dwarf_register_span (gen_rtx_REG (save_mode
, i
));
340 init_one_dwarf_reg_size (i
, save_mode
, mem
, mode
, &init_state
);
343 for (int si
= 0; si
< XVECLEN (span
, 0); si
++)
345 rtx reg
= XVECEXP (span
, 0, si
);
347 init_one_dwarf_reg_size
348 (REGNO (reg
), GET_MODE (reg
), mem
, mode
, &init_state
);
353 if (!init_state
.wrote_return_column
)
354 init_return_column_size (mode
, mem
, DWARF_FRAME_RETURN_COLUMN
);
356 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN
357 init_return_column_size (mode
, mem
, DWARF_ALT_FRAME_RETURN_COLUMN
);
360 targetm
.init_dwarf_reg_sizes_extra (address
);
364 static dw_trace_info
*
365 get_trace_info (rtx_insn
*insn
)
369 return trace_index
->find_with_hash (&dummy
, INSN_UID (insn
));
373 save_point_p (rtx_insn
*insn
)
375 /* Labels, except those that are really jump tables. */
377 return inside_basic_block_p (insn
);
379 /* We split traces at the prologue/epilogue notes because those
380 are points at which the unwind info is usually stable. This
381 makes it easier to find spots with identical unwind info so
382 that we can use remember/restore_state opcodes. */
384 switch (NOTE_KIND (insn
))
386 case NOTE_INSN_PROLOGUE_END
:
387 case NOTE_INSN_EPILOGUE_BEG
:
394 /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */
396 static inline HOST_WIDE_INT
397 div_data_align (HOST_WIDE_INT off
)
399 HOST_WIDE_INT r
= off
/ DWARF_CIE_DATA_ALIGNMENT
;
400 gcc_assert (r
* DWARF_CIE_DATA_ALIGNMENT
== off
);
404 /* Return true if we need a signed version of a given opcode
405 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */
408 need_data_align_sf_opcode (HOST_WIDE_INT off
)
410 return DWARF_CIE_DATA_ALIGNMENT
< 0 ? off
> 0 : off
< 0;
413 /* Return a pointer to a newly allocated Call Frame Instruction. */
415 static inline dw_cfi_ref
418 dw_cfi_ref cfi
= ggc_alloc
<dw_cfi_node
> ();
420 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= 0;
421 cfi
->dw_cfi_oprnd2
.dw_cfi_reg_num
= 0;
426 /* Return a newly allocated CFI row, with no defined data. */
431 dw_cfi_row
*row
= ggc_cleared_alloc
<dw_cfi_row
> ();
433 row
->cfa
.reg
.set_by_dwreg (INVALID_REGNUM
);
438 /* Return a copy of an existing CFI row. */
441 copy_cfi_row (dw_cfi_row
*src
)
443 dw_cfi_row
*dst
= ggc_alloc
<dw_cfi_row
> ();
446 dst
->reg_save
= vec_safe_copy (src
->reg_save
);
451 /* Return a copy of an existing CFA location. */
453 static dw_cfa_location
*
454 copy_cfa (dw_cfa_location
*src
)
456 dw_cfa_location
*dst
= ggc_alloc
<dw_cfa_location
> ();
461 /* Generate a new label for the CFI info to refer to. */
464 dwarf2out_cfi_label (void)
466 int num
= dwarf2out_cfi_label_num
++;
469 ASM_GENERATE_INTERNAL_LABEL (label
, "LCFI", num
);
471 return xstrdup (label
);
474 /* Add CFI either to the current insn stream or to a vector, or both. */
477 add_cfi (dw_cfi_ref cfi
)
479 any_cfis_emitted
= true;
481 if (add_cfi_insn
!= NULL
)
483 add_cfi_insn
= emit_note_after (NOTE_INSN_CFI
, add_cfi_insn
);
484 NOTE_CFI (add_cfi_insn
) = cfi
;
487 if (add_cfi_vec
!= NULL
)
488 vec_safe_push (*add_cfi_vec
, cfi
);
492 add_cfi_args_size (poly_int64 size
)
494 /* We don't yet have a representation for polynomial sizes. */
495 HOST_WIDE_INT const_size
= size
.to_constant ();
497 dw_cfi_ref cfi
= new_cfi ();
499 /* While we can occasionally have args_size < 0 internally, this state
500 should not persist at a point we actually need an opcode. */
501 gcc_assert (const_size
>= 0);
503 cfi
->dw_cfi_opc
= DW_CFA_GNU_args_size
;
504 cfi
->dw_cfi_oprnd1
.dw_cfi_offset
= const_size
;
510 add_cfi_restore (unsigned reg
)
512 dw_cfi_ref cfi
= new_cfi ();
514 cfi
->dw_cfi_opc
= (reg
& ~0x3f ? DW_CFA_restore_extended
: DW_CFA_restore
);
515 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= reg
;
520 /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating
521 that the register column is no longer saved. */
524 update_row_reg_save (dw_cfi_row
*row
, unsigned column
, dw_cfi_ref cfi
)
526 if (vec_safe_length (row
->reg_save
) <= column
)
527 vec_safe_grow_cleared (row
->reg_save
, column
+ 1, true);
528 (*row
->reg_save
)[column
] = cfi
;
531 /* This function fills in aa dw_cfa_location structure from a dwarf location
532 descriptor sequence. */
535 get_cfa_from_loc_descr (dw_cfa_location
*cfa
, struct dw_loc_descr_node
*loc
)
537 struct dw_loc_descr_node
*ptr
;
539 cfa
->base_offset
= 0;
541 cfa
->reg
.set_by_dwreg (INVALID_REGNUM
);
543 for (ptr
= loc
; ptr
!= NULL
; ptr
= ptr
->dw_loc_next
)
545 enum dwarf_location_atom op
= ptr
->dw_loc_opc
;
581 cfa
->reg
.set_by_dwreg (op
- DW_OP_reg0
);
584 cfa
->reg
.set_by_dwreg (ptr
->dw_loc_oprnd1
.v
.val_int
);
619 if (cfa
->reg
.reg
== INVALID_REGNUM
)
623 ? ptr
->dw_loc_oprnd1
.v
.val_int
: op
- DW_OP_breg0
);
624 cfa
->reg
.set_by_dwreg (regno
);
625 cfa
->base_offset
= ptr
->dw_loc_oprnd1
.v
.val_int
;
629 /* Handle case when span can cover multiple registers. We
630 only support the simple case of consecutive registers
631 all with the same size. DWARF that we are dealing with
632 will look something like:
633 <DW_OP_bregx: (r49) 0; DW_OP_const1u: 32; DW_OP_shl;
634 DW_OP_bregx: (r48) 0; DW_OP_plus> */
638 ? ptr
->dw_loc_oprnd1
.v
.val_int
: op
- DW_OP_breg0
);
639 gcc_assert (regno
== cfa
->reg
.reg
- 1);
641 /* From all the consecutive registers used, we want to set
642 cfa->reg.reg to lower number register. */
643 cfa
->reg
.reg
= regno
;
644 /* The offset was the shift value. Use it to get the
645 span_width and then set it to 0. */
646 cfa
->reg
.span_width
= cfa
->offset
.to_constant () / 8;
687 gcc_assert (known_eq (cfa
->offset
, 0));
688 cfa
->offset
= op
- DW_OP_lit0
;
698 gcc_assert (known_eq (cfa
->offset
, 0));
699 cfa
->offset
= ptr
->dw_loc_oprnd1
.v
.val_int
;
702 cfa
->offset
= -cfa
->offset
;
705 /* The offset is already in place. */
707 case DW_OP_plus_uconst
:
708 cfa
->offset
= ptr
->dw_loc_oprnd1
.v
.val_unsigned
;
716 /* Find the previous value for the CFA, iteratively. CFI is the opcode
717 to interpret, *LOC will be updated as necessary, *REMEMBER is used for
718 one level of remember/restore state processing. */
721 lookup_cfa_1 (dw_cfi_ref cfi
, dw_cfa_location
*loc
, dw_cfa_location
*remember
)
723 switch (cfi
->dw_cfi_opc
)
725 case DW_CFA_def_cfa_offset
:
726 case DW_CFA_def_cfa_offset_sf
:
727 loc
->offset
= cfi
->dw_cfi_oprnd1
.dw_cfi_offset
;
729 case DW_CFA_def_cfa_register
:
730 loc
->reg
.set_by_dwreg (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
);
733 case DW_CFA_def_cfa_sf
:
734 loc
->reg
.set_by_dwreg (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
);
735 loc
->offset
= cfi
->dw_cfi_oprnd2
.dw_cfi_offset
;
737 case DW_CFA_def_cfa_expression
:
738 if (cfi
->dw_cfi_oprnd2
.dw_cfi_cfa_loc
)
739 *loc
= *cfi
->dw_cfi_oprnd2
.dw_cfi_cfa_loc
;
741 get_cfa_from_loc_descr (loc
, cfi
->dw_cfi_oprnd1
.dw_cfi_loc
);
744 case DW_CFA_remember_state
:
745 gcc_assert (!remember
->in_use
);
747 remember
->in_use
= 1;
749 case DW_CFA_restore_state
:
750 gcc_assert (remember
->in_use
);
752 remember
->in_use
= 0;
760 /* Determine if two dw_cfa_location structures define the same data. */
763 cfa_equal_p (const dw_cfa_location
*loc1
, const dw_cfa_location
*loc2
)
765 return (loc1
->reg
== loc2
->reg
766 && known_eq (loc1
->offset
, loc2
->offset
)
767 && loc1
->indirect
== loc2
->indirect
768 && (loc1
->indirect
== 0
769 || known_eq (loc1
->base_offset
, loc2
->base_offset
)));
772 /* Determine if two CFI operands are identical. */
775 cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t
, dw_cfi_oprnd
*a
, dw_cfi_oprnd
*b
)
779 case dw_cfi_oprnd_unused
:
781 case dw_cfi_oprnd_reg_num
:
782 return a
->dw_cfi_reg_num
== b
->dw_cfi_reg_num
;
783 case dw_cfi_oprnd_offset
:
784 return a
->dw_cfi_offset
== b
->dw_cfi_offset
;
785 case dw_cfi_oprnd_addr
:
786 return (a
->dw_cfi_addr
== b
->dw_cfi_addr
787 || strcmp (a
->dw_cfi_addr
, b
->dw_cfi_addr
) == 0);
788 case dw_cfi_oprnd_loc
:
789 return loc_descr_equal_p (a
->dw_cfi_loc
, b
->dw_cfi_loc
);
790 case dw_cfi_oprnd_cfa_loc
:
791 return cfa_equal_p (a
->dw_cfi_cfa_loc
, b
->dw_cfi_cfa_loc
);
796 /* Determine if two CFI entries are identical. */
799 cfi_equal_p (dw_cfi_ref a
, dw_cfi_ref b
)
801 enum dwarf_call_frame_info opc
;
803 /* Make things easier for our callers, including missing operands. */
806 if (a
== NULL
|| b
== NULL
)
809 /* Obviously, the opcodes must match. */
811 if (opc
!= b
->dw_cfi_opc
)
814 /* Compare the two operands, re-using the type of the operands as
815 already exposed elsewhere. */
816 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc
),
817 &a
->dw_cfi_oprnd1
, &b
->dw_cfi_oprnd1
)
818 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc
),
819 &a
->dw_cfi_oprnd2
, &b
->dw_cfi_oprnd2
));
822 /* Determine if two CFI_ROW structures are identical. */
825 cfi_row_equal_p (dw_cfi_row
*a
, dw_cfi_row
*b
)
827 size_t i
, n_a
, n_b
, n_max
;
831 if (!cfi_equal_p (a
->cfa_cfi
, b
->cfa_cfi
))
834 else if (!cfa_equal_p (&a
->cfa
, &b
->cfa
))
837 n_a
= vec_safe_length (a
->reg_save
);
838 n_b
= vec_safe_length (b
->reg_save
);
839 n_max
= MAX (n_a
, n_b
);
841 for (i
= 0; i
< n_max
; ++i
)
843 dw_cfi_ref r_a
= NULL
, r_b
= NULL
;
846 r_a
= (*a
->reg_save
)[i
];
848 r_b
= (*b
->reg_save
)[i
];
850 if (!cfi_equal_p (r_a
, r_b
))
854 if (a
->window_save
!= b
->window_save
)
857 if (a
->ra_mangled
!= b
->ra_mangled
)
863 /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining
864 what opcode to emit. Returns the CFI opcode to effect the change, or
865 NULL if NEW_CFA == OLD_CFA. */
868 def_cfa_0 (dw_cfa_location
*old_cfa
, dw_cfa_location
*new_cfa
)
872 /* If nothing changed, no need to issue any call frame instructions. */
873 if (cfa_equal_p (old_cfa
, new_cfa
))
878 HOST_WIDE_INT const_offset
;
879 if (new_cfa
->reg
== old_cfa
->reg
880 && new_cfa
->reg
.span
== 1
881 && !new_cfa
->indirect
882 && !old_cfa
->indirect
883 && new_cfa
->offset
.is_constant (&const_offset
))
885 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating
886 the CFA register did not change but the offset did. The data
887 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or
888 in the assembler via the .cfi_def_cfa_offset directive. */
889 if (const_offset
< 0)
890 cfi
->dw_cfi_opc
= DW_CFA_def_cfa_offset_sf
;
892 cfi
->dw_cfi_opc
= DW_CFA_def_cfa_offset
;
893 cfi
->dw_cfi_oprnd1
.dw_cfi_offset
= const_offset
;
895 else if (new_cfa
->offset
.is_constant ()
896 && known_eq (new_cfa
->offset
, old_cfa
->offset
)
897 && old_cfa
->reg
.reg
!= INVALID_REGNUM
898 && new_cfa
->reg
.span
== 1
899 && !new_cfa
->indirect
900 && !old_cfa
->indirect
)
902 /* Construct a "DW_CFA_def_cfa_register <register>" instruction,
903 indicating the CFA register has changed to <register> but the
904 offset has not changed. This requires the old CFA to have
905 been set as a register plus offset rather than a general
906 DW_CFA_def_cfa_expression. */
907 cfi
->dw_cfi_opc
= DW_CFA_def_cfa_register
;
908 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= new_cfa
->reg
.reg
;
910 else if (new_cfa
->indirect
== 0
911 && new_cfa
->offset
.is_constant (&const_offset
)
912 && new_cfa
->reg
.span
== 1)
914 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction,
915 indicating the CFA register has changed to <register> with
916 the specified offset. The data factoring for DW_CFA_def_cfa_sf
917 happens in output_cfi, or in the assembler via the .cfi_def_cfa
919 if (const_offset
< 0)
920 cfi
->dw_cfi_opc
= DW_CFA_def_cfa_sf
;
922 cfi
->dw_cfi_opc
= DW_CFA_def_cfa
;
923 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= new_cfa
->reg
.reg
;
924 cfi
->dw_cfi_oprnd2
.dw_cfi_offset
= const_offset
;
928 /* Construct a DW_CFA_def_cfa_expression instruction to
929 calculate the CFA using a full location expression since no
930 register-offset pair is available. */
931 struct dw_loc_descr_node
*loc_list
;
933 cfi
->dw_cfi_opc
= DW_CFA_def_cfa_expression
;
934 loc_list
= build_cfa_loc (new_cfa
, 0);
935 cfi
->dw_cfi_oprnd1
.dw_cfi_loc
= loc_list
;
936 if (!new_cfa
->offset
.is_constant ()
937 || !new_cfa
->base_offset
.is_constant ())
938 /* It's hard to reconstruct the CFA location for a polynomial
939 expression, so just cache it instead. */
940 cfi
->dw_cfi_oprnd2
.dw_cfi_cfa_loc
= copy_cfa (new_cfa
);
942 cfi
->dw_cfi_oprnd2
.dw_cfi_cfa_loc
= NULL
;
948 /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */
951 def_cfa_1 (dw_cfa_location
*new_cfa
)
955 if (cur_trace
->cfa_store
.reg
== new_cfa
->reg
&& new_cfa
->indirect
== 0)
956 cur_trace
->cfa_store
.offset
= new_cfa
->offset
;
958 cfi
= def_cfa_0 (&cur_row
->cfa
, new_cfa
);
961 cur_row
->cfa
= *new_cfa
;
962 cur_row
->cfa_cfi
= (cfi
->dw_cfi_opc
== DW_CFA_def_cfa_expression
969 /* Add the CFI for saving a register. REG is the CFA column number.
970 If SREG is INVALID_REGISTER, the register is saved at OFFSET from the CFA;
971 otherwise it is saved in SREG. */
974 reg_save (unsigned int reg
, struct cfa_reg sreg
, poly_int64 offset
)
976 dw_fde_ref fde
= cfun
? cfun
->fde
: NULL
;
977 dw_cfi_ref cfi
= new_cfi ();
979 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= reg
;
981 if (sreg
.reg
== INVALID_REGNUM
)
983 HOST_WIDE_INT const_offset
;
984 /* When stack is aligned, store REG using DW_CFA_expression with FP. */
985 if (fde
&& fde
->stack_realign
)
987 cfi
->dw_cfi_opc
= DW_CFA_expression
;
988 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= reg
;
989 cfi
->dw_cfi_oprnd2
.dw_cfi_loc
990 = build_cfa_aligned_loc (&cur_row
->cfa
, offset
,
991 fde
->stack_realignment
);
993 else if (offset
.is_constant (&const_offset
))
995 if (need_data_align_sf_opcode (const_offset
))
996 cfi
->dw_cfi_opc
= DW_CFA_offset_extended_sf
;
997 else if (reg
& ~0x3f)
998 cfi
->dw_cfi_opc
= DW_CFA_offset_extended
;
1000 cfi
->dw_cfi_opc
= DW_CFA_offset
;
1001 cfi
->dw_cfi_oprnd2
.dw_cfi_offset
= const_offset
;
1005 cfi
->dw_cfi_opc
= DW_CFA_expression
;
1006 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= reg
;
1007 cfi
->dw_cfi_oprnd2
.dw_cfi_loc
1008 = build_cfa_loc (&cur_row
->cfa
, offset
);
1011 else if (sreg
.reg
== reg
)
1013 /* While we could emit something like DW_CFA_same_value or
1014 DW_CFA_restore, we never expect to see something like that
1015 in a prologue. This is more likely to be a bug. A backend
1016 can always bypass this by using REG_CFA_RESTORE directly. */
1019 else if (sreg
.span
> 1)
1021 cfi
->dw_cfi_opc
= DW_CFA_expression
;
1022 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= reg
;
1023 cfi
->dw_cfi_oprnd2
.dw_cfi_loc
= build_span_loc (sreg
);
1027 cfi
->dw_cfi_opc
= DW_CFA_register
;
1028 cfi
->dw_cfi_oprnd2
.dw_cfi_reg_num
= sreg
.reg
;
1032 update_row_reg_save (cur_row
, reg
, cfi
);
1035 /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note
1036 and adjust data structures to match. */
1039 notice_args_size (rtx_insn
*insn
)
1041 poly_int64 args_size
, delta
;
1044 note
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL
);
1048 if (!cur_trace
->eh_head
)
1049 cur_trace
->args_size_defined_for_eh
= true;
1051 args_size
= get_args_size (note
);
1052 delta
= args_size
- cur_trace
->end_true_args_size
;
1053 if (known_eq (delta
, 0))
1056 cur_trace
->end_true_args_size
= args_size
;
1058 /* If the CFA is computed off the stack pointer, then we must adjust
1059 the computation of the CFA as well. */
1060 if (cur_cfa
->reg
== dw_stack_pointer_regnum
)
1062 gcc_assert (!cur_cfa
->indirect
);
1064 /* Convert a change in args_size (always a positive in the
1065 direction of stack growth) to a change in stack pointer. */
1066 if (!STACK_GROWS_DOWNWARD
)
1069 cur_cfa
->offset
+= delta
;
1073 /* A subroutine of scan_trace. INSN is can_throw_internal. Update the
1074 data within the trace related to EH insns and args_size. */
1077 notice_eh_throw (rtx_insn
*insn
)
1079 poly_int64 args_size
= cur_trace
->end_true_args_size
;
1080 if (cur_trace
->eh_head
== NULL
)
1082 cur_trace
->eh_head
= insn
;
1083 cur_trace
->beg_delay_args_size
= args_size
;
1084 cur_trace
->end_delay_args_size
= args_size
;
1086 else if (maybe_ne (cur_trace
->end_delay_args_size
, args_size
))
1088 cur_trace
->end_delay_args_size
= args_size
;
1090 /* ??? If the CFA is the stack pointer, search backward for the last
1091 CFI note and insert there. Given that the stack changed for the
1092 args_size change, there *must* be such a note in between here and
1093 the last eh insn. */
1094 add_cfi_args_size (args_size
);
1098 /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */
1099 /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is
1100 used in places where rtl is prohibited. */
1102 static inline unsigned
1103 dwf_regno (const_rtx reg
)
1105 gcc_assert (REGNO (reg
) < FIRST_PSEUDO_REGISTER
);
1106 return DWARF_FRAME_REGNUM (REGNO (reg
));
1109 /* Like dwf_regno, but when the value can span multiple registers. */
1111 static struct cfa_reg
1112 dwf_cfa_reg (rtx reg
)
1114 struct cfa_reg result
;
1116 gcc_assert (REGNO (reg
) < FIRST_PSEUDO_REGISTER
);
1118 result
.reg
= dwf_regno (reg
);
1120 result
.span_width
= 0;
1122 rtx span
= targetm
.dwarf_register_span (reg
);
1125 /* We only support the simple case of consecutive registers all with the
1127 result
.span
= XVECLEN (span
, 0);
1128 result
.span_width
= GET_MODE_SIZE (GET_MODE (XVECEXP (span
, 0, 0)))
1133 /* Ensure that the above assumption is accurate. */
1134 for (unsigned int i
= 0; i
< result
.span
; i
++)
1136 gcc_assert (GET_MODE_SIZE (GET_MODE (XVECEXP (span
, 0, i
)))
1137 .to_constant () == result
.span_width
);
1138 gcc_assert (REG_P (XVECEXP (span
, 0, i
)));
1139 gcc_assert (dwf_regno (XVECEXP (span
, 0, i
)) == result
.reg
+ i
);
1147 /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */
1150 compare_reg_or_pc (rtx x
, rtx y
)
1152 if (REG_P (x
) && REG_P (y
))
1153 return REGNO (x
) == REGNO (y
);
1157 /* Record SRC as being saved in DEST. DEST may be null to delete an
1158 existing entry. SRC may be a register or PC_RTX. */
1161 record_reg_saved_in_reg (rtx dest
, rtx src
)
1163 reg_saved_in_data
*elt
;
1166 FOR_EACH_VEC_ELT (cur_trace
->regs_saved_in_regs
, i
, elt
)
1167 if (compare_reg_or_pc (elt
->orig_reg
, src
))
1170 cur_trace
->regs_saved_in_regs
.unordered_remove (i
);
1172 elt
->saved_in_reg
= dest
;
1179 reg_saved_in_data e
= {src
, dest
};
1180 cur_trace
->regs_saved_in_regs
.safe_push (e
);
1183 /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at
1184 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */
1187 queue_reg_save (rtx reg
, rtx sreg
, poly_int64 offset
)
1190 queued_reg_save e
= {reg
, sreg
, offset
};
1193 /* Duplicates waste space, but it's also necessary to remove them
1194 for correctness, since the queue gets output in reverse order. */
1195 FOR_EACH_VEC_ELT (queued_reg_saves
, i
, q
)
1196 if (compare_reg_or_pc (q
->reg
, reg
))
1202 queued_reg_saves
.safe_push (e
);
1205 /* Output all the entries in QUEUED_REG_SAVES. */
1208 dwarf2out_flush_queued_reg_saves (void)
1213 FOR_EACH_VEC_ELT (queued_reg_saves
, i
, q
)
1216 struct cfa_reg sreg
;
1218 record_reg_saved_in_reg (q
->saved_reg
, q
->reg
);
1220 if (q
->reg
== pc_rtx
)
1221 reg
= DWARF_FRAME_RETURN_COLUMN
;
1223 reg
= dwf_regno (q
->reg
);
1225 sreg
= dwf_cfa_reg (q
->saved_reg
);
1227 sreg
.set_by_dwreg (INVALID_REGNUM
);
1228 reg_save (reg
, sreg
, q
->cfa_offset
);
1231 queued_reg_saves
.truncate (0);
1234 /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved
1235 location for? Or, does it clobber a register which we've previously
1236 said that some other register is saved in, and for which we now
1237 have a new location for? */
1240 clobbers_queued_reg_save (const_rtx insn
)
1245 FOR_EACH_VEC_ELT (queued_reg_saves
, iq
, q
)
1248 reg_saved_in_data
*rir
;
1250 if (modified_in_p (q
->reg
, insn
))
1253 FOR_EACH_VEC_ELT (cur_trace
->regs_saved_in_regs
, ir
, rir
)
1254 if (compare_reg_or_pc (q
->reg
, rir
->orig_reg
)
1255 && modified_in_p (rir
->saved_in_reg
, insn
))
1262 /* What register, if any, is currently saved in REG? */
1265 reg_saved_in (rtx reg
)
1267 unsigned int regn
= REGNO (reg
);
1269 reg_saved_in_data
*rir
;
1272 FOR_EACH_VEC_ELT (queued_reg_saves
, i
, q
)
1273 if (q
->saved_reg
&& regn
== REGNO (q
->saved_reg
))
1276 FOR_EACH_VEC_ELT (cur_trace
->regs_saved_in_regs
, i
, rir
)
1277 if (regn
== REGNO (rir
->saved_in_reg
))
1278 return rir
->orig_reg
;
1283 /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */
1286 dwarf2out_frame_debug_def_cfa (rtx pat
)
1288 memset (cur_cfa
, 0, sizeof (*cur_cfa
));
1290 pat
= strip_offset (pat
, &cur_cfa
->offset
);
1293 cur_cfa
->indirect
= 1;
1294 pat
= strip_offset (XEXP (pat
, 0), &cur_cfa
->base_offset
);
1296 /* ??? If this fails, we could be calling into the _loc functions to
1297 define a full expression. So far no port does that. */
1298 gcc_assert (REG_P (pat
));
1299 cur_cfa
->reg
= dwf_cfa_reg (pat
);
1302 /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */
1305 dwarf2out_frame_debug_adjust_cfa (rtx pat
)
1309 gcc_assert (GET_CODE (pat
) == SET
);
1310 dest
= XEXP (pat
, 0);
1311 src
= XEXP (pat
, 1);
1313 switch (GET_CODE (src
))
1316 gcc_assert (dwf_cfa_reg (XEXP (src
, 0)) == cur_cfa
->reg
);
1317 cur_cfa
->offset
-= rtx_to_poly_int64 (XEXP (src
, 1));
1327 cur_cfa
->reg
= dwf_cfa_reg (dest
);
1328 gcc_assert (cur_cfa
->indirect
== 0);
1331 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */
1334 dwarf2out_frame_debug_cfa_offset (rtx set
)
1337 rtx src
, addr
, span
;
1338 unsigned int sregno
;
1340 src
= XEXP (set
, 1);
1341 addr
= XEXP (set
, 0);
1342 gcc_assert (MEM_P (addr
));
1343 addr
= XEXP (addr
, 0);
1345 /* As documented, only consider extremely simple addresses. */
1346 switch (GET_CODE (addr
))
1349 gcc_assert (dwf_cfa_reg (addr
) == cur_cfa
->reg
);
1350 offset
= -cur_cfa
->offset
;
1353 gcc_assert (dwf_cfa_reg (XEXP (addr
, 0)) == cur_cfa
->reg
);
1354 offset
= rtx_to_poly_int64 (XEXP (addr
, 1)) - cur_cfa
->offset
;
1363 sregno
= DWARF_FRAME_RETURN_COLUMN
;
1367 span
= targetm
.dwarf_register_span (src
);
1368 sregno
= dwf_regno (src
);
1371 /* ??? We'd like to use queue_reg_save, but we need to come up with
1372 a different flushing heuristic for epilogues. */
1373 struct cfa_reg invalid
;
1374 invalid
.set_by_dwreg (INVALID_REGNUM
);
1376 reg_save (sregno
, invalid
, offset
);
1379 /* We have a PARALLEL describing where the contents of SRC live.
1380 Adjust the offset for each piece of the PARALLEL. */
1381 poly_int64 span_offset
= offset
;
1383 gcc_assert (GET_CODE (span
) == PARALLEL
);
1385 const int par_len
= XVECLEN (span
, 0);
1386 for (int par_index
= 0; par_index
< par_len
; par_index
++)
1388 rtx elem
= XVECEXP (span
, 0, par_index
);
1389 sregno
= dwf_regno (src
);
1390 reg_save (sregno
, invalid
, span_offset
);
1391 span_offset
+= GET_MODE_SIZE (GET_MODE (elem
));
1396 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */
1399 dwarf2out_frame_debug_cfa_register (rtx set
)
1403 struct cfa_reg dregno
;
1405 src
= XEXP (set
, 1);
1406 dest
= XEXP (set
, 0);
1408 record_reg_saved_in_reg (dest
, src
);
1410 sregno
= DWARF_FRAME_RETURN_COLUMN
;
1412 sregno
= dwf_regno (src
);
1414 dregno
= dwf_cfa_reg (dest
);
1416 /* ??? We'd like to use queue_reg_save, but we need to come up with
1417 a different flushing heuristic for epilogues. */
1418 reg_save (sregno
, dregno
, 0);
1421 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */
1424 dwarf2out_frame_debug_cfa_expression (rtx set
)
1426 rtx src
, dest
, span
;
1427 dw_cfi_ref cfi
= new_cfi ();
1430 dest
= SET_DEST (set
);
1431 src
= SET_SRC (set
);
1433 gcc_assert (REG_P (src
));
1434 gcc_assert (MEM_P (dest
));
1436 span
= targetm
.dwarf_register_span (src
);
1439 regno
= dwf_regno (src
);
1441 cfi
->dw_cfi_opc
= DW_CFA_expression
;
1442 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= regno
;
1443 cfi
->dw_cfi_oprnd2
.dw_cfi_loc
1444 = mem_loc_descriptor (XEXP (dest
, 0), get_address_mode (dest
),
1445 GET_MODE (dest
), VAR_INIT_STATUS_INITIALIZED
);
1447 /* ??? We'd like to use queue_reg_save, were the interface different,
1448 and, as above, we could manage flushing for epilogues. */
1450 update_row_reg_save (cur_row
, regno
, cfi
);
1453 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_VAL_EXPRESSION
1457 dwarf2out_frame_debug_cfa_val_expression (rtx set
)
1459 rtx dest
= SET_DEST (set
);
1460 gcc_assert (REG_P (dest
));
1462 rtx span
= targetm
.dwarf_register_span (dest
);
1465 rtx src
= SET_SRC (set
);
1466 dw_cfi_ref cfi
= new_cfi ();
1467 cfi
->dw_cfi_opc
= DW_CFA_val_expression
;
1468 cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
= dwf_regno (dest
);
1469 cfi
->dw_cfi_oprnd2
.dw_cfi_loc
1470 = mem_loc_descriptor (src
, GET_MODE (src
),
1471 GET_MODE (dest
), VAR_INIT_STATUS_INITIALIZED
);
1473 update_row_reg_save (cur_row
, dwf_regno (dest
), cfi
);
1476 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */
1479 dwarf2out_frame_debug_cfa_restore (rtx reg
)
1481 gcc_assert (REG_P (reg
));
1483 rtx span
= targetm
.dwarf_register_span (reg
);
1486 unsigned int regno
= dwf_regno (reg
);
1487 add_cfi_restore (regno
);
1488 update_row_reg_save (cur_row
, regno
, NULL
);
1492 /* We have a PARALLEL describing where the contents of REG live.
1493 Restore the register for each piece of the PARALLEL. */
1494 gcc_assert (GET_CODE (span
) == PARALLEL
);
1496 const int par_len
= XVECLEN (span
, 0);
1497 for (int par_index
= 0; par_index
< par_len
; par_index
++)
1499 reg
= XVECEXP (span
, 0, par_index
);
1500 gcc_assert (REG_P (reg
));
1501 unsigned int regno
= dwf_regno (reg
);
1502 add_cfi_restore (regno
);
1503 update_row_reg_save (cur_row
, regno
, NULL
);
1508 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE.
1510 ??? Perhaps we should note in the CIE where windows are saved (instead
1511 of assuming 0(cfa)) and what registers are in the window. */
1514 dwarf2out_frame_debug_cfa_window_save (void)
1516 dw_cfi_ref cfi
= new_cfi ();
1518 cfi
->dw_cfi_opc
= DW_CFA_GNU_window_save
;
1520 cur_row
->window_save
= true;
1523 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_TOGGLE_RA_MANGLE.
1524 Note: DW_CFA_GNU_window_save dwarf opcode is reused for toggling RA mangle
1525 state, this is a target specific operation on AArch64 and can only be used
1526 on other targets if they don't use the window save operation otherwise. */
1529 dwarf2out_frame_debug_cfa_toggle_ra_mangle (void)
1531 dw_cfi_ref cfi
= new_cfi ();
1533 cfi
->dw_cfi_opc
= DW_CFA_GNU_window_save
;
1535 cur_row
->ra_mangled
= !cur_row
->ra_mangled
;
1538 /* Record call frame debugging information for an expression EXPR,
1539 which either sets SP or FP (adjusting how we calculate the frame
1540 address) or saves a register to the stack or another register.
1541 LABEL indicates the address of EXPR.
1543 This function encodes a state machine mapping rtxes to actions on
1544 cfa, cfa_store, and cfa_temp.reg. We describe these rules so
1545 users need not read the source code.
1547 The High-Level Picture
1549 Changes in the register we use to calculate the CFA: Currently we
1550 assume that if you copy the CFA register into another register, we
1551 should take the other one as the new CFA register; this seems to
1552 work pretty well. If it's wrong for some target, it's simple
1553 enough not to set RTX_FRAME_RELATED_P on the insn in question.
1555 Changes in the register we use for saving registers to the stack:
1556 This is usually SP, but not always. Again, we deduce that if you
1557 copy SP into another register (and SP is not the CFA register),
1558 then the new register is the one we will be using for register
1559 saves. This also seems to work.
1561 Register saves: There's not much guesswork about this one; if
1562 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a
1563 register save, and the register used to calculate the destination
1564 had better be the one we think we're using for this purpose.
1565 It's also assumed that a copy from a call-saved register to another
1566 register is saving that register if RTX_FRAME_RELATED_P is set on
1567 that instruction. If the copy is from a call-saved register to
1568 the *same* register, that means that the register is now the same
1569 value as in the caller.
1571 Except: If the register being saved is the CFA register, and the
1572 offset is nonzero, we are saving the CFA, so we assume we have to
1573 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that
1574 the intent is to save the value of SP from the previous frame.
1576 In addition, if a register has previously been saved to a different
1579 Invariants / Summaries of Rules
1581 cfa current rule for calculating the CFA. It usually
1582 consists of a register and an offset. This is
1583 actually stored in *cur_cfa, but abbreviated
1584 for the purposes of this documentation.
1585 cfa_store register used by prologue code to save things to the stack
1586 cfa_store.offset is the offset from the value of
1587 cfa_store.reg to the actual CFA
1588 cfa_temp register holding an integral value. cfa_temp.offset
1589 stores the value, which will be used to adjust the
1590 stack pointer. cfa_temp is also used like cfa_store,
1591 to track stores to the stack via fp or a temp reg.
1593 Rules 1- 4: Setting a register's value to cfa.reg or an expression
1594 with cfa.reg as the first operand changes the cfa.reg and its
1595 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and
1598 Rules 6- 9: Set a non-cfa.reg register value to a constant or an
1599 expression yielding a constant. This sets cfa_temp.reg
1600 and cfa_temp.offset.
1602 Rule 5: Create a new register cfa_store used to save items to the
1605 Rules 10-14: Save a register to the stack. Define offset as the
1606 difference of the original location and cfa_store's
1607 location (or cfa_temp's location if cfa_temp is used).
1609 Rules 16-20: If AND operation happens on sp in prologue, we assume
1610 stack is realigned. We will use a group of DW_OP_XXX
1611 expressions to represent the location of the stored
1612 register instead of CFA+offset.
1616 "{a,b}" indicates a choice of a xor b.
1617 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg.
1620 (set <reg1> <reg2>:cfa.reg)
1621 effects: cfa.reg = <reg1>
1622 cfa.offset unchanged
1623 cfa_temp.reg = <reg1>
1624 cfa_temp.offset = cfa.offset
1627 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg
1628 {<const_int>,<reg>:cfa_temp.reg}))
1629 effects: cfa.reg = sp if fp used
1630 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp
1631 cfa_store.offset += {+/- <const_int>, cfa_temp.offset}
1632 if cfa_store.reg==sp
1635 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>))
1636 effects: cfa.reg = fp
1637 cfa_offset += +/- <const_int>
1640 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>))
1641 constraints: <reg1> != fp
1643 effects: cfa.reg = <reg1>
1644 cfa_temp.reg = <reg1>
1645 cfa_temp.offset = cfa.offset
1648 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg))
1649 constraints: <reg1> != fp
1651 effects: cfa_store.reg = <reg1>
1652 cfa_store.offset = cfa.offset - cfa_temp.offset
1655 (set <reg> <const_int>)
1656 effects: cfa_temp.reg = <reg>
1657 cfa_temp.offset = <const_int>
1660 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>))
1661 effects: cfa_temp.reg = <reg1>
1662 cfa_temp.offset |= <const_int>
1665 (set <reg> (high <exp>))
1669 (set <reg> (lo_sum <exp> <const_int>))
1670 effects: cfa_temp.reg = <reg>
1671 cfa_temp.offset = <const_int>
1674 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>)
1675 effects: cfa_store.offset -= <const_int>
1676 cfa.offset = cfa_store.offset if cfa.reg == sp
1678 cfa.base_offset = -cfa_store.offset
1681 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>)
1682 effects: cfa_store.offset += -/+ mode_size(mem)
1683 cfa.offset = cfa_store.offset if cfa.reg == sp
1685 cfa.base_offset = -cfa_store.offset
1688 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>))
1691 effects: cfa.reg = <reg1>
1692 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset
1695 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>)
1696 effects: cfa.reg = <reg1>
1697 cfa.base_offset = -{cfa_store,cfa_temp}.offset
1700 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>)
1701 effects: cfa.reg = <reg1>
1702 cfa.base_offset = -cfa_temp.offset
1703 cfa_temp.offset -= mode_size(mem)
1706 (set <reg> {unspec, unspec_volatile})
1707 effects: target-dependent
1710 (set sp (and: sp <const_int>))
1711 constraints: cfa_store.reg == sp
1712 effects: cfun->fde.stack_realign = 1
1713 cfa_store.offset = 0
1714 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp
1717 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int))))
1718 effects: cfa_store.offset += -/+ mode_size(mem)
1721 (set (mem ({pre_inc, pre_dec} sp)) fp)
1722 constraints: fde->stack_realign == 1
1723 effects: cfa_store.offset = 0
1724 cfa.reg != HARD_FRAME_POINTER_REGNUM
1727 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg)
1728 constraints: fde->stack_realign == 1
1730 && cfa.indirect == 0
1731 && cfa.reg != HARD_FRAME_POINTER_REGNUM
1732 effects: Use DW_CFA_def_cfa_expression to define cfa
1733 cfa.reg == fde->drap_reg */
1736 dwarf2out_frame_debug_expr (rtx expr
)
1738 rtx src
, dest
, span
;
1742 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of
1743 the PARALLEL independently. The first element is always processed if
1744 it is a SET. This is for backward compatibility. Other elements
1745 are processed only if they are SETs and the RTX_FRAME_RELATED_P
1746 flag is set in them. */
1747 if (GET_CODE (expr
) == PARALLEL
|| GET_CODE (expr
) == SEQUENCE
)
1750 int limit
= XVECLEN (expr
, 0);
1753 /* PARALLELs have strict read-modify-write semantics, so we
1754 ought to evaluate every rvalue before changing any lvalue.
1755 It's cumbersome to do that in general, but there's an
1756 easy approximation that is enough for all current users:
1757 handle register saves before register assignments. */
1758 if (GET_CODE (expr
) == PARALLEL
)
1759 for (par_index
= 0; par_index
< limit
; par_index
++)
1761 elem
= XVECEXP (expr
, 0, par_index
);
1762 if (GET_CODE (elem
) == SET
1763 && MEM_P (SET_DEST (elem
))
1764 && (RTX_FRAME_RELATED_P (elem
) || par_index
== 0))
1765 dwarf2out_frame_debug_expr (elem
);
1768 for (par_index
= 0; par_index
< limit
; par_index
++)
1770 elem
= XVECEXP (expr
, 0, par_index
);
1771 if (GET_CODE (elem
) == SET
1772 && (!MEM_P (SET_DEST (elem
)) || GET_CODE (expr
) == SEQUENCE
)
1773 && (RTX_FRAME_RELATED_P (elem
) || par_index
== 0))
1774 dwarf2out_frame_debug_expr (elem
);
1779 gcc_assert (GET_CODE (expr
) == SET
);
1781 src
= SET_SRC (expr
);
1782 dest
= SET_DEST (expr
);
1786 rtx rsi
= reg_saved_in (src
);
1793 switch (GET_CODE (dest
))
1796 switch (GET_CODE (src
))
1798 /* Setting FP from SP. */
1800 if (cur_cfa
->reg
== dwf_cfa_reg (src
))
1803 /* Update the CFA rule wrt SP or FP. Make sure src is
1804 relative to the current CFA register.
1806 We used to require that dest be either SP or FP, but the
1807 ARM copies SP to a temporary register, and from there to
1808 FP. So we just rely on the backends to only set
1809 RTX_FRAME_RELATED_P on appropriate insns. */
1810 cur_cfa
->reg
= dwf_cfa_reg (dest
);
1811 cur_trace
->cfa_temp
.reg
= cur_cfa
->reg
;
1812 cur_trace
->cfa_temp
.offset
= cur_cfa
->offset
;
1816 /* Saving a register in a register. */
1817 gcc_assert (!fixed_regs
[REGNO (dest
)]
1818 /* For the SPARC and its register window. */
1819 || (dwf_regno (src
) == DWARF_FRAME_RETURN_COLUMN
));
1821 /* After stack is aligned, we can only save SP in FP
1822 if drap register is used. In this case, we have
1823 to restore stack pointer with the CFA value and we
1824 don't generate this DWARF information. */
1826 && fde
->stack_realign
1827 && REGNO (src
) == STACK_POINTER_REGNUM
)
1829 gcc_assert (REGNO (dest
) == HARD_FRAME_POINTER_REGNUM
1830 && fde
->drap_reg
!= INVALID_REGNUM
1831 && cur_cfa
->reg
!= dwf_cfa_reg (src
)
1834 /* The save of hard frame pointer has been deferred
1835 until this point when Rule 18 applied. Emit it now. */
1836 queue_reg_save (dest
, NULL_RTX
, 0);
1837 /* And as the instruction modifies the hard frame pointer,
1838 flush the queue as well. */
1839 dwarf2out_flush_queued_reg_saves ();
1842 queue_reg_save (src
, dest
, 0);
1849 if (dest
== stack_pointer_rtx
)
1853 if (REG_P (XEXP (src
, 1)))
1855 gcc_assert (dwf_cfa_reg (XEXP (src
, 1))
1856 == cur_trace
->cfa_temp
.reg
);
1857 offset
= cur_trace
->cfa_temp
.offset
;
1859 else if (!poly_int_rtx_p (XEXP (src
, 1), &offset
))
1862 if (XEXP (src
, 0) == hard_frame_pointer_rtx
)
1864 /* Restoring SP from FP in the epilogue. */
1865 gcc_assert (cur_cfa
->reg
== dw_frame_pointer_regnum
);
1866 cur_cfa
->reg
= dw_stack_pointer_regnum
;
1868 else if (GET_CODE (src
) == LO_SUM
)
1869 /* Assume we've set the source reg of the LO_SUM from sp. */
1872 gcc_assert (XEXP (src
, 0) == stack_pointer_rtx
);
1874 if (GET_CODE (src
) != MINUS
)
1876 if (cur_cfa
->reg
== dw_stack_pointer_regnum
)
1877 cur_cfa
->offset
+= offset
;
1878 if (cur_trace
->cfa_store
.reg
== dw_stack_pointer_regnum
)
1879 cur_trace
->cfa_store
.offset
+= offset
;
1881 else if (dest
== hard_frame_pointer_rtx
)
1884 /* Either setting the FP from an offset of the SP,
1885 or adjusting the FP */
1886 gcc_assert (frame_pointer_needed
);
1888 gcc_assert (REG_P (XEXP (src
, 0))
1889 && dwf_cfa_reg (XEXP (src
, 0)) == cur_cfa
->reg
);
1890 offset
= rtx_to_poly_int64 (XEXP (src
, 1));
1891 if (GET_CODE (src
) != MINUS
)
1893 cur_cfa
->offset
+= offset
;
1894 cur_cfa
->reg
= dw_frame_pointer_regnum
;
1898 gcc_assert (GET_CODE (src
) != MINUS
);
1901 if (REG_P (XEXP (src
, 0))
1902 && dwf_cfa_reg (XEXP (src
, 0)) == cur_cfa
->reg
1903 && poly_int_rtx_p (XEXP (src
, 1), &offset
))
1905 /* Setting a temporary CFA register that will be copied
1906 into the FP later on. */
1908 cur_cfa
->offset
+= offset
;
1909 cur_cfa
->reg
= dwf_cfa_reg (dest
);
1910 /* Or used to save regs to the stack. */
1911 cur_trace
->cfa_temp
.reg
= cur_cfa
->reg
;
1912 cur_trace
->cfa_temp
.offset
= cur_cfa
->offset
;
1916 else if (REG_P (XEXP (src
, 0))
1917 && dwf_cfa_reg (XEXP (src
, 0)) == cur_trace
->cfa_temp
.reg
1918 && XEXP (src
, 1) == stack_pointer_rtx
)
1920 /* Setting a scratch register that we will use instead
1921 of SP for saving registers to the stack. */
1922 gcc_assert (cur_cfa
->reg
== dw_stack_pointer_regnum
);
1923 cur_trace
->cfa_store
.reg
= dwf_cfa_reg (dest
);
1924 cur_trace
->cfa_store
.offset
1925 = cur_cfa
->offset
- cur_trace
->cfa_temp
.offset
;
1929 else if (GET_CODE (src
) == LO_SUM
1930 && poly_int_rtx_p (XEXP (src
, 1),
1931 &cur_trace
->cfa_temp
.offset
))
1932 cur_trace
->cfa_temp
.reg
= dwf_cfa_reg (dest
);
1940 case CONST_POLY_INT
:
1941 cur_trace
->cfa_temp
.reg
= dwf_cfa_reg (dest
);
1942 cur_trace
->cfa_temp
.offset
= rtx_to_poly_int64 (src
);
1947 gcc_assert (REG_P (XEXP (src
, 0))
1948 && dwf_cfa_reg (XEXP (src
, 0)) == cur_trace
->cfa_temp
.reg
1949 && CONST_INT_P (XEXP (src
, 1)));
1951 cur_trace
->cfa_temp
.reg
= dwf_cfa_reg (dest
);
1952 if (!can_ior_p (cur_trace
->cfa_temp
.offset
, INTVAL (XEXP (src
, 1)),
1953 &cur_trace
->cfa_temp
.offset
))
1954 /* The target shouldn't generate this kind of CFI note if we
1955 can't represent it. */
1959 /* Skip over HIGH, assuming it will be followed by a LO_SUM,
1960 which will fill in all of the bits. */
1967 case UNSPEC_VOLATILE
:
1968 /* All unspecs should be represented by REG_CFA_* notes. */
1974 /* If this AND operation happens on stack pointer in prologue,
1975 we assume the stack is realigned and we extract the
1977 if (fde
&& XEXP (src
, 0) == stack_pointer_rtx
)
1979 /* We interpret reg_save differently with stack_realign set.
1980 Thus we must flush whatever we have queued first. */
1981 dwarf2out_flush_queued_reg_saves ();
1983 gcc_assert (cur_trace
->cfa_store
.reg
1984 == dwf_cfa_reg (XEXP (src
, 0)));
1985 fde
->stack_realign
= 1;
1986 fde
->stack_realignment
= INTVAL (XEXP (src
, 1));
1987 cur_trace
->cfa_store
.offset
= 0;
1989 if (cur_cfa
->reg
!= dw_stack_pointer_regnum
1990 && cur_cfa
->reg
!= dw_frame_pointer_regnum
)
1992 gcc_assert (cur_cfa
->reg
.span
== 1);
1993 fde
->drap_reg
= cur_cfa
->reg
.reg
;
2005 /* Saving a register to the stack. Make sure dest is relative to the
2007 switch (GET_CODE (XEXP (dest
, 0)))
2013 /* We can't handle variable size modifications. */
2014 offset
= -rtx_to_poly_int64 (XEXP (XEXP (XEXP (dest
, 0), 1), 1));
2016 gcc_assert (REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2017 && cur_trace
->cfa_store
.reg
== dw_stack_pointer_regnum
);
2019 cur_trace
->cfa_store
.offset
+= offset
;
2020 if (cur_cfa
->reg
== dw_stack_pointer_regnum
)
2021 cur_cfa
->offset
= cur_trace
->cfa_store
.offset
;
2023 if (GET_CODE (XEXP (dest
, 0)) == POST_MODIFY
)
2024 offset
-= cur_trace
->cfa_store
.offset
;
2026 offset
= -cur_trace
->cfa_store
.offset
;
2033 offset
= GET_MODE_SIZE (GET_MODE (dest
));
2034 if (GET_CODE (XEXP (dest
, 0)) == PRE_INC
)
2037 gcc_assert ((REGNO (XEXP (XEXP (dest
, 0), 0))
2038 == STACK_POINTER_REGNUM
)
2039 && cur_trace
->cfa_store
.reg
== dw_stack_pointer_regnum
);
2041 cur_trace
->cfa_store
.offset
+= offset
;
2043 /* Rule 18: If stack is aligned, we will use FP as a
2044 reference to represent the address of the stored
2047 && fde
->stack_realign
2049 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
2051 gcc_assert (cur_cfa
->reg
!= dw_frame_pointer_regnum
);
2052 cur_trace
->cfa_store
.offset
= 0;
2056 if (cur_cfa
->reg
== dw_stack_pointer_regnum
)
2057 cur_cfa
->offset
= cur_trace
->cfa_store
.offset
;
2059 if (GET_CODE (XEXP (dest
, 0)) == POST_DEC
)
2060 offset
+= -cur_trace
->cfa_store
.offset
;
2062 offset
= -cur_trace
->cfa_store
.offset
;
2066 /* With an offset. */
2071 struct cfa_reg regno
;
2073 gcc_assert (REG_P (XEXP (XEXP (dest
, 0), 0)));
2074 offset
= rtx_to_poly_int64 (XEXP (XEXP (dest
, 0), 1));
2075 if (GET_CODE (XEXP (dest
, 0)) == MINUS
)
2078 regno
= dwf_cfa_reg (XEXP (XEXP (dest
, 0), 0));
2080 if (cur_cfa
->reg
== regno
)
2081 offset
-= cur_cfa
->offset
;
2082 else if (cur_trace
->cfa_store
.reg
== regno
)
2083 offset
-= cur_trace
->cfa_store
.offset
;
2086 gcc_assert (cur_trace
->cfa_temp
.reg
== regno
);
2087 offset
-= cur_trace
->cfa_temp
.offset
;
2093 /* Without an offset. */
2096 struct cfa_reg regno
= dwf_cfa_reg (XEXP (dest
, 0));
2098 if (cur_cfa
->reg
== regno
)
2099 offset
= -cur_cfa
->offset
;
2100 else if (cur_trace
->cfa_store
.reg
== regno
)
2101 offset
= -cur_trace
->cfa_store
.offset
;
2104 gcc_assert (cur_trace
->cfa_temp
.reg
== regno
);
2105 offset
= -cur_trace
->cfa_temp
.offset
;
2112 gcc_assert (cur_trace
->cfa_temp
.reg
2113 == dwf_cfa_reg (XEXP (XEXP (dest
, 0), 0)));
2114 offset
= -cur_trace
->cfa_temp
.offset
;
2115 cur_trace
->cfa_temp
.offset
-= GET_MODE_SIZE (GET_MODE (dest
));
2123 /* If the source operand of this MEM operation is a memory,
2124 we only care how much stack grew. */
2129 && REGNO (src
) != STACK_POINTER_REGNUM
2130 && REGNO (src
) != HARD_FRAME_POINTER_REGNUM
2131 && dwf_cfa_reg (src
) == cur_cfa
->reg
)
2133 /* We're storing the current CFA reg into the stack. */
2135 if (known_eq (cur_cfa
->offset
, 0))
2138 /* If stack is aligned, putting CFA reg into stack means
2139 we can no longer use reg + offset to represent CFA.
2140 Here we use DW_CFA_def_cfa_expression instead. The
2141 result of this expression equals to the original CFA
2144 && fde
->stack_realign
2145 && cur_cfa
->indirect
== 0
2146 && cur_cfa
->reg
!= dw_frame_pointer_regnum
)
2148 gcc_assert (fde
->drap_reg
== cur_cfa
->reg
.reg
);
2150 cur_cfa
->indirect
= 1;
2151 cur_cfa
->reg
= dw_frame_pointer_regnum
;
2152 cur_cfa
->base_offset
= offset
;
2153 cur_cfa
->offset
= 0;
2155 fde
->drap_reg_saved
= 1;
2159 /* If the source register is exactly the CFA, assume
2160 we're saving SP like any other register; this happens
2162 queue_reg_save (stack_pointer_rtx
, NULL_RTX
, offset
);
2167 /* Otherwise, we'll need to look in the stack to
2168 calculate the CFA. */
2169 rtx x
= XEXP (dest
, 0);
2173 gcc_assert (REG_P (x
));
2175 cur_cfa
->reg
= dwf_cfa_reg (x
);
2176 cur_cfa
->base_offset
= offset
;
2177 cur_cfa
->indirect
= 1;
2183 span
= targetm
.dwarf_register_span (src
);
2190 /* Just verify the hard frame pointer save when doing dynamic
2191 realignment uses expected offset. The actual queue_reg_save
2192 needs to be deferred until the instruction that sets
2193 hard frame pointer to stack pointer, see PR99334 for
2195 gcc_assert (known_eq (offset
, 0));
2197 queue_reg_save (src
, NULL_RTX
, offset
);
2201 /* We have a PARALLEL describing where the contents of SRC live.
2202 Queue register saves for each piece of the PARALLEL. */
2203 poly_int64 span_offset
= offset
;
2205 gcc_assert (GET_CODE (span
) == PARALLEL
);
2207 const int par_len
= XVECLEN (span
, 0);
2208 for (int par_index
= 0; par_index
< par_len
; par_index
++)
2210 rtx elem
= XVECEXP (span
, 0, par_index
);
2211 queue_reg_save (elem
, NULL_RTX
, span_offset
);
2212 span_offset
+= GET_MODE_SIZE (GET_MODE (elem
));
2222 /* Record call frame debugging information for INSN, which either sets
2223 SP or FP (adjusting how we calculate the frame address) or saves a
2224 register to the stack. */
2227 dwarf2out_frame_debug (rtx_insn
*insn
)
2230 bool handled_one
= false;
2232 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2233 switch (REG_NOTE_KIND (note
))
2235 case REG_FRAME_RELATED_EXPR
:
2236 pat
= XEXP (note
, 0);
2239 case REG_CFA_DEF_CFA
:
2240 dwarf2out_frame_debug_def_cfa (XEXP (note
, 0));
2244 case REG_CFA_ADJUST_CFA
:
2249 if (GET_CODE (n
) == PARALLEL
)
2250 n
= XVECEXP (n
, 0, 0);
2252 dwarf2out_frame_debug_adjust_cfa (n
);
2256 case REG_CFA_OFFSET
:
2259 n
= single_set (insn
);
2260 dwarf2out_frame_debug_cfa_offset (n
);
2264 case REG_CFA_REGISTER
:
2269 if (GET_CODE (n
) == PARALLEL
)
2270 n
= XVECEXP (n
, 0, 0);
2272 dwarf2out_frame_debug_cfa_register (n
);
2276 case REG_CFA_EXPRESSION
:
2277 case REG_CFA_VAL_EXPRESSION
:
2280 n
= single_set (insn
);
2282 if (REG_NOTE_KIND (note
) == REG_CFA_EXPRESSION
)
2283 dwarf2out_frame_debug_cfa_expression (n
);
2285 dwarf2out_frame_debug_cfa_val_expression (n
);
2290 case REG_CFA_RESTORE
:
2295 if (GET_CODE (n
) == PARALLEL
)
2296 n
= XVECEXP (n
, 0, 0);
2299 dwarf2out_frame_debug_cfa_restore (n
);
2303 case REG_CFA_SET_VDRAP
:
2307 dw_fde_ref fde
= cfun
->fde
;
2310 gcc_assert (fde
->vdrap_reg
== INVALID_REGNUM
);
2312 fde
->vdrap_reg
= dwf_regno (n
);
2318 case REG_CFA_TOGGLE_RA_MANGLE
:
2319 dwarf2out_frame_debug_cfa_toggle_ra_mangle ();
2323 case REG_CFA_WINDOW_SAVE
:
2324 dwarf2out_frame_debug_cfa_window_save ();
2328 case REG_CFA_FLUSH_QUEUE
:
2329 /* The actual flush happens elsewhere. */
2339 pat
= PATTERN (insn
);
2341 dwarf2out_frame_debug_expr (pat
);
2343 /* Check again. A parallel can save and update the same register.
2344 We could probably check just once, here, but this is safer than
2345 removing the check at the start of the function. */
2346 if (clobbers_queued_reg_save (pat
))
2347 dwarf2out_flush_queued_reg_saves ();
2351 /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */
2354 change_cfi_row (dw_cfi_row
*old_row
, dw_cfi_row
*new_row
)
2356 size_t i
, n_old
, n_new
, n_max
;
2359 if (new_row
->cfa_cfi
&& !cfi_equal_p (old_row
->cfa_cfi
, new_row
->cfa_cfi
))
2360 add_cfi (new_row
->cfa_cfi
);
2363 cfi
= def_cfa_0 (&old_row
->cfa
, &new_row
->cfa
);
2368 n_old
= vec_safe_length (old_row
->reg_save
);
2369 n_new
= vec_safe_length (new_row
->reg_save
);
2370 n_max
= MAX (n_old
, n_new
);
2372 for (i
= 0; i
< n_max
; ++i
)
2374 dw_cfi_ref r_old
= NULL
, r_new
= NULL
;
2377 r_old
= (*old_row
->reg_save
)[i
];
2379 r_new
= (*new_row
->reg_save
)[i
];
2383 else if (r_new
== NULL
)
2384 add_cfi_restore (i
);
2385 else if (!cfi_equal_p (r_old
, r_new
))
2389 if (!old_row
->window_save
&& new_row
->window_save
)
2391 dw_cfi_ref cfi
= new_cfi ();
2393 gcc_assert (!old_row
->ra_mangled
&& !new_row
->ra_mangled
);
2394 cfi
->dw_cfi_opc
= DW_CFA_GNU_window_save
;
2398 if (old_row
->ra_mangled
!= new_row
->ra_mangled
)
2400 dw_cfi_ref cfi
= new_cfi ();
2402 gcc_assert (!old_row
->window_save
&& !new_row
->window_save
);
2403 /* DW_CFA_GNU_window_save is reused for toggling RA mangle state. */
2404 cfi
->dw_cfi_opc
= DW_CFA_GNU_window_save
;
2409 /* Examine CFI and return true if a cfi label and set_loc is needed
2410 beforehand. Even when generating CFI assembler instructions, we
2411 still have to add the cfi to the list so that lookup_cfa_1 works
2412 later on. When -g2 and above we even need to force emitting of
2413 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list
2414 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa
2415 and so don't use convert_cfa_to_fb_loc_list. */
2418 cfi_label_required_p (dw_cfi_ref cfi
)
2420 if (!dwarf2out_do_cfi_asm ())
2423 if (dwarf_version
== 2
2424 && debug_info_level
> DINFO_LEVEL_TERSE
2425 && dwarf_debuginfo_p ())
2427 switch (cfi
->dw_cfi_opc
)
2429 case DW_CFA_def_cfa_offset
:
2430 case DW_CFA_def_cfa_offset_sf
:
2431 case DW_CFA_def_cfa_register
:
2432 case DW_CFA_def_cfa
:
2433 case DW_CFA_def_cfa_sf
:
2434 case DW_CFA_def_cfa_expression
:
2435 case DW_CFA_restore_state
:
2444 /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the
2445 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as
2448 add_cfis_to_fde (void)
2450 dw_fde_ref fde
= cfun
->fde
;
2451 rtx_insn
*insn
, *next
;
2453 for (insn
= get_insns (); insn
; insn
= next
)
2455 next
= NEXT_INSN (insn
);
2457 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
2458 fde
->dw_fde_switch_cfi_index
= vec_safe_length (fde
->dw_fde_cfi
);
2460 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_CFI
)
2462 bool required
= cfi_label_required_p (NOTE_CFI (insn
));
2464 if (NOTE_P (next
) && NOTE_KIND (next
) == NOTE_INSN_CFI
)
2466 required
|= cfi_label_required_p (NOTE_CFI (next
));
2467 next
= NEXT_INSN (next
);
2469 else if (active_insn_p (next
)
2470 || (NOTE_P (next
) && (NOTE_KIND (next
)
2471 == NOTE_INSN_SWITCH_TEXT_SECTIONS
)))
2474 next
= NEXT_INSN (next
);
2477 int num
= dwarf2out_cfi_label_num
;
2478 const char *label
= dwarf2out_cfi_label ();
2481 /* Set the location counter to the new label. */
2483 xcfi
->dw_cfi_opc
= DW_CFA_advance_loc4
;
2484 xcfi
->dw_cfi_oprnd1
.dw_cfi_addr
= label
;
2485 vec_safe_push (fde
->dw_fde_cfi
, xcfi
);
2487 rtx_note
*tmp
= emit_note_before (NOTE_INSN_CFI_LABEL
, insn
);
2488 NOTE_LABEL_NUMBER (tmp
) = num
;
2493 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_CFI
)
2494 vec_safe_push (fde
->dw_fde_cfi
, NOTE_CFI (insn
));
2495 insn
= NEXT_INSN (insn
);
2497 while (insn
!= next
);
2502 static void dump_cfi_row (FILE *f
, dw_cfi_row
*row
);
2504 /* If LABEL is the start of a trace, then initialize the state of that
2505 trace from CUR_TRACE and CUR_ROW. */
2508 maybe_record_trace_start (rtx_insn
*start
, rtx_insn
*origin
)
2512 ti
= get_trace_info (start
);
2513 gcc_assert (ti
!= NULL
);
2517 fprintf (dump_file
, " saw edge from trace %u to %u (via %s %d)\n",
2518 cur_trace
->id
, ti
->id
,
2519 (origin
? rtx_name
[(int) GET_CODE (origin
)] : "fallthru"),
2520 (origin
? INSN_UID (origin
) : 0));
2523 poly_int64 args_size
= cur_trace
->end_true_args_size
;
2524 if (ti
->beg_row
== NULL
)
2526 /* This is the first time we've encountered this trace. Propagate
2527 state across the edge and push the trace onto the work list. */
2528 ti
->beg_row
= copy_cfi_row (cur_row
);
2529 ti
->beg_true_args_size
= args_size
;
2531 ti
->cfa_store
= cur_trace
->cfa_store
;
2532 ti
->cfa_temp
= cur_trace
->cfa_temp
;
2533 ti
->regs_saved_in_regs
= cur_trace
->regs_saved_in_regs
.copy ();
2535 trace_work_list
.safe_push (ti
);
2538 fprintf (dump_file
, "\tpush trace %u to worklist\n", ti
->id
);
2543 /* We ought to have the same state incoming to a given trace no
2544 matter how we arrive at the trace. Anything else means we've
2545 got some kind of optimization error. */
2547 if (!cfi_row_equal_p (cur_row
, ti
->beg_row
))
2551 fprintf (dump_file
, "Inconsistent CFI state!\n");
2552 fprintf (dump_file
, "SHOULD have:\n");
2553 dump_cfi_row (dump_file
, ti
->beg_row
);
2554 fprintf (dump_file
, "DO have:\n");
2555 dump_cfi_row (dump_file
, cur_row
);
2562 /* The args_size is allowed to conflict if it isn't actually used. */
2563 if (maybe_ne (ti
->beg_true_args_size
, args_size
))
2564 ti
->args_size_undefined
= true;
2568 /* Similarly, but handle the args_size and CFA reset across EH
2569 and non-local goto edges. */
2572 maybe_record_trace_start_abnormal (rtx_insn
*start
, rtx_insn
*origin
)
2574 poly_int64 save_args_size
, delta
;
2575 dw_cfa_location save_cfa
;
2577 save_args_size
= cur_trace
->end_true_args_size
;
2578 if (known_eq (save_args_size
, 0))
2580 maybe_record_trace_start (start
, origin
);
2584 delta
= -save_args_size
;
2585 cur_trace
->end_true_args_size
= 0;
2587 save_cfa
= cur_row
->cfa
;
2588 if (cur_row
->cfa
.reg
== dw_stack_pointer_regnum
)
2590 /* Convert a change in args_size (always a positive in the
2591 direction of stack growth) to a change in stack pointer. */
2592 if (!STACK_GROWS_DOWNWARD
)
2595 cur_row
->cfa
.offset
+= delta
;
2598 maybe_record_trace_start (start
, origin
);
2600 cur_trace
->end_true_args_size
= save_args_size
;
2601 cur_row
->cfa
= save_cfa
;
2604 /* Propagate CUR_TRACE state to the destinations implied by INSN. */
2605 /* ??? Sadly, this is in large part a duplicate of make_edges. */
2608 create_trace_edges (rtx_insn
*insn
)
2615 rtx_jump_table_data
*table
;
2617 if (find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
2620 if (tablejump_p (insn
, NULL
, &table
))
2622 rtvec vec
= table
->get_labels ();
2624 n
= GET_NUM_ELEM (vec
);
2625 for (i
= 0; i
< n
; ++i
)
2627 rtx_insn
*lab
= as_a
<rtx_insn
*> (XEXP (RTVEC_ELT (vec
, i
), 0));
2628 maybe_record_trace_start (lab
, insn
);
2631 /* Handle casesi dispatch insns. */
2632 if ((tmp
= tablejump_casesi_pattern (insn
)) != NULL_RTX
)
2634 rtx_insn
* lab
= label_ref_label (XEXP (SET_SRC (tmp
), 2));
2635 maybe_record_trace_start (lab
, insn
);
2638 else if (computed_jump_p (insn
))
2642 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, temp
)
2643 maybe_record_trace_start (temp
, insn
);
2645 else if (returnjump_p (insn
))
2647 else if ((tmp
= extract_asm_operands (PATTERN (insn
))) != NULL
)
2649 n
= ASM_OPERANDS_LABEL_LENGTH (tmp
);
2650 for (i
= 0; i
< n
; ++i
)
2653 as_a
<rtx_insn
*> (XEXP (ASM_OPERANDS_LABEL (tmp
, i
), 0));
2654 maybe_record_trace_start (lab
, insn
);
2659 rtx_insn
*lab
= JUMP_LABEL_AS_INSN (insn
);
2660 gcc_assert (lab
!= NULL
);
2661 maybe_record_trace_start (lab
, insn
);
2664 else if (CALL_P (insn
))
2666 /* Sibling calls don't have edges inside this function. */
2667 if (SIBLING_CALL_P (insn
))
2670 /* Process non-local goto edges. */
2671 if (can_nonlocal_goto (insn
))
2672 for (rtx_insn_list
*lab
= nonlocal_goto_handler_labels
;
2675 maybe_record_trace_start_abnormal (lab
->insn (), insn
);
2677 else if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
2679 int i
, n
= seq
->len ();
2680 for (i
= 0; i
< n
; ++i
)
2681 create_trace_edges (seq
->insn (i
));
2685 /* Process EH edges. */
2686 if (CALL_P (insn
) || cfun
->can_throw_non_call_exceptions
)
2688 eh_landing_pad lp
= get_eh_landing_pad_from_rtx (insn
);
2690 maybe_record_trace_start_abnormal (lp
->landing_pad
, insn
);
2694 /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */
2697 scan_insn_after (rtx_insn
*insn
)
2699 if (RTX_FRAME_RELATED_P (insn
))
2700 dwarf2out_frame_debug (insn
);
2701 notice_args_size (insn
);
2704 /* Scan the trace beginning at INSN and create the CFI notes for the
2705 instructions therein. */
2708 scan_trace (dw_trace_info
*trace
, bool entry
)
2710 rtx_insn
*prev
, *insn
= trace
->head
;
2711 dw_cfa_location this_cfa
;
2714 fprintf (dump_file
, "Processing trace %u : start at %s %d\n",
2715 trace
->id
, rtx_name
[(int) GET_CODE (insn
)],
2718 trace
->end_row
= copy_cfi_row (trace
->beg_row
);
2719 trace
->end_true_args_size
= trace
->beg_true_args_size
;
2722 cur_row
= trace
->end_row
;
2724 this_cfa
= cur_row
->cfa
;
2725 cur_cfa
= &this_cfa
;
2727 /* If the current function starts with a non-standard incoming frame
2728 sp offset, emit a note before the first instruction. */
2730 && DEFAULT_INCOMING_FRAME_SP_OFFSET
!= INCOMING_FRAME_SP_OFFSET
)
2732 add_cfi_insn
= insn
;
2733 gcc_assert (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED
);
2734 this_cfa
.offset
= INCOMING_FRAME_SP_OFFSET
;
2735 def_cfa_1 (&this_cfa
);
2738 for (prev
= insn
, insn
= NEXT_INSN (insn
);
2740 prev
= insn
, insn
= NEXT_INSN (insn
))
2744 /* Do everything that happens "before" the insn. */
2745 add_cfi_insn
= prev
;
2747 /* Notice the end of a trace. */
2748 if (BARRIER_P (insn
))
2750 /* Don't bother saving the unneeded queued registers at all. */
2751 queued_reg_saves
.truncate (0);
2754 if (save_point_p (insn
))
2756 /* Propagate across fallthru edges. */
2757 dwarf2out_flush_queued_reg_saves ();
2758 maybe_record_trace_start (insn
, NULL
);
2762 if (DEBUG_INSN_P (insn
) || !inside_basic_block_p (insn
))
2765 /* Handle all changes to the row state. Sequences require special
2766 handling for the positioning of the notes. */
2767 if (rtx_sequence
*pat
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
2770 int i
, n
= pat
->len ();
2772 control
= pat
->insn (0);
2773 if (can_throw_internal (control
))
2774 notice_eh_throw (control
);
2775 dwarf2out_flush_queued_reg_saves ();
2777 if (JUMP_P (control
) && INSN_ANNULLED_BRANCH_P (control
))
2779 /* ??? Hopefully multiple delay slots are not annulled. */
2780 gcc_assert (n
== 2);
2781 gcc_assert (!RTX_FRAME_RELATED_P (control
));
2782 gcc_assert (!find_reg_note (control
, REG_ARGS_SIZE
, NULL
));
2784 elt
= pat
->insn (1);
2786 if (INSN_FROM_TARGET_P (elt
))
2788 cfi_vec save_row_reg_save
;
2790 /* If ELT is an instruction from target of an annulled
2791 branch, the effects are for the target only and so
2792 the args_size and CFA along the current path
2793 shouldn't change. */
2794 add_cfi_insn
= NULL
;
2795 poly_int64 restore_args_size
= cur_trace
->end_true_args_size
;
2796 cur_cfa
= &cur_row
->cfa
;
2797 save_row_reg_save
= vec_safe_copy (cur_row
->reg_save
);
2799 scan_insn_after (elt
);
2801 /* ??? Should we instead save the entire row state? */
2802 gcc_assert (!queued_reg_saves
.length ());
2804 create_trace_edges (control
);
2806 cur_trace
->end_true_args_size
= restore_args_size
;
2807 cur_row
->cfa
= this_cfa
;
2808 cur_row
->reg_save
= save_row_reg_save
;
2809 cur_cfa
= &this_cfa
;
2813 /* If ELT is a annulled branch-taken instruction (i.e.
2814 executed only when branch is not taken), the args_size
2815 and CFA should not change through the jump. */
2816 create_trace_edges (control
);
2818 /* Update and continue with the trace. */
2819 add_cfi_insn
= insn
;
2820 scan_insn_after (elt
);
2821 def_cfa_1 (&this_cfa
);
2826 /* The insns in the delay slot should all be considered to happen
2827 "before" a call insn. Consider a call with a stack pointer
2828 adjustment in the delay slot. The backtrace from the callee
2829 should include the sp adjustment. Unfortunately, that leaves
2830 us with an unavoidable unwinding error exactly at the call insn
2831 itself. For jump insns we'd prefer to avoid this error by
2832 placing the notes after the sequence. */
2833 if (JUMP_P (control
))
2834 add_cfi_insn
= insn
;
2836 for (i
= 1; i
< n
; ++i
)
2838 elt
= pat
->insn (i
);
2839 scan_insn_after (elt
);
2842 /* Make sure any register saves are visible at the jump target. */
2843 dwarf2out_flush_queued_reg_saves ();
2844 any_cfis_emitted
= false;
2846 /* However, if there is some adjustment on the call itself, e.g.
2847 a call_pop, that action should be considered to happen after
2848 the call returns. */
2849 add_cfi_insn
= insn
;
2850 scan_insn_after (control
);
2854 /* Flush data before calls and jumps, and of course if necessary. */
2855 if (can_throw_internal (insn
))
2857 notice_eh_throw (insn
);
2858 dwarf2out_flush_queued_reg_saves ();
2860 else if (!NONJUMP_INSN_P (insn
)
2861 || clobbers_queued_reg_save (insn
)
2862 || find_reg_note (insn
, REG_CFA_FLUSH_QUEUE
, NULL
))
2863 dwarf2out_flush_queued_reg_saves ();
2864 any_cfis_emitted
= false;
2866 add_cfi_insn
= insn
;
2867 scan_insn_after (insn
);
2871 /* Between frame-related-p and args_size we might have otherwise
2872 emitted two cfa adjustments. Do it now. */
2873 def_cfa_1 (&this_cfa
);
2875 /* Minimize the number of advances by emitting the entire queue
2876 once anything is emitted. */
2877 if (any_cfis_emitted
2878 || find_reg_note (insn
, REG_CFA_FLUSH_QUEUE
, NULL
))
2879 dwarf2out_flush_queued_reg_saves ();
2881 /* Note that a test for control_flow_insn_p does exactly the
2882 same tests as are done to actually create the edges. So
2883 always call the routine and let it not create edges for
2884 non-control-flow insns. */
2885 create_trace_edges (control
);
2888 gcc_assert (!cfun
->fde
|| !cfun
->fde
->rule18
);
2889 add_cfi_insn
= NULL
;
2895 /* Scan the function and create the initial set of CFI notes. */
2898 create_cfi_notes (void)
2902 gcc_checking_assert (!queued_reg_saves
.exists ());
2903 gcc_checking_assert (!trace_work_list
.exists ());
2905 /* Always begin at the entry trace. */
2906 ti
= &trace_info
[0];
2907 scan_trace (ti
, true);
2909 while (!trace_work_list
.is_empty ())
2911 ti
= trace_work_list
.pop ();
2912 scan_trace (ti
, false);
2915 queued_reg_saves
.release ();
2916 trace_work_list
.release ();
2919 /* Return the insn before the first NOTE_INSN_CFI after START. */
2922 before_next_cfi_note (rtx_insn
*start
)
2924 rtx_insn
*prev
= start
;
2927 if (NOTE_P (start
) && NOTE_KIND (start
) == NOTE_INSN_CFI
)
2930 start
= NEXT_INSN (start
);
2935 /* Insert CFI notes between traces to properly change state between them. */
2938 connect_traces (void)
2941 dw_trace_info
*prev_ti
, *ti
;
2943 /* ??? Ideally, we should have both queued and processed every trace.
2944 However the current representation of constant pools on various targets
2945 is indistinguishable from unreachable code. Assume for the moment that
2946 we can simply skip over such traces. */
2947 /* ??? Consider creating a DATA_INSN rtx code to indicate that
2948 these are not "real" instructions, and should not be considered.
2949 This could be generically useful for tablejump data as well. */
2950 /* Remove all unprocessed traces from the list. */
2952 VEC_ORDERED_REMOVE_IF_FROM_TO (trace_info
, ix
, ix2
, ti
, 1,
2953 trace_info
.length (), ti
->beg_row
== NULL
);
2954 FOR_EACH_VEC_ELT (trace_info
, ix
, ti
)
2955 gcc_assert (ti
->end_row
!= NULL
);
2957 /* Work from the end back to the beginning. This lets us easily insert
2958 remember/restore_state notes in the correct order wrt other notes. */
2959 n
= trace_info
.length ();
2960 prev_ti
= &trace_info
[n
- 1];
2961 for (i
= n
- 1; i
> 0; --i
)
2963 dw_cfi_row
*old_row
;
2966 prev_ti
= &trace_info
[i
- 1];
2968 add_cfi_insn
= ti
->head
;
2970 /* In dwarf2out_switch_text_section, we'll begin a new FDE
2971 for the portion of the function in the alternate text
2972 section. The row state at the very beginning of that
2973 new FDE will be exactly the row state from the CIE. */
2974 if (ti
->switch_sections
)
2975 old_row
= cie_cfi_row
;
2978 old_row
= prev_ti
->end_row
;
2979 /* If there's no change from the previous end state, fine. */
2980 if (cfi_row_equal_p (old_row
, ti
->beg_row
))
2982 /* Otherwise check for the common case of sharing state with
2983 the beginning of an epilogue, but not the end. Insert
2984 remember/restore opcodes in that case. */
2985 else if (cfi_row_equal_p (prev_ti
->beg_row
, ti
->beg_row
))
2989 /* Note that if we blindly insert the remember at the
2990 start of the trace, we can wind up increasing the
2991 size of the unwind info due to extra advance opcodes.
2992 Instead, put the remember immediately before the next
2993 state change. We know there must be one, because the
2994 state at the beginning and head of the trace differ. */
2995 add_cfi_insn
= before_next_cfi_note (prev_ti
->head
);
2997 cfi
->dw_cfi_opc
= DW_CFA_remember_state
;
3000 add_cfi_insn
= ti
->head
;
3002 cfi
->dw_cfi_opc
= DW_CFA_restore_state
;
3005 /* If the target unwinder does not save the CFA as part of the
3006 register state, we need to restore it separately. */
3007 if (targetm
.asm_out
.should_restore_cfa_state ()
3008 && (cfi
= def_cfa_0 (&old_row
->cfa
, &ti
->beg_row
->cfa
)))
3011 old_row
= prev_ti
->beg_row
;
3013 /* Otherwise, we'll simply change state from the previous end. */
3016 change_cfi_row (old_row
, ti
->beg_row
);
3018 if (dump_file
&& add_cfi_insn
!= ti
->head
)
3022 fprintf (dump_file
, "Fixup between trace %u and %u:\n",
3023 prev_ti
->id
, ti
->id
);
3028 note
= NEXT_INSN (note
);
3029 gcc_assert (NOTE_P (note
) && NOTE_KIND (note
) == NOTE_INSN_CFI
);
3030 output_cfi_directive (dump_file
, NOTE_CFI (note
));
3032 while (note
!= add_cfi_insn
);
3036 /* Connect args_size between traces that have can_throw_internal insns. */
3037 if (cfun
->eh
->lp_array
)
3039 poly_int64 prev_args_size
= 0;
3041 for (i
= 0; i
< n
; ++i
)
3043 ti
= &trace_info
[i
];
3045 if (ti
->switch_sections
)
3048 if (ti
->eh_head
== NULL
)
3051 /* We require either the incoming args_size values to match or the
3052 presence of an insn setting it before the first EH insn. */
3053 gcc_assert (!ti
->args_size_undefined
|| ti
->args_size_defined_for_eh
);
3055 /* In the latter case, we force the creation of a CFI note. */
3056 if (ti
->args_size_undefined
3057 || maybe_ne (ti
->beg_delay_args_size
, prev_args_size
))
3059 /* ??? Search back to previous CFI note. */
3060 add_cfi_insn
= PREV_INSN (ti
->eh_head
);
3061 add_cfi_args_size (ti
->beg_delay_args_size
);
3064 prev_args_size
= ti
->end_delay_args_size
;
3069 /* Set up the pseudo-cfg of instruction traces, as described at the
3070 block comment at the top of the file. */
3073 create_pseudo_cfg (void)
3075 bool saw_barrier
, switch_sections
;
3080 /* The first trace begins at the start of the function,
3081 and begins with the CIE row state. */
3082 trace_info
.create (16);
3083 memset (&ti
, 0, sizeof (ti
));
3084 ti
.head
= get_insns ();
3085 ti
.beg_row
= cie_cfi_row
;
3086 ti
.cfa_store
= cie_cfi_row
->cfa
;
3087 ti
.cfa_temp
.reg
.set_by_dwreg (INVALID_REGNUM
);
3088 trace_info
.quick_push (ti
);
3090 if (cie_return_save
)
3091 ti
.regs_saved_in_regs
.safe_push (*cie_return_save
);
3093 /* Walk all the insns, collecting start of trace locations. */
3094 saw_barrier
= false;
3095 switch_sections
= false;
3096 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3098 if (BARRIER_P (insn
))
3100 else if (NOTE_P (insn
)
3101 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
3103 /* We should have just seen a barrier. */
3104 gcc_assert (saw_barrier
);
3105 switch_sections
= true;
3107 /* Watch out for save_point notes between basic blocks.
3108 In particular, a note after a barrier. Do not record these,
3109 delaying trace creation until the label. */
3110 else if (save_point_p (insn
)
3111 && (LABEL_P (insn
) || !saw_barrier
))
3113 memset (&ti
, 0, sizeof (ti
));
3115 ti
.switch_sections
= switch_sections
;
3116 ti
.id
= trace_info
.length ();
3117 trace_info
.safe_push (ti
);
3119 saw_barrier
= false;
3120 switch_sections
= false;
3124 /* Create the trace index after we've finished building trace_info,
3125 avoiding stale pointer problems due to reallocation. */
3127 = new hash_table
<trace_info_hasher
> (trace_info
.length ());
3129 FOR_EACH_VEC_ELT (trace_info
, i
, tp
)
3131 dw_trace_info
**slot
;
3134 fprintf (dump_file
, "Creating trace %u : start at %s %d%s\n", tp
->id
,
3135 rtx_name
[(int) GET_CODE (tp
->head
)], INSN_UID (tp
->head
),
3136 tp
->switch_sections
? " (section switch)" : "");
3138 slot
= trace_index
->find_slot_with_hash (tp
, INSN_UID (tp
->head
), INSERT
);
3139 gcc_assert (*slot
== NULL
);
3144 /* Record the initial position of the return address. RTL is
3145 INCOMING_RETURN_ADDR_RTX. */
3148 initial_return_save (rtx rtl
)
3151 reg
.set_by_dwreg (INVALID_REGNUM
);
3152 poly_int64 offset
= 0;
3154 switch (GET_CODE (rtl
))
3157 /* RA is in a register. */
3158 reg
= dwf_cfa_reg (rtl
);
3162 /* RA is on the stack. */
3163 rtl
= XEXP (rtl
, 0);
3164 switch (GET_CODE (rtl
))
3167 gcc_assert (REGNO (rtl
) == STACK_POINTER_REGNUM
);
3172 gcc_assert (REGNO (XEXP (rtl
, 0)) == STACK_POINTER_REGNUM
);
3173 offset
= rtx_to_poly_int64 (XEXP (rtl
, 1));
3177 gcc_assert (REGNO (XEXP (rtl
, 0)) == STACK_POINTER_REGNUM
);
3178 offset
= -rtx_to_poly_int64 (XEXP (rtl
, 1));
3188 /* The return address is at some offset from any value we can
3189 actually load. For instance, on the SPARC it is in %i7+8. Just
3190 ignore the offset for now; it doesn't matter for unwinding frames. */
3191 gcc_assert (CONST_INT_P (XEXP (rtl
, 1)));
3192 initial_return_save (XEXP (rtl
, 0));
3199 if (reg
.reg
!= DWARF_FRAME_RETURN_COLUMN
)
3201 if (reg
.reg
!= INVALID_REGNUM
)
3202 record_reg_saved_in_reg (rtl
, pc_rtx
);
3203 reg_save (DWARF_FRAME_RETURN_COLUMN
, reg
, offset
- cur_row
->cfa
.offset
);
3208 create_cie_data (void)
3210 dw_cfa_location loc
;
3211 dw_trace_info cie_trace
;
3213 dw_stack_pointer_regnum
= dwf_cfa_reg (gen_rtx_REG (Pmode
,
3214 STACK_POINTER_REGNUM
));
3216 memset (&cie_trace
, 0, sizeof (cie_trace
));
3217 cur_trace
= &cie_trace
;
3219 add_cfi_vec
= &cie_cfi_vec
;
3220 cie_cfi_row
= cur_row
= new_cfi_row ();
3222 /* On entry, the Canonical Frame Address is at SP. */
3223 memset (&loc
, 0, sizeof (loc
));
3224 loc
.reg
= dw_stack_pointer_regnum
;
3225 /* create_cie_data is called just once per TU, and when using .cfi_startproc
3226 is even done by the assembler rather than the compiler. If the target
3227 has different incoming frame sp offsets depending on what kind of
3228 function it is, use a single constant offset for the target and
3229 if needed, adjust before the first instruction in insn stream. */
3230 loc
.offset
= DEFAULT_INCOMING_FRAME_SP_OFFSET
;
3233 if (targetm
.debug_unwind_info () == UI_DWARF2
3234 || targetm_common
.except_unwind_info (&global_options
) == UI_DWARF2
)
3236 initial_return_save (INCOMING_RETURN_ADDR_RTX
);
3238 /* For a few targets, we have the return address incoming into a
3239 register, but choose a different return column. This will result
3240 in a DW_CFA_register for the return, and an entry in
3241 regs_saved_in_regs to match. If the target later stores that
3242 return address register to the stack, we want to be able to emit
3243 the DW_CFA_offset against the return column, not the intermediate
3244 save register. Save the contents of regs_saved_in_regs so that
3245 we can re-initialize it at the start of each function. */
3246 switch (cie_trace
.regs_saved_in_regs
.length ())
3251 cie_return_save
= ggc_alloc
<reg_saved_in_data
> ();
3252 *cie_return_save
= cie_trace
.regs_saved_in_regs
[0];
3253 cie_trace
.regs_saved_in_regs
.release ();
3265 /* Annotate the function with NOTE_INSN_CFI notes to record the CFI
3266 state at each location within the function. These notes will be
3267 emitted during pass_final. */
3270 execute_dwarf2_frame (void)
3272 /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */
3273 dw_frame_pointer_regnum
3274 = dwf_cfa_reg (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
));
3276 /* The first time we're called, compute the incoming frame state. */
3277 if (cie_cfi_vec
== NULL
)
3280 dwarf2out_alloc_current_fde ();
3282 create_pseudo_cfg ();
3285 create_cfi_notes ();
3289 /* Free all the data we allocated. */
3294 FOR_EACH_VEC_ELT (trace_info
, i
, ti
)
3295 ti
->regs_saved_in_regs
.release ();
3297 trace_info
.release ();
3305 /* Convert a DWARF call frame info. operation to its string name */
3308 dwarf_cfi_name (unsigned int cfi_opc
)
3310 const char *name
= get_DW_CFA_name (cfi_opc
);
3315 return "DW_CFA_<unknown>";
3318 /* This routine will generate the correct assembly data for a location
3319 description based on a cfi entry with a complex address. */
3322 output_cfa_loc (dw_cfi_ref cfi
, int for_eh
)
3324 dw_loc_descr_ref loc
;
3327 if (cfi
->dw_cfi_opc
== DW_CFA_expression
3328 || cfi
->dw_cfi_opc
== DW_CFA_val_expression
)
3331 DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3332 dw2_asm_output_data (1, r
, NULL
);
3333 loc
= cfi
->dw_cfi_oprnd2
.dw_cfi_loc
;
3336 loc
= cfi
->dw_cfi_oprnd1
.dw_cfi_loc
;
3338 /* Output the size of the block. */
3339 size
= size_of_locs (loc
);
3340 dw2_asm_output_data_uleb128 (size
, NULL
);
3342 /* Now output the operations themselves. */
3343 output_loc_sequence (loc
, for_eh
);
3346 /* Similar, but used for .cfi_escape. */
3349 output_cfa_loc_raw (dw_cfi_ref cfi
)
3351 dw_loc_descr_ref loc
;
3354 if (cfi
->dw_cfi_opc
== DW_CFA_expression
3355 || cfi
->dw_cfi_opc
== DW_CFA_val_expression
)
3358 DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3359 fprintf (asm_out_file
, "%#x,", r
);
3360 loc
= cfi
->dw_cfi_oprnd2
.dw_cfi_loc
;
3363 loc
= cfi
->dw_cfi_oprnd1
.dw_cfi_loc
;
3365 /* Output the size of the block. */
3366 size
= size_of_locs (loc
);
3367 dw2_asm_output_data_uleb128_raw (size
);
3368 fputc (',', asm_out_file
);
3370 /* Now output the operations themselves. */
3371 output_loc_sequence_raw (loc
);
3374 /* Output a Call Frame Information opcode and its operand(s). */
3377 output_cfi (dw_cfi_ref cfi
, dw_fde_ref fde
, int for_eh
)
3382 if (cfi
->dw_cfi_opc
== DW_CFA_advance_loc
)
3383 dw2_asm_output_data (1, (cfi
->dw_cfi_opc
3384 | (cfi
->dw_cfi_oprnd1
.dw_cfi_offset
& 0x3f)),
3385 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX
,
3386 ((unsigned HOST_WIDE_INT
)
3387 cfi
->dw_cfi_oprnd1
.dw_cfi_offset
));
3388 else if (cfi
->dw_cfi_opc
== DW_CFA_offset
)
3390 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3391 dw2_asm_output_data (1, (cfi
->dw_cfi_opc
| (r
& 0x3f)),
3392 "DW_CFA_offset, column %#lx", r
);
3393 off
= div_data_align (cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3394 dw2_asm_output_data_uleb128 (off
, NULL
);
3396 else if (cfi
->dw_cfi_opc
== DW_CFA_restore
)
3398 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3399 dw2_asm_output_data (1, (cfi
->dw_cfi_opc
| (r
& 0x3f)),
3400 "DW_CFA_restore, column %#lx", r
);
3404 dw2_asm_output_data (1, cfi
->dw_cfi_opc
,
3405 "%s", dwarf_cfi_name (cfi
->dw_cfi_opc
));
3407 switch (cfi
->dw_cfi_opc
)
3409 case DW_CFA_set_loc
:
3411 dw2_asm_output_encoded_addr_rtx (
3412 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0),
3413 gen_rtx_SYMBOL_REF (Pmode
, cfi
->dw_cfi_oprnd1
.dw_cfi_addr
),
3416 dw2_asm_output_addr (DWARF2_ADDR_SIZE
,
3417 cfi
->dw_cfi_oprnd1
.dw_cfi_addr
, NULL
);
3418 fde
->dw_fde_current_label
= cfi
->dw_cfi_oprnd1
.dw_cfi_addr
;
3421 case DW_CFA_advance_loc1
:
3422 dw2_asm_output_delta (1, cfi
->dw_cfi_oprnd1
.dw_cfi_addr
,
3423 fde
->dw_fde_current_label
, NULL
);
3424 fde
->dw_fde_current_label
= cfi
->dw_cfi_oprnd1
.dw_cfi_addr
;
3427 case DW_CFA_advance_loc2
:
3428 dw2_asm_output_delta (2, cfi
->dw_cfi_oprnd1
.dw_cfi_addr
,
3429 fde
->dw_fde_current_label
, NULL
);
3430 fde
->dw_fde_current_label
= cfi
->dw_cfi_oprnd1
.dw_cfi_addr
;
3433 case DW_CFA_advance_loc4
:
3434 dw2_asm_output_delta (4, cfi
->dw_cfi_oprnd1
.dw_cfi_addr
,
3435 fde
->dw_fde_current_label
, NULL
);
3436 fde
->dw_fde_current_label
= cfi
->dw_cfi_oprnd1
.dw_cfi_addr
;
3439 case DW_CFA_MIPS_advance_loc8
:
3440 dw2_asm_output_delta (8, cfi
->dw_cfi_oprnd1
.dw_cfi_addr
,
3441 fde
->dw_fde_current_label
, NULL
);
3442 fde
->dw_fde_current_label
= cfi
->dw_cfi_oprnd1
.dw_cfi_addr
;
3445 case DW_CFA_offset_extended
:
3446 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3447 dw2_asm_output_data_uleb128 (r
, NULL
);
3448 off
= div_data_align (cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3449 dw2_asm_output_data_uleb128 (off
, NULL
);
3452 case DW_CFA_def_cfa
:
3453 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3454 dw2_asm_output_data_uleb128 (r
, NULL
);
3455 dw2_asm_output_data_uleb128 (cfi
->dw_cfi_oprnd2
.dw_cfi_offset
, NULL
);
3458 case DW_CFA_offset_extended_sf
:
3459 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3460 dw2_asm_output_data_uleb128 (r
, NULL
);
3461 off
= div_data_align (cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3462 dw2_asm_output_data_sleb128 (off
, NULL
);
3465 case DW_CFA_def_cfa_sf
:
3466 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3467 dw2_asm_output_data_uleb128 (r
, NULL
);
3468 off
= div_data_align (cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3469 dw2_asm_output_data_sleb128 (off
, NULL
);
3472 case DW_CFA_restore_extended
:
3473 case DW_CFA_undefined
:
3474 case DW_CFA_same_value
:
3475 case DW_CFA_def_cfa_register
:
3476 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3477 dw2_asm_output_data_uleb128 (r
, NULL
);
3480 case DW_CFA_register
:
3481 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, for_eh
);
3482 dw2_asm_output_data_uleb128 (r
, NULL
);
3483 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd2
.dw_cfi_reg_num
, for_eh
);
3484 dw2_asm_output_data_uleb128 (r
, NULL
);
3487 case DW_CFA_def_cfa_offset
:
3488 case DW_CFA_GNU_args_size
:
3489 dw2_asm_output_data_uleb128 (cfi
->dw_cfi_oprnd1
.dw_cfi_offset
, NULL
);
3492 case DW_CFA_def_cfa_offset_sf
:
3493 off
= div_data_align (cfi
->dw_cfi_oprnd1
.dw_cfi_offset
);
3494 dw2_asm_output_data_sleb128 (off
, NULL
);
3497 case DW_CFA_GNU_window_save
:
3500 case DW_CFA_def_cfa_expression
:
3501 case DW_CFA_expression
:
3502 case DW_CFA_val_expression
:
3503 output_cfa_loc (cfi
, for_eh
);
3506 case DW_CFA_GNU_negative_offset_extended
:
3507 /* Obsoleted by DW_CFA_offset_extended_sf. */
3516 /* Similar, but do it via assembler directives instead. */
3519 output_cfi_directive (FILE *f
, dw_cfi_ref cfi
)
3521 unsigned long r
, r2
;
3523 switch (cfi
->dw_cfi_opc
)
3525 case DW_CFA_advance_loc
:
3526 case DW_CFA_advance_loc1
:
3527 case DW_CFA_advance_loc2
:
3528 case DW_CFA_advance_loc4
:
3529 case DW_CFA_MIPS_advance_loc8
:
3530 case DW_CFA_set_loc
:
3531 /* Should only be created in a code path not followed when emitting
3532 via directives. The assembler is going to take care of this for
3533 us. But this routines is also used for debugging dumps, so
3535 gcc_assert (f
!= asm_out_file
);
3536 fprintf (f
, "\t.cfi_advance_loc\n");
3540 case DW_CFA_offset_extended
:
3541 case DW_CFA_offset_extended_sf
:
3542 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3543 fprintf (f
, "\t.cfi_offset %lu, " HOST_WIDE_INT_PRINT_DEC
"\n",
3544 r
, cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3547 case DW_CFA_restore
:
3548 case DW_CFA_restore_extended
:
3549 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3550 fprintf (f
, "\t.cfi_restore %lu\n", r
);
3553 case DW_CFA_undefined
:
3554 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3555 fprintf (f
, "\t.cfi_undefined %lu\n", r
);
3558 case DW_CFA_same_value
:
3559 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3560 fprintf (f
, "\t.cfi_same_value %lu\n", r
);
3563 case DW_CFA_def_cfa
:
3564 case DW_CFA_def_cfa_sf
:
3565 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3566 fprintf (f
, "\t.cfi_def_cfa %lu, " HOST_WIDE_INT_PRINT_DEC
"\n",
3567 r
, cfi
->dw_cfi_oprnd2
.dw_cfi_offset
);
3570 case DW_CFA_def_cfa_register
:
3571 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3572 fprintf (f
, "\t.cfi_def_cfa_register %lu\n", r
);
3575 case DW_CFA_register
:
3576 r
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd1
.dw_cfi_reg_num
, 1);
3577 r2
= DWARF2_FRAME_REG_OUT (cfi
->dw_cfi_oprnd2
.dw_cfi_reg_num
, 1);
3578 fprintf (f
, "\t.cfi_register %lu, %lu\n", r
, r2
);
3581 case DW_CFA_def_cfa_offset
:
3582 case DW_CFA_def_cfa_offset_sf
:
3583 fprintf (f
, "\t.cfi_def_cfa_offset "
3584 HOST_WIDE_INT_PRINT_DEC
"\n",
3585 cfi
->dw_cfi_oprnd1
.dw_cfi_offset
);
3588 case DW_CFA_remember_state
:
3589 fprintf (f
, "\t.cfi_remember_state\n");
3591 case DW_CFA_restore_state
:
3592 fprintf (f
, "\t.cfi_restore_state\n");
3595 case DW_CFA_GNU_args_size
:
3596 if (f
== asm_out_file
)
3598 fprintf (f
, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size
);
3599 dw2_asm_output_data_uleb128_raw (cfi
->dw_cfi_oprnd1
.dw_cfi_offset
);
3601 fprintf (f
, "\t%s args_size " HOST_WIDE_INT_PRINT_DEC
,
3602 ASM_COMMENT_START
, cfi
->dw_cfi_oprnd1
.dw_cfi_offset
);
3607 fprintf (f
, "\t.cfi_GNU_args_size " HOST_WIDE_INT_PRINT_DEC
"\n",
3608 cfi
->dw_cfi_oprnd1
.dw_cfi_offset
);
3612 case DW_CFA_GNU_window_save
:
3613 fprintf (f
, "\t.cfi_window_save\n");
3616 case DW_CFA_def_cfa_expression
:
3617 case DW_CFA_expression
:
3618 case DW_CFA_val_expression
:
3619 if (f
!= asm_out_file
)
3621 fprintf (f
, "\t.cfi_%scfa_%sexpression ...\n",
3622 cfi
->dw_cfi_opc
== DW_CFA_def_cfa_expression
? "def_" : "",
3623 cfi
->dw_cfi_opc
== DW_CFA_val_expression
? "val_" : "");
3626 fprintf (f
, "\t.cfi_escape %#x,", cfi
->dw_cfi_opc
);
3627 output_cfa_loc_raw (cfi
);
3637 dwarf2out_emit_cfi (dw_cfi_ref cfi
)
3639 if (dwarf2out_do_cfi_asm ())
3640 output_cfi_directive (asm_out_file
, cfi
);
3644 dump_cfi_row (FILE *f
, dw_cfi_row
*row
)
3652 dw_cfa_location dummy
;
3653 memset (&dummy
, 0, sizeof (dummy
));
3654 dummy
.reg
.set_by_dwreg (INVALID_REGNUM
);
3655 cfi
= def_cfa_0 (&dummy
, &row
->cfa
);
3657 output_cfi_directive (f
, cfi
);
3659 FOR_EACH_VEC_SAFE_ELT (row
->reg_save
, i
, cfi
)
3661 output_cfi_directive (f
, cfi
);
3664 void debug_cfi_row (dw_cfi_row
*row
);
3667 debug_cfi_row (dw_cfi_row
*row
)
3669 dump_cfi_row (stderr
, row
);
3673 /* Save the result of dwarf2out_do_frame across PCH.
3674 This variable is tri-state, with 0 unset, >0 true, <0 false. */
3675 static GTY(()) signed char saved_do_cfi_asm
= 0;
3677 /* Decide whether to emit EH frame unwind information for the current
3678 translation unit. */
3681 dwarf2out_do_eh_frame (void)
3684 (flag_unwind_tables
|| flag_exceptions
)
3685 && targetm_common
.except_unwind_info (&global_options
) == UI_DWARF2
;
3688 /* Decide whether we want to emit frame unwind information for the current
3689 translation unit. */
3692 dwarf2out_do_frame (void)
3694 /* We want to emit correct CFA location expressions or lists, so we
3695 have to return true if we're going to generate debug info, even if
3696 we're not going to output frame or unwind info. */
3697 if (dwarf_debuginfo_p () || dwarf_based_debuginfo_p ())
3700 if (saved_do_cfi_asm
> 0)
3703 if (targetm
.debug_unwind_info () == UI_DWARF2
)
3706 if (dwarf2out_do_eh_frame ())
3712 /* Decide whether to emit frame unwind via assembler directives. */
3715 dwarf2out_do_cfi_asm (void)
3719 if (saved_do_cfi_asm
!= 0)
3720 return saved_do_cfi_asm
> 0;
3722 /* Assume failure for a moment. */
3723 saved_do_cfi_asm
= -1;
3725 if (!flag_dwarf2_cfi_asm
|| !dwarf2out_do_frame ())
3727 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE
)
3730 /* Make sure the personality encoding is one the assembler can support.
3731 In particular, aligned addresses can't be handled. */
3732 enc
= ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1);
3733 if ((enc
& 0x70) != 0 && (enc
& 0x70) != DW_EH_PE_pcrel
)
3735 enc
= ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0);
3736 if ((enc
& 0x70) != 0 && (enc
& 0x70) != DW_EH_PE_pcrel
)
3739 /* If we can't get the assembler to emit only .debug_frame, and we don't need
3740 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */
3741 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE
&& !dwarf2out_do_eh_frame ())
3745 saved_do_cfi_asm
= 1;
3751 const pass_data pass_data_dwarf2_frame
=
3753 RTL_PASS
, /* type */
3754 "dwarf2", /* name */
3755 OPTGROUP_NONE
, /* optinfo_flags */
3756 TV_FINAL
, /* tv_id */
3757 0, /* properties_required */
3758 0, /* properties_provided */
3759 0, /* properties_destroyed */
3760 0, /* todo_flags_start */
3761 0, /* todo_flags_finish */
3764 class pass_dwarf2_frame
: public rtl_opt_pass
3767 pass_dwarf2_frame (gcc::context
*ctxt
)
3768 : rtl_opt_pass (pass_data_dwarf2_frame
, ctxt
)
3771 /* opt_pass methods: */
3772 virtual bool gate (function
*);
3773 virtual unsigned int execute (function
*) { return execute_dwarf2_frame (); }
3775 }; // class pass_dwarf2_frame
3778 pass_dwarf2_frame::gate (function
*)
3780 /* Targets which still implement the prologue in assembler text
3781 cannot use the generic dwarf2 unwinding. */
3782 if (!targetm
.have_prologue ())
3785 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit
3786 from the optimized shrink-wrapping annotations that we will compute.
3787 For now, only produce the CFI notes for dwarf2. */
3788 return dwarf2out_do_frame ();
3794 make_pass_dwarf2_frame (gcc::context
*ctxt
)
3796 return new pass_dwarf2_frame (ctxt
);
3799 #include "gt-dwarf2cfi.h"