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update copyrights in config dir.
[official-gcc.git] / gcc / config / arm / arm.h
blob33f5932a8f4ad57e4325f5ca9f088193e9bc5323
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify */
52 #define TARGET_CPU_generic 0x8000
53
54 enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 };
59
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
62
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
64
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75
76 \f
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
80 #endif
81
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #else
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
90 #endif
91 #endif
92
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #else
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #else
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #else
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 #else
108 Unrecognized value in TARGET_CPU_DEFAULT.
109 #endif
110 #endif
111 #endif
112 #endif
113 #endif
114
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
117 #endif
118
119 #define CPP_SPEC "\
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
122
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm720:-D__ARM_ARCH_3__} \
136 %{march=arm7100:-D__ARM_ARCH_3__} \
137 %{march=arm7500:-D__ARM_ARCH_3__} \
138 %{march=arm7500fe:-D__ARM_ARCH_3__} \
139 %{march=arm7m:-D__ARM_ARCH_3M__} \
140 %{march=arm7dm:-D__ARM_ARCH_3M__} \
141 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
142 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
143 %{march=arm8:-D__ARM_ARCH_4__} \
144 %{march=arm810:-D__ARM_ARCH_4__} \
145 %{march=arm9:-D__ARM_ARCH_4T__} \
146 %{march=arm920:-D__ARM_ARCH_4__} \
147 %{march=arm920t:-D__ARM_ARCH_4T__} \
148 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
149 %{march=strongarm:-D__ARM_ARCH_4__} \
150 %{march=strongarm110:-D__ARM_ARCH_4__} \
151 %{march=strongarm1100:-D__ARM_ARCH_4__} \
152 %{march=armv2:-D__ARM_ARCH_2__} \
153 %{march=armv2a:-D__ARM_ARCH_2__} \
154 %{march=armv3:-D__ARM_ARCH_3__} \
155 %{march=armv3m:-D__ARM_ARCH_3M__} \
156 %{march=armv4:-D__ARM_ARCH_4__} \
157 %{march=armv4t:-D__ARM_ARCH_4T__} \
158 %{march=armv5:-D__ARM_ARCH_5__} \
159 %{!march=*: \
160 %{mcpu=arm2:-D__ARM_ARCH_2__} \
161 %{mcpu=arm250:-D__ARM_ARCH_2__} \
162 %{mcpu=arm3:-D__ARM_ARCH_2__} \
163 %{mcpu=arm6:-D__ARM_ARCH_3__} \
164 %{mcpu=arm600:-D__ARM_ARCH_3__} \
165 %{mcpu=arm610:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7:-D__ARM_ARCH_3__} \
167 %{mcpu=arm700:-D__ARM_ARCH_3__} \
168 %{mcpu=arm710:-D__ARM_ARCH_3__} \
169 %{mcpu=arm720:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
172 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
173 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
175 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
176 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
177 %{mcpu=arm8:-D__ARM_ARCH_4__} \
178 %{mcpu=arm810:-D__ARM_ARCH_4__} \
179 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm920:-D__ARM_ARCH_4__} \
181 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
182 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
183 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
184 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
185 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
186 %{!mcpu*:%(cpp_cpu_arch_default)}} \
187 "
188
189 /* Define __APCS_26__ if the PC also contains the PSR */
190 #define CPP_APCS_PC_SPEC "\
191 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
192 -D__APCS_32__} \
193 %{mapcs-26:-D__APCS_26__} \
194 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
195 "
196
197 #ifndef CPP_APCS_PC_DEFAULT_SPEC
198 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
199 #endif
200
201 #define CPP_FLOAT_SPEC "\
202 %{msoft-float:\
203 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
204 -D__SOFTFP__} \
205 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
206 "
207
208 /* Default is hard float, which doesn't define anything */
209 #define CPP_FLOAT_DEFAULT_SPEC ""
210
211 #define CPP_ENDIAN_SPEC "\
212 %{mbig-endian: \
213 %{mlittle-endian: \
214 %e-mbig-endian and -mlittle-endian may not be used together} \
215 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
216 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
217 "
218
219 /* Default is little endian, which doesn't define anything. */
220 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__"
221
222 #define CC1_SPEC ""
223
224 /* This macro defines names of additional specifications to put in the specs
225 that can be used in various specifications like CC1_SPEC. Its definition
226 is an initializer with a subgrouping for each command option.
227
228 Each subgrouping contains a string constant, that defines the
229 specification name, and a string constant that used by the GNU CC driver
230 program.
231
232 Do not define this macro if it does not need to do anything. */
233 #define EXTRA_SPECS \
234 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
235 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
236 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
237 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
238 { "cpp_float", CPP_FLOAT_SPEC }, \
239 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
240 { "cpp_endian", CPP_ENDIAN_SPEC }, \
241 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
242 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
243 SUBTARGET_EXTRA_SPECS
244
245 #define SUBTARGET_EXTRA_SPECS
246 #ifndef SUBTARGET_CPP_SPEC
247 #define SUBTARGET_CPP_SPEC ""
248 #endif
249
250 \f
251 /* Run-time Target Specification. */
252 #ifndef TARGET_VERSION
253 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
254 #endif
255
256 /* Nonzero if the function prologue (and epilogue) should obey
257 the ARM Procedure Call Standard. */
258 #define ARM_FLAG_APCS_FRAME (1 << 0)
259
260 /* Nonzero if the function prologue should output the function name to enable
261 the post mortem debugger to print a backtrace (very useful on RISCOS,
262 unused on RISCiX). Specifying this flag also enables
263 -fno-omit-frame-pointer.
264 XXX Must still be implemented in the prologue. */
265 #define ARM_FLAG_POKE (1 << 1)
266
267 /* Nonzero if floating point instructions are emulated by the FPE, in which
268 case instruction scheduling becomes very uninteresting. */
269 #define ARM_FLAG_FPE (1 << 2)
270
271 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
272 that assume restoration of the condition flags when returning from a
273 branch and link (ie a function). */
274 #define ARM_FLAG_APCS_32 (1 << 3)
275
276 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
277
278 /* Nonzero if stack checking should be performed on entry to each function
279 which allocates temporary variables on the stack. */
280 #define ARM_FLAG_APCS_STACK (1 << 4)
281
282 /* Nonzero if floating point parameters should be passed to functions in
283 floating point registers. */
284 #define ARM_FLAG_APCS_FLOAT (1 << 5)
285
286 /* Nonzero if re-entrant, position independent code should be generated.
287 This is equivalent to -fpic. */
288 #define ARM_FLAG_APCS_REENT (1 << 6)
289
290 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
291 be loaded using either LDRH or LDRB instructions. */
292 #define ARM_FLAG_MMU_TRAPS (1 << 7)
293
294 /* Nonzero if all floating point instructions are missing (and there is no
295 emulator either). Generate function calls for all ops in this case. */
296 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
297
298 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
299 #define ARM_FLAG_BIG_END (1 << 9)
300
301 /* Nonzero if we should compile for Thumb interworking. */
302 #define ARM_FLAG_INTERWORK (1 << 10)
303
304 /* Nonzero if we should have little-endian words even when compiling for
305 big-endian (for backwards compatibility with older versions of GCC). */
306 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
307
308 /* Nonzero if we need to protect the prolog from scheduling */
309 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
310
311 /* Nonzero if a call to abort should be generated if a noreturn
312 function tries to return. */
313 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
314
315 /* Nonzero if function prologues should not load the PIC register. */
316 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
317
318 /* Nonzero if all call instructions should be indirect. */
319 #define ARM_FLAG_LONG_CALLS (1 << 15)
320
321 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
322 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
323 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
324 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
325 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
326 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
327 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
328 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
329 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
330 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
331 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
332 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
333 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
334 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
335 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
336 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
337 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
338
339 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
340 Bit 31 is reserved. See riscix.h. */
341 #ifndef SUBTARGET_SWITCHES
342 #define SUBTARGET_SWITCHES
343 #endif
344
345 #define TARGET_SWITCHES \
346 { \
347 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
348 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
349 "Generate APCS conformant stack frames" }, \
350 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
351 {"poke-function-name", ARM_FLAG_POKE, \
352 "Store function names in object code" }, \
353 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
354 {"fpe", ARM_FLAG_FPE, "" }, \
355 {"apcs-32", ARM_FLAG_APCS_32, \
356 "Use the 32bit version of the APCS" }, \
357 {"apcs-26", -ARM_FLAG_APCS_32, \
358 "Use the 26bit version of the APCS" }, \
359 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
360 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
361 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
362 "Pass FP arguments in FP registers" }, \
363 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
364 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
365 "Generate re-entrant, PIC code" }, \
366 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
367 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
368 "The MMU will trap on unaligned accesses" },\
369 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
370 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
371 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
372 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
373 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
374 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
375 "Use library calls to perform FP operations" }, \
376 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
377 "Use hardware floating point instructions" }, \
378 {"big-endian", ARM_FLAG_BIG_END, \
379 "Assume target CPU is configured as big endian" }, \
380 {"little-endian", -ARM_FLAG_BIG_END, \
381 "Assume target CPU is configured as little endian" }, \
382 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
383 "Assume big endian bytes, little endian words" }, \
384 {"thumb-interwork", ARM_FLAG_INTERWORK, \
385 "Support calls between THUMB and ARM instructions sets" }, \
386 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
387 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
388 "Generate a call to abort if a noreturn function returns"}, \
389 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
390 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
391 "Do not move instructions into a function's prologue" }, \
392 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
393 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
394 "Do not load the PIC register in function prologues" }, \
395 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
396 {"long-calls", ARM_FLAG_LONG_CALLS, \
397 "Generate all call instructions as indirect calls"}, \
398 {"no-long-calls", -ARM_FLAG_LONG_CALLS, ""}, \
399 SUBTARGET_SWITCHES \
400 {"", TARGET_DEFAULT, "" } \
401 }
402
403 #define TARGET_OPTIONS \
404 { \
405 {"cpu=", & arm_select[0].string, \
406 "Specify the name of the target CPU" }, \
407 {"arch=", & arm_select[1].string, \
408 "Specify the name of the target architecture" }, \
409 {"tune=", & arm_select[2].string, "" }, \
410 {"fpe=", & target_fp_name, "" }, \
411 {"fp=", & target_fp_name, \
412 "Specify the version of the floating point emulator" }, \
413 { "structure-size-boundary=", & structure_size_string, \
414 "Specify the minumum bit alignment of structures" }, \
415 { "pic-register=", & arm_pic_register_string, \
416 "Specify the register to be used for PIC addressing" } \
417 }
418
419 struct arm_cpu_select
420 {
421 const char * string;
422 const char * name;
423 const struct processors * processors;
424 };
425
426 /* This is a magic array. If the user specifies a command line switch
427 which matches one of the entries in TARGET_OPTIONS then the corresponding
428 string pointer will be set to the value specified by the user. */
429 extern struct arm_cpu_select arm_select[];
430
431 enum prog_mode_type
432 {
433 prog_mode26,
434 prog_mode32
435 };
436
437 /* Recast the program mode class to be the prog_mode attribute */
438 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
439
440 extern enum prog_mode_type arm_prgmode;
441
442 /* What sort of floating point unit do we have? Hardware or software.
443 If software, is it issue 2 or issue 3? */
444 enum floating_point_type
445 {
446 FP_HARD,
447 FP_SOFT2,
448 FP_SOFT3
449 };
450
451 /* Recast the floating point class to be the floating point attribute. */
452 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
453
454 /* What type of floating point to tune for */
455 extern enum floating_point_type arm_fpu;
456
457 /* What type of floating point instructions are available */
458 extern enum floating_point_type arm_fpu_arch;
459
460 /* Default floating point architecture. Override in sub-target if
461 necessary. */
462 #define FP_DEFAULT FP_SOFT2
463
464 /* Nonzero if the processor has a fast multiply insn, and one that does
465 a 64-bit multiply of two 32-bit values. */
466 extern int arm_fast_multiply;
467
468 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
469 extern int arm_arch4;
470
471 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
472 extern int arm_arch5;
473
474 /* Nonzero if this chip can benefit from load scheduling. */
475 extern int arm_ld_sched;
476
477 /* Nonzero if this chip is a StrongARM. */
478 extern int arm_is_strong;
479
480 /* Nonzero if this chip is a an ARM6 or an ARM7. */
481 extern int arm_is_6_or_7;
482
483 #ifndef TARGET_DEFAULT
484 #define TARGET_DEFAULT 0
485 #endif
486
487 /* The frame pointer register used in gcc has nothing to do with debugging;
488 that is controlled by the APCS-FRAME option. */
489 /* Not fully implemented yet */
490 /* #define CAN_DEBUG_WITHOUT_FP 1 */
491
492 #define TARGET_MEM_FUNCTIONS 1
493
494 #define OVERRIDE_OPTIONS arm_override_options ()
495
496 /* Nonzero if PIC code requires explicit qualifiers to generate
497 PLT and GOT relocs rather than the assembler doing so implicitly.
498 Subtargets can override these if required. */
499 #ifndef NEED_GOT_RELOC
500 #define NEED_GOT_RELOC 0
501 #endif
502 #ifndef NEED_PLT_RELOC
503 #define NEED_PLT_RELOC 0
504 #endif
505
506 /* Nonzero if we need to refer to the GOT with a PC-relative
507 offset. In other words, generate
508
509 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
510
511 rather than
512
513 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
514
515 The default is true, which matches NetBSD. Subtargets can
516 override this if required. */
517 #ifndef GOT_PCREL
518 #define GOT_PCREL 1
519 #endif
520 \f
521 /* Target machine storage Layout. */
522
523
524 /* Define this macro if it is advisable to hold scalars in registers
525 in a wider mode than that declared by the program. In such cases,
526 the value is constrained to be within the bounds of the declared
527 type, but kept valid in the wider mode. The signedness of the
528 extension may differ from that of the type. */
529
530 /* It is far faster to zero extend chars than to sign extend them */
531
532 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
533 if (GET_MODE_CLASS (MODE) == MODE_INT \
534 && GET_MODE_SIZE (MODE) < 4) \
535 { \
536 if (MODE == QImode) \
537 UNSIGNEDP = 1; \
538 else if (MODE == HImode) \
539 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
540 (MODE) = SImode; \
541 }
542
543 /* Define this macro if the promotion described by `PROMOTE_MODE'
544 should also be done for outgoing function arguments. */
545 /* This is required to ensure that push insns always push a word. */
546 #define PROMOTE_FUNCTION_ARGS
547
548 /* Define for XFmode extended real floating point support.
549 This will automatically cause REAL_ARITHMETIC to be defined. */
550 /* For the ARM:
551 I think I have added all the code to make this work. Unfortunately,
552 early releases of the floating point emulation code on RISCiX used a
553 different format for extended precision numbers. On my RISCiX box there
554 is a bug somewhere which causes the machine to lock up when running enquire
555 with long doubles. There is the additional aspect that Norcroft C
556 treats long doubles as doubles and we ought to remain compatible.
557 Perhaps someone with an FPA coprocessor and not running RISCiX would like
558 to try this someday. */
559 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
560
561 /* Disable XFmode patterns in md file */
562 #define ENABLE_XF_PATTERNS 0
563
564 /* Define if you don't want extended real, but do want to use the
565 software floating point emulator for REAL_ARITHMETIC and
566 decimal <-> binary conversion. */
567 /* See comment above */
568 #define REAL_ARITHMETIC
569
570 /* Define this if most significant bit is lowest numbered
571 in instructions that operate on numbered bit-fields. */
572 #define BITS_BIG_ENDIAN 0
573
574 /* Define this if most significant byte of a word is the lowest numbered.
575 Most ARM processors are run in little endian mode, so that is the default.
576 If you want to have it run-time selectable, change the definition in a
577 cover file to be TARGET_BIG_ENDIAN. */
578 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
579
580 /* Define this if most significant word of a multiword number is the lowest
581 numbered.
582 This is always false, even when in big-endian mode. */
583 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
584
585 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
586 on processor pre-defineds when compiling libgcc2.c. */
587 #if defined(__ARMEB__) && !defined(__ARMWEL__)
588 #define LIBGCC2_WORDS_BIG_ENDIAN 1
589 #else
590 #define LIBGCC2_WORDS_BIG_ENDIAN 0
591 #endif
592
593 /* Define this if most significant word of doubles is the lowest numbered.
594 This is always true, even when in little-endian mode. */
595 #define FLOAT_WORDS_BIG_ENDIAN 1
596
597 /* Number of bits in an addressable storage unit */
598 #define BITS_PER_UNIT 8
599
600 #define BITS_PER_WORD 32
601
602 #define UNITS_PER_WORD 4
603
604 #define POINTER_SIZE 32
605
606 #define PARM_BOUNDARY 32
607
608 #define STACK_BOUNDARY 32
609
610 #define FUNCTION_BOUNDARY 32
611
612 #define EMPTY_FIELD_BOUNDARY 32
613
614 #define BIGGEST_ALIGNMENT 32
615
616 /* Make strings word-aligned so strcpy from constants will be faster. */
617 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
618 (TREE_CODE (EXP) == STRING_CST \
619 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
620
621 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
622 value set in previous versions of this toolchain was 8, which produces more
623 compact structures. The command line option -mstructure_size_boundary=<n>
624 can be used to change this value. For compatability with the ARM SDK
625 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
626 0020D) page 2-20 says "Structures are aligned on word boundaries". */
627 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
628 extern int arm_structure_size_boundary;
629
630 /* This is the value used to initialise arm_structure_size_boundary. If a
631 particular arm target wants to change the default value it should change
632 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
633 for an example of this. */
634 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
635 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
636 #endif
637
638 /* Used when parsing command line option -mstructure_size_boundary. */
639 extern const char * structure_size_string;
640
641 /* Non-zero if move instructions will actually fail to work
642 when given unaligned data. */
643 #define STRICT_ALIGNMENT 1
644
645 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
646
647 \f
648 /* Standard register usage. */
649
650 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
651 (S - saved over call).
652
653 r0 * argument word/integer result
654 r1-r3 argument word
655
656 r4-r8 S register variable
657 r9 S (rfp) register variable (real frame pointer)
658
659 r10 F S (sl) stack limit (used by -mapcs-stack-check)
660 r11 F S (fp) argument pointer
661 r12 (ip) temp workspace
662 r13 F S (sp) lower end of current stack frame
663 r14 (lr) link address/workspace
664 r15 F (pc) program counter
665
666 f0 floating point result
667 f1-f3 floating point scratch
668
669 f4-f7 S floating point variable
670
671 cc This is NOT a real register, but is used internally
672 to represent things that use or set the condition
673 codes.
674 sfp This isn't either. It is used during rtl generation
675 since the offset between the frame pointer and the
676 auto's isn't known until after register allocation.
677 afp Nor this, we only need this because of non-local
678 goto. Without it fp appears to be used and the
679 elimination code won't get rid of sfp. It tracks
680 fp exactly at all times.
681
682 *: See CONDITIONAL_REGISTER_USAGE */
683
684 /* The stack backtrace structure is as follows:
685 fp points to here: | save code pointer | [fp]
686 | return link value | [fp, #-4]
687 | return sp value | [fp, #-8]
688 | return fp value | [fp, #-12]
689 [| saved r10 value |]
690 [| saved r9 value |]
691 [| saved r8 value |]
692 [| saved r7 value |]
693 [| saved r6 value |]
694 [| saved r5 value |]
695 [| saved r4 value |]
696 [| saved r3 value |]
697 [| saved r2 value |]
698 [| saved r1 value |]
699 [| saved r0 value |]
700 [| saved f7 value |] three words
701 [| saved f6 value |] three words
702 [| saved f5 value |] three words
703 [| saved f4 value |] three words
704 r0-r3 are not normally saved in a C function. */
705
706 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
707 #define FIRST_PSEUDO_REGISTER 27
708
709 /* 1 for registers that have pervasive standard uses
710 and are not available for the register allocator. */
711 #define FIXED_REGISTERS \
712 { \
713 0,0,0,0,0,0,0,0, \
714 0,0,0,1,0,1,0,1, \
715 0,0,0,0,0,0,0,0, \
716 1,1,1 \
717 }
718
719 /* 1 for registers not available across function calls.
720 These must include the FIXED_REGISTERS and also any
721 registers that can be used without being saved.
722 The latter must include the registers where values are returned
723 and the register where structure-value addresses are passed.
724 Aside from that, you can include as many other registers as you like.
725 The CC is not preserved over function calls on the ARM 6, so it is
726 easier to assume this for all. SFP is preserved, since FP is. */
727 #define CALL_USED_REGISTERS \
728 { \
729 1,1,1,1,0,0,0,0, \
730 0,0,0,1,1,1,1,1, \
731 1,1,1,1,0,0,0,0, \
732 1,1,1 \
733 }
734
735 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
736 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
737 #endif
738
739 #define CONDITIONAL_REGISTER_USAGE \
740 { \
741 if (TARGET_SOFT_FLOAT) \
742 { \
743 int regno; \
744 for (regno = 16; regno < 24; ++regno) \
745 fixed_regs[regno] = call_used_regs[regno] = 1; \
746 } \
747 if (flag_pic) \
748 { \
749 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
750 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
751 } \
752 else if (TARGET_APCS_STACK) \
753 { \
754 fixed_regs[10] = 1; \
755 call_used_regs[10] = 1; \
756 } \
757 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
758 }
759
760 /* These are a couple of extensions to the formats accecpted
761 by asm_fprintf:
762 %@ prints out ASM_COMMENT_START
763 %r prints out REGISTER_PREFIX reg_names[arg] */
764 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
765 case '@': \
766 fputs (ASM_COMMENT_START, FILE); \
767 break; \
768 \
769 case 'r': \
770 fputs (REGISTER_PREFIX, FILE); \
771 fputs (reg_names [va_arg (ARGS, int)], FILE); \
772 break;
773
774 /* Convert fron bytes to ints. */
775 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
776
777 /* The number of (integer) registers required to hold a quantity of type MODE. */
778 #define NUM_REGS(MODE) \
779 NUM_INTS (GET_MODE_SIZE (MODE))
780
781 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
782 #define NUM_REGS2(MODE, TYPE) \
783 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
784
785 /* The number of (integer) argument register available. */
786 #define NUM_ARG_REGS 4
787
788 /* Return the regiser number of the N'th (integer) argument. */
789 #define ARG_REGISTER(N) (N - 1)
790
791 /* The number of the last argument register. */
792 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
793
794 /* Return number of consecutive hard regs needed starting at reg REGNO
795 to hold something of mode MODE.
796 This is ordinarily the length in words of a value of mode MODE
797 but can be less for certain modes in special long registers.
798
799 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
800 mode. */
801 #define HARD_REGNO_NREGS(REGNO, MODE) \
802 (( REGNO >= 16 \
803 && REGNO != FRAME_POINTER_REGNUM \
804 && REGNO != ARG_POINTER_REGNUM) \
805 ? 1 : NUM_REGS (MODE))
806
807 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
808 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
809 regs holding FP. */
810 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
811 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
812 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
813 || REGNO == ARG_POINTER_REGNUM \
814 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
815
816 /* Value is 1 if it is a good idea to tie two pseudo registers
817 when one has mode MODE1 and one has mode MODE2.
818 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
819 for any hard reg, then this must be 0 for correct output. */
820 #define MODES_TIEABLE_P(MODE1, MODE2) \
821 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
822
823 /* Specify the registers used for certain standard purposes.
824 The values of these macros are register numbers. */
825
826 /* Define this if the program counter is overloaded on a register. */
827 #define PC_REGNUM 15
828
829 /* Register to use for pushing function arguments. */
830 #define STACK_POINTER_REGNUM 13
831 #define SP_REGNUM STACK_POINTER_REGNUM
832
833 /* Base register for access to local variables of the function. */
834 #define FRAME_POINTER_REGNUM 25
835
836 /* Define this to be where the real frame pointer is if it is not possible to
837 work out the offset between the frame pointer and the automatic variables
838 until after register allocation has taken place. FRAME_POINTER_REGNUM
839 should point to a special register that we will make sure is eliminated. */
840 #define HARD_FRAME_POINTER_REGNUM 11
841 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
842
843 /* Register which holds return address from a subroutine call. */
844 #define LR_REGNUM 14
845
846 /* Scratch register - used in all kinds of places, eg trampolines. */
847 #define IP_REGNUM 12
848
849 /* Value should be nonzero if functions must have frame pointers.
850 Zero means the frame pointer need not be set up (and parms may be accessed
851 via the stack pointer) in functions that seem suitable.
852 If we have to have a frame pointer we might as well make use of it.
853 APCS says that the frame pointer does not need to be pushed in leaf
854 functions, or simple tail call functions. */
855 #define FRAME_POINTER_REQUIRED \
856 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
857
858 /* Base register for access to arguments of the function. */
859 #define ARG_POINTER_REGNUM 26
860
861 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
862 as an invisible last argument (possible since varargs don't exist in
863 Pascal), so the following is not true. */
864 #define STATIC_CHAIN_REGNUM 8
865
866 /* Register in which address to store a structure value
867 is passed to a function. */
868 #define STRUCT_VALUE_REGNUM 0
869
870 /* Internal, so that we don't need to refer to a raw number */
871 #define CC_REGNUM 24
872
873 /* The order in which register should be allocated. It is good to use ip
874 since no saving is required (though calls clobber it) and it never contains
875 function parameters. It is quite good to use lr since other calls may
876 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
877 least likely to contain a function parameter; in addition results are
878 returned in r0.
879 */
880 #define REG_ALLOC_ORDER \
881 { \
882 3, 2, 1, 0, 12, 14, 4, 5, \
883 6, 7, 8, 10, 9, 11, 13, 15, \
884 16, 17, 18, 19, 20, 21, 22, 23, \
885 24, 25, 26 \
886 }
887 \f
888 /* Register and constant classes. */
889
890 /* Register classes: all ARM regs or all FPU regs---simple! */
891 enum reg_class
892 {
893 NO_REGS,
894 FPU_REGS,
895 GENERAL_REGS,
896 ALL_REGS,
897 LIM_REG_CLASSES
898 };
899
900 #define N_REG_CLASSES (int) LIM_REG_CLASSES
901
902 /* Give names of register classes as strings for dump file. */
903 #define REG_CLASS_NAMES \
904 { \
905 "NO_REGS", \
906 "FPU_REGS", \
907 "GENERAL_REGS", \
908 "ALL_REGS", \
909 }
910
911 /* Define which registers fit in which classes.
912 This is an initializer for a vector of HARD_REG_SET
913 of length N_REG_CLASSES. */
914 #define REG_CLASS_CONTENTS \
915 { \
916 { 0x0000000 }, /* NO_REGS */ \
917 { 0x0FF0000 }, /* FPU_REGS */ \
918 { 0x200FFFF }, /* GENERAL_REGS */ \
919 { 0x2FFFFFF } /* ALL_REGS */ \
920 }
921
922 /* The same information, inverted:
923 Return the class number of the smallest class containing
924 reg number REGNO. This could be a conditional expression
925 or could index an array. */
926 #define REGNO_REG_CLASS(REGNO) \
927 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
928 || REGNO == ARG_POINTER_REGNUM) \
929 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
930 ? NO_REGS : FPU_REGS)
931
932 /* The class value for index registers, and the one for base regs. */
933 #define INDEX_REG_CLASS GENERAL_REGS
934 #define BASE_REG_CLASS GENERAL_REGS
935
936 /* Get reg_class from a letter such as appears in the machine description.
937 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
938 #define REG_CLASS_FROM_LETTER(C) \
939 ((C)=='f' ? FPU_REGS : NO_REGS)
940
941 /* The letters I, J, K, L and M in a register constraint string
942 can be used to stand for particular ranges of immediate operands.
943 This macro defines what the ranges are.
944 C is the letter, and VALUE is a constant value.
945 Return 1 if VALUE is in the range specified by C.
946 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
947 J: valid indexing constants.
948 K: ~value ok in rhs argument of data operand.
949 L: -value ok in rhs argument of data operand.
950 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
951 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
952 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
953 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
954 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
955 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
956 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
957 || (((VALUE) & ((VALUE) - 1)) == 0)) \
958 : 0)
959
960 /* For the ARM, `Q' means that this is a memory operand that is just
961 an offset from a register.
962 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
963 address. This means that the symbol is in the text segment and can be
964 accessed without using a load. */
965
966 #define EXTRA_CONSTRAINT(OP, C) \
967 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
968 : (C) == 'R' ? (GET_CODE (OP) == MEM \
969 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
970 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
971 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
972 : 0)
973
974 /* Constant letter 'G' for the FPU immediate constants.
975 'H' means the same constant negated. */
976 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
977 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
978 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
979
980 /* Given an rtx X being reloaded into a reg required to be
981 in class CLASS, return the class of reg to actually use.
982 In general this is just CLASS; but on some machines
983 in some cases it is preferable to use a more restrictive class. */
984 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
985
986 /* Return the register class of a scratch register needed to copy IN into
987 or out of a register in CLASS in MODE. If it can be done directly,
988 NO_REGS is returned. */
989 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
990 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
991 ? GENERAL_REGS : NO_REGS)
992
993 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
994 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
995 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
996 && (GET_CODE (X) == MEM \
997 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
998 && true_regnum (X) == -1))) \
999 ? GENERAL_REGS : NO_REGS)
1000
1001 /* Try a machine-dependent way of reloading an illegitimate address
1002 operand. If we find one, push the reload and jump to WIN. This
1003 macro is used in only one place: `find_reloads_address' in reload.c.
1004
1005 For the ARM, we wish to handle large displacements off a base
1006 register by splitting the addend across a MOV and the mem insn.
1007 This can cut the number of reloads needed. */
1008 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1009 do \
1010 { \
1011 if (GET_CODE (X) == PLUS \
1012 && GET_CODE (XEXP (X, 0)) == REG \
1013 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1014 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1015 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1016 { \
1017 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1018 HOST_WIDE_INT low, high; \
1019 \
1020 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1021 low = ((val & 0xf) ^ 0x8) - 0x8; \
1022 else if (MODE == SImode \
1023 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1024 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1025 /* Need to be careful, -4096 is not a valid offset */ \
1026 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1027 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1028 /* Need to be careful, -256 is not a valid offset */ \
1029 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1030 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1031 && TARGET_HARD_FLOAT) \
1032 /* Need to be careful, -1024 is not a valid offset */ \
1033 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1034 else \
1035 break; \
1036 \
1037 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
1038 /* Check for overflow or zero */ \
1039 if (low == 0 || high == 0 || (high + low != val)) \
1040 break; \
1041 \
1042 /* Reload the high part into a base reg; leave the low part \
1043 in the mem. */ \
1044 X = gen_rtx_PLUS (GET_MODE (X), \
1045 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1046 GEN_INT (high)), \
1047 GEN_INT (low)); \
1048 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1049 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1050 OPNUM, TYPE); \
1051 goto WIN; \
1052 } \
1053 } \
1054 while (0)
1055
1056 /* Return the maximum number of consecutive registers
1057 needed to represent mode MODE in a register of class CLASS.
1058 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1059 #define CLASS_MAX_NREGS(CLASS, MODE) \
1060 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1061
1062 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1063 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1064 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1065 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1066 ? 20 : 2)
1067 \f
1068 /* Stack layout; function entry, exit and calling. */
1069
1070 /* Define this if pushing a word on the stack
1071 makes the stack pointer a smaller address. */
1072 #define STACK_GROWS_DOWNWARD 1
1073
1074 /* Define this if the nominal address of the stack frame
1075 is at the high-address end of the local variables;
1076 that is, each additional local variable allocated
1077 goes at a more negative offset in the frame. */
1078 #define FRAME_GROWS_DOWNWARD 1
1079
1080 /* Offset within stack frame to start allocating local variables at.
1081 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1082 first local allocated. Otherwise, it is the offset to the BEGINNING
1083 of the first local allocated. */
1084 #define STARTING_FRAME_OFFSET 0
1085
1086 /* If we generate an insn to push BYTES bytes,
1087 this says how many the stack pointer really advances by. */
1088 /* The push insns do not do this rounding implicitly. So don't define this. */
1089 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1090
1091 /* Define this if the maximum size of all the outgoing args is to be
1092 accumulated and pushed during the prologue. The amount can be
1093 found in the variable current_function_outgoing_args_size. */
1094 #define ACCUMULATE_OUTGOING_ARGS 1
1095
1096 /* Offset of first parameter from the argument pointer register value. */
1097 #define FIRST_PARM_OFFSET(FNDECL) 4
1098
1099 /* Value is the number of byte of arguments automatically
1100 popped when returning from a subroutine call.
1101 FUNDECL is the declaration node of the function (as a tree),
1102 FUNTYPE is the data type of the function (as a tree),
1103 or for a library call it is an identifier node for the subroutine name.
1104 SIZE is the number of bytes of arguments passed on the stack.
1105
1106 On the ARM, the caller does not pop any of its arguments that were passed
1107 on the stack. */
1108 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1109
1110 /* Define how to find the value returned by a library function
1111 assuming the value has mode MODE. */
1112 #define LIBCALL_VALUE(MODE) \
1113 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1114 ? gen_rtx_REG (MODE, 16) \
1115 : gen_rtx_REG (MODE, 0))
1116
1117 /* Define how to find the value returned by a function.
1118 VALTYPE is the data type of the value (as a tree).
1119 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1120 otherwise, FUNC is 0. */
1121 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1122 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1123
1124 /* 1 if N is a possible register number for a function value.
1125 On the ARM, only r0 and f0 can return results. */
1126 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1127 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1128
1129 /* How large values are returned */
1130 /* A C expression which can inhibit the returning of certain function values
1131 in registers, based on the type of value. */
1132 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1133
1134 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1135 values must be in memory. On the ARM, they need only do so if larger
1136 than a word, or if they contain elements offset from zero in the struct. */
1137 #define DEFAULT_PCC_STRUCT_RETURN 0
1138
1139 /* Define where to put the arguments to a function.
1140 Value is zero to push the argument on the stack,
1141 or a hard register in which to store the argument.
1142
1143 MODE is the argument's machine mode.
1144 TYPE is the data type of the argument (as a tree).
1145 This is null for libcalls where that information may
1146 not be available.
1147 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1148 the preceding args and about the function being called.
1149 NAMED is nonzero if this argument is a named parameter
1150 (otherwise it is an extra parameter matching an ellipsis).
1151
1152 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1153 other arguments are passed on the stack. If (NAMED == 0) (which happens
1154 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1155 passed in the stack (function_prologue will indeed make it pass in the
1156 stack if necessary). */
1157 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1158 ((NAMED) \
1159 ? ((CUM) >= NUM_ARG_REGS ? 0 : gen_rtx_REG (MODE, CUM))\
1160 : 0)
1161
1162 /* For an arg passed partly in registers and partly in memory,
1163 this is the number of registers used.
1164 For args passed entirely in registers or entirely in memory, zero. */
1165 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1166 ( NUM_ARG_REGS > (CUM) \
1167 && (NUM_ARG_REGS < ((CUM) + NUM_REGS2 (MODE, TYPE))) \
1168 ? NUM_ARG_REGS - (CUM) : 0)
1169
1170 /* A C type for declaring a variable that is used as the first argument of
1171 `FUNCTION_ARG' and other related values. For some target machines, the
1172 type `int' suffices and can hold the number of bytes of argument so far.
1173
1174 On the ARM, this is the number of bytes of arguments scanned so far. */
1175 #define CUMULATIVE_ARGS int
1176
1177 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1178 for a call to a function whose data type is FNTYPE.
1179 For a library call, FNTYPE is 0.
1180 On the ARM, the offset starts at 0. */
1181 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1182 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 1 : 0))
1183
1184 /* Update the data in CUM to advance over an argument
1185 of mode MODE and data type TYPE.
1186 (TYPE is null for libcalls where that information may not be available.) */
1187 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1188 (CUM) += NUM_REGS2 (MODE, TYPE)
1189
1190 /* 1 if N is a possible register number for function argument passing.
1191 On the ARM, r0-r3 are used to pass args. */
1192 #define FUNCTION_ARG_REGNO_P(REGNO) \
1193 ((REGNO) >= 0 && (REGNO) <= 3)
1194
1195 /* Perform any actions needed for a function that is receiving a variable
1196 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1197 of the current parameter. PRETEND_SIZE is a variable that should be set to
1198 the amount of stack that must be pushed by the prolog to pretend that our
1199 caller pushed it.
1200
1201 Normally, this macro will push all remaining incoming registers on the
1202 stack and set PRETEND_SIZE to the length of the registers pushed.
1203
1204 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1205 named arg and all anonymous args onto the stack.
1206 XXX I know the prologue shouldn't be pushing registers, but it is faster
1207 that way. */
1208 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1209 { \
1210 extern int current_function_anonymous_args; \
1211 current_function_anonymous_args = 1; \
1212 if ((CUM) < NUM_ARG_REGS) \
1213 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM)) * UNITS_PER_WORD; \
1214 }
1215
1216 /* Generate assembly output for the start of a function. */
1217 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1218 output_func_prologue ((STREAM), (SIZE))
1219
1220 /* If your target environment doesn't prefix user functions with an
1221 underscore, you may wish to re-define this to prevent any conflicts.
1222 e.g. AOF may prefix mcount with an underscore. */
1223 #ifndef ARM_MCOUNT_NAME
1224 #define ARM_MCOUNT_NAME "*mcount"
1225 #endif
1226
1227 /* Call the function profiler with a given profile label. The Acorn
1228 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1229 On the ARM the full profile code will look like:
1230 .data
1231 LP1
1232 .word 0
1233 .text
1234 mov ip, lr
1235 bl mcount
1236 .word LP1
1237
1238 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1239 will output the .text section.
1240
1241 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1242 ``prof'' doesn't seem to mind about this! */
1243 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1244 { \
1245 char temp[20]; \
1246 rtx sym; \
1247 \
1248 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1249 IP_REGNUM, LR_REGNUM); \
1250 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1251 fputc ('\n', STREAM); \
1252 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1253 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1254 ASM_OUTPUT_INT (STREAM, sym); \
1255 }
1256
1257 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1258 the stack pointer does not matter. The value is tested only in
1259 functions that have frame pointers.
1260 No definition is equivalent to always zero.
1261
1262 On the ARM, the function epilogue recovers the stack pointer from the
1263 frame. */
1264 #define EXIT_IGNORE_STACK 1
1265
1266 /* Generate the assembly code for function exit. */
1267 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1268 output_func_epilogue (SIZE)
1269
1270 /* Determine if the epilogue should be output as RTL.
1271 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1272 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1273
1274 /* Definitions for register eliminations.
1275
1276 This is an array of structures. Each structure initializes one pair
1277 of eliminable registers. The "from" register number is given first,
1278 followed by "to". Eliminations of the same "from" register are listed
1279 in order of preference.
1280
1281 We have two registers that can be eliminated on the ARM. First, the
1282 arg pointer register can often be eliminated in favor of the stack
1283 pointer register. Secondly, the pseudo frame pointer register can always
1284 be eliminated; it is replaced with either the stack or the real frame
1285 pointer. */
1286
1287 #define ELIMINABLE_REGS \
1288 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1289 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1290 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1291 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1292
1293 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1294 Frame pointer elimination is automatically handled.
1295
1296 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1297 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1298 pointer, we must eliminate FRAME_POINTER_REGNUM into
1299 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1300 #define CAN_ELIMINATE(FROM, TO) \
1301 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1302
1303 /* Define the offset between two registers, one to be eliminated, and the other
1304 its replacement, at the start of a routine. */
1305 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1306 { \
1307 int volatile_func = arm_volatile_func (); \
1308 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1309 (OFFSET) = 0; \
1310 else if ((FROM) == FRAME_POINTER_REGNUM \
1311 && (TO) == STACK_POINTER_REGNUM) \
1312 (OFFSET) = current_function_outgoing_args_size \
1313 + ((get_frame_size () + 3) & ~3); \
1314 else \
1315 { \
1316 int regno; \
1317 int offset = 12; \
1318 int saved_hard_reg = 0; \
1319 \
1320 if (! volatile_func) \
1321 { \
1322 for (regno = 0; regno <= 10; regno++) \
1323 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1324 saved_hard_reg = 1, offset += 4; \
1325 /* PIC register is a fixed reg, so call_used_regs set. */ \
1326 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1327 saved_hard_reg = 1, offset += 4; \
1328 for (regno = 16; regno <=23; regno++) \
1329 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1330 offset += 12; \
1331 } \
1332 if ((FROM) == FRAME_POINTER_REGNUM) \
1333 (OFFSET) = -offset; \
1334 else \
1335 { \
1336 if (! frame_pointer_needed) \
1337 offset -= 16; \
1338 if (! volatile_func \
1339 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1340 offset += 4; \
1341 offset += current_function_outgoing_args_size; \
1342 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1343 } \
1344 } \
1345 }
1346
1347 /* Output assembler code for a block containing the constant parts
1348 of a trampoline, leaving space for the variable parts.
1349
1350 On the ARM, (if r8 is the static chain regnum, and remembering that
1351 referencing pc adds an offset of 8) the trampoline looks like:
1352 ldr r8, [pc, #0]
1353 ldr pc, [pc]
1354 .word static chain value
1355 .word function's address
1356 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1357 #define TRAMPOLINE_TEMPLATE(FILE) \
1358 { \
1359 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1360 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1361 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1362 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1363 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1364 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1365 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1366 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1367 }
1368
1369 /* Length in units of the trampoline for entering a nested function. */
1370 #define TRAMPOLINE_SIZE 16
1371
1372 /* Alignment required for a trampoline in units. */
1373 #define TRAMPOLINE_ALIGN 4
1374
1375 /* Emit RTL insns to initialize the variable parts of a trampoline.
1376 FNADDR is an RTX for the address of the function's pure code.
1377 CXT is an RTX for the static chain value for the function. */
1378 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1379 { \
1380 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1381 (CXT)); \
1382 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1383 (FNADDR)); \
1384 }
1385
1386 \f
1387 /* Addressing modes, and classification of registers for them. */
1388
1389 #define HAVE_POST_INCREMENT 1
1390 #define HAVE_PRE_INCREMENT 1
1391 #define HAVE_POST_DECREMENT 1
1392 #define HAVE_PRE_DECREMENT 1
1393
1394 /* Macros to check register numbers against specific register classes. */
1395
1396 /* These assume that REGNO is a hard or pseudo reg number.
1397 They give nonzero only if REGNO is a hard reg of the suitable class
1398 or a pseudo reg currently allocated to a suitable hard reg.
1399 Since they use reg_renumber, they are safe only once reg_renumber
1400 has been allocated, which happens in local-alloc.c.
1401
1402 On the ARM, don't allow the pc to be used. */
1403 #define REGNO_OK_FOR_BASE_P(REGNO) \
1404 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1405 || (REGNO) == ARG_POINTER_REGNUM \
1406 || (unsigned) reg_renumber[(REGNO)] < 15 \
1407 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1408 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1409 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1410 REGNO_OK_FOR_BASE_P(REGNO)
1411
1412 /* Maximum number of registers that can appear in a valid memory address.
1413 Shifts in addresses can't be by a register. */
1414
1415 #define MAX_REGS_PER_ADDRESS 2
1416
1417 /* Recognize any constant value that is a valid address. */
1418 /* XXX We can address any constant, eventually... */
1419
1420 #ifdef AOF_ASSEMBLER
1421
1422 #define CONSTANT_ADDRESS_P(X) \
1423 (GET_CODE (X) == SYMBOL_REF \
1424 && CONSTANT_POOL_ADDRESS_P (X))
1425
1426 #else
1427
1428 #define CONSTANT_ADDRESS_P(X) \
1429 (GET_CODE (X) == SYMBOL_REF \
1430 && (CONSTANT_POOL_ADDRESS_P (X) \
1431 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1432
1433 #endif /* AOF_ASSEMBLER */
1434
1435 /* Nonzero if the constant value X is a legitimate general operand.
1436 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1437
1438 On the ARM, allow any integer (invalid ones are removed later by insn
1439 patterns), nice doubles and symbol_refs which refer to the function's
1440 constant pool XXX. */
1441 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1442
1443 /* Symbols in the text segment can be accessed without indirecting via the
1444 constant pool; it may take an extra binary operation, but this is still
1445 faster than indirecting via memory. Don't do this when not optimizing,
1446 since we won't be calculating al of the offsets necessary to do this
1447 simplification. */
1448 /* This doesn't work with AOF syntax, since the string table may be in
1449 a different AREA. */
1450 #ifndef AOF_ASSEMBLER
1451 #define ENCODE_SECTION_INFO(decl) \
1452 { \
1453 if (optimize > 0 && TREE_CONSTANT (decl) \
1454 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1455 { \
1456 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1457 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1458 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1459 } \
1460 }
1461 #endif
1462
1463 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1464 and check its validity for a certain class.
1465 We have two alternate definitions for each of them.
1466 The usual definition accepts all pseudo regs; the other rejects
1467 them unless they have been allocated suitable hard regs.
1468 The symbol REG_OK_STRICT causes the latter definition to be used. */
1469 #ifndef REG_OK_STRICT
1470
1471 /* Nonzero if X is a hard reg that can be used as a base reg
1472 or if it is a pseudo reg. */
1473 #define REG_OK_FOR_BASE_P(X) \
1474 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1475 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1476
1477 /* Nonzero if X is a hard reg that can be used as an index
1478 or if it is a pseudo reg. */
1479 #define REG_OK_FOR_INDEX_P(X) \
1480 REG_OK_FOR_BASE_P(X)
1481
1482 #define REG_OK_FOR_PRE_POST_P(X) \
1483 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1484 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1485
1486 #else
1487
1488 /* Nonzero if X is a hard reg that can be used as a base reg. */
1489 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1490
1491 /* Nonzero if X is a hard reg that can be used as an index. */
1492 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1493
1494 #define REG_OK_FOR_PRE_POST_P(X) \
1495 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1496 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1497 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1498 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1499
1500 #endif
1501 \f
1502 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1503 that is a valid memory address for an instruction.
1504 The MODE argument is the machine mode for the MEM expression
1505 that wants to use this address.
1506
1507 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1508 #define BASE_REGISTER_RTX_P(X) \
1509 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1510
1511 #define INDEX_REGISTER_RTX_P(X) \
1512 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1513
1514 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1515 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1516 only be small constants. */
1517 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1518 do \
1519 { \
1520 HOST_WIDE_INT range; \
1521 enum rtx_code code = GET_CODE (INDEX); \
1522 \
1523 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1524 { \
1525 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1526 && INTVAL (INDEX) > -1024 \
1527 && (INTVAL (INDEX) & 3) == 0) \
1528 goto LABEL; \
1529 } \
1530 else \
1531 { \
1532 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1533 goto LABEL; \
1534 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1535 && (! arm_arch4 || (MODE) != HImode)) \
1536 { \
1537 rtx xiop0 = XEXP (INDEX, 0); \
1538 rtx xiop1 = XEXP (INDEX, 1); \
1539 if (INDEX_REGISTER_RTX_P (xiop0) \
1540 && power_of_two_operand (xiop1, SImode)) \
1541 goto LABEL; \
1542 if (INDEX_REGISTER_RTX_P (xiop1) \
1543 && power_of_two_operand (xiop0, SImode)) \
1544 goto LABEL; \
1545 } \
1546 if (GET_MODE_SIZE (MODE) <= 4 \
1547 && (code == LSHIFTRT || code == ASHIFTRT \
1548 || code == ASHIFT || code == ROTATERT) \
1549 && (! arm_arch4 || (MODE) != HImode)) \
1550 { \
1551 rtx op = XEXP (INDEX, 1); \
1552 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1553 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1554 && INTVAL (op) <= 31) \
1555 goto LABEL; \
1556 } \
1557 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1558 range = ((MODE) == HImode || (MODE) == QImode) \
1559 ? (arm_arch4 ? 256 : 4095) : 4096; \
1560 if (code == CONST_INT && INTVAL (INDEX) < range \
1561 && INTVAL (INDEX) > -range) \
1562 goto LABEL; \
1563 } \
1564 } \
1565 while (0)
1566
1567 /* Jump to LABEL if X is a valid address RTX. This must also take
1568 REG_OK_STRICT into account when deciding about valid registers, but it uses
1569 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1570 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1571 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1572 refs must be forced though a static cell to ensure addressability. */
1573 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1574 { \
1575 if (BASE_REGISTER_RTX_P (X)) \
1576 goto LABEL; \
1577 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1578 && GET_CODE (XEXP (X, 0)) == REG \
1579 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1580 goto LABEL; \
1581 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1582 && (GET_CODE (X) == LABEL_REF \
1583 || (GET_CODE (X) == CONST \
1584 && GET_CODE (XEXP ((X), 0)) == PLUS \
1585 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1586 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1587 goto LABEL; \
1588 else if ((MODE) == TImode) \
1589 ; \
1590 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1591 { \
1592 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1593 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1594 { \
1595 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1596 if (val == 4 || val == -4 || val == -8) \
1597 goto LABEL; \
1598 } \
1599 } \
1600 else if (GET_CODE (X) == PLUS) \
1601 { \
1602 rtx xop0 = XEXP(X,0); \
1603 rtx xop1 = XEXP(X,1); \
1604 \
1605 if (BASE_REGISTER_RTX_P (xop0)) \
1606 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1607 else if (BASE_REGISTER_RTX_P (xop1)) \
1608 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1609 } \
1610 /* Reload currently can't handle MINUS, so disable this for now */ \
1611 /* else if (GET_CODE (X) == MINUS) \
1612 { \
1613 rtx xop0 = XEXP (X,0); \
1614 rtx xop1 = XEXP (X,1); \
1615 \
1616 if (BASE_REGISTER_RTX_P (xop0)) \
1617 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1618 } */ \
1619 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1620 && GET_CODE (X) == SYMBOL_REF \
1621 && CONSTANT_POOL_ADDRESS_P (X) \
1622 && ! (flag_pic \
1623 && symbol_mentioned_p (get_pool_constant (X)))) \
1624 goto LABEL; \
1625 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1626 && (GET_MODE_SIZE (MODE) <= 4) \
1627 && GET_CODE (XEXP (X, 0)) == REG \
1628 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1629 goto LABEL; \
1630 }
1631 \f
1632 /* Try machine-dependent ways of modifying an illegitimate address
1633 to be legitimate. If we find one, return the new, valid address.
1634 This macro is used in only one place: `memory_address' in explow.c.
1635
1636 OLDX is the address as it was before break_out_memory_refs was called.
1637 In some cases it is useful to look at this to decide what needs to be done.
1638
1639 MODE and WIN are passed so that this macro can use
1640 GO_IF_LEGITIMATE_ADDRESS.
1641
1642 It is always safe for this macro to do nothing. It exists to recognize
1643 opportunities to optimize the output.
1644
1645 On the ARM, try to convert [REG, #BIGCONST]
1646 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1647 where VALIDCONST == 0 in case of TImode. */
1648 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1649 { \
1650 if (GET_CODE (X) == PLUS) \
1651 { \
1652 rtx xop0 = XEXP (X, 0); \
1653 rtx xop1 = XEXP (X, 1); \
1654 \
1655 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1656 xop0 = force_reg (SImode, xop0); \
1657 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1658 xop1 = force_reg (SImode, xop1); \
1659 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1660 { \
1661 HOST_WIDE_INT n, low_n; \
1662 rtx base_reg, val; \
1663 n = INTVAL (xop1); \
1664 \
1665 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1666 { \
1667 low_n = n & 0x0f; \
1668 n &= ~0x0f; \
1669 if (low_n > 4) \
1670 { \
1671 n += 16; \
1672 low_n -= 16; \
1673 } \
1674 } \
1675 else \
1676 { \
1677 low_n = ((MODE) == TImode ? 0 \
1678 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1679 n -= low_n; \
1680 } \
1681 base_reg = gen_reg_rtx (SImode); \
1682 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1683 GEN_INT (n)), NULL_RTX); \
1684 emit_move_insn (base_reg, val); \
1685 (X) = (low_n == 0 ? base_reg \
1686 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1687 } \
1688 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1689 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1690 } \
1691 else if (GET_CODE (X) == MINUS) \
1692 { \
1693 rtx xop0 = XEXP (X, 0); \
1694 rtx xop1 = XEXP (X, 1); \
1695 \
1696 if (CONSTANT_P (xop0)) \
1697 xop0 = force_reg (SImode, xop0); \
1698 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1699 xop1 = force_reg (SImode, xop1); \
1700 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1701 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1702 } \
1703 if (flag_pic) \
1704 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1705 if (memory_address_p (MODE, X)) \
1706 goto WIN; \
1707 }
1708
1709 /* Go to LABEL if ADDR (a legitimate address expression)
1710 has an effect that depends on the machine mode it is used for. */
1711 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1712 { \
1713 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1714 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1715 goto LABEL; \
1716 }
1717 \f
1718 /* Specify the machine mode that this machine uses
1719 for the index in the tablejump instruction. */
1720 #define CASE_VECTOR_MODE SImode
1721
1722 /* Define as C expression which evaluates to nonzero if the tablejump
1723 instruction expects the table to contain offsets from the address of the
1724 table.
1725 Do not define this if the table should contain absolute addresses. */
1726 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1727
1728 /* Specify the tree operation to be used to convert reals to integers. */
1729 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1730
1731 /* This is the kind of divide that is easiest to do in the general case. */
1732 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1733
1734 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1735 unsigned is probably best, but may break some code. */
1736 #ifndef DEFAULT_SIGNED_CHAR
1737 #define DEFAULT_SIGNED_CHAR 0
1738 #endif
1739
1740 /* Don't cse the address of the function being compiled. */
1741 #define NO_RECURSIVE_FUNCTION_CSE 1
1742
1743 /* Max number of bytes we can move from memory to memory
1744 in one reasonably fast instruction. */
1745 #define MOVE_MAX 4
1746
1747 /* Define if operations between registers always perform the operation
1748 on the full register even if a narrower mode is specified. */
1749 #define WORD_REGISTER_OPERATIONS
1750
1751 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1752 will either zero-extend or sign-extend. The value of this macro should
1753 be the code that says which one of the two operations is implicitly
1754 done, NIL if none. */
1755 #define LOAD_EXTEND_OP(MODE) \
1756 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1757 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1758
1759 /* Define this if zero-extension is slow (more than one real instruction).
1760 On the ARM, it is more than one instruction only if not fetching from
1761 memory. */
1762 /* #define SLOW_ZERO_EXTEND */
1763
1764 /* Nonzero if access to memory by bytes is slow and undesirable. */
1765 #define SLOW_BYTE_ACCESS 0
1766
1767 /* Immediate shift counts are truncated by the output routines (or was it
1768 the assembler?). Shift counts in a register are truncated by ARM. Note
1769 that the native compiler puts too large (> 32) immediate shift counts
1770 into a register and shifts by the register, letting the ARM decide what
1771 to do instead of doing that itself. */
1772 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1773 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1774 On the arm, Y in a register is used modulo 256 for the shift. Only for
1775 rotates is modulo 32 used. */
1776 /* #define SHIFT_COUNT_TRUNCATED 1 */
1777
1778 /* All integers have the same format so truncation is easy. */
1779 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1780
1781 /* Calling from registers is a massive pain. */
1782 #define NO_FUNCTION_CSE 1
1783
1784 /* Chars and shorts should be passed as ints. */
1785 #define PROMOTE_PROTOTYPES 1
1786
1787 /* The machine modes of pointers and functions */
1788 #define Pmode SImode
1789 #define FUNCTION_MODE Pmode
1790
1791 /* The structure type of the machine dependent info field of insns
1792 No uses for this yet. */
1793 /* #define INSN_MACHINE_INFO struct machine_info */
1794
1795 /* The relative costs of various types of constants. Note that cse.c defines
1796 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1797 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1798 case CONST_INT: \
1799 if (const_ok_for_arm (INTVAL (RTX))) \
1800 return (OUTER_CODE) == SET ? 2 : -1; \
1801 else if (OUTER_CODE == AND \
1802 && const_ok_for_arm (~INTVAL (RTX))) \
1803 return -1; \
1804 else if ((OUTER_CODE == COMPARE \
1805 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1806 && const_ok_for_arm (-INTVAL (RTX))) \
1807 return -1; \
1808 else \
1809 return 5; \
1810 case CONST: \
1811 case LABEL_REF: \
1812 case SYMBOL_REF: \
1813 return 6; \
1814 case CONST_DOUBLE: \
1815 if (const_double_rtx_ok_for_fpu (RTX)) \
1816 return (OUTER_CODE) == SET ? 2 : -1; \
1817 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1818 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1819 return -1; \
1820 return(7);
1821
1822 #define ARM_FRAME_RTX(X) \
1823 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1824 || (X) == arg_pointer_rtx)
1825
1826 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1827 return arm_rtx_costs (X, CODE);
1828
1829 /* Moves to and from memory are quite expensive */
1830 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1831
1832 /* All address computations that can be done are free, but rtx cost returns
1833 the same for practically all of them. So we weight the different types
1834 of address here in the order (most pref first):
1835 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1836 #define ADDRESS_COST(X) \
1837 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1838 || GET_CODE (X) == SYMBOL_REF) \
1839 ? 0 \
1840 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1841 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1842 ? 10 \
1843 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1844 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1845 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1846 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1847 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1848 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1849 ? 1 : 0)) \
1850 : 4)))))
1851
1852 /* Try to generate sequences that don't involve branches, we can then use
1853 conditional instructions */
1854 #define BRANCH_COST 4
1855
1856 /* A C statement to update the variable COST based on the relationship
1857 between INSN that is dependent on DEP through dependence LINK. */
1858 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1859 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1860 \f
1861 /* Position Independent Code. */
1862 /* We decide which register to use based on the compilation options and
1863 the assembler in use; this is more general than the APCS restriction of
1864 using sb (r9) all the time. */
1865 extern int arm_pic_register;
1866
1867 /* Used when parsing command line option -mpic-register=. */
1868 extern const char * arm_pic_register_string;
1869
1870 /* The register number of the register used to address a table of static
1871 data addresses in memory. */
1872 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1873
1874 #define FINALIZE_PIC arm_finalize_pic ()
1875
1876 /* We can't directly access anything that contains a symbol,
1877 nor can we indirect via the constant pool. */
1878 #define LEGITIMATE_PIC_OPERAND_P(X) \
1879 (! symbol_mentioned_p (X) \
1880 && (! CONSTANT_POOL_ADDRESS_P (X) \
1881 || ! symbol_mentioned_p (get_pool_constant (X))))
1882
1883 /* We need to know when we are making a constant pool; this determines
1884 whether data needs to be in the GOT or can be referenced via a GOT
1885 offset. */
1886 extern int making_const_table;
1887
1888 \f
1889 /* Condition code information. */
1890 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1891 return the mode to be used for the comparison.
1892 CCFPEmode should be used with floating inequalities,
1893 CCFPmode should be used with floating equalities.
1894 CC_NOOVmode should be used with SImode integer equalities.
1895 CC_Zmode should be used if only the Z flag is set correctly
1896 CCmode should be used otherwise. */
1897
1898 #define EXTRA_CC_MODES \
1899 CC(CC_NOOVmode, "CC_NOOV") \
1900 CC(CC_Zmode, "CC_Z") \
1901 CC(CC_SWPmode, "CC_SWP") \
1902 CC(CCFPmode, "CCFP") \
1903 CC(CCFPEmode, "CCFPE") \
1904 CC(CC_DNEmode, "CC_DNE") \
1905 CC(CC_DEQmode, "CC_DEQ") \
1906 CC(CC_DLEmode, "CC_DLE") \
1907 CC(CC_DLTmode, "CC_DLT") \
1908 CC(CC_DGEmode, "CC_DGE") \
1909 CC(CC_DGTmode, "CC_DGT") \
1910 CC(CC_DLEUmode, "CC_DLEU") \
1911 CC(CC_DLTUmode, "CC_DLTU") \
1912 CC(CC_DGEUmode, "CC_DGEU") \
1913 CC(CC_DGTUmode, "CC_DGTU") \
1914 CC(CC_Cmode, "CC_C")
1915
1916 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1917
1918 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1919
1920 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1921 do \
1922 { \
1923 if (GET_CODE (OP1) == CONST_INT \
1924 && ! (const_ok_for_arm (INTVAL (OP1)) \
1925 || (const_ok_for_arm (- INTVAL (OP1))))) \
1926 { \
1927 rtx const_op = OP1; \
1928 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1929 OP1 = const_op; \
1930 } \
1931 } \
1932 while (0)
1933
1934 #define STORE_FLAG_VALUE 1
1935
1936 /* Define the information needed to generate branch insns. This is
1937 stored from the compare operation. Note that we can't use "rtx" here
1938 since it hasn't been defined! */
1939
1940 extern struct rtx_def * arm_compare_op0;
1941 extern struct rtx_def * arm_compare_op1;
1942
1943 /* Define the codes that are matched by predicates in arm.c */
1944 #define PREDICATE_CODES \
1945 {"s_register_operand", {SUBREG, REG}}, \
1946 {"f_register_operand", {SUBREG, REG}}, \
1947 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1948 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1949 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1950 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1951 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1952 {"offsettable_memory_operand", {MEM}}, \
1953 {"bad_signed_byte_operand", {MEM}}, \
1954 {"alignable_memory_operand", {MEM}}, \
1955 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1956 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1957 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1958 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1959 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1960 {"load_multiple_operation", {PARALLEL}}, \
1961 {"store_multiple_operation", {PARALLEL}}, \
1962 {"equality_operator", {EQ, NE}}, \
1963 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1964 {"const_shift_operand", {CONST_INT}}, \
1965 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1966 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1967 {"multi_register_push", {PARALLEL}}, \
1968 {"cc_register", {REG}}, \
1969 {"logical_binary_operator", {AND, IOR, XOR}}, \
1970 {"dominant_cc_register", {REG}},
1971
1972 \f
1973
1974 /* Gcc puts the pool in the wrong place for ARM, since we can only
1975 load addresses a limited distance around the pc. We do some
1976 special munging to move the constant pool values to the correct
1977 point in the code. */
1978 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1979
1980 /* Output an internal label definition. */
1981 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1982 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1983 do \
1984 { \
1985 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1986 \
1987 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1988 && !strcmp (PREFIX, "L")) \
1989 { \
1990 arm_ccfsm_state = 0; \
1991 arm_target_insn = NULL; \
1992 } \
1993 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1994 ASM_OUTPUT_LABEL (STREAM, s); \
1995 } \
1996 while (0)
1997 #endif
1998
1999 /* Output a push or a pop instruction (only used when profiling). */
2000 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2001 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2002
2003 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2004 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
2005
2006 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2007 do \
2008 { \
2009 if (TARGET_POKE_FUNCTION_NAME) \
2010 arm_poke_function_name (STREAM, NAME); \
2011 } \
2012 while (0)
2013
2014 /* Target characters. */
2015 #define TARGET_BELL 007
2016 #define TARGET_BS 010
2017 #define TARGET_TAB 011
2018 #define TARGET_NEWLINE 012
2019 #define TARGET_VT 013
2020 #define TARGET_FF 014
2021 #define TARGET_CR 015
2022 \f
2023 /* Only perform branch elimination (by making instructions conditional) if
2024 we're optimising. Otherwise it's of no use anyway. */
2025 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2026 if (optimize) \
2027 arm_final_prescan_insn (INSN)
2028
2029 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2030 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2031
2032 /* Output an operand of an instruction. */
2033 #define PRINT_OPERAND(STREAM, X, CODE) \
2034 arm_print_operand (STREAM, X, CODE)
2035
2036 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2037 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2038 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffffUL) | \
2039 (((x) & (unsigned HOST_WIDE_INT) 0x80000000UL) \
2040 ? ((~ (HOST_WIDE_INT) 0) \
2041 & ~ (unsigned HOST_WIDE_INT) 0xffffffffUL) \
2042 : 0))))
2043
2044 /* Output the address of an operand. */
2045 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2046 { \
2047 int is_minus = GET_CODE (X) == MINUS; \
2048 \
2049 if (GET_CODE (X) == REG) \
2050 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2051 else if (GET_CODE (X) == PLUS || is_minus) \
2052 { \
2053 rtx base = XEXP (X, 0); \
2054 rtx index = XEXP (X, 1); \
2055 int base_reg; \
2056 HOST_WIDE_INT offset = 0; \
2057 if (GET_CODE (base) != REG) \
2058 { \
2059 /* Ensure that BASE is a register (one of them must be). */ \
2060 rtx temp = base; \
2061 base = index; \
2062 index = temp; \
2063 } \
2064 base_reg = REGNO (base); \
2065 switch (GET_CODE (index)) \
2066 { \
2067 case CONST_INT: \
2068 offset = INTVAL (index); \
2069 if (is_minus) \
2070 offset = -offset; \
2071 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2072 break; \
2073 \
2074 case REG: \
2075 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2076 is_minus ? "-" : "", REGNO (index)); \
2077 break; \
2078 \
2079 case MULT: \
2080 case ASHIFTRT: \
2081 case LSHIFTRT: \
2082 case ASHIFT: \
2083 case ROTATERT: \
2084 { \
2085 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2086 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2087 arm_print_operand (STREAM, index, 'S'); \
2088 fputs ("]", STREAM); \
2089 break; \
2090 } \
2091 \
2092 default: \
2093 abort(); \
2094 } \
2095 } \
2096 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2097 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2098 { \
2099 extern int output_memory_reference_mode; \
2100 \
2101 if (GET_CODE (XEXP (X, 0)) != REG) \
2102 abort (); \
2103 \
2104 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2105 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2106 REGNO (XEXP (X, 0)), \
2107 GET_CODE (X) == PRE_DEC ? "-" : "", \
2108 GET_MODE_SIZE (output_memory_reference_mode)); \
2109 else \
2110 asm_fprintf (STREAM, "[%r], #%s%d", \
2111 REGNO (XEXP (X, 0)), \
2112 GET_CODE (X) == POST_DEC ? "-" : "", \
2113 GET_MODE_SIZE (output_memory_reference_mode)); \
2114 } \
2115 else output_addr_const (STREAM, X); \
2116 }
2117
2118 /* Handles PIC addr specially */
2119 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2120 { \
2121 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2122 { \
2123 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2124 fputs (" - (", STREAM); \
2125 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2126 fputs (")", STREAM); \
2127 } \
2128 else output_addr_const (STREAM, X); \
2129 \
2130 /* Mark symbols as position independent. We only do this in the \
2131 .text segment, not in the .data segment. */ \
2132 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2133 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2134 { \
2135 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2136 fprintf (STREAM, "(GOTOFF)"); \
2137 else if (GET_CODE (X) == LABEL_REF) \
2138 fprintf (STREAM, "(GOTOFF)"); \
2139 else \
2140 fprintf (STREAM, "(GOT)"); \
2141 } \
2142 }
2143
2144 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2145 Used for C++ multiple inheritance. */
2146 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2147 do \
2148 { \
2149 int mi_delta = (DELTA); \
2150 char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2151 int shift = 0; \
2152 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2153 ? 1 : 0); \
2154 if (mi_delta < 0) mi_delta = -mi_delta; \
2155 while (mi_delta != 0) \
2156 { \
2157 if (mi_delta & (3 << shift) == 0) \
2158 shift += 2; \
2159 else \
2160 { \
2161 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2162 mi_op, this_regno, this_regno, \
2163 mi_delta & (0xff << shift)); \
2164 mi_delta &= ~(0xff << shift); \
2165 shift += 8; \
2166 } \
2167 } \
2168 fputs ("\tb\t", FILE); \
2169 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2170 if (NEED_PLT_RELOC) \
2171 fputs ("(PLT)", FILE); \
2172 fputc ('\n', FILE); \
2173 } \
2174 while (0)
2175
2176 /* A C expression whose value is RTL representing the value of the return
2177 address for the frame COUNT steps up from the current frame. */
2178
2179 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2180 ((COUNT == 0) \
2181 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2182 : NULL_RTX)
2183
2184 /* Used to mask out junk bits from the return address, such as
2185 processor state, interrupt status, condition codes and the like. */
2186 #define MASK_RETURN_ADDR \
2187 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2188 in 26 bit mode, the condition codes must be masked out of the \
2189 return address. This does not apply to ARM6 and later processors \
2190 when running in 32 bit mode. */ \
2191 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2192
2193 #endif /* __ARM_H__ */
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