| blob | d7ae3ea582361a20447f6fdb623c209c9484939f |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshhold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
252 #if 0
254 #endif
284 rtx *));
368 {
369 rtx match;
370 rtx replacement;
371 rtx insn;
374 /* Nonzero iff INSN is between START and END, inclusive. */
375 #define INSN_IN_RANGE_P(INSN, START, END) \
376 (INSN_UID (INSN) < max_uid_for_loop \
377 && INSN_LUID (INSN) >= INSN_LUID (START) \
378 && INSN_LUID (INSN) <= INSN_LUID (END))
380 /* Indirect_jump_in_function is computed once per function. */
388 rtx));
389 \f
390 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
391 copy the value of the strength reduced giv to its original register. */
394 /* Cost of using a register, to normalize the benefits of a giv. */
397 void
399 {
405 }
406 \f
407 /* Compute the mapping from uids to luids.
408 LUIDs are numbers assigned to insns, like uids,
409 except that luids increase monotonically through the code.
410 Start at insn START and stop just before END. Assign LUIDs
411 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
412 static int
416 {
418 rtx insn;
421 {
424 /* Don't assign luids to line-number NOTEs, so that the distance in
425 luids between two insns is not affected by -g. */
429 else
430 /* Give a line number note the same luid as preceding insn. */
432 }
434 }
435 \f
436 /* Entry point of this file. Perform loop optimization
437 on the current function. F is the first insn of the function
438 and DUMPFILE is a stream for output of a trace of actions taken
439 (or 0 if none should be output). */
441 void
443 /* f is the first instruction of a chain of insns for one function */
444 rtx f;
447 {
448 rtx insn;
463 /* Count the number of loops. */
467 {
470 max_loop_num++;
471 }
473 /* Don't waste time if no loops. */
479 /* Get size to use for tables indexed by uids.
480 Leave some space for labels allocated by find_and_verify_loops. */
487 /* Allocate storage for array of loops. */
491 /* Find and process each loop.
492 First, find them, and record them in order of their beginnings. */
495 /* Allocate and initialize auxiliary loop information. */
500 /* Now find all register lifetimes. This must be done after
501 find_and_verify_loops, because it might reorder the insns in the
502 function. */
505 /* This must occur after reg_scan so that registers created by gcse
506 will have entries in the register tables.
508 We could have added a call to reg_scan after gcse_main in toplev.c,
509 but moving this call to init_alias_analysis is more efficient. */
512 /* See if we went too far. Note that get_max_uid already returns
513 one more that the maximum uid of all insn. */
516 /* Now reset it to the actual size we need. See above. */
519 /* find_and_verify_loops has already called compute_luids, but it
520 might have rearranged code afterwards, so we need to recompute
521 the luids now. */
524 /* Don't leave gaps in uid_luid for insns that have been
525 deleted. It is possible that the first or last insn
526 using some register has been deleted by cross-jumping.
527 Make sure that uid_luid for that former insn's uid
528 points to the general area where that insn used to be. */
530 {
534 }
539 /* Determine if the function has indirect jump. On some systems
540 this prevents low overhead loop instructions from being used. */
543 /* Now scan the loops, last ones first, since this means inner ones are done
544 before outer ones. */
546 {
551 }
555 /* Clean up. */
560 }
561 \f
562 /* Returns the next insn, in execution order, after INSN. START and
563 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
564 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
565 insn-stream; it is used with loops that are entered near the
566 bottom. */
568 static rtx
571 rtx insn;
572 {
576 {
578 /* Go to the top of the loop, and continue there. */
580 else
581 /* We're done. */
583 }
586 /* We're done. */
590 }
592 /* Optimize one loop described by LOOP. */
594 /* ??? Could also move memory writes out of loops if the destination address
595 is invariant, the source is invariant, the memory write is not volatile,
596 and if we can prove that no read inside the loop can read this address
597 before the write occurs. If there is a read of this address after the
598 write, then we can also mark the memory read as invariant. */
600 static void
604 {
610 rtx p;
611 /* 1 if we are scanning insns that could be executed zero times. */
613 /* 1 if we are scanning insns that might never be executed
614 due to a subroutine call which might exit before they are reached. */
616 /* Number of insns in the loop. */
620 /* The SET from an insn, if it is the only SET in the insn. */
622 /* Chain describing insns movable in current loop. */
624 /* Ratio of extra register life span we can justify
625 for saving an instruction. More if loop doesn't call subroutines
626 since in that case saving an insn makes more difference
627 and more registers are available. */
629 /* Nonzero if we are scanning instructions in a sub-loop. */
638 /* Determine whether this loop starts with a jump down to a test at
639 the end. This will occur for a small number of loops with a test
640 that is too complex to duplicate in front of the loop.
642 We search for the first insn or label in the loop, skipping NOTEs.
643 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
644 (because we might have a loop executed only once that contains a
645 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
646 (in case we have a degenerate loop).
648 Note that if we mistakenly think that a loop is entered at the top
649 when, in fact, it is entered at the exit test, the only effect will be
650 slightly poorer optimization. Making the opposite error can generate
651 incorrect code. Since very few loops now start with a jump to the
652 exit test, the code here to detect that case is very conservative. */
655 p != loop_end
661 ;
665 /* If loop end is the end of the current function, then emit a
666 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
667 note insn. This is the position we use when sinking insns out of
668 the loop. */
671 else
674 /* Set up variables describing this loop. */
678 /* If loop has a jump before the first label,
679 the true entry is the target of that jump.
680 Start scan from there.
681 But record in LOOP->TOP the place where the end-test jumps
682 back to so we can scan that after the end of the loop. */
684 /* Loop entry must be unconditional jump (and not a RETURN) */
687 /* Check to see whether the jump actually
688 jumps out of the loop (meaning it's no loop).
689 This case can happen for things like
690 do {..} while (0). If this label was generated previously
691 by loop, we can't tell anything about it and have to reject
692 the loop. */
694 {
697 }
699 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
700 as required by loop_reg_used_before_p. So skip such loops. (This
701 test may never be true, but it's best to play it safe.)
703 Also, skip loops where we do not start scanning at a label. This
704 test also rejects loops starting with a JUMP_INSN that failed the
705 test above. */
709 {
714 }
716 /* Allocate extra space for REGs that might be created by load_mems.
717 We allocate a little extra slop as well, in the hopes that we
718 won't have to reallocate the regs array. */
723 {
729 }
731 /* Scan through the loop finding insns that are safe to move.
732 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
733 this reg will be considered invariant for subsequent insns.
734 We consider whether subsequent insns use the reg
735 in deciding whether it is worth actually moving.
737 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
738 and therefore it is possible that the insns we are scanning
739 would never be executed. At such times, we must make sure
740 that it is safe to execute the insn once instead of zero times.
741 When MAYBE_NEVER is 0, all insns will be executed at least once
742 so that is not a problem. */
747 {
749 in_libcall--;
751 {
754 in_libcall++;
758 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
760 #endif
762 {
770 /* Figure out what to use as a source of this insn. If a
771 REG_EQUIV note is given or if a REG_EQUAL note with a
772 constant operand is specified, use it as the source and
773 mark that we should move this insn by calling
774 emit_move_insn rather that duplicating the insn.
776 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
777 note is present. */
781 else
782 {
787 {
789 /* A libcall block can use regs that don't appear in
790 the equivalent expression. To move the libcall,
791 we must move those regs too. */
793 }
794 }
796 /* For parallels, add any possible uses to the dependencies, as
797 we can't move the insn without resolving them first. */
799 {
801 {
804 dependencies
806 dependencies);
807 }
808 }
811 than the one where it is set (meaning that
812 something after this point in the loop might
813 depend on its value before the set). */
815 /* And the set is not guaranteed to be executed once
816 the loop starts, or the value before the set is
817 needed before the set occurs...
819 ??? Note we have quadratic behavior here, mitigated
820 by the fact that the previous test will often fail for
821 large loops. Rather than re-scanning the entire loop
822 each time for register usage, we should build tables
823 of the register usage and use them here instead. */
824 && (maybe_never
826 /* It is unsafe to move the set. However, it may be OK to
827 move the source into a new pseudo, and substitute a
828 reg-to-reg copy for the original insn.
830 This code used to consider it OK to move a set of a variable
831 which was not created by the user and not used in an exit
832 test.
833 That behavior is incorrect and was removed. */
836 /* Don't try to optimize a register that was made
837 by loop-optimization for an inner loop.
838 We don't know its life-span, so we can't compute
839 the benefit. */
841 ;
842 /* Don't move the source and add a reg-to-reg copy:
843 - with -Os (this certainly increases size),
844 - if the mode doesn't support copy operations (obviously),
845 - if the source is already a reg (the motion will gain nothing),
846 - if the source is a legitimate constant (likewise). */
848 && (optimize_size
853 ;
856 || (tem2
859 || (tem1
860 = consec_sets_invariant_p
863 p)))
864 /* If the insn can cause a trap (such as divide by zero),
865 can't move it unless it's guaranteed to be executed
866 once loop is entered. Even a function call might
867 prevent the trap insn from being reached
868 (since it might exit!) */
871 {
875 /* A potential lossage is where we have a case where two insns
876 can be combined as long as they are both in the loop, but
877 we move one of them outside the loop. For large loops,
878 this can lose. The most common case of this is the address
879 of a function being called.
881 Therefore, if this register is marked as being used
882 exactly once if we are in a loop with calls
883 (a "large loop"), see if we can replace the usage of
884 this register with the source of this SET. If we can,
885 delete this insn.
887 Don't do this if P has a REG_RETVAL note or if we have
888 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
900 && (! SMALL_REGISTER_CLASSES
904 /* This test is not redundant; SET_SRC (set) might be
905 a call-clobbered register and the life of REGNO
906 might span a call. */
913 {
914 /* Replace any usage in a REG_EQUAL note. Must copy
915 the new source, so that we don't get rtx sharing
916 between the SET_SOURCE and REG_NOTES of insn p. */
918 = (replace_rtx
924 i++)
927 }
936 m->consec
947 /* Set M->cond if either loop_invariant_p
948 or consec_sets_invariant_p returned 2
949 (only conditionally invariant). */
959 /* Add M to the end of the chain MOVABLES. */
963 {
964 /* It is possible for the first instruction to have a
965 REG_EQUAL note but a non-invariant SET_SRC, so we must
966 remember the status of the first instruction in case
967 the last instruction doesn't have a REG_EQUAL note. */
970 /* Skip this insn, not checking REG_LIBCALL notes. */
972 /* Skip the consecutive insns, if there are any. */
974 /* Back up to the last insn of the consecutive group. */
977 /* We must now reset m->move_insn, m->is_equiv, and
978 possibly m->set_src to correspond to the effects of
979 all the insns. */
983 else
984 {
988 else
991 }
992 m->is_equiv
994 }
995 }
996 /* If this register is always set within a STRICT_LOW_PART
997 or set to zero, then its high bytes are constant.
998 So clear them outside the loop and within the loop
999 just load the low bytes.
1000 We must check that the machine has an instruction to do so.
1001 Also, if the value loaded into the register
1002 depends on the same register, this cannot be done. */
1012 {
1015 {
1030 /* If the insn may not be executed on some cycles,
1031 we can't clear the whole reg; clear just high part.
1032 Not even if the reg is used only within this loop.
1033 Consider this:
1034 while (1)
1035 while (s != t) {
1036 if (foo ()) x = *s;
1037 use (x);
1038 }
1039 Clearing x before the inner loop could clobber a value
1040 being saved from the last time around the outer loop.
1041 However, if the reg is not used outside this loop
1042 and all uses of the register are in the same
1043 basic block as the store, there is no problem.
1045 If this insn was made by loop, we don't know its
1046 INSN_LUID and hence must make a conservative
1047 assumption. */
1050 || (labels_in_range_p
1054 else
1063 i++)
1065 /* Add M to the end of the chain MOVABLES. */
1067 }
1068 }
1069 }
1070 }
1071 /* Past a call insn, we get to insns which might not be executed
1072 because the call might exit. This matters for insns that trap.
1073 Constant and pure call insns always return, so they don't count. */
1076 /* Past a label or a jump, we get to insns for which we
1077 can't count on whether or how many times they will be
1078 executed during each iteration. Therefore, we can
1079 only move out sets of trivial variables
1080 (those not used after the loop). */
1081 /* Similar code appears twice in strength_reduce. */
1083 /* If we enter the loop in the middle, and scan around to the
1084 beginning, don't set maybe_never for that. This must be an
1085 unconditional jump, otherwise the code at the top of the
1086 loop might never be executed. Unconditional jumps are
1087 followed by a barrier then the loop_end. */
1093 {
1094 /* At the virtual top of a converted loop, insns are again known to
1095 be executed: logically, the loop begins here even though the exit
1096 code has been duplicated. */
1100 loop_depth++;
1102 loop_depth--;
1103 }
1104 }
1106 /* If one movable subsumes another, ignore that other. */
1110 /* For each movable insn, see if the reg that it loads
1111 leads when it dies right into another conditionally movable insn.
1112 If so, record that the second insn "forces" the first one,
1113 since the second can be moved only if the first is. */
1117 /* See if there are multiple movable insns that load the same value.
1118 If there are, make all but the first point at the first one
1119 through the `match' field, and add the priorities of them
1120 all together as the priority of the first. */
1124 /* Now consider each movable insn to decide whether it is worth moving.
1125 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1127 For machines with few registers this increases code size, so do not
1128 move moveables when optimizing for code size on such machines.
1129 (The 18 below is the value for i386.) */
1133 {
1136 /* Recalculate regs->array if move_movables has created new
1137 registers. */
1139 {
1145 ;
1150 }
1151 }
1153 /* Now candidates that still are negative are those not moved.
1154 Change regs->array[I].set_in_loop to indicate that those are not actually
1155 invariant. */
1160 /* Now that we've moved some things out of the loop, we might be able to
1161 hoist even more memory references. */
1164 /* Recalculate regs->array if load_mems has created new registers. */
1172 ;
1179 {
1181 /* Ensure our label doesn't go away. */
1192 }
1195 /* The movable information is required for strength reduction. */
1201 }
1202 \f
1203 /* Add elements to *OUTPUT to record all the pseudo-regs
1204 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1206 void
1210 {
1218 {
1236 }
1240 {
1244 {
1253 }
1254 }
1255 }
1256 \f
1257 /* Check what regs are referred to in the libcall block ending with INSN,
1258 aside from those mentioned in the equivalent value.
1259 If there are none, return 0.
1260 If there are one or more, return an EXPR_LIST containing all of them. */
1262 rtx
1265 {
1270 /* First, find all the regs used in the libcall block
1271 that are not mentioned as inputs to the result. */
1274 {
1279 }
1282 }
1283 \f
1284 /* Return 1 if all uses of REG
1285 are between INSN and the end of the basic block. */
1287 static int
1290 {
1292 rtx p;
1297 /* Search this basic block for the already recorded last use of the reg. */
1299 {
1301 {
1307 /* Ordinary insn: if this is the last use, we win. */
1313 /* Jump insn: if this is the last use, we win. */
1316 /* Otherwise, it's the end of the basic block, so we lose. */
1321 /* It's the end of the basic block, so we lose. */
1326 }
1327 }
1329 /* The "last use" that was recorded can't be found after the first
1330 use. This can happen when the last use was deleted while
1331 processing an inner loop, this inner loop was then completely
1332 unrolled, and the outer loop is always exited after the inner loop,
1333 so that everything after the first use becomes a single basic block. */
1335 }
1336 \f
1337 /* Compute the benefit of eliminating the insns in the block whose
1338 last insn is LAST. This may be a group of insns used to compute a
1339 value directly or can contain a library call. */
1341 static int
1343 rtx last;
1344 {
1345 rtx insn;
1350 {
1353 routine. */
1357 benefit++;
1358 }
1361 }
1362 \f
1363 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1365 static rtx
1367 rtx insn;
1369 {
1371 {
1372 rtx temp;
1374 /* If first insn of libcall sequence, skip to end. */
1375 /* Do this at start of loop, since INSN is guaranteed to
1376 be an insn here. */
1381 do
1384 }
1387 }
1389 /* Ignore any movable whose insn falls within a libcall
1390 which is part of another movable.
1391 We make use of the fact that the movable for the libcall value
1392 was made later and so appears later on the chain. */
1394 static void
1397 {
1401 {
1402 /* Is this a movable for the value of a libcall? */
1405 {
1406 rtx insn;
1407 /* Check for earlier movables inside that range,
1408 and mark them invalid. We cannot use LUIDs here because
1409 insns created by loop.c for prior loops don't have LUIDs.
1410 Rather than reject all such insns from movables, we just
1411 explicitly check each insn in the libcall (since invariant
1412 libcalls aren't that common). */
1417 }
1418 }
1419 }
1421 /* For each movable insn, see if the reg that it loads
1422 leads when it dies right into another conditionally movable insn.
1423 If so, record that the second insn "forces" the first one,
1424 since the second can be moved only if the first is. */
1426 static void
1429 {
1433 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1435 {
1438 /* ??? Could this be a bug? What if CSE caused the
1439 register of M1 to be used after this insn?
1440 Since CSE does not update regno_last_uid,
1441 this insn M->insn might not be where it dies.
1442 But very likely this doesn't matter; what matters is
1443 that M's reg is computed from M1's reg. */
1448 /* If m->consec, m->set_src isn't valid. */
1452 /* Increase the priority of the moving the first insn
1453 since it permits the second to be moved as well. */
1455 {
1459 }
1460 }
1461 }
1462 \f
1463 /* Find invariant expressions that are equal and can be combined into
1464 one register. */
1466 static void
1470 {
1475 /* Regs that are set more than once are not allowed to match
1476 or be matched. I'm no longer sure why not. */
1477 /* Only pseudo registers are allowed to match or be matched,
1478 since move_movables does not validate the change. */
1479 /* Perhaps testing m->consec_sets would be more appropriate here? */
1486 {
1493 /* We want later insns to match the first one. Don't make the first
1494 one match any later ones. So start this loop at m->next. */
1500 /* A reg used outside the loop mustn't be eliminated. */
1502 /* A reg used for zero-extending mustn't be eliminated. */
1505 ||
1506 (
1507 /* Can combine regs with different modes loaded from the
1508 same constant only if the modes are the same or
1509 if both are integer modes with M wider or the same
1510 width as M1. The check for integer is redundant, but
1511 safe, since the only case of differing destination
1512 modes with equal sources is when both sources are
1513 VOIDmode, i.e., CONST_INT. */
1519 /* See if the source of M1 says it matches M. */
1526 {
1532 }
1533 }
1535 /* Now combine the regs used for zero-extension.
1536 This can be done for those not marked `global'
1537 provided their lives don't overlap. */
1541 {
1544 /* Combine all the registers for extension from mode MODE.
1545 Don't combine any that are used outside this loop. */
1549 {
1556 {
1557 /* First one: don't check for overlap, just record it. */
1560 }
1562 /* Make sure they extend to the same mode.
1563 (Almost always true.) */
1567 /* We already have one: check for overlap with those
1568 already combined together. */
1575 /* No overlap: we can combine this with the others. */
1581 overlap:
1582 ;
1583 }
1584 }
1586 /* Clean up. */
1588 }
1590 /* Returns the number of movable instructions in LOOP that were not
1591 moved outside the loop. */
1593 static int
1596 {
1605 }
1607 \f
1608 /* Return 1 if regs X and Y will become the same if moved. */
1610 static int
1614 {
1631 }
1633 /* Return 1 if X and Y are identical-looking rtx's.
1634 This is the Lisp function EQUAL for rtx arguments.
1636 If two registers are matching movables or a movable register and an
1637 equivalent constant, consider them equal. */
1639 static int
1644 {
1658 /* If we have a register and a constant, they may sometimes be
1659 equal. */
1662 {
1667 }
1670 {
1675 }
1677 /* Otherwise, rtx's of different codes cannot be equal. */
1681 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1682 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1687 /* These three types of rtx's can be compared nonrecursively. */
1696 /* Compare the elements. If any pair of corresponding elements
1697 fail to match, return 0 for the whole things. */
1701 {
1703 {
1715 /* Two vectors must have the same length. */
1719 /* And the corresponding elements must match. */
1738 /* These are just backpointers, so they don't matter. */
1744 /* It is believed that rtx's at this level will never
1745 contain anything but integers and other rtx's,
1746 except for within LABEL_REFs and SYMBOL_REFs. */
1749 }
1750 }
1752 }
1753 \f
1754 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1755 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1756 references is incremented once for each added note. */
1758 static void
1760 rtx x;
1761 rtx insns;
1762 {
1766 rtx insn;
1769 {
1770 /* This code used to ignore labels that referred to dispatch tables to
1771 avoid flow generating (slighly) worse code.
1773 We no longer ignore such label references (see LABEL_REF handling in
1774 mark_jump_label for additional information). */
1777 {
1782 }
1783 }
1787 {
1793 }
1794 }
1795 \f
1796 /* Scan MOVABLES, and move the insns that deserve to be moved.
1797 If two matching movables are combined, replace one reg with the
1798 other throughout. */
1800 static void
1806 {
1811 rtx p;
1814 /* Map of pseudo-register replacements to handle combining
1815 when we move several insns that load the same value
1816 into different pseudo-registers. */
1821 {
1822 /* Describe this movable insn. */
1825 {
1846 }
1848 /* Ignore the insn if it's already done (it matched something else).
1849 Otherwise, see if it is now safe to move. */
1861 {
1863 rtx p;
1866 /* We have an insn that is safe to move.
1867 Compute its desirability. */
1878 /* An insn MUST be moved if we already moved something else
1879 which is safe only if this one is moved too: that is,
1880 if already_moved[REGNO] is nonzero. */
1882 /* An insn is desirable to move if the new lifetime of the
1883 register is no more than THRESHOLD times the old lifetime.
1884 If it's not desirable, it means the loop is so big
1885 that moving won't speed things up much,
1886 and it is liable to make register usage worse. */
1888 /* It is also desirable to move if it can be moved at no
1889 extra cost because something else was already moved. */
1892 || flag_move_all_movables
1897 {
1906 /* Now move the insns that set the reg. */
1909 {
1912 /* Find the end of this chain of matching regs.
1913 Thus, we load each reg in the chain from that one reg.
1914 And that reg is loaded with 0 directly,
1915 since it has ->match == 0. */
1921 /* Mark the moved, invariant reg as being allowed to
1922 share a hard reg with the other matching invariant. */
1926 regs_may_share
1929 regs_may_share));
1937 }
1938 /* If we are to re-generate the item being moved with a
1939 new move insn, first delete what we have and then emit
1940 the move insn before the loop. */
1942 {
1946 {
1947 /* If this is the first insn of a library call sequence,
1948 something is very wrong. */
1953 /* If this is the last insn of a libcall sequence, then
1954 delete every insn in the sequence except the last.
1955 The last insn is handled in the normal manner. */
1958 {
1962 }
1967 /* simplify_giv_expr expects that it can walk the insns
1968 at m->insn forwards and see this old sequence we are
1969 tossing here. delete_insn does preserve the next
1970 pointers, but when we skip over a NOTE we must fix
1971 it up. Otherwise that code walks into the non-deleted
1972 insn stream. */
1977 {
1978 /* Replace the original insn with a move from
1979 our newly created temp. */
1985 }
1986 }
2005 /* The more regs we move, the less we like moving them. */
2007 }
2008 else
2009 {
2011 {
2014 /* If first insn of libcall sequence, skip to end. */
2015 /* Do this at start of loop, since p is guaranteed to
2016 be an insn here. */
2021 /* If last insn of libcall sequence, move all
2022 insns except the last before the loop. The last
2023 insn is handled in the normal manner. */
2026 {
2034 {
2035 rtx body;
2036 rtx n;
2037 rtx next;
2044 /* Find the next insn after TEMP,
2045 not counting USE or NOTE insns. */
2053 /* If that is the call, this may be the insn
2054 that loads the function address.
2056 Extract the function address from the insn
2057 that loads it into a register.
2058 If this insn was cse'd, we get incorrect code.
2060 So emit a new move insn that copies the
2061 function address into the register that the
2062 call insn will use. flow.c will delete any
2063 redundant stores that we have created. */
2068 NULL_RTX)))
2069 {
2075 }
2076 /* We have the call insn.
2077 If it uses the register we suspect it might,
2078 load it with the correct address directly. */
2083 gen_move_insn
2087 {
2089 /* Because the USAGE information potentially
2090 contains objects other than hard registers
2091 we need to copy it. */
2095 }
2096 else
2105 }
2108 }
2110 {
2111 /* P sets REG to zero; but we should clear only
2112 the bits that are not covered by the mode
2113 m->savemode. */
2115 rtx sequence;
2116 rtx tem;
2119 tem = expand_simple_binop
2132 }
2134 {
2136 /* Because the USAGE information potentially
2137 contains objects other than hard registers
2138 we need to copy it. */
2142 }
2144 {
2145 rtx seq;
2146 /* The SET_SRC might not be invariant, so we must
2147 use the REG_EQUAL note. */
2159 }
2161 {
2169 }
2170 else
2174 {
2178 /* If there is a REG_EQUAL note present whose value
2179 is not loop invariant, then delete it, since it
2180 may cause problems with later optimization passes.
2181 It is possible for cse to create such notes
2182 like this as a result of record_jump_cond. */
2187 }
2196 /* If library call, now fix the REG_NOTES that contain
2197 insn pointers, namely REG_LIBCALL on FIRST
2198 and REG_RETVAL on I1. */
2200 {
2204 }
2210 /* simplify_giv_expr expects that it can walk the insns
2211 at m->insn forwards and see this old sequence we are
2212 tossing here. delete_insn does preserve the next
2213 pointers, but when we skip over a NOTE we must fix
2214 it up. Otherwise that code walks into the non-deleted
2215 insn stream. */
2220 {
2221 rtx seq;
2222 /* Replace the original insn with a move from
2223 our newly created temp. */
2229 }
2230 }
2232 /* The more regs we move, the less we like moving them. */
2234 }
2239 {
2240 /* Any other movable that loads the same register
2241 MUST be moved. */
2244 /* This reg has been moved out of one loop. */
2247 /* The reg set here is now invariant. */
2249 {
2253 }
2255 /* Change the length-of-life info for the register
2256 to say it lives at least the full length of this loop.
2257 This will help guide optimizations in outer loops. */
2260 /* This is the old insn before all the moved insns.
2261 We can't use the moved insn because it is out of range
2262 in uid_luid. Only the old insns have luids. */
2266 }
2268 /* Combine with this moved insn any other matching movables. */
2273 {
2274 rtx temp;
2276 /* Schedule the reg loaded by M1
2277 for replacement so that shares the reg of M.
2278 If the modes differ (only possible in restricted
2279 circumstances, make a SUBREG.
2281 Note this assumes that the target dependent files
2282 treat REG and SUBREG equally, including within
2283 GO_IF_LEGITIMATE_ADDRESS and in all the
2284 predicates since we never verify that replacing the
2285 original register with a SUBREG results in a
2286 recognizable insn. */
2289 else
2294 /* Get rid of the matching insn
2295 and prevent further processing of it. */
2298 /* if library call, delete all insns. */
2300 NULL_RTX)))
2302 else
2305 /* Any other movable that loads the same register
2306 MUST be moved. */
2309 /* The reg merged here is now invariant,
2310 if the reg it matches is invariant. */
2312 {
2316 i++)
2318 }
2319 }
2320 }
2323 }
2329 }
2334 /* Go through all the instructions in the loop, making
2335 all the register substitutions scheduled in REG_MAP. */
2339 {
2343 }
2345 /* Clean up. */
2348 }
2351 static void
2355 {
2358 else
2361 }
2364 static void
2367 {
2372 {
2375 }
2376 }
2377 \f
2378 #if 0
2379 /* Scan X and replace the address of any MEM in it with ADDR.
2380 REG is the address that MEM should have before the replacement. */
2382 static void
2385 {
2394 {
2406 /* Short cut for very common case. */
2411 /* Short cut for very common case. */
2416 /* If this MEM uses a reg other than the one we expected,
2417 something is wrong. */
2425 }
2429 {
2433 {
2437 }
2438 }
2439 }
2440 #endif
2441 \f
2442 /* Return the number of memory refs to addresses that vary
2443 in the rtx X. */
2445 static int
2448 rtx x;
2449 {
2460 {
2477 }
2482 {
2486 {
2490 }
2491 }
2493 }
2494 \f
2495 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2496 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2497 `unknown_address_altered', `unknown_constant_address_altered', and
2498 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2499 list `store_mems' in LOOP. */
2501 static void
2504 {
2506 rtx insn;
2510 /* The label after END. Jumping here is just like falling off the
2511 end of the loop. We use next_nonnote_insn instead of next_label
2512 as a hedge against the (pathological) case where some actual insn
2513 might end up between the two. */
2532 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2537 {
2539 {
2542 }
2543 }
2547 {
2549 {
2552 {
2554 /* Count number of loops contained in this one. */
2556 }
2563 {
2566 }
2576 {
2580 {
2585 {
2588 }
2589 else
2590 {
2593 }
2595 do
2596 {
2598 {
2600 {
2601 /* Something tricky. */
2604 }
2607 {
2608 /* A jump outside the current loop. */
2611 }
2612 }
2616 }
2618 }
2619 else
2620 {
2621 /* A return, or something tricky. */
2623 }
2624 }
2625 /* FALLTHRU */
2646 }
2647 }
2649 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2651 anywhere. */
2653 /* We don't want loads for MEMs moved to a location before the
2654 one at which their stack memory becomes allocated. (Note
2655 that this is not a problem for malloc, etc., since those
2656 require actual function calls. */
2657 && ! current_function_calls_alloca
2658 /* There are ways to leave the loop other than falling off the
2659 end. */
2665 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2666 that loop_invariant_p and load_mems can use true_dependence
2667 to determine what is really clobbered. */
2669 {
2672 loop_info->store_mems
2674 }
2676 {
2680 loop_info->store_mems
2682 }
2683 }
2684 \f
2685 /* Invalidate all loops containing LABEL. */
2687 static void
2689 rtx label;
2690 {
2694 }
2696 /* Scan the function looking for loops. Record the start and end of each loop.
2697 Also mark as invalid loops any loops that contain a setjmp or are branched
2698 to from outside the loop. */
2700 static void
2702 rtx f;
2704 {
2705 rtx insn;
2706 rtx label;
2716 /* If there are jumps to undefined labels,
2717 treat them as jumps out of any/all loops.
2718 This also avoids writing past end of tables when there are no loops. */
2721 /* Find boundaries of loops, mark which loops are contained within
2722 loops, and invalidate loops that have setjmp. */
2727 {
2730 {
2734 num_loops++;
2758 }
2762 {
2763 /* In this case, we must invalidate our current loop and any
2764 enclosing loop. */
2766 {
2772 }
2773 }
2775 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2776 enclosing loop, but this doesn't matter. */
2778 }
2780 /* Any loop containing a label used in an initializer must be invalidated,
2781 because it can be jumped into from anywhere. */
2785 /* Any loop containing a label used for an exception handler must be
2786 invalidated, because it can be jumped into from anywhere. */
2789 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2790 loop that it is not contained within, that loop is marked invalid.
2791 If any INSN or CALL_INSN uses a label's address, then the loop containing
2792 that label is marked invalid, because it could be jumped into from
2793 anywhere.
2795 Also look for blocks of code ending in an unconditional branch that
2796 exits the loop. If such a block is surrounded by a conditional
2797 branch around the block, move the block elsewhere (see below) and
2798 invert the jump to point to the code block. This may eliminate a
2799 label in our loop and will simplify processing by both us and a
2800 possible second cse pass. */
2804 {
2808 {
2812 }
2819 /* See if this is an unconditional branch outside the loop. */
2827 {
2828 rtx p;
2834 /* Go backwards until we reach the start of the loop, a label,
2835 or a JUMP_INSN. */
2842 ;
2844 /* Check for the case where we have a jump to an inner nested
2845 loop, and do not perform the optimization in that case. */
2848 {
2851 {
2856 }
2857 }
2859 /* Make sure that the target of P is within the current loop. */
2865 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2866 we have a block of code to try to move.
2868 We look backward and then forward from the target of INSN
2869 to find a BARRIER at the same loop depth as the target.
2870 If we find such a BARRIER, we make a new label for the start
2871 of the block, invert the jump in P and point it to that label,
2872 and move the block of code to the spot we found. */
2877 /* Just ignore jumps to labels that were never emitted.
2878 These always indicate compilation errors. */
2882 /* If it's not safe to move the sequence, then we
2883 mustn't try. */
2886 {
2887 rtx target
2891 rtx tmp;
2893 /* Search for possible garbage past the conditional jumps
2894 and look for the last barrier. */
2902 /* Don't move things inside a tablejump. */
2915 /* Don't move things inside a tablejump. */
2926 {
2930 /* Ensure our label doesn't go away. */
2933 /* Verify that uid_loop is large enough and that
2934 we can invert P. */
2936 {
2939 /* If no suitable BARRIER was found, create a suitable
2940 one before TARGET. Since TARGET is a fall through
2941 path, we'll need to insert a jump around our block
2942 and add a BARRIER before TARGET.
2944 This creates an extra unconditional jump outside
2945 the loop. However, the benefits of removing rarely
2946 executed instructions from inside the loop usually
2947 outweighs the cost of the extra unconditional jump
2948 outside the loop. */
2950 {
2951 rtx temp;
2958 }
2960 /* Include the BARRIER after INSN and copy the
2961 block after LOC. */
2966 /* All those insns are now in TARGET_LOOP. */
2972 /* The label jumped to by INSN is no longer a loop
2973 exit. Unless INSN does not have a label (e.g.,
2974 it is a RETURN insn), search loop->exit_labels
2975 to find its label_ref, and remove it. Also turn
2976 off LABEL_OUTSIDE_LOOP_P bit. */
2978 {
2980 r;
2983 {
2987 else
2990 }
2996 /* If we didn't find it, then something is
2997 wrong. */
3000 }
3002 /* P is now a jump outside the loop, so it must be put
3003 in loop->exit_labels, and marked as such.
3004 The easiest way to do this is to just call
3005 mark_loop_jump again for P. */
3008 /* If INSN now jumps to the insn after it,
3009 delete INSN. */
3014 }
3016 /* Continue the loop after where the conditional
3017 branch used to jump, since the only branch insn
3018 in the block (if it still remains) is an inter-loop
3019 branch and hence needs no processing. */
3025 /* This loop will be continued with NEXT_INSN (insn). */
3027 }
3028 }
3029 }
3030 }
3031 }
3033 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3034 loops it is contained in, mark the target loop invalid.
3036 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3038 static void
3040 rtx x;
3042 {
3048 {
3060 /* There could be a label reference in here. */
3072 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3084 /* Link together all labels that branch outside the loop. This
3085 is used by final_[bg]iv_value and the loop unrolling code. Also
3086 mark this LABEL_REF so we know that this branch should predict
3087 false. */
3089 /* A check to make sure the label is not in an inner nested loop,
3090 since this does not count as a loop exit. */
3092 {
3097 }
3098 else
3102 {
3111 }
3113 /* If this is inside a loop, but not in the current loop or one enclosed
3114 by it, it invalidates at least one loop. */
3119 /* We must invalidate every nested loop containing the target of this
3120 label, except those that also contain the jump insn. */
3123 {
3124 /* Stop when we reach a loop that also contains the jump insn. */
3129 /* If we get here, we know we need to invalidate a loop. */
3136 }
3140 /* If this is not setting pc, ignore. */
3162 /* Strictly speaking this is not a jump into the loop, only a possible
3163 jump out of the loop. However, we have no way to link the destination
3164 of this jump onto the list of exit labels. To be safe we mark this
3165 loop and any containing loops as invalid. */
3167 {
3169 {
3175 }
3176 }
3178 }
3179 }
3180 \f
3181 /* Return nonzero if there is a label in the range from
3182 insn INSN to and including the insn whose luid is END
3183 INSN must have an assigned luid (i.e., it must not have
3184 been previously created by loop.c). */
3186 static int
3188 rtx insn;
3190 {
3192 {
3196 }
3199 }
3201 /* Record that a memory reference X is being set. */
3203 static void
3205 rtx x;
3206 rtx y ATTRIBUTE_UNUSED;
3208 {
3214 /* Count number of memory writes.
3215 This affects heuristics in strength_reduce. */
3218 /* BLKmode MEM means all memory is clobbered. */
3220 {
3223 else
3227 }
3231 }
3233 /* X is a value modified by an INSN that references a biv inside a loop
3234 exit test (ie, X is somehow related to the value of the biv). If X
3235 is a pseudo that is used more than once, then the biv is (effectively)
3236 used more than once. DATA is a pointer to a loop_regs structure. */
3238 static void
3240 rtx x;
3241 rtx y ATTRIBUTE_UNUSED;
3243 {
3258 /* If we do not have usage information, or if we know the register
3259 is used more than once, note that fact for check_dbra_loop. */
3264 }
3265 \f
3266 /* Return nonzero if the rtx X is invariant over the current loop.
3268 The value is 2 if we refer to something only conditionally invariant.
3270 A memory ref is invariant if it is not volatile and does not conflict
3271 with anything stored in `loop_info->store_mems'. */
3273 int
3276 rtx x;
3277 {
3284 rtx mem_list_entry;
3290 {
3298 /* A LABEL_REF is normally invariant, however, if we are unrolling
3299 loops, and this label is inside the loop, then it isn't invariant.
3300 This is because each unrolled copy of the loop body will have
3301 a copy of this label. If this was invariant, then an insn loading
3302 the address of this label into a register might get moved outside
3303 the loop, and then each loop body would end up using the same label.
3305 We don't know the loop bounds here though, so just fail for all
3306 labels. */
3309 else
3318 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3319 since the reg might be set by initialization within the loop. */
3330 /* Out-of-range regs can occur when we are called from unrolling.
3331 These have always been created by the unroller and are set in
3332 the loop, hence are never invariant. */
3343 /* Volatile memory references must be rejected. Do this before
3344 checking for read-only items, so that volatile read-only items
3345 will be rejected also. */
3349 /* See if there is any dependence between a store and this load. */
3352 {
3358 }
3360 /* It's not invalidated by a store in memory
3361 but we must still verify the address is invariant. */
3365 /* Don't mess with insns declared volatile. */
3372 }
3376 {
3378 {
3384 }
3386 {
3389 {
3395 }
3397 }
3398 }
3401 }
3402 \f
3403 /* Return nonzero if all the insns in the loop that set REG
3404 are INSN and the immediately following insns,
3405 and if each of those insns sets REG in an invariant way
3406 (not counting uses of REG in them).
3408 The value is 2 if some of these insns are only conditionally invariant.
3410 We assume that INSN itself is the first set of REG
3411 and that its source is invariant. */
3413 static int
3418 {
3422 rtx temp;
3423 /* Number of sets we have to insist on finding after INSN. */
3429 /* If N_SETS hit the limit, we can't rely on its value. */
3436 {
3438 rtx set;
3443 /* If library call, skip to end of it. */
3452 {
3457 {
3458 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3459 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3460 notes are OK. */
3466 }
3467 }
3469 count--;
3471 {
3474 }
3475 }
3478 /* If loop_invariant_p ever returned 2, we return 2. */
3480 }
3482 #if 0
3483 /* I don't think this condition is sufficient to allow INSN
3484 to be moved, so we no longer test it. */
3486 /* Return 1 if all insns in the basic block of INSN and following INSN
3487 that set REG are invariant according to TABLE. */
3489 static int
3493 {
3498 {
3507 {
3510 }
3511 }
3512 }
3514 \f
3515 /* Look at all uses (not sets) of registers in X. For each, if it is
3516 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3517 a different insn, set USAGE[REGNO] to const0_rtx. */
3519 static void
3522 rtx insn;
3523 rtx x;
3524 {
3536 {
3537 /* Don't count SET_DEST if it is a REG; otherwise count things
3538 in SET_DEST because if a register is partially modified, it won't
3539 show up as a potential movable so we don't care how USAGE is set
3540 for it. */
3544 }
3545 else
3547 {
3553 }
3554 }
3555 \f
3556 /* Count and record any set in X which is contained in INSN. Update
3557 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3558 in X. */
3560 static void
3565 {
3567 /* Don't move a reg that has an explicit clobber.
3568 It's not worth the pain to try to do it correctly. */
3572 {
3580 {
3584 {
3585 /* If this is the first setting of this reg
3586 in current basic block, and it was set before,
3587 it must be set in two basic blocks, so it cannot
3588 be moved out of the loop. */
3592 /* If this is not first setting in current basic block,
3593 see if reg was used in between previous one and this.
3594 If so, neither one can be moved. */
3601 }
3602 }
3603 }
3604 }
3605 \f
3606 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3607 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3608 contained in insn INSN is used by any insn that precedes INSN in
3609 cyclic order starting from the loop entry point.
3611 We don't want to use INSN_LUID here because if we restrict INSN to those
3612 that have a valid INSN_LUID, it means we cannot move an invariant out
3613 from an inner loop past two loops. */
3615 static int
3619 {
3621 rtx p;
3623 /* Scan forward checking for register usage. If we hit INSN, we
3624 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3626 {
3632 }
3635 }
3636 \f
3638 /* Information we collect about arrays that we might want to prefetch. */
3639 struct prefetch_info
3640 {
3644 index. */
3645 HOST_WIDE_INT index;
3647 iteration. */
3649 prefetch area in one iteration. */
3651 This is set only for loops with known
3652 iteration counts and is 0xffffffff
3653 otherwise. */
3657 };
3659 /* Data used by check_store function. */
3660 struct check_store_data
3661 {
3662 rtx mem_address;
3664 };
3670 /* Set mem_write when mem_address is found. Used as callback to
3671 note_stores. */
3672 static void
3676 {
3681 }
3682 \f
3683 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3684 important to get some addresses combined. Later more sophisticated
3685 transformations can be added when necessary.
3687 ??? Same trick with swapping operand is done at several other places.
3688 It can be nice to develop some common way to handle this. */
3690 static int
3693 {
3707 {
3712 }
3713 /* Compare the elements. If any pair of corresponding elements fails to
3714 match, return 0 for the whole thing. */
3718 {
3720 {
3732 /* Two vectors must have the same length. */
3736 /* And the corresponding elements must match. */
3754 /* These are just backpointers, so they don't matter. */
3760 /* It is believed that rtx's at this level will never
3761 contain anything but integers and other rtx's,
3762 except for within LABEL_REFs and SYMBOL_REFs. */
3765 }
3766 }
3768 }
3769 \f
3770 /* Remove constant addition value from the expression X (when present)
3771 and return it. */
3773 static HOST_WIDE_INT
3776 {
3780 /* Avoid clobbering a shared CONST expression. */
3782 {
3786 {
3789 }
3791 }
3794 {
3797 }
3799 /* For plus expression recurse on ourself. */
3801 {
3805 /* In case our parameter was constant, remove extra zero from the
3806 expression. */
3811 }
3814 }
3816 /* Attempt to identify accesses to arrays that are most likely to cause cache
3817 misses, and emit prefetch instructions a few prefetch blocks forward.
3819 To detect the arrays we use the GIV information that was collected by the
3820 strength reduction pass.
3822 The prefetch instructions are generated after the GIV information is done
3823 and before the strength reduction process. The new GIVs are injected into
3824 the strength reduction tables, so the prefetch addresses are optimized as
3825 well.
3827 GIVs are split into base address, stride, and constant addition values.
3828 GIVs with the same address, stride and close addition values are combined
3829 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3830 for write instructions can be used for the block we write to, on machines
3831 that support write prefetches.
3833 Several heuristics are used to determine when to prefetch. They are
3834 controlled by defined symbols that can be overridden for each target. */
3836 static void
3839 {
3855 /* Consider only loops w/o calls. When a call is done, the loop is probably
3856 slow enough to read the memory. */
3858 {
3863 }
3865 /* Don't prefetch in loops known to have few iterations. */
3869 {
3874 }
3876 /* Search all induction variables and pick those interesting for the prefetch
3877 machinery. */
3879 {
3885 /* Expect all BIVs to be executed in each iteration. This makes our
3886 analysis more conservative. */
3888 {
3889 /* Discard non-constant additions that we can't handle well yet, and
3890 BIVs that are executed multiple times; such BIVs ought to be
3891 handled in the nested loop. We accept not_every_iteration BIVs,
3892 since these only result in larger strides and make our
3893 heuristics more conservative. */
3895 {
3897 {
3903 }
3905 }
3908 {
3910 {
3916 }
3918 }
3922 }
3928 {
3929 rtx address;
3930 rtx temp;
3939 /* See whether an induction variable is interesting to us and if
3940 not, report the reason. */
3944 /* We are interested only in constant stride memory references
3945 in order to be able to compute density easily. */
3949 else
3950 {
3953 {
3956 }
3958 /* On some targets, reversed order prefetches are not
3959 worthwhile. */
3963 /* Prefetch of accesses with an extreme stride might not be
3964 worthwhile, either. */
3969 /* Ignore GIVs with varying add values; we can't predict the
3970 value for the next iteration. */
3974 /* Ignore GIVs in the nested loops; they ought to have been
3975 handled already. */
3978 }
3981 {
3987 }
3989 /* Determine the pointer to the basic array we are examining. It is
3990 the sum of the BIV's initial value and the GIV's add_val. */
4000 /* When the GIV is not always executed, we might be better off by
4001 not dirtying the cache pages. */
4004 else
4005 {
4010 }
4012 /* Attempt to find another prefetch to the same array and see if we
4013 can merge this one. */
4017 {
4018 /* In case both access same array (same location
4019 just with small difference in constant indexes), merge
4020 the prefetches. Just do the later and the earlier will
4021 get prefetched from previous iteration.
4022 The artificial threshold should not be too small,
4023 but also not bigger than small portion of memory usually
4024 traversed by single loop. */
4027 {
4036 }
4040 {
4045 }
4046 }
4048 /* Merging failed. */
4050 {
4058 num_prefetches++;
4060 {
4065 }
4066 }
4067 }
4068 }
4071 {
4074 /* Attempt to calculate the total number of bytes fetched by all
4075 iterations of the loop. Avoid overflow. */
4080 else
4085 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4090 {
4095 }
4096 else
4097 {
4103 }
4104 else
4107 /* Find how many prefetch instructions we'll use within the loop. */
4109 {
4115 }
4116 }
4118 /* Determine how many iterations ahead to prefetch within the loop, based
4119 on how many prefetches we currently expect to do within the loop. */
4121 {
4123 {
4129 }
4130 }
4131 /* We'll also use AHEAD to determine how many prefetch instructions to
4132 emit before a loop, so don't leave it zero. */
4137 {
4138 /* Update if we've decided not to prefetch anything within the loop. */
4142 /* Find how many prefetch instructions we'll use before the loop. */
4144 {
4152 }
4155 {
4177 }
4178 }
4181 {
4182 /* Record that this loop uses prefetch instructions. */
4186 {
4191 }
4192 }
4195 {
4199 {
4201 rtx insn;
4205 rtx seq;
4207 /* We can save some effort by offsetting the address on
4208 architectures with offsettable memory references. */
4211 else
4212 {
4218 }
4221 /* Make sure the address operand is valid for prefetch. */
4231 /* Check all insns emitted and record the new GIV
4232 information. */
4235 {
4240 }
4241 }
4244 {
4245 /* Emit insns before the loop to fetch the first cache lines or,
4246 if we're not prefetching within the loop, everything we expect
4247 to need. */
4249 {
4257 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4258 non-constant INIT_VAL to have the same mode as REG, which
4259 in this case we know to be Pmode. */
4261 {
4262 rtx seq;
4269 }
4275 loop_start);
4276 }
4277 }
4278 }
4281 }
4282 \f
4283 /* A "basic induction variable" or biv is a pseudo reg that is set
4284 (within this loop) only by incrementing or decrementing it. */
4285 /* A "general induction variable" or giv is a pseudo reg whose
4286 value is a linear function of a biv. */
4288 /* Bivs are recognized by `basic_induction_var';
4289 Givs by `general_induction_var'. */
4291 /* Communication with routines called via `note_stores'. */
4295 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4299 /* ??? Unfinished optimizations, and possible future optimizations,
4300 for the strength reduction code. */
4302 /* ??? The interaction of biv elimination, and recognition of 'constant'
4303 bivs, may cause problems. */
4305 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4306 performance problems.
4308 Perhaps don't eliminate things that can be combined with an addressing
4309 mode. Find all givs that have the same biv, mult_val, and add_val;
4310 then for each giv, check to see if its only use dies in a following
4311 memory address. If so, generate a new memory address and check to see
4312 if it is valid. If it is valid, then store the modified memory address,
4313 otherwise, mark the giv as not done so that it will get its own iv. */
4315 /* ??? Could try to optimize branches when it is known that a biv is always
4316 positive. */
4318 /* ??? When replace a biv in a compare insn, we should replace with closest
4319 giv so that an optimized branch can still be recognized by the combiner,
4320 e.g. the VAX acb insn. */
4322 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4323 was rerun in loop_optimize whenever a register was added or moved.
4324 Also, some of the optimizations could be a little less conservative. */
4325 \f
4326 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4327 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4328 callback.
4330 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4331 least once for every loop iteration except for the last one.
4333 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4334 loop iteration.
4335 */
4336 void
4339 loop_insn_callback fncall;
4340 {
4345 rtx p;
4347 /* If loop_scan_start points to the loop exit test, we have to be wary of
4348 subversive use of gotos inside expression statements. */
4352 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4356 {
4359 /* Past CODE_LABEL, we get to insns that may be executed multiple
4360 times. The only way we can be sure that they can't is if every
4361 jump insn between here and the end of the loop either
4362 returns, exits the loop, is a jump to a location that is still
4363 behind the label, or is a jump to the loop start. */
4366 {
4372 {
4377 {
4380 else
4384 }
4392 {
4395 }
4396 }
4397 }
4399 /* Past a jump, we get to insns for which we can't count
4400 on whether they will be executed during each iteration. */
4401 /* This code appears twice in strength_reduce. There is also similar
4402 code in scan_loop. */
4404 /* If we enter the loop in the middle, and scan around to the
4405 beginning, don't set not_every_iteration for that.
4406 This can be any kind of jump, since we want to know if insns
4407 will be executed if the loop is executed. */
4412 {
4415 /* If this is a jump outside the loop, then it also doesn't
4416 matter. Check to see if the target of this branch is on the
4417 loop->exits_labels list. */
4425 }
4428 {
4429 /* At the virtual top of a converted loop, insns are again known to
4430 be executed each iteration: logically, the loop begins here
4431 even though the exit code has been duplicated.
4433 Insns are also again known to be executed each iteration at
4434 the LOOP_CONT note. */
4440 loop_depth++;
4442 loop_depth--;
4443 }
4445 /* Note if we pass a loop latch. If we do, then we can not clear
4446 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4447 a loop since a jump before the last CODE_LABEL may have started
4448 a new loop iteration.
4450 Note that LOOP_TOP is only set for rotated loops and we need
4451 this check for all loops, so compare against the CODE_LABEL
4452 which immediately follows LOOP_START. */
4457 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4458 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4459 or not an insn is known to be executed each iteration of the
4460 loop, whether or not any iterations are known to occur.
4462 Therefore, if we have just passed a label and have no more labels
4463 between here and the test insn of the loop, and we have not passed
4464 a jump to the top of the loop, then we know these insns will be
4465 executed each iteration. */
4468 && !past_loop_latch
4473 }
4474 }
4475 \f
4476 static void
4479 {
4482 /* Temporary list pointers for traversing ivs->list. */
4489 /* Scan ivs->list to remove all regs that proved not to be bivs.
4490 Make a sanity check against regs->n_times_set. */
4492 {
4494 /* Above happens if register modified by subreg, etc. */
4495 /* Make sure it is not recognized as a basic induction var: */
4497 /* If never incremented, it is invariant that we decided not to
4498 move. So leave it alone. */
4500 {
4511 }
4512 else
4513 {
4518 }
4519 }
4520 }
4523 /* Determine how BIVS are initialized by looking through pre-header
4524 extended basic block. */
4525 static void
4528 {
4530 /* Temporary list pointers for traversing ivs->list. */
4533 rtx p;
4535 /* Find initial value for each biv by searching backwards from loop_start,
4536 halting at first label. Also record any test condition. */
4540 {
4541 rtx test;
4551 /* Record any test of a biv that branches around the loop if no store
4552 between it and the start of loop. We only care about tests with
4553 constants and registers and only certain of those. */
4563 {
4564 /* If an NE test, we have an initial value! */
4566 {
4570 }
4571 else
4573 }
4574 }
4575 }
4578 /* Look at the each biv and see if we can say anything better about its
4579 initial value from any initializing insns set up above. (This is done
4580 in two passes to avoid missing SETs in a PARALLEL.) */
4581 static void
4584 {
4586 /* Temporary list pointers for traversing ivs->list. */
4591 {
4592 rtx src;
4593 rtx note;
4598 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4599 is a constant, use the value of that. */
4605 else
4618 {
4622 {
4625 }
4626 }
4627 /* If we can't make it a giv,
4628 let biv keep initial value of "itself". */
4631 }
4632 }
4635 /* Search the loop for general induction variables. */
4637 static void
4640 {
4642 }
4645 /* For each giv for which we still don't know whether or not it is
4646 replaceable, check to see if it is replaceable because its final value
4647 can be calculated. */
4649 static void
4652 {
4657 {
4663 }
4664 }
4667 /* Return nonzero if it is possible to eliminate the biv BL provided
4668 all givs are reduced. This is possible if either the reg is not
4669 used outside the loop, or we can compute what its final value will
4670 be. */
4672 static int
4678 {
4679 /* For architectures with a decrement_and_branch_until_zero insn,
4680 don't do this if we put a REG_NONNEG note on the endtest for this
4681 biv. */
4683 #ifdef HAVE_decrement_and_branch_until_zero
4685 {
4690 }
4691 #endif
4693 /* Check that biv is used outside loop or if it has a final value.
4694 Compare against bl->init_insn rather than loop->start. We aren't
4695 concerned with any uses of the biv between init_insn and
4696 loop->start since these won't be affected by the value of the biv
4697 elsewhere in the function, so long as init_insn doesn't use the
4698 biv itself. */
4709 {
4717 }
4719 }
4722 /* Reduce each giv of BL that we have decided to reduce. */
4724 static void
4728 {
4732 {
4735 {
4738 /* If the code for derived givs immediately below has already
4739 allocated a new_reg, we must keep it. */
4743 #ifdef AUTO_INC_DEC
4744 /* If the target has auto-increment addressing modes, and
4745 this is an address giv, then try to put the increment
4746 immediately after its use, so that flow can create an
4747 auto-increment addressing mode. */
4750 /* We don't handle reversed biv's because bl->biv->insn
4751 does not have a valid INSN_LUID. */
4755 {
4756 /* If other giv's have been combined with this one, then
4757 this will work only if all uses of the other giv's occur
4758 before this giv's insn. This is difficult to check.
4760 We simplify this by looking for the common case where
4761 there is one DEST_REG giv, and this giv's insn is the
4762 last use of the dest_reg of that DEST_REG giv. If the
4763 increment occurs after the address giv, then we can
4764 perform the optimization. (Otherwise, the increment
4765 would have to go before other_giv, and we would not be
4766 able to combine it with the address giv to get an
4767 auto-inc address.) */
4769 {
4774 {
4777 else
4779 }
4786 }
4787 /* Check for case where increment is before the address
4788 giv. Do this test in "loop order". */
4797 else
4800 #ifdef HAVE_cc0
4801 {
4802 rtx prev;
4804 /* We can't put an insn immediately after one setting
4805 cc0, or immediately before one using cc0. */
4812 }
4813 #endif
4817 }
4818 #endif
4820 /* For each place where the biv is incremented, add an insn
4821 to increment the new, reduced reg for the giv. */
4823 {
4824 rtx insert_before;
4826 /* Skip if location is the same as a previous one. */
4833 else
4841 /* A multiply is acceptable here
4842 since this is presumed to be seldom executed. */
4846 }
4848 /* Add code at loop start to initialize giv's reduced reg. */
4853 }
4854 }
4855 }
4858 /* Check for givs whose first use is their definition and whose
4859 last use is the definition of another giv. If so, it is likely
4860 dead and should not be used to derive another giv nor to
4861 eliminate a biv. */
4863 static void
4867 {
4871 {
4878 {
4884 }
4885 }
4886 }
4889 static void
4894 {
4898 {
4905 /* Update expression if this was combined, in case other giv was
4906 replaced. */
4911 /* See if this register is known to be a pointer to something. If
4912 so, see if we can find the alignment. First see if there is a
4913 destination register that is a pointer. If so, this shares the
4914 alignment too. Next see if we can deduce anything from the
4915 computational information. If not, and this is a DEST_ADDR
4916 giv, at least we know that it's a pointer, though we don't know
4917 the alignment. */
4925 {
4934 }
4938 {
4946 }
4951 /* Store reduced reg as the address in the memref where we found
4952 this giv. */
4955 {
4957 }
4958 else
4959 {
4961 rtx note;
4963 /* Not replaceable; emit an insn to set the original giv reg from
4964 the reduced giv, same as above. */
4969 /* The original insn may have a REG_EQUAL note. This note is
4970 now incorrect and may result in invalid substitutions later.
4971 The original insn is dead, but may be part of a libcall
4972 sequence, which doesn't seem worth the bother of handling. */
4976 }
4978 /* When a loop is reversed, givs which depend on the reversed
4979 biv, and which are live outside the loop, must be set to their
4980 correct final value. This insn is only needed if the giv is
4981 not replaceable. The correct final value is the same as the
4982 value that the giv starts the reversed loop with. */
4993 {
4998 }
4999 }
5000 }
5003 static int
5008 rtx test_reg;
5009 {
5018 /* Reduce benefit if not replaceable, since we will insert a
5019 move-insn to replace the insn that calculates this giv. Don't do
5020 this unless the giv is a user variable, since it will often be
5021 marked non-replaceable because of the duplication of the exit
5022 code outside the loop. In such a case, the copies we insert are
5023 dead and will be deleted. So they don't have a cost. Similar
5024 situations exist. */
5025 /* ??? The new final_[bg]iv_value code does a much better job of
5026 finding replaceable giv's, and hence this code may no longer be
5027 necessary. */
5032 /* Decrease the benefit to count the add-insns that we will insert
5033 to increment the reduced reg for the giv. ??? This can
5034 overestimate the run-time cost of the additional insns, e.g. if
5035 there are multiple basic blocks that increment the biv, but only
5036 one of these blocks is executed during each iteration. There is
5037 no good way to detect cases like this with the current structure
5038 of the loop optimizer. This code is more accurate for
5039 determining code size than run-time benefits. */
5042 /* Decide whether to strength-reduce this giv or to leave the code
5043 unchanged (recompute it from the biv each time it is used). This
5044 decision can be made independently for each giv. */
5046 #ifdef AUTO_INC_DEC
5047 /* Attempt to guess whether autoincrement will handle some of the
5048 new add insns; if so, increase BENEFIT (undo the subtraction of
5049 add_cost that was done above). */
5051 /* Increasing the benefit is risky, since this is only a guess.
5052 Avoid increasing register pressure in cases where there would
5053 be no other benefit from reducing this giv. */
5056 {
5071 }
5072 #endif
5075 }
5078 /* Free IV structures for LOOP. */
5080 static void
5083 {
5090 {
5096 {
5099 }
5101 {
5104 }
5108 }
5109 }
5112 /* Perform strength reduction and induction variable elimination.
5114 Pseudo registers created during this function will be beyond the
5115 last valid index in several tables including
5116 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5117 problem here, because the added registers cannot be givs outside of
5118 their loop, and hence will never be reconsidered. But scan_loop
5119 must check regnos to make sure they are in bounds. */
5121 static void
5125 {
5129 rtx p;
5130 /* Temporary list pointer for traversing ivs->list. */
5132 /* Ratio of extra register life span we can justify
5133 for saving an instruction. More if loop doesn't call subroutines
5134 since in that case saving an insn makes more difference
5135 and more registers are available. */
5136 /* ??? could set this to last value of threshold in move_movables */
5138 /* Map of pseudo-register replacements. */
5150 /* Find all BIVs in loop. */
5153 /* Exit if there are no bivs. */
5155 {
5156 /* Can still unroll the loop anyways, but indicate that there is no
5157 strength reduction info available. */
5163 }
5165 /* Determine how BIVS are initialized by looking through pre-header
5166 extended basic block. */
5169 /* Look at the each biv and see if we can say anything better about its
5170 initial value from any initializing insns set up above. */
5173 /* Search the loop for general induction variables. */
5176 /* Try to calculate and save the number of loop iterations. This is
5177 set to zero if the actual number can not be calculated. This must
5178 be called after all giv's have been identified, since otherwise it may
5179 fail if the iteration variable is a giv. */
5182 #ifdef HAVE_prefetch
5185 #endif
5187 /* Now for each giv for which we still don't know whether or not it is
5188 replaceable, check to see if it is replaceable because its final value
5189 can be calculated. This must be done after loop_iterations is called,
5190 so that final_giv_value will work correctly. */
5193 /* Try to prove that the loop counter variable (if any) is always
5194 nonnegative; if so, record that fact with a REG_NONNEG note
5195 so that "decrement and branch until zero" insn can be used. */
5198 /* Create reg_map to hold substitutions for replaceable giv regs.
5199 Some givs might have been made from biv increments, so look at
5200 ivs->reg_iv_type for a suitable size. */
5204 /* Examine each iv class for feasibility of strength reduction/induction
5205 variable elimination. */
5208 {
5212 /* Test whether it will be possible to eliminate this biv
5213 provided all givs are reduced. */
5216 /* This will be true at the end, if all givs which depend on this
5217 biv have been strength reduced.
5218 We can't (currently) eliminate the biv unless this is so. */
5221 /* Check each extension dependent giv in this class to see if its
5222 root biv is safe from wrapping in the interior mode. */
5225 /* Combine all giv's for this iv_class. */
5229 {
5237 /* If an insn is not to be strength reduced, then set its ignore
5238 flag, and clear bl->all_reduced. */
5240 /* A giv that depends on a reversed biv must be reduced if it is
5241 used after the loop exit, otherwise, it would have the wrong
5242 value after the loop exit. To make it simple, just reduce all
5243 of such giv's whether or not we know they are used after the loop
5244 exit. */
5249 {
5257 }
5258 else
5259 {
5260 /* Check that we can increment the reduced giv without a
5261 multiply insn. If not, reject it. */
5266 {
5274 }
5275 }
5276 }
5278 /* Check for givs whose first use is their definition and whose
5279 last use is the definition of another giv. If so, it is likely
5280 dead and should not be used to derive another giv nor to
5281 eliminate a biv. */
5284 /* Reduce each giv that we decided to reduce. */
5287 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5288 as not reduced.
5290 For each giv register that can be reduced now: if replaceable,
5291 substitute reduced reg wherever the old giv occurs;
5292 else add new move insn "giv_reg = reduced_reg". */
5295 /* All the givs based on the biv bl have been reduced if they
5296 merit it. */
5298 /* For each giv not marked as maybe dead that has been combined with a
5299 second giv, clear any "maybe dead" mark on that second giv.
5300 v->new_reg will either be or refer to the register of the giv it
5301 combined with.
5303 Doing this clearing avoids problems in biv elimination where
5304 a giv's new_reg is a complex value that can't be put in the
5305 insn but the giv combined with (with a reg as new_reg) is
5306 marked maybe_dead. Since the register will be used in either
5307 case, we'd prefer it be used from the simpler giv. */
5313 /* Try to eliminate the biv, if it is a candidate.
5314 This won't work if ! bl->all_reduced,
5315 since the givs we planned to use might not have been reduced.
5317 We have to be careful that we didn't initially think we could
5318 eliminate this biv because of a giv that we now think may be
5319 dead and shouldn't be used as a biv replacement.
5321 Also, there is the possibility that we may have a giv that looks
5322 like it can be used to eliminate a biv, but the resulting insn
5323 isn't valid. This can happen, for example, on the 88k, where a
5324 JUMP_INSN can compare a register only with zero. Attempts to
5325 replace it with a compare with a constant will fail.
5327 Note that in cases where this call fails, we may have replaced some
5328 of the occurrences of the biv with a giv, but no harm was done in
5329 doing so in the rare cases where it can occur. */
5333 {
5334 /* ?? If we created a new test to bypass the loop entirely,
5335 or otherwise drop straight in, based on this test, then
5336 we might want to rewrite it also. This way some later
5337 pass has more hope of removing the initialization of this
5338 biv entirely. */
5340 /* If final_value != 0, then the biv may be used after loop end
5341 and we must emit an insn to set it just in case.
5343 Reversed bivs already have an insn after the loop setting their
5344 value, so we don't need another one. We can't calculate the
5345 proper final value for such a biv here anyways. */
5354 }
5355 /* See above note wrt final_value. But since we couldn't eliminate
5356 the biv, we must set the value after the loop instead of before. */
5360 }
5362 /* Go through all the instructions in the loop, making all the
5363 register substitutions scheduled in REG_MAP. */
5368 {
5372 }
5375 {
5376 /* When we completely unroll a loop we will likely not need the increment
5377 of the loop BIV and we will not need the conditional branch at the
5378 end of the loop. */
5381 #ifdef HAVE_cc0
5382 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5383 need the comparison before the conditional branch at the end of the
5384 loop. */
5386 #endif
5388 /* We'll need one copy for each loop iteration. */
5391 /* A little slop to account for the ability to remove initialization
5392 code, better CSE, and other secondary benefits of completely
5393 unrolling some loops. */
5396 /* Clamp the value. */
5399 }
5401 /* Unroll loops from within strength reduction so that we can use the
5402 induction variable information that strength_reduce has already
5403 collected. Always unroll loops that would be as small or smaller
5404 unrolled than when rolled. */
5411 #ifdef HAVE_doloop_end
5416 /* In case number of iterations is known, drop branch prediction note
5417 in the branch. Do that only in second loop pass, as loop unrolling
5418 may change the number of iterations performed. */
5420 {
5421 unsigned HOST_WIDE_INT n
5426 }
5434 }
5435 \f
5436 /*Record all basic induction variables calculated in the insn. */
5437 static rtx
5440 rtx p;
5443 {
5445 rtx set;
5446 rtx dest_reg;
5447 rtx inc_val;
5448 rtx mult_val;
5454 {
5459 {
5464 {
5465 /* It is a possible basic induction variable.
5466 Create and initialize an induction structure for it. */
5474 }
5477 }
5478 }
5480 }
5481 \f
5482 /* Record all givs calculated in the insn.
5483 A register is a giv if: it is only set once, it is a function of a
5484 biv and a constant (or invariant), and it is not a biv. */
5485 static rtx
5488 rtx p;
5491 {
5494 rtx set;
5495 /* Look for a general induction variable in a register. */
5500 {
5501 rtx src_reg;
5502 rtx dest_reg;
5503 rtx add_val;
5504 rtx mult_val;
5505 rtx ext_val;
5508 rtx last_consec_insn;
5517 /* Equivalent expression is a giv. */
5522 /* Don't try to handle any regs made by loop optimization.
5523 We have nothing on them in regno_first_uid, etc. */
5525 /* Don't recognize a BASIC_INDUCT_VAR here. */
5527 /* This must be the only place where the register is set. */
5529 /* or all sets must be consecutive and make a giv. */
5534 {
5538 /* If this is a library call, increase benefit. */
5542 /* Skip the consecutive insns, if there are any. */
5550 }
5551 }
5553 #ifndef DONT_REDUCE_ADDR
5554 /* Look for givs which are memory addresses. */
5555 /* This resulted in worse code on a VAX 8600. I wonder if it
5556 still does. */
5559 maybe_multiple);
5560 #endif
5562 /* Update the status of whether giv can derive other givs. This can
5563 change when we pass a label or an insn that updates a biv. */
5568 }
5569 \f
5570 /* Return 1 if X is a valid source for an initial value (or as value being
5571 compared against in an initial test).
5573 X must be either a register or constant and must not be clobbered between
5574 the current insn and the start of the loop.
5576 INSN is the insn containing X. */
5578 static int
5580 rtx x;
5581 rtx insn;
5583 rtx loop_start;
5584 {
5588 /* Only consider pseudos we know about initialized in insns whose luids
5589 we know. */
5594 /* Don't use call-clobbered registers across a call which clobbers it. On
5595 some machines, don't use any hard registers at all. */
5597 && (SMALL_REGISTER_CLASSES
5601 /* Don't use registers that have been clobbered before the start of the
5602 loop. */
5607 }
5608 \f
5609 /* Scan X for memory refs and check each memory address
5610 as a possible giv. INSN is the insn whose pattern X comes from.
5611 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5612 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5613 more than once in each loop iteration. */
5615 static void
5618 rtx x;
5619 rtx insn;
5621 {
5631 {
5647 {
5648 rtx src_reg;
5649 rtx add_val;
5650 rtx mult_val;
5651 rtx ext_val;
5654 /* This code used to disable creating GIVs with mult_val == 1 and
5655 add_val == 0. However, this leads to lost optimizations when
5656 it comes time to combine a set of related DEST_ADDR GIVs, since
5657 this one would not be seen. */
5662 {
5663 /* Found one; record it. */
5672 }
5673 }
5678 }
5680 /* Recursively scan the subexpressions for other mem refs. */
5686 maybe_multiple);
5690 maybe_multiple);
5691 }
5692 \f
5693 /* Fill in the data about one biv update.
5694 V is the `struct induction' in which we record the biv. (It is
5695 allocated by the caller, with alloca.)
5696 INSN is the insn that sets it.
5697 DEST_REG is the biv's reg.
5699 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5700 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5701 being set to INC_VAL.
5703 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5704 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5705 can be executed more than once per iteration. If MAYBE_MULTIPLE
5706 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5707 executed exactly once per iteration. */
5709 static void
5714 rtx insn;
5715 rtx dest_reg;
5716 rtx inc_val;
5717 rtx mult_val;
5721 {
5738 /* Add this to the reg's iv_class, creating a class
5739 if this is the first incrementation of the reg. */
5743 {
5744 /* Create and initialize new iv_class. */
5754 /* Set initial value to the reg itself. */
5757 /* We haven't seen the initializing insn yet */
5767 /* Add this class to ivs->list. */
5771 /* Put it in the array of biv register classes. */
5773 }
5774 else
5775 {
5776 /* Check if location is the same as a previous one. */
5780 {
5783 }
5784 }
5786 /* Update IV_CLASS entry for this biv. */
5795 }
5796 \f
5797 /* Fill in the data about one giv.
5798 V is the `struct induction' in which we record the giv. (It is
5799 allocated by the caller, with alloca.)
5800 INSN is the insn that sets it.
5801 BENEFIT estimates the savings from deleting this insn.
5802 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5803 into a register or is used as a memory address.
5805 SRC_REG is the biv reg which the giv is computed from.
5806 DEST_REG is the giv's reg (if the giv is stored in a reg).
5807 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5808 LOCATION points to the place where this giv's value appears in INSN. */
5810 static void
5815 rtx insn;
5816 rtx src_reg;
5817 rtx dest_reg;
5823 {
5828 rtx temp;
5830 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5831 undo the MULT canonicalization that we performed earlier. */
5861 /* The v->always_computable field is used in update_giv_derive, to
5862 determine whether a giv can be used to derive another giv. For a
5863 DEST_REG giv, INSN computes a new value for the giv, so its value
5864 isn't computable if INSN insn't executed every iteration.
5865 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5866 it does not compute a new value. Hence the value is always computable
5867 regardless of whether INSN is executed each iteration. */
5871 else
5877 {
5880 }
5882 {
5887 /* If the lifetime is zero, it means that this register is
5888 really a dead store. So mark this as a giv that can be
5889 ignored. This will not prevent the biv from being eliminated. */
5895 }
5897 /* Add the giv to the class of givs computed from one biv. */
5901 {
5904 /* Don't count DEST_ADDR. This is supposed to count the number of
5905 insns that calculate givs. */
5909 }
5910 else
5911 /* Fatal error, biv missing for this giv? */
5915 {
5918 }
5919 else
5920 {
5921 /* The giv can be replaced outright by the reduced register only if all
5922 of the following conditions are true:
5923 - the insn that sets the giv is always executed on any iteration
5924 on which the giv is used at all
5925 (there are two ways to deduce this:
5926 either the insn is executed on every iteration,
5927 or all uses follow that insn in the same basic block),
5928 - the giv is not used outside the loop
5929 - no assignments to the biv occur during the giv's lifetime. */
5932 /* Previous line always fails if INSN was moved by loop opt. */
5935 && (! not_every_iteration
5937 {
5938 /* Now check that there are no assignments to the biv within the
5939 giv's lifetime. This requires two separate checks. */
5941 /* Check each biv update, and fail if any are between the first
5942 and last use of the giv.
5944 If this loop contains an inner loop that was unrolled, then
5945 the insn modifying the biv may have been emitted by the loop
5946 unrolling code, and hence does not have a valid luid. Just
5947 mark the biv as not replaceable in this case. It is not very
5948 useful as a biv, because it is used in two different loops.
5949 It is very unlikely that we would be able to optimize the giv
5950 using this biv anyways. */
5955 {
5961 {
5965 }
5966 }
5968 /* If there are any backwards branches that go from after the
5969 biv update to before it, then this giv is not replaceable. */
5973 {
5977 }
5978 }
5979 else
5980 {
5981 /* May still be replaceable, we don't have enough info here to
5982 decide. */
5985 }
5986 }
5988 /* Record whether the add_val contains a const_int, for later use by
5989 combine_givs. */
5990 {
5995 ;
5999 {
6001 {
6006 else
6008 }
6011 }
6012 }
6016 }
6018 /* All this does is determine whether a giv can be made replaceable because
6019 its final value can be calculated. This code can not be part of record_giv
6020 above, because final_giv_value requires that the number of loop iterations
6021 be known, and that can not be accurately calculated until after all givs
6022 have been identified. */
6024 static void
6028 {
6031 /* DEST_ADDR givs will never reach here, because they are always marked
6032 replaceable above in record_giv. */
6034 /* The giv can be replaced outright by the reduced register only if all
6035 of the following conditions are true:
6036 - the insn that sets the giv is always executed on any iteration
6037 on which the giv is used at all
6038 (there are two ways to deduce this:
6039 either the insn is executed on every iteration,
6040 or all uses follow that insn in the same basic block),
6041 - its final value can be calculated (this condition is different
6042 than the one above in record_giv)
6043 - it's not used before the it's set
6044 - no assignments to the biv occur during the giv's lifetime. */
6046 #if 0
6047 /* This is only called now when replaceable is known to be false. */
6048 /* Clear replaceable, so that it won't confuse final_giv_value. */
6050 #endif
6055 {
6058 rtx last_giv_use;
6063 /* When trying to determine whether or not a biv increment occurs
6064 during the lifetime of the giv, we can ignore uses of the variable
6065 outside the loop because final_value is true. Hence we can not
6066 use regno_last_uid and regno_first_uid as above in record_giv. */
6068 /* Search the loop to determine whether any assignments to the
6069 biv occur during the giv's lifetime. Start with the insn
6070 that sets the giv, and search around the loop until we come
6071 back to that insn again.
6073 Also fail if there is a jump within the giv's lifetime that jumps
6074 to somewhere outside the lifetime but still within the loop. This
6075 catches spaghetti code where the execution order is not linear, and
6076 hence the above test fails. Here we assume that the giv lifetime
6077 does not extend from one iteration of the loop to the next, so as
6078 to make the test easier. Since the lifetime isn't known yet,
6079 this requires two loops. See also record_giv above. */
6084 {
6087 {
6090 }
6096 {
6097 /* It is possible for the BIV increment to use the GIV if we
6098 have a cycle. Thus we must be sure to check each insn for
6099 both BIV and GIV uses, and we must check for BIV uses
6100 first. */
6107 {
6109 {
6113 }
6115 }
6116 }
6117 }
6119 /* Now that the lifetime of the giv is known, check for branches
6120 from within the lifetime to outside the lifetime if it is still
6121 replaceable. */
6124 {
6127 {
6140 {
6149 }
6150 }
6151 }
6153 /* If it is replaceable, then save the final value. */
6156 }
6161 }
6162 \f
6163 /* Update the status of whether a giv can derive other givs.
6165 We need to do something special if there is or may be an update to the biv
6166 between the time the giv is defined and the time it is used to derive
6167 another giv.
6169 In addition, a giv that is only conditionally set is not allowed to
6170 derive another giv once a label has been passed.
6172 The cases we look at are when a label or an update to a biv is passed. */
6174 static void
6177 rtx p;
6178 {
6182 rtx tem;
6185 /* Search all IV classes, then all bivs, and finally all givs.
6187 There are three cases we are concerned with. First we have the situation
6188 of a giv that is only updated conditionally. In that case, it may not
6189 derive any givs after a label is passed.
6191 The second case is when a biv update occurs, or may occur, after the
6192 definition of a giv. For certain biv updates (see below) that are
6193 known to occur between the giv definition and use, we can adjust the
6194 giv definition. For others, or when the biv update is conditional,
6195 we must prevent the giv from deriving any other givs. There are two
6196 sub-cases within this case.
6198 If this is a label, we are concerned with any biv update that is done
6199 conditionally, since it may be done after the giv is defined followed by
6200 a branch here (actually, we need to pass both a jump and a label, but
6201 this extra tracking doesn't seem worth it).
6203 If this is a jump, we are concerned about any biv update that may be
6204 executed multiple times. We are actually only concerned about
6205 backward jumps, but it is probably not worth performing the test
6206 on the jump again here.
6208 If this is a biv update, we must adjust the giv status to show that a
6209 subsequent biv update was performed. If this adjustment cannot be done,
6210 the giv cannot derive further givs. */
6216 {
6218 {
6219 /* If cant_derive is already true, there is no point in
6220 checking all of these conditions again. */
6224 /* If this giv is conditionally set and we have passed a label,
6225 it cannot derive anything. */
6229 /* Skip givs that have mult_val == 0, since
6230 they are really invariants. Also skip those that are
6231 replaceable, since we know their lifetime doesn't contain
6232 any biv update. */
6236 /* The only way we can allow this giv to derive another
6237 is if this is a biv increment and we can form the product
6238 of biv->add_val and giv->mult_val. In this case, we will
6239 be able to compute a compensation. */
6241 {
6242 rtx ext_val_dummy;
6253 tem = simplify_giv_expr
6260 else
6262 }
6266 }
6267 }
6268 }
6269 \f
6270 /* Check whether an insn is an increment legitimate for a basic induction var.
6271 X is the source of insn P, or a part of it.
6272 MODE is the mode in which X should be interpreted.
6274 DEST_REG is the putative biv, also the destination of the insn.
6275 We accept patterns of these forms:
6276 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6277 REG = INVARIANT + REG
6279 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6280 store the additive term into *INC_VAL, and store the place where
6281 we found the additive term into *LOCATION.
6283 If X is an assignment of an invariant into DEST_REG, we set
6284 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6286 We also want to detect a BIV when it corresponds to a variable
6287 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6288 of the variable may be a PLUS that adds a SUBREG of that variable to
6289 an invariant and then sign- or zero-extends the result of the PLUS
6290 into the variable.
6292 Most GIVs in such cases will be in the promoted mode, since that is the
6293 probably the natural computation mode (and almost certainly the mode
6294 used for addresses) on the machine. So we view the pseudo-reg containing
6295 the variable as the BIV, as if it were simply incremented.
6297 Note that treating the entire pseudo as a BIV will result in making
6298 simple increments to any GIVs based on it. However, if the variable
6299 overflows in its declared mode but not its promoted mode, the result will
6300 be incorrect. This is acceptable if the variable is signed, since
6301 overflows in such cases are undefined, but not if it is unsigned, since
6302 those overflows are defined. So we only check for SIGN_EXTEND and
6303 not ZERO_EXTEND.
6305 If we cannot find a biv, we return 0. */
6307 static int
6310 rtx x;
6312 rtx dest_reg;
6313 rtx p;
6317 {
6325 {
6331 {
6333 }
6338 {
6340 }
6341 else
6354 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6355 handle addition of promoted variables.
6356 ??? The comment at the start of this function is wrong: promoted
6357 variable increments don't look like it says they do. */
6363 /* If this register is assigned in a previous insn, look at its
6364 source, but don't go outside the loop or past a label. */
6366 /* If this sets a register to itself, we would repeat any previous
6367 biv increment if we applied this strategy blindly. */
6373 {
6374 rtx dest;
6375 do
6376 {
6378 }
6407 }
6408 /* Fall through. */
6410 /* Can accept constant setting of biv only when inside inner most loop.
6411 Otherwise, a biv of an inner loop may be incorrectly recognized
6412 as a biv of the outer loop,
6413 causing code to be moved INTO the inner loop. */
6420 /* convert_modes aborts if we try to convert to or from CCmode, so just
6421 exclude that case. It is very unlikely that a condition code value
6422 would be a useful iterator anyways. convert_modes aborts if we try to
6423 convert a float mode to non-float or vice versa too. */
6427 {
6428 /* Possible bug here? Perhaps we don't know the mode of X. */
6432 }
6433 else
6441 /* Similar, since this can be a sign extension. */
6446 ;
6460 location);
6465 }
6466 }
6467 \f
6468 /* A general induction variable (giv) is any quantity that is a linear
6469 function of a basic induction variable,
6470 i.e. giv = biv * mult_val + add_val.
6471 The coefficients can be any loop invariant quantity.
6472 A giv need not be computed directly from the biv;
6473 it can be computed by way of other givs. */
6475 /* Determine whether X computes a giv.
6476 If it does, return a nonzero value
6477 which is the benefit from eliminating the computation of X;
6478 set *SRC_REG to the register of the biv that it is computed from;
6479 set *ADD_VAL and *MULT_VAL to the coefficients,
6480 such that the value of X is biv * mult + add; */
6482 static int
6486 rtx x;
6494 {
6498 /* If this is an invariant, forget it, it isn't a giv. */
6509 {
6512 /* Since this is now an invariant and wasn't before, it must be a giv
6513 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6514 with. */
6521 /* This is equivalent to a BIV. */
6528 /* Either (plus (biv) (invar)) or
6529 (plus (mult (biv) (invar_1)) (invar_2)). */
6531 {
6534 }
6535 else
6536 {
6539 }
6544 /* ADD_VAL is zero. */
6552 }
6554 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6555 unless they are CONST_INT). */
6563 else
6566 /* Always return true if this is a giv so it will be detected as such,
6567 even if the benefit is zero or negative. This allows elimination
6568 of bivs that might otherwise not be eliminated. */
6570 }
6571 \f
6572 /* Given an expression, X, try to form it as a linear function of a biv.
6573 We will canonicalize it to be of the form
6574 (plus (mult (BIV) (invar_1))
6575 (invar_2))
6576 with possible degeneracies.
6578 The invariant expressions must each be of a form that can be used as a
6579 machine operand. We surround then with a USE rtx (a hack, but localized
6580 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6581 routine; it is the caller's responsibility to strip them.
6583 If no such canonicalization is possible (i.e., two biv's are used or an
6584 expression that is neither invariant nor a biv or giv), this routine
6585 returns 0.
6587 For a nonzero return, the result will have a code of CONST_INT, USE,
6588 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6590 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6595 static rtx
6598 rtx x;
6601 {
6606 rtx tem;
6608 /* If this is not an integer mode, or if we cannot do arithmetic in this
6609 mode, this can't be a giv. */
6616 {
6623 /* Put constant last, CONST_INT last if both constant. */
6631 /* Handle addition of zero, then addition of an invariant. */
6636 {
6639 /* Adding two invariants must result in an invariant, so enclose
6640 addition operation inside a USE and return it. */
6650 else
6659 /* biv + invar or mult + invar. Return sum. */
6663 /* (a + invar_1) + invar_2. Associate. */
6664 return
6670 arg1)),
6675 }
6677 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6678 MULT to reduce cases. */
6684 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6685 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6686 Recurse to associate the second PLUS. */
6691 return
6699 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6715 /* Handle "a - b" as "a + b * (-1)". */
6721 constm1_rtx)),
6730 /* Put constant last, CONST_INT last if both constant. */
6735 /* If second argument is not now constant, not giv. */
6739 /* Handle multiply by 0 or 1. */
6747 {
6749 /* biv * invar. Done. */
6753 /* Product of two constants. */
6757 /* invar * invar is a giv, but attempt to simplify it somehow. */
6763 {
6764 /* (invar_0 * invar_1) * invar_2. Associate. */
6771 arg1)),
6773 }
6774 /* Propagate the MULT expressions to the intermost nodes. */
6776 {
6777 /* (invar_0 + invar_1) * invar_2. Distribute. */
6783 arg1),
6787 arg1)),
6789 }
6793 /* (a * invar_1) * invar_2. Associate. */
6799 arg1)),
6803 /* (a + invar_1) * invar_2. Distribute. */
6808 arg1),
6811 arg1)),
6816 }
6819 /* Shift by constant is multiply by power of two. */
6823 return
6832 /* "-a" is "a * (-1)" */
6838 /* "~a" is "-a - 1". Silly, but easy. */
6842 const1_rtx),
6846 /* Already in proper form for invariant. */
6852 /* Conditionally recognize extensions of simple IVs. After we've
6853 computed loop traversal counts and verified the range of the
6854 source IV, we'll reevaluate this as a GIV. */
6856 {
6859 {
6862 }
6863 }
6867 /* If this is a new register, we can't deal with it. */
6871 /* Check for biv or giv. */
6873 {
6877 {
6880 /* Form expression from giv and add benefit. Ensure this giv
6881 can derive another and subtract any needed adjustment if so. */
6883 /* Increasing the benefit here is risky. The only case in which it
6884 is arguably correct is if this is the only use of V. In other
6885 cases, this will artificially inflate the benefit of the current
6886 giv, and lead to suboptimal code. Thus, it is disabled, since
6887 potentially not reducing an only marginally beneficial giv is
6888 less harmful than reducing many givs that are not really
6889 beneficial. */
6890 {
6894 }
6907 {
6910 }
6911 else
6912 {
6915 }
6917 }
6920 do_default:
6921 /* If it isn't an induction variable, and it is invariant, we
6922 may be able to simplify things further by looking through
6923 the bits we just moved outside the loop. */
6925 {
6931 {
6932 /* Ok, we found a match. Substitute and simplify. */
6934 /* If we match another movable, we must use that, as
6935 this one is going away. */
6940 /* If consec is nonzero, this is a member of a group of
6941 instructions that were moved together. We handle this
6942 case only to the point of seeking to the last insn and
6943 looking for a REG_EQUAL. Fail if we don't find one. */
6945 {
6948 do
6949 {
6951 }
6957 }
6958 else
6959 {
6963 }
6966 {
6967 /* What we are most interested in is pointer
6968 arithmetic on invariants -- only take
6969 patterns we may be able to do something with. */
6975 {
6977 benefit);
6980 }
6985 {
6990 }
6991 }
6993 }
6994 }
6996 }
6998 /* Fall through to general case. */
7000 /* If invariant, return as USE (unless CONST_INT).
7001 Otherwise, not giv. */
7006 {
7015 }
7016 else
7018 }
7019 }
7021 /* This routine folds invariants such that there is only ever one
7022 CONST_INT in the summation. It is only used by simplify_giv_expr. */
7024 static rtx
7027 {
7033 {
7036 }
7039 {
7042 }
7043 else
7044 {
7047 }
7048 }
7050 static rtx
7054 {
7056 {
7060 else
7063 }
7066 else
7069 }
7070 \f
7071 /* Help detect a giv that is calculated by several consecutive insns;
7072 for example,
7073 giv = biv * M
7074 giv = giv + A
7075 The caller has already identified the first insn P as having a giv as dest;
7076 we check that all other insns that set the same register follow
7077 immediately after P, that they alter nothing else,
7078 and that the result of the last is still a giv.
7080 The value is 0 if the reg set in P is not really a giv.
7081 Otherwise, the value is the amount gained by eliminating
7082 all the consecutive insns that compute the value.
7084 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7085 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7087 The coefficients of the ultimate giv value are stored in
7088 *MULT_VAL and *ADD_VAL. */
7090 static int
7095 rtx p;
7096 rtx src_reg;
7097 rtx dest_reg;
7102 {
7108 rtx temp;
7109 rtx set;
7111 /* Indicate that this is a giv so that we can update the value produced in
7112 each insn of the multi-insn sequence.
7114 This induction structure will be used only by the call to
7115 general_induction_var below, so we can allocate it on our stack.
7116 If this is a giv, our caller will replace the induct var entry with
7117 a new induction structure. */
7138 {
7142 /* If libcall, skip to end of call sequence. */
7153 /* Giv created by equivalent expression. */
7159 {
7163 count--;
7167 }
7169 {
7170 /* Allow insns that set something other than this giv to a
7171 constant. Such insns are needed on machines which cannot
7172 include long constants and should not disqualify a giv. */
7181 }
7182 }
7187 }
7188 \f
7189 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7190 represented by G1. If no such expression can be found, or it is clear that
7191 it cannot possibly be a valid address, 0 is returned.
7193 To perform the computation, we note that
7194 G1 = x * v + a and
7195 G2 = y * v + b
7196 where `v' is the biv.
7198 So G2 = (y/b) * G1 + (b - a*y/x).
7200 Note that MULT = y/x.
7202 Update: A and B are now allowed to be additive expressions such that
7203 B contains all variables in A. That is, computing B-A will not require
7204 subtracting variables. */
7206 static rtx
7209 {
7210 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7215 /* If MULT is not 1, we cannot handle A with non-constants, since we
7216 would then be required to subtract multiples of the registers in A.
7217 This is theoretically possible, and may even apply to some Fortran
7218 constructs, but it is a lot of work and we do not attempt it here. */
7223 /* In general these structures are sorted top to bottom (down the PLUS
7224 chain), but not left to right across the PLUS. If B is a higher
7225 order giv than A, we can strip one level and recurse. If A is higher
7226 order, we'll eventually bail out, but won't know that until the end.
7227 If they are the same, we'll strip one level around this loop. */
7230 {
7242 /* We matched: remove one reg completely. */
7245 /* An alternate match. */
7248 /* An alternate match. */
7250 else
7251 {
7252 /* Indicates an extra register in B. Strip one level from B and
7253 recurse, hoping B was the higher order expression. */
7258 }
7259 }
7261 /* Here we are at the last level of A, go through the cases hoping to
7262 get rid of everything but a constant. */
7265 {
7278 }
7280 {
7282 }
7284 {
7289 }
7291 {
7296 else
7298 }
7303 }
7305 rtx
7308 {
7311 /* The value that G1 will be multiplied by must be a constant integer. Also,
7312 the only chance we have of getting a valid address is if b*c/a (see above
7313 for notation) is also an integer. */
7316 {
7321 }
7324 else
7325 {
7326 /* ??? Find out if the one is a multiple of the other? */
7328 }
7332 {
7333 /* Failed. If we've got a multiplication factor between G1 and G2,
7334 scale G1's addend and try again. */
7336 {
7340 {
7341 HOST_WIDE_INT m;
7345 }
7346 else
7347 {
7349 mult);
7350 }
7353 }
7354 }
7358 /* Form simplified final result. */
7363 else
7368 else
7369 {
7372 {
7376 }
7379 }
7380 }
7381 \f
7382 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7383 represented by G1. This indicates that G2 should be combined with G1 and
7384 that G2 can use (either directly or via an address expression) a register
7385 used to represent G1. */
7387 static rtx
7390 {
7393 /* With the introduction of ext dependent givs, we must care for modes.
7394 G2 must not use a wider mode than G1. */
7404 /* If these givs are identical, they can be combined. We use the results
7405 of express_from because the addends are not in a canonical form, so
7406 rtx_equal_p is a weaker test. */
7407 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7408 combination to be the other way round. */
7411 {
7413 }
7415 /* If G2 can be expressed as a function of G1 and that function is valid
7416 as an address and no more expensive than using a register for G2,
7417 the expression of G2 in terms of G1 can be used. */
7424 }
7425 \f
7426 /* Check each extension dependent giv in this class to see if its
7427 root biv is safe from wrapping in the interior mode, which would
7428 make the giv illegal. */
7430 static void
7434 {
7437 HOST_WIDE_INT start_val;
7443 /* Make sure the iteration data is available. We must have
7444 constants in order to be certain of no overflow. */
7445 /* ??? An unknown iteration count with an increment of +-1
7446 combined with friendly exit tests of against an invariant
7447 value is also amenable to optimization. Not implemented. */
7453 /* Make sure the host can represent the arithmetic. */
7455 {
7457 HOST_WIDE_INT s_end_val;
7469 /* Check for host arithmetic overflow. */
7471 {
7473 HOST_WIDE_INT s_max;
7480 /* Check zero extension of biv ok. */
7482 /* Check for host arithmetic overflow. */
7483 && (neg_incr
7486 /* Check for target arithmetic overflow. */
7487 && (neg_incr
7490 {
7492 }
7494 /* Check sign extension of biv ok. */
7495 /* ??? While it is true that overflow with signed and pointer
7496 arithmetic is undefined, I fear too many programmers don't
7497 keep this fact in mind -- myself included on occasion.
7498 So leave alone with the signed overflow optimizations. */
7500 /* Check for host arithmetic overflow. */
7501 && (neg_incr
7504 /* Check for target arithmetic overflow. */
7505 && (neg_incr
7508 {
7510 }
7511 }
7512 }
7514 /* Invalidate givs that fail the tests. */
7517 {
7522 {
7531 /* We don't know whether this value is being used as either
7532 signed or unsigned, so to safely truncate we must satisfy
7533 both. The initial check here verifies the BIV itself;
7534 once that is successful we may check its range wrt the
7535 derived GIV. */
7537 {
7541 /* We know from the above that both endpoints are nonnegative,
7542 and that there is no wrapping. Verify that both endpoints
7543 are within the (signed) range of the outer mode. */
7546 }
7551 }
7554 {
7556 {
7560 }
7561 }
7562 else
7563 {
7565 {
7570 else
7571 {
7576 else
7578 }
7583 }
7586 }
7587 }
7588 }
7590 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7592 rtx
7595 rtx value;
7596 {
7602 /* Recall that check_ext_dependent_givs verified that the known bounds
7603 of a biv did not overflow or wrap with respect to the extension for
7604 the giv. Therefore, constants need no additional adjustment. */
7608 /* Otherwise, we must adjust the value to compensate for the
7609 differing modes of the biv and the giv. */
7611 }
7612 \f
7613 struct combine_givs_stats
7614 {
7617 };
7619 static int
7623 {
7630 /* Stabilize the sort. */
7634 }
7636 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7637 any other. If so, point SAME to the giv combined with and set NEW_REG to
7638 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7639 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7641 static void
7645 {
7646 /* Additional benefit to add for being combined multiple times. */
7654 /* Count givs, because bl->giv_count is incorrect here. */
7658 giv_count++;
7660 giv_array
7671 {
7673 rtx single_use;
7678 /* If a DEST_REG GIV is used only once, do not allow it to combine
7679 with anything, for in doing so we will gain nothing that cannot
7680 be had by simply letting the GIV with which we would have combined
7681 to be reduced on its own. The losage shows up in particular with
7682 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7683 be seen elsewhere as well. */
7690 /* Add an additional weight for zero addends. */
7695 {
7696 rtx this_combine;
7701 {
7704 }
7705 }
7707 }
7709 /* Iterate, combining until we can't. */
7710 restart:
7714 {
7717 {
7723 }
7725 }
7728 {
7734 /* If it has already been combined, skip. */
7739 {
7742 /* If it has already been combined, skip. */
7744 {
7749 /* For destination, we now may replace by mem expression instead
7750 of register. This changes the costs considerably, so add the
7751 compensation. */
7761 /* ??? The new final_[bg]iv_value code does a much better job
7762 of finding replaceable giv's, and hence this code may no
7763 longer be necessary. */
7767 /* To help optimize the next set of combinations, remove
7768 this giv from the benefits of other potential mates. */
7770 {
7774 }
7781 }
7782 }
7784 /* To help optimize the next set of combinations, remove
7785 this giv from the benefits of other potential mates. */
7787 {
7789 {
7793 }
7797 /* We've finished with this giv, and everything it touched.
7798 Restart the combination so that proper weights for the
7799 rest of the givs are properly taken into account. */
7800 /* ??? Ideally we would compact the arrays at this point, so
7801 as to not cover old ground. But sanely compacting
7802 can_combine is tricky. */
7804 }
7805 }
7807 /* Clean up. */
7810 }
7811 \f
7812 /* Generate sequence for REG = B * M + A. */
7814 static rtx
7820 {
7821 rtx seq;
7822 rtx result;
7825 /* Use unsigned arithmetic. */
7833 }
7836 /* Update registers created in insn sequence SEQ. */
7838 static void
7841 rtx seq;
7842 {
7843 rtx insn;
7845 /* Update register info for alias analysis. */
7851 {
7854 {
7861 }
7862 }
7866 }
7869 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7871 void
7878 basic_block before_bb;
7879 rtx before_insn;
7880 {
7881 rtx seq;
7884 {
7887 }
7889 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7892 /* Increase the lifetime of any invariants moved further in code. */
7899 /* It is possible that the expansion created lots of new registers.
7900 Iterate over the sequence we just created and record them all. */
7902 }
7905 /* Emit insns in loop pre-header to set REG = B * M + A. */
7907 void
7914 {
7915 rtx seq;
7917 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7920 /* Increase the lifetime of any invariants moved further in code.
7921 ???? Is this really necessary? */
7928 /* It is possible that the expansion created lots of new registers.
7929 Iterate over the sequence we just created and record them all. */
7931 }
7934 /* Emit insns after loop to set REG = B * M + A. */
7936 void
7943 {
7944 rtx seq;
7946 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7951 /* It is possible that the expansion created lots of new registers.
7952 Iterate over the sequence we just created and record them all. */
7954 }
7958 /* Similar to gen_add_mult, but compute cost rather than generating
7959 sequence. */
7961 static int
7967 {
7977 {
7982 }
7985 }
7986 \f
7987 /* Test whether A * B can be computed without
7988 an actual multiply insn. Value is 1 if so.
7990 ??? This function stinks because it generates a ton of wasted RTL
7991 ??? and as a result fragments GC memory to no end. There are other
7992 ??? places in the compiler which are invoked a lot and do the same
7993 ??? thing, generate wasted RTL just to see if something is possible. */
7995 static int
7997 rtx a;
7998 rtx b;
7999 {
8000 rtx tmp;
8003 /* If only one is constant, make it B. */
8007 /* If first constant, both constant, so don't need multiply. */
8011 /* If second not constant, neither is constant, so would need multiply. */
8015 /* One operand is constant, so might not need multiply insn. Generate the
8016 code for the multiply and see if a call or multiply, or long sequence
8017 of insns is generated. */
8026 {
8029 {
8039 {
8042 }
8045 }
8046 }
8056 }
8057 \f
8058 /* Check to see if loop can be terminated by a "decrement and branch until
8059 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
8060 Also try reversing an increment loop to a decrement loop
8061 to see if the optimization can be performed.
8062 Value is nonzero if optimization was performed. */
8064 /* This is useful even if the architecture doesn't have such an insn,
8065 because it might change a loops which increments from 0 to n to a loop
8066 which decrements from n to 0. A loop that decrements to zero is usually
8067 faster than one that increments from zero. */
8069 /* ??? This could be rewritten to use some of the loop unrolling procedures,
8070 such as approx_final_value, biv_total_increment, loop_iterations, and
8071 final_[bg]iv_value. */
8073 static int
8077 {
8082 rtx reg;
8083 rtx jump_label;
8084 rtx final_value;
8085 rtx start_value;
8086 rtx new_add_val;
8087 rtx comparison;
8088 rtx before_comparison;
8089 rtx p;
8090 rtx jump;
8091 rtx first_compare;
8096 /* If last insn is a conditional branch, and the insn before tests a
8097 register value, try to optimize it. Otherwise, we can't do anything. */
8106 /* Try to compute whether the compare/branch at the loop end is one or
8107 two instructions. */
8113 else
8116 {
8117 /* If more than one condition is present to control the loop, then
8118 do not proceed, as this function does not know how to rewrite
8119 loop tests with more than one condition.
8121 Look backwards from the first insn in the last comparison
8122 sequence and see if we've got another comparison sequence. */
8124 rtx jump1;
8128 }
8130 /* Check all of the bivs to see if the compare uses one of them.
8131 Skip biv's set more than once because we can't guarantee that
8132 it will be zero on the last iteration. Also skip if the biv is
8133 used between its update and the test insn. */
8136 {
8141 first_compare))
8143 }
8148 /* Look for the case where the basic induction variable is always
8149 nonnegative, and equals zero on the last iteration.
8150 In this case, add a reg_note REG_NONNEG, which allows the
8151 m68k DBRA instruction to be used. */
8159 {
8160 /* Initial value must be greater than 0,
8161 init_val % -dec_value == 0 to ensure that it equals zero on
8162 the last iteration */
8168 {
8169 /* register always nonnegative, add REG_NOTE to branch */
8177 }
8179 /* If the decrement is 1 and the value was tested as >= 0 before
8180 the loop, then we can safely optimize. */
8182 {
8195 {
8203 }
8204 }
8205 }
8208 {
8209 /* Try to change inc to dec, so can apply above optimization. */
8210 /* Can do this if:
8211 all registers modified are induction variables or invariant,
8212 all memory references have non-overlapping addresses
8213 (obviously true if only one write)
8214 allow 2 insns for the compare/jump at the end of the loop. */
8215 /* Also, we must avoid any instructions which use both the reversed
8216 biv and another biv. Such instructions will fail if the loop is
8217 reversed. We meet this condition by requiring that either
8218 no_use_except_counting is true, or else that there is only
8219 one biv. */
8221 /* 1 if the iteration var is used only to count iterations. */
8223 /* 1 if the loop has no memory store, or it has a single memory store
8224 which is reversible. */
8230 {
8234 /* If there are no givs for this biv, and the only exit is the
8235 fall through at the end of the loop, then
8236 see if perhaps there are no uses except to count. */
8240 {
8245 /* An insn that sets the biv is okay. */
8246 ;
8250 {
8251 /* If either of these insns uses the biv and sets a pseudo
8252 that has more than one usage, then the biv has uses
8253 other than counting since it's used to derive a value
8254 that is used more than one time. */
8256 regs);
8258 {
8261 }
8262 }
8264 {
8267 }
8268 }
8270 /* A biv has uses besides counting if it is used to set
8271 another biv. */
8275 {
8278 }
8279 }
8282 /* No need to worry about MEMs. */
8283 ;
8285 {
8290 /* If the loop has a single store, and the destination address is
8291 invariant, then we can't reverse the loop, because this address
8292 might then have the wrong value at loop exit.
8293 This would work if the source was invariant also, however, in that
8294 case, the insn should have been moved out of the loop. */
8297 {
8300 /* If we could prove that each of the memory locations
8301 written to was different, then we could reverse the
8302 store -- but we don't presently have any way of
8303 knowing that. */
8306 /* If the store depends on a register that is set after the
8307 store, it depends on the initial value, and is thus not
8308 reversible. */
8310 {
8317 }
8318 }
8319 }
8320 else
8323 /* This code only acts for innermost loops. Also it simplifies
8324 the memory address check by only reversing loops with
8325 zero or one memory access.
8326 Two memory accesses could involve parts of the same array,
8327 and that can't be reversed.
8328 If the biv is used only for counting, than we don't need to worry
8329 about all these things. */
8335 && reversible_mem_store
8340 {
8341 rtx tem;
8343 /* Loop can be reversed. */
8347 /* Now check other conditions:
8349 The increment must be a constant, as must the initial value,
8350 and the comparison code must be LT.
8352 This test can probably be improved since +/- 1 in the constant
8353 can be obtained by changing LT to LE and vice versa; this is
8354 confusing. */
8357 /* for constants, LE gets turned into LT */
8361 {
8372 comparison_const_width
8374 else
8375 comparison_const_width
8379 comparison_sign_mask
8382 /* If the comparison value is not a loop invariant, then we
8383 can not reverse this loop.
8385 ??? If the insns which initialize the comparison value as
8386 a whole compute an invariant result, then we could move
8387 them out of the loop and proceed with loop reversal. */
8395 /* Normalize the initial value if it is an integer and
8396 has no other use except as a counter. This will allow
8397 a few more loops to be reversed. */
8401 {
8403 /* The code below requires comparison_val to be a multiple
8404 of add_val in order to do the loop reversal, so
8405 round up comparison_val to a multiple of add_val.
8406 Since comparison_value is constant, we know that the
8407 current comparison code is LT. */
8409 comparison_val
8411 /* We postpone overflow checks for COMPARISON_VAL here;
8412 even if there is an overflow, we might still be able to
8413 reverse the loop, if converting the loop exit test to
8414 NE is possible. */
8416 }
8418 /* First check if we can do a vanilla loop reversal. */
8420 /* If we have a decrement_and_branch_on_count,
8421 prefer the NE test, since this will allow that
8422 instruction to be generated. Note that we must
8423 use a vanilla loop reversal if the biv is used to
8424 calculate a giv or has a non-counting use. */
8425 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8426 && defined (HAVE_decrement_and_branch_on_count)
8430 #endif
8432 /* Now do postponed overflow checks on COMPARISON_VAL. */
8435 {
8436 /* Register will always be nonnegative, with value
8437 0 on last iteration */
8441 }
8445 {
8448 }
8449 else
8455 /* If the initial value is not zero, or if the comparison
8456 value is not an exact multiple of the increment, then we
8457 can not reverse this loop. */
8460 {
8463 }
8464 else
8465 {
8468 }
8472 /* Reset these in case we normalized the initial value
8473 and comparison value above. */
8476 {
8478 final_value
8480 }
8483 /* Save some info needed to produce the new insns. */
8488 /* Set start_value; if this is not a CONST_INT, we need
8489 to generate a SUB.
8490 Initialize biv to start_value before loop start.
8491 The old initializing insn will be deleted as a
8492 dead store by flow.c. */
8495 {
8498 }
8500 {
8508 start_value
8514 }
8516 {
8519 initial_value);
8523 start_value
8526 }
8527 else
8528 /* We could handle the other cases too, but it'll be
8529 better to have a testcase first. */
8532 /* We may not have a single insn which can increment a reg, so
8533 create a sequence to hold all the insns from expand_inc. */
8542 /* Update biv info to reflect its new status. */
8547 /* Update loop info. */
8556 /* Inc LABEL_NUSES so that delete_insn will
8557 not delete the label. */
8560 /* Emit an insn after the end of the loop to set the biv's
8561 proper exit value if it is used anywhere outside the loop. */
8567 /* Delete compare/branch at end of loop. */
8572 /* Add new compare/branch insn at end of loop. */
8584 ;
8590 {
8592 {
8593 /* Increment of LABEL_NUSES done above. */
8594 /* Register is now always nonnegative,
8595 so add REG_NONNEG note to the branch. */
8598 }
8600 }
8602 /* No insn may reference both the reversed and another biv or it
8603 will fail (see comment near the top of the loop reversal
8604 code).
8605 Earlier on, we have verified that the biv has no use except
8606 counting, or it is the only biv in this function.
8607 However, the code that computes no_use_except_counting does
8608 not verify reg notes. It's possible to have an insn that
8609 references another biv, and has a REG_EQUAL note with an
8610 expression based on the reversed biv. To avoid this case,
8611 remove all REG_EQUAL notes based on the reversed biv
8612 here. */
8615 {
8618 /* If this is a set of a GIV based on the reversed biv, any
8619 REG_EQUAL notes should still be correct. */
8626 {
8631 else
8633 }
8634 }
8636 /* Mark that this biv has been reversed. Each giv which depends
8637 on this biv, and which is also live past the end of the loop
8638 will have to be fixed up. */
8643 {
8647 else
8649 }
8652 }
8653 }
8654 }
8657 }
8658 \f
8659 /* Verify whether the biv BL appears to be eliminable,
8660 based on the insns in the loop that refer to it.
8662 If ELIMINATE_P is nonzero, actually do the elimination.
8664 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8665 determine whether invariant insns should be placed inside or at the
8666 start of the loop. */
8668 static int
8674 {
8677 rtx p;
8679 /* Scan all insns in the loop, stopping if we find one that uses the
8680 biv in a way that we cannot eliminate. */
8683 {
8687 rtx note;
8689 /* If this is a libcall that sets a giv, skip ahead to its end. */
8691 {
8695 {
8700 {
8707 }
8708 }
8709 }
8711 /* Closely examine the insn if the biv is mentioned. */
8716 {
8722 }
8724 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8729 }
8732 {
8737 }
8740 }
8741 \f
8742 /* INSN and REFERENCE are instructions in the same insn chain.
8743 Return nonzero if INSN is first. */
8745 int
8748 {
8752 {
8753 /* Start with test for not first so that INSN == REFERENCE yields not
8754 first. */
8760 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8761 previous insn, hence the <= comparison below does not work if
8762 P is a note. */
8773 }
8774 }
8776 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8777 the offset that we have to take into account due to auto-increment /
8778 div derivation is zero. */
8779 static int
8782 rtx insn;
8783 {
8784 /* If the giv V had the auto-inc address optimization applied
8785 to it, and INSN occurs between the giv insn and the biv
8786 insn, then we'd have to adjust the value used here.
8787 This is rare, so we don't bother to make this possible. */
8796 }
8798 /* If BL appears in X (part of the pattern of INSN), see if we can
8799 eliminate its use. If so, return 1. If not, return 0.
8801 If BIV does not appear in X, return 1.
8803 If ELIMINATE_P is nonzero, actually do the elimination.
8804 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8805 Depending on how many items have been moved out of the loop, it
8806 will either be before INSN (when WHERE_INSN is nonzero) or at the
8807 start of the loop (when WHERE_INSN is zero). */
8809 static int
8815 basic_block where_bb;
8816 rtx where_insn;
8817 {
8823 #ifdef HAVE_cc0
8825 #endif
8831 {
8833 /* If we haven't already been able to do something with this BIV,
8834 we can't eliminate it. */
8840 /* If this sets the BIV, it is not a problem. */
8844 /* If this is an insn that defines a giv, it is also ok because
8845 it will go away when the giv is reduced. */
8850 #ifdef HAVE_cc0
8852 {
8853 /* Can replace with any giv that was reduced and
8854 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8855 Require a constant for MULT_VAL, so we know it's nonzero.
8856 ??? We disable this optimization to avoid potential
8857 overflows. */
8865 {
8872 /* If the giv has the opposite direction of change,
8873 then reverse the comparison. */
8877 else
8880 /* We can probably test that giv's reduced reg. */
8883 }
8885 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8886 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8887 Require a constant for MULT_VAL, so we know it's nonzero.
8888 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8889 overflow problem. */
8901 {
8908 /* If the giv has the opposite direction of change,
8909 then reverse the comparison. */
8913 else
8917 /* Replace biv with the giv's reduced register. */
8922 /* Insn doesn't support that constant or invariant. Copy it
8923 into a register (it will be a loop invariant.) */
8930 /* Substitute the new register for its invariant value in
8931 the compare expression. */
8935 }
8936 }
8937 #endif
8944 /* See if either argument is the biv. */
8949 else
8953 {
8954 /* First try to replace with any giv that has constant positive
8955 mult_val and constant add_val. We might be able to support
8956 negative mult_val, but it seems complex to do it in general. */
8968 {
8972 /* Don't eliminate if the linear combination that makes up
8973 the giv overflows when it is applied to ARG. */
8975 {
8976 rtx add_val;
8980 else
8986 }
8991 /* Replace biv with the giv's reduced reg. */
8994 /* If all constants are actually constant integers and
8995 the derived constant can be directly placed in the COMPARE,
8996 do so. */
8999 {
9002 }
9003 else
9004 {
9005 /* Otherwise, load it into a register. */
9010 }
9016 }
9018 /* Look for giv with positive constant mult_val and nonconst add_val.
9019 Insert insns to calculate new compare value.
9020 ??? Turn this off due to possible overflow. */
9028 {
9029 rtx tem;
9039 /* Replace biv with giv's reduced register. */
9043 /* Compute value to compare against. */
9047 /* Use it in this insn. */
9051 }
9052 }
9054 {
9056 {
9057 /* Look for giv with constant positive mult_val and nonconst
9058 add_val. Insert insns to compute new compare value.
9059 ??? Turn this off due to possible overflow. */
9066 {
9067 rtx tem;
9077 /* Replace biv with giv's reduced register. */
9081 /* Compute value to compare against. */
9088 }
9089 }
9091 /* This code has problems. Basically, you can't know when
9092 seeing if we will eliminate BL, whether a particular giv
9093 of ARG will be reduced. If it isn't going to be reduced,
9094 we can't eliminate BL. We can try forcing it to be reduced,
9095 but that can generate poor code.
9097 The problem is that the benefit of reducing TV, below should
9098 be increased if BL can actually be eliminated, but this means
9099 we might have to do a topological sort of the order in which
9100 we try to process biv. It doesn't seem worthwhile to do
9101 this sort of thing now. */
9103 #if 0
9104 /* Otherwise the reg compared with had better be a biv. */
9109 /* Look for a pair of givs, one for each biv,
9110 with identical coefficients. */
9112 {
9124 {
9131 /* Replace biv with its giv's reduced reg. */
9133 /* Replace other operand with the other giv's
9134 reduced reg. */
9137 }
9138 }
9139 #endif
9140 }
9142 /* If we get here, the biv can't be eliminated. */
9146 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9147 biv is used in it, since it will be replaced. */
9155 }
9157 /* See if any subexpression fails elimination. */
9160 {
9162 {
9175 }
9176 }
9179 }
9180 \f
9181 /* Return nonzero if the last use of REG
9182 is in an insn following INSN in the same basic block. */
9184 static int
9186 rtx reg;
9187 rtx insn;
9188 {
9189 rtx n;
9193 {
9196 }
9198 }
9199 \f
9200 /* Called via `note_stores' to record the initial value of a biv. Here we
9201 just record the location of the set and process it later. */
9203 static void
9205 rtx dest;
9206 rtx set;
9208 {
9219 /* If this is the first set found, record it. */
9221 {
9224 }
9225 }
9226 \f
9227 /* If any of the registers in X are "old" and currently have a last use earlier
9228 than INSN, update them to have a last use of INSN. Their actual last use
9229 will be the previous insn but it will not have a valid uid_luid so we can't
9230 use it. X must be a source expression only. */
9232 static void
9234 rtx x;
9235 rtx insn;
9236 {
9237 /* Check for the case where INSN does not have a valid luid. In this case,
9238 there is no need to modify the regno_last_uid, as this can only happen
9239 when code is inserted after the loop_end to set a pseudo's final value,
9240 and hence this insn will never be the last use of x.
9241 ???? This comment is not correct. See for example loop_givs_reduce.
9242 This may insert an insn before another new insn. */
9246 {
9248 }
9249 else
9250 {
9254 {
9260 }
9261 }
9262 }
9263 \f
9264 /* Given an insn INSN and condition COND, return the condition in a
9265 canonical form to simplify testing by callers. Specifically:
9267 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9268 (2) Both operands will be machine operands; (cc0) will have been replaced.
9269 (3) If an operand is a constant, it will be the second operand.
9270 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9271 for GE, GEU, and LEU.
9273 If the condition cannot be understood, or is an inequality floating-point
9274 comparison which needs to be reversed, 0 will be returned.
9276 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9278 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9279 insn used in locating the condition was found. If a replacement test
9280 of the condition is desired, it should be placed in front of that
9281 insn and we will be sure that the inputs are still valid.
9283 If WANT_REG is nonzero, we wish the condition to be relative to that
9284 register, if possible. Therefore, do not canonicalize the condition
9285 further. */
9287 rtx
9289 rtx insn;
9290 rtx cond;
9293 rtx want_reg;
9294 {
9297 rtx set;
9298 rtx tem;
9316 /* If we are comparing a register with zero, see if the register is set
9317 in the previous insn to a COMPARE or a comparison operation. Perform
9318 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9319 in cse.c */
9324 {
9325 /* Set nonzero when we find something of interest. */
9328 #ifdef HAVE_cc0
9329 /* If comparison with cc0, import actual comparison from compare
9330 insn. */
9332 {
9343 }
9344 #endif
9346 /* If this is a COMPARE, pick up the two things being compared. */
9348 {
9352 }
9356 /* Go back to the previous insn. Stop if it is not an INSN. We also
9357 stop if it isn't a single set or if it has a REG_INC note because
9358 we don't want to bother dealing with it. */
9372 /* If this is setting OP0, get what it sets it to if it looks
9373 relevant. */
9375 {
9377 #ifdef FLOAT_STORE_FLAG_VALUE
9378 REAL_VALUE_TYPE fsfv;
9379 #endif
9381 /* ??? We may not combine comparisons done in a CCmode with
9382 comparisons not done in a CCmode. This is to aid targets
9383 like Alpha that have an IEEE compliant EQ instruction, and
9384 a non-IEEE compliant BEQ instruction. The use of CCmode is
9385 actually artificial, simply to prevent the combination, but
9386 should not affect other platforms.
9388 However, we must allow VOIDmode comparisons to match either
9389 CCmode or non-CCmode comparison, because some ports have
9390 modeless comparisons inside branch patterns.
9392 ??? This mode check should perhaps look more like the mode check
9393 in simplify_comparison in combine. */
9401 && (STORE_FLAG_VALUE
9404 #ifdef FLOAT_STORE_FLAG_VALUE
9409 #endif
9410 ))
9421 && (STORE_FLAG_VALUE
9424 #ifdef FLOAT_STORE_FLAG_VALUE
9429 #endif
9430 ))
9436 {
9439 }
9440 else
9442 }
9445 /* If this sets OP0, but not directly, we have to give up. */
9449 {
9453 {
9458 }
9463 }
9464 }
9466 /* If constant is first, put it last. */
9470 /* If OP0 is the result of a comparison, we weren't able to find what
9471 was really being compared, so fail. */
9475 /* Canonicalize any ordered comparison with integers involving equality
9476 if we can do computations in the relevant mode and we do not
9477 overflow. */
9482 {
9485 unsigned HOST_WIDE_INT max_val
9489 {
9495 /* When cross-compiling, const_val might be sign-extended from
9496 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9516 }
9517 }
9519 /* Never return CC0; return zero instead. */
9524 }
9526 /* Given a jump insn JUMP, return the condition that will cause it to branch
9527 to its JUMP_LABEL. If the condition cannot be understood, or is an
9528 inequality floating-point comparison which needs to be reversed, 0 will
9529 be returned.
9531 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9532 insn used in locating the condition was found. If a replacement test
9533 of the condition is desired, it should be placed in front of that
9534 insn and we will be sure that the inputs are still valid. */
9536 rtx
9538 rtx jump;
9540 {
9541 rtx cond;
9543 rtx set;
9545 /* If this is not a standard conditional jump, we can't parse it. */
9553 /* If this branches to JUMP_LABEL when the condition is false, reverse
9554 the condition. */
9555 reverse
9560 }
9562 /* Similar to above routine, except that we also put an invariant last
9563 unless both operands are invariants. */
9565 rtx
9568 rtx x;
9569 {
9579 }
9581 /* Scan the function and determine whether it has indirect (computed) jumps.
9583 This is taken mostly from flow.c; similar code exists elsewhere
9584 in the compiler. It may be useful to put this into rtlanal.c. */
9585 static int
9587 rtx start;
9588 {
9589 rtx insn;
9596 }
9598 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9599 documentation for LOOP_MEMS for the definition of `appropriate'.
9600 This function is called from prescan_loop via for_each_rtx. */
9602 static int
9606 {
9615 {
9620 /* We're not interested in MEMs that are only clobbered. */
9624 /* We're not interested in the MEM associated with a
9625 CONST_DOUBLE, so there's no need to traverse into this. */
9629 /* We're not interested in any MEMs that only appear in notes. */
9633 /* This is not a MEM. */
9635 }
9637 /* See if we've already seen this MEM. */
9640 {
9642 /* The modes of the two memory accesses are different. If
9643 this happens, something tricky is going on, and we just
9644 don't optimize accesses to this MEM. */
9648 }
9650 /* Resize the array, if necessary. */
9652 {
9655 else
9661 }
9663 /* Actually insert the MEM. */
9665 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9666 because we can't put it in a register. We still store it in the
9667 table, though, so that if we see the same address later, but in a
9668 non-BLK mode, we'll not think we can optimize it at that point. */
9674 }
9677 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9679 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9680 register that is modified by an insn between FROM and TO. If the
9681 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9682 more, stop incrementing it, to avoid overflow.
9684 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9685 register I is used, if it is only used once. Otherwise, it is set
9686 to 0 (for no uses) or const0_rtx for more than one use. This
9687 parameter may be zero, in which case this processing is not done.
9689 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9690 optimize register I. */
9692 static void
9696 {
9699 /* last_set[n] is nonzero iff reg n has been set in the current
9700 basic block. In that case, it is the insn that last set reg n. */
9702 rtx insn;
9708 /* Grow the regs array if not allocated or too small. */
9710 {
9716 /* Zero the new elements. */
9719 }
9721 /* Clear previously scanned fields but do not clear n_times_set. */
9723 {
9727 }
9731 /* Scan the loop, recording register usage. */
9734 {
9736 {
9737 /* Record registers that have exactly one use. */
9740 /* Include uses in REG_EQUAL notes. */
9748 {
9752 last_set);
9753 }
9754 }
9759 /* Invalidate all registers used for function argument passing.
9760 We check rtx_varies_p for the same reason as below, to allow
9761 optimizing PIC calculations. */
9763 {
9764 rtx link;
9766 link;
9768 {
9775 }
9776 }
9777 }
9779 /* Invalidate all hard registers clobbered by calls. With one exception:
9780 a call-clobbered PIC register is still function-invariant for our
9781 purposes, since we can hoist any PIC calculations out of the loop.
9782 Thus the call to rtx_varies_p. */
9787 {
9790 }
9792 #ifdef AVOID_CCMODE_COPIES
9793 /* Don't try to move insns which set CC registers if we should not
9794 create CCmode register copies. */
9798 #endif
9800 /* Set regs->array[I].n_times_set for the new registers. */
9805 }
9807 /* Returns the number of real INSNs in the LOOP. */
9809 static int
9812 {
9814 rtx insn;
9822 }
9824 /* Move MEMs into registers for the duration of the loop. */
9826 static void
9829 {
9836 rtx end_label;
9837 /* Nonzero if the next instruction may never be executed. */
9844 /* We cannot use next_label here because it skips over normal insns. */
9849 /* Check to see if it's possible that some instructions in the loop are
9850 never executed. Also check if there is a goto out of the loop other
9851 than right after the end of the loop. */
9855 {
9859 /* If we enter the loop in the middle, and scan
9860 around to the beginning, don't set maybe_never
9861 for that. This must be an unconditional jump,
9862 otherwise the code at the top of the loop might
9863 never be executed. Unconditional jumps are
9864 followed a by barrier then loop end. */
9869 {
9870 /* If this is a jump outside of the loop but not right
9871 after the end of the loop, we would have to emit new fixup
9872 sequences for each such label. */
9874 JUMP_INSN is executed, we must be conservative. */
9883 /* Something complicated. */
9885 else
9886 /* If there are any more instructions in the loop, they
9887 might not be reached. */
9889 }
9892 }
9894 /* Find start of the extended basic block that enters the loop. */
9898 ;
9903 /* Build table of mems that get set to constant values before the
9904 loop. */
9908 /* Actually move the MEMs. */
9910 {
9911 regset_head load_copies;
9912 regset_head store_copies;
9914 rtx reg;
9916 rtx mem_list_entry;
9920 /* There's no telling whether or not MEM is modified. */
9923 /* Go through the MEMs written to in the loop to see if this
9924 one is aliased by one of them. */
9927 {
9932 {
9933 /* MEM is indeed aliased by this store. */
9936 }
9938 }
9944 /* If this MEM is written to, we must be sure that there
9945 are no reads from another MEM that aliases this one. */
9947 {
9951 {
9955 VOIDmode,
9957 rtx_varies_p))
9958 {
9959 /* It's not safe to hoist loop_info->mems[i] out of
9960 the loop because writes to it might not be
9961 seen by reads from loop_info->mems[j]. */
9964 }
9965 }
9966 }
9969 /* We can't access the MEM outside the loop; it might
9970 cause a trap that wouldn't have happened otherwise. */
9974 /* We thought we were going to lift this MEM out of the
9975 loop, but later discovered that we could not. */
9981 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9982 order to keep scan_loop from moving stores to this MEM
9983 out of the loop just because this REG is neither a
9984 user-variable nor used in the loop test. */
9989 /* Now, replace all references to the MEM with the
9990 corresponding pseudos. */
9995 {
9997 {
9998 rtx set;
10002 /* See if this copies the mem into a register that isn't
10003 modified afterwards. We'll try to do copy propagation
10004 a little further on. */
10006 /* @@@ This test is _way_ too conservative. */
10007 && ! maybe_never
10015 /* See if this copies the mem from a register that isn't
10016 modified afterwards. We'll try to remove the
10017 redundant copy later on by doing a little register
10018 renaming and copy propagation. This will help
10019 to untangle things for the BIV detection code. */
10021 && ! maybe_never
10029 /* If this is a call which uses / clobbers this memory
10030 location, we must not change the interface here. */
10034 {
10038 }
10039 else
10040 /* Replace the memory reference with the shadow register. */
10043 }
10048 }
10053 /* We couldn't replace all occurrences of the MEM. */
10055 else
10056 {
10057 /* Load the memory immediately before LOOP->START, which is
10058 the NOTE_LOOP_BEG. */
10060 rtx set;
10066 {
10070 {
10074 /* Extending hard register lifetimes causes crash
10075 on SRC targets. Doing so on non-SRC is
10076 probably also not good idea, since we most
10077 probably have pseudoregister equivalence as
10078 well. */
10081 }
10082 /* Use the constant equivalence if that is cheap enough. */
10088 {
10091 }
10093 /* If best_equiv is nonzero, we know that MEM is set to a
10094 constant or register before the loop. We will use this
10095 knowledge to initialize the shadow register with that
10096 constant or reg rather than by loading from MEM. */
10099 }
10104 {
10107 {
10110 }
10111 }
10117 {
10119 {
10122 }
10124 /* Store the memory immediately after END, which is
10125 the NOTE_LOOP_END. */
10128 }
10131 {
10136 }
10138 /* Attempt a bit of copy propagation. This helps untangle the
10139 data flow, and enables {basic,general}_induction_var to find
10140 more bivs/givs. */
10141 EXECUTE_IF_SET_IN_REG_SET
10143 {
10145 });
10148 EXECUTE_IF_SET_IN_REG_SET
10150 {
10152 });
10154 }
10155 }
10158 {
10159 /* Now, we need to replace all references to the previous exit
10160 label with the new one. */
10161 replace_label_data rr;
10167 {
10169 }
10170 }
10173 }
10175 /* For communication between note_reg_stored and its caller. */
10176 struct note_reg_stored_arg
10177 {
10179 rtx reg;
10180 };
10182 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10183 is equal to ARG. */
10184 static void
10188 {
10192 }
10194 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10195 There must be exactly one insn that sets this pseudo; it will be
10196 deleted if all replacements succeed and we can prove that the register
10197 is not used after the loop. */
10199 static void
10202 rtx replacement;
10204 {
10205 /* This is the reg that we are copying from. */
10208 rtx insn;
10209 /* These help keep track of whether we replaced all uses of the reg. */
10216 {
10217 rtx set;
10219 /* Only substitute within one extended basic block from the initializing
10220 insn. */
10227 /* Is this the initializing insn? */
10232 {
10239 }
10241 /* Only substitute after seeing the initializing insn. */
10243 {
10250 /* Stop replacing when REPLACEMENT is modified. */
10255 {
10258 /* It is possible that we've turned previously valid REG_EQUAL to
10259 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10260 REPLACEMENT is modified, we get different meaning. */
10264 }
10265 }
10266 }
10270 {
10274 {
10275 rtx first;
10276 rtx retval_note;
10278 /* Assume we're just deleting INIT_INSN. */
10280 /* Look for REG_RETVAL note. If we're deleting the end of
10281 the libcall sequence, the whole sequence can go. */
10283 /* If we found a REG_RETVAL note, find the first instruction
10284 in the sequence. */
10288 /* Delete the instructions. */
10290 }
10293 }
10294 }
10296 /* Replace all the instructions from FIRST up to and including LAST
10297 with NOTE_INSN_DELETED notes. */
10299 static void
10301 rtx first;
10302 rtx last;
10303 {
10305 {
10311 /* If this was the LAST instructions we're supposed to delete,
10312 we're done. */
10317 }
10318 }
10320 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10321 loop LOOP if the order of the sets of these registers can be
10322 swapped. There must be exactly one insn within the loop that sets
10323 this pseudo followed immediately by a move insn that sets
10324 REPLACEMENT with REGNO. */
10325 static void
10328 rtx replacement;
10330 {
10331 rtx insn;
10340 {
10341 /* Search for the insn that copies REGNO to NEW_REGNO? */
10349 }
10352 {
10353 rtx prev_insn;
10354 rtx prev_set;
10356 /* Some DEF-USE info would come in handy here to make this
10357 function more general. For now, just check the previous insn
10358 which is the most likely candidate for setting REGNO. */
10366 {
10367 /* We have:
10368 (set (reg regno) (expr))
10369 (set (reg new_regno) (reg regno))
10371 so try converting this to:
10372 (set (reg new_regno) (expr))
10373 (set (reg regno) (reg new_regno))
10375 The former construct is often generated when a global
10376 variable used for an induction variable is shadowed by a
10377 register (NEW_REGNO). The latter construct improves the
10378 chances of GIV replacement and BIV elimination. */
10388 {
10395 /* Update first use of REGNO. */
10399 /* Now perform copy propagation to hopefully
10400 remove all uses of REGNO within the loop. */
10402 }
10403 }
10404 }
10405 }
10407 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10409 static int
10413 {
10415 {
10419 }
10421 }
10423 /* Returns the first MEM found in NOTE by depth-first search. */
10425 static rtx
10427 rtx note;
10428 {
10432 }
10434 /* Replace MEM with its associated pseudo register. This function is
10435 called from load_mems via for_each_rtx. DATA is actually a pointer
10436 to a structure describing the instruction currently being scanned
10437 and the MEM we are currently replacing. */
10439 static int
10443 {
10451 {
10456 /* We're not interested in the MEM associated with a
10457 CONST_DOUBLE, so there's no need to traverse into one. */
10461 /* This is not a MEM. */
10463 }
10466 /* This is not the MEM we are currently replacing. */
10469 /* Actually replace the MEM. */
10473 }
10475 static void
10477 rtx insn;
10478 rtx mem;
10479 rtx reg;
10481 {
10482 loop_replace_args args;
10490 /* If we hoist a mem write out of the loop, then REG_EQUAL
10491 notes referring to the mem are no longer valid. */
10493 {
10498 {
10502 {
10503 /* Remove the note. */
10506 }
10507 }
10508 }
10509 }
10511 /* Replace one register with another. Called through for_each_rtx; PX points
10512 to the rtx being scanned. DATA is actually a pointer to
10513 a structure of arguments. */
10515 static int
10519 {
10530 }
10532 static void
10534 rtx insn;
10535 rtx reg;
10536 rtx replacement;
10537 {
10538 loop_replace_args args;
10545 }
10546 \f
10547 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10548 (ignored in the interim). */
10550 static rtx
10553 basic_block where_bb ATTRIBUTE_UNUSED;
10554 rtx where_insn;
10555 rtx pattern;
10556 {
10558 }
10561 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10562 in basic block WHERE_BB (ignored in the interim) within the loop
10563 otherwise hoist PATTERN into the loop pre-header. */
10565 rtx
10568 basic_block where_bb ATTRIBUTE_UNUSED;
10569 rtx where_insn;
10570 rtx pattern;
10571 {
10575 }
10578 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10579 WHERE_BB (ignored in the interim) within the loop. */
10581 static rtx
10584 basic_block where_bb ATTRIBUTE_UNUSED;
10585 rtx where_insn;
10586 rtx pattern;
10587 {
10589 }
10592 /* Hoist insn for PATTERN into the loop pre-header. */
10594 rtx
10597 rtx pattern;
10598 {
10600 }
10603 /* Hoist call insn for PATTERN into the loop pre-header. */
10605 static rtx
10608 rtx pattern;
10609 {
10611 }
10614 /* Sink insn for PATTERN after the loop end. */
10616 rtx
10619 rtx pattern;
10620 {
10622 }
10624 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10625 and constant. Emit sequence of instructions to load it into REG. */
10626 static rtx
10629 {
10630 rtx seq;
10638 }
10640 /* If the loop has multiple exits, emit insn for PATTERN before the
10641 loop to ensure that it will always be executed no matter how the
10642 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10643 since this is slightly more efficient. */
10645 static rtx
10648 rtx pattern;
10649 {
10652 else
10654 }
10655 \f
10656 static void
10661 {
10669 iv_num++;
10674 {
10677 }
10678 }
10681 static void
10686 {
10688 rtx incr;
10699 {
10702 }
10704 {
10707 }
10711 {
10715 }
10718 {
10722 }
10724 /* List the increments. */
10726 {
10730 }
10732 /* List the givs. */
10734 {
10739 else
10742 }
10743 }
10746 static void
10751 {
10762 {
10766 }
10769 }
10772 static void
10777 {
10784 else
10800 {
10802 {
10814 }
10815 }
10826 {
10830 }
10833 }
10836 void
10839 {
10841 }
10844 void
10847 {
10849 }
10852 void
10855 {
10857 }
10860 void
10863 {
10865 }
10868 #define LOOP_BLOCK_NUM_1(INSN) \
10869 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10871 /* The notes do not have an assigned block, so look at the next insn. */
10872 #define LOOP_BLOCK_NUM(INSN) \
10873 ((INSN) ? (GET_CODE (INSN) == NOTE \
10874 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10875 : LOOP_BLOCK_NUM_1 (INSN)) \
10876 : -1)
10878 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10880 static void
10885 {
10886 rtx label;
10891 /* Print diagnostics to compare our concept of a loop with
10892 what the loop notes say. */
10907 {
10927 {
10930 {
10933 }
10934 }
10937 /* This can happen when a marked loop appears as two nested loops,
10938 say from while (a || b) {}. The inner loop won't match
10939 the loop markers but the outer one will. */
10942 }
10943 }
10945 /* Call this function from the debugger to dump LOOP. */
10947 void
10950 {
10952 }
10954 /* Call this function from the debugger to dump LOOPS. */
10956 void
10959 {
10961 }