1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
30 #include "double-int.h"
37 #include "fold-const.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
44 #include "hard-reg-set.h"
45 #include "insn-config.h"
46 #include "insn-codes.h"
47 #include "conditions.h"
49 #include "insn-attr.h"
54 #include "statistics.h"
56 #include "fixed-value.h"
65 #include "diagnostic-core.h"
70 #include "target-def.h"
71 #include "common/common-target.h"
72 #include "hash-table.h"
74 #include "dominance.h"
80 #include "cfgcleanup.h"
81 #include "basic-block.h"
82 #include "tree-ssa-alias.h"
83 #include "internal-fn.h"
84 #include "gimple-fold.h"
86 #include "gimple-expr.h"
90 #include "langhooks.h"
95 #include "tree-pass.h"
100 /* Processor costs */
102 struct processor_costs
{
106 /* Integer signed load */
109 /* Integer zeroed load */
113 const int float_load
;
115 /* fmov, fneg, fabs */
116 const int float_move
;
119 const int float_plusminus
;
125 const int float_cmove
;
131 const int float_div_sf
;
134 const int float_div_df
;
137 const int float_sqrt_sf
;
140 const int float_sqrt_df
;
148 /* integer multiply cost for each bit set past the most
149 significant 3, so the formula for multiply cost becomes:
152 highest_bit = highest_clear_bit(rs1);
154 highest_bit = highest_set_bit(rs1);
157 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
159 A value of zero indicates that the multiply costs is fixed,
161 const int int_mul_bit_factor
;
172 /* penalty for shifts, due to scheduling rules etc. */
173 const int shift_penalty
;
177 struct processor_costs cypress_costs
= {
178 COSTS_N_INSNS (2), /* int load */
179 COSTS_N_INSNS (2), /* int signed load */
180 COSTS_N_INSNS (2), /* int zeroed load */
181 COSTS_N_INSNS (2), /* float load */
182 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
183 COSTS_N_INSNS (5), /* fadd, fsub */
184 COSTS_N_INSNS (1), /* fcmp */
185 COSTS_N_INSNS (1), /* fmov, fmovr */
186 COSTS_N_INSNS (7), /* fmul */
187 COSTS_N_INSNS (37), /* fdivs */
188 COSTS_N_INSNS (37), /* fdivd */
189 COSTS_N_INSNS (63), /* fsqrts */
190 COSTS_N_INSNS (63), /* fsqrtd */
191 COSTS_N_INSNS (1), /* imul */
192 COSTS_N_INSNS (1), /* imulX */
193 0, /* imul bit factor */
194 COSTS_N_INSNS (1), /* idiv */
195 COSTS_N_INSNS (1), /* idivX */
196 COSTS_N_INSNS (1), /* movcc/movr */
197 0, /* shift penalty */
201 struct processor_costs supersparc_costs
= {
202 COSTS_N_INSNS (1), /* int load */
203 COSTS_N_INSNS (1), /* int signed load */
204 COSTS_N_INSNS (1), /* int zeroed load */
205 COSTS_N_INSNS (0), /* float load */
206 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
207 COSTS_N_INSNS (3), /* fadd, fsub */
208 COSTS_N_INSNS (3), /* fcmp */
209 COSTS_N_INSNS (1), /* fmov, fmovr */
210 COSTS_N_INSNS (3), /* fmul */
211 COSTS_N_INSNS (6), /* fdivs */
212 COSTS_N_INSNS (9), /* fdivd */
213 COSTS_N_INSNS (12), /* fsqrts */
214 COSTS_N_INSNS (12), /* fsqrtd */
215 COSTS_N_INSNS (4), /* imul */
216 COSTS_N_INSNS (4), /* imulX */
217 0, /* imul bit factor */
218 COSTS_N_INSNS (4), /* idiv */
219 COSTS_N_INSNS (4), /* idivX */
220 COSTS_N_INSNS (1), /* movcc/movr */
221 1, /* shift penalty */
225 struct processor_costs hypersparc_costs
= {
226 COSTS_N_INSNS (1), /* int load */
227 COSTS_N_INSNS (1), /* int signed load */
228 COSTS_N_INSNS (1), /* int zeroed load */
229 COSTS_N_INSNS (1), /* float load */
230 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
231 COSTS_N_INSNS (1), /* fadd, fsub */
232 COSTS_N_INSNS (1), /* fcmp */
233 COSTS_N_INSNS (1), /* fmov, fmovr */
234 COSTS_N_INSNS (1), /* fmul */
235 COSTS_N_INSNS (8), /* fdivs */
236 COSTS_N_INSNS (12), /* fdivd */
237 COSTS_N_INSNS (17), /* fsqrts */
238 COSTS_N_INSNS (17), /* fsqrtd */
239 COSTS_N_INSNS (17), /* imul */
240 COSTS_N_INSNS (17), /* imulX */
241 0, /* imul bit factor */
242 COSTS_N_INSNS (17), /* idiv */
243 COSTS_N_INSNS (17), /* idivX */
244 COSTS_N_INSNS (1), /* movcc/movr */
245 0, /* shift penalty */
249 struct processor_costs leon_costs
= {
250 COSTS_N_INSNS (1), /* int load */
251 COSTS_N_INSNS (1), /* int signed load */
252 COSTS_N_INSNS (1), /* int zeroed load */
253 COSTS_N_INSNS (1), /* float load */
254 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
255 COSTS_N_INSNS (1), /* fadd, fsub */
256 COSTS_N_INSNS (1), /* fcmp */
257 COSTS_N_INSNS (1), /* fmov, fmovr */
258 COSTS_N_INSNS (1), /* fmul */
259 COSTS_N_INSNS (15), /* fdivs */
260 COSTS_N_INSNS (15), /* fdivd */
261 COSTS_N_INSNS (23), /* fsqrts */
262 COSTS_N_INSNS (23), /* fsqrtd */
263 COSTS_N_INSNS (5), /* imul */
264 COSTS_N_INSNS (5), /* imulX */
265 0, /* imul bit factor */
266 COSTS_N_INSNS (5), /* idiv */
267 COSTS_N_INSNS (5), /* idivX */
268 COSTS_N_INSNS (1), /* movcc/movr */
269 0, /* shift penalty */
273 struct processor_costs leon3_costs
= {
274 COSTS_N_INSNS (1), /* int load */
275 COSTS_N_INSNS (1), /* int signed load */
276 COSTS_N_INSNS (1), /* int zeroed load */
277 COSTS_N_INSNS (1), /* float load */
278 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
279 COSTS_N_INSNS (1), /* fadd, fsub */
280 COSTS_N_INSNS (1), /* fcmp */
281 COSTS_N_INSNS (1), /* fmov, fmovr */
282 COSTS_N_INSNS (1), /* fmul */
283 COSTS_N_INSNS (14), /* fdivs */
284 COSTS_N_INSNS (15), /* fdivd */
285 COSTS_N_INSNS (22), /* fsqrts */
286 COSTS_N_INSNS (23), /* fsqrtd */
287 COSTS_N_INSNS (5), /* imul */
288 COSTS_N_INSNS (5), /* imulX */
289 0, /* imul bit factor */
290 COSTS_N_INSNS (35), /* idiv */
291 COSTS_N_INSNS (35), /* idivX */
292 COSTS_N_INSNS (1), /* movcc/movr */
293 0, /* shift penalty */
297 struct processor_costs sparclet_costs
= {
298 COSTS_N_INSNS (3), /* int load */
299 COSTS_N_INSNS (3), /* int signed load */
300 COSTS_N_INSNS (1), /* int zeroed load */
301 COSTS_N_INSNS (1), /* float load */
302 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
303 COSTS_N_INSNS (1), /* fadd, fsub */
304 COSTS_N_INSNS (1), /* fcmp */
305 COSTS_N_INSNS (1), /* fmov, fmovr */
306 COSTS_N_INSNS (1), /* fmul */
307 COSTS_N_INSNS (1), /* fdivs */
308 COSTS_N_INSNS (1), /* fdivd */
309 COSTS_N_INSNS (1), /* fsqrts */
310 COSTS_N_INSNS (1), /* fsqrtd */
311 COSTS_N_INSNS (5), /* imul */
312 COSTS_N_INSNS (5), /* imulX */
313 0, /* imul bit factor */
314 COSTS_N_INSNS (5), /* idiv */
315 COSTS_N_INSNS (5), /* idivX */
316 COSTS_N_INSNS (1), /* movcc/movr */
317 0, /* shift penalty */
321 struct processor_costs ultrasparc_costs
= {
322 COSTS_N_INSNS (2), /* int load */
323 COSTS_N_INSNS (3), /* int signed load */
324 COSTS_N_INSNS (2), /* int zeroed load */
325 COSTS_N_INSNS (2), /* float load */
326 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
327 COSTS_N_INSNS (4), /* fadd, fsub */
328 COSTS_N_INSNS (1), /* fcmp */
329 COSTS_N_INSNS (2), /* fmov, fmovr */
330 COSTS_N_INSNS (4), /* fmul */
331 COSTS_N_INSNS (13), /* fdivs */
332 COSTS_N_INSNS (23), /* fdivd */
333 COSTS_N_INSNS (13), /* fsqrts */
334 COSTS_N_INSNS (23), /* fsqrtd */
335 COSTS_N_INSNS (4), /* imul */
336 COSTS_N_INSNS (4), /* imulX */
337 2, /* imul bit factor */
338 COSTS_N_INSNS (37), /* idiv */
339 COSTS_N_INSNS (68), /* idivX */
340 COSTS_N_INSNS (2), /* movcc/movr */
341 2, /* shift penalty */
345 struct processor_costs ultrasparc3_costs
= {
346 COSTS_N_INSNS (2), /* int load */
347 COSTS_N_INSNS (3), /* int signed load */
348 COSTS_N_INSNS (3), /* int zeroed load */
349 COSTS_N_INSNS (2), /* float load */
350 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
351 COSTS_N_INSNS (4), /* fadd, fsub */
352 COSTS_N_INSNS (5), /* fcmp */
353 COSTS_N_INSNS (3), /* fmov, fmovr */
354 COSTS_N_INSNS (4), /* fmul */
355 COSTS_N_INSNS (17), /* fdivs */
356 COSTS_N_INSNS (20), /* fdivd */
357 COSTS_N_INSNS (20), /* fsqrts */
358 COSTS_N_INSNS (29), /* fsqrtd */
359 COSTS_N_INSNS (6), /* imul */
360 COSTS_N_INSNS (6), /* imulX */
361 0, /* imul bit factor */
362 COSTS_N_INSNS (40), /* idiv */
363 COSTS_N_INSNS (71), /* idivX */
364 COSTS_N_INSNS (2), /* movcc/movr */
365 0, /* shift penalty */
369 struct processor_costs niagara_costs
= {
370 COSTS_N_INSNS (3), /* int load */
371 COSTS_N_INSNS (3), /* int signed load */
372 COSTS_N_INSNS (3), /* int zeroed load */
373 COSTS_N_INSNS (9), /* float load */
374 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
375 COSTS_N_INSNS (8), /* fadd, fsub */
376 COSTS_N_INSNS (26), /* fcmp */
377 COSTS_N_INSNS (8), /* fmov, fmovr */
378 COSTS_N_INSNS (29), /* fmul */
379 COSTS_N_INSNS (54), /* fdivs */
380 COSTS_N_INSNS (83), /* fdivd */
381 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
382 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
383 COSTS_N_INSNS (11), /* imul */
384 COSTS_N_INSNS (11), /* imulX */
385 0, /* imul bit factor */
386 COSTS_N_INSNS (72), /* idiv */
387 COSTS_N_INSNS (72), /* idivX */
388 COSTS_N_INSNS (1), /* movcc/movr */
389 0, /* shift penalty */
393 struct processor_costs niagara2_costs
= {
394 COSTS_N_INSNS (3), /* int load */
395 COSTS_N_INSNS (3), /* int signed load */
396 COSTS_N_INSNS (3), /* int zeroed load */
397 COSTS_N_INSNS (3), /* float load */
398 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
399 COSTS_N_INSNS (6), /* fadd, fsub */
400 COSTS_N_INSNS (6), /* fcmp */
401 COSTS_N_INSNS (6), /* fmov, fmovr */
402 COSTS_N_INSNS (6), /* fmul */
403 COSTS_N_INSNS (19), /* fdivs */
404 COSTS_N_INSNS (33), /* fdivd */
405 COSTS_N_INSNS (19), /* fsqrts */
406 COSTS_N_INSNS (33), /* fsqrtd */
407 COSTS_N_INSNS (5), /* imul */
408 COSTS_N_INSNS (5), /* imulX */
409 0, /* imul bit factor */
410 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
411 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
412 COSTS_N_INSNS (1), /* movcc/movr */
413 0, /* shift penalty */
417 struct processor_costs niagara3_costs
= {
418 COSTS_N_INSNS (3), /* int load */
419 COSTS_N_INSNS (3), /* int signed load */
420 COSTS_N_INSNS (3), /* int zeroed load */
421 COSTS_N_INSNS (3), /* float load */
422 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
423 COSTS_N_INSNS (9), /* fadd, fsub */
424 COSTS_N_INSNS (9), /* fcmp */
425 COSTS_N_INSNS (9), /* fmov, fmovr */
426 COSTS_N_INSNS (9), /* fmul */
427 COSTS_N_INSNS (23), /* fdivs */
428 COSTS_N_INSNS (37), /* fdivd */
429 COSTS_N_INSNS (23), /* fsqrts */
430 COSTS_N_INSNS (37), /* fsqrtd */
431 COSTS_N_INSNS (9), /* imul */
432 COSTS_N_INSNS (9), /* imulX */
433 0, /* imul bit factor */
434 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
435 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
436 COSTS_N_INSNS (1), /* movcc/movr */
437 0, /* shift penalty */
441 struct processor_costs niagara4_costs
= {
442 COSTS_N_INSNS (5), /* int load */
443 COSTS_N_INSNS (5), /* int signed load */
444 COSTS_N_INSNS (5), /* int zeroed load */
445 COSTS_N_INSNS (5), /* float load */
446 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
447 COSTS_N_INSNS (11), /* fadd, fsub */
448 COSTS_N_INSNS (11), /* fcmp */
449 COSTS_N_INSNS (11), /* fmov, fmovr */
450 COSTS_N_INSNS (11), /* fmul */
451 COSTS_N_INSNS (24), /* fdivs */
452 COSTS_N_INSNS (37), /* fdivd */
453 COSTS_N_INSNS (24), /* fsqrts */
454 COSTS_N_INSNS (37), /* fsqrtd */
455 COSTS_N_INSNS (12), /* imul */
456 COSTS_N_INSNS (12), /* imulX */
457 0, /* imul bit factor */
458 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
459 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
460 COSTS_N_INSNS (1), /* movcc/movr */
461 0, /* shift penalty */
464 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
466 #ifdef HAVE_AS_RELAX_OPTION
467 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
468 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
469 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
470 somebody does not branch between the sethi and jmp. */
471 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
473 #define LEAF_SIBCALL_SLOT_RESERVED_P \
474 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
477 /* Vector to say how input registers are mapped to output registers.
478 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
479 eliminate it. You must use -fomit-frame-pointer to get that. */
480 char leaf_reg_remap
[] =
481 { 0, 1, 2, 3, 4, 5, 6, 7,
482 -1, -1, -1, -1, -1, -1, 14, -1,
483 -1, -1, -1, -1, -1, -1, -1, -1,
484 8, 9, 10, 11, 12, 13, -1, 15,
486 32, 33, 34, 35, 36, 37, 38, 39,
487 40, 41, 42, 43, 44, 45, 46, 47,
488 48, 49, 50, 51, 52, 53, 54, 55,
489 56, 57, 58, 59, 60, 61, 62, 63,
490 64, 65, 66, 67, 68, 69, 70, 71,
491 72, 73, 74, 75, 76, 77, 78, 79,
492 80, 81, 82, 83, 84, 85, 86, 87,
493 88, 89, 90, 91, 92, 93, 94, 95,
494 96, 97, 98, 99, 100, 101, 102};
496 /* Vector, indexed by hard register number, which contains 1
497 for a register that is allowable in a candidate for leaf
498 function treatment. */
499 char sparc_leaf_regs
[] =
500 { 1, 1, 1, 1, 1, 1, 1, 1,
501 0, 0, 0, 0, 0, 0, 1, 0,
502 0, 0, 0, 0, 0, 0, 0, 0,
503 1, 1, 1, 1, 1, 1, 0, 1,
504 1, 1, 1, 1, 1, 1, 1, 1,
505 1, 1, 1, 1, 1, 1, 1, 1,
506 1, 1, 1, 1, 1, 1, 1, 1,
507 1, 1, 1, 1, 1, 1, 1, 1,
508 1, 1, 1, 1, 1, 1, 1, 1,
509 1, 1, 1, 1, 1, 1, 1, 1,
510 1, 1, 1, 1, 1, 1, 1, 1,
511 1, 1, 1, 1, 1, 1, 1, 1,
512 1, 1, 1, 1, 1, 1, 1};
514 struct GTY(()) machine_function
516 /* Size of the frame of the function. */
517 HOST_WIDE_INT frame_size
;
519 /* Size of the frame of the function minus the register window save area
520 and the outgoing argument area. */
521 HOST_WIDE_INT apparent_frame_size
;
523 /* Register we pretend the frame pointer is allocated to. Normally, this
524 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
525 record "offset" separately as it may be too big for (reg + disp). */
527 HOST_WIDE_INT frame_base_offset
;
529 /* Number of global or FP registers to be saved (as 4-byte quantities). */
530 int n_global_fp_regs
;
532 /* True if the current function is leaf and uses only leaf regs,
533 so that the SPARC leaf function optimization can be applied.
534 Private version of crtl->uses_only_leaf_regs, see
535 sparc_expand_prologue for the rationale. */
538 /* True if the prologue saves local or in registers. */
539 bool save_local_in_regs_p
;
541 /* True if the data calculated by sparc_expand_prologue are valid. */
542 bool prologue_data_valid_p
;
545 #define sparc_frame_size cfun->machine->frame_size
546 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
547 #define sparc_frame_base_reg cfun->machine->frame_base_reg
548 #define sparc_frame_base_offset cfun->machine->frame_base_offset
549 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
550 #define sparc_leaf_function_p cfun->machine->leaf_function_p
551 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
552 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
554 /* 1 if the next opcode is to be specially indented. */
555 int sparc_indent_opcode
= 0;
557 static void sparc_option_override (void);
558 static void sparc_init_modes (void);
559 static void scan_record_type (const_tree
, int *, int *, int *);
560 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
561 const_tree
, bool, bool, int *, int *);
563 static int supersparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
564 static int hypersparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
566 static void sparc_emit_set_const32 (rtx
, rtx
);
567 static void sparc_emit_set_const64 (rtx
, rtx
);
568 static void sparc_output_addr_vec (rtx
);
569 static void sparc_output_addr_diff_vec (rtx
);
570 static void sparc_output_deferred_case_vectors (void);
571 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
572 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
573 static rtx
sparc_builtin_saveregs (void);
574 static int epilogue_renumber (rtx
*, int);
575 static bool sparc_assemble_integer (rtx
, unsigned int, int);
576 static int set_extends (rtx_insn
*);
577 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
578 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
579 #ifdef TARGET_SOLARIS
580 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
581 tree
) ATTRIBUTE_UNUSED
;
583 static int sparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
584 static int sparc_issue_rate (void);
585 static void sparc_sched_init (FILE *, int, int);
586 static int sparc_use_sched_lookahead (void);
588 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
589 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
590 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
591 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
592 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
594 static bool sparc_function_ok_for_sibcall (tree
, tree
);
595 static void sparc_init_libfuncs (void);
596 static void sparc_init_builtins (void);
597 static void sparc_fpu_init_builtins (void);
598 static void sparc_vis_init_builtins (void);
599 static tree
sparc_builtin_decl (unsigned, bool);
600 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
601 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
602 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
603 HOST_WIDE_INT
, tree
);
604 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
605 HOST_WIDE_INT
, const_tree
);
606 static struct machine_function
* sparc_init_machine_status (void);
607 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
608 static rtx
sparc_tls_get_addr (void);
609 static rtx
sparc_tls_got (void);
610 static int sparc_register_move_cost (machine_mode
,
611 reg_class_t
, reg_class_t
);
612 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
613 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
614 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
615 static bool sparc_function_value_regno_p (const unsigned int);
616 static rtx
sparc_struct_value_rtx (tree
, int);
617 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
618 int *, const_tree
, int);
619 static bool sparc_return_in_memory (const_tree
, const_tree
);
620 static bool sparc_strict_argument_naming (cumulative_args_t
);
621 static void sparc_va_start (tree
, rtx
);
622 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
623 static bool sparc_vector_mode_supported_p (machine_mode
);
624 static bool sparc_tls_referenced_p (rtx
);
625 static rtx
sparc_legitimize_tls_address (rtx
);
626 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
627 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
628 static rtx
sparc_delegitimize_address (rtx
);
629 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
630 static bool sparc_pass_by_reference (cumulative_args_t
,
631 machine_mode
, const_tree
, bool);
632 static void sparc_function_arg_advance (cumulative_args_t
,
633 machine_mode
, const_tree
, bool);
634 static rtx
sparc_function_arg_1 (cumulative_args_t
,
635 machine_mode
, const_tree
, bool, bool);
636 static rtx
sparc_function_arg (cumulative_args_t
,
637 machine_mode
, const_tree
, bool);
638 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
639 machine_mode
, const_tree
, bool);
640 static unsigned int sparc_function_arg_boundary (machine_mode
,
642 static int sparc_arg_partial_bytes (cumulative_args_t
,
643 machine_mode
, tree
, bool);
644 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
645 static void sparc_file_end (void);
646 static bool sparc_frame_pointer_required (void);
647 static bool sparc_can_eliminate (const int, const int);
648 static rtx
sparc_builtin_setjmp_frame_value (void);
649 static void sparc_conditional_register_usage (void);
650 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
651 static const char *sparc_mangle_type (const_tree
);
653 static void sparc_trampoline_init (rtx
, tree
, rtx
);
654 static machine_mode
sparc_preferred_simd_mode (machine_mode
);
655 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
656 static bool sparc_print_operand_punct_valid_p (unsigned char);
657 static void sparc_print_operand (FILE *, rtx
, int);
658 static void sparc_print_operand_address (FILE *, rtx
);
659 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
661 secondary_reload_info
*);
662 static machine_mode
sparc_cstore_mode (enum insn_code icode
);
663 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
665 #ifdef SUBTARGET_ATTRIBUTE_TABLE
666 /* Table of valid machine attributes. */
667 static const struct attribute_spec sparc_attribute_table
[] =
669 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
671 SUBTARGET_ATTRIBUTE_TABLE
,
672 { NULL
, 0, 0, false, false, false, NULL
, false }
676 /* Option handling. */
679 enum cmodel sparc_cmodel
;
681 char sparc_hard_reg_printed
[8];
683 /* Initialize the GCC target structure. */
685 /* The default is to use .half rather than .short for aligned HI objects. */
686 #undef TARGET_ASM_ALIGNED_HI_OP
687 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
689 #undef TARGET_ASM_UNALIGNED_HI_OP
690 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
691 #undef TARGET_ASM_UNALIGNED_SI_OP
692 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
693 #undef TARGET_ASM_UNALIGNED_DI_OP
694 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
696 /* The target hook has to handle DI-mode values. */
697 #undef TARGET_ASM_INTEGER
698 #define TARGET_ASM_INTEGER sparc_assemble_integer
700 #undef TARGET_ASM_FUNCTION_PROLOGUE
701 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
702 #undef TARGET_ASM_FUNCTION_EPILOGUE
703 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
705 #undef TARGET_SCHED_ADJUST_COST
706 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
707 #undef TARGET_SCHED_ISSUE_RATE
708 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
709 #undef TARGET_SCHED_INIT
710 #define TARGET_SCHED_INIT sparc_sched_init
711 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
712 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
714 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
715 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
717 #undef TARGET_INIT_LIBFUNCS
718 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
720 #undef TARGET_LEGITIMIZE_ADDRESS
721 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
722 #undef TARGET_DELEGITIMIZE_ADDRESS
723 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
724 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
725 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
727 #undef TARGET_INIT_BUILTINS
728 #define TARGET_INIT_BUILTINS sparc_init_builtins
729 #undef TARGET_BUILTIN_DECL
730 #define TARGET_BUILTIN_DECL sparc_builtin_decl
731 #undef TARGET_EXPAND_BUILTIN
732 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
733 #undef TARGET_FOLD_BUILTIN
734 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
737 #undef TARGET_HAVE_TLS
738 #define TARGET_HAVE_TLS true
741 #undef TARGET_CANNOT_FORCE_CONST_MEM
742 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
744 #undef TARGET_ASM_OUTPUT_MI_THUNK
745 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
746 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
747 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
749 #undef TARGET_RTX_COSTS
750 #define TARGET_RTX_COSTS sparc_rtx_costs
751 #undef TARGET_ADDRESS_COST
752 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
753 #undef TARGET_REGISTER_MOVE_COST
754 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
756 #undef TARGET_PROMOTE_FUNCTION_MODE
757 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
759 #undef TARGET_FUNCTION_VALUE
760 #define TARGET_FUNCTION_VALUE sparc_function_value
761 #undef TARGET_LIBCALL_VALUE
762 #define TARGET_LIBCALL_VALUE sparc_libcall_value
763 #undef TARGET_FUNCTION_VALUE_REGNO_P
764 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
766 #undef TARGET_STRUCT_VALUE_RTX
767 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
768 #undef TARGET_RETURN_IN_MEMORY
769 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
770 #undef TARGET_MUST_PASS_IN_STACK
771 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
772 #undef TARGET_PASS_BY_REFERENCE
773 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
774 #undef TARGET_ARG_PARTIAL_BYTES
775 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
776 #undef TARGET_FUNCTION_ARG_ADVANCE
777 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
778 #undef TARGET_FUNCTION_ARG
779 #define TARGET_FUNCTION_ARG sparc_function_arg
780 #undef TARGET_FUNCTION_INCOMING_ARG
781 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
782 #undef TARGET_FUNCTION_ARG_BOUNDARY
783 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
785 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
786 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
787 #undef TARGET_STRICT_ARGUMENT_NAMING
788 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
790 #undef TARGET_EXPAND_BUILTIN_VA_START
791 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
792 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
793 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
795 #undef TARGET_VECTOR_MODE_SUPPORTED_P
796 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
798 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
799 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
801 #ifdef SUBTARGET_INSERT_ATTRIBUTES
802 #undef TARGET_INSERT_ATTRIBUTES
803 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
806 #ifdef SUBTARGET_ATTRIBUTE_TABLE
807 #undef TARGET_ATTRIBUTE_TABLE
808 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
811 #undef TARGET_RELAXED_ORDERING
812 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
814 #undef TARGET_OPTION_OVERRIDE
815 #define TARGET_OPTION_OVERRIDE sparc_option_override
817 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
818 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
819 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
822 #undef TARGET_ASM_FILE_END
823 #define TARGET_ASM_FILE_END sparc_file_end
825 #undef TARGET_FRAME_POINTER_REQUIRED
826 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
828 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
829 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
831 #undef TARGET_CAN_ELIMINATE
832 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
834 #undef TARGET_PREFERRED_RELOAD_CLASS
835 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
837 #undef TARGET_SECONDARY_RELOAD
838 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
840 #undef TARGET_CONDITIONAL_REGISTER_USAGE
841 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
843 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
844 #undef TARGET_MANGLE_TYPE
845 #define TARGET_MANGLE_TYPE sparc_mangle_type
848 #undef TARGET_LEGITIMATE_ADDRESS_P
849 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
851 #undef TARGET_LEGITIMATE_CONSTANT_P
852 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
854 #undef TARGET_TRAMPOLINE_INIT
855 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
857 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
858 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
859 #undef TARGET_PRINT_OPERAND
860 #define TARGET_PRINT_OPERAND sparc_print_operand
861 #undef TARGET_PRINT_OPERAND_ADDRESS
862 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
864 /* The value stored by LDSTUB. */
865 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
866 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
868 #undef TARGET_CSTORE_MODE
869 #define TARGET_CSTORE_MODE sparc_cstore_mode
871 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
872 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
874 struct gcc_target targetm
= TARGET_INITIALIZER
;
876 /* Return the memory reference contained in X if any, zero otherwise. */
881 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
890 /* We use a machine specific pass to enable workarounds for errata.
891 We need to have the (essentially) final form of the insn stream in order
892 to properly detect the various hazards. Therefore, this machine specific
893 pass runs as late as possible. The pass is inserted in the pass pipeline
894 at the end of sparc_option_override. */
897 sparc_do_work_around_errata (void)
899 rtx_insn
*insn
, *next
;
901 /* Force all instructions to be split into their final form. */
902 split_all_insns_noflow ();
904 /* Now look for specific patterns in the insn stream. */
905 for (insn
= get_insns (); insn
; insn
= next
)
907 bool insert_nop
= false;
910 /* Look into the instruction in a delay slot. */
911 if (NONJUMP_INSN_P (insn
))
912 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
913 insn
= seq
->insn (1);
915 /* Look for a single-word load into an odd-numbered FP register. */
917 && NONJUMP_INSN_P (insn
)
918 && (set
= single_set (insn
)) != NULL_RTX
919 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
920 && MEM_P (SET_SRC (set
))
921 && REG_P (SET_DEST (set
))
922 && REGNO (SET_DEST (set
)) > 31
923 && REGNO (SET_DEST (set
)) % 2 != 0)
925 /* The wrong dependency is on the enclosing double register. */
926 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
927 unsigned int src1
, src2
, dest
;
930 next
= next_active_insn (insn
);
933 /* If the insn is a branch, then it cannot be problematic. */
934 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
938 code
= INSN_CODE (next
);
942 case CODE_FOR_adddf3
:
943 case CODE_FOR_subdf3
:
944 case CODE_FOR_muldf3
:
945 case CODE_FOR_divdf3
:
946 dest
= REGNO (recog_data
.operand
[0]);
947 src1
= REGNO (recog_data
.operand
[1]);
948 src2
= REGNO (recog_data
.operand
[2]);
953 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
954 if ((src1
== x
|| src2
== x
)
955 && (dest
== src1
|| dest
== src2
))
962 FPOPd %fx, %fx, %fx */
965 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
970 case CODE_FOR_sqrtdf2
:
971 dest
= REGNO (recog_data
.operand
[0]);
972 src1
= REGNO (recog_data
.operand
[1]);
976 if (src1
== x
&& dest
== src1
)
985 /* Look for a single-word load into an integer register. */
986 else if (sparc_fix_ut699
987 && NONJUMP_INSN_P (insn
)
988 && (set
= single_set (insn
)) != NULL_RTX
989 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
990 && mem_ref (SET_SRC (set
)) != NULL_RTX
991 && REG_P (SET_DEST (set
))
992 && REGNO (SET_DEST (set
)) < 32)
994 /* There is no problem if the second memory access has a data
995 dependency on the first single-cycle load. */
996 rtx x
= SET_DEST (set
);
998 next
= next_active_insn (insn
);
1001 /* If the insn is a branch, then it cannot be problematic. */
1002 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1005 /* Look for a second memory access to/from an integer register. */
1006 if ((set
= single_set (next
)) != NULL_RTX
)
1008 rtx src
= SET_SRC (set
);
1009 rtx dest
= SET_DEST (set
);
1012 /* LDD is affected. */
1013 if ((mem
= mem_ref (src
)) != NULL_RTX
1015 && REGNO (dest
) < 32
1016 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1019 /* STD is *not* affected. */
1020 else if (MEM_P (dest
)
1021 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1022 && (src
== CONST0_RTX (GET_MODE (dest
))
1025 && REGNO (src
) != REGNO (x
)))
1026 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1031 /* Look for a single-word load/operation into an FP register. */
1032 else if (sparc_fix_ut699
1033 && NONJUMP_INSN_P (insn
)
1034 && (set
= single_set (insn
)) != NULL_RTX
1035 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1036 && REG_P (SET_DEST (set
))
1037 && REGNO (SET_DEST (set
)) > 31)
1039 /* Number of instructions in the problematic window. */
1040 const int n_insns
= 4;
1041 /* The problematic combination is with the sibling FP register. */
1042 const unsigned int x
= REGNO (SET_DEST (set
));
1043 const unsigned int y
= x
^ 1;
1047 next
= next_active_insn (insn
);
1050 /* If the insn is a branch, then it cannot be problematic. */
1051 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1054 /* Look for a second load/operation into the sibling FP register. */
1055 if (!((set
= single_set (next
)) != NULL_RTX
1056 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1057 && REG_P (SET_DEST (set
))
1058 && REGNO (SET_DEST (set
)) == y
))
1061 /* Look for a (possible) store from the FP register in the next N
1062 instructions, but bail out if it is again modified or if there
1063 is a store from the sibling FP register before this store. */
1064 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1068 after
= next_active_insn (after
);
1072 /* This is a branch with an empty delay slot. */
1073 if (!NONJUMP_INSN_P (after
))
1080 /* This is a branch with a filled delay slot. */
1081 else if (rtx_sequence
*seq
=
1082 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1087 after
= seq
->insn (1);
1089 /* This is a regular instruction. */
1093 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1095 const rtx src
= SET_SRC (set
);
1096 const rtx dest
= SET_DEST (set
);
1097 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1099 /* If the FP register is again modified before the store,
1100 then the store isn't affected. */
1102 && (REGNO (dest
) == x
1103 || (REGNO (dest
) == y
&& size
== 8)))
1106 if (MEM_P (dest
) && REG_P (src
))
1108 /* If there is a store from the sibling FP register
1109 before the store, then the store is not affected. */
1110 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1113 /* Otherwise, the store is affected. */
1114 if (REGNO (src
) == x
&& size
== 4)
1122 /* If we have a branch in the first M instructions, then we
1123 cannot see the (M+2)th instruction so we play safe. */
1124 if (branch_p
&& i
<= (n_insns
- 2))
1133 next
= NEXT_INSN (insn
);
1136 emit_insn_before (gen_nop (), next
);
1144 const pass_data pass_data_work_around_errata
=
1146 RTL_PASS
, /* type */
1147 "errata", /* name */
1148 OPTGROUP_NONE
, /* optinfo_flags */
1149 TV_MACH_DEP
, /* tv_id */
1150 0, /* properties_required */
1151 0, /* properties_provided */
1152 0, /* properties_destroyed */
1153 0, /* todo_flags_start */
1154 0, /* todo_flags_finish */
1157 class pass_work_around_errata
: public rtl_opt_pass
1160 pass_work_around_errata(gcc::context
*ctxt
)
1161 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1164 /* opt_pass methods: */
1165 virtual bool gate (function
*)
1167 /* The only errata we handle are those of the AT697F and UT699. */
1168 return sparc_fix_at697f
!= 0 || sparc_fix_ut699
!= 0;
1171 virtual unsigned int execute (function
*)
1173 return sparc_do_work_around_errata ();
1176 }; // class pass_work_around_errata
1181 make_pass_work_around_errata (gcc::context
*ctxt
)
1183 return new pass_work_around_errata (ctxt
);
1186 /* Helpers for TARGET_DEBUG_OPTIONS. */
1188 dump_target_flag_bits (const int flags
)
1190 if (flags
& MASK_64BIT
)
1191 fprintf (stderr
, "64BIT ");
1192 if (flags
& MASK_APP_REGS
)
1193 fprintf (stderr
, "APP_REGS ");
1194 if (flags
& MASK_FASTER_STRUCTS
)
1195 fprintf (stderr
, "FASTER_STRUCTS ");
1196 if (flags
& MASK_FLAT
)
1197 fprintf (stderr
, "FLAT ");
1198 if (flags
& MASK_FMAF
)
1199 fprintf (stderr
, "FMAF ");
1200 if (flags
& MASK_FPU
)
1201 fprintf (stderr
, "FPU ");
1202 if (flags
& MASK_HARD_QUAD
)
1203 fprintf (stderr
, "HARD_QUAD ");
1204 if (flags
& MASK_POPC
)
1205 fprintf (stderr
, "POPC ");
1206 if (flags
& MASK_PTR64
)
1207 fprintf (stderr
, "PTR64 ");
1208 if (flags
& MASK_STACK_BIAS
)
1209 fprintf (stderr
, "STACK_BIAS ");
1210 if (flags
& MASK_UNALIGNED_DOUBLES
)
1211 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1212 if (flags
& MASK_V8PLUS
)
1213 fprintf (stderr
, "V8PLUS ");
1214 if (flags
& MASK_VIS
)
1215 fprintf (stderr
, "VIS ");
1216 if (flags
& MASK_VIS2
)
1217 fprintf (stderr
, "VIS2 ");
1218 if (flags
& MASK_VIS3
)
1219 fprintf (stderr
, "VIS3 ");
1220 if (flags
& MASK_CBCOND
)
1221 fprintf (stderr
, "CBCOND ");
1222 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1223 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1224 if (flags
& MASK_SPARCLET
)
1225 fprintf (stderr
, "SPARCLET ");
1226 if (flags
& MASK_SPARCLITE
)
1227 fprintf (stderr
, "SPARCLITE ");
1228 if (flags
& MASK_V8
)
1229 fprintf (stderr
, "V8 ");
1230 if (flags
& MASK_V9
)
1231 fprintf (stderr
, "V9 ");
1235 dump_target_flags (const char *prefix
, const int flags
)
1237 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1238 dump_target_flag_bits (flags
);
1239 fprintf(stderr
, "]\n");
1242 /* Validate and override various options, and do some machine dependent
1246 sparc_option_override (void)
1248 static struct code_model
{
1249 const char *const name
;
1250 const enum cmodel value
;
1251 } const cmodels
[] = {
1253 { "medlow", CM_MEDLOW
},
1254 { "medmid", CM_MEDMID
},
1255 { "medany", CM_MEDANY
},
1256 { "embmedany", CM_EMBMEDANY
},
1257 { NULL
, (enum cmodel
) 0 }
1259 const struct code_model
*cmodel
;
1260 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1261 static struct cpu_default
{
1263 const enum processor_type processor
;
1264 } const cpu_default
[] = {
1265 /* There must be one entry here for each TARGET_CPU value. */
1266 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1267 { TARGET_CPU_v8
, PROCESSOR_V8
},
1268 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1269 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1270 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1271 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1272 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1273 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1274 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1275 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1276 { TARGET_CPU_v9
, PROCESSOR_V9
},
1277 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1278 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1279 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1280 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1281 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1282 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1283 { -1, PROCESSOR_V7
}
1285 const struct cpu_default
*def
;
1286 /* Table of values for -m{cpu,tune}=. This must match the order of
1287 the enum processor_type in sparc-opts.h. */
1288 static struct cpu_table
{
1289 const char *const name
;
1292 } const cpu_table
[] = {
1293 { "v7", MASK_ISA
, 0 },
1294 { "cypress", MASK_ISA
, 0 },
1295 { "v8", MASK_ISA
, MASK_V8
},
1296 /* TI TMS390Z55 supersparc */
1297 { "supersparc", MASK_ISA
, MASK_V8
},
1298 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1299 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1300 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1301 { "leon3v7", MASK_ISA
, MASK_LEON3
|MASK_FPU
},
1302 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1303 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1304 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1305 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1306 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1307 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1308 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1309 /* TEMIC sparclet */
1310 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1311 { "v9", MASK_ISA
, MASK_V9
},
1312 /* UltraSPARC I, II, IIi */
1313 { "ultrasparc", MASK_ISA
,
1314 /* Although insns using %y are deprecated, it is a clear win. */
1315 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1316 /* UltraSPARC III */
1317 /* ??? Check if %y issue still holds true. */
1318 { "ultrasparc3", MASK_ISA
,
1319 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1321 { "niagara", MASK_ISA
,
1322 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1324 { "niagara2", MASK_ISA
,
1325 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1327 { "niagara3", MASK_ISA
,
1328 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
1330 { "niagara4", MASK_ISA
,
1331 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1333 const struct cpu_table
*cpu
;
1337 if (sparc_debug_string
!= NULL
)
1342 p
= ASTRDUP (sparc_debug_string
);
1343 while ((q
= strtok (p
, ",")) != NULL
)
1357 if (! strcmp (q
, "all"))
1358 mask
= MASK_DEBUG_ALL
;
1359 else if (! strcmp (q
, "options"))
1360 mask
= MASK_DEBUG_OPTIONS
;
1362 error ("unknown -mdebug-%s switch", q
);
1365 sparc_debug
&= ~mask
;
1367 sparc_debug
|= mask
;
1371 if (TARGET_DEBUG_OPTIONS
)
1373 dump_target_flags("Initial target_flags", target_flags
);
1374 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1377 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1378 SUBTARGET_OVERRIDE_OPTIONS
;
1381 #ifndef SPARC_BI_ARCH
1382 /* Check for unsupported architecture size. */
1383 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1384 error ("%s is not supported by this configuration",
1385 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1388 /* We force all 64bit archs to use 128 bit long double */
1389 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1391 error ("-mlong-double-64 not allowed with -m64");
1392 target_flags
|= MASK_LONG_DOUBLE_128
;
1395 /* Code model selection. */
1396 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1398 #ifdef SPARC_BI_ARCH
1400 sparc_cmodel
= CM_32
;
1403 if (sparc_cmodel_string
!= NULL
)
1407 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1408 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1410 if (cmodel
->name
== NULL
)
1411 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1413 sparc_cmodel
= cmodel
->value
;
1416 error ("-mcmodel= is not supported on 32 bit systems");
1419 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1420 for (i
= 8; i
< 16; i
++)
1421 if (!call_used_regs
[i
])
1423 error ("-fcall-saved-REG is not supported for out registers");
1424 call_used_regs
[i
] = 1;
1427 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1429 /* Set the default CPU. */
1430 if (!global_options_set
.x_sparc_cpu_and_features
)
1432 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1433 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1435 gcc_assert (def
->cpu
!= -1);
1436 sparc_cpu_and_features
= def
->processor
;
1439 if (!global_options_set
.x_sparc_cpu
)
1440 sparc_cpu
= sparc_cpu_and_features
;
1442 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1444 if (TARGET_DEBUG_OPTIONS
)
1446 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1447 fprintf (stderr
, "sparc_cpu: %s\n",
1448 cpu_table
[(int) sparc_cpu
].name
);
1449 dump_target_flags ("cpu->disable", cpu
->disable
);
1450 dump_target_flags ("cpu->enable", cpu
->enable
);
1453 target_flags
&= ~cpu
->disable
;
1454 target_flags
|= (cpu
->enable
1455 #ifndef HAVE_AS_FMAF_HPC_VIS3
1456 & ~(MASK_FMAF
| MASK_VIS3
)
1458 #ifndef HAVE_AS_SPARC4
1461 #ifndef HAVE_AS_LEON
1462 & ~(MASK_LEON
| MASK_LEON3
)
1466 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1467 the processor default. */
1468 if (target_flags_explicit
& MASK_FPU
)
1469 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1471 /* -mvis2 implies -mvis */
1473 target_flags
|= MASK_VIS
;
1475 /* -mvis3 implies -mvis2 and -mvis */
1477 target_flags
|= MASK_VIS2
| MASK_VIS
;
1479 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1482 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
1484 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1486 -m64 also implies v9. */
1487 if (TARGET_VIS
|| TARGET_ARCH64
)
1489 target_flags
|= MASK_V9
;
1490 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1493 /* -mvis also implies -mv8plus on 32-bit */
1494 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1495 target_flags
|= MASK_V8PLUS
;
1497 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1498 if (TARGET_V9
&& TARGET_ARCH32
)
1499 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1501 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1502 if (! TARGET_V9
|| TARGET_ARCH64
)
1503 target_flags
&= ~MASK_V8PLUS
;
1505 /* Don't use stack biasing in 32 bit mode. */
1507 target_flags
&= ~MASK_STACK_BIAS
;
1509 /* Supply a default value for align_functions. */
1510 if (align_functions
== 0
1511 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1512 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1513 || sparc_cpu
== PROCESSOR_NIAGARA
1514 || sparc_cpu
== PROCESSOR_NIAGARA2
1515 || sparc_cpu
== PROCESSOR_NIAGARA3
1516 || sparc_cpu
== PROCESSOR_NIAGARA4
))
1517 align_functions
= 32;
1519 /* Validate PCC_STRUCT_RETURN. */
1520 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1521 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1523 /* Only use .uaxword when compiling for a 64-bit target. */
1525 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1527 /* Do various machine dependent initializations. */
1528 sparc_init_modes ();
1530 /* Set up function hooks. */
1531 init_machine_status
= sparc_init_machine_status
;
1536 case PROCESSOR_CYPRESS
:
1537 sparc_costs
= &cypress_costs
;
1540 case PROCESSOR_SPARCLITE
:
1541 case PROCESSOR_SUPERSPARC
:
1542 sparc_costs
= &supersparc_costs
;
1544 case PROCESSOR_F930
:
1545 case PROCESSOR_F934
:
1546 case PROCESSOR_HYPERSPARC
:
1547 case PROCESSOR_SPARCLITE86X
:
1548 sparc_costs
= &hypersparc_costs
;
1550 case PROCESSOR_LEON
:
1551 sparc_costs
= &leon_costs
;
1553 case PROCESSOR_LEON3
:
1554 case PROCESSOR_LEON3V7
:
1555 sparc_costs
= &leon3_costs
;
1557 case PROCESSOR_SPARCLET
:
1558 case PROCESSOR_TSC701
:
1559 sparc_costs
= &sparclet_costs
;
1562 case PROCESSOR_ULTRASPARC
:
1563 sparc_costs
= &ultrasparc_costs
;
1565 case PROCESSOR_ULTRASPARC3
:
1566 sparc_costs
= &ultrasparc3_costs
;
1568 case PROCESSOR_NIAGARA
:
1569 sparc_costs
= &niagara_costs
;
1571 case PROCESSOR_NIAGARA2
:
1572 sparc_costs
= &niagara2_costs
;
1574 case PROCESSOR_NIAGARA3
:
1575 sparc_costs
= &niagara3_costs
;
1577 case PROCESSOR_NIAGARA4
:
1578 sparc_costs
= &niagara4_costs
;
1580 case PROCESSOR_NATIVE
:
1584 if (sparc_memory_model
== SMM_DEFAULT
)
1586 /* Choose the memory model for the operating system. */
1587 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1588 if (os_default
!= SMM_DEFAULT
)
1589 sparc_memory_model
= os_default
;
1590 /* Choose the most relaxed model for the processor. */
1592 sparc_memory_model
= SMM_RMO
;
1593 else if (TARGET_LEON3
)
1594 sparc_memory_model
= SMM_TSO
;
1595 else if (TARGET_LEON
)
1596 sparc_memory_model
= SMM_SC
;
1598 sparc_memory_model
= SMM_PSO
;
1600 sparc_memory_model
= SMM_SC
;
1603 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1604 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1605 target_flags
|= MASK_LONG_DOUBLE_128
;
1608 if (TARGET_DEBUG_OPTIONS
)
1609 dump_target_flags ("Final target_flags", target_flags
);
1611 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1612 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1613 || sparc_cpu
== PROCESSOR_NIAGARA
1614 || sparc_cpu
== PROCESSOR_NIAGARA2
1615 || sparc_cpu
== PROCESSOR_NIAGARA3
1616 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1618 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1620 global_options
.x_param_values
,
1621 global_options_set
.x_param_values
);
1622 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1623 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1624 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1625 || sparc_cpu
== PROCESSOR_NIAGARA
1626 || sparc_cpu
== PROCESSOR_NIAGARA2
1627 || sparc_cpu
== PROCESSOR_NIAGARA3
1628 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1630 global_options
.x_param_values
,
1631 global_options_set
.x_param_values
);
1633 /* Disable save slot sharing for call-clobbered registers by default.
1634 The IRA sharing algorithm works on single registers only and this
1635 pessimizes for double floating-point registers. */
1636 if (!global_options_set
.x_flag_ira_share_save_slots
)
1637 flag_ira_share_save_slots
= 0;
1639 /* We register a machine specific pass to work around errata, if any.
1640 The pass mut be scheduled as late as possible so that we have the
1641 (essentially) final form of the insn stream to work on.
1642 Registering the pass must be done at start up. It's convenient to
1644 opt_pass
*errata_pass
= make_pass_work_around_errata (g
);
1645 struct register_pass_info insert_pass_work_around_errata
=
1647 errata_pass
, /* pass */
1648 "dbr", /* reference_pass_name */
1649 1, /* ref_pass_instance_number */
1650 PASS_POS_INSERT_AFTER
/* po_op */
1652 register_pass (&insert_pass_work_around_errata
);
1655 /* Miscellaneous utilities. */
1657 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1658 or branch on register contents instructions. */
1661 v9_regcmp_p (enum rtx_code code
)
1663 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1664 || code
== LE
|| code
== GT
);
1667 /* Nonzero if OP is a floating point constant which can
1668 be loaded into an integer register using a single
1669 sethi instruction. */
1674 if (GET_CODE (op
) == CONST_DOUBLE
)
1679 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1680 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1681 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1687 /* Nonzero if OP is a floating point constant which can
1688 be loaded into an integer register using a single
1694 if (GET_CODE (op
) == CONST_DOUBLE
)
1699 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1700 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1701 return SPARC_SIMM13_P (i
);
1707 /* Nonzero if OP is a floating point constant which can
1708 be loaded into an integer register using a high/losum
1709 instruction sequence. */
1712 fp_high_losum_p (rtx op
)
1714 /* The constraints calling this should only be in
1715 SFmode move insns, so any constant which cannot
1716 be moved using a single insn will do. */
1717 if (GET_CODE (op
) == CONST_DOUBLE
)
1722 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1723 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1724 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1730 /* Return true if the address of LABEL can be loaded by means of the
1731 mov{si,di}_pic_label_ref patterns in PIC mode. */
1734 can_use_mov_pic_label_ref (rtx label
)
1736 /* VxWorks does not impose a fixed gap between segments; the run-time
1737 gap can be different from the object-file gap. We therefore can't
1738 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1739 are absolutely sure that X is in the same segment as the GOT.
1740 Unfortunately, the flexibility of linker scripts means that we
1741 can't be sure of that in general, so assume that GOT-relative
1742 accesses are never valid on VxWorks. */
1743 if (TARGET_VXWORKS_RTP
)
1746 /* Similarly, if the label is non-local, it might end up being placed
1747 in a different section than the current one; now mov_pic_label_ref
1748 requires the label and the code to be in the same section. */
1749 if (LABEL_REF_NONLOCAL_P (label
))
1752 /* Finally, if we are reordering basic blocks and partition into hot
1753 and cold sections, this might happen for any label. */
1754 if (flag_reorder_blocks_and_partition
)
1760 /* Expand a move instruction. Return true if all work is done. */
1763 sparc_expand_move (machine_mode mode
, rtx
*operands
)
1765 /* Handle sets of MEM first. */
1766 if (GET_CODE (operands
[0]) == MEM
)
1768 /* 0 is a register (or a pair of registers) on SPARC. */
1769 if (register_or_zero_operand (operands
[1], mode
))
1772 if (!reload_in_progress
)
1774 operands
[0] = validize_mem (operands
[0]);
1775 operands
[1] = force_reg (mode
, operands
[1]);
1779 /* Fixup TLS cases. */
1781 && CONSTANT_P (operands
[1])
1782 && sparc_tls_referenced_p (operands
[1]))
1784 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1788 /* Fixup PIC cases. */
1789 if (flag_pic
&& CONSTANT_P (operands
[1]))
1791 if (pic_address_needs_scratch (operands
[1]))
1792 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1794 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1795 if (GET_CODE (operands
[1]) == LABEL_REF
1796 && can_use_mov_pic_label_ref (operands
[1]))
1800 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1806 gcc_assert (TARGET_ARCH64
);
1807 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1812 if (symbolic_operand (operands
[1], mode
))
1815 = sparc_legitimize_pic_address (operands
[1],
1817 ? operands
[0] : NULL_RTX
);
1822 /* If we are trying to toss an integer constant into FP registers,
1823 or loading a FP or vector constant, force it into memory. */
1824 if (CONSTANT_P (operands
[1])
1825 && REG_P (operands
[0])
1826 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1827 || SCALAR_FLOAT_MODE_P (mode
)
1828 || VECTOR_MODE_P (mode
)))
1830 /* emit_group_store will send such bogosity to us when it is
1831 not storing directly into memory. So fix this up to avoid
1832 crashes in output_constant_pool. */
1833 if (operands
[1] == const0_rtx
)
1834 operands
[1] = CONST0_RTX (mode
);
1836 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1837 always other regs. */
1838 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1839 && (const_zero_operand (operands
[1], mode
)
1840 || const_all_ones_operand (operands
[1], mode
)))
1843 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1844 /* We are able to build any SF constant in integer registers
1845 with at most 2 instructions. */
1847 /* And any DF constant in integer registers. */
1849 && ! can_create_pseudo_p ())))
1852 operands
[1] = force_const_mem (mode
, operands
[1]);
1853 if (!reload_in_progress
)
1854 operands
[1] = validize_mem (operands
[1]);
1858 /* Accept non-constants and valid constants unmodified. */
1859 if (!CONSTANT_P (operands
[1])
1860 || GET_CODE (operands
[1]) == HIGH
1861 || input_operand (operands
[1], mode
))
1867 /* All QImode constants require only one insn, so proceed. */
1872 sparc_emit_set_const32 (operands
[0], operands
[1]);
1876 /* input_operand should have filtered out 32-bit mode. */
1877 sparc_emit_set_const64 (operands
[0], operands
[1]);
1883 /* TImode isn't available in 32-bit mode. */
1884 split_double (operands
[1], &high
, &low
);
1885 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1887 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1899 /* Load OP1, a 32-bit constant, into OP0, a register.
1900 We know it can't be done in one insn when we get
1901 here, the move expander guarantees this. */
1904 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1906 machine_mode mode
= GET_MODE (op0
);
1909 if (can_create_pseudo_p ())
1910 temp
= gen_reg_rtx (mode
);
1912 if (GET_CODE (op1
) == CONST_INT
)
1914 gcc_assert (!small_int_operand (op1
, mode
)
1915 && !const_high_operand (op1
, mode
));
1917 /* Emit them as real moves instead of a HIGH/LO_SUM,
1918 this way CSE can see everything and reuse intermediate
1919 values if it wants. */
1920 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1921 GEN_INT (INTVAL (op1
)
1922 & ~(HOST_WIDE_INT
)0x3ff)));
1924 emit_insn (gen_rtx_SET (VOIDmode
,
1926 gen_rtx_IOR (mode
, temp
,
1927 GEN_INT (INTVAL (op1
) & 0x3ff))));
1931 /* A symbol, emit in the traditional way. */
1932 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1933 gen_rtx_HIGH (mode
, op1
)));
1934 emit_insn (gen_rtx_SET (VOIDmode
,
1935 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1939 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1940 If TEMP is nonzero, we are forbidden to use any other scratch
1941 registers. Otherwise, we are allowed to generate them as needed.
1943 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1944 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1947 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1949 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1952 if (temp
&& GET_MODE (temp
) == TImode
)
1955 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1958 /* SPARC-V9 code-model support. */
1959 switch (sparc_cmodel
)
1962 /* The range spanned by all instructions in the object is less
1963 than 2^31 bytes (2GB) and the distance from any instruction
1964 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1965 than 2^31 bytes (2GB).
1967 The executable must be in the low 4TB of the virtual address
1970 sethi %hi(symbol), %temp1
1971 or %temp1, %lo(symbol), %reg */
1973 temp1
= temp
; /* op0 is allowed. */
1975 temp1
= gen_reg_rtx (DImode
);
1977 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1978 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1982 /* The range spanned by all instructions in the object is less
1983 than 2^31 bytes (2GB) and the distance from any instruction
1984 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1985 than 2^31 bytes (2GB).
1987 The executable must be in the low 16TB of the virtual address
1990 sethi %h44(symbol), %temp1
1991 or %temp1, %m44(symbol), %temp2
1992 sllx %temp2, 12, %temp3
1993 or %temp3, %l44(symbol), %reg */
1998 temp3
= temp
; /* op0 is allowed. */
2002 temp1
= gen_reg_rtx (DImode
);
2003 temp2
= gen_reg_rtx (DImode
);
2004 temp3
= gen_reg_rtx (DImode
);
2007 emit_insn (gen_seth44 (temp1
, op1
));
2008 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2009 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
2010 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2011 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2015 /* The range spanned by all instructions in the object is less
2016 than 2^31 bytes (2GB) and the distance from any instruction
2017 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2018 than 2^31 bytes (2GB).
2020 The executable can be placed anywhere in the virtual address
2023 sethi %hh(symbol), %temp1
2024 sethi %lm(symbol), %temp2
2025 or %temp1, %hm(symbol), %temp3
2026 sllx %temp3, 32, %temp4
2027 or %temp4, %temp2, %temp5
2028 or %temp5, %lo(symbol), %reg */
2031 /* It is possible that one of the registers we got for operands[2]
2032 might coincide with that of operands[0] (which is why we made
2033 it TImode). Pick the other one to use as our scratch. */
2034 if (rtx_equal_p (temp
, op0
))
2036 gcc_assert (ti_temp
);
2037 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2040 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2047 temp1
= gen_reg_rtx (DImode
);
2048 temp2
= gen_reg_rtx (DImode
);
2049 temp3
= gen_reg_rtx (DImode
);
2050 temp4
= gen_reg_rtx (DImode
);
2051 temp5
= gen_reg_rtx (DImode
);
2054 emit_insn (gen_sethh (temp1
, op1
));
2055 emit_insn (gen_setlm (temp2
, op1
));
2056 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2057 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2058 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2059 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2060 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2061 emit_insn (gen_setlo (op0
, temp5
, op1
));
2065 /* Old old old backwards compatibility kruft here.
2066 Essentially it is MEDLOW with a fixed 64-bit
2067 virtual base added to all data segment addresses.
2068 Text-segment stuff is computed like MEDANY, we can't
2069 reuse the code above because the relocation knobs
2072 Data segment: sethi %hi(symbol), %temp1
2073 add %temp1, EMBMEDANY_BASE_REG, %temp2
2074 or %temp2, %lo(symbol), %reg */
2075 if (data_segment_operand (op1
, GET_MODE (op1
)))
2079 temp1
= temp
; /* op0 is allowed. */
2084 temp1
= gen_reg_rtx (DImode
);
2085 temp2
= gen_reg_rtx (DImode
);
2088 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2089 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2090 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2093 /* Text segment: sethi %uhi(symbol), %temp1
2094 sethi %hi(symbol), %temp2
2095 or %temp1, %ulo(symbol), %temp3
2096 sllx %temp3, 32, %temp4
2097 or %temp4, %temp2, %temp5
2098 or %temp5, %lo(symbol), %reg */
2103 /* It is possible that one of the registers we got for operands[2]
2104 might coincide with that of operands[0] (which is why we made
2105 it TImode). Pick the other one to use as our scratch. */
2106 if (rtx_equal_p (temp
, op0
))
2108 gcc_assert (ti_temp
);
2109 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2112 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2119 temp1
= gen_reg_rtx (DImode
);
2120 temp2
= gen_reg_rtx (DImode
);
2121 temp3
= gen_reg_rtx (DImode
);
2122 temp4
= gen_reg_rtx (DImode
);
2123 temp5
= gen_reg_rtx (DImode
);
2126 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2127 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2128 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2129 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2130 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2131 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2132 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2133 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2142 #if HOST_BITS_PER_WIDE_INT == 32
2144 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
2149 /* These avoid problems when cross compiling. If we do not
2150 go through all this hair then the optimizer will see
2151 invalid REG_EQUAL notes or in some cases none at all. */
2152 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2153 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2154 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2155 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2157 /* The optimizer is not to assume anything about exactly
2158 which bits are set for a HIGH, they are unspecified.
2159 Unfortunately this leads to many missed optimizations
2160 during CSE. We mask out the non-HIGH bits, and matches
2161 a plain movdi, to alleviate this problem. */
2163 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2165 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2169 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2171 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
2175 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2177 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2181 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2183 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2186 /* Worker routines for 64-bit constant formation on arch64.
2187 One of the key things to be doing in these emissions is
2188 to create as many temp REGs as possible. This makes it
2189 possible for half-built constants to be used later when
2190 such values are similar to something required later on.
2191 Without doing this, the optimizer cannot see such
2194 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2195 unsigned HOST_WIDE_INT
, int);
2198 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2199 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2201 unsigned HOST_WIDE_INT high_bits
;
2204 high_bits
= (~low_bits
) & 0xffffffff;
2206 high_bits
= low_bits
;
2208 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2211 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2212 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2216 /* If we are XOR'ing with -1, then we should emit a one's complement
2217 instead. This way the combiner will notice logical operations
2218 such as ANDN later on and substitute. */
2219 if ((low_bits
& 0x3ff) == 0x3ff)
2221 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2222 gen_rtx_NOT (DImode
, temp
)));
2226 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2227 gen_safe_XOR64 (temp
,
2228 (-(HOST_WIDE_INT
)0x400
2229 | (low_bits
& 0x3ff)))));
2234 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2235 unsigned HOST_WIDE_INT
, int);
2238 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2239 unsigned HOST_WIDE_INT high_bits
,
2240 unsigned HOST_WIDE_INT low_immediate
,
2245 if ((high_bits
& 0xfffffc00) != 0)
2247 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2248 if ((high_bits
& ~0xfffffc00) != 0)
2249 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2250 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2256 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2260 /* Now shift it up into place. */
2261 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2262 gen_rtx_ASHIFT (DImode
, temp2
,
2263 GEN_INT (shift_count
))));
2265 /* If there is a low immediate part piece, finish up by
2266 putting that in as well. */
2267 if (low_immediate
!= 0)
2268 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2269 gen_safe_OR64 (op0
, low_immediate
)));
2272 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2273 unsigned HOST_WIDE_INT
);
2275 /* Full 64-bit constant decomposition. Even though this is the
2276 'worst' case, we still optimize a few things away. */
2278 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2279 unsigned HOST_WIDE_INT high_bits
,
2280 unsigned HOST_WIDE_INT low_bits
)
2284 if (can_create_pseudo_p ())
2285 sub_temp
= gen_reg_rtx (DImode
);
2287 if ((high_bits
& 0xfffffc00) != 0)
2289 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2290 if ((high_bits
& ~0xfffffc00) != 0)
2291 emit_insn (gen_rtx_SET (VOIDmode
,
2293 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2299 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2303 if (can_create_pseudo_p ())
2305 rtx temp2
= gen_reg_rtx (DImode
);
2306 rtx temp3
= gen_reg_rtx (DImode
);
2307 rtx temp4
= gen_reg_rtx (DImode
);
2309 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2310 gen_rtx_ASHIFT (DImode
, sub_temp
,
2313 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2314 if ((low_bits
& ~0xfffffc00) != 0)
2316 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
2317 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2318 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2319 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2323 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2324 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2329 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2330 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2331 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2334 /* We are in the middle of reload, so this is really
2335 painful. However we do still make an attempt to
2336 avoid emitting truly stupid code. */
2337 if (low1
!= const0_rtx
)
2339 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2340 gen_rtx_ASHIFT (DImode
, sub_temp
,
2341 GEN_INT (to_shift
))));
2342 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2343 gen_rtx_IOR (DImode
, op0
, low1
)));
2351 if (low2
!= const0_rtx
)
2353 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2354 gen_rtx_ASHIFT (DImode
, sub_temp
,
2355 GEN_INT (to_shift
))));
2356 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2357 gen_rtx_IOR (DImode
, op0
, low2
)));
2365 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2366 gen_rtx_ASHIFT (DImode
, sub_temp
,
2367 GEN_INT (to_shift
))));
2368 if (low3
!= const0_rtx
)
2369 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2370 gen_rtx_IOR (DImode
, op0
, low3
)));
2375 /* Analyze a 64-bit constant for certain properties. */
2376 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2377 unsigned HOST_WIDE_INT
,
2378 int *, int *, int *);
2381 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2382 unsigned HOST_WIDE_INT low_bits
,
2383 int *hbsp
, int *lbsp
, int *abbasp
)
2385 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2388 lowest_bit_set
= highest_bit_set
= -1;
2392 if ((lowest_bit_set
== -1)
2393 && ((low_bits
>> i
) & 1))
2395 if ((highest_bit_set
== -1)
2396 && ((high_bits
>> (32 - i
- 1)) & 1))
2397 highest_bit_set
= (64 - i
- 1);
2400 && ((highest_bit_set
== -1)
2401 || (lowest_bit_set
== -1)));
2407 if ((lowest_bit_set
== -1)
2408 && ((high_bits
>> i
) & 1))
2409 lowest_bit_set
= i
+ 32;
2410 if ((highest_bit_set
== -1)
2411 && ((low_bits
>> (32 - i
- 1)) & 1))
2412 highest_bit_set
= 32 - i
- 1;
2415 && ((highest_bit_set
== -1)
2416 || (lowest_bit_set
== -1)));
2418 /* If there are no bits set this should have gone out
2419 as one instruction! */
2420 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2421 all_bits_between_are_set
= 1;
2422 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2426 if ((low_bits
& (1 << i
)) != 0)
2431 if ((high_bits
& (1 << (i
- 32))) != 0)
2434 all_bits_between_are_set
= 0;
2437 *hbsp
= highest_bit_set
;
2438 *lbsp
= lowest_bit_set
;
2439 *abbasp
= all_bits_between_are_set
;
2442 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2445 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2446 unsigned HOST_WIDE_INT low_bits
)
2448 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2451 || high_bits
== 0xffffffff)
2454 analyze_64bit_constant (high_bits
, low_bits
,
2455 &highest_bit_set
, &lowest_bit_set
,
2456 &all_bits_between_are_set
);
2458 if ((highest_bit_set
== 63
2459 || lowest_bit_set
== 0)
2460 && all_bits_between_are_set
!= 0)
2463 if ((highest_bit_set
- lowest_bit_set
) < 21)
2469 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2470 unsigned HOST_WIDE_INT
,
2473 static unsigned HOST_WIDE_INT
2474 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2475 unsigned HOST_WIDE_INT low_bits
,
2476 int lowest_bit_set
, int shift
)
2478 HOST_WIDE_INT hi
, lo
;
2480 if (lowest_bit_set
< 32)
2482 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2483 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2488 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2490 gcc_assert (! (hi
& lo
));
2494 /* Here we are sure to be arch64 and this is an integer constant
2495 being loaded into a register. Emit the most efficient
2496 insn sequence possible. Detection of all the 1-insn cases
2497 has been done already. */
2499 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2501 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2502 int lowest_bit_set
, highest_bit_set
;
2503 int all_bits_between_are_set
;
2506 /* Sanity check that we know what we are working with. */
2507 gcc_assert (TARGET_ARCH64
2508 && (GET_CODE (op0
) == SUBREG
2509 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2511 if (! can_create_pseudo_p ())
2514 if (GET_CODE (op1
) != CONST_INT
)
2516 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2521 temp
= gen_reg_rtx (DImode
);
2523 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2524 low_bits
= (INTVAL (op1
) & 0xffffffff);
2526 /* low_bits bits 0 --> 31
2527 high_bits bits 32 --> 63 */
2529 analyze_64bit_constant (high_bits
, low_bits
,
2530 &highest_bit_set
, &lowest_bit_set
,
2531 &all_bits_between_are_set
);
2533 /* First try for a 2-insn sequence. */
2535 /* These situations are preferred because the optimizer can
2536 * do more things with them:
2538 * sllx %reg, shift, %reg
2540 * srlx %reg, shift, %reg
2541 * 3) mov some_small_const, %reg
2542 * sllx %reg, shift, %reg
2544 if (((highest_bit_set
== 63
2545 || lowest_bit_set
== 0)
2546 && all_bits_between_are_set
!= 0)
2547 || ((highest_bit_set
- lowest_bit_set
) < 12))
2549 HOST_WIDE_INT the_const
= -1;
2550 int shift
= lowest_bit_set
;
2552 if ((highest_bit_set
!= 63
2553 && lowest_bit_set
!= 0)
2554 || all_bits_between_are_set
== 0)
2557 create_simple_focus_bits (high_bits
, low_bits
,
2560 else if (lowest_bit_set
== 0)
2561 shift
= -(63 - highest_bit_set
);
2563 gcc_assert (SPARC_SIMM13_P (the_const
));
2564 gcc_assert (shift
!= 0);
2566 emit_insn (gen_safe_SET64 (temp
, the_const
));
2568 emit_insn (gen_rtx_SET (VOIDmode
,
2570 gen_rtx_ASHIFT (DImode
,
2574 emit_insn (gen_rtx_SET (VOIDmode
,
2576 gen_rtx_LSHIFTRT (DImode
,
2578 GEN_INT (-shift
))));
2582 /* Now a range of 22 or less bits set somewhere.
2583 * 1) sethi %hi(focus_bits), %reg
2584 * sllx %reg, shift, %reg
2585 * 2) sethi %hi(focus_bits), %reg
2586 * srlx %reg, shift, %reg
2588 if ((highest_bit_set
- lowest_bit_set
) < 21)
2590 unsigned HOST_WIDE_INT focus_bits
=
2591 create_simple_focus_bits (high_bits
, low_bits
,
2592 lowest_bit_set
, 10);
2594 gcc_assert (SPARC_SETHI_P (focus_bits
));
2595 gcc_assert (lowest_bit_set
!= 10);
2597 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2599 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2600 if (lowest_bit_set
< 10)
2601 emit_insn (gen_rtx_SET (VOIDmode
,
2603 gen_rtx_LSHIFTRT (DImode
, temp
,
2604 GEN_INT (10 - lowest_bit_set
))));
2605 else if (lowest_bit_set
> 10)
2606 emit_insn (gen_rtx_SET (VOIDmode
,
2608 gen_rtx_ASHIFT (DImode
, temp
,
2609 GEN_INT (lowest_bit_set
- 10))));
2613 /* 1) sethi %hi(low_bits), %reg
2614 * or %reg, %lo(low_bits), %reg
2615 * 2) sethi %hi(~low_bits), %reg
2616 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2619 || high_bits
== 0xffffffff)
2621 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2622 (high_bits
== 0xffffffff));
2626 /* Now, try 3-insn sequences. */
2628 /* 1) sethi %hi(high_bits), %reg
2629 * or %reg, %lo(high_bits), %reg
2630 * sllx %reg, 32, %reg
2634 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2638 /* We may be able to do something quick
2639 when the constant is negated, so try that. */
2640 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2641 (~low_bits
) & 0xfffffc00))
2643 /* NOTE: The trailing bits get XOR'd so we need the
2644 non-negated bits, not the negated ones. */
2645 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2647 if ((((~high_bits
) & 0xffffffff) == 0
2648 && ((~low_bits
) & 0x80000000) == 0)
2649 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2650 && ((~low_bits
) & 0x80000000) != 0))
2652 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2654 if ((SPARC_SETHI_P (fast_int
)
2655 && (~high_bits
& 0xffffffff) == 0)
2656 || SPARC_SIMM13_P (fast_int
))
2657 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2659 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2664 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2665 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2666 sparc_emit_set_const64 (temp
, negated_const
);
2669 /* If we are XOR'ing with -1, then we should emit a one's complement
2670 instead. This way the combiner will notice logical operations
2671 such as ANDN later on and substitute. */
2672 if (trailing_bits
== 0x3ff)
2674 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2675 gen_rtx_NOT (DImode
, temp
)));
2679 emit_insn (gen_rtx_SET (VOIDmode
,
2681 gen_safe_XOR64 (temp
,
2682 (-0x400 | trailing_bits
))));
2687 /* 1) sethi %hi(xxx), %reg
2688 * or %reg, %lo(xxx), %reg
2689 * sllx %reg, yyy, %reg
2691 * ??? This is just a generalized version of the low_bits==0
2692 * thing above, FIXME...
2694 if ((highest_bit_set
- lowest_bit_set
) < 32)
2696 unsigned HOST_WIDE_INT focus_bits
=
2697 create_simple_focus_bits (high_bits
, low_bits
,
2700 /* We can't get here in this state. */
2701 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2703 /* So what we know is that the set bits straddle the
2704 middle of the 64-bit word. */
2705 sparc_emit_set_const64_quick2 (op0
, temp
,
2711 /* 1) sethi %hi(high_bits), %reg
2712 * or %reg, %lo(high_bits), %reg
2713 * sllx %reg, 32, %reg
2714 * or %reg, low_bits, %reg
2716 if (SPARC_SIMM13_P(low_bits
)
2717 && ((int)low_bits
> 0))
2719 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2723 /* The easiest way when all else fails, is full decomposition. */
2724 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2726 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2728 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2729 return the mode to be used for the comparison. For floating-point,
2730 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2731 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2732 processing is needed. */
2735 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2737 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2763 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2764 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2766 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2767 return CCX_NOOVmode
;
2773 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2780 /* Emit the compare insn and return the CC reg for a CODE comparison
2781 with operands X and Y. */
2784 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2789 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2792 mode
= SELECT_CC_MODE (code
, x
, y
);
2794 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2795 fcc regs (cse can't tell they're really call clobbered regs and will
2796 remove a duplicate comparison even if there is an intervening function
2797 call - it will then try to reload the cc reg via an int reg which is why
2798 we need the movcc patterns). It is possible to provide the movcc
2799 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2800 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2801 to tell cse that CCFPE mode registers (even pseudos) are call
2804 /* ??? This is an experiment. Rather than making changes to cse which may
2805 or may not be easy/clean, we do our own cse. This is possible because
2806 we will generate hard registers. Cse knows they're call clobbered (it
2807 doesn't know the same thing about pseudos). If we guess wrong, no big
2808 deal, but if we win, great! */
2810 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2811 #if 1 /* experiment */
2814 /* We cycle through the registers to ensure they're all exercised. */
2815 static int next_fcc_reg
= 0;
2816 /* Previous x,y for each fcc reg. */
2817 static rtx prev_args
[4][2];
2819 /* Scan prev_args for x,y. */
2820 for (reg
= 0; reg
< 4; reg
++)
2821 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2826 prev_args
[reg
][0] = x
;
2827 prev_args
[reg
][1] = y
;
2828 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2830 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2833 cc_reg
= gen_reg_rtx (mode
);
2834 #endif /* ! experiment */
2835 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2836 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2838 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2840 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2841 will only result in an unrecognizable insn so no point in asserting. */
2842 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2848 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2851 gen_compare_reg (rtx cmp
)
2853 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2856 /* This function is used for v9 only.
2857 DEST is the target of the Scc insn.
2858 CODE is the code for an Scc's comparison.
2859 X and Y are the values we compare.
2861 This function is needed to turn
2864 (gt (reg:CCX 100 %icc)
2868 (gt:DI (reg:CCX 100 %icc)
2871 IE: The instruction recognizer needs to see the mode of the comparison to
2872 find the right instruction. We could use "gt:DI" right in the
2873 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2876 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2879 && (GET_MODE (x
) == DImode
2880 || GET_MODE (dest
) == DImode
))
2883 /* Try to use the movrCC insns. */
2885 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2887 && v9_regcmp_p (compare_code
))
2892 /* Special case for op0 != 0. This can be done with one instruction if
2895 if (compare_code
== NE
2896 && GET_MODE (dest
) == DImode
2897 && rtx_equal_p (op0
, dest
))
2899 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2900 gen_rtx_IF_THEN_ELSE (DImode
,
2901 gen_rtx_fmt_ee (compare_code
, DImode
,
2908 if (reg_overlap_mentioned_p (dest
, op0
))
2910 /* Handle the case where dest == x.
2911 We "early clobber" the result. */
2912 op0
= gen_reg_rtx (GET_MODE (x
));
2913 emit_move_insn (op0
, x
);
2916 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2917 if (GET_MODE (op0
) != DImode
)
2919 temp
= gen_reg_rtx (DImode
);
2920 convert_move (temp
, op0
, 0);
2924 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2925 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2926 gen_rtx_fmt_ee (compare_code
, DImode
,
2934 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2937 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2938 && GET_MODE (x
) != CCX_NOOVmode
);
2940 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2941 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2942 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2943 gen_rtx_fmt_ee (compare_code
,
2944 GET_MODE (x
), x
, y
),
2945 const1_rtx
, dest
)));
2951 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2952 without jumps using the addx/subx instructions. */
2955 emit_scc_insn (rtx operands
[])
2962 /* The quad-word fp compare library routines all return nonzero to indicate
2963 true, which is different from the equivalent libgcc routines, so we must
2964 handle them specially here. */
2965 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2967 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2968 GET_CODE (operands
[1]));
2969 operands
[2] = XEXP (operands
[1], 0);
2970 operands
[3] = XEXP (operands
[1], 1);
2973 code
= GET_CODE (operands
[1]);
2977 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2978 more applications). The exception to this is "reg != 0" which can
2979 be done in one instruction on v9 (so we do it). */
2982 if (GET_MODE (x
) == SImode
)
2986 pat
= gen_seqsidi_special (operands
[0], x
, y
);
2988 pat
= gen_seqsisi_special (operands
[0], x
, y
);
2992 else if (GET_MODE (x
) == DImode
)
2994 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
3002 if (GET_MODE (x
) == SImode
)
3006 pat
= gen_snesidi_special (operands
[0], x
, y
);
3008 pat
= gen_snesisi_special (operands
[0], x
, y
);
3012 else if (GET_MODE (x
) == DImode
)
3016 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
3018 pat
= gen_snedi_special (operands
[0], x
, y
);
3026 && GET_MODE (x
) == DImode
3028 && (code
== GTU
|| code
== LTU
))
3029 && gen_v9_scc (operands
[0], code
, x
, y
))
3032 /* We can do LTU and GEU using the addx/subx instructions too. And
3033 for GTU/LEU, if both operands are registers swap them and fall
3034 back to the easy case. */
3035 if (code
== GTU
|| code
== LEU
)
3037 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3038 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3043 code
= swap_condition (code
);
3048 || (!TARGET_VIS3
&& code
== GEU
))
3050 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3051 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3052 gen_compare_reg_1 (code
, x
, y
),
3057 /* All the posibilities to use addx/subx based sequences has been
3058 exhausted, try for a 3 instruction sequence using v9 conditional
3060 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3063 /* Nope, do branches. */
3067 /* Emit a conditional jump insn for the v9 architecture using comparison code
3068 CODE and jump target LABEL.
3069 This function exists to take advantage of the v9 brxx insns. */
3072 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3074 emit_jump_insn (gen_rtx_SET (VOIDmode
,
3076 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3077 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3079 gen_rtx_LABEL_REF (VOIDmode
, label
),
3083 /* Emit a conditional jump insn for the UA2011 architecture using
3084 comparison code CODE and jump target LABEL. This function exists
3085 to take advantage of the UA2011 Compare and Branch insns. */
3088 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3092 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3093 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3095 gen_rtx_LABEL_REF (VOIDmode
, label
),
3098 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
3102 emit_conditional_branch_insn (rtx operands
[])
3104 /* The quad-word fp compare library routines all return nonzero to indicate
3105 true, which is different from the equivalent libgcc routines, so we must
3106 handle them specially here. */
3107 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3109 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3110 GET_CODE (operands
[0]));
3111 operands
[1] = XEXP (operands
[0], 0);
3112 operands
[2] = XEXP (operands
[0], 1);
3115 /* If we can tell early on that the comparison is against a constant
3116 that won't fit in the 5-bit signed immediate field of a cbcond,
3117 use one of the other v9 conditional branch sequences. */
3119 && GET_CODE (operands
[1]) == REG
3120 && (GET_MODE (operands
[1]) == SImode
3121 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3122 && (GET_CODE (operands
[2]) != CONST_INT
3123 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3125 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3129 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3130 && GET_CODE (operands
[1]) == REG
3131 && GET_MODE (operands
[1]) == DImode
)
3133 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3137 operands
[1] = gen_compare_reg (operands
[0]);
3138 operands
[2] = const0_rtx
;
3139 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3140 operands
[1], operands
[2]);
3141 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3146 /* Generate a DFmode part of a hard TFmode register.
3147 REG is the TFmode hard register, LOW is 1 for the
3148 low 64bit of the register and 0 otherwise.
3151 gen_df_reg (rtx reg
, int low
)
3153 int regno
= REGNO (reg
);
3155 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3156 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3157 return gen_rtx_REG (DFmode
, regno
);
3160 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3161 Unlike normal calls, TFmode operands are passed by reference. It is
3162 assumed that no more than 3 operands are required. */
3165 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3167 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3170 /* We only expect to be called for conversions, unary, and binary ops. */
3171 gcc_assert (nargs
== 2 || nargs
== 3);
3173 for (i
= 0; i
< nargs
; ++i
)
3175 rtx this_arg
= operands
[i
];
3178 /* TFmode arguments and return values are passed by reference. */
3179 if (GET_MODE (this_arg
) == TFmode
)
3181 int force_stack_temp
;
3183 force_stack_temp
= 0;
3184 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3185 force_stack_temp
= 1;
3187 if (GET_CODE (this_arg
) == MEM
3188 && ! force_stack_temp
)
3190 tree expr
= MEM_EXPR (this_arg
);
3192 mark_addressable (expr
);
3193 this_arg
= XEXP (this_arg
, 0);
3195 else if (CONSTANT_P (this_arg
)
3196 && ! force_stack_temp
)
3198 this_slot
= force_const_mem (TFmode
, this_arg
);
3199 this_arg
= XEXP (this_slot
, 0);
3203 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3205 /* Operand 0 is the return value. We'll copy it out later. */
3207 emit_move_insn (this_slot
, this_arg
);
3209 ret_slot
= this_slot
;
3211 this_arg
= XEXP (this_slot
, 0);
3218 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3220 if (GET_MODE (operands
[0]) == TFmode
)
3223 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3224 arg
[0], GET_MODE (arg
[0]),
3225 arg
[1], GET_MODE (arg
[1]));
3227 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3228 arg
[0], GET_MODE (arg
[0]),
3229 arg
[1], GET_MODE (arg
[1]),
3230 arg
[2], GET_MODE (arg
[2]));
3233 emit_move_insn (operands
[0], ret_slot
);
3239 gcc_assert (nargs
== 2);
3241 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3242 GET_MODE (operands
[0]), 1,
3243 arg
[1], GET_MODE (arg
[1]));
3245 if (ret
!= operands
[0])
3246 emit_move_insn (operands
[0], ret
);
3250 /* Expand soft-float TFmode calls to sparc abi routines. */
3253 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3275 emit_soft_tfmode_libcall (func
, 3, operands
);
3279 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3283 gcc_assert (code
== SQRT
);
3286 emit_soft_tfmode_libcall (func
, 2, operands
);
3290 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3297 switch (GET_MODE (operands
[1]))
3310 case FLOAT_TRUNCATE
:
3311 switch (GET_MODE (operands
[0]))
3325 switch (GET_MODE (operands
[1]))
3330 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3340 case UNSIGNED_FLOAT
:
3341 switch (GET_MODE (operands
[1]))
3346 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3357 switch (GET_MODE (operands
[0]))
3371 switch (GET_MODE (operands
[0]))
3388 emit_soft_tfmode_libcall (func
, 2, operands
);
3391 /* Expand a hard-float tfmode operation. All arguments must be in
3395 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3399 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3401 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3402 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3406 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3407 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3408 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3409 operands
[1], operands
[2]);
3412 if (register_operand (operands
[0], VOIDmode
))
3415 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3417 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
3419 if (dest
!= operands
[0])
3420 emit_move_insn (operands
[0], dest
);
3424 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3426 if (TARGET_HARD_QUAD
)
3427 emit_hard_tfmode_operation (code
, operands
);
3429 emit_soft_tfmode_binop (code
, operands
);
3433 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3435 if (TARGET_HARD_QUAD
)
3436 emit_hard_tfmode_operation (code
, operands
);
3438 emit_soft_tfmode_unop (code
, operands
);
3442 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3444 if (TARGET_HARD_QUAD
)
3445 emit_hard_tfmode_operation (code
, operands
);
3447 emit_soft_tfmode_cvt (code
, operands
);
3450 /* Return nonzero if a branch/jump/call instruction will be emitting
3451 nop into its delay slot. */
3454 empty_delay_slot (rtx_insn
*insn
)
3458 /* If no previous instruction (should not happen), return true. */
3459 if (PREV_INSN (insn
) == NULL
)
3462 seq
= NEXT_INSN (PREV_INSN (insn
));
3463 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3469 /* Return nonzero if we should emit a nop after a cbcond instruction.
3470 The cbcond instruction does not have a delay slot, however there is
3471 a severe performance penalty if a control transfer appears right
3472 after a cbcond. Therefore we emit a nop when we detect this
3476 emit_cbcond_nop (rtx insn
)
3478 rtx next
= next_active_insn (insn
);
3483 if (NONJUMP_INSN_P (next
)
3484 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3485 next
= XVECEXP (PATTERN (next
), 0, 0);
3486 else if (CALL_P (next
)
3487 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3489 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3491 if (GET_CODE (delay
) == RETURN
)
3493 /* It's a sibling call. Do not emit the nop if we're going
3494 to emit something other than the jump itself as the first
3495 instruction of the sibcall sequence. */
3496 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3501 if (NONJUMP_INSN_P (next
))
3507 /* Return nonzero if TRIAL can go into the call delay slot. */
3510 eligible_for_call_delay (rtx_insn
*trial
)
3514 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3518 call __tls_get_addr, %tgd_call (foo)
3519 add %l7, %o0, %o0, %tgd_add (foo)
3520 while Sun as/ld does not. */
3521 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3524 pat
= PATTERN (trial
);
3526 /* We must reject tgd_add{32|64}, i.e.
3527 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3528 and tldm_add{32|64}, i.e.
3529 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3531 if (GET_CODE (pat
) == SET
3532 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3534 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3536 if (GET_CODE (unspec
) == UNSPEC
3537 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3538 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3545 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3546 instruction. RETURN_P is true if the v9 variant 'return' is to be
3547 considered in the test too.
3549 TRIAL must be a SET whose destination is a REG appropriate for the
3550 'restore' instruction or, if RETURN_P is true, for the 'return'
3554 eligible_for_restore_insn (rtx trial
, bool return_p
)
3556 rtx pat
= PATTERN (trial
);
3557 rtx src
= SET_SRC (pat
);
3558 bool src_is_freg
= false;
3561 /* Since we now can do moves between float and integer registers when
3562 VIS3 is enabled, we have to catch this case. We can allow such
3563 moves when doing a 'return' however. */
3565 if (GET_CODE (src_reg
) == SUBREG
)
3566 src_reg
= SUBREG_REG (src_reg
);
3567 if (GET_CODE (src_reg
) == REG
3568 && SPARC_FP_REG_P (REGNO (src_reg
)))
3571 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3572 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3573 && arith_operand (src
, GET_MODE (src
))
3577 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3579 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3582 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3583 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3584 && arith_double_operand (src
, GET_MODE (src
))
3586 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3588 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3589 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3592 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3593 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3596 /* If we have the 'return' instruction, anything that does not use
3597 local or output registers and can go into a delay slot wins. */
3598 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3601 /* The 'restore src1,src2,dest' pattern for SImode. */
3602 else if (GET_CODE (src
) == PLUS
3603 && register_operand (XEXP (src
, 0), SImode
)
3604 && arith_operand (XEXP (src
, 1), SImode
))
3607 /* The 'restore src1,src2,dest' pattern for DImode. */
3608 else if (GET_CODE (src
) == PLUS
3609 && register_operand (XEXP (src
, 0), DImode
)
3610 && arith_double_operand (XEXP (src
, 1), DImode
))
3613 /* The 'restore src1,%lo(src2),dest' pattern. */
3614 else if (GET_CODE (src
) == LO_SUM
3615 && ! TARGET_CM_MEDMID
3616 && ((register_operand (XEXP (src
, 0), SImode
)
3617 && immediate_operand (XEXP (src
, 1), SImode
))
3619 && register_operand (XEXP (src
, 0), DImode
)
3620 && immediate_operand (XEXP (src
, 1), DImode
))))
3623 /* The 'restore src,src,dest' pattern. */
3624 else if (GET_CODE (src
) == ASHIFT
3625 && (register_operand (XEXP (src
, 0), SImode
)
3626 || register_operand (XEXP (src
, 0), DImode
))
3627 && XEXP (src
, 1) == const1_rtx
)
3633 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3636 eligible_for_return_delay (rtx_insn
*trial
)
3641 /* If the function uses __builtin_eh_return, the eh_return machinery
3642 occupies the delay slot. */
3643 if (crtl
->calls_eh_return
)
3646 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3649 /* In the case of a leaf or flat function, anything can go into the slot. */
3650 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3653 if (!NONJUMP_INSN_P (trial
))
3656 pat
= PATTERN (trial
);
3657 if (GET_CODE (pat
) == PARALLEL
)
3663 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3665 rtx expr
= XVECEXP (pat
, 0, i
);
3666 if (GET_CODE (expr
) != SET
)
3668 if (GET_CODE (SET_DEST (expr
)) != REG
)
3670 regno
= REGNO (SET_DEST (expr
));
3671 if (regno
>= 8 && regno
< 24)
3674 return !epilogue_renumber (&pat
, 1);
3677 if (GET_CODE (pat
) != SET
)
3680 if (GET_CODE (SET_DEST (pat
)) != REG
)
3683 regno
= REGNO (SET_DEST (pat
));
3685 /* Otherwise, only operations which can be done in tandem with
3686 a `restore' or `return' insn can go into the delay slot. */
3687 if (regno
>= 8 && regno
< 24)
3690 /* If this instruction sets up floating point register and we have a return
3691 instruction, it can probably go in. But restore will not work
3693 if (! SPARC_INT_REG_P (regno
))
3694 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3696 return eligible_for_restore_insn (trial
, true);
3699 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3702 eligible_for_sibcall_delay (rtx_insn
*trial
)
3706 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3709 if (!NONJUMP_INSN_P (trial
))
3712 pat
= PATTERN (trial
);
3714 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3716 /* If the tail call is done using the call instruction,
3717 we have to restore %o7 in the delay slot. */
3718 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3721 /* %g1 is used to build the function address */
3722 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3728 if (GET_CODE (pat
) != SET
)
3731 /* Otherwise, only operations which can be done in tandem with
3732 a `restore' insn can go into the delay slot. */
3733 if (GET_CODE (SET_DEST (pat
)) != REG
3734 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3735 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3738 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3740 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3743 return eligible_for_restore_insn (trial
, false);
3746 /* Determine if it's legal to put X into the constant pool. This
3747 is not possible if X contains the address of a symbol that is
3748 not constant (TLS) or not known at final link time (PIC). */
3751 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
3753 switch (GET_CODE (x
))
3758 /* Accept all non-symbolic constants. */
3762 /* Labels are OK iff we are non-PIC. */
3763 return flag_pic
!= 0;
3766 /* 'Naked' TLS symbol references are never OK,
3767 non-TLS symbols are OK iff we are non-PIC. */
3768 if (SYMBOL_REF_TLS_MODEL (x
))
3771 return flag_pic
!= 0;
3774 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3777 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3778 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3786 /* Global Offset Table support. */
3787 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3788 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3790 /* Return the SYMBOL_REF for the Global Offset Table. */
3792 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3797 if (!sparc_got_symbol
)
3798 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3800 return sparc_got_symbol
;
3803 /* Ensure that we are not using patterns that are not OK with PIC. */
3813 op
= recog_data
.operand
[i
];
3814 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3815 && (GET_CODE (op
) != CONST
3816 || (GET_CODE (XEXP (op
, 0)) == MINUS
3817 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3818 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3825 /* Return true if X is an address which needs a temporary register when
3826 reloaded while generating PIC code. */
3829 pic_address_needs_scratch (rtx x
)
3831 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3832 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3833 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3834 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3835 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3841 /* Determine if a given RTX is a valid constant. We already know this
3842 satisfies CONSTANT_P. */
3845 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
3847 switch (GET_CODE (x
))
3851 if (sparc_tls_referenced_p (x
))
3856 if (GET_MODE (x
) == VOIDmode
)
3859 /* Floating point constants are generally not ok.
3860 The only exception is 0.0 and all-ones in VIS. */
3862 && SCALAR_FLOAT_MODE_P (mode
)
3863 && (const_zero_operand (x
, mode
)
3864 || const_all_ones_operand (x
, mode
)))
3870 /* Vector constants are generally not ok.
3871 The only exception is 0 or -1 in VIS. */
3873 && (const_zero_operand (x
, mode
)
3874 || const_all_ones_operand (x
, mode
)))
3886 /* Determine if a given RTX is a valid constant address. */
3889 constant_address_p (rtx x
)
3891 switch (GET_CODE (x
))
3899 if (flag_pic
&& pic_address_needs_scratch (x
))
3901 return sparc_legitimate_constant_p (Pmode
, x
);
3904 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3911 /* Nonzero if the constant value X is a legitimate general operand
3912 when generating PIC code. It is given that flag_pic is on and
3913 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3916 legitimate_pic_operand_p (rtx x
)
3918 if (pic_address_needs_scratch (x
))
3920 if (sparc_tls_referenced_p (x
))
3925 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3927 && INTVAL (X) >= -0x1000 \
3928 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
3930 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3932 && INTVAL (X) >= -0x1000 \
3933 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
3935 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3937 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3938 ordinarily. This changes a bit when generating PIC. */
3941 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
3943 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3945 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3947 else if (GET_CODE (addr
) == PLUS
)
3949 rs1
= XEXP (addr
, 0);
3950 rs2
= XEXP (addr
, 1);
3952 /* Canonicalize. REG comes first, if there are no regs,
3953 LO_SUM comes first. */
3955 && GET_CODE (rs1
) != SUBREG
3957 || GET_CODE (rs2
) == SUBREG
3958 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3960 rs1
= XEXP (addr
, 1);
3961 rs2
= XEXP (addr
, 0);
3965 && rs1
== pic_offset_table_rtx
3967 && GET_CODE (rs2
) != SUBREG
3968 && GET_CODE (rs2
) != LO_SUM
3969 && GET_CODE (rs2
) != MEM
3970 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3971 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3972 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3974 || GET_CODE (rs1
) == SUBREG
)
3975 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3980 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3981 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3983 /* We prohibit REG + REG for TFmode when there are no quad move insns
3984 and we consequently need to split. We do this because REG+REG
3985 is not an offsettable address. If we get the situation in reload
3986 where source and destination of a movtf pattern are both MEMs with
3987 REG+REG address, then only one of them gets converted to an
3988 offsettable address. */
3990 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3993 /* Likewise for TImode, but in all cases. */
3997 /* We prohibit REG + REG on ARCH32 if not optimizing for
3998 DFmode/DImode because then mem_min_alignment is likely to be zero
3999 after reload and the forced split would lack a matching splitter
4001 if (TARGET_ARCH32
&& !optimize
4002 && (mode
== DFmode
|| mode
== DImode
))
4005 else if (USE_AS_OFFSETABLE_LO10
4006 && GET_CODE (rs1
) == LO_SUM
4008 && ! TARGET_CM_MEDMID
4009 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4012 imm1
= XEXP (rs1
, 1);
4013 rs1
= XEXP (rs1
, 0);
4014 if (!CONSTANT_P (imm1
)
4015 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4019 else if (GET_CODE (addr
) == LO_SUM
)
4021 rs1
= XEXP (addr
, 0);
4022 imm1
= XEXP (addr
, 1);
4024 if (!CONSTANT_P (imm1
)
4025 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4028 /* We can't allow TFmode in 32-bit mode, because an offset greater
4029 than the alignment (8) may cause the LO_SUM to overflow. */
4030 if (mode
== TFmode
&& TARGET_ARCH32
)
4033 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4038 if (GET_CODE (rs1
) == SUBREG
)
4039 rs1
= SUBREG_REG (rs1
);
4045 if (GET_CODE (rs2
) == SUBREG
)
4046 rs2
= SUBREG_REG (rs2
);
4053 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4054 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4059 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4060 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4061 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4063 && (! SPARC_INT_REG_P (REGNO (rs2
))
4064 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4065 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4071 /* Return the SYMBOL_REF for the tls_get_addr function. */
4073 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4076 sparc_tls_get_addr (void)
4078 if (!sparc_tls_symbol
)
4079 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4081 return sparc_tls_symbol
;
4084 /* Return the Global Offset Table to be used in TLS mode. */
4087 sparc_tls_got (void)
4089 /* In PIC mode, this is just the PIC offset table. */
4092 crtl
->uses_pic_offset_table
= 1;
4093 return pic_offset_table_rtx
;
4096 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4097 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4098 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4100 load_got_register ();
4101 return global_offset_table_rtx
;
4104 /* In all other cases, we load a new pseudo with the GOT symbol. */
4105 return copy_to_reg (sparc_got ());
4108 /* Return true if X contains a thread-local symbol. */
4111 sparc_tls_referenced_p (rtx x
)
4113 if (!TARGET_HAVE_TLS
)
4116 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4117 x
= XEXP (XEXP (x
, 0), 0);
4119 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4122 /* That's all we handle in sparc_legitimize_tls_address for now. */
4126 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4127 this (thread-local) address. */
4130 sparc_legitimize_tls_address (rtx addr
)
4132 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4135 gcc_assert (can_create_pseudo_p ());
4137 if (GET_CODE (addr
) == SYMBOL_REF
)
4138 switch (SYMBOL_REF_TLS_MODEL (addr
))
4140 case TLS_MODEL_GLOBAL_DYNAMIC
:
4142 temp1
= gen_reg_rtx (SImode
);
4143 temp2
= gen_reg_rtx (SImode
);
4144 ret
= gen_reg_rtx (Pmode
);
4145 o0
= gen_rtx_REG (Pmode
, 8);
4146 got
= sparc_tls_got ();
4147 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4148 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4151 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4152 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4157 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4158 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4161 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4162 insn
= get_insns ();
4164 emit_libcall_block (insn
, ret
, o0
, addr
);
4167 case TLS_MODEL_LOCAL_DYNAMIC
:
4169 temp1
= gen_reg_rtx (SImode
);
4170 temp2
= gen_reg_rtx (SImode
);
4171 temp3
= gen_reg_rtx (Pmode
);
4172 ret
= gen_reg_rtx (Pmode
);
4173 o0
= gen_rtx_REG (Pmode
, 8);
4174 got
= sparc_tls_got ();
4175 emit_insn (gen_tldm_hi22 (temp1
));
4176 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4179 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4180 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4185 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4186 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4189 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4190 insn
= get_insns ();
4192 emit_libcall_block (insn
, temp3
, o0
,
4193 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4194 UNSPEC_TLSLD_BASE
));
4195 temp1
= gen_reg_rtx (SImode
);
4196 temp2
= gen_reg_rtx (SImode
);
4197 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4198 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4200 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4202 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4205 case TLS_MODEL_INITIAL_EXEC
:
4206 temp1
= gen_reg_rtx (SImode
);
4207 temp2
= gen_reg_rtx (SImode
);
4208 temp3
= gen_reg_rtx (Pmode
);
4209 got
= sparc_tls_got ();
4210 emit_insn (gen_tie_hi22 (temp1
, addr
));
4211 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4213 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4215 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4218 ret
= gen_reg_rtx (Pmode
);
4220 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4223 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4227 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4230 case TLS_MODEL_LOCAL_EXEC
:
4231 temp1
= gen_reg_rtx (Pmode
);
4232 temp2
= gen_reg_rtx (Pmode
);
4235 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4236 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4240 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4241 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4243 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4250 else if (GET_CODE (addr
) == CONST
)
4254 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4256 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4257 offset
= XEXP (XEXP (addr
, 0), 1);
4259 base
= force_operand (base
, NULL_RTX
);
4260 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4261 offset
= force_reg (Pmode
, offset
);
4262 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4266 gcc_unreachable (); /* for now ... */
4271 /* Legitimize PIC addresses. If the address is already position-independent,
4272 we return ORIG. Newly generated position-independent addresses go into a
4273 reg. This is REG if nonzero, otherwise we allocate register(s) as
4277 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4279 bool gotdata_op
= false;
4281 if (GET_CODE (orig
) == SYMBOL_REF
4282 /* See the comment in sparc_expand_move. */
4283 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4285 rtx pic_ref
, address
;
4290 gcc_assert (can_create_pseudo_p ());
4291 reg
= gen_reg_rtx (Pmode
);
4296 /* If not during reload, allocate another temp reg here for loading
4297 in the address, so that these instructions can be optimized
4299 rtx temp_reg
= (! can_create_pseudo_p ()
4300 ? reg
: gen_reg_rtx (Pmode
));
4302 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4303 won't get confused into thinking that these two instructions
4304 are loading in the true address of the symbol. If in the
4305 future a PIC rtx exists, that should be used instead. */
4308 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4309 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4313 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4314 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4322 crtl
->uses_pic_offset_table
= 1;
4326 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4327 pic_offset_table_rtx
,
4330 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4331 pic_offset_table_rtx
,
4337 = gen_const_mem (Pmode
,
4338 gen_rtx_PLUS (Pmode
,
4339 pic_offset_table_rtx
, address
));
4340 insn
= emit_move_insn (reg
, pic_ref
);
4343 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4345 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4348 else if (GET_CODE (orig
) == CONST
)
4352 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4353 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4358 gcc_assert (can_create_pseudo_p ());
4359 reg
= gen_reg_rtx (Pmode
);
4362 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4363 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4364 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4365 base
== reg
? NULL_RTX
: reg
);
4367 if (GET_CODE (offset
) == CONST_INT
)
4369 if (SMALL_INT (offset
))
4370 return plus_constant (Pmode
, base
, INTVAL (offset
));
4371 else if (can_create_pseudo_p ())
4372 offset
= force_reg (Pmode
, offset
);
4374 /* If we reach here, then something is seriously wrong. */
4377 return gen_rtx_PLUS (Pmode
, base
, offset
);
4379 else if (GET_CODE (orig
) == LABEL_REF
)
4380 /* ??? We ought to be checking that the register is live instead, in case
4381 it is eliminated. */
4382 crtl
->uses_pic_offset_table
= 1;
4387 /* Try machine-dependent ways of modifying an illegitimate address X
4388 to be legitimate. If we find one, return the new, valid address.
4390 OLDX is the address as it was before break_out_memory_refs was called.
4391 In some cases it is useful to look at this to decide what needs to be done.
4393 MODE is the mode of the operand pointed to by X.
4395 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4398 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4403 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4404 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4405 force_operand (XEXP (x
, 0), NULL_RTX
));
4406 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4407 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4408 force_operand (XEXP (x
, 1), NULL_RTX
));
4409 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4410 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4412 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4413 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4414 force_operand (XEXP (x
, 1), NULL_RTX
));
4416 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4419 if (sparc_tls_referenced_p (x
))
4420 x
= sparc_legitimize_tls_address (x
);
4422 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4423 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4424 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4425 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4426 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4427 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4428 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4429 else if (GET_CODE (x
) == SYMBOL_REF
4430 || GET_CODE (x
) == CONST
4431 || GET_CODE (x
) == LABEL_REF
)
4432 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4437 /* Delegitimize an address that was legitimized by the above function. */
4440 sparc_delegitimize_address (rtx x
)
4442 x
= delegitimize_mem_from_attrs (x
);
4444 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4445 switch (XINT (XEXP (x
, 1), 1))
4447 case UNSPEC_MOVE_PIC
:
4449 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4450 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4456 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4457 if (GET_CODE (x
) == MINUS
4458 && REG_P (XEXP (x
, 0))
4459 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4460 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4461 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4462 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4464 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4465 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4471 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4472 replace the input X, or the original X if no replacement is called for.
4473 The output parameter *WIN is 1 if the calling macro should goto WIN,
4476 For SPARC, we wish to handle addresses by splitting them into
4477 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4478 This cuts the number of extra insns by one.
4480 Do nothing when generating PIC code and the address is a symbolic
4481 operand or requires a scratch register. */
4484 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4485 int opnum
, int type
,
4486 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4488 /* Decompose SImode constants into HIGH+LO_SUM. */
4490 && (mode
!= TFmode
|| TARGET_ARCH64
)
4491 && GET_MODE (x
) == SImode
4492 && GET_CODE (x
) != LO_SUM
4493 && GET_CODE (x
) != HIGH
4494 && sparc_cmodel
<= CM_MEDLOW
4496 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4498 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4499 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4500 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4501 opnum
, (enum reload_type
)type
);
4506 /* We have to recognize what we have already generated above. */
4507 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4509 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4510 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4511 opnum
, (enum reload_type
)type
);
4520 /* Return true if ADDR (a legitimate address expression)
4521 has an effect that depends on the machine mode it is used for.
4527 is not equivalent to
4529 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4531 because [%l7+a+1] is interpreted as the address of (a+1). */
4535 sparc_mode_dependent_address_p (const_rtx addr
,
4536 addr_space_t as ATTRIBUTE_UNUSED
)
4538 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4540 rtx op0
= XEXP (addr
, 0);
4541 rtx op1
= XEXP (addr
, 1);
4542 if (op0
== pic_offset_table_rtx
4543 && symbolic_operand (op1
, VOIDmode
))
4550 #ifdef HAVE_GAS_HIDDEN
4551 # define USE_HIDDEN_LINKONCE 1
4553 # define USE_HIDDEN_LINKONCE 0
4557 get_pc_thunk_name (char name
[32], unsigned int regno
)
4559 const char *reg_name
= reg_names
[regno
];
4561 /* Skip the leading '%' as that cannot be used in a
4565 if (USE_HIDDEN_LINKONCE
)
4566 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4568 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4571 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4574 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4576 int orig_flag_pic
= flag_pic
;
4579 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4582 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4584 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4585 flag_pic
= orig_flag_pic
;
4590 /* Emit code to load the GOT register. */
4593 load_got_register (void)
4595 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4596 if (!global_offset_table_rtx
)
4597 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4599 if (TARGET_VXWORKS_RTP
)
4600 emit_insn (gen_vxworks_load_got ());
4603 /* The GOT symbol is subject to a PC-relative relocation so we need a
4604 helper function to add the PC value and thus get the final value. */
4605 if (!got_helper_rtx
)
4608 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4609 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4612 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4614 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4617 /* Need to emit this whether or not we obey regdecls,
4618 since setjmp/longjmp can cause life info to screw up.
4619 ??? In the case where we don't obey regdecls, this is not sufficient
4620 since we may not fall out the bottom. */
4621 emit_use (global_offset_table_rtx
);
4624 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4625 address of the call target. */
4628 sparc_emit_call_insn (rtx pat
, rtx addr
)
4632 insn
= emit_call_insn (pat
);
4634 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4635 if (TARGET_VXWORKS_RTP
4637 && GET_CODE (addr
) == SYMBOL_REF
4638 && (SYMBOL_REF_DECL (addr
)
4639 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4640 : !SYMBOL_REF_LOCAL_P (addr
)))
4642 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4643 crtl
->uses_pic_offset_table
= 1;
4647 /* Return 1 if RTX is a MEM which is known to be aligned to at
4648 least a DESIRED byte boundary. */
4651 mem_min_alignment (rtx mem
, int desired
)
4653 rtx addr
, base
, offset
;
4655 /* If it's not a MEM we can't accept it. */
4656 if (GET_CODE (mem
) != MEM
)
4660 if (!TARGET_UNALIGNED_DOUBLES
4661 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4664 /* ??? The rest of the function predates MEM_ALIGN so
4665 there is probably a bit of redundancy. */
4666 addr
= XEXP (mem
, 0);
4667 base
= offset
= NULL_RTX
;
4668 if (GET_CODE (addr
) == PLUS
)
4670 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4672 base
= XEXP (addr
, 0);
4674 /* What we are saying here is that if the base
4675 REG is aligned properly, the compiler will make
4676 sure any REG based index upon it will be so
4678 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4679 offset
= XEXP (addr
, 1);
4681 offset
= const0_rtx
;
4684 else if (GET_CODE (addr
) == REG
)
4687 offset
= const0_rtx
;
4690 if (base
!= NULL_RTX
)
4692 int regno
= REGNO (base
);
4694 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4696 /* Check if the compiler has recorded some information
4697 about the alignment of the base REG. If reload has
4698 completed, we already matched with proper alignments.
4699 If not running global_alloc, reload might give us
4700 unaligned pointer to local stack though. */
4702 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4703 || (optimize
&& reload_completed
))
4704 && (INTVAL (offset
) & (desired
- 1)) == 0)
4709 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4713 else if (! TARGET_UNALIGNED_DOUBLES
4714 || CONSTANT_P (addr
)
4715 || GET_CODE (addr
) == LO_SUM
)
4717 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4718 is true, in which case we can only assume that an access is aligned if
4719 it is to a constant address, or the address involves a LO_SUM. */
4723 /* An obviously unaligned address. */
4728 /* Vectors to keep interesting information about registers where it can easily
4729 be got. We used to use the actual mode value as the bit number, but there
4730 are more than 32 modes now. Instead we use two tables: one indexed by
4731 hard register number, and one indexed by mode. */
4733 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4734 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4735 mapped into one sparc_mode_class mode. */
4737 enum sparc_mode_class
{
4738 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4739 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4743 /* Modes for single-word and smaller quantities. */
4745 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4747 /* Modes for double-word and smaller quantities. */
4748 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4750 /* Modes for quad-word and smaller quantities. */
4751 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4753 /* Modes for 8-word and smaller quantities. */
4754 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4756 /* Modes for single-float quantities. */
4757 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4759 /* Modes for double-float and smaller quantities. */
4760 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4762 /* Modes for quad-float and smaller quantities. */
4763 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4765 /* Modes for quad-float pairs and smaller quantities. */
4766 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4768 /* Modes for double-float only quantities. */
4769 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4771 /* Modes for quad-float and double-float only quantities. */
4772 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4774 /* Modes for quad-float pairs and double-float only quantities. */
4775 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4777 /* Modes for condition codes. */
4778 #define CC_MODES (1 << (int) CC_MODE)
4779 #define CCFP_MODES (1 << (int) CCFP_MODE)
4781 /* Value is 1 if register/mode pair is acceptable on sparc.
4782 The funny mixture of D and T modes is because integer operations
4783 do not specially operate on tetra quantities, so non-quad-aligned
4784 registers can hold quadword quantities (except %o4 and %i4 because
4785 they cross fixed registers). */
4787 /* This points to either the 32 bit or the 64 bit version. */
4788 const int *hard_regno_mode_classes
;
4790 static const int hard_32bit_mode_classes
[] = {
4791 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4792 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4793 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4794 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4796 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4797 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4798 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4799 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4801 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4802 and none can hold SFmode/SImode values. */
4803 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4804 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4805 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4806 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4809 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4811 /* %icc, %sfp, %gsr */
4812 CC_MODES
, 0, D_MODES
4815 static const int hard_64bit_mode_classes
[] = {
4816 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4817 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4818 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4819 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4821 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4822 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4823 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4824 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4826 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4827 and none can hold SFmode/SImode values. */
4828 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4829 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4830 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4831 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4834 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4836 /* %icc, %sfp, %gsr */
4837 CC_MODES
, 0, D_MODES
4840 int sparc_mode_class
[NUM_MACHINE_MODES
];
4842 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4845 sparc_init_modes (void)
4849 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4851 machine_mode m
= (machine_mode
) i
;
4852 unsigned int size
= GET_MODE_SIZE (m
);
4854 switch (GET_MODE_CLASS (m
))
4857 case MODE_PARTIAL_INT
:
4858 case MODE_COMPLEX_INT
:
4860 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
4862 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4864 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4865 else if (size
== 16)
4866 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4867 else if (size
== 32)
4868 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4870 sparc_mode_class
[i
] = 0;
4872 case MODE_VECTOR_INT
:
4874 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4876 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4878 sparc_mode_class
[i
] = 0;
4881 case MODE_COMPLEX_FLOAT
:
4883 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4885 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4886 else if (size
== 16)
4887 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4888 else if (size
== 32)
4889 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4891 sparc_mode_class
[i
] = 0;
4894 if (m
== CCFPmode
|| m
== CCFPEmode
)
4895 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4897 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4900 sparc_mode_class
[i
] = 0;
4906 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4908 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4910 /* Initialize the array used by REGNO_REG_CLASS. */
4911 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4913 if (i
< 16 && TARGET_V8PLUS
)
4914 sparc_regno_reg_class
[i
] = I64_REGS
;
4915 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4916 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4918 sparc_regno_reg_class
[i
] = FP_REGS
;
4920 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4922 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4924 sparc_regno_reg_class
[i
] = NO_REGS
;
4928 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4931 save_global_or_fp_reg_p (unsigned int regno
,
4932 int leaf_function ATTRIBUTE_UNUSED
)
4934 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4937 /* Return whether the return address register (%i7) is needed. */
4940 return_addr_reg_needed_p (int leaf_function
)
4942 /* If it is live, for example because of __builtin_return_address (0). */
4943 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4946 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4948 /* Loading the GOT register clobbers %o7. */
4949 || crtl
->uses_pic_offset_table
4950 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4956 /* Return whether REGNO, a local or in register, must be saved/restored. */
4959 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4961 /* General case: call-saved registers live at some point. */
4962 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4965 /* Frame pointer register (%fp) if needed. */
4966 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4969 /* Return address register (%i7) if needed. */
4970 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4973 /* GOT register (%l7) if needed. */
4974 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4977 /* If the function accesses prior frames, the frame pointer and the return
4978 address of the previous frame must be saved on the stack. */
4979 if (crtl
->accesses_prior_frames
4980 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4986 /* Compute the frame size required by the function. This function is called
4987 during the reload pass and also by sparc_expand_prologue. */
4990 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4992 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4993 int args_size
, n_global_fp_regs
= 0;
4994 bool save_local_in_regs_p
= false;
4997 /* If the function allocates dynamic stack space, the dynamic offset is
4998 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4999 if (leaf_function
&& !cfun
->calls_alloca
)
5002 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5004 /* Calculate space needed for global registers. */
5006 for (i
= 0; i
< 8; i
++)
5007 if (save_global_or_fp_reg_p (i
, 0))
5008 n_global_fp_regs
+= 2;
5010 for (i
= 0; i
< 8; i
+= 2)
5011 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5012 n_global_fp_regs
+= 2;
5014 /* In the flat window model, find out which local and in registers need to
5015 be saved. We don't reserve space in the current frame for them as they
5016 will be spilled into the register window save area of the caller's frame.
5017 However, as soon as we use this register window save area, we must create
5018 that of the current frame to make it the live one. */
5020 for (i
= 16; i
< 32; i
++)
5021 if (save_local_or_in_reg_p (i
, leaf_function
))
5023 save_local_in_regs_p
= true;
5027 /* Calculate space needed for FP registers. */
5028 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5029 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5030 n_global_fp_regs
+= 2;
5033 && n_global_fp_regs
== 0
5035 && !save_local_in_regs_p
)
5036 frame_size
= apparent_frame_size
= 0;
5039 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5040 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
5041 apparent_frame_size
+= n_global_fp_regs
* 4;
5043 /* We need to add the size of the outgoing argument area. */
5044 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
5046 /* And that of the register window save area. */
5047 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5049 /* Finally, bump to the appropriate alignment. */
5050 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5053 /* Set up values for use in prologue and epilogue. */
5054 sparc_frame_size
= frame_size
;
5055 sparc_apparent_frame_size
= apparent_frame_size
;
5056 sparc_n_global_fp_regs
= n_global_fp_regs
;
5057 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5062 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5065 sparc_initial_elimination_offset (int to
)
5069 if (to
== STACK_POINTER_REGNUM
)
5070 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5074 offset
+= SPARC_STACK_BIAS
;
5078 /* Output any necessary .register pseudo-ops. */
5081 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5083 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5089 /* Check if %g[2367] were used without
5090 .register being printed for them already. */
5091 for (i
= 2; i
< 8; i
++)
5093 if (df_regs_ever_live_p (i
)
5094 && ! sparc_hard_reg_printed
[i
])
5096 sparc_hard_reg_printed
[i
] = 1;
5097 /* %g7 is used as TLS base register, use #ignore
5098 for it instead of #scratch. */
5099 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5100 i
== 7 ? "ignore" : "scratch");
5107 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5109 #if PROBE_INTERVAL > 4096
5110 #error Cannot use indexed addressing mode for stack probing
5113 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5114 inclusive. These are offsets from the current stack pointer.
5116 Note that we don't use the REG+REG addressing mode for the probes because
5117 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5118 so the advantages of having a single code win here. */
5121 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5123 rtx g1
= gen_rtx_REG (Pmode
, 1);
5125 /* See if we have a constant small number of probes to generate. If so,
5126 that's the easy case. */
5127 if (size
<= PROBE_INTERVAL
)
5129 emit_move_insn (g1
, GEN_INT (first
));
5130 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5131 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5132 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5135 /* The run-time loop is made up of 10 insns in the generic case while the
5136 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5137 else if (size
<= 5 * PROBE_INTERVAL
)
5141 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5142 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5143 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5144 emit_stack_probe (g1
);
5146 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5147 it exceeds SIZE. If only two probes are needed, this will not
5148 generate any code. Then probe at FIRST + SIZE. */
5149 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5151 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5152 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5153 emit_stack_probe (g1
);
5156 emit_stack_probe (plus_constant (Pmode
, g1
,
5157 (i
- PROBE_INTERVAL
) - size
));
5160 /* Otherwise, do the same as above, but in a loop. Note that we must be
5161 extra careful with variables wrapping around because we might be at
5162 the very top (or the very bottom) of the address space and we have
5163 to be able to handle this case properly; in particular, we use an
5164 equality test for the loop condition. */
5167 HOST_WIDE_INT rounded_size
;
5168 rtx g4
= gen_rtx_REG (Pmode
, 4);
5170 emit_move_insn (g1
, GEN_INT (first
));
5173 /* Step 1: round SIZE to the previous multiple of the interval. */
5175 rounded_size
= size
& -PROBE_INTERVAL
;
5176 emit_move_insn (g4
, GEN_INT (rounded_size
));
5179 /* Step 2: compute initial and final value of the loop counter. */
5181 /* TEST_ADDR = SP + FIRST. */
5182 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5183 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5185 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5186 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5191 while (TEST_ADDR != LAST_ADDR)
5193 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5197 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5198 until it is equal to ROUNDED_SIZE. */
5201 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5203 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5206 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5207 that SIZE is equal to ROUNDED_SIZE. */
5209 if (size
!= rounded_size
)
5210 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5213 /* Make sure nothing is scheduled before we are done. */
5214 emit_insn (gen_blockage ());
5217 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5218 absolute addresses. */
5221 output_probe_stack_range (rtx reg1
, rtx reg2
)
5223 static int labelno
= 0;
5224 char loop_lab
[32], end_lab
[32];
5227 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
5228 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
5230 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5232 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
5235 output_asm_insn ("cmp\t%0, %1", xops
);
5237 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
5239 fputs ("\tbe\t", asm_out_file
);
5240 assemble_name_raw (asm_out_file
, end_lab
);
5241 fputc ('\n', asm_out_file
);
5243 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5244 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5245 output_asm_insn (" add\t%0, %1, %0", xops
);
5247 /* Probe at TEST_ADDR and branch. */
5249 fputs ("\tba,pt\t%xcc,", asm_out_file
);
5251 fputs ("\tba\t", asm_out_file
);
5252 assemble_name_raw (asm_out_file
, loop_lab
);
5253 fputc ('\n', asm_out_file
);
5254 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5255 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5257 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
5262 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5263 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5264 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5265 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5266 the action to be performed if it returns false. Return the new offset. */
5268 typedef bool (*sorr_pred_t
) (unsigned int, int);
5269 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5272 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5273 int offset
, int leaf_function
, sorr_pred_t save_p
,
5274 sorr_act_t action_true
, sorr_act_t action_false
)
5280 if (TARGET_ARCH64
&& high
<= 32)
5284 for (i
= low
; i
< high
; i
++)
5286 if (save_p (i
, leaf_function
))
5288 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5290 if (action_true
== SORR_SAVE
)
5292 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5293 RTX_FRAME_RELATED_P (insn
) = 1;
5295 else /* action_true == SORR_RESTORE */
5297 /* The frame pointer must be restored last since its old
5298 value may be used as base address for the frame. This
5299 is problematic in 64-bit mode only because of the lack
5300 of double-word load instruction. */
5301 if (i
== HARD_FRAME_POINTER_REGNUM
)
5304 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5308 else if (action_false
== SORR_ADVANCE
)
5314 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5315 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5320 for (i
= low
; i
< high
; i
+= 2)
5322 bool reg0
= save_p (i
, leaf_function
);
5323 bool reg1
= save_p (i
+ 1, leaf_function
);
5329 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5334 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5339 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5345 if (action_false
== SORR_ADVANCE
)
5350 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5351 if (action_true
== SORR_SAVE
)
5353 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5354 RTX_FRAME_RELATED_P (insn
) = 1;
5358 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5360 set1
= gen_rtx_SET (VOIDmode
, mem
,
5361 gen_rtx_REG (SImode
, regno
));
5362 RTX_FRAME_RELATED_P (set1
) = 1;
5364 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5366 set2
= gen_rtx_SET (VOIDmode
, mem
,
5367 gen_rtx_REG (SImode
, regno
+ 1));
5368 RTX_FRAME_RELATED_P (set2
) = 1;
5369 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5370 gen_rtx_PARALLEL (VOIDmode
,
5371 gen_rtvec (2, set1
, set2
)));
5374 else /* action_true == SORR_RESTORE */
5375 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5377 /* Always preserve double-word alignment. */
5378 offset
= (offset
+ 8) & -8;
5385 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5388 emit_adjust_base_to_offset (rtx base
, int offset
)
5390 /* ??? This might be optimized a little as %g1 might already have a
5391 value close enough that a single add insn will do. */
5392 /* ??? Although, all of this is probably only a temporary fix because
5393 if %g1 can hold a function result, then sparc_expand_epilogue will
5394 lose (the result will be clobbered). */
5395 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5396 emit_move_insn (new_base
, GEN_INT (offset
));
5397 emit_insn (gen_rtx_SET (VOIDmode
,
5398 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5402 /* Emit code to save/restore call-saved global and FP registers. */
5405 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5407 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5409 base
= emit_adjust_base_to_offset (base
, offset
);
5414 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5415 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5416 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5417 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5420 /* Emit code to save/restore call-saved local and in registers. */
5423 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5425 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5427 base
= emit_adjust_base_to_offset (base
, offset
);
5431 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5432 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5435 /* Emit a window_save insn. */
5438 emit_window_save (rtx increment
)
5440 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5441 RTX_FRAME_RELATED_P (insn
) = 1;
5443 /* The incoming return address (%o7) is saved in %i7. */
5444 add_reg_note (insn
, REG_CFA_REGISTER
,
5445 gen_rtx_SET (VOIDmode
,
5446 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5448 INCOMING_RETURN_ADDR_REGNUM
)));
5450 /* The window save event. */
5451 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5453 /* The CFA is %fp, the hard frame pointer. */
5454 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5455 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5456 INCOMING_FRAME_SP_OFFSET
));
5461 /* Generate an increment for the stack pointer. */
5464 gen_stack_pointer_inc (rtx increment
)
5466 return gen_rtx_SET (VOIDmode
,
5468 gen_rtx_PLUS (Pmode
,
5473 /* Expand the function prologue. The prologue is responsible for reserving
5474 storage for the frame, saving the call-saved registers and loading the
5475 GOT register if needed. */
5478 sparc_expand_prologue (void)
5483 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5484 on the final value of the flag means deferring the prologue/epilogue
5485 expansion until just before the second scheduling pass, which is too
5486 late to emit multiple epilogues or return insns.
5488 Of course we are making the assumption that the value of the flag
5489 will not change between now and its final value. Of the three parts
5490 of the formula, only the last one can reasonably vary. Let's take a
5491 closer look, after assuming that the first two ones are set to true
5492 (otherwise the last value is effectively silenced).
5494 If only_leaf_regs_used returns false, the global predicate will also
5495 be false so the actual frame size calculated below will be positive.
5496 As a consequence, the save_register_window insn will be emitted in
5497 the instruction stream; now this insn explicitly references %fp
5498 which is not a leaf register so only_leaf_regs_used will always
5499 return false subsequently.
5501 If only_leaf_regs_used returns true, we hope that the subsequent
5502 optimization passes won't cause non-leaf registers to pop up. For
5503 example, the regrename pass has special provisions to not rename to
5504 non-leaf registers in a leaf function. */
5505 sparc_leaf_function_p
5506 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5508 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5510 if (flag_stack_usage_info
)
5511 current_function_static_stack_size
= size
;
5513 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5515 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5517 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5518 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5519 size
- STACK_CHECK_PROTECT
);
5522 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5527 else if (sparc_leaf_function_p
)
5529 rtx size_int_rtx
= GEN_INT (-size
);
5532 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5533 else if (size
<= 8192)
5535 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5536 RTX_FRAME_RELATED_P (insn
) = 1;
5538 /* %sp is still the CFA register. */
5539 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5543 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5544 emit_move_insn (size_rtx
, size_int_rtx
);
5545 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5546 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5547 gen_stack_pointer_inc (size_int_rtx
));
5550 RTX_FRAME_RELATED_P (insn
) = 1;
5554 rtx size_int_rtx
= GEN_INT (-size
);
5557 emit_window_save (size_int_rtx
);
5558 else if (size
<= 8192)
5560 emit_window_save (GEN_INT (-4096));
5562 /* %sp is not the CFA register anymore. */
5563 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5565 /* Make sure no %fp-based store is issued until after the frame is
5566 established. The offset between the frame pointer and the stack
5567 pointer is calculated relative to the value of the stack pointer
5568 at the end of the function prologue, and moving instructions that
5569 access the stack via the frame pointer between the instructions
5570 that decrement the stack pointer could result in accessing the
5571 register window save area, which is volatile. */
5572 emit_insn (gen_frame_blockage ());
5576 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5577 emit_move_insn (size_rtx
, size_int_rtx
);
5578 emit_window_save (size_rtx
);
5582 if (sparc_leaf_function_p
)
5584 sparc_frame_base_reg
= stack_pointer_rtx
;
5585 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5589 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5590 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5593 if (sparc_n_global_fp_regs
> 0)
5594 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5595 sparc_frame_base_offset
5596 - sparc_apparent_frame_size
,
5599 /* Load the GOT register if needed. */
5600 if (crtl
->uses_pic_offset_table
)
5601 load_got_register ();
5603 /* Advertise that the data calculated just above are now valid. */
5604 sparc_prologue_data_valid_p
= true;
5607 /* Expand the function prologue. The prologue is responsible for reserving
5608 storage for the frame, saving the call-saved registers and loading the
5609 GOT register if needed. */
5612 sparc_flat_expand_prologue (void)
5617 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5619 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5621 if (flag_stack_usage_info
)
5622 current_function_static_stack_size
= size
;
5624 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5626 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5628 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5629 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5630 size
- STACK_CHECK_PROTECT
);
5633 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5636 if (sparc_save_local_in_regs_p
)
5637 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5644 rtx size_int_rtx
, size_rtx
;
5646 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5648 /* We establish the frame (i.e. decrement the stack pointer) first, even
5649 if we use a frame pointer, because we cannot clobber any call-saved
5650 registers, including the frame pointer, if we haven't created a new
5651 register save area, for the sake of compatibility with the ABI. */
5653 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5654 else if (size
<= 8192 && !frame_pointer_needed
)
5656 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5657 RTX_FRAME_RELATED_P (insn
) = 1;
5658 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5662 size_rtx
= gen_rtx_REG (Pmode
, 1);
5663 emit_move_insn (size_rtx
, size_int_rtx
);
5664 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5665 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5666 gen_stack_pointer_inc (size_int_rtx
));
5668 RTX_FRAME_RELATED_P (insn
) = 1;
5670 /* Ensure nothing is scheduled until after the frame is established. */
5671 emit_insn (gen_blockage ());
5673 if (frame_pointer_needed
)
5675 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5676 gen_rtx_MINUS (Pmode
,
5679 RTX_FRAME_RELATED_P (insn
) = 1;
5681 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5682 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5683 plus_constant (Pmode
, stack_pointer_rtx
,
5687 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5689 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5690 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5692 insn
= emit_move_insn (i7
, o7
);
5693 RTX_FRAME_RELATED_P (insn
) = 1;
5695 add_reg_note (insn
, REG_CFA_REGISTER
,
5696 gen_rtx_SET (VOIDmode
, i7
, o7
));
5698 /* Prevent this instruction from ever being considered dead,
5699 even if this function has no epilogue. */
5704 if (frame_pointer_needed
)
5706 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5707 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5711 sparc_frame_base_reg
= stack_pointer_rtx
;
5712 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5715 if (sparc_n_global_fp_regs
> 0)
5716 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5717 sparc_frame_base_offset
5718 - sparc_apparent_frame_size
,
5721 /* Load the GOT register if needed. */
5722 if (crtl
->uses_pic_offset_table
)
5723 load_got_register ();
5725 /* Advertise that the data calculated just above are now valid. */
5726 sparc_prologue_data_valid_p
= true;
5729 /* This function generates the assembly code for function entry, which boils
5730 down to emitting the necessary .register directives. */
5733 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5735 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5737 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5739 sparc_output_scratch_registers (file
);
5742 /* Expand the function epilogue, either normal or part of a sibcall.
5743 We emit all the instructions except the return or the call. */
5746 sparc_expand_epilogue (bool for_eh
)
5748 HOST_WIDE_INT size
= sparc_frame_size
;
5750 if (sparc_n_global_fp_regs
> 0)
5751 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5752 sparc_frame_base_offset
5753 - sparc_apparent_frame_size
,
5756 if (size
== 0 || for_eh
)
5758 else if (sparc_leaf_function_p
)
5761 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5762 else if (size
<= 8192)
5764 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5765 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5769 rtx reg
= gen_rtx_REG (Pmode
, 1);
5770 emit_move_insn (reg
, GEN_INT (size
));
5771 emit_insn (gen_stack_pointer_inc (reg
));
5776 /* Expand the function epilogue, either normal or part of a sibcall.
5777 We emit all the instructions except the return or the call. */
5780 sparc_flat_expand_epilogue (bool for_eh
)
5782 HOST_WIDE_INT size
= sparc_frame_size
;
5784 if (sparc_n_global_fp_regs
> 0)
5785 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5786 sparc_frame_base_offset
5787 - sparc_apparent_frame_size
,
5790 /* If we have a frame pointer, we'll need both to restore it before the
5791 frame is destroyed and use its current value in destroying the frame.
5792 Since we don't have an atomic way to do that in the flat window model,
5793 we save the current value into a temporary register (%g1). */
5794 if (frame_pointer_needed
&& !for_eh
)
5795 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5797 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5798 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5799 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5801 if (sparc_save_local_in_regs_p
)
5802 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5803 sparc_frame_base_offset
,
5806 if (size
== 0 || for_eh
)
5808 else if (frame_pointer_needed
)
5810 /* Make sure the frame is destroyed after everything else is done. */
5811 emit_insn (gen_blockage ());
5813 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5818 emit_insn (gen_blockage ());
5821 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5822 else if (size
<= 8192)
5824 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5825 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5829 rtx reg
= gen_rtx_REG (Pmode
, 1);
5830 emit_move_insn (reg
, GEN_INT (size
));
5831 emit_insn (gen_stack_pointer_inc (reg
));
5836 /* Return true if it is appropriate to emit `return' instructions in the
5837 body of a function. */
5840 sparc_can_use_return_insn_p (void)
5842 return sparc_prologue_data_valid_p
5843 && sparc_n_global_fp_regs
== 0
5845 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5846 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5849 /* This function generates the assembly code for function exit. */
5852 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5854 /* If the last two instructions of a function are "call foo; dslot;"
5855 the return address might point to the first instruction in the next
5856 function and we have to output a dummy nop for the sake of sane
5857 backtraces in such cases. This is pointless for sibling calls since
5858 the return address is explicitly adjusted. */
5860 rtx insn
, last_real_insn
;
5862 insn
= get_last_insn ();
5864 last_real_insn
= prev_real_insn (insn
);
5866 && NONJUMP_INSN_P (last_real_insn
)
5867 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5868 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5871 && CALL_P (last_real_insn
)
5872 && !SIBLING_CALL_P (last_real_insn
))
5873 fputs("\tnop\n", file
);
5875 sparc_output_deferred_case_vectors ();
5878 /* Output a 'restore' instruction. */
5881 output_restore (rtx pat
)
5887 fputs ("\t restore\n", asm_out_file
);
5891 gcc_assert (GET_CODE (pat
) == SET
);
5893 operands
[0] = SET_DEST (pat
);
5894 pat
= SET_SRC (pat
);
5896 switch (GET_CODE (pat
))
5899 operands
[1] = XEXP (pat
, 0);
5900 operands
[2] = XEXP (pat
, 1);
5901 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5904 operands
[1] = XEXP (pat
, 0);
5905 operands
[2] = XEXP (pat
, 1);
5906 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5909 operands
[1] = XEXP (pat
, 0);
5910 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5911 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5915 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5920 /* Output a return. */
5923 output_return (rtx_insn
*insn
)
5925 if (crtl
->calls_eh_return
)
5927 /* If the function uses __builtin_eh_return, the eh_return
5928 machinery occupies the delay slot. */
5929 gcc_assert (!final_sequence
);
5931 if (flag_delayed_branch
)
5933 if (!TARGET_FLAT
&& TARGET_V9
)
5934 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5938 fputs ("\trestore\n", asm_out_file
);
5940 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5943 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5948 fputs ("\trestore\n", asm_out_file
);
5950 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5951 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5954 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5956 /* This is a leaf or flat function so we don't have to bother restoring
5957 the register window, which frees us from dealing with the convoluted
5958 semantics of restore/return. We simply output the jump to the
5959 return address and the insn in the delay slot (if any). */
5961 return "jmp\t%%o7+%)%#";
5965 /* This is a regular function so we have to restore the register window.
5966 We may have a pending insn for the delay slot, which will be either
5967 combined with the 'restore' instruction or put in the delay slot of
5968 the 'return' instruction. */
5974 delay
= NEXT_INSN (insn
);
5977 pat
= PATTERN (delay
);
5979 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5981 epilogue_renumber (&pat
, 0);
5982 return "return\t%%i7+%)%#";
5986 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5987 output_restore (pat
);
5988 PATTERN (delay
) = gen_blockage ();
5989 INSN_CODE (delay
) = -1;
5994 /* The delay slot is empty. */
5996 return "return\t%%i7+%)\n\t nop";
5997 else if (flag_delayed_branch
)
5998 return "jmp\t%%i7+%)\n\t restore";
6000 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6007 /* Output a sibling call. */
6010 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6014 gcc_assert (flag_delayed_branch
);
6016 operands
[0] = call_operand
;
6018 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6020 /* This is a leaf or flat function so we don't have to bother restoring
6021 the register window. We simply output the jump to the function and
6022 the insn in the delay slot (if any). */
6024 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6027 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6030 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6031 it into branch if possible. */
6032 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6037 /* This is a regular function so we have to restore the register window.
6038 We may have a pending insn for the delay slot, which will be combined
6039 with the 'restore' instruction. */
6041 output_asm_insn ("call\t%a0, 0", operands
);
6045 rtx_insn
*delay
= NEXT_INSN (insn
);
6048 output_restore (PATTERN (delay
));
6050 PATTERN (delay
) = gen_blockage ();
6051 INSN_CODE (delay
) = -1;
6054 output_restore (NULL_RTX
);
6060 /* Functions for handling argument passing.
6062 For 32-bit, the first 6 args are normally in registers and the rest are
6063 pushed. Any arg that starts within the first 6 words is at least
6064 partially passed in a register unless its data type forbids.
6066 For 64-bit, the argument registers are laid out as an array of 16 elements
6067 and arguments are added sequentially. The first 6 int args and up to the
6068 first 16 fp args (depending on size) are passed in regs.
6070 Slot Stack Integral Float Float in structure Double Long Double
6071 ---- ----- -------- ----- ------------------ ------ -----------
6072 15 [SP+248] %f31 %f30,%f31 %d30
6073 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6074 13 [SP+232] %f27 %f26,%f27 %d26
6075 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6076 11 [SP+216] %f23 %f22,%f23 %d22
6077 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6078 9 [SP+200] %f19 %f18,%f19 %d18
6079 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6080 7 [SP+184] %f15 %f14,%f15 %d14
6081 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6082 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6083 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6084 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6085 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6086 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6087 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6089 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6091 Integral arguments are always passed as 64-bit quantities appropriately
6094 Passing of floating point values is handled as follows.
6095 If a prototype is in scope:
6096 If the value is in a named argument (i.e. not a stdarg function or a
6097 value not part of the `...') then the value is passed in the appropriate
6099 If the value is part of the `...' and is passed in one of the first 6
6100 slots then the value is passed in the appropriate int reg.
6101 If the value is part of the `...' and is not passed in one of the first 6
6102 slots then the value is passed in memory.
6103 If a prototype is not in scope:
6104 If the value is one of the first 6 arguments the value is passed in the
6105 appropriate integer reg and the appropriate fp reg.
6106 If the value is not one of the first 6 arguments the value is passed in
6107 the appropriate fp reg and in memory.
6110 Summary of the calling conventions implemented by GCC on the SPARC:
6113 size argument return value
6115 small integer <4 int. reg. int. reg.
6116 word 4 int. reg. int. reg.
6117 double word 8 int. reg. int. reg.
6119 _Complex small integer <8 int. reg. int. reg.
6120 _Complex word 8 int. reg. int. reg.
6121 _Complex double word 16 memory int. reg.
6123 vector integer <=8 int. reg. FP reg.
6124 vector integer >8 memory memory
6126 float 4 int. reg. FP reg.
6127 double 8 int. reg. FP reg.
6128 long double 16 memory memory
6130 _Complex float 8 memory FP reg.
6131 _Complex double 16 memory FP reg.
6132 _Complex long double 32 memory FP reg.
6134 vector float any memory memory
6136 aggregate any memory memory
6141 size argument return value
6143 small integer <8 int. reg. int. reg.
6144 word 8 int. reg. int. reg.
6145 double word 16 int. reg. int. reg.
6147 _Complex small integer <16 int. reg. int. reg.
6148 _Complex word 16 int. reg. int. reg.
6149 _Complex double word 32 memory int. reg.
6151 vector integer <=16 FP reg. FP reg.
6152 vector integer 16<s<=32 memory FP reg.
6153 vector integer >32 memory memory
6155 float 4 FP reg. FP reg.
6156 double 8 FP reg. FP reg.
6157 long double 16 FP reg. FP reg.
6159 _Complex float 8 FP reg. FP reg.
6160 _Complex double 16 FP reg. FP reg.
6161 _Complex long double 32 memory FP reg.
6163 vector float <=16 FP reg. FP reg.
6164 vector float 16<s<=32 memory FP reg.
6165 vector float >32 memory memory
6167 aggregate <=16 reg. reg.
6168 aggregate 16<s<=32 memory reg.
6169 aggregate >32 memory memory
6173 Note #1: complex floating-point types follow the extended SPARC ABIs as
6174 implemented by the Sun compiler.
6176 Note #2: integral vector types follow the scalar floating-point types
6177 conventions to match what is implemented by the Sun VIS SDK.
6179 Note #3: floating-point vector types follow the aggregate types
6183 /* Maximum number of int regs for args. */
6184 #define SPARC_INT_ARG_MAX 6
6185 /* Maximum number of fp regs for args. */
6186 #define SPARC_FP_ARG_MAX 16
6188 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6190 /* Handle the INIT_CUMULATIVE_ARGS macro.
6191 Initialize a variable CUM of type CUMULATIVE_ARGS
6192 for a call to a function whose data type is FNTYPE.
6193 For a library call, FNTYPE is 0. */
6196 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
6197 rtx libname ATTRIBUTE_UNUSED
,
6198 tree fndecl ATTRIBUTE_UNUSED
)
6201 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6202 cum
->libcall_p
= fntype
== 0;
6205 /* Handle promotion of pointer and integer arguments. */
6208 sparc_promote_function_mode (const_tree type
,
6211 const_tree fntype ATTRIBUTE_UNUSED
,
6212 int for_return ATTRIBUTE_UNUSED
)
6214 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
6216 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6220 /* Integral arguments are passed as full words, as per the ABI. */
6221 if (GET_MODE_CLASS (mode
) == MODE_INT
6222 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6228 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6231 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6233 return TARGET_ARCH64
? true : false;
6236 /* Scan the record type TYPE and return the following predicates:
6237 - INTREGS_P: the record contains at least one field or sub-field
6238 that is eligible for promotion in integer registers.
6239 - FP_REGS_P: the record contains at least one field or sub-field
6240 that is eligible for promotion in floating-point registers.
6241 - PACKED_P: the record contains at least one field that is packed.
6243 Sub-fields are not taken into account for the PACKED_P predicate. */
6246 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
6251 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6253 if (TREE_CODE (field
) == FIELD_DECL
)
6255 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6256 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
6257 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6258 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6264 if (packed_p
&& DECL_PACKED (field
))
6270 /* Compute the slot number to pass an argument in.
6271 Return the slot number or -1 if passing on the stack.
6273 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6274 the preceding args and about the function being called.
6275 MODE is the argument's machine mode.
6276 TYPE is the data type of the argument (as a tree).
6277 This is null for libcalls where that information may
6279 NAMED is nonzero if this argument is a named parameter
6280 (otherwise it is an extra parameter matching an ellipsis).
6281 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6282 *PREGNO records the register number to use if scalar type.
6283 *PPADDING records the amount of padding needed in words. */
6286 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6287 const_tree type
, bool named
, bool incoming_p
,
6288 int *pregno
, int *ppadding
)
6290 int regbase
= (incoming_p
6291 ? SPARC_INCOMING_INT_ARG_FIRST
6292 : SPARC_OUTGOING_INT_ARG_FIRST
);
6293 int slotno
= cum
->words
;
6294 enum mode_class mclass
;
6299 if (type
&& TREE_ADDRESSABLE (type
))
6305 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6308 /* For SPARC64, objects requiring 16-byte alignment get it. */
6310 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6311 && (slotno
& 1) != 0)
6312 slotno
++, *ppadding
= 1;
6314 mclass
= GET_MODE_CLASS (mode
);
6315 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6317 /* Vector types deserve special treatment because they are
6318 polymorphic wrt their mode, depending upon whether VIS
6319 instructions are enabled. */
6320 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6322 /* The SPARC port defines no floating-point vector modes. */
6323 gcc_assert (mode
== BLKmode
);
6327 /* Integral vector types should either have a vector
6328 mode or an integral mode, because we are guaranteed
6329 by pass_by_reference that their size is not greater
6330 than 16 bytes and TImode is 16-byte wide. */
6331 gcc_assert (mode
!= BLKmode
);
6333 /* Vector integers are handled like floats according to
6335 mclass
= MODE_FLOAT
;
6342 case MODE_COMPLEX_FLOAT
:
6343 case MODE_VECTOR_INT
:
6344 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6346 if (slotno
>= SPARC_FP_ARG_MAX
)
6348 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6349 /* Arguments filling only one single FP register are
6350 right-justified in the outer double FP register. */
6351 if (GET_MODE_SIZE (mode
) <= 4)
6358 case MODE_COMPLEX_INT
:
6359 if (slotno
>= SPARC_INT_ARG_MAX
)
6361 regno
= regbase
+ slotno
;
6365 if (mode
== VOIDmode
)
6366 /* MODE is VOIDmode when generating the actual call. */
6369 gcc_assert (mode
== BLKmode
);
6373 || (TREE_CODE (type
) != VECTOR_TYPE
6374 && TREE_CODE (type
) != RECORD_TYPE
))
6376 if (slotno
>= SPARC_INT_ARG_MAX
)
6378 regno
= regbase
+ slotno
;
6380 else /* TARGET_ARCH64 && type */
6382 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
6384 /* First see what kinds of registers we would need. */
6385 if (TREE_CODE (type
) == VECTOR_TYPE
)
6388 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
6390 /* The ABI obviously doesn't specify how packed structures
6391 are passed. These are defined to be passed in int regs
6392 if possible, otherwise memory. */
6393 if (packed_p
|| !named
)
6394 fpregs_p
= 0, intregs_p
= 1;
6396 /* If all arg slots are filled, then must pass on stack. */
6397 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
6400 /* If there are only int args and all int arg slots are filled,
6401 then must pass on stack. */
6402 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
6405 /* Note that even if all int arg slots are filled, fp members may
6406 still be passed in regs if such regs are available.
6407 *PREGNO isn't set because there may be more than one, it's up
6408 to the caller to compute them. */
6421 /* Handle recursive register counting for structure field layout. */
6423 struct function_arg_record_value_parms
6425 rtx ret
; /* return expression being built. */
6426 int slotno
; /* slot number of the argument. */
6427 int named
; /* whether the argument is named. */
6428 int regbase
; /* regno of the base register. */
6429 int stack
; /* 1 if part of the argument is on the stack. */
6430 int intoffset
; /* offset of the first pending integer field. */
6431 unsigned int nregs
; /* number of words passed in registers. */
6434 static void function_arg_record_value_3
6435 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
6436 static void function_arg_record_value_2
6437 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6438 static void function_arg_record_value_1
6439 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6440 static rtx
function_arg_record_value (const_tree
, machine_mode
, int, int, int);
6441 static rtx
function_arg_union_value (int, machine_mode
, int, int);
6443 /* A subroutine of function_arg_record_value. Traverse the structure
6444 recursively and determine how many registers will be required. */
6447 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
6448 struct function_arg_record_value_parms
*parms
,
6453 /* We need to compute how many registers are needed so we can
6454 allocate the PARALLEL but before we can do that we need to know
6455 whether there are any packed fields. The ABI obviously doesn't
6456 specify how structures are passed in this case, so they are
6457 defined to be passed in int regs if possible, otherwise memory,
6458 regardless of whether there are fp values present. */
6461 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
6463 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6470 /* Compute how many registers we need. */
6471 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6473 if (TREE_CODE (field
) == FIELD_DECL
)
6475 HOST_WIDE_INT bitpos
= startbitpos
;
6477 if (DECL_SIZE (field
) != 0)
6479 if (integer_zerop (DECL_SIZE (field
)))
6482 if (tree_fits_uhwi_p (bit_position (field
)))
6483 bitpos
+= int_bit_position (field
);
6486 /* ??? FIXME: else assume zero offset. */
6488 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6489 function_arg_record_value_1 (TREE_TYPE (field
),
6493 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6494 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6499 if (parms
->intoffset
!= -1)
6501 unsigned int startbit
, endbit
;
6502 int intslots
, this_slotno
;
6504 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
6505 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6507 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6508 this_slotno
= parms
->slotno
+ parms
->intoffset
6511 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6513 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6514 /* We need to pass this field on the stack. */
6518 parms
->nregs
+= intslots
;
6519 parms
->intoffset
= -1;
6522 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
6523 If it wasn't true we wouldn't be here. */
6524 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6525 && DECL_MODE (field
) == BLKmode
)
6526 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6527 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6534 if (parms
->intoffset
== -1)
6535 parms
->intoffset
= bitpos
;
6541 /* A subroutine of function_arg_record_value. Assign the bits of the
6542 structure between parms->intoffset and bitpos to integer registers. */
6545 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
6546 struct function_arg_record_value_parms
*parms
)
6550 unsigned int startbit
, endbit
;
6551 int this_slotno
, intslots
, intoffset
;
6554 if (parms
->intoffset
== -1)
6557 intoffset
= parms
->intoffset
;
6558 parms
->intoffset
= -1;
6560 startbit
= intoffset
& -BITS_PER_WORD
;
6561 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6562 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6563 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
6565 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
6569 /* If this is the trailing part of a word, only load that much into
6570 the register. Otherwise load the whole register. Note that in
6571 the latter case we may pick up unwanted bits. It's not a problem
6572 at the moment but may wish to revisit. */
6574 if (intoffset
% BITS_PER_WORD
!= 0)
6575 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6580 intoffset
/= BITS_PER_UNIT
;
6583 regno
= parms
->regbase
+ this_slotno
;
6584 reg
= gen_rtx_REG (mode
, regno
);
6585 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6586 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6589 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
6594 while (intslots
> 0);
6597 /* A subroutine of function_arg_record_value. Traverse the structure
6598 recursively and assign bits to floating point registers. Track which
6599 bits in between need integer registers; invoke function_arg_record_value_3
6600 to make that happen. */
6603 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
6604 struct function_arg_record_value_parms
*parms
,
6610 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6612 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6619 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6621 if (TREE_CODE (field
) == FIELD_DECL
)
6623 HOST_WIDE_INT bitpos
= startbitpos
;
6625 if (DECL_SIZE (field
) != 0)
6627 if (integer_zerop (DECL_SIZE (field
)))
6630 if (tree_fits_uhwi_p (bit_position (field
)))
6631 bitpos
+= int_bit_position (field
);
6634 /* ??? FIXME: else assume zero offset. */
6636 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6637 function_arg_record_value_2 (TREE_TYPE (field
),
6641 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6642 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6647 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
6648 int regno
, nregs
, pos
;
6649 machine_mode mode
= DECL_MODE (field
);
6652 function_arg_record_value_3 (bitpos
, parms
);
6654 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6657 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6658 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6660 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6662 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6668 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6669 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6671 reg
= gen_rtx_REG (mode
, regno
);
6672 pos
= bitpos
/ BITS_PER_UNIT
;
6673 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6674 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6678 regno
+= GET_MODE_SIZE (mode
) / 4;
6679 reg
= gen_rtx_REG (mode
, regno
);
6680 pos
+= GET_MODE_SIZE (mode
);
6681 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6682 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6688 if (parms
->intoffset
== -1)
6689 parms
->intoffset
= bitpos
;
6695 /* Used by function_arg and sparc_function_value_1 to implement the complex
6696 conventions of the 64-bit ABI for passing and returning structures.
6697 Return an expression valid as a return value for the FUNCTION_ARG
6698 and TARGET_FUNCTION_VALUE.
6700 TYPE is the data type of the argument (as a tree).
6701 This is null for libcalls where that information may
6703 MODE is the argument's machine mode.
6704 SLOTNO is the index number of the argument's slot in the parameter array.
6705 NAMED is nonzero if this argument is a named parameter
6706 (otherwise it is an extra parameter matching an ellipsis).
6707 REGBASE is the regno of the base register for the parameter array. */
6710 function_arg_record_value (const_tree type
, machine_mode mode
,
6711 int slotno
, int named
, int regbase
)
6713 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6714 struct function_arg_record_value_parms parms
;
6717 parms
.ret
= NULL_RTX
;
6718 parms
.slotno
= slotno
;
6719 parms
.named
= named
;
6720 parms
.regbase
= regbase
;
6723 /* Compute how many registers we need. */
6725 parms
.intoffset
= 0;
6726 function_arg_record_value_1 (type
, 0, &parms
, false);
6728 /* Take into account pending integer fields. */
6729 if (parms
.intoffset
!= -1)
6731 unsigned int startbit
, endbit
;
6732 int intslots
, this_slotno
;
6734 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
6735 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6736 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6737 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
6739 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6741 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6742 /* We need to pass this field on the stack. */
6746 parms
.nregs
+= intslots
;
6748 nregs
= parms
.nregs
;
6750 /* Allocate the vector and handle some annoying special cases. */
6753 /* ??? Empty structure has no value? Duh? */
6756 /* Though there's nothing really to store, return a word register
6757 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6758 leads to breakage due to the fact that there are zero bytes to
6760 return gen_rtx_REG (mode
, regbase
);
6764 /* ??? C++ has structures with no fields, and yet a size. Give up
6765 for now and pass everything back in integer registers. */
6766 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6768 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6769 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6771 gcc_assert (nregs
!= 0);
6773 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6775 /* If at least one field must be passed on the stack, generate
6776 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6777 also be passed on the stack. We can't do much better because the
6778 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6779 of structures for which the fields passed exclusively in registers
6780 are not at the beginning of the structure. */
6782 XVECEXP (parms
.ret
, 0, 0)
6783 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6785 /* Fill in the entries. */
6787 parms
.intoffset
= 0;
6788 function_arg_record_value_2 (type
, 0, &parms
, false);
6789 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6791 gcc_assert (parms
.nregs
== nregs
);
6796 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6797 of the 64-bit ABI for passing and returning unions.
6798 Return an expression valid as a return value for the FUNCTION_ARG
6799 and TARGET_FUNCTION_VALUE.
6801 SIZE is the size in bytes of the union.
6802 MODE is the argument's machine mode.
6803 REGNO is the hard register the union will be passed in. */
6806 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
6809 int nwords
= ROUND_ADVANCE (size
), i
;
6812 /* See comment in previous function for empty structures. */
6814 return gen_rtx_REG (mode
, regno
);
6816 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6819 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6821 for (i
= 0; i
< nwords
; i
++)
6823 /* Unions are passed left-justified. */
6824 XVECEXP (regs
, 0, i
)
6825 = gen_rtx_EXPR_LIST (VOIDmode
,
6826 gen_rtx_REG (word_mode
, regno
),
6827 GEN_INT (UNITS_PER_WORD
* i
));
6834 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6835 for passing and returning BLKmode vectors.
6836 Return an expression valid as a return value for the FUNCTION_ARG
6837 and TARGET_FUNCTION_VALUE.
6839 SIZE is the size in bytes of the vector.
6840 REGNO is the FP hard register the vector will be passed in. */
6843 function_arg_vector_value (int size
, int regno
)
6845 const int nregs
= MAX (1, size
/ 8);
6846 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6849 XVECEXP (regs
, 0, 0)
6850 = gen_rtx_EXPR_LIST (VOIDmode
,
6851 gen_rtx_REG (SImode
, regno
),
6854 for (int i
= 0; i
< nregs
; i
++)
6855 XVECEXP (regs
, 0, i
)
6856 = gen_rtx_EXPR_LIST (VOIDmode
,
6857 gen_rtx_REG (DImode
, regno
+ 2*i
),
6863 /* Determine where to put an argument to a function.
6864 Value is zero to push the argument on the stack,
6865 or a hard register in which to store the argument.
6867 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6868 the preceding args and about the function being called.
6869 MODE is the argument's machine mode.
6870 TYPE is the data type of the argument (as a tree).
6871 This is null for libcalls where that information may
6873 NAMED is true if this argument is a named parameter
6874 (otherwise it is an extra parameter matching an ellipsis).
6875 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6876 TARGET_FUNCTION_INCOMING_ARG. */
6879 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
6880 const_tree type
, bool named
, bool incoming_p
)
6882 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6884 int regbase
= (incoming_p
6885 ? SPARC_INCOMING_INT_ARG_FIRST
6886 : SPARC_OUTGOING_INT_ARG_FIRST
);
6887 int slotno
, regno
, padding
;
6888 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6890 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6895 /* Vector types deserve special treatment because they are polymorphic wrt
6896 their mode, depending upon whether VIS instructions are enabled. */
6897 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6899 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6900 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6901 || (TARGET_ARCH64
&& size
<= 16));
6903 if (mode
== BLKmode
)
6904 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
6906 mclass
= MODE_FLOAT
;
6910 return gen_rtx_REG (mode
, regno
);
6912 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6913 and are promoted to registers if possible. */
6914 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6916 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6917 gcc_assert (size
<= 16);
6919 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6922 /* Unions up to 16 bytes in size are passed in integer registers. */
6923 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6925 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6926 gcc_assert (size
<= 16);
6928 return function_arg_union_value (size
, mode
, slotno
, regno
);
6931 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6932 but also have the slot allocated for them.
6933 If no prototype is in scope fp values in register slots get passed
6934 in two places, either fp regs and int regs or fp regs and memory. */
6935 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6936 && SPARC_FP_REG_P (regno
))
6938 rtx reg
= gen_rtx_REG (mode
, regno
);
6939 if (cum
->prototype_p
|| cum
->libcall_p
)
6941 /* "* 2" because fp reg numbers are recorded in 4 byte
6944 /* ??? This will cause the value to be passed in the fp reg and
6945 in the stack. When a prototype exists we want to pass the
6946 value in the reg but reserve space on the stack. That's an
6947 optimization, and is deferred [for a bit]. */
6948 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6949 return gen_rtx_PARALLEL (mode
,
6951 gen_rtx_EXPR_LIST (VOIDmode
,
6952 NULL_RTX
, const0_rtx
),
6953 gen_rtx_EXPR_LIST (VOIDmode
,
6957 /* ??? It seems that passing back a register even when past
6958 the area declared by REG_PARM_STACK_SPACE will allocate
6959 space appropriately, and will not copy the data onto the
6960 stack, exactly as we desire.
6962 This is due to locate_and_pad_parm being called in
6963 expand_call whenever reg_parm_stack_space > 0, which
6964 while beneficial to our example here, would seem to be
6965 in error from what had been intended. Ho hum... -- r~ */
6973 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6977 /* On incoming, we don't need to know that the value
6978 is passed in %f0 and %i0, and it confuses other parts
6979 causing needless spillage even on the simplest cases. */
6983 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6984 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6986 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6987 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6989 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6993 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6994 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6995 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7000 /* All other aggregate types are passed in an integer register in a mode
7001 corresponding to the size of the type. */
7002 else if (type
&& AGGREGATE_TYPE_P (type
))
7004 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7005 gcc_assert (size
<= 16);
7007 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7010 return gen_rtx_REG (mode
, regno
);
7013 /* Handle the TARGET_FUNCTION_ARG target hook. */
7016 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7017 const_tree type
, bool named
)
7019 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7022 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7025 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7026 const_tree type
, bool named
)
7028 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7031 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7034 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7036 return ((TARGET_ARCH64
7037 && (GET_MODE_ALIGNMENT (mode
) == 128
7038 || (type
&& TYPE_ALIGN (type
) == 128)))
7043 /* For an arg passed partly in registers and partly in memory,
7044 this is the number of bytes of registers used.
7045 For args passed entirely in registers or entirely in memory, zero.
7047 Any arg that starts in the first 6 regs but won't entirely fit in them
7048 needs partial registers on v8. On v9, structures with integer
7049 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7050 values that begin in the last fp reg [where "last fp reg" varies with the
7051 mode] will be split between that reg and memory. */
7054 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7055 tree type
, bool named
)
7057 int slotno
, regno
, padding
;
7059 /* We pass false for incoming_p here, it doesn't matter. */
7060 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7061 false, ®no
, &padding
);
7068 if ((slotno
+ (mode
== BLKmode
7069 ? ROUND_ADVANCE (int_size_in_bytes (type
))
7070 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
7071 > SPARC_INT_ARG_MAX
)
7072 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7076 /* We are guaranteed by pass_by_reference that the size of the
7077 argument is not greater than 16 bytes, so we only need to return
7078 one word if the argument is partially passed in registers. */
7080 if (type
&& AGGREGATE_TYPE_P (type
))
7082 int size
= int_size_in_bytes (type
);
7084 if (size
> UNITS_PER_WORD
7085 && slotno
== SPARC_INT_ARG_MAX
- 1)
7086 return UNITS_PER_WORD
;
7088 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7089 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7090 && ! (TARGET_FPU
&& named
)))
7092 /* The complex types are passed as packed types. */
7093 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7094 && slotno
== SPARC_INT_ARG_MAX
- 1)
7095 return UNITS_PER_WORD
;
7097 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7099 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7101 return UNITS_PER_WORD
;
7108 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7109 Specify whether to pass the argument by reference. */
7112 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7113 machine_mode mode
, const_tree type
,
7114 bool named ATTRIBUTE_UNUSED
)
7117 /* Original SPARC 32-bit ABI says that structures and unions,
7118 and quad-precision floats are passed by reference. For Pascal,
7119 also pass arrays by reference. All other base types are passed
7122 Extended ABI (as implemented by the Sun compiler) says that all
7123 complex floats are passed by reference. Pass complex integers
7124 in registers up to 8 bytes. More generally, enforce the 2-word
7125 cap for passing arguments in registers.
7127 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7128 integers are passed like floats of the same size, that is in
7129 registers up to 8 bytes. Pass all vector floats by reference
7130 like structure and unions. */
7131 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7133 /* Catch CDImode, TFmode, DCmode and TCmode. */
7134 || GET_MODE_SIZE (mode
) > 8
7136 && TREE_CODE (type
) == VECTOR_TYPE
7137 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7139 /* Original SPARC 64-bit ABI says that structures and unions
7140 smaller than 16 bytes are passed in registers, as well as
7141 all other base types.
7143 Extended ABI (as implemented by the Sun compiler) says that
7144 complex floats are passed in registers up to 16 bytes. Pass
7145 all complex integers in registers up to 16 bytes. More generally,
7146 enforce the 2-word cap for passing arguments in registers.
7148 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7149 integers are passed like floats of the same size, that is in
7150 registers (up to 16 bytes). Pass all vector floats like structure
7153 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7154 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7155 /* Catch CTImode and TCmode. */
7156 || GET_MODE_SIZE (mode
) > 16);
7159 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7160 Update the data in CUM to advance over an argument
7161 of mode MODE and data type TYPE.
7162 TYPE is null for libcalls where that information may not be available. */
7165 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7166 const_tree type
, bool named
)
7168 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7171 /* We pass false for incoming_p here, it doesn't matter. */
7172 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7174 /* If argument requires leading padding, add it. */
7175 cum
->words
+= padding
;
7179 cum
->words
+= (mode
!= BLKmode
7180 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7181 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7185 if (type
&& AGGREGATE_TYPE_P (type
))
7187 int size
= int_size_in_bytes (type
);
7191 else if (size
<= 16)
7193 else /* passed by reference */
7198 cum
->words
+= (mode
!= BLKmode
7199 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7200 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7205 /* Handle the FUNCTION_ARG_PADDING macro.
7206 For the 64 bit ABI structs are always stored left shifted in their
7210 function_arg_padding (machine_mode mode
, const_tree type
)
7212 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
7215 /* Fall back to the default. */
7216 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7219 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7220 Specify whether to return the return value in memory. */
7223 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7226 /* Original SPARC 32-bit ABI says that structures and unions,
7227 and quad-precision floats are returned in memory. All other
7228 base types are returned in registers.
7230 Extended ABI (as implemented by the Sun compiler) says that
7231 all complex floats are returned in registers (8 FP registers
7232 at most for '_Complex long double'). Return all complex integers
7233 in registers (4 at most for '_Complex long long').
7235 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7236 integers are returned like floats of the same size, that is in
7237 registers up to 8 bytes and in memory otherwise. Return all
7238 vector floats in memory like structure and unions; note that
7239 they always have BLKmode like the latter. */
7240 return (TYPE_MODE (type
) == BLKmode
7241 || TYPE_MODE (type
) == TFmode
7242 || (TREE_CODE (type
) == VECTOR_TYPE
7243 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7245 /* Original SPARC 64-bit ABI says that structures and unions
7246 smaller than 32 bytes are returned in registers, as well as
7247 all other base types.
7249 Extended ABI (as implemented by the Sun compiler) says that all
7250 complex floats are returned in registers (8 FP registers at most
7251 for '_Complex long double'). Return all complex integers in
7252 registers (4 at most for '_Complex TItype').
7254 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7255 integers are returned like floats of the same size, that is in
7256 registers. Return all vector floats like structure and unions;
7257 note that they always have BLKmode like the latter. */
7258 return (TYPE_MODE (type
) == BLKmode
7259 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7262 /* Handle the TARGET_STRUCT_VALUE target hook.
7263 Return where to find the structure return value address. */
7266 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7275 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7276 STRUCT_VALUE_OFFSET
));
7278 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7279 STRUCT_VALUE_OFFSET
));
7281 /* Only follow the SPARC ABI for fixed-size structure returns.
7282 Variable size structure returns are handled per the normal
7283 procedures in GCC. This is enabled by -mstd-struct-return */
7285 && sparc_std_struct_return
7286 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7287 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7289 /* We must check and adjust the return address, as it is
7290 optional as to whether the return object is really
7292 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
7293 rtx scratch
= gen_reg_rtx (SImode
);
7294 rtx_code_label
*endlab
= gen_label_rtx ();
7296 /* Calculate the return object size */
7297 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7298 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7299 /* Construct a temporary return value */
7301 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7303 /* Implement SPARC 32-bit psABI callee return struct checking:
7305 Fetch the instruction where we will return to and see if
7306 it's an unimp instruction (the most significant 10 bits
7308 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7309 plus_constant (Pmode
,
7311 /* Assume the size is valid and pre-adjust */
7312 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7313 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7315 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7316 /* Write the address of the memory pointed to by temp_val into
7317 the memory pointed to by mem */
7318 emit_move_insn (mem
, XEXP (temp_val
, 0));
7319 emit_label (endlab
);
7326 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7327 For v9, function return values are subject to the same rules as arguments,
7328 except that up to 32 bytes may be returned in registers. */
7331 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7334 /* Beware that the two values are swapped here wrt function_arg. */
7335 int regbase
= (outgoing
7336 ? SPARC_INCOMING_INT_ARG_FIRST
7337 : SPARC_OUTGOING_INT_ARG_FIRST
);
7338 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7341 /* Vector types deserve special treatment because they are polymorphic wrt
7342 their mode, depending upon whether VIS instructions are enabled. */
7343 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7345 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7346 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7347 || (TARGET_ARCH64
&& size
<= 32));
7349 if (mode
== BLKmode
)
7350 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7352 mclass
= MODE_FLOAT
;
7355 if (TARGET_ARCH64
&& type
)
7357 /* Structures up to 32 bytes in size are returned in registers. */
7358 if (TREE_CODE (type
) == RECORD_TYPE
)
7360 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7361 gcc_assert (size
<= 32);
7363 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7366 /* Unions up to 32 bytes in size are returned in integer registers. */
7367 else if (TREE_CODE (type
) == UNION_TYPE
)
7369 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7370 gcc_assert (size
<= 32);
7372 return function_arg_union_value (size
, mode
, 0, regbase
);
7375 /* Objects that require it are returned in FP registers. */
7376 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7379 /* All other aggregate types are returned in an integer register in a
7380 mode corresponding to the size of the type. */
7381 else if (AGGREGATE_TYPE_P (type
))
7383 /* All other aggregate types are passed in an integer register
7384 in a mode corresponding to the size of the type. */
7385 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7386 gcc_assert (size
<= 32);
7388 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7390 /* ??? We probably should have made the same ABI change in
7391 3.4.0 as the one we made for unions. The latter was
7392 required by the SCD though, while the former is not
7393 specified, so we favored compatibility and efficiency.
7395 Now we're stuck for aggregates larger than 16 bytes,
7396 because OImode vanished in the meantime. Let's not
7397 try to be unduly clever, and simply follow the ABI
7398 for unions in that case. */
7399 if (mode
== BLKmode
)
7400 return function_arg_union_value (size
, mode
, 0, regbase
);
7405 /* We should only have pointer and integer types at this point. This
7406 must match sparc_promote_function_mode. */
7407 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7411 /* We should only have pointer and integer types at this point. This must
7412 match sparc_promote_function_mode. */
7413 else if (TARGET_ARCH32
7414 && mclass
== MODE_INT
7415 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7418 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7419 regno
= SPARC_FP_ARG_FIRST
;
7423 return gen_rtx_REG (mode
, regno
);
7426 /* Handle TARGET_FUNCTION_VALUE.
7427 On the SPARC, the value is found in the first "output" register, but the
7428 called function leaves it in the first "input" register. */
7431 sparc_function_value (const_tree valtype
,
7432 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7435 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7438 /* Handle TARGET_LIBCALL_VALUE. */
7441 sparc_libcall_value (machine_mode mode
,
7442 const_rtx fun ATTRIBUTE_UNUSED
)
7444 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7447 /* Handle FUNCTION_VALUE_REGNO_P.
7448 On the SPARC, the first "output" reg is used for integer values, and the
7449 first floating point register is used for floating point values. */
7452 sparc_function_value_regno_p (const unsigned int regno
)
7454 return (regno
== 8 || regno
== 32);
7457 /* Do what is necessary for `va_start'. We look at the current function
7458 to determine if stdarg or varargs is used and return the address of
7459 the first unnamed parameter. */
7462 sparc_builtin_saveregs (void)
7464 int first_reg
= crtl
->args
.info
.words
;
7468 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7469 emit_move_insn (gen_rtx_MEM (word_mode
,
7470 gen_rtx_PLUS (Pmode
,
7472 GEN_INT (FIRST_PARM_OFFSET (0)
7475 gen_rtx_REG (word_mode
,
7476 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7478 address
= gen_rtx_PLUS (Pmode
,
7480 GEN_INT (FIRST_PARM_OFFSET (0)
7481 + UNITS_PER_WORD
* first_reg
));
7486 /* Implement `va_start' for stdarg. */
7489 sparc_va_start (tree valist
, rtx nextarg
)
7491 nextarg
= expand_builtin_saveregs ();
7492 std_expand_builtin_va_start (valist
, nextarg
);
7495 /* Implement `va_arg' for stdarg. */
7498 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7501 HOST_WIDE_INT size
, rsize
, align
;
7504 tree ptrtype
= build_pointer_type (type
);
7506 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7509 size
= rsize
= UNITS_PER_WORD
;
7515 size
= int_size_in_bytes (type
);
7516 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
7521 /* For SPARC64, objects requiring 16-byte alignment get it. */
7522 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7523 align
= 2 * UNITS_PER_WORD
;
7525 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7526 are left-justified in their slots. */
7527 if (AGGREGATE_TYPE_P (type
))
7530 size
= rsize
= UNITS_PER_WORD
;
7540 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7541 incr
= fold_convert (sizetype
, incr
);
7542 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7544 incr
= fold_convert (ptr_type_node
, incr
);
7547 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7550 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7551 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7555 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7556 addr
= build_va_arg_indirect_ref (addr
);
7559 /* If the address isn't aligned properly for the type, we need a temporary.
7560 FIXME: This is inefficient, usually we can do this in registers. */
7561 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7563 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7564 tree dest_addr
= build_fold_addr_expr (tmp
);
7565 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7566 3, dest_addr
, addr
, size_int (rsize
));
7567 TREE_ADDRESSABLE (tmp
) = 1;
7568 gimplify_and_add (copy
, pre_p
);
7573 addr
= fold_convert (ptrtype
, addr
);
7575 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7576 gimplify_assign (valist
, incr
, post_p
);
7578 return build_va_arg_indirect_ref (addr
);
7581 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7582 Specify whether the vector mode is supported by the hardware. */
7585 sparc_vector_mode_supported_p (machine_mode mode
)
7587 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7590 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7593 sparc_preferred_simd_mode (machine_mode mode
)
7611 /* Return the string to output an unconditional branch to LABEL, which is
7612 the operand number of the label.
7614 DEST is the destination insn (i.e. the label), INSN is the source. */
7617 output_ubranch (rtx dest
, rtx_insn
*insn
)
7619 static char string
[64];
7620 bool v9_form
= false;
7624 /* Even if we are trying to use cbcond for this, evaluate
7625 whether we can use V9 branches as our backup plan. */
7628 if (INSN_ADDRESSES_SET_P ())
7629 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7630 - INSN_ADDRESSES (INSN_UID (insn
)));
7632 /* Leave some instructions for "slop". */
7633 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7638 bool emit_nop
= emit_cbcond_nop (insn
);
7642 if (delta
< -500 || delta
> 500)
7648 rval
= "ba,a,pt\t%%xcc, %l0";
7655 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7657 rval
= "cwbe\t%%g0, %%g0, %l0";
7663 strcpy (string
, "ba%*,pt\t%%xcc, ");
7665 strcpy (string
, "b%*\t");
7667 p
= strchr (string
, '\0');
7678 /* Return the string to output a conditional branch to LABEL, which is
7679 the operand number of the label. OP is the conditional expression.
7680 XEXP (OP, 0) is assumed to be a condition code register (integer or
7681 floating point) and its mode specifies what kind of comparison we made.
7683 DEST is the destination insn (i.e. the label), INSN is the source.
7685 REVERSED is nonzero if we should reverse the sense of the comparison.
7687 ANNUL is nonzero if we should generate an annulling branch. */
7690 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7693 static char string
[64];
7694 enum rtx_code code
= GET_CODE (op
);
7695 rtx cc_reg
= XEXP (op
, 0);
7696 machine_mode mode
= GET_MODE (cc_reg
);
7697 const char *labelno
, *branch
;
7698 int spaces
= 8, far
;
7701 /* v9 branches are limited to +-1MB. If it is too far away,
7714 fbne,a,pn %fcc2, .LC29
7722 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7725 /* Reversal of FP compares takes care -- an ordered compare
7726 becomes an unordered compare and vice versa. */
7727 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7728 code
= reverse_condition_maybe_unordered (code
);
7730 code
= reverse_condition (code
);
7733 /* Start by writing the branch condition. */
7734 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7785 /* ??? !v9: FP branches cannot be preceded by another floating point
7786 insn. Because there is currently no concept of pre-delay slots,
7787 we can fix this only by always emitting a nop before a floating
7792 strcpy (string
, "nop\n\t");
7793 strcat (string
, branch
);
7806 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7818 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7839 strcpy (string
, branch
);
7841 spaces
-= strlen (branch
);
7842 p
= strchr (string
, '\0');
7844 /* Now add the annulling, the label, and a possible noop. */
7857 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7859 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7860 - INSN_ADDRESSES (INSN_UID (insn
)));
7861 /* Leave some instructions for "slop". */
7862 if (delta
< -260000 || delta
>= 260000)
7866 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7868 static char v9_fcc_labelno
[] = "%%fccX, ";
7869 /* Set the char indicating the number of the fcc reg to use. */
7870 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7871 labelno
= v9_fcc_labelno
;
7874 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7878 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7880 labelno
= "%%xcc, ";
7885 labelno
= "%%icc, ";
7890 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7893 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7906 strcpy (p
, labelno
);
7907 p
= strchr (p
, '\0');
7910 strcpy (p
, ".+12\n\t nop\n\tb\t");
7911 /* Skip the next insn if requested or
7912 if we know that it will be a nop. */
7913 if (annul
|| ! final_sequence
)
7927 /* Emit a library call comparison between floating point X and Y.
7928 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7929 Return the new operator to be used in the comparison sequence.
7931 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7932 values as arguments instead of the TFmode registers themselves,
7933 that's why we cannot call emit_float_lib_cmp. */
7936 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7939 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7941 enum rtx_code new_comparison
;
7946 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7950 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7954 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7958 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7962 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7966 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7977 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7988 tree expr
= MEM_EXPR (x
);
7990 mark_addressable (expr
);
7995 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7996 emit_move_insn (slot0
, x
);
8001 tree expr
= MEM_EXPR (y
);
8003 mark_addressable (expr
);
8008 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8009 emit_move_insn (slot1
, y
);
8012 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8013 emit_library_call (libfunc
, LCT_NORMAL
,
8015 XEXP (slot0
, 0), Pmode
,
8016 XEXP (slot1
, 0), Pmode
);
8021 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8022 emit_library_call (libfunc
, LCT_NORMAL
,
8024 x
, TFmode
, y
, TFmode
);
8029 /* Immediately move the result of the libcall into a pseudo
8030 register so reload doesn't clobber the value if it needs
8031 the return register for a spill reg. */
8032 result
= gen_reg_rtx (mode
);
8033 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8038 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8041 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8042 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8045 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8046 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8048 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8050 tem
= gen_reg_rtx (mode
);
8052 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8054 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8055 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8058 tem
= gen_reg_rtx (mode
);
8060 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8062 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8063 tem2
= gen_reg_rtx (mode
);
8065 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8067 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8068 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8069 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8075 /* Generate an unsigned DImode to FP conversion. This is the same code
8076 optabs would emit if we didn't have TFmode patterns. */
8079 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8081 rtx i0
, i1
, f0
, in
, out
;
8084 in
= force_reg (DImode
, operands
[1]);
8085 rtx_code_label
*neglab
= gen_label_rtx ();
8086 rtx_code_label
*donelab
= gen_label_rtx ();
8087 i0
= gen_reg_rtx (DImode
);
8088 i1
= gen_reg_rtx (DImode
);
8089 f0
= gen_reg_rtx (mode
);
8091 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8093 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
8094 emit_jump_insn (gen_jump (donelab
));
8097 emit_label (neglab
);
8099 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8100 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8101 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8102 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
8103 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8105 emit_label (donelab
);
8108 /* Generate an FP to unsigned DImode conversion. This is the same code
8109 optabs would emit if we didn't have TFmode patterns. */
8112 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8114 rtx i0
, i1
, f0
, in
, out
, limit
;
8117 in
= force_reg (mode
, operands
[1]);
8118 rtx_code_label
*neglab
= gen_label_rtx ();
8119 rtx_code_label
*donelab
= gen_label_rtx ();
8120 i0
= gen_reg_rtx (DImode
);
8121 i1
= gen_reg_rtx (DImode
);
8122 limit
= gen_reg_rtx (mode
);
8123 f0
= gen_reg_rtx (mode
);
8125 emit_move_insn (limit
,
8126 CONST_DOUBLE_FROM_REAL_VALUE (
8127 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8128 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8130 emit_insn (gen_rtx_SET (VOIDmode
,
8132 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8133 emit_jump_insn (gen_jump (donelab
));
8136 emit_label (neglab
);
8138 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8139 emit_insn (gen_rtx_SET (VOIDmode
,
8141 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8142 emit_insn (gen_movdi (i1
, const1_rtx
));
8143 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8144 emit_insn (gen_xordi3 (out
, i0
, i1
));
8146 emit_label (donelab
);
8149 /* Return the string to output a compare and branch instruction to DEST.
8150 DEST is the destination insn (i.e. the label), INSN is the source,
8151 and OP is the conditional expression. */
8154 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8156 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8157 enum rtx_code code
= GET_CODE (op
);
8158 const char *cond_str
, *tmpl
;
8159 int far
, emit_nop
, len
;
8160 static char string
[64];
8163 /* Compare and Branch is limited to +-2KB. If it is too far away,
8175 len
= get_attr_length (insn
);
8178 emit_nop
= len
== 2;
8181 code
= reverse_condition (code
);
8183 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8196 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8211 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8239 int veryfar
= 1, delta
;
8241 if (INSN_ADDRESSES_SET_P ())
8243 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8244 - INSN_ADDRESSES (INSN_UID (insn
)));
8245 /* Leave some instructions for "slop". */
8246 if (delta
>= -260000 && delta
< 260000)
8251 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8253 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8258 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8260 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8263 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8268 /* Return the string to output a conditional branch to LABEL, testing
8269 register REG. LABEL is the operand number of the label; REG is the
8270 operand number of the reg. OP is the conditional expression. The mode
8271 of REG says what kind of comparison we made.
8273 DEST is the destination insn (i.e. the label), INSN is the source.
8275 REVERSED is nonzero if we should reverse the sense of the comparison.
8277 ANNUL is nonzero if we should generate an annulling branch. */
8280 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8281 int annul
, rtx_insn
*insn
)
8283 static char string
[64];
8284 enum rtx_code code
= GET_CODE (op
);
8285 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8290 /* branch on register are limited to +-128KB. If it is too far away,
8303 brgez,a,pn %o1, .LC29
8309 ba,pt %xcc, .LC29 */
8311 far
= get_attr_length (insn
) >= 3;
8313 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8315 code
= reverse_condition (code
);
8317 /* Only 64 bit versions of these instructions exist. */
8318 gcc_assert (mode
== DImode
);
8320 /* Start by writing the branch condition. */
8325 strcpy (string
, "brnz");
8329 strcpy (string
, "brz");
8333 strcpy (string
, "brgez");
8337 strcpy (string
, "brlz");
8341 strcpy (string
, "brlez");
8345 strcpy (string
, "brgz");
8352 p
= strchr (string
, '\0');
8354 /* Now add the annulling, reg, label, and nop. */
8361 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8364 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
8369 *p
= p
< string
+ 8 ? '\t' : ' ';
8377 int veryfar
= 1, delta
;
8379 if (INSN_ADDRESSES_SET_P ())
8381 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8382 - INSN_ADDRESSES (INSN_UID (insn
)));
8383 /* Leave some instructions for "slop". */
8384 if (delta
>= -260000 && delta
< 260000)
8388 strcpy (p
, ".+12\n\t nop\n\t");
8389 /* Skip the next insn if requested or
8390 if we know that it will be a nop. */
8391 if (annul
|| ! final_sequence
)
8401 strcpy (p
, "ba,pt\t%%xcc, ");
8415 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8416 Such instructions cannot be used in the delay slot of return insn on v9.
8417 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8421 epilogue_renumber (register rtx
*where
, int test
)
8423 register const char *fmt
;
8425 register enum rtx_code code
;
8430 code
= GET_CODE (*where
);
8435 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8437 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8438 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8446 /* Do not replace the frame pointer with the stack pointer because
8447 it can cause the delayed instruction to load below the stack.
8448 This occurs when instructions like:
8450 (set (reg/i:SI 24 %i0)
8451 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8452 (const_int -20 [0xffffffec])) 0))
8454 are in the return delayed slot. */
8456 if (GET_CODE (XEXP (*where
, 0)) == REG
8457 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8458 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8459 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8464 if (SPARC_STACK_BIAS
8465 && GET_CODE (XEXP (*where
, 0)) == REG
8466 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8474 fmt
= GET_RTX_FORMAT (code
);
8476 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8481 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8482 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8485 else if (fmt
[i
] == 'e'
8486 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8492 /* Leaf functions and non-leaf functions have different needs. */
8495 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8498 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8500 static const int *const reg_alloc_orders
[] = {
8501 reg_leaf_alloc_order
,
8502 reg_nonleaf_alloc_order
};
8505 order_regs_for_local_alloc (void)
8507 static int last_order_nonleaf
= 1;
8509 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8511 last_order_nonleaf
= !last_order_nonleaf
;
8512 memcpy ((char *) reg_alloc_order
,
8513 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8514 FIRST_PSEUDO_REGISTER
* sizeof (int));
8518 /* Return 1 if REG and MEM are legitimate enough to allow the various
8519 mem<-->reg splits to be run. */
8522 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8524 /* Punt if we are here by mistake. */
8525 gcc_assert (reload_completed
);
8527 /* We must have an offsettable memory reference. */
8528 if (! offsettable_memref_p (mem
))
8531 /* If we have legitimate args for ldd/std, we do not want
8532 the split to happen. */
8533 if ((REGNO (reg
) % 2) == 0
8534 && mem_min_alignment (mem
, 8))
8541 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8544 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8548 if (GET_CODE (reg1
) == SUBREG
)
8549 reg1
= SUBREG_REG (reg1
);
8550 if (GET_CODE (reg1
) != REG
)
8552 regno1
= REGNO (reg1
);
8554 if (GET_CODE (reg2
) == SUBREG
)
8555 reg2
= SUBREG_REG (reg2
);
8556 if (GET_CODE (reg2
) != REG
)
8558 regno2
= REGNO (reg2
);
8560 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8565 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8566 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8573 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8574 This makes them candidates for using ldd and std insns.
8576 Note reg1 and reg2 *must* be hard registers. */
8579 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8581 /* We might have been passed a SUBREG. */
8582 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8585 if (REGNO (reg1
) % 2 != 0)
8588 /* Integer ldd is deprecated in SPARC V9 */
8589 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8592 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8595 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8598 This can only happen when addr1 and addr2, the addresses in mem1
8599 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8600 addr1 must also be aligned on a 64-bit boundary.
8602 Also iff dependent_reg_rtx is not null it should not be used to
8603 compute the address for mem1, i.e. we cannot optimize a sequence
8615 But, note that the transformation from:
8620 is perfectly fine. Thus, the peephole2 patterns always pass us
8621 the destination register of the first load, never the second one.
8623 For stores we don't have a similar problem, so dependent_reg_rtx is
8627 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8631 HOST_WIDE_INT offset1
;
8633 /* The mems cannot be volatile. */
8634 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8637 /* MEM1 should be aligned on a 64-bit boundary. */
8638 if (MEM_ALIGN (mem1
) < 64)
8641 addr1
= XEXP (mem1
, 0);
8642 addr2
= XEXP (mem2
, 0);
8644 /* Extract a register number and offset (if used) from the first addr. */
8645 if (GET_CODE (addr1
) == PLUS
)
8647 /* If not a REG, return zero. */
8648 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8652 reg1
= REGNO (XEXP (addr1
, 0));
8653 /* The offset must be constant! */
8654 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8656 offset1
= INTVAL (XEXP (addr1
, 1));
8659 else if (GET_CODE (addr1
) != REG
)
8663 reg1
= REGNO (addr1
);
8664 /* This was a simple (mem (reg)) expression. Offset is 0. */
8668 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8669 if (GET_CODE (addr2
) != PLUS
)
8672 if (GET_CODE (XEXP (addr2
, 0)) != REG
8673 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8676 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8679 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8682 /* The first offset must be evenly divisible by 8 to ensure the
8683 address is 64 bit aligned. */
8684 if (offset1
% 8 != 0)
8687 /* The offset for the second addr must be 4 more than the first addr. */
8688 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8691 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8696 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8699 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
8701 rtx x
= widen_memory_access (mem1
, mode
, 0);
8702 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8706 /* Return 1 if reg is a pseudo, or is the first register in
8707 a hard register pair. This makes it suitable for use in
8708 ldd and std insns. */
8711 register_ok_for_ldd (rtx reg
)
8713 /* We might have been passed a SUBREG. */
8717 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8718 return (REGNO (reg
) % 2 == 0);
8723 /* Return 1 if OP, a MEM, has an address which is known to be
8724 aligned to an 8-byte boundary. */
8727 memory_ok_for_ldd (rtx op
)
8729 /* In 64-bit mode, we assume that the address is word-aligned. */
8730 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8733 if (! can_create_pseudo_p ()
8734 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8740 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8743 sparc_print_operand_punct_valid_p (unsigned char code
)
8756 /* Implement TARGET_PRINT_OPERAND.
8757 Print operand X (an rtx) in assembler syntax to file FILE.
8758 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8759 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8762 sparc_print_operand (FILE *file
, rtx x
, int code
)
8767 /* Output an insn in a delay slot. */
8769 sparc_indent_opcode
= 1;
8771 fputs ("\n\t nop", file
);
8774 /* Output an annul flag if there's nothing for the delay slot and we
8775 are optimizing. This is always used with '(' below.
8776 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8777 this is a dbx bug. So, we only do this when optimizing.
8778 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8779 Always emit a nop in case the next instruction is a branch. */
8780 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8784 /* Output a 'nop' if there's nothing for the delay slot and we are
8785 not optimizing. This is always used with '*' above. */
8786 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8787 fputs ("\n\t nop", file
);
8788 else if (final_sequence
)
8789 sparc_indent_opcode
= 1;
8792 /* Output the right displacement from the saved PC on function return.
8793 The caller may have placed an "unimp" insn immediately after the call
8794 so we have to account for it. This insn is used in the 32-bit ABI
8795 when calling a function that returns a non zero-sized structure. The
8796 64-bit ABI doesn't have it. Be careful to have this test be the same
8797 as that for the call. The exception is when sparc_std_struct_return
8798 is enabled, the psABI is followed exactly and the adjustment is made
8799 by the code in sparc_struct_value_rtx. The call emitted is the same
8800 when sparc_std_struct_return is enabled. */
8802 && cfun
->returns_struct
8803 && !sparc_std_struct_return
8804 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8805 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8807 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8813 /* Output the Embedded Medium/Anywhere code model base register. */
8814 fputs (EMBMEDANY_BASE_REG
, file
);
8817 /* Print some local dynamic TLS name. */
8818 if (const char *name
= get_some_local_dynamic_name ())
8819 assemble_name (file
, name
);
8821 output_operand_lossage ("'%%&' used without any "
8822 "local dynamic TLS references");
8826 /* Adjust the operand to take into account a RESTORE operation. */
8827 if (GET_CODE (x
) == CONST_INT
)
8829 else if (GET_CODE (x
) != REG
)
8830 output_operand_lossage ("invalid %%Y operand");
8831 else if (REGNO (x
) < 8)
8832 fputs (reg_names
[REGNO (x
)], file
);
8833 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8834 fputs (reg_names
[REGNO (x
)-16], file
);
8836 output_operand_lossage ("invalid %%Y operand");
8839 /* Print out the low order register name of a register pair. */
8840 if (WORDS_BIG_ENDIAN
)
8841 fputs (reg_names
[REGNO (x
)+1], file
);
8843 fputs (reg_names
[REGNO (x
)], file
);
8846 /* Print out the high order register name of a register pair. */
8847 if (WORDS_BIG_ENDIAN
)
8848 fputs (reg_names
[REGNO (x
)], file
);
8850 fputs (reg_names
[REGNO (x
)+1], file
);
8853 /* Print out the second register name of a register pair or quad.
8854 I.e., R (%o0) => %o1. */
8855 fputs (reg_names
[REGNO (x
)+1], file
);
8858 /* Print out the third register name of a register quad.
8859 I.e., S (%o0) => %o2. */
8860 fputs (reg_names
[REGNO (x
)+2], file
);
8863 /* Print out the fourth register name of a register quad.
8864 I.e., T (%o0) => %o3. */
8865 fputs (reg_names
[REGNO (x
)+3], file
);
8868 /* Print a condition code register. */
8869 if (REGNO (x
) == SPARC_ICC_REG
)
8871 /* We don't handle CC[X]_NOOVmode because they're not supposed
8873 if (GET_MODE (x
) == CCmode
)
8874 fputs ("%icc", file
);
8875 else if (GET_MODE (x
) == CCXmode
)
8876 fputs ("%xcc", file
);
8881 /* %fccN register */
8882 fputs (reg_names
[REGNO (x
)], file
);
8885 /* Print the operand's address only. */
8886 output_address (XEXP (x
, 0));
8889 /* In this case we need a register. Use %g0 if the
8890 operand is const0_rtx. */
8892 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8894 fputs ("%g0", file
);
8901 switch (GET_CODE (x
))
8903 case IOR
: fputs ("or", file
); break;
8904 case AND
: fputs ("and", file
); break;
8905 case XOR
: fputs ("xor", file
); break;
8906 default: output_operand_lossage ("invalid %%A operand");
8911 switch (GET_CODE (x
))
8913 case IOR
: fputs ("orn", file
); break;
8914 case AND
: fputs ("andn", file
); break;
8915 case XOR
: fputs ("xnor", file
); break;
8916 default: output_operand_lossage ("invalid %%B operand");
8920 /* This is used by the conditional move instructions. */
8923 enum rtx_code rc
= GET_CODE (x
);
8927 case NE
: fputs ("ne", file
); break;
8928 case EQ
: fputs ("e", file
); break;
8929 case GE
: fputs ("ge", file
); break;
8930 case GT
: fputs ("g", file
); break;
8931 case LE
: fputs ("le", file
); break;
8932 case LT
: fputs ("l", file
); break;
8933 case GEU
: fputs ("geu", file
); break;
8934 case GTU
: fputs ("gu", file
); break;
8935 case LEU
: fputs ("leu", file
); break;
8936 case LTU
: fputs ("lu", file
); break;
8937 case LTGT
: fputs ("lg", file
); break;
8938 case UNORDERED
: fputs ("u", file
); break;
8939 case ORDERED
: fputs ("o", file
); break;
8940 case UNLT
: fputs ("ul", file
); break;
8941 case UNLE
: fputs ("ule", file
); break;
8942 case UNGT
: fputs ("ug", file
); break;
8943 case UNGE
: fputs ("uge", file
); break;
8944 case UNEQ
: fputs ("ue", file
); break;
8945 default: output_operand_lossage ("invalid %%C operand");
8950 /* This are used by the movr instruction pattern. */
8953 enum rtx_code rc
= GET_CODE (x
);
8956 case NE
: fputs ("ne", file
); break;
8957 case EQ
: fputs ("e", file
); break;
8958 case GE
: fputs ("gez", file
); break;
8959 case LT
: fputs ("lz", file
); break;
8960 case LE
: fputs ("lez", file
); break;
8961 case GT
: fputs ("gz", file
); break;
8962 default: output_operand_lossage ("invalid %%D operand");
8969 /* Print a sign-extended character. */
8970 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8971 fprintf (file
, "%d", i
);
8976 /* Operand must be a MEM; write its address. */
8977 if (GET_CODE (x
) != MEM
)
8978 output_operand_lossage ("invalid %%f operand");
8979 output_address (XEXP (x
, 0));
8984 /* Print a sign-extended 32-bit value. */
8986 if (GET_CODE(x
) == CONST_INT
)
8988 else if (GET_CODE(x
) == CONST_DOUBLE
)
8989 i
= CONST_DOUBLE_LOW (x
);
8992 output_operand_lossage ("invalid %%s operand");
8995 i
= trunc_int_for_mode (i
, SImode
);
8996 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9001 /* Do nothing special. */
9005 /* Undocumented flag. */
9006 output_operand_lossage ("invalid operand output code");
9009 if (GET_CODE (x
) == REG
)
9010 fputs (reg_names
[REGNO (x
)], file
);
9011 else if (GET_CODE (x
) == MEM
)
9014 /* Poor Sun assembler doesn't understand absolute addressing. */
9015 if (CONSTANT_P (XEXP (x
, 0)))
9016 fputs ("%g0+", file
);
9017 output_address (XEXP (x
, 0));
9020 else if (GET_CODE (x
) == HIGH
)
9022 fputs ("%hi(", file
);
9023 output_addr_const (file
, XEXP (x
, 0));
9026 else if (GET_CODE (x
) == LO_SUM
)
9028 sparc_print_operand (file
, XEXP (x
, 0), 0);
9029 if (TARGET_CM_MEDMID
)
9030 fputs ("+%l44(", file
);
9032 fputs ("+%lo(", file
);
9033 output_addr_const (file
, XEXP (x
, 1));
9036 else if (GET_CODE (x
) == CONST_DOUBLE
9037 && (GET_MODE (x
) == VOIDmode
9038 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
9040 if (CONST_DOUBLE_HIGH (x
) == 0)
9041 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
9042 else if (CONST_DOUBLE_HIGH (x
) == -1
9043 && CONST_DOUBLE_LOW (x
) < 0)
9044 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
9046 output_operand_lossage ("long long constant not a valid immediate operand");
9048 else if (GET_CODE (x
) == CONST_DOUBLE
)
9049 output_operand_lossage ("floating point constant not a valid immediate operand");
9050 else { output_addr_const (file
, x
); }
9053 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9056 sparc_print_operand_address (FILE *file
, rtx x
)
9058 register rtx base
, index
= 0;
9060 register rtx addr
= x
;
9063 fputs (reg_names
[REGNO (addr
)], file
);
9064 else if (GET_CODE (addr
) == PLUS
)
9066 if (CONST_INT_P (XEXP (addr
, 0)))
9067 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9068 else if (CONST_INT_P (XEXP (addr
, 1)))
9069 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9071 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9072 if (GET_CODE (base
) == LO_SUM
)
9074 gcc_assert (USE_AS_OFFSETABLE_LO10
9076 && ! TARGET_CM_MEDMID
);
9077 output_operand (XEXP (base
, 0), 0);
9078 fputs ("+%lo(", file
);
9079 output_address (XEXP (base
, 1));
9080 fprintf (file
, ")+%d", offset
);
9084 fputs (reg_names
[REGNO (base
)], file
);
9086 fprintf (file
, "%+d", offset
);
9087 else if (REG_P (index
))
9088 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9089 else if (GET_CODE (index
) == SYMBOL_REF
9090 || GET_CODE (index
) == LABEL_REF
9091 || GET_CODE (index
) == CONST
)
9092 fputc ('+', file
), output_addr_const (file
, index
);
9093 else gcc_unreachable ();
9096 else if (GET_CODE (addr
) == MINUS
9097 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9099 output_addr_const (file
, XEXP (addr
, 0));
9101 output_addr_const (file
, XEXP (addr
, 1));
9102 fputs ("-.)", file
);
9104 else if (GET_CODE (addr
) == LO_SUM
)
9106 output_operand (XEXP (addr
, 0), 0);
9107 if (TARGET_CM_MEDMID
)
9108 fputs ("+%l44(", file
);
9110 fputs ("+%lo(", file
);
9111 output_address (XEXP (addr
, 1));
9115 && GET_CODE (addr
) == CONST
9116 && GET_CODE (XEXP (addr
, 0)) == MINUS
9117 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9118 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9119 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9121 addr
= XEXP (addr
, 0);
9122 output_addr_const (file
, XEXP (addr
, 0));
9123 /* Group the args of the second CONST in parenthesis. */
9125 /* Skip past the second CONST--it does nothing for us. */
9126 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9127 /* Close the parenthesis. */
9132 output_addr_const (file
, addr
);
9136 /* Target hook for assembling integer objects. The sparc version has
9137 special handling for aligned DI-mode objects. */
9140 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9142 /* ??? We only output .xword's for symbols and only then in environments
9143 where the assembler can handle them. */
9144 if (aligned_p
&& size
== 8
9145 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
9149 assemble_integer_with_op ("\t.xword\t", x
);
9154 assemble_aligned_integer (4, const0_rtx
);
9155 assemble_aligned_integer (4, x
);
9159 return default_assemble_integer (x
, size
, aligned_p
);
9162 /* Return the value of a code used in the .proc pseudo-op that says
9163 what kind of result this function returns. For non-C types, we pick
9164 the closest C type. */
9166 #ifndef SHORT_TYPE_SIZE
9167 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9170 #ifndef INT_TYPE_SIZE
9171 #define INT_TYPE_SIZE BITS_PER_WORD
9174 #ifndef LONG_TYPE_SIZE
9175 #define LONG_TYPE_SIZE BITS_PER_WORD
9178 #ifndef LONG_LONG_TYPE_SIZE
9179 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9182 #ifndef FLOAT_TYPE_SIZE
9183 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9186 #ifndef DOUBLE_TYPE_SIZE
9187 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9190 #ifndef LONG_DOUBLE_TYPE_SIZE
9191 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9195 sparc_type_code (register tree type
)
9197 register unsigned long qualifiers
= 0;
9198 register unsigned shift
;
9200 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9201 setting more, since some assemblers will give an error for this. Also,
9202 we must be careful to avoid shifts of 32 bits or more to avoid getting
9203 unpredictable results. */
9205 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9207 switch (TREE_CODE (type
))
9213 qualifiers
|= (3 << shift
);
9218 qualifiers
|= (2 << shift
);
9222 case REFERENCE_TYPE
:
9224 qualifiers
|= (1 << shift
);
9228 return (qualifiers
| 8);
9231 case QUAL_UNION_TYPE
:
9232 return (qualifiers
| 9);
9235 return (qualifiers
| 10);
9238 return (qualifiers
| 16);
9241 /* If this is a range type, consider it to be the underlying
9243 if (TREE_TYPE (type
) != 0)
9246 /* Carefully distinguish all the standard types of C,
9247 without messing up if the language is not C. We do this by
9248 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9249 look at both the names and the above fields, but that's redundant.
9250 Any type whose size is between two C types will be considered
9251 to be the wider of the two types. Also, we do not have a
9252 special code to use for "long long", so anything wider than
9253 long is treated the same. Note that we can't distinguish
9254 between "int" and "long" in this code if they are the same
9255 size, but that's fine, since neither can the assembler. */
9257 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9258 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9260 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9261 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9263 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9264 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9267 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9270 /* If this is a range type, consider it to be the underlying
9272 if (TREE_TYPE (type
) != 0)
9275 /* Carefully distinguish all the standard types of C,
9276 without messing up if the language is not C. */
9278 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9279 return (qualifiers
| 6);
9282 return (qualifiers
| 7);
9284 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9285 /* ??? We need to distinguish between double and float complex types,
9286 but I don't know how yet because I can't reach this code from
9287 existing front-ends. */
9288 return (qualifiers
| 7); /* Who knows? */
9291 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9297 gcc_unreachable (); /* Not a type! */
9304 /* Nested function support. */
9306 /* Emit RTL insns to initialize the variable parts of a trampoline.
9307 FNADDR is an RTX for the address of the function's pure code.
9308 CXT is an RTX for the static chain value for the function.
9310 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9311 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9312 (to store insns). This is a bit excessive. Perhaps a different
9313 mechanism would be better here.
9315 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9318 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9320 /* SPARC 32-bit trampoline:
9323 sethi %hi(static), %g2
9325 or %g2, %lo(static), %g2
9327 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9328 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9332 (adjust_address (m_tramp
, SImode
, 0),
9333 expand_binop (SImode
, ior_optab
,
9334 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9335 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9336 NULL_RTX
, 1, OPTAB_DIRECT
));
9339 (adjust_address (m_tramp
, SImode
, 4),
9340 expand_binop (SImode
, ior_optab
,
9341 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9342 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9343 NULL_RTX
, 1, OPTAB_DIRECT
));
9346 (adjust_address (m_tramp
, SImode
, 8),
9347 expand_binop (SImode
, ior_optab
,
9348 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9349 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9350 NULL_RTX
, 1, OPTAB_DIRECT
));
9353 (adjust_address (m_tramp
, SImode
, 12),
9354 expand_binop (SImode
, ior_optab
,
9355 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9356 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9357 NULL_RTX
, 1, OPTAB_DIRECT
));
9359 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9360 aligned on a 16 byte boundary so one flush clears it all. */
9361 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9362 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9363 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9364 && sparc_cpu
!= PROCESSOR_NIAGARA
9365 && sparc_cpu
!= PROCESSOR_NIAGARA2
9366 && sparc_cpu
!= PROCESSOR_NIAGARA3
9367 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9368 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9370 /* Call __enable_execute_stack after writing onto the stack to make sure
9371 the stack address is accessible. */
9372 #ifdef HAVE_ENABLE_EXECUTE_STACK
9373 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9374 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9379 /* The 64-bit version is simpler because it makes more sense to load the
9380 values as "immediate" data out of the trampoline. It's also easier since
9381 we can read the PC without clobbering a register. */
9384 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9386 /* SPARC 64-bit trampoline:
9395 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9396 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9397 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9398 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9399 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9400 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9401 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9402 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9403 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9404 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9405 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9407 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9408 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9409 && sparc_cpu
!= PROCESSOR_NIAGARA
9410 && sparc_cpu
!= PROCESSOR_NIAGARA2
9411 && sparc_cpu
!= PROCESSOR_NIAGARA3
9412 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9413 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9415 /* Call __enable_execute_stack after writing onto the stack to make sure
9416 the stack address is accessible. */
9417 #ifdef HAVE_ENABLE_EXECUTE_STACK
9418 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9419 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9423 /* Worker for TARGET_TRAMPOLINE_INIT. */
9426 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9428 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9429 cxt
= force_reg (Pmode
, cxt
);
9431 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9433 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9436 /* Adjust the cost of a scheduling dependency. Return the new cost of
9437 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9440 supersparc_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
9442 enum attr_type insn_type
;
9444 if (! recog_memoized (insn
))
9447 insn_type
= get_attr_type (insn
);
9449 if (REG_NOTE_KIND (link
) == 0)
9451 /* Data dependency; DEP_INSN writes a register that INSN reads some
9454 /* if a load, then the dependence must be on the memory address;
9455 add an extra "cycle". Note that the cost could be two cycles
9456 if the reg was written late in an instruction group; we ca not tell
9458 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9461 /* Get the delay only if the address of the store is the dependence. */
9462 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9464 rtx pat
= PATTERN(insn
);
9465 rtx dep_pat
= PATTERN (dep_insn
);
9467 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9468 return cost
; /* This should not happen! */
9470 /* The dependency between the two instructions was on the data that
9471 is being stored. Assume that this implies that the address of the
9472 store is not dependent. */
9473 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9476 return cost
+ 3; /* An approximation. */
9479 /* A shift instruction cannot receive its data from an instruction
9480 in the same cycle; add a one cycle penalty. */
9481 if (insn_type
== TYPE_SHIFT
)
9482 return cost
+ 3; /* Split before cascade into shift. */
9486 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9487 INSN writes some cycles later. */
9489 /* These are only significant for the fpu unit; writing a fp reg before
9490 the fpu has finished with it stalls the processor. */
9492 /* Reusing an integer register causes no problems. */
9493 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9501 hypersparc_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
9503 enum attr_type insn_type
, dep_type
;
9504 rtx pat
= PATTERN(insn
);
9505 rtx dep_pat
= PATTERN (dep_insn
);
9507 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9510 insn_type
= get_attr_type (insn
);
9511 dep_type
= get_attr_type (dep_insn
);
9513 switch (REG_NOTE_KIND (link
))
9516 /* Data dependency; DEP_INSN writes a register that INSN reads some
9523 /* Get the delay iff the address of the store is the dependence. */
9524 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9527 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9534 /* If a load, then the dependence must be on the memory address. If
9535 the addresses aren't equal, then it might be a false dependency */
9536 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9538 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9539 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9540 || GET_CODE (SET_SRC (pat
)) != MEM
9541 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9542 XEXP (SET_SRC (pat
), 0)))
9550 /* Compare to branch latency is 0. There is no benefit from
9551 separating compare and branch. */
9552 if (dep_type
== TYPE_COMPARE
)
9554 /* Floating point compare to branch latency is less than
9555 compare to conditional move. */
9556 if (dep_type
== TYPE_FPCMP
)
9565 /* Anti-dependencies only penalize the fpu unit. */
9566 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9578 sparc_adjust_cost(rtx_insn
*insn
, rtx link
, rtx_insn
*dep
, int cost
)
9582 case PROCESSOR_SUPERSPARC
:
9583 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
9585 case PROCESSOR_HYPERSPARC
:
9586 case PROCESSOR_SPARCLITE86X
:
9587 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
9596 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9597 int sched_verbose ATTRIBUTE_UNUSED
,
9598 int max_ready ATTRIBUTE_UNUSED
)
9602 sparc_use_sched_lookahead (void)
9604 if (sparc_cpu
== PROCESSOR_NIAGARA
9605 || sparc_cpu
== PROCESSOR_NIAGARA2
9606 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9608 if (sparc_cpu
== PROCESSOR_NIAGARA4
)
9610 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9611 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9613 if ((1 << sparc_cpu
) &
9614 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9615 (1 << PROCESSOR_SPARCLITE86X
)))
9621 sparc_issue_rate (void)
9625 case PROCESSOR_NIAGARA
:
9626 case PROCESSOR_NIAGARA2
:
9627 case PROCESSOR_NIAGARA3
:
9630 case PROCESSOR_NIAGARA4
:
9632 /* Assume V9 processors are capable of at least dual-issue. */
9634 case PROCESSOR_SUPERSPARC
:
9636 case PROCESSOR_HYPERSPARC
:
9637 case PROCESSOR_SPARCLITE86X
:
9639 case PROCESSOR_ULTRASPARC
:
9640 case PROCESSOR_ULTRASPARC3
:
9646 set_extends (rtx_insn
*insn
)
9648 register rtx pat
= PATTERN (insn
);
9650 switch (GET_CODE (SET_SRC (pat
)))
9652 /* Load and some shift instructions zero extend. */
9655 /* sethi clears the high bits */
9657 /* LO_SUM is used with sethi. sethi cleared the high
9658 bits and the values used with lo_sum are positive */
9660 /* Store flag stores 0 or 1 */
9670 rtx op0
= XEXP (SET_SRC (pat
), 0);
9671 rtx op1
= XEXP (SET_SRC (pat
), 1);
9672 if (GET_CODE (op1
) == CONST_INT
)
9673 return INTVAL (op1
) >= 0;
9674 if (GET_CODE (op0
) != REG
)
9676 if (sparc_check_64 (op0
, insn
) == 1)
9678 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9683 rtx op0
= XEXP (SET_SRC (pat
), 0);
9684 rtx op1
= XEXP (SET_SRC (pat
), 1);
9685 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9687 if (GET_CODE (op1
) == CONST_INT
)
9688 return INTVAL (op1
) >= 0;
9689 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9692 return GET_MODE (SET_SRC (pat
)) == SImode
;
9693 /* Positive integers leave the high bits zero. */
9695 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
9697 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
9700 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9702 return sparc_check_64 (SET_SRC (pat
), insn
);
9708 /* We _ought_ to have only one kind per function, but... */
9709 static GTY(()) rtx sparc_addr_diff_list
;
9710 static GTY(()) rtx sparc_addr_list
;
9713 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9715 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9717 sparc_addr_diff_list
9718 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9720 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9724 sparc_output_addr_vec (rtx vec
)
9726 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9727 int idx
, vlen
= XVECLEN (body
, 0);
9729 #ifdef ASM_OUTPUT_ADDR_VEC_START
9730 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9733 #ifdef ASM_OUTPUT_CASE_LABEL
9734 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9737 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9740 for (idx
= 0; idx
< vlen
; idx
++)
9742 ASM_OUTPUT_ADDR_VEC_ELT
9743 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9746 #ifdef ASM_OUTPUT_ADDR_VEC_END
9747 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9752 sparc_output_addr_diff_vec (rtx vec
)
9754 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9755 rtx base
= XEXP (XEXP (body
, 0), 0);
9756 int idx
, vlen
= XVECLEN (body
, 1);
9758 #ifdef ASM_OUTPUT_ADDR_VEC_START
9759 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9762 #ifdef ASM_OUTPUT_CASE_LABEL
9763 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9766 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9769 for (idx
= 0; idx
< vlen
; idx
++)
9771 ASM_OUTPUT_ADDR_DIFF_ELT
9774 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9775 CODE_LABEL_NUMBER (base
));
9778 #ifdef ASM_OUTPUT_ADDR_VEC_END
9779 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9784 sparc_output_deferred_case_vectors (void)
9789 if (sparc_addr_list
== NULL_RTX
9790 && sparc_addr_diff_list
== NULL_RTX
)
9793 /* Align to cache line in the function's code section. */
9794 switch_to_section (current_function_section ());
9796 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9798 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9800 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9801 sparc_output_addr_vec (XEXP (t
, 0));
9802 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9803 sparc_output_addr_diff_vec (XEXP (t
, 0));
9805 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9808 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9809 unknown. Return 1 if the high bits are zero, -1 if the register is
9812 sparc_check_64 (rtx x
, rtx_insn
*insn
)
9814 /* If a register is set only once it is safe to ignore insns this
9815 code does not know how to handle. The loop will either recognize
9816 the single set and return the correct value or fail to recognize
9821 gcc_assert (GET_CODE (x
) == REG
);
9823 if (GET_MODE (x
) == DImode
)
9824 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9826 if (flag_expensive_optimizations
9827 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9833 insn
= get_last_insn_anywhere ();
9838 while ((insn
= PREV_INSN (insn
)))
9840 switch (GET_CODE (insn
))
9853 rtx pat
= PATTERN (insn
);
9854 if (GET_CODE (pat
) != SET
)
9856 if (rtx_equal_p (x
, SET_DEST (pat
)))
9857 return set_extends (insn
);
9858 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9859 return set_extends (insn
);
9860 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9868 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9869 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9872 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
9874 static char asm_code
[60];
9876 /* The scratch register is only required when the destination
9877 register is not a 64-bit global or out register. */
9878 if (which_alternative
!= 2)
9879 operands
[3] = operands
[0];
9881 /* We can only shift by constants <= 63. */
9882 if (GET_CODE (operands
[2]) == CONST_INT
)
9883 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9885 if (GET_CODE (operands
[1]) == CONST_INT
)
9887 output_asm_insn ("mov\t%1, %3", operands
);
9891 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9892 if (sparc_check_64 (operands
[1], insn
) <= 0)
9893 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9894 output_asm_insn ("or\t%L1, %3, %3", operands
);
9897 strcpy (asm_code
, opcode
);
9899 if (which_alternative
!= 2)
9900 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9903 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9906 /* Output rtl to increment the profiler label LABELNO
9907 for profiling a function entry. */
9910 sparc_profile_hook (int labelno
)
9915 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9916 if (NO_PROFILE_COUNTERS
)
9918 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9922 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9923 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9924 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9928 #ifdef TARGET_SOLARIS
9929 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9932 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9933 tree decl ATTRIBUTE_UNUSED
)
9935 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9937 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9941 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9943 if (!(flags
& SECTION_DEBUG
))
9944 fputs (",#alloc", asm_out_file
);
9945 if (flags
& SECTION_WRITE
)
9946 fputs (",#write", asm_out_file
);
9947 if (flags
& SECTION_TLS
)
9948 fputs (",#tls", asm_out_file
);
9949 if (flags
& SECTION_CODE
)
9950 fputs (",#execinstr", asm_out_file
);
9952 /* Sun as only supports #nobits/#progbits since Solaris 10. */
9953 if (HAVE_AS_SPARC_NOBITS
)
9955 if (flags
& SECTION_BSS
)
9956 fputs (",#nobits", asm_out_file
);
9958 fputs (",#progbits", asm_out_file
);
9961 fputc ('\n', asm_out_file
);
9963 #endif /* TARGET_SOLARIS */
9965 /* We do not allow indirect calls to be optimized into sibling calls.
9967 We cannot use sibling calls when delayed branches are disabled
9968 because they will likely require the call delay slot to be filled.
9970 Also, on SPARC 32-bit we cannot emit a sibling call when the
9971 current function returns a structure. This is because the "unimp
9972 after call" convention would cause the callee to return to the
9973 wrong place. The generic code already disallows cases where the
9974 function being called returns a structure.
9976 It may seem strange how this last case could occur. Usually there
9977 is code after the call which jumps to epilogue code which dumps the
9978 return value into the struct return area. That ought to invalidate
9979 the sibling call right? Well, in the C++ case we can end up passing
9980 the pointer to the struct return area to a constructor (which returns
9981 void) and then nothing else happens. Such a sibling call would look
9982 valid without the added check here.
9984 VxWorks PIC PLT entries require the global pointer to be initialized
9985 on entry. We therefore can't emit sibling calls to them. */
9987 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9990 && flag_delayed_branch
9991 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9992 && !(TARGET_VXWORKS_RTP
9994 && !targetm
.binds_local_p (decl
)));
9997 /* libfunc renaming. */
10000 sparc_init_libfuncs (void)
10004 /* Use the subroutines that Sun's library provides for integer
10005 multiply and divide. The `*' prevents an underscore from
10006 being prepended by the compiler. .umul is a little faster
10008 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10009 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10010 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10011 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10012 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10014 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10015 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10016 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10017 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10018 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10019 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10021 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10022 is because with soft-float, the SFmode and DFmode sqrt
10023 instructions will be absent, and the compiler will notice and
10024 try to use the TFmode sqrt instruction for calls to the
10025 builtin function sqrt, but this fails. */
10027 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10029 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10030 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10031 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10032 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10033 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10034 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10036 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10037 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10038 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10039 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10041 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10042 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10043 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10044 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10046 if (DITF_CONVERSION_LIBFUNCS
)
10048 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10049 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10050 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10051 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10054 if (SUN_CONVERSION_LIBFUNCS
)
10056 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10057 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10058 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10059 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10064 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10065 do not exist in the library. Make sure the compiler does not
10066 emit calls to them by accident. (It should always use the
10067 hardware instructions.) */
10068 set_optab_libfunc (smul_optab
, SImode
, 0);
10069 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10070 set_optab_libfunc (udiv_optab
, SImode
, 0);
10071 set_optab_libfunc (smod_optab
, SImode
, 0);
10072 set_optab_libfunc (umod_optab
, SImode
, 0);
10074 if (SUN_INTEGER_MULTIPLY_64
)
10076 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10077 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10078 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10079 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10080 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10083 if (SUN_CONVERSION_LIBFUNCS
)
10085 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10086 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10087 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10088 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10093 /* SPARC builtins. */
10094 enum sparc_builtins
10096 /* FPU builtins. */
10097 SPARC_BUILTIN_LDFSR
,
10098 SPARC_BUILTIN_STFSR
,
10100 /* VIS 1.0 builtins. */
10101 SPARC_BUILTIN_FPACK16
,
10102 SPARC_BUILTIN_FPACK32
,
10103 SPARC_BUILTIN_FPACKFIX
,
10104 SPARC_BUILTIN_FEXPAND
,
10105 SPARC_BUILTIN_FPMERGE
,
10106 SPARC_BUILTIN_FMUL8X16
,
10107 SPARC_BUILTIN_FMUL8X16AU
,
10108 SPARC_BUILTIN_FMUL8X16AL
,
10109 SPARC_BUILTIN_FMUL8SUX16
,
10110 SPARC_BUILTIN_FMUL8ULX16
,
10111 SPARC_BUILTIN_FMULD8SUX16
,
10112 SPARC_BUILTIN_FMULD8ULX16
,
10113 SPARC_BUILTIN_FALIGNDATAV4HI
,
10114 SPARC_BUILTIN_FALIGNDATAV8QI
,
10115 SPARC_BUILTIN_FALIGNDATAV2SI
,
10116 SPARC_BUILTIN_FALIGNDATADI
,
10117 SPARC_BUILTIN_WRGSR
,
10118 SPARC_BUILTIN_RDGSR
,
10119 SPARC_BUILTIN_ALIGNADDR
,
10120 SPARC_BUILTIN_ALIGNADDRL
,
10121 SPARC_BUILTIN_PDIST
,
10122 SPARC_BUILTIN_EDGE8
,
10123 SPARC_BUILTIN_EDGE8L
,
10124 SPARC_BUILTIN_EDGE16
,
10125 SPARC_BUILTIN_EDGE16L
,
10126 SPARC_BUILTIN_EDGE32
,
10127 SPARC_BUILTIN_EDGE32L
,
10128 SPARC_BUILTIN_FCMPLE16
,
10129 SPARC_BUILTIN_FCMPLE32
,
10130 SPARC_BUILTIN_FCMPNE16
,
10131 SPARC_BUILTIN_FCMPNE32
,
10132 SPARC_BUILTIN_FCMPGT16
,
10133 SPARC_BUILTIN_FCMPGT32
,
10134 SPARC_BUILTIN_FCMPEQ16
,
10135 SPARC_BUILTIN_FCMPEQ32
,
10136 SPARC_BUILTIN_FPADD16
,
10137 SPARC_BUILTIN_FPADD16S
,
10138 SPARC_BUILTIN_FPADD32
,
10139 SPARC_BUILTIN_FPADD32S
,
10140 SPARC_BUILTIN_FPSUB16
,
10141 SPARC_BUILTIN_FPSUB16S
,
10142 SPARC_BUILTIN_FPSUB32
,
10143 SPARC_BUILTIN_FPSUB32S
,
10144 SPARC_BUILTIN_ARRAY8
,
10145 SPARC_BUILTIN_ARRAY16
,
10146 SPARC_BUILTIN_ARRAY32
,
10148 /* VIS 2.0 builtins. */
10149 SPARC_BUILTIN_EDGE8N
,
10150 SPARC_BUILTIN_EDGE8LN
,
10151 SPARC_BUILTIN_EDGE16N
,
10152 SPARC_BUILTIN_EDGE16LN
,
10153 SPARC_BUILTIN_EDGE32N
,
10154 SPARC_BUILTIN_EDGE32LN
,
10155 SPARC_BUILTIN_BMASK
,
10156 SPARC_BUILTIN_BSHUFFLEV4HI
,
10157 SPARC_BUILTIN_BSHUFFLEV8QI
,
10158 SPARC_BUILTIN_BSHUFFLEV2SI
,
10159 SPARC_BUILTIN_BSHUFFLEDI
,
10161 /* VIS 3.0 builtins. */
10162 SPARC_BUILTIN_CMASK8
,
10163 SPARC_BUILTIN_CMASK16
,
10164 SPARC_BUILTIN_CMASK32
,
10165 SPARC_BUILTIN_FCHKSM16
,
10166 SPARC_BUILTIN_FSLL16
,
10167 SPARC_BUILTIN_FSLAS16
,
10168 SPARC_BUILTIN_FSRL16
,
10169 SPARC_BUILTIN_FSRA16
,
10170 SPARC_BUILTIN_FSLL32
,
10171 SPARC_BUILTIN_FSLAS32
,
10172 SPARC_BUILTIN_FSRL32
,
10173 SPARC_BUILTIN_FSRA32
,
10174 SPARC_BUILTIN_PDISTN
,
10175 SPARC_BUILTIN_FMEAN16
,
10176 SPARC_BUILTIN_FPADD64
,
10177 SPARC_BUILTIN_FPSUB64
,
10178 SPARC_BUILTIN_FPADDS16
,
10179 SPARC_BUILTIN_FPADDS16S
,
10180 SPARC_BUILTIN_FPSUBS16
,
10181 SPARC_BUILTIN_FPSUBS16S
,
10182 SPARC_BUILTIN_FPADDS32
,
10183 SPARC_BUILTIN_FPADDS32S
,
10184 SPARC_BUILTIN_FPSUBS32
,
10185 SPARC_BUILTIN_FPSUBS32S
,
10186 SPARC_BUILTIN_FUCMPLE8
,
10187 SPARC_BUILTIN_FUCMPNE8
,
10188 SPARC_BUILTIN_FUCMPGT8
,
10189 SPARC_BUILTIN_FUCMPEQ8
,
10190 SPARC_BUILTIN_FHADDS
,
10191 SPARC_BUILTIN_FHADDD
,
10192 SPARC_BUILTIN_FHSUBS
,
10193 SPARC_BUILTIN_FHSUBD
,
10194 SPARC_BUILTIN_FNHADDS
,
10195 SPARC_BUILTIN_FNHADDD
,
10196 SPARC_BUILTIN_UMULXHI
,
10197 SPARC_BUILTIN_XMULX
,
10198 SPARC_BUILTIN_XMULXHI
,
10203 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10204 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10206 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10207 function decl or NULL_TREE if the builtin was not added. */
10210 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10214 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10218 sparc_builtins
[code
] = t
;
10219 sparc_builtins_icode
[code
] = icode
;
10225 /* Likewise, but also marks the function as "const". */
10228 def_builtin_const (const char *name
, enum insn_code icode
,
10229 enum sparc_builtins code
, tree type
)
10231 tree t
= def_builtin (name
, icode
, code
, type
);
10234 TREE_READONLY (t
) = 1;
10239 /* Implement the TARGET_INIT_BUILTINS target hook.
10240 Create builtin functions for special SPARC instructions. */
10243 sparc_init_builtins (void)
10246 sparc_fpu_init_builtins ();
10249 sparc_vis_init_builtins ();
10252 /* Create builtin functions for FPU instructions. */
10255 sparc_fpu_init_builtins (void)
10258 = build_function_type_list (void_type_node
,
10259 build_pointer_type (unsigned_type_node
), 0);
10260 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10261 SPARC_BUILTIN_LDFSR
, ftype
);
10262 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10263 SPARC_BUILTIN_STFSR
, ftype
);
10266 /* Create builtin functions for VIS instructions. */
10269 sparc_vis_init_builtins (void)
10271 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10272 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10273 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10274 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10275 tree v2si
= build_vector_type (intSI_type_node
, 2);
10276 tree v1si
= build_vector_type (intSI_type_node
, 1);
10278 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10279 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10280 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10281 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10282 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10283 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10284 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10285 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10286 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10287 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10288 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10289 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10290 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10291 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10292 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10294 intDI_type_node
, 0);
10295 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10297 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10299 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10301 intDI_type_node
, 0);
10302 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10304 intSI_type_node
, 0);
10305 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10307 intSI_type_node
, 0);
10308 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10310 intDI_type_node
, 0);
10311 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10314 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10317 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10319 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10321 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10323 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10325 tree void_ftype_di
= build_function_type_list (void_type_node
,
10326 intDI_type_node
, 0);
10327 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10328 void_type_node
, 0);
10329 tree void_ftype_si
= build_function_type_list (void_type_node
,
10330 intSI_type_node
, 0);
10331 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10333 float_type_node
, 0);
10334 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10336 double_type_node
, 0);
10338 /* Packing and expanding vectors. */
10339 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10340 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10341 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10342 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10343 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10344 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10345 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10346 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10347 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10348 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10350 /* Multiplications. */
10351 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10352 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10353 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10354 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10355 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10356 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10357 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10358 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10359 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10360 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10361 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10362 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10363 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10364 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10366 /* Data aligning. */
10367 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10368 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10369 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10370 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10371 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10372 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10373 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10374 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10376 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10377 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10378 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10379 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10383 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10384 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10385 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10386 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10390 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10391 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10392 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10393 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10396 /* Pixel distance. */
10397 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10398 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10400 /* Edge handling. */
10403 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10404 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10405 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10406 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10407 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10408 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10409 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10410 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10411 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10412 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10413 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10414 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10418 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10419 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10420 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10421 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10422 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10423 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10424 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10425 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10426 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10427 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10428 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10429 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10432 /* Pixel compare. */
10435 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10436 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10437 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10438 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10439 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10440 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10441 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10442 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10443 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10444 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10445 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10446 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10447 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10448 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10449 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10450 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10454 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10455 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10456 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10457 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10458 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10459 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10460 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10461 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10462 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10463 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10464 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10465 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10466 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10467 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10468 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10469 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10472 /* Addition and subtraction. */
10473 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10474 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10475 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10476 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10477 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10478 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10479 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10480 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10481 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10482 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10483 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10484 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10485 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10486 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10487 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10488 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10490 /* Three-dimensional array addressing. */
10493 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10494 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10495 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10496 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10497 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10498 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10502 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10503 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10504 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10505 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10506 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10507 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10512 /* Edge handling. */
10515 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10516 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10517 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10518 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10519 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10520 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10521 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10522 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10523 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10524 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10525 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10526 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10530 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10531 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10532 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10533 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10534 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10535 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10536 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10537 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10538 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10539 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10540 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10541 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10544 /* Byte mask and shuffle. */
10546 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10547 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10549 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10550 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10551 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10552 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10553 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10554 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10555 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10556 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10557 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10558 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10565 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10566 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10567 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10568 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10569 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10570 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10574 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10575 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10576 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10577 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10578 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10579 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10582 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10583 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10585 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10586 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10587 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10588 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10589 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10590 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10591 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10592 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10593 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10594 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10595 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10596 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10597 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10598 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10599 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10600 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10603 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10604 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10606 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10607 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10609 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10610 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10611 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10612 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10613 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10614 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10616 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10617 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10618 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10619 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10620 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10621 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10622 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10623 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10624 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10625 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10626 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10627 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10628 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10629 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10630 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10631 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10635 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10636 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10637 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10638 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10639 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10640 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10641 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10642 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10646 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10647 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10648 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10649 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
10650 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10651 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
10652 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10653 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
10656 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10657 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
10658 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10659 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
10660 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10661 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
10662 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10663 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
10664 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10665 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
10666 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10667 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
10669 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10670 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
10671 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10672 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
10673 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10674 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
10678 /* Implement TARGET_BUILTIN_DECL hook. */
10681 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10683 if (code
>= SPARC_BUILTIN_MAX
)
10684 return error_mark_node
;
10686 return sparc_builtins
[code
];
10689 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10692 sparc_expand_builtin (tree exp
, rtx target
,
10693 rtx subtarget ATTRIBUTE_UNUSED
,
10694 machine_mode tmode ATTRIBUTE_UNUSED
,
10695 int ignore ATTRIBUTE_UNUSED
)
10697 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10698 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10699 enum insn_code icode
= sparc_builtins_icode
[code
];
10700 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10701 call_expr_arg_iterator iter
;
10708 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10710 || GET_MODE (target
) != tmode
10711 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10712 op
[0] = gen_reg_rtx (tmode
);
10717 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10719 const struct insn_operand_data
*insn_op
;
10722 if (arg
== error_mark_node
)
10726 idx
= arg_count
- !nonvoid
;
10727 insn_op
= &insn_data
[icode
].operand
[idx
];
10728 op
[arg_count
] = expand_normal (arg
);
10730 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
10732 if (!address_operand (op
[arg_count
], SImode
))
10734 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
10735 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
10737 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
10740 else if (insn_op
->mode
== V1DImode
10741 && GET_MODE (op
[arg_count
]) == DImode
)
10742 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10744 else if (insn_op
->mode
== V1SImode
10745 && GET_MODE (op
[arg_count
]) == SImode
)
10746 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10748 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10750 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10756 pat
= GEN_FCN (icode
) (op
[0]);
10760 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10762 pat
= GEN_FCN (icode
) (op
[1]);
10765 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10768 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10771 gcc_unreachable ();
10779 return (nonvoid
? op
[0] : const0_rtx
);
10782 /* Return the upper 16 bits of the 8x16 multiplication. */
10785 sparc_vis_mul8x16 (int e8
, int e16
)
10787 return (e8
* e16
+ 128) / 256;
10790 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10791 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10794 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
10795 tree inner_type
, tree cst0
, tree cst1
)
10797 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10802 case SPARC_BUILTIN_FMUL8X16
:
10803 for (i
= 0; i
< num
; ++i
)
10806 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10807 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10808 n_elts
[i
] = build_int_cst (inner_type
, val
);
10812 case SPARC_BUILTIN_FMUL8X16AU
:
10813 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10815 for (i
= 0; i
< num
; ++i
)
10818 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10820 n_elts
[i
] = build_int_cst (inner_type
, val
);
10824 case SPARC_BUILTIN_FMUL8X16AL
:
10825 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10827 for (i
= 0; i
< num
; ++i
)
10830 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10832 n_elts
[i
] = build_int_cst (inner_type
, val
);
10837 gcc_unreachable ();
10841 /* Implement TARGET_FOLD_BUILTIN hook.
10843 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10844 result of the function call is ignored. NULL_TREE is returned if the
10845 function could not be folded. */
10848 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10849 tree
*args
, bool ignore
)
10851 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10852 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10853 tree arg0
, arg1
, arg2
;
10858 case SPARC_BUILTIN_LDFSR
:
10859 case SPARC_BUILTIN_STFSR
:
10860 case SPARC_BUILTIN_ALIGNADDR
:
10861 case SPARC_BUILTIN_WRGSR
:
10862 case SPARC_BUILTIN_BMASK
:
10863 case SPARC_BUILTIN_CMASK8
:
10864 case SPARC_BUILTIN_CMASK16
:
10865 case SPARC_BUILTIN_CMASK32
:
10869 return build_zero_cst (rtype
);
10874 case SPARC_BUILTIN_FEXPAND
:
10878 if (TREE_CODE (arg0
) == VECTOR_CST
)
10880 tree inner_type
= TREE_TYPE (rtype
);
10884 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10885 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10886 n_elts
[i
] = build_int_cst (inner_type
,
10888 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10889 return build_vector (rtype
, n_elts
);
10893 case SPARC_BUILTIN_FMUL8X16
:
10894 case SPARC_BUILTIN_FMUL8X16AU
:
10895 case SPARC_BUILTIN_FMUL8X16AL
:
10901 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10903 tree inner_type
= TREE_TYPE (rtype
);
10904 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10905 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
10906 return build_vector (rtype
, n_elts
);
10910 case SPARC_BUILTIN_FPMERGE
:
10916 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10918 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10920 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10922 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10923 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10926 return build_vector (rtype
, n_elts
);
10930 case SPARC_BUILTIN_PDIST
:
10931 case SPARC_BUILTIN_PDISTN
:
10936 if (code
== SPARC_BUILTIN_PDIST
)
10942 arg2
= integer_zero_node
;
10944 if (TREE_CODE (arg0
) == VECTOR_CST
10945 && TREE_CODE (arg1
) == VECTOR_CST
10946 && TREE_CODE (arg2
) == INTEGER_CST
)
10948 bool overflow
= false;
10949 widest_int result
= wi::to_widest (arg2
);
10953 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10955 tree e0
= VECTOR_CST_ELT (arg0
, i
);
10956 tree e1
= VECTOR_CST_ELT (arg1
, i
);
10958 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10960 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
10961 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
10962 if (wi::neg_p (tmp
))
10963 tmp
= wi::neg (tmp
, &neg2_ovf
);
10966 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
10967 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
10970 gcc_assert (!overflow
);
10972 return wide_int_to_tree (rtype
, result
);
10982 /* ??? This duplicates information provided to the compiler by the
10983 ??? scheduler description. Some day, teach genautomata to output
10984 ??? the latencies and then CSE will just use that. */
10987 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
10988 int *total
, bool speed ATTRIBUTE_UNUSED
)
10990 machine_mode mode
= GET_MODE (x
);
10991 bool float_mode_p
= FLOAT_MODE_P (mode
);
10996 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
11014 if (GET_MODE (x
) == VOIDmode
11015 && ((CONST_DOUBLE_HIGH (x
) == 0
11016 && CONST_DOUBLE_LOW (x
) < 0x1000)
11017 || (CONST_DOUBLE_HIGH (x
) == -1
11018 && CONST_DOUBLE_LOW (x
) < 0
11019 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
11026 /* If outer-code was a sign or zero extension, a cost
11027 of COSTS_N_INSNS (1) was already added in. This is
11028 why we are subtracting it back out. */
11029 if (outer_code
== ZERO_EXTEND
)
11031 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11033 else if (outer_code
== SIGN_EXTEND
)
11035 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11037 else if (float_mode_p
)
11039 *total
= sparc_costs
->float_load
;
11043 *total
= sparc_costs
->int_load
;
11051 *total
= sparc_costs
->float_plusminus
;
11053 *total
= COSTS_N_INSNS (1);
11060 gcc_assert (float_mode_p
);
11061 *total
= sparc_costs
->float_mul
;
11064 if (GET_CODE (sub
) == NEG
)
11065 sub
= XEXP (sub
, 0);
11066 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
11069 if (GET_CODE (sub
) == NEG
)
11070 sub
= XEXP (sub
, 0);
11071 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
11077 *total
= sparc_costs
->float_mul
;
11078 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11079 *total
= COSTS_N_INSNS (25);
11085 if (sparc_costs
->int_mul_bit_factor
)
11089 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11091 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11092 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11095 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
11096 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
11098 rtx x1
= XEXP (x
, 1);
11099 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
11100 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
11102 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
11104 for (; value2
!= 0; value2
&= value2
- 1)
11112 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11113 bit_cost
= COSTS_N_INSNS (bit_cost
);
11116 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11117 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11119 *total
= sparc_costs
->int_mul
+ bit_cost
;
11126 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11135 if (mode
== DFmode
)
11136 *total
= sparc_costs
->float_div_df
;
11138 *total
= sparc_costs
->float_div_sf
;
11142 if (mode
== DImode
)
11143 *total
= sparc_costs
->int_divX
;
11145 *total
= sparc_costs
->int_div
;
11150 if (! float_mode_p
)
11152 *total
= COSTS_N_INSNS (1);
11159 case UNSIGNED_FLOAT
:
11163 case FLOAT_TRUNCATE
:
11164 *total
= sparc_costs
->float_move
;
11168 if (mode
== DFmode
)
11169 *total
= sparc_costs
->float_sqrt_df
;
11171 *total
= sparc_costs
->float_sqrt_sf
;
11176 *total
= sparc_costs
->float_cmp
;
11178 *total
= COSTS_N_INSNS (1);
11183 *total
= sparc_costs
->float_cmove
;
11185 *total
= sparc_costs
->int_cmove
;
11189 /* Handle the NAND vector patterns. */
11190 if (sparc_vector_mode_supported_p (GET_MODE (x
))
11191 && GET_CODE (XEXP (x
, 0)) == NOT
11192 && GET_CODE (XEXP (x
, 1)) == NOT
)
11194 *total
= COSTS_N_INSNS (1);
11205 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11208 general_or_i64_p (reg_class_t rclass
)
11210 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11213 /* Implement TARGET_REGISTER_MOVE_COST. */
11216 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
11217 reg_class_t from
, reg_class_t to
)
11219 bool need_memory
= false;
11221 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11222 need_memory
= true;
11223 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11224 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11228 int size
= GET_MODE_SIZE (mode
);
11229 if (size
== 8 || size
== 4)
11231 if (! TARGET_ARCH32
|| size
== 4)
11237 need_memory
= true;
11242 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11243 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11244 || sparc_cpu
== PROCESSOR_NIAGARA
11245 || sparc_cpu
== PROCESSOR_NIAGARA2
11246 || sparc_cpu
== PROCESSOR_NIAGARA3
11247 || sparc_cpu
== PROCESSOR_NIAGARA4
)
11256 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11257 This is achieved by means of a manual dynamic stack space allocation in
11258 the current frame. We make the assumption that SEQ doesn't contain any
11259 function calls, with the possible exception of calls to the GOT helper. */
11262 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11264 /* We must preserve the lowest 16 words for the register save area. */
11265 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11266 /* We really need only 2 words of fresh stack space. */
11267 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11270 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11271 SPARC_STACK_BIAS
+ offset
));
11273 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11274 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
11276 emit_insn (gen_rtx_SET (VOIDmode
,
11277 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11281 emit_insn (gen_rtx_SET (VOIDmode
,
11283 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11284 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
11285 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11288 /* Output the assembler code for a thunk function. THUNK_DECL is the
11289 declaration for the thunk function itself, FUNCTION is the decl for
11290 the target function. DELTA is an immediate constant offset to be
11291 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11292 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11295 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11296 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11299 rtx this_rtx
, funexp
;
11301 unsigned int int_arg_first
;
11303 reload_completed
= 1;
11304 epilogue_completed
= 1;
11306 emit_note (NOTE_INSN_PROLOGUE_END
);
11310 sparc_leaf_function_p
= 1;
11312 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11314 else if (flag_delayed_branch
)
11316 /* We will emit a regular sibcall below, so we need to instruct
11317 output_sibcall that we are in a leaf function. */
11318 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11320 /* This will cause final.c to invoke leaf_renumber_regs so we
11321 must behave as if we were in a not-yet-leafified function. */
11322 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11326 /* We will emit the sibcall manually below, so we will need to
11327 manually spill non-leaf registers. */
11328 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11330 /* We really are in a leaf function. */
11331 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11334 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11335 returns a structure, the structure return pointer is there instead. */
11337 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11338 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11340 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11342 /* Add DELTA. When possible use a plain add, otherwise load it into
11343 a register first. */
11346 rtx delta_rtx
= GEN_INT (delta
);
11348 if (! SPARC_SIMM13_P (delta
))
11350 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11351 emit_move_insn (scratch
, delta_rtx
);
11352 delta_rtx
= scratch
;
11355 /* THIS_RTX += DELTA. */
11356 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11359 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11362 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11363 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11365 gcc_assert (vcall_offset
< 0);
11367 /* SCRATCH = *THIS_RTX. */
11368 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11370 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11371 may not have any available scratch register at this point. */
11372 if (SPARC_SIMM13_P (vcall_offset
))
11374 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11375 else if (! fixed_regs
[5]
11376 /* The below sequence is made up of at least 2 insns,
11377 while the default method may need only one. */
11378 && vcall_offset
< -8192)
11380 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11381 emit_move_insn (scratch2
, vcall_offset_rtx
);
11382 vcall_offset_rtx
= scratch2
;
11386 rtx increment
= GEN_INT (-4096);
11388 /* VCALL_OFFSET is a negative number whose typical range can be
11389 estimated as -32768..0 in 32-bit mode. In almost all cases
11390 it is therefore cheaper to emit multiple add insns than
11391 spilling and loading the constant into a register (at least
11393 while (! SPARC_SIMM13_P (vcall_offset
))
11395 emit_insn (gen_add2_insn (scratch
, increment
));
11396 vcall_offset
+= 4096;
11398 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11401 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11402 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11403 gen_rtx_PLUS (Pmode
,
11405 vcall_offset_rtx
)));
11407 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11408 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11411 /* Generate a tail call to the target function. */
11412 if (! TREE_USED (function
))
11414 assemble_external (function
);
11415 TREE_USED (function
) = 1;
11417 funexp
= XEXP (DECL_RTL (function
), 0);
11419 if (flag_delayed_branch
)
11421 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
11422 insn
= emit_call_insn (gen_sibcall (funexp
));
11423 SIBLING_CALL_P (insn
) = 1;
11427 /* The hoops we have to jump through in order to generate a sibcall
11428 without using delay slots... */
11429 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
11433 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
11435 load_got_register (); /* clobbers %o7 */
11436 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
11437 seq
= get_insns ();
11439 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
11441 else if (TARGET_ARCH32
)
11443 emit_insn (gen_rtx_SET (VOIDmode
,
11445 gen_rtx_HIGH (SImode
, funexp
)));
11446 emit_insn (gen_rtx_SET (VOIDmode
,
11448 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
11450 else /* TARGET_ARCH64 */
11452 switch (sparc_cmodel
)
11456 /* The destination can serve as a temporary. */
11457 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
11462 /* The destination cannot serve as a temporary. */
11463 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
11465 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
11466 seq
= get_insns ();
11468 emit_and_preserve (seq
, spill_reg
, 0);
11472 gcc_unreachable ();
11476 emit_jump_insn (gen_indirect_jump (scratch
));
11481 /* Run just enough of rest_of_compilation to get the insns emitted.
11482 There's not really enough bulk here to make other passes such as
11483 instruction scheduling worth while. Note that use_thunk calls
11484 assemble_start_function and assemble_end_function. */
11485 insn
= get_insns ();
11486 shorten_branches (insn
);
11487 final_start_function (insn
, file
, 1);
11488 final (insn
, file
, 1);
11489 final_end_function ();
11491 reload_completed
= 0;
11492 epilogue_completed
= 0;
11495 /* Return true if sparc_output_mi_thunk would be able to output the
11496 assembler code for the thunk function specified by the arguments
11497 it is passed, and false otherwise. */
11499 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
11500 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
11501 HOST_WIDE_INT vcall_offset
,
11502 const_tree function ATTRIBUTE_UNUSED
)
11504 /* Bound the loop used in the default method above. */
11505 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
11508 /* How to allocate a 'struct machine_function'. */
11510 static struct machine_function
*
11511 sparc_init_machine_status (void)
11513 return ggc_cleared_alloc
<machine_function
> ();
11516 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11517 We need to emit DTP-relative relocations. */
11520 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11525 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11528 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11531 gcc_unreachable ();
11533 output_addr_const (file
, x
);
11537 /* Do whatever processing is required at the end of a file. */
11540 sparc_file_end (void)
11542 /* If we need to emit the special GOT helper function, do so now. */
11543 if (got_helper_rtx
)
11545 const char *name
= XSTR (got_helper_rtx
, 0);
11546 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11547 #ifdef DWARF2_UNWIND_INFO
11551 if (USE_HIDDEN_LINKONCE
)
11553 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11554 get_identifier (name
),
11555 build_function_type_list (void_type_node
,
11557 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11558 NULL_TREE
, void_type_node
);
11559 TREE_PUBLIC (decl
) = 1;
11560 TREE_STATIC (decl
) = 1;
11561 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11562 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11563 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11564 resolve_unique_section (decl
, 0, flag_function_sections
);
11565 allocate_struct_function (decl
, true);
11566 cfun
->is_thunk
= 1;
11567 current_function_decl
= decl
;
11568 init_varasm_status ();
11569 assemble_start_function (decl
, name
);
11573 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11574 switch_to_section (text_section
);
11576 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11577 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11580 #ifdef DWARF2_UNWIND_INFO
11581 do_cfi
= dwarf2out_do_cfi_asm ();
11583 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11585 if (flag_delayed_branch
)
11586 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11587 reg_name
, reg_name
);
11589 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11590 reg_name
, reg_name
);
11591 #ifdef DWARF2_UNWIND_INFO
11593 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11597 if (NEED_INDICATE_EXEC_STACK
)
11598 file_end_indicate_exec_stack ();
11600 #ifdef TARGET_SOLARIS
11601 solaris_file_end ();
11605 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11606 /* Implement TARGET_MANGLE_TYPE. */
11608 static const char *
11609 sparc_mangle_type (const_tree type
)
11612 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11613 && TARGET_LONG_DOUBLE_128
)
11616 /* For all other types, use normal C++ mangling. */
11621 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11622 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11623 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11626 sparc_emit_membar_for_model (enum memmodel model
,
11627 int load_store
, int before_after
)
11629 /* Bits for the MEMBAR mmask field. */
11630 const int LoadLoad
= 1;
11631 const int StoreLoad
= 2;
11632 const int LoadStore
= 4;
11633 const int StoreStore
= 8;
11635 int mm
= 0, implied
= 0;
11637 switch (sparc_memory_model
)
11640 /* Sequential Consistency. All memory transactions are immediately
11641 visible in sequential execution order. No barriers needed. */
11642 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11646 /* Total Store Ordering: all memory transactions with store semantics
11647 are followed by an implied StoreStore. */
11648 implied
|= StoreStore
;
11650 /* If we're not looking for a raw barrer (before+after), then atomic
11651 operations get the benefit of being both load and store. */
11652 if (load_store
== 3 && before_after
== 1)
11653 implied
|= StoreLoad
;
11657 /* Partial Store Ordering: all memory transactions with load semantics
11658 are followed by an implied LoadLoad | LoadStore. */
11659 implied
|= LoadLoad
| LoadStore
;
11661 /* If we're not looking for a raw barrer (before+after), then atomic
11662 operations get the benefit of being both load and store. */
11663 if (load_store
== 3 && before_after
== 2)
11664 implied
|= StoreLoad
| StoreStore
;
11668 /* Relaxed Memory Ordering: no implicit bits. */
11672 gcc_unreachable ();
11675 if (before_after
& 1)
11677 if (model
== MEMMODEL_RELEASE
11678 || model
== MEMMODEL_ACQ_REL
11679 || model
== MEMMODEL_SEQ_CST
)
11681 if (load_store
& 1)
11682 mm
|= LoadLoad
| StoreLoad
;
11683 if (load_store
& 2)
11684 mm
|= LoadStore
| StoreStore
;
11687 if (before_after
& 2)
11689 if (model
== MEMMODEL_ACQUIRE
11690 || model
== MEMMODEL_ACQ_REL
11691 || model
== MEMMODEL_SEQ_CST
)
11693 if (load_store
& 1)
11694 mm
|= LoadLoad
| LoadStore
;
11695 if (load_store
& 2)
11696 mm
|= StoreLoad
| StoreStore
;
11700 /* Remove the bits implied by the system memory model. */
11703 /* For raw barriers (before+after), always emit a barrier.
11704 This will become a compile-time barrier if needed. */
11705 if (mm
|| before_after
== 3)
11706 emit_insn (gen_membar (GEN_INT (mm
)));
11709 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11710 compare and swap on the word containing the byte or half-word. */
11713 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11714 rtx oldval
, rtx newval
)
11716 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11717 rtx addr
= gen_reg_rtx (Pmode
);
11718 rtx off
= gen_reg_rtx (SImode
);
11719 rtx oldv
= gen_reg_rtx (SImode
);
11720 rtx newv
= gen_reg_rtx (SImode
);
11721 rtx oldvalue
= gen_reg_rtx (SImode
);
11722 rtx newvalue
= gen_reg_rtx (SImode
);
11723 rtx res
= gen_reg_rtx (SImode
);
11724 rtx resv
= gen_reg_rtx (SImode
);
11725 rtx memsi
, val
, mask
, cc
;
11727 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
11728 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11730 if (Pmode
!= SImode
)
11731 addr1
= gen_lowpart (SImode
, addr1
);
11732 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11733 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11735 memsi
= gen_rtx_MEM (SImode
, addr
);
11736 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11737 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11739 val
= copy_to_reg (memsi
);
11741 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11742 gen_rtx_XOR (SImode
, off
,
11743 GEN_INT (GET_MODE (mem
) == QImode
11746 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11747 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11749 if (GET_MODE (mem
) == QImode
)
11750 mask
= force_reg (SImode
, GEN_INT (0xff));
11752 mask
= force_reg (SImode
, GEN_INT (0xffff));
11754 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
11755 gen_rtx_ASHIFT (SImode
, mask
, off
)));
11757 emit_insn (gen_rtx_SET (VOIDmode
, val
,
11758 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11761 oldval
= gen_lowpart (SImode
, oldval
);
11762 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11763 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11765 newval
= gen_lowpart_common (SImode
, newval
);
11766 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11767 gen_rtx_ASHIFT (SImode
, newval
, off
)));
11769 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11770 gen_rtx_AND (SImode
, oldv
, mask
)));
11772 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11773 gen_rtx_AND (SImode
, newv
, mask
)));
11775 rtx_code_label
*end_label
= gen_label_rtx ();
11776 rtx_code_label
*loop_label
= gen_label_rtx ();
11777 emit_label (loop_label
);
11779 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
11780 gen_rtx_IOR (SImode
, oldv
, val
)));
11782 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
11783 gen_rtx_IOR (SImode
, newv
, val
)));
11785 emit_move_insn (bool_result
, const1_rtx
);
11787 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11789 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11791 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
11792 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11795 emit_move_insn (bool_result
, const0_rtx
);
11797 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11798 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
11800 /* Use cbranchcc4 to separate the compare and branch! */
11801 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11802 cc
, const0_rtx
, loop_label
));
11804 emit_label (end_label
);
11806 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11807 gen_rtx_AND (SImode
, res
, mask
)));
11809 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11810 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11812 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11815 /* Expand code to perform a compare-and-swap. */
11818 sparc_expand_compare_and_swap (rtx operands
[])
11820 rtx bval
, retval
, mem
, oldval
, newval
;
11822 enum memmodel model
;
11824 bval
= operands
[0];
11825 retval
= operands
[1];
11827 oldval
= operands
[3];
11828 newval
= operands
[4];
11829 model
= (enum memmodel
) INTVAL (operands
[6]);
11830 mode
= GET_MODE (mem
);
11832 sparc_emit_membar_for_model (model
, 3, 1);
11834 if (reg_overlap_mentioned_p (retval
, oldval
))
11835 oldval
= copy_to_reg (oldval
);
11837 if (mode
== QImode
|| mode
== HImode
)
11838 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11841 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11844 if (mode
== SImode
)
11845 gen
= gen_atomic_compare_and_swapsi_1
;
11847 gen
= gen_atomic_compare_and_swapdi_1
;
11848 emit_insn (gen (retval
, mem
, oldval
, newval
));
11850 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11852 convert_move (bval
, x
, 1);
11855 sparc_emit_membar_for_model (model
, 3, 2);
11859 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
11863 sel
= gen_lowpart (DImode
, sel
);
11867 /* inp = xxxxxxxAxxxxxxxB */
11868 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11869 NULL_RTX
, 1, OPTAB_DIRECT
);
11870 /* t_1 = ....xxxxxxxAxxx. */
11871 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11872 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11873 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11874 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11875 /* sel = .......B */
11876 /* t_1 = ...A.... */
11877 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11878 /* sel = ...A...B */
11879 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11880 /* sel = AAAABBBB * 4 */
11881 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11882 /* sel = { A*4, A*4+1, A*4+2, ... } */
11886 /* inp = xxxAxxxBxxxCxxxD */
11887 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11888 NULL_RTX
, 1, OPTAB_DIRECT
);
11889 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11890 NULL_RTX
, 1, OPTAB_DIRECT
);
11891 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11892 NULL_RTX
, 1, OPTAB_DIRECT
);
11893 /* t_1 = ..xxxAxxxBxxxCxx */
11894 /* t_2 = ....xxxAxxxBxxxC */
11895 /* t_3 = ......xxxAxxxBxx */
11896 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11898 NULL_RTX
, 1, OPTAB_DIRECT
);
11899 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11901 NULL_RTX
, 1, OPTAB_DIRECT
);
11902 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11903 GEN_INT (0x070000),
11904 NULL_RTX
, 1, OPTAB_DIRECT
);
11905 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11906 GEN_INT (0x07000000),
11907 NULL_RTX
, 1, OPTAB_DIRECT
);
11908 /* sel = .......D */
11909 /* t_1 = .....C.. */
11910 /* t_2 = ...B.... */
11911 /* t_3 = .A...... */
11912 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11913 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11914 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11915 /* sel = .A.B.C.D */
11916 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11917 /* sel = AABBCCDD * 2 */
11918 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11919 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11923 /* input = xAxBxCxDxExFxGxH */
11924 sel
= expand_simple_binop (DImode
, AND
, sel
,
11925 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11927 NULL_RTX
, 1, OPTAB_DIRECT
);
11928 /* sel = .A.B.C.D.E.F.G.H */
11929 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11930 NULL_RTX
, 1, OPTAB_DIRECT
);
11931 /* t_1 = ..A.B.C.D.E.F.G. */
11932 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11933 NULL_RTX
, 1, OPTAB_DIRECT
);
11934 /* sel = .AABBCCDDEEFFGGH */
11935 sel
= expand_simple_binop (DImode
, AND
, sel
,
11936 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11938 NULL_RTX
, 1, OPTAB_DIRECT
);
11939 /* sel = ..AB..CD..EF..GH */
11940 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11941 NULL_RTX
, 1, OPTAB_DIRECT
);
11942 /* t_1 = ....AB..CD..EF.. */
11943 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11944 NULL_RTX
, 1, OPTAB_DIRECT
);
11945 /* sel = ..ABABCDCDEFEFGH */
11946 sel
= expand_simple_binop (DImode
, AND
, sel
,
11947 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11948 NULL_RTX
, 1, OPTAB_DIRECT
);
11949 /* sel = ....ABCD....EFGH */
11950 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11951 NULL_RTX
, 1, OPTAB_DIRECT
);
11952 /* t_1 = ........ABCD.... */
11953 sel
= gen_lowpart (SImode
, sel
);
11954 t_1
= gen_lowpart (SImode
, t_1
);
11958 gcc_unreachable ();
11961 /* Always perform the final addition/merge within the bmask insn. */
11962 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, t_1
));
11965 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11968 sparc_frame_pointer_required (void)
11970 /* If the stack pointer is dynamically modified in the function, it cannot
11971 serve as the frame pointer. */
11972 if (cfun
->calls_alloca
)
11975 /* If the function receives nonlocal gotos, it needs to save the frame
11976 pointer in the nonlocal_goto_save_area object. */
11977 if (cfun
->has_nonlocal_label
)
11980 /* In flat mode, that's it. */
11984 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11985 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11988 /* The way this is structured, we can't eliminate SFP in favor of SP
11989 if the frame pointer is required: we want to use the SFP->HFP elimination
11990 in that case. But the test in update_eliminables doesn't know we are
11991 assuming below that we only do the former elimination. */
11994 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11996 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
11999 /* Return the hard frame pointer directly to bypass the stack bias. */
12002 sparc_builtin_setjmp_frame_value (void)
12004 return hard_frame_pointer_rtx
;
12007 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12008 they won't be allocated. */
12011 sparc_conditional_register_usage (void)
12013 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12015 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12016 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12018 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12019 /* then honor it. */
12020 if (TARGET_ARCH32
&& fixed_regs
[5])
12022 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12027 for (regno
= SPARC_FIRST_V9_FP_REG
;
12028 regno
<= SPARC_LAST_V9_FP_REG
;
12030 fixed_regs
[regno
] = 1;
12031 /* %fcc0 is used by v8 and v9. */
12032 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12033 regno
<= SPARC_LAST_V9_FCC_REG
;
12035 fixed_regs
[regno
] = 1;
12040 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12041 fixed_regs
[regno
] = 1;
12043 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12044 /* then honor it. Likewise with g3 and g4. */
12045 if (fixed_regs
[2] == 2)
12046 fixed_regs
[2] = ! TARGET_APP_REGS
;
12047 if (fixed_regs
[3] == 2)
12048 fixed_regs
[3] = ! TARGET_APP_REGS
;
12049 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12050 fixed_regs
[4] = ! TARGET_APP_REGS
;
12051 else if (TARGET_CM_EMBMEDANY
)
12053 else if (fixed_regs
[4] == 2)
12058 /* Disable leaf functions. */
12059 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12060 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12061 leaf_reg_remap
[regno
] = regno
;
12064 global_regs
[SPARC_GSR_REG
] = 1;
12067 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12069 - We can't load constants into FP registers.
12070 - We can't load FP constants into integer registers when soft-float,
12071 because there is no soft-float pattern with a r/F constraint.
12072 - We can't load FP constants into integer registers for TFmode unless
12073 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12074 - Try and reload integer constants (symbolic or otherwise) back into
12075 registers directly, rather than having them dumped to memory. */
12078 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12080 machine_mode mode
= GET_MODE (x
);
12081 if (CONSTANT_P (x
))
12083 if (FP_REG_CLASS_P (rclass
)
12084 || rclass
== GENERAL_OR_FP_REGS
12085 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12086 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12087 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12090 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12091 return GENERAL_REGS
;
12093 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12095 if (! FP_REG_CLASS_P (rclass
)
12096 || !(const_zero_operand (x
, mode
)
12097 || const_all_ones_operand (x
, mode
)))
12104 && (rclass
== EXTRA_FP_REGS
12105 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12107 int regno
= true_regnum (x
);
12109 if (SPARC_INT_REG_P (regno
))
12110 return (rclass
== EXTRA_FP_REGS
12111 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12117 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12118 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12121 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12125 gcc_assert (! TARGET_ARCH64
);
12127 if (sparc_check_64 (operands
[1], insn
) <= 0)
12128 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12129 if (which_alternative
== 1)
12130 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12131 if (GET_CODE (operands
[2]) == CONST_INT
)
12133 if (which_alternative
== 1)
12135 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12136 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12137 output_asm_insn (mulstr
, operands
);
12138 return "srlx\t%L0, 32, %H0";
12142 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12143 output_asm_insn ("or\t%L1, %3, %3", operands
);
12144 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12145 output_asm_insn (mulstr
, operands
);
12146 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12147 return "mov\t%3, %L0";
12150 else if (rtx_equal_p (operands
[1], operands
[2]))
12152 if (which_alternative
== 1)
12154 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12155 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12156 output_asm_insn (mulstr
, operands
);
12157 return "srlx\t%L0, 32, %H0";
12161 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12162 output_asm_insn ("or\t%L1, %3, %3", operands
);
12163 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12164 output_asm_insn (mulstr
, operands
);
12165 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12166 return "mov\t%3, %L0";
12169 if (sparc_check_64 (operands
[2], insn
) <= 0)
12170 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12171 if (which_alternative
== 1)
12173 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12174 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12175 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12176 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12177 output_asm_insn (mulstr
, operands
);
12178 return "srlx\t%L0, 32, %H0";
12182 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12183 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12184 output_asm_insn ("or\t%L1, %3, %3", operands
);
12185 output_asm_insn ("or\t%L2, %4, %4", operands
);
12186 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12187 output_asm_insn (mulstr
, operands
);
12188 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12189 return "mov\t%3, %L0";
12193 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12194 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12195 and INNER_MODE are the modes describing TARGET. */
12198 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
12199 machine_mode inner_mode
)
12201 rtx t1
, final_insn
, sel
;
12204 t1
= gen_reg_rtx (mode
);
12206 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12207 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12212 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12213 bmask
= 0x45674567;
12216 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12217 bmask
= 0x67676767;
12220 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12221 bmask
= 0x77777777;
12224 gcc_unreachable ();
12227 sel
= force_reg (SImode
, GEN_INT (bmask
));
12228 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, const0_rtx
));
12229 emit_insn (final_insn
);
12232 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12233 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12236 vector_init_fpmerge (rtx target
, rtx elt
)
12238 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12240 t1
= gen_reg_rtx (V4QImode
);
12241 elt
= convert_modes (SImode
, QImode
, elt
, true);
12242 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12244 t2
= gen_reg_rtx (V8QImode
);
12245 t2_low
= gen_lowpart (V4QImode
, t2
);
12246 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12248 t3
= gen_reg_rtx (V8QImode
);
12249 t3_low
= gen_lowpart (V4QImode
, t3
);
12250 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12252 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12255 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12256 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12259 vector_init_faligndata (rtx target
, rtx elt
)
12261 rtx t1
= gen_reg_rtx (V4HImode
);
12264 elt
= convert_modes (SImode
, HImode
, elt
, true);
12265 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12267 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12268 force_reg (SImode
, GEN_INT (6)),
12271 for (i
= 0; i
< 4; i
++)
12272 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12275 /* Emit code to initialize TARGET to values for individual fields VALS. */
12278 sparc_expand_vector_init (rtx target
, rtx vals
)
12280 const machine_mode mode
= GET_MODE (target
);
12281 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
12282 const int n_elts
= GET_MODE_NUNITS (mode
);
12288 for (i
= 0; i
< n_elts
; i
++)
12290 rtx x
= XVECEXP (vals
, 0, i
);
12291 if (!CONSTANT_P (x
))
12294 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12300 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12304 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12306 if (GET_MODE_SIZE (inner_mode
) == 4)
12308 emit_move_insn (gen_lowpart (SImode
, target
),
12309 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12312 else if (GET_MODE_SIZE (inner_mode
) == 8)
12314 emit_move_insn (gen_lowpart (DImode
, target
),
12315 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12319 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12320 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12322 emit_move_insn (gen_highpart (word_mode
, target
),
12323 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12324 emit_move_insn (gen_lowpart (word_mode
, target
),
12325 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12329 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12333 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12336 if (mode
== V8QImode
)
12338 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12341 if (mode
== V4HImode
)
12343 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12348 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12349 for (i
= 0; i
< n_elts
; i
++)
12350 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12351 i
* GET_MODE_SIZE (inner_mode
)),
12352 XVECEXP (vals
, 0, i
));
12353 emit_move_insn (target
, mem
);
12356 /* Implement TARGET_SECONDARY_RELOAD. */
12359 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12360 machine_mode mode
, secondary_reload_info
*sri
)
12362 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12364 sri
->icode
= CODE_FOR_nothing
;
12365 sri
->extra_cost
= 0;
12367 /* We need a temporary when loading/storing a HImode/QImode value
12368 between memory and the FPU registers. This can happen when combine puts
12369 a paradoxical subreg in a float/fix conversion insn. */
12370 if (FP_REG_CLASS_P (rclass
)
12371 && (mode
== HImode
|| mode
== QImode
)
12372 && (GET_CODE (x
) == MEM
12373 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12374 && true_regnum (x
) == -1)))
12375 return GENERAL_REGS
;
12377 /* On 32-bit we need a temporary when loading/storing a DFmode value
12378 between unaligned memory and the upper FPU registers. */
12380 && rclass
== EXTRA_FP_REGS
12382 && GET_CODE (x
) == MEM
12383 && ! mem_min_alignment (x
, 8))
12386 if (((TARGET_CM_MEDANY
12387 && symbolic_operand (x
, mode
))
12388 || (TARGET_CM_EMBMEDANY
12389 && text_segment_operand (x
, mode
)))
12393 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12395 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12399 if (TARGET_VIS3
&& TARGET_ARCH32
)
12401 int regno
= true_regnum (x
);
12403 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12404 to move 8-byte values in 4-byte pieces. This only works via
12405 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12406 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12407 an FP_REGS intermediate move. */
12408 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12409 || ((general_or_i64_p (rclass
)
12410 || rclass
== GENERAL_OR_FP_REGS
)
12411 && SPARC_FP_REG_P (regno
)))
12413 sri
->extra_cost
= 2;
12421 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12422 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12425 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
12427 enum rtx_code rc
= GET_CODE (operands
[1]);
12428 machine_mode cmp_mode
;
12429 rtx cc_reg
, dst
, cmp
;
12432 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
12435 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
12436 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
12438 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
12439 rc
= GET_CODE (cmp
);
12442 if (! rtx_equal_p (operands
[2], dst
)
12443 && ! rtx_equal_p (operands
[3], dst
))
12445 if (reg_overlap_mentioned_p (dst
, cmp
))
12446 dst
= gen_reg_rtx (mode
);
12448 emit_move_insn (dst
, operands
[3]);
12450 else if (operands
[2] == dst
)
12452 operands
[2] = operands
[3];
12454 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
12455 rc
= reverse_condition_maybe_unordered (rc
);
12457 rc
= reverse_condition (rc
);
12460 if (XEXP (cmp
, 1) == const0_rtx
12461 && GET_CODE (XEXP (cmp
, 0)) == REG
12462 && cmp_mode
== DImode
12463 && v9_regcmp_p (rc
))
12464 cc_reg
= XEXP (cmp
, 0);
12466 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
12468 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
12470 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
12471 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
12473 if (dst
!= operands
[0])
12474 emit_move_insn (operands
[0], dst
);
12479 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12480 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12481 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12482 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12483 code to be used for the condition mask. */
12486 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12488 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12489 enum rtx_code code
= GET_CODE (operands
[3]);
12491 mask
= gen_reg_rtx (Pmode
);
12492 cop0
= operands
[4];
12493 cop1
= operands
[5];
12494 if (code
== LT
|| code
== GE
)
12498 code
= swap_condition (code
);
12499 t
= cop0
; cop0
= cop1
; cop1
= t
;
12502 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12504 fcmp
= gen_rtx_UNSPEC (Pmode
,
12505 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12508 cmask
= gen_rtx_UNSPEC (DImode
,
12509 gen_rtvec (2, mask
, gsr
),
12512 bshuf
= gen_rtx_UNSPEC (mode
,
12513 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12516 emit_insn (gen_rtx_SET (VOIDmode
, mask
, fcmp
));
12517 emit_insn (gen_rtx_SET (VOIDmode
, gsr
, cmask
));
12519 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], bshuf
));
12522 /* On sparc, any mode which naturally allocates into the float
12523 registers should return 4 here. */
12526 sparc_regmode_natural_size (machine_mode mode
)
12528 int size
= UNITS_PER_WORD
;
12532 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12534 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12541 /* Return TRUE if it is a good idea to tie two pseudo registers
12542 when one has mode MODE1 and one has mode MODE2.
12543 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12544 for any hard reg, then this must be FALSE for correct output.
12546 For V9 we have to deal with the fact that only the lower 32 floating
12547 point registers are 32-bit addressable. */
12550 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12552 enum mode_class mclass1
, mclass2
;
12553 unsigned short size1
, size2
;
12555 if (mode1
== mode2
)
12558 mclass1
= GET_MODE_CLASS (mode1
);
12559 mclass2
= GET_MODE_CLASS (mode2
);
12560 if (mclass1
!= mclass2
)
12566 /* Classes are the same and we are V9 so we have to deal with upper
12567 vs. lower floating point registers. If one of the modes is a
12568 4-byte mode, and the other is not, we have to mark them as not
12569 tieable because only the lower 32 floating point register are
12570 addressable 32-bits at a time.
12572 We can't just test explicitly for SFmode, otherwise we won't
12573 cover the vector mode cases properly. */
12575 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12578 size1
= GET_MODE_SIZE (mode1
);
12579 size2
= GET_MODE_SIZE (mode2
);
12580 if ((size1
> 4 && size2
== 4)
12581 || (size2
> 4 && size1
== 4))
12587 /* Implement TARGET_CSTORE_MODE. */
12589 static machine_mode
12590 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
12592 return (TARGET_ARCH64
? DImode
: SImode
);
12595 /* Return the compound expression made of T1 and T2. */
12598 compound_expr (tree t1
, tree t2
)
12600 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
12603 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12606 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12611 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
12612 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
12614 /* We generate the equivalent of feholdexcept (&fenv_var):
12616 unsigned int fenv_var;
12617 __builtin_store_fsr (&fenv_var);
12619 unsigned int tmp1_var;
12620 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12622 __builtin_load_fsr (&tmp1_var); */
12624 tree fenv_var
= create_tmp_var (unsigned_type_node
);
12625 mark_addressable (fenv_var
);
12626 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
12627 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
12628 tree hold_stfsr
= build_call_expr (stfsr
, 1, fenv_addr
);
12630 tree tmp1_var
= create_tmp_var (unsigned_type_node
);
12631 mark_addressable (tmp1_var
);
12632 tree masked_fenv_var
12633 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
12634 build_int_cst (unsigned_type_node
,
12635 ~(accrued_exception_mask
| trap_enable_mask
)));
12637 = build2 (MODIFY_EXPR
, void_type_node
, tmp1_var
, masked_fenv_var
);
12639 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
12640 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
12641 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12643 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
12645 /* We reload the value of tmp1_var to clear the exceptions:
12647 __builtin_load_fsr (&tmp1_var); */
12649 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12651 /* We generate the equivalent of feupdateenv (&fenv_var):
12653 unsigned int tmp2_var;
12654 __builtin_store_fsr (&tmp2_var);
12656 __builtin_load_fsr (&fenv_var);
12658 if (SPARC_LOW_FE_EXCEPT_VALUES)
12660 __atomic_feraiseexcept ((int) tmp2_var); */
12662 tree tmp2_var
= create_tmp_var (unsigned_type_node
);
12663 mark_addressable (tmp2_var
);
12664 tree tmp3_addr
= build_fold_addr_expr (tmp2_var
);
12665 tree update_stfsr
= build_call_expr (stfsr
, 1, tmp3_addr
);
12667 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
12669 tree atomic_feraiseexcept
12670 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12672 = build_call_expr (atomic_feraiseexcept
, 1,
12673 fold_convert (integer_type_node
, tmp2_var
));
12675 if (SPARC_LOW_FE_EXCEPT_VALUES
)
12677 tree shifted_tmp2_var
12678 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
12679 build_int_cst (unsigned_type_node
, 5));
12681 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
12682 update_call
= compound_expr (update_shift
, update_call
);
12686 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
12689 #include "gt-sparc.h"