gcc/config/i386/znver1.md

   1 ;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19
  20 (define_attr "znver1_decode" "direct,vector,double"
  21   (const_string "direct"))
  22
  23 ;; AMD znver1 Scheduling
  24 ;; Modeling automatons for zen decoders, integer execution pipes,
  25 ;; AGU pipes and floating point execution units.
  26 (define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu")
  27
  28 ;; Decoders unit has 4 decoders and all of them can decode fast path
  29 ;; and vector type instructions.
  30 (define_cpu_unit "znver1-decode0" "znver1")
  31 (define_cpu_unit "znver1-decode1" "znver1")
  32 (define_cpu_unit "znver1-decode2" "znver1")
  33 (define_cpu_unit "znver1-decode3" "znver1")
  34
  35 ;; Currently blocking all decoders for vector path instructions as
  36 ;; they are dispatched separetely as microcode sequence.
  37 ;; Fix me: Need to revisit this.
  38 (define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3")
  39
  40 ;; Direct instructions can be issued to any of the four decoders.
  41 (define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3")
  42
  43 ;; Fix me: Need to revisit this later to simulate fast path double behaviour.
  44 (define_reservation "znver1-double" "znver1-direct")
  45
  46
  47 ;; Integer unit 4 ALU pipes.
  48 (define_cpu_unit "znver1-ieu0" "znver1_ieu")
  49 (define_cpu_unit "znver1-ieu1" "znver1_ieu")
  50 (define_cpu_unit "znver1-ieu2" "znver1_ieu")
  51 (define_cpu_unit "znver1-ieu3" "znver1_ieu")
  52 (define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3")
  53
  54 ;; 2 AGU pipes.
  55 (define_cpu_unit "znver1-agu0" "znver1_agu")
  56 (define_cpu_unit "znver1-agu1" "znver1_agu")
  57 (define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1")
  58
  59 (define_reservation "znver1-load" "znver1-agu-reserve")
  60 (define_reservation "znver1-store" "znver1-agu-reserve")
  61
  62 ;; vectorpath (microcoded) instructions are single issue instructions.
  63 ;; So, they occupy all the integer units.
  64 (define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1
  65                                       +znver1-ieu2+znver1-ieu3
  66                                       +znver1-agu0+znver1-agu1")
  67
  68 ;; Floating point unit 4 FP pipes.
  69 (define_cpu_unit "znver1-fp0" "znver1_fp")
  70 (define_cpu_unit "znver1-fp1" "znver1_fp")
  71 (define_cpu_unit "znver1-fp2" "znver1_fp")
  72 (define_cpu_unit "znver1-fp3" "znver1_fp")
  73
  74 (define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3")
  75
  76 (define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1
  77                                       +znver1-fp2+znver1-fp3
  78                                       +znver1-agu0+znver1-agu1")
  79
  80 ;; Call instruction
  81 (define_insn_reservation "znver1_call" 1
  82                          (and (eq_attr "cpu" "znver1")
  83                               (eq_attr "type" "call,callv"))
  84                          "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3")
  85
  86 ;; General instructions
  87 (define_insn_reservation "znver1_push" 1
  88                          (and (eq_attr "cpu" "znver1")
  89                               (and (eq_attr "type" "push")
  90                                    (eq_attr "memory" "none,unknown")))
  91                          "znver1-direct,znver1-store")
  92
  93 (define_insn_reservation "znver1_push_store" 1
  94                          (and (eq_attr "cpu" "znver1")
  95                               (and (eq_attr "type" "push")
  96                                    (eq_attr "memory" "store")))
  97                          "znver1-direct,znver1-store")
  98
  99 (define_insn_reservation "znver1_push_both" 5
 100                          (and (eq_attr "cpu" "znver1")
 101                               (and (eq_attr "type" "push")
 102                                    (eq_attr "memory" "both")))
 103                          "znver1-direct,znver1-load,znver1-store")
 104
 105 ;; Leave
 106 (define_insn_reservation "znver1_leave" 1
 107                          (and (eq_attr "cpu" "znver1")
 108                               (eq_attr "type" "leave"))
 109                          "znver1-double,znver1-ieu, znver1-store")
 110
 111 ;; Integer Instructions or General intructions
 112 ;; Multiplications
 113 ;; Reg operands
 114 (define_insn_reservation "znver1_imul" 3
 115                          (and (eq_attr "cpu" "znver1")
 116                               (and (eq_attr "type" "imul")
 117                                    (eq_attr "memory" "none")))
 118                          "znver1-direct,znver1-ieu1")
 119
 120 (define_insn_reservation "znver1_imul_mem" 7
 121                          (and (eq_attr "cpu" "znver1")
 122                               (and (eq_attr "type" "imul")
 123                                    (eq_attr "memory" "!none")))
 124                          "znver1-direct,znver1-load, znver1-ieu1")
 125
 126 ;; Divisions
 127 ;; Reg operands
 128 (define_insn_reservation "znver1_idiv_DI" 41
 129                          (and (eq_attr "cpu" "znver1")
 130                               (and (eq_attr "type" "idiv")
 131                                    (and (eq_attr "mode" "DI")
 132                                         (eq_attr "memory" "none"))))
 133                          "znver1-double,znver1-ieu2*41")
 134
 135 (define_insn_reservation "znver1_idiv_SI" 25
 136                          (and (eq_attr "cpu" "znver1")
 137                               (and (eq_attr "type" "idiv")
 138                                    (and (eq_attr "mode" "SI")
 139                                         (eq_attr "memory" "none"))))
 140                          "znver1-double,znver1-ieu2*25")
 141
 142 (define_insn_reservation "znver1_idiv_HI" 17
 143                          (and (eq_attr "cpu" "znver1")
 144                               (and (eq_attr "type" "idiv")
 145                                    (and (eq_attr "mode" "HI")
 146                                         (eq_attr "memory" "none"))))
 147                          "znver1-double,znver1-ieu2*17")
 148
 149 (define_insn_reservation "znver1_idiv_QI" 12
 150                          (and (eq_attr "cpu" "znver1")
 151                               (and (eq_attr "type" "idiv")
 152                                    (and (eq_attr "mode" "QI")
 153                                         (eq_attr "memory" "none"))))
 154                          "znver1-direct,znver1-ieu2*12")
 155
 156 ;; Mem operands
 157 (define_insn_reservation "znver1_idiv_mem_DI" 45
 158                          (and (eq_attr "cpu" "znver1")
 159                               (and (eq_attr "type" "idiv")
 160                                    (and (eq_attr "mode" "DI")
 161                                         (eq_attr "memory" "none"))))
 162                          "znver1-double,znver1-load,znver1-ieu2*41")
 163
 164 (define_insn_reservation "znver1_idiv_mem_SI" 29
 165                          (and (eq_attr "cpu" "znver1")
 166                               (and (eq_attr "type" "idiv")
 167                                    (and (eq_attr "mode" "SI")
 168                                         (eq_attr "memory" "none"))))
 169                          "znver1-double,znver1-load,znver1-ieu2*25")
 170
 171 (define_insn_reservation "znver1_idiv_mem_HI" 21
 172                          (and (eq_attr "cpu" "znver1")
 173                               (and (eq_attr "type" "idiv")
 174                                    (and (eq_attr "mode" "HI")
 175                                         (eq_attr "memory" "none"))))
 176                          "znver1-double,znver1-load,znver1-ieu2*17")
 177
 178 (define_insn_reservation "znver1_idiv_mem_QI" 16
 179                          (and (eq_attr "cpu" "znver1")
 180                               (and (eq_attr "type" "idiv")
 181                                    (and (eq_attr "mode" "QI")
 182                                         (eq_attr "memory" "none"))))
 183                          "znver1-direct,znver1-load,znver1-ieu2*12")
 184
 185 ;; STR ISHIFT which are micro coded.
 186 ;; Fix me: Latency need to be rechecked.
 187 (define_insn_reservation "znver1_str_ishift" 6
 188                          (and (eq_attr "cpu" "znver1")
 189                               (and (eq_attr "type" "str,ishift")
 190                                    (eq_attr "memory" "both,store")))
 191                          "znver1-vector,znver1-ivector")
 192 ;; MOV - integer moves
 193 (define_insn_reservation "znver1_load_imov_double" 2
 194                          (and (eq_attr "cpu" "znver1")
 195                               (and (eq_attr "znver1_decode" "double")
 196                                    (and (eq_attr "type" "imovx")
 197                                         (eq_attr "memory" "none,load"))))
 198                          "znver1-double,znver1-ieu")
 199
 200 (define_insn_reservation "znver1_load_imov_direct" 1
 201                          (and (eq_attr "cpu" "znver1")
 202                               (and (eq_attr "type" "imov,imovx")
 203                                    (eq_attr "memory" "none,load")))
 204                          "znver1-direct,znver1-ieu")
 205
 206 ;; INTEGER/GENERAL instructions
 207 ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
 208 (define_insn_reservation "znver1_insn" 1
 209                          (and (eq_attr "cpu" "znver1")
 210                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec")
 211                                    (eq_attr "memory" "none,unknown")))
 212                          "znver1-direct,znver1-ieu")
 213
 214 (define_insn_reservation "znver1_insn_load" 5
 215                          (and (eq_attr "cpu" "znver1")
 216                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec")
 217                                    (eq_attr "memory" "load")))
 218                          "znver1-direct,znver1-load,znver1-ieu")
 219
 220 (define_insn_reservation "znver1_insn_store" 1
 221                          (and (eq_attr "cpu" "znver1")
 222                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 223                                    (eq_attr "memory" "store")))
 224                          "znver1-direct,znver1-ieu,znver1-store")
 225
 226 (define_insn_reservation "znver1_insn_both" 5
 227                          (and (eq_attr "cpu" "znver1")
 228                               (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
 229                                    (eq_attr "memory" "both")))
 230                          "znver1-direct,znver1-load,znver1-ieu,znver1-store")
 231
 232 ;; Fix me: Other vector type insns keeping latency 6 as of now.
 233 (define_insn_reservation "znver1_ieu_vector" 6
 234                          (and (eq_attr "cpu" "znver1")
 235                               (eq_attr "type" "other,str,multi"))
 236                          "znver1-vector,znver1-ivector")
 237
 238 ;; ALU1 register operands.
 239 (define_insn_reservation "znver1_alu1_vector" 3
 240                          (and (eq_attr "cpu" "znver1")
 241                               (and (eq_attr "znver1_decode" "vector")
 242                                    (and (eq_attr "type" "alu1")
 243                                         (eq_attr "memory" "none,unknown"))))
 244                          "znver1-vector,znver1-ivector")
 245
 246 (define_insn_reservation "znver1_alu1_double" 2
 247                          (and (eq_attr "cpu" "znver1")
 248                               (and (eq_attr "znver1_decode" "double")
 249                                    (and (eq_attr "type" "alu1")
 250                                         (eq_attr "memory" "none,unknown"))))
 251                          "znver1-double,znver1-ieu")
 252
 253 (define_insn_reservation "znver1_alu1_direct" 1
 254                          (and (eq_attr "cpu" "znver1")
 255                               (and (eq_attr "znver1_decode" "direct")
 256                                    (and (eq_attr "type" "alu1")
 257                                         (eq_attr "memory" "none,unknown"))))
 258                          "znver1-direct,znver1-ieu")
 259
 260 ;; Branches : Fix me need to model conditional branches.
 261 (define_insn_reservation "znver1_branch" 1
 262                          (and (eq_attr "cpu" "znver1")
 263                               (and (eq_attr "type" "ibr")
 264                                    (eq_attr "memory" "none")))
 265                           "znver1-direct")
 266
 267 ;; Indirect branches check latencies.
 268 (define_insn_reservation "znver1_indirect_branch_mem" 6
 269                          (and (eq_attr "cpu" "znver1")
 270                               (and (eq_attr "type" "ibr")
 271                                    (eq_attr "memory" "load")))
 272                          "znver1-vector,znver1-ivector")
 273
 274 ;; LEA executes in ALU units with 1 cycle latency.
 275 (define_insn_reservation "znver1_lea" 1
 276                          (and (eq_attr "cpu" "znver1")
 277                               (eq_attr "type" "lea"))
 278                          "znver1-direct,znver1-ieu")
 279
 280 ;; Other integer instrucions
 281 (define_insn_reservation "znver1_idirect" 1
 282                          (and (eq_attr "cpu" "znver1")
 283                               (and (eq_attr "unit" "integer,unknown")
 284                                    (eq_attr "memory" "none,unknown")))
 285                          "znver1-direct,znver1-ieu")
 286
 287 ;;  Floating point
 288 (define_insn_reservation "znver1_fp_cmov" 6
 289                          (and (eq_attr "cpu" "znver1")
 290                               (eq_attr "type" "fcmov"))
 291                          "znver1-vector,znver1-fvector")
 292
 293 (define_insn_reservation "znver1_fp_mov_direct_load" 5
 294                          (and (eq_attr "cpu" "znver1")
 295                               (and (eq_attr "znver1_decode" "direct")
 296                                    (and (eq_attr "type" "fmov")
 297                                         (eq_attr "memory" "load"))))
 298                          "znver1-direct,znver1-load,znver1-fp3|znver1-fp1")
 299
 300 (define_insn_reservation "znver1_fp_mov_direct_store" 5
 301                          (and (eq_attr "cpu" "znver1")
 302                               (and (eq_attr "znver1_decode" "direct")
 303                                    (and (eq_attr "type" "fmov")
 304                                         (eq_attr "memory" "store"))))
 305                          "znver1-direct,znver1-fp2|znver1-fp3,znver1-store")
 306
 307 (define_insn_reservation "znver1_fp_mov_double" 4
 308                          (and (eq_attr "cpu" "znver1")
 309                               (and (eq_attr "znver1_decode" "double")
 310                                    (and (eq_attr "type" "fmov")
 311                                         (eq_attr "memory" "none"))))
 312                          "znver1-double,znver1-fp3")
 313
 314 (define_insn_reservation "znver1_fp_mov_double_load" 9
 315                          (and (eq_attr "cpu" "znver1")
 316                               (and (eq_attr "znver1_decode" "double")
 317                                    (and (eq_attr "type" "fmov")
 318                                         (eq_attr "memory" "load"))))
 319                          "znver1-double,znver1-load,znver1-fp3")
 320
 321 (define_insn_reservation "znver1_fp_mov_direct" 1
 322                          (and (eq_attr "cpu" "znver1")
 323                               (eq_attr "type" "fmov"))
 324                          "znver1-direct,znver1-fp3")
 325
 326 (define_insn_reservation "znver1_fp_spc_direct" 5
 327                          (and (eq_attr "cpu" "znver1")
 328                               (and (eq_attr "type" "fpspc")
 329                                    (eq_attr "memory" "store")))
 330                          "znver1-direct,znver1-fp3,znver1-fp2")
 331
 332 (define_insn_reservation "znver1_fp_insn_vector" 6
 333                          (and (eq_attr "cpu" "znver1")
 334                               (and (eq_attr "znver1_decode" "vector")
 335                                    (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
 336                          "znver1-vector,znver1-fvector")
 337
 338 ;; FABS
 339 (define_insn_reservation "znver1_fp_fsgn" 1
 340                          (and (eq_attr "cpu" "znver1")
 341                               (eq_attr "type" "fsgn"))
 342                          "znver1-direct,znver1-fp3")
 343
 344 (define_insn_reservation "znver1_fp_fcmp" 2
 345                          (and (eq_attr "cpu" "znver1")
 346                               (and (eq_attr "memory" "none")
 347                                    (and (eq_attr "znver1_decode" "double")
 348                                         (eq_attr "type" "fcmp"))))
 349                          "znver1-double,znver1-fp0,znver1-fp2")
 350
 351 (define_insn_reservation "znver1_fp_fcmp_load" 6
 352                          (and (eq_attr "cpu" "znver1")
 353                               (and (eq_attr "memory" "none")
 354                                    (and (eq_attr "znver1_decode" "double")
 355                                         (eq_attr "type" "fcmp"))))
 356                          "znver1-double,znver1-load, znver1-fp0,znver1-fp2")
 357
 358 ;;FADD FSUB FMUL
 359 (define_insn_reservation "znver1_fp_op_mul" 5
 360                          (and (eq_attr "cpu" "znver1")
 361                               (and (eq_attr "type" "fop,fmul")
 362                                    (eq_attr "memory" "none")))
 363                          "znver1-direct,znver1-fp0*5")
 364
 365 (define_insn_reservation "znver1_fp_op_mul_load" 9
 366                          (and (eq_attr "cpu" "znver1")
 367                               (and (eq_attr "type" "fop,fmul")
 368                                    (eq_attr "memory" "load")))
 369                          "znver1-direct,znver1-load,znver1-fp0*5")
 370
 371 (define_insn_reservation "znver1_fp_op_imul_load" 13
 372                          (and (eq_attr "cpu" "znver1")
 373                               (and (eq_attr "type" "fop,fmul")
 374                                    (and (eq_attr "fp_int_src" "true")
 375                                         (eq_attr "memory" "load"))))
 376                         "znver1-double,znver1-load,znver1-fp3,znver1-fp0")
 377
 378 (define_insn_reservation "znver1_fp_op_div" 15
 379                          (and (eq_attr "cpu" "znver1")
 380                               (and (eq_attr "type" "fdiv")
 381                                    (eq_attr "memory" "none")))
 382                          "znver1-direct,znver1-fp3*15")
 383
 384 (define_insn_reservation "znver1_fp_op_div_load" 19
 385                          (and (eq_attr "cpu" "znver1")
 386                               (and (eq_attr "type" "fdiv")
 387                                    (eq_attr "memory" "load")))
 388                          "znver1-direct,znver1-load,znver1-fp3*15")
 389
 390 (define_insn_reservation "znver1_fp_op_idiv_load" 24
 391                          (and (eq_attr "cpu" "znver1")
 392                               (and (eq_attr "type" "fdiv")
 393                                    (and (eq_attr "fp_int_src" "true")
 394                                         (eq_attr "memory" "load"))))
 395                          "znver1-double,znver1-load,znver1-fp3*19")
 396
 397 ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
 398 (define_insn_reservation "znver1_fp_insn" 1
 399                          (and (eq_attr "cpu" "znver1")
 400                               (eq_attr "type" "mmx"))
 401                          "znver1-direct,znver1-fpu")
 402
 403 (define_insn_reservation "znver1_mmx_add" 1
 404                          (and (eq_attr "cpu" "znver1")
 405                               (and (eq_attr "type" "mmxadd")
 406                                    (eq_attr "memory" "none")))
 407                          "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
 408
 409 (define_insn_reservation "znver1_mmx_add_load" 5
 410                          (and (eq_attr "cpu" "znver1")
 411                               (and (eq_attr "type" "mmxadd")
 412                                    (eq_attr "memory" "load")))
 413                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 414
 415 (define_insn_reservation "znver1_mmx_cmp" 1
 416                          (and (eq_attr "cpu" "znver1")
 417                               (and (eq_attr "type" "mmxcmp")
 418                                    (eq_attr "memory" "none")))
 419                          "znver1-direct,znver1-fp0|znver1-fp3")
 420
 421 (define_insn_reservation "znver1_mmx_cmp_load" 5
 422                          (and (eq_attr "cpu" "znver1")
 423                               (and (eq_attr "type" "mmxcmp")
 424                                    (eq_attr "memory" "load")))
 425                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
 426
 427 (define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1
 428                          (and (eq_attr "cpu" "znver1")
 429                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
 430                                    (eq_attr "memory" "none")))
 431                          "znver1-direct,znver1-fp1|znver1-fp2")
 432
 433 (define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 5
 434                          (and (eq_attr "cpu" "znver1")
 435                               (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
 436                                    (eq_attr "memory" "load")))
 437                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 438
 439 (define_insn_reservation "znver1_mmx_shift_move" 1
 440                          (and (eq_attr "cpu" "znver1")
 441                               (and (eq_attr "type" "mmxshft,mmxmov")
 442                                    (eq_attr "memory" "none")))
 443                          "znver1-direct,znver1-fp2")
 444
 445 (define_insn_reservation "znver1_mmx_shift_move_load" 5
 446                          (and (eq_attr "cpu" "znver1")
 447                               (and (eq_attr "type" "mmxshft,mmxmov")
 448                                    (eq_attr "memory" "load")))
 449                          "znver1-direct,znver1-load,znver1-fp2")
 450
 451 (define_insn_reservation "znver1_mmx_move_store" 1
 452                          (and (eq_attr "cpu" "znver1")
 453                               (and (eq_attr "type" "mmxshft,mmxmov")
 454                                    (eq_attr "memory" "store,both")))
 455                           "znver1-direct,znver1-fp2,znver1-store")
 456
 457 (define_insn_reservation "znver1_mmx_mul" 3
 458                          (and (eq_attr "cpu" "znver1")
 459                               (and (eq_attr "type" "mmxmul")
 460                                    (eq_attr "memory" "none")))
 461                           "znver1-direct,znver1-fp0*3")
 462
 463 (define_insn_reservation "znver1_mmx_load" 7
 464                          (and (eq_attr "cpu" "znver1")
 465                               (and (eq_attr "type" "mmxmul")
 466                                    (eq_attr "memory" "load")))
 467                          "znver1-direct,znver1-load,znver1-fp0*3")
 468
 469 (define_insn_reservation "znver1_avx256_log" 1
 470                          (and (eq_attr "cpu" "znver1")
 471                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 472                                    (and (eq_attr "type" "sselog")
 473                                         (eq_attr "memory" "none"))))
 474                          "znver1-double,znver1-fpu")
 475
 476 (define_insn_reservation "znver1_avx256_log_load" 5
 477                          (and (eq_attr "cpu" "znver1")
 478                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 479                                    (and (eq_attr "type" "sselog")
 480                                         (eq_attr "memory" "load"))))
 481                          "znver1-double,znver1-load,znver1-fpu")
 482
 483 (define_insn_reservation "znver1_sse_log" 1
 484                          (and (eq_attr "cpu" "znver1")
 485                               (and (eq_attr "type" "sselog")
 486                                    (eq_attr "memory" "none")))
 487                          "znver1-direct,znver1-fpu")
 488
 489 (define_insn_reservation "znver1_sse_log_load" 5
 490                          (and (eq_attr "cpu" "znver1")
 491                               (and (eq_attr "type" "sselog")
 492                                    (eq_attr "memory" "load")))
 493                          "znver1-direct,znver1-load,znver1-fpu")
 494
 495 (define_insn_reservation "znver1_avx256_log1" 1
 496                          (and (eq_attr "cpu" "znver1")
 497                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 498                                    (and (eq_attr "type" "sselog1")
 499                                         (eq_attr "memory" "none"))))
 500                          "znver1-double,znver1-fp1|znver1-fp2")
 501
 502 (define_insn_reservation "znver1_avx256_log1_load" 5
 503                          (and (eq_attr "cpu" "znver1")
 504                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 505                                    (and (eq_attr "type" "sselog1")
 506                                         (eq_attr "memory" "!none"))))
 507                          "znver1-double,znver1-load,znver1-fp1|znver1-fp2")
 508
 509 (define_insn_reservation "znver1_sse_log1" 1
 510                          (and (eq_attr "cpu" "znver1")
 511                               (and (eq_attr "type" "sselog1")
 512                                    (eq_attr "memory" "none")))
 513                          "znver1-direct,znver1-fp1|znver1-fp2")
 514
 515 (define_insn_reservation "znver1_sse_log1_load" 5
 516                          (and (eq_attr "cpu" "znver1")
 517                               (and (eq_attr "type" "sselog1")
 518                                    (eq_attr "memory" "!none")))
 519                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 520
 521 (define_insn_reservation "znver1_sse_comi" 1
 522                          (and (eq_attr "cpu" "znver1")
 523                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 524                                    (and (eq_attr "prefix" "!vex")
 525                                         (and (eq_attr "prefix_extra" "0")
 526                                              (and (eq_attr "type" "ssecomi")
 527                                                   (eq_attr "memory" "none"))))))
 528                          "znver1-direct,znver1-fp0|znver1-fp1")
 529
 530 (define_insn_reservation "znver1_sse_comi_load" 5
 531                          (and (eq_attr "cpu" "znver1")
 532                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 533                                    (and (eq_attr "prefix" "!vex")
 534                                         (and (eq_attr "prefix_extra" "0")
 535                                              (and (eq_attr "type" "ssecomi")
 536                                                   (eq_attr "memory" "load"))))))
 537                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
 538
 539 (define_insn_reservation "znver1_sse_comi_double" 2
 540                          (and (eq_attr "cpu" "znver1")
 541                               (and (eq_attr "mode" "V4SF,V2DF,TI")
 542                                    (and (eq_attr "prefix" "vex")
 543                                         (and (eq_attr "prefix_extra" "0")
 544                                              (and (eq_attr "type" "ssecomi")
 545                                                   (eq_attr "memory" "none"))))))
 546                          "znver1-double,znver1-fp0|znver1-fp1")
 547
 548 (define_insn_reservation "znver1_sse_comi_double_load" 7
 549                          (and (eq_attr "cpu" "znver1")
 550                               (and (eq_attr "mode" "V4SF,V2DF,TI")
 551                                    (and (eq_attr "prefix" "vex")
 552                                         (and (eq_attr "prefix_extra" "0")
 553                                              (and (eq_attr "type" "ssecomi")
 554                                                   (eq_attr "memory" "load"))))))
 555                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
 556
 557 (define_insn_reservation "znver1_sse_test" 1
 558                          (and (eq_attr "cpu" "znver1")
 559                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 560                                    (and (eq_attr "prefix_extra" "1")
 561                                         (and (eq_attr "type" "ssecomi")
 562                                              (eq_attr "memory" "none")))))
 563                          "znver1-direct,znver1-fp1|znver1-fp2")
 564
 565 (define_insn_reservation "znver1_sse_test_load" 5
 566                          (and (eq_attr "cpu" "znver1")
 567                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 568                                    (and (eq_attr "prefix_extra" "1")
 569                                         (and (eq_attr "type" "ssecomi")
 570                                              (eq_attr "memory" "load")))))
 571                          "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
 572
 573 ;; SSE moves
 574 ;; Fix me:  Need to revist this again some of the moves may be restricted
 575 ;; to some fpu pipes.
 576 (define_insn_reservation "znver1_sse_mov" 2
 577                          (and (eq_attr "cpu" "znver1")
 578                               (and (eq_attr "mode" "SI")
 579                                    (and (eq_attr "isa" "avx")
 580                                         (and (eq_attr "type" "ssemov")
 581                                              (eq_attr "memory" "none")))))
 582                          "znver1-direct,znver1-ieu0")
 583
 584 (define_insn_reservation "znver1_avx_mov" 2
 585                          (and (eq_attr "cpu" "znver1")
 586                               (and (eq_attr "mode" "TI")
 587                                    (and (eq_attr "isa" "avx")
 588                                         (and (eq_attr "type" "ssemov")
 589                                              (and (match_operand:SI 1 "register_operand")
 590                                                   (eq_attr "memory" "none"))))))
 591                          "znver1-direct,znver1-ieu2")
 592
 593 (define_insn_reservation "znver1_sseavx_mov" 1
 594                          (and (eq_attr "cpu" "znver1")
 595                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 596                                    (and (eq_attr "type" "ssemov")
 597                                         (eq_attr "memory" "none"))))
 598                          "znver1-direct,znver1-fpu")
 599
 600 (define_insn_reservation "znver1_sseavx_mov_store" 1
 601                          (and (eq_attr "cpu" "znver1")
 602                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 603                                    (and (eq_attr "type" "ssemov")
 604                                         (eq_attr "memory" "store"))))
 605                         "znver1-direct,znver1-fpu,znver1-store")
 606
 607 (define_insn_reservation "znver1_sseavx_mov_load" 5
 608                          (and (eq_attr "cpu" "znver1")
 609                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 610                                    (and (eq_attr "type" "ssemov")
 611                                         (eq_attr "memory" "load"))))
 612                          "znver1-direct,znver1-load,znver1-fpu")
 613
 614 (define_insn_reservation "znver1_avx256_mov" 1
 615                          (and (eq_attr "cpu" "znver1")
 616                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 617                                    (and (eq_attr "type" "ssemov")
 618                                         (eq_attr "memory" "none"))))
 619                          "znver1-double,znver1-fpu")
 620
 621 (define_insn_reservation "znver1_avx256_mov_store" 1
 622                          (and (eq_attr "cpu" "znver1")
 623                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 624                                    (and (eq_attr "type" "ssemov")
 625                                         (eq_attr "memory" "store"))))
 626                          "znver1-double,znver1-fpu,znver1-store")
 627
 628 (define_insn_reservation "znver1_avx256_mov_load" 5
 629                          (and (eq_attr "cpu" "znver1")
 630                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 631                                    (and (eq_attr "type" "ssemov")
 632                                         (eq_attr "memory" "load"))))
 633                          "znver1-double,znver1-load,znver1-fpu")
 634
 635 ;; SSE add
 636 (define_insn_reservation "znver1_sseavx_add" 3
 637                          (and (eq_attr "cpu" "znver1")
 638                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 639                                    (and (eq_attr "type" "sseadd")
 640                                         (eq_attr "memory" "none"))))
 641                          "znver1-direct,znver1-fp2|znver1-fp3")
 642
 643 (define_insn_reservation "znver1_sseavx_add_load" 7
 644                          (and (eq_attr "cpu" "znver1")
 645                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
 646                                    (and (eq_attr "type" "sseadd")
 647                                         (eq_attr "memory" "load"))))
 648                          "znver1-direct,znver1-load,znver1-fp2|znver1-fp3")
 649
 650 (define_insn_reservation "znver1_avx256_add" 3
 651                          (and (eq_attr "cpu" "znver1")
 652                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 653                                    (and (eq_attr "type" "sseadd")
 654                                         (eq_attr "memory" "none"))))
 655                          "znver1-double,znver1-fp2|znver1-fp3")
 656
 657 (define_insn_reservation "znver1_avx256_add_load" 7
 658                          (and (eq_attr "cpu" "znver1")
 659                               (and (eq_attr "mode" "V8SF,V4DF,OI")
 660                                    (and (eq_attr "type" "sseadd")
 661                                         (eq_attr "memory" "load"))))
 662                          "znver1-double,znver1-load,znver1-fp2|znver1-fp3")
 663
 664 (define_insn_reservation "znver1_sseavx_fma" 5
 665                          (and (eq_attr "cpu" "znver1")
 666                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 667                                    (and (eq_attr "type" "ssemuladd")
 668                                         (eq_attr "memory" "none"))))
 669                          "znver1-direct,(znver1-fp0+znver1-fp3)|(znver1-fp1+znver1-fp3)")
 670
 671 (define_insn_reservation "znver1_sseavx_fma_load" 9
 672                          (and (eq_attr "cpu" "znver1")
 673                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 674                                    (and (eq_attr "type" "ssemuladd")
 675                                         (eq_attr "memory" "load"))))
 676                         "znver1-direct,znver1-load,(znver1-fp0+znver1-fp3)|(znver1-fp1+znver1-fp3)")
 677
 678 (define_insn_reservation "znver1_avx256_fma" 5
 679                          (and (eq_attr "cpu" "znver1")
 680                               (and (eq_attr "mode" "V8SF,V4DF")
 681                                    (and (eq_attr "type" "ssemuladd")
 682                                         (eq_attr "memory" "none"))))
 683                          "znver1-double,(znver1-fp0+znver1-fp3)|(znver1-fp1+znver1-fp3)")
 684
 685 (define_insn_reservation "znver1_avx256_fma_load" 9
 686                          (and (eq_attr "cpu" "znver1")
 687                               (and (eq_attr "mode" "V8SF,V4DF")
 688                                    (and (eq_attr "type" "ssemuladd")
 689                                         (eq_attr "memory" "load"))))
 690                          "znver1-double,znver1-load,(znver1-fp0+znver1-fp3)|(znver1-fp1+znver1-fp3)")
 691
 692 (define_insn_reservation "znver1_sseavx_iadd" 1
 693                          (and (eq_attr "cpu" "znver1")
 694                               (and (eq_attr "mode" "DI,TI")
 695                                    (and (eq_attr "type" "sseiadd")
 696                                         (eq_attr "memory" "none"))))
 697                          "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
 698
 699 (define_insn_reservation "znver1_sseavx_iadd_load" 5
 700                          (and (eq_attr "cpu" "znver1")
 701                               (and (eq_attr "mode" "DI,TI")
 702                                    (and (eq_attr "type" "sseiadd")
 703                                         (eq_attr "memory" "load"))))
 704                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 705
 706 (define_insn_reservation "znver1_avx256_iadd" 1
 707                          (and (eq_attr "cpu" "znver1")
 708                               (and (eq_attr "mode" "OI")
 709                                    (and (eq_attr "type" "sseiadd")
 710                                         (eq_attr "memory" "none"))))
 711                          "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3")
 712
 713 (define_insn_reservation "znver1_avx256_iadd_load" 5
 714                          (and (eq_attr "cpu" "znver1")
 715                               (and (eq_attr "mode" "OI")
 716                                    (and (eq_attr "type" "sseiadd")
 717                                         (eq_attr "memory" "load"))))
 718                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
 719
 720 ;; SSE conversions.
 721 (define_insn_reservation "znver1_ssecvtsf_si_load" 9
 722                          (and (eq_attr "cpu" "znver1")
 723                               (and (eq_attr "mode" "SI")
 724                                    (and (eq_attr "type" "sseicvt")
 725                                         (and (match_operand:SF 1 "memory_operand")
 726                                              (eq_attr "memory" "load")))))
 727                          "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
 728
 729 (define_insn_reservation "znver1_ssecvtdf_si" 5
 730                          (and (eq_attr "cpu" "znver1")
 731                               (and (eq_attr "mode" "SI")
 732                                    (and (match_operand:DF 1 "register_operand")
 733                                         (and (eq_attr "type" "sseicvt")
 734                                              (eq_attr "memory" "none")))))
 735                          "znver1-double,znver1-fp3,znver1-ieu0")
 736
 737 (define_insn_reservation "znver1_ssecvtdf_si_load" 9
 738                          (and (eq_attr "cpu" "znver1")
 739                               (and (eq_attr "mode" "SI")
 740                                    (and (eq_attr "type" "sseicvt")
 741                                         (and (match_operand:DF 1 "memory_operand")
 742                                              (eq_attr "memory" "load")))))
 743                          "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
 744
 745 ;; All other used ssecvt fp3 pipes
 746 ;; Check: Need to revisit this again.
 747 ;; Some SSE converts may use different pipe combinations.
 748 (define_insn_reservation "znver1_ssecvt" 4
 749                          (and (eq_attr "cpu" "znver1")
 750                               (and (eq_attr "type" "ssecvt")
 751                                    (eq_attr "memory" "none")))
 752                          "znver1-direct,znver1-fp3")
 753
 754 (define_insn_reservation "znver1_ssecvt_load" 8
 755                          (and (eq_attr "cpu" "znver1")
 756                               (and (eq_attr "type" "ssecvt")
 757                                    (eq_attr "memory" "load")))
 758                          "znver1-direct,znver1-load,znver1-fp3")
 759
 760 ;; SSE div
 761 (define_insn_reservation "znver1_ssediv_ss_ps" 10
 762                          (and (eq_attr "cpu" "znver1")
 763                               (and (eq_attr "mode" "V4SF,SF")
 764                                    (and (eq_attr "type" "ssediv")
 765                                         (eq_attr "memory" "none"))))
 766                          "znver1-direct,znver1-fp3*10")
 767
 768 (define_insn_reservation "znver1_ssediv_ss_ps_load" 14
 769                          (and (eq_attr "cpu" "znver1")
 770                               (and (eq_attr "mode" "V4SF,SF")
 771                                    (and (eq_attr "type" "ssediv")
 772                                         (eq_attr "memory" "load"))))
 773                          "znver1-direct,znver1-load,znver1-fp3*10")
 774
 775 (define_insn_reservation "znver1_ssediv_sd_pd" 13
 776                          (and (eq_attr "cpu" "znver1")
 777                               (and (eq_attr "mode" "V2DF,DF")
 778                                    (and (eq_attr "type" "ssediv")
 779                                         (eq_attr "memory" "none"))))
 780                          "znver1-direct,znver1-fp3*13")
 781
 782 (define_insn_reservation "znver1_ssediv_sd_pd_load" 17
 783                          (and (eq_attr "cpu" "znver1")
 784                               (and (eq_attr "mode" "V2DF,DF")
 785                                    (and (eq_attr "type" "ssediv")
 786                                         (eq_attr "memory" "load"))))
 787                          "znver1-direct,znver1-load,znver1-fp3*13")
 788
 789 (define_insn_reservation "znver1_ssediv_avx256_ps" 12
 790                          (and (eq_attr "cpu" "znver1")
 791                               (and (eq_attr "mode" "V8SF")
 792                                    (and (eq_attr "memory" "none")
 793                                         (eq_attr "type" "ssediv"))))
 794                          "znver1-double,znver1-fp3*12")
 795
 796 (define_insn_reservation "znver1_ssediv_avx256_ps_load" 16
 797                          (and (eq_attr "cpu" "znver1")
 798                               (and (eq_attr "mode" "V8SF")
 799                                    (and (eq_attr "type" "ssediv")
 800                                         (eq_attr "memory" "load"))))
 801                          "znver1-double,znver1-load,znver1-fp3*12")
 802
 803 (define_insn_reservation "znver1_ssediv_avx256_pd" 15
 804                          (and (eq_attr "cpu" "znver1")
 805                               (and (eq_attr "mode" "V4DF")
 806                                    (and (eq_attr "type" "ssediv")
 807                                         (eq_attr "memory" "none"))))
 808                          "znver1-double,znver1-fp3*15")
 809
 810 (define_insn_reservation "znver1_ssediv_avx256_pd_load" 18
 811                          (and (eq_attr "cpu" "znver1")
 812                               (and (eq_attr "mode" "V4DF")
 813                                    (and (eq_attr "type" "ssediv")
 814                                         (eq_attr "memory" "load"))))
 815                          "znver1-double,znver1-load,znver1-fp3*15")
 816 ;; SSE MUL
 817 (define_insn_reservation "znver1_ssemul_ss_ps" 3
 818                          (and (eq_attr "cpu" "znver1")
 819                               (and (eq_attr "mode" "V4SF,SF")
 820                                    (and (eq_attr "type" "ssemul")
 821                                         (eq_attr "memory" "none"))))
 822                          "znver1-direct,(znver1-fp0|znver1-fp1)*3")
 823
 824 (define_insn_reservation "znver1_ssemul_ss_ps_load" 7
 825                          (and (eq_attr "cpu" "znver1")
 826                               (and (eq_attr "mode" "V4SF,SF")
 827                                    (and (eq_attr "type" "ssemul")
 828                                         (eq_attr "memory" "load"))))
 829                          "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
 830
 831 (define_insn_reservation "znver1_ssemul_avx256_ps" 3
 832                          (and (eq_attr "cpu" "znver1")
 833                               (and (eq_attr "mode" "V8SF")
 834                                    (and (eq_attr "type" "ssemul")
 835                                         (eq_attr "memory" "none"))))
 836                          "znver1-double,(znver1-fp0|znver1-fp1)*3")
 837
 838 (define_insn_reservation "znver1_ssemul_avx256_ps_load" 7
 839                          (and (eq_attr "cpu" "znver1")
 840                               (and (eq_attr "mode" "V8SF")
 841                                    (and (eq_attr "type" "ssemul")
 842                                         (eq_attr "memory" "load"))))
 843                          "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3")
 844
 845 (define_insn_reservation "znver1_ssemul_sd_pd" 4
 846                          (and (eq_attr "cpu" "znver1")
 847                               (and (eq_attr "mode" "V2DF,DF")
 848                                    (and (eq_attr "type" "ssemul")
 849                                         (eq_attr "memory" "none"))))
 850                          "znver1-direct,(znver1-fp0|znver1-fp1)*4")
 851
 852 (define_insn_reservation "znver1_ssemul_sd_pd_load" 8
 853                          (and (eq_attr "cpu" "znver1")
 854                               (and (eq_attr "mode" "V2DF,DF")
 855                                    (and (eq_attr "type" "ssemul")
 856                                         (eq_attr "memory" "load"))))
 857                          "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4")
 858
 859 (define_insn_reservation "znver1_ssemul_avx256_pd" 5
 860                          (and (eq_attr "cpu" "znver1")
 861                               (and (eq_attr "mode" "V4DF")
 862                                    (and (eq_attr "mode" "V4DF")
 863                                         (and (eq_attr "type" "ssemul")
 864                                              (eq_attr "memory" "none")))))
 865                          "znver1-double,(znver1-fp0|znver1-fp1)*4")
 866
 867 (define_insn_reservation "znver1_ssemul_avx256_pd_load" 8
 868                          (and (eq_attr "cpu" "znver1")
 869                               (and (eq_attr "mode" "V4DF")
 870                                    (and (eq_attr "type" "ssemul")
 871                                         (eq_attr "memory" "load"))))
 872                          "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4")
 873
 874 ;;SSE imul
 875 (define_insn_reservation "znver1_sseimul" 3
 876                          (and (eq_attr "cpu" "znver1")
 877                               (and (eq_attr "mode" "TI")
 878                                    (and (eq_attr "type" "ssemul")
 879                                         (eq_attr "memory" "none"))))
 880                          "znver1-direct,znver1-fp0*3")
 881
 882 (define_insn_reservation "znver1_sseimul_avx256" 4
 883                          (and (eq_attr "cpu" "znver1")
 884                               (and (eq_attr "mode" "OI")
 885                                    (and (eq_attr "type" "ssemul")
 886                                         (eq_attr "memory" "none"))))
 887                          "znver1-double,znver1-fp0*4")
 888
 889 (define_insn_reservation "znver1_sseimul_load" 7
 890                          (and (eq_attr "cpu" "znver1")
 891                               (and (eq_attr "mode" "TI")
 892                                    (and (eq_attr "type" "ssemul")
 893                                         (eq_attr "memory" "load"))))
 894                          "znver1-direct,znver1-load,znver1-fp0*3")
 895
 896 (define_insn_reservation "znver1_sseimul_avx256_load" 8
 897                          (and (eq_attr "cpu" "znver1")
 898                               (and (eq_attr "mode" "OI")
 899                                    (and (eq_attr "type" "ssemul")
 900                                         (eq_attr "memory" "load"))))
 901                          "znver1-double,znver1-load,znver1-fp0*4")
 902
 903 (define_insn_reservation "znver1_sseimul_di" 4
 904                          (and (eq_attr "cpu" "znver1")
 905                               (and (eq_attr "mode" "DI")
 906                                    (and (eq_attr "memory" "none")
 907                                         (eq_attr "type" "ssemul"))))
 908                          "znver1-direct,znver1-fp0*4")
 909
 910 (define_insn_reservation "znver1_sseimul_load_di" 8
 911                          (and (eq_attr "cpu" "znver1")
 912                               (and (eq_attr "mode" "DI")
 913                                    (and (eq_attr "type" "ssemul")
 914                                         (eq_attr "memory" "load"))))
 915                          "znver1-direct,znver1-load,znver1-fp0*4")
 916
 917 ;; SSE compares
 918 (define_insn_reservation "znver1_sse_cmp" 1
 919                          (and (eq_attr "cpu" "znver1")
 920                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 921                                    (and (eq_attr "type" "ssecmp")
 922                                         (eq_attr "memory" "none"))))
 923                          "znver1-direct,znver1-fp0|znver1-fp1")
 924
 925 (define_insn_reservation "znver1_sse_cmp_load" 5
 926                          (and (eq_attr "cpu" "znver1")
 927                               (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
 928                                    (and (eq_attr "type" "ssecmp")
 929                                         (eq_attr "memory" "load"))))
 930                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
 931
 932 (define_insn_reservation "znver1_sse_cmp_avx256" 1
 933                          (and (eq_attr "cpu" "znver1")
 934                               (and (eq_attr "mode" "V8SF,V4DF")
 935                                    (and (eq_attr "type" "ssecmp")
 936                                         (eq_attr "memory" "none"))))
 937                         "znver1-double,znver1-fp0|znver1-fp1")
 938
 939 (define_insn_reservation "znver1_sse_cmp_avx256_load" 5
 940                          (and (eq_attr "cpu" "znver1")
 941                               (and (eq_attr "mode" "V8SF,V4DF")
 942                                    (and (eq_attr "type" "ssecmp")
 943                                         (eq_attr "memory" "load"))))
 944                          "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
 945
 946 (define_insn_reservation "znver1_sse_icmp" 1
 947                          (and (eq_attr "cpu" "znver1")
 948                               (and (eq_attr "mode" "QI,HI,SI,DI,TI")
 949                                    (and (eq_attr "type" "ssecmp")
 950                                         (eq_attr "memory" "none"))))
 951                          "znver1-direct,znver1-fp0|znver1-fp3")
 952
 953 (define_insn_reservation "znver1_sse_icmp_load" 5
 954                          (and (eq_attr "cpu" "znver1")
 955                               (and (eq_attr "mode" "QI,HI,SI,DI,TI")
 956                                    (and (eq_attr "type" "ssecmp")
 957                                         (eq_attr "memory" "load"))))
 958                          "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
 959
 960 (define_insn_reservation "znver1_sse_icmp_avx256" 1
 961                          (and (eq_attr "cpu" "znver1")
 962                               (and (eq_attr "mode" "OI")
 963                                    (and (eq_attr "type" "ssecmp")
 964                                         (eq_attr "memory" "none"))))
 965                          "znver1-double,znver1-fp0|znver1-fp3")
 966
 967 (define_insn_reservation "znver1_sse_icmp_avx256_load" 5
 968                          (and (eq_attr "cpu" "znver1")
 969                               (and (eq_attr "mode" "OI")
 970                                    (and (eq_attr "type" "ssecmp")
 971                                         (eq_attr "memory" "load"))))
 972                          "znver1-double,znver1-load,znver1-fp0|znver1-fp3")
 973