| blob | d9161b257e8257a483bf74ae110f19f9a8ade3ae |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
54 REG_DEAD note is lost
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
57 linking
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
95 /* Number of attempts to combine instructions in this function. */
99 /* Number of attempts that got as far as substitution in this function. */
103 /* Number of instructions combined with added SETs in this function. */
107 /* Number of instructions combined in this function. */
111 /* Totals over entire compilation. */
115 /* combine_instructions may try to replace the right hand side of the
116 second instruction with the value of an associated REG_EQUAL note
117 before throwing it at try_combine. That is problematic when there
118 is a REG_DEAD note for a register used in the old right hand side
119 and can cause distribute_notes to do wrong things. This is the
120 second instruction if it has been so modified, null otherwise. */
124 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
128 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
131 \f
133 /* Record last point of death of (hard or pseudo) register n. */
136 /* Record last point of modification of (hard or pseudo) register n. */
139 /* The next group of fields allows the recording of the last value assigned
140 to (hard or pseudo) register n. We use this information to see if an
141 operation being processed is redundant given a prior operation performed
142 on the register. For example, an `and' with a constant is redundant if
143 all the zero bits are already known to be turned off.
145 We use an approach similar to that used by cse, but change it in the
146 following ways:
148 (1) We do not want to reinitialize at each label.
149 (2) It is useful, but not critical, to know the actual value assigned
150 to a register. Often just its form is helpful.
152 Therefore, we maintain the following fields:
154 last_set_value the last value assigned
155 last_set_label records the value of label_tick when the
156 register was assigned
157 last_set_table_tick records the value of label_tick when a
158 value using the register is assigned
159 last_set_invalid set to true when it is not valid
160 to use the value of this register in some
161 register's value
163 To understand the usage of these tables, it is important to understand
164 the distinction between the value in last_set_value being valid and
165 the register being validly contained in some other expression in the
166 table.
168 (The next two parameters are out of date).
170 reg_stat[i].last_set_value is valid if it is nonzero, and either
171 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
173 Register I may validly appear in any expression returned for the value
174 of another register if reg_n_sets[i] is 1. It may also appear in the
175 value for register J if reg_stat[j].last_set_invalid is zero, or
176 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
178 If an expression is found in the table containing a register which may
179 not validly appear in an expression, the register is replaced by
180 something that won't match, (clobber (const_int 0)). */
182 /* Record last value assigned to (hard or pseudo) register n. */
184 rtx last_set_value;
186 /* Record the value of label_tick when an expression involving register n
187 is placed in last_set_value. */
191 /* Record the value of label_tick when the value for register n is placed in
192 last_set_value. */
196 /* These fields are maintained in parallel with last_set_value and are
197 used to store the mode in which the register was last set, the bits
198 that were known to be zero when it was last set, and the number of
199 sign bits copies it was known to have when it was last set. */
205 /* Set to true if references to register n in expressions should not be
206 used. last_set_invalid is set nonzero when this register is being
207 assigned to and last_set_table_tick == label_tick. */
211 /* Some registers that are set more than once and used in more than one
212 basic block are nevertheless always set in similar ways. For example,
213 a QImode register may be loaded from memory in two places on a machine
214 where byte loads zero extend.
216 We record in the following fields if a register has some leading bits
217 that are always equal to the sign bit, and what we know about the
218 nonzero bits of a register, specifically which bits are known to be
219 zero.
221 If an entry is zero, it means that we don't know anything special. */
227 /* Record the value of the label_tick when the last truncation
228 happened. The field truncated_to_mode is only valid if
229 truncation_label == label_tick. */
233 /* Record the last truncation seen for this register. If truncation
234 is not a nop to this mode we might be able to save an explicit
235 truncation if we know that value already contains a truncated
236 value. */
239 };
244 /* One plus the highest pseudo for which we track REG_N_SETS.
245 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
246 but during combine_split_insns new pseudos can be created. As we don't have
247 updated DF information in that case, it is hard to initialize the array
248 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
249 so instead of growing the arrays, just assume all newly created pseudos
250 during combine might be set multiple times. */
254 /* Record the luid of the last insn that invalidated memory
255 (anything that writes memory, and subroutine calls, but not pushes). */
259 /* Record the luid of the last CALL_INSN
260 so we can tell whether a potential combination crosses any calls. */
264 /* When `subst' is called, this is the insn that is being modified
265 (by combining in a previous insn). The PATTERN of this insn
266 is still the old pattern partially modified and it should not be
267 looked at, but this may be used to examine the successors of the insn
268 to judge whether a simplification is valid. */
272 /* This is the lowest LUID that `subst' is currently dealing with.
273 get_last_value will not return a value if the register was set at or
274 after this LUID. If not for this mechanism, we could get confused if
275 I2 or I1 in try_combine were an insn that used the old value of a register
276 to obtain a new value. In that case, we might erroneously get the
277 new value of the register when we wanted the old one. */
281 /* This contains any hard registers that are used in newpat; reg_dead_at_p
282 must consider all these registers to be always live. */
286 /* This is an insn to which a LOG_LINKS entry has been added. If this
287 insn is the earlier than I2 or I3, combine should rescan starting at
288 that location. */
292 /* And similarly, for notes. */
296 /* Basic block in which we are performing combines. */
300 \f
301 /* Length of the currently allocated uid_insn_cost array. */
305 /* The following array records the insn_cost for every insn
306 in the instruction stream. */
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as struct insn_link pointers. */
317 };
323 {
327 }
329 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
330 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
332 #define FOR_EACH_LOG_LINK(L, INSN) \
333 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
335 /* Links for LOG_LINKS are allocated from this obstack. */
339 /* Allocate a link. */
343 {
351 }
353 /* Incremented for each basic block. */
357 /* Reset to label_tick for each extended basic block in scanning order. */
361 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
362 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
366 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
367 be safely used. It is zero while computing them and after combine has
368 completed. This former test prevents propagating values based on
369 previously set values, which can be incorrect if a variable is modified
370 in a loop. */
374 \f
375 /* Record one modification to rtl structure
376 to be undone by storing old_contents into *where. */
380 struct undo
381 {
386 };
388 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
389 num_undo says how many are currently recorded.
391 other_insn is nonzero if we have modified some other insn in the process
392 of working on subst_insn. It must be verified too. */
394 struct undobuf
395 {
399 };
403 /* Number of times the pseudo being substituted for
404 was found and replaced. */
409 scalar_int_mode,
412 scalar_int_mode,
486 \f
488 /* It is not safe to use ordinary gen_lowpart in combine.
489 See comments in gen_lowpart_for_combine. */
490 #undef RTL_HOOKS_GEN_LOWPART
491 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
493 /* Our implementation of gen_lowpart never emits a new pseudo. */
494 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
497 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
500 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
503 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
508 \f
509 /* Convenience wrapper for the canonicalize_comparison target hook.
510 Target hooks cannot use enum rtx_code. */
514 {
518 }
520 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 PATTERN cannot be split. Otherwise, it returns an insn sequence.
522 This is a wrapper around split_insns which ensures that the
523 reg_stat vector is made larger if the splitter creates a new
524 register. */
528 {
537 }
539 /* This is used by find_single_use to locate an rtx in LOC that
540 contains exactly one use of DEST, which is typically a REG.
541 It returns a pointer to the innermost rtx expression
542 containing DEST. Appearances of DEST that are being used to
543 totally replace it are not counted. */
547 {
556 {
560 CASE_CONST_ANY:
565 /* If the destination is anything other than PC, a REG or a SUBREG
566 of a REG that occupies all of the REG, the insn uses DEST if
567 it is mentioned in the destination or the source. Otherwise, we
568 need just check the source. */
584 }
586 /* If it wasn't one of the common cases above, check each expression and
587 vector of this code. Look for a unique usage of DEST. */
591 {
593 {
598 else
604 /* Duplicate usage. */
606 }
608 {
612 {
618 else
625 }
626 }
627 }
630 }
633 /* See if DEST, produced in INSN, is used only a single time in the
634 sequel. If so, return a pointer to the innermost rtx expression in which
635 it is used.
637 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
639 Otherwise, we find the single use by finding an insn that has a
640 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
641 only referenced once in that insn, we know that it must be the first
642 and last insn referencing DEST. */
646 {
647 basic_block bb;
660 {
666 {
671 }
672 }
675 }
676 \f
677 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
678 insn. The substitution can be undone by undo_all. If INTO is already
679 set to NEWVAL, do not record this change. Because computing NEWVAL might
680 also call SUBST, we have to compute it before we put anything into
681 the undo table. */
683 static void
685 {
692 /* We'd like to catch as many invalid transformations here as
693 possible. Unfortunately, there are way too many mode changes
694 that are perfectly valid, so we'd waste too much effort for
695 little gain doing the checks here. Focus on catching invalid
696 transformations involving integer constants. */
699 {
700 /* Sanity check that we're replacing oldval with a CONST_INT
701 that is a valid sign-extension for the original mode. */
705 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
706 CONST_INT is not valid, because after the replacement, the
707 original mode would be gone. Unfortunately, we can't tell
708 when do_SUBST is called to replace the operand thereof, so we
709 perform this test on oldval instead, checking whether an
710 invalid replacement took place before we got here. */
715 }
719 else
728 }
730 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
732 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
733 for the value of a HOST_WIDE_INT value (including CONST_INT) is
734 not safe. */
736 static void
738 {
747 else
756 }
758 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but just substitute the mode. This is used when
761 changing the mode of a pseudo-register, so that any other
762 references to the entry in the regno_reg_rtx array will change as
763 well. */
765 static void
767 {
777 else
786 }
788 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
790 static void
792 {
801 else
810 }
812 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
813 \f
814 /* Subroutine of try_combine. Determine whether the replacement patterns
815 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
816 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
817 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
818 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
819 of all the instructions can be estimated and the replacements are more
820 expensive than the original sequence. */
822 static bool
825 {
830 /* Lookup the original insn_costs. */
835 {
838 {
842 }
843 else
844 {
848 }
849 }
850 else
851 {
854 }
856 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
857 correct that. */
862 /* Calculate the replacement insn_costs. */
871 {
881 }
882 else
883 {
886 }
889 {
898 optimize_this_for_speed_p);
902 {
905 }
906 else
908 }
910 /* Disallow this combination if both new_cost and old_cost are greater than
911 zero, and new_cost is greater than old cost. */
915 {
934 else
936 }
941 /* Update the uid_insn_cost array with the replacement costs. */
945 {
949 }
952 }
955 /* Delete any insns that copy a register to itself.
956 Return true if the CFG was changed. */
958 static bool
960 {
962 basic_block bb;
967 {
969 {
972 {
977 }
978 }
979 }
982 }
984 \f
985 /* Return false if we do not want to (or cannot) combine DEF. */
986 static bool
988 {
989 /* Do not consider if it is pre/post modification in MEM. */
995 /* Do not combine frame pointer adjustments. */
998 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1006 }
1008 /* Return false if we do not want to (or cannot) combine USE. */
1009 static bool
1011 {
1012 /* Do not consider the usage of the stack pointer by function call. */
1017 }
1019 /* Fill in log links field for all insns. */
1021 static void
1023 {
1024 basic_block bb;
1031 /* Pass through each block from the end, recording the uses of each
1032 register and establishing log links when def is encountered.
1033 Note that we do not clear next_use array in order to save time,
1034 so we have to test whether the use is in the same basic block as def.
1036 There are a few cases below when we do not consider the definition or
1037 usage -- these are taken from original flow.c did. Don't ask me why it is
1038 done this way; I don't know and if it works, I don't want to know. */
1041 {
1043 {
1047 /* Log links are created only once. */
1051 {
1067 /* flow.c claimed:
1069 We don't build a LOG_LINK for hard registers contained
1070 in ASM_OPERANDs. If these registers get replaced,
1071 we might wind up changing the semantics of the insn,
1072 even if reload can make what appear to be valid
1073 assignments later. */
1078 /* Don't add duplicate links between instructions. */
1087 }
1092 }
1093 }
1096 }
1098 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1099 true if we found a LOG_LINK that proves that A feeds B. This only works
1100 if there are no instructions between A and B which could have a link
1101 depending on A, since in that case we would not record a link for B. */
1103 static bool
1105 {
1111 }
1112 \f
1113 /* Main entry point for combiner. F is the first insn of the function.
1114 NREGS is the first unused pseudo-reg number.
1116 Return nonzero if the CFG was changed (e.g. if the combiner has
1117 turned an indirect jump instruction into a direct jump). */
1118 static bool
1120 {
1124 basic_block last_bb;
1144 /* Allocate array for insn info. */
1152 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1153 problems when, for example, we have j <<= 1 in a loop. */
1158 /* Scan all SETs and see if we can deduce anything about what
1159 bits are known to be zero for some registers and how many copies
1160 of the sign bit are known to exist for those registers.
1162 Also set any known values so that we can use it while searching
1163 for what bits are known to be set. */
1166 /* Allow the entry block and the first block to fall into the same EBB.
1167 Conceptually the incoming promotions are assigned to the entry block. */
1172 {
1177 label_tick++;
1185 {
1186 rtx links;
1198 insn);
1200 /* Record the current insn_cost of this instruction. */
1203 {
1206 }
1207 }
1208 }
1212 /* Now scan all the insns in forward order. */
1220 {
1223 /* Ignore instruction combination in basic blocks that are going to
1224 be removed as unreachable anyway. See PR82386. */
1232 label_tick++;
1242 {
1256 /* See if we know about function return values before this
1257 insn based upon SUBREG flags. */
1260 /* See if we can find hardregs and subreg of pseudos in
1261 narrower modes. This could help turning TRUNCATEs
1262 into SUBREGs. */
1265 /* Try this insn with each insn it links back to. */
1271 {
1274 }
1276 /* Try each sequence of three linked insns ending with this one. */
1280 {
1283 /* If the linked insn has been replaced by a note, then there
1284 is no point in pursuing this chain any further. */
1292 {
1295 }
1296 }
1298 /* Try combining an insn with two different insns whose results it
1299 uses. */
1309 {
1312 }
1314 /* Try four-instruction combinations. */
1317 {
1321 /* If the linked insn has been replaced by a note, then there
1322 is no point in pursuing this chain any further. */
1327 {
1331 /* I0 -> I1 -> I2 -> I3. */
1337 {
1340 }
1341 /* I0, I1 -> I2, I2 -> I3. */
1348 {
1351 }
1352 }
1355 {
1359 /* I0 -> I2; I1, I2 -> I3. */
1365 {
1368 }
1369 /* I0 -> I1; I1, I2 -> I3. */
1375 {
1378 }
1379 }
1380 }
1382 /* Try this insn with each REG_EQUAL note it links back to. */
1384 {
1391 /* Avoid using a register that may already been marked
1392 dead by an earlier instruction. */
1400 {
1401 /* Temporarily replace the set's source with the
1402 contents of the REG_EQUAL note. The insn will
1403 be deleted or recognized by try_combine. */
1414 last_combined_insn);
1417 {
1420 }
1424 }
1425 }
1430 retry:
1431 ;
1432 }
1433 }
1443 /* Clean up. */
1449 {
1452 {
1455 }
1457 }
1467 /* Make recognizer allow volatile MEMs again. */
1471 }
1473 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1475 static void
1477 {
1483 }
1484 \f
1485 /* Set up any promoted values for incoming argument registers. */
1487 static void
1489 {
1490 tree arg;
1495 {
1500 /* Only continue if the incoming argument is in a register. */
1504 /* Determine, if possible, whether all call sites of the current
1505 function lie within the current compilation unit. (This does
1506 take into account the exporting of a function via taking its
1507 address, and so forth.) */
1508 strictly_local
1511 /* The mode and signedness of the argument before any promotions happen
1512 (equal to the mode of the pseudo holding it at that stage). */
1516 /* The mode and signedness of the argument after any source language and
1517 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1521 /* The mode and signedness of the argument as it is actually passed,
1522 see assign_parm_setup_reg in function.cc. */
1526 /* The mode of the register in which the argument is being passed. */
1529 /* Eliminate sign extensions in the callee when:
1530 (a) A mode promotion has occurred; */
1533 /* (b) The mode of the register is the same as the mode of
1534 the argument as it is passed; */
1537 /* (c) There's no language level extension; */
1539 ;
1540 /* (c.1) All callers are from the current compilation unit. If that's
1541 the case we don't have to rely on an ABI, we only have to know
1542 what we're generating right now, and we know that we will do the
1543 mode1 to mode2 promotion with the given sign. */
1546 /* (c.2) The combination of the two promotions is useful. This is
1547 true when the signs match, or if the first promotion is unsigned.
1548 In the later case, (sign_extend (zero_extend x)) is the same as
1549 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1555 /* Record that the value was promoted from mode1 to mode3,
1556 so that any sign extension at the head of the current
1557 function may be eliminated. */
1561 }
1562 }
1564 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1565 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1566 because some machines (maybe most) will actually do the sign-extension and
1567 this is the conservative approach.
1569 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1570 kludge. */
1572 static rtx
1574 {
1575 scalar_int_mode int_mode;
1584 }
1586 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1587 and SET. */
1589 static void
1591 rtx x)
1592 {
1602 {
1606 }
1608 /* Don't call nonzero_bits if it cannot change anything. */
1610 {
1619 }
1621 /* Don't call num_sign_bit_copies if it cannot change anything. */
1623 {
1626 {
1630 }
1633 }
1634 }
1636 /* Called via note_stores. If X is a pseudo that is narrower than
1637 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1639 If we are setting only a portion of X and we can't figure out what
1640 portion, assume all bits will be used since we don't know what will
1641 be happening.
1643 Similarly, set how many bits of X are known to be copies of the sign bit
1644 at all locations in the function. This is the smallest number implied
1645 by any set of X. */
1647 static void
1649 {
1651 scalar_int_mode mode;
1655 /* If this register is undefined at the start of the file, we can't
1656 say what its contents were. */
1657 && ! REGNO_REG_SET_P
1661 {
1665 {
1669 }
1671 /* If this register is being initialized using itself, and the
1672 register is uninitialized in this basic block, and there are
1673 no LOG_LINKS which set the register, then part of the
1674 register is uninitialized. In that case we can't assume
1675 anything about the number of nonzero bits.
1677 ??? We could do better if we checked this in
1678 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1679 could avoid making assumptions about the insn which initially
1680 sets the register, while still using the information in other
1681 insns. We would have to be careful to check every insn
1682 involved in the combination. */
1688 {
1695 {
1699 }
1700 }
1702 /* If this is a complex assignment, see if we can convert it into a
1703 simple assignment. */
1706 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1707 set what we know about X. */
1713 else
1714 {
1717 }
1718 }
1719 }
1720 \f
1721 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1722 optionally insns that were previously combined into I3 or that will be
1723 combined into the merger of INSN and I3. The order is PRED, PRED2,
1724 INSN, SUCC, SUCC2, I3.
1726 Return false if the combination is not allowed for any reason.
1728 If the combination is allowed, *PDEST will be set to the single
1729 destination of INSN and *PSRC to the single source, and this function
1730 will return true. */
1732 static bool
1736 {
1741 rtx link;
1746 {
1748 {
1753 }
1758 }
1762 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1763 or a PARALLEL consisting of such a SET and CLOBBERs.
1765 If INSN has CLOBBER parallel parts, ignore them for our processing.
1766 By definition, these happen during the execution of the insn. When it
1767 is merged with another insn, all bets are off. If they are, in fact,
1768 needed and aren't also supplied in I3, they may be added by
1769 recog_for_combine. Otherwise, it won't match.
1771 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1772 note.
1774 Get the source and destination of INSN. If more than one, can't
1775 combine. */
1781 {
1783 {
1787 {
1788 /* This is important to combine floating point insns
1789 for the SH4 port. */
1791 /* Combining an isolated USE doesn't make sense.
1792 We depend here on combinable_i3pat to reject them. */
1793 /* The code below this loop only verifies that the inputs of
1794 the SET in INSN do not change. We call reg_set_between_p
1795 to verify that the REG in the USE does not change between
1796 I3 and INSN.
1797 If the USE in INSN was for a pseudo register, the matching
1798 insn pattern will likely match any register; combining this
1799 with any other USE would only be safe if we knew that the
1800 used registers have identical values, or if there was
1801 something to tell them apart, e.g. different modes. For
1802 now, we forgo such complicated tests and simply disallow
1803 combining of USES of pseudo registers with any other USE. */
1806 {
1811 do
1812 {
1822 }
1824 }
1827 /* We can ignore CLOBBERs. */
1832 /* Ignore SETs whose result isn't used but not those that
1833 have side-effects. */
1839 /* If we have already found a SET, this is a second one and
1840 so we cannot combine with this insn. */
1848 /* Anything else means we can't combine. */
1850 }
1851 }
1854 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1855 so don't do anything with it. */
1858 }
1859 else
1865 /* The simplification in expand_field_assignment may call back to
1866 get_last_value, so set safe guard here. */
1872 /* Do not eliminate user-specified register if it is in an
1873 asm input because we may break the register asm usage defined
1874 in GCC manual if allow to do so.
1875 Be aware that this may cover more cases than we expect but this
1876 should be harmless. */
1881 /* Don't eliminate a store in the stack pointer. */
1883 /* Don't combine with an insn that sets a register to itself if it has
1884 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1886 /* Can't merge an ASM_OPERANDS. */
1888 /* Can't merge a function call. */
1890 /* Don't eliminate a function call argument. */
1896 /* Don't substitute into an incremented register. */
1900 /* Don't substitute into a non-local goto, this confuses CFG. */
1902 /* Make sure that DEST is not used after INSN but before SUCC, or
1903 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1904 || (!all_adjacent
1905 && ((succ2
1910 || (succ
1911 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1912 that case SUCC is not in the insn stream, so use SUCC2
1913 instead for this test. */
1915 succ2
1918 /* Make sure that the value that is to be substituted for the register
1919 does not use any registers whose values alter in between. However,
1920 If the insns are adjacent, a use can't cross a set even though we
1921 think it might (this can happen for a sequence of insns each setting
1922 the same destination; last_set of that register might point to
1923 a NOTE). If INSN has a REG_EQUIV note, the register is always
1924 equivalent to the memory so the substitution is valid even if there
1925 are intervening stores. Also, don't move a volatile asm or
1926 UNSPEC_VOLATILE across any other insns. */
1927 || (! all_adjacent
1933 /* Don't combine across a CALL_INSN, because that would possibly
1934 change whether the life span of some REGs crosses calls or not,
1935 and it is a pain to update that information.
1936 Exception: if source is a constant, moving it later can't hurt.
1937 Accept that as a special case. */
1941 /* DEST must be a REG. */
1943 {
1944 /* If register alignment is being enforced for multi-word items in all
1945 cases except for parameters, it is possible to have a register copy
1946 insn referencing a hard register that is not allowed to contain the
1947 mode being copied and which would not be valid as an operand of most
1948 insns. Eliminate this problem by not combining with such an insn.
1950 Also, on some machines we don't want to extend the life of a hard
1951 register. */
1956 /* Don't extend the life of a hard register unless it is
1957 user variable (if we have few registers) or it can't
1958 fit into the desired register (meaning something special
1959 is going on).
1960 Also avoid substituting a return register into I3, because
1961 reload can't handle a conflict with constraints of other
1962 inputs. */
1967 }
1968 else
1975 {
1978 /* If the clobber represents an earlyclobber operand, we must not
1979 substitute an expression containing the clobbered register.
1980 As we do not analyze the constraint strings here, we have to
1981 make the conservative assumption. However, if the register is
1982 a fixed hard reg, the clobber cannot represent any operand;
1983 we leave it up to the machine description to either accept or
1984 reject use-and-clobber patterns. */
1990 }
1992 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1993 or not), reject, unless nothing volatile comes between it and I3 */
1996 {
1997 /* Make sure neither succ nor succ2 contains a volatile reference. */
2002 /* We'll check insns between INSN and I3 below. */
2003 }
2005 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2006 to be an explicit register variable, and was chosen for a reason. */
2012 /* If INSN contains volatile references (specifically volatile MEMs),
2013 we cannot combine across any other volatile references.
2014 Even if INSN doesn't contain volatile references, any intervening
2015 volatile insn might affect machine state. */
2018 ? volatile_refs_p
2025 /* If INSN contains an autoincrement or autodecrement, make sure that
2026 register is not used between there and I3, and not already used in
2027 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2028 Also insist that I3 not be a jump if using LRA; if it were one
2029 and the incremented register were spilled, we would lose.
2030 Reload handles this correctly. */
2048 /* If we get here, we have passed all the tests and the combination is
2049 to be allowed. */
2055 }
2056 \f
2057 /* LOC is the location within I3 that contains its pattern or the component
2058 of a PARALLEL of the pattern. We validate that it is valid for combining.
2060 One problem is if I3 modifies its output, as opposed to replacing it
2061 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2062 doing so would produce an insn that is not equivalent to the original insns.
2064 Consider:
2066 (set (reg:DI 101) (reg:DI 100))
2067 (set (subreg:SI (reg:DI 101) 0) <foo>)
2069 This is NOT equivalent to:
2071 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2072 (set (reg:DI 101) (reg:DI 100))])
2074 Not only does this modify 100 (in which case it might still be valid
2075 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2077 We can also run into a problem if I2 sets a register that I1
2078 uses and I1 gets directly substituted into I3 (not via I2). In that
2079 case, we would be getting the wrong value of I2DEST into I3, so we
2080 must reject the combination. This case occurs when I2 and I1 both
2081 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2082 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2083 of a SET must prevent combination from occurring. The same situation
2084 can occur for I0, in which case I0_NOT_IN_SRC is set.
2086 Before doing the above check, we first try to expand a field assignment
2087 into a set of logical operations.
2089 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2090 we place a register that is both set and used within I3. If more than one
2091 such register is detected, we fail.
2093 Return true if the combination is valid, false otherwise. */
2095 static bool
2098 {
2102 {
2107 rtx subdest;
2114 /* Check for the case where I3 modifies its output, as discussed
2115 above. We don't want to prevent pseudos from being combined
2116 into the address of a MEM, so only prevent the combination if
2117 i1 or i2 set the same MEM. */
2127 /* This is the same test done in can_combine_p except we can't test
2128 all_adjacent; we don't have to, since this instruction will stay
2129 in place, thus we are not considering increasing the lifetime of
2130 INNER_DEST.
2132 Also, if this insn sets a function argument, combining it with
2133 something that might need a spill could clobber a previous
2134 function argument; the all_adjacent test in can_combine_p also
2135 checks this; here, we do a more specific test for this case. */
2145 /* If DEST is used in I3, it is being killed in this insn, so
2146 record that for later. We have to consider paradoxical
2147 subregs here, since they kill the whole register, but we
2148 ignore partial subregs, STRICT_LOW_PART, etc.
2149 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2150 STACK_POINTER_REGNUM, since these are always considered to be
2151 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2159 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2165 {
2170 }
2171 }
2174 {
2181 }
2184 }
2185 \f
2186 /* Return true if X is an arithmetic expression that contains a multiplication
2187 and division. We don't count multiplications by powers of two here. */
2189 static bool
2191 {
2193 {
2209 }
2210 }
2211 \f
2212 /* Determine whether INSN can be used in a combination. Return true if
2213 not. This is used in try_combine to detect early some cases where we
2214 can't perform combinations. */
2216 static bool
2218 {
2219 rtx set;
2222 /* If this isn't really an insn, we can't do anything.
2223 This can occur when flow deletes an insn that it has merged into an
2224 auto-increment address. */
2228 /* Never combine loads and stores involving hard regs that are likely
2229 to be spilled. The register allocator can usually handle such
2230 reg-reg moves by tying. If we allow the combiner to make
2231 substitutions of likely-spilled regs, reload might die.
2232 As an exception, we allow combinations involving fixed regs; these are
2233 not available to the register allocator so there's no risk involved. */
2247 #ifdef LEAF_REGISTERS
2249 #else
2250 )
2251 #endif
2258 }
2260 struct likely_spilled_retval_info
2261 {
2264 };
2266 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2267 hard registers that are known to be written to / clobbered in full. */
2268 static void
2270 {
2287 else
2290 }
2292 /* Return true iff part of the return value is live during INSN, and
2293 it is likely spilled. This can happen when more than one insn is needed
2294 to copy the return value, e.g. when we consider to combine into the
2295 second copy insn for a complex value. */
2297 static bool
2299 {
2301 rtx reg;
2304 /* We assume here that no machine mode needs more than
2305 32 hard registers when the value overlaps with a register
2306 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2321 /* Disregard parts of the return value that are set later. */
2330 /* Check if any of the (probably) live return value registers is
2331 likely spilled. */
2332 nregs --;
2333 do
2334 {
2340 }
2342 /* Adjust INSN after we made a change to its destination.
2344 Changing the destination can invalidate notes that say something about
2345 the results of the insn and a LOG_LINK pointing to the insn. */
2347 static void
2349 {
2350 /* For notes, be conservative and simply remove them. */
2353 /* The new insn will have a destination that was previously the destination
2354 of an insn just above it. Call distribute_links to make a LOG_LINK from
2355 the next use of that destination. */
2371 }
2373 /* Return TRUE if combine can reuse reg X in mode MODE.
2374 ADDED_SETS is trueif the original set is still required. */
2375 static bool
2377 {
2383 /* Don't change between modes with different underlying register sizes,
2384 since this could lead to invalid subregs. */
2390 /* Allow hard registers if the new mode is legal, and occupies no more
2391 registers than the old mode. */
2396 /* Or a pseudo that is only used once. */
2399 && !added_sets
2401 }
2404 /* Check whether X, the destination of a set, refers to part of
2405 the register specified by REG. */
2407 static bool
2409 {
2410 /* Check that reg is an integer mode register. */
2422 }
2424 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2425 by an arbitrary number of CLOBBERs. */
2426 static bool
2428 {
2443 {
2450 }
2452 }
2454 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2455 CLOBBERs), can be split into individual SETs in that order, without
2456 changing semantics. */
2457 static bool
2459 {
2467 {
2476 }
2479 }
2481 /* Return whether X is just a single_set, with the source
2482 a general_operand. */
2483 static bool
2485 {
2491 }
2493 /* Callback function to count autoincs. */
2495 static int
2497 {
2501 }
2503 /* Try to combine the insns I0, I1 and I2 into I3.
2504 Here I0, I1 and I2 appear earlier than I3.
2505 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2506 I3.
2508 If we are combining more than two insns and the resulting insn is not
2509 recognized, try splitting it into two insns. If that happens, I2 and I3
2510 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2511 Otherwise, I0, I1 and I2 are pseudo-deleted.
2513 Return 0 if the combination does not work. Then nothing is changed.
2514 If we did the combination, return the insn at which combine should
2515 resume scanning.
2517 Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2518 new direct jump instruction.
2520 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2521 been I3 passed to an earlier try_combine within the same basic
2522 block. */
2527 {
2528 /* New patterns for I3 and I2, respectively. */
2532 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2533 dead. */
2535 /* Total number of SETs to put into I3. */
2537 /* Nonzero if I2's or I1's body now appears in I3. */
2539 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2541 /* Contains I3 if the destination of I3 is used in its source, which means
2542 that the old life of I3 is being killed. If that usage is placed into
2543 I2 and not in I3, a REG_DEAD note must be made. */
2545 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2547 /* Copy of SET_SRC of I1 and I0, if needed. */
2549 /* Set if I2DEST was reused as a scratch register. */
2551 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2553 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2559 /* Notes that must be added to REG_NOTES in I3 and I2. */
2561 /* Notes that we substituted I3 into I2 instead of the normal case. */
2563 /* Notes that I1, I2 or I3 is a MULT operation. */
2573 rtx temp_expr;
2576 rtx new_other_notes;
2581 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2582 never be). */
2586 /* Only try four-insn combinations when there's high likelihood of
2587 success. Look for simple insns, such as loads of constants or
2588 binary operations involving a constant. */
2590 {
2600 {
2603 rtx src;
2608 {
2611 }
2613 ngood++;
2616 nshift++;
2617 }
2619 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2620 are likely manipulating its value. Ideally we'll be able to combine
2621 all four insns into a bitfield insertion of some kind.
2623 Note the source in I0 might be inside a sign/zero extension and the
2624 memory modes in I0 and I3 might be different. So extract the address
2625 from the destination of I3 and search for it in the source of I0.
2627 In the event that there's a match but the source/dest do not actually
2628 refer to the same memory, the worst that happens is we try some
2629 combinations that we wouldn't have otherwise. */
2631 /* Ensure the source of SET0 is a MEM, possibly buried inside
2632 an extension. */
2638 /* Ensure the destination of SET3 is a MEM. */
2640 /* Would it be better to extract the base address for the MEM
2641 in SET3 and look for that? I don't have cases where it matters
2642 but I could envision such cases. */
2648 }
2650 /* Exit early if one of the insns involved can't be used for
2651 combinations. */
2662 combine_attempts++;
2665 /* Reset the hard register usage information. */
2669 {
2676 else
2686 }
2688 /* If multiple insns feed into one of I2 or I3, they can be in any
2689 order. To simplify the code below, reorder them in sequence. */
2700 /* First check for one important special case that the code below will
2701 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2702 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2703 we may be able to replace that destination with the destination of I3.
2704 This occurs in the common code where we compute both a quotient and
2705 remainder into a structure, in which case we want to do the computation
2706 directly into the structure to avoid register-register copies.
2708 Note that this case handles both multiple sets in I2 and also cases
2709 where I2 has a number of CLOBBERs inside the PARALLEL.
2711 We make very conservative checks below and only try to handle the
2712 most common cases of this. For example, we only handle the case
2713 where I2 and I3 are adjacent to avoid making difficult register
2714 usage tests. */
2722 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2723 below would need to check what is inside (and reg_overlap_mentioned_p
2724 doesn't support those codes anyway). Don't allow those destinations;
2725 the resulting insn isn't likely to be recognized anyway. */
2731 {
2734 /* Make sure that the destination of I3,
2735 which we are going to substitute into one output of I2,
2736 is not used within another output of I2. We must avoid making this:
2737 (parallel [(set (mem (reg 69)) ...)
2738 (set (reg 69) ...)])
2739 which is not well-defined as to order of actions.
2740 (Besides, reload can't handle output reloads for this.)
2742 The problem can also happen if the dest of I3 is a memory ref,
2743 if another dest in I2 is an indirect memory ref.
2745 Neither can this PARALLEL be an asm. We do not allow combining
2746 that usually (see can_combine_p), so do not here either. */
2749 {
2758 }
2764 {
2765 combine_merges++;
2775 /* Replace the dest in I2 with our dest and make the resulting
2776 insn the new pattern for I3. Then skip to where we validate
2777 the pattern. Everything was set up above. */
2782 }
2783 }
2785 /* If I2 is setting a pseudo to a constant and I3 is setting some
2786 sub-part of it to another constant, merge them by making a new
2787 constant. */
2795 {
2802 {
2807 {
2813 }
2814 }
2815 else
2816 {
2820 {
2823 }
2824 }
2827 {
2828 /* If this is the low part, we're done. */
2830 ;
2831 /* Handle the case where inner is twice the size of outer. */
2835 /* Otherwise give up for now. */
2836 else
2838 }
2841 {
2849 combine_merges++;
2856 /* Replace the source in I2 with the new constant and make the
2857 resulting insn the new pattern for I3. Then skip to where we
2858 validate the pattern. Everything was set up above. */
2864 /* The dest of I3 has been replaced with the dest of I2. */
2867 }
2868 }
2870 /* If we have no I1 and I2 looks like:
2871 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2872 (set Y OP)])
2873 make up a dummy I1 that is
2874 (set Y OP)
2875 and change I2 to be
2876 (set (reg:CC X) (compare:CC Y (const_int 0)))
2878 (We can ignore any trailing CLOBBERs.)
2880 This undoes a previous combination and allows us to match a branch-and-
2881 decrement insn. */
2893 {
2894 /* We make I1 with the same INSN_UID as I2. This gives it
2895 the same DF_INSN_LUID for value tracking. Our fake I1 will
2896 never appear in the insn stream so giving it the same INSN_UID
2897 as I2 will not cause a problem. */
2910 }
2912 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2913 make those two SETs separate I1 and I2 insns, and make an I0 that is
2914 the original I1. */
2922 {
2923 /* If there is no I1, there is no I0 either. */
2926 /* We make I1 with the same INSN_UID as I2. This gives it
2927 the same DF_INSN_LUID for value tracking. Our fake I1 will
2928 never appear in the insn stream so giving it the same INSN_UID
2929 as I2 will not cause a problem. */
2937 }
2939 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2941 {
2946 }
2948 {
2953 }
2955 {
2960 }
2962 /* With non-call exceptions we can end up trying to combine multiple
2963 insns with possible EH side effects. Make sure we can combine
2964 that to a single insn which means there must be at most one insn
2965 in the combination with an EH side effect. */
2967 {
2972 {
2978 {
2984 }
2985 }
2986 }
2988 /* Record whether i2 and i3 are trivial moves. */
2992 /* Record whether I2DEST is used in I2SRC and similarly for the other
2993 cases. Knowing this will help in register status updating below. */
3004 /* For the earlier insns, determine which of the subsequent ones they
3005 feed. */
3012 /* Ensure that I3's pattern can be the destination of combines. */
3018 {
3021 }
3023 /* See if any of the insns is a MULT operation. Unless one is, we will
3024 reject a combination that is, since it must be slower. Be conservative
3025 here. */
3033 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3034 We used to do this EXCEPT in one case: I3 has a post-inc in an
3035 output operand. However, that exception can give rise to insns like
3036 mov r3,(r3)+
3037 which is a famous insn on the PDP-11 where the value of r3 used as the
3038 source was model-dependent. Avoid this sort of thing. */
3040 #if 0
3046 /* It's not the exception. */
3047 #endif
3049 {
3050 rtx link;
3056 {
3059 }
3060 }
3062 /* See if the SETs in I1 or I2 need to be kept around in the merged
3063 instruction: whenever the value set there is still needed past I3.
3064 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3066 For the SET in I1, we have two cases: if I1 and I2 independently feed
3067 into I3, the set in I1 needs to be kept around unless I1DEST dies
3068 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3069 in I1 needs to be kept around unless I1DEST dies or is set in either
3070 I2 or I3. The same considerations apply to I0. */
3077 else
3085 else
3088 /* We are about to copy insns for the case where they need to be kept
3089 around. Check that they can be copied in the merged instruction. */
3095 {
3098 }
3100 /* We cannot safely duplicate volatile references in any case. */
3105 {
3108 }
3110 /* Count how many auto_inc expressions there were in the original insns;
3111 we need to have the same number in the resulting patterns. */
3120 /* If the set in I2 needs to be kept around, we must make a copy of
3121 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3122 PATTERN (I2), we are only substituting for the original I1DEST, not into
3123 an already-substituted copy. This also prevents making self-referential
3124 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3125 I2DEST. */
3128 {
3131 else
3133 }
3136 {
3139 else
3141 }
3144 {
3147 else
3149 }
3151 combine_merges++;
3153 /* Substitute in the latest insn for the regs set by the earlier ones. */
3159 /* Many machines have insns that can both perform an
3160 arithmetic operation and set the condition code. These operations will
3161 be represented as a PARALLEL with the first element of the vector
3162 being a COMPARE of an arithmetic operation with the constant zero.
3163 The second element of the vector will set some pseudo to the result
3164 of the same arithmetic operation. If we simplify the COMPARE, we won't
3165 match such a pattern and so will generate an extra insn. Here we test
3166 for this case, where both the comparison and the operation result are
3167 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3168 I2SRC. Later we will make the PARALLEL that contains I2. */
3174 {
3175 rtx newpat_dest;
3181 scalar_int_mode mode;
3190 {
3196 }
3198 /* Do the rest only if op1 is const0_rtx, which may be the
3199 result of simplification. */
3201 {
3202 /* If a single use of the CC is found, prepare to modify it
3203 when SELECT_CC_MODE returns a new CC-class mode, or when
3204 the above simplify_compare_const() returned a new comparison
3205 operator. undobuf.other_insn is assigned the CC use insn
3206 when modifying it. */
3208 {
3209 #ifdef SELECT_CC_MODE
3210 machine_mode new_mode
3215 {
3220 else
3221 {
3224 }
3225 }
3226 #endif
3227 /* Cases for modifying the CC-using comparison. */
3229 /* ??? Do we need to verify the zero rtx? */
3231 {
3232 /* Replace cc_use_loc with entire new RTX. */
3237 }
3239 {
3240 /* Just replace the CC reg with a new mode. */
3243 }
3244 }
3246 /* Now we modify the current newpat:
3247 First, SET_DEST(newpat) is updated if the CC mode has been
3248 altered. For targets without SELECT_CC_MODE, this should be
3249 optimized away. */
3252 /* This is always done to propagate i2src into newpat. */
3255 /* Create new version of i2pat if needed; the below PARALLEL
3256 creation needs this to work correctly. */
3260 }
3261 }
3264 {
3265 /* It is possible that the source of I2 or I1 may be performing
3266 an unneeded operation, such as a ZERO_EXTEND of something
3267 that is known to have the high part zero. Handle that case
3268 by letting subst look at the inner insns.
3270 Another way to do this would be to have a function that tries
3271 to simplify a single insn instead of merging two or more
3272 insns. We don't do this because of the potential of infinite
3273 loops and because of the potential extra memory required.
3274 However, doing it the way we are is a bit of a kludge and
3275 doesn't catch all cases.
3277 But only do this if -fexpensive-optimizations since it slows
3278 things down and doesn't usually win.
3280 This is not done in the COMPARE case above because the
3281 unmodified I2PAT is used in the PARALLEL and so a pattern
3282 with a modified I2SRC would not match. */
3285 {
3286 /* Pass pc_rtx so no substitutions are done, just
3287 simplifications. */
3289 {
3292 }
3296 }
3301 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3302 copy of I2SRC each time we substitute it, in order to avoid creating
3303 self-referential RTL when we will be substituting I1SRC for I1DEST
3304 later. Likewise if I0 feeds into I2, either directly or indirectly
3305 through I1, and I0DEST is in I0SRC. */
3312 /* Record whether I2's body now appears within I3's body. */
3314 }
3316 /* If we already got a failure, don't try to do more. Otherwise, try to
3317 substitute I1 if we have it. */
3320 {
3321 /* Before we can do this substitution, we must redo the test done
3322 above (see detailed comments there) that ensures I1DEST isn't
3323 mentioned in any SETs in NEWPAT that are field assignments. */
3326 {
3329 }
3334 /* If the following substitution will modify I1SRC, make a copy of it
3335 for the case where it is substituted for I1DEST in I2PAT later. */
3339 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3340 copy of I1SRC each time we substitute it, in order to avoid creating
3341 self-referential RTL when we will be substituting I0SRC for I0DEST
3342 later. */
3347 /* Record whether I1's body now appears within I3's body. */
3349 }
3351 /* Likewise for I0 if we have it. */
3354 {
3357 {
3360 }
3362 /* If the following substitution will modify I0SRC, make a copy of it
3363 for the case where it is substituted for I0DEST in I1PAT later. */
3366 /* And a copy for I0DEST in I2PAT substitution. */
3375 }
3378 {
3383 {
3388 }
3389 }
3391 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3392 to count all the ways that I2SRC and I1SRC can be used. */
3401 /* Fail if we tried to make a new register. */
3403 /* Fail if we couldn't do something and have a CLOBBER. */
3405 /* Fail if this new pattern is a MULT and we didn't have one before
3406 at the outer level. */
3409 {
3412 }
3414 /* If the actions of the earlier insns must be kept
3415 in addition to substituting them into the latest one,
3416 we must make a new PARALLEL for the latest insn
3417 to hold additional the SETs. */
3420 {
3422 combine_extras++;
3425 {
3431 }
3432 else
3433 {
3438 }
3444 {
3451 }
3453 {
3463 }
3464 }
3466 validate_replacement:
3468 /* Note which hard regs this insn has as inputs. */
3471 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3472 consider splitting this pattern, we might need these clobbers. */
3475 {
3481 }
3483 /* We have recognized nothing yet. */
3486 /* See if this is a PARALLEL of two SETs where one SET's destination is
3487 a register that is unused and this isn't marked as an instruction that
3488 might trap in an EH region. In that case, we just need the other SET.
3489 We prefer this over the PARALLEL.
3491 This can occur when simplifying a divmod insn. We *must* test for this
3492 case here because the code below that splits two independent SETs doesn't
3493 handle this case correctly when it updates the register status.
3495 It's pointless doing this if we originally had two sets, one from
3496 i3, and one from i2. Combining then splitting the parallel results
3497 in the original i2 again plus an invalid insn (which we delete).
3498 The net effect is only to move instructions around, which makes
3499 debug info less accurate.
3501 If the remaining SET came from I2 its destination should not be used
3502 between I2 and I3. See PR82024. */
3507 {
3518 {
3521 }
3530 {
3535 {
3541 }
3542 }
3546 }
3548 /* Is the result of combination a valid instruction? */
3552 /* If we were combining three insns and the result is a simple SET
3553 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3554 insns. There are two ways to do this. It can be split using a
3555 machine-specific method (like when you have an addition of a large
3556 constant) or by combine in the function find_split_point. */
3560 {
3564 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3565 use I2DEST as a scratch register will help. In the latter case,
3566 convert I2DEST to the mode of the source of NEWPAT if we can. */
3570 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3571 inputs of NEWPAT. */
3573 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3574 possible to try that as a scratch reg. This would require adding
3575 more code to make it work though. */
3578 {
3581 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3582 (temporarily, until we are committed to this instruction
3583 combination) does not work: for example, any call to nonzero_bits
3584 on the register (from a splitter in the MD file, for example)
3585 will get the old information, which is invalid.
3587 Since nowadays we can create registers during combine just fine,
3588 we should just create a new one here, not reuse i2dest. */
3590 /* First try to split using the original register as a
3591 scratch register. */
3595 i2dest)));
3598 /* If that didn't work, try changing the mode of I2DEST if
3599 we can. */
3604 {
3606 rtx ni2dest;
3610 else
3611 {
3614 }
3616 parallel = (gen_rtx_PARALLEL
3620 ni2dest))));
3625 {
3633 }
3634 }
3637 }
3639 /* If recog_for_combine has discarded clobbers, try to use them
3640 again for the split. */
3642 {
3645 }
3648 {
3653 }
3657 {
3667 /* If I2 or I3 has multiple SETs, we won't know how to track
3668 register status, so don't use these insns. If I2's destination
3669 is used between I2 and I3, we also can't use these insns. */
3679 /* It is possible that both insns now set the destination of I3.
3680 If so, we must show an extra use of it. */
3683 {
3702 }
3703 }
3705 /* If we can split it and use I2DEST, go ahead and see if that
3706 helps things be recognized. Verify that none of the registers
3707 are set between I2 and I3. */
3710 /* We need I2DEST in the proper mode. If it is a hard register
3711 or the only use of a pseudo, we can change its mode.
3712 Make sure we don't change a hard register to have a mode that
3713 isn't valid for it, or change the number of registers. */
3720 /* We can't overwrite I2DEST if its value is still used by
3721 NEWPAT. */
3723 /* We should not split a possibly trapping part when we
3724 care about non-call EH and have REG_EH_REGION notes
3725 to distribute. */
3727 && has_non_call_exception
3729 {
3738 /* *SPLIT may be part of I2SRC, so make sure we have the
3739 original expression around for later debug processing.
3740 We should not need I2SRC any more in other cases. */
3743 else
3746 /* Get NEWDEST as a register in the proper mode. We have already
3747 validated that we can do this. */
3749 {
3752 else
3753 {
3756 }
3757 }
3759 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3760 an ASHIFT. This can occur if it was inside a PLUS and hence
3761 appeared to be a memory address. This is a kludge. */
3766 {
3770 /* Update split_code because we may not have a multiply
3771 anymore. */
3773 }
3775 /* Similarly for (plus (mult FOO (const_int pow2))). */
3781 {
3786 i_rtx));
3787 /* Update split_code because we may not have a multiply
3788 anymore. */
3790 }
3792 #ifdef INSN_SCHEDULING
3793 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3794 be written as a ZERO_EXTEND. */
3796 {
3797 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3798 what it really is. */
3803 else
3806 }
3807 #endif
3809 /* Attempt to split binary operators using arithmetic identities. */
3813 {
3820 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3822 {
3827 }
3828 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3835 {
3841 /* Split both "((X op Y) op X) op Y" and
3842 "((X op Y) op Y) op X" as "T op T" where T is
3843 "X op Y". */
3846 {
3851 }
3852 /* Split "((X op X) op Y) op Y)" as "T op T" where
3853 T is "X op Y". */
3855 {
3861 }
3862 }
3863 }
3866 {
3869 }
3873 /* recog_for_combine might have added CLOBBERs to newi2pat.
3874 Make sure NEWPAT does not depend on the clobbered regs. */
3878 {
3881 {
3884 }
3885 }
3887 /* If the split point was a MULT and we didn't have one before,
3888 don't use one now. */
3891 }
3892 }
3894 /* Check for a case where we loaded from memory in a narrow mode and
3895 then sign extended it, but we need both registers. In that case,
3896 we have a PARALLEL with both loads from the same memory location.
3897 We can split this into a load from memory followed by a register-register
3898 copy. This saves at least one insn, more if register allocation can
3899 eliminate the copy.
3901 We cannot do this if the destination of the first assignment is a
3902 condition code register. We eliminate this case by making sure
3903 the SET_DEST and SET_SRC have the same mode.
3905 We cannot do this if the destination of the second assignment is
3906 a register that we have already assumed is zero-extended. Similarly
3907 for a SUBREG of such a register. */
3926 BITS_PER_WORD)
3928 HOST_BITS_PER_INT)
3936 BITS_PER_WORD)
3938 HOST_BITS_PER_INT)
3945 {
3946 rtx ni2dest;
3960 }
3962 /* Similarly, check for a case where we have a PARALLEL of two independent
3963 SETs but we started with three insns. In this case, we can do the sets
3964 as two separate insns. This case occurs when some SET allows two
3965 other insns to combine, but the destination of that SET is still live.
3967 Also do this if we started with two insns and (at least) one of the
3968 resulting sets is a noop; this noop will be deleted later.
3970 Also do this if we started with two insns neither of which was a simple
3971 move. */
3978 && (i1
3992 {
3996 /* Normally, it doesn't matter which of the two is done first, but
3997 one which uses any regs/memory set in between i2 and i3 can't
3998 be first. The PARALLEL might also have been pre-existing in i3,
3999 so we need to make sure that we won't wrongly hoist a SET to i2
4000 that would conflict with a death note present in there, or would
4001 have its dest modified between i2 and i3. */
4009 /* If I3 is a jump, ensure that set0 is a jump so that
4010 we do not create invalid RTL. */
4012 )
4013 {
4016 }
4024 /* If I3 is a jump, ensure that set1 is a jump so that
4025 we do not create invalid RTL. */
4027 )
4028 {
4031 }
4032 else
4033 {
4036 }
4041 {
4042 /* recog_for_combine might have added CLOBBERs to newi2pat.
4043 Make sure NEWPAT does not depend on the clobbered regs. */
4045 {
4048 {
4051 {
4054 }
4055 }
4056 }
4060 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4061 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4062 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4064 {
4067 {
4071 {
4074 }
4075 }
4076 }
4080 }
4081 }
4083 /* If it still isn't recognized, fail and change things back the way they
4084 were. */
4086 /* Is the result a reasonable ASM_OPERANDS? */
4088 {
4091 }
4093 /* If we had to change another insn, make sure it is valid also. */
4095 {
4103 {
4106 }
4107 }
4109 /* Only allow this combination if insn_cost reports that the
4110 replacement instructions are cheaper than the originals. */
4112 {
4115 }
4118 {
4123 {
4128 /* Temporarily revert mode back. */
4132 {
4133 /* If we used i2dest as a scratch register with a
4134 different mode, substitute it for the original
4135 i2src while its original mode is temporarily
4136 restored, and then clear i2scratch so that we don't
4137 do it again later. */
4139 this_basic_block);
4141 /* Put back the new mode. */
4143 }
4144 else
4145 {
4150 {
4153 }
4154 else
4155 {
4162 }
4164 /* We're dealing with a reg that changed mode but not
4165 meaning, so we want to turn it into a subreg for
4166 the new mode. However, because of REG sharing and
4167 because its mode had already changed, we have to do
4168 it in two steps. First, replace any debug uses of
4169 reg, with its original mode temporarily restored,
4170 with this copy we have created; then, replace the
4171 copy with the SUBREG of the original shared reg,
4172 once again changed to the new mode. */
4174 this_basic_block);
4178 this_basic_block);
4179 }
4180 }
4181 }
4183 /* If we will be able to accept this, we have made a
4184 change to the destination of I3. This requires us to
4185 do a few adjustments. */
4188 {
4191 }
4193 /* We now know that we can do this combination. Merge the insns and
4194 update the status of registers and LOG_LINKS. */
4197 {
4202 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4203 ensure that they are still valid. Then add any non-duplicate
4204 notes added by recog_for_combine. */
4206 {
4215 /* Simply drop equal note since it may be no longer valid
4216 for other_insn. It may be possible to record that CC
4217 register is changed and only discard those notes, but
4218 in practice it's unnecessary complication and doesn't
4219 give any meaningful improvement.
4221 See PR78559. */
4225 }
4229 NULL_RTX);
4230 }
4233 {
4234 /* I3 now uses what used to be its destination and which is now
4235 I2's destination. This requires us to do a few adjustments. */
4238 }
4241 {
4242 /* We might need a LOG_LINK from I3 to I2. But then we used to
4243 have one, so we still will.
4245 However, some later insn might be using I2's dest and have
4246 a LOG_LINK pointing at I3. We should change it to point at
4247 I2 instead. */
4249 /* newi2pat is usually a SET here; however, recog_for_combine might
4250 have added some clobbers. */
4258 {
4263 !done
4264 && insn
4268 {
4274 {
4278 }
4279 }
4280 }
4281 }
4283 {
4288 /* Compute which registers we expect to eliminate. newi2pat may be setting
4289 either i3dest or i2dest, so we must check it. */
4292 || !i2dest_killed
4294 /* For i1, we need to compute both local elimination and global
4295 elimination information with respect to newi2pat because i1dest
4296 may be the same as i3dest, in which case newi2pat may be setting
4297 i1dest. Global information is used when distributing REG_DEAD
4298 note for i2 and i3, in which case it does matter if newi2pat sets
4299 i1dest or not.
4301 Local information is used when distributing REG_DEAD note for i1,
4302 in which case it doesn't matter if newi2pat sets i1dest or not.
4303 See PR62151, if we have four insns combination:
4304 i0: r0 <- i0src
4305 i1: r1 <- i1src (using r0)
4306 REG_DEAD (r0)
4307 i2: r0 <- i2src (using r1)
4308 i3: r3 <- i3src (using r0)
4309 ix: using r0
4310 From i1's point of view, r0 is eliminated, no matter if it is set
4311 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4312 should be discarded.
4314 Note local information only affects cases in forms like "I1->I2->I3",
4315 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4316 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4317 i0dest anyway. */
4319 || !i1dest_killed
4324 /* Same case as i1. */
4331 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4332 clear them. */
4340 /* Ensure that we do not have something that should not be shared but
4341 occurs multiple times in the new insns. Check this by first
4342 resetting all the `used' flags and then copying anything is shared. */
4366 {
4369 {
4371 {
4372 /* I2SRC must still be meaningful at this point. Some
4373 splitting operations can invalidate I2SRC, but those
4374 operations do not apply to calls. */
4378 }
4385 }
4386 }
4391 /* We had one special case above where I2 had more than one set and
4392 we replaced a destination of one of those sets with the destination
4393 of I3. In that case, we have to update LOG_LINKS of insns later
4394 in this basic block. Note that this (expensive) case is rare.
4396 Also, in this case, we must pretend that all REG_NOTEs for I2
4397 actually came from I3, so that REG_UNUSED notes from I2 will be
4398 properly handled. */
4401 {
4410 temp_insn
4420 {
4425 }
4426 else
4429 }
4437 {
4440 this_basic_block);
4443 }
4444 else
4445 {
4448 this_basic_block);
4450 }
4453 {
4458 this_basic_block);
4460 }
4463 {
4468 this_basic_block);
4470 }
4472 /* Get death notes for everything that is now used in either I3 or
4473 I2 and used to die in a previous insn. If we built two new
4474 patterns, move from I1 to I2 then I2 to I3 so that we get the
4475 proper movement on registers that I2 modifies. */
4481 else
4487 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4504 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4505 know these are REG_UNUSED and want them to go to the desired insn,
4506 so we always pass it as i3. */
4510 NULL_RTX);
4514 NULL_RTX);
4516 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4517 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4518 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4519 in that case, it might delete I2. Similarly for I2 and I1.
4520 Show an additional death due to the REG_DEAD note we make here. If
4521 we discard it in distribute_notes, we will decrement it again. */
4524 {
4529 else
4532 }
4535 {
4540 else
4543 }
4546 {
4551 else
4554 }
4557 {
4562 else
4565 }
4573 {
4578 /* The insn that used to set this register doesn't exist, and
4579 this life of the register may not exist either. See if one of
4580 I3's links points to an insn that sets I2DEST. If it does,
4581 that is now the last known value for I2DEST. If we don't update
4582 this and I2 set the register to a value that depended on its old
4583 contents, we will get confused. If this insn is used, thing
4584 will be set correctly in combine_instructions. */
4592 /* If the reg formerly set in I2 died only once and that was in I3,
4593 zero its use count so it won't make `reload' do any work. */
4596 && ! i2dest_in_i2src
4599 }
4602 {
4615 && ! i1dest_in_i1src
4618 }
4621 {
4634 && ! i0dest_in_i0src
4637 }
4639 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4640 been made to this insn. The order is important, because newi2pat
4641 can affect nonzero_bits of newpat. */
4645 }
4648 {
4650 {
4653 }
4655 }
4658 {
4660 {
4663 }
4665 }
4668 {
4670 {
4673 }
4675 }
4678 {
4680 {
4683 }
4685 }
4688 {
4690 {
4693 }
4695 }
4697 /* Set new_direct_jump_p if a new return or simple jump instruction
4698 has been created. Adjust the CFG accordingly. */
4700 {
4704 }
4709 {
4712 }
4716 {
4722 }
4727 {
4733 }
4735 /* A noop might also need cleaning up of CFG, if it comes from the
4736 simplification of a jump. */
4741 {
4744 }
4751 {
4754 }
4756 combine_successes++;
4766 }
4767 \f
4768 /* Get a marker for undoing to the current state. */
4772 {
4774 }
4776 /* Undo the modifications up to the marker. */
4778 static void
4780 {
4784 {
4789 {
4805 }
4809 }
4812 }
4814 /* Undo all the modifications recorded in undobuf. */
4816 static void
4818 {
4820 }
4822 /* We've committed to accepting the changes we made. Move all
4823 of the undos to the free list. */
4825 static void
4827 {
4831 {
4835 }
4837 }
4838 \f
4839 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4840 where we have an arithmetic expression and return that point. LOC will
4841 be inside INSN.
4843 try_combine will call this function to see if an insn can be split into
4844 two insns. */
4848 {
4858 /* First special-case some codes. */
4860 {
4862 #ifdef INSN_SCHEDULING
4863 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4864 point. */
4867 #endif
4871 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4872 using LO_SUM and HIGH. */
4875 {
4883 }
4885 /* If we have a PLUS whose second operand is a constant and the
4886 address is not valid, perhaps we can split it up using
4887 the machine-specific way to split large constants. We use
4888 the first pseudo-reg (one of the virtual regs) as a placeholder;
4889 it will not remain in the result. */
4894 {
4897 subst_insn);
4899 /* This should have produced two insns, each of which sets our
4900 placeholder. If the source of the second is a valid address,
4901 we can put both sources together and make a split point
4902 in the middle. */
4915 && memory_address_addr_space_p
4918 {
4922 /* Replace the placeholder in SRC2 with SRC1. If we can
4923 find where in SRC2 it was placed, that can become our
4924 split point and we can replace this address with SRC2.
4925 Just try two obvious places. */
4936 {
4939 }
4940 }
4942 /* If that didn't work and we have a nested plus, like:
4943 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4944 is valid address, try to split (REG1 * CONST1). */
4951 {
4956 {
4959 }
4961 }
4968 {
4973 {
4976 }
4978 }
4980 /* If that didn't work, perhaps the first operand is complex and
4981 needs to be computed separately, so make a split point there.
4982 This will occur on machines that just support REG + CONST
4983 and have a constant moved through some previous computation. */
4988 }
4990 /* If we have a PLUS whose first operand is complex, try computing it
4991 separately by making a split there. */
5002 /* See if we can split SET_SRC as it stands. */
5007 /* See if we can split SET_DEST as it stands. */
5012 /* See if this is a bitfield assignment with everything constant. If
5013 so, this is an IOR of an AND, so split it into that. */
5025 {
5031 rtx or_mask;
5040 else
5041 {
5047 or_mask));
5048 }
5055 }
5057 /* Otherwise, see if this is an operation that we can split into two.
5058 If so, try to split that. */
5062 {
5064 /* If we are AND'ing with a large constant that is only a single
5065 bit and the result is only being used in a context where we
5066 need to know if it is zero or nonzero, replace it with a bit
5067 extraction. This will avoid the large constant, which might
5068 have taken more than one insn to make. If the constant were
5069 not a valid argument to the AND but took only one insn to make,
5070 this is no worse, but if it took more than one insn, it will
5071 be better. */
5081 {
5087 {
5090 }
5091 }
5095 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5096 is known to be on, this can be converted into a NEG of a shift. */
5102 {
5109 pos_rtx)));
5114 }
5120 /* We can't optimize if either mode is a partial integer
5121 mode as we don't know how many bits are significant
5122 in those modes. */
5138 {
5146 }
5151 }
5157 {
5158 /* For unsigned, we have a choice of a shift followed by an
5159 AND or two shifts. Use two shifts for field sizes where the
5160 constant might be too large. We assume here that we can
5161 always at least get 8-bit constants in an AND insn, which is
5162 true for every current RISC. */
5165 {
5166 unsigned HOST_WIDE_INT mask
5171 gen_rtx_LSHIFTRT
5178 }
5179 else
5180 {
5184 gen_rtx_fmt_ee
5194 }
5195 }
5197 /* See if this is a simple operation with a constant as the second
5198 operand. It might be that this constant is out of range and hence
5199 could be used as a split point. */
5207 /* Finally, see if this is a simple operation with its first operand
5208 not in a register. The operation might require this operand in a
5209 register, so return it as a split point. We can always do this
5210 because if the first operand were another operation, we would have
5211 already found it as a split point. */
5220 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5221 it is better to write this as (not (ior A B)) so we can split it.
5222 Similarly for IOR. */
5224 {
5232 }
5234 /* Many RISC machines have a large set of logical insns. If the
5235 second operand is a NOT, put it first so we will try to split the
5236 other operand first. */
5238 {
5242 }
5247 /* Canonicalization can produce (minus A (mult B C)), where C is a
5248 constant. It may be better to try splitting (plus (mult B -C) A)
5249 instead if this isn't a multiply by a power of two. */
5253 {
5261 mode)),
5264 }
5266 /* Split at a multiply-accumulate instruction. However if this is
5267 the SET_SRC, we likely do not have such an instruction and it's
5268 worthless to try this split. */
5277 }
5279 /* Otherwise, select our actions depending on our rtx class. */
5281 {
5287 /* fall through */
5295 /* fall through */
5297 /* Some machines have (and (shift ...) ...) insns. If X is not
5298 an AND, but XEXP (X, 0) is, use it as our split point. */
5308 /* Otherwise, we don't have a split point. */
5310 }
5311 }
5312 \f
5313 /* Throughout X, replace FROM with TO, and return the result.
5314 The result is TO if X is FROM;
5315 otherwise the result is X, but its contents may have been modified.
5316 If they were modified, a record was made in undobuf so that
5317 undo_all will (among other things) return X to its original state.
5319 If the number of changes necessary is too much to record to undo,
5320 the excess changes are not made, so the result is invalid.
5321 The changes already made can still be undone.
5322 undobuf.num_undo is incremented for such changes, so by testing that
5323 the caller can tell whether the result is valid.
5325 `n_occurrences' is incremented each time FROM is replaced.
5327 IN_DEST is true if we are processing the SET_DEST of a SET.
5329 IN_COND is true if we are at the top level of a condition.
5331 UNIQUE_COPY is true if each substitution must be unique. We do this
5332 by copying if `n_occurrences' is nonzero. */
5334 static rtx
5336 {
5341 rtx new_rtx;
5343 /* Two expressions are equal if they are identical copies of a shared
5344 RTX or if they are both registers with the same register number
5345 and mode. */
5347 #define COMBINE_RTX_EQUAL_P(X,Y) \
5348 ((X) == (Y) \
5349 || (REG_P (X) && REG_P (Y) \
5350 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5352 /* Do not substitute into clobbers of regs -- this will never result in
5353 valid RTL. */
5358 {
5359 n_occurrences++;
5361 }
5363 /* If X and FROM are the same register but different modes, they
5364 will not have been seen as equal above. However, the log links code
5365 will make a LOG_LINKS entry for that case. If we do nothing, we
5366 will try to rerecognize our original insn and, when it succeeds,
5367 we will delete the feeding insn, which is incorrect.
5369 So force this insn not to match in this (rare) case. */
5374 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5375 of which may contain things that can be combined. */
5379 /* It is possible to have a subexpression appear twice in the insn.
5380 Suppose that FROM is a register that appears within TO.
5381 Then, after that subexpression has been scanned once by `subst',
5382 the second time it is scanned, TO may be found. If we were
5383 to scan TO here, we would find FROM within it and create a
5384 self-referent rtl structure which is completely wrong. */
5388 /* Parallel asm_operands need special attention because all of the
5389 inputs are shared across the arms. Furthermore, unsharing the
5390 rtl results in recognition failures. Failure to handle this case
5391 specially can result in circular rtl.
5393 Solve this by doing a normal pass across the first entry of the
5394 parallel, and only processing the SET_DESTs of the subsequent
5395 entries. Ug. */
5400 {
5403 /* If this substitution failed, this whole thing fails. */
5411 {
5415 {
5418 /* If this substitution failed, this whole thing fails. */
5424 }
5425 }
5426 }
5427 else
5428 {
5432 /* We don't need to process a SET_DEST that is a register or PC, so
5433 set up to skip this common case. All other cases where we want
5434 to suppress replacing something inside a SET_SRC are handled via
5435 the IN_DEST operand. */
5441 /* Trying to simplify the operands of a widening MULT is not likely
5442 to create RTL matching a machine insn. */
5454 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5455 constant. */
5460 {
5462 {
5465 {
5467 {
5470 n_occurrences++;
5471 }
5472 else
5473 {
5477 /* If this substitution failed, this whole thing
5478 fails. */
5482 }
5485 }
5486 }
5488 {
5489 /* If this is a register being set, ignore it. */
5496 ;
5499 {
5500 /* In general, don't install a subreg involving two
5501 modes not tieable. It can worsen register
5502 allocation, and can even make invalid reload
5503 insns, since the reg inside may need to be copied
5504 from in the outside mode, and that may be invalid
5505 if it is an fp reg copied in integer mode.
5507 We allow an exception to this: It is valid if
5508 it is inside another SUBREG and the mode of that
5509 SUBREG and the mode of the inside of TO is
5510 tieable. */
5529 n_occurrences++;
5530 }
5531 else
5532 /* If we are in a SET_DEST, suppress most cases unless we
5533 have gone inside a MEM, in which case we want to
5534 simplify the address. We assume here that things that
5535 are actually part of the destination have their inner
5536 parts in the first expression. This is true for SUBREG,
5537 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5538 things aside from REG and MEM that should appear in a
5539 SET_DEST. */
5541 (((in_dest
5547 unique_copy);
5549 /* If we found that we will have to reject this combination,
5550 indicate that by returning the CLOBBER ourselves, rather than
5551 an expression containing it. This will speed things up as
5552 well as prevent accidents where two CLOBBERs are considered
5553 to be equal, thus producing an incorrect simplification. */
5559 {
5567 }
5573 {
5575 new_rtx,
5579 }
5580 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5581 etc. arguments, otherwise we can ICE before trying to recog
5582 it. See PR104446. */
5586 else
5588 }
5589 }
5590 }
5592 /* Check if we are loading something from the constant pool via float
5593 extension; in this case we would undo compress_float_constant
5594 optimization and degenerate constant load to an immediate value. */
5598 {
5602 }
5604 /* Try to simplify X. If the simplification changed the code, it is likely
5605 that further simplification will help, so loop, but limit the number
5606 of repetitions that will be performed. */
5609 {
5610 /* If X is sufficiently simple, don't bother trying to do anything
5611 with it. */
5620 /* We no longer know the original mode of operand 0 since we
5621 have changed the form of X) */
5623 }
5626 }
5627 \f
5628 /* If X is a commutative operation whose operands are not in the canonical
5629 order, use substitutions to swap them. */
5631 static void
5633 {
5636 {
5640 }
5647 /* Two operands have same precedence, then
5648 first bit of mask select first operand. */
5651 {
5657 else
5662 }
5663 }
5665 /* Simplify X, a piece of RTL. We just operate on the expression at the
5666 outer level; call `subst' to simplify recursively. Return the new
5667 expression.
5669 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5670 if we are inside a SET_DEST. IN_COND is true if we are at the top level
5671 of a condition. */
5673 static rtx
5675 {
5678 scalar_int_mode int_mode;
5679 rtx temp;
5682 /* If this is a commutative operation, put a constant last and a complex
5683 expression first. We don't need to do this for comparisons here. */
5686 /* Try to fold this expression in case we have constants that weren't
5687 present before. */
5690 {
5698 {
5701 {
5705 }
5708 }
5721 }
5724 {
5729 }
5731 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5732 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5733 things. Check for cases where both arms are testing the same
5734 condition.
5736 Don't do anything if all operands are very simple. */
5749 {
5754 /* If everything is a comparison, what we have is highly unlikely
5755 to be simpler, so don't use it. */
5758 /* Similarly, if we end up with one of the expressions the same
5759 as the original, it is certainly not simpler. */
5762 {
5769 /* Simplify the alternative arms; this may collapse the true and
5770 false arms to store-flag values. Be careful to use copy_rtx
5771 here since true_rtx or false_rtx might share RTL with x as a
5772 result of the if_then_else_cond call above. */
5778 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5779 is unlikely to be simpler. */
5782 {
5785 /* Restarting if we generate a store-flag expression will cause
5786 us to loop. Just drop through in this case. */
5788 /* If the result values are STORE_FLAG_VALUE and zero, we can
5789 just make the comparison operation. */
5800 /* Likewise, we can make the negate of a comparison operation
5801 if the result values are - STORE_FLAG_VALUE and zero. */
5809 mode);
5820 mode);
5824 }
5825 }
5826 }
5828 /* First see if we can apply the inverse distributive law. */
5831 {
5835 }
5837 /* If CODE is an associative operation not otherwise handled, see if we
5838 can associate some operands. This can win if they are constants or
5839 if they are logically related (i.e. (a & b) & a). */
5845 {
5847 {
5851 rtx inner;
5853 /* Make sure we pass the constant operand if any as the second
5854 one if this is a commutative operation. */
5862 /* For commutative operations, try the other pair if that one
5863 didn't simplify. */
5865 {
5870 }
5874 }
5875 }
5877 /* A little bit of algebraic simplification here. */
5879 {
5881 /* Ensure that our address has any ASHIFTs converted to MULT in case
5882 address-recognizing predicates are called later. */
5891 /* See if this can be moved to simplify_subreg. */
5894 /* Don't call gen_lowpart if the inner mode
5895 is VOIDmode and we cannot simplify it, as SUBREG without
5896 inner mode is invalid. */
5903 {
5904 rtx temp;
5910 /* If op is known to have all lower bits zero, the result is zero. */
5924 }
5926 /* Don't change the mode of the MEM if that would change the meaning
5927 of the address. */
5934 /* Note that we cannot do any narrowing for non-constants since
5935 we might have been counting on using the fact that some bits were
5936 zero. We now do this in the SET. */
5943 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5944 replaced by (lshiftrt X C). This will convert
5945 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5953 /* If X has only a single bit that might be nonzero, say, bit I, convert
5954 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5955 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5956 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5957 or a SUBREG of one since we'd be making the expression more
5958 complex if it was just a register. */
5965 {
5966 rtx temp1 = simplify_shift_const
5972 /* If all we did was surround TEMP with the two shifts, we
5973 haven't improved anything, so don't use it. Otherwise,
5974 we are better off with TEMP1. */
5979 }
5983 /* We can't handle truncation to a partial integer mode here
5984 because we don't know the real bitsize of the partial
5985 integer mode. */
5994 /* We can truncate a constant value and return it. */
5995 {
5996 poly_int64 c;
5999 }
6001 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6002 whose value is a comparison can be replaced with a subreg if
6003 STORE_FLAG_VALUE permits. */
6013 /* (const (const X)) can become (const X). Do it this way rather than
6014 returning the inner CONST since CONST can be shared with a
6015 REG_EQUAL note. */
6021 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6022 can add in an offset. find_split_point will split this address up
6023 again if it doesn't match. */
6030 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6031 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6032 bit-field and can be replaced by either a sign_extend or a
6033 sign_extract. The `and' may be a zero_extend and the two
6034 <c>, -<c> constants may be reversed. */
6051 return simplify_shift_const
6058 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6059 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6060 the bitsize of the mode - 1. This allows simplification of
6061 "a = (b & 8) == 0;" */
6068 return simplify_shift_const
6072 const1_rtx),
6076 /* If we are adding two things that have no bits in common, convert
6077 the addition into an IOR. This will often be further simplified,
6078 for example in cases like ((a & 1) + (a & 2)), which can
6079 become a & 3. */
6084 {
6085 /* Try to simplify the expression further. */
6089 /* If we could, great. If not, do not go ahead with the IOR
6090 replacement, since PLUS appears in many special purpose
6091 address arithmetic instructions. */
6099 }
6101 /* Canonicalize x + x into x << 1. */
6110 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6111 (and <foo> (const_int pow2-1)) */
6122 /* If we have (mult (plus A B) C), apply the distributive law and then
6123 the inverse distributive law to see if things simplify. This
6124 occurs mostly in addresses, often when unrolling loops. */
6127 {
6131 }
6133 /* Try simplify a*(b/c) as (a*b)/c. */
6136 {
6142 }
6146 /* If this is a divide by a power of two, treat it as a shift if
6147 its first operand is a shift. */
6167 /* If the first operand is a condition code, we can't do anything
6168 with it. */
6171 {
6179 /* Simplify our comparison, if possible. */
6182 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6183 if only the low-order bit is possibly nonzero in X (such as when
6184 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6185 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6186 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6187 (plus X 1).
6189 Remove any ZERO_EXTRACT we made when thinking this was a
6190 comparison. It may now be simpler to use, e.g., an AND. If a
6191 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6192 the call to make_compound_operation in the SET case.
6194 Don't apply these optimizations if the caller would
6195 prefer a comparison rather than a value.
6196 E.g., for the condition in an IF_THEN_ELSE most targets need
6197 an explicit comparison. */
6200 ;
6218 {
6222 int_mode);
6223 }
6231 {
6235 const1_rtx);
6236 }
6245 {
6248 }
6250 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6251 those above. */
6253 ;
6270 {
6274 int_mode);
6275 }
6284 {
6288 int_mode);
6289 }
6291 /* If X is 0/1, (eq X 0) is X-1. */
6298 {
6301 }
6303 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6304 one bit that might be nonzero, we can convert (ne x 0) to
6305 (ashift x c) where C puts the bit in the sign bit. Remove any
6306 AND with STORE_FLAG_VALUE when we are done, since we are only
6307 going to test the sign bit. */
6315 {
6321 else
6323 }
6325 /* If the code changed, return a whole new comparison.
6326 We also need to avoid using SUBST in cases where
6327 simplify_comparison has widened a comparison with a CONST_INT,
6328 since in that case the wider CONST_INT may fail the sanity
6329 checks in do_SUBST. */
6336 /* Otherwise, keep this operation, but maybe change its operands.
6337 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6340 }
6350 /* If we are processing SET_DEST, we are done. */
6368 /* If this is a shift by a constant amount, simplify it. */
6376 (HOST_WIDE_INT_1U
6381 {
6385 /* If we select a low-part subreg, return that. */
6387 {
6391 }
6392 }
6396 }
6399 }
6400 \f
6401 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6403 static rtx
6405 {
6412 rtx temp;
6415 rtx reversed;
6418 /* Simplify storing of the truth value. */
6423 /* Also when the truth value has to be reversed. */
6429 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6430 in it is being compared against certain values. Get the true and false
6431 comparisons and see if that says anything about the value of each arm. */
6437 {
6438 HOST_WIDE_INT nzb;
6444 /* If FALSE_CODE is EQ, swap the codes and arms. */
6447 {
6450 }
6452 scalar_int_mode from_mode;
6454 {
6455 /* If we are comparing against zero and the expression being
6456 tested has only a single bit that might be nonzero, that is
6457 its value when it is not equal to zero. Similarly if it is
6458 known to be -1 or 0. */
6462 {
6465 }
6470 {
6473 }
6474 }
6476 /* Now simplify an arm if we know the value of the register in the
6477 branch and it is used in the arm. Be careful due to the potential
6478 of locally-shared RTL. */
6495 }
6497 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6498 reversed, do so to avoid needing two sets of patterns for
6499 subtract-and-branch insns. Similarly if we have a constant in the true
6500 arm, the false arm is the same as the first operand of the comparison, or
6501 the false arm is more complicated than the true arm. */
6514 {
6522 /* It is possible that the conditional has been simplified out. */
6525 }
6527 /* If the two arms are identical, we don't need the comparison. */
6532 /* Convert a == b ? b : a to "a". */
6544 /* Look for cases where we have (abs x) or (neg (abs X)). */
6547 && comparison_p
6554 {
6560 return
6563 mode);
6566 }
6568 /* Look for MIN or MAX. */
6571 || (flag_unsafe_math_optimizations
6574 && comparison_p
6579 {
6594 }
6596 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6597 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6598 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6599 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6600 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6601 neither 1 or -1, but it isn't worth checking for. */
6604 && comparison_p
6607 {
6623 /* If an identity-zero op is commutative, check whether there
6624 would be a match if we swapped the operands. */
6645 {
6649 }
6662 {
6666 }
6683 {
6687 }
6700 {
6704 }
6707 {
6717 const_true_rtx));
6725 }
6726 }
6728 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6729 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6730 negation of a single bit, we can convert this operation to a shift. We
6731 can actually do this more generally, but it doesn't seem worth it. */
6743 return
6747 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6748 non-zero bit in A is C1. */
6756 {
6762 }
6765 }
6766 \f
6767 /* Simplify X, a SET expression. Return the new expression. */
6769 static rtx
6771 {
6774 machine_mode mode
6778 scalar_int_mode int_mode;
6780 /* (set (pc) (return)) gets written as (return). */
6784 /* Now that we know for sure which bits of SRC we are using, see if we can
6785 simplify the expression for the object knowing that we only need the
6786 low-order bits. */
6789 {
6792 }
6794 /* If the source is a COMPARE, look for the use of the comparison result
6795 and try to simplify it unless we already have used undobuf.other_insn. */
6801 {
6810 {
6813 {
6816 }
6817 }
6818 else
6826 {
6830 }
6831 else
6832 {
6837 /* Attempt to simplify CC user. */
6839 {
6843 }
6845 /* Convert X into a no-op move. */
6849 }
6851 /* Simplify our comparison, if possible. */
6854 #ifdef SELECT_CC_MODE
6855 /* If this machine has CC modes other than CCmode, check to see if we
6856 need to use a different CC mode here. */
6865 else
6868 /* If the mode changed, we have to change SET_DEST, the mode in the
6869 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6870 a hard register, just build new versions with the proper mode. If it
6871 is a pseudo, we lose unless it is only time we set the pseudo, in
6872 which case we can safely change its mode. */
6874 {
6876 {
6878 rtx new_dest;
6882 else
6883 {
6886 }
6893 }
6894 }
6897 /* If the code changed, we have to build a new comparison in
6898 undobuf.other_insn. */
6900 {
6909 /* If the only change we made was to change an EQ into an NE or
6910 vice versa, OP0 has only one bit that might be nonzero, and OP1
6911 is zero, check if changing the user of the condition code will
6912 produce a valid insn. If it won't, we can keep the original code
6913 in that insn by surrounding our operation with an XOR. */
6920 {
6925 {
6932 }
6933 }
6934 }
6939 /* Don't generate a compare of a CC with 0, just use that CC. */
6941 {
6944 }
6945 /* Otherwise, if we didn't previously have the same COMPARE we
6946 want, create it from scratch. */
6949 {
6952 }
6953 }
6954 else
6955 {
6956 /* Get SET_SRC in a form where we have placed back any
6957 compound expressions. Then do the checks below. */
6960 }
6962 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6963 and X being a REG or (subreg (reg)), we may be able to convert this to
6964 (set (subreg:m2 x) (op)).
6966 We can always do this if M1 is narrower than M2 because that means that
6967 we only care about the low bits of the result.
6969 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6970 perform a narrower operation than requested since the high-order bits will
6971 be undefined. On machine where it is defined, this transformation is safe
6972 as long as M1 and M2 have the same number of words. */
6976 && (known_equal_after_align_up
6979 UNITS_PER_WORD))
6988 {
6991 dest));
6995 }
6997 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6998 would require a paradoxical subreg. Replace the subreg with a
6999 zero_extend to avoid the reload that would otherwise be required.
7000 Don't do this unless we have a scalar integer mode, otherwise the
7001 transformation is incorrect. */
7008 {
7013 }
7015 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7016 are comparing an item known to be 0 or -1 against 0, use a logical
7017 operation instead. Check for one of the arms being an IOR of the other
7018 arm with some value. We compute three terms to be IOR'ed together. In
7019 practice, at most two will be nonzero. Then we do the IOR's. */
7027 && (!HAVE_conditional_move
7032 {
7057 int_mode),
7058 false_rtx);
7064 term3));
7067 }
7069 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7070 whole thing fail. */
7075 else
7076 /* Convert this into a field assignment operation, if possible. */
7078 }
7079 \f
7080 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7081 result. */
7083 static rtx
7085 {
7088 scalar_int_mode mode;
7091 {
7093 /* We can call simplify_and_const_int only if we don't lose
7094 any (sign) bits when converting INTVAL (op1) to
7095 "unsigned HOST_WIDE_INT". */
7100 {
7107 }
7109 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7110 apply the distributive law and then the inverse distributive
7111 law to see if things simplify. */
7113 {
7117 }
7119 {
7123 }
7127 /* If we have (ior (and A B) C), apply the distributive law and then
7128 the inverse distributive law to see if things simplify. */
7131 {
7135 }
7138 {
7142 }
7147 }
7150 }
7151 \f
7152 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7153 operations" because they can be replaced with two more basic operations.
7154 ZERO_EXTEND is also considered "compound" because it can be replaced with
7155 an AND operation, which is simpler, though only one operation.
7157 The function expand_compound_operation is called with an rtx expression
7158 and will convert it to the appropriate shifts and AND operations,
7159 simplifying at each stage.
7161 The function make_compound_operation is called to convert an expression
7162 consisting of shifts and ANDs into the equivalent compound expression.
7163 It is the inverse of this function, loosely speaking. */
7165 static rtx
7167 {
7171 rtx tem;
7172 scalar_int_mode inner_mode;
7175 {
7178 /* FALLTHRU */
7180 /* We can't necessarily use a const_int for a multiword mode;
7181 it depends on implicitly extending the value.
7182 Since we don't know the right way to extend it,
7183 we can't tell whether the implicit way is right.
7185 Even for a mode that is no wider than a const_int,
7186 we can't win, because we need to sign extend one of its bits through
7187 the rest of it, and we don't know which bit. */
7191 /* Reject modes that aren't scalar integers because turning vector
7192 or complex modes into shifts causes problems. */
7196 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7197 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7198 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7199 reloaded. If not for that, MEM's would very rarely be safe.
7201 Reject modes bigger than a word, because we might not be able
7202 to reference a two-register group starting with an arbitrary register
7203 (and currently gen_lowpart might crash for a SUBREG). */
7209 /* If the inner object has VOIDmode (the only way this can happen
7210 is if it is an ASM_OPERANDS), we can't do anything since we don't
7211 know how much masking to do. */
7220 /* fall through */
7223 /* If the operand is a CLOBBER, just return it. */
7231 /* Reject modes that aren't scalar integers because turning vector
7232 or complex modes into shifts causes problems. */
7239 /* This should stay within the object being extracted, fail otherwise. */
7250 }
7252 /* We've rejected non-scalar operations by now. */
7255 /* Convert sign extension to zero extension, if we know that the high
7256 bit is not set, as this is easier to optimize. It will be converted
7257 back to cheaper alternative in make_extraction. */
7263 {
7267 /* Make sure this is a profitable operation. */
7274 else
7276 }
7278 /* We can optimize some special cases of ZERO_EXTEND. */
7280 {
7281 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7282 know that the last value didn't have any inappropriate bits
7283 set. */
7291 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7300 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7301 is a comparison and STORE_FLAG_VALUE permits. This is like
7302 the first case, but it works even when MODE is larger
7303 than HOST_WIDE_INT. */
7311 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7320 }
7322 /* If we reach here, we want to return a pair of shifts. The inner
7323 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7324 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7325 logical depending on the value of UNSIGNEDP.
7327 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7328 converted into an AND of a shift.
7330 We must check for the case where the left shift would have a negative
7331 count. This can happen in a case like (x >> 31) & 255 on machines
7332 that can't shift by a constant. On those machines, we would first
7333 combine the shift with the AND to produce a variable-position
7334 extraction. Then the constant of 31 would be substituted in
7335 to produce such a position. */
7339 {
7347 }
7349 {
7357 }
7358 else
7359 /* Any other cases we can't handle. */
7362 /* If we couldn't do this for some reason, return the original
7363 expression. */
7368 }
7369 \f
7370 /* X is a SET which contains an assignment of one object into
7371 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7372 or certain SUBREGS). If possible, convert it into a series of
7373 logical operations.
7375 We half-heartedly support variable positions, but do not at all
7376 support variable lengths. */
7378 static const_rtx
7380 {
7381 rtx inner;
7385 scalar_int_mode compute_mode;
7387 /* Loop until we find something we can't simplify. */
7389 {
7392 {
7398 MAX_MODE_INT);
7399 }
7402 {
7410 /* A constant position should stay within the width of INNER. */
7415 {
7421 /* If position is ADJUST - X, new position is X. */
7423 else
7427 pos);
7428 }
7429 }
7431 /* If the destination is a subreg that overwrites the whole of the inner
7432 register, we can move the subreg to the source. */
7434 /* We need SUBREGs to compute nonzero_bits properly. */
7435 && nonzero_sign_valid
7437 {
7439 gen_lowpart
7443 }
7444 else
7450 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7452 {
7453 /* Don't do anything for vector or complex integral types. */
7457 /* Try to find an integral mode to pun with. */
7463 }
7465 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7469 /* Don't try to compute in too wide unsupported modes. */
7473 /* Now compute the equivalent expression. Make a copy of INNER
7474 for the SET_DEST in case it is a MEM into which we will substitute;
7475 we don't want shared RTL in that case. */
7477 compute_mode);
7481 compute_mode,
7483 compute_mode),
7484 inner);
7489 mask),
7490 pos);
7495 }
7498 }
7499 \f
7500 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7501 it is an RTX that represents the (variable) starting position; otherwise,
7502 POS is the (constant) starting bit position. Both are counted from the LSB.
7504 UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7506 IN_DEST is true if this is a reference in the destination of a SET.
7507 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7508 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7509 be used.
7511 IN_COMPARE is true if we are in a COMPARE. This means that a
7512 ZERO_EXTRACT should be built even for bits starting at bit 0.
7514 MODE is the desired mode of the result (if IN_DEST == 0).
7516 The result is an RTX for the extraction or NULL_RTX if the target
7517 can't handle it. */
7519 static rtx
7523 {
7524 /* This mode describes the size of the storage area
7525 to fetch the overall value from. Within that, we
7526 ignore the POS lowest bits, etc. */
7528 machine_mode inner_mode;
7529 scalar_int_mode wanted_inner_mode;
7535 HOST_WIDE_INT orig_pos;
7543 /* If trying or potentionally trying to extract
7544 bits outside of is_mode, don't look through
7545 non-paradoxical SUBREGs. See PR82192. */
7548 {
7549 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7550 consider just the QI as the memory to extract from.
7551 The subreg adds or removes high bits; its mode is
7552 irrelevant to the meaning of this extraction,
7553 since POS and LEN count from the lsb. */
7557 }
7562 {
7563 /* We're extracting the least significant bits of an rtx
7564 (ashift X (const_int C)), where LEN > C. Extract the
7565 least significant (LEN - C) bits of X, giving an rtx
7566 whose mode is MODE, then shift it left C times. */
7572 }
7576 {
7577 /* We're extracting the least significant bits of an rtx
7578 (mult X (const_int 2^C)), where LEN > C. Extract the
7579 least significant (LEN - C) bits of X, giving an rtx
7580 whose mode is MODE, then multiply it by 2^C. */
7583 {
7589 }
7590 }
7592 /* If trying or potentionally trying to extract
7593 bits outside of is_mode, don't look through
7594 TRUNCATE. See PR82192. */
7601 /* See if this can be done without an extraction. We never can if the
7602 width of the field is not the same as that of some integer mode. For
7603 registers, we can only avoid the extraction if the position is at the
7604 low-order bit and this is either not in the destination or we have the
7605 appropriate STRICT_LOW_PART operation available.
7607 For MEM, we can avoid an extract if the field starts on an appropriate
7608 boundary and we can change the mode of the memory reference. */
7610 scalar_int_mode tmode;
7619 && (! in_dest
7623 && (pos
7626 /* We can't do this if we are widening INNER_MODE (it
7627 may not be aligned, for one thing). */
7634 {
7635 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7636 field. If the original and current mode are the same, we need not
7637 adjust the offset. Otherwise, we do if bytes big endian.
7639 If INNER is not a MEM, get a piece consisting of just the field
7640 of interest (in this case POS % BITS_PER_WORD must be 0). */
7643 {
7644 poly_int64 offset;
7646 /* POS counts from lsb, but make OFFSET count in memory order. */
7650 else
7654 }
7656 {
7658 {
7659 /* We can't call gen_lowpart in a DEST since we
7660 always want a SUBREG (see below) and it would sometimes
7661 return a new hard register. */
7663 {
7664 poly_uint64 offset
7667 /* Avoid creating invalid subregs, for example when
7668 simplifying (x>>32)&255. */
7673 }
7674 else
7676 }
7677 else
7679 }
7680 else
7682 len >= HOST_BITS_PER_WIDE_INT
7683 ? HOST_WIDE_INT_M1U
7686 /* If this extraction is going into the destination of a SET,
7687 make a STRICT_LOW_PART unless we made a MEM. */
7702 /* If we know that no extraneous bits are set, and that the high
7703 bit is not set, convert the extraction to the cheaper of
7704 sign and zero extension, that are equivalent in these cases. */
7710 {
7714 /* Prefer ZERO_EXTENSION, since it gives more information to
7715 backends. */
7720 }
7722 /* Otherwise, sign- or zero-extend unless we already are in the
7723 proper mode. */
7727 }
7729 /* Unless this is a COMPARE or we have a funny memory reference,
7730 don't do anything with zero-extending field extracts starting at
7731 the low-order bit since they are simple AND operations. */
7736 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7737 if the position is not a constant and the length is not 1. In all
7738 other cases, we would only be going outside our object in cases when
7739 an original shift would have been undefined. */
7748 /* If INNER is not from memory, we want it to have the mode of a register
7749 extraction pattern's structure operand, or word_mode if there is no
7750 such pattern. The same applies to extraction_mode and pos_mode
7751 and their respective operands.
7753 For memory, assume that the desired extraction_mode and pos_mode
7754 are the same as for a register operation, since at present we don't
7755 have named patterns for aligned memory structures. */
7760 {
7764 }
7766 /* Never narrow an object, since that might not be safe. */
7772 /* Punt if len is too large for extraction_mode. */
7778 else
7779 {
7780 /* Be careful not to go beyond the extracted object and maintain the
7781 natural alignment of the memory. */
7786 }
7791 {
7792 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7793 BITS_BIG_ENDIAN style. If position is constant, compute new
7794 position. Otherwise, build subtraction.
7795 Note that POS is relative to the mode of the original argument.
7796 If it's a MEM we need to recompute POS relative to that.
7797 However, if we're extracting from (or inserting into) a register,
7798 we want to recompute POS relative to wanted_inner_mode. */
7807 else
7808 pos_rtx
7811 pos_rtx);
7812 /* POS may be less than 0 now, but we check for that below.
7813 Note that it can only be less than 0 if !MEM_P (inner). */
7814 }
7816 /* If INNER has a wider mode, and this is a constant extraction, try to
7817 make it smaller and adjust the byte to point to the byte containing
7818 the value. */
7821 && ! pos_rtx
7826 {
7829 /* The computations below will be correct if the machine is big
7830 endian in both bits and bytes or little endian in bits and bytes.
7831 If it is mixed, we must adjust. */
7833 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7834 adjust OFFSET to compensate. */
7839 /* We can now move to the desired byte. */
7850 }
7852 /* If INNER is not memory, get it into the proper mode. If we are changing
7853 its mode, POS must be a constant and smaller than the size of the new
7854 mode. */
7856 {
7857 /* On the LHS, don't create paradoxical subregs implicitely truncating
7858 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7861 wanted_inner_mode))
7873 pos_rtx
7875 ? HOST_WIDE_INT_M1U
7878 }
7880 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7881 have to zero extend. Otherwise, we can just use a SUBREG.
7883 We dealt with constant rtxes earlier, so pos_rtx cannot
7884 have VOIDmode at this point. */
7888 {
7892 /* If we know that no extraneous bits are set, and that the high
7893 bit is not set, convert extraction to cheaper one - either
7894 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7895 cases. */
7903 {
7907 /* Prefer ZERO_EXTENSION, since it gives more information to
7908 backends. */
7912 }
7914 }
7916 /* Make POS_RTX unless we already have it and it is correct. If we don't
7917 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7918 be a CONST_INT. */
7925 /* Make the required operation. See if we can use existing rtx. */
7932 }
7933 \f
7934 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7935 can be commuted with any other operations in X. Return X without
7936 that shift if so. */
7938 static rtx
7940 {
7942 rtx tem;
7945 {
7947 /* This is the shift itself. If it is wide enough, we will return
7948 either the value being shifted if the shift count is equal to
7949 COUNT or a shift for the difference. */
7963 /* If we can safely shift this constant and we find the inner shift,
7964 make a new operation. */
7969 {
7973 }
7978 }
7981 }
7982 \f
7983 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7984 level of the expression and MODE is its mode. IN_CODE is as for
7985 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7986 that should be used when recursing on operands of *X_PTR.
7988 There are two possible actions:
7990 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7991 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7993 - Return a new rtx, which the caller returns directly. */
7995 static rtx
7999 {
8007 rtx tem;
8008 scalar_int_mode inner_mode;
8012 {
8015 }
8017 /* Process depending on the code of this operation. If NEW is set
8018 nonzero, it will be returned. */
8021 {
8023 /* Convert shifts by constants into multiplications if inside
8024 an address. */
8028 {
8034 {
8037 }
8040 }
8049 {
8053 }
8056 {
8060 mode));
8062 }
8063 else
8064 {
8067 }
8077 {
8081 }
8084 {
8088 mode));
8090 }
8091 else
8092 {
8096 }
8099 /* If the second operand is not a constant, we can't do anything
8100 with it. */
8104 /* If the constant is a power of two minus one and the first operand
8105 is a logical right shift, make an extraction. */
8108 {
8112 }
8114 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8121 {
8128 /* If we narrowed the mode when dropping the subreg, then we lose. */
8132 /* If that didn't give anything, see if the AND simplifies on
8133 its own. */
8135 {
8139 }
8140 }
8141 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8147 {
8148 /* Apply the distributive law, and then try to make extractions. */
8155 }
8157 /* If we are have (and (rotate X C) M) and C is larger than the number
8158 of bits in M, this is an extraction. */
8164 {
8171 }
8173 /* On machines without logical shifts, if the operand of the AND is
8174 a logical shift and our mask turns off all the propagated sign
8175 bits, we can replace the logical shift with an arithmetic shift. */
8183 {
8193 next_code),
8195 }
8197 /* If the constant is one less than a power of two, this might be
8198 representable by an extraction even if no shift is present.
8199 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8200 we are in a COMPARE. */
8204 next_code),
8208 /* If we are in a comparison and this is an AND with a power of two,
8209 convert this into the appropriate bit extract. */
8215 next_code),
8218 /* If the one operand is a paradoxical subreg of a register or memory and
8219 the constant (limited to the smaller mode) has only zero bits where
8220 the sub expression has known zero bits, this can be expressed as
8221 a zero_extend. */
8223 {
8224 rtx sub;
8232 {
8236 /* original AND constant with all the known zero bits set */
8239 {
8243 }
8244 }
8245 }
8250 /* If the sign bit is known to be zero, replace this with an
8251 arithmetic shift. */
8256 {
8259 next_code),
8262 }
8264 /* fall through */
8270 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8271 this is a SIGN_EXTRACT. */
8278 {
8286 }
8288 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8289 If so, try to merge the shifts into a SIGN_EXTEND. We could
8290 also do this for some cases of SIGN_EXTRACT, but it doesn't
8291 seem worth the effort; the case checked for occurs on Alpha. */
8302 next_code),
8309 /* Call ourselves recursively on the inner expression. If we are
8310 narrowing the object and it has a different RTL code from
8311 what it originally did, do this SUBREG as a force_to_mode. */
8312 {
8316 /* If the SUBREG is masking of a logical right shift,
8317 make an extraction. */
8324 {
8333 }
8335 /* If in_code is COMPARE, it isn't always safe to pass it through
8336 to the recursive make_compound_operation call. */
8340 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8341 is (const_int 0), rather than
8342 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8343 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8344 for non-equality comparisons against 0 is not equivalent
8345 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8355 simplified
8363 {
8364 rtx newer
8367 /* If we have something other than a SUBREG, we might have
8368 done an expansion, so rerun ourselves. */
8372 /* force_to_mode can expand compounds. If it just re-expanded
8373 the compound, use gen_lowpart to convert to the desired
8374 mode. */
8376 /* Likewise if it re-expanded the compound only partially.
8377 This happens for SUBREG of ZERO_EXTRACT if they extract
8378 the same number of bits. */
8387 }
8391 }
8396 }
8402 }
8404 /* Look at the expression rooted at X. Look for expressions
8405 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8406 Form these expressions.
8408 Return the new rtx, usually just X.
8410 Also, for machines like the VAX that don't have logical shift insns,
8411 try to convert logical to arithmetic shift operations in cases where
8412 they are equivalent. This undoes the canonicalizations to logical
8413 shifts done elsewhere.
8415 We try, as much as possible, to re-use rtl expressions to save memory.
8417 IN_CODE says what kind of expression we are processing. Normally, it is
8418 SET. In a memory address it is MEM. When processing the arguments of
8419 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8420 precisely it is an equality comparison against zero. */
8422 rtx
8424 {
8431 /* Select the code to be used in recursive calls. Once we are inside an
8432 address, we stay there. If we have a comparison, set to COMPARE,
8433 but once inside, go back to our default of SET. */
8440 scalar_int_mode mode;
8442 {
8448 }
8450 /* Now recursively process each operand of this operation. We need to
8451 handle ZERO_EXTEND specially so that we don't lose track of the
8452 inner mode. */
8454 {
8462 }
8467 {
8470 }
8473 {
8476 }
8480 }
8481 \f
8482 /* Given M see if it is a value that would select a field of bits
8483 within an item, but not the entire word. Return -1 if not.
8484 Otherwise, return the starting position of the field, where 0 is the
8485 low-order bit.
8487 *PLEN is set to the length of the field. */
8489 static int
8491 {
8492 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8497 /* Now shift off the low-order zero bits and see if we have a
8498 power of two minus 1. */
8506 }
8507 \f
8508 /* If X refers to a register that equals REG in value, replace these
8509 references with REG. */
8510 static rtx
8512 {
8520 {
8553 /* FALLTHRU */
8557 {
8561 else
8563 }
8565 /* fall through */
8572 {
8575 {
8577 {
8580 }
8582 }
8583 }
8585 {
8588 {
8591 {
8593 {
8596 }
8598 }
8599 }
8600 }
8603 }
8606 }
8608 /* Return X converted to MODE. If the value is already truncated to
8609 MODE we can just return a subreg even though in the general case we
8610 would need an explicit truncation. */
8612 static rtx
8614 {
8619 {
8620 /* Bit-cast X into an integer mode. */
8625 }
8628 }
8630 /* See if X can be simplified knowing that we will only refer to it in
8631 MODE and will only refer to those bits that are nonzero in MASK.
8632 If other bits are being computed or if masking operations are done
8633 that select a superset of the bits in MASK, they can sometimes be
8634 ignored.
8636 Return a possibly simplified expression, but always convert X to
8637 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8639 If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8640 are all off in X. This is used when X will be complemented, by either
8641 NOT, NEG, or XOR. */
8643 static rtx
8646 {
8649 machine_mode op_mode;
8652 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8653 code below will do the wrong thing since the mode of such an
8654 expression is VOIDmode.
8656 Also do nothing if X is a CLOBBER; this can happen if X was
8657 the return value from a call to gen_lowpart. */
8661 /* We want to perform the operation in its present mode unless we know
8662 that the operation is valid in MODE, in which case we do the operation
8663 in MODE. */
8668 /* It is not valid to do a right-shift in a narrower mode
8669 than the one it came in with. */
8674 /* Truncate MASK to fit OP_MODE. */
8678 /* Determine what bits of X are guaranteed to be (non)zero. */
8681 /* If none of the bits in X are needed, return a zero. */
8685 /* If X is a CONST_INT, return a new one. Do this here since the
8686 test below will fail. */
8688 {
8691 else
8692 {
8695 }
8696 }
8698 /* If X is narrower than MODE and we want all the bits in X's mode, just
8699 get X in the proper mode. */
8704 /* We can ignore the effect of a SUBREG if it narrows the mode or
8705 if the constant masks to zero all the bits the mode doesn't have. */
8709 || (mask
8717 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8718 integer too. */
8724 }
8726 /* Subroutine of force_to_mode that handles cases in which both X and
8727 the result are scalar integers. MODE is the mode of the result,
8728 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8729 is preferred for simplified versions of X. The other arguments
8730 are as for force_to_mode. */
8732 static rtx
8736 {
8741 poly_int64 const_op0;
8743 /* When we have an arithmetic operation, or a shift whose count we
8744 do not know, we need to assume that all bits up to the highest-order
8745 bit in MASK will be needed. This is how we form such a mask. */
8748 else
8752 {
8754 /* If X is a (clobber (const_int)), return it since we know we are
8755 generating something that won't match. */
8768 /* Similarly for a truncate. */
8772 /* If this is an AND with a constant, convert it into an AND
8773 whose constant is the AND of that constant with MASK. If it
8774 remains an AND of MASK, delete it since it is redundant. */
8777 {
8782 /* If X is still an AND, see if it is an AND with a mask that
8783 is just some low-order bits. If so, and it is MASK, we don't
8784 need it. */
8790 /* If it remains an AND, try making another AND with the bits
8791 in the mode mask that aren't in MASK turned on. If the
8792 constant in the AND is wide enough, this might make a
8793 cheaper constant. */
8798 {
8799 unsigned HOST_WIDE_INT cval
8801 rtx y;
8808 }
8811 }
8816 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8817 low-order bits (as in an alignment operation) and FOO is already
8818 aligned to that boundary, mask C1 to that boundary as well.
8819 This may eliminate that PLUS and, later, the AND. */
8821 {
8825 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8826 number, sign extend it. */
8839 }
8841 /* fall through */
8844 /* Substituting into the operands of a widening MULT is not likely to
8845 create RTL matching a machine insn. */
8855 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8856 most significant bit in MASK since carries from those bits will
8857 affect the bits we are interested in. */
8862 /* If X is (minus C Y) where C's least set bit is larger than any bit
8863 in the mask, then we may replace with (neg Y). */
8866 {
8869 }
8871 /* Similarly, if C contains every bit in the fuller_mask, then we may
8872 replace with (not Y). */
8875 {
8878 }
8885 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8886 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8887 operation which may be a bitfield extraction. Ensure that the
8888 constant we form is not wider than the mode of X. */
8900 {
8903 xmode);
8909 }
8911 binop:
8912 /* For most binary operations, just propagate into the operation and
8913 change the mode if we have an operation of that mode. */
8918 /* If we ended up truncating both operands, truncate the result of the
8919 operation instead. */
8922 {
8925 }
8931 {
8934 }
8938 /* For left shifts, do the same, but just for the first operand.
8939 However, we cannot do anything with shifts where we cannot
8940 guarantee that the counts are smaller than the size of the mode
8941 because such a count will have a different meaning in a
8942 wider mode. */
8952 /* If the shift count is a constant and we can do arithmetic in
8953 the mode of the shift, refine which bits we need. Otherwise, use the
8954 conservative form of the mask. */
8960 else
8968 {
8971 }
8975 /* Here we can only do something if the shift count is a constant,
8976 this shift constant is valid for the host, and we can do arithmetic
8977 in OP_MODE. */
8983 {
8987 /* Select the mask of the bits we need for the shift operand. */
8990 /* We can only change the mode of the shift if we can do arithmetic
8991 in the mode of the shift and INNER_MASK is no wider than the
8992 width of X's mode. */
8999 {
9002 }
9003 }
9005 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9006 shift and AND produces only copies of the sign bit (C2 is one less
9007 than a power of two), we can do this with just a shift. */
9011 /* The shift puts one of the sign bit copies in the least significant
9012 bit. */
9017 /* Number of bits left after the shift must be more than the mask
9018 needs. */
9021 /* Must be more sign bit copies than the mask needs. */
9024 {
9028 }
9032 /* If we are just looking for the sign bit, we don't need this shift at
9033 all, even if it has a variable count. */
9037 /* If this is a shift by a constant, get a mask that contains those bits
9038 that are not copies of the sign bit. We then have two cases: If
9039 MASK only includes those bits, this can be a logical shift, which may
9040 allow simplifications. If MASK is a single-bit field not within
9041 those bits, we are requesting a copy of the sign bit and hence can
9042 shift the sign bit to the appropriate location. */
9046 {
9050 /* If the considered data is wider than HOST_WIDE_INT, we can't
9051 represent a mask for all its bits in a single scalar.
9052 But we only care about the lower bits, so calculate these. */
9055 {
9058 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9059 is the number of bits a full-width mask would have set.
9060 We need only shift if these are fewer than nonzero can
9061 hold. If not, we must keep all bits set in nonzero. */
9066 + HOST_BITS_PER_WIDE_INT
9068 }
9069 else
9070 {
9073 }
9076 {
9081 }
9084 {
9085 x = simplify_shift_const
9091 }
9092 }
9094 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9095 even if the shift count isn't a constant. */
9099 shiftrt:
9101 /* If this is a zero- or sign-extension operation that just affects bits
9102 we don't care about, remove it. Be sure the call above returned
9103 something that is still a shift. */
9118 /* If the shift count is constant and we can do computations
9119 in the mode of X, compute where the bits we care about are.
9120 Otherwise, we can't do anything. Don't change the mode of
9121 the shift or propagate MODE into the shift, though. */
9124 {
9133 }
9137 /* If we just want the low-order bit, the NEG isn't needed since it
9138 won't change the low-order bit. */
9142 /* We need any bits less significant than the most significant bit in
9143 MASK since carries from those bits will affect the bits we are
9144 interested in. */
9149 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9150 same as the XOR case above. Ensure that the constant we form is not
9151 wider than the mode of X. */
9159 {
9166 }
9168 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9169 use the full mask inside the NOT. */
9172 unop:
9175 next_select));
9177 {
9180 }
9184 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9185 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9186 which is equal to STORE_FLAG_VALUE. */
9198 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9199 written in a narrower mode. We play it safe and do not do so. */
9215 }
9217 /* Ensure we return a value of the proper mode. */
9219 }
9220 \f
9221 /* Return nonzero if X is an expression that has one of two values depending on
9222 whether some other value is zero or nonzero. In that case, we return the
9223 value that is being tested, *PTRUE is set to the value if the rtx being
9224 returned has a nonzero value, and *PFALSE is set to the other alternative.
9226 If we return zero, we set *PTRUE and *PFALSE to X. */
9228 static rtx
9230 {
9235 scalar_int_mode int_mode;
9237 /* If we are comparing a value against zero, we are done. */
9240 {
9244 }
9246 /* If this is a unary operation whose operand has one of two values, apply
9247 our opcode to compute those values. */
9250 {
9255 }
9257 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9258 make can't possibly match and would suppress other optimizations. */
9260 ;
9262 /* If this is a binary operation, see if either side has only one of two
9263 values. If either one does or if both do and they are conditional on
9264 the same value, compute the new true and false values. */
9266 {
9274 {
9275 /* Try to enable a simplification by undoing work done by
9276 if_then_else_cond if it converted a REG into something more
9277 complex. */
9279 {
9282 }
9283 else
9284 {
9287 }
9288 }
9292 {
9293 /* If if_then_else_cond returned zero, then true/false are the
9294 same rtl. We must copy one of them to prevent invalid rtl
9295 sharing. */
9302 {
9307 }
9308 else
9309 {
9312 }
9315 }
9317 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9318 operands is zero when the other is nonzero, and vice-versa,
9319 and STORE_FLAG_VALUE is 1 or -1. */
9325 {
9343 {
9350 const_true_rtx);
9352 }
9353 }
9355 /* Similarly for MULT, AND and UMIN, except that for these the result
9356 is always zero. */
9360 {
9374 {
9377 }
9378 }
9379 }
9382 {
9383 /* If we have IF_THEN_ELSE already, extract the condition and
9384 canonicalize it if it is NE or EQ. */
9390 {
9393 }
9394 else
9396 }
9398 /* If X is a SUBREG, we can narrow both the true and false values
9399 if the inner expression, if there is a condition. */
9403 {
9409 {
9413 }
9414 }
9416 /* If X is a constant, this isn't special and will cause confusions
9417 if we treat it as such. Likewise if it is equivalent to a constant. */
9420 ;
9422 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9423 will be least confusing to the rest of the compiler. */
9425 {
9428 }
9430 /* If X is known to be either 0 or -1, those are the true and
9431 false values when testing X. */
9436 {
9439 }
9441 /* Likewise for 0 or a single bit. */
9444 {
9447 }
9449 /* Otherwise fail; show no condition with true and false values the same. */
9452 }
9453 \f
9454 /* Return the value of expression X given the fact that condition COND
9455 is known to be true when applied to REG as its first operand and VAL
9456 as its second. X is known to not be shared and so can be modified in
9457 place.
9459 We only handle the simplest cases, and specifically those cases that
9460 arise with IF_THEN_ELSE expressions. */
9462 static rtx
9464 {
9472 /* If either operand of the condition is a floating point value,
9473 then we have to avoid collapsing an EQ comparison. */
9483 /* If X is (abs REG) and we know something about REG's relationship
9484 with zero, we may be able to simplify this. */
9488 {
9497 }
9499 /* The only other cases we handle are MIN, MAX, and comparisons if the
9500 operands are the same as REG and VAL. */
9503 {
9505 {
9508 }
9511 {
9513 {
9521 else
9523 }
9526 {
9529 /* Do not reverse the condition when it is NE or EQ.
9530 This is because we cannot conclude anything about
9531 the value of 'SMAX (x, y)' when x is not equal to y,
9532 but we can when x equals y. */
9538 {
9549 }
9550 }
9551 }
9552 }
9554 {
9559 {
9560 /* We must simplify subreg here, before we lose track of the
9561 original inner_mode. */
9566 else
9568 }
9571 }
9572 /* We don't have to handle SIGN_EXTEND here, because even in the
9573 case of replacing something with a modeless CONST_INT, a
9574 CONST_INT is already (supposed to be) a valid sign extension for
9575 its narrower mode, which implies it's already properly
9576 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9577 story is different. */
9579 {
9584 {
9585 /* We must simplify the zero_extend here, before we lose
9586 track of the original inner_mode. */
9591 else
9593 }
9596 }
9600 {
9607 }
9610 }
9611 \f
9612 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9613 assignment as a field assignment. */
9615 static bool
9617 {
9619 {
9627 }
9635 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9636 Note that all SUBREGs of MEM are paradoxical; otherwise they
9637 would have been rewritten. */
9650 /* We used to see if get_last_value of X and Y were the same but that's
9651 not correct. In one direction, we'll cause the assignment to have
9652 the wrong destination and in the case, we'll import a register into this
9653 insn that might have already have been dead. So fail if none of the
9654 above cases are true. */
9656 }
9657 \f
9658 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9659 Return that assignment if so.
9661 We only handle the most common cases. */
9663 static rtx
9665 {
9668 rtx assign;
9670 HOST_WIDE_INT c1;
9671 HOST_WIDE_INT pos;
9673 rtx other;
9675 /* All the rules in this function are specific to scalar integers. */
9676 scalar_int_mode mode;
9680 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9681 a clear of a one-bit field. We will have changed it to
9682 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9683 for a SUBREG. */
9689 {
9695 }
9704 {
9711 }
9713 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9714 one-bit field. */
9718 {
9724 }
9726 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9727 SRC is an AND with all bits of that field set, then we can discard
9728 the AND. */
9733 {
9740 else
9743 /* Complete overlap. We can remove the source AND. */
9747 /* Partial overlap. We can reduce the source AND. */
9749 {
9753 }
9754 }
9756 /* The other case we handle is assignments into a constant-position
9757 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9758 a mask that has all one bits except for a group of zero bits and
9759 OTHER is known to have zeros where C1 has ones, this is such an
9760 assignment. Compute the position and length from C1. Shift OTHER
9761 to the appropriate position, force it to the required mode, and
9762 make the extraction. Check for the AND in both operands. */
9764 /* One or more SUBREGs might obscure the constant-position field
9765 assignment. The first one we are likely to encounter is an outer
9766 narrowing SUBREG, which we can just strip for the purposes of
9767 identifying the constant-field assignment. */
9784 /* The second SUBREG that might get in the way is a paradoxical
9785 SUBREG around the first operand of the AND. We want to
9786 pretend the operand is as wide as the destination here. We
9787 do this by adjusting the MEM to wider mode for the sole
9788 purpose of the call to rtx_equal_for_field_assignment_p. Also
9789 note this trick only works for MEMs. */
9801 /* The second SUBREG that might get in the way is a paradoxical
9802 SUBREG around the first operand of the AND. We want to
9803 pretend the operand is as wide as the destination here. We
9804 do this by adjusting the MEM to wider mode for the sole
9805 purpose of the call to rtx_equal_for_field_assignment_p. Also
9806 note this trick only works for MEMs. */
9814 else
9829 /* The mode to use for the source is the mode of the assignment, or of
9830 what is inside a possible STRICT_LOW_PART. */
9834 /* Shift OTHER right POS places and make it the source, restricting it
9835 to the proper length and mode. */
9839 dest);
9841 len >= HOST_BITS_PER_WIDE_INT
9842 ? HOST_WIDE_INT_M1U
9845 /* If SRC is masked by an AND that does not make a difference in
9846 the value being stored, strip it. */
9857 }
9858 \f
9859 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9860 if so. */
9862 static rtx
9864 {
9868 rtx tem;
9870 /* Distributivity is not true for floating point as it can change the
9871 value. So we don't do it unless -funsafe-math-optimizations. */
9876 /* The outer operation can only be one of the following: */
9884 /* If either operand is a primitive we can't do anything, so get out
9885 fast. */
9895 /* See if the inner and outer operations distribute. */
9897 {
9902 /* These all distribute except over PLUS. */
9913 /* This is also a multiply, so it distributes over everything. */
9916 /* This used to handle SUBREG, but this turned out to be counter-
9917 productive, since (subreg (op ...)) usually is not handled by
9918 insn patterns, and this "optimization" therefore transformed
9919 recognizable patterns into unrecognizable ones. Therefore the
9920 SUBREG case was removed from here.
9922 It is possible that distributing SUBREG over arithmetic operations
9923 leads to an intermediate result than can then be optimized further,
9924 e.g. by moving the outer SUBREG to the other side of a SET as done
9925 in simplify_set. This seems to have been the original intent of
9926 handling SUBREGs here.
9928 However, with current GCC this does not appear to actually happen,
9929 at least on major platforms. If some case is found where removing
9930 the SUBREG case here prevents follow-on optimizations, distributing
9931 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9935 }
9937 /* Set LHS and RHS to the inner operands (A and B in the example
9938 above) and set OTHER to the common operand (C in the example).
9939 There is only one way to do this unless the inner operation is
9940 commutative. */
9952 else
9955 /* Form the new inner operation, seeing if it simplifies first. */
9958 /* There is one exception to the general way of distributing:
9959 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9961 {
9964 }
9966 /* We may be able to continuing distributing the result, so call
9967 ourselves recursively on the inner operation before forming the
9968 outer operation, which we return. */
9971 }
9973 /* See if X is of the form (* (+ A B) C), and if so convert to
9974 (+ (* A C) (* B C)) and try to simplify.
9976 Most of the time, this results in no change. However, if some of
9977 the operands are the same or inverses of each other, simplifications
9978 will result.
9980 For example, (and (ior A B) (not B)) can occur as the result of
9981 expanding a bit field assignment. When we apply the distributive
9982 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9983 which then simplifies to (and (A (not B))).
9985 Note that no checks happen on the validity of applying the inverse
9986 distributive law. This is pointless since we can do it in the
9987 few places where this routine is called.
9989 N is the index of the term that is decomposed (the arithmetic operation,
9990 i.e. (+ A B) in the first example above). !N is the index of the term that
9991 is distributed, i.e. of C in the first example above. */
9992 static rtx
9994 {
9995 machine_mode mode;
9999 /* Distributivity is not true for floating point as it can change the
10000 value. So we don't do it unless -funsafe-math-optimizations. */
10017 /* Special case (and (xor B C) (not A)), which is equivalent to
10018 (xor (ior A B) (ior A C)) */
10020 {
10023 }
10026 {
10027 /* Distribute the second term. */
10030 }
10031 else
10032 {
10033 /* Distribute the first term. */
10036 }
10046 }
10047 \f
10048 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10049 in MODE. Return an equivalent form, if different from (and VAROP
10050 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10052 static rtx
10055 {
10058 rtx orig_varop;
10066 /* Simplify VAROP knowing that we will be only looking at some of the
10067 bits in it.
10069 Note by passing in CONSTOP, we guarantee that the bits not set in
10070 CONSTOP are not significant and will never be examined. We must
10071 ensure that is the case by explicitly masking out those bits
10072 before returning. */
10075 /* If VAROP is a CLOBBER, we will fail so return it. */
10079 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10080 to VAROP and return the new constant. */
10084 /* See what bits may be nonzero in VAROP. Unlike the general case of
10085 a call to nonzero_bits, here we don't care about bits outside
10086 MODE unless WORD_REGISTER_OPERATIONS is true. */
10093 /* Turn off all bits in the constant that are known to already be zero.
10094 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10095 which is tested below. */
10099 /* If we don't have any bits left, return zero. */
10103 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10104 a power of two, we can replace this with an ASHIFT. */
10109 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10110 or XOR, then try to apply the distributive law. This may eliminate
10111 operations if either branch can be simplified because of the AND.
10112 It may also make some cases more complex, but those cases probably
10113 won't match a pattern either with or without this. */
10116 {
10118 return
10119 gen_lowpart
10121 apply_distributive_law
10125 constop),
10128 constop))));
10129 }
10131 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10132 the AND and see if one of the operands simplifies to zero. If so, we
10133 may eliminate it. */
10137 {
10146 }
10148 /* Make a SUBREG if necessary. If we can't make it, fail. */
10153 /* If we are only masking insignificant bits, return VAROP. */
10160 /* Otherwise, return an AND. */
10162 }
10165 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10166 in MODE.
10168 Return an equivalent form, if different from X. Otherwise, return X. If
10169 X is zero, we are to always construct the equivalent form. */
10171 static rtx
10174 {
10185 }
10186 \f
10187 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10188 We don't care about bits outside of those defined in MODE.
10189 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10191 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10192 a shift, AND, or zero_extract, we can do better. */
10194 static rtx
10196 scalar_int_mode mode,
10198 {
10199 rtx tem;
10202 /* If X is a register whose nonzero bits value is current, use it.
10203 Otherwise, if X is a register whose value we can find, use that
10204 value. Otherwise, use the previously-computed global nonzero bits
10205 for this register. */
10220 && !REGNO_REG_SET_P
10223 {
10224 /* Note that, even if the precision of last_set_mode is lower than that
10225 of mode, record_value_for_reg invoked nonzero_bits on the register
10226 with nonzero_bits_mode (because last_set_mode is necessarily integral
10227 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10228 are all valid, hence in mode too since nonzero_bits_mode is defined
10229 to the largest HWI_COMPUTABLE_MODE_P mode. */
10232 }
10236 {
10241 }
10244 {
10248 /* We don't know anything about the upper bits. */
10252 }
10255 }
10257 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10258 end of X that are known to be equal to the sign bit. X will be used
10259 in mode MODE; the returned value will always be between 1 and the
10260 number of bits in MODE. */
10262 static rtx
10264 scalar_int_mode mode,
10266 {
10267 rtx tem;
10280 && !REGNO_REG_SET_P
10283 {
10286 }
10297 }
10298 \f
10299 /* Return the number of "extended" bits there are in X, when interpreted
10300 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10301 unsigned quantities, this is the number of high-order zero bits.
10302 For signed quantities, this is the number of copies of the sign bit
10303 minus 1. In both case, this function returns the number of "spare"
10304 bits. For example, if two quantities for which this function returns
10305 at least 1 are added, the addition is known not to overflow.
10307 This function will always return 0 unless called during combine, which
10308 implies that it must be called from a define_split. */
10310 unsigned int
10312 {
10316 scalar_int_mode int_mode;
10324 }
10326 /* This function is called from `simplify_shift_const' to merge two
10327 outer operations. Specifically, we have already found that we need
10328 to perform operation *POP0 with constant *PCONST0 at the outermost
10329 position. We would now like to also perform OP1 with constant CONST1
10330 (with *POP0 being done last).
10332 Return true if we can do the operation and update *POP0 and *PCONST0 with
10333 the resulting operation. *PCOMP_P is set to true if we would need to
10334 complement the innermost operand, otherwise it is unchanged.
10336 MODE is the mode in which the operation will be done. No bits outside
10337 the width of this mode matter. It is assumed that the width of this mode
10338 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10340 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10341 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10342 result is simply *PCONST0.
10344 If the resulting operation cannot be expressed as one operation, we
10345 return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10347 static bool
10351 {
10358 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10362 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10363 if OP0 is SET. */
10372 {
10374 {
10392 }
10393 }
10395 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10399 /* If the two constants aren't the same, we can't do anything. The
10400 remaining six cases can all be done. */
10404 else
10406 {
10409 /* (a & b) | b == b */
10412 /* (a ^ b) | b == a | b */
10413 {;}
10418 /* (a & b) ^ b == (~a) & b */
10421 /* (a | b) ^ b == a & ~b */
10427 /* (a | b) & b == b */
10430 /* (a ^ b) & b) == (~a) & b */
10435 }
10437 /* Check for NO-OP cases. */
10450 /* ??? Slightly redundant with the above mask, but not entirely.
10451 Moving this above means we'd have to sign-extend the mode mask
10452 for the final test. */
10457 }
10458 \f
10459 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10460 the shift in. The original shift operation CODE is performed on OP in
10461 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10462 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10463 result of the shift is subject to operation OUTER_CODE with operand
10464 OUTER_CONST. */
10466 static scalar_int_mode
10470 {
10473 /* In general we can't perform in wider mode for right shift and rotate. */
10475 {
10477 /* We can still widen if the bits brought in from the left are identical
10478 to the sign bit of ORIG_MODE. */
10486 /* Similarly here but with zero bits. */
10491 /* We can also widen if the bits brought in will be masked off. This
10492 operation is performed in ORIG_MODE. */
10494 {
10500 }
10501 /* fall through */
10511 }
10512 }
10514 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10515 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10516 if we cannot simplify it. Otherwise, return a simplified value.
10518 The shift is normally computed in the widest mode we find in VAROP, as
10519 long as it isn't a different number of words than RESULT_MODE. Exceptions
10520 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10522 static rtx
10525 {
10530 machine_mode shift_mode;
10532 /* We form (outer_op (code varop count) (outer_const)). */
10538 /* Make sure and truncate the "natural" shift on the way in. We don't
10539 want to do this inside the loop as it makes it more difficult to
10540 combine shifts. */
10544 /* If we were given an invalid count, don't do anything except exactly
10545 what was requested. */
10552 /* Unless one of the branches of the `if' in this loop does a `continue',
10553 we will `break' the loop after the `if'. */
10556 {
10557 /* If we have an operand of (clobber (const_int 0)), fail. */
10561 /* Convert ROTATERT to ROTATE. */
10563 {
10567 }
10571 {
10572 /* We only change the modes of scalar shifts. */
10578 }
10580 scalar_int_mode shift_unit_mode
10583 /* Handle cases where the count is greater than the size of the mode
10584 minus 1. For ASHIFT, use the size minus one as the count (this can
10585 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10586 take the count modulo the size. For other shifts, the result is
10587 zero.
10589 Since these shifts are being produced by the compiler by combining
10590 multiple operations, each of which are defined, we know what the
10591 result is supposed to be. */
10594 {
10599 else
10600 {
10601 /* We can't simply return zero because there may be an
10602 outer op. */
10606 }
10607 }
10609 /* If we discovered we had to complement VAROP, leave. Making a NOT
10610 here would cause an infinite loop. */
10615 {
10616 /* An arithmetic right shift of a quantity known to be -1 or 0
10617 is a no-op. */
10621 {
10624 }
10626 /* If we are doing an arithmetic right shift and discarding all but
10627 the sign bit copies, this is equivalent to doing a shift by the
10628 bitsize minus one. Convert it into that shift because it will
10629 often allow other simplifications. */
10636 /* We simplify the tests below and elsewhere by converting
10637 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10638 `make_compound_operation' will convert it to an ASHIFTRT for
10639 those machines (such as VAX) that don't have an LSHIFTRT. */
10644 shift_unit_mode)))
10656 }
10659 {
10666 {
10669 }
10673 /* The following rules apply only to scalars. */
10678 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10679 minus the width of a smaller mode, we can do this with a
10680 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10687 {
10696 }
10700 /* The following rules apply only to scalars. */
10706 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10707 the same number of words as what we've seen so far. Then store
10708 the widest mode in MODE. */
10715 {
10720 }
10724 /* Some machines use MULT instead of ASHIFT because MULT
10725 is cheaper. But it is still better on those machines to
10726 merge two shifts into one. */
10729 {
10734 }
10738 /* Similar, for when divides are cheaper. */
10741 {
10746 }
10750 /* If we are extracting just the sign bit of an arithmetic
10751 right shift, that shift is not needed. However, the sign
10752 bit of a wider mode may be different from what would be
10753 interpreted as the sign bit in a narrower mode, so, if
10754 the result is narrower, don't discard the shift. */
10759 {
10762 }
10764 /* fall through */
10769 /* The following rules apply only to scalars. */
10776 /* Here we have two nested shifts. The result is usually the
10777 AND of a new shift with a mask. We compute the result below. */
10783 {
10787 rtx mask_rtx;
10789 /* We have one common special case. We can't do any merging if
10790 the inner code is an ASHIFTRT of a smaller mode. However, if
10791 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10792 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10793 we can convert it to
10794 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10795 This simplifies certain SIGN_EXTEND operations. */
10799 {
10800 /* C3 has the low-order C1 bits zero. */
10812 }
10814 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10815 than C1 high-order bits equal to the sign bit, we can convert
10816 this to either an ASHIFT or an ASHIFTRT depending on the
10817 two counts.
10819 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10825 {
10829 {
10832 }
10835 }
10837 /* There are some cases we can't do. If CODE is ASHIFTRT,
10838 we can only do this if FIRST_CODE is also ASHIFTRT.
10840 We can't do the case when CODE is ROTATE and FIRST_CODE is
10841 ASHIFTRT.
10843 If the mode of this shift is not the mode of the outer shift,
10844 we can't do this if either shift is a right shift or ROTATE.
10846 Finally, we can't do any of these if the mode is too wide
10847 unless the codes are the same.
10849 Handle the case where the shift codes are the same
10850 first. */
10853 {
10862 }
10873 /* To compute the mask to apply after the shift, shift the
10874 nonzero bits of the inner shift the same way the
10875 outer shift will. */
10878 int_result_mode);
10880 mask_rtx
10884 /* Give up if we can't compute an outer operation to use. */
10892 /* If the shifts are in the same direction, we add the
10893 counts. Otherwise, we subtract them. */
10897 else
10900 /* If COUNT is positive, the new shift is usually CODE,
10901 except for the two exceptions below, in which case it is
10902 FIRST_CODE. If the count is negative, FIRST_CODE should
10903 always be used */
10913 }
10915 /* If we have (A << B << C) for any shift, we can convert this to
10916 (A << C << B). This wins if A is a constant. Only try this if
10917 B is not a constant. */
10922 {
10923 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10924 sure the result will be masked. See PR70222. */
10932 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10933 up outer sign extension (often left and right shift) is
10934 hardly more efficient than the original. See PR70429.
10935 Similarly punt for rotates with different modes.
10936 See PR97386. */
10944 count_rtx);
10948 }
10952 /* The following rules apply only to scalars. */
10956 /* Make this fit the case below. */
10963 /* The following rules apply only to scalars. */
10969 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10970 with C the size of VAROP - 1 and the shift is logical if
10971 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10972 we have an (le X 0) operation. If we have an arithmetic shift
10973 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10974 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10982 {
10985 const0_rtx);
10991 }
10993 /* If we have (shift (logical)), move the logical to the outside
10994 to allow it to possibly combine with another logical and the
10995 shift to combine with another shift. This also canonicalizes to
10996 what a ZERO_EXTRACT looks like. Also, some machines have
10997 (and (shift)) insns. */
11000 /* We can't do this if we have (ashiftrt (xor)) and the
11001 constant has its sign bit set in shift_unit_mode with
11002 shift_unit_mode wider than result_mode. */
11015 {
11018 }
11020 /* If we can't do that, try to simplify the shift in each arm of the
11021 logical expression, make a new logical expression, and apply
11022 the inverse distributive law. This also can't be done for
11023 (ashiftrt (xor)) where we've widened the shift and the constant
11024 changes the sign bit. */
11030 {
11042 }
11046 /* The following rules apply only to scalars. */
11051 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11052 says that the sign bit can be tested, FOO has mode MODE, C is
11053 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11054 that may be nonzero. */
11064 {
11068 }
11072 /* The following rules apply only to scalars. */
11077 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11078 than the number of bits in the mode is equivalent to A. */
11082 {
11086 }
11088 /* NEG commutes with ASHIFT since it is multiplication. Move the
11089 NEG outside to allow shifts to combine. */
11093 {
11096 }
11100 /* The following rules apply only to scalars. */
11105 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11106 is one less than the number of bits in the mode is
11107 equivalent to (xor A 1). */
11114 {
11118 }
11120 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11121 that might be nonzero in BAR are those being shifted out and those
11122 bits are known zero in FOO, we can replace the PLUS with FOO.
11123 Similarly in the other operand order. This code occurs when
11124 we are computing the size of a variable-size array. */
11131 {
11134 }
11142 {
11145 }
11147 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11158 {
11161 }
11163 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11164 signbit', and attempt to change the PLUS to an XOR and move it to
11165 the outer operation as is done above in the AND/IOR/XOR case
11166 leg for shift(logical). See details in logical handling above
11167 for reasoning in doing so. */
11179 {
11182 }
11187 /* The following rules apply only to scalars. */
11192 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11193 with C the size of VAROP - 1 and the shift is logical if
11194 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11195 we have a (gt X 0) operation. If the shift is arithmetic with
11196 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11197 we have a (neg (gt X 0)) operation. */
11206 {
11209 const0_rtx);
11215 }
11219 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11220 if the truncate does not affect the value. */
11227 {
11231 new_count);
11234 new_count_rtx);
11238 }
11243 }
11246 }
11250 {
11251 /* We only change the modes of scalar shifts. */
11256 }
11258 /* We have now finished analyzing the shift. The result should be
11259 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11260 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11261 to the result of the shift. OUTER_CONST is the relevant constant,
11262 but we must turn off all bits turned off in the shift. */
11270 /* Make a SUBREG if necessary. If we can't make it, fail. */
11275 /* If we have an outer operation and we just made a shift, it is
11276 possible that we could have simplified the shift were it not
11277 for the outer operation. So try to do the simplification
11278 recursively. */
11282 else
11289 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11290 turn off all the bits that the shift would have turned off. */
11292 /* We only change the modes of scalar shifts. */
11296 /* Do the remainder of the processing in RESULT_MODE. */
11299 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11300 operation. */
11305 {
11315 {
11316 /* This means that we have determined that the result is
11317 equivalent to a constant. This should be rare. */
11320 }
11323 else
11326 }
11329 }
11331 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11332 The result of the shift is RESULT_MODE. If we cannot simplify it,
11333 return X or, if it is NULL, synthesize the expression with
11334 simplify_gen_binary. Otherwise, return a simplified value.
11336 The shift is normally computed in the widest mode we find in VAROP, as
11337 long as it isn't a different number of words than RESULT_MODE. Exceptions
11338 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11340 static rtx
11343 {
11354 }
11356 \f
11357 /* A subroutine of recog_for_combine. See there for arguments and
11358 return value. */
11360 static int
11362 {
11364 rtx pat_without_clobbers;
11372 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11373 we use to indicate that something didn't match. If we find such a
11374 thing, force rejection. */
11388 {
11391 else
11394 }
11396 /* If it isn't, there is the possibility that we previously had an insn
11397 that clobbered some register as a side effect, but the combined
11398 insn doesn't need to do that. So try once more without the clobbers
11399 unless this represents an ASM insn. */
11403 {
11408 {
11411 pos++;
11412 }
11422 {
11425 else
11428 }
11429 }
11436 /* Recognize all noop sets, these will be killed by followup pass. */
11440 /* If we had any clobbers to add, make a new pattern than contains
11441 them. Then check to make sure that all of them are dead. */
11443 {
11453 else
11460 {
11465 {
11469 }
11470 }
11472 }
11476 {
11484 /* Allow targets to reject combined insn. */
11486 {
11489 dump_file);
11491 /* Callers expect recog_for_combine to strip
11492 clobbers from the pattern on failure. */
11497 }
11502 }
11508 }
11510 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11511 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11512 Return whether anything was so changed. */
11514 static bool
11516 {
11522 {
11534 {
11544 else
11548 {
11554 }
11555 }
11561 {
11566 {
11572 }
11573 }
11578 {
11582 }
11583 else
11589 {
11592 }
11596 }
11603 scalar_int_mode mode;
11609 {
11623 else
11631 }
11634 }
11636 /* Like recog, but we receive the address of a pointer to a new pattern.
11637 We try to match the rtx that the pointer points to.
11638 If that fails, we may try to modify or replace the pattern,
11639 storing the replacement into the same pointer object.
11641 Modifications include deletion or addition of CLOBBERs. If the
11642 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11643 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11644 (and undo if that fails).
11646 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11647 the CLOBBERs are placed.
11649 The value is the final insn code from the pattern ultimately matched,
11650 or -1. */
11652 static int
11654 {
11664 {
11665 /* For an unrecognized single set of a constant, try placing it in
11666 the constant pool, if this function already uses one. */
11671 {
11677 {
11680 }
11681 }
11682 else
11684 }
11686 {
11689 {
11693 }
11694 }
11697 {
11702 }
11705 }
11706 \f
11707 /* Like gen_lowpart_general but for use by combine. In combine it
11708 is not possible to create any new pseudoregs. However, it is
11709 safe to create invalid memory addresses, because combine will
11710 try to recognize them and all they will do is make the combine
11711 attempt fail.
11713 If for some reason this cannot do its job, an rtx
11714 (clobber (const_int 0)) is returned.
11715 An insn containing that will not be recognized. */
11717 static rtx
11719 {
11721 rtx result;
11726 /* We can only support MODE being wider than a word if X is a
11727 constant integer or has a mode the same size. */
11733 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11734 won't know what to do. So we will strip off the SUBREG here and
11735 process normally. */
11737 {
11740 /* For use in case we fall down into the address adjustments
11741 further below, we need to adjust the known mode and size of
11742 x; imode and isize, since we just adjusted x. */
11747 }
11755 {
11756 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11757 address. */
11762 /* If we want to refer to something bigger than the original memref,
11763 generate a paradoxical subreg instead. That will force a reload
11764 of the original memref X. */
11770 }
11772 /* If X is a comparison operator, rewrite it in a new mode. This
11773 probably won't match, but may allow further simplifications. */
11779 /* If we couldn't simplify X any other way, just enclose it in a
11780 SUBREG. Normally, this SUBREG won't match, but some patterns may
11781 include an explicit SUBREG or we may simplify it further in combine. */
11782 else
11783 {
11784 rtx res;
11787 {
11792 }
11796 }
11798 fail:
11800 }
11801 \f
11802 /* Try to simplify a comparison between OP0 and a constant OP1,
11803 where CODE is the comparison code that will be tested, into a
11804 (CODE OP0 const0_rtx) form.
11806 The result is a possibly different comparison code to use.
11807 *POP1 may be updated. */
11809 static enum rtx_code
11812 {
11813 scalar_int_mode int_mode;
11816 /* Get the constant we are comparing against and turn off all bits
11817 not on in our mode. */
11821 /* If we are comparing against a constant power of two and the value
11822 being compared can only have that single bit nonzero (e.g., it was
11823 `and'ed with that bit), we can replace this with a comparison
11824 with zero. */
11833 {
11836 }
11838 /* Similarly, if we are comparing a value known to be either -1 or
11839 0 with -1, change it to the opposite comparison against zero. */
11845 {
11848 }
11850 /* Do some canonicalizations based on the comparison code. We prefer
11851 comparisons against zero and then prefer equality comparisons.
11852 If we can reduce the size of a constant, we will do that too. */
11854 {
11856 /* < C is equivalent to <= (C - 1) */
11858 {
11861 /* ... fall through to LE case below. */
11863 }
11864 else
11868 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11870 {
11873 }
11875 /* If we are doing a <= 0 comparison on a value known to have
11876 a zero sign bit, we can replace this with == 0. */
11887 /* >= C is equivalent to > (C - 1). */
11889 {
11892 /* ... fall through to GT below. */
11894 }
11895 else
11899 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11901 {
11904 }
11906 /* If we are doing a > 0 comparison on a value known to have
11907 a zero sign bit, we can replace this with != 0. */
11918 /* < C is equivalent to <= (C - 1). */
11920 {
11923 /* ... fall through ... */
11925 }
11926 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11931 {
11935 }
11936 else
11940 /* unsigned <= 0 is equivalent to == 0 */
11943 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11947 == ((HOST_WIDE_INT_1U
11949 {
11952 }
11956 /* >= C is equivalent to > (C - 1). */
11958 {
11961 /* ... fall through ... */
11963 }
11965 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11970 {
11974 }
11975 else
11979 /* unsigned > 0 is equivalent to != 0 */
11982 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11986 == (HOST_WIDE_INT_1U
11988 {
11991 }
11996 }
12000 }
12001 \f
12002 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12003 comparison code that will be tested.
12005 The result is a possibly different comparison code to use. *POP0 and
12006 *POP1 may be updated.
12008 It is possible that we might detect that a comparison is either always
12009 true or always false. However, we do not perform general constant
12010 folding in combine, so this knowledge isn't useful. Such tautologies
12011 should have been detected earlier. Hence we ignore all such cases. */
12013 static enum rtx_code
12015 {
12021 opt_scalar_int_mode tmode_iter;
12023 /* Try a few ways of applying the same transformation to both operands. */
12025 {
12026 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12027 so check specially. */
12046 {
12049 }
12051 /* If both operands are the same constant shift, see if we can ignore the
12052 shift. We can if the shift is a rotate or if the bits shifted out of
12053 this shift are known to be zero for both inputs and if the type of
12054 comparison is compatible with the shift. */
12067 {
12080 else
12082 }
12084 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12085 SUBREGs are of the same mode, and, in both cases, the AND would
12086 be redundant if the comparison was done in the narrower mode,
12087 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12088 and the operand's possibly nonzero bits are 0xffffff01; in that case
12089 if we only care about QImode, we don't need the AND). This case
12090 occurs if the output mode of an scc insn is not SImode and
12091 STORE_FLAG_VALUE == 1 (e.g., the 386).
12093 Similarly, check for a case where the AND's are ZERO_EXTEND
12094 operations from some narrower mode even though a SUBREG is not
12095 present. */
12100 {
12116 {
12120 /* The resulting comparison is always unsigned since we masked
12121 off the original sign bit. */
12125 }
12131 {
12137 }
12141 }
12143 /* If both operands are NOT, we can strip off the outer operation
12144 and adjust the comparison code for swapped operands; similarly for
12145 NEG, except that this must be an equality comparison. */
12151 else
12153 }
12155 /* If the first operand is a constant, swap the operands and adjust the
12156 comparison code appropriately, but don't do this if the second operand
12157 is already a constant integer. */
12159 {
12162 }
12164 /* We now enter a loop during which we will try to simplify the comparison.
12165 For the most part, we only are concerned with comparisons with zero,
12166 but some things may really be comparisons with zero but not start
12167 out looking that way. */
12170 {
12172 scalar_int_mode int_mode;
12176 HOST_WIDE_INT const_op;
12178 /* We only want to handle integral modes. This catches VOIDmode,
12179 CCmode, and the floating-point modes. An exception is that we
12180 can handle VOIDmode if OP0 is a COMPARE or a comparison
12181 operation. */
12188 /* Try to simplify the compare to constant, possibly changing the
12189 comparison op, and/or changing op1 to zero. */
12193 /* Compute some predicates to simplify code below. */
12200 /* If this is a sign bit comparison and we can do arithmetic in
12201 MODE, say that we will only be needing the sign bit of OP0. */
12206 HOST_WIDE_INT_1U
12210 {
12211 /* We can't do anything if OP0 is a condition code value, rather
12212 than an actual data value. */
12217 /* Get the two operands being compared. */
12220 else
12223 /* Check for the cases where we simply want the result of the
12224 earlier test or the opposite of that result. */
12228 {
12232 else
12236 {
12241 }
12242 }
12244 }
12250 /* Now try cases based on the opcode of OP0. If none of the cases
12251 does a "continue", we exit this loop immediately after the
12252 switch. */
12257 {
12259 /* If we are extracting a single bit from a variable position in
12260 a constant that has only a single bit set and are comparing it
12261 with zero, we can convert this into an equality comparison
12262 between the position and the location of the single bit. */
12263 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12264 have already reduced the shift count modulo the word size. */
12270 {
12278 /* Result is nonzero iff shift count is equal to I. */
12281 }
12283 /* fall through */
12288 {
12291 }
12295 /* If testing for equality, we can take the NOT of the constant. */
12298 {
12302 }
12304 /* If just looking at the sign bit, reverse the sense of the
12305 comparison. */
12307 {
12311 }
12315 /* If testing for equality, we can take the NEG of the constant. */
12318 {
12322 }
12324 /* The remaining cases only apply to comparisons with zero. */
12328 /* When X is ABS or is known positive,
12329 (neg X) is < 0 if and only if X != 0. */
12337 {
12341 }
12343 /* If we have NEG of something whose two high-order bits are the
12344 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12346 {
12350 }
12354 /* If we are testing equality and our count is a constant, we
12355 can perform the inverse operation on our RHS. */
12359 {
12363 }
12365 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12366 a particular bit. Convert it to an AND of a constant of that
12367 bit. This will be converted into a ZERO_EXTRACT. */
12372 {
12374 (HOST_WIDE_INT_1U
12379 }
12381 /* Fall through. */
12384 /* ABS is ignorable inside an equality comparison with zero. */
12386 {
12389 }
12393 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12394 (compare FOO CONST) if CONST fits in FOO's mode and we
12395 are either testing inequality or have an unsigned
12396 comparison with ZERO_EXTEND or a signed comparison with
12397 SIGN_EXTEND. But don't do it if we don't have a compare
12398 insn of the given mode, since we'd have to revert it
12399 later on, and then we wouldn't know whether to sign- or
12400 zero-extend. */
12402 && ! unsigned_comparison_p
12406 {
12409 }
12413 /* Check for the case where we are comparing A - C1 with C2, that is
12415 (subreg:MODE (plus (A) (-C1))) op (C2)
12417 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12418 comparison in the wider mode. One of the following two conditions
12419 must be true in order for this to be valid:
12421 1. The mode extension results in the same bit pattern being added
12422 on both sides and the comparison is equality or unsigned. As
12423 C2 has been truncated to fit in MODE, the pattern can only be
12424 all 0s or all 1s.
12426 2. The mode extension results in the sign bit being copied on
12427 each side.
12429 The difficulty here is that we have predicates for A but not for
12430 (A - C1) so we need to check that C1 is within proper bounds so
12431 as to perturbate A as little as possible. */
12440 {
12448 /* (A - C1) zero-extends if it is positive and sign-extends
12449 if it is negative, C2 both zero- and sign-extends. */
12453 /* (A - C1) sign-extends if it is positive and 1-extends
12454 if it is negative, C2 both sign- and 1-extends. */
12461 /* (A - C1) always sign-extends, like C2. */
12465 {
12468 }
12469 }
12471 /* If the inner mode is narrower and we are extracting the low part,
12472 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12474 ;
12483 {
12484 /* Remove outer subregs that don't do anything. */
12489 {
12493 }
12495 }
12496 else
12499 /* FALLTHROUGH */
12508 {
12511 }
12515 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12516 this for equality comparisons due to pathological cases involving
12517 overflows. */
12521 {
12525 }
12527 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12530 {
12534 }
12538 /* We used to optimize signed comparisons against zero, but that
12539 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12540 arrive here as equality comparisons, or (GEU, LTU) are
12541 optimized away. No need to special-case them. */
12543 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12544 (eq B (minus A C)), whichever simplifies. We can only do
12545 this for equality comparisons due to pathological cases involving
12546 overflows. */
12550 {
12554 }
12559 {
12563 }
12565 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12566 of bits in X minus 1, is one iff X > 0. */
12571 {
12575 }
12579 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12580 if C is zero or B is a constant. */
12584 {
12588 }
12593 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12594 iff X <= 0. */
12598 {
12602 }
12606 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12607 will be converted to a ZERO_EXTRACT later. */
12611 {
12616 }
12618 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12619 zero and X is a comparison and C1 and C2 describe only bits set
12620 in STORE_FLAG_VALUE, we can compare with X. */
12628 {
12635 {
12638 }
12639 }
12641 /* If we are doing an equality comparison of an AND of a bit equal
12642 to the sign bit, replace this with a LT or GE comparison of
12643 the underlying value. */
12650 {
12654 }
12656 /* If this AND operation is really a ZERO_EXTEND from a narrower
12657 mode, the constant fits within that mode, and this is either an
12658 equality or unsigned comparison, try to do this comparison in
12659 the narrower mode.
12661 Note that in:
12663 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12664 -> (ne:DI (reg:SI 4) (const_int 0))
12666 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12667 known to hold a value of the required mode the
12668 transformation is invalid. */
12676 {
12679 }
12681 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12682 fits in both M1 and M2 and the SUBREG is either paradoxical
12683 or represents the low part, permute the SUBREG and the AND
12684 and try again. */
12687 {
12689 /* Require an integral mode, to avoid creating something like
12690 (AND:SF ...). */
12693 /* It is unsafe to commute the AND into the SUBREG if the
12694 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12695 not defined. As originally written the upper bits
12696 have a defined value due to the AND operation.
12697 However, if we commute the AND inside the SUBREG then
12698 they no longer have defined values and the meaning of
12699 the code has been changed.
12700 Also C1 should not change value in the smaller mode,
12701 see PR67028 (a positive C1 can become negative in the
12702 smaller mode, so that the AND does no longer mask the
12703 upper bits). */
12704 && ((WORD_REGISTER_OPERATIONS
12716 {
12722 }
12723 }
12725 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12729 {
12734 }
12736 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12737 (eq (and (lshiftrt X) 1) 0).
12738 Also handle the case where (not X) is expressed using xor. */
12742 {
12752 == HOST_WIDE_INT_1U
12754 {
12755 op0
12760 }
12761 }
12765 /* If we have (compare (ashift FOO N) (const_int C)) and
12766 the high order N bits of FOO (N+1 if an inequality comparison)
12767 are known to be zero, we can do this by comparing FOO with C
12768 shifted right N bits so long as the low-order N bits of C are
12769 zero. */
12781 {
12782 /* We must perform a logical shift, not an arithmetic one,
12783 as we want the top N bits of C to be zero. */
12790 }
12792 /* If we are doing a sign bit comparison, it means we are testing
12793 a particular bit. Convert it to the appropriate AND. */
12796 {
12798 (HOST_WIDE_INT_1U
12803 }
12805 /* If this an equality comparison with zero and we are shifting
12806 the low bit to the sign bit, we can convert this to an AND of the
12807 low-order bit. */
12811 {
12814 }
12818 /* If this is an equality comparison with zero, we can do this
12819 as a logical shift, which might be much simpler. */
12822 {
12827 }
12829 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12830 do the comparison in a narrower mode. */
12840 {
12843 }
12845 /* Likewise if OP0 is a PLUS of a sign extension with a
12846 constant, which is usually represented with the PLUS
12847 between the shifts. */
12859 {
12867 new_const);
12869 }
12871 /* FALLTHROUGH */
12873 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12874 the low order N bits of FOO are known to be zero, we can do this
12875 by comparing FOO with C shifted left N bits so long as no
12876 overflow occurs. Even if the low order N bits of FOO aren't known
12877 to be zero, if the comparison is >= or < we can use the same
12878 optimization and for > or <= by setting all the low
12879 order N bits in the comparison constant. */
12890 {
12891 unsigned HOST_WIDE_INT low_bits
12893 & ((HOST_WIDE_INT_1U
12896 {
12897 /* If the shift was logical, then we must make the condition
12898 unsigned. */
12907 const_op
12912 }
12913 }
12915 /* If we are using this shift to extract just the sign bit, we
12916 can replace this with an LT or GE comparison. */
12921 {
12925 }
12930 }
12933 }
12935 /* Now make any compound operations involved in this comparison. Then,
12936 check for an outmost SUBREG on OP0 that is not doing anything or is
12937 paradoxical. The latter transformation must only be performed when
12938 it is known that the "extra" bits will be the same in op0 and op1 or
12939 that they don't matter. There are three cases to consider:
12941 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12942 care bits and we can assume they have any convenient value. So
12943 making the transformation is safe.
12945 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12946 In this case the upper bits of op0 are undefined. We should not make
12947 the simplification in that case as we do not know the contents of
12948 those bits.
12950 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12951 In that case we know those bits are zeros or ones. We must also be
12952 sure that they are the same as the upper bits of op1.
12954 We can never remove a SUBREG for a non-equality comparison because
12955 the sign bit is in a different place in the underlying object. */
12968 {
12970 {
12971 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12972 implemented. */
12974 {
12977 }
12978 }
12982 {
12987 }
12988 }
12990 /* We now do the opposite procedure: Some machines don't have compare
12991 insns in all modes. If OP0's mode is an integer mode smaller than a
12992 word and we can't do a compare in that mode, see if there is a larger
12993 mode for which we can do the compare. There are a number of cases in
12994 which we can use the wider mode. */
13000 {
13005 {
13008 /* If this is a test for negative, we can make an explicit
13009 test of the sign bit. Test this first so we can use
13010 a paradoxical subreg to extend OP0. */
13014 {
13015 unsigned HOST_WIDE_INT sign
13022 }
13024 /* If the only nonzero bits in OP0 and OP1 are those in the
13025 narrower mode and this is an equality or unsigned comparison,
13026 we can use the wider mode. Similarly for sign-extended
13027 values, in which case it is true for all comparisons. */
13044 {
13045 /* If OP0 is an AND and we don't have an AND in MODE either,
13046 make a new AND in the proper mode. */
13054 else
13055 {
13057 {
13062 }
13063 else
13064 {
13069 }
13071 }
13072 }
13073 }
13074 }
13076 /* We may have changed the comparison operands. Re-canonicalize. */
13078 {
13081 }
13083 /* If this machine only supports a subset of valid comparisons, see if we
13084 can convert an unsupported one into a supported one. */
13091 }
13092 \f
13093 /* Utility function for record_value_for_reg. Count number of
13094 rtxs in X. */
13095 static int
13097 {
13104 {
13124 }
13135 }
13136 \f
13137 /* Utility function for following routine. Called when X is part of a value
13138 being stored into last_set_value. Sets last_set_table_tick
13139 for each register mentioned. Similar to mention_regs in cse.cc */
13141 static void
13143 {
13149 {
13155 {
13158 }
13161 }
13165 {
13166 /* Check for identical subexpressions. If x contains
13167 identical subexpression we only have to traverse one of
13168 them. */
13170 {
13171 /* Note that at this point x1 has already been
13172 processed. */
13176 /* If x0 and x1 are identical then there is no need to
13177 process x0. */
13181 /* If x0 is identical to a subexpression of x1 then while
13182 processing x1, x0 has already been processed. Thus we
13183 are done with x. */
13188 /* If x1 is identical to a subexpression of x0 then we
13189 still have to process the rest of x0. */
13192 {
13195 }
13196 }
13199 }
13203 }
13205 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13206 are saying that the register is clobbered and we no longer know its
13207 value. If INSN is zero, don't update reg_stat[].last_set; this is
13208 only permitted with VALUE also zero and is used to invalidate the
13209 register. */
13211 static void
13213 {
13219 /* If VALUE contains REG and we have a previous value for REG, substitute
13220 the previous value. */
13222 {
13223 rtx tem;
13225 /* Set things up so get_last_value is allowed to see anything set up to
13226 our insn. */
13230 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13231 it isn't going to be useful and will take a lot of time to process,
13232 so just use the CLOBBER. */
13235 {
13241 {
13242 /* If there are two or more occurrences of REG in VALUE,
13243 prevent the value from growing too much. */
13246 }
13249 }
13250 }
13252 /* For each register modified, show we don't know its value, that
13253 we don't know about its bitwise content, that its value has been
13254 updated, and that we don't know the location of the death of the
13255 register. */
13257 {
13269 }
13271 /* Mark registers that are being referenced in this value. */
13275 /* Now update the status of each register being set.
13276 If someone is using this register in this block, set this register
13277 to invalid since we will get confused between the two lives in this
13278 basic block. This makes using this register always invalid. In cse, we
13279 scan the table to invalidate all entries using this register, but this
13280 is too much work for us. */
13283 {
13289 else
13291 }
13293 /* The value being assigned might refer to X (like in "x++;"). In that
13294 case, we must replace it with (clobber (const_int 0)) to prevent
13295 infinite loops. */
13298 {
13302 }
13304 /* For the main register being modified, update the value, the mode, the
13305 nonzero bits, and the number of sign bit copies. */
13310 {
13318 rsp->last_set_sign_bit_copies
13320 }
13321 }
13323 /* Called via note_stores from record_dead_and_set_regs to handle one
13324 SET or CLOBBER in an insn. DATA is the instruction in which the
13325 set is occurring. */
13327 static void
13329 {
13336 {
13340 }
13343 {
13344 /* If we are setting the whole register, we know its value. Otherwise
13345 show that we don't know the value. We can handle a SUBREG if it's
13346 the low part, but we must be careful with paradoxical SUBREGs on
13347 RISC architectures because we cannot strip e.g. an extension around
13348 a load and record the naked load since the RTL middle-end considers
13349 that the upper bits are defined according to LOAD_EXTEND_OP. */
13356 BITS_PER_WORD)
13359 WORD_REGISTER_OPERATIONS
13365 else
13367 }
13369 /* Ignore pushes, they clobber nothing. */
13372 }
13374 /* Update the records of when each REG was most recently set or killed
13375 for the things done by INSN. This is the last thing done in processing
13376 INSN in the combiner loop.
13378 We update reg_stat[], in particular fields last_set, last_set_value,
13379 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13380 last_death, and also the similar information mem_last_set (which insn
13381 most recently modified memory) and last_call_luid (which insn was the
13382 most recent subroutine call). */
13384 static void
13386 {
13387 rtx link;
13391 {
13394 {
13399 {
13404 }
13405 }
13408 }
13411 {
13412 HARD_REG_SET callee_clobbers
13414 hard_reg_set_iterator hrsi;
13416 {
13419 /* ??? We could try to preserve some information from the last
13420 set of register I if the call doesn't actually clobber
13421 (reg:last_set_mode I), which might be true for ABIs with
13422 partial clobbers. However, it would be difficult to
13423 update last_set_nonzero_bits and last_sign_bit_copies
13424 to account for the part of I that actually was clobbered.
13425 It wouldn't help much anyway, since we rarely see this
13426 situation before RA. */
13436 }
13440 /* We can't combine into a call pattern. Remember, though, that
13441 the return value register is set at this LUID. We could
13442 still replace a register with the return value from the
13443 wrong subroutine call! */
13445 }
13446 else
13448 }
13450 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13451 register present in the SUBREG, so for each such SUBREG go back and
13452 adjust nonzero and sign bit information of the registers that are
13453 known to have some zero/sign bits set.
13455 This is needed because when combine blows the SUBREGs away, the
13456 information on zero/sign bits is lost and further combines can be
13457 missed because of that. */
13459 static void
13461 {
13463 rtx set;
13471 {
13480 {
13483 }
13487 {
13490 }
13493 {
13496 }
13497 else
13499 }
13500 }
13502 /* Check if X, a register, is known to contain a value already
13503 truncated to MODE. In this case we can use a subreg to refer to
13504 the truncated value even though in the generic case we would need
13505 an explicit truncation. */
13507 static bool
13509 {
13521 }
13523 /* If X is a hard reg or a subreg record the mode that the register is
13524 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13525 able to turn a truncate into a subreg using this information. Return true
13526 if traversing X is complete. */
13528 static bool
13530 {
13531 machine_mode truncated_mode;
13535 {
13547 }
13548 /* ??? For hard-regs we now record everything. We might be able to
13549 optimize this using last_set_mode. */
13552 else
13559 {
13562 }
13565 }
13567 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13568 the modes they are used in. This can help truning TRUNCATEs into
13569 SUBREGs. */
13571 static void
13573 {
13578 }
13580 /* Scan X for promoted SUBREGs. For each one found,
13581 note what it implies to the registers used in it. */
13583 static void
13585 {
13590 else
13591 {
13597 {
13607 }
13608 }
13609 }
13610 \f
13611 /* Verify that all the registers and memory references mentioned in *LOC are
13612 still valid. *LOC was part of a value set in INSN when label_tick was
13613 equal to TICK. Return false if some are not. If REPLACE is true, replace
13614 the invalid references with (clobber (const_int 0)) and return true. This
13615 replacement is useful because we often can get useful information about
13616 the form of a value (e.g., if it was produced by a shift that always
13617 produces -1 or 0) even though we don't know exactly what registers it
13618 was produced from. */
13620 static bool
13622 {
13629 {
13635 {
13638 /* If this is a pseudo-register that was only set once and not
13639 live at the beginning of the function, it is always valid. */
13643 && (!REGNO_REG_SET_P
13645 regno)))
13647 {
13651 }
13652 }
13655 }
13656 /* If this is a memory reference, make sure that there were no stores after
13657 it that might have clobbered the value. We don't have alias info, so we
13658 assume any store invalidates it. Moreover, we only have local UIDs, so
13659 we also assume that there were stores in the intervening basic blocks. */
13662 {
13666 }
13669 {
13671 {
13672 /* Check for identical subexpressions. If x contains
13673 identical subexpression we only have to traverse one of
13674 them. */
13676 {
13677 /* Note that at this point x0 has already been checked
13678 and found valid. */
13682 /* If x0 and x1 are identical then x is also valid. */
13686 /* If x1 is identical to a subexpression of x0 then
13687 while checking x0, x1 has already been checked. Thus
13688 it is valid and so as x. */
13693 /* If x0 is identical to a subexpression of x1 then x is
13694 valid iff the rest of x1 is valid. */
13697 return
13701 }
13705 }
13711 }
13713 /* If we haven't found a reason for it to be invalid, it is valid. */
13715 }
13717 /* Get the last value assigned to X, if known. Some registers
13718 in the value may be replaced with (clobber (const_int 0)) if their value
13719 is known longer known reliably. */
13721 static rtx
13723 {
13725 rtx value;
13728 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13729 then convert it to the desired mode. If this is a paradoxical SUBREG,
13730 we cannot predict what values the "extra" bits might have. */
13744 /* If we don't have a value, or if it isn't for this basic block and
13745 it's either a hard register, set more than once, or it's a live
13746 at the beginning of the function, return 0.
13748 Because if it's not live at the beginning of the function then the reg
13749 is always set before being used (is never used without being set).
13750 And, if it's set only once, and it's always set before use, then all
13751 uses must have the same last value, even if it's not from this basic
13752 block. */
13759 || REGNO_REG_SET_P
13763 /* If the value was set in a later insn than the ones we are processing,
13764 we can't use it even if the register was only set once. */
13769 /* If fewer bits were set than what we are asked for now, we cannot use
13770 the value. */
13775 /* If the value has all its registers valid, return it. */
13780 /* Otherwise, make a copy and replace any invalid register with
13781 (clobber (const_int 0)). If that fails for some reason, return 0. */
13789 }
13790 \f
13791 /* Define three variables used for communication between the following
13792 routines. */
13796 rtx reg_dead_reg;
13798 /* Function called via note_stores from reg_dead_at_p.
13800 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13801 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13803 static void
13805 {
13815 }
13817 /* Return true if REG is known to be dead at INSN.
13819 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13820 referencing REG, it is dead. If we hit a SET referencing REG, it is
13821 live. Otherwise, see if it is live or dead at the start of the basic
13822 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13823 must be assumed to be always live. */
13825 static bool
13827 {
13828 basic_block block;
13831 /* Set variables for reg_dead_at_p_1. */
13838 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13839 we allow the machine description to decide whether use-and-clobber
13840 patterns are OK. */
13842 {
13846 }
13848 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13849 beginning of basic block. */
13852 {
13854 {
13864 }
13870 }
13872 /* Look at live-in sets for the basic block that we were in. */
13878 }
13879 \f
13880 /* Note hard registers in X that are used. */
13882 static void
13884 {
13890 {
13894 CASE_CONST_ANY:
13902 /* If we are clobbering a MEM, mark any hard registers inside the
13903 address as used. */
13910 /* A hard reg in a wide mode may really be multiple registers.
13911 If so, mark all of them just like the first. */
13913 {
13914 /* None of this applies to the stack, frame or arg pointers. */
13916 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13924 }
13928 {
13929 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13930 the address. */
13942 }
13947 }
13949 /* Recursively scan the operands of this expression. */
13951 {
13955 {
13959 {
13964 }
13965 }
13966 }
13967 }
13968 \f
13969 /* Remove register number REGNO from the dead registers list of INSN.
13971 Return the note used to record the death, if there was one. */
13973 rtx
13975 {
13982 }
13984 /* For each register (hardware or pseudo) used within expression X, if its
13985 death is in an instruction with luid between FROM_LUID (inclusive) and
13986 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13987 list headed by PNOTES.
13989 That said, don't move registers killed by maybe_kill_insn.
13991 This is done when X is being merged by combination into TO_INSN. These
13992 notes will then be distributed as needed. */
13994 static void
13997 {
14003 {
14007 /* If we do not know where the register died, it may still die between
14008 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14010 {
14015 {
14017 {
14021 }
14024 }
14025 }
14027 /* Don't move the register if it gets killed in between from and to. */
14036 {
14039 /* It is possible for the call above to return 0. This can occur
14040 when last_death points to I2 or I1 that we combined with.
14041 In that case make a new note.
14043 We must also check for the case where X is a hard register
14044 and NOTE is a death note for a range of hard registers
14045 including X. In that case, we must put REG_DEAD notes for
14046 the remaining registers in place of NOTE. */
14050 {
14059 }
14061 /* If we didn't find any note, or if we found a REG_DEAD note that
14062 covers only part of the given reg, and we have a multi-reg hard
14063 register, then to be safe we must check for REG_DEAD notes
14064 for each register other than the first. They could have
14065 their own REG_DEAD notes lying around. */
14072 {
14079 else
14085 }
14088 {
14091 }
14092 else
14094 }
14097 }
14100 {
14105 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14106 that accesses one word of a multi-word item, some
14107 piece of everything register in the expression is used by
14108 this insn, so remove any old death. */
14109 /* ??? So why do we test for equality of the sizes? */
14115 {
14118 }
14120 /* If this is some other SUBREG, we know it replaces the entire
14121 value, so use that as the destination. */
14125 /* If this is a MEM, adjust deaths of anything used in the address.
14126 For a REG (the only other possibility), the entire value is
14127 being replaced so the old value is not used in this insn. */
14133 }
14142 {
14144 {
14149 }
14152 }
14153 }
14154 \f
14155 /* Return true if X is the target of a bit-field assignment in BODY, the
14156 pattern of an insn. X must be a REG. */
14158 static bool
14160 {
14164 {
14166 rtx target;
14173 else
14190 }
14198 }
14199 \f
14200 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14201 as appropriate. I3 and I2 are the insns resulting from the combination
14202 insns including FROM (I2 may be zero).
14204 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14205 not need REG_DEAD notes because they are being substituted for. This
14206 saves searching in the most common cases.
14208 Each note in the list is either ignored or placed on some insns, depending
14209 on the type of note. */
14211 static void
14214 {
14216 rtx tem_note;
14220 {
14225 {
14228 /* Doesn't matter much where we put this, as long as it's somewhere.
14229 It is preferable to keep these notes on branches, which is most
14230 likely to be i3. */
14237 else
14238 {
14241 }
14245 {
14246 /* The landing pad handling needs to be kept in sync with the
14247 prerequisite checking in try_combine. */
14249 /* A REG_EH_REGION note transfering control can only ever come
14250 from i3. */
14253 /* We are making sure there is a single effective REG_EH_REGION
14254 note and it's valid to put it on i3. */
14257 /* Throw away stray notes on insns that can never throw or
14258 make a nonlocal goto. */
14259 ;
14260 else
14261 {
14264 else
14265 {
14267 /* If i3 can still trap preserve the note, otherwise we've
14268 combined things such that we can now prove that the
14269 instructions can't trap. Drop the note in this case. */
14272 }
14273 }
14275 }
14278 /* ??? How to distribute between i3-i1. Assume i3 contains the
14279 entire adjustment. Assert i3 contains at least some adjust. */
14281 {
14283 /* fixup_args_size_notes looks at REG_NORETURN note,
14284 so ensure the note is placed there first. */
14286 {
14290 {
14296 }
14297 }
14299 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14300 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14303 && !ACCUMULATE_OUTGOING_ARGS
14305 }
14314 /* These notes must remain with the call. It should not be
14315 possible for both I2 and I3 to be a call. */
14318 else
14319 {
14322 }
14326 /* Any clobbers for i3 may still exist, and so we must process
14327 REG_UNUSED notes from that insn.
14329 Any clobbers from i2 or i1 can only exist if they were added by
14330 recog_for_combine. In that case, recog_for_combine created the
14331 necessary REG_UNUSED notes. Trying to keep any original
14332 REG_UNUSED notes from these insns can cause incorrect output
14333 if it is for the same register as the original i3 dest.
14334 In that case, we will notice that the register is set in i3,
14335 and then add a REG_UNUSED note for the destination of i3, which
14336 is wrong. However, it is possible to have REG_UNUSED notes from
14337 i2 or i1 for register which were both used and clobbered, so
14338 we keep notes from i2 or i1 if they will turn into REG_DEAD
14339 notes. */
14341 /* If this register is set or clobbered between FROM_INSN and I3,
14342 we should not create a note for it. */
14346 /* If this register is set or clobbered in I3, put the note there
14347 unless there is one already. */
14349 {
14357 }
14358 /* Otherwise, if this register is used by I3, then this register
14359 now dies here, so we must put a REG_DEAD note here unless there
14360 is one already. */
14366 {
14369 }
14371 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14372 but we can't tell which at this point. We must reset any
14373 expectations we had about the value that was previously
14374 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14375 and, if appropriate, restore its previous value, but we
14376 don't have enough information for that at this point. */
14377 else
14378 {
14381 /* Otherwise, if this register is now referenced in i2
14382 then the register used to be modified in one of the
14383 original insns. If it was i3 (say, in an unused
14384 parallel), it's now completely gone, so the note can
14385 be discarded. But if it was modified in i2, i1 or i0
14386 and we still reference it in i2, then we're
14387 referencing the previous value, and since the
14388 register was modified and REG_UNUSED, we know that
14389 the previous value is now dead. So, if we only
14390 reference the register in i2, we change the note to
14391 REG_DEAD, to reflect the previous value. However, if
14392 we're also setting or clobbering the register as
14393 scratch, we know (because the register was not
14394 referenced in i3) that it's unused, just as it was
14395 unused before, and we place the note in i2. */
14398 {
14407 }
14408 }
14415 /* These notes say something about results of an insn. We can
14416 only support them if they used to be on I3 in which case they
14417 remain on I3. Otherwise they are ignored.
14419 If the note refers to an expression that is not a constant, we
14420 must also ignore the note since we cannot tell whether the
14421 equivalence is still true. It might be possible to do
14422 slightly better than this (we only have a problem if I2DEST
14423 or I1DEST is present in the expression), but it doesn't
14424 seem worth the trouble. */
14432 /* These notes say something about how a register is used. They must
14433 be present on any use of the register in I2 or I3. */
14438 {
14441 else
14443 }
14448 /* This can show up in several ways -- either directly in the
14449 pattern, or hidden off in the constant pool with (or without?)
14450 a REG_EQUAL note. */
14451 /* ??? Ignore the without-reg_equal-note problem for now. */
14463 {
14466 else
14468 }
14470 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14471 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14472 there. */
14477 {
14484 }
14490 {
14498 }
14502 /* This note says something about the value of a register prior
14503 to the execution of an insn. It is too much trouble to see
14504 if the note is still correct in all situations. It is better
14505 to simply delete it. */
14509 /* If we replaced the right hand side of FROM_INSN with a
14510 REG_EQUAL note, the original use of the dying register
14511 will not have been combined into I3 and I2. In such cases,
14512 FROM_INSN is guaranteed to be the first of the combined
14513 instructions, so we simply need to search back before
14514 FROM_INSN for the previous use or set of this register,
14515 then alter the notes there appropriately.
14517 If the register is used as an input in I3, it dies there.
14518 Similarly for I2, if it is nonzero and adjacent to I3.
14520 If the register is not used as an input in either I3 or I2
14521 and it is not one of the registers we were supposed to eliminate,
14522 there are two possibilities. We might have a non-adjacent I2
14523 or we might have somehow eliminated an additional register
14524 from a computation. For example, we might have had A & B where
14525 we discover that B will always be zero. In this case we will
14526 eliminate the reference to A.
14528 In both cases, we must search to see if we can find a previous
14529 use of A and put the death note there. */
14535 else
14536 {
14542 {
14543 /* If the new I2 sets the same register that is marked
14544 dead in the note, we do not in general know where to
14545 put the note. One important case we _can_ handle is
14546 when the note comes from I3. */
14549 else
14551 }
14558 && !(i2mod
14560 i2mod_old_rhs)))
14565 }
14568 {
14572 {
14574 {
14578 }
14580 /* If the register is being set at TEM_INSN, see if that is all
14581 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14582 into a REG_UNUSED note instead. Don't delete sets to
14583 global register vars. */
14587 {
14597 ;
14599 /* Verify that it was the set, and not a clobber that
14600 modified the register.
14602 If we cannot delete the setter due to side
14603 effects, mark the user with an UNUSED note instead
14604 of deleting it. */
14608 {
14609 /* Move the notes and links of TEM_INSN elsewhere.
14610 This might delete other dead insns recursively.
14611 First set the pattern to something that won't use
14612 any register. */
14630 }
14631 else
14632 {
14635 /* If there isn't already a REG_UNUSED note, put one
14636 here. Do not place a REG_DEAD note, even if
14637 the register is also used here; that would not
14638 match the algorithm used in lifetime analysis
14639 and can cause the consistency check in the
14640 scheduler to fail. */
14645 }
14646 }
14650 {
14653 /* If we are doing a 3->2 combination, and we have a
14654 register which formerly died in i3 and was not used
14655 by i2, which now no longer dies in i3 and is used in
14656 i2 but does not die in i2, and place is between i2
14657 and i3, then we may need to move a link from place to
14658 i2. */
14660 && from_insn
14663 {
14667 }
14669 }
14673 }
14675 }
14677 /* If the register is set or already dead at PLACE, we needn't do
14678 anything with this note if it is still a REG_DEAD note.
14679 We check here if it is set at all, not if is it totally replaced,
14680 which is what `dead_or_set_p' checks, so also check for it being
14681 set partially. */
14684 {
14690 {
14691 /* Unless the register previously died in PLACE, clear
14692 last_death. [I no longer understand why this is
14693 being done.] */
14697 }
14698 else
14701 /* If this is a death note for a hard reg that is occupying
14702 multiple registers, ensure that we are still using all
14703 parts of the object. If we find a piece of the object
14704 that is unused, we must arrange for an appropriate REG_DEAD
14705 note to be added for it. However, we can't just emit a USE
14706 and tag the note to it, since the register might actually
14707 be dead; so we recourse, and the recursive call then finds
14708 the previous insn that used this register. */
14711 {
14720 {
14723 }
14726 {
14727 /* Put only REG_DEAD notes for pieces that are
14728 not already dead or set. */
14732 {
14739 {
14741 NULL_RTX);
14745 NULL_RTX);
14746 }
14751 {
14753 {
14757 }
14761 {
14764 }
14765 }
14766 }
14769 }
14770 }
14771 }
14775 /* Any other notes should not be present at this point in the
14776 compilation. */
14778 }
14781 {
14785 /* Set added_notes_insn to the earliest insn we added a note to. */
14789 }
14792 {
14795 /* Set added_notes_insn to the earliest insn we added a note to. */
14799 }
14800 }
14801 }
14802 \f
14803 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14804 I3, I2, and I1 to new locations. This is also called to add a link
14805 pointing at I3 when I3's destination is changed. */
14807 static void
14809 {
14813 {
14820 /* If the insn that this link points to is a NOTE, ignore it. */
14829 {
14832 {
14848 }
14851 }
14852 else
14865 /* A LOG_LINK is defined as being placed on the first insn that uses
14866 a register and points to the insn that sets the register. Start
14867 searching at the next insn after the target of the link and stop
14868 when we reach a set of the register or the end of the basic block.
14870 Note that this correctly handles the link that used to point from
14871 I3 to I2. Also note that not much searching is typically done here
14872 since most links don't point very far away. */
14881 {
14885 }
14888 {
14891 }
14895 /* If we found a place to put the link, place it there unless there
14896 is already a link to the same insn as LINK at that point. */
14899 {
14907 {
14911 /* Set added_links_insn to the earliest insn we added a
14912 link to. */
14916 }
14917 }
14918 }
14919 }
14920 \f
14921 /* Check for any register or memory mentioned in EQUIV that is not
14922 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14923 of EXPR where some registers may have been replaced by constants. */
14925 static bool
14927 {
14930 {
14935 }
14937 }
14938 \f
14939 DEBUG_FUNCTION void
14941 {
14942 fprintf
14944 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14946 }
14948 void
14950 {
14951 fprintf
14953 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14955 }
14956 \f
14957 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
14958 the reg-to-reg copy can usefully combine with later instructions, but we
14959 do not want to combine the hard reg into later instructions, for that
14960 restricts register allocation. */
14961 static void
14963 {
14964 basic_block bb;
14967 {
14971 {
14994 }
14995 }
14996 }
14998 /* Try combining insns through substitution. */
14999 static void
15001 {
15011 bool rebuild_jump_labels_after_combine
15014 /* Combining insns may have turned an indirect jump into a
15015 direct jump. Rebuild the JUMP_LABEL fields of jumping
15016 instructions. */
15018 {
15025 }
15028 }
15033 {
15043 };
15046 {
15050 {}
15052 /* opt_pass methods: */
15055 {
15058 }
15064 rtl_opt_pass *
15066 {
15068 }