1 2024-03-08 Martin Jambor <mjambor@suse.cz>
4 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
5 id->killed_new_ssa_names.
7 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
10 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
11 for non-reload pseudo too.
13 2024-03-08 David Faust <david.faust@oracle.com>
15 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
16 not attempt inline expansion if size is above threshold.
17 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
18 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
21 2024-03-08 Richard Biener <rguenther@suse.de>
23 PR tree-optimization/114269
24 PR tree-optimization/114074
25 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
26 in the third CASE_CONVERT case as well.
27 (chrec_fold_multiply): Handle sign-conversions from unsigned
28 by performing the operation in the unsigned type.
30 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
32 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
33 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
35 2024-03-08 Jakub Jelinek <jakub@redhat.com>
37 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
38 asm_noperands < 0 means it is not asm goto too.
40 2024-03-08 Jakub Jelinek <jakub@redhat.com>
43 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
45 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
46 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
47 ix86_noreturn_no_callee_saved_registers is enabled.
48 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
50 2024-03-08 Jakub Jelinek <jakub@redhat.com>
53 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
54 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
56 2024-03-08 demin.han <demin.han@starfivetech.com>
59 * config/riscv/riscv-vector-costs.cc: Fix ICE
61 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
63 * fwprop.cc (forward_propagate_into): Return false for volatile set
66 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
69 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
70 (aarch64_expand_cpymem): Emit single load/store only.
71 (aarch64_set_one_block): Emit single stores only.
73 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
76 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
79 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
81 * doc/cppopts.texi: Remove incorrect claim about -dD not
82 outputting predefined macros.
84 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
87 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
88 and simplify else if with else.
90 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
92 * system.h: Include safe-ctype.h after C++ standard headers.
94 2024-03-07 Jakub Jelinek <jakub@redhat.com>
96 PR rtl-optimization/110079
97 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
100 2024-03-07 Jakub Jelinek <jakub@redhat.com>
103 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
104 if val is not HOST_WIDE_INT_MIN or if mode has exactly
105 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
108 2024-03-07 Jakub Jelinek <jakub@redhat.com>
111 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
112 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
115 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
117 * config.gcc: Add a case for loongarch*-*-linux-musl*.
118 * config/loongarch/linux.h: Disable the multilib-compatible
119 treatment for *musl* targets.
120 * config/loongarch/musl.h: New file.
122 2024-03-07 Jakub Jelinek <jakub@redhat.com>
124 PR tree-optimization/114009
125 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
126 argument even for GENERIC, not just for GIMPLE.
127 * match.pd (a * !a -> 0): New simplifications.
129 2024-03-07 demin.han <demin.han@starfivetech.com>
131 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
132 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
133 (expand_vec_cmp_float): Adapt arguments
135 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
138 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
139 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
140 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
141 (<plusminus:insn>v2qi3): Enable for optimize_size instead
142 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
143 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
144 (<any_shift:insn>v2qi3): Enable for optimize_size instead
145 of optimize_function_for_size_p.
147 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
151 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
153 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
155 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
156 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
158 (costs::add_stmt_cost): Also adjust cost for statements without
160 * config/riscv/riscv-vector-costs.h: Define zero constant.
162 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
165 * config/arm/arm.md (NOCOND): Improve comment.
166 (arm_rev*) Add predicable.
167 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
170 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
174 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
175 operands when the comparison operand is the same as the false
178 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
180 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
181 Eliminate common code and use generic code instead.
183 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
185 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
188 2024-03-06 Richard Biener <rguenther@suse.de>
190 PR tree-optimization/114239
191 * tree-vect-loop.cc (vect_get_vect_def): Remove.
192 (vect_create_epilog_for_reduction): The passed in stmt_info
193 should now be the live stmt that produces the scalar reduction
194 result. Revert PR114192 fix. Base reduction info off
195 info_for_reduction. Remove special handling of
196 early-break/peeled, restore original vector def gathering.
197 Make sure to pick the correct exit PHIs.
198 (vectorizable_live_operation): Pass in the proper stmt_info
199 for early break exits.
201 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
203 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
204 out-of-class definitions of static constants.
206 2024-03-06 Richard Biener <rguenther@suse.de>
208 PR tree-optimization/114249
209 * tree-vect-slp.cc (vect_build_slp_instance): Move making
210 a BB reduction lane number even ...
211 (vect_slp_check_for_roots): ... here to avoid leaking
214 2024-03-06 Richard Biener <rguenther@suse.de>
216 PR tree-optimization/114246
217 * tree-ssa-dse.cc (increment_start_addr): Strip useless
218 type conversions from the adjusted address.
220 2024-03-06 Jakub Jelinek <jakub@redhat.com>
222 PR rtl-optimization/114190
223 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
224 Call df_remove_problem for df_note before calling df_analyze.
226 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
227 Indu Bhagat <indu.bhagat@oracle.com>
230 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
231 in the correct order of the dimensions.
232 (gen_ctf_subrange_type): Refactor out handling of
233 DW_TAG_subrange_type DIE to here.
235 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
238 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
240 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
242 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
244 * config/aarch64/aarch64-sme.md
245 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
246 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
247 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
248 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
249 (early_ra::maybe_convert_to_strided_access): Remove support for
250 strided LUTI2 and LUTI4.
252 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
255 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
256 low_register_operand.
258 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
260 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
261 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
262 to "X = Y, X o= CST".
264 2024-03-05 Xi Ruoyao <xry111@xry111.site>
266 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
267 s9 as an alias of r22.
269 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
271 * config/avr/avr-protos.h (avr_out_insv): New proto.
272 * config/avr/avr.cc (avr_out_insv): New function.
273 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
274 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
275 * config/avr/avr.md (define_attr "adjust_len") Add insv.
276 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
277 Add constraint alternative where the 3rd operand is a power
278 of 2, and the source register may differ from the destination.
279 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
280 instructions. Set attr "length" to "insv".
281 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
283 2024-03-05 Richard Biener <rguenther@suse.de>
285 PR tree-optimization/114231
286 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
287 processing a BB SLP root.
289 2024-03-05 Jakub Jelinek <jakub@redhat.com>
291 PR rtl-optimization/114211
292 * lower-subreg.cc (resolve_simple_move): For double-word
293 rotates by BITS_PER_WORD if there is overlap between source
294 and destination use a temporary.
296 2024-03-05 Jakub Jelinek <jakub@redhat.com>
299 * gimple-lower-bitint.cc: Include stor-layout.h.
300 (mergeable_op): Return true for BIT_FIELD_REF.
301 (struct bitint_large_huge): Declare handle_bit_field_ref method.
302 (bitint_large_huge::handle_bit_field_ref): New method.
303 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
305 2024-03-05 Jakub Jelinek <jakub@redhat.com>
308 * config/i386/i386.h (enum call_saved_registers_type): Add
309 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
310 * config/i386/i386-options.cc (ix86_set_func_type): Remove
311 has_no_callee_saved_registers variable, add no_callee_saved_registers
312 instead, initialize it depending on whether it is
313 no_callee_saved_registers function or not. Don't set it if
314 no_caller_saved_registers attribute is present. Adjust users.
315 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
316 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
317 TYPE_NO_CALLEE_SAVED_REGISTERS.
318 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
320 2024-03-05 Pan Li <pan2.li@intel.com>
322 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
323 mode_size related code.
325 2024-03-05 Patrick Palka <ppalka@redhat.com>
327 * doc/invoke.texi (-Wno-global-module): Document.
329 2024-03-04 David Faust <david.faust@oracle.com>
331 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
332 * config/bpf/bpf.cc (bpf_expand_setmem): New.
333 * config/bpf/bpf.md (setmemdi): New define_expand.
335 2024-03-04 Jakub Jelinek <jakub@redhat.com>
337 PR rtl-optimization/113010
338 * combine.cc (simplify_comparison): Guard the
339 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
340 and initialize inner_mode.
342 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
344 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
346 (VMLALDAVXQ): Remove iterator.
347 (VMLALDAVXQ_P): Likewise.
348 (VMLALDAVAXQ): Likewise.
349 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
350 mode iterator attribute with V4BI mode.
351 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
352 VMLALDAVAXQ_U): Remove unused unspecs.
354 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
356 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
357 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
359 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
360 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
361 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
362 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
363 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
364 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
365 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
366 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
367 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
368 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
370 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
372 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
373 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
374 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
375 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
376 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
377 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
378 (arm_vcx1q<a>v16qi): Likewise.
379 (arm_vcx1qav16qi): Likewise.
380 (arm_vcx1qv16qi): Likewise.
381 (arm_vcx2q<a>_p_v16qi): Likewise.
382 (arm_vcx2q<a>v16qi): Likewise.
383 (arm_vcx2qav16qi): Likewise.
384 (arm_vcx2qv16qi): Likewise.
385 (arm_vcx3q<a>_p_v16qi): Likewise.
386 (arm_vcx3q<a>v16qi): Likewise.
387 (arm_vcx3qav16qi): Likewise.
388 (arm_vcx3qv16qi): Likewise.
389 (@mve_<mve_insn>q_<supf><mode>): Likewise.
390 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
391 (@mve_<mve_insn>q_<supf>v4si): Likewise.
392 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
393 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
394 (@mve_<mve_insn>q_f<mode>): Likewise.
395 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
396 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
397 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
398 (@mve_<mve_insn>q_m_f<mode>): Likewise.
399 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
400 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
401 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
402 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
403 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
404 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
405 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
406 (mve_v<absneg_str>q_f<mode>): Likewise.
407 (mve_<mve_addsubmul>q<mode>): Likewise.
408 (mve_<mve_addsubmul>q_f<mode>): Likewise.
409 (mve_vadciq_<supf>v4si): Likewise.
410 (mve_vadciq_m_<supf>v4si): Likewise.
411 (mve_vadcq_<supf>v4si): Likewise.
412 (mve_vadcq_m_<supf>v4si): Likewise.
413 (mve_vandq_<supf><mode>): Likewise.
414 (mve_vandq_f<mode>): Likewise.
415 (mve_vandq_m_<supf><mode>): Likewise.
416 (mve_vandq_m_f<mode>): Likewise.
417 (mve_vandq_s<mode>): Likewise.
418 (mve_vandq_u<mode>): Likewise.
419 (mve_vbicq_<supf><mode>): Likewise.
420 (mve_vbicq_f<mode>): Likewise.
421 (mve_vbicq_m_<supf><mode>): Likewise.
422 (mve_vbicq_m_f<mode>): Likewise.
423 (mve_vbicq_m_n_<supf><mode>): Likewise.
424 (mve_vbicq_n_<supf><mode>): Likewise.
425 (mve_vbicq_s<mode>): Likewise.
426 (mve_vbicq_u<mode>): Likewise.
427 (@mve_vclzq_s<mode>): Likewise.
428 (mve_vclzq_u<mode>): Likewise.
429 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
430 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
431 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
432 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
433 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
434 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
435 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
436 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
437 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
438 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
439 (mve_vcvtaq_<supf><mode>): Likewise.
440 (mve_vcvtaq_m_<supf><mode>): Likewise.
441 (mve_vcvtbq_f16_f32v8hf): Likewise.
442 (mve_vcvtbq_f32_f16v4sf): Likewise.
443 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
444 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
445 (mve_vcvtmq_<supf><mode>): Likewise.
446 (mve_vcvtmq_m_<supf><mode>): Likewise.
447 (mve_vcvtnq_<supf><mode>): Likewise.
448 (mve_vcvtnq_m_<supf><mode>): Likewise.
449 (mve_vcvtpq_<supf><mode>): Likewise.
450 (mve_vcvtpq_m_<supf><mode>): Likewise.
451 (mve_vcvtq_from_f_<supf><mode>): Likewise.
452 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
453 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
454 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
455 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
456 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
457 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
458 (mve_vcvtq_to_f_<supf><mode>): Likewise.
459 (mve_vcvttq_f16_f32v8hf): Likewise.
460 (mve_vcvttq_f32_f16v4sf): Likewise.
461 (mve_vcvttq_m_f16_f32v8hf): Likewise.
462 (mve_vcvttq_m_f32_f16v4sf): Likewise.
463 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
464 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
465 (mve_veorq_s><mode>): Likewise.
466 (mve_veorq_u><mode>): Likewise.
467 (mve_veorq_f<mode>): Likewise.
468 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
469 (mve_vidupq_u<mode>_insn): Likewise.
470 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
471 (mve_viwdupq_wb_u<mode>_insn): Likewise.
472 (mve_vldrbq_<supf><mode>): Likewise.
473 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
474 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
475 (mve_vldrbq_z_<supf><mode>): Likewise.
476 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
477 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
478 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
479 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
480 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
481 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
482 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
483 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
484 (mve_vldrhq_<supf><mode>): Likewise.
485 (mve_vldrhq_fv8hf): Likewise.
486 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
487 (mve_vldrhq_gather_offset_fv8hf): Likewise.
488 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
489 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
490 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
491 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
492 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
493 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
494 (mve_vldrhq_z_<supf><mode>): Likewise.
495 (mve_vldrhq_z_fv8hf): Likewise.
496 (mve_vldrwq_<supf>v4si): Likewise.
497 (mve_vldrwq_fv4sf): Likewise.
498 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
499 (mve_vldrwq_gather_base_fv4sf): Likewise.
500 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
501 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
502 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
503 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
504 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
505 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
506 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
507 (mve_vldrwq_gather_offset_fv4sf): Likewise.
508 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
509 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
510 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
511 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
512 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
513 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
514 (mve_vldrwq_z_<supf>v4si): Likewise.
515 (mve_vldrwq_z_fv4sf): Likewise.
516 (mve_vmvnq_s<mode>): Likewise.
517 (mve_vmvnq_u<mode>): Likewise.
518 (mve_vornq_<supf><mode>): Likewise.
519 (mve_vornq_f<mode>): Likewise.
520 (mve_vornq_m_<supf><mode>): Likewise.
521 (mve_vornq_m_f<mode>): Likewise.
522 (mve_vornq_s<mode>): Likewise.
523 (mve_vornq_u<mode>): Likewise.
524 (mve_vorrq_<supf><mode>): Likewise.
525 (mve_vorrq_f<mode>): Likewise.
526 (mve_vorrq_m_<supf><mode>): Likewise.
527 (mve_vorrq_m_f<mode>): Likewise.
528 (mve_vorrq_m_n_<supf><mode>): Likewise.
529 (mve_vorrq_n_<supf><mode>): Likewise.
530 (mve_vorrq_s<mode>): Likewise.
531 (mve_vorrq_s<mode>): Likewise.
532 (mve_vsbciq_<supf>v4si): Likewise.
533 (mve_vsbciq_m_<supf>v4si): Likewise.
534 (mve_vsbcq_<supf>v4si): Likewise.
535 (mve_vsbcq_m_<supf>v4si): Likewise.
536 (mve_vshlcq_<supf><mode>): Likewise.
537 (mve_vshlcq_m_<supf><mode>): Likewise.
538 (mve_vshrq_m_n_<supf><mode>): Likewise.
539 (mve_vshrq_n_<supf><mode>): Likewise.
540 (mve_vstrbq_<supf><mode>): Likewise.
541 (mve_vstrbq_p_<supf><mode>): Likewise.
542 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
543 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
544 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
545 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
546 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
547 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
548 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
549 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
550 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
551 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
552 (mve_vstrhq_<supf><mode>): Likewise.
553 (mve_vstrhq_fv8hf): Likewise.
554 (mve_vstrhq_p_<supf><mode>): Likewise.
555 (mve_vstrhq_p_fv8hf): Likewise.
556 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
557 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
558 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
559 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
560 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
561 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
562 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
563 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
564 (mve_vstrwq_<supf>v4si): Likewise.
565 (mve_vstrwq_fv4sf): Likewise.
566 (mve_vstrwq_p_<supf>v4si): Likewise.
567 (mve_vstrwq_p_fv4sf): Likewise.
568 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
569 (mve_vstrwq_scatter_base_fv4sf): Likewise.
570 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
571 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
572 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
573 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
574 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
575 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
576 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
577 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
578 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
579 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
580 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
581 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
582 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
583 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
585 2024-03-04 Marek Polacek <polacek@redhat.com>
587 * doc/extend.texi: Update [[gnu::no_dangling]].
589 2024-03-04 Andrew Stubbs <ams@baylibre.com>
591 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
592 * expr.cc (store_constructor): Likewise.
593 (do_store_flag): Likewise.
595 2024-03-04 Mark Wielaard <mark@klomp.org>
597 * common.opt.urls: Regenerate.
598 * config/avr/avr.opt.urls: Likewise.
599 * config/i386/i386.opt.urls: Likewise.
600 * config/pru/pru.opt.urls: Likewise.
601 * config/riscv/riscv.opt.urls: Likewise.
602 * config/rs6000/rs6000.opt.urls: Likewise.
604 2024-03-04 Richard Biener <rguenther@suse.de>
606 PR tree-optimization/114197
607 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
608 there are volatile bitfield accesses.
609 (pass_if_conversion::execute): Throw away result if the
610 if-converted and original loops are not nested as expected.
612 2024-03-04 Richard Biener <rguenther@suse.de>
614 PR tree-optimization/114164
615 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
616 the code generated for mask argument setup is not supported.
618 2024-03-04 Richard Biener <rguenther@suse.de>
620 PR tree-optimization/114203
621 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
622 adjustment before making the result defined at zero.
624 2024-03-04 Richard Biener <rguenther@suse.de>
626 PR tree-optimization/114192
627 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
628 appropriate def for the live out stmt in case of an alternate
631 2024-03-04 Jakub Jelinek <jakub@redhat.com>
634 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
635 unshare_expr when creating a MEM_REF from MEM_REF.
636 (bitint_large_huge::lower_stmt): Call unshare_expr.
638 2024-03-04 Jakub Jelinek <jakub@redhat.com>
641 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
642 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
645 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
648 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
649 lowpart_subreg to perform type conversion, to avoid confusion
650 over the offset to use in the call to simplify_reg_subreg.
652 2024-03-03 Greg McGary <gkm@rivosinc.com>
654 PR rtl-optimization/113010
655 * combine.cc (simplify_comparison): Simplify a SUBREG on
656 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
659 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
661 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
662 Use bool in place of int for boolean logic (if possible).
663 Move declarations to definitions (if possible).
664 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
665 * config/avr/avr-dimode.md: Same.
666 * config/avr/constraints.md: Same.
667 * config/avr/predicates.md: Same.
669 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
672 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
673 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
674 simplify insn RTX using UMUL_HIGHPART rtx_code.
675 (*umuldi3_highpart_const): Remove.
677 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
680 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
681 * config/avr/avr.cc (_reg_unused_after): Make static. And
682 add 3rd argument to skip the current insn.
683 (reg_unused_after): Adjust call of reg_unused_after.
684 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
685 unneeded frame pointer adjustments.
687 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
690 * config/avr/avr.md (define_attr "cc"): Remove.
691 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
693 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
694 its uses. Add insn argument.
695 (avr_out_plus_symbol): Remove pcc argument and its uses.
696 (avr_out_plus): Remove pcc argument and its uses.
697 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
698 (avr_out_round): Adjust call of avr_out_plus.
700 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
702 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
705 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
708 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
709 is not an insn, but e.g. a code label.
711 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
713 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
714 * config/avr/avr.cc: Use them instead of magic numbers when it
715 means a register number.
717 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
719 * config/avr/avr.cc: Adjust some comments.
721 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
724 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
725 the low part of the frame pointer with 8-bit stack pointer.
727 2024-03-01 Patrick Palka <ppalka@redhat.com>
731 * tree-inline.cc (remap_decl): Handle copy_decl returning the
733 (remap_decls): Handle remap_decl returning the original decl.
734 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
737 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
739 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
741 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
742 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
743 (movhi_internal, movqi_internal): Likewise.
744 (movsf_softfloat, movsf_hardfloat): Likewise.
745 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
746 (movdf_softfloat): Likewise.
748 2024-03-01 Marek Polacek <polacek@redhat.com>
752 * doc/extend.texi: Document gnu::no_dangling.
753 * doc/invoke.texi: Mention that gnu::no_dangling disables
754 -Wdangling-reference.
756 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
758 * config/avr/avr.opt: Overhaul help screen.
760 2024-03-01 Jakub Jelinek <jakub@redhat.com>
761 Tobias Burnus <tburnus@baylibre.com>
764 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
765 lang_hooks.decls.omp_disregard_value_expr for
766 (first)private in target regions.
768 2024-03-01 Jakub Jelinek <jakub@redhat.com>
771 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
772 n_named_args initially before INIT_CUMULATIVE_ARGS to
773 structure_value_addr_parm rather than 0, after it don't modify
774 it if strict_argument_naming and clear only if
775 !pretend_outgoing_varargs_named.
777 2024-03-01 Jakub Jelinek <jakub@redhat.com>
780 * dwarf2out.cc (should_move_die_to_comdat): Return false for
781 aggregates without DW_AT_byte_size attribute or with non-constant
784 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
786 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
787 valid values for level.
789 2024-03-01 Richard Biener <rguenther@suse.de>
792 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
793 Allow the folding if before lowering and the current IL
794 isn't supported with vcond_mask.
796 2024-03-01 xuli <xuli1@eswincomputing.com>
798 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
799 attribute to riscv_attribute_table.
800 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
801 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
802 * doc/extend.texi: Add riscv_vector_cc attribute description.
804 2024-03-01 Pan Li <pan2.li@intel.com>
807 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
808 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
809 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
810 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
811 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
812 comments for option replacement.
813 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
814 riscv_autovec_preference to rvv_vector_bits.
815 (vls_mode_valid_p): Ditto.
816 (estimated_poly_value): Ditto.
817 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
818 vector chunks and honor new option mrvv-vector-bits.
819 (riscv_override_options_internal): Update comments and rename the
821 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
822 internal option param=riscv-autovec-preference.
824 2024-03-01 Jakub Jelinek <jakub@redhat.com>
826 * function.cc (assign_parms): Only call assign_parms_setup_varargs
827 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
829 2024-03-01 Jakub Jelinek <jakub@redhat.com>
832 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
833 rhs1 of a VCE to have no underlying variable if it is a load and
836 2024-02-29 David Malcolm <dmalcolm@redhat.com>
839 * function.cc (function_name): Make param const.
840 * function.h (function_name): Likewise.
842 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
845 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
846 * config/avr/avr.opt (-mfuse-add=): New target option.
847 * common/config/avr/avr-common.cc (avr_option_optimization_table)
848 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
849 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
850 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
851 * config/avr/avr-protos.h (avr_split_tiny_move)
852 (make_avr_pass_fuse_add): New protos.
853 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
854 avr_split_tiny_move to split indirect memory accesses.
855 (gen_move_clobbercc): New define_expand helper.
856 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
857 (avr_pass_fuse_add): New class from rtl_opt_pass.
858 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
859 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
860 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
861 of PLUS addressing for AVR_TINY.
862 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
863 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
864 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
866 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
869 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
870 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
871 (avr_function_arg): Set it.
872 (avr_frame_pointer_required_p): Use it instead of .nregs.
874 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
877 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
878 static and mark with GTY.
880 2024-02-29 Xi Ruoyao <xry111@xry111.site>
882 * config/loongarch/loongarch.md
883 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
885 2024-02-29 Xi Ruoyao <xry111@xry111.site>
887 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
888 (crc): New define_int_attr.
889 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
891 (loongarch_<crc>_w_<size>_w): ... here.
893 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
896 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
897 extend the expected value if needed.
899 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
901 * config.gcc (target_gtfiles): Change coreout to btfext-out.
902 (extra_objs): Change coreout to btfext-out.
903 * config/bpf/coreout.cc: Rename to btfext-out.cc.
904 * config/bpf/btfext-out.cc: Add.
905 * config/bpf/coreout.h: Rename to btfext-out.h.
906 * config/bpf/btfext-out.h: Add.
907 * config/bpf/core-builtins.cc: Change include.
908 * config/bpf/core-builtins.h: Change include.
909 * config/bpf/t-bpf: Accomodate renamed files.
911 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
914 * config/bpf/bpf.cc (bpf_function_prologue): Define target
916 * config/bpf/coreout.cc (brf_ext_info_section)
917 (btf_ext_info): Move from coreout.h
918 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
919 (bpf_core_reloc): Rename to btf_ext_core_reloc.
920 (btf_ext): Add static variable.
921 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
922 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
923 (btf_ext_add_string, btf_funcinfo_type_callback)
924 (btf_add_func_info_for, btf_validate_funcinfo)
925 (btf_ext_info_len, output_btfext_func_info): Add function.
926 (output_btfext_header, bpf_core_reloc_add)
927 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
928 Change to support new structs.
929 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
930 Move and change in coreout.cc.
931 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
933 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
935 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
936 enabled by default for BPF.
937 (bpf_file_end): Call BTF deallocation.
938 (bpf_asm_init_sections): Correct condition.
939 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
941 (ctf_debuf_finish): Correct condition for calling
944 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
946 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
947 (traverse_btf_func_types): Define function.
948 * ctfc.h (funcs_traverse_callback): Typedef for function
950 (traverse_btf_func_types): Add prototype.
952 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
954 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
956 2024-02-28 Richard Biener <rguenther@suse.de>
958 PR tree-optimization/113831
959 PR tree-optimization/108355
960 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
963 2024-02-28 Richard Biener <rguenther@suse.de>
965 PR tree-optimization/114121
966 * tree-ssa-sccvn.h (vn_reference_s::offset,
967 vn_reference_s::max_size): New fields.
968 (vn_reference_insert_pieces): Adjust prototype.
969 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
970 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
971 size, allow using "don't know" state.
972 (vn_walk_cb_data::finish): Pass along offset/max_size.
973 (vn_reference_lookup_or_insert_for_pieces): Take offset and
974 max_size as argument and use it.
975 (vn_reference_lookup_3): Properly adjust offset and max_size
976 according to the adjusted ao_ref.
977 (vn_reference_lookup_pieces): Initialize offset and max_size.
978 (vn_reference_lookup): Likewise.
979 (vn_reference_lookup_call): Likewise.
980 (vn_reference_insert): Likewise.
981 (visit_reference_op_call): Likewise.
982 (vn_reference_insert_pieces): Take offset and max_size
983 as argument and use it.
985 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
987 PR tree-optimization/114075
988 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
991 2024-02-28 Jakub Jelinek <jakub@redhat.com>
993 PR tree-optimization/114041
994 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
995 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
997 2024-02-28 Jakub Jelinek <jakub@redhat.com>
999 PR tree-optimization/113988
1000 * stor-layout.h (bitwise_mode_for_size): Declare.
1001 * stor-layout.cc (bitwise_mode_for_size): New function.
1002 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1003 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1004 Use BITS_PER_UNIT instead of 8.
1006 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
1009 * config/i386/mmx.md (V248FI): Add V2BF mode.
1012 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
1014 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
1015 if either ref->offset is not byte aligned or ref->size is not known
1016 to be equal to ref->max_size.
1017 (maybe_trim_complex_store): Fix description.
1018 (maybe_trim_constructor_store): Likewise.
1019 (maybe_trim_partially_dead_store): Likewise.
1021 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
1023 * config/arm/mmintrin.h: Warn if this header is included without
1024 defining __ENABLE_DEPRECATED_IWMMXT.
1026 2024-02-27 Richard Biener <rguenther@suse.de>
1028 PR tree-optimization/114074
1029 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
1030 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
1031 Handle poly vs. non-poly multiplication correctly with respect
1032 to undefined behavior on overflow.
1034 2024-02-27 Jakub Jelinek <jakub@redhat.com>
1036 PR rtl-optimization/114044
1037 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
1038 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
1039 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
1040 expand_PARITY): Declare.
1041 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
1042 expand_CTZ, expand_FFS, expand_PARITY): New functions.
1043 (expand_POPCOUNT): Use expand_bitquery.
1045 2024-02-27 Richard Biener <rguenther@suse.de>
1047 PR tree-optimization/114081
1048 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1049 Perform manual dominator update for prologue peeling.
1050 (vect_do_peeling): Properly update dominators after adding the
1051 prologue-around guard.
1053 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1055 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
1056 (mstrict-X): Tag as "Optimization".
1058 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
1060 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
1061 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
1063 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1064 H.J. Lu <hjl.tools@gmail.com>
1066 PR rtl-optimization/113617
1067 * varasm.cc (default_elf_select_rtx_section): For
1068 references to private symbols in comdat sections
1069 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
1070 or .rodata.<comdat> comdat sections.
1072 2024-02-26 Richard Biener <rguenther@suse.de>
1074 PR tree-optimization/114099
1075 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1076 Create and fill in a needed virtual LC PHI for the alternate
1077 exits. Remove code dealing with that missing.
1079 2024-02-26 Richard Biener <rguenther@suse.de>
1081 PR tree-optimization/114068
1082 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
1084 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
1085 on the main exit if needed. Remove band-aid for the case
1088 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1091 * config/i386/i386-options.cc (ix86_set_func_type): Check
1092 interrupt instead of noreturn attribute.
1094 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1096 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
1099 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1101 PR tree-optimization/114090
1102 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
1103 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
1105 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
1107 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1109 PR middle-end/114084
1110 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
1111 if all subtrees of var0 come from one of the op0 or op1 operands
1112 and all subtrees of con0 come from the other one. Don't clear
1113 variables which are never used afterwards.
1115 2024-02-26 Richard Biener <rguenther@suse.de>
1117 PR middle-end/114070
1118 * genmatch.cc (parser::parse_c_expr): Do not record operand
1119 lists but only mark operators used.
1120 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
1121 Properly guard the case of tcc_comparison changing the VEC_COND
1124 2024-02-26 Jakub Jelinek <jakub@redhat.com>
1127 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
1128 to printed instruction.
1130 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
1133 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
1134 __builtin_ia32_ldtilecfg.
1135 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
1136 * config/i386/i386-builtin.def (BDESC): Add
1137 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
1138 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
1139 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
1140 * config/i386/i386.md (ldtilecfg): New pattern.
1141 (sttilecfg): Likewise.
1143 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
1145 PR tree-optimization/113205
1146 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
1147 the proposed layout if it does not allow a source partition with
1148 layout 2 to keep that layout.
1150 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1152 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
1153 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
1154 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
1155 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
1156 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
1157 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
1159 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
1160 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
1161 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
1162 HOST_WIDE_INT_UC macros.
1163 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
1164 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
1165 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
1166 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
1168 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
1169 * config/i386/constraints.md (define_constraint "L"): Use
1170 HOST_WIDE_INT_C macro.
1171 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
1173 (movl + movb peephole2): Likewise.
1174 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
1175 (const_32bit_mask): Likewise.
1177 2024-02-24 Jakub Jelinek <jakub@redhat.com>
1179 PR middle-end/114073
1180 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
1181 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
1182 types like vector or complex types.
1183 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
1184 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
1185 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
1187 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
1190 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
1191 Return false if inner mode is already Pmode.
1192 (rvv_builder::is_all_same_sequence): New function.
1193 (expand_vec_init): Emit broadcast if sequence is all same.
1195 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1198 * config/aarch64/aarch64-early-ra.cc
1199 (early_ra::m_current_region): New member variable.
1200 (early_ra::m_fpr_recency): Likewise.
1201 (early_ra::start_new_region): Bump m_current_region.
1202 (early_ra::allocate_colors): Prefer less recently used registers
1203 in the event of a tie. Add a comment to explain why we prefer(ed)
1204 higher-numbered registers.
1205 (early_ra::find_oldest_color): Prefer less recently used registers
1207 (early_ra::finalize_allocation): Update recency information for
1208 allocated registers.
1209 (early_ra::process_blocks): Initialize m_current_region and
1212 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1215 * config/aarch64/aarch64-early-ra.cc
1216 (early_ra::test_strictness): New enum.
1217 (early_ra::is_chain_candidate): Add a strictness parameter to
1218 control whether only correctness matters, or whether both correctness
1219 and heuristics should be used. Handle multiple levels of equivalence.
1220 (early_ra::find_related_start): Update call accordingly.
1221 (early_ra::strided_polarity_pref): Likewise.
1222 (early_ra::form_chains): Likewise.
1223 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
1224 correctness mode rather than trying to inline the test.
1226 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
1229 * config/aarch64/aarch64-early-ra.cc
1230 (early_ra::find_related_start): Account for definitions by shared
1231 registers when testing for a single register definition.
1232 (early_ra::accumulate_defs): New function.
1233 (early_ra::record_copy): If A shares B's register, fold A's
1234 definition information into B's. Fold A's use information into B's.
1236 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
1238 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
1239 if R_X86_64_CODE_6_GOTTPOFF is supported.
1240 * config.in: Regenerated.
1241 * configure: Likewise.
1242 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
1243 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
1245 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
1248 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
1249 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
1251 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1253 PR rtl-optimization/114054
1254 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
1255 temp variable instead of target parameter for result.
1257 2024-02-23 Jakub Jelinek <jakub@redhat.com>
1259 PR tree-optimization/114040
1260 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
1261 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
1262 probability from likely to unlikely. When handling the true true
1263 store, first cast to limb_access_type and then to l's type.
1265 2024-02-23 Richard Biener <rguenther@suse.de>
1268 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
1270 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1273 * config/riscv/arch-canonicalize: Move to python3
1274 * config/riscv/multilib-generator: Likewise
1276 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
1278 * doc/invoke.texi: Document -mcpu.
1280 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
1282 * configure: Regenerate.
1283 * configure.ac: Add parameter "--fatal-warnings" to assemble
1284 when checking whether the assemble support conditional branch
1287 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1290 * doc/extend.texi: (__extension__): Remove comments about scope
1291 tokens vs. two colons.
1293 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
1295 PR tree-optimization/109804
1296 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
1297 DEMANGLE_COMPONENT_UNNAMED_TYPE.
1299 2024-02-22 Richard Biener <rguenther@suse.de>
1301 PR tree-optimization/114048
1302 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
1303 can also produce -1 off.
1305 2024-02-22 Richard Biener <rguenther@suse.de>
1307 PR tree-optimization/114027
1308 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
1309 condition reduction classification only for single-element
1312 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1315 * profile-count.h (profile_count::dump): Remove overload with
1316 char * first argument.
1317 * profile-count.cc (profile_count::dump): Change overload with char *
1318 first argument which uses sprintf into the overfload with FILE *
1319 first argument and use fprintf instead. Remove overload which wrapped
1322 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1324 PR tree-optimization/113993
1325 * tree-call-cdce.cc (get_no_error_domain): Handle
1326 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
1327 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
1328 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1329 the as the F128 suffixed cases, otherwise as non-suffixed ones.
1330 Handle BUILT_IN_{EXP,POW}10L for
1331 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
1334 2024-02-22 Jakub Jelinek <jakub@redhat.com>
1336 PR tree-optimization/114038
1337 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
1338 loop exit condition if end is divisible by limb_prec.
1340 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
1342 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
1343 problem of mabi=, mno-flush-func, mexplicit-relocs;
1344 add missing leading - of mbranch-cost option.
1345 * config/mips/mips.opt.urls: Regenerate.
1347 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
1350 * config/rs6000/constraints.md (we): Update internal doc without
1351 referring to option -mpower9-vector.
1352 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
1354 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
1355 OTHER_P8_VECTOR_MASKS): Merge to ...
1356 (OTHER_VSX_VECTOR_MASKS): ... here.
1357 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
1358 some error message handlings and explicit option mask adjustments on
1359 explicit option power{8,9}-vector conflicting with other options.
1360 (rs6000_print_isa_options): Update comments.
1361 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
1362 related array items and handlings.
1363 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
1365 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
1367 * doc/extend.texi: Remove documentation referring to option
1369 * doc/invoke.texi: Remove documentation for option
1370 -mpower{8,9}-vector and adjust some documentation referring to them.
1371 * doc/md.texi: Update documentation for constraint we.
1372 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
1374 2024-02-22 Pan Li <pan2.li@intel.com>
1377 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
1378 the version to 0.12.
1380 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1382 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
1384 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1385 Robin Dapp <rdapp.gcc@gmail.com>
1387 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1388 (generic_ooo_vec_load): Ditto
1389 (generic_ooo_vec_store): Ditto
1390 (generic_ooo_vec_loadstore_seg): Ditto
1391 (generic_ooo_vec_alu): Ditto
1392 (generic_ooo_vec_fcmp): Ditto
1393 (generic_ooo_vec_imul): Ditto
1394 (generic_ooo_vec_fadd): Ditto
1395 (generic_ooo_vec_fmul): Ditto
1396 (generic_ooo_crypto): Ditto
1397 (generic_ooo_perm): Ditto
1398 (generic_ooo_vec_reduction): Ditto
1399 (generic_ooo_vec_ordered_reduction): Ditto
1400 (generic_ooo_vec_idiv): Ditto
1401 (generic_ooo_vec_float_divsqrt): Ditto
1402 (generic_ooo_vec_mask): Ditto
1403 (generic_ooo_vec_vesetvl): Ditto
1404 (generic_ooo_vec_setrm): Ditto
1405 (generic_ooo_vec_readlen): Ditto
1406 * config/riscv/riscv.md: Include generic-vector-ooo
1407 * config/riscv/generic-vector-ooo.md: New file. To here
1409 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
1411 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1412 (generic_ooo_branch): Ditto
1413 * config/riscv/generic.md (generic_sfb_alu): Ditto
1414 (generic_fmul_half): Ditto
1415 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1416 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
1417 (sifive_7_popcount): Ditto
1418 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
1419 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
1420 * config/riscv/vector.md: Change rdfrm to fmove
1421 * config/riscv/zc.md: Change pushpop to load/store
1423 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
1425 * doc/invoke.texi (Warning Options): Fix typos.
1427 2024-02-21 David Faust <david.faust@oracle.com>
1429 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
1430 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
1431 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
1433 2024-02-21 Martin Jambor <mjambor@suse.cz>
1436 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
1437 initializers in the contructor.
1438 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
1439 * ipa-cp.h: New file.
1440 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
1441 (ipcp_value_source): Move to ipa-cp.h.
1442 (ipcp_value_base): Likewise.
1443 (ipcp_value): Likewise.
1444 (ipcp_lattice): Likewise.
1445 (ipcp_agg_lattice): Likewise.
1446 (ipcp_bits_lattice): Likewise.
1447 (ipcp_vr_lattice): Likewise.
1448 (ipcp_param_lattices): Likewise.
1449 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
1450 (ipa_value_from_jfunc): Adjust a check for empty lattices.
1451 (ipa_context_from_jfunc): Likewise.
1452 (ipa_agg_value_from_jfunc): Likewise.
1453 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
1454 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
1455 just in contiguous memory.
1456 (ipcp_store_vr_results): Adjust a check for empty lattices.
1457 * auto-profile.cc: Include sreal.h and ipa-cp.h.
1458 * cgraph.cc: Likewise.
1459 * cgraphclones.cc: Likewise.
1460 * cgraphunit.cc: Likewise.
1461 * config/aarch64/aarch64.cc: Likewise.
1462 * config/i386/i386-builtins.cc: Likewise.
1463 * config/i386/i386-expand.cc: Likewise.
1464 * config/i386/i386-features.cc: Likewise.
1465 * config/i386/i386-options.cc: Likewise.
1466 * config/i386/i386.cc: Likewise.
1467 * config/rs6000/rs6000.cc: Likewise.
1468 * config/s390/s390.cc: Likewise.
1469 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
1470 files to be included in gtype-desc.cc.
1471 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
1472 * ipa-devirt.cc: Likewise.
1473 * ipa-fnsummary.cc: Likewise.
1474 * ipa-icf.cc: Likewise.
1475 * ipa-inline-analysis.cc: Likewise.
1476 * ipa-inline-transform.cc: Likewise.
1477 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
1478 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
1479 * ipa-param-manipulation.cc: Likewise.
1480 * ipa-predicate.cc: Likewise.
1481 * ipa-profile.cc: Likewise.
1482 * ipa-prop.cc: Likewise.
1483 (ipa_node_params_t::duplicate): Assert new lattices remain empty
1484 instead of setting them to NULL.
1485 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
1486 * ipa-split.cc: Likewise.
1487 * ipa-sra.cc: Likewise.
1488 * ipa-strub.cc: Likewise.
1489 * ipa-utils.cc: Likewise.
1491 * toplev.cc: Likewise.
1492 * tree-ssa-ccp.cc: Likewise.
1493 * tree-ssa-sccvn.cc: Likewise.
1494 * tree-vrp.cc: Likewise.
1496 2024-02-21 Tamar Christina <tamar.christina@arm.com>
1498 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
1501 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1503 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1504 Use aarch64_gen_compare_zero_and_branch rather than emitting
1507 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1509 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
1510 Remove duplicated call.
1512 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1514 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
1515 Check that each individual piece of state is shared in the same
1516 way, rather than using an aggregate check for PSTATE.ZA.
1518 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1520 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1521 In the code that commits a lazy save, only zero ZA if the function
1522 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
1524 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1526 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
1527 directly inserting the associated sequence
1528 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
1531 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1534 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
1535 fold the SVE allocation into the initial allocation if the
1536 initial allocation includes a VG save.
1538 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
1541 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
1542 contain jumps even if called after initial RTL expansion.
1543 * mode-switching.cc: Include cfgbuild.h.
1544 (optimize_mode_switching): Allow the sequence returned by the
1545 emit hook to contain internal jumps. Record which blocks
1546 contain such jumps and split the blocks at the end.
1547 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
1548 non-debug insns when scanning the sequence.
1550 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
1552 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
1553 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
1555 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1557 * doc/invoke.texi (-mmcu): Add information about MCU specs.
1559 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
1561 * doc/invoke.texi (-minrt): Clarify that main
1562 must take no arguments.
1564 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1566 * config/avr/builtins.def: Use function prototypes of given size
1568 * config/avr/avr.cc (avr_init_builtins): Adjust types required
1570 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
1572 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
1574 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
1577 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
1579 * config/bpf/bpf.opt: Add help information for -mcpu.
1581 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
1584 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
1586 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
1588 * config/aarch64/aarch64.md (is_call): New attribute.
1589 (*and<mode>3nr_compare0): Rename to...
1590 (@aarch64_and<mode>3nr_compare0): ...this.
1591 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
1592 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
1593 * config/aarch64/aarch64-speculation.cc: Update file comment to
1594 describe the new late pass.
1595 (aarch64_do_track_speculation): Handle is_call insns like other calls.
1596 (pass_track_speculation): Add an is_late member variable.
1597 (pass_track_speculation::gate): Run the late pass for streaming-
1598 compatible functions and the early pass for other functions.
1599 (make_pass_track_speculation): Update accordingly.
1600 (make_pass_late_track_speculation): New function.
1601 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
1603 (aarch64_guard_switch_pstate_sm): Use it.
1605 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
1607 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
1608 Register these builtins with a pointer to uint64_t rather than unsigned
1611 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1614 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
1615 Conditionalize on '!TARGET_RDNA2_PLUS'.
1616 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
1617 (gcn_expand_reduc_scalar):
1618 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
1620 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
1622 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
1623 '__gfx90a__' target CPU definition. Add some safeguards for the future.
1625 2024-02-19 Richard Biener <rguenther@suse.de>
1627 PR rtl-optimization/54052
1628 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
1629 local defs by LR_OUT.
1631 2024-02-19 Jakub Jelinek <jakub@redhat.com>
1633 PR tree-optimization/113967
1634 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
1635 in condition that @rpos is multiple of vector element size.
1637 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
1640 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
1641 Suppress vsetvl fusion.
1643 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
1646 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
1647 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
1648 (ix86_emit_save_regs): Don't generate push2 if
1649 ix86_can_use_push2pop2 return false.
1650 (ix86_expand_epilogue): Don't generate pop2 if
1651 ix86_can_use_push2pop2 return false.
1653 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1655 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
1656 Note on complete device support.
1658 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
1660 * doc/extend.texi (AVR Function Attributes): Fuse description
1661 of "signal" and "interrupt" attribute. Link pseudo instruction.
1663 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1665 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
1666 symbol type conversions.
1667 (__cacop_d): Likewise.
1668 (__cpucfg): Likewise.
1669 (__asrtle_d): Likewise.
1670 (__asrtgt_d): Likewise.
1671 (__lddir_d): Likewise.
1672 (__ldpte_d): Likewise.
1673 (__crc_w_b_w): Likewise.
1674 (__crc_w_h_w): Likewise.
1675 (__crc_w_w_w): Likewise.
1676 (__crc_w_d_w): Likewise.
1677 (__crcc_w_b_w): Likewise.
1678 (__crcc_w_h_w): Likewise.
1679 (__crcc_w_w_w): Likewise.
1680 (__crcc_w_d_w): Likewise.
1681 (__csrrd_w): Likewise.
1682 (__csrwr_w): Likewise.
1683 (__csrxchg_w): Likewise.
1684 (__csrrd_d): Likewise.
1685 (__csrwr_d): Likewise.
1686 (__csrxchg_d): Likewise.
1687 (__iocsrrd_b): Likewise.
1688 (__iocsrrd_h): Likewise.
1689 (__iocsrrd_w): Likewise.
1690 (__iocsrrd_d): Likewise.
1691 (__iocsrwr_b): Likewise.
1692 (__iocsrwr_h): Likewise.
1693 (__iocsrwr_w): Likewise.
1694 (__iocsrwr_d): Likewise.
1695 (__frecipe_s): Likewise.
1696 (__frecipe_d): Likewise.
1697 (__frsqrte_s): Likewise.
1698 (__frsqrte_d): Likewise.
1700 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
1702 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
1703 function return value type to unsigned short.
1705 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
1707 * doc/sourcebuild.texi: add scan-assembler-bound
1709 2024-02-16 Jason Merrill <jason@redhat.com>
1711 * gdbhooks.py: Fix regex syntax.
1713 2024-02-16 Richard Biener <rguenther@suse.de>
1715 PR tree-optimization/113895
1716 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
1717 consistency checking when there are out-of-bound array
1718 accesses. Allow -1 off when from an array reference with
1721 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1724 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
1727 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1729 * doc/sourcebuild.texi (Effective-Target Keywords, Other
1730 attribugs): Document linker_plugin.
1731 (Require Support): Document dg-require-linker-plugin.
1733 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
1736 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
1737 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
1738 (RISCV_MINOR_VERSION_BASE): Ditto.
1739 (RISCV_REVISION_VERSION_BASE): Ditto.
1740 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
1741 rather than magic number.
1742 * config/riscv/riscv.h (riscv_arch_help): New.
1743 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
1744 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
1745 --print-supported-extensions.
1746 * config/riscv/riscv.opt (march=help): New.
1747 (print-supported-extensions): New.
1748 (-print-supported-extensions): New.
1749 * doc/invoke.texi (RISC-V Options): Document -march=help.
1751 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
1754 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
1755 for indirect calls with 4 or more arguments in pac-enabled functions.
1757 2024-02-15 David Faust <david.faust@oracle.com>
1759 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
1760 use ldxb instead of ldxh.
1762 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1764 PR middle-end/113921
1765 * cfgrtl.h (prepend_insn_to_edge): New declaration.
1766 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
1768 (prepend_insn_to_edge): New function.
1769 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
1770 insert_insn_on_edge.
1772 2024-02-15 Richard Biener <rguenther@suse.de>
1774 PR tree-optimization/111156
1775 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
1776 at the pattern stmt if any.
1778 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
1781 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
1782 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
1783 * config/avr/avr.cc (avr_adiw_reg_p): New function.
1784 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
1785 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
1786 * config/avr/avr.md: Same.
1787 (attr "isa") <tiny, no_tiny>: Remove.
1788 <adiw, no_adiw>: Add.
1789 (define_insn, define_insn_and_split): When an alternative has
1790 constraint "w", then set attribute "isa" to "adiw".
1791 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
1792 Built-in define __AVR_HAVE_ADIW__.
1793 * doc/invoke.texi (AVR Options): Document it.
1795 2024-02-15 Andrew Stubbs <ams@baylibre.com>
1797 * config/gcn/gcn-valu.md
1798 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
1799 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
1800 details are supported on RDNA devices.
1802 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1804 PR middle-end/113508
1805 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
1806 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
1807 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
1808 Add sentence about what the mode m is.
1810 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
1812 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
1813 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
1816 2024-02-15 Richard Biener <rguenther@suse.de>
1818 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
1821 2024-02-15 Jakub Jelinek <jakub@redhat.com>
1823 PR tree-optimization/113567
1824 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
1825 _BitInt multiplication, division or modulo with
1826 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
1827 force the affected inputs into a new SSA_NAME.
1829 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
1832 * config/i386/mmx.md (V248FI): New mode iterator.
1834 (vec_shl_<V248FI:mode>): New expander.
1835 (vec_shl_<V24FI_32:mode>): Ditto.
1836 (vec_shr_<V248FI:mode>): Ditto.
1837 (vec_shr_<V24FI_32:mode>): Ditto.
1838 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
1839 (vec_shr_<V248FI:mode>): Ditto.
1841 2024-02-14 Jan Hubicka <jh@suse.cz>
1843 PR tree-optimization/111054
1844 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
1846 2024-02-14 Tamar Christina <tamar.christina@arm.com>
1848 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
1850 2024-02-14 Richard Biener <rguenther@suse.de>
1852 PR tree-optimization/113910
1853 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
1856 2024-02-14 Jakub Jelinek <jakub@redhat.com>
1858 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
1859 (pp_integer_with_precision): For unsigned ptrdiff_t printing
1860 with u, o or x print ptrdiff_t argument converted to
1861 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
1863 2024-02-14 Richard Biener <rguenther@suse.de>
1865 PR middle-end/113576
1866 * expr.cc (do_store_flag): For vector bool compares of vectors
1867 with padding zero that.
1868 * dojump.cc (do_compare_and_jump): Likewise.
1870 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
1872 * doc/install.texi (Prerequisites): Update gettext link.
1874 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
1877 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
1878 Return false if the incoming stack isn't 16-byte aligned.
1880 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
1882 PR middle-end/113904
1883 * omp-general.cc (struct omp_ts_info): Update for splitting of
1884 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1885 * omp-selectors.h (enum omp_tp_type): Replace
1886 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
1888 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
1891 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
1892 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
1894 2024-02-13 Richard Biener <rguenther@suse.de>
1896 PR tree-optimization/113895
1897 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
1898 offset to discover constant array indices in bits, handle
1899 COMPONENT_REF to bitfields.
1901 2024-02-13 Richard Biener <rguenther@suse.de>
1903 PR tree-optimization/113831
1904 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
1907 2024-02-13 Richard Biener <rguenther@suse.de>
1909 PR tree-optimization/113902
1910 * tree-vect-loop.cc (move_early_exit_stmts): Track
1911 last_seen_vuse for VUSE updating.
1913 2024-02-13 Tamar Christina <tamar.christina@arm.com>
1915 PR tree-optimization/113734
1916 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
1917 an early break loop as partial.
1919 2024-02-13 Richard Biener <rguenther@suse.de>
1921 PR tree-optimization/113898
1922 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
1923 missing accumulated off adjustment.
1925 2024-02-13 Jakub Jelinek <jakub@redhat.com>
1927 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
1928 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
1929 it against UINT_MAX and ULONG_MAX.
1931 2024-02-13 David Malcolm <dmalcolm@redhat.com>
1933 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
1935 (emit_diagnostic_valist_meta): ...this.
1936 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
1937 (emit_diagnostic_valist_meta): ...this.
1939 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1941 PR tree-optimization/113849
1942 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
1943 fast path for widening casts where !m_upwards_2limb and lhs_type
1944 has precision which is a multiple of limb_prec.
1946 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1949 * attribs.cc (extract_attribute_substring): Remove.
1950 (lookup_scoped_attribute_spec): Don't call it.
1952 2024-02-12 Jakub Jelinek <jakub@redhat.com>
1954 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
1955 and cast to fmt_size_t instead of %lu and cast to unsigned long.
1957 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
1959 * Makefile.in: Add no-info dependency.
1960 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
1962 * configure: Regenerate.
1964 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
1967 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
1968 available to all sub-targets.
1969 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1970 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
1972 2024-02-12 Richard Biener <rguenther@suse.de>
1974 PR tree-optimization/113831
1975 PR tree-optimization/108355
1976 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
1977 we see variable array indices and get_ref_base_and_extent
1978 can resolve those to constants fix up the ops to constants
1980 (ao_ref_init_from_vn_reference): Use 'off' member for
1981 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
1982 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
1984 2024-02-12 Pan Li <pan2.li@intel.com>
1986 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
1987 Replace args to arguments for misspelled term.
1989 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
1992 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
1993 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
1994 when not linked with -mrodata-in-ram.
1996 2024-02-12 Richard Biener <rguenther@suse.de>
1998 PR tree-optimization/113863
1999 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2000 Record crossed virtual PHIs.
2001 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2004 2024-02-10 Marek Polacek <polacek@redhat.com>
2009 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2011 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2013 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2014 computation of idx for i == 4 of bitint_prec_huge.
2016 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2018 PR middle-end/110754
2019 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2020 decls create PARM_DECL with pointer to original type, set
2021 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2022 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
2023 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
2024 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
2025 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
2026 of the var as argument.
2028 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2030 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
2031 size_t and precision 4 for ptrdiff_t. Formatting fix.
2032 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
2034 (test_pp_format): Test t and z modifiers.
2035 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
2037 2024-02-10 Jakub Jelinek <jakub@redhat.com>
2039 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
2040 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
2041 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2042 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
2043 and casts to fmt_size_t instead of "%ld" and casts to long.
2044 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
2045 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
2046 instead of "%lu" and casts to unsigned long.
2047 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
2049 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2050 and casts to fmt_size_t instead of "%ld" and casts to long.
2051 * cfgexpand.cc (dump_stack_var_partition): Use
2052 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
2053 and casts to unsigned long.
2054 * gengtype.cc (adjust_field_rtx_def): Likewise.
2055 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
2056 and casts to fmt_size_t instead of "%ld" and casts to long.
2057 * postreload-gcse.cc (dump_hash_table): Likewise.
2058 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
2059 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
2060 (ggc_internal_alloc, ggc_free): Likewise.
2061 * genpreds.cc (write_lookup_constraint_1): Likewise.
2062 (write_insn_constraint_len): Likewise.
2063 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
2064 and casts to fmt_size_t instead of "%ld" and casts to long.
2065 * varasm.cc (output_constant_pool_contents): Use
2066 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
2067 * var-tracking.cc (dump_var): Likewise.
2069 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2071 PR tree-optimization/113783
2072 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
2073 through VIEW_CONVERT_EXPR for final cast checks. Handle
2074 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
2076 (gimple_lower_bitint): Don't merge mergeable operations or other
2077 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
2078 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
2081 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2083 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
2084 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
2085 HOST_SIZE_T_PRINT_HEX_PURE): Define.
2086 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
2089 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2091 PR middle-end/113415
2092 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
2093 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
2094 of hand written loop with emit_insn of copy_insn and emit original
2095 after_rtl_seq on the last edge.
2097 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2099 PR tree-optimization/113818
2100 * gimple-lower-bitint.cc (add_eh_edge): New function.
2101 (bitint_large_huge::handle_load,
2102 bitint_large_huge::lower_mergeable_stmt,
2103 bitint_large_huge::lower_muldiv_stmt): Use it.
2105 2024-02-09 Jakub Jelinek <jakub@redhat.com>
2107 PR tree-optimization/113774
2108 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
2109 emit any comparison if m_first and low + 1 is equal to
2110 m_upwards_2limb, simplify condition for that. If not
2111 single_comparison, not m_first and we can prove that the idx <= low
2112 comparison will be always true, emit instead of idx <= low
2113 comparison low <= low such that cfg cleanup will optimize it at
2114 the end of the pass.
2116 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
2118 PR tree-optimization/113735
2119 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
2122 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2124 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
2125 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
2127 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
2131 * config/i386/constraints.md: List all constraints with j prefix.
2132 (j>): Change auto-dec to auto-inc in documentation.
2133 (je): Changed to a memory constraint with APX NDD TLS operand
2135 (jM): New memory constraint for APX NDD instructions.
2137 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
2138 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
2139 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
2140 (*add<mode>_1[SWI48]): Use je and jM.
2141 (addsi_1_zext): Use jM.
2142 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
2143 (*sub<mode>_1[SWI]): Use jM.
2144 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
2145 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
2146 (*and<dwi>3_doubleword): Likewise.
2148 (*andsi_1_zext): Likewise.
2149 (*and<mode>_1[SWI24]): Likewise.
2150 (*<code><dwi>3_doubleword[any_or]): Use rjO
2151 (*code<mode>_1[any_or SWI248]): Use jM.
2152 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
2153 * config/i386/predicates.md (apx_ndd_memory_operand): New.
2154 (apx_ndd_add_memory_operand): Likewise.
2156 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2159 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
2160 * doc/avr-mmcu.texi: Rebuild.
2162 2024-02-08 Tamar Christina <tamar.christina@arm.com>
2164 PR tree-optimization/113808
2165 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
2166 value cross iterations.
2168 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2170 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
2171 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
2173 2024-02-08 Richard Biener <rguenther@suse.de>
2175 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2176 Revert last change to dr_may_alias_p.
2178 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
2180 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
2181 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
2182 Remove spec asm_misc.
2183 * config/avr/specs.h: Same.
2185 2024-02-08 Pan Li <pan2.li@intel.com>
2188 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
2189 sure the c.arg_num is >= 2 before checking.
2190 (struct build_frm_base): Ditto.
2191 (struct narrow_alu_def): Ditto.
2193 2024-02-07 Richard Biener <rguenther@suse.de>
2195 PR tree-optimization/113796
2196 * tree-if-conv.cc (combine_blocks): Wipe range-info before
2197 replacing PHIs and inserting predicates.
2199 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
2200 Uros Bizjak <ubizjak@gmail.com>
2203 * config/i386/i386-features.cc (timode_convert_cst): New helper
2204 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
2206 (timode_scalar_chain::convert_op): Use timode_convert_cst.
2207 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
2208 Use timode_convert_cst.
2210 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
2212 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
2213 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
2214 (AARCH64_FL_DEBUGv8p9): Likewise.
2215 (AARCH64_FL_FGT2): Likewise.Likewise.
2216 (AARCH64_FL_ITE): Likewise.
2217 (AARCH64_FL_PFAR): Likewise.
2218 (AARCH64_FL_PMUv3_ICNTR): Likewise.
2219 (AARCH64_FL_PMUv3_SS): Likewise.
2220 (AARCH64_FL_PMUv3p9): Likewise.
2221 (AARCH64_FL_RASv2): Likewise.
2222 (AARCH64_FL_S1PIE): Likewise.
2223 (AARCH64_FL_S1POE): Likewise.
2224 (AARCH64_FL_S2PIE): Likewise.
2225 (AARCH64_FL_S2POE): Likewise.
2226 (AARCH64_FL_SCTLR2): Likewise.
2227 (AARCH64_FL_SEBEP): Likewise.
2228 (AARCH64_FL_SPE_FDS): Likewise.
2229 (AARCH64_FL_TCR2): Likewise.
2231 2024-02-07 Richard Biener <rguenther@suse.de>
2233 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2234 Only check whether reads are in-bound in places that are not safe.
2235 Fix dependence check. Add missing newline. Clarify comments.
2237 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2239 PR tree-optimization/113750
2240 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
2241 for single predecessor when doing early break vect.
2242 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
2245 2024-02-07 Tamar Christina <tamar.christina@arm.com>
2247 PR tree-optimization/113731
2248 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
2250 * gimple-iterator.h (gsi_move_before): Default new param to
2252 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
2255 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2257 PR tree-optimization/113756
2258 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
2259 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
2260 of lh_bits value and mask.
2262 2024-02-07 Jakub Jelinek <jakub@redhat.com>
2264 PR tree-optimization/113753
2265 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
2266 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
2267 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
2268 so that they start with r[half_blocks_needed] lowest bit. Fix up
2269 computation of top mask for SIGNED.
2271 2024-02-07 Pan Li <pan2.li@intel.com>
2274 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
2275 the signature of func.
2276 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
2277 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
2278 overloaded func with empty args error.
2280 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
2283 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
2284 R10_REG after sorry.
2286 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
2288 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
2289 Move before new caller, and add ".default" suffix.
2290 (get_suffixed_assembler_name): New.
2291 (make_resolver_func): Use get_suffixed_assembler_name.
2292 (aarch64_generate_version_dispatcher_body): Redo name mangling.
2294 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2297 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
2298 element from std::pair<unsigned int, char> to an unnamed struct.
2299 Adjust uses of tile range variable.
2301 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2303 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
2304 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
2306 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2309 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
2310 reset maxlen to sizetype maximum.
2312 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2314 PR tree-optimization/113736
2315 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2316 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
2318 2024-02-06 Jakub Jelinek <jakub@redhat.com>
2320 PR tree-optimization/113759
2321 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
2322 or from_unsignedN differs from properties of typeN, update typeN
2323 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
2324 uselessly convertible to typeN, convert it using fold_convert or
2325 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
2326 (convert_plusminus_to_widen): Likewise.
2328 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
2331 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
2332 vector structure modes correctly.
2334 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
2336 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
2339 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
2342 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
2343 (x86_function_profiler): Call x86_64_select_profile_regnum to
2344 get a scratch register for large model profiling.
2346 2024-02-05 Richard Ball <richard.ball@arm.com>
2348 * config/arm/arm.cc (arm_output_mi_thunk): Emit
2349 insn for bti_c when bti is enabled.
2351 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2353 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
2356 2024-02-05 Xi Ruoyao <xry111@xry111.site>
2358 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
2359 (neg<mode>2): Change the mode iterator from MSA to IMSA because
2360 in FP arithmetic we cannot use (0 - x) for -x.
2361 (neg<mode>2): New define_insn to implement FP vector negation,
2362 using a bnegi instruction to negate the sign bit.
2364 2024-02-05 Richard Biener <rguenther@suse.de>
2366 PR tree-optimization/113707
2367 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
2368 checking the avail set treat out-of-region defines as
2371 2024-02-05 Richard Biener <rguenther@suse.de>
2373 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
2374 the default mode when building a pointer.
2376 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2378 PR tree-optimization/113737
2379 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
2380 has just a single label, remove it and make single successor edge
2383 2024-02-05 Jakub Jelinek <jakub@redhat.com>
2386 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2387 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
2390 2024-02-05 Richard Biener <rguenther@suse.de>
2393 * config/i386/i386-expand.cc
2394 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
2395 Use a new pseudo for the skipped number of bytes.
2397 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2399 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
2400 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
2403 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
2405 * config/riscv/riscv.md: Include sifive-p400.md.
2406 * config/riscv/sifive-p400.md: New file.
2407 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2408 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2410 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
2411 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2412 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
2414 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2416 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
2417 Add missing ":SI" to the match_operator.
2419 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2421 * config/xtensa/xtensa.md (SHI): New mode iterator.
2422 (2 split patterns related to constsynth):
2423 Change to also accept HImode operands.
2425 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
2427 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
2430 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2432 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
2434 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
2435 (elmsgnbit): Likewise.
2436 (neg<mode:FVEC>2): New define_insn.
2437 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
2438 are now instantiated in simd.md.
2440 2024-02-04 Xi Ruoyao <xry111@xry111.site>
2442 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
2443 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
2446 2024-02-04 Li Wei <liwei@loongson.cn>
2448 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
2449 (loongarch_expand_vselect_vconcat): Ditto.
2450 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
2451 all 128-bit constant permutation situations.
2452 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
2453 (loongarch_is_imm_set_shuffle): Renamed function name.
2454 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
2455 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
2456 extract-even and extract-odd permutations.
2457 (loongarch_is_odd_extraction): Delete.
2458 (loongarch_is_even_extraction): Ditto.
2459 (loongarch_expand_vec_perm_const): Adjust.
2461 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2463 PR middle-end/113722
2464 * wide-int.cc (wi::bswap_large): Rename third argument from
2465 len to xlen and adjust use in safe_uhwi. Add len variable, set
2466 it to BLOCKS_NEEDED (precision) and use it for clearing of val
2467 and as canonize argument. Clear val using memset instead of
2470 2024-02-03 Jakub Jelinek <jakub@redhat.com>
2472 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
2473 mmi.preferred_base + mmi.size - sizeof (void *).
2475 2024-02-03 Xi Ruoyao <xry111@xry111.site>
2477 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
2478 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
2479 the ODR-violating locale declaration.
2481 2024-02-02 Tamar Christina <tamar.christina@arm.com>
2483 PR tree-optimization/113588
2484 PR tree-optimization/113467
2485 * tree-vect-data-refs.cc
2486 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
2487 (vect_analyze_early_break_dependences): Update comments.
2489 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
2492 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
2493 and PA_BUILTIN_SET_FPSR builtins.
2494 * (pa_builtins_icode): Declare.
2495 * (def_builtin, pa_fpu_init_builtins): New.
2496 * (pa_init_builtins): Initialize FPU builtins.
2497 * (pa_builtin_decl, pa_expand_builtin_1): New.
2498 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
2499 PA_BUILTIN_SET_FPSR builtins.
2500 * (pa_atomic_assign_expand_fenv): New.
2501 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
2503 (get_fpsr, put_fpsr): New expanders.
2504 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
2507 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2510 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
2512 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
2514 * doc/extend.texi (Common Type Attributes): Fix typo in
2515 description of hardbool.
2517 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2519 PR tree-optimization/113692
2520 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
2521 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
2524 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2526 PR middle-end/113699
2527 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
2528 uninitialized large/huge _BitInt SSA_NAME inputs.
2530 2024-02-02 Jakub Jelinek <jakub@redhat.com>
2532 PR middle-end/113705
2533 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
2534 around wi::to_wide in order to compare value in prec precision.
2536 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
2539 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2541 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2543 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2545 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
2547 2024-02-02 Pan Li <pan2.li@intel.com>
2549 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
2550 (riscv_pass_by_reference): Ditto.
2551 (riscv_fntype_abi): Ditto.
2553 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2555 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
2556 (pre_vsetvl::cleaup): Remove vsetvl_pre.
2557 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
2559 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
2561 * config/loongarch/larchintrin.h
2562 (__frecipe_s): Update function return type.
2563 (__frecipe_d): Ditto.
2564 (__frsqrte_s): Ditto.
2565 (__frsqrte_d): Ditto.
2567 2024-02-02 Li Wei <liwei@loongson.cn>
2569 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
2570 (loongarch_vector_costs::add_stmt_cost): Adjust.
2572 2024-02-02 Xi Ruoyao <xry111@xry111.site>
2574 * config/loongarch/loongarch.md (unspec): Add
2575 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
2576 (la_pcrel64_two_parts): New define_insn.
2577 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
2578 typo in the comment.
2579 (loongarch_call_tls_get_addr): If -mcmodel=extreme
2580 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
2581 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
2582 note to allow CSE addressing __tls_get_addr.
2583 (loongarch_legitimize_tls_address): If -mcmodel=extreme
2584 -mexplicit-relocs={always,auto}, address TLS IE symbols with
2585 la_pcrel64_two_parts.
2586 (loongarch_split_symbol): If -mcmodel=extreme
2587 -mexplicit-relocs={always,auto}, address symbols with
2588 la_pcrel64_two_parts.
2589 (loongarch_output_mi_thunk): Clean up unreachable code. If
2590 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
2591 thunks with la_pcrel64_two_parts.
2593 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2595 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
2596 Add support for call36.
2598 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2600 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2601 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
2602 the macro instruction loading symbol address is not applicable.
2603 (loongarch_call_tls_get_addr): Adjust code.
2604 (loongarch_legitimize_tls_address): Likewise.
2606 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2608 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
2609 Add function declaration.
2610 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
2611 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
2613 (loongarch_load_tls): Added macro support in extreme mode.
2614 (loongarch_call_tls_get_addr): Likewise.
2615 (loongarch_legitimize_tls_address): Likewise.
2616 (loongarch_force_address): Likewise.
2617 (loongarch_legitimize_move): Likewise.
2618 (loongarch_output_mi_thunk): Likewise.
2619 (loongarch_option_override_internal): Remove the code that detects
2620 explicit relocs status.
2621 (loongarch_handle_model_attribute): Likewise.
2622 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
2623 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
2624 (symbolic_off64_or_reg_operand): Likewise.
2626 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2628 * config/loongarch/loongarch.cc (loongarch_load_tls):
2629 Load all types of tls symbols through one function.
2630 (loongarch_got_load_tls_gd): Delete.
2631 (loongarch_got_load_tls_ld): Delete.
2632 (loongarch_got_load_tls_ie): Delete.
2633 (loongarch_got_load_tls_le): Delete.
2634 (loongarch_call_tls_get_addr): Modify the called function name.
2635 (loongarch_legitimize_tls_address): Likewise.
2636 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
2637 (@load_tls<mode>): New template.
2638 (@got_load_tls_ld<mode>): Delete.
2639 (@got_load_tls_le<mode>): Delete.
2640 (@got_load_tls_ie<mode>): Delete.
2642 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
2644 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
2645 (loongarch_legitimize_address): Add logical transformation code.
2647 2024-02-01 Marek Polacek <polacek@redhat.com>
2649 * doc/invoke.texi: Update -Wdangling-reference documentation.
2651 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
2654 * config/i386/i386.md (*cmp<dwi>_doubleword):
2655 Do not force SUBREG pieces to pseudos.
2657 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
2659 * config/pa/pa.md (atomic_storedi_1): Fix bug in
2662 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
2664 * config/avr/avr.cc: Tabify.
2666 2024-02-01 Richard Ball <richard.ball@arm.com>
2668 PR tree-optimization/111268
2669 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
2670 Add variable-length check for vector input arguments
2673 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2675 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
2676 hard-code number of SGPR/VGPR/AVGPR registers.
2677 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
2678 SGPR/VGPR/AVGPR registers.
2680 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2682 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
2683 attribute, and include sifive-p600.md.
2684 * config/riscv/generic-ooo.md: Update type attribute.
2685 * config/riscv/generic.md: Update type attribute.
2686 * config/riscv/sifive-7.md: Update type attribute.
2687 * config/riscv/sifive-p600.md: New file.
2688 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
2689 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
2691 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
2692 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
2693 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
2695 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
2697 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
2698 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
2699 * config/riscv/riscv.opt: New macro for 7 new unprivileged
2701 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
2702 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
2704 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2706 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
2707 -static-libasan. Add missing whitespace.
2709 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2711 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
2712 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
2713 Don't 'define_constants'.
2715 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2717 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
2719 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
2721 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
2722 [TARGET_RDNA3]: Adjust.
2724 2024-02-01 Richard Biener <rguenther@suse.de>
2726 PR tree-optimization/113693
2727 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
2728 data when available.
2730 2024-02-01 Jakub Jelinek <jakub@redhat.com>
2731 Jason Merrill <jason@redhat.com>
2734 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
2735 on variables which were promoted to TREE_STATIC.
2737 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
2738 Richard Biener <rguenther@suse.de>
2741 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
2742 information via tree_non_zero_bits to check if this operand
2743 is suitably extended for a widening (or highpart) multiplication.
2744 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
2745 isn't already of the claimed type.
2747 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2750 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2752 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2753 (generic_ooo_branch): ditto
2754 * config/riscv/generic.md (generic_sfb_alu): ditto
2755 (generic_fmul_half): ditto
2756 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2757 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2758 (sifive_7_popcount): ditto
2759 * config/riscv/vector.md: change rdfrm to fmove
2760 * config/riscv/zc.md: change pushpop to load/store
2762 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2765 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2766 Robin Dapp <rdapp.gcc@gmail.com>
2768 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2769 (generic_ooo_vec_load): ditto
2770 (generic_ooo_vec_store): ditto
2771 (generic_ooo_vec_loadstore_seg): ditto
2772 (generic_ooo_vec_alu): ditto
2773 (generic_ooo_vec_fcmp): ditto
2774 (generic_ooo_vec_imul): ditto
2775 (generic_ooo_vec_fadd): ditto
2776 (generic_ooo_vec_fmul): ditto
2777 (generic_ooo_crypto): ditto
2778 (generic_ooo_perm): ditto
2779 (generic_ooo_vec_reduction): ditto
2780 (generic_ooo_vec_ordered_reduction): ditto
2781 (generic_ooo_vec_idiv): ditto
2782 (generic_ooo_vec_float_divsqrt): ditto
2783 (generic_ooo_vec_mask): ditto
2784 (generic_ooo_vec_vesetvl): ditto
2785 (generic_ooo_vec_setrm): ditto
2786 (generic_ooo_vec_readlen): ditto
2787 * config/riscv/riscv.md: include generic-vector-ooo
2788 * config/riscv/generic-vector-ooo.md: New file. to here
2790 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2793 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2795 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2797 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2799 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
2801 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2802 Robin Dapp <rdapp.gcc@gmail.com>
2804 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2805 (generic_ooo_vec_load): ditto
2806 (generic_ooo_vec_store): ditto
2807 (generic_ooo_vec_loadstore_seg): ditto
2808 (generic_ooo_vec_alu): ditto
2809 (generic_ooo_vec_fcmp): ditto
2810 (generic_ooo_vec_imul): ditto
2811 (generic_ooo_vec_fadd): ditto
2812 (generic_ooo_vec_fmul): ditto
2813 (generic_ooo_crypto): ditto
2814 (generic_ooo_perm): ditto
2815 (generic_ooo_vec_reduction): ditto
2816 (generic_ooo_vec_ordered_reduction): ditto
2817 (generic_ooo_vec_idiv): ditto
2818 (generic_ooo_vec_float_divsqrt): ditto
2819 (generic_ooo_vec_mask): ditto
2820 (generic_ooo_vec_vesetvl): ditto
2821 (generic_ooo_vec_setrm): ditto
2822 (generic_ooo_vec_readlen): ditto
2823 * config/riscv/riscv.md: include generic-vector-ooo
2824 * config/riscv/generic-vector-ooo.md: New file. to here
2826 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
2828 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2829 (generic_ooo_branch): ditto
2830 * config/riscv/generic.md (generic_sfb_alu): ditto
2831 (generic_fmul_half): ditto
2832 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2833 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
2834 (sifive_7_popcount): ditto
2835 * config/riscv/vector.md: change rdfrm to fmove
2836 * config/riscv/zc.md: change pushpop to load/store
2838 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
2841 * config/aarch64/aarch64-simd.md (split for movv8di):
2842 For strict aligned mode, use DImode instead of TImode.
2844 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
2846 PR middle-end/113607
2847 * match.pd: Make sure else values match when folding a
2848 vec_cond into a conditional operation.
2850 2024-01-31 Marek Polacek <polacek@redhat.com>
2852 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
2854 2024-01-31 Tamar Christina <tamar.christina@arm.com>
2855 Matthew Malcomson <matthew.malcomson@arm.com>
2858 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
2860 * builtins.cc (expand_builtin): Include HWASAN when checking for
2863 2024-01-31 Richard Biener <rguenther@suse.de>
2865 PR middle-end/110176
2866 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
2867 to match INTEGER_CST only without outstanding conversion.
2869 2024-01-31 Alex Coplan <alex.coplan@arm.com>
2872 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
2873 V16QImode for the full 16-byte FPR saves in the vector PCS case.
2875 2024-01-31 Richard Biener <rguenther@suse.de>
2877 PR tree-optimization/111444
2878 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
2879 vn_reference_lookup_2 when optimistically skipping may-defs.
2881 2024-01-31 Richard Biener <rguenther@suse.de>
2883 PR tree-optimization/113630
2884 * tree-ssa-pre.cc (compute_avail): Avoid registering a
2885 reference with a representation with not matching base
2888 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2890 PR rtl-optimization/113656
2891 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
2892 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
2894 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2897 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
2898 with BLKmode are larger than DWARF2_ADDR_SIZE.
2900 2024-01-31 Jakub Jelinek <jakub@redhat.com>
2902 PR tree-optimization/113639
2903 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2904 For VIEW_CONVERT_EXPR set rhs1 to its operand.
2906 2024-01-31 Richard Biener <rguenther@suse.de>
2908 PR tree-optimization/113670
2909 * tree-vect-data-refs.cc (vect_check_gather_scatter):
2910 Make sure we can take the address of the reference base.
2912 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
2914 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
2915 ATA5835, ATtiny64AUTO, ATA5700M322.
2916 * doc/avr-mmcu.texi: Rebuild.
2918 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2921 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
2924 2024-01-31 Alexandre Oliva <oliva@adacore.com>
2926 PR middle-end/112917
2927 PR middle-end/113100
2928 * builtins.cc (expand_builtin_stack_address): Use
2929 STACK_ADDRESS_OFFSET.
2930 * doc/extend.texi (__builtin_stack_address): Adjust.
2931 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
2932 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
2933 * doc/tm.texi: Rebuilt.
2935 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2938 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
2939 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
2940 (pre_vsetvl::compute_transparent): New function.
2941 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
2943 2024-01-30 Fangrui Song <maskray@google.com>
2946 * config/i386/constraints.md: Define constraint "Ws".
2947 * doc/md.texi: Document it.
2949 2024-01-30 Marek Polacek <polacek@redhat.com>
2953 * doc/invoke.texi: Update -Wdangling-reference description.
2955 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
2957 * config/xtensa/constraints.md (R, T, U):
2958 Change define_constraint to define_memory_constraint.
2959 * config/xtensa/predicates.md (move_operand): Don't check that a
2960 constant pool operand size is a multiple of UNITS_PER_WORD.
2961 * config/xtensa/xtensa.cc
2962 (xtensa_lra_p, TARGET_LRA_P): Remove.
2963 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
2964 clause as it can no longer be true.
2965 (fixup_subreg_mem): Drop function.
2966 (xtensa_output_integer_literal_parts): Consider 16-bit wide
2968 (xtensa_legitimate_constant_p): Add short-circuit path for
2969 integer load instructions. Don't check that mode size is
2970 at least UNITS_PER_WORD.
2971 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
2972 rather reload_in_progress and reload_completed.
2973 (doloop_end): Drop operand 2.
2974 (movhi_internal): Add alternative loading constant from a
2976 (define_split for DI register_operand): Don't limit to
2977 !TARGET_AUTO_LITPOOLS.
2978 * config/xtensa/xtensa.opt (mlra): Change to no effect.
2980 2024-01-30 Pan Li <pan2.li@intel.com>
2982 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
2983 calculate the gpr count required by vls mode.
2984 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
2985 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
2987 (riscv_get_arg_info): Add vls mode handling.
2988 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
2990 2024-01-30 Richard Biener <rguenther@suse.de>
2992 PR tree-optimization/113659
2993 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2994 Handle main exit without virtual use.
2996 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
2998 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3000 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
3003 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3004 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3005 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3006 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3007 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3008 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3010 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3013 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3014 Mark all registers that occur in addresses as needing a GPR.
3016 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
3019 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3020 the containing insn as an extra parameter. Reset debug instructions
3021 if they reference a register that is no longer used by real insns.
3022 (early_ra::apply_allocation): Update calls accordingly.
3024 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3026 PR tree-optimization/113603
3027 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
3028 count_nonzero_bytes call refetch si using get_strinfo in case it
3029 has been unshared in the meantime.
3031 2024-01-30 Jakub Jelinek <jakub@redhat.com>
3033 PR middle-end/101195
3034 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
3035 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
3037 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
3039 * config/riscv/thead.cc (th_print_operand_address): Change %ld
3042 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
3043 Manolis Tsamis <manolis.tsamis@vrull.eu>
3044 Philipp Tomsich <philipp.tomsich@vrull.eu>
3046 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
3047 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
3049 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
3050 Call on framework moved later.
3052 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
3054 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
3055 instruction in naked function epilogues.
3057 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
3060 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
3061 gcc_cv_as_mips_explicit_relocs.
3062 * configure: Regnerated.
3064 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
3067 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
3068 Correct generated RTL.
3069 (arm_rev16si2_alt1): Correctly handle conditional execution.
3070 (arm_rev16si2_alt2): Likewise.
3072 2024-01-29 Richard Biener <rguenther@suse.de>
3074 PR middle-end/113622
3075 * expr.cc (expand_assignment): Spill hard registers if
3076 we index them with a variable offset.
3078 2024-01-29 Richard Biener <rguenther@suse.de>
3080 PR middle-end/113622
3081 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
3082 Also allow DECL_HARD_REGISTER variables.
3084 2024-01-29 Alex Coplan <alex.coplan@arm.com>
3087 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
3088 Use iterate_safely when iterating over debug uses.
3089 (fixup_debug_uses): Likewise.
3090 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
3091 over nondebug insns instead of manually maintaining the next insn.
3092 * iterator-utils.h (class safe_iterator): New.
3093 (iterate_safely): New.
3095 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
3098 * config/i386/i386-options.cc (ix86_set_func_type): Save
3099 callee-saved registers in noreturn functions for -O0/-Og.
3101 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3104 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
3105 define for !TARGET_RDNA2_PLUS.
3107 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
3110 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
3111 workaround for right shifts.
3112 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
3113 (vect_determine_precisions_from_range): Be more selective about
3114 which codes can be narrowed based on their input and output ranges.
3115 For shifts, require at least one more bit of precision than the
3116 maximum shift amount.
3118 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3120 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
3122 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3124 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
3125 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
3128 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
3131 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
3132 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
3133 (SET_SRAM_ECC_UNSET): ... this.
3134 (copy_early_debug_info): Remove gfx900 special case, now handled as
3135 part of the generic handling.
3136 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
3138 2024-01-29 Jakub Jelinek <jakub@redhat.com>
3140 PR tree-optimization/110603
3141 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
3142 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
3143 overwritten anyway). Avoid creating invalid range with minlen
3144 larger than maxlen. Formatting fix.
3146 2024-01-29 Richard Biener <rguenther@suse.de>
3149 * tree-inline.cc (initialize_inlined_parameters): Reverse
3150 the decl chain of inlined parameters.
3152 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3154 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
3155 alignment of CFString constants by setting DECL_USER_ALIGN.
3157 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
3158 Jakub Jelinek <jakub@redhat.com>
3161 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
3162 and BUILT_IN_GCC_NESTED_PTR_DELETED.
3163 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
3164 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
3165 rename the library fallbacks to __gcc_nested_func_ptr_created and
3166 __gcc_nested_func_ptr_deleted.
3167 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
3168 and __gcc_nested_func_ptr_deleted.
3169 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
3170 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
3171 * tree.cc (build_common_builtin_nodes): Build the
3172 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
3173 builtins only for non-explicit.
3175 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
3177 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
3179 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3182 * config/i386/i386-options.cc (ix86_set_func_type): Don't
3183 save and restore callee saved registers for a noreturn function
3184 with nothrow or compiled with -fno-exceptions.
3186 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
3190 * config/i386/i386-expand.cc (ix86_expand_call): Replace
3191 no_caller_saved_registers check with call_saved_registers check.
3192 Clobber all registers that are not used by the callee with
3193 no_callee_saved_registers attribute.
3194 * config/i386/i386-options.cc (ix86_set_func_type): Set
3195 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
3196 noreturn function. Disallow no_callee_saved_registers with
3197 interrupt or no_caller_saved_registers attributes together.
3198 (ix86_set_current_function): Replace no_caller_saved_registers
3199 check with call_saved_registers check.
3200 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
3201 (ix86_handle_call_saved_registers_attribute): This.
3202 (ix86_gnu_attributes): Add
3203 ix86_handle_call_saved_registers_attribute.
3204 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
3205 no_caller_saved_registers check with call_saved_registers check.
3206 (ix86_function_ok_for_sibcall): Don't allow callee with
3207 no_callee_saved_registers attribute when the calling function
3208 has callee-saved registers.
3209 (ix86_comp_type_attributes): Also check
3210 no_callee_saved_registers.
3211 (ix86_epilogue_uses): Replace no_caller_saved_registers check
3212 with call_saved_registers check.
3213 (ix86_hard_regno_scratch_ok): Likewise.
3214 (ix86_save_reg): Replace no_caller_saved_registers check with
3215 call_saved_registers check. Don't save any registers for
3216 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
3217 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
3218 no_callee_saved_registers attribute is called.
3219 (find_drap_reg): Replace no_caller_saved_registers check with
3220 call_saved_registers check.
3221 * config/i386/i386.h (call_saved_registers_type): New enum.
3222 (machine_function): Replace no_caller_saved_registers with
3223 call_saved_registers.
3224 * doc/extend.texi: Document no_callee_saved_registers attribute.
3226 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3228 PR tree-optimization/113614
3229 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
3230 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
3231 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
3233 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3235 PR tree-optimization/113568
3236 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
3237 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
3238 in the widening extension checks.
3240 2024-01-27 Jakub Jelinek <jakub@redhat.com>
3242 * gimple-lower-bitint.cc (gimple_lower_bitint): For
3243 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
3245 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
3247 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
3248 the warning for an attribute-always_inline without inline declaration.
3250 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
3253 * genopinit.cc (main): Split init_all_optabs into functions
3254 of 1000 patterns each.
3256 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3258 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
3260 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
3261 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
3264 2024-01-26 Andrew Stubbs <ams@baylibre.com>
3266 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
3267 * config/gcn/gcn-valu.md (all_convert): New iterator.
3268 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
3269 define_expand, and rename the old one to ...
3270 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
3271 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
3272 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
3273 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
3274 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
3275 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
3276 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
3277 (<u>mulqihi3_scalar): Likewise.
3279 2024-01-26 Richard Biener <rguenther@suse.de>
3281 PR tree-optimization/113602
3282 * tree-data-ref.cc (dr_analyze_innermost): Fail when
3283 the base object isn't addressable.
3285 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
3287 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
3288 "--amdhsa-code-object-version=" argument.
3289 (ASM_SPEC): Use it; replace previous version of it.
3291 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3293 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
3294 (pre_vsetvl::emit_vsetvl): Ditto.
3296 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3298 * config/loongarch/lasx.md (vec_extract<mode>_0):
3299 New define_insn_and_split patten.
3301 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
3303 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
3305 2024-01-26 Li Wei <liwei@loongson.cn>
3307 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
3309 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3312 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
3314 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
3317 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
3318 undefined shift after the call to exact_log2.
3320 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
3323 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
3324 before taking the negative of it.
3326 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
3329 * lra-constraints.cc (curr_insn_transform): Change class even for
3330 spilled pseudo successfully matched with with NO_REGS.
3332 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
3335 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
3337 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
3340 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
3341 (aarch64_expand_epilogue): Use the new function.
3342 (aarch64_split_compare_and_swap): Likewise.
3343 (aarch64_split_atomic_op): Likewise.
3345 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
3347 PR middle-end/112971
3348 * fold-const.cc (simplify_const_binop): New function for binop
3349 simplification of two constant vectors when element-wise
3350 handling is not necessary.
3351 (const_binop): Call new function.
3353 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
3355 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
3356 * config/riscv/constraints.md: Likewise.
3357 * config/riscv/corev.def: Likewise.
3358 * config/riscv/corev.md: Likewise.
3359 * config/riscv/predicates.md: Likewise.
3360 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
3361 * config/riscv/riscv-ftypes.def: Likewise.
3362 * config/riscv/riscv.opt: Likewise.
3363 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
3364 * doc/extend.texi: Add XCVbitmanip builtin documentation.
3365 * doc/sourcebuild.texi: Likewise.
3367 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
3369 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
3371 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
3374 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
3375 (riscv_fntype_abi): Ditto.
3376 * config/riscv/riscv.opt: Ditto.
3378 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3380 PR middle-end/113574
3381 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
3382 count against TYPE_PRECISION rather than TYPE_SIZE.
3384 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3387 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
3388 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
3390 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3393 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
3394 whether each split instruction is a load that clobbers the source
3395 address. Emit that instruction last if so.
3397 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
3400 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
3402 (<optab><Vnarrowq><mode>2): Use it instead of generating a
3403 paradoxical subreg for the input.
3405 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3407 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
3408 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
3409 predecessors dump information.
3411 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3413 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
3414 redundant full available computation.
3415 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3417 2024-01-25 Jakub Jelinek <jakub@redhat.com>
3419 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
3420 * doc/rtl.texi (CONST_VECTOR): Likewise.
3422 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3424 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
3425 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
3426 (pass_vsetvl::execute): Ditto.
3427 * config/riscv/riscv.opt: Ditto.
3429 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
3431 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
3432 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
3434 2024-01-25 Richard Biener <rguenther@suse.de>
3436 PR tree-optimization/113576
3437 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
3438 exits with may_be_zero niters when its the last one.
3440 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
3442 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3443 For symbols of type tls, non-zero Offset is not generated.
3445 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
3447 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
3448 P9 with m32 and mpowerpc64.
3450 2024-01-25 liuhongt <hongtao.liu@intel.com>
3452 * config/i386/i386-options.cc (ix86_option_override_internal):
3453 Enable -mlam=u57 by default when compiled with
3454 -fsanitize=hwaddress.
3456 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
3458 * common/config/riscv/riscv-common.cc (riscv_implied_info):
3459 Remove {"ztso", "a"}.
3461 2024-01-24 Martin Jambor <mjambor@suse.cz>
3465 * cgraph.h (cgraph_edge): Add a parameter to
3466 redirect_call_stmt_to_callee.
3467 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
3468 parameter to modify_call.
3469 (ipa_release_ssas_in_hash): Declare.
3470 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
3471 parameter killed_ssas, pass it to padjs->modify_call.
3472 * ipa-param-manipulation.cc (purge_all_uses): New function.
3473 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
3474 Instead of substituting uses, invoke purge_all_uses. If
3475 hash of killed SSAs has not been provided, create a temporary one
3476 and release SSAs that have been added to it.
3477 (compare_ssa_versions): New function.
3478 (ipa_release_ssas_in_hash): Likewise.
3479 * tree-inline.cc (redirect_all_calls): Create
3480 id->killed_new_ssa_names earlier, pass it to edge redirection,
3482 (copy_body): Release SSAs in id->killed_new_ssa_names.
3484 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
3487 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
3488 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
3490 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
3493 * config/riscv/sfb.md: New splitters to rewrite single bit
3494 sign extension as the condition to SFB instructions.
3496 2024-01-24 Jan Hubicka <jh@suse.cz>
3499 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
3500 (fmin-function-alignment): New parameter.
3501 * doc/invoke.texi: (-fmin-function-alignment): Document.
3502 (-falign-functions,-falign-loops,-falign-labels): Mention that
3503 aglinments are ignored in cold code.
3504 * varasm.cc (assemble_start_function): Handle min-function-alignment.
3506 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3509 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
3511 * config/aarch64/iterators.md (VQDIV): Remove.
3512 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
3513 SVE_I_SIMD_DI): New.
3514 (VPRED, sve_lane_con): Add V4SI and V2DI.
3515 * config/aarch64/aarch64-sve.md (<optab><mode>3,
3516 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
3517 (mul<mode>3): New, split from <optab><mode>3.
3518 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
3519 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
3520 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
3521 SVE_FULL_HSDI_SIMD_DI.
3523 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3525 PR tree-optimization/113552
3526 * config/aarch64/aarch64.cc
3527 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
3529 2024-01-24 Martin Jambor <mjambor@suse.cz>
3532 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
3533 count is equal or greater than the limit. Use the limit from the
3536 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
3538 * configure.ac: Detect the explicit relocs support for
3539 mips, and define C macro MIPS_EXPLICIT_RELOCS.
3540 * config.in: Regenerated.
3541 * configure: Regenerated.
3542 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
3543 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
3544 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
3545 !TARGET_EXPLICIT_RELOCS instead of just set it.
3546 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
3547 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
3548 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
3549 and define -m(no-)explicit-relocs as aliases.
3551 2024-01-24 Alex Coplan <alex.coplan@arm.com>
3553 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3555 (-mlate-ldp-fusion): Likewise.
3557 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3559 * tree-vect-loop.cc (vect_get_vect_def,
3560 vect_create_epilog_for_reduction): Rename main_exit_p to
3563 2024-01-24 Tamar Christina <tamar.christina@arm.com>
3565 PR tree-optimization/113364
3566 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
3567 early exits then we must reduce from the first offset for all of them.
3569 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3572 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
3574 (get_bb_index): Ditto.
3575 (pre_vsetvl::compute_avl_def_data): Ditto.
3576 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
3577 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
3579 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
3580 Richard Sandiford <richard.sandiford@arm.com>
3583 * ccmp.cc (ccmp_candidate_p): Add outer argument.
3584 Allow if the outer is true and the lhs is used more
3586 (expand_ccmp_expr): Update call to ccmp_candidate_p.
3587 * expr.h (expand_expr_real_gassign): Declare.
3588 * expr.cc (expand_expr_real_gassign): New function, split out from...
3589 (expand_expr_real_1): ...here.
3590 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
3592 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3595 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
3596 (fixup_debug_use): New.
3597 (fixup_debug_uses_trailing_add): New.
3598 (fixup_debug_uses): New. Use it ...
3599 (ldp_bb_info::fuse_pair): ... here.
3600 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
3601 fix up debug uses of the base register that are affected by
3602 folding in the trailing add insn.
3604 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3607 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
3608 Update trailing nondebug uses of the base register in the case
3609 of cancelling writeback.
3611 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3614 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
3615 (debug_insn_use_iterator): New.
3616 (set_info::first_debug_insn_use): New.
3617 (set_info::debug_insn_uses): New.
3618 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
3619 (set_info::first_debug_insn_use): New.
3620 (set_info::debug_insn_uses): New.
3622 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3625 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
3626 Don't record hazards against the opposite insn in the pair.
3628 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3631 * config/aarch64/aarch64-ldp-fusion.cc
3632 (struct stp_change_builder): New.
3633 (decide_stp_strategy): Reanme to ...
3634 (try_repurpose_store): ... this.
3635 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
3636 construct stp changes. Fix up uses when inserting new stp insns.
3638 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3641 * rtl-ssa.h: Include hash-set.h.
3642 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
3643 new_sets parameter and use it to keep track of new user-created sets.
3644 (function_info::apply_changes_to_insn): Also call add_def on new sets.
3645 (function_info::change_insns): Add hash_set to keep track of new
3646 user-created defs. Plumb it through.
3647 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
3648 apply_changes_to_insn.
3650 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3653 * rtl-ssa/accesses.cc (function_info::create_use): New.
3654 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
3655 Ensure new uses end up referring to permanent defs.
3656 * rtl-ssa/functions.h (function_info::create_use): Declare.
3658 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3661 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
3662 to finalize_new_accesses from the backwards placement loop, run it
3663 forwards in a separate loop.
3665 2024-01-23 Richard Biener <rguenther@suse.de>
3667 PR tree-optimization/113552
3668 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
3669 floor_log2 instead of exact_log2 on the number of calls.
3671 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
3672 Jakub Jelinek <jakub@redhat.com>
3674 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
3677 2024-01-23 Richard Biener <rguenther@suse.de>
3679 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3680 Separate single and multi-exit case when creating PHIs between
3681 the main and epilogue.
3683 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
3686 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
3687 MODE_single variants of functions that don't take tuple arguments.
3689 2024-01-23 Alex Coplan <alex.coplan@arm.com>
3692 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
3693 Don't assert recog success, just punt if the writeback pair
3696 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3698 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
3699 ATTRIBUTE_UNUSED to decl.
3701 2024-01-23 Richard Biener <rguenther@suse.de>
3704 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
3705 handle unexpected but bogus DIE contexts when not checking
3708 2024-01-23 Jakub Jelinek <jakub@redhat.com>
3710 PR tree-optimization/113462
3711 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
3712 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
3713 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
3714 sizes between 129 and 8192 bytes.
3716 2024-01-23 Xi Ruoyao <xry111@xry111.site>
3718 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3719 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
3720 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
3721 (loongarch_call_tls_get_addr): Do not split symbols of
3722 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
3723 EXPLICIT_RELOCS_AUTO.
3725 2024-01-23 Richard Biener <rguenther@suse.de>
3727 * alias.cc (known_base_value_p): Remove.
3728 (find_base_value): Remove PLUS/MINUS handling
3729 when both operands are not CONST_INT_P.
3731 2024-01-23 Richard Biener <rguenther@suse.de>
3733 PR rtl-optimization/113255
3734 * alias.cc (find_base_term): Remove PLUS/MINUS handling
3735 when both operands are not CONST_INT_P.
3737 2024-01-23 Richard Biener <rguenther@suse.de>
3740 * dwarf2out.cc (dwarf2out_finish): Reset all type units
3741 for the fat part of an LTO compile.
3743 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
3745 * doc/sourcebuild.texi: Add attributes for keywords.
3747 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
3750 * doc/invoke.texi (Warning Options): Correct lists of options
3751 enabled by -Wall and -Wextra by checking against common.opt
3754 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
3757 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
3758 instead of cpu_optaliases.
3759 (check_arch): Use arch_opt_alias instead of arch_optaliases.
3761 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3763 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
3764 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
3765 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
3767 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3770 * config/riscv/riscv.md: Use reg instead of subreg.
3772 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
3775 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
3776 to match the compiler default.
3777 (simple_object_copy_lto_debug_sections): Never unlink the outfile
3778 on error as the caller does so.
3779 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
3780 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
3782 2024-01-22 Richard Biener <rguenther@suse.de>
3784 PR tree-optimization/113373
3785 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3786 Create LC PHIs in the exit blocks where necessary.
3787 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
3788 to handle missing LC PHIs.
3789 (find_connected_edge): Remove.
3790 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
3792 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3794 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
3796 2024-01-22 xuli <xuli1@eswincomputing.com>
3799 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
3800 (registered_function::overloaded_hash):refactor.
3801 (resolve_overloaded_builtin):avoid internal ICE.
3803 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
3807 * calls.cc (emit_library_call_value_1): Pass valid TYPE
3809 * expr.cc (emit_push_insn): Likewise.
3811 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3813 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
3814 correcction version of last change.
3816 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
3818 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
3819 fix bugs in signature.
3821 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
3822 Richard Biener <rguenther@suse.de>
3824 PR rtl-optimization/111267
3825 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
3826 profitable_p method to likely_profitable_p.
3827 (try_fwprop_subst_node): Update call to likely_profitable_p.
3828 Only bail-out early when !prop.likely_profitable_p for instructions
3829 that are not single sets. When comparing costs, bail-out if the
3830 cost is unchanged and !prop.likely_profitable_p.
3832 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3835 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
3836 isn't enabled by -Wunused unless -Wextra is provided, and that
3837 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
3838 -Wunused doesn't enable -Wunused-* options documented as behaving
3839 otherwise, and list them explicitly.
3841 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
3844 * doc/invoke.texi (Warning Options): Fix broken example and
3845 clean up/reorganize the others. Also describe what the short-form
3848 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
3851 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
3852 (Warning Options): Correct/edit discussion of -Warray-parameter
3853 to make the first example less confusing, and fill in missing info.
3855 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3857 PR tree-optimization/113462
3858 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
3859 Handle rhs1 INTEGER_CST like SSA_NAME.
3861 2024-01-20 Jakub Jelinek <jakub@redhat.com>
3863 PR tree-optimization/113491
3864 * tree-switch-conversion.cc (switch_conversion::build_constructors):
3865 If elt.index has precision higher than sizetype, fold_convert it to
3867 (switch_conversion::array_value_type): Return type if type is
3868 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
3869 (switch_conversion::build_arrays): Use unsigned_type_for rather than
3870 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
3871 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
3872 higher than sizetype, use sizetype as tidx type and fold_convert the
3873 subtraction to sizetype.
3875 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3877 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
3878 (riscv_vector_mode_supported_any_target_p): Ditto.
3880 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3883 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
3884 (TARGET_ZERO_CALL_USED_REGS): Define.
3886 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
3889 * config/m68k/m68k.cc (output_andsi3): Use QImode for
3890 address adjusted for 1-byte RMW access.
3891 (output_iorsi3): Likewise.
3892 (output_xorsi3): Likewise.
3894 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3896 * doc/invoke.texi (RISC-V Options): Add list of supported
3899 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3902 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
3903 (RVV_VUNDEF): Ditto.
3904 * config/riscv/riscv-vsetvl.cc: Add timevar.
3906 2024-01-19 Richard Biener <rguenther@suse.de>
3909 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
3910 an early DIE but there should be, do not pretend there is.
3912 2024-01-19 Richard Biener <rguenther@suse.de>
3914 PR tree-optimization/113494
3915 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3916 Handle endless loop on exit. Handle re-allocated PHI.
3918 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3920 PR tree-optimization/113464
3921 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
3922 optimize loads into GIMPLE_ASM stmts.
3924 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3926 PR tree-optimization/113463
3927 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
3928 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
3931 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3933 PR tree-optimization/113459
3934 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
3935 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
3936 of SCALAR_INT_TYPE_MODE if type has BLKmode.
3937 (vn_reference_lookup_3): Likewise. Formatting fix.
3939 2024-01-19 Jakub Jelinek <jakub@redhat.com>
3940 Richard Biener <rguenther@suse.de>
3942 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
3943 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
3944 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
3945 but adjust_address also for BLKmode mode and MEM op0.
3947 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
3949 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
3952 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3954 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
3956 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3958 * common/config/riscv/riscv-common.cc
3959 (riscv_subset_list::parse_std_ext): Remove.
3960 (riscv_subset_list::parse_multiletter_ext): Remove.
3961 * config/riscv/riscv-subset.h
3962 (riscv_subset_list::parse_std_ext): Remove.
3963 (riscv_subset_list::parse_multiletter_ext): Remove.
3965 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3967 * common/config/riscv/riscv-common.cc
3968 (riscv_subset_list::parse_single_std_ext): New parameter.
3969 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3970 (riscv_subset_list::parse_single_ext): Ditto.
3971 (riscv_subset_list::parse): Relax the order for the input of ISA
3973 * config/riscv/riscv-subset.h
3974 (riscv_subset_list::parse_single_std_ext): New parameter.
3975 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
3976 (riscv_subset_list::parse_single_ext): Ditto.
3978 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3980 * common/config/riscv/riscv-common.cc
3981 (riscv_subset_list::parse_base_ext): New.
3982 (riscv_subset_list::parse): Extract part of logic into
3983 riscv_subset_list::parse_base_ext.
3984 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
3987 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
3989 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
3992 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
3994 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
3997 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
4000 * doc/extend.texi (Common Variable Attributes): Explain what
4001 happens when multiple variables with cleanups are in the same scope.
4003 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4006 * doc/extend.texi (Common Function Attributes): Document that
4007 noinline also disables some interprocedural optimizations and
4008 improve flow to the part about using inline asm instead to
4009 disable calls from being optimized away completely. Remove the
4010 sentence that says noipa is mainly for internal compiler testing.
4012 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
4014 PR tree-optimization/69807
4015 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4017 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
4020 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4021 from x86 Windows Options.
4023 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4026 * doc/extend.texi (C Extensions): Add new section to menu.
4027 (Function Attributes): Move dangling index entries to....
4028 (Const and Volatile Functions): New section.
4030 2024-01-18 David Malcolm <dmalcolm@redhat.com>
4032 PR middle-end/112684
4033 * toplev.cc (toplev::main): Don't ICE in
4034 -fdiagnostics-generate-patch when exiting after options,
4035 since no edit context will have been created.
4037 2024-01-18 Richard Biener <rguenther@suse.de>
4039 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
4042 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4044 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
4045 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
4047 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4048 Jin Ma <jinma@linux.alibaba.com>
4049 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4050 Christoph Müllner <christoph.muellner@vrull.eu>
4052 * config/riscv/thead.cc
4053 (th_asm_output_opcode): Rewrite some instructions.
4055 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4056 Jin Ma <jinma@linux.alibaba.com>
4057 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4058 Christoph Müllner <christoph.muellner@vrull.eu>
4060 * config/riscv/riscv.md (none,thv,rvv): New attribute.
4061 (no,yes): Add an attribute to disable alternative
4062 for xtheadvector or RVV1.0.
4063 * config/riscv/vector.md:
4064 Disable alternatives that destination register overlaps
4065 source register group for xtheadvector.
4067 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4068 Jin Ma <jinma@linux.alibaba.com>
4069 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4070 Christoph Müllner <christoph.muellner@vrull.eu>
4072 * config/riscv/riscv-vector-builtins-bases.cc
4073 (class th_loadstore_width): Define new builtin bases.
4074 (class th_extract): Define new builtin bases.
4075 (BASE): Define new builtin bases.
4076 * config/riscv/riscv-vector-builtins-bases.h:
4077 Define new builtin class.
4078 * config/riscv/riscv-vector-builtins-shapes.cc
4079 (struct th_loadstore_width_def): Define new builtin shapes.
4080 (struct th_indexed_loadstore_width_def):
4081 Define new builtin shapes.
4082 (struct th_extract_def): Define new builtin shapes.
4083 (SHAPE): Define new builtin shapes.
4084 * config/riscv/riscv-vector-builtins-shapes.h:
4085 Define new builtin shapes.
4086 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
4087 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
4088 * config/riscv/riscv-vector-builtins.h
4089 (enum required_ext): Add new XTheadVector member.
4090 (struct function_group_info): Likewise.
4091 * config/riscv/t-riscv:
4092 Add thead-vector-builtins-functions.def
4093 * config/riscv/thead-vector.md
4094 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
4095 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
4096 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
4097 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
4098 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
4099 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
4100 (@pred_th_extract<mode>): Likewise.
4101 (*pred_th_extract<mode>): Likewise.
4102 * config/riscv/thead-vector-builtins-functions.def: New file.
4104 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4105 Jin Ma <jinma@linux.alibaba.com>
4106 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4107 Christoph Müllner <christoph.muellner@vrull.eu>
4109 * config.gcc: Add files for XTheadVector intrinsics.
4110 * config/riscv/autovec.md: Guard XTheadVector.
4111 * config/riscv/predicates.md: Disable immediate vl
4113 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
4114 Add pragma for XTheadVector.
4115 * config/riscv/riscv-string.cc (riscv_expand_block_move):
4117 * config/riscv/riscv-v.cc (vls_mode_valid_p):
4119 * config/riscv/riscv-vector-builtins-bases.cc:
4120 Do not normalize vsetvl instructions for XTheadVector.
4121 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
4122 New check type function.
4123 (build_one): Adjust for XTheadVector.
4124 * config/riscv/riscv-vector-switch.def (ENTRY):
4125 Disable fractional mode for the XTheadVector extension.
4126 (TUPLE_ENTRY): Likewise.
4127 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
4129 (riscv_preferred_simd_mode): Likewsie.
4130 (riscv_autovectorize_vector_modes): Likewise.
4131 (riscv_vector_mode_supported_any_target_p): Likewise.
4132 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
4133 * config/riscv/thead.cc (th_asm_output_opcode):
4134 Rewrite vsetvl instructions.
4135 * config/riscv/vector.md:
4136 Include thead-vector.md and change fractional LMUL
4138 * config/riscv/riscv_th_vector.h: New file.
4139 * config/riscv/thead-vector.md: New file.
4141 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4142 Jin Ma <jinma@linux.alibaba.com>
4143 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4144 Christoph Müllner <christoph.muellner@vrull.eu>
4146 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
4147 Add new function to add assembler insn code prefix/suffix.
4148 (th_asm_output_opcode):
4149 Add Thead function to add assembler insn code prefix/suffix.
4150 * config/riscv/riscv.cc (riscv_asm_output_opcode):
4151 Implement function to add assembler insn code prefix/suffix.
4152 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
4153 Add new function to add assembler insn code prefix/suffix.
4154 * config/riscv/thead.cc (th_asm_output_opcode):
4155 Implement Thead function to add assembler insn code
4158 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
4159 Jin Ma <jinma@linux.alibaba.com>
4160 Xianmiao Qu <cooper.qu@linux.alibaba.com>
4161 Christoph Müllner <christoph.muellner@vrull.eu>
4163 * common/config/riscv/riscv-common.cc
4164 (riscv_subset_list::parse): Add new vendor extension.
4165 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
4167 * config/riscv/riscv.opt: Add new mask.
4169 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4171 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
4172 to be conditional on macosx-version-min.
4174 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4176 * config/darwin.cc (darwin_objc1_section): Use the correct
4177 meta-data version for constant strings.
4178 (machopic_select_section): Assert if we fail to handle CFString
4179 sections as Obejctive-C meta-data or drectly.
4181 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4183 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
4184 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
4185 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
4186 versions when the object format is Mach-O.
4188 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
4191 * config/darwin.cc (machopic_select_section): Handle C and C++
4193 (darwin_rename_builtins): Move this out of the CFString code.
4194 (darwin_libc_has_function): Likewise.
4195 (darwin_build_constant_cfstring): Create an anonymous var to
4197 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
4200 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4203 * haifa-sched.cc (dep_list_size): Make global.
4204 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
4205 * sched-int.h (dep_list_size): Declare.
4207 2024-01-18 Martin Jambor <mjambor@suse.cz>
4209 PR tree-optimization/110422
4210 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
4213 2024-01-18 Richard Biener <rguenther@suse.de>
4215 PR tree-optimization/113475
4216 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
4217 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
4218 (phi_analyzer::~phi_analyzer): Deallocate and free collected
4220 (phi_analyzer::process_phi): Record allocated phi_groups.
4222 2024-01-18 Richard Biener <rguenther@suse.de>
4224 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
4225 storage for gvec_oprnds elements.
4227 2024-01-18 Richard Biener <rguenther@suse.de>
4229 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
4230 prefer all later exits we can handle.
4231 (vect_analyze_loop_form): Free the allocated loop body.
4234 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4236 * config/avr/avr-log.cc: Tabify.
4238 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4240 * config/riscv/autovec.md: Support vi variant.
4242 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4244 * config/avr/avr-devices.cc: Tabify.
4246 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4248 * config/avr/avr-c.cc: Tabify.
4250 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4252 * config/avr/driver-avr.cc: Tabify.
4254 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4256 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
4258 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4260 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
4262 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4264 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
4265 minline-strcmp, minline-strncmp, minline-strlen,
4266 -param=riscv-vector-abi): Remove Bool keywords.
4268 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4271 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
4272 support. Add missing space after , in emitted assembly in some
4273 cases. Formatting fixes.
4275 2024-01-18 Xi Ruoyao <xry111@xry111.site>
4277 * config/loongarch/loongarch.md (movsi_internal): Remove
4280 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
4282 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
4283 in the diagnostic, and capitalize the device name.
4284 (print_mcu): Generate specs such that:
4285 <*check_rodata_in_ram>: New.
4286 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
4287 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
4288 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
4290 2024-01-18 Jakub Jelinek <jakub@redhat.com>
4293 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
4294 Common and Optimization.
4296 2024-01-18 Richard Biener <rguenther@suse.de>
4298 PR tree-optimization/113431
4299 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
4300 When there is an invariant load we might not preserve
4303 2024-01-18 Richard Biener <rguenther@suse.de>
4305 PR tree-optimization/113374
4306 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
4307 * tree-vect-loop.cc (move_early_exit_stmts): Update
4309 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4310 Refactor. Preserve virtual LC PHIs on all exits.
4312 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
4314 * config/loongarch/loongarch.cc (loongarch_split_symbol):
4315 Assign the '/u' attribute to the mem.
4317 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4319 PR middle-end/110847
4320 * doc/invoke.texi (Option Summary): Document negative forms of
4321 -Wtsan and -Wxor-used-as-pow.
4322 (Warning Options): Likewise.
4324 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4327 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
4329 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
4331 * doc/extend.texi (Common Function Attributes): Re-alphabetize
4333 (Common Variable Attributes): Likewise.
4334 (Common Type Attributes): Likewise.
4336 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4338 PR middle-end/111659
4339 * doc/extend.texi (Common Variable Attributes): Fix long lines
4340 in documentation of strict_flex_array + other minor copy-editing.
4341 Add a cross-reference to -Wstrict-flex-arrays.
4342 * doc/invoke.texi (Option Summary): Fix whitespace in tables
4343 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
4344 (C Dialect Options): Combine the docs for the two
4345 -fstrict-flex-arrays forms into a single entry. Note this option
4346 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
4347 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
4348 Minor copy-editing. Add cross references to the strict_flex_array
4349 attribute and -fstrict-flex-arrays option. Add note that this
4350 option depends on -ftree-vrp.
4352 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
4355 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
4356 only allow REG operands instead of allowing all.
4358 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4360 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
4361 Remove redundant checks in else condition for readablity.
4362 (earliest_fuse_vsetvl_info) Print iteration count in debug
4364 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
4365 dump details in certain cases.
4367 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
4369 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
4370 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
4371 * config/riscv/riscv-vsetvl.cc
4372 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
4373 (pass_vsetvl::execute): Use vsetvl_strategy.
4375 2024-01-17 Jan Hubicka <jh@suse.cz>
4377 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
4378 accidental hack reseting offset.
4380 2024-01-17 Jan Hubicka <jh@suse.cz>
4382 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
4383 handling of X86_TUNE_AVOID_512FMA_CHAINS.
4385 2024-01-17 Jan Hubicka <jh@suse.cz>
4386 Jakub Jelinek <jakub@redhat.com>
4388 PR tree-optimization/110852
4389 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
4391 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
4392 PRED_COMBINED_VALUE_PREDICTIONS_PHI
4393 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
4394 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
4396 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4398 PR tree-optimization/113421
4399 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
4401 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
4402 formatting. Start at vop rather than cvop even if stmt is a store
4403 and needs_operand_addr.
4405 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4407 PR middle-end/113410
4408 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
4409 If access_nelts is integral with larger precision than sizetype,
4410 fold_convert it to sizetype.
4412 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4414 PR tree-optimization/113408
4415 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
4416 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
4419 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4421 PR middle-end/113406
4422 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
4423 regardless of whether is_gimple_reg_type (restype) or not.
4425 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4427 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
4428 funcions -> functions, and use were instead of was.
4429 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
4430 and guaranteee -> guarantee.
4431 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
4433 2024-01-17 Jakub Jelinek <jakub@redhat.com>
4435 PR middle-end/113409
4436 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
4438 (omp_extract_for_data): Use build_bitint_type rather than
4439 build_nonstandard_integer_type if either iter_type or loop->v type
4441 * omp-expand.cc (expand_omp_for_generic,
4442 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
4443 BITINT_TYPE like INTEGER_TYPE.
4445 2024-01-17 Richard Biener <rguenther@suse.de>
4447 PR tree-optimization/113371
4448 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
4449 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4450 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
4451 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
4453 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
4455 PR rtl-optimization/96388
4456 PR rtl-optimization/111554
4457 * sched-deps.cc (find_inc): Avoid exponential behavior.
4459 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4462 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
4463 from C++ Language Options to Warning Options. Add entry for
4465 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
4467 (Warning Options): ...to here. Minor copy-editing to fix typo
4470 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
4472 * config/mips/mips.cc (mips_compute_frame_info): If another
4473 register is used as global_pointer, mark $GP live false.
4475 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
4478 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
4479 give the section a light copy-editing pass.
4481 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4483 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
4484 * config/aarch64/aarch64-tune.md: Regenerated.
4485 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
4487 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
4490 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
4491 badly formed CONST expressions.
4493 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4495 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
4497 2024-01-16 Daniel Cederman <cederman@gaisler.com>
4499 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
4500 * config/sparc/sync.md (membar_storeload): Turn into named insn
4501 and add GR712RC errata workaround.
4502 (membar_v8): Add GR712RC errata workaround.
4504 2024-01-16 Andreas Larsson <andreas@gaisler.com>
4506 * config/sparc/sync.md (*membar_storeload_leon3): Remove
4507 (*membar_storeload): Enable for LEON
4509 2024-01-16 Jakub Jelinek <jakub@redhat.com>
4511 PR tree-optimization/113372
4513 PR middle-end/110115
4514 PR middle-end/111422
4515 * cfgexpand.cc (add_scope_conflicts_2): New function.
4516 (add_scope_conflicts_1): Use it.
4518 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
4520 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
4521 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
4522 * doc/avr-mmcu.texi: Regenerate.
4524 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
4526 PR tree-optimization/113091
4527 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
4528 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
4529 scalar use with new function.
4530 (vect_bb_slp_mark_live_stmts): New function as entry to existing
4531 overriden functions with same name.
4532 (vect_slp_analyze_operations): Call new entry function to mark
4535 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4538 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
4539 for RVV in big-endian mode.
4541 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
4543 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
4544 (riscv_pass_in_vector_p): Delete.
4545 (riscv_init_cumulative_args): Delete the checking.
4546 (riscv_get_arg_info): Delete the checking.
4547 (riscv_function_value): Delete the checking.
4548 * config/riscv/riscv.h: Delete the member for checking.
4550 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4552 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
4554 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4556 * config.gcc: Include riscv_bitmanip.h.
4557 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
4558 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
4559 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
4560 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
4561 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
4562 * config/riscv/riscv-ftypes.def (2): New ftypes.
4563 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
4564 (RISCV_BUILTIN_NO_PREFIX): Likewise.
4565 * config/riscv/riscv_bitmanip.h: New file.
4567 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
4569 * config.gcc: Include riscv_crypto.h.
4570 * config/riscv/riscv_crypto.h: New file.
4572 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
4574 PR middle-end/113354
4575 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
4576 in the insn if the corresponding operand does not require hard
4579 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
4582 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
4583 * config/avr/driver-avr.cc (avr_no_devlib): New function.
4584 (avr_devicespecs_file): Use it to remove -nodevicelib from the
4585 options for cores only.
4586 * config/avr/avr-arch.h (avr_get_parch): New prototype.
4587 * config/avr/avr-devices.cc (avr_get_parch): New function.
4589 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4592 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
4593 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
4594 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
4596 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4599 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
4600 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
4601 * config/riscv/riscv-vector-costs.h: New function.
4603 2024-01-15 Richard Biener <rguenther@suse.de>
4605 PR tree-optimization/113385
4606 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4607 First redirect, then split the exit edge.
4609 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4611 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
4612 Remove m_num_vector_iterations.
4613 * config/riscv/riscv-vector-costs.h: Ditto.
4615 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
4618 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
4619 (-mbranch-cost): Set "Optimization" flag.
4621 2024-01-15 Jakub Jelinek <jakub@redhat.com>
4623 PR tree-optimization/113370
4624 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
4625 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
4626 set it to just prec % limb_prec.
4628 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4631 * config/riscv/vector.md: Fix ternary attributes.
4633 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
4636 * configure.ac [target=avr]: Check availability of emulations
4637 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
4638 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
4639 * configure: Regenerate.
4640 * config.in: Regenerate.
4641 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
4642 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
4643 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
4644 * config/avr/avr-arch.h (enum avr_device_specific_features):
4646 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
4648 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
4649 (avr_set_core_architecture): Set avr_arch_index.
4650 (have_avrxmega2_flmap, have_avrxmega4_flmap)
4651 (have_avrxmega3_rodata_in_flash): Set new static const bool according
4652 to configure results.
4653 (avr_rodata_in_flash_p): New function using them.
4654 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
4655 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
4656 (avr_asm_named_section): Track avr_has_rodata_p.
4657 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
4658 and not avr_rodata_in_flash_p ().
4659 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
4660 (LINK_SPEC): Add %(link_rodata_in_ram).
4661 (LINK_ARCH_SPEC): Remove.
4662 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
4663 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
4664 const bool according to configure results.
4665 (diagnose_mrodata_in_ram): New function.
4666 (print_mcu): Generate specs with the following changes:
4667 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
4668 need to extend avr/specs.h each time we add a new bell or whistle.
4669 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
4670 -m[no-]rodata-in-ram.
4671 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
4672 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
4673 <*cpp>: Add %(cpp_rodata_in_ram).
4674 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
4676 <*self_spec>: Add -mflmap or %<mflmap as needed.
4678 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
4680 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
4681 not the GPR iterator. Adjust pattern name and mode attribute
4684 2024-01-13 Jakub Jelinek <jakub@redhat.com>
4686 PR tree-optimization/113361
4687 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
4688 Fix up determination of the type for > limb_prec constants.
4690 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4692 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
4693 Add web-link to the avr-gcc wiki.
4695 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4697 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
4698 documentation for a version without argument, which is not supported.
4700 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4702 * config/arm/arm_neon.h
4703 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
4704 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
4705 (vld1_f16_x4, vld1_f32_x4): New.
4706 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
4707 (vld1_bf16_x4): New.
4708 (vld1q_types_x4): Updated to use vld1q_x4
4709 from arm_neon_builtins.def
4710 * config/arm/arm_neon_builtins.def
4711 (vld1_x4): Updated entries.
4712 (vld1q_x4): New entries, but comes from the old vld1_x4
4713 * config/arm/neon.md
4714 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
4716 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4718 * config/arm/arm_neon.h
4719 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
4720 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
4721 (vld1_f16_x3, vld1_f32_x3): New.
4722 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
4723 (vld1_bf16_x3): New.
4724 (vld1q_types_x3): Updated to use vld1q_x3 from
4725 arm_neon_builtins.def
4726 * config/arm/arm_neon_builtins.def
4727 (vld1_x3): Updated entries.
4728 (vld1q_x3): New entries, but comes from the old vld1_x2
4729 * config/arm/neon.md
4730 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
4732 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4734 * config/arm/arm_neon.h
4735 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
4736 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
4737 (vld1_f16_x2, vld1_f32_x2): New.
4738 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
4739 (vld1_bf16_x2): New.
4740 (vld1q_types_x2): Updated to use vld1q_x2 from
4741 arm_neon_builtins.def
4742 * config/arm/arm_neon_builtins.def
4743 (vld1_x2): Updated entries.
4744 (vld1q_x2): New entries, but comes from the old vld1_x2
4745 * config/arm/neon.md
4746 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4749 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4751 * config/arm/arm_neon.h
4752 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
4753 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
4754 (vst1q_f16_x4, vst1q_f32_x4): New.
4755 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
4756 (vst1q_bf16_x4): New.
4757 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
4758 * config/arm/neon.md
4759 (neon_vst1q_x4<mode>): New.
4760 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
4761 * config/arm/unspecs.md
4762 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
4764 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4766 * config/arm/arm_neon.h
4767 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
4768 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
4769 (vst1q_f16_x3, vst1q_f32_x3): New.
4770 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
4771 (vst1q_bf16_x3): New.
4772 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
4773 * config/arm/neon.md
4774 (neon_vst1q_x3<mode>): New.
4775 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
4776 * config/arm/unspecs.md
4777 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
4779 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4781 * config/arm/arm_neon.h
4782 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
4783 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
4784 (vst1q_f16_x2, vst1q_f32_x2): New.
4785 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
4786 (vst1q_bf16_x2): New.
4787 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
4788 * config/arm/neon.md
4789 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
4791 * config/arm/iterators.md
4792 (VMEMX2): New mode iterator.
4793 (VMEMX2_q): New mode attribute.
4795 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4797 * config/arm/arm_neon.h
4798 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
4799 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
4800 (vst1_f16_x4, vst1_f32_x4): New.
4801 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
4802 (vst1_bf16_x4): New.
4803 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
4804 * config/arm/neon.md (vst1_x4<mode>): New.
4806 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4808 * config/arm/arm_neon.h
4809 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
4810 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
4811 (vst1_f16_x3, vst1_f32_x3): New.
4812 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
4813 (vst1_bf16_x3): New.
4814 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
4815 * config/arm/neon.md (vst1_x3<mode>): New.
4817 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4819 * config/arm/arm_neon.h
4820 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
4821 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
4822 (vst1_f16_x2, vst1_f32_x2): New.
4823 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
4824 (vst1_bf16_x2): New.
4825 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
4826 * config/arm/neon.md (vst1_x2<mode>): New.
4828 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4830 * config/arm/arm_neon.h
4831 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
4832 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
4833 (vld1q_f16_x4, vld1q_f32_x4): New.
4834 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
4835 (vld1q_bf16_x4): New.
4836 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
4837 * config/arm/neon.md
4838 (neon_vld1_x4<mode>): New.
4839 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
4840 * config/arm/unspecs.md
4841 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
4843 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4845 * config/arm/arm_neon.h
4846 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
4847 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
4848 (vld1q_f16_x3, vld1q_f32_x3): New.
4849 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
4850 (vld1q_bf16_x3): New.
4851 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
4852 * config/arm/neon.md
4853 (neon_vld1_x3<mode>): New.
4854 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
4855 * config/arm/unspecs.md
4856 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
4858 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
4860 * config/arm/arm_neon.h
4861 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
4862 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
4863 (vld1q_f16_x2, vld1q_f32_x2): New.
4864 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
4865 (vld1q_bf16_x2): New.
4866 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
4867 * config/arm/neon.md (vld1_x2<mode>): New.
4869 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4871 PR tree-optimization/113287
4872 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
4874 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4876 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
4877 * tree-vect-loop.cc (vect_transform_loop): Likewise.
4879 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4881 PR tree-optimization/113178
4882 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
4885 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4887 PR tree-optimization/113237
4888 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
4889 existing LCSSA variable for exit when all exits are early break.
4891 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4893 PR tree-optimization/113137
4894 PR tree-optimization/113136
4895 PR tree-optimization/113172
4896 PR tree-optimization/113178
4897 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4898 Maintain PHIs on inverted loops.
4899 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
4900 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
4902 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
4904 2024-01-12 Tamar Christina <tamar.christina@arm.com>
4906 PR tree-optimization/113135
4907 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
4908 dependency analysis.
4910 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
4912 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
4913 diagnostics class member name for abort of error.
4915 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
4917 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
4918 format string to %s argument.
4920 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
4921 Jakub Jelinek <jakub@redhat.com>
4923 PR middle-end/113182
4924 * varasm.cc (process_pending_assemble_externals,
4925 assemble_external_libcall): Use targetm.strip_name_encoding
4926 before calling get_identifier.
4928 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4931 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
4932 New member variable.
4933 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
4935 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
4936 * config/aarch64/aarch64-simd.md
4937 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
4938 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
4939 zip2 for zero-extends to...
4940 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
4941 instruction. Fix big-endian handling.
4942 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
4943 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
4944 zip1 for zero-extends to...
4945 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
4946 Fix big-endian handling.
4947 (*aarch64_zip1_uxtl): New pattern.
4948 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
4949 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
4950 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
4951 (aarch64_gen_shareable_zero): Use it.
4952 (aarch64_split_simd_shift_p): New function.
4954 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4956 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
4957 (function_beg_insn): New macro.
4958 * function.cc (expand_function_start): Initialize function_beg_insn.
4960 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4963 * config/aarch64/aarch64-sve-builtins.h
4964 (function_builder::m_overload_names): Replace with...
4965 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
4967 (add_overloaded_function): Update accordingly, using get_identifier
4968 to get a GGC-friendly record of the name.
4970 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
4973 * config/aarch64/aarch64-sve-builtins.def: Don't include
4974 aarch64-sve-builtins-sme.def.
4975 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
4976 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
4977 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
4978 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
4979 requires AARCH64_FL_SME2.
4980 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
4981 AARCH64_FL_SME adjustment here.
4982 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
4983 include SME intrinsics.
4984 (sme_function_groups): New array.
4985 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
4986 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
4988 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4991 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
4992 (struct cpu_vector_cost): Add regmove struct.
4993 (get_vector_costs): Export as global.
4994 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
4995 (costs::add_stmt_cost): Ditto.
4996 * config/riscv/riscv.cc (get_common_costs): Export global function.
4998 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5000 PR tree-optimization/113334
5001 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5002 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5003 to determine if number should be extended by all ones rather than zero
5006 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5008 PR tree-optimization/113330
5009 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5012 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5014 PR tree-optimization/113323
5015 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5016 check for lhs being large/huge _BitInt not in m_names.
5018 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5020 PR tree-optimization/113316
5021 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5022 uninitialized large/huge _BitInt arguments to calls.
5024 2024-01-12 Jakub Jelinek <jakub@redhat.com>
5026 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
5027 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
5028 CEIL (TYPE_PRECISION (t), limb_prec).
5029 (bitint_large_huge::handle_cast): Likewise.
5031 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
5034 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5035 Use assemble_function_label_final () for Power ELF V1 ABI.
5036 * output.h (assemble_function_label_final): New function.
5037 * varasm.cc (assemble_function_label_raw): Use
5038 assemble_function_label_final ().
5039 (assemble_function_label_final): New function.
5041 2024-01-12 Richard Biener <rguenther@suse.de>
5043 PR middle-end/113344
5044 * match.pd ((double)float CMP (double)float -> float CMP float):
5045 Perform result type check only for vectors.
5046 * fold-const.cc (fold_binary_loc): Likewise.
5048 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5050 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
5051 (usdot_prod<mode>): Ditto.
5052 (sdot_prod<mode>): Ditto.
5053 (udot_prod<mode>): Ditto.
5055 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
5058 * config/i386/i386-c.cc (ix86_target_macros_internal):
5059 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
5061 2024-01-12 Richard Biener <rguenther@suse.de>
5064 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
5065 Do not generate code when d.testing_p.
5067 2024-01-12 liuhongt <hongtao.liu@intel.com>
5070 * doc/invoke.texi (fcf-protection=): Update documents.
5072 2024-01-12 Pan Li <pan2.li@intel.com>
5074 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
5075 comments of predicate func riscv_v_ext_mode_p.
5077 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
5079 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
5080 Modify ABI-name length of vfloat16m8_t
5082 2024-01-12 Li Wei <liwei@loongson.cn>
5084 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
5087 2024-01-12 Li Wei <liwei@loongson.cn>
5089 * config/loongarch/loongarch.md (add<mode>3): Removed.
5093 (*addsi3_extended): Removed.
5094 (addsi3_extended): New.
5096 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
5098 * config/riscv/thead.md: Add limits for splits.
5100 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5102 PR middle-end/113322
5103 * expr.cc (do_store_flag): Don't try single bit tests with
5104 comparison on vector types.
5106 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
5108 PR tree-optimization/113301
5109 * match.pd (`1/x`): Delay signed case until late.
5111 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5113 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
5115 (AVR Internal Options): ...this new @subsubsection.
5117 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
5119 PR rtl-optimization/112918
5120 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
5121 (in_class_p): Restrict condition for narrowing class in case of
5122 allow_all_reload_class_changes_p.
5123 (process_alt_operands): Try to match operand without and with
5124 narrowing reg class. Discourage narrowing the class. Finish insn
5125 matching only if there is no class narrowing.
5126 (curr_insn_transform): Pass true to in_class_p for reg operand win.
5128 2024-01-11 Richard Biener <rguenther@suse.de>
5130 PR tree-optimization/112505
5131 * tree-vect-loop.cc (vectorizable_induction): Reject
5132 bit-precision induction.
5134 2024-01-11 Richard Biener <rguenther@suse.de>
5136 PR tree-optimization/113126
5137 * match.pd ((double)float CMP (double)float -> float CMP float):
5138 Make sure the boolean type is the same.
5139 * fold-const.cc (fold_binary_loc): Likewise.
5141 2024-01-11 Richard Biener <rguenther@suse.de>
5143 PR tree-optimization/112636
5144 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
5145 estimate_numbers_of_iterations before querying
5146 get_max_loop_iterations_int.
5147 (pass_ch::execute): Initialize SCEV and loops appropriately.
5149 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
5151 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
5153 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
5154 * doc/extend.texi (AVR Variable Attributes): Improve documentation
5155 of io, io_low and address attributes.
5156 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
5157 * doc/avr-mmcu.texi: Rebuild.
5159 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
5162 * config/loongarch/genopts/loongarch.opt.in: Mark options with
5163 the "Save" property.
5164 * config/loongarch/loongarch.opt: Same.
5165 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
5166 according to la_target.
5167 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
5168 RESTORE} for the la_target structure; Rename option conditions
5169 to have the same "la_" prefix.
5170 * config/loongarch/loongarch.h: Same.
5172 2024-01-11 Pan Li <pan2.li@intel.com>
5174 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
5175 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
5177 2024-01-11 Alex Coplan <alex.coplan@arm.com>
5180 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
5181 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
5182 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
5183 synthesize these if needed. Update caller ...
5184 (ldp_bb_info::fuse_pair): ... here.
5185 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
5186 and either insn is frame-related.
5187 (find_trailing_add): Punt on frame-related insns.
5188 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
5189 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
5191 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
5193 * config/mips/mips.cc (mips_start_function_definition):
5194 Add ATTRIBUTE_UNUSED.
5196 2024-01-11 Richard Biener <rguenther@suse.de>
5198 PR middle-end/112740
5199 * expr.cc (store_constructor): Check the integer vector
5200 mask has a single bit per element before using sign-extension
5201 to expand an uniform vector.
5203 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5205 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
5206 preempt VLS on unknown NITERS loop.
5208 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
5210 * doc/invoke.texi: Add -mevex512.
5212 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
5214 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
5215 (*nor<mode>3): Likewise.
5216 (nor<mode>3): Likewise.
5217 (*negsi2_extended): New template.
5218 (*<optab>si3_internal): Likewise.
5219 (*one_cmplsi2_internal): Likewise.
5220 (*norsi3_internal): Likewise.
5221 (*<optab>nsi_internal): Likewise.
5222 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
5223 modified bit operation to make the optimization work.
5225 2024-01-11 liuhongt <hongtao.liu@intel.com>
5228 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
5230 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5232 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
5233 (get_vector_costs): Ditto.
5234 (riscv_builtin_vectorization_cost): Ditto.
5236 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5238 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
5240 2024-01-10 Antoni Boucher <bouanto@zoho.com>
5243 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
5244 ipa_free_size_summary.
5245 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
5246 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
5247 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
5248 * ipa-prop.h (ipa_prop_cc_finalize): New function.
5249 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
5250 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
5251 ipa_sra_cc_finalize): New functions.
5252 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
5253 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
5255 Include ipa-utils.h.
5257 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
5259 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
5260 (th_int_get_save_adjustment): Likewise.
5261 (th_int_adjust_cfi_prologue): Likewise.
5262 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
5263 (TH_INT_INTERRUPT): New macro.
5264 (riscv_expand_prologue): Add the processing of XTheadInt.
5265 (riscv_expand_epilogue): Likewise.
5266 * config/riscv/riscv.h (BITSET_P): Moved to here.
5267 * config/riscv/riscv.md: New unspec.
5268 * config/riscv/thead.cc (th_int_get_mask): New function.
5269 (th_int_get_save_adjustment): Likewise.
5270 (th_int_adjust_cfi_prologue): Likewise.
5271 * config/riscv/thead.md (th_int_push): New pattern.
5272 (th_int_pop): new pattern.
5274 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5276 PR tree-optimization/112468
5277 * doc/sourcebuild.texi: Document ifn_copysign.
5278 * match.pd: Only apply transformation if target supports the IFN.
5280 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
5282 PR tree-optimization/112581
5283 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
5284 mark_ssa_maybe_undefs.
5285 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
5286 variables can not be reassociated.
5287 (init_range_entry): Check for uninitialized variables too.
5288 (init_reassoc): Call mark_ssa_maybe_undefs.
5290 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
5292 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
5293 Also handle sign extension.
5295 2024-01-10 Alex Coplan <alex.coplan@arm.com>
5297 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5299 (-mlate-ldp-fusion): Likewise.
5301 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5303 PR tree-optimization/113287
5304 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
5305 instead of using BRANCH_EDGE to determine true edge.
5307 2024-01-10 Richard Biener <rguenther@suse.de>
5309 PR tree-optimization/113078
5310 * tree-vect-loop.cc (check_reduction_path): Canonicalize
5311 .COND_SUB to .COND_ADD.
5313 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5315 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
5316 Handle prefix mappings before calling find_opt.
5317 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
5318 "-fno-"-prefixed command-line option.
5319 * opts-common.cc (get_option_prefix_remapping): New.
5320 * opts.h (get_option_prefix_remapping): New decl.
5322 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5324 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
5325 m_urlifier to pp_output_formatted_text.
5326 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
5327 (obstack_append_string): New overload, taking a length.
5328 (urlify_quoted_string): Pass in an obstack ptr, rather than using
5329 that of the pp's buffer. Generalize to handle trailing text in
5330 the buffer beyond the run of quoted text.
5331 (class quoting_info): New.
5332 (on_begin_quote): New.
5333 (on_end_quote): New.
5334 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
5335 it to calls to on_begin_quote and on_end_quote.
5336 (struct auto_obstack): New.
5337 (quoting_info::handle_phase_3): New.
5338 (pp_output_formatted_text): Add urlifier param. Use it if there
5339 is deferred urlification. Delete m_quotes.
5340 (selftest::pp_printf_with_urlifier): Pass urlifier to
5341 pp_output_formatted_text.
5342 (selftest::test_urlification): Update results for the existing
5343 case of quoted text stradding chunks; add more such test cases.
5344 * pretty-print.h (class quoting_info): New forward decl.
5345 (chunk_info::m_quotes): New field.
5346 (pp_output_formatted_text): Add optional urlifier param.
5348 2024-01-10 David Malcolm <dmalcolm@redhat.com>
5350 * pretty-print.cc (selftest::test_pp_format): Add selftest
5351 coverage for numbered args.
5353 2024-01-10 Tamar Christina <tamar.christina@arm.com>
5355 PR tree-optimization/113144
5356 PR tree-optimization/113145
5357 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5358 Update all BB that the original exits dominated.
5360 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
5362 * dwarf2out.cc (modified_type_die): Extend the support of reverse
5363 storage order to enumeration types if -gstrict-dwarf is not passed.
5364 (gen_enumeration_type_die): Add REVERSE parameter and generate the
5365 DIE immediately after the existing one if it is true.
5366 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
5367 call to gen_enumeration_type_die.
5368 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
5369 first recursive call as well as the call to gen_tagged_type_die.
5370 (gen_type_die): Add REVERSE parameter and pass it in the call to
5371 gen_type_die_with_usage.
5373 2024-01-10 Jakub Jelinek <jakub@redhat.com>
5375 PR tree-optimization/113120
5376 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
5377 with root->size TYPE_PRECISION don't build anything new.
5378 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
5379 rather than build_nonstandard_integer_type.
5381 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
5383 * config/i386/i386.opt: Adjust document.
5384 * doc/invoke.texi: Add description for
5385 -mapx-inline-asm-use-gpr32.
5387 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5389 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
5390 (avg<v_double_trunc>3_floor): New pattern.
5391 (<u>avg<v_double_trunc>3_ceil): Remove.
5392 (avg<v_double_trunc>3_ceil): New pattern.
5393 (uavg<mode>3_floor): Ditto.
5394 (uavg<mode>3_ceil): Ditto.
5395 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
5396 (enum insn_type): Ditto.
5397 * config/riscv/riscv-v.cc: Ditto.
5398 * config/riscv/vector-iterators.md (ashiftrt): Remove.
5400 * config/riscv/vector.md: Add VLS modes.
5402 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5405 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
5406 (vczlsbb_char): New int attribute.
5407 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
5408 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
5409 (*vctzlsbb_zext_<mode>): Rename to ...
5410 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
5413 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5416 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
5417 of the last argument from altivec_register_operand to any_operand. If
5418 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
5419 otherwise if it doesn't satisfy altivec_register_operand, force it to
5420 REG using copy_to_mode_reg.
5422 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
5424 PR middle-end/113100
5425 * builtins.cc (expand_builtin_stack_address): Guard stack point
5426 adjustment with SPARC_STACK_BOUNDARY_HACK.
5428 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5430 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
5431 argument string definitions.
5432 * config/loongarch/loongarch-str.h: Same.
5433 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
5434 as aliases to -mexplicit-relocs={always,none}
5435 * config/loongarch/loongarch.opt: Regenerate.
5436 * config/loongarch/loongarch.cc: Same.
5438 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5440 * config/loongarch/loongarch-def.h: Define constants with
5441 enums instead of Macros.
5443 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5445 * config/loongarch/genopts/loongarch-strings: Rename.
5446 * config/loongarch/genopts/loongarch.opt.in: Same.
5447 * config/loongarch/loongarch-cpu.cc: Same.
5448 * config/loongarch/loongarch-def.cc: Same.
5449 * config/loongarch/loongarch-def.h: Same.
5450 * config/loongarch/loongarch-opts.cc: Same.
5451 * config/loongarch/loongarch-opts.h: Same.
5452 * config/loongarch/loongarch-str.h: Same.
5453 * config/loongarch/loongarch.opt: Same.
5455 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
5457 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
5458 variable with the common la_ prefix.
5459 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
5460 flags as saved using TargetVariable.
5461 * config/loongarch/loongarch.opt: Same.
5462 * config/loongarch/loongarch-def.h: Define evolution_set to
5463 mark changes to the -march default.
5464 * config/loongarch/loongarch-driver.cc: Same.
5465 * config/loongarch/loongarch-opts.cc: Same.
5466 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
5467 conditions around the la_target structure.
5468 * config/loongarch/loongarch.cc: Same.
5469 * config/loongarch/loongarch.md: Same.
5470 * config/loongarch/loongarch-builtins.cc: Same.
5471 * config/loongarch/loongarch-c.cc: Same.
5472 * config/loongarch/lasx.md: Same.
5473 * config/loongarch/lsx.md: Same.
5474 * config/loongarch/sync.md: Same.
5476 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
5478 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
5481 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
5483 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
5485 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5487 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
5489 (vectorizable_live_operation): Likewise.
5491 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5493 PR tree-optimization/113199
5494 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
5497 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5500 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
5501 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
5502 GTY(()) declaration before the definition, drop GTY(()) drom the
5505 2024-01-09 Richard Biener <rguenther@suse.de>
5507 PR tree-optimization/113026
5508 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
5509 redundant and wrong niter bound setting. Move niter
5510 bound adjustment down.
5512 2024-01-09 Tamar Christina <tamar.christina@arm.com>
5514 PR middle-end/113163
5515 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
5516 Reject non-linear inductions that aren't supported.
5518 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5520 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
5521 left shift implementation strategies.
5522 (arc_shift_info): Type for each entry of the shift strategy table.
5523 (arc_shift_context_idx): Return a integer value for each code
5524 generation context, used as an index
5525 (arc_ashl_alg): Table indexed by context and shifted bit count.
5526 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
5527 left shift implementation.
5528 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
5529 provide accurate costs, when optimizing for speed or size.
5531 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5533 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
5535 2024-01-09 Julian Brown <julian@codesourcery.com>
5537 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
5538 processed out before gimplification.
5539 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
5540 * tree.def (OMP_ARRAY_SECTION): New tree code.
5542 2024-01-09 Jakub Jelinek <jakub@redhat.com>
5544 PR tree-optimization/113210
5545 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
5546 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
5547 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
5550 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
5552 PR rtl-optimization/113140
5553 * reorg.cc (fill_slots_from_thread): If we are to branch after the
5554 last instruction of the function, create an end label.
5556 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
5557 Hongtao Liu <hongtao.liu@intel.com>
5560 * config/i386/i386-expand.cc
5561 (ix86_convert_const_wide_int_to_broadcast): Allow call to
5562 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
5563 (ix86_broadcast_from_constant): Revert recent change; Return a
5564 suitable MEMREF independently of mode/target combinations.
5565 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
5566 to decide whether expansion is possible/preferrable. Only try
5567 forcing DImode constants to memory (and trying again) if calling
5568 ix86_expand_vector_init_duplicate fails with an DImode immediate
5570 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
5571 V4SImode for suitable immediate constants.
5572 <case E_V4DImode>: Try using V8SImode for suitable constants.
5573 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
5574 <case E_V2HImode>: Likewise.
5575 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
5576 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
5577 <label widen>: Handle CONT_INTs via simplify_binary_operation.
5578 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
5579 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
5580 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
5581 (ix86_expand_vector_init): Move try using a broadcast for all_same
5582 with ix86_expand_vector_init_duplicate before using constant pool.
5584 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5586 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
5588 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
5590 * config/arm/arm-cpus.in (cortex-m52): New cpu.
5591 * config/arm/arm-tables.opt: Regenerate.
5592 * config/arm/arm-tune.md: Regenerate.
5594 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
5596 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
5597 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
5598 (@vec_concatz<mode>): New insn pattern.
5599 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
5600 Handle VALS containing two vectors.
5602 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5604 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
5605 (vundefined): Ditto.
5607 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
5609 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5610 Add new function_base for crypto vector.
5611 (class bitmanip): Ditto.
5612 (class b_reverse):Ditto.
5613 (class vwsll): Ditto.
5614 (class clmul): Ditto.
5615 (class vg_nhab): Ditto.
5616 (class crypto_vv):Ditto.
5617 (class crypto_vi):Ditto.
5618 (class vaeskf2_vsm3c):Ditto.
5619 (class vsm3me): Ditto.
5620 (BASE): Add BASE declaration for crypto vector.
5621 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5622 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5623 Add crypto vector intrinsic definition.
5651 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5652 Add new function_shape for crypto vector.
5653 (struct crypto_vi_def): Ditto.
5654 (struct crypto_vv_no_op_type_def): Ditto.
5655 (SHAPE): Add SHAPE declaration of crypto vector.
5656 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5657 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5658 Add new data type for crypto vector.
5659 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5660 (vuint32mf2_t): Ditto.
5661 (vuint32m1_t): Ditto.
5662 (vuint32m2_t): Ditto.
5663 (vuint32m4_t): Ditto.
5664 (vuint32m8_t): Ditto.
5665 (vuint64m1_t): Ditto.
5666 (vuint64m2_t): Ditto.
5667 (vuint64m4_t): Ditto.
5668 (vuint64m8_t): Ditto.
5669 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5670 Add new data struct for crypto vector.
5671 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5672 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
5673 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
5675 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
5678 * varasm.cc (assemble_function_label_raw): Do not call
5679 asan_function_start () without the current function.
5681 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5684 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
5685 extern and kernel_helper attributed function decls.
5687 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
5689 * btfout.cc (output_btf_strs): Changed.
5691 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5693 * config/gcn/mkoffload.cc (main): Handle gfx1100
5694 when setting the default XNACK.
5696 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
5698 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
5699 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
5700 (ASM_SPEC): Handle gfx1100.
5701 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
5702 (enum gcn_isa): Add ISA_RDNA3.
5703 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
5704 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5705 * config/gcn/gcn.cc (gcn_option_override,
5706 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
5707 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
5708 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5709 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
5711 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
5712 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
5714 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
5715 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
5716 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
5717 (isa_has_combined_avgprs, main): Handle gfx1100.
5718 * config/gcn/t-omp-device (isa): Add gfx1100.
5720 2024-01-08 Richard Biener <rguenther@suse.de>
5722 * doc/invoke.texi (-mmovbe): Clarify.
5724 2024-01-08 Richard Biener <rguenther@suse.de>
5726 PR tree-optimization/113026
5727 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
5728 Avoid an epilog in more cases.
5729 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
5730 epilogues niter upper bounds and estimates.
5732 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5734 PR tree-optimization/113228
5735 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
5737 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5739 PR tree-optimization/113120
5740 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
5741 large _BitInt zero INTEGER_CST PHI argument.
5743 2024-01-08 Jakub Jelinek <jakub@redhat.com>
5745 PR tree-optimization/113119
5746 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
5747 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
5748 is before REALPART_EXPR.
5750 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
5753 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
5754 range when diagnosing attribute "io" and "io_low" are out of range.
5755 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
5756 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
5757 in contexts other than static storage.
5758 (avr_asm_output_aligned_decl_common): Move output of decls with
5759 attribute "address", "io", and "io_low" to...
5760 (avr_output_addr_attrib): ...this new function.
5761 (avr_asm_asm_output_aligned_bss): Remove output for decls with
5762 attribute "address", "io", and "io_low".
5763 (avr_encode_section_info): Rectify handling of decls with attribute
5764 "address", "io", and "io_low".
5766 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5768 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
5769 (elf_flags): Remove XNACK from the default value.
5770 (main): Set a default XNACK according to the arch.
5772 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
5774 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
5775 (process_asm): Don't count avgprs.
5777 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
5779 * config/i386/i386.opt: Add supported sub-features.
5780 * doc/extend.texi: Add description for target attribute.
5782 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
5784 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
5786 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
5787 Uros Bizjak <ubizjak@gmail.com>
5790 * config/i386/i386-features.cc (compute_convert_gain): Include
5791 the overhead of explicit load and store (movd) instructions when
5792 converting non-store scalar operations with memory destinations.
5793 Various indentation whitespace fixes.
5795 2024-01-07 Tamar Christina <tamar.christina@arm.com>
5797 * config/arm/neon.md (cbranch<mode>4): New.
5799 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5801 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
5803 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
5805 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
5807 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5810 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
5813 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5815 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
5816 (variable_vectorized_p): Teach loop invariant.
5817 (has_unexpected_spills_p): Ditto.
5819 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5821 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
5822 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
5823 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
5825 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
5828 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
5829 (aarch64-vect-compare-costs): ...this.
5830 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
5832 (-param=aarch64-vect-compare-costs=): ...this new param.
5833 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
5834 Don't disable it when vectorizing for Advanced SIMD only.
5835 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
5836 whenever aarch64_vect_compare_costs is true.
5838 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
5840 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
5841 Modify the method of determining the memory offset of [x]vld/[x]vst.
5842 (lasx_mxst_<lasxfmt_f>): Likewise.
5843 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
5844 (loongarch_address_insns): Likewise.
5845 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
5846 (lsx_st_<lsxfmt_f>): Likewise.
5847 * config/loongarch/predicates.md (aq10b_operand): Likewise.
5848 (aq10h_operand): Likewise.
5849 (aq10w_operand): Likewise.
5850 (aq10d_operand): Likewise.
5852 2024-01-05 Alex Coplan <alex.coplan@arm.com>
5855 * config/aarch64/aarch64-ldp-fusion.cc
5856 (ldp_bb_info::try_fuse_pair): If the second access can throw,
5857 narrow the move range to exactly that insn.
5859 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5861 * asan.cc (asan_function_start): Drop switch_to_section ().
5862 (asan_emit_stack_protection): Set .LASANPC alignment.
5863 * config/i386/i386.cc: Use assemble_function_label_raw ()
5864 instead of ASM_OUTPUT_LABEL ().
5865 * config/s390/s390.cc (s390_asm_output_function_label):
5867 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
5868 * final.cc (final_start_function_1): Drop
5869 asan_function_start ().
5870 * output.h (assemble_function_label_raw): New function.
5871 * varasm.cc (assemble_function_label_raw): Likewise.
5873 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
5875 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
5876 Use ASM_OUTPUT_FUNCTION_LABEL ().
5877 * config/alpha/alpha.cc (alpha_start_function): Likewise.
5878 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5879 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
5880 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5881 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5882 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
5883 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
5884 * config/ia64/ia64.cc (ia64_start_function): Likewise.
5885 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
5887 * config/microblaze/microblaze.cc (microblaze_function_prologue):
5889 * config/mips/mips.cc (mips_start_unique_function): Return the
5891 (mips_start_function_definition): Use
5892 ASM_OUTPUT_FUNCTION_LABEL ().
5893 (mips_finish_stub): Pass the tree to
5894 mips_start_function_definition ().
5895 (mips16_build_function_stub): Likewise.
5896 (mips16_build_call_stub): Likewise.
5897 (mips_output_function_prologue): Likewise.
5898 * config/pa/pa.cc (pa_output_function_label): Use
5899 ASM_OUTPUT_FUNCTION_LABEL ().
5900 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
5901 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
5903 (rs6000_xcoff_declare_function_name): Likewise.
5905 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5907 PR tree-optimization/113201
5908 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
5909 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
5911 2024-01-05 Jakub Jelinek <jakub@redhat.com>
5913 PR tree-optimization/90693
5914 * tree-ssa-math-opts.cc (match_single_bit_test): If
5915 tree_expr_nonzero_p (arg), remember it in the second argument to
5916 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
5917 arg ^ (arg - 1) > arg - 1.
5918 * internal-fn.cc (expand_POPCOUNT): If second argument to
5919 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
5920 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
5922 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
5924 * config/riscv/riscv-v.cc (expand_load_store):
5926 (expand_cond_len_op): Ditto.
5927 (expand_gather_scatter): Ditto.
5928 (expand_lanes_load_store): Ditto.
5929 (expand_fold_extract_last): Ditto.
5931 2024-01-05 Pan Li <pan2.li@intel.com>
5934 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
5936 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
5937 Add new function_base for crypto vector.
5938 (class bitmanip): Ditto.
5939 (class b_reverse):Ditto.
5940 (class vwsll): Ditto.
5941 (class clmul): Ditto.
5942 (class vg_nhab): Ditto.
5943 (class crypto_vv):Ditto.
5944 (class crypto_vi):Ditto.
5945 (class vaeskf2_vsm3c):Ditto.
5946 (class vsm3me): Ditto.
5947 (BASE): Add BASE declaration for crypto vector.
5948 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
5949 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
5950 Add crypto vector intrinsic definition.
5978 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
5979 Add new function_shape for crypto vector.
5980 (struct crypto_vi_def): Ditto.
5981 (struct crypto_vv_no_op_type_def): Ditto.
5982 (SHAPE): Add SHAPE declaration of crypto vector.
5983 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
5984 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
5985 Add new data type for crypto vector.
5986 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5987 (vuint32mf2_t): Ditto.
5988 (vuint32m1_t): Ditto.
5989 (vuint32m2_t): Ditto.
5990 (vuint32m4_t): Ditto.
5991 (vuint32m8_t): Ditto.
5992 (vuint64m1_t): Ditto.
5993 (vuint64m2_t): Ditto.
5994 (vuint64m4_t): Ditto.
5995 (vuint64m8_t): Ditto.
5996 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
5997 Add new data struct for crypto vector.
5998 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
5999 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6000 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6002 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6004 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6005 Add new function_base for crypto vector.
6006 (class bitmanip): Ditto.
6007 (class b_reverse):Ditto.
6008 (class vwsll): Ditto.
6009 (class clmul): Ditto.
6010 (class vg_nhab): Ditto.
6011 (class crypto_vv):Ditto.
6012 (class crypto_vi):Ditto.
6013 (class vaeskf2_vsm3c):Ditto.
6014 (class vsm3me): Ditto.
6015 (BASE): Add BASE declaration for crypto vector.
6016 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6017 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6018 Add crypto vector intrinsic definition.
6046 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6047 Add new function_shape for crypto vector.
6048 (struct crypto_vi_def): Ditto.
6049 (struct crypto_vv_no_op_type_def): Ditto.
6050 (SHAPE): Add SHAPE declaration of crypto vector.
6051 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6052 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6053 Add new data type for crypto vector.
6054 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6055 (vuint32mf2_t): Ditto.
6056 (vuint32m1_t): Ditto.
6057 (vuint32m2_t): Ditto.
6058 (vuint32m4_t): Ditto.
6059 (vuint32m8_t): Ditto.
6060 (vuint64m1_t): Ditto.
6061 (vuint64m2_t): Ditto.
6062 (vuint64m4_t): Ditto.
6063 (vuint64m8_t): Ditto.
6064 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6065 Add new data struct for crypto vector.
6066 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6067 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6068 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6070 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6072 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6074 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
6076 PR tree-optimization/113186
6077 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
6078 Match `^` with the `==` for 1bit integral types.
6079 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
6082 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6084 * toplev.cc (general_init): Pass lang_mask to urlifier.
6086 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6088 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
6090 (diagnostic_context::make_option_url): Update for lang_mask param.
6091 * gcc-urlifier.cc: Include "opts.h" and "options.h".
6092 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
6093 (gcc_urlifier::m_lang_mask): New field.
6094 (doc_urls): Make static.
6095 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
6096 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6097 Look for an option by name before trying a binary search in
6099 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
6100 (gcc_urlifier::get_url_suffix_for_option): New.
6101 (make_gcc_urlifier): Add lang_mask param.
6102 (selftest::gcc_urlifier_cc_tests): Update for above changes.
6103 Verify that a URL is found for "-fpack-struct".
6104 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
6105 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
6106 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
6107 to make_gcc_urlifier.
6108 * opts-diagnostic.h (get_option_url): Add lang_mask param.
6109 * opts.cc (get_option_html_page): Remove special-casing for
6111 (get_option_url_suffix): New.
6112 (get_option_url): Reimplement.
6113 (selftest::test_get_option_html_page): Rename to...
6114 (selftest::test_get_option_url_suffix): ...this and update for
6116 (selftest::opts_cc_tests): Update for renaming.
6117 * opts.h: Include "rich-location.h".
6118 (get_option_url_suffix): New decl.
6120 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6122 * Makefile.in (ALL_OPT_URL_FILES): New.
6123 (GCC_OBJS): Add options-urls.o.
6125 (OBJS-libcommon): Likewise.
6126 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
6127 inputs to opt-gather.awk.
6128 (options-urls.cc): New Makefile target.
6129 * opt-functions.awk (url_suffix): New function.
6130 (lang_url_suffix): New function.
6131 * options-urls-cc-gen.awk: New file.
6132 * opts.h (get_opt_url_suffix): New decl.
6134 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6136 * params.opt.urls: New file, autogenerated by
6137 regenerate-opt-urls.py.
6139 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6141 * common.opt.urls: New file, autogenerated by
6142 regenerate-opt-urls.py.
6143 * config/aarch64/aarch64.opt.urls: Likewise.
6144 * config/alpha/alpha.opt.urls: Likewise.
6145 * config/alpha/elf.opt.urls: Likewise.
6146 * config/arc/arc-tables.opt.urls: Likewise.
6147 * config/arc/arc.opt.urls: Likewise.
6148 * config/arm/arm-tables.opt.urls: Likewise.
6149 * config/arm/arm.opt.urls: Likewise.
6150 * config/arm/vxworks.opt.urls: Likewise.
6151 * config/avr/avr.opt.urls: Likewise.
6152 * config/bpf/bpf.opt.urls: Likewise.
6153 * config/c6x/c6x-tables.opt.urls: Likewise.
6154 * config/c6x/c6x.opt.urls: Likewise.
6155 * config/cris/cris.opt.urls: Likewise.
6156 * config/cris/elf.opt.urls: Likewise.
6157 * config/csky/csky.opt.urls: Likewise.
6158 * config/csky/csky_tables.opt.urls: Likewise.
6159 * config/darwin.opt.urls: Likewise.
6160 * config/dragonfly.opt.urls: Likewise.
6161 * config/epiphany/epiphany.opt.urls: Likewise.
6162 * config/fr30/fr30.opt.urls: Likewise.
6163 * config/freebsd.opt.urls: Likewise.
6164 * config/frv/frv.opt.urls: Likewise.
6165 * config/ft32/ft32.opt.urls: Likewise.
6166 * config/fused-madd.opt.urls: Likewise.
6167 * config/g.opt.urls: Likewise.
6168 * config/gcn/gcn.opt.urls: Likewise.
6169 * config/gnu-user.opt.urls: Likewise.
6170 * config/h8300/h8300.opt.urls: Likewise.
6171 * config/hpux11.opt.urls: Likewise.
6172 * config/i386/cygming.opt.urls: Likewise.
6173 * config/i386/cygwin.opt.urls: Likewise.
6174 * config/i386/djgpp.opt.urls: Likewise.
6175 * config/i386/i386.opt.urls: Likewise.
6176 * config/i386/mingw-w64.opt.urls: Likewise.
6177 * config/i386/mingw.opt.urls: Likewise.
6178 * config/i386/nto.opt.urls: Likewise.
6179 * config/ia64/ia64.opt.urls: Likewise.
6180 * config/ia64/ilp32.opt.urls: Likewise.
6181 * config/ia64/vms.opt.urls: Likewise.
6182 * config/iq2000/iq2000.opt.urls: Likewise.
6183 * config/linux-android.opt.urls: Likewise.
6184 * config/linux.opt.urls: Likewise.
6185 * config/lm32/lm32.opt.urls: Likewise.
6186 * config/loongarch/loongarch.opt.urls: Likewise.
6187 * config/lynx.opt.urls: Likewise.
6188 * config/m32c/m32c.opt.urls: Likewise.
6189 * config/m32r/m32r.opt.urls: Likewise.
6190 * config/m68k/ieee.opt.urls: Likewise.
6191 * config/m68k/m68k-tables.opt.urls: Likewise.
6192 * config/m68k/m68k.opt.urls: Likewise.
6193 * config/m68k/uclinux.opt.urls: Likewise.
6194 * config/mcore/mcore.opt.urls: Likewise.
6195 * config/microblaze/microblaze.opt.urls: Likewise.
6196 * config/mips/mips-tables.opt.urls: Likewise.
6197 * config/mips/mips.opt.urls: Likewise.
6198 * config/mips/sde.opt.urls: Likewise.
6199 * config/mmix/mmix.opt.urls: Likewise.
6200 * config/mn10300/mn10300.opt.urls: Likewise.
6201 * config/moxie/moxie.opt.urls: Likewise.
6202 * config/msp430/msp430.opt.urls: Likewise.
6203 * config/nds32/nds32-elf.opt.urls: Likewise.
6204 * config/nds32/nds32-linux.opt.urls: Likewise.
6205 * config/nds32/nds32.opt.urls: Likewise.
6206 * config/netbsd-elf.opt.urls: Likewise.
6207 * config/netbsd.opt.urls: Likewise.
6208 * config/nios2/elf.opt.urls: Likewise.
6209 * config/nios2/nios2.opt.urls: Likewise.
6210 * config/nvptx/nvptx-gen.opt.urls: Likewise.
6211 * config/nvptx/nvptx.opt.urls: Likewise.
6212 * config/openbsd.opt.urls: Likewise.
6213 * config/or1k/elf.opt.urls: Likewise.
6214 * config/or1k/or1k.opt.urls: Likewise.
6215 * config/pa/pa-hpux.opt.urls: Likewise.
6216 * config/pa/pa-hpux1010.opt.urls: Likewise.
6217 * config/pa/pa-hpux1111.opt.urls: Likewise.
6218 * config/pa/pa-hpux1131.opt.urls: Likewise.
6219 * config/pa/pa.opt.urls: Likewise.
6220 * config/pa/pa64-hpux.opt.urls: Likewise.
6221 * config/pdp11/pdp11.opt.urls: Likewise.
6222 * config/pru/pru.opt.urls: Likewise.
6223 * config/riscv/riscv.opt.urls: Likewise.
6224 * config/rl78/rl78.opt.urls: Likewise.
6225 * config/rpath.opt.urls: Likewise.
6226 * config/rs6000/476.opt.urls: Likewise.
6227 * config/rs6000/aix64.opt.urls: Likewise.
6228 * config/rs6000/darwin.opt.urls: Likewise.
6229 * config/rs6000/linux64.opt.urls: Likewise.
6230 * config/rs6000/rs6000-tables.opt.urls: Likewise.
6231 * config/rs6000/rs6000.opt.urls: Likewise.
6232 * config/rs6000/sysv4.opt.urls: Likewise.
6233 * config/rtems.opt.urls: Likewise.
6234 * config/rx/elf.opt.urls: Likewise.
6235 * config/rx/rx.opt.urls: Likewise.
6236 * config/s390/s390.opt.urls: Likewise.
6237 * config/s390/tpf.opt.urls: Likewise.
6238 * config/sh/sh.opt.urls: Likewise.
6239 * config/sh/superh.opt.urls: Likewise.
6240 * config/sol2.opt.urls: Likewise.
6241 * config/sparc/long-double-switch.opt.urls: Likewise.
6242 * config/sparc/sparc.opt.urls: Likewise.
6243 * config/stormy16/stormy16.opt.urls: Likewise.
6244 * config/v850/v850.opt.urls: Likewise.
6245 * config/vax/elf.opt.urls: Likewise.
6246 * config/vax/vax.opt.urls: Likewise.
6247 * config/visium/visium.opt.urls: Likewise.
6248 * config/vms/vms.opt.urls: Likewise.
6249 * config/vxworks-smp.opt.urls: Likewise.
6250 * config/vxworks.opt.urls: Likewise.
6251 * config/xtensa/elf.opt.urls: Likewise.
6252 * config/xtensa/uclinux.opt.urls: Likewise.
6253 * config/xtensa/xtensa.opt.urls: Likewise.
6254 * config/bfin/bfin.opt.urls: New file.
6256 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6258 * Makefile.in (OPT_URLS_HTML_DEPS): New.
6259 (regenerate-opt-urls): New target.
6260 (regenerate-opt-urls-unit-test): New target.
6261 * doc/options.texi (Option properties): Add UrlSuffix and
6262 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
6263 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
6264 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
6265 and Makefile.in's OPT_URLS_HTML_DEPS.
6266 (Anatomy of a Target Back End): Add
6267 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
6268 * regenerate-opt-urls.py: New file.
6270 2024-01-04 David Malcolm <dmalcolm@redhat.com>
6272 * diagnostic-format-sarif.cc
6273 (sarif_builder::make_logical_location_object): Convert to...
6274 (make_sarif_logical_location_object): ...this.
6275 (sarif_builder::set_any_logical_locs_arr): Update for above
6277 (sarif_builder::make_thread_flow_location_object): Call
6278 maybe_add_sarif_properties on each diagnostic_event.
6279 * diagnostic-format-sarif.h (class logical_location): New forward
6281 (make_sarif_logical_location_object): New decl.
6282 * diagnostic-path.h (class sarif_object): New forward decl.
6283 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
6285 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
6286 Patrick Lin <patrick@andestech.com>
6287 Rufus Chen <rufus@andestech.com>
6288 Monk Chiang <monk.chiang@sifive.com>
6290 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
6291 with Nan-boxing value.
6292 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
6294 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
6295 Jeff Law <jlaw@ventanamicro.com>
6297 PR rtl-optimization/104914
6298 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
6299 a sign or zero extension is only required if the modified field
6300 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
6301 targets, don't refer to the temporarily incorrectly extended value
6302 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
6304 2024-01-04 Pan Li <pan2.li@intel.com>
6307 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6309 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6311 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6313 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
6315 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
6317 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
6320 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6322 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
6323 (compute_nregs_for_mode): Refine LMUL.
6324 (max_number_of_live_regs): Ditto.
6325 (compute_estimated_lmul): Ditto.
6326 (has_unexpected_spills_p): Ditto.
6328 2024-01-04 Li Wei <liwei@loongson.cn>
6330 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
6331 Remove useless forward declaration.
6332 (loongarch_is_even_extraction): Remove useless forward declaration.
6333 (loongarch_try_expand_lsx_vshuf_const): Removed.
6334 (loongarch_expand_vec_perm_const_1): Merged.
6335 (loongarch_is_double_duplicate): Removed.
6336 (loongarch_is_center_extraction): Ditto.
6337 (loongarch_is_reversing_permutation): Ditto.
6338 (loongarch_is_di_misalign_extract): Ditto.
6339 (loongarch_is_si_misalign_extract): Ditto.
6340 (loongarch_is_lasx_lowpart_extract): Ditto.
6341 (loongarch_is_op_reverse_perm): Ditto.
6342 (loongarch_is_single_op_perm): Ditto.
6343 (loongarch_is_divisible_perm): Ditto.
6344 (loongarch_is_triple_stride_extract): Ditto.
6345 (loongarch_expand_vec_perm_const_2): Merged.
6346 (loongarch_expand_vec_perm_const): New.
6347 (loongarch_vectorize_vec_perm_const): Adjust.
6349 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
6351 * omp-general.cc: Fix comment typos and misplaced/confusing
6352 comments. Delete redundant include of omp-general.h.
6354 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6356 PR rtl-optimization/104914
6357 * config/mips/mips.md (insqisi_extended): New patterns.
6358 (inshisi_extended): Ditto.
6360 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6362 * config/mips/mips.cc (mips_insn_cost): New function.
6364 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
6366 * config/mips/mips.md (perf_ratio): New attribute.
6368 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6372 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
6373 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
6374 blocks belong to infinite loop.
6375 (pre_vsetvl::emit_vsetvl): Remove fake edges.
6376 * config/riscv/t-riscv: Add a new include file.
6378 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6380 * config/riscv/vector.md: Fix indent.
6382 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6384 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
6385 OMP_CLAUSE__SIMDUID_.
6386 * tree.cc (omp_clause_num_ops): Update position of entry for
6387 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
6388 (omp_clause_code_name): Likewise.
6390 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
6392 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
6393 printing of FUNC_MAP/IND_FUNC_MAP labels.
6395 2024-01-03 Jakub Jelinek <jakub@redhat.com>
6397 * gcc.cc (process_command): Update copyright notice dates.
6398 * gcov-dump.cc (print_version): Ditto.
6399 * gcov.cc (print_version): Ditto.
6400 * gcov-tool.cc (print_version): Ditto.
6401 * gengtype.cc (create_file): Ditto.
6402 * doc/cpp.texi: Bump @copying's copyright year.
6403 * doc/cppinternals.texi: Ditto.
6404 * doc/gcc.texi: Ditto.
6405 * doc/gccint.texi: Ditto.
6406 * doc/gcov.texi: Ditto.
6407 * doc/install.texi: Ditto.
6408 * doc/invoke.texi: Ditto.
6410 2024-01-03 Xi Ruoyao <xry111@xry111.site>
6412 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
6413 (fmin<mode>3): Likewise.
6414 (reduc_fmax_scal_<mode>3): New define_expand.
6415 (reduc_fmin_scal_<mode>3): Likewise.
6417 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6420 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
6421 (max_number_of_live_regs): Ditto.
6422 (has_unexpected_spills_p): Ditto.
6424 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6425 Jin Ma <jinma@linux.alibaba.com>
6426 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6427 Christoph Müllner <christoph.muellner@vrull.eu>
6429 * config/riscv/vector.md:
6430 Use vector_length_operand for vsetvl patterns.
6432 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6434 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
6435 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
6437 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
6439 * config/aarch64/aarch64-tuning-flags.def
6440 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
6441 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
6442 * config/aarch64/aarch64.cc
6443 (aarch64_override_options_internal): Set
6444 param_fully_pipelined_fma according to tuning option.
6445 * config/aarch64/tuning_models/ampere1.h: Add
6446 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
6447 * config/aarch64/tuning_models/ampere1a.h: Likewise.
6448 * config/aarch64/tuning_models/ampere1b.h: Likewise.
6450 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6452 * config/riscv/vector-crypto.md: Modify copyright year.
6454 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6456 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
6458 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
6460 * config.in: Regenerate.
6461 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
6462 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
6463 Added TLS Le Relax support.
6464 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
6465 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
6466 * configure: Regenerate.
6467 * configure.ac: Check if binutils supports TLS le relax.
6469 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
6471 * config/riscv/iterators.md: Add rotate insn name.
6472 * config/riscv/riscv.md: Add new insns name for crypto vector.
6473 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
6474 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
6475 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
6477 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6480 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
6481 pointer type liveness count.
6483 Copyright (C) 2024 Free Software Foundation, Inc.
6485 Copying and distribution of this file, with or without modification,
6486 are permitted in any medium without royalty provided the copyright
6487 notice and this notice are preserved.