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1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
54 REG_DEAD note is lost
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
57 linking
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
95 /* Number of attempts to combine instructions in this function. */
99 /* Number of attempts that got as far as substitution in this function. */
103 /* Number of instructions combined with added SETs in this function. */
107 /* Number of instructions combined in this function. */
111 /* combine_instructions may try to replace the right hand side of the
112 second instruction with the value of an associated REG_EQUAL note
113 before throwing it at try_combine. That is problematic when there
114 is a REG_DEAD note for a register used in the old right hand side
115 and can cause distribute_notes to do wrong things. This is the
116 second instruction if it has been so modified, null otherwise. */
120 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
124 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
127 \f
129 /* Record last point of death of (hard or pseudo) register n. */
132 /* Record last point of modification of (hard or pseudo) register n. */
135 /* The next group of fields allows the recording of the last value assigned
136 to (hard or pseudo) register n. We use this information to see if an
137 operation being processed is redundant given a prior operation performed
138 on the register. For example, an `and' with a constant is redundant if
139 all the zero bits are already known to be turned off.
141 We use an approach similar to that used by cse, but change it in the
142 following ways:
144 (1) We do not want to reinitialize at each label.
145 (2) It is useful, but not critical, to know the actual value assigned
146 to a register. Often just its form is helpful.
148 Therefore, we maintain the following fields:
150 last_set_value the last value assigned
151 last_set_label records the value of label_tick when the
152 register was assigned
153 last_set_table_tick records the value of label_tick when a
154 value using the register is assigned
155 last_set_invalid set to true when it is not valid
156 to use the value of this register in some
157 register's value
159 To understand the usage of these tables, it is important to understand
160 the distinction between the value in last_set_value being valid and
161 the register being validly contained in some other expression in the
162 table.
164 (The next two parameters are out of date).
166 reg_stat[i].last_set_value is valid if it is nonzero, and either
167 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
169 Register I may validly appear in any expression returned for the value
170 of another register if reg_n_sets[i] is 1. It may also appear in the
171 value for register J if reg_stat[j].last_set_invalid is zero, or
172 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
174 If an expression is found in the table containing a register which may
175 not validly appear in an expression, the register is replaced by
176 something that won't match, (clobber (const_int 0)). */
178 /* Record last value assigned to (hard or pseudo) register n. */
180 rtx last_set_value;
182 /* Record the value of label_tick when an expression involving register n
183 is placed in last_set_value. */
187 /* Record the value of label_tick when the value for register n is placed in
188 last_set_value. */
192 /* These fields are maintained in parallel with last_set_value and are
193 used to store the mode in which the register was last set, the bits
194 that were known to be zero when it was last set, and the number of
195 sign bits copies it was known to have when it was last set. */
201 /* Set to true if references to register n in expressions should not be
202 used. last_set_invalid is set nonzero when this register is being
203 assigned to and last_set_table_tick == label_tick. */
207 /* Some registers that are set more than once and used in more than one
208 basic block are nevertheless always set in similar ways. For example,
209 a QImode register may be loaded from memory in two places on a machine
210 where byte loads zero extend.
212 We record in the following fields if a register has some leading bits
213 that are always equal to the sign bit, and what we know about the
214 nonzero bits of a register, specifically which bits are known to be
215 zero.
217 If an entry is zero, it means that we don't know anything special. */
223 /* Record the value of the label_tick when the last truncation
224 happened. The field truncated_to_mode is only valid if
225 truncation_label == label_tick. */
229 /* Record the last truncation seen for this register. If truncation
230 is not a nop to this mode we might be able to save an explicit
231 truncation if we know that value already contains a truncated
232 value. */
235 };
240 /* One plus the highest pseudo for which we track REG_N_SETS.
241 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 but during combine_split_insns new pseudos can be created. As we don't have
243 updated DF information in that case, it is hard to initialize the array
244 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 so instead of growing the arrays, just assume all newly created pseudos
246 during combine might be set multiple times. */
250 /* Record the luid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
255 /* Record the luid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
268 /* This is the lowest LUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this LUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
284 that location. */
288 /* And similarly, for notes. */
292 /* Basic block in which we are performing combines. */
296 \f
297 /* Length of the currently allocated uid_insn_cost array. */
301 /* The following array records the insn_cost for every insn
302 in the instruction stream. */
306 /* The following array records the LOG_LINKS for every insn in the
307 instruction stream as struct insn_link pointers. */
313 };
319 {
323 }
325 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
326 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 #define FOR_EACH_LOG_LINK(L, INSN) \
329 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 /* Links for LOG_LINKS are allocated from this obstack. */
335 /* Allocate a link. */
339 {
347 }
349 /* Incremented for each basic block. */
353 /* Reset to label_tick for each extended basic block in scanning order. */
357 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
358 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
362 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
363 be safely used. It is zero while computing them and after combine has
364 completed. This former test prevents propagating values based on
365 previously set values, which can be incorrect if a variable is modified
366 in a loop. */
370 \f
371 /* Record one modification to rtl structure
372 to be undone by storing old_contents into *where. */
376 struct undo
377 {
382 };
384 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
385 num_undo says how many are currently recorded.
387 other_insn is nonzero if we have modified some other insn in the process
388 of working on subst_insn. It must be verified too. */
390 struct undobuf
391 {
395 };
399 /* Number of times the pseudo being substituted for
400 was found and replaced. */
405 scalar_int_mode,
408 scalar_int_mode,
482 \f
484 /* It is not safe to use ordinary gen_lowpart in combine.
485 See comments in gen_lowpart_for_combine. */
486 #undef RTL_HOOKS_GEN_LOWPART
487 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
489 /* Our implementation of gen_lowpart never emits a new pseudo. */
490 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
491 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
493 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
494 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
496 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
497 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
499 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
500 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
504 \f
505 /* Convenience wrapper for the canonicalize_comparison target hook.
506 Target hooks cannot use enum rtx_code. */
510 {
514 }
516 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
517 PATTERN cannot be split. Otherwise, it returns an insn sequence.
518 This is a wrapper around split_insns which ensures that the
519 reg_stat vector is made larger if the splitter creates a new
520 register. */
524 {
533 }
535 /* This is used by find_single_use to locate an rtx in LOC that
536 contains exactly one use of DEST, which is typically a REG.
537 It returns a pointer to the innermost rtx expression
538 containing DEST. Appearances of DEST that are being used to
539 totally replace it are not counted. */
543 {
552 {
556 CASE_CONST_ANY:
561 /* If the destination is anything other than PC, a REG or a SUBREG
562 of a REG that occupies all of the REG, the insn uses DEST if
563 it is mentioned in the destination or the source. Otherwise, we
564 need just check the source. */
580 }
582 /* If it wasn't one of the common cases above, check each expression and
583 vector of this code. Look for a unique usage of DEST. */
587 {
589 {
594 else
600 /* Duplicate usage. */
602 }
604 {
608 {
614 else
621 }
622 }
623 }
626 }
629 /* See if DEST, produced in INSN, is used only a single time in the
630 sequel. If so, return a pointer to the innermost rtx expression in which
631 it is used.
633 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
635 Otherwise, we find the single use by finding an insn that has a
636 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
637 only referenced once in that insn, we know that it must be the first
638 and last insn referencing DEST. */
642 {
643 basic_block bb;
656 {
662 {
667 }
668 }
671 }
672 \f
673 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
674 insn. The substitution can be undone by undo_all. If INTO is already
675 set to NEWVAL, do not record this change. Because computing NEWVAL might
676 also call SUBST, we have to compute it before we put anything into
677 the undo table. */
679 static void
681 {
688 /* We'd like to catch as many invalid transformations here as
689 possible. Unfortunately, there are way too many mode changes
690 that are perfectly valid, so we'd waste too much effort for
691 little gain doing the checks here. Focus on catching invalid
692 transformations involving integer constants. */
695 {
696 /* Sanity check that we're replacing oldval with a CONST_INT
697 that is a valid sign-extension for the original mode. */
701 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
702 CONST_INT is not valid, because after the replacement, the
703 original mode would be gone. Unfortunately, we can't tell
704 when do_SUBST is called to replace the operand thereof, so we
705 perform this test on oldval instead, checking whether an
706 invalid replacement took place before we got here. */
711 }
715 else
724 }
726 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
728 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
729 for the value of a HOST_WIDE_INT value (including CONST_INT) is
730 not safe. */
732 static void
734 {
743 else
752 }
754 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
756 /* Similar to SUBST, but just substitute the mode. This is used when
757 changing the mode of a pseudo-register, so that any other
758 references to the entry in the regno_reg_rtx array will change as
759 well. */
761 static void
763 {
773 else
782 }
784 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
786 static void
788 {
797 else
806 }
808 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
809 \f
810 /* Subroutine of try_combine. Determine whether the replacement patterns
811 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
812 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
813 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
814 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
815 of all the instructions can be estimated and the replacements are more
816 expensive than the original sequence. */
818 static bool
821 {
826 /* Lookup the original insn_costs. */
831 {
834 {
838 }
839 else
840 {
844 }
845 }
846 else
847 {
850 }
852 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
853 correct that. */
858 /* Calculate the replacement insn_costs. */
867 {
877 }
878 else
879 {
882 }
885 {
894 optimize_this_for_speed_p);
898 {
901 }
902 else
904 }
906 /* Disallow this combination if both new_cost and old_cost are greater than
907 zero, and new_cost is greater than old cost. */
911 {
930 else
932 }
937 /* Update the uid_insn_cost array with the replacement costs. */
941 {
945 }
948 }
951 /* Delete any insns that copy a register to itself.
952 Return true if the CFG was changed. */
954 static bool
956 {
958 basic_block bb;
963 {
965 {
968 {
973 }
974 }
975 }
978 }
980 \f
981 /* Return false if we do not want to (or cannot) combine DEF. */
982 static bool
984 {
985 /* Do not consider if it is pre/post modification in MEM. */
991 /* Do not combine frame pointer adjustments. */
994 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1002 }
1004 /* Return false if we do not want to (or cannot) combine USE. */
1005 static bool
1007 {
1008 /* Do not consider the usage of the stack pointer by function call. */
1013 }
1015 /* Fill in log links field for all insns. */
1017 static void
1019 {
1020 basic_block bb;
1027 /* Pass through each block from the end, recording the uses of each
1028 register and establishing log links when def is encountered.
1029 Note that we do not clear next_use array in order to save time,
1030 so we have to test whether the use is in the same basic block as def.
1032 There are a few cases below when we do not consider the definition or
1033 usage -- these are taken from original flow.c did. Don't ask me why it is
1034 done this way; I don't know and if it works, I don't want to know. */
1037 {
1039 {
1043 /* Log links are created only once. */
1047 {
1063 /* flow.c claimed:
1065 We don't build a LOG_LINK for hard registers contained
1066 in ASM_OPERANDs. If these registers get replaced,
1067 we might wind up changing the semantics of the insn,
1068 even if reload can make what appear to be valid
1069 assignments later. */
1074 /* Don't add duplicate links between instructions. */
1083 }
1088 }
1089 }
1092 }
1094 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095 true if we found a LOG_LINK that proves that A feeds B. This only works
1096 if there are no instructions between A and B which could have a link
1097 depending on A, since in that case we would not record a link for B. */
1099 static bool
1101 {
1107 }
1108 \f
1109 /* Main entry point for combiner. F is the first insn of the function.
1110 NREGS is the first unused pseudo-reg number.
1112 Return nonzero if the CFG was changed (e.g. if the combiner has
1113 turned an indirect jump instruction into a direct jump). */
1114 static bool
1116 {
1120 basic_block last_bb;
1140 /* Allocate array for insn info. */
1148 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1149 problems when, for example, we have j <<= 1 in a loop. */
1154 /* Scan all SETs and see if we can deduce anything about what
1155 bits are known to be zero for some registers and how many copies
1156 of the sign bit are known to exist for those registers.
1158 Also set any known values so that we can use it while searching
1159 for what bits are known to be set. */
1162 /* Allow the entry block and the first block to fall into the same EBB.
1163 Conceptually the incoming promotions are assigned to the entry block. */
1168 {
1173 label_tick++;
1181 {
1182 rtx links;
1194 insn);
1196 /* Record the current insn_cost of this instruction. */
1199 {
1202 }
1203 }
1204 }
1208 /* Now scan all the insns in forward order. */
1216 {
1219 /* Ignore instruction combination in basic blocks that are going to
1220 be removed as unreachable anyway. See PR82386. */
1228 label_tick++;
1238 {
1252 /* See if we know about function return values before this
1253 insn based upon SUBREG flags. */
1256 /* See if we can find hardregs and subreg of pseudos in
1257 narrower modes. This could help turning TRUNCATEs
1258 into SUBREGs. */
1261 /* Try this insn with each insn it links back to. */
1267 {
1270 }
1272 /* Try each sequence of three linked insns ending with this one. */
1276 {
1279 /* If the linked insn has been replaced by a note, then there
1280 is no point in pursuing this chain any further. */
1288 {
1291 }
1292 }
1294 /* Try combining an insn with two different insns whose results it
1295 uses. */
1305 {
1308 }
1310 /* Try four-instruction combinations. */
1313 {
1317 /* If the linked insn has been replaced by a note, then there
1318 is no point in pursuing this chain any further. */
1323 {
1327 /* I0 -> I1 -> I2 -> I3. */
1333 {
1336 }
1337 /* I0, I1 -> I2, I2 -> I3. */
1344 {
1347 }
1348 }
1351 {
1355 /* I0 -> I2; I1, I2 -> I3. */
1361 {
1364 }
1365 /* I0 -> I1; I1, I2 -> I3. */
1371 {
1374 }
1375 }
1376 }
1378 /* Try this insn with each REG_EQUAL note it links back to. */
1380 {
1387 /* Avoid using a register that may already been marked
1388 dead by an earlier instruction. */
1396 {
1397 /* Temporarily replace the set's source with the
1398 contents of the REG_EQUAL note. The insn will
1399 be deleted or recognized by try_combine. */
1410 last_combined_insn);
1413 {
1416 }
1420 }
1421 }
1426 retry:
1427 ;
1428 }
1429 }
1439 /* Clean up. */
1445 {
1448 {
1451 }
1453 }
1463 /* Make recognizer allow volatile MEMs again. */
1467 }
1469 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1471 static void
1473 {
1479 }
1480 \f
1481 /* Set up any promoted values for incoming argument registers. */
1483 static void
1485 {
1486 tree arg;
1491 {
1496 /* Only continue if the incoming argument is in a register. */
1500 /* Determine, if possible, whether all call sites of the current
1501 function lie within the current compilation unit. (This does
1502 take into account the exporting of a function via taking its
1503 address, and so forth.) */
1504 strictly_local
1507 /* The mode and signedness of the argument before any promotions happen
1508 (equal to the mode of the pseudo holding it at that stage). */
1512 /* The mode and signedness of the argument after any source language and
1513 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1517 /* The mode and signedness of the argument as it is actually passed,
1518 see assign_parm_setup_reg in function.cc. */
1522 /* The mode of the register in which the argument is being passed. */
1525 /* Eliminate sign extensions in the callee when:
1526 (a) A mode promotion has occurred; */
1529 /* (b) The mode of the register is the same as the mode of
1530 the argument as it is passed; */
1533 /* (c) There's no language level extension; */
1535 ;
1536 /* (c.1) All callers are from the current compilation unit. If that's
1537 the case we don't have to rely on an ABI, we only have to know
1538 what we're generating right now, and we know that we will do the
1539 mode1 to mode2 promotion with the given sign. */
1542 /* (c.2) The combination of the two promotions is useful. This is
1543 true when the signs match, or if the first promotion is unsigned.
1544 In the later case, (sign_extend (zero_extend x)) is the same as
1545 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1551 /* Record that the value was promoted from mode1 to mode3,
1552 so that any sign extension at the head of the current
1553 function may be eliminated. */
1557 }
1558 }
1560 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1561 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1562 because some machines (maybe most) will actually do the sign-extension and
1563 this is the conservative approach.
1565 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1566 kludge. */
1568 static rtx
1570 {
1571 scalar_int_mode int_mode;
1580 }
1582 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1583 and SET. */
1585 static void
1587 rtx x)
1588 {
1598 {
1602 }
1604 /* Don't call nonzero_bits if it cannot change anything. */
1606 {
1615 }
1617 /* Don't call num_sign_bit_copies if it cannot change anything. */
1619 {
1622 {
1626 }
1629 }
1630 }
1632 /* Called via note_stores. If X is a pseudo that is narrower than
1633 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1635 If we are setting only a portion of X and we can't figure out what
1636 portion, assume all bits will be used since we don't know what will
1637 be happening.
1639 Similarly, set how many bits of X are known to be copies of the sign bit
1640 at all locations in the function. This is the smallest number implied
1641 by any set of X. */
1643 static void
1645 {
1647 scalar_int_mode mode;
1651 /* If this register is undefined at the start of the file, we can't
1652 say what its contents were. */
1653 && ! REGNO_REG_SET_P
1657 {
1661 {
1665 }
1667 /* If this register is being initialized using itself, and the
1668 register is uninitialized in this basic block, and there are
1669 no LOG_LINKS which set the register, then part of the
1670 register is uninitialized. In that case we can't assume
1671 anything about the number of nonzero bits.
1673 ??? We could do better if we checked this in
1674 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1675 could avoid making assumptions about the insn which initially
1676 sets the register, while still using the information in other
1677 insns. We would have to be careful to check every insn
1678 involved in the combination. */
1684 {
1691 {
1695 }
1696 }
1698 /* If this is a complex assignment, see if we can convert it into a
1699 simple assignment. */
1702 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1703 set what we know about X. */
1709 else
1710 {
1713 }
1714 }
1715 }
1716 \f
1717 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1718 optionally insns that were previously combined into I3 or that will be
1719 combined into the merger of INSN and I3. The order is PRED, PRED2,
1720 INSN, SUCC, SUCC2, I3.
1722 Return false if the combination is not allowed for any reason.
1724 If the combination is allowed, *PDEST will be set to the single
1725 destination of INSN and *PSRC to the single source, and this function
1726 will return true. */
1728 static bool
1732 {
1737 rtx link;
1742 {
1744 {
1749 }
1754 }
1758 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1759 or a PARALLEL consisting of such a SET and CLOBBERs.
1761 If INSN has CLOBBER parallel parts, ignore them for our processing.
1762 By definition, these happen during the execution of the insn. When it
1763 is merged with another insn, all bets are off. If they are, in fact,
1764 needed and aren't also supplied in I3, they may be added by
1765 recog_for_combine. Otherwise, it won't match.
1767 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1768 note.
1770 Get the source and destination of INSN. If more than one, can't
1771 combine. */
1777 {
1779 {
1783 {
1784 /* This is important to combine floating point insns
1785 for the SH4 port. */
1787 /* Combining an isolated USE doesn't make sense.
1788 We depend here on combinable_i3pat to reject them. */
1789 /* The code below this loop only verifies that the inputs of
1790 the SET in INSN do not change. We call reg_set_between_p
1791 to verify that the REG in the USE does not change between
1792 I3 and INSN.
1793 If the USE in INSN was for a pseudo register, the matching
1794 insn pattern will likely match any register; combining this
1795 with any other USE would only be safe if we knew that the
1796 used registers have identical values, or if there was
1797 something to tell them apart, e.g. different modes. For
1798 now, we forgo such complicated tests and simply disallow
1799 combining of USES of pseudo registers with any other USE. */
1802 {
1807 do
1808 {
1818 }
1820 }
1823 /* We can ignore CLOBBERs. */
1828 /* Ignore SETs whose result isn't used but not those that
1829 have side-effects. */
1835 /* If we have already found a SET, this is a second one and
1836 so we cannot combine with this insn. */
1844 /* Anything else means we can't combine. */
1846 }
1847 }
1850 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1851 so don't do anything with it. */
1854 }
1855 else
1861 /* The simplification in expand_field_assignment may call back to
1862 get_last_value, so set safe guard here. */
1868 /* Do not eliminate user-specified register if it is in an
1869 asm input because we may break the register asm usage defined
1870 in GCC manual if allow to do so.
1871 Be aware that this may cover more cases than we expect but this
1872 should be harmless. */
1877 /* Don't eliminate a store in the stack pointer. */
1879 /* Don't combine with an insn that sets a register to itself if it has
1880 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1882 /* Can't merge an ASM_OPERANDS. */
1884 /* Can't merge a function call. */
1886 /* Don't eliminate a function call argument. */
1892 /* Don't substitute into an incremented register. */
1896 /* Don't substitute into a non-local goto, this confuses CFG. */
1898 /* Make sure that DEST is not used after INSN but before SUCC, or
1899 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1900 || (!all_adjacent
1901 && ((succ2
1906 || (succ
1907 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1908 that case SUCC is not in the insn stream, so use SUCC2
1909 instead for this test. */
1911 succ2
1914 /* Make sure that the value that is to be substituted for the register
1915 does not use any registers whose values alter in between. However,
1916 If the insns are adjacent, a use can't cross a set even though we
1917 think it might (this can happen for a sequence of insns each setting
1918 the same destination; last_set of that register might point to
1919 a NOTE). If INSN has a REG_EQUIV note, the register is always
1920 equivalent to the memory so the substitution is valid even if there
1921 are intervening stores. Also, don't move a volatile asm or
1922 UNSPEC_VOLATILE across any other insns. */
1923 || (! all_adjacent
1929 /* Don't combine across a CALL_INSN, because that would possibly
1930 change whether the life span of some REGs crosses calls or not,
1931 and it is a pain to update that information.
1932 Exception: if source is a constant, moving it later can't hurt.
1933 Accept that as a special case. */
1937 /* DEST must be a REG. */
1939 {
1940 /* If register alignment is being enforced for multi-word items in all
1941 cases except for parameters, it is possible to have a register copy
1942 insn referencing a hard register that is not allowed to contain the
1943 mode being copied and which would not be valid as an operand of most
1944 insns. Eliminate this problem by not combining with such an insn.
1946 Also, on some machines we don't want to extend the life of a hard
1947 register. */
1952 /* Don't extend the life of a hard register unless it is
1953 user variable (if we have few registers) or it can't
1954 fit into the desired register (meaning something special
1955 is going on).
1956 Also avoid substituting a return register into I3, because
1957 reload can't handle a conflict with constraints of other
1958 inputs. */
1963 }
1964 else
1971 {
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1986 }
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1992 {
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1998 /* We'll check insns between INSN and I3 below. */
1999 }
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2014 ? volatile_refs_p
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump if using LRA; if it were one
2025 and the incremented register were spilled, we would lose.
2026 Reload handles this correctly. */
2044 /* If we get here, we have passed all the tests and the combination is
2045 to be allowed. */
2051 }
2052 \f
2053 /* LOC is the location within I3 that contains its pattern or the component
2054 of a PARALLEL of the pattern. We validate that it is valid for combining.
2056 One problem is if I3 modifies its output, as opposed to replacing it
2057 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2058 doing so would produce an insn that is not equivalent to the original insns.
2060 Consider:
2062 (set (reg:DI 101) (reg:DI 100))
2063 (set (subreg:SI (reg:DI 101) 0) <foo>)
2065 This is NOT equivalent to:
2067 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2068 (set (reg:DI 101) (reg:DI 100))])
2070 Not only does this modify 100 (in which case it might still be valid
2071 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2073 We can also run into a problem if I2 sets a register that I1
2074 uses and I1 gets directly substituted into I3 (not via I2). In that
2075 case, we would be getting the wrong value of I2DEST into I3, so we
2076 must reject the combination. This case occurs when I2 and I1 both
2077 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2078 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2079 of a SET must prevent combination from occurring. The same situation
2080 can occur for I0, in which case I0_NOT_IN_SRC is set.
2082 Before doing the above check, we first try to expand a field assignment
2083 into a set of logical operations.
2085 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2086 we place a register that is both set and used within I3. If more than one
2087 such register is detected, we fail.
2089 Return true if the combination is valid, false otherwise. */
2091 static bool
2094 {
2098 {
2103 rtx subdest;
2110 /* Check for the case where I3 modifies its output, as discussed
2111 above. We don't want to prevent pseudos from being combined
2112 into the address of a MEM, so only prevent the combination if
2113 i1 or i2 set the same MEM. */
2123 /* This is the same test done in can_combine_p except we can't test
2124 all_adjacent; we don't have to, since this instruction will stay
2125 in place, thus we are not considering increasing the lifetime of
2126 INNER_DEST.
2128 Also, if this insn sets a function argument, combining it with
2129 something that might need a spill could clobber a previous
2130 function argument; the all_adjacent test in can_combine_p also
2131 checks this; here, we do a more specific test for this case. */
2141 /* If DEST is used in I3, it is being killed in this insn, so
2142 record that for later. We have to consider paradoxical
2143 subregs here, since they kill the whole register, but we
2144 ignore partial subregs, STRICT_LOW_PART, etc.
2145 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2146 STACK_POINTER_REGNUM, since these are always considered to be
2147 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2155 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2161 {
2166 }
2167 }
2170 {
2177 }
2180 }
2181 \f
2182 /* Return true if X is an arithmetic expression that contains a multiplication
2183 and division. We don't count multiplications by powers of two here. */
2185 static bool
2187 {
2189 {
2205 }
2206 }
2207 \f
2208 /* Determine whether INSN can be used in a combination. Return true if
2209 not. This is used in try_combine to detect early some cases where we
2210 can't perform combinations. */
2212 static bool
2214 {
2215 rtx set;
2218 /* If this isn't really an insn, we can't do anything.
2219 This can occur when flow deletes an insn that it has merged into an
2220 auto-increment address. */
2224 /* Never combine loads and stores involving hard regs that are likely
2225 to be spilled. The register allocator can usually handle such
2226 reg-reg moves by tying. If we allow the combiner to make
2227 substitutions of likely-spilled regs, reload might die.
2228 As an exception, we allow combinations involving fixed regs; these are
2229 not available to the register allocator so there's no risk involved. */
2243 #ifdef LEAF_REGISTERS
2245 #else
2246 )
2247 #endif
2254 }
2256 struct likely_spilled_retval_info
2257 {
2260 };
2262 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2263 hard registers that are known to be written to / clobbered in full. */
2264 static void
2266 {
2283 else
2286 }
2288 /* Return true iff part of the return value is live during INSN, and
2289 it is likely spilled. This can happen when more than one insn is needed
2290 to copy the return value, e.g. when we consider to combine into the
2291 second copy insn for a complex value. */
2293 static bool
2295 {
2297 rtx reg;
2300 /* We assume here that no machine mode needs more than
2301 32 hard registers when the value overlaps with a register
2302 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2317 /* Disregard parts of the return value that are set later. */
2326 /* Check if any of the (probably) live return value registers is
2327 likely spilled. */
2328 nregs --;
2329 do
2330 {
2336 }
2338 /* Adjust INSN after we made a change to its destination.
2340 Changing the destination can invalidate notes that say something about
2341 the results of the insn and a LOG_LINK pointing to the insn. */
2343 static void
2345 {
2346 /* For notes, be conservative and simply remove them. */
2349 /* The new insn will have a destination that was previously the destination
2350 of an insn just above it. Call distribute_links to make a LOG_LINK from
2351 the next use of that destination. */
2367 }
2369 /* Return TRUE if combine can reuse reg X in mode MODE.
2370 ADDED_SETS is trueif the original set is still required. */
2371 static bool
2373 {
2379 /* Don't change between modes with different underlying register sizes,
2380 since this could lead to invalid subregs. */
2386 /* Allow hard registers if the new mode is legal, and occupies no more
2387 registers than the old mode. */
2392 /* Or a pseudo that is only used once. */
2395 && !added_sets
2397 }
2400 /* Check whether X, the destination of a set, refers to part of
2401 the register specified by REG. */
2403 static bool
2405 {
2406 /* Check that reg is an integer mode register. */
2418 }
2420 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2421 by an arbitrary number of CLOBBERs. */
2422 static bool
2424 {
2439 {
2446 }
2448 }
2450 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2451 CLOBBERs), can be split into individual SETs in that order, without
2452 changing semantics. */
2453 static bool
2455 {
2463 {
2472 }
2475 }
2477 /* Return whether X is just a single_set, with the source
2478 a general_operand. */
2479 static bool
2481 {
2487 }
2489 /* Callback function to count autoincs. */
2491 static int
2493 {
2497 }
2499 /* Try to combine the insns I0, I1 and I2 into I3.
2500 Here I0, I1 and I2 appear earlier than I3.
2501 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2502 I3.
2504 If we are combining more than two insns and the resulting insn is not
2505 recognized, try splitting it into two insns. If that happens, I2 and I3
2506 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2507 Otherwise, I0, I1 and I2 are pseudo-deleted.
2509 Return 0 if the combination does not work. Then nothing is changed.
2510 If we did the combination, return the insn at which combine should
2511 resume scanning.
2513 Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2514 new direct jump instruction.
2516 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2517 been I3 passed to an earlier try_combine within the same basic
2518 block. */
2523 {
2524 /* New patterns for I3 and I2, respectively. */
2528 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2529 dead. */
2531 /* Total number of SETs to put into I3. */
2533 /* Nonzero if I2's or I1's body now appears in I3. */
2535 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2537 /* Contains I3 if the destination of I3 is used in its source, which means
2538 that the old life of I3 is being killed. If that usage is placed into
2539 I2 and not in I3, a REG_DEAD note must be made. */
2541 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2543 /* Copy of SET_SRC of I1 and I0, if needed. */
2545 /* Set if I2DEST was reused as a scratch register. */
2547 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2549 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2555 /* Notes that must be added to REG_NOTES in I3 and I2. */
2557 /* Notes that we substituted I3 into I2 instead of the normal case. */
2559 /* Notes that I1, I2 or I3 is a MULT operation. */
2569 rtx temp_expr;
2572 rtx new_other_notes;
2577 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2578 never be). */
2582 /* Only try four-insn combinations when there's high likelihood of
2583 success. Look for simple insns, such as loads of constants or
2584 binary operations involving a constant. */
2586 {
2596 {
2599 rtx src;
2604 {
2607 }
2609 ngood++;
2612 nshift++;
2613 }
2615 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2616 are likely manipulating its value. Ideally we'll be able to combine
2617 all four insns into a bitfield insertion of some kind.
2619 Note the source in I0 might be inside a sign/zero extension and the
2620 memory modes in I0 and I3 might be different. So extract the address
2621 from the destination of I3 and search for it in the source of I0.
2623 In the event that there's a match but the source/dest do not actually
2624 refer to the same memory, the worst that happens is we try some
2625 combinations that we wouldn't have otherwise. */
2627 /* Ensure the source of SET0 is a MEM, possibly buried inside
2628 an extension. */
2634 /* Ensure the destination of SET3 is a MEM. */
2636 /* Would it be better to extract the base address for the MEM
2637 in SET3 and look for that? I don't have cases where it matters
2638 but I could envision such cases. */
2644 }
2646 /* Exit early if one of the insns involved can't be used for
2647 combinations. */
2658 combine_attempts++;
2661 /* Reset the hard register usage information. */
2665 {
2672 else
2682 }
2684 /* If multiple insns feed into one of I2 or I3, they can be in any
2685 order. To simplify the code below, reorder them in sequence. */
2696 /* First check for one important special case that the code below will
2697 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2698 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2699 we may be able to replace that destination with the destination of I3.
2700 This occurs in the common code where we compute both a quotient and
2701 remainder into a structure, in which case we want to do the computation
2702 directly into the structure to avoid register-register copies.
2704 Note that this case handles both multiple sets in I2 and also cases
2705 where I2 has a number of CLOBBERs inside the PARALLEL.
2707 We make very conservative checks below and only try to handle the
2708 most common cases of this. For example, we only handle the case
2709 where I2 and I3 are adjacent to avoid making difficult register
2710 usage tests. */
2718 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2719 below would need to check what is inside (and reg_overlap_mentioned_p
2720 doesn't support those codes anyway). Don't allow those destinations;
2721 the resulting insn isn't likely to be recognized anyway. */
2727 {
2730 /* Make sure that the destination of I3,
2731 which we are going to substitute into one output of I2,
2732 is not used within another output of I2. We must avoid making this:
2733 (parallel [(set (mem (reg 69)) ...)
2734 (set (reg 69) ...)])
2735 which is not well-defined as to order of actions.
2736 (Besides, reload can't handle output reloads for this.)
2738 The problem can also happen if the dest of I3 is a memory ref,
2739 if another dest in I2 is an indirect memory ref.
2741 Neither can this PARALLEL be an asm. We do not allow combining
2742 that usually (see can_combine_p), so do not here either. */
2745 {
2754 }
2760 {
2761 combine_merges++;
2771 /* Replace the dest in I2 with our dest and make the resulting
2772 insn the new pattern for I3. Then skip to where we validate
2773 the pattern. Everything was set up above. */
2778 }
2779 }
2781 /* If I2 is setting a pseudo to a constant and I3 is setting some
2782 sub-part of it to another constant, merge them by making a new
2783 constant. */
2791 {
2798 {
2803 {
2809 }
2810 }
2811 else
2812 {
2816 {
2819 }
2820 }
2823 {
2824 /* If this is the low part, we're done. */
2826 ;
2827 /* Handle the case where inner is twice the size of outer. */
2831 /* Otherwise give up for now. */
2832 else
2834 }
2837 {
2845 combine_merges++;
2852 /* Replace the source in I2 with the new constant and make the
2853 resulting insn the new pattern for I3. Then skip to where we
2854 validate the pattern. Everything was set up above. */
2860 /* The dest of I3 has been replaced with the dest of I2. */
2863 }
2864 }
2866 /* If we have no I1 and I2 looks like:
2867 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2868 (set Y OP)])
2869 make up a dummy I1 that is
2870 (set Y OP)
2871 and change I2 to be
2872 (set (reg:CC X) (compare:CC Y (const_int 0)))
2874 (We can ignore any trailing CLOBBERs.)
2876 This undoes a previous combination and allows us to match a branch-and-
2877 decrement insn. */
2889 {
2890 /* We make I1 with the same INSN_UID as I2. This gives it
2891 the same DF_INSN_LUID for value tracking. Our fake I1 will
2892 never appear in the insn stream so giving it the same INSN_UID
2893 as I2 will not cause a problem. */
2906 }
2908 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2909 make those two SETs separate I1 and I2 insns, and make an I0 that is
2910 the original I1. */
2918 {
2919 /* If there is no I1, there is no I0 either. */
2922 /* We make I1 with the same INSN_UID as I2. This gives it
2923 the same DF_INSN_LUID for value tracking. Our fake I1 will
2924 never appear in the insn stream so giving it the same INSN_UID
2925 as I2 will not cause a problem. */
2933 }
2935 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2937 {
2942 }
2944 {
2949 }
2951 {
2956 }
2958 /* With non-call exceptions we can end up trying to combine multiple
2959 insns with possible EH side effects. Make sure we can combine
2960 that to a single insn which means there must be at most one insn
2961 in the combination with an EH side effect. */
2963 {
2968 {
2974 {
2980 }
2981 }
2982 }
2984 /* Record whether i2 and i3 are trivial moves. */
2988 /* Record whether I2DEST is used in I2SRC and similarly for the other
2989 cases. Knowing this will help in register status updating below. */
3000 /* For the earlier insns, determine which of the subsequent ones they
3001 feed. */
3008 /* Ensure that I3's pattern can be the destination of combines. */
3014 {
3017 }
3019 /* See if any of the insns is a MULT operation. Unless one is, we will
3020 reject a combination that is, since it must be slower. Be conservative
3021 here. */
3029 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3030 We used to do this EXCEPT in one case: I3 has a post-inc in an
3031 output operand. However, that exception can give rise to insns like
3032 mov r3,(r3)+
3033 which is a famous insn on the PDP-11 where the value of r3 used as the
3034 source was model-dependent. Avoid this sort of thing. */
3036 #if 0
3042 /* It's not the exception. */
3043 #endif
3045 {
3046 rtx link;
3052 {
3055 }
3056 }
3058 /* See if the SETs in I1 or I2 need to be kept around in the merged
3059 instruction: whenever the value set there is still needed past I3.
3060 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3062 For the SET in I1, we have two cases: if I1 and I2 independently feed
3063 into I3, the set in I1 needs to be kept around unless I1DEST dies
3064 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3065 in I1 needs to be kept around unless I1DEST dies or is set in either
3066 I2 or I3. The same considerations apply to I0. */
3073 else
3081 else
3084 /* We are about to copy insns for the case where they need to be kept
3085 around. Check that they can be copied in the merged instruction. */
3091 {
3094 }
3096 /* We cannot safely duplicate volatile references in any case. */
3101 {
3104 }
3106 /* Count how many auto_inc expressions there were in the original insns;
3107 we need to have the same number in the resulting patterns. */
3116 /* If the set in I2 needs to be kept around, we must make a copy of
3117 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118 PATTERN (I2), we are only substituting for the original I1DEST, not into
3119 an already-substituted copy. This also prevents making self-referential
3120 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121 I2DEST. */
3124 {
3127 else
3129 }
3132 {
3135 else
3137 }
3140 {
3143 else
3145 }
3147 combine_merges++;
3149 /* Substitute in the latest insn for the regs set by the earlier ones. */
3155 /* Many machines have insns that can both perform an
3156 arithmetic operation and set the condition code. These operations will
3157 be represented as a PARALLEL with the first element of the vector
3158 being a COMPARE of an arithmetic operation with the constant zero.
3159 The second element of the vector will set some pseudo to the result
3160 of the same arithmetic operation. If we simplify the COMPARE, we won't
3161 match such a pattern and so will generate an extra insn. Here we test
3162 for this case, where both the comparison and the operation result are
3163 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164 I2SRC. Later we will make the PARALLEL that contains I2. */
3170 {
3171 rtx newpat_dest;
3177 scalar_int_mode mode;
3186 {
3192 }
3194 /* Do the rest only if op1 is const0_rtx, which may be the
3195 result of simplification. */
3197 {
3198 /* If a single use of the CC is found, prepare to modify it
3199 when SELECT_CC_MODE returns a new CC-class mode, or when
3200 the above simplify_compare_const() returned a new comparison
3201 operator. undobuf.other_insn is assigned the CC use insn
3202 when modifying it. */
3204 {
3205 #ifdef SELECT_CC_MODE
3206 machine_mode new_mode
3211 {
3216 else
3217 {
3220 }
3221 }
3222 #endif
3223 /* Cases for modifying the CC-using comparison. */
3225 /* ??? Do we need to verify the zero rtx? */
3227 {
3228 /* Replace cc_use_loc with entire new RTX. */
3233 }
3235 {
3236 /* Just replace the CC reg with a new mode. */
3239 }
3240 }
3242 /* Now we modify the current newpat:
3243 First, SET_DEST(newpat) is updated if the CC mode has been
3244 altered. For targets without SELECT_CC_MODE, this should be
3245 optimized away. */
3248 /* This is always done to propagate i2src into newpat. */
3251 /* Create new version of i2pat if needed; the below PARALLEL
3252 creation needs this to work correctly. */
3256 }
3257 }
3260 {
3261 /* It is possible that the source of I2 or I1 may be performing
3262 an unneeded operation, such as a ZERO_EXTEND of something
3263 that is known to have the high part zero. Handle that case
3264 by letting subst look at the inner insns.
3266 Another way to do this would be to have a function that tries
3267 to simplify a single insn instead of merging two or more
3268 insns. We don't do this because of the potential of infinite
3269 loops and because of the potential extra memory required.
3270 However, doing it the way we are is a bit of a kludge and
3271 doesn't catch all cases.
3273 But only do this if -fexpensive-optimizations since it slows
3274 things down and doesn't usually win.
3276 This is not done in the COMPARE case above because the
3277 unmodified I2PAT is used in the PARALLEL and so a pattern
3278 with a modified I2SRC would not match. */
3281 {
3282 /* Pass pc_rtx so no substitutions are done, just
3283 simplifications. */
3285 {
3288 }
3292 }
3297 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3298 copy of I2SRC each time we substitute it, in order to avoid creating
3299 self-referential RTL when we will be substituting I1SRC for I1DEST
3300 later. Likewise if I0 feeds into I2, either directly or indirectly
3301 through I1, and I0DEST is in I0SRC. */
3308 /* Record whether I2's body now appears within I3's body. */
3310 }
3312 /* If we already got a failure, don't try to do more. Otherwise, try to
3313 substitute I1 if we have it. */
3316 {
3317 /* Before we can do this substitution, we must redo the test done
3318 above (see detailed comments there) that ensures I1DEST isn't
3319 mentioned in any SETs in NEWPAT that are field assignments. */
3322 {
3325 }
3330 /* If the following substitution will modify I1SRC, make a copy of it
3331 for the case where it is substituted for I1DEST in I2PAT later. */
3335 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3336 copy of I1SRC each time we substitute it, in order to avoid creating
3337 self-referential RTL when we will be substituting I0SRC for I0DEST
3338 later. */
3343 /* Record whether I1's body now appears within I3's body. */
3345 }
3347 /* Likewise for I0 if we have it. */
3350 {
3353 {
3356 }
3358 /* If the following substitution will modify I0SRC, make a copy of it
3359 for the case where it is substituted for I0DEST in I1PAT later. */
3362 /* And a copy for I0DEST in I2PAT substitution. */
3371 }
3374 {
3379 {
3384 }
3385 }
3387 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3388 to count all the ways that I2SRC and I1SRC can be used. */
3397 /* Fail if we tried to make a new register. */
3399 /* Fail if we couldn't do something and have a CLOBBER. */
3401 /* Fail if this new pattern is a MULT and we didn't have one before
3402 at the outer level. */
3405 {
3408 }
3410 /* If the actions of the earlier insns must be kept
3411 in addition to substituting them into the latest one,
3412 we must make a new PARALLEL for the latest insn
3413 to hold additional the SETs. */
3416 {
3418 combine_extras++;
3421 {
3427 }
3428 else
3429 {
3434 }
3440 {
3447 }
3449 {
3459 }
3460 }
3462 validate_replacement:
3464 /* Note which hard regs this insn has as inputs. */
3467 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3468 consider splitting this pattern, we might need these clobbers. */
3471 {
3477 }
3479 /* We have recognized nothing yet. */
3482 /* See if this is a PARALLEL of two SETs where one SET's destination is
3483 a register that is unused and this isn't marked as an instruction that
3484 might trap in an EH region. In that case, we just need the other SET.
3485 We prefer this over the PARALLEL.
3487 This can occur when simplifying a divmod insn. We *must* test for this
3488 case here because the code below that splits two independent SETs doesn't
3489 handle this case correctly when it updates the register status.
3491 It's pointless doing this if we originally had two sets, one from
3492 i3, and one from i2. Combining then splitting the parallel results
3493 in the original i2 again plus an invalid insn (which we delete).
3494 The net effect is only to move instructions around, which makes
3495 debug info less accurate.
3497 If the remaining SET came from I2 its destination should not be used
3498 between I2 and I3. See PR82024. */
3503 {
3514 {
3517 }
3526 {
3531 {
3537 }
3538 }
3542 }
3544 /* Is the result of combination a valid instruction? */
3548 /* If we were combining three insns and the result is a simple SET
3549 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3550 insns. There are two ways to do this. It can be split using a
3551 machine-specific method (like when you have an addition of a large
3552 constant) or by combine in the function find_split_point. */
3556 {
3560 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3561 use I2DEST as a scratch register will help. In the latter case,
3562 convert I2DEST to the mode of the source of NEWPAT if we can. */
3566 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3567 inputs of NEWPAT. */
3569 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3570 possible to try that as a scratch reg. This would require adding
3571 more code to make it work though. */
3574 {
3577 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3578 (temporarily, until we are committed to this instruction
3579 combination) does not work: for example, any call to nonzero_bits
3580 on the register (from a splitter in the MD file, for example)
3581 will get the old information, which is invalid.
3583 Since nowadays we can create registers during combine just fine,
3584 we should just create a new one here, not reuse i2dest. */
3586 /* First try to split using the original register as a
3587 scratch register. */
3591 i2dest)));
3594 /* If that didn't work, try changing the mode of I2DEST if
3595 we can. */
3600 {
3602 rtx ni2dest;
3606 else
3607 {
3610 }
3612 parallel = (gen_rtx_PARALLEL
3616 ni2dest))));
3621 {
3629 }
3630 }
3633 }
3635 /* If recog_for_combine has discarded clobbers, try to use them
3636 again for the split. */
3638 {
3641 }
3644 {
3649 }
3653 {
3663 /* If I2 or I3 has multiple SETs, we won't know how to track
3664 register status, so don't use these insns. If I2's destination
3665 is used between I2 and I3, we also can't use these insns. */
3675 /* It is possible that both insns now set the destination of I3.
3676 If so, we must show an extra use of it. */
3679 {
3698 }
3699 }
3701 /* If we can split it and use I2DEST, go ahead and see if that
3702 helps things be recognized. Verify that none of the registers
3703 are set between I2 and I3. */
3706 /* We need I2DEST in the proper mode. If it is a hard register
3707 or the only use of a pseudo, we can change its mode.
3708 Make sure we don't change a hard register to have a mode that
3709 isn't valid for it, or change the number of registers. */
3716 /* We can't overwrite I2DEST if its value is still used by
3717 NEWPAT. */
3719 /* We should not split a possibly trapping part when we
3720 care about non-call EH and have REG_EH_REGION notes
3721 to distribute. */
3723 && has_non_call_exception
3725 {
3734 /* *SPLIT may be part of I2SRC, so make sure we have the
3735 original expression around for later debug processing.
3736 We should not need I2SRC any more in other cases. */
3739 else
3742 /* Get NEWDEST as a register in the proper mode. We have already
3743 validated that we can do this. */
3745 {
3748 else
3749 {
3752 }
3753 }
3755 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3756 an ASHIFT. This can occur if it was inside a PLUS and hence
3757 appeared to be a memory address. This is a kludge. */
3762 {
3766 /* Update split_code because we may not have a multiply
3767 anymore. */
3769 }
3771 /* Similarly for (plus (mult FOO (const_int pow2))). */
3777 {
3782 i_rtx));
3783 /* Update split_code because we may not have a multiply
3784 anymore. */
3786 }
3788 #ifdef INSN_SCHEDULING
3789 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3790 be written as a ZERO_EXTEND. */
3792 {
3793 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3794 what it really is. */
3799 else
3802 }
3803 #endif
3805 /* Attempt to split binary operators using arithmetic identities. */
3809 {
3816 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3818 {
3823 }
3824 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3831 {
3837 /* Split both "((X op Y) op X) op Y" and
3838 "((X op Y) op Y) op X" as "T op T" where T is
3839 "X op Y". */
3842 {
3847 }
3848 /* Split "((X op X) op Y) op Y)" as "T op T" where
3849 T is "X op Y". */
3851 {
3857 }
3858 }
3859 }
3862 {
3865 }
3869 /* recog_for_combine might have added CLOBBERs to newi2pat.
3870 Make sure NEWPAT does not depend on the clobbered regs. */
3874 {
3877 {
3880 }
3881 }
3883 /* If the split point was a MULT and we didn't have one before,
3884 don't use one now. */
3887 }
3888 }
3890 /* Check for a case where we loaded from memory in a narrow mode and
3891 then sign extended it, but we need both registers. In that case,
3892 we have a PARALLEL with both loads from the same memory location.
3893 We can split this into a load from memory followed by a register-register
3894 copy. This saves at least one insn, more if register allocation can
3895 eliminate the copy.
3897 We cannot do this if the destination of the first assignment is a
3898 condition code register. We eliminate this case by making sure
3899 the SET_DEST and SET_SRC have the same mode.
3901 We cannot do this if the destination of the second assignment is
3902 a register that we have already assumed is zero-extended. Similarly
3903 for a SUBREG of such a register. */
3922 BITS_PER_WORD)
3924 HOST_BITS_PER_INT)
3932 BITS_PER_WORD)
3934 HOST_BITS_PER_INT)
3941 {
3942 rtx ni2dest;
3956 }
3958 /* Similarly, check for a case where we have a PARALLEL of two independent
3959 SETs but we started with three insns. In this case, we can do the sets
3960 as two separate insns. This case occurs when some SET allows two
3961 other insns to combine, but the destination of that SET is still live.
3963 Also do this if we started with two insns and (at least) one of the
3964 resulting sets is a noop; this noop will be deleted later.
3966 Also do this if we started with two insns neither of which was a simple
3967 move. */
3974 && (i1
3988 {
3992 /* Normally, it doesn't matter which of the two is done first, but
3993 one which uses any regs/memory set in between i2 and i3 can't
3994 be first. The PARALLEL might also have been pre-existing in i3,
3995 so we need to make sure that we won't wrongly hoist a SET to i2
3996 that would conflict with a death note present in there, or would
3997 have its dest modified between i2 and i3. */
4005 /* If I3 is a jump, ensure that set0 is a jump so that
4006 we do not create invalid RTL. */
4008 )
4009 {
4012 }
4020 /* If I3 is a jump, ensure that set1 is a jump so that
4021 we do not create invalid RTL. */
4023 )
4024 {
4027 }
4028 else
4029 {
4032 }
4037 {
4038 /* recog_for_combine might have added CLOBBERs to newi2pat.
4039 Make sure NEWPAT does not depend on the clobbered regs. */
4041 {
4044 {
4047 {
4050 }
4051 }
4052 }
4056 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4057 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4058 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4060 {
4063 {
4067 {
4070 }
4071 }
4072 }
4076 }
4077 }
4079 /* If it still isn't recognized, fail and change things back the way they
4080 were. */
4082 /* Is the result a reasonable ASM_OPERANDS? */
4084 {
4087 }
4089 /* If we had to change another insn, make sure it is valid also. */
4091 {
4099 {
4102 }
4103 }
4105 /* Only allow this combination if insn_cost reports that the
4106 replacement instructions are cheaper than the originals. */
4108 {
4111 }
4114 {
4119 {
4124 /* Temporarily revert mode back. */
4128 {
4129 /* If we used i2dest as a scratch register with a
4130 different mode, substitute it for the original
4131 i2src while its original mode is temporarily
4132 restored, and then clear i2scratch so that we don't
4133 do it again later. */
4135 this_basic_block);
4137 /* Put back the new mode. */
4139 }
4140 else
4141 {
4146 {
4149 }
4150 else
4151 {
4158 }
4160 /* We're dealing with a reg that changed mode but not
4161 meaning, so we want to turn it into a subreg for
4162 the new mode. However, because of REG sharing and
4163 because its mode had already changed, we have to do
4164 it in two steps. First, replace any debug uses of
4165 reg, with its original mode temporarily restored,
4166 with this copy we have created; then, replace the
4167 copy with the SUBREG of the original shared reg,
4168 once again changed to the new mode. */
4170 this_basic_block);
4174 this_basic_block);
4175 }
4176 }
4177 }
4179 /* If we will be able to accept this, we have made a
4180 change to the destination of I3. This requires us to
4181 do a few adjustments. */
4184 {
4187 }
4189 /* We now know that we can do this combination. Merge the insns and
4190 update the status of registers and LOG_LINKS. */
4193 {
4198 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4199 ensure that they are still valid. Then add any non-duplicate
4200 notes added by recog_for_combine. */
4202 {
4211 /* Simply drop equal note since it may be no longer valid
4212 for other_insn. It may be possible to record that CC
4213 register is changed and only discard those notes, but
4214 in practice it's unnecessary complication and doesn't
4215 give any meaningful improvement.
4217 See PR78559. */
4221 }
4225 NULL_RTX);
4226 }
4229 {
4230 /* I3 now uses what used to be its destination and which is now
4231 I2's destination. This requires us to do a few adjustments. */
4234 }
4237 {
4238 /* We might need a LOG_LINK from I3 to I2. But then we used to
4239 have one, so we still will.
4241 However, some later insn might be using I2's dest and have
4242 a LOG_LINK pointing at I3. We should change it to point at
4243 I2 instead. */
4245 /* newi2pat is usually a SET here; however, recog_for_combine might
4246 have added some clobbers. */
4254 {
4259 !done
4260 && insn
4264 {
4270 {
4274 }
4275 }
4276 }
4277 }
4279 {
4284 /* Compute which registers we expect to eliminate. newi2pat may be setting
4285 either i3dest or i2dest, so we must check it. */
4288 || !i2dest_killed
4290 /* For i1, we need to compute both local elimination and global
4291 elimination information with respect to newi2pat because i1dest
4292 may be the same as i3dest, in which case newi2pat may be setting
4293 i1dest. Global information is used when distributing REG_DEAD
4294 note for i2 and i3, in which case it does matter if newi2pat sets
4295 i1dest or not.
4297 Local information is used when distributing REG_DEAD note for i1,
4298 in which case it doesn't matter if newi2pat sets i1dest or not.
4299 See PR62151, if we have four insns combination:
4300 i0: r0 <- i0src
4301 i1: r1 <- i1src (using r0)
4302 REG_DEAD (r0)
4303 i2: r0 <- i2src (using r1)
4304 i3: r3 <- i3src (using r0)
4305 ix: using r0
4306 From i1's point of view, r0 is eliminated, no matter if it is set
4307 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4308 should be discarded.
4310 Note local information only affects cases in forms like "I1->I2->I3",
4311 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4312 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4313 i0dest anyway. */
4315 || !i1dest_killed
4320 /* Same case as i1. */
4327 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4328 clear them. */
4336 /* Ensure that we do not have something that should not be shared but
4337 occurs multiple times in the new insns. Check this by first
4338 resetting all the `used' flags and then copying anything is shared. */
4362 {
4365 {
4367 {
4368 /* I2SRC must still be meaningful at this point. Some
4369 splitting operations can invalidate I2SRC, but those
4370 operations do not apply to calls. */
4374 }
4381 }
4382 }
4387 /* We had one special case above where I2 had more than one set and
4388 we replaced a destination of one of those sets with the destination
4389 of I3. In that case, we have to update LOG_LINKS of insns later
4390 in this basic block. Note that this (expensive) case is rare.
4392 Also, in this case, we must pretend that all REG_NOTEs for I2
4393 actually came from I3, so that REG_UNUSED notes from I2 will be
4394 properly handled. */
4397 {
4406 temp_insn
4416 {
4421 }
4422 else
4425 }
4433 {
4436 this_basic_block);
4439 }
4440 else
4441 {
4444 this_basic_block);
4446 }
4449 {
4454 this_basic_block);
4456 }
4459 {
4464 this_basic_block);
4466 }
4468 /* Get death notes for everything that is now used in either I3 or
4469 I2 and used to die in a previous insn. If we built two new
4470 patterns, move from I1 to I2 then I2 to I3 so that we get the
4471 proper movement on registers that I2 modifies. */
4477 else
4483 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4500 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4501 know these are REG_UNUSED and want them to go to the desired insn,
4502 so we always pass it as i3. */
4506 NULL_RTX);
4510 NULL_RTX);
4512 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4513 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4514 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4515 in that case, it might delete I2. Similarly for I2 and I1.
4516 Show an additional death due to the REG_DEAD note we make here. If
4517 we discard it in distribute_notes, we will decrement it again. */
4520 {
4525 else
4528 }
4531 {
4536 else
4539 }
4542 {
4547 else
4550 }
4553 {
4558 else
4561 }
4569 {
4574 /* The insn that used to set this register doesn't exist, and
4575 this life of the register may not exist either. See if one of
4576 I3's links points to an insn that sets I2DEST. If it does,
4577 that is now the last known value for I2DEST. If we don't update
4578 this and I2 set the register to a value that depended on its old
4579 contents, we will get confused. If this insn is used, thing
4580 will be set correctly in combine_instructions. */
4588 /* If the reg formerly set in I2 died only once and that was in I3,
4589 zero its use count so it won't make `reload' do any work. */
4592 && ! i2dest_in_i2src
4595 }
4598 {
4611 && ! i1dest_in_i1src
4614 }
4617 {
4630 && ! i0dest_in_i0src
4633 }
4635 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4636 been made to this insn. The order is important, because newi2pat
4637 can affect nonzero_bits of newpat. */
4641 }
4644 {
4646 {
4649 }
4651 }
4654 {
4656 {
4659 }
4661 }
4664 {
4666 {
4669 }
4671 }
4674 {
4676 {
4679 }
4681 }
4684 {
4686 {
4689 }
4691 }
4693 /* Set new_direct_jump_p if a new return or simple jump instruction
4694 has been created. Adjust the CFG accordingly. */
4696 {
4700 }
4705 {
4708 }
4712 {
4718 }
4723 {
4729 }
4731 /* A noop might also need cleaning up of CFG, if it comes from the
4732 simplification of a jump. */
4737 {
4740 }
4747 {
4750 }
4752 combine_successes++;
4762 }
4763 \f
4764 /* Get a marker for undoing to the current state. */
4768 {
4770 }
4772 /* Undo the modifications up to the marker. */
4774 static void
4776 {
4780 {
4785 {
4801 }
4805 }
4808 }
4810 /* Undo all the modifications recorded in undobuf. */
4812 static void
4814 {
4816 }
4818 /* We've committed to accepting the changes we made. Move all
4819 of the undos to the free list. */
4821 static void
4823 {
4827 {
4831 }
4833 }
4834 \f
4835 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4836 where we have an arithmetic expression and return that point. LOC will
4837 be inside INSN.
4839 try_combine will call this function to see if an insn can be split into
4840 two insns. */
4844 {
4854 /* First special-case some codes. */
4856 {
4858 #ifdef INSN_SCHEDULING
4859 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4860 point. */
4863 #endif
4867 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4868 using LO_SUM and HIGH. */
4871 {
4879 }
4881 /* If we have a PLUS whose second operand is a constant and the
4882 address is not valid, perhaps we can split it up using
4883 the machine-specific way to split large constants. We use
4884 the first pseudo-reg (one of the virtual regs) as a placeholder;
4885 it will not remain in the result. */
4890 {
4893 subst_insn);
4895 /* This should have produced two insns, each of which sets our
4896 placeholder. If the source of the second is a valid address,
4897 we can put both sources together and make a split point
4898 in the middle. */
4911 && memory_address_addr_space_p
4914 {
4918 /* Replace the placeholder in SRC2 with SRC1. If we can
4919 find where in SRC2 it was placed, that can become our
4920 split point and we can replace this address with SRC2.
4921 Just try two obvious places. */
4932 {
4935 }
4936 }
4938 /* If that didn't work and we have a nested plus, like:
4939 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4940 is valid address, try to split (REG1 * CONST1). */
4947 {
4952 {
4955 }
4957 }
4964 {
4969 {
4972 }
4974 }
4976 /* If that didn't work, perhaps the first operand is complex and
4977 needs to be computed separately, so make a split point there.
4978 This will occur on machines that just support REG + CONST
4979 and have a constant moved through some previous computation. */
4984 }
4986 /* If we have a PLUS whose first operand is complex, try computing it
4987 separately by making a split there. */
4998 /* See if we can split SET_SRC as it stands. */
5003 /* See if we can split SET_DEST as it stands. */
5008 /* See if this is a bitfield assignment with everything constant. If
5009 so, this is an IOR of an AND, so split it into that. */
5021 {
5027 rtx or_mask;
5036 else
5037 {
5043 or_mask));
5044 }
5051 }
5053 /* Otherwise, see if this is an operation that we can split into two.
5054 If so, try to split that. */
5058 {
5060 /* If we are AND'ing with a large constant that is only a single
5061 bit and the result is only being used in a context where we
5062 need to know if it is zero or nonzero, replace it with a bit
5063 extraction. This will avoid the large constant, which might
5064 have taken more than one insn to make. If the constant were
5065 not a valid argument to the AND but took only one insn to make,
5066 this is no worse, but if it took more than one insn, it will
5067 be better. */
5077 {
5083 {
5086 }
5087 }
5091 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5092 is known to be on, this can be converted into a NEG of a shift. */
5098 {
5105 pos_rtx)));
5110 }
5116 /* We can't optimize if either mode is a partial integer
5117 mode as we don't know how many bits are significant
5118 in those modes. */
5134 {
5142 }
5147 }
5153 {
5154 /* For unsigned, we have a choice of a shift followed by an
5155 AND or two shifts. Use two shifts for field sizes where the
5156 constant might be too large. We assume here that we can
5157 always at least get 8-bit constants in an AND insn, which is
5158 true for every current RISC. */
5161 {
5162 unsigned HOST_WIDE_INT mask
5167 gen_rtx_LSHIFTRT
5174 }
5175 else
5176 {
5180 gen_rtx_fmt_ee
5190 }
5191 }
5193 /* See if this is a simple operation with a constant as the second
5194 operand. It might be that this constant is out of range and hence
5195 could be used as a split point. */
5203 /* Finally, see if this is a simple operation with its first operand
5204 not in a register. The operation might require this operand in a
5205 register, so return it as a split point. We can always do this
5206 because if the first operand were another operation, we would have
5207 already found it as a split point. */
5216 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5217 it is better to write this as (not (ior A B)) so we can split it.
5218 Similarly for IOR. */
5220 {
5228 }
5230 /* Many RISC machines have a large set of logical insns. If the
5231 second operand is a NOT, put it first so we will try to split the
5232 other operand first. */
5234 {
5238 }
5243 /* Canonicalization can produce (minus A (mult B C)), where C is a
5244 constant. It may be better to try splitting (plus (mult B -C) A)
5245 instead if this isn't a multiply by a power of two. */
5249 {
5257 mode)),
5260 }
5262 /* Split at a multiply-accumulate instruction. However if this is
5263 the SET_SRC, we likely do not have such an instruction and it's
5264 worthless to try this split. */
5273 }
5275 /* Otherwise, select our actions depending on our rtx class. */
5277 {
5283 /* fall through */
5291 /* fall through */
5293 /* Some machines have (and (shift ...) ...) insns. If X is not
5294 an AND, but XEXP (X, 0) is, use it as our split point. */
5304 /* Otherwise, we don't have a split point. */
5306 }
5307 }
5308 \f
5309 /* Throughout X, replace FROM with TO, and return the result.
5310 The result is TO if X is FROM;
5311 otherwise the result is X, but its contents may have been modified.
5312 If they were modified, a record was made in undobuf so that
5313 undo_all will (among other things) return X to its original state.
5315 If the number of changes necessary is too much to record to undo,
5316 the excess changes are not made, so the result is invalid.
5317 The changes already made can still be undone.
5318 undobuf.num_undo is incremented for such changes, so by testing that
5319 the caller can tell whether the result is valid.
5321 `n_occurrences' is incremented each time FROM is replaced.
5323 IN_DEST is true if we are processing the SET_DEST of a SET.
5325 IN_COND is true if we are at the top level of a condition.
5327 UNIQUE_COPY is true if each substitution must be unique. We do this
5328 by copying if `n_occurrences' is nonzero. */
5330 static rtx
5332 {
5337 rtx new_rtx;
5339 /* Two expressions are equal if they are identical copies of a shared
5340 RTX or if they are both registers with the same register number
5341 and mode. */
5343 #define COMBINE_RTX_EQUAL_P(X,Y) \
5344 ((X) == (Y) \
5345 || (REG_P (X) && REG_P (Y) \
5346 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5348 /* Do not substitute into clobbers of regs -- this will never result in
5349 valid RTL. */
5354 {
5355 n_occurrences++;
5357 }
5359 /* If X and FROM are the same register but different modes, they
5360 will not have been seen as equal above. However, the log links code
5361 will make a LOG_LINKS entry for that case. If we do nothing, we
5362 will try to rerecognize our original insn and, when it succeeds,
5363 we will delete the feeding insn, which is incorrect.
5365 So force this insn not to match in this (rare) case. */
5370 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5371 of which may contain things that can be combined. */
5375 /* It is possible to have a subexpression appear twice in the insn.
5376 Suppose that FROM is a register that appears within TO.
5377 Then, after that subexpression has been scanned once by `subst',
5378 the second time it is scanned, TO may be found. If we were
5379 to scan TO here, we would find FROM within it and create a
5380 self-referent rtl structure which is completely wrong. */
5384 /* Parallel asm_operands need special attention because all of the
5385 inputs are shared across the arms. Furthermore, unsharing the
5386 rtl results in recognition failures. Failure to handle this case
5387 specially can result in circular rtl.
5389 Solve this by doing a normal pass across the first entry of the
5390 parallel, and only processing the SET_DESTs of the subsequent
5391 entries. Ug. */
5396 {
5399 /* If this substitution failed, this whole thing fails. */
5407 {
5411 {
5414 /* If this substitution failed, this whole thing fails. */
5420 }
5421 }
5422 }
5423 else
5424 {
5428 /* We don't need to process a SET_DEST that is a register or PC, so
5429 set up to skip this common case. All other cases where we want
5430 to suppress replacing something inside a SET_SRC are handled via
5431 the IN_DEST operand. */
5437 /* Trying to simplify the operands of a widening MULT is not likely
5438 to create RTL matching a machine insn. */
5450 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5451 constant. */
5456 {
5458 {
5461 {
5463 {
5466 n_occurrences++;
5467 }
5468 else
5469 {
5473 /* If this substitution failed, this whole thing
5474 fails. */
5478 }
5481 }
5482 }
5484 {
5485 /* If this is a register being set, ignore it. */
5492 ;
5495 {
5496 /* In general, don't install a subreg involving two
5497 modes not tieable. It can worsen register
5498 allocation, and can even make invalid reload
5499 insns, since the reg inside may need to be copied
5500 from in the outside mode, and that may be invalid
5501 if it is an fp reg copied in integer mode.
5503 We allow an exception to this: It is valid if
5504 it is inside another SUBREG and the mode of that
5505 SUBREG and the mode of the inside of TO is
5506 tieable. */
5525 n_occurrences++;
5526 }
5527 else
5528 /* If we are in a SET_DEST, suppress most cases unless we
5529 have gone inside a MEM, in which case we want to
5530 simplify the address. We assume here that things that
5531 are actually part of the destination have their inner
5532 parts in the first expression. This is true for SUBREG,
5533 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5534 things aside from REG and MEM that should appear in a
5535 SET_DEST. */
5537 (((in_dest
5543 unique_copy);
5545 /* If we found that we will have to reject this combination,
5546 indicate that by returning the CLOBBER ourselves, rather than
5547 an expression containing it. This will speed things up as
5548 well as prevent accidents where two CLOBBERs are considered
5549 to be equal, thus producing an incorrect simplification. */
5555 {
5563 }
5569 {
5571 new_rtx,
5575 }
5576 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5577 etc. arguments, otherwise we can ICE before trying to recog
5578 it. See PR104446. */
5582 else
5584 }
5585 }
5586 }
5588 /* Check if we are loading something from the constant pool via float
5589 extension; in this case we would undo compress_float_constant
5590 optimization and degenerate constant load to an immediate value. */
5594 {
5598 }
5600 /* Try to simplify X. If the simplification changed the code, it is likely
5601 that further simplification will help, so loop, but limit the number
5602 of repetitions that will be performed. */
5605 {
5606 /* If X is sufficiently simple, don't bother trying to do anything
5607 with it. */
5616 /* We no longer know the original mode of operand 0 since we
5617 have changed the form of X) */
5619 }
5622 }
5623 \f
5624 /* If X is a commutative operation whose operands are not in the canonical
5625 order, use substitutions to swap them. */
5627 static void
5629 {
5632 {
5636 }
5643 /* Two operands have same precedence, then
5644 first bit of mask select first operand. */
5647 {
5653 else
5658 }
5659 }
5661 /* Simplify X, a piece of RTL. We just operate on the expression at the
5662 outer level; call `subst' to simplify recursively. Return the new
5663 expression.
5665 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5666 if we are inside a SET_DEST. IN_COND is true if we are at the top level
5667 of a condition. */
5669 static rtx
5671 {
5674 scalar_int_mode int_mode;
5675 rtx temp;
5678 /* If this is a commutative operation, put a constant last and a complex
5679 expression first. We don't need to do this for comparisons here. */
5682 /* Try to fold this expression in case we have constants that weren't
5683 present before. */
5686 {
5694 {
5697 {
5701 }
5704 }
5717 }
5720 {
5725 }
5727 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5728 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5729 things. Check for cases where both arms are testing the same
5730 condition.
5732 Don't do anything if all operands are very simple. */
5745 {
5750 /* If everything is a comparison, what we have is highly unlikely
5751 to be simpler, so don't use it. */
5754 /* Similarly, if we end up with one of the expressions the same
5755 as the original, it is certainly not simpler. */
5758 {
5765 /* Simplify the alternative arms; this may collapse the true and
5766 false arms to store-flag values. Be careful to use copy_rtx
5767 here since true_rtx or false_rtx might share RTL with x as a
5768 result of the if_then_else_cond call above. */
5774 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5775 is unlikely to be simpler. */
5778 {
5781 /* Restarting if we generate a store-flag expression will cause
5782 us to loop. Just drop through in this case. */
5784 /* If the result values are STORE_FLAG_VALUE and zero, we can
5785 just make the comparison operation. */
5796 /* Likewise, we can make the negate of a comparison operation
5797 if the result values are - STORE_FLAG_VALUE and zero. */
5805 mode);
5816 mode);
5820 }
5821 }
5822 }
5824 /* First see if we can apply the inverse distributive law. */
5827 {
5831 }
5833 /* If CODE is an associative operation not otherwise handled, see if we
5834 can associate some operands. This can win if they are constants or
5835 if they are logically related (i.e. (a & b) & a). */
5841 {
5843 {
5847 rtx inner;
5849 /* Make sure we pass the constant operand if any as the second
5850 one if this is a commutative operation. */
5858 /* For commutative operations, try the other pair if that one
5859 didn't simplify. */
5861 {
5866 }
5870 }
5871 }
5873 /* A little bit of algebraic simplification here. */
5875 {
5877 /* Ensure that our address has any ASHIFTs converted to MULT in case
5878 address-recognizing predicates are called later. */
5887 /* See if this can be moved to simplify_subreg. */
5890 /* Don't call gen_lowpart if the inner mode
5891 is VOIDmode and we cannot simplify it, as SUBREG without
5892 inner mode is invalid. */
5899 {
5900 rtx temp;
5906 /* If op is known to have all lower bits zero, the result is zero. */
5920 }
5922 /* Don't change the mode of the MEM if that would change the meaning
5923 of the address. */
5930 /* Note that we cannot do any narrowing for non-constants since
5931 we might have been counting on using the fact that some bits were
5932 zero. We now do this in the SET. */
5939 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5940 replaced by (lshiftrt X C). This will convert
5941 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5949 /* If X has only a single bit that might be nonzero, say, bit I, convert
5950 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5951 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5952 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5953 or a SUBREG of one since we'd be making the expression more
5954 complex if it was just a register. */
5961 {
5962 rtx temp1 = simplify_shift_const
5968 /* If all we did was surround TEMP with the two shifts, we
5969 haven't improved anything, so don't use it. Otherwise,
5970 we are better off with TEMP1. */
5975 }
5979 /* We can't handle truncation to a partial integer mode here
5980 because we don't know the real bitsize of the partial
5981 integer mode. */
5990 /* We can truncate a constant value and return it. */
5991 {
5992 poly_int64 c;
5995 }
5997 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
5998 whose value is a comparison can be replaced with a subreg if
5999 STORE_FLAG_VALUE permits. */
6009 /* (const (const X)) can become (const X). Do it this way rather than
6010 returning the inner CONST since CONST can be shared with a
6011 REG_EQUAL note. */
6017 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6018 can add in an offset. find_split_point will split this address up
6019 again if it doesn't match. */
6026 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6027 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6028 bit-field and can be replaced by either a sign_extend or a
6029 sign_extract. The `and' may be a zero_extend and the two
6030 <c>, -<c> constants may be reversed. */
6047 return simplify_shift_const
6054 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6055 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6056 the bitsize of the mode - 1. This allows simplification of
6057 "a = (b & 8) == 0;" */
6064 return simplify_shift_const
6068 const1_rtx),
6072 /* If we are adding two things that have no bits in common, convert
6073 the addition into an IOR. This will often be further simplified,
6074 for example in cases like ((a & 1) + (a & 2)), which can
6075 become a & 3. */
6080 {
6081 /* Try to simplify the expression further. */
6085 /* If we could, great. If not, do not go ahead with the IOR
6086 replacement, since PLUS appears in many special purpose
6087 address arithmetic instructions. */
6095 }
6097 /* Canonicalize x + x into x << 1. */
6106 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6107 (and <foo> (const_int pow2-1)) */
6118 /* If we have (mult (plus A B) C), apply the distributive law and then
6119 the inverse distributive law to see if things simplify. This
6120 occurs mostly in addresses, often when unrolling loops. */
6123 {
6127 }
6129 /* Try simplify a*(b/c) as (a*b)/c. */
6132 {
6138 }
6142 /* If this is a divide by a power of two, treat it as a shift if
6143 its first operand is a shift. */
6163 /* If the first operand is a condition code, we can't do anything
6164 with it. */
6167 {
6175 /* Simplify our comparison, if possible. */
6178 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6179 if only the low-order bit is possibly nonzero in X (such as when
6180 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6181 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6182 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6183 (plus X 1).
6185 Remove any ZERO_EXTRACT we made when thinking this was a
6186 comparison. It may now be simpler to use, e.g., an AND. If a
6187 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6188 the call to make_compound_operation in the SET case.
6190 Don't apply these optimizations if the caller would
6191 prefer a comparison rather than a value.
6192 E.g., for the condition in an IF_THEN_ELSE most targets need
6193 an explicit comparison. */
6196 ;
6214 {
6218 int_mode);
6219 }
6227 {
6231 const1_rtx);
6232 }
6241 {
6244 }
6246 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6247 those above. */
6249 ;
6266 {
6270 int_mode);
6271 }
6280 {
6284 int_mode);
6285 }
6287 /* If X is 0/1, (eq X 0) is X-1. */
6294 {
6297 }
6299 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6300 one bit that might be nonzero, we can convert (ne x 0) to
6301 (ashift x c) where C puts the bit in the sign bit. Remove any
6302 AND with STORE_FLAG_VALUE when we are done, since we are only
6303 going to test the sign bit. */
6311 {
6317 else
6319 }
6321 /* If the code changed, return a whole new comparison.
6322 We also need to avoid using SUBST in cases where
6323 simplify_comparison has widened a comparison with a CONST_INT,
6324 since in that case the wider CONST_INT may fail the sanity
6325 checks in do_SUBST. */
6332 /* Otherwise, keep this operation, but maybe change its operands.
6333 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6336 }
6346 /* If we are processing SET_DEST, we are done. */
6364 /* If this is a shift by a constant amount, simplify it. */
6372 (HOST_WIDE_INT_1U
6377 {
6381 /* If we select a low-part subreg, return that. */
6383 {
6387 }
6388 }
6392 }
6395 }
6396 \f
6397 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6399 static rtx
6401 {
6408 rtx temp;
6411 rtx reversed;
6414 /* Simplify storing of the truth value. */
6419 /* Also when the truth value has to be reversed. */
6425 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6426 in it is being compared against certain values. Get the true and false
6427 comparisons and see if that says anything about the value of each arm. */
6433 {
6434 HOST_WIDE_INT nzb;
6440 /* If FALSE_CODE is EQ, swap the codes and arms. */
6443 {
6446 }
6448 scalar_int_mode from_mode;
6450 {
6451 /* If we are comparing against zero and the expression being
6452 tested has only a single bit that might be nonzero, that is
6453 its value when it is not equal to zero. Similarly if it is
6454 known to be -1 or 0. */
6458 {
6461 }
6466 {
6469 }
6470 }
6472 /* Now simplify an arm if we know the value of the register in the
6473 branch and it is used in the arm. Be careful due to the potential
6474 of locally-shared RTL. */
6491 }
6493 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6494 reversed, do so to avoid needing two sets of patterns for
6495 subtract-and-branch insns. Similarly if we have a constant in the true
6496 arm, the false arm is the same as the first operand of the comparison, or
6497 the false arm is more complicated than the true arm. */
6510 {
6518 /* It is possible that the conditional has been simplified out. */
6521 }
6523 /* If the two arms are identical, we don't need the comparison. */
6528 /* Convert a == b ? b : a to "a". */
6540 /* Look for cases where we have (abs x) or (neg (abs X)). */
6543 && comparison_p
6550 {
6556 return
6559 mode);
6562 }
6564 /* Look for MIN or MAX. */
6567 || (flag_unsafe_math_optimizations
6570 && comparison_p
6575 {
6590 }
6592 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6593 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6594 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6595 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6596 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6597 neither 1 or -1, but it isn't worth checking for. */
6600 && comparison_p
6603 {
6619 /* If an identity-zero op is commutative, check whether there
6620 would be a match if we swapped the operands. */
6641 {
6645 }
6658 {
6662 }
6679 {
6683 }
6696 {
6700 }
6703 {
6713 const_true_rtx));
6721 }
6722 }
6724 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6725 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6726 negation of a single bit, we can convert this operation to a shift. We
6727 can actually do this more generally, but it doesn't seem worth it. */
6739 return
6743 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6744 non-zero bit in A is C1. */
6752 {
6758 }
6761 }
6762 \f
6763 /* Simplify X, a SET expression. Return the new expression. */
6765 static rtx
6767 {
6770 machine_mode mode
6774 scalar_int_mode int_mode;
6776 /* (set (pc) (return)) gets written as (return). */
6780 /* Now that we know for sure which bits of SRC we are using, see if we can
6781 simplify the expression for the object knowing that we only need the
6782 low-order bits. */
6785 {
6788 }
6790 /* If the source is a COMPARE, look for the use of the comparison result
6791 and try to simplify it unless we already have used undobuf.other_insn. */
6797 {
6806 {
6809 {
6812 }
6813 }
6814 else
6822 {
6826 }
6827 else
6828 {
6833 /* Attempt to simplify CC user. */
6835 {
6839 }
6841 /* Convert X into a no-op move. */
6845 }
6847 /* Simplify our comparison, if possible. */
6850 #ifdef SELECT_CC_MODE
6851 /* If this machine has CC modes other than CCmode, check to see if we
6852 need to use a different CC mode here. */
6861 else
6864 /* If the mode changed, we have to change SET_DEST, the mode in the
6865 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6866 a hard register, just build new versions with the proper mode. If it
6867 is a pseudo, we lose unless it is only time we set the pseudo, in
6868 which case we can safely change its mode. */
6870 {
6872 {
6874 rtx new_dest;
6878 else
6879 {
6882 }
6889 }
6890 }
6893 /* If the code changed, we have to build a new comparison in
6894 undobuf.other_insn. */
6896 {
6905 /* If the only change we made was to change an EQ into an NE or
6906 vice versa, OP0 has only one bit that might be nonzero, and OP1
6907 is zero, check if changing the user of the condition code will
6908 produce a valid insn. If it won't, we can keep the original code
6909 in that insn by surrounding our operation with an XOR. */
6916 {
6921 {
6928 }
6929 }
6930 }
6935 /* Don't generate a compare of a CC with 0, just use that CC. */
6937 {
6940 }
6941 /* Otherwise, if we didn't previously have the same COMPARE we
6942 want, create it from scratch. */
6945 {
6948 }
6949 }
6950 else
6951 {
6952 /* Get SET_SRC in a form where we have placed back any
6953 compound expressions. Then do the checks below. */
6956 }
6958 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6959 and X being a REG or (subreg (reg)), we may be able to convert this to
6960 (set (subreg:m2 x) (op)).
6962 We can always do this if M1 is narrower than M2 because that means that
6963 we only care about the low bits of the result.
6965 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6966 perform a narrower operation than requested since the high-order bits will
6967 be undefined. On machine where it is defined, this transformation is safe
6968 as long as M1 and M2 have the same number of words. */
6972 && (known_equal_after_align_up
6975 UNITS_PER_WORD))
6984 {
6987 dest));
6991 }
6993 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6994 would require a paradoxical subreg. Replace the subreg with a
6995 zero_extend to avoid the reload that would otherwise be required.
6996 Don't do this unless we have a scalar integer mode, otherwise the
6997 transformation is incorrect. */
7004 {
7009 }
7011 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7012 are comparing an item known to be 0 or -1 against 0, use a logical
7013 operation instead. Check for one of the arms being an IOR of the other
7014 arm with some value. We compute three terms to be IOR'ed together. In
7015 practice, at most two will be nonzero. Then we do the IOR's. */
7023 && (!HAVE_conditional_move
7028 {
7053 int_mode),
7054 false_rtx);
7060 term3));
7063 }
7065 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7066 whole thing fail. */
7071 else
7072 /* Convert this into a field assignment operation, if possible. */
7074 }
7075 \f
7076 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7077 result. */
7079 static rtx
7081 {
7084 scalar_int_mode mode;
7087 {
7089 /* We can call simplify_and_const_int only if we don't lose
7090 any (sign) bits when converting INTVAL (op1) to
7091 "unsigned HOST_WIDE_INT". */
7096 {
7103 }
7105 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7106 apply the distributive law and then the inverse distributive
7107 law to see if things simplify. */
7109 {
7113 }
7115 {
7119 }
7123 /* If we have (ior (and A B) C), apply the distributive law and then
7124 the inverse distributive law to see if things simplify. */
7127 {
7131 }
7134 {
7138 }
7143 }
7146 }
7147 \f
7148 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7149 operations" because they can be replaced with two more basic operations.
7150 ZERO_EXTEND is also considered "compound" because it can be replaced with
7151 an AND operation, which is simpler, though only one operation.
7153 The function expand_compound_operation is called with an rtx expression
7154 and will convert it to the appropriate shifts and AND operations,
7155 simplifying at each stage.
7157 The function make_compound_operation is called to convert an expression
7158 consisting of shifts and ANDs into the equivalent compound expression.
7159 It is the inverse of this function, loosely speaking. */
7161 static rtx
7163 {
7167 rtx tem;
7168 scalar_int_mode inner_mode;
7171 {
7174 /* FALLTHRU */
7176 /* We can't necessarily use a const_int for a multiword mode;
7177 it depends on implicitly extending the value.
7178 Since we don't know the right way to extend it,
7179 we can't tell whether the implicit way is right.
7181 Even for a mode that is no wider than a const_int,
7182 we can't win, because we need to sign extend one of its bits through
7183 the rest of it, and we don't know which bit. */
7187 /* Reject modes that aren't scalar integers because turning vector
7188 or complex modes into shifts causes problems. */
7192 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7193 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7194 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7195 reloaded. If not for that, MEM's would very rarely be safe.
7197 Reject modes bigger than a word, because we might not be able
7198 to reference a two-register group starting with an arbitrary register
7199 (and currently gen_lowpart might crash for a SUBREG). */
7205 /* If the inner object has VOIDmode (the only way this can happen
7206 is if it is an ASM_OPERANDS), we can't do anything since we don't
7207 know how much masking to do. */
7216 /* fall through */
7219 /* If the operand is a CLOBBER, just return it. */
7227 /* Reject modes that aren't scalar integers because turning vector
7228 or complex modes into shifts causes problems. */
7235 /* This should stay within the object being extracted, fail otherwise. */
7246 }
7248 /* We've rejected non-scalar operations by now. */
7251 /* Convert sign extension to zero extension, if we know that the high
7252 bit is not set, as this is easier to optimize. It will be converted
7253 back to cheaper alternative in make_extraction. */
7259 {
7263 /* Make sure this is a profitable operation. */
7270 else
7272 }
7274 /* We can optimize some special cases of ZERO_EXTEND. */
7276 {
7277 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7278 know that the last value didn't have any inappropriate bits
7279 set. */
7287 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7296 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7297 is a comparison and STORE_FLAG_VALUE permits. This is like
7298 the first case, but it works even when MODE is larger
7299 than HOST_WIDE_INT. */
7307 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7316 }
7318 /* If we reach here, we want to return a pair of shifts. The inner
7319 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7320 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7321 logical depending on the value of UNSIGNEDP.
7323 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7324 converted into an AND of a shift.
7326 We must check for the case where the left shift would have a negative
7327 count. This can happen in a case like (x >> 31) & 255 on machines
7328 that can't shift by a constant. On those machines, we would first
7329 combine the shift with the AND to produce a variable-position
7330 extraction. Then the constant of 31 would be substituted in
7331 to produce such a position. */
7335 {
7343 }
7345 {
7353 }
7354 else
7355 /* Any other cases we can't handle. */
7358 /* If we couldn't do this for some reason, return the original
7359 expression. */
7364 }
7365 \f
7366 /* X is a SET which contains an assignment of one object into
7367 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7368 or certain SUBREGS). If possible, convert it into a series of
7369 logical operations.
7371 We half-heartedly support variable positions, but do not at all
7372 support variable lengths. */
7374 static const_rtx
7376 {
7377 rtx inner;
7381 scalar_int_mode compute_mode;
7383 /* Loop until we find something we can't simplify. */
7385 {
7388 {
7394 MAX_MODE_INT);
7395 }
7398 {
7406 /* A constant position should stay within the width of INNER. */
7411 {
7417 /* If position is ADJUST - X, new position is X. */
7419 else
7423 pos);
7424 }
7425 }
7427 /* If the destination is a subreg that overwrites the whole of the inner
7428 register, we can move the subreg to the source. */
7430 /* We need SUBREGs to compute nonzero_bits properly. */
7431 && nonzero_sign_valid
7433 {
7435 gen_lowpart
7439 }
7440 else
7446 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7448 {
7449 /* Don't do anything for vector or complex integral types. */
7453 /* Try to find an integral mode to pun with. */
7459 }
7461 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7465 /* Don't try to compute in too wide unsupported modes. */
7469 /* Now compute the equivalent expression. Make a copy of INNER
7470 for the SET_DEST in case it is a MEM into which we will substitute;
7471 we don't want shared RTL in that case. */
7473 compute_mode);
7477 compute_mode,
7479 compute_mode),
7480 inner);
7485 mask),
7486 pos);
7491 }
7494 }
7495 \f
7496 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7497 it is an RTX that represents the (variable) starting position; otherwise,
7498 POS is the (constant) starting bit position. Both are counted from the LSB.
7500 UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7502 IN_DEST is true if this is a reference in the destination of a SET.
7503 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7504 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7505 be used.
7507 IN_COMPARE is true if we are in a COMPARE. This means that a
7508 ZERO_EXTRACT should be built even for bits starting at bit 0.
7510 MODE is the desired mode of the result (if IN_DEST == 0).
7512 The result is an RTX for the extraction or NULL_RTX if the target
7513 can't handle it. */
7515 static rtx
7519 {
7520 /* This mode describes the size of the storage area
7521 to fetch the overall value from. Within that, we
7522 ignore the POS lowest bits, etc. */
7524 machine_mode inner_mode;
7525 scalar_int_mode wanted_inner_mode;
7531 HOST_WIDE_INT orig_pos;
7539 /* If trying or potentionally trying to extract
7540 bits outside of is_mode, don't look through
7541 non-paradoxical SUBREGs. See PR82192. */
7544 {
7545 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7546 consider just the QI as the memory to extract from.
7547 The subreg adds or removes high bits; its mode is
7548 irrelevant to the meaning of this extraction,
7549 since POS and LEN count from the lsb. */
7553 }
7558 {
7559 /* We're extracting the least significant bits of an rtx
7560 (ashift X (const_int C)), where LEN > C. Extract the
7561 least significant (LEN - C) bits of X, giving an rtx
7562 whose mode is MODE, then shift it left C times. */
7568 }
7572 {
7573 /* We're extracting the least significant bits of an rtx
7574 (mult X (const_int 2^C)), where LEN > C. Extract the
7575 least significant (LEN - C) bits of X, giving an rtx
7576 whose mode is MODE, then multiply it by 2^C. */
7579 {
7585 }
7586 }
7588 /* If trying or potentionally trying to extract
7589 bits outside of is_mode, don't look through
7590 TRUNCATE. See PR82192. */
7597 /* See if this can be done without an extraction. We never can if the
7598 width of the field is not the same as that of some integer mode. For
7599 registers, we can only avoid the extraction if the position is at the
7600 low-order bit and this is either not in the destination or we have the
7601 appropriate STRICT_LOW_PART operation available.
7603 For MEM, we can avoid an extract if the field starts on an appropriate
7604 boundary and we can change the mode of the memory reference. */
7606 scalar_int_mode tmode;
7615 && (! in_dest
7619 && (pos
7622 /* We can't do this if we are widening INNER_MODE (it
7623 may not be aligned, for one thing). */
7630 {
7631 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7632 field. If the original and current mode are the same, we need not
7633 adjust the offset. Otherwise, we do if bytes big endian.
7635 If INNER is not a MEM, get a piece consisting of just the field
7636 of interest (in this case POS % BITS_PER_WORD must be 0). */
7639 {
7640 poly_int64 offset;
7642 /* POS counts from lsb, but make OFFSET count in memory order. */
7646 else
7650 }
7652 {
7654 {
7655 /* We can't call gen_lowpart in a DEST since we
7656 always want a SUBREG (see below) and it would sometimes
7657 return a new hard register. */
7659 {
7660 poly_uint64 offset
7663 /* Avoid creating invalid subregs, for example when
7664 simplifying (x>>32)&255. */
7669 }
7670 else
7672 }
7673 else
7675 }
7676 else
7678 len >= HOST_BITS_PER_WIDE_INT
7679 ? HOST_WIDE_INT_M1U
7682 /* If this extraction is going into the destination of a SET,
7683 make a STRICT_LOW_PART unless we made a MEM. */
7698 /* If we know that no extraneous bits are set, and that the high
7699 bit is not set, convert the extraction to the cheaper of
7700 sign and zero extension, that are equivalent in these cases. */
7706 {
7710 /* Prefer ZERO_EXTENSION, since it gives more information to
7711 backends. */
7716 }
7718 /* Otherwise, sign- or zero-extend unless we already are in the
7719 proper mode. */
7723 }
7725 /* Unless this is a COMPARE or we have a funny memory reference,
7726 don't do anything with zero-extending field extracts starting at
7727 the low-order bit since they are simple AND operations. */
7732 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7733 if the position is not a constant and the length is not 1. In all
7734 other cases, we would only be going outside our object in cases when
7735 an original shift would have been undefined. */
7744 /* If INNER is not from memory, we want it to have the mode of a register
7745 extraction pattern's structure operand, or word_mode if there is no
7746 such pattern. The same applies to extraction_mode and pos_mode
7747 and their respective operands.
7749 For memory, assume that the desired extraction_mode and pos_mode
7750 are the same as for a register operation, since at present we don't
7751 have named patterns for aligned memory structures. */
7756 {
7760 }
7762 /* Never narrow an object, since that might not be safe. */
7768 /* Punt if len is too large for extraction_mode. */
7774 else
7775 {
7776 /* Be careful not to go beyond the extracted object and maintain the
7777 natural alignment of the memory. */
7782 }
7787 {
7788 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7789 BITS_BIG_ENDIAN style. If position is constant, compute new
7790 position. Otherwise, build subtraction.
7791 Note that POS is relative to the mode of the original argument.
7792 If it's a MEM we need to recompute POS relative to that.
7793 However, if we're extracting from (or inserting into) a register,
7794 we want to recompute POS relative to wanted_inner_mode. */
7803 else
7804 pos_rtx
7807 pos_rtx);
7808 /* POS may be less than 0 now, but we check for that below.
7809 Note that it can only be less than 0 if !MEM_P (inner). */
7810 }
7812 /* If INNER has a wider mode, and this is a constant extraction, try to
7813 make it smaller and adjust the byte to point to the byte containing
7814 the value. */
7817 && ! pos_rtx
7822 {
7825 /* The computations below will be correct if the machine is big
7826 endian in both bits and bytes or little endian in bits and bytes.
7827 If it is mixed, we must adjust. */
7829 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7830 adjust OFFSET to compensate. */
7835 /* We can now move to the desired byte. */
7846 }
7848 /* If INNER is not memory, get it into the proper mode. If we are changing
7849 its mode, POS must be a constant and smaller than the size of the new
7850 mode. */
7852 {
7853 /* On the LHS, don't create paradoxical subregs implicitely truncating
7854 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7857 wanted_inner_mode))
7869 pos_rtx
7871 ? HOST_WIDE_INT_M1U
7874 }
7876 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7877 have to zero extend. Otherwise, we can just use a SUBREG.
7879 We dealt with constant rtxes earlier, so pos_rtx cannot
7880 have VOIDmode at this point. */
7884 {
7888 /* If we know that no extraneous bits are set, and that the high
7889 bit is not set, convert extraction to cheaper one - either
7890 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7891 cases. */
7899 {
7903 /* Prefer ZERO_EXTENSION, since it gives more information to
7904 backends. */
7908 }
7910 }
7912 /* Make POS_RTX unless we already have it and it is correct. If we don't
7913 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7914 be a CONST_INT. */
7921 /* Make the required operation. See if we can use existing rtx. */
7928 }
7929 \f
7930 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7931 can be commuted with any other operations in X. Return X without
7932 that shift if so. */
7934 static rtx
7936 {
7938 rtx tem;
7941 {
7943 /* This is the shift itself. If it is wide enough, we will return
7944 either the value being shifted if the shift count is equal to
7945 COUNT or a shift for the difference. */
7959 /* If we can safely shift this constant and we find the inner shift,
7960 make a new operation. */
7965 {
7969 }
7974 }
7977 }
7978 \f
7979 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7980 level of the expression and MODE is its mode. IN_CODE is as for
7981 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7982 that should be used when recursing on operands of *X_PTR.
7984 There are two possible actions:
7986 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7987 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7989 - Return a new rtx, which the caller returns directly. */
7991 static rtx
7995 {
8003 rtx tem;
8004 scalar_int_mode inner_mode;
8008 {
8011 }
8013 /* Process depending on the code of this operation. If NEW is set
8014 nonzero, it will be returned. */
8017 {
8019 /* Convert shifts by constants into multiplications if inside
8020 an address. */
8024 {
8030 {
8033 }
8036 }
8045 {
8049 }
8052 {
8056 mode));
8058 }
8059 else
8060 {
8063 }
8073 {
8077 }
8080 {
8084 mode));
8086 }
8087 else
8088 {
8092 }
8095 /* If the second operand is not a constant, we can't do anything
8096 with it. */
8100 /* If the constant is a power of two minus one and the first operand
8101 is a logical right shift, make an extraction. */
8104 {
8108 }
8110 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8117 {
8124 /* If we narrowed the mode when dropping the subreg, then we lose. */
8128 /* If that didn't give anything, see if the AND simplifies on
8129 its own. */
8131 {
8135 }
8136 }
8137 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8143 {
8144 /* Apply the distributive law, and then try to make extractions. */
8151 }
8153 /* If we are have (and (rotate X C) M) and C is larger than the number
8154 of bits in M, this is an extraction. */
8160 {
8167 }
8169 /* On machines without logical shifts, if the operand of the AND is
8170 a logical shift and our mask turns off all the propagated sign
8171 bits, we can replace the logical shift with an arithmetic shift. */
8179 {
8189 next_code),
8191 }
8193 /* If the constant is one less than a power of two, this might be
8194 representable by an extraction even if no shift is present.
8195 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8196 we are in a COMPARE. */
8200 next_code),
8204 /* If we are in a comparison and this is an AND with a power of two,
8205 convert this into the appropriate bit extract. */
8211 next_code),
8214 /* If the one operand is a paradoxical subreg of a register or memory and
8215 the constant (limited to the smaller mode) has only zero bits where
8216 the sub expression has known zero bits, this can be expressed as
8217 a zero_extend. */
8219 {
8220 rtx sub;
8228 {
8232 /* original AND constant with all the known zero bits set */
8235 {
8239 }
8240 }
8241 }
8246 /* If the sign bit is known to be zero, replace this with an
8247 arithmetic shift. */
8252 {
8255 next_code),
8258 }
8260 /* fall through */
8266 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8267 this is a SIGN_EXTRACT. */
8274 {
8282 }
8284 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8285 If so, try to merge the shifts into a SIGN_EXTEND. We could
8286 also do this for some cases of SIGN_EXTRACT, but it doesn't
8287 seem worth the effort; the case checked for occurs on Alpha. */
8298 next_code),
8305 /* Call ourselves recursively on the inner expression. If we are
8306 narrowing the object and it has a different RTL code from
8307 what it originally did, do this SUBREG as a force_to_mode. */
8308 {
8312 /* If the SUBREG is masking of a logical right shift,
8313 make an extraction. */
8320 {
8329 }
8331 /* If in_code is COMPARE, it isn't always safe to pass it through
8332 to the recursive make_compound_operation call. */
8336 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8337 is (const_int 0), rather than
8338 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8339 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8340 for non-equality comparisons against 0 is not equivalent
8341 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8351 simplified
8359 {
8360 rtx newer
8363 /* If we have something other than a SUBREG, we might have
8364 done an expansion, so rerun ourselves. */
8368 /* force_to_mode can expand compounds. If it just re-expanded
8369 the compound, use gen_lowpart to convert to the desired
8370 mode. */
8372 /* Likewise if it re-expanded the compound only partially.
8373 This happens for SUBREG of ZERO_EXTRACT if they extract
8374 the same number of bits. */
8383 }
8387 }
8392 }
8398 }
8400 /* Look at the expression rooted at X. Look for expressions
8401 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8402 Form these expressions.
8404 Return the new rtx, usually just X.
8406 Also, for machines like the VAX that don't have logical shift insns,
8407 try to convert logical to arithmetic shift operations in cases where
8408 they are equivalent. This undoes the canonicalizations to logical
8409 shifts done elsewhere.
8411 We try, as much as possible, to re-use rtl expressions to save memory.
8413 IN_CODE says what kind of expression we are processing. Normally, it is
8414 SET. In a memory address it is MEM. When processing the arguments of
8415 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8416 precisely it is an equality comparison against zero. */
8418 rtx
8420 {
8427 /* Select the code to be used in recursive calls. Once we are inside an
8428 address, we stay there. If we have a comparison, set to COMPARE,
8429 but once inside, go back to our default of SET. */
8436 scalar_int_mode mode;
8438 {
8444 }
8446 /* Now recursively process each operand of this operation. We need to
8447 handle ZERO_EXTEND specially so that we don't lose track of the
8448 inner mode. */
8450 {
8458 }
8463 {
8466 }
8469 {
8472 }
8476 }
8477 \f
8478 /* Given M see if it is a value that would select a field of bits
8479 within an item, but not the entire word. Return -1 if not.
8480 Otherwise, return the starting position of the field, where 0 is the
8481 low-order bit.
8483 *PLEN is set to the length of the field. */
8485 static int
8487 {
8488 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8493 /* Now shift off the low-order zero bits and see if we have a
8494 power of two minus 1. */
8502 }
8503 \f
8504 /* If X refers to a register that equals REG in value, replace these
8505 references with REG. */
8506 static rtx
8508 {
8516 {
8549 /* FALLTHRU */
8553 {
8557 else
8559 }
8561 /* fall through */
8568 {
8571 {
8573 {
8576 }
8578 }
8579 }
8581 {
8584 {
8587 {
8589 {
8592 }
8594 }
8595 }
8596 }
8599 }
8602 }
8604 /* Return X converted to MODE. If the value is already truncated to
8605 MODE we can just return a subreg even though in the general case we
8606 would need an explicit truncation. */
8608 static rtx
8610 {
8615 {
8616 /* Bit-cast X into an integer mode. */
8621 }
8624 }
8626 /* See if X can be simplified knowing that we will only refer to it in
8627 MODE and will only refer to those bits that are nonzero in MASK.
8628 If other bits are being computed or if masking operations are done
8629 that select a superset of the bits in MASK, they can sometimes be
8630 ignored.
8632 Return a possibly simplified expression, but always convert X to
8633 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8635 If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8636 are all off in X. This is used when X will be complemented, by either
8637 NOT, NEG, or XOR. */
8639 static rtx
8642 {
8645 machine_mode op_mode;
8648 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8649 code below will do the wrong thing since the mode of such an
8650 expression is VOIDmode.
8652 Also do nothing if X is a CLOBBER; this can happen if X was
8653 the return value from a call to gen_lowpart. */
8657 /* We want to perform the operation in its present mode unless we know
8658 that the operation is valid in MODE, in which case we do the operation
8659 in MODE. */
8664 /* It is not valid to do a right-shift in a narrower mode
8665 than the one it came in with. */
8670 /* Truncate MASK to fit OP_MODE. */
8674 /* Determine what bits of X are guaranteed to be (non)zero. */
8677 /* If none of the bits in X are needed, return a zero. */
8681 /* If X is a CONST_INT, return a new one. Do this here since the
8682 test below will fail. */
8684 {
8687 else
8688 {
8691 }
8692 }
8694 /* If X is narrower than MODE and we want all the bits in X's mode, just
8695 get X in the proper mode. */
8700 /* We can ignore the effect of a SUBREG if it narrows the mode or
8701 if the constant masks to zero all the bits the mode doesn't have. */
8705 || (mask
8713 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8714 integer too. */
8720 }
8722 /* Subroutine of force_to_mode that handles cases in which both X and
8723 the result are scalar integers. MODE is the mode of the result,
8724 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8725 is preferred for simplified versions of X. The other arguments
8726 are as for force_to_mode. */
8728 static rtx
8732 {
8737 poly_int64 const_op0;
8739 /* When we have an arithmetic operation, or a shift whose count we
8740 do not know, we need to assume that all bits up to the highest-order
8741 bit in MASK will be needed. This is how we form such a mask. */
8744 else
8748 {
8750 /* If X is a (clobber (const_int)), return it since we know we are
8751 generating something that won't match. */
8764 /* Similarly for a truncate. */
8768 /* If this is an AND with a constant, convert it into an AND
8769 whose constant is the AND of that constant with MASK. If it
8770 remains an AND of MASK, delete it since it is redundant. */
8773 {
8778 /* If X is still an AND, see if it is an AND with a mask that
8779 is just some low-order bits. If so, and it is MASK, we don't
8780 need it. */
8786 /* If it remains an AND, try making another AND with the bits
8787 in the mode mask that aren't in MASK turned on. If the
8788 constant in the AND is wide enough, this might make a
8789 cheaper constant. */
8794 {
8795 unsigned HOST_WIDE_INT cval
8797 rtx y;
8804 }
8807 }
8812 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8813 low-order bits (as in an alignment operation) and FOO is already
8814 aligned to that boundary, mask C1 to that boundary as well.
8815 This may eliminate that PLUS and, later, the AND. */
8817 {
8821 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8822 number, sign extend it. */
8835 }
8837 /* fall through */
8840 /* Substituting into the operands of a widening MULT is not likely to
8841 create RTL matching a machine insn. */
8851 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8852 most significant bit in MASK since carries from those bits will
8853 affect the bits we are interested in. */
8858 /* If X is (minus C Y) where C's least set bit is larger than any bit
8859 in the mask, then we may replace with (neg Y). */
8862 {
8865 }
8867 /* Similarly, if C contains every bit in the fuller_mask, then we may
8868 replace with (not Y). */
8871 {
8874 }
8881 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8882 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8883 operation which may be a bitfield extraction. Ensure that the
8884 constant we form is not wider than the mode of X. */
8896 {
8899 xmode);
8905 }
8907 binop:
8908 /* For most binary operations, just propagate into the operation and
8909 change the mode if we have an operation of that mode. */
8914 /* If we ended up truncating both operands, truncate the result of the
8915 operation instead. */
8918 {
8921 }
8927 {
8930 }
8934 /* For left shifts, do the same, but just for the first operand.
8935 However, we cannot do anything with shifts where we cannot
8936 guarantee that the counts are smaller than the size of the mode
8937 because such a count will have a different meaning in a
8938 wider mode. */
8948 /* If the shift count is a constant and we can do arithmetic in
8949 the mode of the shift, refine which bits we need. Otherwise, use the
8950 conservative form of the mask. */
8956 else
8964 {
8967 }
8971 /* Here we can only do something if the shift count is a constant,
8972 this shift constant is valid for the host, and we can do arithmetic
8973 in OP_MODE. */
8979 {
8983 /* Select the mask of the bits we need for the shift operand. */
8986 /* We can only change the mode of the shift if we can do arithmetic
8987 in the mode of the shift and INNER_MASK is no wider than the
8988 width of X's mode. */
8995 {
8998 }
8999 }
9001 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9002 shift and AND produces only copies of the sign bit (C2 is one less
9003 than a power of two), we can do this with just a shift. */
9007 /* The shift puts one of the sign bit copies in the least significant
9008 bit. */
9013 /* Number of bits left after the shift must be more than the mask
9014 needs. */
9017 /* Must be more sign bit copies than the mask needs. */
9020 {
9024 }
9028 /* If we are just looking for the sign bit, we don't need this shift at
9029 all, even if it has a variable count. */
9033 /* If this is a shift by a constant, get a mask that contains those bits
9034 that are not copies of the sign bit. We then have two cases: If
9035 MASK only includes those bits, this can be a logical shift, which may
9036 allow simplifications. If MASK is a single-bit field not within
9037 those bits, we are requesting a copy of the sign bit and hence can
9038 shift the sign bit to the appropriate location. */
9042 {
9046 /* If the considered data is wider than HOST_WIDE_INT, we can't
9047 represent a mask for all its bits in a single scalar.
9048 But we only care about the lower bits, so calculate these. */
9051 {
9054 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9055 is the number of bits a full-width mask would have set.
9056 We need only shift if these are fewer than nonzero can
9057 hold. If not, we must keep all bits set in nonzero. */
9062 + HOST_BITS_PER_WIDE_INT
9064 }
9065 else
9066 {
9069 }
9072 {
9077 }
9080 {
9081 x = simplify_shift_const
9087 }
9088 }
9090 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9091 even if the shift count isn't a constant. */
9095 shiftrt:
9097 /* If this is a zero- or sign-extension operation that just affects bits
9098 we don't care about, remove it. Be sure the call above returned
9099 something that is still a shift. */
9114 /* If the shift count is constant and we can do computations
9115 in the mode of X, compute where the bits we care about are.
9116 Otherwise, we can't do anything. Don't change the mode of
9117 the shift or propagate MODE into the shift, though. */
9120 {
9129 }
9133 /* If we just want the low-order bit, the NEG isn't needed since it
9134 won't change the low-order bit. */
9138 /* We need any bits less significant than the most significant bit in
9139 MASK since carries from those bits will affect the bits we are
9140 interested in. */
9145 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9146 same as the XOR case above. Ensure that the constant we form is not
9147 wider than the mode of X. */
9155 {
9162 }
9164 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9165 use the full mask inside the NOT. */
9168 unop:
9171 next_select));
9173 {
9176 }
9180 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9181 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9182 which is equal to STORE_FLAG_VALUE. */
9194 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9195 written in a narrower mode. We play it safe and do not do so. */
9211 }
9213 /* Ensure we return a value of the proper mode. */
9215 }
9216 \f
9217 /* Return nonzero if X is an expression that has one of two values depending on
9218 whether some other value is zero or nonzero. In that case, we return the
9219 value that is being tested, *PTRUE is set to the value if the rtx being
9220 returned has a nonzero value, and *PFALSE is set to the other alternative.
9222 If we return zero, we set *PTRUE and *PFALSE to X. */
9224 static rtx
9226 {
9231 scalar_int_mode int_mode;
9233 /* If we are comparing a value against zero, we are done. */
9236 {
9240 }
9242 /* If this is a unary operation whose operand has one of two values, apply
9243 our opcode to compute those values. */
9246 {
9251 }
9253 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9254 make can't possibly match and would suppress other optimizations. */
9256 ;
9258 /* If this is a binary operation, see if either side has only one of two
9259 values. If either one does or if both do and they are conditional on
9260 the same value, compute the new true and false values. */
9262 {
9270 {
9271 /* Try to enable a simplification by undoing work done by
9272 if_then_else_cond if it converted a REG into something more
9273 complex. */
9275 {
9278 }
9279 else
9280 {
9283 }
9284 }
9288 {
9289 /* If if_then_else_cond returned zero, then true/false are the
9290 same rtl. We must copy one of them to prevent invalid rtl
9291 sharing. */
9298 {
9303 }
9304 else
9305 {
9308 }
9311 }
9313 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9314 operands is zero when the other is nonzero, and vice-versa,
9315 and STORE_FLAG_VALUE is 1 or -1. */
9321 {
9339 {
9346 const_true_rtx);
9348 }
9349 }
9351 /* Similarly for MULT, AND and UMIN, except that for these the result
9352 is always zero. */
9356 {
9370 {
9373 }
9374 }
9375 }
9378 {
9379 /* If we have IF_THEN_ELSE already, extract the condition and
9380 canonicalize it if it is NE or EQ. */
9386 {
9389 }
9390 else
9392 }
9394 /* If X is a SUBREG, we can narrow both the true and false values
9395 if the inner expression, if there is a condition. */
9399 {
9405 {
9409 }
9410 }
9412 /* If X is a constant, this isn't special and will cause confusions
9413 if we treat it as such. Likewise if it is equivalent to a constant. */
9416 ;
9418 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9419 will be least confusing to the rest of the compiler. */
9421 {
9424 }
9426 /* If X is known to be either 0 or -1, those are the true and
9427 false values when testing X. */
9432 {
9435 }
9437 /* Likewise for 0 or a single bit. */
9440 {
9443 }
9445 /* Otherwise fail; show no condition with true and false values the same. */
9448 }
9449 \f
9450 /* Return the value of expression X given the fact that condition COND
9451 is known to be true when applied to REG as its first operand and VAL
9452 as its second. X is known to not be shared and so can be modified in
9453 place.
9455 We only handle the simplest cases, and specifically those cases that
9456 arise with IF_THEN_ELSE expressions. */
9458 static rtx
9460 {
9468 /* If either operand of the condition is a floating point value,
9469 then we have to avoid collapsing an EQ comparison. */
9479 /* If X is (abs REG) and we know something about REG's relationship
9480 with zero, we may be able to simplify this. */
9484 {
9493 }
9495 /* The only other cases we handle are MIN, MAX, and comparisons if the
9496 operands are the same as REG and VAL. */
9499 {
9501 {
9504 }
9507 {
9509 {
9517 else
9519 }
9522 {
9525 /* Do not reverse the condition when it is NE or EQ.
9526 This is because we cannot conclude anything about
9527 the value of 'SMAX (x, y)' when x is not equal to y,
9528 but we can when x equals y. */
9534 {
9545 }
9546 }
9547 }
9548 }
9550 {
9555 {
9556 /* We must simplify subreg here, before we lose track of the
9557 original inner_mode. */
9562 else
9564 }
9567 }
9568 /* We don't have to handle SIGN_EXTEND here, because even in the
9569 case of replacing something with a modeless CONST_INT, a
9570 CONST_INT is already (supposed to be) a valid sign extension for
9571 its narrower mode, which implies it's already properly
9572 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9573 story is different. */
9575 {
9580 {
9581 /* We must simplify the zero_extend here, before we lose
9582 track of the original inner_mode. */
9587 else
9589 }
9592 }
9596 {
9603 }
9606 }
9607 \f
9608 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9609 assignment as a field assignment. */
9611 static bool
9613 {
9615 {
9623 }
9631 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9632 Note that all SUBREGs of MEM are paradoxical; otherwise they
9633 would have been rewritten. */
9646 /* We used to see if get_last_value of X and Y were the same but that's
9647 not correct. In one direction, we'll cause the assignment to have
9648 the wrong destination and in the case, we'll import a register into this
9649 insn that might have already have been dead. So fail if none of the
9650 above cases are true. */
9652 }
9653 \f
9654 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9655 Return that assignment if so.
9657 We only handle the most common cases. */
9659 static rtx
9661 {
9664 rtx assign;
9666 HOST_WIDE_INT c1;
9667 HOST_WIDE_INT pos;
9669 rtx other;
9671 /* All the rules in this function are specific to scalar integers. */
9672 scalar_int_mode mode;
9676 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9677 a clear of a one-bit field. We will have changed it to
9678 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9679 for a SUBREG. */
9685 {
9691 }
9700 {
9707 }
9709 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9710 one-bit field. */
9714 {
9720 }
9722 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9723 SRC is an AND with all bits of that field set, then we can discard
9724 the AND. */
9729 {
9736 else
9739 /* Complete overlap. We can remove the source AND. */
9743 /* Partial overlap. We can reduce the source AND. */
9745 {
9749 }
9750 }
9752 /* The other case we handle is assignments into a constant-position
9753 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9754 a mask that has all one bits except for a group of zero bits and
9755 OTHER is known to have zeros where C1 has ones, this is such an
9756 assignment. Compute the position and length from C1. Shift OTHER
9757 to the appropriate position, force it to the required mode, and
9758 make the extraction. Check for the AND in both operands. */
9760 /* One or more SUBREGs might obscure the constant-position field
9761 assignment. The first one we are likely to encounter is an outer
9762 narrowing SUBREG, which we can just strip for the purposes of
9763 identifying the constant-field assignment. */
9780 /* The second SUBREG that might get in the way is a paradoxical
9781 SUBREG around the first operand of the AND. We want to
9782 pretend the operand is as wide as the destination here. We
9783 do this by adjusting the MEM to wider mode for the sole
9784 purpose of the call to rtx_equal_for_field_assignment_p. Also
9785 note this trick only works for MEMs. */
9797 /* The second SUBREG that might get in the way is a paradoxical
9798 SUBREG around the first operand of the AND. We want to
9799 pretend the operand is as wide as the destination here. We
9800 do this by adjusting the MEM to wider mode for the sole
9801 purpose of the call to rtx_equal_for_field_assignment_p. Also
9802 note this trick only works for MEMs. */
9810 else
9825 /* The mode to use for the source is the mode of the assignment, or of
9826 what is inside a possible STRICT_LOW_PART. */
9830 /* Shift OTHER right POS places and make it the source, restricting it
9831 to the proper length and mode. */
9835 dest);
9837 len >= HOST_BITS_PER_WIDE_INT
9838 ? HOST_WIDE_INT_M1U
9841 /* If SRC is masked by an AND that does not make a difference in
9842 the value being stored, strip it. */
9853 }
9854 \f
9855 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9856 if so. */
9858 static rtx
9860 {
9864 rtx tem;
9866 /* Distributivity is not true for floating point as it can change the
9867 value. So we don't do it unless -funsafe-math-optimizations. */
9872 /* The outer operation can only be one of the following: */
9880 /* If either operand is a primitive we can't do anything, so get out
9881 fast. */
9891 /* See if the inner and outer operations distribute. */
9893 {
9898 /* These all distribute except over PLUS. */
9909 /* This is also a multiply, so it distributes over everything. */
9912 /* This used to handle SUBREG, but this turned out to be counter-
9913 productive, since (subreg (op ...)) usually is not handled by
9914 insn patterns, and this "optimization" therefore transformed
9915 recognizable patterns into unrecognizable ones. Therefore the
9916 SUBREG case was removed from here.
9918 It is possible that distributing SUBREG over arithmetic operations
9919 leads to an intermediate result than can then be optimized further,
9920 e.g. by moving the outer SUBREG to the other side of a SET as done
9921 in simplify_set. This seems to have been the original intent of
9922 handling SUBREGs here.
9924 However, with current GCC this does not appear to actually happen,
9925 at least on major platforms. If some case is found where removing
9926 the SUBREG case here prevents follow-on optimizations, distributing
9927 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9931 }
9933 /* Set LHS and RHS to the inner operands (A and B in the example
9934 above) and set OTHER to the common operand (C in the example).
9935 There is only one way to do this unless the inner operation is
9936 commutative. */
9948 else
9951 /* Form the new inner operation, seeing if it simplifies first. */
9954 /* There is one exception to the general way of distributing:
9955 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9957 {
9960 }
9962 /* We may be able to continuing distributing the result, so call
9963 ourselves recursively on the inner operation before forming the
9964 outer operation, which we return. */
9967 }
9969 /* See if X is of the form (* (+ A B) C), and if so convert to
9970 (+ (* A C) (* B C)) and try to simplify.
9972 Most of the time, this results in no change. However, if some of
9973 the operands are the same or inverses of each other, simplifications
9974 will result.
9976 For example, (and (ior A B) (not B)) can occur as the result of
9977 expanding a bit field assignment. When we apply the distributive
9978 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9979 which then simplifies to (and (A (not B))).
9981 Note that no checks happen on the validity of applying the inverse
9982 distributive law. This is pointless since we can do it in the
9983 few places where this routine is called.
9985 N is the index of the term that is decomposed (the arithmetic operation,
9986 i.e. (+ A B) in the first example above). !N is the index of the term that
9987 is distributed, i.e. of C in the first example above. */
9988 static rtx
9990 {
9991 machine_mode mode;
9995 /* Distributivity is not true for floating point as it can change the
9996 value. So we don't do it unless -funsafe-math-optimizations. */
10013 /* Special case (and (xor B C) (not A)), which is equivalent to
10014 (xor (ior A B) (ior A C)) */
10016 {
10019 }
10022 {
10023 /* Distribute the second term. */
10026 }
10027 else
10028 {
10029 /* Distribute the first term. */
10032 }
10042 }
10043 \f
10044 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10045 in MODE. Return an equivalent form, if different from (and VAROP
10046 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10048 static rtx
10051 {
10054 rtx orig_varop;
10062 /* Simplify VAROP knowing that we will be only looking at some of the
10063 bits in it.
10065 Note by passing in CONSTOP, we guarantee that the bits not set in
10066 CONSTOP are not significant and will never be examined. We must
10067 ensure that is the case by explicitly masking out those bits
10068 before returning. */
10071 /* If VAROP is a CLOBBER, we will fail so return it. */
10075 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10076 to VAROP and return the new constant. */
10080 /* See what bits may be nonzero in VAROP. Unlike the general case of
10081 a call to nonzero_bits, here we don't care about bits outside
10082 MODE unless WORD_REGISTER_OPERATIONS is true. */
10089 /* Turn off all bits in the constant that are known to already be zero.
10090 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10091 which is tested below. */
10095 /* If we don't have any bits left, return zero. */
10099 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10100 a power of two, we can replace this with an ASHIFT. */
10105 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10106 or XOR, then try to apply the distributive law. This may eliminate
10107 operations if either branch can be simplified because of the AND.
10108 It may also make some cases more complex, but those cases probably
10109 won't match a pattern either with or without this. */
10112 {
10114 return
10115 gen_lowpart
10117 apply_distributive_law
10121 constop),
10124 constop))));
10125 }
10127 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10128 the AND and see if one of the operands simplifies to zero. If so, we
10129 may eliminate it. */
10133 {
10142 }
10144 /* Make a SUBREG if necessary. If we can't make it, fail. */
10149 /* If we are only masking insignificant bits, return VAROP. */
10156 /* Otherwise, return an AND. */
10158 }
10161 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10162 in MODE.
10164 Return an equivalent form, if different from X. Otherwise, return X. If
10165 X is zero, we are to always construct the equivalent form. */
10167 static rtx
10170 {
10181 }
10182 \f
10183 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10184 We don't care about bits outside of those defined in MODE.
10185 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10187 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10188 a shift, AND, or zero_extract, we can do better. */
10190 static rtx
10192 scalar_int_mode mode,
10194 {
10195 rtx tem;
10198 /* If X is a register whose nonzero bits value is current, use it.
10199 Otherwise, if X is a register whose value we can find, use that
10200 value. Otherwise, use the previously-computed global nonzero bits
10201 for this register. */
10216 && !REGNO_REG_SET_P
10219 {
10220 /* Note that, even if the precision of last_set_mode is lower than that
10221 of mode, record_value_for_reg invoked nonzero_bits on the register
10222 with nonzero_bits_mode (because last_set_mode is necessarily integral
10223 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10224 are all valid, hence in mode too since nonzero_bits_mode is defined
10225 to the largest HWI_COMPUTABLE_MODE_P mode. */
10228 }
10232 {
10237 }
10240 {
10244 /* We don't know anything about the upper bits. */
10248 }
10251 }
10253 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10254 end of X that are known to be equal to the sign bit. X will be used
10255 in mode MODE; the returned value will always be between 1 and the
10256 number of bits in MODE. */
10258 static rtx
10260 scalar_int_mode mode,
10262 {
10263 rtx tem;
10276 && !REGNO_REG_SET_P
10279 {
10282 }
10293 }
10294 \f
10295 /* Return the number of "extended" bits there are in X, when interpreted
10296 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10297 unsigned quantities, this is the number of high-order zero bits.
10298 For signed quantities, this is the number of copies of the sign bit
10299 minus 1. In both case, this function returns the number of "spare"
10300 bits. For example, if two quantities for which this function returns
10301 at least 1 are added, the addition is known not to overflow.
10303 This function will always return 0 unless called during combine, which
10304 implies that it must be called from a define_split. */
10306 unsigned int
10308 {
10312 scalar_int_mode int_mode;
10320 }
10322 /* This function is called from `simplify_shift_const' to merge two
10323 outer operations. Specifically, we have already found that we need
10324 to perform operation *POP0 with constant *PCONST0 at the outermost
10325 position. We would now like to also perform OP1 with constant CONST1
10326 (with *POP0 being done last).
10328 Return true if we can do the operation and update *POP0 and *PCONST0 with
10329 the resulting operation. *PCOMP_P is set to true if we would need to
10330 complement the innermost operand, otherwise it is unchanged.
10332 MODE is the mode in which the operation will be done. No bits outside
10333 the width of this mode matter. It is assumed that the width of this mode
10334 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10336 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10337 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10338 result is simply *PCONST0.
10340 If the resulting operation cannot be expressed as one operation, we
10341 return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10343 static bool
10347 {
10354 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10358 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10359 if OP0 is SET. */
10368 {
10370 {
10388 }
10389 }
10391 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10395 /* If the two constants aren't the same, we can't do anything. The
10396 remaining six cases can all be done. */
10400 else
10402 {
10405 /* (a & b) | b == b */
10408 /* (a ^ b) | b == a | b */
10409 {;}
10414 /* (a & b) ^ b == (~a) & b */
10417 /* (a | b) ^ b == a & ~b */
10423 /* (a | b) & b == b */
10426 /* (a ^ b) & b) == (~a) & b */
10431 }
10433 /* Check for NO-OP cases. */
10446 /* ??? Slightly redundant with the above mask, but not entirely.
10447 Moving this above means we'd have to sign-extend the mode mask
10448 for the final test. */
10453 }
10454 \f
10455 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10456 the shift in. The original shift operation CODE is performed on OP in
10457 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10458 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10459 result of the shift is subject to operation OUTER_CODE with operand
10460 OUTER_CONST. */
10462 static scalar_int_mode
10466 {
10469 /* In general we can't perform in wider mode for right shift and rotate. */
10471 {
10473 /* We can still widen if the bits brought in from the left are identical
10474 to the sign bit of ORIG_MODE. */
10482 /* Similarly here but with zero bits. */
10487 /* We can also widen if the bits brought in will be masked off. This
10488 operation is performed in ORIG_MODE. */
10490 {
10496 }
10497 /* fall through */
10507 }
10508 }
10510 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10511 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10512 if we cannot simplify it. Otherwise, return a simplified value.
10514 The shift is normally computed in the widest mode we find in VAROP, as
10515 long as it isn't a different number of words than RESULT_MODE. Exceptions
10516 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10518 static rtx
10521 {
10526 machine_mode shift_mode;
10528 /* We form (outer_op (code varop count) (outer_const)). */
10534 /* Make sure and truncate the "natural" shift on the way in. We don't
10535 want to do this inside the loop as it makes it more difficult to
10536 combine shifts. */
10540 /* If we were given an invalid count, don't do anything except exactly
10541 what was requested. */
10548 /* Unless one of the branches of the `if' in this loop does a `continue',
10549 we will `break' the loop after the `if'. */
10552 {
10553 /* If we have an operand of (clobber (const_int 0)), fail. */
10557 /* Convert ROTATERT to ROTATE. */
10559 {
10563 }
10567 {
10568 /* We only change the modes of scalar shifts. */
10574 }
10576 scalar_int_mode shift_unit_mode
10579 /* Handle cases where the count is greater than the size of the mode
10580 minus 1. For ASHIFT, use the size minus one as the count (this can
10581 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10582 take the count modulo the size. For other shifts, the result is
10583 zero.
10585 Since these shifts are being produced by the compiler by combining
10586 multiple operations, each of which are defined, we know what the
10587 result is supposed to be. */
10590 {
10595 else
10596 {
10597 /* We can't simply return zero because there may be an
10598 outer op. */
10602 }
10603 }
10605 /* If we discovered we had to complement VAROP, leave. Making a NOT
10606 here would cause an infinite loop. */
10611 {
10612 /* An arithmetic right shift of a quantity known to be -1 or 0
10613 is a no-op. */
10617 {
10620 }
10622 /* If we are doing an arithmetic right shift and discarding all but
10623 the sign bit copies, this is equivalent to doing a shift by the
10624 bitsize minus one. Convert it into that shift because it will
10625 often allow other simplifications. */
10632 /* We simplify the tests below and elsewhere by converting
10633 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10634 `make_compound_operation' will convert it to an ASHIFTRT for
10635 those machines (such as VAX) that don't have an LSHIFTRT. */
10640 shift_unit_mode)))
10652 }
10655 {
10662 {
10665 }
10669 /* The following rules apply only to scalars. */
10674 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10675 minus the width of a smaller mode, we can do this with a
10676 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10683 {
10692 }
10696 /* The following rules apply only to scalars. */
10702 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10703 the same number of words as what we've seen so far. Then store
10704 the widest mode in MODE. */
10711 {
10716 }
10720 /* Some machines use MULT instead of ASHIFT because MULT
10721 is cheaper. But it is still better on those machines to
10722 merge two shifts into one. */
10725 {
10730 }
10734 /* Similar, for when divides are cheaper. */
10737 {
10742 }
10746 /* If we are extracting just the sign bit of an arithmetic
10747 right shift, that shift is not needed. However, the sign
10748 bit of a wider mode may be different from what would be
10749 interpreted as the sign bit in a narrower mode, so, if
10750 the result is narrower, don't discard the shift. */
10755 {
10758 }
10760 /* fall through */
10765 /* The following rules apply only to scalars. */
10772 /* Here we have two nested shifts. The result is usually the
10773 AND of a new shift with a mask. We compute the result below. */
10779 {
10783 rtx mask_rtx;
10785 /* We have one common special case. We can't do any merging if
10786 the inner code is an ASHIFTRT of a smaller mode. However, if
10787 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10788 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10789 we can convert it to
10790 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10791 This simplifies certain SIGN_EXTEND operations. */
10795 {
10796 /* C3 has the low-order C1 bits zero. */
10808 }
10810 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10811 than C1 high-order bits equal to the sign bit, we can convert
10812 this to either an ASHIFT or an ASHIFTRT depending on the
10813 two counts.
10815 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10821 {
10825 {
10828 }
10831 }
10833 /* There are some cases we can't do. If CODE is ASHIFTRT,
10834 we can only do this if FIRST_CODE is also ASHIFTRT.
10836 We can't do the case when CODE is ROTATE and FIRST_CODE is
10837 ASHIFTRT.
10839 If the mode of this shift is not the mode of the outer shift,
10840 we can't do this if either shift is a right shift or ROTATE.
10842 Finally, we can't do any of these if the mode is too wide
10843 unless the codes are the same.
10845 Handle the case where the shift codes are the same
10846 first. */
10849 {
10858 }
10869 /* To compute the mask to apply after the shift, shift the
10870 nonzero bits of the inner shift the same way the
10871 outer shift will. */
10874 int_result_mode);
10876 mask_rtx
10880 /* Give up if we can't compute an outer operation to use. */
10888 /* If the shifts are in the same direction, we add the
10889 counts. Otherwise, we subtract them. */
10893 else
10896 /* If COUNT is positive, the new shift is usually CODE,
10897 except for the two exceptions below, in which case it is
10898 FIRST_CODE. If the count is negative, FIRST_CODE should
10899 always be used */
10909 }
10911 /* If we have (A << B << C) for any shift, we can convert this to
10912 (A << C << B). This wins if A is a constant. Only try this if
10913 B is not a constant. */
10918 {
10919 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10920 sure the result will be masked. See PR70222. */
10928 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10929 up outer sign extension (often left and right shift) is
10930 hardly more efficient than the original. See PR70429.
10931 Similarly punt for rotates with different modes.
10932 See PR97386. */
10940 count_rtx);
10944 }
10948 /* The following rules apply only to scalars. */
10952 /* Make this fit the case below. */
10959 /* The following rules apply only to scalars. */
10965 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10966 with C the size of VAROP - 1 and the shift is logical if
10967 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10968 we have an (le X 0) operation. If we have an arithmetic shift
10969 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10970 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10978 {
10981 const0_rtx);
10987 }
10989 /* If we have (shift (logical)), move the logical to the outside
10990 to allow it to possibly combine with another logical and the
10991 shift to combine with another shift. This also canonicalizes to
10992 what a ZERO_EXTRACT looks like. Also, some machines have
10993 (and (shift)) insns. */
10996 /* We can't do this if we have (ashiftrt (xor)) and the
10997 constant has its sign bit set in shift_unit_mode with
10998 shift_unit_mode wider than result_mode. */
11011 {
11014 }
11016 /* If we can't do that, try to simplify the shift in each arm of the
11017 logical expression, make a new logical expression, and apply
11018 the inverse distributive law. This also can't be done for
11019 (ashiftrt (xor)) where we've widened the shift and the constant
11020 changes the sign bit. */
11026 {
11038 }
11042 /* The following rules apply only to scalars. */
11047 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11048 says that the sign bit can be tested, FOO has mode MODE, C is
11049 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11050 that may be nonzero. */
11060 {
11064 }
11068 /* The following rules apply only to scalars. */
11073 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11074 than the number of bits in the mode is equivalent to A. */
11078 {
11082 }
11084 /* NEG commutes with ASHIFT since it is multiplication. Move the
11085 NEG outside to allow shifts to combine. */
11089 {
11092 }
11096 /* The following rules apply only to scalars. */
11101 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11102 is one less than the number of bits in the mode is
11103 equivalent to (xor A 1). */
11110 {
11114 }
11116 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11117 that might be nonzero in BAR are those being shifted out and those
11118 bits are known zero in FOO, we can replace the PLUS with FOO.
11119 Similarly in the other operand order. This code occurs when
11120 we are computing the size of a variable-size array. */
11127 {
11130 }
11138 {
11141 }
11143 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11154 {
11157 }
11159 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11160 signbit', and attempt to change the PLUS to an XOR and move it to
11161 the outer operation as is done above in the AND/IOR/XOR case
11162 leg for shift(logical). See details in logical handling above
11163 for reasoning in doing so. */
11175 {
11178 }
11183 /* The following rules apply only to scalars. */
11188 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11189 with C the size of VAROP - 1 and the shift is logical if
11190 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11191 we have a (gt X 0) operation. If the shift is arithmetic with
11192 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11193 we have a (neg (gt X 0)) operation. */
11202 {
11205 const0_rtx);
11211 }
11215 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11216 if the truncate does not affect the value. */
11223 {
11227 new_count);
11230 new_count_rtx);
11234 }
11239 }
11242 }
11246 {
11247 /* We only change the modes of scalar shifts. */
11252 }
11254 /* We have now finished analyzing the shift. The result should be
11255 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11256 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11257 to the result of the shift. OUTER_CONST is the relevant constant,
11258 but we must turn off all bits turned off in the shift. */
11266 /* Make a SUBREG if necessary. If we can't make it, fail. */
11271 /* If we have an outer operation and we just made a shift, it is
11272 possible that we could have simplified the shift were it not
11273 for the outer operation. So try to do the simplification
11274 recursively. */
11278 else
11285 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11286 turn off all the bits that the shift would have turned off. */
11288 /* We only change the modes of scalar shifts. */
11292 /* Do the remainder of the processing in RESULT_MODE. */
11295 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11296 operation. */
11301 {
11311 {
11312 /* This means that we have determined that the result is
11313 equivalent to a constant. This should be rare. */
11316 }
11319 else
11322 }
11325 }
11327 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11328 The result of the shift is RESULT_MODE. If we cannot simplify it,
11329 return X or, if it is NULL, synthesize the expression with
11330 simplify_gen_binary. Otherwise, return a simplified value.
11332 The shift is normally computed in the widest mode we find in VAROP, as
11333 long as it isn't a different number of words than RESULT_MODE. Exceptions
11334 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11336 static rtx
11339 {
11350 }
11352 \f
11353 /* A subroutine of recog_for_combine. See there for arguments and
11354 return value. */
11356 static int
11358 {
11360 rtx pat_without_clobbers;
11368 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11369 we use to indicate that something didn't match. If we find such a
11370 thing, force rejection. */
11384 {
11387 else
11390 }
11392 /* If it isn't, there is the possibility that we previously had an insn
11393 that clobbered some register as a side effect, but the combined
11394 insn doesn't need to do that. So try once more without the clobbers
11395 unless this represents an ASM insn. */
11399 {
11404 {
11407 pos++;
11408 }
11418 {
11421 else
11424 }
11425 }
11432 /* Recognize all noop sets, these will be killed by followup pass. */
11436 /* If we had any clobbers to add, make a new pattern than contains
11437 them. Then check to make sure that all of them are dead. */
11439 {
11449 else
11456 {
11461 {
11465 }
11466 }
11468 }
11472 {
11480 /* Allow targets to reject combined insn. */
11482 {
11485 dump_file);
11487 /* Callers expect recog_for_combine to strip
11488 clobbers from the pattern on failure. */
11493 }
11498 }
11504 }
11506 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11507 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11508 Return whether anything was so changed. */
11510 static bool
11512 {
11518 {
11530 {
11540 else
11544 {
11550 }
11551 }
11557 {
11562 {
11568 }
11569 }
11574 {
11578 }
11579 else
11585 {
11588 }
11592 }
11599 scalar_int_mode mode;
11605 {
11619 else
11627 }
11630 }
11632 /* Like recog, but we receive the address of a pointer to a new pattern.
11633 We try to match the rtx that the pointer points to.
11634 If that fails, we may try to modify or replace the pattern,
11635 storing the replacement into the same pointer object.
11637 Modifications include deletion or addition of CLOBBERs. If the
11638 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11639 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11640 (and undo if that fails).
11642 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11643 the CLOBBERs are placed.
11645 The value is the final insn code from the pattern ultimately matched,
11646 or -1. */
11648 static int
11650 {
11660 {
11661 /* For an unrecognized single set of a constant, try placing it in
11662 the constant pool, if this function already uses one. */
11667 {
11673 {
11676 }
11677 }
11678 else
11680 }
11682 {
11685 {
11689 }
11690 }
11693 {
11698 }
11701 }
11702 \f
11703 /* Like gen_lowpart_general but for use by combine. In combine it
11704 is not possible to create any new pseudoregs. However, it is
11705 safe to create invalid memory addresses, because combine will
11706 try to recognize them and all they will do is make the combine
11707 attempt fail.
11709 If for some reason this cannot do its job, an rtx
11710 (clobber (const_int 0)) is returned.
11711 An insn containing that will not be recognized. */
11713 static rtx
11715 {
11717 rtx result;
11722 /* We can only support MODE being wider than a word if X is a
11723 constant integer or has a mode the same size. */
11729 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11730 won't know what to do. So we will strip off the SUBREG here and
11731 process normally. */
11733 {
11736 /* For use in case we fall down into the address adjustments
11737 further below, we need to adjust the known mode and size of
11738 x; imode and isize, since we just adjusted x. */
11743 }
11751 {
11752 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11753 address. */
11758 /* If we want to refer to something bigger than the original memref,
11759 generate a paradoxical subreg instead. That will force a reload
11760 of the original memref X. */
11766 }
11768 /* If X is a comparison operator, rewrite it in a new mode. This
11769 probably won't match, but may allow further simplifications. */
11775 /* If we couldn't simplify X any other way, just enclose it in a
11776 SUBREG. Normally, this SUBREG won't match, but some patterns may
11777 include an explicit SUBREG or we may simplify it further in combine. */
11778 else
11779 {
11780 rtx res;
11783 {
11788 }
11792 }
11794 fail:
11796 }
11797 \f
11798 /* Try to simplify a comparison between OP0 and a constant OP1,
11799 where CODE is the comparison code that will be tested, into a
11800 (CODE OP0 const0_rtx) form.
11802 The result is a possibly different comparison code to use.
11803 *POP0 and *POP1 may be updated. */
11805 static enum rtx_code
11808 {
11809 scalar_int_mode int_mode;
11813 /* Get the constant we are comparing against and turn off all bits
11814 not on in our mode. */
11818 /* If we are comparing against a constant power of two and the value
11819 being compared can only have that single bit nonzero (e.g., it was
11820 `and'ed with that bit), we can replace this with a comparison
11821 with zero. */
11830 {
11833 }
11835 /* Similarly, if we are comparing a value known to be either -1 or
11836 0 with -1, change it to the opposite comparison against zero. */
11842 {
11845 }
11847 /* Do some canonicalizations based on the comparison code. We prefer
11848 comparisons against zero and then prefer equality comparisons.
11849 If we can reduce the size of a constant, we will do that too. */
11851 {
11853 /* < C is equivalent to <= (C - 1) */
11855 {
11858 /* ... fall through to LE case below. */
11860 }
11861 else
11865 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11867 {
11870 }
11872 /* If we are doing a <= 0 comparison on a value known to have
11873 a zero sign bit, we can replace this with == 0. */
11884 /* >= C is equivalent to > (C - 1). */
11886 {
11889 /* ... fall through to GT below. */
11891 }
11892 else
11896 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11898 {
11901 }
11903 /* If we are doing a > 0 comparison on a value known to have
11904 a zero sign bit, we can replace this with != 0. */
11915 /* < C is equivalent to <= (C - 1). */
11917 {
11920 /* ... fall through ... */
11922 }
11923 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11928 {
11932 }
11933 else
11937 /* unsigned <= 0 is equivalent to == 0 */
11940 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11944 == ((HOST_WIDE_INT_1U
11946 {
11949 }
11953 /* >= C is equivalent to > (C - 1). */
11955 {
11958 /* ... fall through ... */
11960 }
11962 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11967 {
11971 }
11972 else
11976 /* unsigned > 0 is equivalent to != 0 */
11979 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11983 == (HOST_WIDE_INT_1U
11985 {
11988 }
11993 }
11995 /* Narrow non-symmetric comparison of memory and constant as e.g.
11996 x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
11997 significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
11998 x0 >= 0x40. */
12004 /* The optimization makes only sense for constants which are big enough
12005 so that we have a chance to chop off something at all. */
12007 /* Ensure that we do not overflow during normalization. */
12012 {
12013 unsigned HOST_WIDE_INT n
12017 /* Normalize code to either LEU or GEU. */
12019 {
12022 }
12024 {
12027 }
12028 else
12031 scalar_int_mode narrow_mode_iter;
12033 {
12040 {
12043 }
12044 }
12047 {
12049 {
12052 HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12057 }
12058 poly_int64 offset = (BYTES_BIG_ENDIAN
12065 }
12066 }
12070 }
12071 \f
12072 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12073 comparison code that will be tested.
12075 The result is a possibly different comparison code to use. *POP0 and
12076 *POP1 may be updated.
12078 It is possible that we might detect that a comparison is either always
12079 true or always false. However, we do not perform general constant
12080 folding in combine, so this knowledge isn't useful. Such tautologies
12081 should have been detected earlier. Hence we ignore all such cases. */
12083 static enum rtx_code
12085 {
12091 opt_scalar_int_mode tmode_iter;
12093 /* Try a few ways of applying the same transformation to both operands. */
12095 {
12096 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12097 so check specially. */
12116 {
12119 }
12121 /* If both operands are the same constant shift, see if we can ignore the
12122 shift. We can if the shift is a rotate or if the bits shifted out of
12123 this shift are known to be zero for both inputs and if the type of
12124 comparison is compatible with the shift. */
12137 {
12150 else
12152 }
12154 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12155 SUBREGs are of the same mode, and, in both cases, the AND would
12156 be redundant if the comparison was done in the narrower mode,
12157 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12158 and the operand's possibly nonzero bits are 0xffffff01; in that case
12159 if we only care about QImode, we don't need the AND). This case
12160 occurs if the output mode of an scc insn is not SImode and
12161 STORE_FLAG_VALUE == 1 (e.g., the 386).
12163 Similarly, check for a case where the AND's are ZERO_EXTEND
12164 operations from some narrower mode even though a SUBREG is not
12165 present. */
12170 {
12186 {
12190 /* The resulting comparison is always unsigned since we masked
12191 off the original sign bit. */
12195 }
12201 {
12207 }
12211 }
12213 /* If both operands are NOT, we can strip off the outer operation
12214 and adjust the comparison code for swapped operands; similarly for
12215 NEG, except that this must be an equality comparison. */
12221 else
12223 }
12225 /* If the first operand is a constant, swap the operands and adjust the
12226 comparison code appropriately, but don't do this if the second operand
12227 is already a constant integer. */
12229 {
12232 }
12234 /* We now enter a loop during which we will try to simplify the comparison.
12235 For the most part, we only are concerned with comparisons with zero,
12236 but some things may really be comparisons with zero but not start
12237 out looking that way. */
12240 {
12242 scalar_int_mode int_mode;
12246 HOST_WIDE_INT const_op;
12248 /* We only want to handle integral modes. This catches VOIDmode,
12249 CCmode, and the floating-point modes. An exception is that we
12250 can handle VOIDmode if OP0 is a COMPARE or a comparison
12251 operation. */
12258 /* Try to simplify the compare to constant, possibly changing the
12259 comparison op, and/or changing op1 to zero. */
12263 /* Compute some predicates to simplify code below. */
12270 /* If this is a sign bit comparison and we can do arithmetic in
12271 MODE, say that we will only be needing the sign bit of OP0. */
12276 HOST_WIDE_INT_1U
12280 {
12281 /* We can't do anything if OP0 is a condition code value, rather
12282 than an actual data value. */
12287 /* Get the two operands being compared. */
12290 else
12293 /* Check for the cases where we simply want the result of the
12294 earlier test or the opposite of that result. */
12298 {
12302 else
12306 {
12311 }
12312 }
12314 }
12320 /* Now try cases based on the opcode of OP0. If none of the cases
12321 does a "continue", we exit this loop immediately after the
12322 switch. */
12327 {
12329 /* If we are extracting a single bit from a variable position in
12330 a constant that has only a single bit set and are comparing it
12331 with zero, we can convert this into an equality comparison
12332 between the position and the location of the single bit. */
12333 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12334 have already reduced the shift count modulo the word size. */
12340 {
12348 /* Result is nonzero iff shift count is equal to I. */
12351 }
12353 /* fall through */
12358 {
12361 }
12365 /* If testing for equality, we can take the NOT of the constant. */
12368 {
12372 }
12374 /* If just looking at the sign bit, reverse the sense of the
12375 comparison. */
12377 {
12381 }
12385 /* If testing for equality, we can take the NEG of the constant. */
12388 {
12392 }
12394 /* The remaining cases only apply to comparisons with zero. */
12398 /* When X is ABS or is known positive,
12399 (neg X) is < 0 if and only if X != 0. */
12407 {
12411 }
12413 /* If we have NEG of something whose two high-order bits are the
12414 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12416 {
12420 }
12424 /* If we are testing equality and our count is a constant, we
12425 can perform the inverse operation on our RHS. */
12429 {
12433 }
12435 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12436 a particular bit. Convert it to an AND of a constant of that
12437 bit. This will be converted into a ZERO_EXTRACT. */
12442 {
12444 (HOST_WIDE_INT_1U
12449 }
12451 /* Fall through. */
12454 /* ABS is ignorable inside an equality comparison with zero. */
12456 {
12459 }
12463 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12464 (compare FOO CONST) if CONST fits in FOO's mode and we
12465 are either testing inequality or have an unsigned
12466 comparison with ZERO_EXTEND or a signed comparison with
12467 SIGN_EXTEND. But don't do it if we don't have a compare
12468 insn of the given mode, since we'd have to revert it
12469 later on, and then we wouldn't know whether to sign- or
12470 zero-extend. */
12472 && ! unsigned_comparison_p
12476 {
12479 }
12483 /* Check for the case where we are comparing A - C1 with C2, that is
12485 (subreg:MODE (plus (A) (-C1))) op (C2)
12487 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12488 comparison in the wider mode. One of the following two conditions
12489 must be true in order for this to be valid:
12491 1. The mode extension results in the same bit pattern being added
12492 on both sides and the comparison is equality or unsigned. As
12493 C2 has been truncated to fit in MODE, the pattern can only be
12494 all 0s or all 1s.
12496 2. The mode extension results in the sign bit being copied on
12497 each side.
12499 The difficulty here is that we have predicates for A but not for
12500 (A - C1) so we need to check that C1 is within proper bounds so
12501 as to perturbate A as little as possible. */
12510 {
12518 /* (A - C1) zero-extends if it is positive and sign-extends
12519 if it is negative, C2 both zero- and sign-extends. */
12523 /* (A - C1) sign-extends if it is positive and 1-extends
12524 if it is negative, C2 both sign- and 1-extends. */
12531 /* (A - C1) always sign-extends, like C2. */
12535 {
12538 }
12539 }
12541 /* If the inner mode is narrower and we are extracting the low part,
12542 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12544 ;
12553 {
12554 /* Remove outer subregs that don't do anything. */
12559 {
12563 }
12565 }
12566 else
12569 /* FALLTHROUGH */
12578 {
12581 }
12585 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12586 this for equality comparisons due to pathological cases involving
12587 overflows. */
12591 {
12595 }
12597 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12600 {
12604 }
12608 /* We used to optimize signed comparisons against zero, but that
12609 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12610 arrive here as equality comparisons, or (GEU, LTU) are
12611 optimized away. No need to special-case them. */
12613 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12614 (eq B (minus A C)), whichever simplifies. We can only do
12615 this for equality comparisons due to pathological cases involving
12616 overflows. */
12620 {
12624 }
12629 {
12633 }
12635 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12636 of bits in X minus 1, is one iff X > 0. */
12641 {
12645 }
12649 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12650 if C is zero or B is a constant. */
12654 {
12658 }
12663 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12664 iff X <= 0. */
12668 {
12672 }
12676 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12677 will be converted to a ZERO_EXTRACT later. */
12681 {
12686 }
12688 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12689 zero and X is a comparison and C1 and C2 describe only bits set
12690 in STORE_FLAG_VALUE, we can compare with X. */
12698 {
12705 {
12708 }
12709 }
12711 /* If we are doing an equality comparison of an AND of a bit equal
12712 to the sign bit, replace this with a LT or GE comparison of
12713 the underlying value. */
12720 {
12724 }
12726 /* If this AND operation is really a ZERO_EXTEND from a narrower
12727 mode, the constant fits within that mode, and this is either an
12728 equality or unsigned comparison, try to do this comparison in
12729 the narrower mode.
12731 Note that in:
12733 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12734 -> (ne:DI (reg:SI 4) (const_int 0))
12736 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12737 known to hold a value of the required mode the
12738 transformation is invalid. */
12746 {
12749 }
12751 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12752 fits in both M1 and M2 and the SUBREG is either paradoxical
12753 or represents the low part, permute the SUBREG and the AND
12754 and try again. */
12757 {
12759 /* Require an integral mode, to avoid creating something like
12760 (AND:SF ...). */
12763 /* It is unsafe to commute the AND into the SUBREG if the
12764 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12765 not defined. As originally written the upper bits
12766 have a defined value due to the AND operation.
12767 However, if we commute the AND inside the SUBREG then
12768 they no longer have defined values and the meaning of
12769 the code has been changed.
12770 Also C1 should not change value in the smaller mode,
12771 see PR67028 (a positive C1 can become negative in the
12772 smaller mode, so that the AND does no longer mask the
12773 upper bits). */
12774 && ((WORD_REGISTER_OPERATIONS
12786 {
12792 }
12793 }
12795 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12799 {
12804 }
12806 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12807 (eq (and (lshiftrt X) 1) 0).
12808 Also handle the case where (not X) is expressed using xor. */
12812 {
12822 == HOST_WIDE_INT_1U
12824 {
12825 op0
12830 }
12831 }
12835 /* If we have (compare (ashift FOO N) (const_int C)) and
12836 the high order N bits of FOO (N+1 if an inequality comparison)
12837 are known to be zero, we can do this by comparing FOO with C
12838 shifted right N bits so long as the low-order N bits of C are
12839 zero. */
12851 {
12852 /* We must perform a logical shift, not an arithmetic one,
12853 as we want the top N bits of C to be zero. */
12860 }
12862 /* If we are doing a sign bit comparison, it means we are testing
12863 a particular bit. Convert it to the appropriate AND. */
12866 {
12868 (HOST_WIDE_INT_1U
12873 }
12875 /* If this an equality comparison with zero and we are shifting
12876 the low bit to the sign bit, we can convert this to an AND of the
12877 low-order bit. */
12881 {
12884 }
12888 /* If this is an equality comparison with zero, we can do this
12889 as a logical shift, which might be much simpler. */
12892 {
12897 }
12899 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12900 do the comparison in a narrower mode. */
12910 {
12913 }
12915 /* Likewise if OP0 is a PLUS of a sign extension with a
12916 constant, which is usually represented with the PLUS
12917 between the shifts. */
12929 {
12937 new_const);
12939 }
12941 /* FALLTHROUGH */
12943 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12944 the low order N bits of FOO are known to be zero, we can do this
12945 by comparing FOO with C shifted left N bits so long as no
12946 overflow occurs. Even if the low order N bits of FOO aren't known
12947 to be zero, if the comparison is >= or < we can use the same
12948 optimization and for > or <= by setting all the low
12949 order N bits in the comparison constant. */
12960 {
12961 unsigned HOST_WIDE_INT low_bits
12963 & ((HOST_WIDE_INT_1U
12966 {
12967 /* If the shift was logical, then we must make the condition
12968 unsigned. */
12977 const_op
12982 }
12983 }
12985 /* If we are using this shift to extract just the sign bit, we
12986 can replace this with an LT or GE comparison. */
12991 {
12995 }
13000 }
13003 }
13005 /* Now make any compound operations involved in this comparison. Then,
13006 check for an outmost SUBREG on OP0 that is not doing anything or is
13007 paradoxical. The latter transformation must only be performed when
13008 it is known that the "extra" bits will be the same in op0 and op1 or
13009 that they don't matter. There are three cases to consider:
13011 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13012 care bits and we can assume they have any convenient value. So
13013 making the transformation is safe.
13015 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13016 In this case the upper bits of op0 are undefined. We should not make
13017 the simplification in that case as we do not know the contents of
13018 those bits.
13020 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13021 In that case we know those bits are zeros or ones. We must also be
13022 sure that they are the same as the upper bits of op1.
13024 We can never remove a SUBREG for a non-equality comparison because
13025 the sign bit is in a different place in the underlying object. */
13038 {
13040 {
13041 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13042 implemented. */
13044 {
13047 }
13048 }
13052 {
13057 }
13058 }
13060 /* We now do the opposite procedure: Some machines don't have compare
13061 insns in all modes. If OP0's mode is an integer mode smaller than a
13062 word and we can't do a compare in that mode, see if there is a larger
13063 mode for which we can do the compare. There are a number of cases in
13064 which we can use the wider mode. */
13070 {
13075 {
13078 /* If this is a test for negative, we can make an explicit
13079 test of the sign bit. Test this first so we can use
13080 a paradoxical subreg to extend OP0. */
13084 {
13085 unsigned HOST_WIDE_INT sign
13092 }
13094 /* If the only nonzero bits in OP0 and OP1 are those in the
13095 narrower mode and this is an equality or unsigned comparison,
13096 we can use the wider mode. Similarly for sign-extended
13097 values, in which case it is true for all comparisons. */
13114 {
13115 /* If OP0 is an AND and we don't have an AND in MODE either,
13116 make a new AND in the proper mode. */
13124 else
13125 {
13127 {
13132 }
13133 else
13134 {
13139 }
13141 }
13142 }
13143 }
13144 }
13146 /* We may have changed the comparison operands. Re-canonicalize. */
13148 {
13151 }
13153 /* If this machine only supports a subset of valid comparisons, see if we
13154 can convert an unsupported one into a supported one. */
13161 }
13162 \f
13163 /* Utility function for record_value_for_reg. Count number of
13164 rtxs in X. */
13165 static int
13167 {
13174 {
13194 }
13205 }
13206 \f
13207 /* Utility function for following routine. Called when X is part of a value
13208 being stored into last_set_value. Sets last_set_table_tick
13209 for each register mentioned. Similar to mention_regs in cse.cc */
13211 static void
13213 {
13219 {
13225 {
13228 }
13231 }
13235 {
13236 /* Check for identical subexpressions. If x contains
13237 identical subexpression we only have to traverse one of
13238 them. */
13240 {
13241 /* Note that at this point x1 has already been
13242 processed. */
13246 /* If x0 and x1 are identical then there is no need to
13247 process x0. */
13251 /* If x0 is identical to a subexpression of x1 then while
13252 processing x1, x0 has already been processed. Thus we
13253 are done with x. */
13258 /* If x1 is identical to a subexpression of x0 then we
13259 still have to process the rest of x0. */
13262 {
13265 }
13266 }
13269 }
13273 }
13275 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13276 are saying that the register is clobbered and we no longer know its
13277 value. If INSN is zero, don't update reg_stat[].last_set; this is
13278 only permitted with VALUE also zero and is used to invalidate the
13279 register. */
13281 static void
13283 {
13289 /* If VALUE contains REG and we have a previous value for REG, substitute
13290 the previous value. */
13292 {
13293 rtx tem;
13295 /* Set things up so get_last_value is allowed to see anything set up to
13296 our insn. */
13300 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13301 it isn't going to be useful and will take a lot of time to process,
13302 so just use the CLOBBER. */
13305 {
13311 {
13312 /* If there are two or more occurrences of REG in VALUE,
13313 prevent the value from growing too much. */
13316 }
13319 }
13320 }
13322 /* For each register modified, show we don't know its value, that
13323 we don't know about its bitwise content, that its value has been
13324 updated, and that we don't know the location of the death of the
13325 register. */
13327 {
13339 }
13341 /* Mark registers that are being referenced in this value. */
13345 /* Now update the status of each register being set.
13346 If someone is using this register in this block, set this register
13347 to invalid since we will get confused between the two lives in this
13348 basic block. This makes using this register always invalid. In cse, we
13349 scan the table to invalidate all entries using this register, but this
13350 is too much work for us. */
13353 {
13359 else
13361 }
13363 /* The value being assigned might refer to X (like in "x++;"). In that
13364 case, we must replace it with (clobber (const_int 0)) to prevent
13365 infinite loops. */
13368 {
13372 }
13374 /* For the main register being modified, update the value, the mode, the
13375 nonzero bits, and the number of sign bit copies. */
13380 {
13388 rsp->last_set_sign_bit_copies
13390 }
13391 }
13393 /* Called via note_stores from record_dead_and_set_regs to handle one
13394 SET or CLOBBER in an insn. DATA is the instruction in which the
13395 set is occurring. */
13397 static void
13399 {
13406 {
13410 }
13413 {
13414 /* If we are setting the whole register, we know its value. */
13417 /* We can handle a SUBREG if it's the low part, but we must be
13418 careful with paradoxical SUBREGs on RISC architectures because
13419 we cannot strip e.g. an extension around a load and record the
13420 naked load since the RTL middle-end considers that the upper bits
13421 are defined according to LOAD_EXTEND_OP. */
13426 BITS_PER_WORD)
13428 {
13437 else
13438 {
13448 }
13449 }
13450 /* Otherwise show that we don't know the value. */
13451 else
13453 }
13455 /* Ignore pushes, they clobber nothing. */
13458 }
13460 /* Update the records of when each REG was most recently set or killed
13461 for the things done by INSN. This is the last thing done in processing
13462 INSN in the combiner loop.
13464 We update reg_stat[], in particular fields last_set, last_set_value,
13465 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13466 last_death, and also the similar information mem_last_set (which insn
13467 most recently modified memory) and last_call_luid (which insn was the
13468 most recent subroutine call). */
13470 static void
13472 {
13473 rtx link;
13477 {
13480 {
13485 {
13490 }
13491 }
13494 }
13497 {
13498 HARD_REG_SET callee_clobbers
13500 hard_reg_set_iterator hrsi;
13502 {
13505 /* ??? We could try to preserve some information from the last
13506 set of register I if the call doesn't actually clobber
13507 (reg:last_set_mode I), which might be true for ABIs with
13508 partial clobbers. However, it would be difficult to
13509 update last_set_nonzero_bits and last_sign_bit_copies
13510 to account for the part of I that actually was clobbered.
13511 It wouldn't help much anyway, since we rarely see this
13512 situation before RA. */
13522 }
13526 /* We can't combine into a call pattern. Remember, though, that
13527 the return value register is set at this LUID. We could
13528 still replace a register with the return value from the
13529 wrong subroutine call! */
13531 }
13532 else
13534 }
13536 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13537 register present in the SUBREG, so for each such SUBREG go back and
13538 adjust nonzero and sign bit information of the registers that are
13539 known to have some zero/sign bits set.
13541 This is needed because when combine blows the SUBREGs away, the
13542 information on zero/sign bits is lost and further combines can be
13543 missed because of that. */
13545 static void
13547 {
13549 rtx set;
13557 {
13566 {
13569 }
13573 {
13576 }
13579 {
13582 }
13583 else
13585 }
13586 }
13588 /* Check if X, a register, is known to contain a value already
13589 truncated to MODE. In this case we can use a subreg to refer to
13590 the truncated value even though in the generic case we would need
13591 an explicit truncation. */
13593 static bool
13595 {
13607 }
13609 /* If X is a hard reg or a subreg record the mode that the register is
13610 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13611 able to turn a truncate into a subreg using this information. Return true
13612 if traversing X is complete. */
13614 static bool
13616 {
13617 machine_mode truncated_mode;
13621 {
13633 }
13634 /* ??? For hard-regs we now record everything. We might be able to
13635 optimize this using last_set_mode. */
13638 else
13645 {
13648 }
13651 }
13653 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13654 the modes they are used in. This can help truning TRUNCATEs into
13655 SUBREGs. */
13657 static void
13659 {
13664 }
13666 /* Scan X for promoted SUBREGs. For each one found,
13667 note what it implies to the registers used in it. */
13669 static void
13671 {
13676 else
13677 {
13683 {
13693 }
13694 }
13695 }
13696 \f
13697 /* Verify that all the registers and memory references mentioned in *LOC are
13698 still valid. *LOC was part of a value set in INSN when label_tick was
13699 equal to TICK. Return false if some are not. If REPLACE is true, replace
13700 the invalid references with (clobber (const_int 0)) and return true. This
13701 replacement is useful because we often can get useful information about
13702 the form of a value (e.g., if it was produced by a shift that always
13703 produces -1 or 0) even though we don't know exactly what registers it
13704 was produced from. */
13706 static bool
13708 {
13715 {
13721 {
13724 /* If this is a pseudo-register that was only set once and not
13725 live at the beginning of the function, it is always valid. */
13729 && (!REGNO_REG_SET_P
13731 regno)))
13733 {
13737 }
13738 }
13741 }
13742 /* If this is a memory reference, make sure that there were no stores after
13743 it that might have clobbered the value. We don't have alias info, so we
13744 assume any store invalidates it. Moreover, we only have local UIDs, so
13745 we also assume that there were stores in the intervening basic blocks. */
13748 {
13752 }
13755 {
13757 {
13758 /* Check for identical subexpressions. If x contains
13759 identical subexpression we only have to traverse one of
13760 them. */
13762 {
13763 /* Note that at this point x0 has already been checked
13764 and found valid. */
13768 /* If x0 and x1 are identical then x is also valid. */
13772 /* If x1 is identical to a subexpression of x0 then
13773 while checking x0, x1 has already been checked. Thus
13774 it is valid and so as x. */
13779 /* If x0 is identical to a subexpression of x1 then x is
13780 valid iff the rest of x1 is valid. */
13783 return
13787 }
13791 }
13797 }
13799 /* If we haven't found a reason for it to be invalid, it is valid. */
13801 }
13803 /* Get the last value assigned to X, if known. Some registers
13804 in the value may be replaced with (clobber (const_int 0)) if their value
13805 is known longer known reliably. */
13807 static rtx
13809 {
13811 rtx value;
13814 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13815 then convert it to the desired mode. If this is a paradoxical SUBREG,
13816 we cannot predict what values the "extra" bits might have. */
13830 /* If we don't have a value, or if it isn't for this basic block and
13831 it's either a hard register, set more than once, or it's a live
13832 at the beginning of the function, return 0.
13834 Because if it's not live at the beginning of the function then the reg
13835 is always set before being used (is never used without being set).
13836 And, if it's set only once, and it's always set before use, then all
13837 uses must have the same last value, even if it's not from this basic
13838 block. */
13845 || REGNO_REG_SET_P
13849 /* If the value was set in a later insn than the ones we are processing,
13850 we can't use it even if the register was only set once. */
13855 /* If fewer bits were set than what we are asked for now, we cannot use
13856 the value. */
13861 /* If the value has all its registers valid, return it. */
13866 /* Otherwise, make a copy and replace any invalid register with
13867 (clobber (const_int 0)). If that fails for some reason, return 0. */
13875 }
13876 \f
13877 /* Define three variables used for communication between the following
13878 routines. */
13882 rtx reg_dead_reg;
13884 /* Function called via note_stores from reg_dead_at_p.
13886 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13887 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13889 static void
13891 {
13901 }
13903 /* Return true if REG is known to be dead at INSN.
13905 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13906 referencing REG, it is dead. If we hit a SET referencing REG, it is
13907 live. Otherwise, see if it is live or dead at the start of the basic
13908 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13909 must be assumed to be always live. */
13911 static bool
13913 {
13914 basic_block block;
13917 /* Set variables for reg_dead_at_p_1. */
13924 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13925 we allow the machine description to decide whether use-and-clobber
13926 patterns are OK. */
13928 {
13932 }
13934 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13935 beginning of basic block. */
13938 {
13940 {
13950 }
13956 }
13958 /* Look at live-in sets for the basic block that we were in. */
13964 }
13965 \f
13966 /* Note hard registers in X that are used. */
13968 static void
13970 {
13976 {
13980 CASE_CONST_ANY:
13988 /* If we are clobbering a MEM, mark any hard registers inside the
13989 address as used. */
13996 /* A hard reg in a wide mode may really be multiple registers.
13997 If so, mark all of them just like the first. */
13999 {
14000 /* None of this applies to the stack, frame or arg pointers. */
14002 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14010 }
14014 {
14015 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14016 the address. */
14028 }
14033 }
14035 /* Recursively scan the operands of this expression. */
14037 {
14041 {
14045 {
14050 }
14051 }
14052 }
14053 }
14054 \f
14055 /* Remove register number REGNO from the dead registers list of INSN.
14057 Return the note used to record the death, if there was one. */
14059 rtx
14061 {
14068 }
14070 /* For each register (hardware or pseudo) used within expression X, if its
14071 death is in an instruction with luid between FROM_LUID (inclusive) and
14072 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14073 list headed by PNOTES.
14075 That said, don't move registers killed by maybe_kill_insn.
14077 This is done when X is being merged by combination into TO_INSN. These
14078 notes will then be distributed as needed. */
14080 static void
14083 {
14089 {
14093 /* If we do not know where the register died, it may still die between
14094 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14096 {
14101 {
14103 {
14107 }
14110 }
14111 }
14113 /* Don't move the register if it gets killed in between from and to. */
14122 {
14125 /* It is possible for the call above to return 0. This can occur
14126 when last_death points to I2 or I1 that we combined with.
14127 In that case make a new note.
14129 We must also check for the case where X is a hard register
14130 and NOTE is a death note for a range of hard registers
14131 including X. In that case, we must put REG_DEAD notes for
14132 the remaining registers in place of NOTE. */
14136 {
14145 }
14147 /* If we didn't find any note, or if we found a REG_DEAD note that
14148 covers only part of the given reg, and we have a multi-reg hard
14149 register, then to be safe we must check for REG_DEAD notes
14150 for each register other than the first. They could have
14151 their own REG_DEAD notes lying around. */
14158 {
14165 else
14171 }
14174 {
14177 }
14178 else
14180 }
14183 }
14186 {
14191 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14192 that accesses one word of a multi-word item, some
14193 piece of everything register in the expression is used by
14194 this insn, so remove any old death. */
14195 /* ??? So why do we test for equality of the sizes? */
14201 {
14204 }
14206 /* If this is some other SUBREG, we know it replaces the entire
14207 value, so use that as the destination. */
14211 /* If this is a MEM, adjust deaths of anything used in the address.
14212 For a REG (the only other possibility), the entire value is
14213 being replaced so the old value is not used in this insn. */
14219 }
14228 {
14230 {
14235 }
14238 }
14239 }
14240 \f
14241 /* Return true if X is the target of a bit-field assignment in BODY, the
14242 pattern of an insn. X must be a REG. */
14244 static bool
14246 {
14250 {
14252 rtx target;
14259 else
14276 }
14284 }
14285 \f
14286 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14287 as appropriate. I3 and I2 are the insns resulting from the combination
14288 insns including FROM (I2 may be zero).
14290 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14291 not need REG_DEAD notes because they are being substituted for. This
14292 saves searching in the most common cases.
14294 Each note in the list is either ignored or placed on some insns, depending
14295 on the type of note. */
14297 static void
14300 {
14302 rtx tem_note;
14306 {
14311 {
14314 /* Doesn't matter much where we put this, as long as it's somewhere.
14315 It is preferable to keep these notes on branches, which is most
14316 likely to be i3. */
14323 else
14324 {
14327 }
14331 {
14332 /* The landing pad handling needs to be kept in sync with the
14333 prerequisite checking in try_combine. */
14335 /* A REG_EH_REGION note transfering control can only ever come
14336 from i3. */
14339 /* We are making sure there is a single effective REG_EH_REGION
14340 note and it's valid to put it on i3. */
14343 /* Throw away stray notes on insns that can never throw or
14344 make a nonlocal goto. */
14345 ;
14346 else
14347 {
14350 else
14351 {
14353 /* If i3 can still trap preserve the note, otherwise we've
14354 combined things such that we can now prove that the
14355 instructions can't trap. Drop the note in this case. */
14358 }
14359 }
14361 }
14364 /* ??? How to distribute between i3-i1. Assume i3 contains the
14365 entire adjustment. Assert i3 contains at least some adjust. */
14367 {
14369 /* fixup_args_size_notes looks at REG_NORETURN note,
14370 so ensure the note is placed there first. */
14372 {
14376 {
14382 }
14383 }
14385 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14386 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14389 && !ACCUMULATE_OUTGOING_ARGS
14391 }
14400 /* These notes must remain with the call. It should not be
14401 possible for both I2 and I3 to be a call. */
14404 else
14405 {
14408 }
14412 /* Any clobbers for i3 may still exist, and so we must process
14413 REG_UNUSED notes from that insn.
14415 Any clobbers from i2 or i1 can only exist if they were added by
14416 recog_for_combine. In that case, recog_for_combine created the
14417 necessary REG_UNUSED notes. Trying to keep any original
14418 REG_UNUSED notes from these insns can cause incorrect output
14419 if it is for the same register as the original i3 dest.
14420 In that case, we will notice that the register is set in i3,
14421 and then add a REG_UNUSED note for the destination of i3, which
14422 is wrong. However, it is possible to have REG_UNUSED notes from
14423 i2 or i1 for register which were both used and clobbered, so
14424 we keep notes from i2 or i1 if they will turn into REG_DEAD
14425 notes. */
14427 /* If this register is set or clobbered between FROM_INSN and I3,
14428 we should not create a note for it. */
14432 /* If this register is set or clobbered in I3, put the note there
14433 unless there is one already. */
14435 {
14443 }
14444 /* Otherwise, if this register is used by I3, then this register
14445 now dies here, so we must put a REG_DEAD note here unless there
14446 is one already. */
14452 {
14455 }
14457 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14458 but we can't tell which at this point. We must reset any
14459 expectations we had about the value that was previously
14460 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14461 and, if appropriate, restore its previous value, but we
14462 don't have enough information for that at this point. */
14463 else
14464 {
14467 /* Otherwise, if this register is now referenced in i2
14468 then the register used to be modified in one of the
14469 original insns. If it was i3 (say, in an unused
14470 parallel), it's now completely gone, so the note can
14471 be discarded. But if it was modified in i2, i1 or i0
14472 and we still reference it in i2, then we're
14473 referencing the previous value, and since the
14474 register was modified and REG_UNUSED, we know that
14475 the previous value is now dead. So, if we only
14476 reference the register in i2, we change the note to
14477 REG_DEAD, to reflect the previous value. However, if
14478 we're also setting or clobbering the register as
14479 scratch, we know (because the register was not
14480 referenced in i3) that it's unused, just as it was
14481 unused before, and we place the note in i2. */
14484 {
14493 }
14494 }
14501 /* These notes say something about results of an insn. We can
14502 only support them if they used to be on I3 in which case they
14503 remain on I3. Otherwise they are ignored.
14505 If the note refers to an expression that is not a constant, we
14506 must also ignore the note since we cannot tell whether the
14507 equivalence is still true. It might be possible to do
14508 slightly better than this (we only have a problem if I2DEST
14509 or I1DEST is present in the expression), but it doesn't
14510 seem worth the trouble. */
14518 /* These notes say something about how a register is used. They must
14519 be present on any use of the register in I2 or I3. */
14524 {
14527 else
14529 }
14534 /* This can show up in several ways -- either directly in the
14535 pattern, or hidden off in the constant pool with (or without?)
14536 a REG_EQUAL note. */
14537 /* ??? Ignore the without-reg_equal-note problem for now. */
14549 {
14552 else
14554 }
14556 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14557 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14558 there. */
14563 {
14570 }
14576 {
14584 }
14588 /* This note says something about the value of a register prior
14589 to the execution of an insn. It is too much trouble to see
14590 if the note is still correct in all situations. It is better
14591 to simply delete it. */
14595 /* If we replaced the right hand side of FROM_INSN with a
14596 REG_EQUAL note, the original use of the dying register
14597 will not have been combined into I3 and I2. In such cases,
14598 FROM_INSN is guaranteed to be the first of the combined
14599 instructions, so we simply need to search back before
14600 FROM_INSN for the previous use or set of this register,
14601 then alter the notes there appropriately.
14603 If the register is used as an input in I3, it dies there.
14604 Similarly for I2, if it is nonzero and adjacent to I3.
14606 If the register is not used as an input in either I3 or I2
14607 and it is not one of the registers we were supposed to eliminate,
14608 there are two possibilities. We might have a non-adjacent I2
14609 or we might have somehow eliminated an additional register
14610 from a computation. For example, we might have had A & B where
14611 we discover that B will always be zero. In this case we will
14612 eliminate the reference to A.
14614 In both cases, we must search to see if we can find a previous
14615 use of A and put the death note there. */
14621 else
14622 {
14628 {
14629 /* If the new I2 sets the same register that is marked
14630 dead in the note, we do not in general know where to
14631 put the note. One important case we _can_ handle is
14632 when the note comes from I3. */
14635 else
14637 }
14644 && !(i2mod
14646 i2mod_old_rhs)))
14651 }
14654 {
14658 {
14660 {
14664 }
14666 /* If the register is being set at TEM_INSN, see if that is all
14667 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14668 into a REG_UNUSED note instead. Don't delete sets to
14669 global register vars. */
14673 {
14683 ;
14685 /* Verify that it was the set, and not a clobber that
14686 modified the register.
14688 If we cannot delete the setter due to side
14689 effects, mark the user with an UNUSED note instead
14690 of deleting it. */
14694 {
14695 /* Move the notes and links of TEM_INSN elsewhere.
14696 This might delete other dead insns recursively.
14697 First set the pattern to something that won't use
14698 any register. */
14716 }
14717 else
14718 {
14721 /* If there isn't already a REG_UNUSED note, put one
14722 here. Do not place a REG_DEAD note, even if
14723 the register is also used here; that would not
14724 match the algorithm used in lifetime analysis
14725 and can cause the consistency check in the
14726 scheduler to fail. */
14731 }
14732 }
14736 {
14739 /* If we are doing a 3->2 combination, and we have a
14740 register which formerly died in i3 and was not used
14741 by i2, which now no longer dies in i3 and is used in
14742 i2 but does not die in i2, and place is between i2
14743 and i3, then we may need to move a link from place to
14744 i2. */
14746 && from_insn
14749 {
14753 }
14755 }
14759 }
14761 }
14763 /* If the register is set or already dead at PLACE, we needn't do
14764 anything with this note if it is still a REG_DEAD note.
14765 We check here if it is set at all, not if is it totally replaced,
14766 which is what `dead_or_set_p' checks, so also check for it being
14767 set partially. */
14770 {
14776 {
14777 /* Unless the register previously died in PLACE, clear
14778 last_death. [I no longer understand why this is
14779 being done.] */
14783 }
14784 else
14787 /* If this is a death note for a hard reg that is occupying
14788 multiple registers, ensure that we are still using all
14789 parts of the object. If we find a piece of the object
14790 that is unused, we must arrange for an appropriate REG_DEAD
14791 note to be added for it. However, we can't just emit a USE
14792 and tag the note to it, since the register might actually
14793 be dead; so we recourse, and the recursive call then finds
14794 the previous insn that used this register. */
14797 {
14806 {
14809 }
14812 {
14813 /* Put only REG_DEAD notes for pieces that are
14814 not already dead or set. */
14818 {
14825 {
14827 NULL_RTX);
14831 NULL_RTX);
14832 }
14837 {
14839 {
14843 }
14847 {
14850 }
14851 }
14852 }
14855 }
14856 }
14857 }
14861 /* Any other notes should not be present at this point in the
14862 compilation. */
14864 }
14867 {
14871 /* Set added_notes_insn to the earliest insn we added a note to. */
14875 }
14878 {
14881 /* Set added_notes_insn to the earliest insn we added a note to. */
14885 }
14886 }
14887 }
14888 \f
14889 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14890 I3, I2, and I1 to new locations. This is also called to add a link
14891 pointing at I3 when I3's destination is changed. */
14893 static void
14895 {
14899 {
14906 /* If the insn that this link points to is a NOTE, ignore it. */
14915 {
14918 {
14934 }
14937 }
14938 else
14951 /* A LOG_LINK is defined as being placed on the first insn that uses
14952 a register and points to the insn that sets the register. Start
14953 searching at the next insn after the target of the link and stop
14954 when we reach a set of the register or the end of the basic block.
14956 Note that this correctly handles the link that used to point from
14957 I3 to I2. Also note that not much searching is typically done here
14958 since most links don't point very far away. */
14967 {
14971 }
14974 {
14977 }
14981 /* If we found a place to put the link, place it there unless there
14982 is already a link to the same insn as LINK at that point. */
14985 {
14993 {
14997 /* Set added_links_insn to the earliest insn we added a
14998 link to. */
15002 }
15003 }
15004 }
15005 }
15006 \f
15007 /* Check for any register or memory mentioned in EQUIV that is not
15008 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15009 of EXPR where some registers may have been replaced by constants. */
15011 static bool
15013 {
15016 {
15021 }
15023 }
15024 \f
15025 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15026 the reg-to-reg copy can usefully combine with later instructions, but we
15027 do not want to combine the hard reg into later instructions, for that
15028 restricts register allocation. */
15029 static void
15031 {
15032 basic_block bb;
15035 {
15039 {
15062 }
15063 }
15064 }
15066 /* Try combining insns through substitution. */
15067 static void
15069 {
15079 bool rebuild_jump_labels_after_combine
15082 /* Combining insns may have turned an indirect jump into a
15083 direct jump. Rebuild the JUMP_LABEL fields of jumping
15084 instructions. */
15086 {
15093 }
15096 }
15101 {
15111 };
15114 {
15118 {}
15120 /* opt_pass methods: */
15123 {
15126 }
15132 rtl_opt_pass *
15134 {
15136 }