1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
37 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 All the pseudos that were formerly allocated to the hard regs that
58 are now in use as reload regs must be ``spilled''. This means
59 that they go to other hard regs, or to stack slots if no other
60 available hard regs can be found. Spilling can invalidate more
61 insns, requiring additional need for reloads, so we must keep checking
62 until the process stabilizes.
64 For machines with different classes of registers, we must keep track
65 of the register class needed for each reload, and make sure that
66 we allocate enough reload registers of each class.
68 The file reload.c contains the code that checks one insn for
69 validity and reports the reloads that it needs. This file
70 is in charge of scanning the entire rtl code, accumulating the
71 reload needs, spilling, assigning reload registers to use for
72 fixing up each insn, and generating the new insns to copy values
73 into the reload registers. */
76 #ifndef REGISTER_MOVE_COST
77 #define REGISTER_MOVE_COST(x, y) 2
80 /* During reload_as_needed, element N contains a REG rtx for the hard reg
81 into which reg N has been reloaded (perhaps for a previous insn). */
82 static rtx
*reg_last_reload_reg
;
84 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
85 for an output reload that stores into reg N. */
86 static char *reg_has_output_reload
;
88 /* Indicates which hard regs are reload-registers for an output reload
89 in the current insn. */
90 static HARD_REG_SET reg_is_output_reload
;
92 /* Element N is the constant value to which pseudo reg N is equivalent,
93 or zero if pseudo reg N is not equivalent to a constant.
94 find_reloads looks at this in order to replace pseudo reg N
95 with the constant it stands for. */
96 rtx
*reg_equiv_constant
;
98 /* Element N is a memory location to which pseudo reg N is equivalent,
99 prior to any register elimination (such as frame pointer to stack
100 pointer). Depending on whether or not it is a valid address, this value
101 is transferred to either reg_equiv_address or reg_equiv_mem. */
102 rtx
*reg_equiv_memory_loc
;
104 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
105 This is used when the address is not valid as a memory address
106 (because its displacement is too big for the machine.) */
107 rtx
*reg_equiv_address
;
109 /* Element N is the memory slot to which pseudo reg N is equivalent,
110 or zero if pseudo reg N is not equivalent to a memory slot. */
113 /* Widest width in which each pseudo reg is referred to (via subreg). */
114 static int *reg_max_ref_width
;
116 /* Element N is the insn that initialized reg N from its equivalent
117 constant or memory slot. */
118 static rtx
*reg_equiv_init
;
120 /* During reload_as_needed, element N contains the last pseudo regno reloaded
121 into hard register N. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
126 /* During reload_as_needed, element N contains the insn for which
127 hard register N was last used. Its contents are significant only
128 when reg_reloaded_valid is set for this register. */
129 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
131 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
132 static HARD_REG_SET reg_reloaded_valid
;
133 /* Indicate if the register was dead at the end of the reload.
134 This is only valid if reg_reloaded_contents is set and valid. */
135 static HARD_REG_SET reg_reloaded_dead
;
137 /* Number of spill-regs so far; number of valid elements of spill_regs. */
140 /* In parallel with spill_regs, contains REG rtx's for those regs.
141 Holds the last rtx used for any given reg, or 0 if it has never
142 been used for spilling yet. This rtx is reused, provided it has
144 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
146 /* In parallel with spill_regs, contains nonzero for a spill reg
147 that was stored after the last time it was used.
148 The precise value is the insn generated to do the store. */
149 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
151 /* This table is the inverse mapping of spill_regs:
152 indexed by hard reg number,
153 it contains the position of that reg in spill_regs,
154 or -1 for something that is not in spill_regs. */
155 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
157 /* This reg set indicates registers that may not be used for retrying global
158 allocation. The registers that may not be used include all spill registers
159 and the frame pointer (if we are using one). */
160 HARD_REG_SET forbidden_regs
;
162 /* This reg set indicates registers that are not good for spill registers.
163 They will not be used to complete groups of spill registers. This includes
164 all fixed registers, registers that may be eliminated, and, if
165 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
167 (spill_reg_order prevents these registers from being used to start a
169 static HARD_REG_SET bad_spill_regs
;
171 /* Describes order of use of registers for reloading
172 of spilled pseudo-registers. `spills' is the number of
173 elements that are actually valid; new ones are added at the end. */
174 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
176 /* This reg set indicates those registers that have been used a spill
177 registers. This information is used in reorg.c, to help figure out
178 what registers are live at any point. It is assumed that all spill_regs
179 are dead at every CODE_LABEL. */
181 HARD_REG_SET used_spill_regs
;
183 /* Index of last register assigned as a spill register. We allocate in
184 a round-robin fashion. */
186 static int last_spill_reg
;
188 /* Describes order of preference for putting regs into spill_regs.
189 Contains the numbers of all the hard regs, in order most preferred first.
190 This order is different for each function.
191 It is set up by order_regs_for_reload.
192 Empty elements at the end contain -1. */
193 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
195 /* 1 for a hard register that appears explicitly in the rtl
196 (for example, function value registers, special registers
197 used by insns, structure value pointer registers). */
198 static char regs_explicitly_used
[FIRST_PSEUDO_REGISTER
];
200 /* Indicates if a register was counted against the need for
201 groups. 0 means it can count against max_nongroup instead. */
202 static HARD_REG_SET counted_for_groups
;
204 /* Indicates if a register was counted against the need for
205 non-groups. 0 means it can become part of a new group.
206 During choose_reload_regs, 1 here means don't use this reg
207 as part of a group, even if it seems to be otherwise ok. */
208 static HARD_REG_SET counted_for_nongroups
;
210 /* Nonzero if indirect addressing is supported on the machine; this means
211 that spilling (REG n) does not require reloading it into a register in
212 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
213 value indicates the level of indirect addressing supported, e.g., two
214 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
217 static char spill_indirect_levels
;
219 /* Nonzero if indirect addressing is supported when the innermost MEM is
220 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
221 which these are valid is the same as spill_indirect_levels, above. */
223 char indirect_symref_ok
;
225 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
227 char double_reg_address_ok
;
229 /* Record the stack slot for each spilled hard register. */
231 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
233 /* Width allocated so far for that stack slot. */
235 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
237 /* Indexed by register class and basic block number, nonzero if there is
238 any need for a spill register of that class in that basic block.
239 The pointer is 0 if we did stupid allocation and don't know
240 the structure of basic blocks. */
242 char *basic_block_needs
[N_REG_CLASSES
];
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid
;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
251 int caller_save_needed
;
253 /* The register class to use for a base register when reloading an
254 address. This is normally BASE_REG_CLASS, but it may be different
255 when using SMALL_REGISTER_CLASSES and passing parameters in
257 enum reg_class reload_address_base_reg_class
;
259 /* The register class to use for an index register when reloading an
260 address. This is normally INDEX_REG_CLASS, but it may be different
261 when using SMALL_REGISTER_CLASSES and passing parameters in
263 enum reg_class reload_address_index_reg_class
;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress
= 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
274 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
275 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
281 struct obstack reload_obstack
;
282 char *reload_firstobj
;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of labels that must never be deleted. */
288 extern rtx forced_labels
;
290 /* Allocation number table from global register allocation. */
291 extern int *reg_allocno
;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
298 static struct elim_table
300 int from
; /* Register number to be eliminated. */
301 int to
; /* Register number used as replacement. */
302 int initial_offset
; /* Initial difference between values. */
303 int can_eliminate
; /* Non-zero if this elimination can be done. */
304 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 int offset
; /* Current offset between the two regs. */
307 int max_offset
; /* Maximum offset between the two regs. */
308 int previous_offset
; /* Offset at end of previous insn. */
309 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx
; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx
; /* REG rtx for the replacement. */
318 /* If a set of eliminable registers was specified, define the table from it.
319 Otherwise, default to the normal case of the frame pointer being
320 replaced by the stack pointer. */
322 #ifdef ELIMINABLE_REGS
325 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
328 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
330 /* Record the number of pending eliminations that have an offset not equal
331 to their initial offset. If non-zero, we use a new copy of each
332 replacement result in any insns encountered. */
333 static int num_not_at_initial_offset
;
335 /* Count the number of registers that we may be able to eliminate. */
336 static int num_eliminable
;
338 /* For each label, we record the offset of each elimination. If we reach
339 a label by more than one path and an offset differs, we cannot do the
340 elimination. This information is indexed by the number of the label.
341 The first table is an array of flags that records whether we have yet
342 encountered a label and the second table is an array of arrays, one
343 entry in the latter array for each elimination. */
345 static char *offsets_known_at
;
346 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
348 /* Number of labels in the current function. */
350 static int num_labels
;
352 struct hard_reg_n_uses
{ int regno
; int uses
; };
354 static int calculate_needs_all_insns
PROTO((rtx
, int));
355 static int calculate_needs
PROTO((int, rtx
, rtx
, int));
356 static int find_reload_regs
PROTO((int, FILE *));
357 static int find_tworeg_group
PROTO((int, int, FILE *));
358 static int find_group
PROTO((int, int, FILE *));
359 static int possible_group_p
PROTO((int, int *));
360 static void count_possible_groups
PROTO((int *, enum machine_mode
*,
362 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
365 static void spill_failure
PROTO((rtx
));
366 static int new_spill_reg
PROTO((int, int, int *, int *, int,
368 static void delete_dead_insn
PROTO((rtx
));
369 static void alter_reg
PROTO((int, int));
370 static void mark_scratch_live
PROTO((rtx
));
371 static void set_label_offsets
PROTO((rtx
, rtx
, int));
372 static int eliminate_regs_in_insn
PROTO((rtx
, int));
373 static void mark_not_eliminable
PROTO((rtx
, rtx
));
374 static int spill_hard_reg
PROTO((int, int, FILE *, int));
375 static void scan_paradoxical_subregs
PROTO((rtx
));
376 static int hard_reg_use_compare
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
377 static void order_regs_for_reload
PROTO((int));
378 static int compare_spill_regs
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
379 static void reload_as_needed
PROTO((rtx
, int));
380 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
381 static int reload_reg_class_lower
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
382 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
384 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
386 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
387 static int reload_reg_free_before_p
PROTO((int, int, enum reload_type
, int));
388 static int reload_reg_free_for_value_p
PROTO((int, int, enum reload_type
, rtx
, rtx
, int));
389 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
390 static int allocate_reload_reg
PROTO((int, rtx
, int, int));
391 static void choose_reload_regs
PROTO((rtx
, rtx
));
392 static void merge_assigned_reloads
PROTO((rtx
));
393 static void emit_reload_insns
PROTO((rtx
));
394 static void delete_output_reload
PROTO((rtx
, int, rtx
));
395 static void inc_for_reload
PROTO((rtx
, rtx
, int));
396 static int constraint_accepts_reg_p
PROTO((char *, rtx
));
397 static void reload_cse_invalidate_regno
PROTO((int, enum machine_mode
, int));
398 static int reload_cse_mem_conflict_p
PROTO((rtx
, rtx
));
399 static void reload_cse_invalidate_mem
PROTO((rtx
));
400 static void reload_cse_invalidate_rtx
PROTO((rtx
, rtx
));
401 static int reload_cse_regno_equal_p
PROTO((int, rtx
, enum machine_mode
));
402 static int reload_cse_noop_set_p
PROTO((rtx
, rtx
));
403 static int reload_cse_simplify_set
PROTO((rtx
, rtx
));
404 static int reload_cse_simplify_operands
PROTO((rtx
));
405 static void reload_cse_check_clobber
PROTO((rtx
, rtx
));
406 static void reload_cse_record_set
PROTO((rtx
, rtx
));
407 static void reload_cse_delete_death_notes
PROTO((rtx
));
408 static void reload_cse_no_longer_dead
PROTO((int, enum machine_mode
));
410 /* Initialize the reload pass once per compilation. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode
,
424 gen_rtx_REG (Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
426 spill_indirect_levels
= 0;
428 while (memory_address_p (QImode
, tem
))
430 spill_indirect_levels
++;
431 tem
= gen_rtx_MEM (Pmode
, tem
);
434 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
436 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
437 indirect_symref_ok
= memory_address_p (QImode
, tem
);
439 /* See if reg+reg is a valid (and offsettable) address. */
441 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
443 tem
= gen_rtx_PLUS (Pmode
,
444 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
445 gen_rtx_REG (Pmode
, i
));
446 /* This way, we make sure that reg+reg is an offsettable address. */
447 tem
= plus_constant (tem
, 4);
449 if (memory_address_p (QImode
, tem
))
451 double_reg_address_ok
= 1;
456 /* Initialize obstack for our rtl allocation. */
457 gcc_obstack_init (&reload_obstack
);
458 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
460 /* Decide which register class should be used when reloading
461 addresses. If we are using SMALL_REGISTER_CLASSES, and any
462 parameters are passed in registers, then we do not want to use
463 those registers when reloading an address. Otherwise, if a
464 function argument needs a reload, we may wind up clobbering
465 another argument to the function which was already computed. If
466 we find a subset class which simply avoids those registers, we
467 use it instead. ??? It would be better to only use the
468 restricted class when we actually are loading function arguments,
469 but that is hard to determine. */
470 reload_address_base_reg_class
= BASE_REG_CLASS
;
471 reload_address_index_reg_class
= INDEX_REG_CLASS
;
472 if (SMALL_REGISTER_CLASSES
)
475 HARD_REG_SET base
, index
;
478 COPY_HARD_REG_SET (base
, reg_class_contents
[BASE_REG_CLASS
]);
479 COPY_HARD_REG_SET (index
, reg_class_contents
[INDEX_REG_CLASS
]);
480 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
482 if (FUNCTION_ARG_REGNO_P (regno
))
484 CLEAR_HARD_REG_BIT (base
, regno
);
485 CLEAR_HARD_REG_BIT (index
, regno
);
489 GO_IF_HARD_REG_EQUAL (base
, reg_class_contents
[BASE_REG_CLASS
],
491 for (p
= reg_class_subclasses
[BASE_REG_CLASS
];
492 *p
!= LIM_REG_CLASSES
;
495 GO_IF_HARD_REG_EQUAL (base
, reg_class_contents
[*p
], usebase
);
498 reload_address_base_reg_class
= *p
;
503 GO_IF_HARD_REG_EQUAL (index
, reg_class_contents
[INDEX_REG_CLASS
],
505 for (p
= reg_class_subclasses
[INDEX_REG_CLASS
];
506 *p
!= LIM_REG_CLASSES
;
509 GO_IF_HARD_REG_EQUAL (index
, reg_class_contents
[*p
], useindex
);
512 reload_address_index_reg_class
= *p
;
519 /* Global variables used by reload and its subroutines. */
521 /* Set during calculate_needs if an insn needs reloading. */
522 static int something_needs_reloads
;
523 /* Set during calculate_needs if an insn needs register elimination. */
524 static int something_needs_elimination
;
526 /* Indicate whether caller saves need a spill register. */
527 static enum reg_class caller_save_spill_class
= NO_REGS
;
528 static int caller_save_group_size
= 1;
530 /* For each class, number of reload regs needed in that class.
531 This is the maximum over all insns of the needs in that class
532 of the individual insn. */
533 static int max_needs
[N_REG_CLASSES
];
535 /* For each class, size of group of consecutive regs
536 that is needed for the reloads of this class. */
537 static int group_size
[N_REG_CLASSES
];
539 /* For each class, max number of consecutive groups needed.
540 (Each group contains group_size[CLASS] consecutive registers.) */
541 static int max_groups
[N_REG_CLASSES
];
543 /* For each class, max number needed of regs that don't belong
544 to any of the groups. */
545 static int max_nongroups
[N_REG_CLASSES
];
547 /* For each class, the machine mode which requires consecutive
548 groups of regs of that class.
549 If two different modes ever require groups of one class,
550 they must be the same size and equally restrictive for that class,
551 otherwise we can't handle the complexity. */
552 static enum machine_mode group_mode
[N_REG_CLASSES
];
554 /* Record the insn where each maximum need is first found. */
555 static rtx max_needs_insn
[N_REG_CLASSES
];
556 static rtx max_groups_insn
[N_REG_CLASSES
];
557 static rtx max_nongroups_insn
[N_REG_CLASSES
];
559 /* Nonzero means we couldn't get enough spill regs. */
562 /* Main entry point for the reload pass.
564 FIRST is the first insn of the function being compiled.
566 GLOBAL nonzero means we were called from global_alloc
567 and should attempt to reallocate any pseudoregs that we
568 displace from hard regs we will use for reloads.
569 If GLOBAL is zero, we do not have enough information to do that,
570 so any pseudo reg that is spilled must go to the stack.
572 DUMPFILE is the global-reg debugging dump file stream, or 0.
573 If it is nonzero, messages are written to it to describe
574 which registers are seized as reload regs, which pseudo regs
575 are spilled from them, and where the pseudo regs are reallocated to.
577 Return value is nonzero if reload failed
578 and we must not do any more for this function. */
581 reload (first
, global
, dumpfile
)
588 register struct elim_table
*ep
;
590 /* The two pointers used to track the true location of the memory used
591 for label offsets. */
592 char *real_known_ptr
= NULL_PTR
;
593 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
595 int something_changed
;
597 /* Make sure even insns with volatile mem refs are recognizable. */
602 /* Enable find_equiv_reg to distinguish insns made by reload. */
603 reload_first_uid
= get_max_uid ();
605 caller_save_spill_class
= NO_REGS
;
606 caller_save_group_size
= 1;
608 for (i
= 0; i
< N_REG_CLASSES
; i
++)
609 basic_block_needs
[i
] = 0;
611 #ifdef SECONDARY_MEMORY_NEEDED
612 /* Initialize the secondary memory table. */
613 clear_secondary_mem ();
616 /* Remember which hard regs appear explicitly
617 before we merge into `regs_ever_live' the ones in which
618 pseudo regs have been allocated. */
619 bcopy (regs_ever_live
, regs_explicitly_used
, sizeof regs_ever_live
);
621 /* We don't have a stack slot for any spill reg yet. */
622 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
623 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
625 /* Initialize the save area information for caller-save, in case some
629 /* Compute which hard registers are now in use
630 as homes for pseudo registers.
631 This is done here rather than (eg) in global_alloc
632 because this point is reached even if not optimizing. */
633 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
636 /* A function that receives a nonlocal goto must save all call-saved
638 if (current_function_has_nonlocal_label
)
639 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
641 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
642 regs_ever_live
[i
] = 1;
645 for (i
= 0; i
< scratch_list_length
; i
++)
647 mark_scratch_live (scratch_list
[i
]);
649 /* Make sure that the last insn in the chain
650 is not something that needs reloading. */
651 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
653 /* Find all the pseudo registers that didn't get hard regs
654 but do have known equivalent constants or memory slots.
655 These include parameters (known equivalent to parameter slots)
656 and cse'd or loop-moved constant memory addresses.
658 Record constant equivalents in reg_equiv_constant
659 so they will be substituted by find_reloads.
660 Record memory equivalents in reg_mem_equiv so they can
661 be substituted eventually by altering the REG-rtx's. */
663 reg_equiv_constant
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
664 bzero ((char *) reg_equiv_constant
, max_regno
* sizeof (rtx
));
665 reg_equiv_memory_loc
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
666 bzero ((char *) reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
667 reg_equiv_mem
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
668 bzero ((char *) reg_equiv_mem
, max_regno
* sizeof (rtx
));
669 reg_equiv_init
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
670 bzero ((char *) reg_equiv_init
, max_regno
* sizeof (rtx
));
671 reg_equiv_address
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
672 bzero ((char *) reg_equiv_address
, max_regno
* sizeof (rtx
));
673 reg_max_ref_width
= (int *) xmalloc (max_regno
* sizeof (int));
674 bzero ((char *) reg_max_ref_width
, max_regno
* sizeof (int));
676 if (SMALL_REGISTER_CLASSES
)
677 CLEAR_HARD_REG_SET (forbidden_regs
);
679 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
680 Also find all paradoxical subregs and find largest such for each pseudo.
681 On machines with small register classes, record hard registers that
682 are used for user variables. These can never be used for spills.
683 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
684 caller-saved registers must be marked live. */
686 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
688 rtx set
= single_set (insn
);
690 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
691 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
692 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
693 if (! call_used_regs
[i
])
694 regs_ever_live
[i
] = 1;
696 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
698 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
700 #ifdef LEGITIMATE_PIC_OPERAND_P
701 && (! CONSTANT_P (XEXP (note
, 0)) || ! flag_pic
702 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
706 rtx x
= XEXP (note
, 0);
707 i
= REGNO (SET_DEST (set
));
708 if (i
> LAST_VIRTUAL_REGISTER
)
710 if (GET_CODE (x
) == MEM
)
712 /* If the operand is a PLUS, the MEM may be shared,
713 so make sure we have an unshared copy here. */
714 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
717 reg_equiv_memory_loc
[i
] = x
;
719 else if (CONSTANT_P (x
))
721 if (LEGITIMATE_CONSTANT_P (x
))
722 reg_equiv_constant
[i
] = x
;
724 reg_equiv_memory_loc
[i
]
725 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
730 /* If this register is being made equivalent to a MEM
731 and the MEM is not SET_SRC, the equivalencing insn
732 is one with the MEM as a SET_DEST and it occurs later.
733 So don't mark this insn now. */
734 if (GET_CODE (x
) != MEM
735 || rtx_equal_p (SET_SRC (set
), x
))
736 reg_equiv_init
[i
] = insn
;
741 /* If this insn is setting a MEM from a register equivalent to it,
742 this is the equivalencing insn. */
743 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
744 && GET_CODE (SET_SRC (set
)) == REG
745 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
746 && rtx_equal_p (SET_DEST (set
),
747 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
748 reg_equiv_init
[REGNO (SET_SRC (set
))] = insn
;
750 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
751 scan_paradoxical_subregs (PATTERN (insn
));
754 /* Does this function require a frame pointer? */
756 frame_pointer_needed
= (! flag_omit_frame_pointer
757 #ifdef EXIT_IGNORE_STACK
758 /* ?? If EXIT_IGNORE_STACK is set, we will not save
759 and restore sp for alloca. So we can't eliminate
760 the frame pointer in that case. At some point,
761 we should improve this by emitting the
762 sp-adjusting insns for this case. */
763 || (current_function_calls_alloca
764 && EXIT_IGNORE_STACK
)
766 || FRAME_POINTER_REQUIRED
);
770 /* Initialize the table of registers to eliminate. The way we do this
771 depends on how the eliminable registers were defined. */
772 #ifdef ELIMINABLE_REGS
773 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
775 ep
->can_eliminate
= ep
->can_eliminate_previous
776 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
777 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
780 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
781 = ! frame_pointer_needed
;
784 /* Count the number of eliminable registers and build the FROM and TO
785 REG rtx's. Note that code in gen_rtx will cause, e.g.,
786 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
787 We depend on this. */
788 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
790 num_eliminable
+= ep
->can_eliminate
;
791 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
792 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
795 num_labels
= max_label_num () - get_first_label_num ();
797 /* Allocate the tables used to store offset information at labels. */
798 /* We used to use alloca here, but the size of what it would try to
799 allocate would occasionally cause it to exceed the stack limit and
800 cause a core dump. */
801 real_known_ptr
= xmalloc (num_labels
);
803 = (int (*)[NUM_ELIMINABLE_REGS
])
804 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
806 offsets_known_at
= real_known_ptr
- get_first_label_num ();
808 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
810 /* Alter each pseudo-reg rtx to contain its hard reg number.
811 Assign stack slots to the pseudos that lack hard regs or equivalents.
812 Do not touch virtual registers. */
814 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
817 /* If we have some registers we think can be eliminated, scan all insns to
818 see if there is an insn that sets one of these registers to something
819 other than itself plus a constant. If so, the register cannot be
820 eliminated. Doing this scan here eliminates an extra pass through the
821 main reload loop in the most common case where register elimination
823 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
824 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
825 || GET_CODE (insn
) == CALL_INSN
)
826 note_stores (PATTERN (insn
), mark_not_eliminable
);
828 #ifndef REGISTER_CONSTRAINTS
829 /* If all the pseudo regs have hard regs,
830 except for those that are never referenced,
831 we know that no reloads are needed. */
832 /* But that is not true if there are register constraints, since
833 in that case some pseudos might be in the wrong kind of hard reg. */
835 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
836 if (reg_renumber
[i
] == -1 && REG_N_REFS (i
) != 0)
839 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
841 free (real_known_ptr
);
843 free (reg_equiv_constant
);
844 free (reg_equiv_memory_loc
);
845 free (reg_equiv_mem
);
846 free (reg_equiv_init
);
847 free (reg_equiv_address
);
848 free (reg_max_ref_width
);
853 /* Compute the order of preference for hard registers to spill.
854 Store them by decreasing preference in potential_reload_regs. */
856 order_regs_for_reload (global
);
858 /* So far, no hard regs have been spilled. */
860 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
861 spill_reg_order
[i
] = -1;
863 /* Initialize to -1, which means take the first spill register. */
866 /* On most machines, we can't use any register explicitly used in the
867 rtl as a spill register. But on some, we have to. Those will have
868 taken care to keep the life of hard regs as short as possible. */
870 if (! SMALL_REGISTER_CLASSES
)
871 COPY_HARD_REG_SET (forbidden_regs
, bad_spill_regs
);
873 /* Spill any hard regs that we know we can't eliminate. */
874 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
875 if (! ep
->can_eliminate
)
876 spill_hard_reg (ep
->from
, global
, dumpfile
, 1);
878 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
879 if (frame_pointer_needed
)
880 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, global
, dumpfile
, 1);
884 for (i
= 0; i
< N_REG_CLASSES
; i
++)
886 basic_block_needs
[i
] = (char *) alloca (n_basic_blocks
);
887 bzero (basic_block_needs
[i
], n_basic_blocks
);
890 /* From now on, we need to emit any moves without making new pseudos. */
891 reload_in_progress
= 1;
893 /* This loop scans the entire function each go-round
894 and repeats until one repetition spills no additional hard regs. */
896 /* This flag is set when a pseudo reg is spilled,
897 to require another pass. Note that getting an additional reload
898 reg does not necessarily imply any pseudo reg was spilled;
899 sometimes we find a reload reg that no pseudo reg was allocated in. */
900 something_changed
= 1;
901 /* This flag is set if there are any insns that require reloading. */
902 something_needs_reloads
= 0;
903 /* This flag is set if there are any insns that require register
905 something_needs_elimination
= 0;
906 while (something_changed
)
909 HOST_WIDE_INT starting_frame_size
;
910 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
911 int previous_frame_pointer_needed
= frame_pointer_needed
;
913 static char *reg_class_names
[] = REG_CLASS_NAMES
;
915 something_changed
= 0;
916 bzero ((char *) max_needs
, sizeof max_needs
);
917 bzero ((char *) max_groups
, sizeof max_groups
);
918 bzero ((char *) max_nongroups
, sizeof max_nongroups
);
919 bzero ((char *) max_needs_insn
, sizeof max_needs_insn
);
920 bzero ((char *) max_groups_insn
, sizeof max_groups_insn
);
921 bzero ((char *) max_nongroups_insn
, sizeof max_nongroups_insn
);
922 bzero ((char *) group_size
, sizeof group_size
);
923 for (i
= 0; i
< N_REG_CLASSES
; i
++)
924 group_mode
[i
] = VOIDmode
;
926 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
927 here because the stack size may be a part of the offset computation
928 for register elimination, and there might have been new stack slots
929 created in the last iteration of this loop. */
930 assign_stack_local (BLKmode
, 0, 0);
932 starting_frame_size
= get_frame_size ();
934 /* Reset all offsets on eliminable registers to their initial values. */
935 #ifdef ELIMINABLE_REGS
936 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
938 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
939 ep
->previous_offset
= ep
->offset
940 = ep
->max_offset
= ep
->initial_offset
;
943 #ifdef INITIAL_FRAME_POINTER_OFFSET
944 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
946 if (!FRAME_POINTER_REQUIRED
)
948 reg_eliminate
[0].initial_offset
= 0;
950 reg_eliminate
[0].previous_offset
= reg_eliminate
[0].max_offset
951 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
954 num_not_at_initial_offset
= 0;
956 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
958 /* Set a known offset for each forced label to be at the initial offset
959 of each elimination. We do this because we assume that all
960 computed jumps occur from a location where each elimination is
961 at its initial offset. */
963 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
965 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
967 /* For each pseudo register that has an equivalent location defined,
968 try to eliminate any eliminable registers (such as the frame pointer)
969 assuming initial offsets for the replacement register, which
972 If the resulting location is directly addressable, substitute
973 the MEM we just got directly for the old REG.
975 If it is not addressable but is a constant or the sum of a hard reg
976 and constant, it is probably not addressable because the constant is
977 out of range, in that case record the address; we will generate
978 hairy code to compute the address in a register each time it is
979 needed. Similarly if it is a hard register, but one that is not
980 valid as an address register.
982 If the location is not addressable, but does not have one of the
983 above forms, assign a stack slot. We have to do this to avoid the
984 potential of producing lots of reloads if, e.g., a location involves
985 a pseudo that didn't get a hard register and has an equivalent memory
986 location that also involves a pseudo that didn't get a hard register.
988 Perhaps at some point we will improve reload_when_needed handling
989 so this problem goes away. But that's very hairy. */
991 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
992 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
994 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
996 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
998 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
999 else if (CONSTANT_P (XEXP (x
, 0))
1000 || (GET_CODE (XEXP (x
, 0)) == REG
1001 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
1002 || (GET_CODE (XEXP (x
, 0)) == PLUS
1003 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1004 && (REGNO (XEXP (XEXP (x
, 0), 0))
1005 < FIRST_PSEUDO_REGISTER
)
1006 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
1007 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
1010 /* Make a new stack slot. Then indicate that something
1011 changed so we go back and recompute offsets for
1012 eliminable registers because the allocation of memory
1013 below might change some offset. reg_equiv_{mem,address}
1014 will be set up for this pseudo on the next pass around
1016 reg_equiv_memory_loc
[i
] = 0;
1017 reg_equiv_init
[i
] = 0;
1019 something_changed
= 1;
1023 /* If we allocated another pseudo to the stack, redo elimination
1025 if (something_changed
)
1028 /* If caller-saves needs a group, initialize the group to include
1029 the size and mode required for caller-saves. */
1031 if (caller_save_group_size
> 1)
1033 group_mode
[(int) caller_save_spill_class
] = Pmode
;
1034 group_size
[(int) caller_save_spill_class
] = caller_save_group_size
;
1037 something_changed
|= calculate_needs_all_insns (first
, global
);
1039 /* If we allocated any new memory locations, make another pass
1040 since it might have changed elimination offsets. */
1041 if (starting_frame_size
!= get_frame_size ())
1042 something_changed
= 1;
1045 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1047 if (max_needs
[i
] > 0)
1049 ";; Need %d reg%s of class %s (for insn %d).\n",
1050 max_needs
[i
], max_needs
[i
] == 1 ? "" : "s",
1051 reg_class_names
[i
], INSN_UID (max_needs_insn
[i
]));
1052 if (max_nongroups
[i
] > 0)
1054 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1055 max_nongroups
[i
], max_nongroups
[i
] == 1 ? "" : "s",
1056 reg_class_names
[i
], INSN_UID (max_nongroups_insn
[i
]));
1057 if (max_groups
[i
] > 0)
1059 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1060 max_groups
[i
], max_groups
[i
] == 1 ? "" : "s",
1061 mode_name
[(int) group_mode
[i
]],
1062 reg_class_names
[i
], INSN_UID (max_groups_insn
[i
]));
1065 /* If we have caller-saves, set up the save areas and see if caller-save
1066 will need a spill register. */
1068 if (caller_save_needed
)
1070 /* Set the offsets for setup_save_areas. */
1071 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
1073 ep
->previous_offset
= ep
->max_offset
;
1075 if ( ! setup_save_areas (&something_changed
)
1076 && caller_save_spill_class
== NO_REGS
)
1078 /* The class we will need depends on whether the machine
1079 supports the sum of two registers for an address; see
1080 find_address_reloads for details. */
1082 caller_save_spill_class
1083 = double_reg_address_ok
? INDEX_REG_CLASS
: BASE_REG_CLASS
;
1084 caller_save_group_size
1085 = CLASS_MAX_NREGS (caller_save_spill_class
, Pmode
);
1086 something_changed
= 1;
1090 /* See if anything that happened changes which eliminations are valid.
1091 For example, on the Sparc, whether or not the frame pointer can
1092 be eliminated can depend on what registers have been used. We need
1093 not check some conditions again (such as flag_omit_frame_pointer)
1094 since they can't have changed. */
1096 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1097 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
1098 #ifdef ELIMINABLE_REGS
1099 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
1102 ep
->can_eliminate
= 0;
1104 /* Look for the case where we have discovered that we can't replace
1105 register A with register B and that means that we will now be
1106 trying to replace register A with register C. This means we can
1107 no longer replace register C with register B and we need to disable
1108 such an elimination, if it exists. This occurs often with A == ap,
1109 B == sp, and C == fp. */
1111 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1113 struct elim_table
*op
;
1114 register int new_to
= -1;
1116 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
1118 /* Find the current elimination for ep->from, if there is a
1120 for (op
= reg_eliminate
;
1121 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
1122 if (op
->from
== ep
->from
&& op
->can_eliminate
)
1128 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1130 for (op
= reg_eliminate
;
1131 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
1132 if (op
->from
== new_to
&& op
->to
== ep
->to
)
1133 op
->can_eliminate
= 0;
1137 /* See if any registers that we thought we could eliminate the previous
1138 time are no longer eliminable. If so, something has changed and we
1139 must spill the register. Also, recompute the number of eliminable
1140 registers and see if the frame pointer is needed; it is if there is
1141 no elimination of the frame pointer that we can perform. */
1143 frame_pointer_needed
= 1;
1144 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1146 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
1147 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
1148 frame_pointer_needed
= 0;
1150 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
1152 ep
->can_eliminate_previous
= 0;
1153 spill_hard_reg (ep
->from
, global
, dumpfile
, 1);
1154 something_changed
= 1;
1159 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1160 /* If we didn't need a frame pointer last time, but we do now, spill
1161 the hard frame pointer. */
1162 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
1164 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, global
, dumpfile
, 1);
1165 something_changed
= 1;
1169 /* If all needs are met, we win. */
1171 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1172 if (max_needs
[i
] > 0 || max_groups
[i
] > 0 || max_nongroups
[i
] > 0)
1174 if (i
== N_REG_CLASSES
&& ! something_changed
)
1177 /* Not all needs are met; must spill some hard regs. */
1179 /* Put all registers spilled so far back in potential_reload_regs, but
1180 put them at the front, since we've already spilled most of the
1181 pseudos in them (we might have left some pseudos unspilled if they
1182 were in a block that didn't need any spill registers of a conflicting
1183 class. We used to try to mark off the need for those registers,
1184 but doing so properly is very complex and reallocating them is the
1185 simpler approach. First, "pack" potential_reload_regs by pushing
1186 any nonnegative entries towards the end. That will leave room
1187 for the registers we already spilled.
1189 Also, undo the marking of the spill registers from the last time
1190 around in FORBIDDEN_REGS since we will be probably be allocating
1193 ??? It is theoretically possible that we might end up not using one
1194 of our previously-spilled registers in this allocation, even though
1195 they are at the head of the list. It's not clear what to do about
1196 this, but it was no better before, when we marked off the needs met
1197 by the previously-spilled registers. With the current code, globals
1198 can be allocated into these registers, but locals cannot. */
1202 for (i
= j
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1203 if (potential_reload_regs
[i
] != -1)
1204 potential_reload_regs
[j
--] = potential_reload_regs
[i
];
1206 for (i
= 0; i
< n_spills
; i
++)
1208 potential_reload_regs
[i
] = spill_regs
[i
];
1209 spill_reg_order
[spill_regs
[i
]] = -1;
1210 CLEAR_HARD_REG_BIT (forbidden_regs
, spill_regs
[i
]);
1216 something_changed
|= find_reload_regs (global
, dumpfile
);
1221 /* If global-alloc was run, notify it of any register eliminations we have
1224 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1225 if (ep
->can_eliminate
)
1226 mark_elimination (ep
->from
, ep
->to
);
1228 /* Insert code to save and restore call-clobbered hard regs
1229 around calls. Tell if what mode to use so that we will process
1230 those insns in reload_as_needed if we have to. */
1232 if (caller_save_needed
)
1233 save_call_clobbered_regs (num_eliminable
? QImode
1234 : caller_save_spill_class
!= NO_REGS
? HImode
1237 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1238 If that insn didn't set the register (i.e., it copied the register to
1239 memory), just delete that insn instead of the equivalencing insn plus
1240 anything now dead. If we call delete_dead_insn on that insn, we may
1241 delete the insn that actually sets the register if the register die
1242 there and that is incorrect. */
1244 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1245 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0
1246 && GET_CODE (reg_equiv_init
[i
]) != NOTE
)
1248 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (reg_equiv_init
[i
])))
1249 delete_dead_insn (reg_equiv_init
[i
]);
1252 PUT_CODE (reg_equiv_init
[i
], NOTE
);
1253 NOTE_SOURCE_FILE (reg_equiv_init
[i
]) = 0;
1254 NOTE_LINE_NUMBER (reg_equiv_init
[i
]) = NOTE_INSN_DELETED
;
1258 /* Use the reload registers where necessary
1259 by generating move instructions to move the must-be-register
1260 values into or out of the reload registers. */
1262 if (something_needs_reloads
|| something_needs_elimination
1263 || (caller_save_needed
&& num_eliminable
)
1264 || caller_save_spill_class
!= NO_REGS
)
1265 reload_as_needed (first
, global
);
1267 /* If we were able to eliminate the frame pointer, show that it is no
1268 longer live at the start of any basic block. If it ls live by
1269 virtue of being in a pseudo, that pseudo will be marked live
1270 and hence the frame pointer will be known to be live via that
1273 if (! frame_pointer_needed
)
1274 for (i
= 0; i
< n_basic_blocks
; i
++)
1275 CLEAR_REGNO_REG_SET (basic_block_live_at_start
[i
],
1276 HARD_FRAME_POINTER_REGNUM
);
1278 /* Come here (with failure set nonzero) if we can't get enough spill regs
1279 and we decide not to abort about it. */
1282 reload_in_progress
= 0;
1284 /* Now eliminate all pseudo regs by modifying them into
1285 their equivalent memory references.
1286 The REG-rtx's for the pseudos are modified in place,
1287 so all insns that used to refer to them now refer to memory.
1289 For a reg that has a reg_equiv_address, all those insns
1290 were changed by reloading so that no insns refer to it any longer;
1291 but the DECL_RTL of a variable decl may refer to it,
1292 and if so this causes the debugging info to mention the variable. */
1294 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1298 int is_readonly
= 0;
1300 if (reg_equiv_memory_loc
[i
])
1302 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1303 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1306 if (reg_equiv_mem
[i
])
1307 addr
= XEXP (reg_equiv_mem
[i
], 0);
1309 if (reg_equiv_address
[i
])
1310 addr
= reg_equiv_address
[i
];
1314 if (reg_renumber
[i
] < 0)
1316 rtx reg
= regno_reg_rtx
[i
];
1317 XEXP (reg
, 0) = addr
;
1318 REG_USERVAR_P (reg
) = 0;
1319 RTX_UNCHANGING_P (reg
) = is_readonly
;
1320 MEM_IN_STRUCT_P (reg
) = in_struct
;
1321 /* We have no alias information about this newly created
1323 MEM_ALIAS_SET (reg
) = 0;
1324 PUT_CODE (reg
, MEM
);
1326 else if (reg_equiv_mem
[i
])
1327 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1331 /* Make a pass over all the insns and delete all USEs which we inserted
1332 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P
1333 is defined, also remove death notes for things that are no longer
1334 registers or no longer die in the insn (e.g., an input and output
1335 pseudo being tied). */
1337 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1338 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1340 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1344 if (GET_CODE (PATTERN (insn
)) == USE
1345 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1347 PUT_CODE (insn
, NOTE
);
1348 NOTE_SOURCE_FILE (insn
) = 0;
1349 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1352 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1353 for (note
= REG_NOTES (insn
); note
; note
= next
)
1355 next
= XEXP (note
, 1);
1356 if (REG_NOTE_KIND (note
) == REG_DEAD
1357 && (GET_CODE (XEXP (note
, 0)) != REG
1358 || reg_set_p (XEXP (note
, 0), PATTERN (insn
))))
1359 remove_note (insn
, note
);
1364 /* If we are doing stack checking, give a warning if this function's
1365 frame size is larger than we expect. */
1366 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1368 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1370 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1371 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1372 size
+= UNITS_PER_WORD
;
1374 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1375 warning ("frame size too large for reliable stack checking");
1378 /* Indicate that we no longer have known memory locations or constants. */
1379 reg_equiv_constant
= 0;
1380 reg_equiv_memory_loc
= 0;
1383 free (real_known_ptr
);
1388 free (scratch_list
);
1391 free (scratch_block
);
1394 free (reg_equiv_constant
);
1395 free (reg_equiv_memory_loc
);
1396 free (reg_equiv_mem
);
1397 free (reg_equiv_init
);
1398 free (reg_equiv_address
);
1399 free (reg_max_ref_width
);
1401 CLEAR_HARD_REG_SET (used_spill_regs
);
1402 for (i
= 0; i
< n_spills
; i
++)
1403 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1408 /* Walk the insns of the current function, starting with FIRST, and collect
1409 information about the need to do register elimination and the need to
1412 calculate_needs_all_insns (first
, global
)
1417 int something_changed
= 0;
1419 /* Keep track of which basic blocks are needing the reloads. */
1422 /* Compute the most additional registers needed by any instruction.
1423 Collect information separately for each class of regs. */
1425 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1427 if (global
&& this_block
+ 1 < n_basic_blocks
1428 && insn
== basic_block_head
[this_block
+1])
1431 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1432 might include REG_LABEL), we need to see what effects this
1433 has on the known offsets at labels. */
1435 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1436 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1437 && REG_NOTES (insn
) != 0))
1438 set_label_offsets (insn
, insn
, 0);
1440 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1442 rtx old_body
= PATTERN (insn
);
1443 int old_code
= INSN_CODE (insn
);
1444 rtx old_notes
= REG_NOTES (insn
);
1445 int did_elimination
= 0;
1447 /* Nonzero means don't use a reload reg that overlaps
1448 the place where a function value can be returned. */
1449 rtx avoid_return_reg
= 0;
1451 /* Set avoid_return_reg if this is an insn
1452 that might use the value of a function call. */
1453 if (SMALL_REGISTER_CLASSES
&& GET_CODE (insn
) == CALL_INSN
)
1455 if (GET_CODE (PATTERN (insn
)) == SET
)
1456 after_call
= SET_DEST (PATTERN (insn
));
1457 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1458 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1459 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
1463 else if (SMALL_REGISTER_CLASSES
&& after_call
!= 0
1464 && !(GET_CODE (PATTERN (insn
)) == SET
1465 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
)
1466 && GET_CODE (PATTERN (insn
)) != USE
)
1468 if (reg_referenced_p (after_call
, PATTERN (insn
)))
1469 avoid_return_reg
= after_call
;
1473 /* If needed, eliminate any eliminable registers. */
1475 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1477 /* Analyze the instruction. */
1478 find_reloads (insn
, 0, spill_indirect_levels
, global
,
1481 /* Remember for later shortcuts which insns had any reloads or
1482 register eliminations.
1484 One might think that it would be worthwhile to mark insns
1485 that need register replacements but not reloads, but this is
1486 not safe because find_reloads may do some manipulation of
1487 the insn (such as swapping commutative operands), which would
1488 be lost when we restore the old pattern after register
1489 replacement. So the actions of find_reloads must be redone in
1490 subsequent passes or in reload_as_needed.
1492 However, it is safe to mark insns that need reloads
1493 but not register replacement. */
1495 PUT_MODE (insn
, (did_elimination
? QImode
1496 : n_reloads
? HImode
1497 : GET_MODE (insn
) == DImode
? DImode
1500 /* Discard any register replacements done. */
1501 if (did_elimination
)
1503 obstack_free (&reload_obstack
, reload_firstobj
);
1504 PATTERN (insn
) = old_body
;
1505 INSN_CODE (insn
) = old_code
;
1506 REG_NOTES (insn
) = old_notes
;
1507 something_needs_elimination
= 1;
1510 /* If this insn has no reloads, we need not do anything except
1511 in the case of a CALL_INSN when we have caller-saves and
1512 caller-save needs reloads. */
1515 || (GET_CODE (insn
) == CALL_INSN
1516 && caller_save_spill_class
!= NO_REGS
))
1517 something_changed
|= calculate_needs (this_block
, insn
,
1518 avoid_return_reg
, global
);
1521 /* Note that there is a continue statement above. */
1523 return something_changed
;
1526 /* To compute the number of reload registers of each class
1527 needed for an insn, we must simulate what choose_reload_regs
1528 can do. We do this by splitting an insn into an "input" and
1529 an "output" part. RELOAD_OTHER reloads are used in both.
1530 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1531 which must be live over the entire input section of reloads,
1532 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1533 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1536 The registers needed for output are RELOAD_OTHER and
1537 RELOAD_FOR_OUTPUT, which are live for the entire output
1538 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1539 reloads for each operand.
1541 The total number of registers needed is the maximum of the
1542 inputs and outputs. */
1545 calculate_needs (this_block
, insn
, avoid_return_reg
, global
)
1547 rtx insn
, avoid_return_reg
;
1550 int something_changed
= 0;
1555 /* [0] is normal, [1] is nongroup. */
1556 int regs
[2][N_REG_CLASSES
];
1557 int groups
[N_REG_CLASSES
];
1560 /* Each `struct needs' corresponds to one RELOAD_... type. */
1564 struct needs output
;
1566 struct needs other_addr
;
1567 struct needs op_addr
;
1568 struct needs op_addr_reload
;
1569 struct needs in_addr
[MAX_RECOG_OPERANDS
];
1570 struct needs in_addr_addr
[MAX_RECOG_OPERANDS
];
1571 struct needs out_addr
[MAX_RECOG_OPERANDS
];
1572 struct needs out_addr_addr
[MAX_RECOG_OPERANDS
];
1575 something_needs_reloads
= 1;
1576 bzero ((char *) &insn_needs
, sizeof insn_needs
);
1578 /* Count each reload once in every class
1579 containing the reload's own class. */
1581 for (i
= 0; i
< n_reloads
; i
++)
1583 register enum reg_class
*p
;
1584 enum reg_class
class = reload_reg_class
[i
];
1586 enum machine_mode mode
;
1587 struct needs
*this_needs
;
1589 /* Don't count the dummy reloads, for which one of the
1590 regs mentioned in the insn can be used for reloading.
1591 Don't count optional reloads.
1592 Don't count reloads that got combined with others. */
1593 if (reload_reg_rtx
[i
] != 0
1594 || reload_optional
[i
] != 0
1595 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1596 && ! reload_secondary_p
[i
]))
1599 /* Show that a reload register of this class is needed
1600 in this basic block. We do not use insn_needs and
1601 insn_groups because they are overly conservative for
1603 if (global
&& ! basic_block_needs
[(int) class][this_block
])
1605 basic_block_needs
[(int) class][this_block
] = 1;
1606 something_changed
= 1;
1609 mode
= reload_inmode
[i
];
1610 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1611 mode
= reload_outmode
[i
];
1612 size
= CLASS_MAX_NREGS (class, mode
);
1614 /* Decide which time-of-use to count this reload for. */
1615 switch (reload_when_needed
[i
])
1618 this_needs
= &insn_needs
.other
;
1620 case RELOAD_FOR_INPUT
:
1621 this_needs
= &insn_needs
.input
;
1623 case RELOAD_FOR_OUTPUT
:
1624 this_needs
= &insn_needs
.output
;
1626 case RELOAD_FOR_INSN
:
1627 this_needs
= &insn_needs
.insn
;
1629 case RELOAD_FOR_OTHER_ADDRESS
:
1630 this_needs
= &insn_needs
.other_addr
;
1632 case RELOAD_FOR_INPUT_ADDRESS
:
1633 this_needs
= &insn_needs
.in_addr
[reload_opnum
[i
]];
1635 case RELOAD_FOR_INPADDR_ADDRESS
:
1636 this_needs
= &insn_needs
.in_addr_addr
[reload_opnum
[i
]];
1638 case RELOAD_FOR_OUTPUT_ADDRESS
:
1639 this_needs
= &insn_needs
.out_addr
[reload_opnum
[i
]];
1641 case RELOAD_FOR_OUTADDR_ADDRESS
:
1642 this_needs
= &insn_needs
.out_addr_addr
[reload_opnum
[i
]];
1644 case RELOAD_FOR_OPERAND_ADDRESS
:
1645 this_needs
= &insn_needs
.op_addr
;
1647 case RELOAD_FOR_OPADDR_ADDR
:
1648 this_needs
= &insn_needs
.op_addr_reload
;
1654 enum machine_mode other_mode
, allocate_mode
;
1656 /* Count number of groups needed separately from
1657 number of individual regs needed. */
1658 this_needs
->groups
[(int) class]++;
1659 p
= reg_class_superclasses
[(int) class];
1660 while (*p
!= LIM_REG_CLASSES
)
1661 this_needs
->groups
[(int) *p
++]++;
1663 /* Record size and mode of a group of this class. */
1664 /* If more than one size group is needed,
1665 make all groups the largest needed size. */
1666 if (group_size
[(int) class] < size
)
1668 other_mode
= group_mode
[(int) class];
1669 allocate_mode
= mode
;
1671 group_size
[(int) class] = size
;
1672 group_mode
[(int) class] = mode
;
1677 allocate_mode
= group_mode
[(int) class];
1680 /* Crash if two dissimilar machine modes both need
1681 groups of consecutive regs of the same class. */
1683 if (other_mode
!= VOIDmode
&& other_mode
!= allocate_mode
1684 && ! modes_equiv_for_class_p (allocate_mode
,
1686 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1691 this_needs
->regs
[reload_nongroup
[i
]][(int) class] += 1;
1692 p
= reg_class_superclasses
[(int) class];
1693 while (*p
!= LIM_REG_CLASSES
)
1694 this_needs
->regs
[reload_nongroup
[i
]][(int) *p
++] += 1;
1700 /* All reloads have been counted for this insn;
1701 now merge the various times of use.
1702 This sets insn_needs, etc., to the maximum total number
1703 of registers needed at any point in this insn. */
1705 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1707 int j
, in_max
, out_max
;
1709 /* Compute normal and nongroup needs. */
1710 for (j
= 0; j
<= 1; j
++)
1713 for (in_max
= 0, out_max
= 0, k
= 0; k
< reload_n_operands
; k
++)
1715 in_max
= MAX (in_max
,
1716 (insn_needs
.in_addr
[k
].regs
[j
][i
]
1717 + insn_needs
.in_addr_addr
[k
].regs
[j
][i
]));
1718 out_max
= MAX (out_max
, insn_needs
.out_addr
[k
].regs
[j
][i
]);
1719 out_max
= MAX (out_max
,
1720 insn_needs
.out_addr_addr
[k
].regs
[j
][i
]);
1723 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1724 and operand addresses but not things used to reload
1725 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1726 don't conflict with things needed to reload inputs or
1729 in_max
= MAX (MAX (insn_needs
.op_addr
.regs
[j
][i
],
1730 insn_needs
.op_addr_reload
.regs
[j
][i
]),
1733 out_max
= MAX (out_max
, insn_needs
.insn
.regs
[j
][i
]);
1735 insn_needs
.input
.regs
[j
][i
]
1736 = MAX (insn_needs
.input
.regs
[j
][i
]
1737 + insn_needs
.op_addr
.regs
[j
][i
]
1738 + insn_needs
.insn
.regs
[j
][i
],
1739 in_max
+ insn_needs
.input
.regs
[j
][i
]);
1741 insn_needs
.output
.regs
[j
][i
] += out_max
;
1742 insn_needs
.other
.regs
[j
][i
]
1743 += MAX (MAX (insn_needs
.input
.regs
[j
][i
],
1744 insn_needs
.output
.regs
[j
][i
]),
1745 insn_needs
.other_addr
.regs
[j
][i
]);
1749 /* Now compute group needs. */
1750 for (in_max
= 0, out_max
= 0, j
= 0; j
< reload_n_operands
; j
++)
1752 in_max
= MAX (in_max
, insn_needs
.in_addr
[j
].groups
[i
]);
1753 in_max
= MAX (in_max
, insn_needs
.in_addr_addr
[j
].groups
[i
]);
1754 out_max
= MAX (out_max
, insn_needs
.out_addr
[j
].groups
[i
]);
1755 out_max
= MAX (out_max
, insn_needs
.out_addr_addr
[j
].groups
[i
]);
1758 in_max
= MAX (MAX (insn_needs
.op_addr
.groups
[i
],
1759 insn_needs
.op_addr_reload
.groups
[i
]),
1761 out_max
= MAX (out_max
, insn_needs
.insn
.groups
[i
]);
1763 insn_needs
.input
.groups
[i
]
1764 = MAX (insn_needs
.input
.groups
[i
]
1765 + insn_needs
.op_addr
.groups
[i
]
1766 + insn_needs
.insn
.groups
[i
],
1767 in_max
+ insn_needs
.input
.groups
[i
]);
1769 insn_needs
.output
.groups
[i
] += out_max
;
1770 insn_needs
.other
.groups
[i
]
1771 += MAX (MAX (insn_needs
.input
.groups
[i
],
1772 insn_needs
.output
.groups
[i
]),
1773 insn_needs
.other_addr
.groups
[i
]);
1776 /* If this is a CALL_INSN and caller-saves will need
1777 a spill register, act as if the spill register is
1778 needed for this insn. However, the spill register
1779 can be used by any reload of this insn, so we only
1780 need do something if no need for that class has
1783 The assumption that every CALL_INSN will trigger a
1784 caller-save is highly conservative, however, the number
1785 of cases where caller-saves will need a spill register but
1786 a block containing a CALL_INSN won't need a spill register
1787 of that class should be quite rare.
1789 If a group is needed, the size and mode of the group will
1790 have been set up at the beginning of this loop. */
1792 if (GET_CODE (insn
) == CALL_INSN
1793 && caller_save_spill_class
!= NO_REGS
)
1796 /* See if this register would conflict with any reload that
1797 needs a group or any reload that needs a nongroup. */
1798 int nongroup_need
= 0;
1799 int *caller_save_needs
;
1801 for (j
= 0; j
< n_reloads
; j
++)
1802 if (reg_classes_intersect_p (caller_save_spill_class
,
1803 reload_reg_class
[j
])
1804 && ((CLASS_MAX_NREGS
1805 (reload_reg_class
[j
],
1806 (GET_MODE_SIZE (reload_outmode
[j
])
1807 > GET_MODE_SIZE (reload_inmode
[j
]))
1808 ? reload_outmode
[j
] : reload_inmode
[j
])
1810 || reload_nongroup
[j
]))
1817 = (caller_save_group_size
> 1
1818 ? insn_needs
.other
.groups
1819 : insn_needs
.other
.regs
[nongroup_need
]);
1821 if (caller_save_needs
[(int) caller_save_spill_class
] == 0)
1823 register enum reg_class
*p
1824 = reg_class_superclasses
[(int) caller_save_spill_class
];
1826 caller_save_needs
[(int) caller_save_spill_class
]++;
1828 while (*p
!= LIM_REG_CLASSES
)
1829 caller_save_needs
[(int) *p
++] += 1;
1832 /* Show that this basic block will need a register of
1836 && ! (basic_block_needs
[(int) caller_save_spill_class
]
1839 basic_block_needs
[(int) caller_save_spill_class
]
1841 something_changed
= 1;
1845 /* If this insn stores the value of a function call,
1846 and that value is in a register that has been spilled,
1847 and if the insn needs a reload in a class
1848 that might use that register as the reload register,
1849 then add an extra need in that class.
1850 This makes sure we have a register available that does
1851 not overlap the return value. */
1853 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
1855 int regno
= REGNO (avoid_return_reg
);
1857 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
1859 int basic_needs
[N_REG_CLASSES
], basic_groups
[N_REG_CLASSES
];
1861 /* First compute the "basic needs", which counts a
1862 need only in the smallest class in which it
1865 bcopy ((char *) insn_needs
.other
.regs
[0],
1866 (char *) basic_needs
, sizeof basic_needs
);
1867 bcopy ((char *) insn_needs
.other
.groups
,
1868 (char *) basic_groups
, sizeof basic_groups
);
1870 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1874 if (basic_needs
[i
] >= 0)
1875 for (p
= reg_class_superclasses
[i
];
1876 *p
!= LIM_REG_CLASSES
; p
++)
1877 basic_needs
[(int) *p
] -= basic_needs
[i
];
1879 if (basic_groups
[i
] >= 0)
1880 for (p
= reg_class_superclasses
[i
];
1881 *p
!= LIM_REG_CLASSES
; p
++)
1882 basic_groups
[(int) *p
] -= basic_groups
[i
];
1885 /* Now count extra regs if there might be a conflict with
1886 the return value register. */
1888 for (r
= regno
; r
< regno
+ nregs
; r
++)
1889 if (spill_reg_order
[r
] >= 0)
1890 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1891 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], r
))
1893 if (basic_needs
[i
] > 0)
1897 insn_needs
.other
.regs
[0][i
]++;
1898 p
= reg_class_superclasses
[i
];
1899 while (*p
!= LIM_REG_CLASSES
)
1900 insn_needs
.other
.regs
[0][(int) *p
++]++;
1902 if (basic_groups
[i
] > 0)
1906 insn_needs
.other
.groups
[i
]++;
1907 p
= reg_class_superclasses
[i
];
1908 while (*p
!= LIM_REG_CLASSES
)
1909 insn_needs
.other
.groups
[(int) *p
++]++;
1914 /* For each class, collect maximum need of any insn. */
1916 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1918 if (max_needs
[i
] < insn_needs
.other
.regs
[0][i
])
1920 max_needs
[i
] = insn_needs
.other
.regs
[0][i
];
1921 max_needs_insn
[i
] = insn
;
1923 if (max_groups
[i
] < insn_needs
.other
.groups
[i
])
1925 max_groups
[i
] = insn_needs
.other
.groups
[i
];
1926 max_groups_insn
[i
] = insn
;
1928 if (max_nongroups
[i
] < insn_needs
.other
.regs
[1][i
])
1930 max_nongroups
[i
] = insn_needs
.other
.regs
[1][i
];
1931 max_nongroups_insn
[i
] = insn
;
1934 return something_changed
;
1937 /* Find a group of exactly 2 registers.
1939 First try to fill out the group by spilling a single register which
1940 would allow completion of the group.
1942 Then try to create a new group from a pair of registers, neither of
1943 which are explicitly used.
1945 Then try to create a group from any pair of registers. */
1947 find_tworeg_group (global
, class, dumpfile
)
1953 /* First, look for a register that will complete a group. */
1954 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1958 j
= potential_reload_regs
[i
];
1959 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1960 && ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1961 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1962 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1963 && HARD_REGNO_MODE_OK (other
, group_mode
[class])
1964 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, other
)
1965 /* We don't want one part of another group.
1966 We could get "two groups" that overlap! */
1967 && ! TEST_HARD_REG_BIT (counted_for_groups
, other
))
1968 || (j
< FIRST_PSEUDO_REGISTER
- 1
1969 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1970 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1971 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1972 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1973 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, other
)
1974 && ! TEST_HARD_REG_BIT (counted_for_groups
, other
))))
1976 register enum reg_class
*p
;
1978 /* We have found one that will complete a group,
1979 so count off one group as provided. */
1980 max_groups
[class]--;
1981 p
= reg_class_superclasses
[class];
1982 while (*p
!= LIM_REG_CLASSES
)
1984 if (group_size
[(int) *p
] <= group_size
[class])
1985 max_groups
[(int) *p
]--;
1989 /* Indicate both these regs are part of a group. */
1990 SET_HARD_REG_BIT (counted_for_groups
, j
);
1991 SET_HARD_REG_BIT (counted_for_groups
, other
);
1995 /* We can't complete a group, so start one. */
1996 /* Look for a pair neither of which is explicitly used. */
1997 if (SMALL_REGISTER_CLASSES
&& i
== FIRST_PSEUDO_REGISTER
)
1998 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2001 j
= potential_reload_regs
[i
];
2002 /* Verify that J+1 is a potential reload reg. */
2003 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
2004 if (potential_reload_regs
[k
] == j
+ 1)
2006 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
2007 && k
< FIRST_PSEUDO_REGISTER
2008 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
2009 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
2010 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
2011 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
2012 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
2014 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1)
2015 /* Reject J at this stage
2016 if J+1 was explicitly used. */
2017 && ! regs_explicitly_used
[j
+ 1])
2020 /* Now try any group at all
2021 whose registers are not in bad_spill_regs. */
2022 if (i
== FIRST_PSEUDO_REGISTER
)
2023 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2026 j
= potential_reload_regs
[i
];
2027 /* Verify that J+1 is a potential reload reg. */
2028 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
2029 if (potential_reload_regs
[k
] == j
+ 1)
2031 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
2032 && k
< FIRST_PSEUDO_REGISTER
2033 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
2034 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
2035 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
2036 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
2037 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, j
+ 1)
2038 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
2042 /* I should be the index in potential_reload_regs
2043 of the new reload reg we have found. */
2045 if (i
< FIRST_PSEUDO_REGISTER
)
2046 return new_spill_reg (i
, class, max_needs
, NULL_PTR
,
2049 /* There are no groups left to spill. */
2050 spill_failure (max_groups_insn
[class]);
2055 /* Find a group of more than 2 registers.
2056 Look for a sufficient sequence of unspilled registers, and spill them all
2059 find_group (global
, class, dumpfile
)
2064 int something_changed
= 0;
2067 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2071 j
= potential_reload_regs
[i
];
2073 && j
+ group_size
[class] <= FIRST_PSEUDO_REGISTER
2074 && HARD_REGNO_MODE_OK (j
, group_mode
[class]))
2076 /* Check each reg in the sequence. */
2077 for (k
= 0; k
< group_size
[class]; k
++)
2078 if (! (spill_reg_order
[j
+ k
] < 0
2079 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
2080 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
2082 /* We got a full sequence, so spill them all. */
2083 if (k
== group_size
[class])
2085 register enum reg_class
*p
;
2086 for (k
= 0; k
< group_size
[class]; k
++)
2089 SET_HARD_REG_BIT (counted_for_groups
, j
+ k
);
2090 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
2091 if (potential_reload_regs
[idx
] == j
+ k
)
2093 something_changed
|= new_spill_reg (idx
, class, max_needs
,
2098 /* We have found one that will complete a group,
2099 so count off one group as provided. */
2100 max_groups
[class]--;
2101 p
= reg_class_superclasses
[class];
2102 while (*p
!= LIM_REG_CLASSES
)
2104 if (group_size
[(int) *p
]
2105 <= group_size
[class])
2106 max_groups
[(int) *p
]--;
2109 return something_changed
;
2113 /* There are no groups left. */
2114 spill_failure (max_groups_insn
[class]);
2119 /* Find more reload regs to satisfy the remaining need.
2120 Do it by ascending class number, since otherwise a reg
2121 might be spilled for a big class and might fail to count
2122 for a smaller class even though it belongs to that class.
2124 Count spilled regs in `spills', and add entries to
2125 `spill_regs' and `spill_reg_order'.
2127 ??? Note there is a problem here.
2128 When there is a need for a group in a high-numbered class,
2129 and also need for non-group regs that come from a lower class,
2130 the non-group regs are chosen first. If there aren't many regs,
2131 they might leave no room for a group.
2133 This was happening on the 386. To fix it, we added the code
2134 that calls possible_group_p, so that the lower class won't
2135 break up the last possible group.
2137 Really fixing the problem would require changes above
2138 in counting the regs already spilled, and in choose_reload_regs.
2139 It might be hard to avoid introducing bugs there. */
2142 find_reload_regs (global
, dumpfile
)
2147 int something_changed
= 0;
2149 CLEAR_HARD_REG_SET (counted_for_groups
);
2150 CLEAR_HARD_REG_SET (counted_for_nongroups
);
2152 for (class = 0; class < N_REG_CLASSES
; class++)
2154 /* First get the groups of registers.
2155 If we got single registers first, we might fragment
2157 while (max_groups
[class] > 0)
2159 /* If any single spilled regs happen to form groups,
2160 count them now. Maybe we don't really need
2161 to spill another group. */
2162 count_possible_groups (group_size
, group_mode
, max_groups
, class);
2164 if (max_groups
[class] <= 0)
2167 /* Groups of size 2 (the only groups used on most machines)
2168 are treated specially. */
2169 if (group_size
[class] == 2)
2170 something_changed
|= find_tworeg_group (global
, class, dumpfile
);
2172 something_changed
|= find_group (global
, class, dumpfile
);
2178 /* Now similarly satisfy all need for single registers. */
2180 while (max_needs
[class] > 0 || max_nongroups
[class] > 0)
2183 /* If we spilled enough regs, but they weren't counted
2184 against the non-group need, see if we can count them now.
2185 If so, we can avoid some actual spilling. */
2186 if (max_needs
[class] <= 0 && max_nongroups
[class] > 0)
2187 for (i
= 0; i
< n_spills
; i
++)
2189 int regno
= spill_regs
[i
];
2190 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2191 && !TEST_HARD_REG_BIT (counted_for_groups
, regno
)
2192 && !TEST_HARD_REG_BIT (counted_for_nongroups
, regno
)
2193 && max_nongroups
[class] > 0)
2195 register enum reg_class
*p
;
2197 SET_HARD_REG_BIT (counted_for_nongroups
, regno
);
2198 max_nongroups
[class]--;
2199 p
= reg_class_superclasses
[class];
2200 while (*p
!= LIM_REG_CLASSES
)
2201 max_nongroups
[(int) *p
++]--;
2204 if (max_needs
[class] <= 0 && max_nongroups
[class] <= 0)
2207 /* Consider the potential reload regs that aren't
2208 yet in use as reload regs, in order of preference.
2209 Find the most preferred one that's in this class. */
2211 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2213 int regno
= potential_reload_regs
[i
];
2215 && TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2216 /* If this reg will not be available for groups,
2217 pick one that does not foreclose possible groups.
2218 This is a kludge, and not very general,
2219 but it should be sufficient to make the 386 work,
2220 and the problem should not occur on machines with
2222 && (max_nongroups
[class] == 0
2223 || possible_group_p (regno
, max_groups
)))
2227 /* If we couldn't get a register, try to get one even if we
2228 might foreclose possible groups. This may cause problems
2229 later, but that's better than aborting now, since it is
2230 possible that we will, in fact, be able to form the needed
2231 group even with this allocation. */
2233 if (i
>= FIRST_PSEUDO_REGISTER
2234 && (asm_noperands (max_needs
[class] > 0
2235 ? max_needs_insn
[class]
2236 : max_nongroups_insn
[class])
2238 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2239 if (potential_reload_regs
[i
] >= 0
2240 && TEST_HARD_REG_BIT (reg_class_contents
[class],
2241 potential_reload_regs
[i
]))
2244 /* I should be the index in potential_reload_regs
2245 of the new reload reg we have found. */
2247 if (i
>= FIRST_PSEUDO_REGISTER
)
2249 /* There are no possible registers left to spill. */
2250 spill_failure (max_needs
[class] > 0 ? max_needs_insn
[class]
2251 : max_nongroups_insn
[class]);
2256 something_changed
|= new_spill_reg (i
, class, max_needs
,
2257 max_nongroups
, global
,
2261 return something_changed
;
2265 /* Nonzero if, after spilling reg REGNO for non-groups,
2266 it will still be possible to find a group if we still need one. */
2269 possible_group_p (regno
, max_groups
)
2274 int class = (int) NO_REGS
;
2276 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
2277 if (max_groups
[i
] > 0)
2283 if (class == (int) NO_REGS
)
2286 /* Consider each pair of consecutive registers. */
2287 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2289 /* Ignore pairs that include reg REGNO. */
2290 if (i
== regno
|| i
+ 1 == regno
)
2293 /* Ignore pairs that are outside the class that needs the group.
2294 ??? Here we fail to handle the case where two different classes
2295 independently need groups. But this never happens with our
2296 current machine descriptions. */
2297 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2298 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2301 /* A pair of consecutive regs we can still spill does the trick. */
2302 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2303 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2304 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2307 /* A pair of one already spilled and one we can spill does it
2308 provided the one already spilled is not otherwise reserved. */
2309 if (spill_reg_order
[i
] < 0
2310 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2311 && spill_reg_order
[i
+ 1] >= 0
2312 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
+ 1)
2313 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
+ 1))
2315 if (spill_reg_order
[i
+ 1] < 0
2316 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2317 && spill_reg_order
[i
] >= 0
2318 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
)
2319 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
))
2326 /* Count any groups of CLASS that can be formed from the registers recently
2330 count_possible_groups (group_size
, group_mode
, max_groups
, class)
2332 enum machine_mode
*group_mode
;
2339 /* Now find all consecutive groups of spilled registers
2340 and mark each group off against the need for such groups.
2341 But don't count them against ordinary need, yet. */
2343 if (group_size
[class] == 0)
2346 CLEAR_HARD_REG_SET (new);
2348 /* Make a mask of all the regs that are spill regs in class I. */
2349 for (i
= 0; i
< n_spills
; i
++)
2350 if (TEST_HARD_REG_BIT (reg_class_contents
[class], spill_regs
[i
])
2351 && ! TEST_HARD_REG_BIT (counted_for_groups
, spill_regs
[i
])
2352 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]))
2353 SET_HARD_REG_BIT (new, spill_regs
[i
]);
2355 /* Find each consecutive group of them. */
2356 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
&& max_groups
[class] > 0; i
++)
2357 if (TEST_HARD_REG_BIT (new, i
)
2358 && i
+ group_size
[class] <= FIRST_PSEUDO_REGISTER
2359 && HARD_REGNO_MODE_OK (i
, group_mode
[class]))
2361 for (j
= 1; j
< group_size
[class]; j
++)
2362 if (! TEST_HARD_REG_BIT (new, i
+ j
))
2365 if (j
== group_size
[class])
2367 /* We found a group. Mark it off against this class's need for
2368 groups, and against each superclass too. */
2369 register enum reg_class
*p
;
2371 max_groups
[class]--;
2372 p
= reg_class_superclasses
[class];
2373 while (*p
!= LIM_REG_CLASSES
)
2375 if (group_size
[(int) *p
] <= group_size
[class])
2376 max_groups
[(int) *p
]--;
2380 /* Don't count these registers again. */
2381 for (j
= 0; j
< group_size
[class]; j
++)
2382 SET_HARD_REG_BIT (counted_for_groups
, i
+ j
);
2385 /* Skip to the last reg in this group. When i is incremented above,
2386 it will then point to the first reg of the next possible group. */
2391 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2392 another mode that needs to be reloaded for the same register class CLASS.
2393 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2394 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2396 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2397 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2398 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2399 causes unnecessary failures on machines requiring alignment of register
2400 groups when the two modes are different sizes, because the larger mode has
2401 more strict alignment rules than the smaller mode. */
2404 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2405 enum machine_mode allocate_mode
, other_mode
;
2406 enum reg_class
class;
2409 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2411 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2412 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2413 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2419 /* Handle the failure to find a register to spill.
2420 INSN should be one of the insns which needed this particular spill reg. */
2423 spill_failure (insn
)
2426 if (asm_noperands (PATTERN (insn
)) >= 0)
2427 error_for_asm (insn
, "`asm' needs too many reloads");
2429 fatal_insn ("Unable to find a register to spill.", insn
);
2432 /* Add a new register to the tables of available spill-registers
2433 (as well as spilling all pseudos allocated to the register).
2434 I is the index of this register in potential_reload_regs.
2435 CLASS is the regclass whose need is being satisfied.
2436 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2437 so that this register can count off against them.
2438 MAX_NONGROUPS is 0 if this register is part of a group.
2439 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2442 new_spill_reg (i
, class, max_needs
, max_nongroups
, global
, dumpfile
)
2450 register enum reg_class
*p
;
2452 int regno
= potential_reload_regs
[i
];
2454 if (i
>= FIRST_PSEUDO_REGISTER
)
2455 abort (); /* Caller failed to find any register. */
2457 if (fixed_regs
[regno
] || TEST_HARD_REG_BIT (forbidden_regs
, regno
))
2459 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2460 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2461 This may be due to a compiler bug or to impossible asm\n\
2462 statements or clauses.", regno
, reg_names
[regno
], reg_class_names
[class]);
2465 /* Make reg REGNO an additional reload reg. */
2467 potential_reload_regs
[i
] = -1;
2468 spill_regs
[n_spills
] = regno
;
2469 spill_reg_order
[regno
] = n_spills
;
2471 fprintf (dumpfile
, "Spilling reg %d.\n", spill_regs
[n_spills
]);
2473 /* Clear off the needs we just satisfied. */
2476 p
= reg_class_superclasses
[class];
2477 while (*p
!= LIM_REG_CLASSES
)
2478 max_needs
[(int) *p
++]--;
2480 if (max_nongroups
&& max_nongroups
[class] > 0)
2482 SET_HARD_REG_BIT (counted_for_nongroups
, regno
);
2483 max_nongroups
[class]--;
2484 p
= reg_class_superclasses
[class];
2485 while (*p
!= LIM_REG_CLASSES
)
2486 max_nongroups
[(int) *p
++]--;
2489 /* Spill every pseudo reg that was allocated to this reg
2490 or to something that overlaps this reg. */
2492 val
= spill_hard_reg (spill_regs
[n_spills
], global
, dumpfile
, 0);
2494 /* If there are some registers still to eliminate and this register
2495 wasn't ever used before, additional stack space may have to be
2496 allocated to store this register. Thus, we may have changed the offset
2497 between the stack and frame pointers, so mark that something has changed.
2498 (If new pseudos were spilled, thus requiring more space, VAL would have
2499 been set non-zero by the call to spill_hard_reg above since additional
2500 reloads may be needed in that case.
2502 One might think that we need only set VAL to 1 if this is a call-used
2503 register. However, the set of registers that must be saved by the
2504 prologue is not identical to the call-used set. For example, the
2505 register used by the call insn for the return PC is a call-used register,
2506 but must be saved by the prologue. */
2507 if (num_eliminable
&& ! regs_ever_live
[spill_regs
[n_spills
]])
2510 regs_ever_live
[spill_regs
[n_spills
]] = 1;
2516 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2517 data that is dead in INSN. */
2520 delete_dead_insn (insn
)
2523 rtx prev
= prev_real_insn (insn
);
2526 /* If the previous insn sets a register that dies in our insn, delete it
2528 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2529 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2530 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2531 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2532 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2533 delete_dead_insn (prev
);
2535 PUT_CODE (insn
, NOTE
);
2536 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2537 NOTE_SOURCE_FILE (insn
) = 0;
2540 /* Modify the home of pseudo-reg I.
2541 The new home is present in reg_renumber[I].
2543 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2544 or it may be -1, meaning there is none or it is not relevant.
2545 This is used so that all pseudos spilled from a given hard reg
2546 can share one stack slot. */
2549 alter_reg (i
, from_reg
)
2553 /* When outputting an inline function, this can happen
2554 for a reg that isn't actually used. */
2555 if (regno_reg_rtx
[i
] == 0)
2558 /* If the reg got changed to a MEM at rtl-generation time,
2560 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2563 /* Modify the reg-rtx to contain the new hard reg
2564 number or else to contain its pseudo reg number. */
2565 REGNO (regno_reg_rtx
[i
])
2566 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2568 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2569 allocate a stack slot for it. */
2571 if (reg_renumber
[i
] < 0
2572 && REG_N_REFS (i
) > 0
2573 && reg_equiv_constant
[i
] == 0
2574 && reg_equiv_memory_loc
[i
] == 0)
2577 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2578 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2581 /* Each pseudo reg has an inherent size which comes from its own mode,
2582 and a total size which provides room for paradoxical subregs
2583 which refer to the pseudo reg in wider modes.
2585 We can use a slot already allocated if it provides both
2586 enough inherent space and enough total space.
2587 Otherwise, we allocate a new slot, making sure that it has no less
2588 inherent space, and no less total space, then the previous slot. */
2591 /* No known place to spill from => no slot to reuse. */
2592 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2593 inherent_size
== total_size
? 0 : -1);
2594 if (BYTES_BIG_ENDIAN
)
2595 /* Cancel the big-endian correction done in assign_stack_local.
2596 Get the address of the beginning of the slot.
2597 This is so we can do a big-endian correction unconditionally
2599 adjust
= inherent_size
- total_size
;
2601 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2603 /* Reuse a stack slot if possible. */
2604 else if (spill_stack_slot
[from_reg
] != 0
2605 && spill_stack_slot_width
[from_reg
] >= total_size
2606 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2608 x
= spill_stack_slot
[from_reg
];
2609 /* Allocate a bigger slot. */
2612 /* Compute maximum size needed, both for inherent size
2613 and for total size. */
2614 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2616 if (spill_stack_slot
[from_reg
])
2618 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2620 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2621 if (spill_stack_slot_width
[from_reg
] > total_size
)
2622 total_size
= spill_stack_slot_width
[from_reg
];
2624 /* Make a slot with that size. */
2625 x
= assign_stack_local (mode
, total_size
,
2626 inherent_size
== total_size
? 0 : -1);
2628 if (BYTES_BIG_ENDIAN
)
2630 /* Cancel the big-endian correction done in assign_stack_local.
2631 Get the address of the beginning of the slot.
2632 This is so we can do a big-endian correction unconditionally
2634 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2636 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2639 plus_constant (XEXP (x
, 0), adjust
));
2641 spill_stack_slot
[from_reg
] = stack_slot
;
2642 spill_stack_slot_width
[from_reg
] = total_size
;
2645 /* On a big endian machine, the "address" of the slot
2646 is the address of the low part that fits its inherent mode. */
2647 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2648 adjust
+= (total_size
- inherent_size
);
2650 /* If we have any adjustment to make, or if the stack slot is the
2651 wrong mode, make a new stack slot. */
2652 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2654 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2655 plus_constant (XEXP (x
, 0), adjust
));
2657 /* If this was shared among registers, must ensure we never
2658 set it readonly since that can cause scheduling
2659 problems. Note we would only have in this adjustment
2660 case in any event, since the code above doesn't set it. */
2663 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2666 /* Save the stack slot for later. */
2667 reg_equiv_memory_loc
[i
] = x
;
2671 /* Mark the slots in regs_ever_live for the hard regs
2672 used by pseudo-reg number REGNO. */
2675 mark_home_live (regno
)
2678 register int i
, lim
;
2679 i
= reg_renumber
[regno
];
2682 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2684 regs_ever_live
[i
++] = 1;
2687 /* Mark the registers used in SCRATCH as being live. */
2690 mark_scratch_live (scratch
)
2694 int regno
= REGNO (scratch
);
2695 int lim
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (scratch
));
2697 for (i
= regno
; i
< lim
; i
++)
2698 regs_ever_live
[i
] = 1;
2701 /* This function handles the tracking of elimination offsets around branches.
2703 X is a piece of RTL being scanned.
2705 INSN is the insn that it came from, if any.
2707 INITIAL_P is non-zero if we are to set the offset to be the initial
2708 offset and zero if we are setting the offset of the label to be the
2712 set_label_offsets (x
, insn
, initial_p
)
2717 enum rtx_code code
= GET_CODE (x
);
2720 struct elim_table
*p
;
2725 if (LABEL_REF_NONLOCAL_P (x
))
2730 /* ... fall through ... */
2733 /* If we know nothing about this label, set the desired offsets. Note
2734 that this sets the offset at a label to be the offset before a label
2735 if we don't know anything about the label. This is not correct for
2736 the label after a BARRIER, but is the best guess we can make. If
2737 we guessed wrong, we will suppress an elimination that might have
2738 been possible had we been able to guess correctly. */
2740 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2742 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2743 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2744 = (initial_p
? reg_eliminate
[i
].initial_offset
2745 : reg_eliminate
[i
].offset
);
2746 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2749 /* Otherwise, if this is the definition of a label and it is
2750 preceded by a BARRIER, set our offsets to the known offset of
2754 && (tem
= prev_nonnote_insn (insn
)) != 0
2755 && GET_CODE (tem
) == BARRIER
)
2757 num_not_at_initial_offset
= 0;
2758 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2760 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
2761 = offsets_at
[CODE_LABEL_NUMBER (x
)][i
];
2762 if (reg_eliminate
[i
].can_eliminate
2763 && (reg_eliminate
[i
].offset
2764 != reg_eliminate
[i
].initial_offset
))
2765 num_not_at_initial_offset
++;
2770 /* If neither of the above cases is true, compare each offset
2771 with those previously recorded and suppress any eliminations
2772 where the offsets disagree. */
2774 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2775 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2776 != (initial_p
? reg_eliminate
[i
].initial_offset
2777 : reg_eliminate
[i
].offset
))
2778 reg_eliminate
[i
].can_eliminate
= 0;
2783 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2785 /* ... fall through ... */
2789 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2790 and hence must have all eliminations at their initial offsets. */
2791 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2792 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2793 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2798 /* Each of the labels in the address vector must be at their initial
2799 offsets. We want the first field for ADDR_VEC and the second
2800 field for ADDR_DIFF_VEC. */
2802 for (i
= 0; i
< XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2803 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2808 /* We only care about setting PC. If the source is not RETURN,
2809 IF_THEN_ELSE, or a label, disable any eliminations not at
2810 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2811 isn't one of those possibilities. For branches to a label,
2812 call ourselves recursively.
2814 Note that this can disable elimination unnecessarily when we have
2815 a non-local goto since it will look like a non-constant jump to
2816 someplace in the current function. This isn't a significant
2817 problem since such jumps will normally be when all elimination
2818 pairs are back to their initial offsets. */
2820 if (SET_DEST (x
) != pc_rtx
)
2823 switch (GET_CODE (SET_SRC (x
)))
2830 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2834 tem
= XEXP (SET_SRC (x
), 1);
2835 if (GET_CODE (tem
) == LABEL_REF
)
2836 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2837 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2840 tem
= XEXP (SET_SRC (x
), 2);
2841 if (GET_CODE (tem
) == LABEL_REF
)
2842 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2843 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2851 /* If we reach here, all eliminations must be at their initial
2852 offset because we are doing a jump to a variable address. */
2853 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2854 if (p
->offset
!= p
->initial_offset
)
2855 p
->can_eliminate
= 0;
2863 /* Used for communication between the next two function to properly share
2864 the vector for an ASM_OPERANDS. */
2866 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2868 /* Scan X and replace any eliminable registers (such as fp) with a
2869 replacement (such as sp), plus an offset.
2871 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2872 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2873 MEM, we are allowed to replace a sum of a register and the constant zero
2874 with the register, which we cannot do outside a MEM. In addition, we need
2875 to record the fact that a register is referenced outside a MEM.
2877 If INSN is an insn, it is the insn containing X. If we replace a REG
2878 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2879 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2880 the REG is being modified.
2882 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2883 That's used when we eliminate in expressions stored in notes.
2884 This means, do not set ref_outside_mem even if the reference
2887 If we see a modification to a register we know about, take the
2888 appropriate action (see case SET, below).
2890 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2891 replacements done assuming all offsets are at their initial values. If
2892 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2893 encounter, return the actual location so that find_reloads will do
2894 the proper thing. */
2897 eliminate_regs (x
, mem_mode
, insn
)
2899 enum machine_mode mem_mode
;
2902 enum rtx_code code
= GET_CODE (x
);
2903 struct elim_table
*ep
;
2926 /* This is only for the benefit of the debugging backends, which call
2927 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2928 removed after CSE. */
2929 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2930 if (GET_CODE (new) == MEM
)
2931 return XEXP (new, 0);
2937 /* First handle the case where we encounter a bare register that
2938 is eliminable. Replace it with a PLUS. */
2939 if (regno
< FIRST_PSEUDO_REGISTER
)
2941 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2943 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2946 /* Refs inside notes don't count for this purpose. */
2947 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2948 || GET_CODE (insn
) == INSN_LIST
)))
2949 ep
->ref_outside_mem
= 1;
2950 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2954 else if (reg_equiv_memory_loc
&& reg_equiv_memory_loc
[regno
]
2955 && (reg_equiv_address
[regno
] || num_not_at_initial_offset
))
2957 /* In this case, find_reloads would attempt to either use an
2958 incorrect address (if something is not at its initial offset)
2959 or substitute an replaced address into an insn (which loses
2960 if the offset is changed by some later action). So we simply
2961 return the replaced stack slot (assuming it is changed by
2962 elimination) and ignore the fact that this is actually a
2963 reference to the pseudo. Ensure we make a copy of the
2964 address in case it is shared. */
2965 new = eliminate_regs (reg_equiv_memory_loc
[regno
], mem_mode
, insn
);
2966 if (new != reg_equiv_memory_loc
[regno
])
2968 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
2969 && GET_CODE (insn
) != INSN_LIST
)
2970 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
, x
), insn
))
2971 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
2972 return copy_rtx (new);
2978 /* If this is the sum of an eliminable register and a constant, rework
2980 if (GET_CODE (XEXP (x
, 0)) == REG
2981 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2982 && CONSTANT_P (XEXP (x
, 1)))
2984 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2986 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2989 /* Refs inside notes don't count for this purpose. */
2990 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2991 || GET_CODE (insn
) == INSN_LIST
)))
2992 ep
->ref_outside_mem
= 1;
2994 /* The only time we want to replace a PLUS with a REG (this
2995 occurs when the constant operand of the PLUS is the negative
2996 of the offset) is when we are inside a MEM. We won't want
2997 to do so at other times because that would change the
2998 structure of the insn in a way that reload can't handle.
2999 We special-case the commonest situation in
3000 eliminate_regs_in_insn, so just replace a PLUS with a
3001 PLUS here, unless inside a MEM. */
3002 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3003 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
3006 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
3007 plus_constant (XEXP (x
, 1),
3008 ep
->previous_offset
));
3011 /* If the register is not eliminable, we are done since the other
3012 operand is a constant. */
3016 /* If this is part of an address, we want to bring any constant to the
3017 outermost PLUS. We will do this by doing register replacement in
3018 our operands and seeing if a constant shows up in one of them.
3020 We assume here this is part of an address (or a "load address" insn)
3021 since an eliminable register is not likely to appear in any other
3024 If we have (plus (eliminable) (reg)), we want to produce
3025 (plus (plus (replacement) (reg) (const))). If this was part of a
3026 normal add insn, (plus (replacement) (reg)) will be pushed as a
3027 reload. This is the desired action. */
3030 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3031 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
3033 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
3035 /* If one side is a PLUS and the other side is a pseudo that
3036 didn't get a hard register but has a reg_equiv_constant,
3037 we must replace the constant here since it may no longer
3038 be in the position of any operand. */
3039 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
3040 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
3041 && reg_renumber
[REGNO (new1
)] < 0
3042 && reg_equiv_constant
!= 0
3043 && reg_equiv_constant
[REGNO (new1
)] != 0)
3044 new1
= reg_equiv_constant
[REGNO (new1
)];
3045 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
3046 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
3047 && reg_renumber
[REGNO (new0
)] < 0
3048 && reg_equiv_constant
[REGNO (new0
)] != 0)
3049 new0
= reg_equiv_constant
[REGNO (new0
)];
3051 new = form_sum (new0
, new1
);
3053 /* As above, if we are not inside a MEM we do not want to
3054 turn a PLUS into something else. We might try to do so here
3055 for an addition of 0 if we aren't optimizing. */
3056 if (! mem_mode
&& GET_CODE (new) != PLUS
)
3057 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
3065 /* If this is the product of an eliminable register and a
3066 constant, apply the distribute law and move the constant out
3067 so that we have (plus (mult ..) ..). This is needed in order
3068 to keep load-address insns valid. This case is pathological.
3069 We ignore the possibility of overflow here. */
3070 if (GET_CODE (XEXP (x
, 0)) == REG
3071 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3072 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3073 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3075 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
3078 /* Refs inside notes don't count for this purpose. */
3079 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
3080 || GET_CODE (insn
) == INSN_LIST
)))
3081 ep
->ref_outside_mem
= 1;
3084 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
3085 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
3088 /* ... fall through ... */
3093 case DIV
: case UDIV
:
3094 case MOD
: case UMOD
:
3095 case AND
: case IOR
: case XOR
:
3096 case ROTATERT
: case ROTATE
:
3097 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
3099 case GE
: case GT
: case GEU
: case GTU
:
3100 case LE
: case LT
: case LEU
: case LTU
:
3102 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3104 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
3106 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
3107 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
3112 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3115 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3116 if (new != XEXP (x
, 0))
3117 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
3120 /* ... fall through ... */
3123 /* Now do eliminations in the rest of the chain. If this was
3124 an EXPR_LIST, this might result in allocating more memory than is
3125 strictly needed, but it simplifies the code. */
3128 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
3129 if (new != XEXP (x
, 1))
3130 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
3138 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3139 if (ep
->to_rtx
== XEXP (x
, 0))
3141 int size
= GET_MODE_SIZE (mem_mode
);
3143 /* If more bytes than MEM_MODE are pushed, account for them. */
3144 #ifdef PUSH_ROUNDING
3145 if (ep
->to_rtx
== stack_pointer_rtx
)
3146 size
= PUSH_ROUNDING (size
);
3148 if (code
== PRE_DEC
|| code
== POST_DEC
)
3154 /* Fall through to generic unary operation case. */
3155 case STRICT_LOW_PART
:
3157 case SIGN_EXTEND
: case ZERO_EXTEND
:
3158 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3159 case FLOAT
: case FIX
:
3160 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3164 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3165 if (new != XEXP (x
, 0))
3166 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3170 /* Similar to above processing, but preserve SUBREG_WORD.
3171 Convert (subreg (mem)) to (mem) if not paradoxical.
3172 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3173 pseudo didn't get a hard reg, we must replace this with the
3174 eliminated version of the memory location because push_reloads
3175 may do the replacement in certain circumstances. */
3176 if (GET_CODE (SUBREG_REG (x
)) == REG
3177 && (GET_MODE_SIZE (GET_MODE (x
))
3178 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3179 && reg_equiv_memory_loc
!= 0
3180 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
3182 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
3185 /* If we didn't change anything, we must retain the pseudo. */
3186 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
3187 new = SUBREG_REG (x
);
3190 /* In this case, we must show that the pseudo is used in this
3191 insn so that delete_output_reload will do the right thing. */
3192 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3193 && GET_CODE (insn
) != INSN_LIST
)
3194 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
,
3197 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
3199 /* Ensure NEW isn't shared in case we have to reload it. */
3200 new = copy_rtx (new);
3204 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
3206 if (new != XEXP (x
, 0))
3208 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
3209 int new_size
= GET_MODE_SIZE (GET_MODE (new));
3211 if (GET_CODE (new) == MEM
3212 && ((x_size
< new_size
3213 #ifdef WORD_REGISTER_OPERATIONS
3214 /* On these machines, combine can create rtl of the form
3215 (set (subreg:m1 (reg:m2 R) 0) ...)
3216 where m1 < m2, and expects something interesting to
3217 happen to the entire word. Moreover, it will use the
3218 (reg:m2 R) later, expecting all bits to be preserved.
3219 So if the number of words is the same, preserve the
3220 subreg so that push_reloads can see it. */
3221 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
3224 || (x_size
== new_size
))
3227 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
3228 enum machine_mode mode
= GET_MODE (x
);
3230 if (BYTES_BIG_ENDIAN
)
3231 offset
+= (MIN (UNITS_PER_WORD
,
3232 GET_MODE_SIZE (GET_MODE (new)))
3233 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
3235 PUT_MODE (new, mode
);
3236 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
3240 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
3246 /* If using a register that is the source of an eliminate we still
3247 think can be performed, note it cannot be performed since we don't
3248 know how this register is used. */
3249 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3250 if (ep
->from_rtx
== XEXP (x
, 0))
3251 ep
->can_eliminate
= 0;
3253 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3254 if (new != XEXP (x
, 0))
3255 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3259 /* If clobbering a register that is the replacement register for an
3260 elimination we still think can be performed, note that it cannot
3261 be performed. Otherwise, we need not be concerned about it. */
3262 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3263 if (ep
->to_rtx
== XEXP (x
, 0))
3264 ep
->can_eliminate
= 0;
3266 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3267 if (new != XEXP (x
, 0))
3268 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3274 /* Properly handle sharing input and constraint vectors. */
3275 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
3277 /* When we come to a new vector not seen before,
3278 scan all its elements; keep the old vector if none
3279 of them changes; otherwise, make a copy. */
3280 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
3281 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
3282 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3283 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
3286 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3287 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
3290 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
3291 new_asm_operands_vec
= old_asm_operands_vec
;
3293 new_asm_operands_vec
3294 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
3297 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3298 if (new_asm_operands_vec
== old_asm_operands_vec
)
3301 new = gen_rtx_ASM_OPERANDS (VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
3302 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
3303 ASM_OPERANDS_OUTPUT_IDX (x
),
3304 new_asm_operands_vec
,
3305 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
3306 ASM_OPERANDS_SOURCE_FILE (x
),
3307 ASM_OPERANDS_SOURCE_LINE (x
));
3308 new->volatil
= x
->volatil
;
3313 /* Check for setting a register that we know about. */
3314 if (GET_CODE (SET_DEST (x
)) == REG
)
3316 /* See if this is setting the replacement register for an
3319 If DEST is the hard frame pointer, we do nothing because we
3320 assume that all assignments to the frame pointer are for
3321 non-local gotos and are being done at a time when they are valid
3322 and do not disturb anything else. Some machines want to
3323 eliminate a fake argument pointer (or even a fake frame pointer)
3324 with either the real frame or the stack pointer. Assignments to
3325 the hard frame pointer must not prevent this elimination. */
3327 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3329 if (ep
->to_rtx
== SET_DEST (x
)
3330 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3332 /* If it is being incremented, adjust the offset. Otherwise,
3333 this elimination can't be done. */
3334 rtx src
= SET_SRC (x
);
3336 if (GET_CODE (src
) == PLUS
3337 && XEXP (src
, 0) == SET_DEST (x
)
3338 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3339 ep
->offset
-= INTVAL (XEXP (src
, 1));
3341 ep
->can_eliminate
= 0;
3344 /* Now check to see we are assigning to a register that can be
3345 eliminated. If so, it must be as part of a PARALLEL, since we
3346 will not have been called if this is a single SET. So indicate
3347 that we can no longer eliminate this reg. */
3348 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3350 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3351 ep
->can_eliminate
= 0;
3354 /* Now avoid the loop below in this common case. */
3356 rtx new0
= eliminate_regs (SET_DEST (x
), 0, insn
);
3357 rtx new1
= eliminate_regs (SET_SRC (x
), 0, insn
);
3359 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3360 write a CLOBBER insn. */
3361 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3362 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3363 && GET_CODE (insn
) != INSN_LIST
)
3364 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, SET_DEST (x
)), insn
);
3366 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3367 return gen_rtx_SET (VOIDmode
, new0
, new1
);
3373 /* This is only for the benefit of the debugging backends, which call
3374 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3375 removed after CSE. */
3376 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
3377 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
3379 /* Our only special processing is to pass the mode of the MEM to our
3380 recursive call and copy the flags. While we are here, handle this
3381 case more efficiently. */
3382 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
3383 if (new != XEXP (x
, 0))
3385 new = gen_rtx_MEM (GET_MODE (x
), new);
3386 new->volatil
= x
->volatil
;
3387 new->unchanging
= x
->unchanging
;
3388 new->in_struct
= x
->in_struct
;
3398 /* Process each of our operands recursively. If any have changed, make a
3400 fmt
= GET_RTX_FORMAT (code
);
3401 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3405 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
3406 if (new != XEXP (x
, i
) && ! copied
)
3408 rtx new_x
= rtx_alloc (code
);
3409 bcopy ((char *) x
, (char *) new_x
,
3410 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3411 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
3417 else if (*fmt
== 'E')
3420 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3422 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3423 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3425 rtvec new_v
= gen_rtvec_vv (XVECLEN (x
, i
),
3429 rtx new_x
= rtx_alloc (code
);
3430 bcopy ((char *) x
, (char *) new_x
,
3431 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3432 + (sizeof (new_x
->fld
[0])
3433 * GET_RTX_LENGTH (code
))));
3437 XVEC (x
, i
) = new_v
;
3440 XVECEXP (x
, i
, j
) = new;
3448 /* Scan INSN and eliminate all eliminable registers in it.
3450 If REPLACE is nonzero, do the replacement destructively. Also
3451 delete the insn as dead it if it is setting an eliminable register.
3453 If REPLACE is zero, do all our allocations in reload_obstack.
3455 If no eliminations were done and this insn doesn't require any elimination
3456 processing (these are not identical conditions: it might be updating sp,
3457 but not referencing fp; this needs to be seen during reload_as_needed so
3458 that the offset between fp and sp can be taken into consideration), zero
3459 is returned. Otherwise, 1 is returned. */
3462 eliminate_regs_in_insn (insn
, replace
)
3466 rtx old_body
= PATTERN (insn
);
3467 rtx old_set
= single_set (insn
);
3470 struct elim_table
*ep
;
3473 push_obstacks (&reload_obstack
, &reload_obstack
);
3475 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
3476 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3478 /* Check for setting an eliminable register. */
3479 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3480 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3482 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3483 /* If this is setting the frame pointer register to the
3484 hardware frame pointer register and this is an elimination
3485 that will be done (tested above), this insn is really
3486 adjusting the frame pointer downward to compensate for
3487 the adjustment done before a nonlocal goto. */
3488 if (ep
->from
== FRAME_POINTER_REGNUM
3489 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3491 rtx src
= SET_SRC (old_set
);
3493 rtx prev_insn
, prev_set
;
3495 if (src
== ep
->to_rtx
)
3497 else if (GET_CODE (src
) == PLUS
3498 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3499 && XEXP (src
, 1) == ep
->to_rtx
)
3500 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3501 else if (GET_CODE (src
) == PLUS
3502 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3503 && XEXP (src
, 0) == ep
->to_rtx
)
3504 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3505 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
3506 && (prev_set
= single_set (prev_insn
)) != 0
3507 && rtx_equal_p (SET_DEST (prev_set
), src
))
3509 src
= SET_SRC (prev_set
);
3510 if (src
== ep
->to_rtx
)
3512 else if (GET_CODE (src
) == PLUS
3513 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3514 && XEXP (src
, 1) == ep
->to_rtx
)
3515 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3516 else if (GET_CODE (src
) == PLUS
3517 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3518 && XEXP (src
, 0) == ep
->to_rtx
)
3519 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3527 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3529 /* First see if this insn remains valid when we
3530 make the change. If not, keep the INSN_CODE
3531 the same and let reload fit it up. */
3532 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3533 validate_change (insn
, &SET_DEST (old_set
),
3535 if (! apply_change_group ())
3537 SET_SRC (old_set
) = src
;
3538 SET_DEST (old_set
) = ep
->to_rtx
;
3548 /* In this case this insn isn't serving a useful purpose. We
3549 will delete it in reload_as_needed once we know that this
3550 elimination is, in fact, being done.
3552 If REPLACE isn't set, we can't delete this insn, but needn't
3553 process it since it won't be used unless something changes. */
3555 delete_dead_insn (insn
);
3560 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3561 in the insn is the negative of the offset in FROM. Substitute
3562 (set (reg) (reg to)) for the insn and change its code.
3564 We have to do this here, rather than in eliminate_regs, do that we can
3565 change the insn code. */
3567 if (GET_CODE (SET_SRC (old_set
)) == PLUS
3568 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3569 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
)
3570 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3572 if (ep
->from_rtx
== XEXP (SET_SRC (old_set
), 0)
3573 && ep
->can_eliminate
)
3575 /* We must stop at the first elimination that will be used.
3576 If this one would replace the PLUS with a REG, do it
3577 now. Otherwise, quit the loop and let eliminate_regs
3578 do its normal replacement. */
3579 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_set
), 1)))
3581 /* We assume here that we don't need a PARALLEL of
3582 any CLOBBERs for this assignment. There's not
3583 much we can do if we do need it. */
3584 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3587 INSN_CODE (insn
) = -1;
3596 old_asm_operands_vec
= 0;
3598 /* Replace the body of this insn with a substituted form. If we changed
3599 something, return non-zero.
3601 If we are replacing a body that was a (set X (plus Y Z)), try to
3602 re-recognize the insn. We do this in case we had a simple addition
3603 but now can do this as a load-address. This saves an insn in this
3606 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3607 if (new_body
!= old_body
)
3609 /* If we aren't replacing things permanently and we changed something,
3610 make another copy to ensure that all the RTL is new. Otherwise
3611 things can go wrong if find_reload swaps commutative operands
3612 and one is inside RTL that has been copied while the other is not. */
3614 /* Don't copy an asm_operands because (1) there's no need and (2)
3615 copy_rtx can't do it properly when there are multiple outputs. */
3616 if (! replace
&& asm_noperands (old_body
) < 0)
3617 new_body
= copy_rtx (new_body
);
3619 /* If we had a move insn but now we don't, rerecognize it. This will
3620 cause spurious re-recognition if the old move had a PARALLEL since
3621 the new one still will, but we can't call single_set without
3622 having put NEW_BODY into the insn and the re-recognition won't
3623 hurt in this rare case. */
3625 && ((GET_CODE (SET_SRC (old_set
)) == REG
3626 && (GET_CODE (new_body
) != SET
3627 || GET_CODE (SET_SRC (new_body
)) != REG
))
3628 /* If this was a load from or store to memory, compare
3629 the MEM in recog_operand to the one in the insn. If they
3630 are not equal, then rerecognize the insn. */
3632 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3633 && SET_SRC (old_set
) != recog_operand
[1])
3634 || (GET_CODE (SET_DEST (old_set
)) == MEM
3635 && SET_DEST (old_set
) != recog_operand
[0])))
3636 /* If this was an add insn before, rerecognize. */
3637 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3639 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3640 /* If recognition fails, store the new body anyway.
3641 It's normal to have recognition failures here
3642 due to bizarre memory addresses; reloading will fix them. */
3643 PATTERN (insn
) = new_body
;
3646 PATTERN (insn
) = new_body
;
3651 /* Loop through all elimination pairs. See if any have changed and
3652 recalculate the number not at initial offset.
3654 Compute the maximum offset (minimum offset if the stack does not
3655 grow downward) for each elimination pair.
3657 We also detect a cases where register elimination cannot be done,
3658 namely, if a register would be both changed and referenced outside a MEM
3659 in the resulting insn since such an insn is often undefined and, even if
3660 not, we cannot know what meaning will be given to it. Note that it is
3661 valid to have a register used in an address in an insn that changes it
3662 (presumably with a pre- or post-increment or decrement).
3664 If anything changes, return nonzero. */
3666 num_not_at_initial_offset
= 0;
3667 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3669 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3670 ep
->can_eliminate
= 0;
3672 ep
->ref_outside_mem
= 0;
3674 if (ep
->previous_offset
!= ep
->offset
)
3677 ep
->previous_offset
= ep
->offset
;
3678 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3679 num_not_at_initial_offset
++;
3681 #ifdef STACK_GROWS_DOWNWARD
3682 ep
->max_offset
= MAX (ep
->max_offset
, ep
->offset
);
3684 ep
->max_offset
= MIN (ep
->max_offset
, ep
->offset
);
3689 /* If we changed something, perform elimination in REG_NOTES. This is
3690 needed even when REPLACE is zero because a REG_DEAD note might refer
3691 to a register that we eliminate and could cause a different number
3692 of spill registers to be needed in the final reload pass than in
3694 if (val
&& REG_NOTES (insn
) != 0)
3695 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3703 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3704 replacement we currently believe is valid, mark it as not eliminable if X
3705 modifies DEST in any way other than by adding a constant integer to it.
3707 If DEST is the frame pointer, we do nothing because we assume that
3708 all assignments to the hard frame pointer are nonlocal gotos and are being
3709 done at a time when they are valid and do not disturb anything else.
3710 Some machines want to eliminate a fake argument pointer with either the
3711 frame or stack pointer. Assignments to the hard frame pointer must not
3712 prevent this elimination.
3714 Called via note_stores from reload before starting its passes to scan
3715 the insns of the function. */
3718 mark_not_eliminable (dest
, x
)
3724 /* A SUBREG of a hard register here is just changing its mode. We should
3725 not see a SUBREG of an eliminable hard register, but check just in
3727 if (GET_CODE (dest
) == SUBREG
)
3728 dest
= SUBREG_REG (dest
);
3730 if (dest
== hard_frame_pointer_rtx
)
3733 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3734 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3735 && (GET_CODE (x
) != SET
3736 || GET_CODE (SET_SRC (x
)) != PLUS
3737 || XEXP (SET_SRC (x
), 0) != dest
3738 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3740 reg_eliminate
[i
].can_eliminate_previous
3741 = reg_eliminate
[i
].can_eliminate
= 0;
3746 /* Kick all pseudos out of hard register REGNO.
3747 If GLOBAL is nonzero, try to find someplace else to put them.
3748 If DUMPFILE is nonzero, log actions taken on that file.
3750 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3751 because we found we can't eliminate some register. In the case, no pseudos
3752 are allowed to be in the register, even if they are only in a block that
3753 doesn't require spill registers, unlike the case when we are spilling this
3754 hard reg to produce another spill register.
3756 Return nonzero if any pseudos needed to be kicked out. */
3759 spill_hard_reg (regno
, global
, dumpfile
, cant_eliminate
)
3765 enum reg_class
class = REGNO_REG_CLASS (regno
);
3766 int something_changed
= 0;
3769 SET_HARD_REG_BIT (forbidden_regs
, regno
);
3772 regs_ever_live
[regno
] = 1;
3774 /* Spill every pseudo reg that was allocated to this reg
3775 or to something that overlaps this reg. */
3777 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3778 if (reg_renumber
[i
] >= 0
3779 && reg_renumber
[i
] <= regno
3781 + HARD_REGNO_NREGS (reg_renumber
[i
],
3782 PSEUDO_REGNO_MODE (i
))
3785 /* If this register belongs solely to a basic block which needed no
3786 spilling of any class that this register is contained in,
3787 leave it be, unless we are spilling this register because
3788 it was a hard register that can't be eliminated. */
3790 if (! cant_eliminate
3791 && basic_block_needs
[0]
3792 && REG_BASIC_BLOCK (i
) >= 0
3793 && basic_block_needs
[(int) class][REG_BASIC_BLOCK (i
)] == 0)
3797 for (p
= reg_class_superclasses
[(int) class];
3798 *p
!= LIM_REG_CLASSES
; p
++)
3799 if (basic_block_needs
[(int) *p
][REG_BASIC_BLOCK (i
)] > 0)
3802 if (*p
== LIM_REG_CLASSES
)
3806 /* Mark it as no longer having a hard register home. */
3807 reg_renumber
[i
] = -1;
3808 /* We will need to scan everything again. */
3809 something_changed
= 1;
3811 retry_global_alloc (i
, forbidden_regs
);
3813 alter_reg (i
, regno
);
3816 if (reg_renumber
[i
] == -1)
3817 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3819 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3820 i
, reg_renumber
[i
]);
3823 for (i
= 0; i
< scratch_list_length
; i
++)
3826 && regno
>= REGNO (scratch_list
[i
])
3827 && regno
< REGNO (scratch_list
[i
])
3828 + HARD_REGNO_NREGS (REGNO (scratch_list
[i
]),
3829 GET_MODE (scratch_list
[i
])))
3831 if (! cant_eliminate
&& basic_block_needs
[0]
3832 && ! basic_block_needs
[(int) class][scratch_block
[i
]])
3836 for (p
= reg_class_superclasses
[(int) class];
3837 *p
!= LIM_REG_CLASSES
; p
++)
3838 if (basic_block_needs
[(int) *p
][scratch_block
[i
]] > 0)
3841 if (*p
== LIM_REG_CLASSES
)
3844 PUT_CODE (scratch_list
[i
], SCRATCH
);
3845 scratch_list
[i
] = 0;
3846 something_changed
= 1;
3851 return something_changed
;
3854 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3855 Also mark any hard registers used to store user variables as
3856 forbidden from being used for spill registers. */
3859 scan_paradoxical_subregs (x
)
3864 register enum rtx_code code
= GET_CODE (x
);
3869 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3870 && REG_USERVAR_P (x
))
3871 SET_HARD_REG_BIT (forbidden_regs
, REGNO (x
));
3886 if (GET_CODE (SUBREG_REG (x
)) == REG
3887 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3888 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3889 = GET_MODE_SIZE (GET_MODE (x
));
3896 fmt
= GET_RTX_FORMAT (code
);
3897 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3900 scan_paradoxical_subregs (XEXP (x
, i
));
3901 else if (fmt
[i
] == 'E')
3904 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
3905 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3911 hard_reg_use_compare (p1p
, p2p
)
3912 const GENERIC_PTR p1p
;
3913 const GENERIC_PTR p2p
;
3915 struct hard_reg_n_uses
*p1
= (struct hard_reg_n_uses
*)p1p
,
3916 *p2
= (struct hard_reg_n_uses
*)p2p
;
3917 int tem
= p1
->uses
- p2
->uses
;
3918 if (tem
!= 0) return tem
;
3919 /* If regs are equally good, sort by regno,
3920 so that the results of qsort leave nothing to chance. */
3921 return p1
->regno
- p2
->regno
;
3924 /* Choose the order to consider regs for use as reload registers
3925 based on how much trouble would be caused by spilling one.
3926 Store them in order of decreasing preference in potential_reload_regs. */
3929 order_regs_for_reload (global
)
3936 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
3938 CLEAR_HARD_REG_SET (bad_spill_regs
);
3940 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3941 potential_reload_regs
[i
] = -1;
3943 /* Count number of uses of each hard reg by pseudo regs allocated to it
3944 and then order them by decreasing use. */
3946 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3948 hard_reg_n_uses
[i
].uses
= 0;
3949 hard_reg_n_uses
[i
].regno
= i
;
3952 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3954 int regno
= reg_renumber
[i
];
3957 int lim
= regno
+ HARD_REGNO_NREGS (regno
, PSEUDO_REGNO_MODE (i
));
3960 /* If allocated by local-alloc, show more uses since
3961 we're not going to be able to reallocate it, but
3962 we might if allocated by global alloc. */
3963 if (global
&& reg_allocno
[i
] < 0)
3964 hard_reg_n_uses
[regno
].uses
+= (REG_N_REFS (i
) + 1) / 2;
3966 hard_reg_n_uses
[regno
++].uses
+= REG_N_REFS (i
);
3969 large
+= REG_N_REFS (i
);
3972 /* Now fixed registers (which cannot safely be used for reloading)
3973 get a very high use count so they will be considered least desirable.
3974 Registers used explicitly in the rtl code are almost as bad. */
3976 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3980 hard_reg_n_uses
[i
].uses
+= 2 * large
+ 2;
3981 SET_HARD_REG_BIT (bad_spill_regs
, i
);
3983 else if (regs_explicitly_used
[i
])
3985 hard_reg_n_uses
[i
].uses
+= large
+ 1;
3986 if (! SMALL_REGISTER_CLASSES
)
3987 /* ??? We are doing this here because of the potential
3988 that bad code may be generated if a register explicitly
3989 used in an insn was used as a spill register for that
3990 insn. But not using these are spill registers may lose
3991 on some machine. We'll have to see how this works out. */
3992 SET_HARD_REG_BIT (bad_spill_regs
, i
);
3995 hard_reg_n_uses
[HARD_FRAME_POINTER_REGNUM
].uses
+= 2 * large
+ 2;
3996 SET_HARD_REG_BIT (bad_spill_regs
, HARD_FRAME_POINTER_REGNUM
);
3998 #ifdef ELIMINABLE_REGS
3999 /* If registers other than the frame pointer are eliminable, mark them as
4001 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
4003 hard_reg_n_uses
[reg_eliminate
[i
].from
].uses
+= 2 * large
+ 2;
4004 SET_HARD_REG_BIT (bad_spill_regs
, reg_eliminate
[i
].from
);
4008 /* Prefer registers not so far used, for use in temporary loading.
4009 Among them, if REG_ALLOC_ORDER is defined, use that order.
4010 Otherwise, prefer registers not preserved by calls. */
4012 #ifdef REG_ALLOC_ORDER
4013 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4015 int regno
= reg_alloc_order
[i
];
4017 if (hard_reg_n_uses
[regno
].uses
== 0)
4018 potential_reload_regs
[o
++] = regno
;
4021 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4023 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
])
4024 potential_reload_regs
[o
++] = i
;
4026 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4028 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
])
4029 potential_reload_regs
[o
++] = i
;
4033 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
4034 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
4036 /* Now add the regs that are already used,
4037 preferring those used less often. The fixed and otherwise forbidden
4038 registers will be at the end of this list. */
4040 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4041 if (hard_reg_n_uses
[i
].uses
!= 0)
4042 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4045 /* Used in reload_as_needed to sort the spilled regs. */
4048 compare_spill_regs (r1p
, r2p
)
4049 const GENERIC_PTR r1p
;
4050 const GENERIC_PTR r2p
;
4052 short r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4056 /* Reload pseudo-registers into hard regs around each insn as needed.
4057 Additional register load insns are output before the insn that needs it
4058 and perhaps store insns after insns that modify the reloaded pseudo reg.
4060 reg_last_reload_reg and reg_reloaded_contents keep track of
4061 which registers are already available in reload registers.
4062 We update these for the reloads that we perform,
4063 as the insns are scanned. */
4066 reload_as_needed (first
, live_known
)
4076 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
4077 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
4078 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
4079 bzero ((char *) reg_last_reload_reg
, max_regno
* sizeof (rtx
));
4080 reg_has_output_reload
= (char *) alloca (max_regno
);
4081 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4083 /* Reset all offsets on eliminable registers to their initial values. */
4084 #ifdef ELIMINABLE_REGS
4085 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
4087 INITIAL_ELIMINATION_OFFSET (reg_eliminate
[i
].from
, reg_eliminate
[i
].to
,
4088 reg_eliminate
[i
].initial_offset
);
4089 reg_eliminate
[i
].previous_offset
4090 = reg_eliminate
[i
].offset
= reg_eliminate
[i
].initial_offset
;
4093 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
4094 reg_eliminate
[0].previous_offset
4095 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
4098 num_not_at_initial_offset
= 0;
4100 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4101 pack registers with group needs. */
4104 qsort (spill_regs
, n_spills
, sizeof (short), compare_spill_regs
);
4105 for (i
= 0; i
< n_spills
; i
++)
4106 spill_reg_order
[spill_regs
[i
]] = i
;
4109 for (insn
= first
; insn
;)
4111 register rtx next
= NEXT_INSN (insn
);
4113 /* Notice when we move to a new basic block. */
4114 if (live_known
&& this_block
+ 1 < n_basic_blocks
4115 && insn
== basic_block_head
[this_block
+1])
4118 /* If we pass a label, copy the offsets from the label information
4119 into the current offsets of each elimination. */
4120 if (GET_CODE (insn
) == CODE_LABEL
)
4122 num_not_at_initial_offset
= 0;
4123 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
4125 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
4126 = offsets_at
[CODE_LABEL_NUMBER (insn
)][i
];
4127 if (reg_eliminate
[i
].can_eliminate
4128 && (reg_eliminate
[i
].offset
4129 != reg_eliminate
[i
].initial_offset
))
4130 num_not_at_initial_offset
++;
4134 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
4136 rtx avoid_return_reg
= 0;
4137 rtx oldpat
= PATTERN (insn
);
4139 /* Set avoid_return_reg if this is an insn
4140 that might use the value of a function call. */
4141 if (SMALL_REGISTER_CLASSES
&& GET_CODE (insn
) == CALL_INSN
)
4143 if (GET_CODE (PATTERN (insn
)) == SET
)
4144 after_call
= SET_DEST (PATTERN (insn
));
4145 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
4146 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
4147 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
4151 else if (SMALL_REGISTER_CLASSES
&& after_call
!= 0
4152 && !(GET_CODE (PATTERN (insn
)) == SET
4153 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
)
4154 && GET_CODE (PATTERN (insn
)) != USE
)
4156 if (reg_referenced_p (after_call
, PATTERN (insn
)))
4157 avoid_return_reg
= after_call
;
4161 /* If this is a USE and CLOBBER of a MEM, ensure that any
4162 references to eliminable registers have been removed. */
4164 if ((GET_CODE (PATTERN (insn
)) == USE
4165 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4166 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
4167 XEXP (XEXP (PATTERN (insn
), 0), 0)
4168 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4169 GET_MODE (XEXP (PATTERN (insn
), 0)),
4172 /* If we need to do register elimination processing, do so.
4173 This might delete the insn, in which case we are done. */
4174 if (num_eliminable
&& GET_MODE (insn
) == QImode
)
4176 eliminate_regs_in_insn (insn
, 1);
4177 if (GET_CODE (insn
) == NOTE
)
4184 if (GET_MODE (insn
) == VOIDmode
)
4186 /* First find the pseudo regs that must be reloaded for this insn.
4187 This info is returned in the tables reload_... (see reload.h).
4188 Also modify the body of INSN by substituting RELOAD
4189 rtx's for those pseudo regs. */
4192 bzero (reg_has_output_reload
, max_regno
);
4193 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4195 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4201 rtx prev
= PREV_INSN (insn
), next
= NEXT_INSN (insn
);
4205 /* If this block has not had spilling done for a
4206 particular clas and we have any non-optionals that need a
4207 spill reg in that class, abort. */
4209 for (class = 0; class < N_REG_CLASSES
; class++)
4210 if (basic_block_needs
[class] != 0
4211 && basic_block_needs
[class][this_block
] == 0)
4212 for (i
= 0; i
< n_reloads
; i
++)
4213 if (class == (int) reload_reg_class
[i
]
4214 && reload_reg_rtx
[i
] == 0
4215 && ! reload_optional
[i
]
4216 && (reload_in
[i
] != 0 || reload_out
[i
] != 0
4217 || reload_secondary_p
[i
] != 0))
4218 fatal_insn ("Non-optional registers need a spill register", insn
);
4220 /* Now compute which reload regs to reload them into. Perhaps
4221 reusing reload regs from previous insns, or else output
4222 load insns to reload them. Maybe output store insns too.
4223 Record the choices of reload reg in reload_reg_rtx. */
4224 choose_reload_regs (insn
, avoid_return_reg
);
4226 /* Merge any reloads that we didn't combine for fear of
4227 increasing the number of spill registers needed but now
4228 discover can be safely merged. */
4229 if (SMALL_REGISTER_CLASSES
)
4230 merge_assigned_reloads (insn
);
4232 /* Generate the insns to reload operands into or out of
4233 their reload regs. */
4234 emit_reload_insns (insn
);
4236 /* Substitute the chosen reload regs from reload_reg_rtx
4237 into the insn's body (or perhaps into the bodies of other
4238 load and store insn that we just made for reloading
4239 and that we moved the structure into). */
4242 /* If this was an ASM, make sure that all the reload insns
4243 we have generated are valid. If not, give an error
4246 if (asm_noperands (PATTERN (insn
)) >= 0)
4247 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4248 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
4249 && (recog_memoized (p
) < 0
4250 || (insn_extract (p
),
4251 ! constrain_operands (INSN_CODE (p
), 1))))
4253 error_for_asm (insn
,
4254 "`asm' operand requires impossible reload");
4256 NOTE_SOURCE_FILE (p
) = 0;
4257 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
4260 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4261 is no longer validly lying around to save a future reload.
4262 Note that this does not detect pseudos that were reloaded
4263 for this insn in order to be stored in
4264 (obeying register constraints). That is correct; such reload
4265 registers ARE still valid. */
4266 note_stores (oldpat
, forget_old_reloads_1
);
4268 /* There may have been CLOBBER insns placed after INSN. So scan
4269 between INSN and NEXT and use them to forget old reloads. */
4270 for (x
= NEXT_INSN (insn
); x
!= next
; x
= NEXT_INSN (x
))
4271 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
4272 note_stores (PATTERN (x
), forget_old_reloads_1
);
4275 /* Likewise for regs altered by auto-increment in this insn.
4276 But note that the reg-notes are not changed by reloading:
4277 they still contain the pseudo-regs, not the spill regs. */
4278 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4279 if (REG_NOTE_KIND (x
) == REG_INC
)
4281 /* See if this pseudo reg was reloaded in this insn.
4282 If so, its last-reload info is still valid
4283 because it is based on this insn's reload. */
4284 for (i
= 0; i
< n_reloads
; i
++)
4285 if (reload_out
[i
] == XEXP (x
, 0))
4289 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
4293 /* A reload reg's contents are unknown after a label. */
4294 if (GET_CODE (insn
) == CODE_LABEL
)
4295 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4297 /* Don't assume a reload reg is still good after a call insn
4298 if it is a call-used reg. */
4299 else if (GET_CODE (insn
) == CALL_INSN
)
4300 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4302 /* In case registers overlap, allow certain insns to invalidate
4303 particular hard registers. */
4305 #ifdef INSN_CLOBBERS_REGNO_P
4306 for (i
= 0 ; i
< FIRST_PSEUDO_REGISTER
; i
++)
4307 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
4308 && INSN_CLOBBERS_REGNO_P (insn
, i
))
4309 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
);
4320 /* Discard all record of any value reloaded from X,
4321 or reloaded in X from someplace else;
4322 unless X is an output reload reg of the current insn.
4324 X may be a hard reg (the reload reg)
4325 or it may be a pseudo reg that was reloaded from. */
4328 forget_old_reloads_1 (x
, ignored
)
4330 rtx ignored ATTRIBUTE_UNUSED
;
4336 /* note_stores does give us subregs of hard regs. */
4337 while (GET_CODE (x
) == SUBREG
)
4339 offset
+= SUBREG_WORD (x
);
4343 if (GET_CODE (x
) != REG
)
4346 regno
= REGNO (x
) + offset
;
4348 if (regno
>= FIRST_PSEUDO_REGISTER
)
4353 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4354 /* Storing into a spilled-reg invalidates its contents.
4355 This can happen if a block-local pseudo is allocated to that reg
4356 and it wasn't spilled because this block's total need is 0.
4357 Then some insn might have an optional reload and use this reg. */
4358 for (i
= 0; i
< nr
; i
++)
4359 /* But don't do this if the reg actually serves as an output
4360 reload reg in the current instruction. */
4362 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4363 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4366 /* Since value of X has changed,
4367 forget any value previously copied from it. */
4370 /* But don't forget a copy if this is the output reload
4371 that establishes the copy's validity. */
4372 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4373 reg_last_reload_reg
[regno
+ nr
] = 0;
4376 /* For each reload, the mode of the reload register. */
4377 static enum machine_mode reload_mode
[MAX_RELOADS
];
4379 /* For each reload, the largest number of registers it will require. */
4380 static int reload_nregs
[MAX_RELOADS
];
4382 /* Comparison function for qsort to decide which of two reloads
4383 should be handled first. *P1 and *P2 are the reload numbers. */
4386 reload_reg_class_lower (r1p
, r2p
)
4387 const GENERIC_PTR r1p
;
4388 const GENERIC_PTR r2p
;
4390 register int r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4393 /* Consider required reloads before optional ones. */
4394 t
= reload_optional
[r1
] - reload_optional
[r2
];
4398 /* Count all solitary classes before non-solitary ones. */
4399 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
4400 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
4404 /* Aside from solitaires, consider all multi-reg groups first. */
4405 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
4409 /* Consider reloads in order of increasing reg-class number. */
4410 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
4414 /* If reloads are equally urgent, sort by reload number,
4415 so that the results of qsort leave nothing to chance. */
4419 /* The following HARD_REG_SETs indicate when each hard register is
4420 used for a reload of various parts of the current insn. */
4422 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4423 static HARD_REG_SET reload_reg_used
;
4424 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4425 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4426 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4427 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4428 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4429 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4430 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4431 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4432 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4433 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4434 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4435 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4436 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4437 static HARD_REG_SET reload_reg_used_in_op_addr
;
4438 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4439 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4440 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4441 static HARD_REG_SET reload_reg_used_in_insn
;
4442 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4443 static HARD_REG_SET reload_reg_used_in_other_addr
;
4445 /* If reg is in use as a reload reg for any sort of reload. */
4446 static HARD_REG_SET reload_reg_used_at_all
;
4448 /* If reg is use as an inherited reload. We just mark the first register
4450 static HARD_REG_SET reload_reg_used_for_inherit
;
4452 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4453 TYPE. MODE is used to indicate how many consecutive regs are
4457 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4460 enum reload_type type
;
4461 enum machine_mode mode
;
4463 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4466 for (i
= regno
; i
< nregs
+ regno
; i
++)
4471 SET_HARD_REG_BIT (reload_reg_used
, i
);
4474 case RELOAD_FOR_INPUT_ADDRESS
:
4475 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4478 case RELOAD_FOR_INPADDR_ADDRESS
:
4479 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4482 case RELOAD_FOR_OUTPUT_ADDRESS
:
4483 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4486 case RELOAD_FOR_OUTADDR_ADDRESS
:
4487 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4490 case RELOAD_FOR_OPERAND_ADDRESS
:
4491 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4494 case RELOAD_FOR_OPADDR_ADDR
:
4495 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4498 case RELOAD_FOR_OTHER_ADDRESS
:
4499 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4502 case RELOAD_FOR_INPUT
:
4503 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4506 case RELOAD_FOR_OUTPUT
:
4507 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4510 case RELOAD_FOR_INSN
:
4511 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4515 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4519 /* Similarly, but show REGNO is no longer in use for a reload. */
4522 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4525 enum reload_type type
;
4526 enum machine_mode mode
;
4528 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4531 for (i
= regno
; i
< nregs
+ regno
; i
++)
4536 CLEAR_HARD_REG_BIT (reload_reg_used
, i
);
4539 case RELOAD_FOR_INPUT_ADDRESS
:
4540 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4543 case RELOAD_FOR_INPADDR_ADDRESS
:
4544 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4547 case RELOAD_FOR_OUTPUT_ADDRESS
:
4548 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4551 case RELOAD_FOR_OUTADDR_ADDRESS
:
4552 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4555 case RELOAD_FOR_OPERAND_ADDRESS
:
4556 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4559 case RELOAD_FOR_OPADDR_ADDR
:
4560 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4563 case RELOAD_FOR_OTHER_ADDRESS
:
4564 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4567 case RELOAD_FOR_INPUT
:
4568 CLEAR_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4571 case RELOAD_FOR_OUTPUT
:
4572 CLEAR_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4575 case RELOAD_FOR_INSN
:
4576 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4582 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4583 specified by OPNUM and TYPE. */
4586 reload_reg_free_p (regno
, opnum
, type
)
4589 enum reload_type type
;
4593 /* In use for a RELOAD_OTHER means it's not available for anything. */
4594 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4600 /* In use for anything means we can't use it for RELOAD_OTHER. */
4601 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4602 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4603 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4606 for (i
= 0; i
< reload_n_operands
; i
++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4617 case RELOAD_FOR_INPUT
:
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4625 /* If it is used for some other input, can't use it. */
4626 for (i
= 0; i
< reload_n_operands
; i
++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4630 /* If it is used in a later operand's address, can't use it. */
4631 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4638 case RELOAD_FOR_INPUT_ADDRESS
:
4639 /* Can't use a register if it is used for an input address for this
4640 operand or used as an input in an earlier one. */
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4645 for (i
= 0; i
< opnum
; i
++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4651 case RELOAD_FOR_INPADDR_ADDRESS
:
4652 /* Can't use a register if it is used for an input address
4653 for this operand or used as an input in an earlier
4655 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4658 for (i
= 0; i
< opnum
; i
++)
4659 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4664 case RELOAD_FOR_OUTPUT_ADDRESS
:
4665 /* Can't use a register if it is used for an output address for this
4666 operand or used as an output in this or a later operand. */
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4670 for (i
= opnum
; i
< reload_n_operands
; i
++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4676 case RELOAD_FOR_OUTADDR_ADDRESS
:
4677 /* Can't use a register if it is used for an output address
4678 for this operand or used as an output in this or a
4680 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4683 for (i
= opnum
; i
< reload_n_operands
; i
++)
4684 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4689 case RELOAD_FOR_OPERAND_ADDRESS
:
4690 for (i
= 0; i
< reload_n_operands
; i
++)
4691 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4694 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4695 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4697 case RELOAD_FOR_OPADDR_ADDR
:
4698 for (i
= 0; i
< reload_n_operands
; i
++)
4699 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4702 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4704 case RELOAD_FOR_OUTPUT
:
4705 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4706 outputs, or an operand address for this or an earlier output. */
4707 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4710 for (i
= 0; i
< reload_n_operands
; i
++)
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4714 for (i
= 0; i
<= opnum
; i
++)
4715 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4716 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4721 case RELOAD_FOR_INSN
:
4722 for (i
= 0; i
< reload_n_operands
; i
++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4727 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4728 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4730 case RELOAD_FOR_OTHER_ADDRESS
:
4731 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4736 /* Return 1 if the value in reload reg REGNO, as used by a reload
4737 needed for the part of the insn specified by OPNUM and TYPE,
4738 is not in use for a reload in any prior part of the insn.
4740 We can assume that the reload reg was already tested for availability
4741 at the time it is needed, and we should not check this again,
4742 in case the reg has already been marked in use.
4744 However, if EQUIV is set, we are checking the availability of a register
4745 holding an equivalence to the value to be loaded into the reload register,
4746 not the availability of the reload register itself.
4748 This is still less stringent than what reload_reg_free_p checks; for
4749 example, compare the checks for RELOAD_OTHER. */
4752 reload_reg_free_before_p (regno
, opnum
, type
, equiv
)
4755 enum reload_type type
;
4762 case RELOAD_FOR_OTHER_ADDRESS
:
4763 /* These always come first. */
4764 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
))
4769 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4771 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4773 /* If this use is for part of the insn,
4774 check the reg is not in use for any prior part. It is tempting
4775 to try to do this by falling through from objecs that occur
4776 later in the insn to ones that occur earlier, but that will not
4777 correctly take into account the fact that here we MUST ignore
4778 things that would prevent the register from being allocated in
4779 the first place, since we know that it was allocated. */
4781 case RELOAD_FOR_OUTPUT_ADDRESS
:
4783 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4785 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4786 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4788 /* ... fall through ... */
4789 case RELOAD_FOR_OUTADDR_ADDRESS
:
4791 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
)
4792 || TEST_HARD_REG_BIT (reload_reg_used
, regno
)))
4794 /* Earlier reloads are for earlier outputs or their addresses,
4795 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4796 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4798 for (i
= 0; i
< opnum
; i
++)
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4803 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4806 for (i
= 0; i
< reload_n_operands
; i
++)
4807 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4809 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4813 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4814 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4815 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4816 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4818 case RELOAD_FOR_OUTPUT
:
4819 case RELOAD_FOR_INSN
:
4820 /* There is no reason to call this function for output reloads, thus
4821 anything we'd put here wouldn't be tested. So just abort. */
4824 case RELOAD_FOR_OPERAND_ADDRESS
:
4825 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4828 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4829 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4832 /* ... fall through ... */
4834 case RELOAD_FOR_OPADDR_ADDR
:
4837 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4838 || TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4840 for (i
= 0; i
< reload_n_operands
; i
++)
4841 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4844 /* These can't conflict with inputs, or each other, so all we have to
4845 test is input addresses and the addresses of OTHER items. */
4847 for (i
= 0; i
< reload_n_operands
; i
++)
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4849 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4852 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4854 case RELOAD_FOR_INPUT
:
4855 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4858 /* The only things earlier are the address for this and
4859 earlier inputs, other inputs (which we know we don't conflict
4860 with), and addresses of RELOAD_OTHER objects. */
4862 for (i
= 0; i
<= opnum
; i
++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4867 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4869 case RELOAD_FOR_INPUT_ADDRESS
:
4870 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4871 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4873 /* ... fall through ... */
4874 case RELOAD_FOR_INPADDR_ADDRESS
:
4875 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4878 /* Similarly, all we have to check is for use in earlier inputs'
4880 for (i
= 0; i
< opnum
; i
++)
4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4882 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4885 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4890 /* Return 1 if the value in reload reg REGNO, as used by a reload
4891 needed for the part of the insn specified by OPNUM and TYPE,
4892 is still available in REGNO at the end of the insn.
4894 We can assume that the reload reg was already tested for availability
4895 at the time it is needed, and we should not check this again,
4896 in case the reg has already been marked in use. */
4899 reload_reg_reaches_end_p (regno
, opnum
, type
)
4902 enum reload_type type
;
4909 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4910 its value must reach the end. */
4913 /* If this use is for part of the insn,
4914 its value reaches if no subsequent part uses the same register.
4915 Just like the above function, don't try to do this with lots
4918 case RELOAD_FOR_OTHER_ADDRESS
:
4919 /* Here we check for everything else, since these don't conflict
4920 with anything else and everything comes later. */
4922 for (i
= 0; i
< reload_n_operands
; i
++)
4923 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4924 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4925 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4926 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4927 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4928 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4931 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4932 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4933 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4935 case RELOAD_FOR_INPUT_ADDRESS
:
4936 case RELOAD_FOR_INPADDR_ADDRESS
:
4937 /* Similar, except that we check only for this and subsequent inputs
4938 and the address of only subsequent inputs and we do not need
4939 to check for RELOAD_OTHER objects since they are known not to
4942 for (i
= opnum
; i
< reload_n_operands
; i
++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4946 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4947 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4948 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4951 for (i
= 0; i
< reload_n_operands
; i
++)
4952 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4953 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4954 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4957 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4960 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4961 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4963 case RELOAD_FOR_INPUT
:
4964 /* Similar to input address, except we start at the next operand for
4965 both input and input address and we do not check for
4966 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4969 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4970 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4971 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4972 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4975 /* ... fall through ... */
4977 case RELOAD_FOR_OPERAND_ADDRESS
:
4978 /* Check outputs and their addresses. */
4980 for (i
= 0; i
< reload_n_operands
; i
++)
4981 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4982 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4983 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4988 case RELOAD_FOR_OPADDR_ADDR
:
4989 for (i
= 0; i
< reload_n_operands
; i
++)
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4995 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4996 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4998 case RELOAD_FOR_INSN
:
4999 /* These conflict with other outputs with RELOAD_OTHER. So
5000 we need only check for output addresses. */
5004 /* ... fall through ... */
5006 case RELOAD_FOR_OUTPUT
:
5007 case RELOAD_FOR_OUTPUT_ADDRESS
:
5008 case RELOAD_FOR_OUTADDR_ADDRESS
:
5009 /* We already know these can't conflict with a later output. So the
5010 only thing to check are later output addresses. */
5011 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5022 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5025 This function uses the same algorithm as reload_reg_free_p above. */
5028 reloads_conflict (r1
, r2
)
5031 enum reload_type r1_type
= reload_when_needed
[r1
];
5032 enum reload_type r2_type
= reload_when_needed
[r2
];
5033 int r1_opnum
= reload_opnum
[r1
];
5034 int r2_opnum
= reload_opnum
[r2
];
5036 /* RELOAD_OTHER conflicts with everything. */
5037 if (r2_type
== RELOAD_OTHER
)
5040 /* Otherwise, check conflicts differently for each type. */
5044 case RELOAD_FOR_INPUT
:
5045 return (r2_type
== RELOAD_FOR_INSN
5046 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5047 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5048 || r2_type
== RELOAD_FOR_INPUT
5049 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5050 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5051 && r2_opnum
> r1_opnum
));
5053 case RELOAD_FOR_INPUT_ADDRESS
:
5054 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5055 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5057 case RELOAD_FOR_INPADDR_ADDRESS
:
5058 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5059 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5061 case RELOAD_FOR_OUTPUT_ADDRESS
:
5062 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5063 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5065 case RELOAD_FOR_OUTADDR_ADDRESS
:
5066 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5067 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5069 case RELOAD_FOR_OPERAND_ADDRESS
:
5070 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5071 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5073 case RELOAD_FOR_OPADDR_ADDR
:
5074 return (r2_type
== RELOAD_FOR_INPUT
5075 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5077 case RELOAD_FOR_OUTPUT
:
5078 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5079 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5080 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5081 && r2_opnum
>= r1_opnum
));
5083 case RELOAD_FOR_INSN
:
5084 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5085 || r2_type
== RELOAD_FOR_INSN
5086 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5088 case RELOAD_FOR_OTHER_ADDRESS
:
5089 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5099 /* Vector of reload-numbers showing the order in which the reloads should
5101 short reload_order
[MAX_RELOADS
];
5103 /* Indexed by reload number, 1 if incoming value
5104 inherited from previous insns. */
5105 char reload_inherited
[MAX_RELOADS
];
5107 /* For an inherited reload, this is the insn the reload was inherited from,
5108 if we know it. Otherwise, this is 0. */
5109 rtx reload_inheritance_insn
[MAX_RELOADS
];
5111 /* If non-zero, this is a place to get the value of the reload,
5112 rather than using reload_in. */
5113 rtx reload_override_in
[MAX_RELOADS
];
5115 /* For each reload, the hard register number of the register used,
5116 or -1 if we did not need a register for this reload. */
5117 int reload_spill_index
[MAX_RELOADS
];
5119 /* Return 1 if the value in reload reg REGNO, as used by a reload
5120 needed for the part of the insn specified by OPNUM and TYPE,
5121 may be used to load VALUE into it.
5123 Other read-only reloads with the same value do not conflict
5124 unless OUT is non-zero and these other reloads have to live while
5125 output reloads live.
5127 RELOADNUM is the number of the reload we want to load this value for;
5128 a reload does not conflict with itself.
5130 The caller has to make sure that there is no conflict with the return
5133 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
)
5136 enum reload_type type
;
5143 /* We use some pseudo 'time' value to check if the lifetimes of the
5144 new register use would overlap with the one of a previous reload
5145 that is not read-only or uses a different value.
5146 The 'time' used doesn't have to be linear in any shape or form, just
5148 Some reload types use different 'buckets' for each operand.
5149 So there are MAX_RECOG_OPERANDS different time values for each
5151 We compute TIME1 as the time when the register for the prospective
5152 new reload ceases to be live, and TIME2 for each existing
5153 reload as the time when that the reload register of that reload
5155 Where there is little to be gained by exact lifetime calculations,
5156 we just make conservative assumptions, i.e. a longer lifetime;
5157 this is done in the 'default:' cases. */
5160 case RELOAD_FOR_OTHER_ADDRESS
:
5163 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5164 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5165 respectively, to the time values for these, we get distinct time
5166 values. To get distinct time values for each operand, we have to
5167 multiply opnum by at least three. We round that up to four because
5168 multiply by four is often cheaper. */
5169 case RELOAD_FOR_INPADDR_ADDRESS
:
5170 time1
= opnum
* 4 + 1;
5172 case RELOAD_FOR_INPUT_ADDRESS
:
5173 time1
= opnum
* 4 + 2;
5175 case RELOAD_FOR_INPUT
:
5176 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5177 instruction is executed. */
5178 time1
= (MAX_RECOG_OPERANDS
- 1) * 4 + 3;
5180 /* opnum * 4 + 3 < opnum * 4 + 4
5181 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5182 case RELOAD_FOR_OUTPUT_ADDRESS
:
5183 time1
= MAX_RECOG_OPERANDS
* 4 + opnum
;
5186 time1
= MAX_RECOG_OPERANDS
* 5;
5189 for (i
= 0; i
< n_reloads
; i
++)
5191 rtx reg
= reload_reg_rtx
[i
];
5192 if (reg
&& GET_CODE (reg
) == REG
5193 && ((unsigned) regno
- true_regnum (reg
)
5194 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
5198 && reload_when_needed
[i
] != RELOAD_FOR_INPUT
5199 && reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
5200 && reload_when_needed
[i
] != RELOAD_FOR_INPADDR_ADDRESS
)
5202 if (! reload_in
[i
] || ! rtx_equal_p (reload_in
[i
], value
)
5206 switch (reload_when_needed
[i
])
5208 case RELOAD_FOR_OTHER_ADDRESS
:
5211 case RELOAD_FOR_INPADDR_ADDRESS
:
5212 time2
= reload_opnum
[i
] * 4 + 1;
5214 case RELOAD_FOR_INPUT_ADDRESS
:
5215 time2
= reload_opnum
[i
] * 4 + 2;
5217 case RELOAD_FOR_INPUT
:
5218 time2
= reload_opnum
[i
] * 4 + 3;
5220 case RELOAD_FOR_OUTPUT
:
5221 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5222 instruction is executed. */
5223 time2
= MAX_RECOG_OPERANDS
* 4;
5225 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5226 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5227 case RELOAD_FOR_OUTPUT_ADDRESS
:
5228 time2
= MAX_RECOG_OPERANDS
* 4 + reload_opnum
[i
];
5231 if (! reload_in
[i
] || rtx_equal_p (reload_in
[i
], value
))
5233 time2
= MAX_RECOG_OPERANDS
* 4;
5247 /* Find a spill register to use as a reload register for reload R.
5248 LAST_RELOAD is non-zero if this is the last reload for the insn being
5251 Set reload_reg_rtx[R] to the register allocated.
5253 If NOERROR is nonzero, we return 1 if successful,
5254 or 0 if we couldn't find a spill reg and we didn't change anything. */
5257 allocate_reload_reg (r
, insn
, last_reload
, noerror
)
5269 /* If we put this reload ahead, thinking it is a group,
5270 then insist on finding a group. Otherwise we can grab a
5271 reg that some other reload needs.
5272 (That can happen when we have a 68000 DATA_OR_FP_REG
5273 which is a group of data regs or one fp reg.)
5274 We need not be so restrictive if there are no more reloads
5277 ??? Really it would be nicer to have smarter handling
5278 for that kind of reg class, where a problem like this is normal.
5279 Perhaps those classes should be avoided for reloading
5280 by use of more alternatives. */
5282 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
5284 /* If we want a single register and haven't yet found one,
5285 take any reg in the right class and not in use.
5286 If we want a consecutive group, here is where we look for it.
5288 We use two passes so we can first look for reload regs to
5289 reuse, which are already in use for other reloads in this insn,
5290 and only then use additional registers.
5291 I think that maximizing reuse is needed to make sure we don't
5292 run out of reload regs. Suppose we have three reloads, and
5293 reloads A and B can share regs. These need two regs.
5294 Suppose A and B are given different regs.
5295 That leaves none for C. */
5296 for (pass
= 0; pass
< 2; pass
++)
5298 /* I is the index in spill_regs.
5299 We advance it round-robin between insns to use all spill regs
5300 equally, so that inherited reloads have a chance
5301 of leapfrogging each other. Don't do this, however, when we have
5302 group needs and failure would be fatal; if we only have a relatively
5303 small number of spill registers, and more than one of them has
5304 group needs, then by starting in the middle, we may end up
5305 allocating the first one in such a way that we are not left with
5306 sufficient groups to handle the rest. */
5308 if (noerror
|| ! force_group
)
5313 for (count
= 0; count
< n_spills
; count
++)
5315 int class = (int) reload_reg_class
[r
];
5317 i
= (i
+ 1) % n_spills
;
5319 if ((reload_reg_free_p (spill_regs
[i
], reload_opnum
[r
],
5320 reload_when_needed
[r
])
5322 /* We check reload_reg_used to make sure we
5323 don't clobber the return register. */
5324 && ! TEST_HARD_REG_BIT (reload_reg_used
, spill_regs
[i
])
5325 && reload_reg_free_for_value_p (spill_regs
[i
],
5327 reload_when_needed
[r
],
5330 && TEST_HARD_REG_BIT (reg_class_contents
[class], spill_regs
[i
])
5331 && HARD_REGNO_MODE_OK (spill_regs
[i
], reload_mode
[r
])
5332 /* Look first for regs to share, then for unshared. But
5333 don't share regs used for inherited reloads; they are
5334 the ones we want to preserve. */
5336 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5338 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5341 int nr
= HARD_REGNO_NREGS (spill_regs
[i
], reload_mode
[r
]);
5342 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5343 (on 68000) got us two FP regs. If NR is 1,
5344 we would reject both of them. */
5346 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
5347 /* If we need only one reg, we have already won. */
5350 /* But reject a single reg if we demand a group. */
5355 /* Otherwise check that as many consecutive regs as we need
5357 Also, don't use for a group registers that are
5358 needed for nongroups. */
5359 if (! TEST_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]))
5362 regno
= spill_regs
[i
] + nr
- 1;
5363 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5364 && spill_reg_order
[regno
] >= 0
5365 && reload_reg_free_p (regno
, reload_opnum
[r
],
5366 reload_when_needed
[r
])
5367 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
5377 /* If we found something on pass 1, omit pass 2. */
5378 if (count
< n_spills
)
5382 /* We should have found a spill register by now. */
5383 if (count
== n_spills
)
5390 /* I is the index in SPILL_REG_RTX of the reload register we are to
5391 allocate. Get an rtx for it and find its register number. */
5393 new = spill_reg_rtx
[i
];
5395 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
5396 spill_reg_rtx
[i
] = new
5397 = gen_rtx_REG (reload_mode
[r
], spill_regs
[i
]);
5399 regno
= true_regnum (new);
5401 /* Detect when the reload reg can't hold the reload mode.
5402 This used to be one `if', but Sequent compiler can't handle that. */
5403 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5405 enum machine_mode test_mode
= VOIDmode
;
5407 test_mode
= GET_MODE (reload_in
[r
]);
5408 /* If reload_in[r] has VOIDmode, it means we will load it
5409 in whatever mode the reload reg has: to wit, reload_mode[r].
5410 We have already tested that for validity. */
5411 /* Aside from that, we need to test that the expressions
5412 to reload from or into have modes which are valid for this
5413 reload register. Otherwise the reload insns would be invalid. */
5414 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
5415 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5416 if (! (reload_out
[r
] != 0
5417 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
5419 /* The reg is OK. */
5422 /* Mark as in use for this insn the reload regs we use
5424 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
5425 reload_when_needed
[r
], reload_mode
[r
]);
5427 reload_reg_rtx
[r
] = new;
5428 reload_spill_index
[r
] = spill_regs
[i
];
5433 /* The reg is not OK. */
5438 if (asm_noperands (PATTERN (insn
)) < 0)
5439 /* It's the compiler's fault. */
5440 fatal_insn ("Could not find a spill register", insn
);
5442 /* It's the user's fault; the operand's mode and constraint
5443 don't match. Disable this reload so we don't crash in final. */
5444 error_for_asm (insn
,
5445 "`asm' operand constraint incompatible with operand size");
5448 reload_reg_rtx
[r
] = 0;
5449 reload_optional
[r
] = 1;
5450 reload_secondary_p
[r
] = 1;
5455 /* Assign hard reg targets for the pseudo-registers we must reload
5456 into hard regs for this insn.
5457 Also output the instructions to copy them in and out of the hard regs.
5459 For machines with register classes, we are responsible for
5460 finding a reload reg in the proper class. */
5463 choose_reload_regs (insn
, avoid_return_reg
)
5465 rtx avoid_return_reg
;
5468 int max_group_size
= 1;
5469 enum reg_class group_class
= NO_REGS
;
5472 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5473 char save_reload_inherited
[MAX_RELOADS
];
5474 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
5475 rtx save_reload_override_in
[MAX_RELOADS
];
5476 int save_reload_spill_index
[MAX_RELOADS
];
5477 HARD_REG_SET save_reload_reg_used
;
5478 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5479 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5480 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5481 HARD_REG_SET save_reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5482 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5483 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5484 HARD_REG_SET save_reload_reg_used_in_op_addr
;
5485 HARD_REG_SET save_reload_reg_used_in_op_addr_reload
;
5486 HARD_REG_SET save_reload_reg_used_in_insn
;
5487 HARD_REG_SET save_reload_reg_used_in_other_addr
;
5488 HARD_REG_SET save_reload_reg_used_at_all
;
5490 bzero (reload_inherited
, MAX_RELOADS
);
5491 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5492 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5494 CLEAR_HARD_REG_SET (reload_reg_used
);
5495 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5496 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5497 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5498 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5499 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5501 for (i
= 0; i
< reload_n_operands
; i
++)
5503 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5504 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5505 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5506 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5507 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5508 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5511 /* Don't bother with avoiding the return reg
5512 if we have no mandatory reload that could use it. */
5513 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
5516 int regno
= REGNO (avoid_return_reg
);
5518 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
5521 for (r
= regno
; r
< regno
+ nregs
; r
++)
5522 if (spill_reg_order
[r
] >= 0)
5523 for (j
= 0; j
< n_reloads
; j
++)
5524 if (!reload_optional
[j
] && reload_reg_rtx
[j
] == 0
5525 && (reload_in
[j
] != 0 || reload_out
[j
] != 0
5526 || reload_secondary_p
[j
])
5528 TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[j
]], r
))
5531 avoid_return_reg
= 0;
5534 #if 0 /* Not needed, now that we can always retry without inheritance. */
5535 /* See if we have more mandatory reloads than spill regs.
5536 If so, then we cannot risk optimizations that could prevent
5537 reloads from sharing one spill register.
5539 Since we will try finding a better register than reload_reg_rtx
5540 unless it is equal to reload_in or reload_out, count such reloads. */
5543 int tem
= SMALL_REGISTER_CLASSES
? (avoid_return_reg
!= 0): 0;
5544 for (j
= 0; j
< n_reloads
; j
++)
5545 if (! reload_optional
[j
]
5546 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
5547 && (reload_reg_rtx
[j
] == 0
5548 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
5549 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
5556 /* Don't use the subroutine call return reg for a reload
5557 if we are supposed to avoid it. */
5558 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
5560 int regno
= REGNO (avoid_return_reg
);
5562 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
5565 for (r
= regno
; r
< regno
+ nregs
; r
++)
5566 if (spill_reg_order
[r
] >= 0)
5567 SET_HARD_REG_BIT (reload_reg_used
, r
);
5570 /* In order to be certain of getting the registers we need,
5571 we must sort the reloads into order of increasing register class.
5572 Then our grabbing of reload registers will parallel the process
5573 that provided the reload registers.
5575 Also note whether any of the reloads wants a consecutive group of regs.
5576 If so, record the maximum size of the group desired and what
5577 register class contains all the groups needed by this insn. */
5579 for (j
= 0; j
< n_reloads
; j
++)
5581 reload_order
[j
] = j
;
5582 reload_spill_index
[j
] = -1;
5585 = (reload_inmode
[j
] == VOIDmode
5586 || (GET_MODE_SIZE (reload_outmode
[j
])
5587 > GET_MODE_SIZE (reload_inmode
[j
])))
5588 ? reload_outmode
[j
] : reload_inmode
[j
];
5590 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
5592 if (reload_nregs
[j
] > 1)
5594 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
5595 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
5598 /* If we have already decided to use a certain register,
5599 don't use it in another way. */
5600 if (reload_reg_rtx
[j
])
5601 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
5602 reload_when_needed
[j
], reload_mode
[j
]);
5606 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5608 bcopy ((char *) reload_reg_rtx
, (char *) save_reload_reg_rtx
,
5609 sizeof reload_reg_rtx
);
5610 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
5611 bcopy ((char *) reload_inheritance_insn
,
5612 (char *) save_reload_inheritance_insn
,
5613 sizeof reload_inheritance_insn
);
5614 bcopy ((char *) reload_override_in
, (char *) save_reload_override_in
,
5615 sizeof reload_override_in
);
5616 bcopy ((char *) reload_spill_index
, (char *) save_reload_spill_index
,
5617 sizeof reload_spill_index
);
5618 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
5619 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
5620 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
5621 reload_reg_used_in_op_addr
);
5623 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload
,
5624 reload_reg_used_in_op_addr_reload
);
5626 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
5627 reload_reg_used_in_insn
);
5628 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
5629 reload_reg_used_in_other_addr
);
5631 for (i
= 0; i
< reload_n_operands
; i
++)
5633 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
5634 reload_reg_used_in_output
[i
]);
5635 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
5636 reload_reg_used_in_input
[i
]);
5637 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
5638 reload_reg_used_in_input_addr
[i
]);
5639 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr
[i
],
5640 reload_reg_used_in_inpaddr_addr
[i
]);
5641 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
5642 reload_reg_used_in_output_addr
[i
]);
5643 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr
[i
],
5644 reload_reg_used_in_outaddr_addr
[i
]);
5647 /* If -O, try first with inheritance, then turning it off.
5648 If not -O, don't do inheritance.
5649 Using inheritance when not optimizing leads to paradoxes
5650 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5651 because one side of the comparison might be inherited. */
5653 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5655 /* Process the reloads in order of preference just found.
5656 Beyond this point, subregs can be found in reload_reg_rtx.
5658 This used to look for an existing reloaded home for all
5659 of the reloads, and only then perform any new reloads.
5660 But that could lose if the reloads were done out of reg-class order
5661 because a later reload with a looser constraint might have an old
5662 home in a register needed by an earlier reload with a tighter constraint.
5664 To solve this, we make two passes over the reloads, in the order
5665 described above. In the first pass we try to inherit a reload
5666 from a previous insn. If there is a later reload that needs a
5667 class that is a proper subset of the class being processed, we must
5668 also allocate a spill register during the first pass.
5670 Then make a second pass over the reloads to allocate any reloads
5671 that haven't been given registers yet. */
5673 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5675 for (j
= 0; j
< n_reloads
; j
++)
5677 register int r
= reload_order
[j
];
5679 /* Ignore reloads that got marked inoperative. */
5680 if (reload_out
[r
] == 0 && reload_in
[r
] == 0
5681 && ! reload_secondary_p
[r
])
5684 /* If find_reloads chose a to use reload_in or reload_out as a reload
5685 register, we don't need to chose one. Otherwise, try even if it
5686 found one since we might save an insn if we find the value lying
5688 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
5689 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
5690 || rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])))
5693 #if 0 /* No longer needed for correct operation.
5694 It might give better code, or might not; worth an experiment? */
5695 /* If this is an optional reload, we can't inherit from earlier insns
5696 until we are sure that any non-optional reloads have been allocated.
5697 The following code takes advantage of the fact that optional reloads
5698 are at the end of reload_order. */
5699 if (reload_optional
[r
] != 0)
5700 for (i
= 0; i
< j
; i
++)
5701 if ((reload_out
[reload_order
[i
]] != 0
5702 || reload_in
[reload_order
[i
]] != 0
5703 || reload_secondary_p
[reload_order
[i
]])
5704 && ! reload_optional
[reload_order
[i
]]
5705 && reload_reg_rtx
[reload_order
[i
]] == 0)
5706 allocate_reload_reg (reload_order
[i
], insn
, 0, inheritance
);
5709 /* First see if this pseudo is already available as reloaded
5710 for a previous insn. We cannot try to inherit for reloads
5711 that are smaller than the maximum number of registers needed
5712 for groups unless the register we would allocate cannot be used
5715 We could check here to see if this is a secondary reload for
5716 an object that is already in a register of the desired class.
5717 This would avoid the need for the secondary reload register.
5718 But this is complex because we can't easily determine what
5719 objects might want to be loaded via this reload. So let a
5720 register be allocated here. In `emit_reload_insns' we suppress
5721 one of the loads in the case described above. */
5725 register int regno
= -1;
5726 enum machine_mode mode
;
5728 if (reload_in
[r
] == 0)
5730 else if (GET_CODE (reload_in
[r
]) == REG
)
5732 regno
= REGNO (reload_in
[r
]);
5733 mode
= GET_MODE (reload_in
[r
]);
5735 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
5737 regno
= REGNO (reload_in_reg
[r
]);
5738 mode
= GET_MODE (reload_in_reg
[r
]);
5740 else if (GET_CODE (reload_in
[r
]) == MEM
)
5742 rtx prev
= prev_nonnote_insn (insn
), note
;
5744 if (prev
&& GET_CODE (prev
) == INSN
5745 && GET_CODE (PATTERN (prev
)) == USE
5746 && GET_CODE (XEXP (PATTERN (prev
), 0)) == REG
5747 && (REGNO (XEXP (PATTERN (prev
), 0))
5748 >= FIRST_PSEUDO_REGISTER
)
5749 && (note
= find_reg_note (prev
, REG_EQUAL
, NULL_RTX
))
5750 && GET_CODE (XEXP (note
, 0)) == MEM
)
5752 rtx addr
= XEXP (XEXP (note
, 0), 0);
5754 = (GET_MODE_SIZE (GET_MODE (addr
))
5755 - GET_MODE_SIZE (GET_MODE (reload_in
[r
])));
5757 && rtx_equal_p ((BYTES_BIG_ENDIAN
5758 ? plus_constant (addr
, size_diff
)
5760 XEXP (reload_in
[r
], 0)))
5762 regno
= REGNO (XEXP (PATTERN (prev
), 0));
5763 mode
= GET_MODE (reload_in
[r
]);
5768 /* This won't work, since REGNO can be a pseudo reg number.
5769 Also, it takes much more hair to keep track of all the things
5770 that can invalidate an inherited reload of part of a pseudoreg. */
5771 else if (GET_CODE (reload_in
[r
]) == SUBREG
5772 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
5773 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
5776 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5778 i
= REGNO (reg_last_reload_reg
[regno
]);
5780 if (reg_reloaded_contents
[i
] == regno
5781 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5782 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
5783 >= GET_MODE_SIZE (mode
))
5784 && HARD_REGNO_MODE_OK (i
, reload_mode
[r
])
5785 && TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5787 && (reload_nregs
[r
] == max_group_size
5788 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5790 && ((reload_reg_free_p (i
, reload_opnum
[r
],
5791 reload_when_needed
[r
])
5792 && reload_reg_free_before_p (i
, reload_opnum
[r
],
5793 reload_when_needed
[r
],
5795 || reload_reg_free_for_value_p (i
, reload_opnum
[r
],
5796 reload_when_needed
[r
],
5800 /* If a group is needed, verify that all the subsequent
5801 registers still have their values intact. */
5803 = HARD_REGNO_NREGS (i
, reload_mode
[r
]);
5806 for (k
= 1; k
< nr
; k
++)
5807 if (reg_reloaded_contents
[i
+ k
] != regno
5808 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5815 /* We found a register that contains the
5816 value we need. If this register is the
5817 same as an `earlyclobber' operand of the
5818 current insn, just mark it as a place to
5819 reload from since we can't use it as the
5820 reload register itself. */
5822 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5823 if (reg_overlap_mentioned_for_reload_p
5824 (reg_last_reload_reg
[regno
],
5825 reload_earlyclobbers
[i1
]))
5828 if (i1
!= n_earlyclobbers
5829 /* Don't use it if we'd clobber a pseudo reg. */
5830 || (spill_reg_order
[i
] < 0
5832 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5833 /* Don't really use the inherited spill reg
5834 if we need it wider than we've got it. */
5835 || (GET_MODE_SIZE (reload_mode
[r
])
5836 > GET_MODE_SIZE (mode
)))
5837 reload_override_in
[r
] = reg_last_reload_reg
[regno
];
5841 /* We can use this as a reload reg. */
5842 /* Mark the register as in use for this part of
5844 mark_reload_reg_in_use (i
,
5846 reload_when_needed
[r
],
5848 reload_reg_rtx
[r
] = reg_last_reload_reg
[regno
];
5849 reload_inherited
[r
] = 1;
5850 reload_inheritance_insn
[r
]
5851 = reg_reloaded_insn
[i
];
5852 reload_spill_index
[r
] = i
;
5853 for (k
= 0; k
< nr
; k
++)
5854 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5862 /* Here's another way to see if the value is already lying around. */
5864 && reload_in
[r
] != 0
5865 && ! reload_inherited
[r
]
5866 && reload_out
[r
] == 0
5867 && (CONSTANT_P (reload_in
[r
])
5868 || GET_CODE (reload_in
[r
]) == PLUS
5869 || GET_CODE (reload_in
[r
]) == REG
5870 || GET_CODE (reload_in
[r
]) == MEM
)
5871 && (reload_nregs
[r
] == max_group_size
5872 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
5875 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
5876 -1, NULL_PTR
, 0, reload_mode
[r
]);
5881 if (GET_CODE (equiv
) == REG
)
5882 regno
= REGNO (equiv
);
5883 else if (GET_CODE (equiv
) == SUBREG
)
5885 /* This must be a SUBREG of a hard register.
5886 Make a new REG since this might be used in an
5887 address and not all machines support SUBREGs
5889 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
5890 equiv
= gen_rtx_REG (reload_mode
[r
], regno
);
5896 /* If we found a spill reg, reject it unless it is free
5897 and of the desired class. */
5899 && ((spill_reg_order
[regno
] >= 0
5900 && ! (reload_reg_free_before_p (regno
, reload_opnum
[r
],
5901 reload_when_needed
[r
], 1)
5902 || reload_reg_free_for_value_p (regno
,
5904 reload_when_needed
[r
],
5907 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5911 if (equiv
!= 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
))
5914 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5917 /* We found a register that contains the value we need.
5918 If this register is the same as an `earlyclobber' operand
5919 of the current insn, just mark it as a place to reload from
5920 since we can't use it as the reload register itself. */
5923 for (i
= 0; i
< n_earlyclobbers
; i
++)
5924 if (reg_overlap_mentioned_for_reload_p (equiv
,
5925 reload_earlyclobbers
[i
]))
5927 reload_override_in
[r
] = equiv
;
5932 /* If the equiv register we have found is explicitly clobbered
5933 in the current insn, it depends on the reload type if we
5934 can use it, use it for reload_override_in, or not at all.
5935 In particular, we then can't use EQUIV for a
5936 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5938 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
5940 switch (reload_when_needed
[r
])
5942 case RELOAD_FOR_OTHER_ADDRESS
:
5943 case RELOAD_FOR_INPADDR_ADDRESS
:
5944 case RELOAD_FOR_INPUT_ADDRESS
:
5945 case RELOAD_FOR_OPADDR_ADDR
:
5948 case RELOAD_FOR_INPUT
:
5949 case RELOAD_FOR_OPERAND_ADDRESS
:
5950 reload_override_in
[r
] = equiv
;
5958 /* If we found an equivalent reg, say no code need be generated
5959 to load it, and use it as our reload reg. */
5960 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5962 int nr
= HARD_REGNO_NREGS (regno
, reload_mode
[r
]);
5964 reload_reg_rtx
[r
] = equiv
;
5965 reload_inherited
[r
] = 1;
5967 /* If reg_reloaded_valid is not set for this register,
5968 there might be a stale spill_reg_store lying around.
5969 We must clear it, since otherwise emit_reload_insns
5970 might delete the store. */
5971 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5972 spill_reg_store
[regno
] = NULL_RTX
;
5973 /* If any of the hard registers in EQUIV are spill
5974 registers, mark them as in use for this insn. */
5975 for (k
= 0; k
< nr
; k
++)
5977 i
= spill_reg_order
[regno
+ k
];
5980 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
5981 reload_when_needed
[r
],
5983 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5990 /* If we found a register to use already, or if this is an optional
5991 reload, we are done. */
5992 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
5995 #if 0 /* No longer needed for correct operation. Might or might not
5996 give better code on the average. Want to experiment? */
5998 /* See if there is a later reload that has a class different from our
5999 class that intersects our class or that requires less register
6000 than our reload. If so, we must allocate a register to this
6001 reload now, since that reload might inherit a previous reload
6002 and take the only available register in our class. Don't do this
6003 for optional reloads since they will force all previous reloads
6004 to be allocated. Also don't do this for reloads that have been
6007 for (i
= j
+ 1; i
< n_reloads
; i
++)
6009 int s
= reload_order
[i
];
6011 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
6012 && ! reload_secondary_p
[s
])
6013 || reload_optional
[s
])
6016 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
6017 && reg_classes_intersect_p (reload_reg_class
[r
],
6018 reload_reg_class
[s
]))
6019 || reload_nregs
[s
] < reload_nregs
[r
])
6026 allocate_reload_reg (r
, insn
, j
== n_reloads
- 1, inheritance
);
6030 /* Now allocate reload registers for anything non-optional that
6031 didn't get one yet. */
6032 for (j
= 0; j
< n_reloads
; j
++)
6034 register int r
= reload_order
[j
];
6036 /* Ignore reloads that got marked inoperative. */
6037 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
6040 /* Skip reloads that already have a register allocated or are
6042 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
6045 if (! allocate_reload_reg (r
, insn
, j
== n_reloads
- 1, inheritance
))
6049 /* If that loop got all the way, we have won. */
6054 /* Loop around and try without any inheritance. */
6055 /* First undo everything done by the failed attempt
6056 to allocate with inheritance. */
6057 bcopy ((char *) save_reload_reg_rtx
, (char *) reload_reg_rtx
,
6058 sizeof reload_reg_rtx
);
6059 bcopy ((char *) save_reload_inherited
, (char *) reload_inherited
,
6060 sizeof reload_inherited
);
6061 bcopy ((char *) save_reload_inheritance_insn
,
6062 (char *) reload_inheritance_insn
,
6063 sizeof reload_inheritance_insn
);
6064 bcopy ((char *) save_reload_override_in
, (char *) reload_override_in
,
6065 sizeof reload_override_in
);
6066 bcopy ((char *) save_reload_spill_index
, (char *) reload_spill_index
,
6067 sizeof reload_spill_index
);
6068 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
6069 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
6070 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
6071 save_reload_reg_used_in_op_addr
);
6072 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload
,
6073 save_reload_reg_used_in_op_addr_reload
);
6074 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
6075 save_reload_reg_used_in_insn
);
6076 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
6077 save_reload_reg_used_in_other_addr
);
6079 for (i
= 0; i
< reload_n_operands
; i
++)
6081 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
6082 save_reload_reg_used_in_input
[i
]);
6083 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
6084 save_reload_reg_used_in_output
[i
]);
6085 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
6086 save_reload_reg_used_in_input_addr
[i
]);
6087 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
],
6088 save_reload_reg_used_in_inpaddr_addr
[i
]);
6089 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
6090 save_reload_reg_used_in_output_addr
[i
]);
6091 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
],
6092 save_reload_reg_used_in_outaddr_addr
[i
]);
6096 /* If we thought we could inherit a reload, because it seemed that
6097 nothing else wanted the same reload register earlier in the insn,
6098 verify that assumption, now that all reloads have been assigned. */
6100 for (j
= 0; j
< n_reloads
; j
++)
6102 register int r
= reload_order
[j
];
6104 if (reload_inherited
[r
] && reload_reg_rtx
[r
] != 0
6105 && ! (reload_reg_free_before_p (true_regnum (reload_reg_rtx
[r
]),
6107 reload_when_needed
[r
], 0)
6108 || reload_reg_free_for_value_p (true_regnum (reload_reg_rtx
[r
]),
6110 reload_when_needed
[r
],
6113 reload_inherited
[r
] = 0;
6114 /* If we can inherit a RELOAD_FOR_INPUT, then we do not need its related
6115 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads.
6116 ??? This could be extended to other reload types, but these are
6117 more tricky to handle:
6118 RELOAD_FOR_OTHER_ADDRESS reloads might have been merged, so we
6119 can't eliminate them without a check that *all* references are
6120 now unused due to inheritance.
6121 While RELOAD_FOR_INPADDR_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS are
6122 not merged, we can't be sure that we have eliminated the use of
6123 that particular reload if we have seen just one
6124 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_OUTPUT_ADDRESS being inherited,
6125 since there might be multiple of the latter two reloads for a single
6127 RELOAD_FOR_OPADDR_ADDR reloads for different operands are not
6128 merged, but might share the same register by courtesy of
6129 reload_reg_free_for_value_p. reload_reg_used_in_op_addr_reload
6130 does not differentiate by opnum, thus calling clear_reload_reg_in_use
6131 for one of these reloads would mark the register as free even though
6132 another RELOAD_FOR_OPADDR_ADDR reload might still use it. */
6133 else if (reload_inherited
[r
] && reload_when_needed
[r
] == RELOAD_FOR_INPUT
)
6135 for (i
= 0; i
< n_reloads
; i
++)
6137 if ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6138 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6139 && reload_opnum
[i
] == reload_opnum
[r
]
6140 && reload_in
[i
] && reload_reg_rtx
[i
])
6142 int regno
= true_regnum (reload_reg_rtx
[i
]);
6145 if (spill_reg_order
[regno
] >= 0)
6146 clear_reload_reg_in_use (regno
, reload_opnum
[i
],
6147 reload_when_needed
[i
],
6149 reload_reg_rtx
[i
] = 0;
6150 reload_spill_index
[i
] = -1;
6151 remove_replacements (i
);
6156 /* If we found a better place to reload from,
6157 validate it in the same fashion, if it is a reload reg. */
6158 if (reload_override_in
[r
]
6159 && (GET_CODE (reload_override_in
[r
]) == REG
6160 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6162 int regno
= true_regnum (reload_override_in
[r
]);
6163 if (spill_reg_order
[regno
] >= 0
6164 && ! reload_reg_free_before_p (regno
, reload_opnum
[r
],
6165 reload_when_needed
[r
], 1))
6166 reload_override_in
[r
] = 0;
6170 /* Now that reload_override_in is known valid,
6171 actually override reload_in. */
6172 for (j
= 0; j
< n_reloads
; j
++)
6173 if (reload_override_in
[j
])
6174 reload_in
[j
] = reload_override_in
[j
];
6176 /* If this reload won't be done because it has been cancelled or is
6177 optional and not inherited, clear reload_reg_rtx so other
6178 routines (such as subst_reloads) don't get confused. */
6179 for (j
= 0; j
< n_reloads
; j
++)
6180 if (reload_reg_rtx
[j
] != 0
6181 && ((reload_optional
[j
] && ! reload_inherited
[j
])
6182 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
6183 && ! reload_secondary_p
[j
])))
6185 int regno
= true_regnum (reload_reg_rtx
[j
]);
6187 if (spill_reg_order
[regno
] >= 0)
6188 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
6189 reload_when_needed
[j
], reload_mode
[j
]);
6190 reload_reg_rtx
[j
] = 0;
6193 /* Record which pseudos and which spill regs have output reloads. */
6194 for (j
= 0; j
< n_reloads
; j
++)
6196 register int r
= reload_order
[j
];
6198 i
= reload_spill_index
[r
];
6200 /* I is nonneg if this reload uses a register.
6201 If reload_reg_rtx[r] is 0, this is an optional reload
6202 that we opted to ignore. */
6203 if (reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
6204 && reload_reg_rtx
[r
] != 0)
6206 register int nregno
= REGNO (reload_out
[r
]);
6209 if (nregno
< FIRST_PSEUDO_REGISTER
)
6210 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
6213 reg_has_output_reload
[nregno
+ nr
] = 1;
6217 nr
= HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6219 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6222 if (reload_when_needed
[r
] != RELOAD_OTHER
6223 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
6224 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
6230 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6231 reloads of the same item for fear that we might not have enough reload
6232 registers. However, normally they will get the same reload register
6233 and hence actually need not be loaded twice.
6235 Here we check for the most common case of this phenomenon: when we have
6236 a number of reloads for the same object, each of which were allocated
6237 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6238 reload, and is not modified in the insn itself. If we find such,
6239 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6240 This will not increase the number of spill registers needed and will
6241 prevent redundant code. */
6244 merge_assigned_reloads (insn
)
6249 /* Scan all the reloads looking for ones that only load values and
6250 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6251 assigned and not modified by INSN. */
6253 for (i
= 0; i
< n_reloads
; i
++)
6255 int conflicting_input
= 0;
6256 int max_input_address_opnum
= -1;
6257 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6259 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
6260 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
6261 || reg_set_p (reload_reg_rtx
[i
], insn
))
6264 /* Look at all other reloads. Ensure that the only use of this
6265 reload_reg_rtx is in a reload that just loads the same value
6266 as we do. Note that any secondary reloads must be of the identical
6267 class since the values, modes, and result registers are the
6268 same, so we need not do anything with any secondary reloads. */
6270 for (j
= 0; j
< n_reloads
; j
++)
6272 if (i
== j
|| reload_reg_rtx
[j
] == 0
6273 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
6277 if (reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6278 && reload_opnum
[j
] > max_input_address_opnum
)
6279 max_input_address_opnum
= reload_opnum
[j
];
6281 /* If the reload regs aren't exactly the same (e.g, different modes)
6282 or if the values are different, we can't merge this reload.
6283 But if it is an input reload, we might still merge
6284 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6286 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6287 || reload_out
[j
] != 0 || reload_in
[j
] == 0
6288 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
6290 if (reload_when_needed
[j
] != RELOAD_FOR_INPUT
6291 || ((reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
6292 || reload_opnum
[i
] > reload_opnum
[j
])
6293 && reload_when_needed
[i
] != RELOAD_FOR_OTHER_ADDRESS
))
6295 conflicting_input
= 1;
6296 if (min_conflicting_input_opnum
> reload_opnum
[j
])
6297 min_conflicting_input_opnum
= reload_opnum
[j
];
6301 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6302 we, in fact, found any matching reloads. */
6305 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6307 for (j
= 0; j
< n_reloads
; j
++)
6308 if (i
!= j
&& reload_reg_rtx
[j
] != 0
6309 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6310 && (! conflicting_input
6311 || reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6312 || reload_when_needed
[j
] == RELOAD_FOR_OTHER_ADDRESS
))
6314 reload_when_needed
[i
] = RELOAD_OTHER
;
6316 reload_spill_index
[j
] = -1;
6317 transfer_replacements (i
, j
);
6320 /* If this is now RELOAD_OTHER, look for any reloads that load
6321 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6322 if they were for inputs, RELOAD_OTHER for outputs. Note that
6323 this test is equivalent to looking for reloads for this operand
6326 if (reload_when_needed
[i
] == RELOAD_OTHER
)
6327 for (j
= 0; j
< n_reloads
; j
++)
6328 if (reload_in
[j
] != 0
6329 && reload_when_needed
[i
] != RELOAD_OTHER
6330 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
6332 reload_when_needed
[j
]
6333 = ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6334 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6335 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6341 /* Output insns to reload values in and out of the chosen reload regs. */
6344 emit_reload_insns (insn
)
6348 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6349 rtx other_input_address_reload_insns
= 0;
6350 rtx other_input_reload_insns
= 0;
6351 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6352 rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6353 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6354 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6355 rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6356 rtx operand_reload_insns
= 0;
6357 rtx other_operand_reload_insns
= 0;
6358 rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6359 rtx following_insn
= NEXT_INSN (insn
);
6360 rtx before_insn
= insn
;
6362 /* Values to be put in spill_reg_store are put here first. */
6363 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6364 HARD_REG_SET reg_reloaded_died
;
6366 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6368 for (j
= 0; j
< reload_n_operands
; j
++)
6369 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6370 = inpaddr_address_reload_insns
[j
]
6371 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6372 = outaddr_address_reload_insns
[j
]
6373 = other_output_reload_insns
[j
] = 0;
6375 /* Now output the instructions to copy the data into and out of the
6376 reload registers. Do these in the order that the reloads were reported,
6377 since reloads of base and index registers precede reloads of operands
6378 and the operands may need the base and index registers reloaded. */
6380 for (j
= 0; j
< n_reloads
; j
++)
6383 rtx oldequiv_reg
= 0;
6384 rtx this_reload_insn
= 0;
6385 int expect_occurrences
= 1;
6387 if (reload_spill_index
[j
] >= 0)
6388 new_spill_reg_store
[reload_spill_index
[j
]] = 0;
6391 if (old
!= 0 && ! reload_inherited
[j
]
6392 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
6393 && reload_reg_rtx
[j
] != 0)
6395 register rtx reloadreg
= reload_reg_rtx
[j
];
6397 enum machine_mode mode
;
6400 /* Determine the mode to reload in.
6401 This is very tricky because we have three to choose from.
6402 There is the mode the insn operand wants (reload_inmode[J]).
6403 There is the mode of the reload register RELOADREG.
6404 There is the intrinsic mode of the operand, which we could find
6405 by stripping some SUBREGs.
6406 It turns out that RELOADREG's mode is irrelevant:
6407 we can change that arbitrarily.
6409 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6410 then the reload reg may not support QImode moves, so use SImode.
6411 If foo is in memory due to spilling a pseudo reg, this is safe,
6412 because the QImode value is in the least significant part of a
6413 slot big enough for a SImode. If foo is some other sort of
6414 memory reference, then it is impossible to reload this case,
6415 so previous passes had better make sure this never happens.
6417 Then consider a one-word union which has SImode and one of its
6418 members is a float, being fetched as (SUBREG:SF union:SI).
6419 We must fetch that as SFmode because we could be loading into
6420 a float-only register. In this case OLD's mode is correct.
6422 Consider an immediate integer: it has VOIDmode. Here we need
6423 to get a mode from something else.
6425 In some cases, there is a fourth mode, the operand's
6426 containing mode. If the insn specifies a containing mode for
6427 this operand, it overrides all others.
6429 I am not sure whether the algorithm here is always right,
6430 but it does the right things in those cases. */
6432 mode
= GET_MODE (old
);
6433 if (mode
== VOIDmode
)
6434 mode
= reload_inmode
[j
];
6436 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6437 /* If we need a secondary register for this operation, see if
6438 the value is already in a register in that class. Don't
6439 do this if the secondary register will be used as a scratch
6442 if (reload_secondary_in_reload
[j
] >= 0
6443 && reload_secondary_in_icode
[j
] == CODE_FOR_nothing
6446 = find_equiv_reg (old
, insn
,
6447 reload_reg_class
[reload_secondary_in_reload
[j
]],
6448 -1, NULL_PTR
, 0, mode
);
6451 /* If reloading from memory, see if there is a register
6452 that already holds the same value. If so, reload from there.
6453 We can pass 0 as the reload_reg_p argument because
6454 any other reload has either already been emitted,
6455 in which case find_equiv_reg will see the reload-insn,
6456 or has yet to be emitted, in which case it doesn't matter
6457 because we will use this equiv reg right away. */
6459 if (oldequiv
== 0 && optimize
6460 && (GET_CODE (old
) == MEM
6461 || (GET_CODE (old
) == REG
6462 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6463 && reg_renumber
[REGNO (old
)] < 0)))
6464 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6465 -1, NULL_PTR
, 0, mode
);
6469 int regno
= true_regnum (oldequiv
);
6471 /* If OLDEQUIV is a spill register, don't use it for this
6472 if any other reload needs it at an earlier stage of this insn
6473 or at this stage. */
6474 if (spill_reg_order
[regno
] >= 0
6475 && (! reload_reg_free_p (regno
, reload_opnum
[j
],
6476 reload_when_needed
[j
])
6477 || ! reload_reg_free_before_p (regno
, reload_opnum
[j
],
6478 reload_when_needed
[j
], 1)))
6481 /* If OLDEQUIV is not a spill register,
6482 don't use it if any other reload wants it. */
6483 if (spill_reg_order
[regno
] < 0)
6486 for (k
= 0; k
< n_reloads
; k
++)
6487 if (reload_reg_rtx
[k
] != 0 && k
!= j
6488 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx
[k
],
6496 /* If it is no cheaper to copy from OLDEQUIV into the
6497 reload register than it would be to move from memory,
6498 don't use it. Likewise, if we need a secondary register
6502 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
6503 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
6504 reload_reg_class
[j
])
6505 >= MEMORY_MOVE_COST (mode
, reload_reg_class
[j
], 1)))
6506 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6507 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6511 #ifdef SECONDARY_MEMORY_NEEDED
6512 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6513 reload_reg_class
[j
],
6522 else if (GET_CODE (oldequiv
) == REG
)
6523 oldequiv_reg
= oldequiv
;
6524 else if (GET_CODE (oldequiv
) == SUBREG
)
6525 oldequiv_reg
= SUBREG_REG (oldequiv
);
6527 /* If we are reloading from a register that was recently stored in
6528 with an output-reload, see if we can prove there was
6529 actually no need to store the old value in it. */
6531 if (optimize
&& GET_CODE (oldequiv
) == REG
6532 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6533 && spill_reg_store
[REGNO (oldequiv
)]
6534 && GET_CODE (old
) == REG
&& dead_or_set_p (insn
, old
)
6535 /* This is unsafe if operand occurs more than once in current
6536 insn. Perhaps some occurrences weren't reloaded. */
6537 && count_occurrences (PATTERN (insn
), old
) == 1)
6538 delete_output_reload (insn
, j
, spill_reg_store
[REGNO (oldequiv
)]);
6540 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6541 then load RELOADREG from OLDEQUIV. Note that we cannot use
6542 gen_lowpart_common since it can do the wrong thing when
6543 RELOADREG has a multi-word mode. Note that RELOADREG
6544 must always be a REG here. */
6546 if (GET_MODE (reloadreg
) != mode
)
6547 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6548 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6549 oldequiv
= SUBREG_REG (oldequiv
);
6550 if (GET_MODE (oldequiv
) != VOIDmode
6551 && mode
!= GET_MODE (oldequiv
))
6552 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6554 /* Switch to the right place to emit the reload insns. */
6555 switch (reload_when_needed
[j
])
6558 where
= &other_input_reload_insns
;
6560 case RELOAD_FOR_INPUT
:
6561 where
= &input_reload_insns
[reload_opnum
[j
]];
6563 case RELOAD_FOR_INPUT_ADDRESS
:
6564 where
= &input_address_reload_insns
[reload_opnum
[j
]];
6566 case RELOAD_FOR_INPADDR_ADDRESS
:
6567 where
= &inpaddr_address_reload_insns
[reload_opnum
[j
]];
6569 case RELOAD_FOR_OUTPUT_ADDRESS
:
6570 where
= &output_address_reload_insns
[reload_opnum
[j
]];
6572 case RELOAD_FOR_OUTADDR_ADDRESS
:
6573 where
= &outaddr_address_reload_insns
[reload_opnum
[j
]];
6575 case RELOAD_FOR_OPERAND_ADDRESS
:
6576 where
= &operand_reload_insns
;
6578 case RELOAD_FOR_OPADDR_ADDR
:
6579 where
= &other_operand_reload_insns
;
6581 case RELOAD_FOR_OTHER_ADDRESS
:
6582 where
= &other_input_address_reload_insns
;
6588 push_to_sequence (*where
);
6591 /* Auto-increment addresses must be reloaded in a special way. */
6592 if (GET_CODE (oldequiv
) == POST_INC
6593 || GET_CODE (oldequiv
) == POST_DEC
6594 || GET_CODE (oldequiv
) == PRE_INC
6595 || GET_CODE (oldequiv
) == PRE_DEC
)
6597 /* We are not going to bother supporting the case where a
6598 incremented register can't be copied directly from
6599 OLDEQUIV since this seems highly unlikely. */
6600 if (reload_secondary_in_reload
[j
] >= 0)
6602 /* Prevent normal processing of this reload. */
6604 /* Output a special code sequence for this case. */
6605 inc_for_reload (reloadreg
, oldequiv
, reload_inc
[j
]);
6608 /* If we are reloading a pseudo-register that was set by the previous
6609 insn, see if we can get rid of that pseudo-register entirely
6610 by redirecting the previous insn into our reload register. */
6612 else if (optimize
&& GET_CODE (old
) == REG
6613 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6614 && dead_or_set_p (insn
, old
)
6615 /* This is unsafe if some other reload
6616 uses the same reg first. */
6617 && reload_reg_free_before_p (REGNO (reloadreg
),
6619 reload_when_needed
[j
], 0))
6621 rtx temp
= PREV_INSN (insn
);
6622 while (temp
&& GET_CODE (temp
) == NOTE
)
6623 temp
= PREV_INSN (temp
);
6625 && GET_CODE (temp
) == INSN
6626 && GET_CODE (PATTERN (temp
)) == SET
6627 && SET_DEST (PATTERN (temp
)) == old
6628 /* Make sure we can access insn_operand_constraint. */
6629 && asm_noperands (PATTERN (temp
)) < 0
6630 /* This is unsafe if prev insn rejects our reload reg. */
6631 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
6633 /* This is unsafe if operand occurs more than once in current
6634 insn. Perhaps some occurrences aren't reloaded. */
6635 && count_occurrences (PATTERN (insn
), old
) == 1
6636 /* Don't risk splitting a matching pair of operands. */
6637 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6639 /* Store into the reload register instead of the pseudo. */
6640 SET_DEST (PATTERN (temp
)) = reloadreg
;
6641 /* If these are the only uses of the pseudo reg,
6642 pretend for GDB it lives in the reload reg we used. */
6643 if (REG_N_DEATHS (REGNO (old
)) == 1
6644 && REG_N_SETS (REGNO (old
)) == 1)
6646 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
6647 alter_reg (REGNO (old
), -1);
6653 /* We can't do that, so output an insn to load RELOADREG. */
6657 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6658 rtx second_reload_reg
= 0;
6659 enum insn_code icode
;
6661 /* If we have a secondary reload, pick up the secondary register
6662 and icode, if any. If OLDEQUIV and OLD are different or
6663 if this is an in-out reload, recompute whether or not we
6664 still need a secondary register and what the icode should
6665 be. If we still need a secondary register and the class or
6666 icode is different, go back to reloading from OLD if using
6667 OLDEQUIV means that we got the wrong type of register. We
6668 cannot have different class or icode due to an in-out reload
6669 because we don't make such reloads when both the input and
6670 output need secondary reload registers. */
6672 if (reload_secondary_in_reload
[j
] >= 0)
6674 int secondary_reload
= reload_secondary_in_reload
[j
];
6675 rtx real_oldequiv
= oldequiv
;
6678 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6679 and similarly for OLD.
6680 See comments in get_secondary_reload in reload.c. */
6681 if (GET_CODE (oldequiv
) == REG
6682 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6683 && reg_equiv_mem
[REGNO (oldequiv
)] != 0)
6684 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
6686 if (GET_CODE (old
) == REG
6687 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6688 && reg_equiv_mem
[REGNO (old
)] != 0)
6689 real_old
= reg_equiv_mem
[REGNO (old
)];
6691 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
6692 icode
= reload_secondary_in_icode
[j
];
6694 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6695 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
6697 enum reg_class new_class
6698 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6699 mode
, real_oldequiv
);
6701 if (new_class
== NO_REGS
)
6702 second_reload_reg
= 0;
6705 enum insn_code new_icode
;
6706 enum machine_mode new_mode
;
6708 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6709 REGNO (second_reload_reg
)))
6710 oldequiv
= old
, real_oldequiv
= real_old
;
6713 new_icode
= reload_in_optab
[(int) mode
];
6714 if (new_icode
!= CODE_FOR_nothing
6715 && ((insn_operand_predicate
[(int) new_icode
][0]
6716 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
6718 || (insn_operand_predicate
[(int) new_icode
][1]
6719 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
6720 (real_oldequiv
, mode
)))))
6721 new_icode
= CODE_FOR_nothing
;
6723 if (new_icode
== CODE_FOR_nothing
)
6726 new_mode
= insn_operand_mode
[(int) new_icode
][2];
6728 if (GET_MODE (second_reload_reg
) != new_mode
)
6730 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6732 oldequiv
= old
, real_oldequiv
= real_old
;
6735 = gen_rtx_REG (new_mode
,
6736 REGNO (second_reload_reg
));
6742 /* If we still need a secondary reload register, check
6743 to see if it is being used as a scratch or intermediate
6744 register and generate code appropriately. If we need
6745 a scratch register, use REAL_OLDEQUIV since the form of
6746 the insn may depend on the actual address if it is
6749 if (second_reload_reg
)
6751 if (icode
!= CODE_FOR_nothing
)
6753 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6754 second_reload_reg
));
6759 /* See if we need a scratch register to load the
6760 intermediate register (a tertiary reload). */
6761 enum insn_code tertiary_icode
6762 = reload_secondary_in_icode
[secondary_reload
];
6764 if (tertiary_icode
!= CODE_FOR_nothing
)
6766 rtx third_reload_reg
6767 = reload_reg_rtx
[reload_secondary_in_reload
[secondary_reload
]];
6769 emit_insn ((GEN_FCN (tertiary_icode
)
6770 (second_reload_reg
, real_oldequiv
,
6771 third_reload_reg
)));
6774 gen_reload (second_reload_reg
, oldequiv
,
6776 reload_when_needed
[j
]);
6778 oldequiv
= second_reload_reg
;
6784 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6785 gen_reload (reloadreg
, oldequiv
, reload_opnum
[j
],
6786 reload_when_needed
[j
]);
6788 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6789 /* We may have to make a REG_DEAD note for the secondary reload
6790 register in the insns we just made. Find the last insn that
6791 mentioned the register. */
6792 if (! special
&& second_reload_reg
6793 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg
)))
6797 for (prev
= get_last_insn (); prev
;
6798 prev
= PREV_INSN (prev
))
6799 if (GET_RTX_CLASS (GET_CODE (prev
) == 'i')
6800 && reg_overlap_mentioned_for_reload_p (second_reload_reg
,
6803 REG_NOTES (prev
) = gen_rtx_EXPR_LIST (REG_DEAD
,
6812 this_reload_insn
= get_last_insn ();
6813 /* End this sequence. */
6814 *where
= get_insns ();
6818 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6819 e.g. inheriting a SImode output reload for
6820 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6821 if (optimize
&& reload_inherited
[j
] && reload_in
[j
]
6822 && GET_CODE (reload_in
[j
]) == MEM
6823 && reload_spill_index
[j
] >= 0
6824 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6827 = count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1 ? 0 : -1;
6829 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6831 /* Add a note saying the input reload reg
6832 dies in this insn, if anyone cares. */
6833 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6835 && reload_reg_rtx
[j
] != old
6836 && reload_reg_rtx
[j
] != 0
6837 && reload_out
[j
] == 0
6838 && ! reload_inherited
[j
]
6839 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx
[j
])))
6841 register rtx reloadreg
= reload_reg_rtx
[j
];
6844 /* We can't abort here because we need to support this for sched.c.
6845 It's not terrible to miss a REG_DEAD note, but we should try
6846 to figure out how to do this correctly. */
6847 /* The code below is incorrect for address-only reloads. */
6848 if (reload_when_needed
[j
] != RELOAD_OTHER
6849 && reload_when_needed
[j
] != RELOAD_FOR_INPUT
)
6853 /* Add a death note to this insn, for an input reload. */
6855 if ((reload_when_needed
[j
] == RELOAD_OTHER
6856 || reload_when_needed
[j
] == RELOAD_FOR_INPUT
)
6857 && ! dead_or_set_p (insn
, reloadreg
))
6859 = gen_rtx_EXPR_LIST (REG_DEAD
,
6860 reloadreg
, REG_NOTES (insn
));
6863 /* When we inherit a reload, the last marked death of the reload reg
6864 may no longer really be a death. */
6865 if (reload_reg_rtx
[j
] != 0
6866 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx
[j
]))
6867 && reload_inherited
[j
])
6869 /* Handle inheriting an output reload.
6870 Remove the death note from the output reload insn. */
6871 if (reload_spill_index
[j
] >= 0
6872 && GET_CODE (reload_in
[j
]) == REG
6873 && spill_reg_store
[reload_spill_index
[j
]] != 0
6874 && find_regno_note (spill_reg_store
[reload_spill_index
[j
]],
6875 REG_DEAD
, REGNO (reload_reg_rtx
[j
])))
6876 remove_death (REGNO (reload_reg_rtx
[j
]),
6877 spill_reg_store
[reload_spill_index
[j
]]);
6878 /* Likewise for input reloads that were inherited. */
6879 else if (reload_spill_index
[j
] >= 0
6880 && GET_CODE (reload_in
[j
]) == REG
6881 && spill_reg_store
[reload_spill_index
[j
]] == 0
6882 && reload_inheritance_insn
[j
] != 0
6883 && find_regno_note (reload_inheritance_insn
[j
], REG_DEAD
,
6884 REGNO (reload_reg_rtx
[j
])))
6885 remove_death (REGNO (reload_reg_rtx
[j
]),
6886 reload_inheritance_insn
[j
]);
6891 /* We got this register from find_equiv_reg.
6892 Search back for its last death note and get rid of it.
6893 But don't search back too far.
6894 Don't go past a place where this reg is set,
6895 since a death note before that remains valid. */
6896 for (prev
= PREV_INSN (insn
);
6897 prev
&& GET_CODE (prev
) != CODE_LABEL
;
6898 prev
= PREV_INSN (prev
))
6899 if (GET_RTX_CLASS (GET_CODE (prev
)) == 'i'
6900 && dead_or_set_p (prev
, reload_reg_rtx
[j
]))
6902 if (find_regno_note (prev
, REG_DEAD
,
6903 REGNO (reload_reg_rtx
[j
])))
6904 remove_death (REGNO (reload_reg_rtx
[j
]), prev
);
6910 /* We might have used find_equiv_reg above to choose an alternate
6911 place from which to reload. If so, and it died, we need to remove
6912 that death and move it to one of the insns we just made. */
6914 if (oldequiv_reg
!= 0
6915 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg
)))
6919 for (prev
= PREV_INSN (insn
); prev
&& GET_CODE (prev
) != CODE_LABEL
;
6920 prev
= PREV_INSN (prev
))
6921 if (GET_RTX_CLASS (GET_CODE (prev
)) == 'i'
6922 && dead_or_set_p (prev
, oldequiv_reg
))
6924 if (find_regno_note (prev
, REG_DEAD
, REGNO (oldequiv_reg
)))
6926 for (prev1
= this_reload_insn
;
6927 prev1
; prev1
= PREV_INSN (prev1
))
6928 if (GET_RTX_CLASS (GET_CODE (prev1
) == 'i')
6929 && reg_overlap_mentioned_for_reload_p (oldequiv_reg
,
6932 REG_NOTES (prev1
) = gen_rtx_EXPR_LIST (REG_DEAD
,
6937 remove_death (REGNO (oldequiv_reg
), prev
);
6944 /* If we are reloading a register that was recently stored in with an
6945 output-reload, see if we can prove there was
6946 actually no need to store the old value in it. */
6948 if (optimize
&& reload_inherited
[j
] && reload_spill_index
[j
] >= 0
6949 && reload_in
[j
] != 0
6950 && GET_CODE (reload_in
[j
]) == REG
6952 /* There doesn't seem to be any reason to restrict this to pseudos
6953 and doing so loses in the case where we are copying from a
6954 register of the wrong class. */
6955 && REGNO (reload_in
[j
]) >= FIRST_PSEUDO_REGISTER
6957 && spill_reg_store
[reload_spill_index
[j
]] != 0
6958 /* This is unsafe if some other reload uses the same reg first. */
6959 && reload_reg_free_before_p (reload_spill_index
[j
],
6960 reload_opnum
[j
], reload_when_needed
[j
],
6962 && dead_or_set_p (insn
, reload_in
[j
])
6963 /* This is unsafe if operand occurs more than once in current
6964 insn. Perhaps some occurrences weren't reloaded. */
6965 && (count_occurrences (PATTERN (insn
), reload_in
[j
])
6966 == expect_occurrences
))
6967 delete_output_reload (insn
, j
,
6968 spill_reg_store
[reload_spill_index
[j
]]);
6970 /* Input-reloading is done. Now do output-reloading,
6971 storing the value from the reload-register after the main insn
6972 if reload_out[j] is nonzero.
6974 ??? At some point we need to support handling output reloads of
6975 JUMP_INSNs or insns that set cc0. */
6976 old
= reload_out
[j
];
6978 && reload_reg_rtx
[j
] != old
6979 && reload_reg_rtx
[j
] != 0)
6981 register rtx reloadreg
= reload_reg_rtx
[j
];
6982 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6983 register rtx second_reloadreg
= 0;
6986 enum machine_mode mode
;
6989 /* An output operand that dies right away does need a reload,
6990 but need not be copied from it. Show the new location in the
6992 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6993 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6995 XEXP (note
, 0) = reload_reg_rtx
[j
];
6998 /* Likewise for a SUBREG of an operand that dies. */
6999 else if (GET_CODE (old
) == SUBREG
7000 && GET_CODE (SUBREG_REG (old
)) == REG
7001 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7004 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7008 else if (GET_CODE (old
) == SCRATCH
)
7009 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7010 but we don't want to make an output reload. */
7014 /* Strip off of OLD any size-increasing SUBREGs such as
7015 (SUBREG:SI foo:QI 0). */
7017 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
7018 && (GET_MODE_SIZE (GET_MODE (old
))
7019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
7020 old
= SUBREG_REG (old
);
7023 /* If is a JUMP_INSN, we can't support output reloads yet. */
7024 if (GET_CODE (insn
) == JUMP_INSN
)
7027 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7030 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
7032 /* Determine the mode to reload in.
7033 See comments above (for input reloading). */
7035 mode
= GET_MODE (old
);
7036 if (mode
== VOIDmode
)
7038 /* VOIDmode should never happen for an output. */
7039 if (asm_noperands (PATTERN (insn
)) < 0)
7040 /* It's the compiler's fault. */
7041 fatal_insn ("VOIDmode on an output", insn
);
7042 error_for_asm (insn
, "output operand is constant in `asm'");
7043 /* Prevent crash--use something we know is valid. */
7045 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7048 if (GET_MODE (reloadreg
) != mode
)
7049 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7051 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7053 /* If we need two reload regs, set RELOADREG to the intermediate
7054 one, since it will be stored into OLD. We might need a secondary
7055 register only for an input reload, so check again here. */
7057 if (reload_secondary_out_reload
[j
] >= 0)
7061 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
7062 && reg_equiv_mem
[REGNO (old
)] != 0)
7063 real_old
= reg_equiv_mem
[REGNO (old
)];
7065 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
7069 second_reloadreg
= reloadreg
;
7070 reloadreg
= reload_reg_rtx
[reload_secondary_out_reload
[j
]];
7072 /* See if RELOADREG is to be used as a scratch register
7073 or as an intermediate register. */
7074 if (reload_secondary_out_icode
[j
] != CODE_FOR_nothing
)
7076 emit_insn ((GEN_FCN (reload_secondary_out_icode
[j
])
7077 (real_old
, second_reloadreg
, reloadreg
)));
7082 /* See if we need both a scratch and intermediate reload
7085 int secondary_reload
= reload_secondary_out_reload
[j
];
7086 enum insn_code tertiary_icode
7087 = reload_secondary_out_icode
[secondary_reload
];
7089 if (GET_MODE (reloadreg
) != mode
)
7090 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7092 if (tertiary_icode
!= CODE_FOR_nothing
)
7095 = reload_reg_rtx
[reload_secondary_out_reload
[secondary_reload
]];
7098 /* Copy primary reload reg to secondary reload reg.
7099 (Note that these have been swapped above, then
7100 secondary reload reg to OLD using our insn. */
7102 /* If REAL_OLD is a paradoxical SUBREG, remove it
7103 and try to put the opposite SUBREG on
7105 if (GET_CODE (real_old
) == SUBREG
7106 && (GET_MODE_SIZE (GET_MODE (real_old
))
7107 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7108 && 0 != (tem
= gen_lowpart_common
7109 (GET_MODE (SUBREG_REG (real_old
)),
7111 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7113 gen_reload (reloadreg
, second_reloadreg
,
7114 reload_opnum
[j
], reload_when_needed
[j
]);
7115 emit_insn ((GEN_FCN (tertiary_icode
)
7116 (real_old
, reloadreg
, third_reloadreg
)));
7121 /* Copy between the reload regs here and then to
7124 gen_reload (reloadreg
, second_reloadreg
,
7125 reload_opnum
[j
], reload_when_needed
[j
]);
7131 /* Output the last reload insn. */
7136 /* Don't output the last reload if OLD is not the dest of
7137 INSN and is in the src and is clobbered by INSN. */
7138 if (! flag_expensive_optimizations
7139 || GET_CODE (old
) != REG
7140 || !(set
= single_set (insn
))
7141 || rtx_equal_p (old
, SET_DEST (set
))
7142 || !reg_mentioned_p (old
, SET_SRC (set
))
7143 || !regno_clobbered_p (REGNO (old
), insn
))
7144 gen_reload (old
, reloadreg
, reload_opnum
[j
],
7145 reload_when_needed
[j
]);
7148 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7149 /* If final will look at death notes for this reg,
7150 put one on the last output-reload insn to use it. Similarly
7151 for any secondary register. */
7152 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg
)))
7153 for (p
= get_last_insn (); p
; p
= PREV_INSN (p
))
7154 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
7155 && reg_overlap_mentioned_for_reload_p (reloadreg
,
7157 REG_NOTES (p
) = gen_rtx_EXPR_LIST (REG_DEAD
,
7158 reloadreg
, REG_NOTES (p
));
7160 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7161 if (! special
&& second_reloadreg
7162 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg
)))
7163 for (p
= get_last_insn (); p
; p
= PREV_INSN (p
))
7164 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
7165 && reg_overlap_mentioned_for_reload_p (second_reloadreg
,
7167 REG_NOTES (p
) = gen_rtx_EXPR_LIST (REG_DEAD
,
7172 /* Look at all insns we emitted, just to be safe. */
7173 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7174 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
7176 rtx pat
= PATTERN (p
);
7178 /* If this output reload doesn't come from a spill reg,
7179 clear any memory of reloaded copies of the pseudo reg.
7180 If this output reload comes from a spill reg,
7181 reg_has_output_reload will make this do nothing. */
7182 note_stores (pat
, forget_old_reloads_1
);
7184 if (reg_mentioned_p (reload_reg_rtx
[j
], pat
))
7186 if (reload_spill_index
[j
] < 0
7187 && GET_CODE (pat
) == SET
7188 && SET_SRC (pat
) == reload_reg_rtx
[j
])
7190 int src
= REGNO (SET_SRC (pat
));
7192 reload_spill_index
[j
] = src
;
7193 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7194 if (find_regno_note (insn
, REG_DEAD
, src
))
7195 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7197 if (reload_spill_index
[j
] >= 0)
7199 int s
= reload_secondary_out_reload
[j
];
7200 rtx set
= single_set (p
);
7201 /* If this reload copies only to the secondary reload
7202 register, the secondary reload does the actual
7204 if (s
>= 0 && set
== NULL_RTX
)
7205 ; /* We can't tell what function the secondary reload
7206 has and where the actual store to the pseudo is
7207 made; leave new_spill_reg_store alone. */
7209 && SET_SRC (set
) == reload_reg_rtx
[j
]
7210 && SET_DEST (set
) == reload_reg_rtx
[s
])
7212 /* Usually the next instruction will be the
7213 secondary reload insn; if we can confirm
7214 that it is, setting new_spill_reg_store to
7215 that insn will allow an extra optimization. */
7216 rtx s_reg
= reload_reg_rtx
[s
];
7217 rtx next
= NEXT_INSN (p
);
7218 reload_out
[s
] = reload_out
[j
];
7219 set
= single_set (next
);
7220 if (set
&& SET_SRC (set
) == s_reg
7221 && ! new_spill_reg_store
[REGNO (s_reg
)])
7222 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7225 new_spill_reg_store
[reload_spill_index
[j
]] = p
;
7230 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7232 emit_insns (other_output_reload_insns
[reload_opnum
[j
]]);
7233 other_output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7236 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7242 /* Now write all the insns we made for reloads in the order expected by
7243 the allocation functions. Prior to the insn being reloaded, we write
7244 the following reloads:
7246 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7248 RELOAD_OTHER reloads.
7250 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7251 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7252 RELOAD_FOR_INPUT reload for the operand.
7254 RELOAD_FOR_OPADDR_ADDRS reloads.
7256 RELOAD_FOR_OPERAND_ADDRESS reloads.
7258 After the insn being reloaded, we write the following:
7260 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7261 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7262 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7263 reloads for the operand. The RELOAD_OTHER output reloads are
7264 output in descending order by reload number. */
7266 emit_insns_before (other_input_address_reload_insns
, before_insn
);
7267 emit_insns_before (other_input_reload_insns
, before_insn
);
7269 for (j
= 0; j
< reload_n_operands
; j
++)
7271 emit_insns_before (inpaddr_address_reload_insns
[j
], before_insn
);
7272 emit_insns_before (input_address_reload_insns
[j
], before_insn
);
7273 emit_insns_before (input_reload_insns
[j
], before_insn
);
7276 emit_insns_before (other_operand_reload_insns
, before_insn
);
7277 emit_insns_before (operand_reload_insns
, before_insn
);
7279 for (j
= 0; j
< reload_n_operands
; j
++)
7281 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7282 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7283 emit_insns_before (output_reload_insns
[j
], following_insn
);
7284 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7287 /* Move death notes from INSN
7288 to output-operand-address and output reload insns. */
7289 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7292 /* Loop over those insns, last ones first. */
7293 for (insn1
= PREV_INSN (following_insn
); insn1
!= insn
;
7294 insn1
= PREV_INSN (insn1
))
7295 if (GET_CODE (insn1
) == INSN
&& GET_CODE (PATTERN (insn1
)) == SET
)
7297 rtx source
= SET_SRC (PATTERN (insn1
));
7298 rtx dest
= SET_DEST (PATTERN (insn1
));
7300 /* The note we will examine next. */
7301 rtx reg_notes
= REG_NOTES (insn
);
7302 /* The place that pointed to this note. */
7303 rtx
*prev_reg_note
= ®_NOTES (insn
);
7305 /* If the note is for something used in the source of this
7306 reload insn, or in the output address, move the note. */
7309 rtx next_reg_notes
= XEXP (reg_notes
, 1);
7310 if (REG_NOTE_KIND (reg_notes
) == REG_DEAD
7311 && GET_CODE (XEXP (reg_notes
, 0)) == REG
7312 && ((GET_CODE (dest
) != REG
7313 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes
, 0),
7315 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes
, 0),
7318 *prev_reg_note
= next_reg_notes
;
7319 XEXP (reg_notes
, 1) = REG_NOTES (insn1
);
7320 REG_NOTES (insn1
) = reg_notes
;
7323 prev_reg_note
= &XEXP (reg_notes
, 1);
7325 reg_notes
= next_reg_notes
;
7331 /* For all the spill regs newly reloaded in this instruction,
7332 record what they were reloaded from, so subsequent instructions
7333 can inherit the reloads.
7335 Update spill_reg_store for the reloads of this insn.
7336 Copy the elements that were updated in the loop above. */
7338 for (j
= 0; j
< n_reloads
; j
++)
7340 register int r
= reload_order
[j
];
7341 register int i
= reload_spill_index
[r
];
7343 /* I is nonneg if this reload used a register.
7344 If reload_reg_rtx[r] is 0, this is an optional reload
7345 that we opted to ignore. */
7347 if (i
>= 0 && reload_reg_rtx
[r
] != 0)
7350 = HARD_REGNO_NREGS (i
, GET_MODE (reload_reg_rtx
[r
]));
7352 int part_reaches_end
= 0;
7353 int all_reaches_end
= 1;
7355 /* For a multi register reload, we need to check if all or part
7356 of the value lives to the end. */
7357 for (k
= 0; k
< nr
; k
++)
7359 if (reload_reg_reaches_end_p (i
+ k
, reload_opnum
[r
],
7360 reload_when_needed
[r
]))
7361 part_reaches_end
= 1;
7363 all_reaches_end
= 0;
7366 /* Ignore reloads that don't reach the end of the insn in
7368 if (all_reaches_end
)
7370 /* First, clear out memory of what used to be in this spill reg.
7371 If consecutive registers are used, clear them all. */
7373 for (k
= 0; k
< nr
; k
++)
7374 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7376 /* Maybe the spill reg contains a copy of reload_out. */
7377 if (reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
)
7379 register int nregno
= REGNO (reload_out
[r
]);
7380 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7381 : HARD_REGNO_NREGS (nregno
,
7382 GET_MODE (reload_reg_rtx
[r
])));
7384 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7385 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7387 /* If NREGNO is a hard register, it may occupy more than
7388 one register. If it does, say what is in the
7389 rest of the registers assuming that both registers
7390 agree on how many words the object takes. If not,
7391 invalidate the subsequent registers. */
7393 if (nregno
< FIRST_PSEUDO_REGISTER
)
7394 for (k
= 1; k
< nnr
; k
++)
7395 reg_last_reload_reg
[nregno
+ k
]
7397 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7398 REGNO (reload_reg_rtx
[r
]) + k
)
7401 /* Now do the inverse operation. */
7402 for (k
= 0; k
< nr
; k
++)
7404 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7405 reg_reloaded_contents
[i
+ k
]
7406 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7409 reg_reloaded_insn
[i
+ k
] = insn
;
7410 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7414 /* Maybe the spill reg contains a copy of reload_in. Only do
7415 something if there will not be an output reload for
7416 the register being reloaded. */
7417 else if (reload_out
[r
] == 0
7418 && reload_in
[r
] != 0
7419 && spill_reg_order
[i
] >= 0
7420 && ((GET_CODE (reload_in
[r
]) == REG
7421 && ! reg_has_output_reload
[REGNO (reload_in
[r
])])
7422 || (GET_CODE (reload_in_reg
[r
]) == REG
7423 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])])))
7425 register int nregno
;
7428 if (GET_CODE (reload_in
[r
]) == REG
)
7429 nregno
= REGNO (reload_in
[r
]);
7431 nregno
= REGNO (reload_in_reg
[r
]);
7433 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7434 : HARD_REGNO_NREGS (nregno
,
7435 GET_MODE (reload_reg_rtx
[r
])));
7437 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7439 if (nregno
< FIRST_PSEUDO_REGISTER
)
7440 for (k
= 1; k
< nnr
; k
++)
7441 reg_last_reload_reg
[nregno
+ k
]
7443 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7444 REGNO (reload_reg_rtx
[r
]) + k
)
7447 /* Unless we inherited this reload, show we haven't
7448 recently done a store. */
7449 if (! reload_inherited
[r
])
7450 spill_reg_store
[i
] = 0;
7452 for (k
= 0; k
< nr
; k
++)
7454 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7455 reg_reloaded_contents
[i
+ k
]
7456 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7459 reg_reloaded_insn
[i
+ k
] = insn
;
7460 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7465 /* However, if part of the reload reaches the end, then we must
7466 invalidate the old info for the part that survives to the end. */
7467 else if (part_reaches_end
)
7469 for (k
= 0; k
< nr
; k
++)
7470 if (reload_reg_reaches_end_p (i
+ k
,
7472 reload_when_needed
[r
]))
7473 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7477 /* The following if-statement was #if 0'd in 1.34 (or before...).
7478 It's reenabled in 1.35 because supposedly nothing else
7479 deals with this problem. */
7481 /* If a register gets output-reloaded from a non-spill register,
7482 that invalidates any previous reloaded copy of it.
7483 But forget_old_reloads_1 won't get to see it, because
7484 it thinks only about the original insn. So invalidate it here. */
7485 if (i
< 0 && reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
)
7487 register int nregno
= REGNO (reload_out
[r
]);
7488 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7489 reg_last_reload_reg
[nregno
] = 0;
7492 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (reload_out
[r
]));
7494 while (num_regs
-- > 0)
7495 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7499 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7502 /* Emit code to perform a reload from IN (which may be a reload register) to
7503 OUT (which may also be a reload register). IN or OUT is from operand
7504 OPNUM with reload type TYPE.
7506 Returns first insn emitted. */
7509 gen_reload (out
, in
, opnum
, type
)
7513 enum reload_type type
;
7515 rtx last
= get_last_insn ();
7518 /* If IN is a paradoxical SUBREG, remove it and try to put the
7519 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7520 if (GET_CODE (in
) == SUBREG
7521 && (GET_MODE_SIZE (GET_MODE (in
))
7522 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7523 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7524 in
= SUBREG_REG (in
), out
= tem
;
7525 else if (GET_CODE (out
) == SUBREG
7526 && (GET_MODE_SIZE (GET_MODE (out
))
7527 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7528 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7529 out
= SUBREG_REG (out
), in
= tem
;
7531 /* How to do this reload can get quite tricky. Normally, we are being
7532 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7533 register that didn't get a hard register. In that case we can just
7534 call emit_move_insn.
7536 We can also be asked to reload a PLUS that adds a register or a MEM to
7537 another register, constant or MEM. This can occur during frame pointer
7538 elimination and while reloading addresses. This case is handled by
7539 trying to emit a single insn to perform the add. If it is not valid,
7540 we use a two insn sequence.
7542 Finally, we could be called to handle an 'o' constraint by putting
7543 an address into a register. In that case, we first try to do this
7544 with a named pattern of "reload_load_address". If no such pattern
7545 exists, we just emit a SET insn and hope for the best (it will normally
7546 be valid on machines that use 'o').
7548 This entire process is made complex because reload will never
7549 process the insns we generate here and so we must ensure that
7550 they will fit their constraints and also by the fact that parts of
7551 IN might be being reloaded separately and replaced with spill registers.
7552 Because of this, we are, in some sense, just guessing the right approach
7553 here. The one listed above seems to work.
7555 ??? At some point, this whole thing needs to be rethought. */
7557 if (GET_CODE (in
) == PLUS
7558 && (GET_CODE (XEXP (in
, 0)) == REG
7559 || GET_CODE (XEXP (in
, 0)) == SUBREG
7560 || GET_CODE (XEXP (in
, 0)) == MEM
)
7561 && (GET_CODE (XEXP (in
, 1)) == REG
7562 || GET_CODE (XEXP (in
, 1)) == SUBREG
7563 || CONSTANT_P (XEXP (in
, 1))
7564 || GET_CODE (XEXP (in
, 1)) == MEM
))
7566 /* We need to compute the sum of a register or a MEM and another
7567 register, constant, or MEM, and put it into the reload
7568 register. The best possible way of doing this is if the machine
7569 has a three-operand ADD insn that accepts the required operands.
7571 The simplest approach is to try to generate such an insn and see if it
7572 is recognized and matches its constraints. If so, it can be used.
7574 It might be better not to actually emit the insn unless it is valid,
7575 but we need to pass the insn as an operand to `recog' and
7576 `insn_extract' and it is simpler to emit and then delete the insn if
7577 not valid than to dummy things up. */
7579 rtx op0
, op1
, tem
, insn
;
7582 op0
= find_replacement (&XEXP (in
, 0));
7583 op1
= find_replacement (&XEXP (in
, 1));
7585 /* Since constraint checking is strict, commutativity won't be
7586 checked, so we need to do that here to avoid spurious failure
7587 if the add instruction is two-address and the second operand
7588 of the add is the same as the reload reg, which is frequently
7589 the case. If the insn would be A = B + A, rearrange it so
7590 it will be A = A + B as constrain_operands expects. */
7592 if (GET_CODE (XEXP (in
, 1)) == REG
7593 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7594 tem
= op0
, op0
= op1
, op1
= tem
;
7596 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7597 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7599 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7600 code
= recog_memoized (insn
);
7604 insn_extract (insn
);
7605 /* We want constrain operands to treat this insn strictly in
7606 its validity determination, i.e., the way it would after reload
7608 if (constrain_operands (code
, 1))
7612 delete_insns_since (last
);
7614 /* If that failed, we must use a conservative two-insn sequence.
7615 use move to copy constant, MEM, or pseudo register to the reload
7616 register since "move" will be able to handle an arbitrary operand,
7617 unlike add which can't, in general. Then add the registers.
7619 If there is another way to do this for a specific machine, a
7620 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7623 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7624 || (GET_CODE (op1
) == REG
7625 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
7626 tem
= op0
, op0
= op1
, op1
= tem
;
7628 gen_reload (out
, op0
, opnum
, type
);
7630 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7631 This fixes a problem on the 32K where the stack pointer cannot
7632 be used as an operand of an add insn. */
7634 if (rtx_equal_p (op0
, op1
))
7637 insn
= emit_insn (gen_add2_insn (out
, op1
));
7639 /* If that failed, copy the address register to the reload register.
7640 Then add the constant to the reload register. */
7642 code
= recog_memoized (insn
);
7646 insn_extract (insn
);
7647 /* We want constrain operands to treat this insn strictly in
7648 its validity determination, i.e., the way it would after reload
7650 if (constrain_operands (code
, 1))
7652 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7654 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7659 delete_insns_since (last
);
7661 gen_reload (out
, op1
, opnum
, type
);
7662 insn
= emit_insn (gen_add2_insn (out
, op0
));
7663 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7666 #ifdef SECONDARY_MEMORY_NEEDED
7667 /* If we need a memory location to do the move, do it that way. */
7668 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7669 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7670 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7671 REGNO_REG_CLASS (REGNO (out
)),
7674 /* Get the memory to use and rewrite both registers to its mode. */
7675 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7677 if (GET_MODE (loc
) != GET_MODE (out
))
7678 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7680 if (GET_MODE (loc
) != GET_MODE (in
))
7681 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7683 gen_reload (loc
, in
, opnum
, type
);
7684 gen_reload (out
, loc
, opnum
, type
);
7688 /* If IN is a simple operand, use gen_move_insn. */
7689 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7690 emit_insn (gen_move_insn (out
, in
));
7692 #ifdef HAVE_reload_load_address
7693 else if (HAVE_reload_load_address
)
7694 emit_insn (gen_reload_load_address (out
, in
));
7697 /* Otherwise, just write (set OUT IN) and hope for the best. */
7699 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7701 /* Return the first insn emitted.
7702 We can not just return get_last_insn, because there may have
7703 been multiple instructions emitted. Also note that gen_move_insn may
7704 emit more than one insn itself, so we can not assume that there is one
7705 insn emitted per emit_insn_before call. */
7707 return last
? NEXT_INSN (last
) : get_insns ();
7710 /* Delete a previously made output-reload
7711 whose result we now believe is not needed.
7712 First we double-check.
7714 INSN is the insn now being processed.
7715 OUTPUT_RELOAD_INSN is the insn of the output reload.
7716 J is the reload-number for this insn. */
7719 delete_output_reload (insn
, j
, output_reload_insn
)
7722 rtx output_reload_insn
;
7726 /* Get the raw pseudo-register referred to. */
7728 rtx reg
= reload_in
[j
];
7729 while (GET_CODE (reg
) == SUBREG
)
7730 reg
= SUBREG_REG (reg
);
7732 /* If the pseudo-reg we are reloading is no longer referenced
7733 anywhere between the store into it and here,
7734 and no jumps or labels intervene, then the value can get
7735 here through the reload reg alone.
7736 Otherwise, give up--return. */
7737 for (i1
= NEXT_INSN (output_reload_insn
);
7738 i1
!= insn
; i1
= NEXT_INSN (i1
))
7740 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7742 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7743 && reg_mentioned_p (reg
, PATTERN (i1
)))
7745 /* If this is just a single USE with an REG_EQUAL note in front
7746 of INSN, this is no problem, because this mentions just the
7747 address that we are using here.
7748 But if there is more than one such USE, the insn might use
7749 the operand directly, or another reload might do that.
7750 This is analogous to the count_occurences check in the callers. */
7751 int num_occurences
= 0;
7753 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
7754 && find_reg_note (i1
, REG_EQUAL
, NULL_RTX
))
7756 num_occurences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7757 i1
= NEXT_INSN (i1
);
7759 if (num_occurences
== 1 && i1
== insn
)
7765 /* The caller has already checked that REG dies or is set in INSN.
7766 It has also checked that we are optimizing, and thus some inaccurancies
7767 in the debugging information are acceptable.
7768 So we could just delete output_reload_insn.
7769 But in some cases we can improve the debugging information without
7770 sacrificing optimization - maybe even improving the code:
7771 See if the pseudo reg has been completely replaced
7772 with reload regs. If so, delete the store insn
7773 and forget we had a stack slot for the pseudo. */
7774 if (reload_out
[j
] != reload_in
[j
]
7775 && REG_N_DEATHS (REGNO (reg
)) == 1
7776 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7777 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7781 /* We know that it was used only between here
7782 and the beginning of the current basic block.
7783 (We also know that the last use before INSN was
7784 the output reload we are thinking of deleting, but never mind that.)
7785 Search that range; see if any ref remains. */
7786 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7788 rtx set
= single_set (i2
);
7790 /* Uses which just store in the pseudo don't count,
7791 since if they are the only uses, they are dead. */
7792 if (set
!= 0 && SET_DEST (set
) == reg
)
7794 if (GET_CODE (i2
) == CODE_LABEL
7795 || GET_CODE (i2
) == JUMP_INSN
)
7797 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7798 && reg_mentioned_p (reg
, PATTERN (i2
)))
7800 /* Some other ref remains; just delete the output reload we
7802 delete_insn (output_reload_insn
);
7807 /* Delete the now-dead stores into this pseudo. */
7808 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7810 rtx set
= single_set (i2
);
7812 if (set
!= 0 && SET_DEST (set
) == reg
)
7814 /* This might be a basic block head,
7815 thus don't use delete_insn. */
7816 PUT_CODE (i2
, NOTE
);
7817 NOTE_SOURCE_FILE (i2
) = 0;
7818 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7820 if (GET_CODE (i2
) == CODE_LABEL
7821 || GET_CODE (i2
) == JUMP_INSN
)
7825 /* For the debugging info,
7826 say the pseudo lives in this reload reg. */
7827 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
7828 alter_reg (REGNO (reg
), -1);
7830 delete_insn (output_reload_insn
);
7834 /* Output reload-insns to reload VALUE into RELOADREG.
7835 VALUE is an autoincrement or autodecrement RTX whose operand
7836 is a register or memory location;
7837 so reloading involves incrementing that location.
7839 INC_AMOUNT is the number to increment or decrement by (always positive).
7840 This cannot be deduced from VALUE. */
7843 inc_for_reload (reloadreg
, value
, inc_amount
)
7848 /* REG or MEM to be copied and incremented. */
7849 rtx incloc
= XEXP (value
, 0);
7850 /* Nonzero if increment after copying. */
7851 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7857 /* No hard register is equivalent to this register after
7858 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7859 we could inc/dec that register as well (maybe even using it for
7860 the source), but I'm not sure it's worth worrying about. */
7861 if (GET_CODE (incloc
) == REG
)
7862 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7864 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7865 inc_amount
= - inc_amount
;
7867 inc
= GEN_INT (inc_amount
);
7869 /* If this is post-increment, first copy the location to the reload reg. */
7871 emit_insn (gen_move_insn (reloadreg
, incloc
));
7873 /* See if we can directly increment INCLOC. Use a method similar to that
7876 last
= get_last_insn ();
7877 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7878 gen_rtx_PLUS (GET_MODE (incloc
),
7881 code
= recog_memoized (add_insn
);
7884 insn_extract (add_insn
);
7885 if (constrain_operands (code
, 1))
7887 /* If this is a pre-increment and we have incremented the value
7888 where it lives, copy the incremented value to RELOADREG to
7889 be used as an address. */
7892 emit_insn (gen_move_insn (reloadreg
, incloc
));
7898 delete_insns_since (last
);
7900 /* If couldn't do the increment directly, must increment in RELOADREG.
7901 The way we do this depends on whether this is pre- or post-increment.
7902 For pre-increment, copy INCLOC to the reload register, increment it
7903 there, then save back. */
7907 emit_insn (gen_move_insn (reloadreg
, incloc
));
7908 emit_insn (gen_add2_insn (reloadreg
, inc
));
7909 emit_insn (gen_move_insn (incloc
, reloadreg
));
7914 Because this might be a jump insn or a compare, and because RELOADREG
7915 may not be available after the insn in an input reload, we must do
7916 the incrementation before the insn being reloaded for.
7918 We have already copied INCLOC to RELOADREG. Increment the copy in
7919 RELOADREG, save that back, then decrement RELOADREG so it has
7920 the original value. */
7922 emit_insn (gen_add2_insn (reloadreg
, inc
));
7923 emit_insn (gen_move_insn (incloc
, reloadreg
));
7924 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7930 /* Return 1 if we are certain that the constraint-string STRING allows
7931 the hard register REG. Return 0 if we can't be sure of this. */
7934 constraint_accepts_reg_p (string
, reg
)
7939 int regno
= true_regnum (reg
);
7942 /* Initialize for first alternative. */
7944 /* Check that each alternative contains `g' or `r'. */
7946 switch (c
= *string
++)
7949 /* If an alternative lacks `g' or `r', we lose. */
7952 /* If an alternative lacks `g' or `r', we lose. */
7955 /* Initialize for next alternative. */
7960 /* Any general reg wins for this alternative. */
7961 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
7965 /* Any reg in specified class wins for this alternative. */
7967 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
7969 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
7975 /* Return the number of places FIND appears within X, but don't count
7976 an occurrence if some SET_DEST is FIND. */
7979 count_occurrences (x
, find
)
7980 register rtx x
, find
;
7983 register enum rtx_code code
;
7984 register char *format_ptr
;
7992 code
= GET_CODE (x
);
8007 if (SET_DEST (x
) == find
)
8008 return count_occurrences (SET_SRC (x
), find
);
8015 format_ptr
= GET_RTX_FORMAT (code
);
8018 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8020 switch (*format_ptr
++)
8023 count
+= count_occurrences (XEXP (x
, i
), find
);
8027 if (XVEC (x
, i
) != NULL
)
8029 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8030 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
8038 /* This array holds values which are equivalent to a hard register
8039 during reload_cse_regs. Each array element is an EXPR_LIST of
8040 values. Each time a hard register is set, we set the corresponding
8041 array element to the value. Each time a hard register is copied
8042 into memory, we add the memory location to the corresponding array
8043 element. We don't store values or memory addresses with side
8044 effects in this array.
8046 If the value is a CONST_INT, then the mode of the containing
8047 EXPR_LIST is the mode in which that CONST_INT was referenced.
8049 We sometimes clobber a specific entry in a list. In that case, we
8050 just set XEXP (list-entry, 0) to 0. */
8052 static rtx
*reg_values
;
8054 /* This is a preallocated REG rtx which we use as a temporary in
8055 reload_cse_invalidate_regno, so that we don't need to allocate a
8056 new one each time through a loop in that function. */
8058 static rtx invalidate_regno_rtx
;
8060 /* This is a set of registers for which we must remove REG_DEAD notes in
8061 previous insns, because our modifications made them invalid. That can
8062 happen if we introduced the register into the current insn, or we deleted
8063 the current insn which used to set the register. */
8065 static HARD_REG_SET no_longer_dead_regs
;
8067 /* Invalidate any entries in reg_values which depend on REGNO,
8068 including those for REGNO itself. This is called if REGNO is
8069 changing. If CLOBBER is true, then always forget anything we
8070 currently know about REGNO. MODE is the mode of the assignment to
8071 REGNO, which is used to determine how many hard registers are being
8072 changed. If MODE is VOIDmode, then only REGNO is being changed;
8073 this is used when invalidating call clobbered registers across a
8077 reload_cse_invalidate_regno (regno
, mode
, clobber
)
8079 enum machine_mode mode
;
8085 /* Our callers don't always go through true_regnum; we may see a
8086 pseudo-register here from a CLOBBER or the like. We probably
8087 won't ever see a pseudo-register that has a real register number,
8088 for we check anyhow for safety. */
8089 if (regno
>= FIRST_PSEUDO_REGISTER
)
8090 regno
= reg_renumber
[regno
];
8094 if (mode
== VOIDmode
)
8095 endregno
= regno
+ 1;
8097 endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
8100 for (i
= regno
; i
< endregno
; i
++)
8103 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8107 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8109 if (XEXP (x
, 0) != 0
8110 && refers_to_regno_p (regno
, endregno
, XEXP (x
, 0), NULL_PTR
))
8112 /* If this is the only entry on the list, clear
8113 reg_values[i]. Otherwise, just clear this entry on
8115 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8125 /* We must look at earlier registers, in case REGNO is part of a
8126 multi word value but is not the first register. If an earlier
8127 register has a value in a mode which overlaps REGNO, then we must
8128 invalidate that earlier register. Note that we do not need to
8129 check REGNO or later registers (we must not check REGNO itself,
8130 because we would incorrectly conclude that there was a conflict). */
8132 for (i
= 0; i
< regno
; i
++)
8136 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8138 if (XEXP (x
, 0) != 0)
8140 PUT_MODE (invalidate_regno_rtx
, GET_MODE (x
));
8141 REGNO (invalidate_regno_rtx
) = i
;
8142 if (refers_to_regno_p (regno
, endregno
, invalidate_regno_rtx
,
8145 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8153 /* The memory at address MEM_BASE is being changed.
8154 Return whether this change will invalidate VAL. */
8157 reload_cse_mem_conflict_p (mem_base
, val
)
8165 code
= GET_CODE (val
);
8168 /* Get rid of a few simple cases quickly. */
8181 if (GET_MODE (mem_base
) == BLKmode
8182 || GET_MODE (val
) == BLKmode
)
8184 if (anti_dependence (val
, mem_base
))
8186 /* The address may contain nested MEMs. */
8193 fmt
= GET_RTX_FORMAT (code
);
8195 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8199 if (reload_cse_mem_conflict_p (mem_base
, XEXP (val
, i
)))
8202 else if (fmt
[i
] == 'E')
8206 for (j
= 0; j
< XVECLEN (val
, i
); j
++)
8207 if (reload_cse_mem_conflict_p (mem_base
, XVECEXP (val
, i
, j
)))
8215 /* Invalidate any entries in reg_values which are changed because of a
8216 store to MEM_RTX. If this is called because of a non-const call
8217 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8220 reload_cse_invalidate_mem (mem_rtx
)
8225 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8229 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8231 if (XEXP (x
, 0) != 0
8232 && reload_cse_mem_conflict_p (mem_rtx
, XEXP (x
, 0)))
8234 /* If this is the only entry on the list, clear
8235 reg_values[i]. Otherwise, just clear this entry on
8237 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8248 /* Invalidate DEST, which is being assigned to or clobbered. The
8249 second parameter exists so that this function can be passed to
8250 note_stores; it is ignored. */
8253 reload_cse_invalidate_rtx (dest
, ignore
)
8255 rtx ignore ATTRIBUTE_UNUSED
;
8257 while (GET_CODE (dest
) == STRICT_LOW_PART
8258 || GET_CODE (dest
) == SIGN_EXTRACT
8259 || GET_CODE (dest
) == ZERO_EXTRACT
8260 || GET_CODE (dest
) == SUBREG
)
8261 dest
= XEXP (dest
, 0);
8263 if (GET_CODE (dest
) == REG
)
8264 reload_cse_invalidate_regno (REGNO (dest
), GET_MODE (dest
), 1);
8265 else if (GET_CODE (dest
) == MEM
)
8266 reload_cse_invalidate_mem (dest
);
8269 /* Possibly delete death notes on the insns before INSN if modifying INSN
8270 extended the lifespan of the registers. */
8273 reload_cse_delete_death_notes (insn
)
8278 for (dreg
= 0; dreg
< FIRST_PSEUDO_REGISTER
; dreg
++)
8282 if (! TEST_HARD_REG_BIT (no_longer_dead_regs
, dreg
))
8285 for (trial
= prev_nonnote_insn (insn
);
8287 && GET_CODE (trial
) != CODE_LABEL
8288 && GET_CODE (trial
) != BARRIER
);
8289 trial
= prev_nonnote_insn (trial
))
8291 if (find_regno_note (trial
, REG_DEAD
, dreg
))
8293 remove_death (dreg
, trial
);
8300 /* Record that the current insn uses hard reg REGNO in mode MODE. This
8301 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
8302 notes for this register. */
8305 reload_cse_no_longer_dead (regno
, mode
)
8307 enum machine_mode mode
;
8309 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
8312 SET_HARD_REG_BIT (no_longer_dead_regs
, regno
);
8318 /* Do a very simple CSE pass over the hard registers.
8320 This function detects no-op moves where we happened to assign two
8321 different pseudo-registers to the same hard register, and then
8322 copied one to the other. Reload will generate a useless
8323 instruction copying a register to itself.
8325 This function also detects cases where we load a value from memory
8326 into two different registers, and (if memory is more expensive than
8327 registers) changes it to simply copy the first register into the
8330 Another optimization is performed that scans the operands of each
8331 instruction to see whether the value is already available in a
8332 hard register. It then replaces the operand with the hard register
8333 if possible, much like an optional reload would. */
8336 reload_cse_regs (first
)
8344 init_alias_analysis ();
8346 reg_values
= (rtx
*) alloca (FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8347 bzero ((char *)reg_values
, FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8349 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8350 free them when we are done. */
8351 push_obstacks (&reload_obstack
, &reload_obstack
);
8352 firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
8354 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8355 memory for a non-const call instruction. */
8356 callmem
= gen_rtx_MEM (BLKmode
, const0_rtx
);
8358 /* This is used in reload_cse_invalidate_regno to avoid consing a
8359 new REG in a loop in that function. */
8360 invalidate_regno_rtx
= gen_rtx_REG (VOIDmode
, 0);
8362 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8366 if (GET_CODE (insn
) == CODE_LABEL
)
8368 /* Forget all the register values at a code label. We don't
8369 try to do anything clever around jumps. */
8370 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8376 #ifdef NON_SAVING_SETJMP
8377 if (NON_SAVING_SETJMP
&& GET_CODE (insn
) == NOTE
8378 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
8380 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8387 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8390 CLEAR_HARD_REG_SET (no_longer_dead_regs
);
8392 /* If this is a call instruction, forget anything stored in a
8393 call clobbered register, or, if this is not a const call, in
8395 if (GET_CODE (insn
) == CALL_INSN
)
8397 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8398 if (call_used_regs
[i
])
8399 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8401 if (! CONST_CALL_P (insn
))
8402 reload_cse_invalidate_mem (callmem
);
8405 body
= PATTERN (insn
);
8406 if (GET_CODE (body
) == SET
)
8409 if (reload_cse_noop_set_p (body
, insn
))
8411 /* If this sets the return value of the function, we must keep
8412 a USE around, in case this is in a different basic block
8413 than the final USE. Otherwise, we could loose important
8414 register lifeness information on SMALL_REGISTER_CLASSES
8415 machines, where return registers might be used as spills:
8416 subsequent passes assume that spill registers are dead at
8417 the end of a basic block. */
8418 if (REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8421 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, SET_DEST (body
));
8422 INSN_CODE (insn
) = -1;
8423 REG_NOTES (insn
) = NULL_RTX
;
8424 push_obstacks (&reload_obstack
, &reload_obstack
);
8428 PUT_CODE (insn
, NOTE
);
8429 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8430 NOTE_SOURCE_FILE (insn
) = 0;
8432 reload_cse_delete_death_notes (insn
);
8434 /* We're done with this insn. */
8438 /* It's not a no-op, but we can try to simplify it. */
8439 CLEAR_HARD_REG_SET (no_longer_dead_regs
);
8440 count
+= reload_cse_simplify_set (body
, insn
);
8442 if (count
> 0 && apply_change_group ())
8443 reload_cse_delete_death_notes (insn
);
8444 else if (reload_cse_simplify_operands (insn
))
8445 reload_cse_delete_death_notes (insn
);
8447 reload_cse_record_set (body
, body
);
8449 else if (GET_CODE (body
) == PARALLEL
)
8452 rtx value
= NULL_RTX
;
8454 /* If every action in a PARALLEL is a noop, we can delete
8455 the entire PARALLEL. */
8456 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8458 rtx part
= XVECEXP (body
, 0, i
);
8459 if (GET_CODE (part
) == SET
)
8461 if (! reload_cse_noop_set_p (part
, insn
))
8463 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8467 value
= SET_DEST (part
);
8470 else if (GET_CODE (part
) != CLOBBER
)
8478 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8479 INSN_CODE (insn
) = -1;
8480 REG_NOTES (insn
) = NULL_RTX
;
8481 push_obstacks (&reload_obstack
, &reload_obstack
);
8485 PUT_CODE (insn
, NOTE
);
8486 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8487 NOTE_SOURCE_FILE (insn
) = 0;
8489 reload_cse_delete_death_notes (insn
);
8491 /* We're done with this insn. */
8495 /* It's not a no-op, but we can try to simplify it. */
8496 CLEAR_HARD_REG_SET (no_longer_dead_regs
);
8497 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8498 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8499 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8501 if (count
> 0 && apply_change_group ())
8502 reload_cse_delete_death_notes (insn
);
8503 else if (reload_cse_simplify_operands (insn
))
8504 reload_cse_delete_death_notes (insn
);
8506 /* Look through the PARALLEL and record the values being
8507 set, if possible. Also handle any CLOBBERs. */
8508 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8510 rtx x
= XVECEXP (body
, 0, i
);
8512 if (GET_CODE (x
) == SET
)
8513 reload_cse_record_set (x
, body
);
8515 note_stores (x
, reload_cse_invalidate_rtx
);
8519 note_stores (body
, reload_cse_invalidate_rtx
);
8522 /* Clobber any registers which appear in REG_INC notes. We
8523 could keep track of the changes to their values, but it is
8524 unlikely to help. */
8528 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
8529 if (REG_NOTE_KIND (x
) == REG_INC
)
8530 reload_cse_invalidate_rtx (XEXP (x
, 0), NULL_RTX
);
8534 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8535 after we have processed the insn. */
8536 if (GET_CODE (insn
) == CALL_INSN
)
8540 for (x
= CALL_INSN_FUNCTION_USAGE (insn
); x
; x
= XEXP (x
, 1))
8541 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
8542 reload_cse_invalidate_rtx (XEXP (XEXP (x
, 0), 0), NULL_RTX
);
8546 /* Free all the temporary structures we created, and go back to the
8547 regular obstacks. */
8548 obstack_free (&reload_obstack
, firstobj
);
8552 /* Return whether the values known for REGNO are equal to VAL. MODE
8553 is the mode of the object that VAL is being copied to; this matters
8554 if VAL is a CONST_INT. */
8557 reload_cse_regno_equal_p (regno
, val
, mode
)
8560 enum machine_mode mode
;
8567 for (x
= reg_values
[regno
]; x
; x
= XEXP (x
, 1))
8568 if (XEXP (x
, 0) != 0
8569 && rtx_equal_p (XEXP (x
, 0), val
)
8570 && (! flag_float_store
|| GET_CODE (XEXP (x
, 0)) != MEM
8571 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
8572 && (GET_CODE (val
) != CONST_INT
8573 || mode
== GET_MODE (x
)
8574 || (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8575 /* On a big endian machine if the value spans more than
8576 one register then this register holds the high part of
8577 it and we can't use it.
8579 ??? We should also compare with the high part of the
8581 && !(WORDS_BIG_ENDIAN
8582 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
8583 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
8584 GET_MODE_BITSIZE (GET_MODE (x
))))))
8590 /* See whether a single set is a noop. SET is the set instruction we
8591 are should check, and INSN is the instruction from which it came. */
8594 reload_cse_noop_set_p (set
, insn
)
8599 enum machine_mode dest_mode
;
8603 src
= SET_SRC (set
);
8604 dest
= SET_DEST (set
);
8605 dest_mode
= GET_MODE (dest
);
8607 if (side_effects_p (src
))
8610 dreg
= true_regnum (dest
);
8611 sreg
= true_regnum (src
);
8613 /* Check for setting a register to itself. In this case, we don't
8614 have to worry about REG_DEAD notes. */
8615 if (dreg
>= 0 && dreg
== sreg
)
8621 /* Check for setting a register to itself. */
8625 /* Check for setting a register to a value which we already know
8626 is in the register. */
8627 else if (reload_cse_regno_equal_p (dreg
, src
, dest_mode
))
8630 /* Check for setting a register DREG to another register SREG
8631 where SREG is equal to a value which is already in DREG. */
8636 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
8640 if (XEXP (x
, 0) == 0)
8643 if (dest_mode
== GET_MODE (x
))
8645 else if (GET_MODE_BITSIZE (dest_mode
)
8646 < GET_MODE_BITSIZE (GET_MODE (x
)))
8647 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
8652 && reload_cse_regno_equal_p (dreg
, tmp
, dest_mode
))
8660 else if (GET_CODE (dest
) == MEM
)
8662 /* Check for storing a register to memory when we know that the
8663 register is equivalent to the memory location. */
8665 && reload_cse_regno_equal_p (sreg
, dest
, dest_mode
)
8666 && ! side_effects_p (dest
))
8670 /* If we can delete this SET, then we need to look for an earlier
8671 REG_DEAD note on DREG, and remove it if it exists. */
8672 if (ret
&& dreg
>= 0)
8674 if (! find_regno_note (insn
, REG_UNUSED
, dreg
))
8675 reload_cse_no_longer_dead (dreg
, dest_mode
);
8681 /* Try to simplify a single SET instruction. SET is the set pattern.
8682 INSN is the instruction it came from.
8683 This function only handles one case: if we set a register to a value
8684 which is not a register, we try to find that value in some other register
8685 and change the set into a register copy. */
8688 reload_cse_simplify_set (set
, insn
)
8694 enum machine_mode dest_mode
;
8695 enum reg_class dclass
;
8698 dreg
= true_regnum (SET_DEST (set
));
8702 src
= SET_SRC (set
);
8703 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8706 dclass
= REGNO_REG_CLASS (dreg
);
8708 /* If memory loads are cheaper than register copies, don't change them. */
8709 if (GET_CODE (src
) == MEM
8710 && MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1) < 2)
8713 /* If the constant is cheaper than a register, don't change it. */
8714 if (CONSTANT_P (src
)
8715 && rtx_cost (src
, SET
) < 2)
8718 dest_mode
= GET_MODE (SET_DEST (set
));
8719 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8722 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i
), dclass
) == 2
8723 && reload_cse_regno_equal_p (i
, src
, dest_mode
))
8727 /* Pop back to the real obstacks while changing the insn. */
8730 validated
= validate_change (insn
, &SET_SRC (set
),
8731 gen_rtx_REG (dest_mode
, i
), 1);
8733 /* Go back to the obstack we are using for temporary
8735 push_obstacks (&reload_obstack
, &reload_obstack
);
8737 if (validated
&& ! find_regno_note (insn
, REG_UNUSED
, i
))
8739 reload_cse_no_longer_dead (i
, dest_mode
);
8747 /* Try to replace operands in INSN with equivalent values that are already
8748 in registers. This can be viewed as optional reloading.
8750 For each non-register operand in the insn, see if any hard regs are
8751 known to be equivalent to that operand. Record the alternatives which
8752 can accept these hard registers. Among all alternatives, select the
8753 ones which are better or equal to the one currently matching, where
8754 "better" is in terms of '?' and '!' constraints. Among the remaining
8755 alternatives, select the one which replaces most operands with
8759 reload_cse_simplify_operands (insn
)
8762 #ifdef REGISTER_CONSTRAINTS
8763 int insn_code_number
, n_operands
, n_alternatives
;
8766 char *constraints
[MAX_RECOG_OPERANDS
];
8768 /* Vector recording how bad an alternative is. */
8769 int *alternative_reject
;
8770 /* Vector recording how many registers can be introduced by choosing
8771 this alternative. */
8772 int *alternative_nregs
;
8773 /* Array of vectors recording, for each operand and each alternative,
8774 which hard register to substitute, or -1 if the operand should be
8776 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8777 /* Array of alternatives, sorted in order of decreasing desirability. */
8778 int *alternative_order
;
8779 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
8781 /* Find out some information about this insn. */
8782 insn_code_number
= recog_memoized (insn
);
8783 /* We don't modify asm instructions. */
8784 if (insn_code_number
< 0)
8787 n_operands
= insn_n_operands
[insn_code_number
];
8788 n_alternatives
= insn_n_alternatives
[insn_code_number
];
8790 if (n_alternatives
== 0 || n_operands
== 0)
8792 insn_extract (insn
);
8794 /* Figure out which alternative currently matches. */
8795 if (! constrain_operands (insn_code_number
, 1))
8796 fatal_insn_not_found (insn
);
8798 alternative_reject
= (int *) alloca (n_alternatives
* sizeof (int));
8799 alternative_nregs
= (int *) alloca (n_alternatives
* sizeof (int));
8800 alternative_order
= (int *) alloca (n_alternatives
* sizeof (int));
8801 bzero ((char *)alternative_reject
, n_alternatives
* sizeof (int));
8802 bzero ((char *)alternative_nregs
, n_alternatives
* sizeof (int));
8804 for (i
= 0; i
< n_operands
; i
++)
8806 enum machine_mode mode
;
8810 op_alt_regno
[i
] = (int *) alloca (n_alternatives
* sizeof (int));
8811 for (j
= 0; j
< n_alternatives
; j
++)
8812 op_alt_regno
[i
][j
] = -1;
8814 p
= constraints
[i
] = insn_operand_constraint
[insn_code_number
][i
];
8815 mode
= insn_operand_mode
[insn_code_number
][i
];
8817 /* Add the reject values for each alternative given by the constraints
8818 for this operand. */
8826 alternative_reject
[j
] += 3;
8828 alternative_reject
[j
] += 300;
8831 /* We won't change operands which are already registers. We
8832 also don't want to modify output operands. */
8833 regno
= true_regnum (recog_operand
[i
]);
8835 || constraints
[i
][0] == '='
8836 || constraints
[i
][0] == '+')
8839 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8841 int class = (int) NO_REGS
;
8843 if (! reload_cse_regno_equal_p (regno
, recog_operand
[i
], mode
))
8846 REGNO (reg
) = regno
;
8847 PUT_MODE (reg
, mode
);
8849 /* We found a register equal to this operand. Now look for all
8850 alternatives that can accept this register and have not been
8851 assigned a register they can use yet. */
8860 case '=': case '+': case '?':
8861 case '#': case '&': case '!':
8863 case '0': case '1': case '2': case '3': case '4':
8864 case 'm': case '<': case '>': case 'V': case 'o':
8865 case 'E': case 'F': case 'G': case 'H':
8866 case 's': case 'i': case 'n':
8867 case 'I': case 'J': case 'K': case 'L':
8868 case 'M': case 'N': case 'O': case 'P':
8869 #ifdef EXTRA_CONSTRAINT
8870 case 'Q': case 'R': case 'S': case 'T': case 'U':
8873 /* These don't say anything we care about. */
8877 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8882 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER (c
)];
8885 case ',': case '\0':
8886 /* See if REGNO fits this alternative, and set it up as the
8887 replacement register if we don't have one for this
8888 alternative yet and the operand being replaced is not
8889 a cheap CONST_INT. */
8890 if (op_alt_regno
[i
][j
] == -1
8891 && reg_fits_class_p (reg
, class, 0, mode
)
8892 && (GET_CODE (recog_operand
[i
]) != CONST_INT
8893 || rtx_cost (recog_operand
[i
], SET
) > rtx_cost (reg
, SET
)))
8895 alternative_nregs
[j
]++;
8896 op_alt_regno
[i
][j
] = regno
;
8908 /* Record all alternatives which are better or equal to the currently
8909 matching one in the alternative_order array. */
8910 for (i
= j
= 0; i
< n_alternatives
; i
++)
8911 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8912 alternative_order
[j
++] = i
;
8915 /* Sort it. Given a small number of alternatives, a dumb algorithm
8916 won't hurt too much. */
8917 for (i
= 0; i
< n_alternatives
- 1; i
++)
8920 int best_reject
= alternative_reject
[alternative_order
[i
]];
8921 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8924 for (j
= i
+ 1; j
< n_alternatives
; j
++)
8926 int this_reject
= alternative_reject
[alternative_order
[j
]];
8927 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8929 if (this_reject
< best_reject
8930 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8933 best_reject
= this_reject
;
8934 best_nregs
= this_nregs
;
8938 tmp
= alternative_order
[best
];
8939 alternative_order
[best
] = alternative_order
[i
];
8940 alternative_order
[i
] = tmp
;
8943 /* Substitute the operands as determined by op_alt_regno for the best
8945 j
= alternative_order
[0];
8946 CLEAR_HARD_REG_SET (no_longer_dead_regs
);
8948 /* Pop back to the real obstacks while changing the insn. */
8951 for (i
= 0; i
< n_operands
; i
++)
8953 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][i
];
8954 if (op_alt_regno
[i
][j
] == -1)
8957 reload_cse_no_longer_dead (op_alt_regno
[i
][j
], mode
);
8958 validate_change (insn
, recog_operand_loc
[i
],
8959 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8962 for (i
= insn_n_dups
[insn_code_number
] - 1; i
>= 0; i
--)
8964 int op
= recog_dup_num
[i
];
8965 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][op
];
8967 if (op_alt_regno
[op
][j
] == -1)
8970 reload_cse_no_longer_dead (op_alt_regno
[op
][j
], mode
);
8971 validate_change (insn
, recog_dup_loc
[i
],
8972 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8975 /* Go back to the obstack we are using for temporary
8977 push_obstacks (&reload_obstack
, &reload_obstack
);
8979 return apply_change_group ();
8985 /* These two variables are used to pass information from
8986 reload_cse_record_set to reload_cse_check_clobber. */
8988 static int reload_cse_check_clobbered
;
8989 static rtx reload_cse_check_src
;
8991 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8992 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8993 second argument, which is passed by note_stores, is ignored. */
8996 reload_cse_check_clobber (dest
, ignore
)
8998 rtx ignore ATTRIBUTE_UNUSED
;
9000 if (reg_overlap_mentioned_p (dest
, reload_cse_check_src
))
9001 reload_cse_check_clobbered
= 1;
9004 /* Record the result of a SET instruction. SET is the set pattern.
9005 BODY is the pattern of the insn that it came from. */
9008 reload_cse_record_set (set
, body
)
9014 enum machine_mode dest_mode
;
9016 dest
= SET_DEST (set
);
9017 src
= SET_SRC (set
);
9018 dreg
= true_regnum (dest
);
9019 sreg
= true_regnum (src
);
9020 dest_mode
= GET_MODE (dest
);
9022 /* Some machines don't define AUTO_INC_DEC, but they still use push
9023 instructions. We need to catch that case here in order to
9024 invalidate the stack pointer correctly. Note that invalidating
9025 the stack pointer is different from invalidating DEST. */
9027 while (GET_CODE (x
) == SUBREG
9028 || GET_CODE (x
) == ZERO_EXTRACT
9029 || GET_CODE (x
) == SIGN_EXTRACT
9030 || GET_CODE (x
) == STRICT_LOW_PART
)
9032 if (push_operand (x
, GET_MODE (x
)))
9034 reload_cse_invalidate_rtx (stack_pointer_rtx
, NULL_RTX
);
9035 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9039 /* We can only handle an assignment to a register, or a store of a
9040 register to a memory location. For other cases, we just clobber
9041 the destination. We also have to just clobber if there are side
9042 effects in SRC or DEST. */
9043 if ((dreg
< 0 && GET_CODE (dest
) != MEM
)
9044 || side_effects_p (src
)
9045 || side_effects_p (dest
))
9047 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9052 /* We don't try to handle values involving CC, because it's a pain
9053 to keep track of when they have to be invalidated. */
9054 if (reg_mentioned_p (cc0_rtx
, src
)
9055 || reg_mentioned_p (cc0_rtx
, dest
))
9057 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9062 /* If BODY is a PARALLEL, then we need to see whether the source of
9063 SET is clobbered by some other instruction in the PARALLEL. */
9064 if (GET_CODE (body
) == PARALLEL
)
9068 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9072 x
= XVECEXP (body
, 0, i
);
9076 reload_cse_check_clobbered
= 0;
9077 reload_cse_check_src
= src
;
9078 note_stores (x
, reload_cse_check_clobber
);
9079 if (reload_cse_check_clobbered
)
9081 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9091 /* This is an assignment to a register. Update the value we
9092 have stored for the register. */
9097 /* This is a copy from one register to another. Any values
9098 which were valid for SREG are now valid for DREG. If the
9099 mode changes, we use gen_lowpart_common to extract only
9100 the part of the value that is copied. */
9101 reg_values
[dreg
] = 0;
9102 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9106 if (XEXP (x
, 0) == 0)
9108 if (dest_mode
== GET_MODE (XEXP (x
, 0)))
9110 else if (GET_MODE_BITSIZE (dest_mode
)
9111 > GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
9114 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9116 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, tmp
,
9121 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, src
, NULL_RTX
);
9123 /* We've changed DREG, so invalidate any values held by other
9124 registers that depend upon it. */
9125 reload_cse_invalidate_regno (dreg
, dest_mode
, 0);
9127 /* If this assignment changes more than one hard register,
9128 forget anything we know about the others. */
9129 for (i
= 1; i
< HARD_REGNO_NREGS (dreg
, dest_mode
); i
++)
9130 reg_values
[dreg
+ i
] = 0;
9132 else if (GET_CODE (dest
) == MEM
)
9134 /* Invalidate conflicting memory locations. */
9135 reload_cse_invalidate_mem (dest
);
9137 /* If we're storing a register to memory, add DEST to the list
9139 if (sreg
>= 0 && ! side_effects_p (dest
))
9140 reg_values
[sreg
] = gen_rtx_EXPR_LIST (dest_mode
, dest
,
9145 /* We should have bailed out earlier. */