1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998-2021 Free Software Foundation, Inc.
3 ;; Contributed by Axis Communications.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The original PO technology requires these to be ordered by speed,
22 ;; so that assigner will pick the fastest.
24 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
27 ;; There are several instructions that are orthogonal in size, and seems
28 ;; they could be matched by a single pattern without a specified size
29 ;; for the operand that is orthogonal. However, this did not work on
30 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
31 ;; constant is substituted into an operand, the actual mode must be
32 ;; deduced from the pattern. There is reasonable hope that that has been
33 ;; fixed, so FIXME: try again.
35 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
36 ;; are marked with a "!" constraint modifier to avoid being reloaded
37 ;; into. This is because gcc would otherwise prefer to use the constant
38 ;; pool and its offsettable address instead of reloading to an
39 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
40 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
42 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
43 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
44 ;; pointer). Thus the instructions that get into trouble have specific
45 ;; checks against matching frame_pointer_rtx.
46 ;; ??? But it should be re-checked for gcc > 2.7.2
47 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
51 ;; Stack frame deallocation barrier.
52 CRIS_UNSPEC_FRAME_DEALLOC
54 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
60 [(CRIS_STATIC_CHAIN_REGNUM 7)
61 (CRIS_REAL_FP_REGNUM 8)
71 ;; We need an attribute to define whether an instruction can be put in
72 ;; a branch-delay slot or not, and whether it has a delay slot.
74 ;; Branches and return instructions have a delay slot, and cannot
75 ;; themselves be put in a delay slot. This has changed *for short
76 ;; branches only* between architecture variants, but the possible win
77 ;; is presumed negligible compared to the added complexity of the machine
78 ;; description: one would have to add always-correct infrastructure to
79 ;; distinguish short branches.
81 ;; Whether an instruction can be put in a delay slot depends on the
82 ;; instruction (all short instructions except jumps and branches)
83 ;; and the addressing mode (must not be prefixed or referring to pc).
84 ;; In short, any "slottable" instruction must be 16 bit and not refer
85 ;; to pc, or alter it.
87 ;; The possible values are "yes", "no", "has_slot", and "has_return_slot".
88 ;; Yes/no tells whether the insn is slottable or not.
89 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
90 ;; call delay slot, as it's located in the address *after* the call insn,
91 ;; and the unwind machinery doesn't know about delay slots.
92 ;; Has_slot means that the insn is a branch insn (which are
93 ;; not considered slottable since that is generally true). Having the
94 ;; seemingly illogical value "has_slot" means we do not have to add
95 ;; another attribute just to say that an insn has a delay-slot, since it
96 ;; also infers that it is not slottable. Better names for the attribute
97 ;; were found to be longer and not add readability to the machine
99 ;; Has_return_slot is similar, for the return insn.
101 ;; The default that is defined here for this attribute is "no", not
102 ;; slottable, not having a delay-slot, so there's no need to worry about
103 ;; it being wrong for non-branch and return instructions.
104 ;; The default could depend on the kind of insn and the addressing
105 ;; mode, but that would need more attributes and hairier, more error
108 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
109 ;; register. The constraints 'Q' and '>' together match all possible
110 ;; memory operands that are slottable.
111 ;; For other operands, you need to check if it has a valid "slottable"
112 ;; quick-immediate operand, where the particular signedness-variation
113 ;; may match the constraints 'I' or 'J'.), and include it in the
114 ;; constraint pattern for the slottable pattern. An alternative using
115 ;; only "r" constraints is most often slottable.
117 (define_attr "slottable" "no,yes,has_slot,has_return_slot"
120 ;; We also need attributes to sanely determine the condition code
121 ;; state. This attribute isn't used as-is, just as a template,
122 ;; effectively a dummy except in a substitution setting CRIS_CC0_REGNUM
123 ;; to a specific value.
124 (define_attr "cc" "none,clobber,normal" (const_string "normal"))
126 ;; The attribute "_enabled" is appended to "cc", forming "cc_enabled" to
127 ;; pick out certain alternatives when generating a useful
128 ;; condition-code-setting. See the "enabled" attribute.
129 (define_attr "cc_enabled" "none,clobber,normal" (const_string "normal"))
131 ;; At the moment, this attribute is just used to help bb-reorder do its
132 ;; work; the default 0 doesn't help it. Many insns have other lengths,
133 ;; though none are shorter.
134 (define_attr "length" "" (const_int 2))
136 ;; A branch has one delay-slot. The instruction in the
137 ;; delay-slot is always executed, independent of whether the branch is
138 ;; taken or not. Note that besides setting "slottable" to "has_slot",
139 ;; there also has to be a "%#" at the end of a "delayed" instruction
140 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
141 ;; catch it and print a "nop" if necessary. This method was stolen from
144 (define_delay (eq_attr "slottable" "has_slot")
145 [(eq_attr "slottable" "yes") (nil) (nil)])
147 ;; The insn in the return insn slot must not be the
148 ;; return-address-register restore. FIXME: Use has_slot and express
149 ;; as a parallel with a use of the return-address-register (currently
150 ;; only SRP). However, this requires an amount of fixing tests for
151 ;; naked RETURN in middle-end.
152 (define_delay (eq_attr "slottable" "has_return_slot")
153 [(and (eq_attr "slottable" "yes")
154 (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")))
157 (define_attr "enabled" "no,yes"
159 (eq_attr "cc_enabled" "normal")
161 (const_string "no")))
163 ;; Iterator definitions.
165 ;; For the "usual" pattern size alternatives.
166 (define_mode_iterator BWD [SI HI QI])
167 (define_mode_iterator BWDD [DI SI HI QI])
169 ;; To be able to refer to the same mode_attr for both a multi-mode
170 ;; and a mode-specific pattern, we use some singleton iterators.
171 (define_mode_iterator DI_ [DI])
172 (define_mode_iterator SI_ [SI])
174 (define_mode_iterator WD [SI HI])
175 (define_mode_iterator BW [HI QI])
176 (define_mode_attr S [(SI "HI") (HI "QI")])
177 (define_mode_attr s [(SI "hi") (HI "qi")])
178 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
179 (define_mode_attr mm [(SI ".w") (HI ".b")])
180 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
182 ;; For the sign_extend+zero_extend variants.
183 (define_code_iterator szext [sign_extend zero_extend])
184 (define_code_attr u [(sign_extend "") (zero_extend "u")])
185 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
187 ;; For extended-operand variants.
188 (define_code_iterator plusminus [plus minus])
189 (define_code_attr addsub [(plus "add") (minus "sub")])
191 ;; Similar, other cases also matching bound/umin.
192 (define_code_iterator plusminusumin [plus minus umin])
194 ;; Ditto, commutative operators (i.e. not minus).
195 (define_code_iterator plusumin [plus umin])
197 ;; The addsubbo and nd code-attributes form a hack. We need to output
198 ;; "addu.b", "subu.b" but "bound.b" (no "u"-suffix) which means we'd
199 ;; need to refer to one iterator from the next. But, that can't be
200 ;; done. Instead output the "u" for unsigned as the "u" in "bound",
201 ;; i.e. the mnemonic as three parts including the extend-letter, and
202 ;; with an empty third part for "add" and "sub".
203 (define_code_attr addsubbo [(plus "add") (minus "sub") (umin "bo")])
204 (define_code_attr nd [(plus "") (minus "") (umin "nd")])
206 ;; For the shift variants.
207 (define_code_iterator shift [ashiftrt lshiftrt ashift])
208 (define_code_iterator shiftrt [ashiftrt lshiftrt])
209 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
210 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
212 ;; Compares, branches, cbranch, cstore. Conditions gt and le are CC_NZVC.
213 ;; Others start out as CCmode and can degenerate to CC_NZmode.
214 ;; Incidental setters are either CC_NZVCmode or CC_NZmode. See also
216 (define_mode_iterator NZSET [CC_NZ])
217 (define_mode_iterator NZUSE [CC CC_NZ CC_NZVC])
218 (define_mode_iterator NZVCSET [CC CC_NZVC CC_NZ])
219 (define_mode_iterator NZVCUSE [CC_NZVC])
220 (define_mode_iterator ZnNNZSET [CC_ZnN CC_NZ])
221 (define_mode_iterator ZnNNZUSE [CC CC_ZnN CC_NZ CC_NZVC])
224 (define_code_iterator cond [eq ne gtu ltu geu leu gt le lt ge])
226 ;; Just equal and not equal.
227 (define_code_iterator zcond [eq ne])
229 ;; Conditions that look only at Z and/or N (or can do with that).
230 (define_code_iterator nzcond [eq ne gtu leu lt ge])
232 ;; The complement of nzcond within cond; conditions that look (also) on V
234 (define_code_iterator nzvccond [geu ltu gt le])
236 ;; Within nzcond, those that give different opcodes when operands are
237 ;; reversed or that can ignore V or C. Also, the complement of zcond
239 (define_code_iterator rnzcond [gtu leu lt ge])
241 ;; CRIS condition mnemonic.
242 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
243 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
245 ;; CRIS reverse condition mnemonic.
246 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
247 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
249 ;; Mnemomic for the CRIS condition when V or C can be ignored.
250 (define_code_attr oCC [(lt "mi") (ge "pl") (gtu "eq") (ltu "ne")])
253 (define_code_attr roCC [(lt "pl") (ge "mi") (gtu "eq") (ltu "ne")])
255 ;; CC_Z_IN_NOT_N, a.k.a. CC_ZnNmode.
256 (define_code_attr znnCC [(eq "pl") (ne "mi")])
258 ;;; ...and the reverse
259 (define_code_attr rznnCC [(eq "mi") (ne "pl")])
261 ;; Required unoptimized CCmode, different for nzcond and nzvccond.
262 (define_code_attr xCC [(eq "CC") (ne "CC") (gtu "CC") (ltu "CC_NZVC")
263 (geu "CC_NZVC") (leu "CC") (lt "CC") (ge "CC")
264 (gt "CC_NZVC") (le "CC_NZVC")])
266 ;; Substitutions to describe condition-code settings.
268 (define_subst_attr "setnz" "setnz_subst" "" "_setnz")
269 (define_subst_attr "ccnz" "setnz_subst" "" "_enabled")
270 (define_subst_attr "anz" "setnz_subst" "" "*")
272 (define_subst "setnz_subst"
273 [(set (match_operand 0)
275 (clobber (reg:CC CRIS_CC0_REGNUM))]
277 [(set (reg:CC_NZ CRIS_CC0_REGNUM)
278 (compare:CC_NZ (match_dup 1) (const_int 0)))
279 (set (match_dup 0) (match_dup 1))])
281 (define_subst_attr "setnzvc" "setnzvc_subst" "" "_setnzvc")
282 (define_subst_attr "ccnzvc" "setnzvc_subst" "" "_enabled")
283 (define_subst_attr "anzvc" "setnzvc_subst" "" "*")
285 (define_subst "setnzvc_subst"
286 [(set (match_operand 0)
288 (clobber (reg:CC CRIS_CC0_REGNUM))]
290 [(set (reg:CC_NZVC CRIS_CC0_REGNUM)
291 (compare:CC_NZVC (match_dup 1) (const_int 0)))
292 (set (match_dup 0) (match_dup 1))])
294 (define_subst_attr "setcc" "setcc_subst" "" "_setcc")
295 (define_subst_attr "cccc" "setcc_subst" "" "_enabled")
296 (define_subst_attr "acc" "setcc_subst" "" "*")
298 (define_subst "setcc_subst"
299 [(set (match_operand 0)
301 (clobber (reg:CC CRIS_CC0_REGNUM))]
303 [(set (reg:CC CRIS_CC0_REGNUM)
304 (compare:CC (match_dup 1) (const_int 0)))
305 (set (match_dup 0) (match_dup 1))])
307 ;; Operand and operator predicates.
309 (include "predicates.md")
310 (include "constraints.md")
312 ;; It seems that the position of the sign-bit and the fact that 0.0 is
313 ;; all 0-bits would make "tstsf" a straight-forward implementation;
314 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
317 ;; FIXME: Do that some time.
321 ;; These are used for compare insn, cbranch and cstore.
322 ;; FIXME: Port-local reversing of operands is not done. Still needed?
323 ;; (It shouldn't be; it should be done as part of register allocation.)
324 (define_mode_attr sCC_destc
325 [(DI "r, r,r,r,r,r,r") (SI "r,r, r, r,r,r") (HI "r, r, r,r") (QI "r, r, r,r")])
326 (define_mode_attr cmp_op0c
327 [(DI "rm,r,r,r,r,r,r") (SI "r,r, rQ>,r,r,m") (HI "r, rQ>,r,m") (QI "r, rQ>,r,m")])
328 (define_mode_attr cmp_op1c
329 [(DI "M,Kc,I,P,n,r,o") (SI "I,rQ>,M, P,g,M") (HI "rQ>,M, g,M") (QI "rQ>,M, g,M")])
331 ;; We could optimize the sizes of the immediate operands for various
332 ;; cases, but that is not worth it because of the very little usage of
333 ;; DImode for anything else but a structure/block-mode. Just do the
334 ;; obvious stuff for the straight-forward constraint letters.
336 (define_insn "*cmpdi<NZVCSET:mode>"
337 [(set (reg:NZVCSET CRIS_CC0_REGNUM)
339 (match_operand:DI_ 0 "nonimmediate_operand" "<cmp_op0c>")
340 (match_operand:DI_ 1 "general_operand" "<cmp_op1c>")))]
343 test.d %M0\;ax\;test.d %H0
344 cmpq %1,%M0\;ax\;cmpq 0,%H0
345 cmpq %1,%M0\;ax\;cmpq -1,%H0
346 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
347 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
348 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
349 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
351 ;; Note that compare insns with side effect addressing mode (e.g.):
353 ;; cmp.S [rx=ry+i],rz;
354 ;; cmp.S [%3=%1+%2],%0
356 ;; are *not* usable for gcc since the reloader *does not accept*
357 ;; cc0-changing insns with side-effects other than setting the condition
358 ;; codes. The reason is that the reload stage *may* cause another insn to
359 ;; be output after the main instruction, in turn invalidating cc0 for the
360 ;; insn using the test. (This does not apply to the CRIS case, since a
361 ;; reload for output -- move to memory -- does not change the condition
362 ;; code. Unfortunately we have no way to describe that at the moment. I
363 ;; think code would improve being in the order of one percent faster.
365 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
366 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
367 ;; constants, but sometimes gcc will find its way to use it for other
368 ;; (memory) operands. Avoid side-effect patterns, though (see above).
370 (define_insn "*cmp_ext<BW:mode><NZVCSET:mode>"
371 [(set (reg:NZVCSET CRIS_CC0_REGNUM)
373 (match_operand:SI 0 "register_operand" "r,r")
374 (match_operator:SI 2 "cris_extend_operator"
375 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
378 [(set_attr "slottable" "yes,no")])
380 ;; The "normal" compare patterns, from SI on. Special-cases with zero
381 ;; are covered above.
383 (define_insn "*cmpsi<NZVCSET:mode>"
384 [(set (reg:NZVCSET CRIS_CC0_REGNUM)
386 (match_operand:SI_ 0 "nonimmediate_operand" "<cmp_op0c>")
387 (match_operand:SI_ 1 "general_operand" "<cmp_op1c>")))]
396 [(set_attr "slottable" "yes,yes,yes,no,no,no")])
398 (define_insn "*cmp<BW:mode><NZVCSET:mode>"
399 [(set (reg:NZVCSET CRIS_CC0_REGNUM)
401 (match_operand:BW 0 "nonimmediate_operand" "<cmp_op0c>")
402 (match_operand:BW 1 "general_operand" "<cmp_op1c>")))]
409 [(set_attr "slottable" "yes,yes,no,no")])
411 ;; Pattern matching the BTST insn.
412 ;; It is useful for "if (i & val)" constructs, where val is an exact
413 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
414 ;; of zeros starting at bit 0).
416 ;; SImode. This mode is the only one needed, since gcc automatically
417 ;; extends subregs for lower-size modes.
418 (define_insn "*btst<mode>"
419 [(set (reg:ZnNNZSET CRIS_CC0_REGNUM)
422 (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp")
423 (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n")
424 (match_operand:SI 2 "nonmemory_operand" "M, M,Kc,n,r, r,r"))
426 ;; Either it is a single bit, or consecutive ones starting at 0.
428 && CONST_INT_P (operands[1])
429 && ((operands[1] == const1_rtx && <MODE>mode == CC_ZnNmode)
430 || (operands[2] == const0_rtx && <MODE>mode == CC_NZmode))
431 && (REG_S_P (operands[0])
432 || (operands[1] == const1_rtx
433 && REG_S_P (operands[2])
434 && CONST_INT_P (operands[0])
435 && exact_log2 (INTVAL (operands[0])) >= 0))
438 ;; The next-to-last "&&" condition above should be caught by some kind of
439 ;; canonicalization in gcc, but we can easily help with it here.
440 ;; It results from expressions of the type
441 ;; "power_of_2_value & (1 << y)". FIXME: Add testcase.
443 ;; Since there may be codes with tests in on bits (in constant position)
444 ;; beyond the size of a word, handle that by assuming those bits are 0.
445 ;; GCC should handle that, but it's a matter of easily-added belts while
446 ;; having suspenders.
456 [(set_attr "slottable" "yes")])
460 ;; The whole mandatory movdi family is here; expander, "anonymous"
461 ;; recognizer and splitter. We're forced to have a movdi pattern,
462 ;; although GCC should be able to split it up itself. Normally it can,
463 ;; but if other insns have DI operands (as is the case here), reload
464 ;; must be able to generate or match a movdi. many testcases fail at
465 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
466 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
467 ;; However, a patch from Richard Kenner (similar to the cause of
468 ;; discussion at the URL above), indicates otherwise. See
469 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
470 ;; The truth has IMO is not been decided yet, so check from time to
471 ;; time by disabling the movdi patterns.
473 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
474 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
475 ;; A cmpdi RTX needs reloading (global):
476 ;; (insn 185 326 186 (set (cc0)
477 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
478 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
480 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
481 ;; out of the instruction (into a register), since one of the operands
482 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
483 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
484 ;; wrt. overlap). The bad things happen with the synthesis in
485 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
486 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
487 ;; 22 is recognized to have an equivalent in memory which is substituted
488 ;; straight in, and we end up with an unrecognizable insn:
489 ;; (insn 325 324 326 (set (reg:SI 9 r9)
490 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
491 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
493 ;; which is the first part of the reloaded synthesized "movdi".
494 ;; The right thing would be to add equivalent replacement locations for
495 ;; insn with pseudos that need more reloading. The question is where.
497 (define_expand "movdi"
499 [(set (match_operand:DI 0 "nonimmediate_operand")
500 (match_operand:DI 1 "general_operand"))
501 (clobber (reg:CC CRIS_CC0_REGNUM))])]
504 if (MEM_P (operands[0])
505 && operands[1] != const0_rtx
506 && can_create_pseudo_p ())
507 operands[1] = copy_to_mode_reg (DImode, operands[1]);
509 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
510 prefer to split up constants early, like this. The testcase in
511 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
512 resulting subreg sets when using the construct from mcore (as of FSF
513 CVS, version -r 1.5), and it believes that the high part (the last one
514 emitted) is the final value. */
515 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
516 && ! reload_completed
517 && ! reload_in_progress)
520 rtx op0 = operands[0];
521 rtx op1 = operands[1];
524 emit_move_insn (operand_subword (op0, 0, 1, DImode),
525 operand_subword (op1, 0, 1, DImode));
526 emit_move_insn (operand_subword (op0, 1, 1, DImode),
527 operand_subword (op1, 1, 1, DImode));
528 insns = get_insns ();
536 (define_insn_and_split "*movdi_insn"
537 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
538 (match_operand:DI 1 "general_operand" "rx,g,rxM"))
539 (clobber (reg:CC CRIS_CC0_REGNUM))]
540 "(register_operand (operands[0], DImode)
541 || register_operand (operands[1], DImode)
542 || operands[1] == const0_rtx)"
544 "&& reload_completed"
546 "operands[2] = cris_split_movdx (operands);")
548 ;; Normal move patterns from SI on.
550 (define_expand "movsi"
553 (match_operand:SI 0 "nonimmediate_operand")
554 (match_operand:SI 1 "general_operand"))
555 (clobber (reg:CC CRIS_CC0_REGNUM))])]
558 /* If the output goes to a MEM, make sure we have zero or a register as
560 if (MEM_P (operands[0])
561 && ! REG_S_P (operands[1])
562 && operands[1] != const0_rtx
563 && can_create_pseudo_p ())
564 operands[1] = force_reg (SImode, operands[1]);
566 /* At post-reload time, we'll get here for e.g. split multi-mode insns
567 with a memory destination. Go directly to the clobber-less variant.
568 FIXME: Also applies to special-register source or destination. */
570 && (MEM_P (operands[0]) || operands[1] == const0_rtx))
572 emit_insn (gen_rtx_SET (operands[0], operands[1]));
577 ;; We provide CC, CC_NZ and CC_NZVC variants, as moves clear V and C
578 ;; and the result is thus usable in a compare against 0.
579 (define_insn "*movsi_internal<setcc><setnz><setnzvc>"
581 (match_operand:SI 0 "nonimmediate_operand"
582 "=r,r, r,Q>,r,Q>,g,r,r,g,rQ>,x, m,x")
583 (match_operand:SI 1 "general_operand"
584 "r,Q>,M,M, I,r, M,n,g,r,x, rQ>,x,gi"))
585 (clobber (reg:CC CRIS_CC0_REGNUM))]
586 ;; Note that we prefer not to use the S alternative (if for some reason
587 ;; it competes with others) above, but g matches S.
590 /* Better to have c-switch here; it is worth it to optimize the size of
591 move insns. The alternative would be to try to find more constraint
592 letters. FIXME: Check again. It seems this could shrink a bit. */
593 switch (which_alternative)
600 return "move.d %1,%0";
613 /* Constants -32..31 except 0. */
615 return "moveq %1,%0";
617 /* We can win a little on constants -32768..-33, 32..65535. */
619 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
621 if (INTVAL (operands[1]) < 256)
622 return "movu.b %1,%0";
623 return "movu.w %1,%0";
625 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
627 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
628 return "movs.b %1,%0";
629 return "movs.w %1,%0";
631 return "move.d %1,%0";
637 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,yes,yes,no,no")
638 (set_attr "cc<cccc><ccnz><ccnzvc>"
639 "*,*,none,none,*,none,none,*,*,none,none,none,none,none")])
643 (define_insn "<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"
645 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
646 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))
647 (clobber (reg:CC CRIS_CC0_REGNUM))]
650 switch (which_alternative)
657 return "move.w %1,%0";
666 return "moveq %1,%0";
669 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
671 if (INTVAL (operands[1]) > 0)
672 return "movu.b %1,%0";
673 return "movs.b %1,%0";
675 return "move.w %1,%0";
677 return "movEq %b1,%0";
679 return "BOGUS: %1 to %0";
682 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
683 (set_attr "cc<cccc><ccnz><ccnzvc>" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
685 (define_insn "movstricthi"
688 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
689 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))
690 (clobber (reg:CC CRIS_CC0_REGNUM))]
701 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
703 (define_expand "reload_in<mode>"
704 [(set (match_operand:BW 2 "register_operand" "=r")
705 (match_operand:BW 1 "memory_operand" "m"))
706 (set (match_operand:BW 0 "register_operand" "=x")
711 (define_expand "reload_out<mode>"
712 [(set (match_operand:BW 2 "register_operand" "=&r")
713 (match_operand:BW 1 "register_operand" "x"))
714 (set (match_operand:BW 0 "memory_operand" "=m")
719 (define_insn "<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"
720 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
721 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))
722 (clobber (reg:CC CRIS_CC0_REGNUM))]
737 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
738 (set_attr "cc<cccc><ccnz><ccnzvc>"
739 "*,none,*,none,none,*,none,none,clobber,*,none,none")])
741 (define_insn "movstrictqi"
742 [(set (strict_low_part
743 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
744 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))
745 (clobber (reg:CC CRIS_CC0_REGNUM))]
756 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
758 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
759 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
760 ;; all ones); the worthwhile one is "0.0".
761 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
764 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
765 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))
766 (clobber (reg:CC CRIS_CC0_REGNUM))]
783 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
785 ;; Post-reload, for memory destinations, split the clobber-variant and
786 ;; get rid of the clobber.
788 (define_split ;; "*mov_tomem<mode>_split"
789 [(set (match_operand:BWD 0 "memory_operand")
790 (match_operand:BWD 1 "nonmemory_operand"))
791 (clobber (reg:CC CRIS_CC0_REGNUM))]
793 [(set (match_dup 0) (match_dup 1))]
796 ;; Exclude moving special-registers to memory from matching for
797 ;; less-than-SImode, as they are SImode only (or actually, the size of
798 ;; the register, but the ones free for "x" are naturally SImode; see
799 ;; special measures taken for reload).
800 ;; This might be a belt-and-suspenders thing, as a move from special
801 ;; register to memory in less-than-SImode should not have made it here.
803 (define_mode_attr mov_tomem_enabled
804 [(SI "yes,yes,yes,yes,yes,yes")
805 (HI "yes,yes,no,yes,yes,no")
806 (QI "yes,yes,no,yes,yes,no")])
808 (define_insn "*mov_tomem<mode>"
809 [(set (match_operand:BWD 0 "memory_operand" "=Q>,Q>,Q>,m,m,m")
810 (match_operand:BWD 1 "nonmemory_operand" "M, r, x, M,r,x"))]
819 [(set_attr "slottable" "yes,yes,yes,no,no,no")
820 (set_attr "enabled" "<mov_tomem_enabled>")])
822 (define_split ;; "*mov_fromzero<mode>_split"
823 [(set (match_operand:BWD 0 "register_operand") (const_int 0))
824 (clobber (reg:CC CRIS_CC0_REGNUM))]
826 && REGNO(operands[0]) <= CRIS_LAST_GENERAL_REGISTER"
827 [(set (match_dup 0) (const_int 0))]
830 (define_insn "*mov_fromzero<mode>"
831 [(set (match_operand:BWD 0 "register_operand" "=r") (const_int 0))]
834 [(set_attr "slottable" "yes")])
836 ;; Movem patterns. Primarily for use in function prologue and epilogue.
837 ;; Unfortunately, movem stores R0 in the highest memory location, thus
838 ;; the opposite of the expectation for the standard names "load_multiple"
839 ;; and "store_multiple".
841 (define_insn "*cris_load_multiple"
842 [(match_parallel 0 "cris_load_multiple_op"
843 [(set (match_operand:SI 1 "register_operand" "=r,r")
844 (match_operand:SI 2 "memory_operand" "Q,m"))])]
847 [(set_attr "cc" "none")
848 (set_attr "slottable" "yes,no")
849 ;; Not true, but setting the length to 0 causes return sequences (ret
850 ;; movem) to have the cost they had when (return) included the movem
851 ;; and reduces the performance penalty taken for needing to emit an
852 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
853 ;; FIXME: temporary change until all insn lengths are correctly
854 ;; described. FIXME: have better target control over bb-reorder.
855 (set_attr "length" "0")])
857 (define_insn "*cris_store_multiple"
858 [(match_parallel 0 "cris_store_multiple_op"
859 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
860 (match_operand:SI 1 "register_operand" "r,r"))])]
863 [(set_attr "cc" "none")
864 (set_attr "slottable" "yes,no")])
867 ;; Sign- and zero-extend insns with standard names.
868 ;; Those for integer source operand are ordered with the widest source
873 (define_insn "extendsidi2"
874 [(set (match_operand:DI 0 "register_operand" "=r")
875 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))
876 (clobber (reg:CC CRIS_CC0_REGNUM))]
878 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
880 (define_insn "extend<mode>di2"
881 [(set (match_operand:DI 0 "register_operand" "=r")
882 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))
883 (clobber (reg:CC CRIS_CC0_REGNUM))]
885 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
887 (define_insn "<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"
888 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
889 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))
890 (clobber (reg:CC CRIS_CC0_REGNUM))]
893 [(set_attr "slottable" "yes,yes,no")])
895 ;; To do a byte->word extension, extend to dword, except that the top half
896 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
898 (define_insn "extendqihi2"
899 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
900 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))
901 (clobber (reg:CC CRIS_CC0_REGNUM))]
904 [(set_attr "slottable" "yes,yes,no")])
907 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
908 ;; specify them here.
910 (define_insn "<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"
911 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
913 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))
914 (clobber (reg:CC CRIS_CC0_REGNUM))]
917 [(set_attr "slottable" "yes,yes,no")])
919 ;; Same comment as sign-extend QImode to HImode above applies.
921 (define_insn "zero_extendqihi2"
922 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
924 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))
925 (clobber (reg:CC CRIS_CC0_REGNUM))]
928 [(set_attr "slottable" "yes,yes,no")])
930 ;; Add operations, standard names.
932 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
933 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
935 (define_expand "adddi3"
937 [(set (match_operand:DI 0 "register_operand")
938 (plus:DI (match_operand:DI 1 "register_operand")
939 (match_operand:DI 2 "general_operand")))
940 (clobber (reg:CC CRIS_CC0_REGNUM))])]
944 (define_insn "*adddi3<setnz>"
945 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
946 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
947 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))
948 (clobber (reg:CC CRIS_CC0_REGNUM))]
951 addq %2,%M0\;ax\;addq 0,%H0
952 subq %n2,%M0\;ax\;subq 0,%H0
953 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
954 add.d %M2,%M0\;ax\;add.d %H2,%H0
955 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
957 (define_expand "add<mode>3"
959 [(set (match_operand:BWD 0 "register_operand")
961 (match_operand:BWD 1 "register_operand")
962 (match_operand:BWD 2 "general_operand")))
963 (clobber (reg:CC CRIS_CC0_REGNUM))])]
967 (define_insn "*addsi3<setnz>"
968 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r, r")
970 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0,r, r")
971 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))
972 (clobber (reg:CC CRIS_CC0_REGNUM))]
974 ;; The last constraint is due to that after reload, the '%' is not
975 ;; honored, and canonicalization doesn't care about keeping the same
976 ;; register as in destination. This will happen after insn splitting.
980 switch (which_alternative)
984 return "add.d %2,%0";
988 return "subq %n2,%0";
990 /* 'Known value', but not in -63..63.
991 Check if addu/subu may be used. */
992 if (INTVAL (operands[2]) > 0)
994 if (INTVAL (operands[2]) < 256)
995 return "addu.b %2,%0";
996 if (INTVAL (operands[2]) < 65536)
997 return "addu.w %2,%0";
1001 if (INTVAL (operands[2]) >= -255)
1002 return "subu.b %n2,%0";
1003 if (INTVAL (operands[2]) >= -65535)
1004 return "subu.w %n2,%0";
1006 return "add.d %2,%0";
1008 return "add.d %2,%0";
1010 return "add.d %2,%1,%0";
1012 return "add.d %1,%0";
1014 return "BOGUS addsi %2+%1 to %0";
1017 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
1019 (define_insn "*addhi3<setnz>"
1020 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1021 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1022 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))
1023 (clobber (reg:CC CRIS_CC0_REGNUM))]
1032 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1033 (set_attr "cc<ccnz>" "normal,normal,clobber,clobber,normal,normal")])
1035 (define_insn "*addqi3<setnz>"
1036 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1037 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1038 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))
1039 (clobber (reg:CC CRIS_CC0_REGNUM))]
1049 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1050 (set_attr "cc<ccnz>" "normal,normal,clobber,clobber,clobber,normal,normal")])
1054 ;; Note that because of insn canonicalization these will *seldom* but
1055 ;; rarely be used with a known constant as an operand.
1057 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1058 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1060 (define_expand "subdi3"
1062 [(set (match_operand:DI 0 "register_operand")
1063 (minus:DI (match_operand:DI 1 "register_operand")
1064 (match_operand:DI 2 "general_operand")))
1065 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1069 (define_insn "*subdi3<setnz>"
1070 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1072 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))
1073 (clobber (reg:CC CRIS_CC0_REGNUM))]
1076 subq %2,%M0\;ax\;subq 0,%H0
1077 addq %n2,%M0\;ax\;addq 0,%H0
1078 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1079 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1080 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1082 (define_expand "sub<mode>3"
1084 [(set (match_operand:BWD 0 "register_operand")
1086 (match_operand:BWD 1 "register_operand")
1087 (match_operand:BWD 2 "general_operand")))
1088 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1092 (define_insn "*subsi3<setnz>"
1093 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1095 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1096 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))
1097 (clobber (reg:CC CRIS_CC0_REGNUM))]
1100 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1101 ;; But then again, %2 should not be negative.
1112 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1114 (define_insn "*sub<mode>3<setnz>"
1115 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
1116 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
1117 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))
1118 (clobber (reg:CC CRIS_CC0_REGNUM))]
1127 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1128 (set_attr "cc<ccnz>" "normal,normal,clobber,clobber,normal,normal")])
1130 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
1133 ;; FIXME: GCC should widen.
1135 (define_insn "*<addsub><su>qihi"
1136 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1138 (match_operand:HI 1 "register_operand" "0,0,0,r")
1139 (szext:HI (match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To"))))
1140 (clobber (reg:CC CRIS_CC0_REGNUM))]
1141 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
1142 && (operands[1] != frame_pointer_rtx || <plusminus:CODE> != PLUS)"
1144 <addsub><su>.b %2,%0
1145 <addsub><su>.b %2,%0
1146 <addsub><su>.b %2,%0
1147 <addsub><su>.b %2,%1,%0"
1148 [(set_attr "slottable" "yes,yes,no,no")
1149 (set_attr "cc" "clobber")])
1151 ;; FIXME: bound is actually also <setnzvc>, but is so rarely used in this
1152 ;; form that it's not worthwhile to make that distinction.
1153 (define_insn "*<addsubbo><su><nd><mode>si<setnz>"
1154 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1156 (match_operand:SI 1 "register_operand" "0,0,0,r")
1157 (szext:SI (match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To"))))
1158 (clobber (reg:CC CRIS_CC0_REGNUM))]
1159 "(<plusminusumin:CODE> != UMIN || <szext:CODE> == ZERO_EXTEND)
1160 && (operands[1] != frame_pointer_rtx || <plusminusumin:CODE> != PLUS)"
1162 <addsubbo><su><nd><m> %2,%0
1163 <addsubbo><su><nd><m> %2,%0
1164 <addsubbo><su><nd><m> %2,%0
1165 <addsubbo><su><nd><m> %2,%1,%0"
1166 [(set_attr "slottable" "yes,yes,no,no")])
1168 ;; We may have swapped operands for add or bound.
1169 ;; For commutative operands, these are the canonical forms.
1173 (define_insn "*add<su>qihi_swap"
1174 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
1176 (szext:HI (match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To"))
1177 (match_operand:HI 1 "register_operand" "0,0,0,r")))
1178 (clobber (reg:CC CRIS_CC0_REGNUM))]
1179 "operands[1] != frame_pointer_rtx"
1185 [(set_attr "slottable" "yes,yes,no,no")
1186 (set_attr "cc" "clobber")])
1188 (define_insn "*<addsubbo><su><nd><mode>si<setnz>_swap"
1189 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1191 (szext:SI (match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To"))
1192 (match_operand:SI 1 "register_operand" "0,0,0,r")))
1193 (clobber (reg:CC CRIS_CC0_REGNUM))]
1194 "(<plusumin:CODE> != UMIN || <szext:CODE> == ZERO_EXTEND)
1195 && operands[1] != frame_pointer_rtx"
1197 <addsubbo><su><nd><m> %2,%0
1198 <addsubbo><su><nd><m> %2,%0
1199 <addsubbo><su><nd><m> %2,%0
1200 <addsubbo><su><nd><m> %2,%1,%0"
1201 [(set_attr "slottable" "yes,yes,no,no")])
1203 ;; This is the special case when we use what corresponds to the
1204 ;; instruction above in "casesi". Do *not* change it to use the generic
1205 ;; pattern and "REG 15" as pc; I did that and it led to madness and
1206 ;; maintenance problems: Instead of (as imagined) recognizing and removing
1207 ;; or replacing this pattern with something simpler, other variant
1208 ;; patterns were recognized or combined, including some prefix variants
1209 ;; where the value in pc is not that of the next instruction (which means
1210 ;; this instruction actually *is* special and *should* be marked as such).
1211 ;; When switching from the "generic pattern match" approach to this simpler
1212 ;; approach, there were insignificant differences in gcc, ipps and
1213 ;; product code, somehow due to scratching reload behind the ear or
1214 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
1215 ;; product code became .001% smaller but "looked better". The testcase
1216 ;; "ipps" was just different at register allocation).
1218 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
1219 ;; pattern with the default-label as the else, with the "if" being
1220 ;; index-is-less-than the max number of cases plus one. The default-label
1221 ;; is attached to the end of the case-table at time of output.
1223 (define_insn "*casesi_adds_w"
1226 (ltu (match_operand:SI 0 "register_operand" "r")
1227 (match_operand:SI 1 "const_int_operand" "n"))
1228 (plus:SI (sign_extend:SI
1230 (plus:SI (mult:SI (match_dup 0) (const_int 2))
1233 (label_ref (match_operand 2 "" ""))))
1234 (use (label_ref (match_operand 3 "" "")))
1235 (clobber (reg:CC CRIS_CC0_REGNUM))]
1236 "operands[0] != frame_pointer_rtx"
1237 "adds.w [$pc+%0.w],$pc"
1238 [(set_attr "cc" "clobber")])
1240 ;; Multiply instructions.
1242 ;; Sometimes powers of 2 (which are normally canonicalized to a
1243 ;; left-shift) appear here, as a result of address reloading.
1244 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
1246 ;; FIXME: This may be unnecessary now.
1247 ;; Explicitly named for convenience of having a gen_... function.
1249 (define_insn "addi_mul"
1250 [(set (match_operand:SI 0 "register_operand" "=r")
1252 (match_operand:SI 1 "register_operand" "%0")
1253 (match_operand:SI 2 "const_int_operand" "n")))
1254 (clobber (reg:CC CRIS_CC0_REGNUM))]
1255 "operands[0] != frame_pointer_rtx
1256 && operands[1] != frame_pointer_rtx
1257 && CONST_INT_P (operands[2])
1258 && (INTVAL (operands[2]) == 2
1259 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
1260 || INTVAL (operands[2]) == 5)"
1262 if (INTVAL (operands[2]) == 2)
1264 else if (INTVAL (operands[2]) == 4)
1266 else if (INTVAL (operands[2]) == 3)
1267 return "addi %0.w,%0";
1268 else if (INTVAL (operands[2]) == 5)
1269 return "addi %0.d,%0";
1270 return "BAD: adr_mulsi: %0=%1*%2";
1272 [(set_attr "slottable" "yes")
1273 ;; No flags are changed if this insn is "addi", but it does not seem
1274 ;; worth the trouble to distinguish that to the lslq cases.
1275 (set_attr "cc" "clobber")])
1277 ;; The addi insn as it is normally used.
1279 (define_insn "*addi"
1280 [(set (match_operand:SI 0 "register_operand" "=r")
1282 (ashift:SI (match_operand:SI 2 "register_operand" "r")
1283 (match_operand:SI 3 "const_int_operand" "n"))
1284 (match_operand:SI 1 "register_operand" "0")))]
1285 "operands[0] != frame_pointer_rtx
1286 && operands[1] != frame_pointer_rtx
1287 && CONST_INT_P (operands[3])
1288 && (INTVAL (operands[3]) == 1 || INTVAL (operands[3]) == 2)"
1290 [(set_attr "slottable" "yes")
1291 (set_attr "cc" "none")])
1293 ;; The mult-vs-ashift canonicalization-cleanup plagues us: nothing in
1294 ;; reload transforms a "scaled multiplication" into an ashift in a
1295 ;; reloaded address; it's passed as-is and expected to be recognized,
1296 ;; or else we get a tell-tale "unrecognizable insn".
1297 ;; On top of that, we *should* match the bare insn, as a *matching
1298 ;; pattern* (as opposed to e.g. a reload_load_address expander
1299 ;; changing the mul into an ashift), so can_reload_into will re-use
1300 ;; registers in the reloaded expression instead of allocating a new
1302 (define_insn_and_split "*addi_reload"
1303 [(set (match_operand:SI 0 "register_operand" "=r")
1305 (mult:SI (match_operand:SI 2 "register_operand" "r")
1306 (match_operand:SI 3 "const_int_operand" "n"))
1307 (match_operand:SI 1 "register_operand" "0")))]
1308 "operands[0] != frame_pointer_rtx
1309 && operands[1] != frame_pointer_rtx
1310 && CONST_INT_P (operands[3])
1311 && (INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)
1312 && (reload_in_progress || reload_completed)"
1316 (plus:SI (ashift:SI (match_dup 2) (match_dup 3)) (match_dup 1)))]
1317 "operands[3] = operands[3] == const2_rtx ? const1_rtx : const2_rtx;")
1319 ;; This pattern is usually generated after reload, so a '%' is
1320 ;; ineffective; use explicit combinations.
1321 (define_insn "*addi_b_<mode>"
1322 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1324 (match_operand:BWD 1 "register_operand" "0,r")
1325 (match_operand:BWD 2 "register_operand" "r,0")))]
1330 [(set_attr "slottable" "yes")])
1332 ;; Strip the dccr clobber from addM3 with register operands, if the
1333 ;; next instruction isn't using it.
1334 ;; Not clobbering dccr may let cmpelim match a later compare with a
1335 ;; previous operation of interest. This has to run before cmpelim so it
1336 ;; can't be a peephole2. See gcc.target/cris/pr93372-45.c for a
1338 (define_split ;; "*add<mode>3_addi"
1340 [(set (match_operand:BWD 0 "register_operand")
1342 (match_operand:BWD 1 "register_operand")
1343 (match_operand:BWD 2 "register_operand")))
1344 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1346 [(set (match_dup 0) (plus:BWD (match_dup 1) (match_dup 2)))]
1348 rtx reg = operands[0];
1349 rtx_insn *i = next_nonnote_nondebug_insn_bb (curr_insn);
1351 while (i != NULL_RTX && (!INSN_P (i) || DEBUG_INSN_P (i)))
1352 i = next_nonnote_nondebug_insn_bb (i);
1354 if (i == NULL_RTX || reg_mentioned_p (reg, i) || BARRIER_P (i))
1358 (define_insn "<u>mul<s><mode>3"
1359 [(set (match_operand:WD 0 "register_operand" "=r")
1361 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
1362 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
1363 (clobber (match_scratch:SI 3 "=h"))
1364 (clobber (reg:CC CRIS_CC0_REGNUM))]
1365 "TARGET_HAS_MUL_INSNS"
1366 "%!mul<su><mm> %2,%0"
1367 [(set (attr "slottable")
1368 (if_then_else (match_test "TARGET_MUL_BUG")
1370 (const_string "yes")))
1371 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
1372 ;; For muls.b, this really extends to SImode, so cc should be
1373 ;; considered clobbered.
1374 ;; For muls.w, it's just N unusable here, but let's be safe.
1375 (set_attr "cc" "clobber")])
1377 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
1378 ;; confused and will erroneously use it instead of umulhisi3, failing (at
1379 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
1380 ;; Inspection of optab code shows that there must be only one widening
1381 ;; multiplication per mode widened to.
1383 (define_insn "mulsi3"
1384 [(set (match_operand:SI 0 "register_operand" "=r")
1385 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1386 (match_operand:SI 2 "register_operand" "r")))
1387 (clobber (match_scratch:SI 3 "=h"))
1388 (clobber (reg:CC CRIS_CC0_REGNUM))]
1389 "TARGET_HAS_MUL_INSNS"
1391 [(set (attr "slottable")
1392 (if_then_else (match_test "TARGET_MUL_BUG")
1394 (const_string "yes")))
1395 ;; Just N unusable here, but let's be safe.
1396 (set_attr "cc" "clobber")])
1398 ;; A few multiply variations.
1400 ;; When needed, we can get the high 32 bits from the overflow
1401 ;; register. We don't care to split and optimize these.
1403 (define_insn "<u>mulsidi3"
1404 [(set (match_operand:DI 0 "register_operand" "=r")
1406 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
1407 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
1408 (clobber (match_scratch:SI 3 "=h"))
1409 (clobber (reg:CC CRIS_CC0_REGNUM))]
1410 "TARGET_HAS_MUL_INSNS"
1411 "%!mul<su>.d %2,%M0\;move $mof,%H0")
1413 ;; These two patterns may be expressible by other means, perhaps by making
1414 ;; [u]?mulsidi3 a define_expand.
1416 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
1417 ;; cause a move into the clobbered register *before* the insn, then
1418 ;; after the insn, mof is moved too, rather than the clobber assigned
1419 ;; the last mof target. This became apparent when making MOF and SRP
1420 ;; visible registers, with the necessary tweak to smulsi3_highpart.
1421 ;; Because these patterns are used in division by constants, that damage
1422 ;; is visible (ipps regression tests). Therefore the last two
1423 ;; alternatives, "helping" reload to avoid an unnecessary move, but
1424 ;; punished by force of one "?". Check code from "int d (int a) {return
1425 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
1427 (define_insn "<su>mulsi3_highpart"
1428 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
1432 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
1433 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
1435 (clobber (match_scratch:SI 3 "=1,2,h,h"))
1436 (clobber (reg:CC CRIS_CC0_REGNUM))]
1437 "TARGET_HAS_MUL_INSNS"
1441 %!mul<su>.d %2,%1\;move $mof,%0
1442 %!mul<su>.d %1,%2\;move $mof,%0"
1443 [(set_attr "slottable" "yes,yes,no,no")
1444 (set_attr "cc" "clobber")])
1446 ;; Divide and modulus instructions. CRIS only has a step instruction.
1448 (define_insn "dstep_shift"
1449 [(set (match_operand:SI 0 "register_operand" "=r")
1451 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1453 (match_operand:SI 2 "register_operand" "r"))
1454 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
1456 (match_operand:SI 4 "register_operand" "2"))
1457 (ashift:SI (match_operand:SI 5 "register_operand" "0")
1459 (clobber (reg:CC CRIS_CC0_REGNUM))]
1462 [(set_attr "slottable" "yes")])
1464 ;; Here's a variant with mult instead of ashift.
1466 ;; FIXME: This should be investigated. Which one matches through combination?
1468 (define_insn "dstep_mul"
1469 [(set (match_operand:SI 0 "register_operand" "=r")
1471 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1473 (match_operand:SI 2 "register_operand" "r"))
1474 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
1476 (match_operand:SI 4 "register_operand" "2"))
1477 (mult:SI (match_operand:SI 5 "register_operand" "0")
1479 (clobber (reg:CC CRIS_CC0_REGNUM))]
1480 "operands[0] != frame_pointer_rtx
1481 && operands[1] != frame_pointer_rtx
1482 && operands[2] != frame_pointer_rtx
1483 && operands[3] != frame_pointer_rtx"
1485 [(set_attr "slottable" "yes")])
1487 ;; Logical operators.
1491 ;; There is no use in defining "anddi3", because gcc can expand this by
1492 ;; itself, and make reasonable code without interference.
1494 ;; If the first operand is memory or a register and is the same as the
1495 ;; second operand, and the third operand is -256 or -65536, we can use
1496 ;; CLEAR instead. Or, if the first operand is a register, and the third
1497 ;; operand is 255 or 65535, we can zero_extend.
1498 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
1499 ;; to be common enough to be worthwhile.
1500 ;; FIXME: This should be made obsolete.
1502 (define_expand "andsi3"
1504 [(set (match_operand:SI 0 "nonimmediate_operand")
1505 (and:SI (match_operand:SI 1 "nonimmediate_operand")
1506 (match_operand:SI 2 "general_operand")))
1507 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1510 if (! (CONST_INT_P (operands[2])
1511 && (((INTVAL (operands[2]) == -256
1512 || INTVAL (operands[2]) == -65536)
1513 && rtx_equal_p (operands[1], operands[0]))
1514 || ((INTVAL (operands[2]) == 255
1515 || INTVAL (operands[2]) == 65535)
1516 && REG_P (operands[0])))))
1518 /* Make intermediate steps if operand0 is not a register or
1519 operand1 is not a register, and hope that the reload pass will
1520 make something useful out of it. Note that the operands are
1521 *not* canonicalized. For the moment, I chicken out on this,
1522 because all or most ports do not describe 'and' with
1523 canonicalized operands, and I seem to remember magic in reload,
1524 checking that operand1 has constraint '%0', in which case
1525 operand0 and operand1 must have similar predicates.
1526 FIXME: Investigate. */
1527 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
1528 rtx reg1 = operands[1];
1532 emit_move_insn (reg0, reg1);
1536 cris_emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (SImode, reg1,
1539 /* Make sure we get the right *final* destination. */
1540 if (! REG_P (operands[0]))
1541 emit_move_insn (operands[0], reg0);
1547 ;; Some special cases of andsi3.
1549 (define_insn "*andsi_movu"
1550 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1551 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
1552 (match_operand:SI 2 "const_int_operand" "n,n,n")))
1553 (clobber (reg:CC CRIS_CC0_REGNUM))]
1554 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
1555 && !side_effects_p (operands[1])"
1557 [(set_attr "slottable" "yes,yes,no")])
1559 ;; FIXME: Remember, this does *not* actually affect condition codes;
1560 ;; get rid of the clobber.
1561 (define_insn "*andsi_clear"
1562 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
1563 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
1564 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))
1565 (clobber (reg:CC CRIS_CC0_REGNUM))]
1566 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
1567 && !side_effects_p (operands[0])"
1575 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1576 (set_attr "cc" "none")])
1578 ;; This is a catch-all pattern, taking care of everything that was not
1579 ;; matched in the insns above.
1581 ;; Sidenote: the tightening from "nonimmediate_operand" to
1582 ;; "register_operand" for operand 1 actually increased the register
1583 ;; pressure (worse code). That will hopefully change with an
1584 ;; improved reload pass.
1586 (define_insn "*expanded_andsi<setcc><setnz><setnzvc>"
1587 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
1588 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
1589 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))
1590 (clobber (reg:CC CRIS_CC0_REGNUM))]
1598 [(set_attr "slottable" "yes,yes,yes,no,no")])
1600 ;; For both QI and HI we may use the quick patterns. This results in
1601 ;; useless condition codes, but that is used rarely enough for it to
1602 ;; normally be a win (could check ahead for use of CRIS_CC0_REGNUM, but
1603 ;; seems to be more pain than win).
1605 ;; FIXME: See note for andsi3
1607 (define_expand "andhi3"
1609 [(set (match_operand:HI 0 "nonimmediate_operand")
1610 (and:HI (match_operand:HI 1 "nonimmediate_operand")
1611 (match_operand:HI 2 "general_operand")))
1612 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1615 if (! (CONST_INT_P (operands[2])
1616 && (((INTVAL (operands[2]) == -256
1617 || INTVAL (operands[2]) == 65280)
1618 && rtx_equal_p (operands[1], operands[0]))
1619 || (INTVAL (operands[2]) == 255
1620 && REG_P (operands[0])))))
1622 /* See comment for andsi3. */
1623 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
1624 rtx reg1 = operands[1];
1628 emit_move_insn (reg0, reg1);
1632 cris_emit_insn (gen_rtx_SET (reg0, gen_rtx_AND (HImode, reg1,
1635 /* Make sure we get the right destination. */
1636 if (! REG_P (operands[0]))
1637 emit_move_insn (operands[0], reg0);
1643 ;; Some fast andhi3 special cases.
1645 (define_insn "*andhi_movu"
1646 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1647 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
1649 (clobber (reg:CC CRIS_CC0_REGNUM))]
1650 "!side_effects_p (operands[1])"
1652 [(set_attr "slottable" "yes,yes,no")])
1654 (define_insn "*andhi_clear"
1655 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
1656 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
1658 (clobber (reg:CC CRIS_CC0_REGNUM))]
1659 "!side_effects_p (operands[0])"
1661 [(set_attr "slottable" "yes,yes,no")
1662 (set_attr "cc" "none")])
1664 ;; Catch-all andhi3 pattern.
1666 (define_insn "*expanded_andhi<setcc><setnz><setnzvc>"
1667 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r, r,r,r,r")
1668 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0, 0,0,0,r")
1669 (match_operand:HI 2 "general_operand" "I,Kc,r,Q>,L,O,g,!To")))
1670 ;; The "Kc" alternative above, is there to match for cmpelim;
1671 ;; it will be dominated by the "I" alternative at other times.
1672 (clobber (reg:CC CRIS_CC0_REGNUM))]
1674 ;; Sidenote: the tightening from "general_operand" to
1675 ;; "register_operand" for operand 1 actually increased the register
1676 ;; pressure (worse code). That will hopefully change with an
1677 ;; improved reload pass.
1689 [(set_attr "slottable" "yes,yes,yes,yes,no,yes,no,no")
1690 (set_attr "cc<cccc><ccnz><ccnzvc>"
1691 "clobber,normal,normal,normal,normal,clobber,normal,normal")])
1693 ;; A strict_low_part pattern.
1695 ;; Note the use of (match_dup 0) for the first operand of the operation
1696 ;; here. Reload can't handle an operand pair where one is read-write
1697 ;; and must match a read, like in:
1699 ;; (set (strict_low_part
1700 ;; (subreg:QI (reg/v:SI 0 r0 [orig:36 data ] [36]) 0))
1702 ;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0)
1703 ;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32}
1705 ;; (Note: the example is obsolete.)
1706 ;; In theory, it could reload this as a movstrictqi of the register
1707 ;; operand at the and:QI to the destination register and change the
1708 ;; and:QI operand to the same as the read-write output operand and the
1709 ;; result would be recognized, but it doesn't recognize that's a valid
1710 ;; reload for a strict_low_part-destination; it just sees a "+" at the
1711 ;; destination constraints. Better than adding complexity to reload is
1712 ;; to follow the lead of m68k (see comment that begins with "These insns
1713 ;; must use MATCH_DUP") since prehistoric times and make it just a
1714 ;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with
1715 ;; input-constraints matching input-output-constraints, e.g. "+r" <- "0".
1717 (define_insn "*andhi_lowpart"
1718 [(set (strict_low_part
1719 (match_operand:HI 0 "register_operand" "+r,r,r"))
1720 (and:HI (match_dup 0)
1721 (match_operand:HI 1 "general_operand" "r,Q>,g")))
1722 (clobber (reg:CC CRIS_CC0_REGNUM))]
1728 [(set_attr "slottable" "yes,yes,no")])
1730 (define_expand "andqi3"
1732 [(set (match_operand:QI 0 "register_operand")
1733 (and:QI (match_operand:QI 1 "register_operand")
1734 (match_operand:QI 2 "general_operand")))
1735 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1739 (define_insn "*andqi3<setcc><setnz><setnzvc>"
1740 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r, r,r,r")
1741 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0, 0,0,r")
1742 (match_operand:QI 2 "general_operand" "I,Kc,r,Q>,O,g,!To")))
1743 (clobber (reg:CC CRIS_CC0_REGNUM))]
1753 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1754 (set_attr "cc<cccc><ccnz><ccnzvc>"
1755 "clobber,normal,normal,normal,clobber,normal,normal")])
1757 (define_insn "*andqi_lowpart"
1758 [(set (strict_low_part
1759 (match_operand:QI 0 "register_operand" "+r,r,r"))
1760 (and:QI (match_dup 0)
1761 (match_operand:QI 1 "general_operand" "r,Q>,g")))
1762 (clobber (reg:CC CRIS_CC0_REGNUM))]
1768 [(set_attr "slottable" "yes,yes,no")])
1772 ;; Same comment as anddi3 applies here - no need for such a pattern.
1774 ;; It seems there's no need to jump through hoops to get good code such as
1777 (define_expand "ior<mode>3"
1779 [(set (match_operand:BWD 0 "register_operand")
1780 (ior:BWD (match_operand:BWD 1 "register_operand")
1781 (match_operand:BWD 2 "general_operand")))
1782 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1786 (define_insn "*iorsi3<setcc><setnz><setnzvc>"
1787 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
1788 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
1789 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))
1790 (clobber (reg:CC CRIS_CC0_REGNUM))]
1799 [(set_attr "slottable" "yes,yes,yes,no,no,no")
1800 (set_attr "cc<cccc><ccnz><ccnzvc>"
1801 "normal,normal,normal,clobber,normal,normal")])
1803 (define_insn "*iorhi3<setcc><setnz><setnzvc>"
1804 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
1805 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
1806 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))
1807 (clobber (reg:CC CRIS_CC0_REGNUM))]
1817 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
1818 (set_attr "cc<cccc><ccnz><ccnzvc>"
1819 "clobber,normal,normal,normal,clobber,normal,normal")])
1821 (define_insn "*iorqi3<setcc><setnz><setnzvc>"
1822 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
1823 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
1824 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))
1825 (clobber (reg:CC CRIS_CC0_REGNUM))]
1834 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1835 (set_attr "cc<cccc><ccnz><ccnzvc>"
1836 "clobber,normal,normal,clobber,normal,normal")])
1840 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
1841 ;; FIXME: Do we really need the shorter variants?
1843 (define_insn "<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"
1844 [(set (match_operand:SI 0 "register_operand" "=r")
1845 (xor:SI (match_operand:SI 1 "register_operand" "%0")
1846 (match_operand:SI 2 "register_operand" "r")))
1847 (clobber (reg:CC CRIS_CC0_REGNUM))]
1850 [(set_attr "slottable" "yes")])
1852 (define_insn "xor<mode>3"
1853 [(set (match_operand:BW 0 "register_operand" "=r")
1854 (xor:BW (match_operand:BW 1 "register_operand" "%0")
1855 (match_operand:BW 2 "register_operand" "r")))
1856 (clobber (reg:CC CRIS_CC0_REGNUM))]
1859 [(set_attr "slottable" "yes")
1860 (set_attr "cc" "clobber")])
1864 ;; Questionable use, here mostly as a (slightly usable) define_expand
1867 (define_expand "negsf2"
1869 [(set (match_dup 2) (match_dup 3))
1870 (clobber (reg:CC CRIS_CC0_REGNUM))])
1871 (parallel [(set (match_operand:SF 0 "register_operand")
1872 (neg:SF (match_operand:SF 1 "register_operand")))
1874 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1877 operands[2] = gen_reg_rtx (SImode);
1878 operands[3] = GEN_INT (1 << 31);
1881 (define_insn "*expanded_negsf2"
1882 [(set (match_operand:SF 0 "register_operand" "=r")
1883 (neg:SF (match_operand:SF 1 "register_operand" "0")))
1884 (use (match_operand:SI 2 "register_operand" "r"))
1885 (clobber (reg:CC CRIS_CC0_REGNUM))]
1888 [(set_attr "slottable" "yes")])
1890 ;; No "negdi2" although we could make one up that may be faster than
1891 ;; the one in libgcc.
1893 (define_insn "<anz>neg<mode>2<setnz>"
1894 [(set (match_operand:BWD 0 "register_operand" "=r")
1895 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))
1896 (clobber (reg:CC CRIS_CC0_REGNUM))]
1899 [(set_attr "slottable" "yes")])
1903 ;; See comment on anddi3 - no need for a DImode pattern.
1904 ;; See also xor comment.
1906 (define_insn "<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"
1907 [(set (match_operand:SI 0 "register_operand" "=r")
1908 (not:SI (match_operand:SI 1 "register_operand" "0")))
1909 (clobber (reg:CC CRIS_CC0_REGNUM))]
1912 [(set_attr "slottable" "yes")])
1914 (define_insn "one_cmpl<mode>2"
1915 [(set (match_operand:BW 0 "register_operand" "=r")
1916 (not:BW (match_operand:BW 1 "register_operand" "0")))
1917 (clobber (reg:CC CRIS_CC0_REGNUM))]
1920 [(set_attr "slottable" "yes")
1921 (set_attr "cc" "clobber")])
1923 ;; Arithmetic/Logical shift right (and SI left).
1925 (define_insn "<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"
1926 [(set (match_operand:SI 0 "register_operand" "=r")
1927 (shift:SI (match_operand:SI 1 "register_operand" "0")
1928 (match_operand:SI 2 "nonmemory_operand" "Kcr")))
1929 (clobber (reg:CC CRIS_CC0_REGNUM))]
1932 if (REG_S_P (operands[2]))
1933 return "<slr>.d %2,%0";
1935 return "<slr>q %2,%0";
1937 [(set_attr "slottable" "yes")])
1939 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
1940 ;; the destination) when it changes shifts of lower modes into SImode,
1941 ;; it is better to make these expands an anonymous patterns instead of
1942 ;; the more correct define_insns. This occurs when gcc thinks that is
1943 ;; is better to widen to SImode and use immediate shift count.
1945 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
1947 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
1948 ;; mentioning "shiftrt"), so we need two patterns.
1949 (define_expand "ashr<mode>3"
1952 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand")))
1953 (clobber (reg:CC CRIS_CC0_REGNUM))])
1956 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand")))
1957 (clobber (reg:CC CRIS_CC0_REGNUM))])
1959 [(set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
1960 (clobber (reg:CC CRIS_CC0_REGNUM))])
1962 [(set (match_operand:BW 0 "general_operand")
1963 (subreg:BW (match_dup 5) 0))
1964 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1969 for (i = 3; i < 6; i++)
1970 operands[i] = gen_reg_rtx (SImode);
1973 (define_expand "lshr<mode>3"
1976 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand")))
1977 (clobber (reg:CC CRIS_CC0_REGNUM))])
1980 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand")))
1981 (clobber (reg:CC CRIS_CC0_REGNUM))])
1983 [(set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
1984 (clobber (reg:CC CRIS_CC0_REGNUM))])
1986 [(set (match_operand:BW 0 "general_operand")
1987 (subreg:BW (match_dup 5) 0))
1988 (clobber (reg:CC CRIS_CC0_REGNUM))])]
1993 for (i = 3; i < 6; i++)
1994 operands[i] = gen_reg_rtx (SImode);
1997 (define_insn "*expanded_<shlr><mode>"
1998 [(set (match_operand:BW 0 "register_operand" "=r")
1999 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
2000 (match_operand:BW 2 "register_operand" "r")))
2001 (clobber (reg:CC CRIS_CC0_REGNUM))]
2004 [(set_attr "slottable" "yes")])
2006 (define_insn "*<shlr><mode>_lowpart"
2007 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2008 (shiftrt:BW (match_dup 0)
2009 (match_operand:BW 1 "register_operand" "r")))
2010 (clobber (reg:CC CRIS_CC0_REGNUM))]
2013 [(set_attr "slottable" "yes")])
2015 ;; Arithmetic/logical shift left.
2017 ;; For narrower modes than SI, we can use lslq although it makes cc
2018 ;; unusable. The win is that we do not have to reload the shift-count
2021 (define_insn "ashl<mode>3"
2022 [(set (match_operand:BW 0 "register_operand" "=r,r")
2023 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
2024 (match_operand:BW 2 "nonmemory_operand" "r,Kc")))
2025 (clobber (reg:CC CRIS_CC0_REGNUM))]
2029 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
2031 : (CONSTANT_P (operands[2])
2032 ? "lslq %2,%0" : "lsl<m> %2,%0");
2034 [(set_attr "slottable" "yes")
2035 (set_attr "cc" "*,clobber")])
2037 ;; A strict_low_part matcher.
2039 (define_insn "*ashl<mode>_lowpart"
2040 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
2041 (ashift:BW (match_dup 0)
2042 (match_operand:HI 1 "register_operand" "r")))
2043 (clobber (reg:CC CRIS_CC0_REGNUM))]
2046 [(set_attr "slottable" "yes")])
2048 ;; Various strange insns that gcc likes.
2050 ;; Fortunately, it is simple to construct an abssf (although it may not
2051 ;; be very much used in practice).
2053 (define_insn "abssf2"
2054 [(set (match_operand:SF 0 "register_operand" "=r")
2055 (abs:SF (match_operand:SF 1 "register_operand" "0")))
2056 (clobber (reg:CC CRIS_CC0_REGNUM))]
2058 "lslq 1,%0\;lsrq 1,%0")
2060 (define_insn "abssi2"
2061 [(set (match_operand:SI 0 "register_operand" "=r")
2062 (abs:SI (match_operand:SI 1 "register_operand" "r")))
2063 (clobber (reg:CC CRIS_CC0_REGNUM))]
2066 [(set_attr "slottable" "yes")])
2068 ;; FIXME: GCC should be able to do these expansions itself.
2070 (define_expand "abs<mode>2"
2073 (sign_extend:SI (match_operand:BW 1 "general_operand")))
2074 (clobber (reg:CC CRIS_CC0_REGNUM))])
2076 [(set (match_dup 3) (abs:SI (match_dup 2)))
2077 (clobber (reg:CC CRIS_CC0_REGNUM))])
2079 [(set (match_operand:BW 0 "register_operand")
2080 (subreg:BW (match_dup 3) 0))
2081 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2083 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
2085 (define_insn "<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"
2086 [(set (match_operand:SI 0 "register_operand" "=r")
2087 (clz:SI (match_operand:SI 1 "register_operand" "r")))
2088 (clobber (reg:CC CRIS_CC0_REGNUM))]
2091 [(set_attr "slottable" "yes")])
2093 (define_insn "<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"
2094 [(set (match_operand:SI 0 "register_operand" "=r")
2095 (bswap:SI (match_operand:SI 1 "register_operand" "0")))
2096 (clobber (reg:CC CRIS_CC0_REGNUM))]
2099 [(set_attr "slottable" "yes")])
2101 ;; This instruction swaps all bits in a register.
2102 ;; That means that the most significant bit is put in the place
2103 ;; of the least significant bit, and so on.
2105 (define_insn "cris_swap_bits"
2106 [(set (match_operand:SI 0 "register_operand" "=r")
2107 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
2108 CRIS_UNSPEC_SWAP_BITS))
2109 (clobber (reg:CC CRIS_CC0_REGNUM))]
2112 [(set_attr "slottable" "yes")])
2114 ;; Implement ctz using two instructions, one for bit swap and one for clz.
2115 ;; Defines a scratch register to avoid clobbering input.
2117 (define_expand "ctzsi2"
2120 (match_operand:SI 1 "register_operand"))
2121 (clobber (reg:CC CRIS_CC0_REGNUM))])
2124 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
2125 (clobber (reg:CC CRIS_CC0_REGNUM))])
2127 [(set (match_operand:SI 0 "register_operand")
2128 (clz:SI (match_dup 2)))
2129 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2130 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
2131 "operands[2] = gen_reg_rtx (SImode);")
2133 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
2134 ;; operation supported by gcc. Used in casesi, but used now and then in
2137 (define_expand "uminsi3"
2139 [(set (match_operand:SI 0 "register_operand")
2140 (umin:SI (match_operand:SI 1 "register_operand")
2141 (match_operand:SI 2 "general_operand")))
2142 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2146 (define_insn "*uminsi3<setcc><setnz><setnzvc>"
2147 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
2148 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
2149 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))
2150 (clobber (reg:CC CRIS_CC0_REGNUM))]
2153 if (CONST_INT_P (operands[2]))
2155 /* Constant operands are zero-extended, so only 32-bit operands
2157 if (INTVAL (operands[2]) >= 0)
2159 if (INTVAL (operands[2]) < 256)
2160 return "bound.b %2,%0";
2162 if (INTVAL (operands[2]) < 65536)
2163 return "bound.w %2,%0";
2166 else if (which_alternative == 3)
2167 return "bound.d %2,%1,%0";
2169 return "bound.d %2,%0";
2171 [(set_attr "slottable" "yes,yes,no,no")])
2173 ;; Jump and branch insns.
2177 (label_ref (match_operand 0 "" "")))]
2180 [(set_attr "slottable" "has_slot")])
2182 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
2183 ;; here, since the insn is not recognized as an indirect jump by
2184 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
2185 ;; change from general_operand to nonimmediate_operand (at least the docs
2186 ;; should be changed), but then again the pattern is called indirect_jump.
2187 (define_expand "indirect_jump"
2188 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
2192 (define_insn "*indirect_jump"
2193 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
2197 ;; Return insn. Used whenever the epilogue is very simple; if it is only
2198 ;; a single ret or jump [sp+]. No allocated stack space or saved
2199 ;; registers are allowed.
2200 ;; Note that for this pattern, although named, it is ok to check the
2201 ;; context of the insn in the test, not only compiler switches.
2203 (define_expand "return"
2205 "cris_simple_epilogue ()"
2206 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
2208 (define_insn "*return_expanded"
2212 return cris_return_address_on_stack_for_return ()
2213 ? "jump [$sp+]" : "ret%#";
2215 [(set (attr "slottable")
2217 (match_test "cris_return_address_on_stack_for_return ()")
2219 (const_string "has_return_slot")))])
2221 (define_expand "prologue"
2224 "cris_expand_prologue (); DONE;")
2226 (define_expand "epilogue"
2229 "cris_expand_epilogue (); DONE;")
2231 ;; Conditional branches.
2233 (define_expand "cbranch<mode>4"
2237 (match_operator 0 "ordered_comparison_operator"
2238 [(match_operand:BWDD 1 "nonimmediate_operand")
2239 (match_operand:BWDD 2 "general_operand")])
2240 (label_ref (match_operand 3 ""))
2242 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2244 "cris_reduce_compare (&operands[0], &operands[1], &operands[2]);")
2246 (define_insn_and_split "*cbranch<mode><code>4"
2250 (match_operand:BWDD 0 "nonimmediate_operand" "<cmp_op0c>")
2251 (match_operand:BWDD 1 "general_operand" "<cmp_op1c>"))
2252 (label_ref (match_operand 2 ""))
2254 (clobber (reg:CC CRIS_CC0_REGNUM))]
2257 "&& reload_completed"
2258 [(set (reg:<xCC> CRIS_CC0_REGNUM)
2259 (compare:<xCC> (match_dup 0) (match_dup 1)))
2261 (if_then_else (cond (reg:<xCC> CRIS_CC0_REGNUM) (const_int 0))
2262 (label_ref (match_dup 2))
2266 ;; Test a single bit at operand[0] against 0/non-0.
2267 (define_insn_and_split "*cbranch<mode>4_btstrq1_<CC>"
2272 (match_operand:BWD 0 "register_operand" "r,r")
2274 (match_operand:SI 1 "nonmemory_operand" "Kc,r"))
2276 (label_ref (match_operand 2 ""))
2278 (clobber (reg:CC CRIS_CC0_REGNUM))]
2281 "&& reload_completed"
2282 [(set (reg:CC_ZnN CRIS_CC0_REGNUM)
2284 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
2287 (if_then_else (zcond (reg:CC_ZnN CRIS_CC0_REGNUM) (const_int 0))
2288 (label_ref (match_dup 2))
2292 ;; Test a field of bits starting at bit 0 against 0/non-0.
2293 (define_insn_and_split "*cbranch<mode>4_btstqb0_<CC>"
2298 (match_operand:BWD 0 "register_operand" "r")
2299 (match_operand 1 "const_int_operand" "Kc")
2302 (label_ref (match_operand 2 ""))
2304 (clobber (reg:CC CRIS_CC0_REGNUM))]
2307 "&& reload_completed"
2308 [(set (reg:CC_NZ CRIS_CC0_REGNUM)
2310 (zero_extract:SI (match_dup 0) (match_dup 1) (const_int 0))
2313 (if_then_else (zcond (reg:CC_NZ CRIS_CC0_REGNUM) (const_int 0))
2314 (label_ref (match_dup 2))
2319 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
2320 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
2323 (define_insn "*b<zcond:code><mode>"
2325 (if_then_else (zcond (reg:ZnNNZUSE CRIS_CC0_REGNUM)
2327 (label_ref (match_operand 0 "" ""))
2331 return <MODE>mode == CC_ZnNmode ? "b<znnCC> %l0%#" : "b<CC> %l0%#";
2333 [(set_attr "slottable" "has_slot")])
2335 (define_insn "*b<nzvccond:code><mode>"
2337 (if_then_else (nzvccond (reg:NZVCUSE CRIS_CC0_REGNUM)
2339 (label_ref (match_operand 0 "" ""))
2343 [(set_attr "slottable" "has_slot")])
2345 (define_insn "*b<rnzcond:code><mode>"
2347 (if_then_else (rnzcond (reg:NZUSE CRIS_CC0_REGNUM)
2349 (label_ref (match_operand 0 "" ""))
2353 return <MODE>mode == CC_NZmode ? "b<oCC> %l0%#": "b<CC> %l0%#";
2355 [(set_attr "slottable" "has_slot")])
2357 ;; Reversed anonymous patterns to the ones above, as mandated.
2359 (define_insn "*b<nzcond:code>_reversed<mode>"
2361 (if_then_else (nzcond (reg:ZnNNZUSE CRIS_CC0_REGNUM)
2364 (label_ref (match_operand 0 "" ""))))]
2367 return <MODE>mode == CC_ZnNmode ? "b<rznnCC> %l0%#" : "b<rCC> %l0%#";
2369 [(set_attr "slottable" "has_slot")])
2371 (define_insn "*b<nzvccond:code>_reversed<mode>"
2373 (if_then_else (nzvccond (reg:NZVCUSE CRIS_CC0_REGNUM)
2376 (label_ref (match_operand 0 "" ""))))]
2379 [(set_attr "slottable" "has_slot")])
2381 (define_insn "*b<rnzcond:code>_reversed<mode>"
2383 (if_then_else (rnzcond (reg:NZUSE CRIS_CC0_REGNUM)
2386 (label_ref (match_operand 0 "" ""))))]
2389 return <MODE>mode == CC_NZmode ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
2391 [(set_attr "slottable" "has_slot")])
2393 ;; Set on condition: sCC.
2395 (define_expand "cstore<mode>4"
2397 [(set (match_operand:SI 0 "register_operand")
2398 (match_operator:SI 1 "ordered_comparison_operator"
2399 [(match_operand:BWDD 2 "nonimmediate_operand")
2400 (match_operand:BWDD 3 "general_operand")]))
2401 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2403 "cris_reduce_compare (&operands[1], &operands[2], &operands[3]);")
2405 (define_insn_and_split "*cstore<mode><code>4"
2406 [(set (match_operand:SI 0 "register_operand" "=<sCC_destc>")
2408 (match_operand:BWDD 1 "nonimmediate_operand" "<cmp_op0c>")
2409 (match_operand:BWDD 2 "general_operand" "<cmp_op1c>")))
2410 (clobber (reg:CC CRIS_CC0_REGNUM))]
2413 "&& reload_completed"
2414 [(set (reg:<xCC> CRIS_CC0_REGNUM)
2415 (compare:<xCC> (match_dup 1) (match_dup 2)))
2417 (cond:SI (reg:<xCC> CRIS_CC0_REGNUM) (const_int 0)))]
2420 ;; Like bCC, we have to check the overflow bit for
2421 ;; signed conditions.
2423 (define_insn "*s<nzcond:code><mode>"
2424 [(set (match_operand:SI 0 "register_operand" "=r")
2425 (nzcond:SI (reg:NZUSE CRIS_CC0_REGNUM) (const_int 0)))]
2428 [(set_attr "slottable" "yes")
2429 (set_attr "cc" "none")])
2431 (define_insn "*s<rnzcond:code><mode>"
2432 [(set (match_operand:SI 0 "register_operand" "=r")
2433 (rnzcond:SI (reg:NZUSE CRIS_CC0_REGNUM) (const_int 0)))]
2436 return <MODE>mode == CC_NZmode ? "s<oCC> %0" : "s<CC> %0";
2438 [(set_attr "slottable" "yes")
2439 (set_attr "cc" "none")])
2441 (define_insn "*s<nzvccond:code><mode>"
2442 [(set (match_operand:SI 0 "register_operand" "=r")
2443 (nzvccond:SI (reg:NZVCUSE CRIS_CC0_REGNUM) (const_int 0)))]
2446 [(set_attr "slottable" "yes")
2447 (set_attr "cc" "none")])
2451 ;; We need to make these patterns "expand", since the real operand is
2452 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
2453 ;; and cannot be checked if it were a "normal" pattern.
2454 ;; Note that "call" and "call_value" are *always* called with a
2455 ;; mem-operand for operand 0 and 1 respective. What happens for combined
2456 ;; instructions is a different issue.
2458 (define_expand "call"
2459 [(parallel [(call (match_operand:SI 0 "indirect_operand")
2460 (match_operand 1 "general_operand"))
2461 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2464 operands[1] = const0_rtx;
2467 ;; Accept operands for operand 0 in order of preference.
2469 (define_insn "*expanded_call"
2470 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
2472 (clobber (reg:SI CRIS_SRP_REGNUM))]
2476 (define_expand "call_value"
2477 [(parallel [(set (match_operand 0 "")
2478 (call (match_operand:SI 1 "indirect_operand")
2479 (match_operand 2 "")))
2480 (clobber (reg:SI CRIS_SRP_REGNUM))])]
2483 operands[2] = const0_rtx;
2486 ;; The validity other than "general" of
2487 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
2488 ;; order of preference (Q includes r, but r is shorter, faster).
2489 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
2490 ;; than requiring getting rPIC + sym:PLT into a register.
2492 (define_insn "*expanded_call_value"
2493 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
2494 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
2496 (clobber (reg:SI CRIS_SRP_REGNUM))]
2499 [(set_attr "cc" "clobber")])
2501 ;; Used in debugging. No use for the direct pattern; unfilled
2502 ;; delayed-branches are taken care of by other means.
2508 [(set_attr "cc" "none")])
2510 ;; Same as the gdb trap breakpoint: would cause a SIGTRAP for
2511 ;; cris-linux* and will work in freestanding environments with
2512 ;; sufficient framework.
2514 [(trap_if (const_int 1) (const_int 8))]
2515 "TARGET_TRAP_USING_BREAK8"
2518 ;; We need to stop accesses to the stack after the memory is
2519 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
2520 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
2521 ;; want to use a naked (unspec_volatile) as that would stop any
2522 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
2523 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
2524 ;; still has the effect of an unspec_volatile.
2525 (define_insn "cris_frame_deallocated_barrier"
2526 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
2527 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
2530 [(set_attr "length" "0")])
2532 ;; We expand on casesi so we can use "bound" and "add offset fetched from
2533 ;; a table to pc" (adds.w [pc+%0.w],pc).
2535 ;; Note: if you change the "parallel" (or add anything after it) in
2536 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
2537 ;; accordingly, to add the default case at the end of the jump-table.
2539 (define_expand "casesi"
2541 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
2542 (clobber (reg:CC CRIS_CC0_REGNUM))])
2545 (minus:SI (match_dup 5)
2546 (match_operand:SI 1 "const_int_operand")))
2547 (clobber (reg:CC CRIS_CC0_REGNUM))])
2550 (umin:SI (match_dup 6)
2551 (match_operand:SI 2 "const_int_operand")))
2552 (clobber (reg:CC CRIS_CC0_REGNUM))])
2556 (ltu (match_dup 7) (match_dup 2))
2557 (plus:SI (sign_extend:SI
2559 (plus:SI (mult:SI (match_dup 7) (const_int 2))
2562 (label_ref (match_operand 4 ""))))
2563 (use (label_ref (match_operand 3 "")))
2564 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2567 operands[2] = plus_constant (SImode, operands[2], 1);
2568 operands[5] = gen_reg_rtx (SImode);
2569 operands[6] = gen_reg_rtx (SImode);
2570 operands[7] = gen_reg_rtx (SImode);
2575 ;; Various peephole optimizations.
2577 ;; Do not add patterns that you do not know will be matched.
2578 ;; Please also add a self-contained testcase.
2580 ;; We have trouble with and:s and shifts. Maybe something is broken in
2581 ;; gcc? Or it could just be that bit-field insn expansion is a bit
2582 ;; suboptimal when not having extzv insns. Or combine being over-eager
2583 ;; to canonicalize to "and", and ignorant on the benefits of the right
2584 ;; mixture of "and" and "zero-extend".
2586 ;; Testcase for the following peephole: gcc.target/cris/peep2-movulsr.c
2588 ;; Where equivalent and where the "and" argument doesn't fit "andq" but
2589 ;; is 16 bits or smaller, replace the "and" with a zero-extend preceding
2590 ;; the shift. A zero-extend is shorter and faster than "and" with a
2593 (define_peephole2 ; movulsr
2595 [(set (match_operand:SI 0 "register_operand")
2596 (lshiftrt:SI (match_dup 0)
2597 (match_operand:SI 1 "const_int_operand")))
2598 (clobber (reg:CC CRIS_CC0_REGNUM))])
2601 (and:SI (match_dup 0)
2602 (match_operand 2 "const_int_operand")))
2603 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2604 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) <= 0xffff
2605 && (((INTVAL (operands[2]) <= 0xff ? 0xff : 0xffff) >> INTVAL (operands[1]))
2606 == INTVAL (operands[2]))"
2608 ;; The zero-extend is expressed as an "and", only because that's easier
2609 ;; than messing with zero-extend of a subreg.
2610 [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 3)))
2611 (clobber (reg:CC CRIS_CC0_REGNUM))])
2613 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
2614 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2617 = INTVAL (operands[2]) <= 0xff ? GEN_INT (0xff) : GEN_INT (0xffff);
2620 ;; Testcase for the following four peepholes: gcc.target/cris/peep2-xsrand.c
2622 (define_peephole2 ; asrandb
2624 [(set (match_operand:SI 0 "register_operand")
2625 (ashiftrt:SI (match_dup 0)
2626 (match_operand:SI 1 "const_int_operand")))
2627 (clobber (reg:CC CRIS_CC0_REGNUM))])
2630 (and:SI (match_dup 0)
2631 (match_operand 2 "const_int_operand")))
2632 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2633 "INTVAL (operands[2]) > 31
2634 && INTVAL (operands[2]) < 255
2635 && INTVAL (operands[1]) > 23
2636 /* Check that the and-operation enables us to use logical-shift. */
2637 && (INTVAL (operands[2])
2638 & ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U
2639 << (32 - INTVAL (operands[1]))))) == 0"
2641 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
2642 (clobber (reg:CC CRIS_CC0_REGNUM))])
2644 [(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))
2645 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2647 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
2648 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
2651 (define_peephole2 ; asrandw
2653 [(set (match_operand:SI 0 "register_operand")
2654 (ashiftrt:SI (match_dup 0)
2655 (match_operand:SI 1 "const_int_operand")))
2656 (clobber (reg:CC CRIS_CC0_REGNUM))])
2659 (and:SI (match_dup 0) (match_operand 2 "const_int_operand")))
2660 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2661 "INTVAL (operands[2]) > 31
2662 && INTVAL (operands[2]) < 65535
2663 && INTVAL (operands[2]) != 255
2664 && INTVAL (operands[1]) > 15
2665 /* Check that the and-operation enables us to use logical-shift. */
2666 && (INTVAL (operands[2])
2667 & ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U
2668 << (32 - INTVAL (operands[1]))))) == 0"
2670 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
2671 (clobber (reg:CC CRIS_CC0_REGNUM))])
2673 [(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))
2674 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2676 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
2677 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
2680 (define_peephole2 ; lsrandb
2682 [(set (match_operand:SI 0 "register_operand")
2683 (lshiftrt:SI (match_dup 0)
2684 (match_operand:SI 1 "const_int_operand")))
2685 (clobber (reg:CC CRIS_CC0_REGNUM))])
2688 (and:SI (match_dup 0) (match_operand 2 "const_int_operand")))
2689 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2690 "INTVAL (operands[2]) > 31
2691 && INTVAL (operands[2]) < 255
2692 && INTVAL (operands[1]) > 23"
2694 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
2695 (clobber (reg:CC CRIS_CC0_REGNUM))])
2697 [(set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))
2698 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2700 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
2701 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
2704 (define_peephole2 ; lsrandw
2706 [(set (match_operand:SI 0 "register_operand")
2707 (lshiftrt:SI (match_dup 0)
2708 (match_operand:SI 1 "const_int_operand")))
2709 (clobber (reg:CC CRIS_CC0_REGNUM))])
2712 (and:SI (match_dup 0) (match_operand 2 "const_int_operand")))
2713 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2714 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
2715 && INTVAL (operands[2]) != 255
2716 && INTVAL (operands[1]) > 15"
2718 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
2719 (clobber (reg:CC CRIS_CC0_REGNUM))])
2721 [(set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))
2722 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2724 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
2725 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
2728 ;; There seems to be no other way to make GCC (including 4.8/trunk at
2729 ;; r186932) optimally reload an instruction that looks like
2730 ;; and.d reg_or_mem,const_32__65535,other_reg
2731 ;; where other_reg is the destination.
2733 ;; movu.[bw] reg_or_mem,reg_32
2734 ;; and.[bw] trunc_int_for_mode([bw], const_32__65535),reg_32 ;; or andq
2735 ;; but it turns into:
2736 ;; move.d reg_or_mem,reg_32
2737 ;; and.d const_32__65535,reg_32
2738 ;; Fix it with these two peephole2's.
2739 ;; Testcases: gcc.target/cris/peep2-andu1.c gcc.target/cris/peep2-andu2.c
2741 (define_peephole2 ; andu
2743 [(set (match_operand:SI 0 "register_operand")
2744 (match_operand:SI 1 "nonimmediate_operand"))
2745 (clobber (reg:CC CRIS_CC0_REGNUM))])
2747 [(set (match_operand:SI 2 "register_operand")
2748 (and:SI (match_dup 0)
2749 (match_operand:SI 3 "const_int_operand")))
2750 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2751 ;; Since the size of the memory access could be made different here,
2752 ;; don't do this for a mem-volatile access.
2753 "REGNO (operands[2]) == REGNO (operands[0])
2754 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
2755 && !satisfies_constraint_I (operands[3])
2756 && !side_effects_p (operands[1])
2757 && (!REG_P (operands[1])
2758 || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)"
2760 [(set (match_dup 0) (match_dup 4))
2761 (clobber (reg:CC CRIS_CC0_REGNUM))])
2763 [(set (match_dup 5) (match_dup 6))
2764 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2766 machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
2768 = satisfies_constraint_O (operands[3]) ? SImode : zmode;
2770 = (REG_S_P (operands[1])
2771 ? gen_rtx_REG (zmode, REGNO (operands[1]))
2772 : adjust_address (operands[1], zmode, 0));
2774 = gen_rtx_ZERO_EXTEND (SImode, op1);
2775 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
2777 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
2778 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
2780 ? QImode : amode)));
2783 ;; Since r186861, gcc.target/cris/peep2-andu2.c trigs this pattern, with which
2790 ;; Only do this for values fitting the quick immediate operand.
2791 (define_peephole2 ; andqu
2793 [(set (match_operand:SI 0 "register_operand")
2794 (match_operand:SI 1 "const_int_operand"))
2795 (clobber (reg:CC CRIS_CC0_REGNUM))])
2798 (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand")))
2799 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2800 ;; Since the size of the memory access will be made different here,
2801 ;; don't do this for a volatile access or a post-incremented address.
2802 "satisfies_constraint_O (operands[1])
2803 && !side_effects_p (operands[2])
2804 && !reg_overlap_mentioned_p (operands[0], operands[2])"
2806 [(set (match_dup 0) (match_dup 3))
2807 (clobber (reg:CC CRIS_CC0_REGNUM))])
2809 [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))
2810 (clobber (reg:CC CRIS_CC0_REGNUM))])]
2812 machine_mode zmode = INTVAL (operands[1]) <= 255 ? QImode : HImode;
2814 = (REG_S_P (operands[2])
2815 ? gen_rtx_REG (zmode, REGNO (operands[2]))
2816 : adjust_address (operands[2], zmode, 0));
2817 operands[3] = gen_rtx_ZERO_EXTEND (SImode, op1);
2818 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));
2823 ;; comment-start: ";; "
2824 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
2825 ;; eval: (modify-syntax-entry ?[ "(]")
2826 ;; eval: (modify-syntax-entry ?] ")[")
2827 ;; eval: (modify-syntax-entry ?{ "(}")
2828 ;; eval: (modify-syntax-entry ?} "){")
2829 ;; eval: (setq indent-tabs-mode t)