1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
34 #include "fold-const.h"
36 #include "stor-layout.h"
45 #include "diagnostic-core.h"
51 #include "tm-constrs.h"
53 #include "insn-codes.h"
59 #include "cfgcleanup.h"
64 /* This file should be included last. */
65 #include "target-def.h"
67 /* Usable when we have an amount to add or subtract, and want the
68 optimal size of the insn. */
69 #define ADDITIVE_SIZE_MODIFIER(size) \
70 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
72 #define LOSE_AND_RETURN(msgid, x) \
75 cris_operand_lossage (msgid, x); \
79 enum cris_retinsn_type
80 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
82 /* Per-function machine data. */
83 struct GTY(()) machine_function
85 int needs_return_address_on_stack
;
87 /* This is the number of registers we save in the prologue due to
91 enum cris_retinsn_type return_type
;
94 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
96 static char cris_output_insn_is_bound
= 0;
98 /* In code for output macros, this is how we know whether e.g. constant
99 goes in code or in a static initializer. */
100 static int in_code
= 0;
102 /* Fix for reg_overlap_mentioned_p. */
103 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
105 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
106 int *, const_tree
, int);
108 static unsigned int cris_atomic_align_for_mode (machine_mode
);
110 static void cris_print_base (rtx
, FILE *);
112 static void cris_print_index (rtx
, FILE *);
114 static void cris_output_addr_const (FILE *, rtx
);
116 static struct machine_function
* cris_init_machine_status (void);
118 static rtx
cris_struct_value_rtx (tree
, int);
120 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
121 tree type
, int *, int);
123 static int cris_initial_frame_pointer_offset (void);
125 static void cris_operand_lossage (const char *, rtx
);
127 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
129 static void cris_print_operand (FILE *, rtx
, int);
131 static void cris_print_operand_address (FILE *, rtx
);
133 static bool cris_print_operand_punct_valid_p (unsigned char code
);
135 static bool cris_output_addr_const_extra (FILE *, rtx
);
137 static void cris_conditional_register_usage (void);
139 static void cris_asm_output_mi_thunk
140 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
142 static void cris_file_start (void);
143 static void cris_init_libfuncs (void);
145 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
147 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
148 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
149 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
150 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
151 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
153 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
155 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
157 static rtx
cris_function_incoming_arg (cumulative_args_t
,
158 machine_mode
, const_tree
, bool);
159 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
161 static rtx_insn
*cris_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
163 vec
<rtx
> &, HARD_REG_SET
&);
164 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
166 static void cris_option_override (void);
168 static bool cris_frame_pointer_required (void);
170 static void cris_asm_trampoline_template (FILE *);
171 static void cris_trampoline_init (rtx
, tree
, rtx
);
173 static rtx
cris_function_value(const_tree
, const_tree
, bool);
174 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
175 static bool cris_function_value_regno_p (const unsigned int);
176 static void cris_file_end (void);
178 /* This is the parsed result of the "-max-stack-stackframe=" option. If
179 it (still) is zero, then there was no such option given. */
180 int cris_max_stackframe
= 0;
182 /* This is the parsed result of the "-march=" option, if given. */
183 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
185 #undef TARGET_ASM_ALIGNED_HI_OP
186 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
187 #undef TARGET_ASM_ALIGNED_SI_OP
188 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
189 #undef TARGET_ASM_ALIGNED_DI_OP
190 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
192 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
193 available in ELF. These "normal" pseudos do not have any alignment
194 constraints or side-effects. */
195 #undef TARGET_ASM_UNALIGNED_HI_OP
196 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
198 #undef TARGET_ASM_UNALIGNED_SI_OP
199 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
201 #undef TARGET_ASM_UNALIGNED_DI_OP
202 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
204 #undef TARGET_PRINT_OPERAND
205 #define TARGET_PRINT_OPERAND cris_print_operand
206 #undef TARGET_PRINT_OPERAND_ADDRESS
207 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
208 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
209 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
210 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
211 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
213 #undef TARGET_CONDITIONAL_REGISTER_USAGE
214 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
216 #undef TARGET_ASM_OUTPUT_MI_THUNK
217 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
218 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
219 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
221 #undef TARGET_ASM_FILE_START
222 #define TARGET_ASM_FILE_START cris_file_start
223 #undef TARGET_ASM_FILE_END
224 #define TARGET_ASM_FILE_END cris_file_end
226 #undef TARGET_INIT_LIBFUNCS
227 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
229 #undef TARGET_LEGITIMATE_ADDRESS_P
230 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
232 #undef TARGET_LEGITIMATE_CONSTANT_P
233 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
235 #undef TARGET_PREFERRED_RELOAD_CLASS
236 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
238 #undef TARGET_REGISTER_MOVE_COST
239 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
240 #undef TARGET_MEMORY_MOVE_COST
241 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
242 #undef TARGET_RTX_COSTS
243 #define TARGET_RTX_COSTS cris_rtx_costs
244 #undef TARGET_ADDRESS_COST
245 #define TARGET_ADDRESS_COST cris_address_cost
247 #undef TARGET_PROMOTE_FUNCTION_MODE
248 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
250 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
251 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
253 #undef TARGET_STRUCT_VALUE_RTX
254 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
255 #undef TARGET_SETUP_INCOMING_VARARGS
256 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
257 #undef TARGET_PASS_BY_REFERENCE
258 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
259 #undef TARGET_ARG_PARTIAL_BYTES
260 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
261 #undef TARGET_FUNCTION_ARG
262 #define TARGET_FUNCTION_ARG cris_function_arg
263 #undef TARGET_FUNCTION_INCOMING_ARG
264 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
265 #undef TARGET_FUNCTION_ARG_ADVANCE
266 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
267 #undef TARGET_MD_ASM_ADJUST
268 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
270 #undef TARGET_CANNOT_FORCE_CONST_MEM
271 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
273 #undef TARGET_FRAME_POINTER_REQUIRED
274 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
276 #undef TARGET_OPTION_OVERRIDE
277 #define TARGET_OPTION_OVERRIDE cris_option_override
279 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
280 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
281 #undef TARGET_TRAMPOLINE_INIT
282 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
284 #undef TARGET_FUNCTION_VALUE
285 #define TARGET_FUNCTION_VALUE cris_function_value
286 #undef TARGET_LIBCALL_VALUE
287 #define TARGET_LIBCALL_VALUE cris_libcall_value
288 #undef TARGET_FUNCTION_VALUE_REGNO_P
289 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
291 struct gcc_target targetm
= TARGET_INITIALIZER
;
293 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
296 cris_movem_load_rest_p (rtx op
, int offs
)
298 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
304 unsigned int regno
= 0;
306 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
307 other than (MEM reg). */
309 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
310 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
311 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
314 /* Check a possible post-inc indicator. */
315 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
317 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
318 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
324 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
325 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
326 || !CONST_INT_P (inc
)
327 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
337 regno
= reg_count
- 1;
340 elt
= XVECEXP (op
, 0, offs
);
341 src_addr
= XEXP (SET_SRC (elt
), 0);
343 if (GET_CODE (elt
) != SET
344 || !REG_P (SET_DEST (elt
))
345 || GET_MODE (SET_DEST (elt
)) != SImode
346 || REGNO (SET_DEST (elt
)) != regno
347 || !MEM_P (SET_SRC (elt
))
348 || GET_MODE (SET_SRC (elt
)) != SImode
349 || !memory_address_p (SImode
, src_addr
))
352 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
354 rtx elt
= XVECEXP (op
, 0, i
);
357 if (GET_CODE (elt
) != SET
358 || !REG_P (SET_DEST (elt
))
359 || GET_MODE (SET_DEST (elt
)) != SImode
360 || REGNO (SET_DEST (elt
)) != regno
361 || !MEM_P (SET_SRC (elt
))
362 || GET_MODE (SET_SRC (elt
)) != SImode
363 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
364 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
365 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
366 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
373 /* Worker function for predicate for the parallel contents in a movem
377 cris_store_multiple_op_p (rtx op
)
379 int reg_count
= XVECLEN (op
, 0);
390 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
391 other than (MEM reg) and (MEM (PLUS reg const)). */
395 elt
= XVECEXP (op
, 0, 0);
397 if (GET_CODE (elt
) != SET
)
400 dest
= SET_DEST (elt
);
402 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
405 dest_addr
= XEXP (dest
, 0);
407 /* Check a possible post-inc indicator. */
408 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
410 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
411 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
417 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
418 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
419 || !CONST_INT_P (inc
)
420 /* Support increment by number of registers, and by the offset
421 of the destination, if it has the form (MEM (PLUS reg
423 || !((REG_P (dest_addr
)
424 && REGNO (dest_addr
) == REGNO (reg
)
425 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
426 || (GET_CODE (dest_addr
) == PLUS
427 && REG_P (XEXP (dest_addr
, 0))
428 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
429 && CONST_INT_P (XEXP (dest_addr
, 1))
430 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
441 regno
= reg_count
- 1;
444 if (GET_CODE (elt
) != SET
445 || !REG_P (SET_SRC (elt
))
446 || GET_MODE (SET_SRC (elt
)) != SImode
447 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
448 || !MEM_P (SET_DEST (elt
))
449 || GET_MODE (SET_DEST (elt
)) != SImode
)
452 if (REG_P (dest_addr
))
454 dest_base
= dest_addr
;
457 else if (GET_CODE (dest_addr
) == PLUS
458 && REG_P (XEXP (dest_addr
, 0))
459 && CONST_INT_P (XEXP (dest_addr
, 1)))
461 dest_base
= XEXP (dest_addr
, 0);
462 offset
= INTVAL (XEXP (dest_addr
, 1));
467 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
469 rtx elt
= XVECEXP (op
, 0, i
);
472 if (GET_CODE (elt
) != SET
473 || !REG_P (SET_SRC (elt
))
474 || GET_MODE (SET_SRC (elt
)) != SImode
475 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
476 || !MEM_P (SET_DEST (elt
))
477 || GET_MODE (SET_DEST (elt
)) != SImode
478 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
479 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
480 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
481 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
488 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
491 cris_conditional_register_usage (void)
493 /* FIXME: This isn't nice. We should be able to use that register for
494 something else if the PIC table isn't needed. */
496 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
497 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
499 /* Allow use of ACR (PC in pre-V32) and tweak order. */
502 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
505 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
508 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
510 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
513 if (TARGET_HAS_MUL_INSNS
)
514 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
516 /* On early versions, we must use the 16-bit condition-code register,
517 which has another name. */
518 if (cris_cpu_version
< 8)
519 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
522 /* Return crtl->uses_pic_offset_table. For use in cris.md,
523 since some generated files do not include function.h. */
526 cris_cfun_uses_pic_table (void)
528 return crtl
->uses_pic_offset_table
;
531 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
532 We can't put PIC addresses in the constant pool, not even the ones that
533 can be reached as pc-relative as we can't tell when or how to do that. */
536 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
538 enum cris_symbol_type t
= cris_symbol_type_of (x
);
542 || t
== cris_got_symbol
543 || t
== cris_rel_symbol
;
546 /* Given an rtx, return the text string corresponding to the CODE of X.
547 Intended for use in the assembly language output section of a
553 cris_output_insn_is_bound
= 0;
554 switch (GET_CODE (x
))
565 /* This function is for retrieving a part of an instruction name for
566 an operator, for immediate output. If that ever happens for
567 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
569 internal_error ("MULT case in cris_op_str");
605 /* Used to control the sign/zero-extend character for the 'E' modifier.
607 cris_output_insn_is_bound
= 1;
612 return "Unknown operator";
617 /* Emit an error message when we're in an asm, and a fatal error for
618 "normal" insns. Formatted output isn't easily implemented, since we
619 use output_operand_lossage to output the actual message and handle the
620 categorization of the error. */
623 cris_operand_lossage (const char *msgid
, rtx op
)
626 output_operand_lossage ("%s", msgid
);
629 /* Print an index part of an address to file. */
632 cris_print_index (rtx index
, FILE *file
)
634 /* Make the index "additive" unless we'll output a negative number, in
635 which case the sign character is free (as in free beer). */
636 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
640 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
641 else if (CRIS_CONSTANT_P (index
))
642 cris_output_addr_const (file
, index
);
643 else if (GET_CODE (index
) == MULT
)
645 fprintf (file
, "$%s.",
646 reg_names
[REGNO (XEXP (index
, 0))]);
648 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
650 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
652 rtx inner
= XEXP (index
, 0);
653 rtx inner_inner
= XEXP (inner
, 0);
655 if (GET_CODE (inner_inner
) == POST_INC
)
657 fprintf (file
, "[$%s+].",
658 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
659 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
663 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
665 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
668 else if (MEM_P (index
))
670 rtx inner
= XEXP (index
, 0);
671 if (GET_CODE (inner
) == POST_INC
)
672 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
674 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
677 cris_operand_lossage ("unexpected index-type in cris_print_index",
681 /* Print a base rtx of an address to file. */
684 cris_print_base (rtx base
, FILE *file
)
687 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
688 else if (GET_CODE (base
) == POST_INC
)
690 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
691 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
694 cris_operand_lossage ("unexpected base-type in cris_print_base",
698 /* Usable as a guard in expressions. */
701 cris_fatal (char *arg
)
703 internal_error (arg
);
705 /* We'll never get here; this is just to appease compilers. */
709 /* Return nonzero if REGNO is an ordinary register that *needs* to be
710 saved together with other registers, possibly by a MOVEM instruction,
711 or is saved for target-independent reasons. There may be
712 target-dependent reasons to save the register anyway; this is just a
713 wrapper for a complicated conditional. */
716 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
719 (((df_regs_ever_live_p (regno
)
720 && !call_used_regs
[regno
])
721 || (regno
== PIC_OFFSET_TABLE_REGNUM
723 /* It is saved anyway, if there would be a gap. */
725 && df_regs_ever_live_p (regno
+ 1)
726 && !call_used_regs
[regno
+ 1]))))
727 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
728 && regno
!= CRIS_SRP_REGNUM
)
729 || (crtl
->calls_eh_return
730 && (regno
== EH_RETURN_DATA_REGNO (0)
731 || regno
== EH_RETURN_DATA_REGNO (1)
732 || regno
== EH_RETURN_DATA_REGNO (2)
733 || regno
== EH_RETURN_DATA_REGNO (3)));
736 /* The PRINT_OPERAND worker. */
739 cris_print_operand (FILE *file
, rtx x
, int code
)
743 /* Size-strings corresponding to MULT expressions. */
744 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
746 /* New code entries should just be added to the switch below. If
747 handling is finished, just return. If handling was just a
748 modification of the operand, the modified operand should be put in
749 "operand", and then do a break to let default handling
750 (zero-modifier) output the operand. */
755 /* Print the unsigned supplied integer as if it were signed
756 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
757 if (!satisfies_constraint_O (x
))
758 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
759 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
760 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
764 /* Print assembler code for operator. */
765 fprintf (file
, "%s", cris_op_str (operand
));
770 /* A movem modifier working on a parallel; output the register
774 if (GET_CODE (x
) != PARALLEL
)
775 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
777 /* The second item can be (set reg (plus reg const)) to denote a
780 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
782 : XVECLEN (x
, 0) - 1);
784 fprintf (file
, "$%s", reg_names
[regno
]);
790 /* A similar movem modifier; output the memory operand. */
793 if (GET_CODE (x
) != PARALLEL
)
794 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
796 /* The lowest mem operand is in the first item, but perhaps it
797 needs to be output as postincremented. */
798 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
799 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
800 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
802 /* The second item can be a (set reg (plus reg const)) to denote
804 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
806 /* It's a post-increment, if the address is a naked (reg). */
808 addr
= gen_rtx_POST_INC (SImode
, addr
);
811 /* Otherwise, it's a side-effect; RN=RN+M. */
812 fprintf (file
, "[$%s=$%s%s%d]",
813 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
814 reg_names
[REGNO (XEXP (addr
, 0))],
815 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
816 (int) INTVAL (XEXP (addr
, 1)));
820 output_address (addr
);
825 /* Adjust a power of two to its log2. */
826 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
827 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
828 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
832 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
833 respectively. This modifier also terminates the inhibiting
834 effects of the 'x' modifier. */
835 cris_output_insn_is_bound
= 0;
836 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
840 if (INTVAL (x
) <= 255)
842 else if (INTVAL (x
) <= 65535)
852 /* For a non-integer, print the size of the operand. */
853 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
854 ? 'd' : GET_MODE (x
) == HImode
? 'w'
855 : GET_MODE (x
) == QImode
? 'b'
856 /* If none of the above, emit an erroneous size letter. */
862 /* Const_int: print b for -127 <= x <= 255,
863 w for -32768 <= x <= 65535, else die. */
865 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
866 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
867 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
871 /* If this is a GOT-symbol, print the size-letter corresponding to
872 -fpic/-fPIC. For everything else, print "d". */
874 && GET_CODE (x
) == CONST
875 && GET_CODE (XEXP (x
, 0)) == UNSPEC
876 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
881 /* Output a 'nop' if there's nothing for the delay slot.
882 This method stolen from the sparc files. */
883 if (dbr_sequence_length () == 0)
884 fputs ("\n\tnop", file
);
888 /* Output directive for alignment padded with "nop" insns.
889 Optimizing for size, it's plain 4-byte alignment, otherwise we
890 align the section to a cache-line (32 bytes) and skip at max 2
891 bytes, i.e. we skip if it's the last insn on a cache-line. The
892 latter is faster by a small amount (for two test-programs 99.6%
893 and 99.9%) and larger by a small amount (ditto 100.1% and
894 100.2%). This is supposed to be the simplest yet performance-
895 wise least intrusive way to make sure the immediately following
896 (supposed) muls/mulu insn isn't located at the end of a
900 ? ".p2alignw 2,0x050f\n\t"
901 : ".p2alignw 5,0x050f,2\n\t", file
);
905 /* The PIC register. */
907 internal_error ("invalid use of ':' modifier");
908 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
912 /* Print high (most significant) part of something. */
913 switch (GET_CODE (operand
))
916 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
917 value is kept here, and so may be other than 0 or -1. */
918 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
919 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
923 /* High part of a long long constant. */
924 if (GET_MODE (operand
) == VOIDmode
)
926 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
930 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
933 /* Print reg + 1. Check that there's not an attempt to print
934 high-parts of registers like stack-pointer or higher, except
935 for SRP (where the "high part" is MOF). */
936 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
937 && (REGNO (operand
) != CRIS_SRP_REGNUM
938 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
939 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
940 LOSE_AND_RETURN ("bad register", operand
);
941 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
945 /* Adjust memory address to high part. */
947 rtx adj_mem
= operand
;
949 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
951 /* Adjust so we can use two SImode in DImode.
952 Calling adj_offsettable_operand will make sure it is an
953 offsettable address. Don't do this for a postincrement
954 though; it should remain as it was. */
955 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
957 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
959 output_address (XEXP (adj_mem
, 0));
964 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
968 /* Strip the MEM expression. */
969 operand
= XEXP (operand
, 0);
973 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
974 iterators and attributes in cris.md to avoid the need for %x
975 and %E (and %e) and state passed between those modifiers. */
976 cris_output_insn_is_bound
= 0;
979 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
980 cris_output_insn_is_bound is nonzero. */
981 if (GET_CODE (operand
) != SIGN_EXTEND
982 && GET_CODE (operand
) != ZERO_EXTEND
983 && !CONST_INT_P (operand
))
984 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
986 if (cris_output_insn_is_bound
)
988 cris_output_insn_is_bound
= 0;
992 putc (GET_CODE (operand
) == SIGN_EXTEND
993 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
998 /* Print the size letter of the inner element. We can do it by
999 calling ourselves with the 's' modifier. */
1000 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1001 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1002 cris_print_operand (file
, XEXP (operand
, 0), 's');
1006 /* Print the least significant part of operand. */
1007 if (GET_CODE (operand
) == CONST_DOUBLE
)
1009 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1012 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1014 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1015 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1018 /* Otherwise the least significant part equals the normal part,
1019 so handle it normally. */
1023 /* When emitting an add for the high part of a DImode constant, we
1024 want to use addq for 0 and adds.w for -1. */
1025 if (!CONST_INT_P (operand
))
1026 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1027 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1031 /* For const_int operands, print the additive mnemonic and the
1032 modified operand (byte-sized operands don't save anything):
1033 N=MIN_INT..-65536: add.d N
1034 -65535..-64: subu.w -N
1038 65536..MAX_INT: add.d N.
1039 (Emitted mnemonics are capitalized to simplify testing.)
1040 For anything else (N.B: only register is valid), print "add.d". */
1041 if (REG_P (operand
))
1043 fprintf (file
, "Add.d ");
1045 /* Deal with printing the operand by dropping through to the
1052 gcc_assert (CONST_INT_P (operand
));
1054 val
= INTVAL (operand
);
1055 if (!IN_RANGE (val
, -65535, 65535))
1056 fprintf (file
, "Add.d %d", val
);
1057 else if (val
<= -64)
1058 fprintf (file
, "Subu.w %d", -val
);
1060 fprintf (file
, "Subq %d", -val
);
1062 fprintf (file
, "Addq %d", val
);
1063 else if (val
<= 65535)
1064 fprintf (file
, "Addu.w %d", val
);
1070 /* If the operand is an integer -31..31, print "q" else ".d". */
1071 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1072 fprintf (file
, "q");
1074 fprintf (file
, ".d");
1078 /* If this is a GOT symbol, force it to be emitted as :GOT and
1079 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1080 Avoid making this too much of a special case. */
1081 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1083 int flag_pic_save
= flag_pic
;
1086 cris_output_addr_const (file
, operand
);
1087 flag_pic
= flag_pic_save
;
1093 /* When emitting an sub for the high part of a DImode constant, we
1094 want to use subq for 0 and subs.w for -1. */
1095 if (!CONST_INT_P (operand
))
1096 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1097 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1101 /* Print the operand as the index-part of an address.
1102 Easiest way out is to use cris_print_index. */
1103 cris_print_index (operand
, file
);
1107 /* Print the size letter for an operand to a MULT, which must be a
1108 const_int with a suitable value. */
1109 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1110 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1111 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1115 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1117 && GET_CODE (operand
) == CONST
1118 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1119 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1120 fprintf (file
, "u.w");
1122 fprintf (file
, ".d");
1126 /* No code, print as usual. */
1130 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1133 /* Print an operand as without a modifier letter. */
1134 switch (GET_CODE (operand
))
1137 if (REGNO (operand
) > 15
1138 && REGNO (operand
) != CRIS_MOF_REGNUM
1139 && REGNO (operand
) != CRIS_SRP_REGNUM
1140 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1141 internal_error ("internal error: bad register: %d", REGNO (operand
));
1142 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1146 output_address (XEXP (operand
, 0));
1150 if (GET_MODE (operand
) == VOIDmode
)
1151 /* A long long constant. */
1152 output_addr_const (file
, operand
);
1155 /* Only single precision is allowed as plain operands the
1156 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1161 /* FIXME: Perhaps check overflow of the "single". */
1162 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1163 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1165 fprintf (file
, "0x%lx", l
);
1172 cris_output_addr_const (file
, operand
);
1178 /* For a (MULT (reg X) const_int) we output "rX.S". */
1179 int i
= CONST_INT_P (XEXP (operand
, 1))
1180 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1181 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1182 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1185 || (!CONST_INT_P (XEXP (operand
, 0))
1186 && !CONST_INT_P (XEXP (operand
, 1))))
1187 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1189 cris_print_base (reg
, file
);
1190 fprintf (file
, ".%c",
1191 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1193 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1199 /* No need to handle all strange variants, let output_addr_const
1201 if (CRIS_CONSTANT_P (operand
))
1203 cris_output_addr_const (file
, operand
);
1207 LOSE_AND_RETURN ("unexpected operand", x
);
1212 cris_print_operand_punct_valid_p (unsigned char code
)
1214 return (code
== '#' || code
== '!' || code
== ':');
1217 /* The PRINT_OPERAND_ADDRESS worker. */
1220 cris_print_operand_address (FILE *file
, rtx x
)
1222 /* All these were inside MEM:s so output indirection characters. */
1225 if (CONSTANT_ADDRESS_P (x
))
1226 cris_output_addr_const (file
, x
);
1227 else if (cris_base_or_autoincr_p (x
, true))
1228 cris_print_base (x
, file
);
1229 else if (GET_CODE (x
) == PLUS
)
1235 if (cris_base_p (x1
, true))
1237 cris_print_base (x1
, file
);
1238 cris_print_index (x2
, file
);
1240 else if (cris_base_p (x2
, true))
1242 cris_print_base (x2
, file
);
1243 cris_print_index (x1
, file
);
1246 LOSE_AND_RETURN ("unrecognized address", x
);
1250 /* A DIP. Output more indirection characters. */
1252 cris_print_base (XEXP (x
, 0), file
);
1256 LOSE_AND_RETURN ("unrecognized address", x
);
1261 /* The RETURN_ADDR_RTX worker.
1262 We mark that the return address is used, either by EH or
1263 __builtin_return_address, for use by the function prologue and
1264 epilogue. FIXME: This isn't optimal; we just use the mark in the
1265 prologue and epilogue to say that the return address is to be stored
1266 in the stack frame. We could return SRP for leaf-functions and use the
1267 initial-value machinery. */
1270 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1272 cfun
->machine
->needs_return_address_on_stack
= 1;
1274 /* The return-address is stored just above the saved frame-pointer (if
1275 present). Apparently we can't eliminate from the frame-pointer in
1276 that direction, so use the incoming args (maybe pretended) pointer. */
1278 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1282 /* Accessor used in cris.md:return because cfun->machine isn't available
1286 cris_return_address_on_stack (void)
1288 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1289 || cfun
->machine
->needs_return_address_on_stack
;
1292 /* Accessor used in cris.md:return because cfun->machine isn't available
1296 cris_return_address_on_stack_for_return (void)
1298 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1299 : cris_return_address_on_stack ();
1302 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1303 handles FP -> SP elimination offset. */
1306 cris_initial_frame_pointer_offset (void)
1310 /* Initial offset is 0 if we don't have a frame pointer. */
1312 bool got_really_used
= false;
1314 if (crtl
->uses_pic_offset_table
)
1316 push_topmost_sequence ();
1318 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1320 pop_topmost_sequence ();
1323 /* And 4 for each register pushed. */
1324 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1325 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1328 /* And then, last, we add the locals allocated. */
1329 offs
+= get_frame_size ();
1331 /* And more; the accumulated args size. */
1332 offs
+= crtl
->outgoing_args_size
;
1334 /* Then round it off, in case we use aligned stack. */
1335 if (TARGET_STACK_ALIGN
)
1336 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1341 /* The INITIAL_ELIMINATION_OFFSET worker.
1342 Calculate the difference between imaginary registers such as frame
1343 pointer and the stack pointer. Used to eliminate the frame pointer
1344 and imaginary arg pointer. */
1347 cris_initial_elimination_offset (int fromreg
, int toreg
)
1350 = cris_initial_frame_pointer_offset ();
1352 /* We should be able to use regs_ever_live and related prologue
1353 information here, or alpha should not as well. */
1354 bool return_address_on_stack
= cris_return_address_on_stack ();
1356 /* Here we act as if the frame-pointer were needed. */
1357 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1359 if (fromreg
== ARG_POINTER_REGNUM
1360 && toreg
== FRAME_POINTER_REGNUM
)
1361 return ap_fp_offset
;
1363 /* Between the frame pointer and the stack are only "normal" stack
1364 variables and saved registers. */
1365 if (fromreg
== FRAME_POINTER_REGNUM
1366 && toreg
== STACK_POINTER_REGNUM
)
1367 return fp_sp_offset
;
1369 /* We need to balance out the frame pointer here. */
1370 if (fromreg
== ARG_POINTER_REGNUM
1371 && toreg
== STACK_POINTER_REGNUM
)
1372 return ap_fp_offset
+ fp_sp_offset
- 4;
1377 /* Nonzero if X is a hard reg that can be used as an index. */
1379 reg_ok_for_base_p (const_rtx x
, bool strict
)
1381 return ((! strict
&& ! HARD_REGISTER_P (x
))
1382 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1385 /* Nonzero if X is a hard reg that can be used as an index. */
1387 reg_ok_for_index_p (const_rtx x
, bool strict
)
1389 return reg_ok_for_base_p (x
, strict
);
1392 /* No symbol can be used as an index (or more correct, as a base) together
1393 with a register with PIC; the PIC register must be there. */
1396 cris_constant_index_p (const_rtx x
)
1398 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1401 /* True if X is a valid base register. */
1404 cris_base_p (const_rtx x
, bool strict
)
1406 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1409 /* True if X is a valid index register. */
1412 cris_index_p (const_rtx x
, bool strict
)
1414 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1417 /* True if X is a valid base register with or without autoincrement. */
1420 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1422 return (cris_base_p (x
, strict
)
1423 || (GET_CODE (x
) == POST_INC
1424 && cris_base_p (XEXP (x
, 0), strict
)
1425 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1428 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1431 cris_bdap_index_p (const_rtx x
, bool strict
)
1434 && GET_MODE (x
) == SImode
1435 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1436 || (GET_CODE (x
) == SIGN_EXTEND
1437 && MEM_P (XEXP (x
, 0))
1438 && (GET_MODE (XEXP (x
, 0)) == HImode
1439 || GET_MODE (XEXP (x
, 0)) == QImode
)
1440 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1443 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1446 cris_biap_index_p (const_rtx x
, bool strict
)
1448 return (cris_index_p (x
, strict
)
1449 || (GET_CODE (x
) == MULT
1450 && cris_index_p (XEXP (x
, 0), strict
)
1451 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1454 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1456 A PIC operand looks like a normal symbol here. At output we dress it
1457 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1458 symbol) so we exclude all addressing modes where we can't replace a
1459 plain "symbol" with that. A global PIC symbol does not fit anywhere
1460 here (but is thankfully a general_operand in itself). A local PIC
1461 symbol is valid for the plain "symbol + offset" case. */
1464 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1468 if (cris_base_or_autoincr_p (x
, strict
))
1470 else if (TARGET_V32
)
1471 /* Nothing else is valid then. */
1473 else if (cris_constant_index_p (x
))
1476 else if (GET_CODE (x
) == PLUS
)
1481 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1482 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1483 /* BDAP Rs[+], Rd. */
1484 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1485 && ((cris_base_p (x1
, strict
)
1486 && cris_bdap_index_p (x2
, strict
))
1487 || (cris_base_p (x2
, strict
)
1488 && cris_bdap_index_p (x1
, strict
))
1490 || (cris_base_p (x1
, strict
)
1491 && cris_biap_index_p (x2
, strict
))
1492 || (cris_base_p (x2
, strict
)
1493 && cris_biap_index_p (x1
, strict
)))))
1498 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1499 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1500 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1507 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1508 PIC constants that aren't legitimized. FIXME: there used to be a
1509 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1510 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1511 While that may be seen as a bug, that guarantee seems a wart by design,
1512 so don't bother; fix the documentation instead. */
1515 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1517 enum cris_symbol_type t
;
1520 return LEGITIMATE_PIC_OPERAND_P (x
);
1522 t
= cris_symbol_type_of (x
);
1526 || t
== cris_offsettable_symbol
1527 || t
== cris_unspec
;
1530 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1533 cris_reload_address_legitimized (rtx x
,
1534 machine_mode mode ATTRIBUTE_UNUSED
,
1535 int opnum ATTRIBUTE_UNUSED
,
1537 int ind_levels ATTRIBUTE_UNUSED
)
1539 enum reload_type type
= (enum reload_type
) itype
;
1543 if (GET_CODE (x
) != PLUS
)
1551 op1p
= &XEXP (x
, 1);
1556 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1558 rtx op00
= XEXP (op0
, 0);
1559 rtx op000
= XEXP (op00
, 0);
1560 rtx
*op000p
= &XEXP (op00
, 0);
1562 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1564 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1566 bool something_reloaded
= false;
1568 if (GET_CODE (op000
) == POST_INC
1569 && REG_P (XEXP (op000
, 0))
1570 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1571 /* No, this gets too complicated and is too rare to care
1572 about trying to improve on the general code Here.
1573 As the return-value is an all-or-nothing indicator, we
1574 punt on the other register too. */
1578 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1580 /* The address of the inner mem is a pseudo or wrong
1581 reg: reload that. */
1582 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1583 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1584 something_reloaded
= true;
1587 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1589 /* Base register is a pseudo or wrong reg: reload it. */
1590 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1591 GET_MODE (x
), VOIDmode
, 0, 0,
1593 something_reloaded
= true;
1596 gcc_assert (something_reloaded
);
1606 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1608 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1609 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1610 out a constant into the constant pool, we will trap this case and
1611 return something a bit more sane. FIXME: Check if this is a bug.
1612 Beware that we must not "override" classes that can be specified as
1613 constraint letters, or else asm operands using them will fail when
1614 they need to be reloaded. FIXME: Investigate whether that constitutes
1618 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1620 if (rclass
!= ACR_REGS
1621 && rclass
!= MOF_REGS
1622 && rclass
!= MOF_SRP_REGS
1623 && rclass
!= SRP_REGS
1624 && rclass
!= CC0_REGS
1625 && rclass
!= SPECIAL_REGS
)
1626 return GENERAL_REGS
;
1631 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1634 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1635 reg_class_t from
, reg_class_t to
)
1637 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1638 their move cost within that class is higher. How about 7? That's 3
1639 for a move to a GENERAL_REGS register, 3 for the move from the
1640 GENERAL_REGS register, and 1 for the increased register pressure.
1641 Also, it's higher than the memory move cost, as it should.
1642 We also do this for ALL_REGS, since we don't want that class to be
1643 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1644 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1645 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1646 used when a GENERAL_REGS should be used, even if there are call-saved
1647 GENERAL_REGS left to allocate. This is because the fall-back when
1648 the most preferred register class isn't available, isn't the next
1649 (or next good) wider register class, but the *most widest* register
1650 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1652 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1653 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1654 || from
== ALL_REGS
|| to
== ALL_REGS
)
1657 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1658 generally prefer GENERAL_REGS. */
1659 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1660 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1666 /* Worker function for TARGET_MEMORY_MOVE_COST.
1668 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1672 cris_memory_move_cost (machine_mode mode
,
1673 reg_class_t rclass ATTRIBUTE_UNUSED
,
1674 bool in ATTRIBUTE_UNUSED
)
1683 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1684 FIXME: this code is historical; its functionality should be
1685 refactored to look at insn attributes and moved to
1686 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1689 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1691 /* "Normal" means, for:
1696 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1697 register or (v32 and (...) is -32..-1), then CC does not change.
1698 CC_NO_OVERFLOW unless (...) is reg or mem.
1707 (set (reg1) (mem (bdap/biap)))
1708 (set (reg2) (bdap/biap))):
1709 CC is (reg1) and (mem (reg2))
1712 (set (mem (bdap/biap)) (reg1)) [or 0]
1713 (set (reg2) (bdap/biap))):
1716 (where reg and mem includes strict_low_parts variants thereof)
1718 For all others, assume CC is clobbered.
1719 Note that we do not have to care about setting CC_NO_OVERFLOW,
1720 since the overflow flag is set to 0 (i.e. right) for
1721 instructions where it does not have any sane sense, but where
1722 other flags have meanings. (This includes shifts; the carry is
1725 Note that there are other parallel constructs we could match,
1726 but we don't do that yet. */
1728 if (GET_CODE (exp
) == SET
)
1730 /* FIXME: Check when this happens. It looks like we should
1731 actually do a CC_STATUS_INIT here to be safe. */
1732 if (SET_DEST (exp
) == pc_rtx
)
1735 /* Record CC0 changes, so we do not have to output multiple
1737 if (SET_DEST (exp
) == cc0_rtx
)
1741 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1742 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1743 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1745 cc_status
.value1
= SET_SRC (exp
);
1747 /* Handle flags for the special btstq on one bit. */
1748 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1749 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1751 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1753 cc_status
.flags
= CC_INVERTED
;
1755 /* A one-bit btstq. */
1756 cc_status
.flags
= CC_Z_IN_NOT_N
;
1759 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1761 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1762 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1763 /* For some reason gcc will not canonicalize compare
1764 operations, reversing the sign by itself if
1765 operands are in wrong order. */
1766 /* (But NOT inverted; eq is still eq.) */
1767 cc_status
.flags
= CC_REVERSED
;
1769 /* This seems to be overlooked by gcc. FIXME: Check again.
1770 FIXME: Is it really safe? */
1772 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1773 XEXP (SET_SRC (exp
), 0),
1774 XEXP (SET_SRC (exp
), 1));
1778 else if (REG_P (SET_DEST (exp
))
1779 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1780 && REG_P (XEXP (SET_DEST (exp
), 0))))
1782 /* A register is set; normally CC is set to show that no
1783 test insn is needed. Catch the exceptions. */
1785 /* If not to cc0, then no "set"s in non-natural mode give
1787 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1788 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1790 /* ... except add:s and sub:s in DImode. */
1791 if (GET_MODE (SET_DEST (exp
)) == DImode
1792 && (GET_CODE (SET_SRC (exp
)) == PLUS
1793 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1796 cc_status
.value1
= SET_DEST (exp
);
1797 cc_status
.value2
= SET_SRC (exp
);
1799 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1801 cc_status
.value2
= 0;
1803 /* Add and sub may set V, which gets us
1804 unoptimizable results in "gt" and "le" condition
1806 cc_status
.flags
|= CC_NO_OVERFLOW
;
1811 else if (SET_SRC (exp
) == const0_rtx
1812 || (REG_P (SET_SRC (exp
))
1813 && (REGNO (SET_SRC (exp
))
1814 > CRIS_LAST_GENERAL_REGISTER
))
1816 && REG_P (SET_DEST (exp
))
1817 && satisfies_constraint_I (SET_SRC (exp
))))
1819 /* There's no CC0 change for this case. Just check
1821 if (cc_status
.value1
1822 && modified_in_p (cc_status
.value1
, insn
))
1823 cc_status
.value1
= 0;
1825 if (cc_status
.value2
1826 && modified_in_p (cc_status
.value2
, insn
))
1827 cc_status
.value2
= 0;
1834 cc_status
.value1
= SET_DEST (exp
);
1835 cc_status
.value2
= SET_SRC (exp
);
1837 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1839 cc_status
.value2
= 0;
1841 /* Some operations may set V, which gets us
1842 unoptimizable results in "gt" and "le" condition
1844 if (GET_CODE (SET_SRC (exp
)) == PLUS
1845 || GET_CODE (SET_SRC (exp
)) == MINUS
1846 || GET_CODE (SET_SRC (exp
)) == NEG
)
1847 cc_status
.flags
|= CC_NO_OVERFLOW
;
1849 /* For V32, nothing with a register destination sets
1850 C and V usefully. */
1852 cc_status
.flags
|= CC_NO_OVERFLOW
;
1857 else if (MEM_P (SET_DEST (exp
))
1858 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1859 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1861 /* When SET to MEM, then CC is not changed (except for
1863 if (cc_status
.value1
1864 && modified_in_p (cc_status
.value1
, insn
))
1865 cc_status
.value1
= 0;
1867 if (cc_status
.value2
1868 && modified_in_p (cc_status
.value2
, insn
))
1869 cc_status
.value2
= 0;
1874 else if (GET_CODE (exp
) == PARALLEL
)
1876 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1877 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1878 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1880 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1881 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1885 /* For "move.S [rx=ry+o],rz", say CC reflects
1886 value1=rz and value2=[rx] */
1887 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1889 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1890 XEXP (XVECEXP (exp
, 0, 1), 0));
1892 /* Huh? A side-effect cannot change the destination
1894 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1896 internal_error ("internal error: sideeffect-insn affecting main effect");
1898 /* For V32, moves to registers don't set C and V. */
1900 cc_status
.flags
|= CC_NO_OVERFLOW
;
1903 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1904 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1905 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1907 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1908 say flags are not changed, except for overlap. */
1909 if (cc_status
.value1
1910 && modified_in_p (cc_status
.value1
, insn
))
1911 cc_status
.value1
= 0;
1913 if (cc_status
.value2
1914 && modified_in_p (cc_status
.value2
, insn
))
1915 cc_status
.value2
= 0;
1922 /* If we got here, the case wasn't covered by the code above. */
1926 /* This function looks into the pattern to see how this insn affects
1929 Used when to eliminate test insns before a condition-code user,
1930 such as a "scc" insn or a conditional branch. This includes
1931 checking if the entities that cc was updated by, are changed by the
1934 Currently a jumble of the old peek-inside-the-insn and the newer
1935 check-cc-attribute methods. */
1938 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1940 enum attr_cc attrval
= get_attr_cc (insn
);
1942 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1943 to still set CC_REVERSED as below, since that's required by some
1944 compare insn alternatives. (FIXME: GCC should do this virtual
1945 operand swap by itself.) A test-case that may otherwise fail is
1946 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1951 if (attrval
== CC_REV
)
1952 cc_status
.flags
= CC_REVERSED
;
1956 /* Slowly, we're converting to using attributes to control the setting
1957 of condition-code status. */
1961 /* Even if it is "none", a setting may clobber a previous
1962 cc-value, so check. */
1963 if (GET_CODE (exp
) == SET
)
1965 if (cc_status
.value1
1966 && modified_in_p (cc_status
.value1
, insn
))
1967 cc_status
.value1
= 0;
1969 if (cc_status
.value2
1970 && modified_in_p (cc_status
.value2
, insn
))
1971 cc_status
.value2
= 0;
1982 cris_normal_notice_update_cc (exp
, insn
);
1984 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1985 can change bge => bpl and blt => bmi by passing on to the cc0
1986 user that V should not be considered; bgt and ble are taken
1987 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1988 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1989 cc_status
.flags
|= CC_NO_OVERFLOW
;
1993 internal_error ("unknown cc_attr value");
1999 /* Return != 0 if the return sequence for the current function is short,
2000 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
2001 registers must be saved, so return 0 then. */
2004 cris_simple_epilogue (void)
2007 unsigned int reglimit
= STACK_POINTER_REGNUM
;
2008 bool got_really_used
= false;
2010 if (! reload_completed
2011 || frame_pointer_needed
2012 || get_frame_size () != 0
2013 || crtl
->args
.pretend_args_size
2015 || crtl
->outgoing_args_size
2016 || crtl
->calls_eh_return
2018 /* If we're not supposed to emit prologue and epilogue, we must
2019 not emit return-type instructions. */
2020 || !TARGET_PROLOGUE_EPILOGUE
)
2023 /* Can't return from stacked return address with v32. */
2024 if (TARGET_V32
&& cris_return_address_on_stack ())
2027 if (crtl
->uses_pic_offset_table
)
2029 push_topmost_sequence ();
2031 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2032 pop_topmost_sequence ();
2035 /* No simple epilogue if there are saved registers. */
2036 for (regno
= 0; regno
< reglimit
; regno
++)
2037 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2043 /* Emit checking that MEM is aligned for an access in MODE, failing
2044 that, executing a "break 8" (or call to abort, if "break 8" is
2048 cris_emit_trap_for_misalignment (rtx mem
)
2050 rtx addr
, reg
, ok_label
, andop
;
2052 int natural_alignment
;
2053 gcc_assert (MEM_P (mem
));
2055 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2056 addr
= XEXP (mem
, 0);
2057 reg
= force_reg (Pmode
, addr
);
2058 ok_label
= gen_label_rtx ();
2060 /* This will yield a btstq without a separate register used, usually -
2061 with the exception for PRE hoisting the "and" but not the branch
2062 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2063 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2064 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2065 NULL_RTX
, Pmode
, 1, ok_label
);
2066 jmp
= get_last_insn ();
2067 gcc_assert (JUMP_P (jmp
));
2069 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2070 expand_builtin_trap ();
2071 emit_label (ok_label
);
2074 /* Expand a return insn (just one insn) marked as using SRP or stack
2075 slot depending on parameter ON_STACK. */
2078 cris_expand_return (bool on_stack
)
2080 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2081 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2082 GCC expect just (return) to do the right thing when optimizing, so
2083 we do that until they're fixed. Currently, all return insns in a
2084 function must be the same (not really a limiting factor) so we need
2085 to check that it doesn't change half-way through. */
2086 emit_jump_insn (ret_rtx
);
2088 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2089 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2091 cfun
->machine
->return_type
2092 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2095 /* Compute a (partial) cost for rtx X. Return true if the complete
2096 cost has been computed, and false if subexpressions should be
2097 scanned. In either case, *TOTAL contains the cost result. */
2100 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2107 HOST_WIDE_INT val
= INTVAL (x
);
2110 else if (val
< 32 && val
>= -32)
2112 /* Eight or 16 bits are a word and cycle more expensive. */
2113 else if (val
<= 32767 && val
>= -32768)
2115 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2116 another word. FIXME: This isn't linear to 16 bits. */
2132 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2135 /* Make 0.0 cheap, else test-insns will not be used. */
2140 /* If we have one arm of an ADDI, make sure it gets the cost of
2141 one insn, i.e. zero cost for this operand, and just the cost
2142 of the PLUS, as the insn is created by combine from a PLUS
2143 and an ASHIFT, and the MULT cost below would make the
2144 combined value be larger than the separate insns. The insn
2145 validity is checked elsewhere by combine.
2147 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2148 function should be rewritten. */
2149 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2155 /* Identify values that are no powers of two. Powers of 2 are
2156 taken care of already and those values should not be changed. */
2157 if (!CONST_INT_P (XEXP (x
, 1))
2158 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2160 /* If we have a multiply insn, then the cost is between
2161 1 and 2 "fast" instructions. */
2162 if (TARGET_HAS_MUL_INSNS
)
2164 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2168 /* Estimate as 4 + 4 * #ofbits. */
2169 *total
= COSTS_N_INSNS (132);
2178 if (!CONST_INT_P (XEXP (x
, 1))
2179 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2181 /* Estimate this as 4 + 8 * #of bits. */
2182 *total
= COSTS_N_INSNS (260);
2188 if (CONST_INT_P (XEXP (x
, 1))
2189 /* Two constants may actually happen before optimization. */
2190 && !CONST_INT_P (XEXP (x
, 0))
2191 && !satisfies_constraint_I (XEXP (x
, 1)))
2194 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2196 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2202 if (outer_code
!= COMPARE
)
2206 case ZERO_EXTEND
: case SIGN_EXTEND
:
2207 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2215 /* The ADDRESS_COST worker. */
2218 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2219 addr_space_t as ATTRIBUTE_UNUSED
,
2220 bool speed ATTRIBUTE_UNUSED
)
2222 /* The metric to use for the cost-macros is unclear.
2223 The metric used here is (the number of cycles needed) / 2,
2224 where we consider equal a cycle for a word of code and a cycle to
2225 read memory. FIXME: Adding "+ 1" to all values would avoid
2226 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2227 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2228 Unfortunately(?) such a hack would expose other pessimizations,
2229 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2230 loop there, without apparent reason. */
2232 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2233 if (cris_base_or_autoincr_p (x
, false))
2236 /* An indirect mem must be a DIP. This means two bytes extra for code,
2237 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2241 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2242 an extra DIP prefix and 4 bytes of constant in most cases. */
2246 /* Handle BIAP and BDAP prefixes. */
2247 if (GET_CODE (x
) == PLUS
)
2249 rtx tem1
= XEXP (x
, 0);
2250 rtx tem2
= XEXP (x
, 1);
2252 /* Local extended canonicalization rule: the first operand must
2253 be REG, unless it's an operation (MULT). */
2254 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2255 tem1
= tem2
, tem2
= XEXP (x
, 0);
2257 /* We'll "assume" we have canonical RTX now. */
2258 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2260 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2261 recognize the typical MULT which is always in tem1 because of
2262 insn canonicalization. */
2263 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2267 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2268 PLUS is always found in tem2. */
2269 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2272 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2274 if (satisfies_constraint_L (tem2
))
2277 /* A BDAP with some other constant is 2 bytes extra. */
2278 if (CRIS_CONSTANT_P (tem2
))
2279 return (2 + 2 + 2) / 2;
2281 /* BDAP with something indirect should have a higher cost than
2282 BIAP with register. FIXME: Should it cost like a MEM or more? */
2283 return (2 + 2 + 2) / 2;
2286 /* What else? Return a high cost. It matters only for valid
2287 addressing modes. */
2291 /* Check various objections to the side-effect. Used in the test-part
2292 of an anonymous insn describing an insn with a possible side-effect.
2293 Returns nonzero if the implied side-effect is ok.
2296 ops : An array of rtx:es. lreg, rreg, rval,
2297 The variables multop and other_op are indexes into this,
2298 or -1 if they are not applicable.
2299 lreg : The register that gets assigned in the side-effect.
2300 rreg : One register in the side-effect expression
2301 rval : The other register, or an int.
2302 multop : An integer to multiply rval with.
2303 other_op : One of the entities of the main effect,
2304 whose mode we must consider. */
2307 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2308 int lreg
, int rreg
, int rval
,
2309 int multop
, int other_op
)
2311 /* Find what value to multiply with, for rx =ry + rz * n. */
2312 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2314 rtx reg_rtx
= ops
[rreg
];
2315 rtx val_rtx
= ops
[rval
];
2317 /* The operands may be swapped. Canonicalize them in reg_rtx and
2318 val_rtx, where reg_rtx always is a reg (for this constraint to
2320 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2321 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2323 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2324 we have no business. */
2325 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2328 /* Don't do this when -mno-split. */
2329 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2332 /* The mult expression may be hidden in lreg. FIXME: Add more
2333 commentary about that. */
2334 if (GET_CODE (val_rtx
) == MULT
)
2336 mult
= INTVAL (XEXP (val_rtx
, 1));
2337 val_rtx
= XEXP (val_rtx
, 0);
2341 /* First check the "other operand". */
2344 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2347 /* Check if the lvalue register is the same as the "other
2348 operand". If so, the result is undefined and we shouldn't do
2349 this. FIXME: Check again. */
2350 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2351 && cris_base_p (ops
[other_op
],
2352 reload_in_progress
|| reload_completed
)
2353 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2354 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2358 /* Do not accept frame_pointer_rtx as any operand. */
2359 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2360 || ops
[rval
] == frame_pointer_rtx
2361 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2365 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2368 /* Do not allow rx = rx + n if a normal add or sub with same size
2370 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2371 && CONST_INT_P (val_rtx
)
2372 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2375 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2376 if (CRIS_CONSTANT_P (val_rtx
))
2380 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2381 reload_in_progress
|| reload_completed
))
2384 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2385 && MEM_P (XEXP (val_rtx
, 0))
2386 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2387 reload_in_progress
|| reload_completed
))
2390 /* If we got here, it's not a valid addressing mode. */
2393 else if (code
== MULT
2395 && cris_base_p (val_rtx
,
2396 reload_in_progress
|| reload_completed
)))
2398 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2399 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2400 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2403 /* Do not allow bad multiply-values. */
2404 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2407 /* Only allow r + ... */
2408 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2411 /* If we got here, all seems ok.
2412 (All checks need to be done above). */
2416 /* If we get here, the caller got its initial tests wrong. */
2417 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2420 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2421 insn for other reasons. */
2424 cris_cc0_user_requires_cmp (rtx insn
)
2426 rtx_insn
*cc0_user
= NULL
;
2430 gcc_assert (insn
!= NULL
);
2435 cc0_user
= next_cc0_user (insn
);
2436 if (cc0_user
== NULL
)
2439 body
= PATTERN (cc0_user
);
2440 set
= single_set (cc0_user
);
2442 /* Users can be sCC and bCC. */
2443 if (JUMP_P (cc0_user
)
2444 && GET_CODE (body
) == SET
2445 && SET_DEST (body
) == pc_rtx
2446 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2447 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2450 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2451 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2456 GET_CODE (SET_SRC (body
)) == GT
2457 || GET_CODE (SET_SRC (body
)) == LE
;
2463 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2464 does not handle the case where the IN operand is strict_low_part; it
2465 does handle it for X. Test-case in Axis-20010516. This function takes
2466 care of that for THIS port. FIXME: strict_low_part is going away
2470 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2472 /* The function reg_overlap_mentioned now handles when X is
2473 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2474 if (GET_CODE (in
) == STRICT_LOW_PART
)
2477 return reg_overlap_mentioned_p (x
, in
);
2480 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2481 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2485 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2487 gcc_assert (flag_pic
);
2489 switch (GET_CODE (x
))
2498 if (GET_CODE (x
) != CONST
)
2503 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2504 if (GET_CODE (x
) == PLUS
2505 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2506 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2507 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2508 && CONST_INT_P (XEXP (x
, 1)))
2511 if (GET_CODE (x
) == UNSPEC
)
2512 switch (XINT (x
, 1))
2514 /* A PCREL operand is only valid for call and movsi. */
2515 case CRIS_UNSPEC_PLT_PCREL
:
2516 case CRIS_UNSPEC_PCREL
:
2517 return !any_operand
;
2519 case CRIS_UNSPEC_PLT_GOTREL
:
2520 case CRIS_UNSPEC_PLTGOTREAD
:
2521 case CRIS_UNSPEC_GOTREAD
:
2522 case CRIS_UNSPEC_GOTREL
:
2528 return cris_symbol_type_of (x
) == cris_no_symbol
;
2531 /* Helper function to find the right symbol-type to generate,
2532 given the original (non-PIC) representation. */
2534 enum cris_symbol_type
2535 cris_symbol_type_of (const_rtx x
)
2537 switch (GET_CODE (x
))
2541 ? (SYMBOL_REF_LOCAL_P (x
)
2542 ? cris_rel_symbol
: cris_got_symbol
)
2543 : cris_offsettable_symbol
;
2546 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2549 return cris_symbol_type_of (XEXP (x
, 0));
2554 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2555 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2557 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2559 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2560 return cris_got_symbol_needing_fixup
;
2562 return t1
!= cris_no_symbol
? t1
: t2
;
2567 return cris_no_symbol
;
2573 fatal_insn ("unrecognized supposed constant", x
);
2579 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2582 cris_legitimate_pic_operand (rtx x
)
2584 /* Symbols are not valid PIC operands as-is; just constants. */
2585 return cris_valid_pic_const (x
, true);
2588 /* Queue an .ident string in the queue of top-level asm statements.
2589 If the front-end is done, we must be being called from toplev.c.
2590 In that case, do nothing. */
2592 cris_asm_output_ident (const char *string
)
2594 if (symtab
->state
!= PARSING
)
2597 default_asm_output_ident_directive (string
);
2600 /* The ASM_OUTPUT_CASE_END worker. */
2603 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2605 /* Step back, over the label for the table, to the actual casejump and
2606 assert that we find only what's expected. */
2607 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2608 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2609 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2610 gcc_assert (whole_jump_insn
!= NULL_RTX
2611 && (JUMP_P (whole_jump_insn
)
2612 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2613 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2614 /* Get the pattern of the casejump, so we can extract the default label. */
2615 whole_jump_insn
= PATTERN (whole_jump_insn
);
2619 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2620 filled. We also output the offset word a little differently. */
2622 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2623 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2625 asm_fprintf (stream
,
2626 "\t.word %LL%d-.%s\n",
2627 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2628 (parallel_jump
, 0, 0),
2630 (TARGET_PDEBUG
? "; default" : ""));
2634 asm_fprintf (stream
,
2635 "\t.word %LL%d-%LL%d%s\n",
2636 CODE_LABEL_NUMBER (XEXP
2638 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2641 (TARGET_PDEBUG
? "; default" : ""));
2644 /* The TARGET_OPTION_OVERRIDE worker.
2645 As is the norm, this also parses -mfoo=bar type parameters. */
2648 cris_option_override (void)
2650 if (cris_max_stackframe_str
)
2652 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2654 /* Do some sanity checking. */
2655 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2656 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2657 cris_max_stackframe
, 0x20000000);
2660 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2661 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2662 cris_cpu_version
= CRIS_CPU_SVINTO
;
2663 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2664 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2666 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2670 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2672 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2673 cris_cpu_version
= 3;
2675 if (strcmp ("svinto", cris_cpu_str
) == 0
2676 || strcmp ("etrax100", cris_cpu_str
) == 0)
2677 cris_cpu_version
= 8;
2679 if (strcmp ("ng", cris_cpu_str
) == 0
2680 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2681 cris_cpu_version
= 10;
2683 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2684 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2687 /* Set the target flags. */
2688 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2689 target_flags
|= MASK_ETRAX4_ADD
;
2691 /* If this is Svinto or higher, align for 32 bit accesses. */
2692 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2694 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2695 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2698 /* Note that we do not add new flags when it can be completely
2699 described with a macro that uses -mcpu=X. So
2700 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2706 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2708 if (strcmp ("etrax4", cris_tune_str
) == 0)
2711 if (strcmp ("svinto", cris_tune_str
) == 0
2712 || strcmp ("etrax100", cris_tune_str
) == 0)
2715 if (strcmp ("ng", cris_tune_str
) == 0
2716 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2719 if (cris_tune
< 0 || cris_tune
> 32)
2720 error ("unknown CRIS cpu version specification in -mtune= : %s",
2723 if (cris_tune
>= CRIS_CPU_SVINTO
)
2724 /* We have currently nothing more to tune than alignment for
2727 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2728 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2731 if (cris_cpu_version
>= CRIS_CPU_V32
)
2732 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2736 /* Use error rather than warning, so invalid use is easily
2737 detectable. Still change to the values we expect, to avoid
2741 error ("-fPIC and -fpic are not supported in this configuration");
2745 /* Turn off function CSE. We need to have the addresses reach the
2746 call expanders to get PLT-marked, as they could otherwise be
2747 compared against zero directly or indirectly. After visiting the
2748 call expanders they will then be cse:ed, as the call expanders
2749 force_reg the addresses, effectively forcing flag_no_function_cse
2751 flag_no_function_cse
= 1;
2754 /* Set the per-function-data initializer. */
2755 init_machine_status
= cris_init_machine_status
;
2758 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2761 cris_asm_output_mi_thunk (FILE *stream
,
2762 tree thunkdecl ATTRIBUTE_UNUSED
,
2763 HOST_WIDE_INT delta
,
2764 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2767 /* Make sure unwind info is emitted for the thunk if needed. */
2768 final_start_function (emit_barrier (), stream
, 1);
2771 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2772 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2773 reg_names
[CRIS_FIRST_ARG_REG
]);
2775 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2776 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2777 reg_names
[CRIS_FIRST_ARG_REG
]);
2781 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2783 name
= (* targetm
.strip_name_encoding
) (name
);
2787 fprintf (stream
, "\tba ");
2788 assemble_name (stream
, name
);
2789 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2793 fprintf (stream
, "add.d ");
2794 assemble_name (stream
, name
);
2795 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2800 fprintf (stream
, "jump ");
2801 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2802 fprintf (stream
, "\n");
2805 fprintf (stream
, "\tnop\n");
2808 final_end_function ();
2811 /* Boilerplate emitted at start of file.
2813 NO_APP *only at file start* means faster assembly. It also means
2814 comments are not allowed. In some cases comments will be output
2815 for debugging purposes. Make sure they are allowed then. */
2817 cris_file_start (void)
2819 /* These expressions can vary at run time, so we cannot put
2820 them into TARGET_INITIALIZER. */
2821 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2823 default_file_start ();
2826 /* Output that goes at the end of the file, similarly. */
2829 cris_file_end (void)
2831 /* For CRIS, the default is to assume *no* executable stack, so output
2832 an executable-stack-note only when needed. */
2833 if (TARGET_LINUX
&& trampolines_created
)
2834 file_end_indicate_exec_stack ();
2837 /* Rename the function calls for integer multiply and divide. */
2839 cris_init_libfuncs (void)
2841 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2842 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2843 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2844 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2845 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2847 /* Atomic data being unaligned is unfortunately a reality.
2849 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2851 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2852 "__cris_atcmpxchgr32");
2853 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2854 "__cris_atcmpxchgr16");
2858 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2862 cris_init_expanders (void)
2864 /* Nothing here at the moment. */
2867 /* Zero initialization is OK for all current fields. */
2869 static struct machine_function
*
2870 cris_init_machine_status (void)
2872 return ggc_cleared_alloc
<machine_function
> ();
2875 /* Split a 2 word move (DI or presumably DF) into component parts.
2876 Originally a copy of gen_split_move_double in m32r.c. */
2879 cris_split_movdx (rtx
*operands
)
2881 machine_mode mode
= GET_MODE (operands
[0]);
2882 rtx dest
= operands
[0];
2883 rtx src
= operands
[1];
2886 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2887 longer happen; after reload there are no SUBREGs any more, and we're
2888 only called after reload. */
2889 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2894 int dregno
= REGNO (dest
);
2896 /* Reg-to-reg copy. */
2899 int sregno
= REGNO (src
);
2901 int reverse
= (dregno
== sregno
+ 1);
2903 /* We normally copy the low-numbered register first. However, if
2904 the first register operand 0 is the same as the second register of
2905 operand 1, we must copy in the opposite order. */
2906 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
2907 operand_subword (src
, reverse
, TRUE
, mode
)));
2909 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
2910 operand_subword (src
, !reverse
, TRUE
, mode
)));
2912 /* Constant-to-reg copy. */
2913 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2916 split_double (src
, &words
[0], &words
[1]);
2917 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
2920 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
2923 /* Mem-to-reg copy. */
2924 else if (MEM_P (src
))
2926 /* If the high-address word is used in the address, we must load it
2927 last. Otherwise, load it first. */
2928 rtx addr
= XEXP (src
, 0);
2929 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2931 /* The original code implies that we can't do
2932 move.x [rN+],rM move.x [rN],rM+1
2933 when rN is dead, because of REG_NOTES damage. That is
2934 consistent with what I've seen, so don't try it.
2936 We have two different cases here; if the addr is POST_INC,
2937 just pass it through, otherwise add constants. */
2939 if (GET_CODE (addr
) == POST_INC
)
2944 /* Whenever we emit insns with post-incremented
2945 addresses ourselves, we must add a post-inc note
2947 mem
= change_address (src
, SImode
, addr
);
2949 = gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
), mem
);
2950 insn
= emit_insn (insn
);
2951 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2953 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2956 mem
= copy_rtx (mem
);
2958 = gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2959 insn
= emit_insn (insn
);
2960 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2962 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2967 /* Make sure we don't get any other addresses with
2968 embedded postincrements. They should be stopped in
2969 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2971 if (side_effects_p (addr
))
2972 fatal_insn ("unexpected side-effects in address", addr
);
2974 emit_insn (gen_rtx_SET
2975 (operand_subword (dest
, reverse
, TRUE
, mode
),
2978 plus_constant (Pmode
, addr
,
2979 reverse
* UNITS_PER_WORD
))));
2980 emit_insn (gen_rtx_SET
2981 (operand_subword (dest
, ! reverse
, TRUE
, mode
),
2984 plus_constant (Pmode
, addr
,
2990 internal_error ("unknown src");
2992 /* Reg-to-mem copy or clear mem. */
2993 else if (MEM_P (dest
)
2995 || src
== const0_rtx
2996 || src
== CONST0_RTX (DFmode
)))
2998 rtx addr
= XEXP (dest
, 0);
3000 if (GET_CODE (addr
) == POST_INC
)
3005 /* Whenever we emit insns with post-incremented addresses
3006 ourselves, we must add a post-inc note manually. */
3007 mem
= change_address (dest
, SImode
, addr
);
3009 = gen_rtx_SET (mem
, operand_subword (src
, 0, TRUE
, mode
));
3010 insn
= emit_insn (insn
);
3011 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3013 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3016 mem
= copy_rtx (mem
);
3017 insn
= gen_rtx_SET (mem
, operand_subword (src
, 1, TRUE
, mode
));
3018 insn
= emit_insn (insn
);
3019 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3021 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3026 /* Make sure we don't get any other addresses with embedded
3027 postincrements. They should be stopped in
3028 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3029 if (side_effects_p (addr
))
3030 fatal_insn ("unexpected side-effects in address", addr
);
3032 emit_insn (gen_rtx_SET
3033 (change_address (dest
, SImode
, addr
),
3034 operand_subword (src
, 0, TRUE
, mode
)));
3036 emit_insn (gen_rtx_SET
3037 (change_address (dest
, SImode
,
3038 plus_constant (Pmode
, addr
,
3040 operand_subword (src
, 1, TRUE
, mode
)));
3045 internal_error ("unknown dest");
3052 /* The expander for the prologue pattern name. */
3055 cris_expand_prologue (void)
3058 int size
= get_frame_size ();
3059 /* Shorten the used name for readability. */
3060 int cfoa_size
= crtl
->outgoing_args_size
;
3061 int last_movem_reg
= -1;
3064 int return_address_on_stack
= cris_return_address_on_stack ();
3065 int got_really_used
= false;
3066 int n_movem_regs
= 0;
3067 int pretend
= crtl
->args
.pretend_args_size
;
3069 /* Don't do anything if no prologues or epilogues are wanted. */
3070 if (!TARGET_PROLOGUE_EPILOGUE
)
3073 CRIS_ASSERT (size
>= 0);
3075 if (crtl
->uses_pic_offset_table
)
3077 /* A reference may have been optimized out (like the abort () in
3078 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3080 push_topmost_sequence ();
3082 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3083 pop_topmost_sequence ();
3086 /* Align the size to what's best for the CPU model. */
3087 if (TARGET_STACK_ALIGN
)
3088 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3092 /* See also cris_setup_incoming_varargs where
3093 cfun->machine->stdarg_regs is set. There are other setters of
3094 crtl->args.pretend_args_size than stdarg handling, like
3095 for an argument passed with parts in R13 and stack. We must
3096 not store R13 into the pretend-area for that case, as GCC does
3097 that itself. "Our" store would be marked as redundant and GCC
3098 will attempt to remove it, which will then be flagged as an
3099 internal error; trying to remove a frame-related insn. */
3100 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3102 framesize
+= pretend
;
3104 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3106 regno
--, pretend
-= 4, stdarg_regs
--)
3108 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3109 plus_constant (Pmode
,
3112 /* FIXME: When dwarf2 frame output and unless asynchronous
3113 exceptions, make dwarf2 bundle together all stack
3114 adjustments like it does for registers between stack
3116 RTX_FRAME_RELATED_P (insn
) = 1;
3118 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3119 set_mem_alias_set (mem
, get_varargs_alias_set ());
3120 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3122 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3123 the value isn't restored, so we don't want to tell dwarf2
3124 that it's been stored to stack, else EH handling info would
3128 /* For other setters of crtl->args.pretend_args_size, we
3129 just adjust the stack by leaving the remaining size in
3130 "pretend", handled below. */
3133 /* Save SRP if not a leaf function. */
3134 if (return_address_on_stack
)
3136 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3137 plus_constant (Pmode
, stack_pointer_rtx
,
3140 RTX_FRAME_RELATED_P (insn
) = 1;
3142 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3143 set_mem_alias_set (mem
, get_frame_alias_set ());
3144 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3145 RTX_FRAME_RELATED_P (insn
) = 1;
3149 /* Set up the frame pointer, if needed. */
3150 if (frame_pointer_needed
)
3152 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3153 plus_constant (Pmode
, stack_pointer_rtx
,
3156 RTX_FRAME_RELATED_P (insn
) = 1;
3158 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3159 set_mem_alias_set (mem
, get_frame_alias_set ());
3160 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3161 RTX_FRAME_RELATED_P (insn
) = 1;
3163 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3164 RTX_FRAME_RELATED_P (insn
) = 1;
3169 /* Between frame-pointer and saved registers lie the area for local
3170 variables. If we get here with "pretended" size remaining, count
3171 it into the general stack size. */
3174 /* Get a contiguous sequence of registers, starting with R0, that need
3176 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3178 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3182 /* Check if movem may be used for registers so far. */
3183 if (regno
== last_movem_reg
+ 1)
3184 /* Yes, update next expected register. */
3185 last_movem_reg
= regno
;
3188 /* We cannot use movem for all registers. We have to flush
3189 any movem:ed registers we got so far. */
3190 if (last_movem_reg
!= -1)
3193 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3195 /* It is a win to use a side-effect assignment for
3196 64 <= size <= 128. But side-effect on movem was
3197 not usable for CRIS v0..3. Also only do it if
3198 side-effects insns are allowed. */
3199 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3200 && (last_movem_reg
+ 1) * 4 + size
<= 128
3201 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3202 && TARGET_SIDE_EFFECT_PREFIXES
)
3205 = gen_rtx_MEM (SImode
,
3206 plus_constant (Pmode
, stack_pointer_rtx
,
3207 -(n_saved
* 4 + size
)));
3208 set_mem_alias_set (mem
, get_frame_alias_set ());
3210 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3211 -(n_saved
* 4 + size
),
3217 = gen_rtx_SET (stack_pointer_rtx
,
3218 plus_constant (Pmode
, stack_pointer_rtx
,
3219 -(n_saved
* 4 + size
)));
3220 insn
= emit_insn (insn
);
3221 RTX_FRAME_RELATED_P (insn
) = 1;
3223 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3224 set_mem_alias_set (mem
, get_frame_alias_set ());
3225 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3229 framesize
+= n_saved
* 4 + size
;
3230 last_movem_reg
= -1;
3234 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3235 plus_constant (Pmode
,
3238 RTX_FRAME_RELATED_P (insn
) = 1;
3240 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3241 set_mem_alias_set (mem
, get_frame_alias_set ());
3242 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
3243 RTX_FRAME_RELATED_P (insn
) = 1;
3245 framesize
+= 4 + size
;
3251 /* Check after, if we could movem all registers. This is the normal case. */
3252 if (last_movem_reg
!= -1)
3255 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3257 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3258 do it if side-effects insns are allowed. */
3259 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3260 && (last_movem_reg
+ 1) * 4 + size
<= 128
3261 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3262 && TARGET_SIDE_EFFECT_PREFIXES
)
3265 = gen_rtx_MEM (SImode
,
3266 plus_constant (Pmode
, stack_pointer_rtx
,
3267 -(n_saved
* 4 + size
)));
3268 set_mem_alias_set (mem
, get_frame_alias_set ());
3269 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3270 -(n_saved
* 4 + size
), true);
3275 = gen_rtx_SET (stack_pointer_rtx
,
3276 plus_constant (Pmode
, stack_pointer_rtx
,
3277 -(n_saved
* 4 + size
)));
3278 insn
= emit_insn (insn
);
3279 RTX_FRAME_RELATED_P (insn
) = 1;
3281 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3282 set_mem_alias_set (mem
, get_frame_alias_set ());
3283 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3286 framesize
+= n_saved
* 4 + size
;
3287 /* We have to put outgoing argument space after regs. */
3290 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3291 plus_constant (Pmode
,
3294 RTX_FRAME_RELATED_P (insn
) = 1;
3295 framesize
+= cfoa_size
;
3298 else if ((size
+ cfoa_size
) > 0)
3300 insn
= emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3301 plus_constant (Pmode
,
3303 -(cfoa_size
+ size
))));
3304 RTX_FRAME_RELATED_P (insn
) = 1;
3305 framesize
+= size
+ cfoa_size
;
3308 /* Set up the PIC register, if it is used. */
3309 if (got_really_used
)
3312 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3313 emit_move_insn (pic_offset_table_rtx
, got
);
3315 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3316 follow exceptional paths and tries to delete the GOT load as
3317 unused, if it isn't used on the non-exceptional paths. Other
3318 ports have similar or other cover-ups, or plain bugs marking
3319 the GOT register load as maybe-dead. To see this, remove the
3320 line below and try libsupc++/vec.cc or a trivial
3321 "static void y (); void x () {try {y ();} catch (...) {}}". */
3322 emit_use (pic_offset_table_rtx
);
3325 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3326 warning (0, "stackframe too big: %d bytes", framesize
);
3329 /* The expander for the epilogue pattern. */
3332 cris_expand_epilogue (void)
3335 int size
= get_frame_size ();
3336 int last_movem_reg
= -1;
3337 int argspace_offset
= crtl
->outgoing_args_size
;
3338 int pretend
= crtl
->args
.pretend_args_size
;
3340 bool return_address_on_stack
= cris_return_address_on_stack ();
3341 /* A reference may have been optimized out
3342 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3343 so check that it's still used. */
3344 int got_really_used
= false;
3345 int n_movem_regs
= 0;
3347 if (!TARGET_PROLOGUE_EPILOGUE
)
3350 if (crtl
->uses_pic_offset_table
)
3352 /* A reference may have been optimized out (like the abort () in
3353 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3355 push_topmost_sequence ();
3357 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3358 pop_topmost_sequence ();
3361 /* Align byte count of stack frame. */
3362 if (TARGET_STACK_ALIGN
)
3363 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3365 /* Check how many saved regs we can movem. They start at r0 and must
3368 regno
< FIRST_PSEUDO_REGISTER
;
3370 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3374 if (regno
== last_movem_reg
+ 1)
3375 last_movem_reg
= regno
;
3380 /* If there was only one register that really needed to be saved
3381 through movem, don't use movem. */
3382 if (n_movem_regs
== 1)
3383 last_movem_reg
= -1;
3385 /* Now emit "normal" move insns for all regs higher than the movem
3387 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3388 regno
> last_movem_reg
;
3390 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3394 if (argspace_offset
)
3396 /* There is an area for outgoing parameters located before
3397 the saved registers. We have to adjust for that. */
3398 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3399 plus_constant (Pmode
, stack_pointer_rtx
,
3401 /* Make sure we only do this once. */
3402 argspace_offset
= 0;
3405 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3406 stack_pointer_rtx
));
3407 set_mem_alias_set (mem
, get_frame_alias_set ());
3408 insn
= emit_move_insn (gen_raw_REG (SImode
, regno
), mem
);
3410 /* Whenever we emit insns with post-incremented addresses
3411 ourselves, we must add a post-inc note manually. */
3413 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3416 /* If we have any movem-restore, do it now. */
3417 if (last_movem_reg
!= -1)
3421 if (argspace_offset
)
3423 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3424 plus_constant (Pmode
, stack_pointer_rtx
,
3426 argspace_offset
= 0;
3429 mem
= gen_rtx_MEM (SImode
,
3430 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3431 set_mem_alias_set (mem
, get_frame_alias_set ());
3433 = emit_insn (cris_gen_movem_load (mem
,
3434 GEN_INT (last_movem_reg
+ 1), 0));
3435 /* Whenever we emit insns with post-incremented addresses
3436 ourselves, we must add a post-inc note manually. */
3437 if (side_effects_p (PATTERN (insn
)))
3439 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3442 /* If we don't clobber all of the allocated stack area (we've already
3443 deallocated saved registers), GCC might want to schedule loads from
3444 the stack to *after* the stack-pointer restore, which introduces an
3445 interrupt race condition. This happened for the initial-value
3446 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3447 other failure for that test). It also happened for the stack slot
3448 for the return value in (one version of)
3449 linux/fs/dcache.c:__d_lookup, at least with "-O2
3450 -fno-omit-frame-pointer". */
3452 /* Restore frame pointer if necessary. */
3453 if (frame_pointer_needed
)
3457 emit_insn (gen_cris_frame_deallocated_barrier ());
3459 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3460 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3461 stack_pointer_rtx
));
3462 set_mem_alias_set (mem
, get_frame_alias_set ());
3463 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3465 /* Whenever we emit insns with post-incremented addresses
3466 ourselves, we must add a post-inc note manually. */
3468 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3470 else if ((size
+ argspace_offset
) != 0)
3472 emit_insn (gen_cris_frame_deallocated_barrier ());
3474 /* If there was no frame-pointer to restore sp from, we must
3475 explicitly deallocate local variables. */
3477 /* Handle space for outgoing parameters that hasn't been handled
3479 size
+= argspace_offset
;
3481 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3482 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3485 /* If this function has no pushed register parameters
3486 (stdargs/varargs), and if it is not a leaf function, then we have
3487 the return address on the stack. */
3488 if (return_address_on_stack
&& pretend
== 0)
3490 if (TARGET_V32
|| crtl
->calls_eh_return
)
3494 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3495 mem
= gen_rtx_MEM (SImode
,
3496 gen_rtx_POST_INC (SImode
,
3497 stack_pointer_rtx
));
3498 set_mem_alias_set (mem
, get_frame_alias_set ());
3499 insn
= emit_move_insn (srpreg
, mem
);
3501 /* Whenever we emit insns with post-incremented addresses
3502 ourselves, we must add a post-inc note manually. */
3504 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3506 if (crtl
->calls_eh_return
)
3507 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3509 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3510 cris_expand_return (false);
3513 cris_expand_return (true);
3518 /* If we pushed some register parameters, then adjust the stack for
3522 /* If SRP is stored on the way, we need to restore it first. */
3523 if (return_address_on_stack
)
3526 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3529 mem
= gen_rtx_MEM (SImode
,
3530 gen_rtx_POST_INC (SImode
,
3531 stack_pointer_rtx
));
3532 set_mem_alias_set (mem
, get_frame_alias_set ());
3533 insn
= emit_move_insn (srpreg
, mem
);
3535 /* Whenever we emit insns with post-incremented addresses
3536 ourselves, we must add a post-inc note manually. */
3538 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3541 emit_insn (gen_rtx_SET (stack_pointer_rtx
,
3542 plus_constant (Pmode
, stack_pointer_rtx
,
3546 /* Perform the "physical" unwinding that the EH machinery calculated. */
3547 if (crtl
->calls_eh_return
)
3548 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3550 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3551 cris_expand_return (false);
3554 /* Worker function for generating movem from mem for load_multiple. */
3557 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3559 int nregs
= INTVAL (nregs_rtx
);
3563 rtx srcreg
= XEXP (src
, 0);
3564 unsigned int regno
= nregs
- 1;
3573 if (GET_CODE (srcreg
) == POST_INC
)
3574 srcreg
= XEXP (srcreg
, 0);
3576 CRIS_ASSERT (REG_P (srcreg
));
3578 /* Don't use movem for just one insn. The insns are equivalent except
3579 for the pipeline hazard (on v32); movem does not forward the loaded
3580 registers so there's a three cycles penalty for their use. */
3582 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3584 vec
= rtvec_alloc (nprefix
+ nregs
3585 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3587 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3589 RTVEC_ELT (vec
, nprefix
+ 1)
3590 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3594 src
= replace_equiv_address (src
, srcreg
);
3595 RTVEC_ELT (vec
, nprefix
)
3596 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3599 for (i
= 1; i
< nregs
; i
++, eltno
++)
3601 RTVEC_ELT (vec
, nprefix
+ eltno
)
3602 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3603 adjust_address_nv (src
, SImode
, i
* 4));
3607 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3610 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3611 are added that the dwarf2 machinery understands. */
3614 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3617 int nregs
= INTVAL (nregs_rtx
);
3622 rtx destreg
= XEXP (dest
, 0);
3623 unsigned int regno
= nregs
- 1;
3632 if (GET_CODE (destreg
) == POST_INC
)
3633 increment
+= nregs
* 4;
3635 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3636 destreg
= XEXP (destreg
, 0);
3638 CRIS_ASSERT (REG_P (destreg
));
3640 /* Don't use movem for just one insn. The insns are equivalent except
3641 for the pipeline hazard (on v32); movem does not forward the loaded
3642 registers so there's a three cycles penalty for use. */
3645 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3649 insn
= emit_insn (mov
);
3651 RTX_FRAME_RELATED_P (insn
) = 1;
3655 /* If there was a request for a side-effect, create the ordinary
3657 vec
= rtvec_alloc (2);
3659 RTVEC_ELT (vec
, 0) = mov
;
3660 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3664 RTX_FRAME_RELATED_P (mov
) = 1;
3665 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3670 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3672 = gen_rtx_SET (replace_equiv_address (dest
,
3673 plus_constant (Pmode
, destreg
,
3675 gen_rtx_REG (SImode
, regno
));
3678 /* The dwarf2 info wants this mark on each component in a parallel
3679 that's part of the prologue (though it's optional on the first
3682 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3687 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3689 ? increment
: nregs
* 4));
3693 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3695 /* Don't call adjust_address_nv on a post-incremented address if
3697 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3698 dest
= replace_equiv_address (dest
, destreg
);
3701 for (i
= 1; i
< nregs
; i
++, eltno
++)
3703 RTVEC_ELT (vec
, eltno
)
3704 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3705 gen_rtx_REG (SImode
, regno
));
3707 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3712 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3714 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3715 we need to keep the stack adjustment separate, after the
3716 MEM-setters. Else the stack-adjustment in the second component of
3717 the parallel would be mishandled; the offsets for the SETs that
3718 follow it would be wrong. We prepare for this by adding a
3719 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3720 followed by the increment. Note that we have FRAME_RELATED_P on
3721 all the SETs, including the original stack adjustment SET in the
3727 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3728 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3729 for (i
= 1; i
< nregs
; i
++)
3731 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3732 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3733 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3736 RTX_FRAME_RELATED_P (insn
) = 1;
3742 /* Worker function for expanding the address for PIC function calls. */
3745 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3749 gcc_assert (flag_pic
&& MEM_P (op
));
3752 /* It might be that code can be generated that jumps to 0 (or to a
3753 specific address). Don't die on that. (There is a
3755 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3757 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3759 CRIS_ASSERT (can_create_pseudo_p ());
3761 /* For local symbols (non-PLT), just get the plain symbol
3762 reference into a register. For symbols that can be PLT, make
3764 if (t
== cris_rel_symbol
)
3766 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3767 into a register caused performance regression for 3.2.1,
3768 observable in __floatdidf and elsewhere in libgcc. */
3771 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3772 HOST_WIDE_INT offs
= get_integer_term (op
);
3774 /* We can't get calls to sym+N, N integer, can we? */
3775 gcc_assert (offs
== 0);
3777 op
= gen_rtx_CONST (Pmode
,
3778 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3779 CRIS_UNSPEC_PCREL
));
3782 op
= force_reg (Pmode
, op
);
3785 *markerp
= const0_rtx
;
3787 else if (t
== cris_got_symbol
)
3789 if (TARGET_AVOID_GOTPLT
)
3791 /* Change a "jsr sym" into (allocate register rM, rO)
3792 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3793 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3794 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3798 crtl
->uses_pic_offset_table
= 1;
3799 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3801 ? CRIS_UNSPEC_PLT_PCREL
3802 : CRIS_UNSPEC_PLT_GOTREL
);
3803 tem
= gen_rtx_CONST (Pmode
, tem
);
3808 rm
= gen_reg_rtx (Pmode
);
3809 emit_move_insn (rm
, tem
);
3810 ro
= gen_reg_rtx (Pmode
);
3811 if (expand_binop (Pmode
, add_optab
, rm
,
3812 pic_offset_table_rtx
,
3813 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3814 internal_error ("expand_binop failed in movsi got");
3820 /* Change a "jsr sym" into (allocate register rM, rO)
3821 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3822 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3823 marked as not trapping and not aliasing. No "move.d
3824 [rO],rP" as that would invite to re-use of a value
3825 that should not be reused. FIXME: Need a peephole2
3826 for cases when this is cse:d from the call, to change
3827 back to just get the PLT entry address, so we don't
3828 resolve the same symbol over and over (the memory
3829 access of the PLTGOT isn't constant). */
3830 rtx tem
, mem
, rm
, ro
;
3832 gcc_assert (can_create_pseudo_p ());
3833 crtl
->uses_pic_offset_table
= 1;
3834 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3835 CRIS_UNSPEC_PLTGOTREAD
);
3836 rm
= gen_reg_rtx (Pmode
);
3837 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3838 ro
= gen_reg_rtx (Pmode
);
3839 if (expand_binop (Pmode
, add_optab
, rm
,
3840 pic_offset_table_rtx
,
3841 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3842 internal_error ("expand_binop failed in movsi got");
3843 mem
= gen_rtx_MEM (Pmode
, ro
);
3845 /* This MEM doesn't alias anything. Whether it aliases
3846 other same symbols is unimportant. */
3847 set_mem_alias_set (mem
, new_alias_set ());
3848 MEM_NOTRAP_P (mem
) = 1;
3852 /* We need to prepare this call to go through the PLT; we
3853 need to make GOT available. */
3854 *markerp
= pic_offset_table_rtx
;
3857 /* Can't possibly get anything else for a function-call, right? */
3858 fatal_insn ("unidentifiable call op", op
);
3860 /* If the validizing variant is called, it will try to validize
3861 the address as a valid any-operand constant, but as it's only
3862 valid for calls and moves, it will fail and always be forced
3864 *opp
= replace_equiv_address_nv (*opp
, op
);
3867 /* Can't tell what locality a call to a non-constant address has;
3868 better make the GOT register alive at it.
3869 FIXME: Can we see whether the register has known constant
3871 *markerp
= pic_offset_table_rtx
;
3874 /* Make sure operands are in the right order for an addsi3 insn as
3875 generated by a define_split. Nothing but REG_P as the first
3876 operand is recognized by addsi3 after reload. OPERANDS contains
3877 the operands, with the first at OPERANDS[N] and the second at
3881 cris_order_for_addsi3 (rtx
*operands
, int n
)
3883 if (!REG_P (operands
[n
]))
3885 rtx tem
= operands
[n
];
3886 operands
[n
] = operands
[n
+ 1];
3887 operands
[n
+ 1] = tem
;
3891 /* Use from within code, from e.g. PRINT_OPERAND and
3892 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3893 different things depending on whether code operand or constant is
3897 cris_output_addr_const (FILE *file
, rtx x
)
3900 output_addr_const (file
, x
);
3904 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3907 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3909 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3911 if (flag_pic
&& in_code
> 0)
3913 const char *origstr
= XSTR (x
, 0);
3915 str
= (* targetm
.strip_name_encoding
) (origstr
);
3916 assemble_name (file
, str
);
3919 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3920 output_operand_lossage ("PIC register isn't set up");
3923 assemble_name (file
, XSTR (x
, 0));
3926 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3929 cris_asm_output_label_ref (FILE *file
, char *buf
)
3931 if (flag_pic
&& in_code
> 0)
3933 assemble_name (file
, buf
);
3936 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3937 internal_error ("emitting PIC operand, but PIC register "
3941 assemble_name (file
, buf
);
3944 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3947 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3949 switch (GET_CODE (xconst
))
3954 x
= XVECEXP (xconst
, 0, 0);
3955 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3956 || GET_CODE (x
) == LABEL_REF
3957 || GET_CODE (x
) == CONST
);
3958 output_addr_const (file
, x
);
3959 switch (XINT (xconst
, 1))
3961 case CRIS_UNSPEC_PCREL
:
3962 /* We only get this with -fpic/PIC to tell it apart from an
3963 invalid symbol. We can't tell here, but it should only
3964 be the operand of a call or movsi. */
3965 gcc_assert (TARGET_V32
&& flag_pic
);
3968 case CRIS_UNSPEC_PLT_PCREL
:
3969 gcc_assert (TARGET_V32
);
3970 fprintf (file
, ":PLT");
3973 case CRIS_UNSPEC_PLT_GOTREL
:
3974 gcc_assert (!TARGET_V32
);
3975 fprintf (file
, ":PLTG");
3978 case CRIS_UNSPEC_GOTREL
:
3979 gcc_assert (!TARGET_V32
);
3980 fprintf (file
, ":GOTOFF");
3983 case CRIS_UNSPEC_GOTREAD
:
3985 fprintf (file
, ":GOT16");
3987 fprintf (file
, ":GOT");
3990 case CRIS_UNSPEC_PLTGOTREAD
:
3992 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3994 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
4007 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4010 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4011 int incoming ATTRIBUTE_UNUSED
)
4013 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
4016 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4019 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4020 machine_mode mode ATTRIBUTE_UNUSED
,
4021 tree type ATTRIBUTE_UNUSED
,
4022 int *pretend_arg_size
,
4025 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4027 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4029 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4030 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4031 *pretend_arg_size
= stdarg_regs
* 4;
4035 fprintf (asm_out_file
,
4036 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4037 ca
->regs
, *pretend_arg_size
, second_time
);
4040 /* Return true if TYPE must be passed by invisible reference.
4041 For cris, we pass <= 8 bytes by value, others by reference. */
4044 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4045 machine_mode mode
, const_tree type
,
4046 bool named ATTRIBUTE_UNUSED
)
4048 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4049 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4052 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4053 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4054 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4057 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4059 int *punsignedp ATTRIBUTE_UNUSED
,
4060 const_tree fntype ATTRIBUTE_UNUSED
,
4063 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4064 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4065 Maybe pointless as of now, but let's keep the old behavior. */
4066 if (for_return
== 1)
4068 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4071 /* Atomic types require alignment to be at least their "natural" size. */
4074 cris_atomic_align_for_mode (machine_mode mode
)
4076 return GET_MODE_BITSIZE (mode
);
4079 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4083 cris_function_value(const_tree type
,
4084 const_tree func ATTRIBUTE_UNUSED
,
4085 bool outgoing ATTRIBUTE_UNUSED
)
4087 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4090 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4094 cris_libcall_value (machine_mode mode
,
4095 const_rtx fun ATTRIBUTE_UNUSED
)
4097 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4100 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4104 cris_function_value_regno_p (const unsigned int regno
)
4106 return (regno
== CRIS_FIRST_ARG_REG
);
4110 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4111 tree type
, bool named ATTRIBUTE_UNUSED
)
4113 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4114 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4115 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4116 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4117 return UNITS_PER_WORD
;
4123 cris_function_arg_1 (cumulative_args_t ca_v
,
4124 machine_mode mode ATTRIBUTE_UNUSED
,
4125 const_tree type ATTRIBUTE_UNUSED
,
4126 bool named
, bool incoming
)
4128 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4130 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4131 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4136 /* Worker function for TARGET_FUNCTION_ARG.
4137 The void_type_node is sent as a "closing" call. */
4140 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4141 const_tree type
, bool named
)
4143 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4146 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4148 The differences between this and the previous, is that this one checks
4149 that an argument is named, since incoming stdarg/varargs arguments are
4150 pushed onto the stack, and we don't have to check against the "closing"
4151 void_type_node TYPE parameter. */
4154 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4155 const_tree type
, bool named
)
4157 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4160 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4163 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4164 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4166 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4168 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4171 /* Worker function for TARGET_MD_ASM_ADJUST. */
4174 cris_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> &inputs
,
4175 vec
<const char *> &constraints
,
4176 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
4178 /* For the time being, all asms clobber condition codes.
4179 Revisit when there's a reasonable use for inputs/outputs
4180 that mention condition codes. */
4181 clobbers
.safe_push (gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
4182 SET_HARD_REG_BIT (clobbered_regs
, CRIS_CC0_REGNUM
);
4184 /* Determine if the source using MOF. If it is, automatically
4185 clobbering MOF would cause it to have impossible constraints. */
4187 /* Look for a use of the MOF constraint letter: h. */
4188 for (unsigned i
= 0, n
= constraints
.length(); i
< n
; ++i
)
4189 if (strchr (constraints
[i
], 'h') != NULL
)
4192 /* Look for an output or an input that touches MOF. */
4193 rtx mof_reg
= gen_rtx_REG (SImode
, CRIS_MOF_REGNUM
);
4194 for (unsigned i
= 0, n
= outputs
.length(); i
< n
; ++i
)
4195 if (reg_overlap_mentioned_p (mof_reg
, outputs
[i
]))
4197 for (unsigned i
= 0, n
= inputs
.length(); i
< n
; ++i
)
4198 if (reg_overlap_mentioned_p (mof_reg
, inputs
[i
]))
4201 /* No direct reference to MOF or its constraint.
4202 Clobber it for backward compatibility. */
4203 clobbers
.safe_push (mof_reg
);
4204 SET_HARD_REG_BIT (clobbered_regs
, CRIS_MOF_REGNUM
);
4208 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4210 Really only needed if the stack frame has variable length (alloca
4211 or variable sized local arguments (GNU C extension). See PR39499 and
4212 PR38609 for the reason this isn't just 0. */
4215 cris_frame_pointer_required (void)
4217 return !crtl
->sp_is_unchanging
;
4220 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4222 This looks too complicated, and it is. I assigned r7 to be the
4223 static chain register, but it is call-saved, so we have to save it,
4224 and come back to restore it after the call, so we have to save srp...
4225 Anyway, trampolines are rare enough that we can cope with this
4226 somewhat lack of elegance.
4227 (Do not be tempted to "straighten up" whitespace in the asms; the
4228 assembler #NO_APP state mandates strict spacing). */
4229 /* ??? See the i386 regparm=3 implementation that pushes the static
4230 chain value to the stack in the trampoline, and uses a call-saved
4231 register when called directly. */
4234 cris_asm_trampoline_template (FILE *f
)
4238 /* This normally-unused nop insn acts as an instruction to
4239 the simulator to flush its instruction cache. None of
4240 the other instructions in the trampoline template suits
4241 as a trigger for V32. The pc-relative addressing mode
4242 works nicely as a trigger for V10.
4243 FIXME: Have specific V32 template (possibly avoiding the
4244 use of a special instruction). */
4245 fprintf (f
, "\tclearf x\n");
4246 /* We have to use a register as an intermediate, choosing
4247 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4248 so we can use it for address indirection and jsr target. */
4249 fprintf (f
, "\tmove $r1,$mof\n");
4251 fprintf (f
, "\tmove.d 0,$r1\n");
4252 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4253 fprintf (f
, "\taddq 6,$r1\n");
4254 fprintf (f
, "\tmove $mof,[$r1]\n");
4255 fprintf (f
, "\taddq 6,$r1\n");
4256 fprintf (f
, "\tmove $srp,[$r1]\n");
4258 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4260 fprintf (f
, "\tmove.d 0,$r1\n");
4261 fprintf (f
, "\tjsr $r1\n");
4262 fprintf (f
, "\tsetf\n");
4264 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4266 fprintf (f
, "\tmove.d 0,$r1\n");
4268 fprintf (f
, "\tmove.d 0,$r9\n");
4269 fprintf (f
, "\tjump $r9\n");
4270 fprintf (f
, "\tsetf\n");
4274 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4275 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4276 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4277 fprintf (f
, "\tjsr 0\n");
4278 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4279 fprintf (f
, "\tjump 0\n");
4283 /* Implement TARGET_TRAMPOLINE_INIT. */
4286 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4288 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4289 rtx tramp
= XEXP (m_tramp
, 0);
4292 emit_block_move (m_tramp
, assemble_trampoline_template (),
4293 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4297 mem
= adjust_address (m_tramp
, SImode
, 6);
4298 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4299 mem
= adjust_address (m_tramp
, SImode
, 22);
4300 emit_move_insn (mem
, chain_value
);
4301 mem
= adjust_address (m_tramp
, SImode
, 28);
4302 emit_move_insn (mem
, fnaddr
);
4306 mem
= adjust_address (m_tramp
, SImode
, 10);
4307 emit_move_insn (mem
, chain_value
);
4308 mem
= adjust_address (m_tramp
, SImode
, 16);
4309 emit_move_insn (mem
, fnaddr
);
4312 /* Note that there is no need to do anything with the cache for
4313 sake of a trampoline. */
4318 /* Various small functions to replace macros. Only called from a
4319 debugger. They might collide with gcc functions or system functions,
4320 so only emit them when '#if 1' above. */
4322 enum rtx_code
Get_code (rtx
);
4327 return GET_CODE (x
);
4330 const char *Get_mode (rtx
);
4335 return GET_MODE_NAME (GET_MODE (x
));
4338 rtx
Xexp (rtx
, int);
4346 rtx
Xvecexp (rtx
, int, int);
4349 Xvecexp (rtx x
, int n
, int m
)
4351 return XVECEXP (x
, n
, m
);
4354 int Get_rtx_len (rtx
);
4359 return GET_RTX_LENGTH (GET_CODE (x
));
4362 /* Use upper-case to distinguish from local variables that are sometimes
4363 called next_insn and prev_insn. */
4365 rtx
Next_insn (rtx
);
4368 Next_insn (rtx insn
)
4370 return NEXT_INSN (insn
);
4373 rtx
Prev_insn (rtx
);
4376 Prev_insn (rtx insn
)
4378 return PREV_INSN (insn
);
4382 #include "gt-cris.h"
4386 * eval: (c-set-style "gnu")
4387 * indent-tabs-mode: t