| blob | d4101cb4acdda1865e1adffbaa51b1e1efd7c3ce |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
55 #ifndef CHECK_STACK_LIMIT
56 #define CHECK_STACK_LIMIT (-1)
57 #endif
59 /* Return index of given mode in mult and division cost tables. */
60 #define MODE_INDEX(mode) \
61 ((mode) == QImode ? 0 \
62 : (mode) == HImode ? 1 \
63 : (mode) == SImode ? 2 \
64 : (mode) == DImode ? 3 \
65 : 4)
67 /* Processor costs (relative to an add) */
68 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
69 #define COSTS_N_BYTES(N) ((N) * 2)
71 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
73 static const
96 in QImode, HImode and SImode.
97 Relative to reg-reg move (2). */
101 in SFmode, DFmode and XFmode */
103 in SFmode, DFmode and XFmode */
106 in SImode and DImode */
108 in SImode and DImode */
111 in SImode, DImode and TImode */
113 in SImode, DImode and TImode */
128 };
130 /* Processor costs (relative to an add) */
131 static const
154 in QImode, HImode and SImode.
155 Relative to reg-reg move (2). */
159 in SFmode, DFmode and XFmode */
161 in SFmode, DFmode and XFmode */
164 in SImode and DImode */
166 in SImode and DImode */
169 in SImode, DImode and TImode */
171 in SImode, DImode and TImode */
183 DUMMY_STRINGOP_ALGS},
185 DUMMY_STRINGOP_ALGS},
186 };
188 static const
211 in QImode, HImode and SImode.
212 Relative to reg-reg move (2). */
216 in SFmode, DFmode and XFmode */
218 in SFmode, DFmode and XFmode */
221 in SImode and DImode */
223 in SImode and DImode */
226 in SImode, DImode and TImode */
228 in SImode, DImode and TImode */
240 DUMMY_STRINGOP_ALGS},
242 DUMMY_STRINGOP_ALGS}
243 };
245 static const
268 in QImode, HImode and SImode.
269 Relative to reg-reg move (2). */
273 in SFmode, DFmode and XFmode */
275 in SFmode, DFmode and XFmode */
278 in SImode and DImode */
280 in SImode and DImode */
283 in SImode, DImode and TImode */
285 in SImode, DImode and TImode */
297 DUMMY_STRINGOP_ALGS},
299 DUMMY_STRINGOP_ALGS}
300 };
302 static const
325 in QImode, HImode and SImode.
326 Relative to reg-reg move (2). */
330 in SFmode, DFmode and XFmode */
332 in SFmode, DFmode and XFmode */
335 in SImode and DImode */
337 in SImode and DImode */
340 in SImode, DImode and TImode */
342 in SImode, DImode and TImode */
353 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
354 the alignment). For small blocks inline loop is still a noticeable win, for bigger
355 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
356 more expensive startup time in CPU, but after 4K the difference is down in the noise.
357 */
360 DUMMY_STRINGOP_ALGS},
363 DUMMY_STRINGOP_ALGS}
364 };
366 static const
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
394 in SFmode, DFmode and XFmode */
396 in SFmode, DFmode and XFmode */
400 in SImode and DImode */
402 in SImode and DImode */
405 in SImode, DImode and TImode */
407 in SImode, DImode and TImode */
419 DUMMY_STRINGOP_ALGS},
421 DUMMY_STRINGOP_ALGS}
422 };
424 static const
447 in QImode, HImode and SImode.
448 Relative to reg-reg move (2). */
452 in SFmode, DFmode and XFmode */
454 in SFmode, DFmode and XFmode */
457 in SImode and DImode */
459 in SImode and DImode */
462 in SImode, DImode and TImode */
464 in SImode, DImode and TImode */
476 DUMMY_STRINGOP_ALGS},
478 DUMMY_STRINGOP_ALGS}
479 };
481 static const
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
509 in SFmode, DFmode and XFmode */
511 in SFmode, DFmode and XFmode */
514 in SImode and DImode */
516 in SImode and DImode */
519 in SImode, DImode and TImode */
521 in SImode, DImode and TImode */
532 /* For some reason, Athlon deals better with REP prefix (relative to loops)
533 compared to K8. Alignment becomes important after 8 bytes for memcpy and
534 128 bytes for memset. */
536 DUMMY_STRINGOP_ALGS},
538 DUMMY_STRINGOP_ALGS}
539 };
541 static const
564 in QImode, HImode and SImode.
565 Relative to reg-reg move (2). */
569 in SFmode, DFmode and XFmode */
571 in SFmode, DFmode and XFmode */
574 in SImode and DImode */
576 in SImode and DImode */
579 in SImode, DImode and TImode */
581 in SImode, DImode and TImode */
584 /* New AMD processors never drop prefetches; if they cannot be performed
585 immediately, they are queued. We set number of simultaneous prefetches
586 to a large constant to reflect this (it probably is not a good idea not
587 to limit number of prefetches at all, as their execution also takes some
588 time). */
597 /* K8 has optimized REP instruction for medium sized blocks, but for very small
598 blocks it is better to use loop. For large blocks, libcall can do
599 nontemporary accesses and beat inline considerably. */
605 };
629 in QImode, HImode and SImode.
630 Relative to reg-reg move (2). */
634 in SFmode, DFmode and XFmode */
636 in SFmode, DFmode and XFmode */
639 in SImode and DImode */
641 in SImode and DImode */
644 in SImode, DImode and TImode */
646 in SImode, DImode and TImode */
648 /* On K8
649 MOVD reg64, xmmreg Double FSTORE 4
650 MOVD reg32, xmmreg Double FSTORE 4
651 On AMDFAM10
652 MOVD reg64, xmmreg Double FADD 3
653 1/1 1/1
654 MOVD reg32, xmmreg Double FADD 3
655 1/1 1/1 */
657 /* New AMD processors never drop prefetches; if they cannot be performed
658 immediately, they are queued. We set number of simultaneous prefetches
659 to a large constant to reflect this (it probably is not a good idea not
660 to limit number of prefetches at all, as their execution also takes some
661 time). */
671 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
672 very small blocks it is better to use loop. For large blocks, libcall can
673 do nontemporary accesses and beat inline considerably. */
679 };
681 static const
704 in QImode, HImode and SImode.
705 Relative to reg-reg move (2). */
709 in SFmode, DFmode and XFmode */
711 in SFmode, DFmode and XFmode */
714 in SImode and DImode */
716 in SImode and DImode */
719 in SImode, DImode and TImode */
721 in SImode, DImode and TImode */
733 DUMMY_STRINGOP_ALGS},
736 DUMMY_STRINGOP_ALGS},
737 };
739 static const
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
767 in SFmode, DFmode and XFmode */
769 in SFmode, DFmode and XFmode */
772 in SImode and DImode */
774 in SImode and DImode */
777 in SImode, DImode and TImode */
779 in SImode, DImode and TImode */
797 };
799 static const
822 in QImode, HImode and SImode.
823 Relative to reg-reg move (2). */
827 in SFmode, DFmode and XFmode */
831 in SImode and DImode */
833 in SImode and DImode */
836 in SImode, DImode and TImode */
838 in SImode, DImode and TImode */
856 };
858 /* Generic64 should produce code tuned for Nocona and K8. */
859 static const
862 /* On all chips taken into consideration lea is 2 cycles and more. With
863 this cost however our current implementation of synth_mult results in
864 use of unnecessary temporary registers causing regression on several
865 SPECfp benchmarks. */
886 in QImode, HImode and SImode.
887 Relative to reg-reg move (2). */
891 in SFmode, DFmode and XFmode */
893 in SFmode, DFmode and XFmode */
896 in SImode and DImode */
898 in SImode and DImode */
901 in SImode, DImode and TImode */
903 in SImode, DImode and TImode */
907 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
908 is increased to perhaps more appropriate value of 5. */
920 };
922 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
923 static const
946 in QImode, HImode and SImode.
947 Relative to reg-reg move (2). */
951 in SFmode, DFmode and XFmode */
953 in SFmode, DFmode and XFmode */
956 in SImode and DImode */
958 in SImode and DImode */
961 in SImode, DImode and TImode */
963 in SImode, DImode and TImode */
975 DUMMY_STRINGOP_ALGS},
977 DUMMY_STRINGOP_ALGS},
978 };
982 /* Processor feature/optimization bitmasks. */
983 #define m_386 (1<<PROCESSOR_I386)
984 #define m_486 (1<<PROCESSOR_I486)
985 #define m_PENT (1<<PROCESSOR_PENTIUM)
986 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
987 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
988 #define m_NOCONA (1<<PROCESSOR_NOCONA)
989 #define m_CORE2 (1<<PROCESSOR_CORE2)
991 #define m_GEODE (1<<PROCESSOR_GEODE)
992 #define m_K6 (1<<PROCESSOR_K6)
993 #define m_K6_GEODE (m_K6 | m_GEODE)
994 #define m_K8 (1<<PROCESSOR_K8)
995 #define m_ATHLON (1<<PROCESSOR_ATHLON)
996 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
997 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
998 #define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
1000 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1001 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1003 /* Generic instruction choice should be common subset of supported CPUs
1004 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1005 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1007 /* Feature tests against the various tunings. */
1009 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1010 negatively, so enabling for Generic64 seems like good code size
1011 tradeoff. We can't enable it for 32bit generic because it does not
1012 work well with PPro base chips. */
1015 /* X86_TUNE_PUSH_MEMORY */
1019 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1022 /* X86_TUNE_USE_BIT_TEST */
1023 m_386,
1025 /* X86_TUNE_UNROLL_STRLEN */
1028 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1032 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1033 on simulation result. But after P4 was made, no performance benefit
1034 was observed with branch hints. It also increases the code size.
1035 As a result, icc never generates branch hints. */
1038 /* X86_TUNE_DOUBLE_WITH_ADD */
1041 /* X86_TUNE_USE_SAHF */
1045 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1046 partial dependencies. */
1050 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1051 register stalls on Generic32 compilation setting as well. However
1052 in current implementation the partial register stalls are not eliminated
1053 very well - they can be introduced via subregs synthesized by combine
1054 and can happen in caller/callee saving sequences. Because this option
1055 pays back little on PPro based chips and is in conflict with partial reg
1056 dependencies used by Athlon/P4 based chips, it is better to leave it off
1057 for generic32 for now. */
1058 m_PPRO,
1060 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1063 /* X86_TUNE_USE_HIMODE_FIOP */
1066 /* X86_TUNE_USE_SIMODE_FIOP */
1069 /* X86_TUNE_USE_MOV0 */
1070 m_K6,
1072 /* X86_TUNE_USE_CLTD */
1075 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1076 m_PENT4,
1078 /* X86_TUNE_SPLIT_LONG_MOVES */
1079 m_PPRO,
1081 /* X86_TUNE_READ_MODIFY_WRITE */
1084 /* X86_TUNE_READ_MODIFY */
1087 /* X86_TUNE_PROMOTE_QIMODE */
1091 /* X86_TUNE_FAST_PREFIX */
1094 /* X86_TUNE_SINGLE_STRINGOP */
1097 /* X86_TUNE_QIMODE_MATH */
1100 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1101 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1102 might be considered for Generic32 if our scheme for avoiding partial
1103 stalls was more effective. */
1106 /* X86_TUNE_PROMOTE_QI_REGS */
1109 /* X86_TUNE_PROMOTE_HI_REGS */
1110 m_PPRO,
1112 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1115 /* X86_TUNE_ADD_ESP_8 */
1119 /* X86_TUNE_SUB_ESP_4 */
1122 /* X86_TUNE_SUB_ESP_8 */
1126 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1127 for DFmode copies */
1131 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1134 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1135 conflict here in between PPro/Pentium4 based chips that thread 128bit
1136 SSE registers as single units versus K8 based chips that divide SSE
1137 registers to two 64bit halves. This knob promotes all store destinations
1138 to be 128bit to allow register renaming on 128bit SSE units, but usually
1139 results in one extra microop on 64bit SSE units. Experimental results
1140 shows that disabling this option on P4 brings over 20% SPECfp regression,
1141 while enabling it on K8 brings roughly 2.4% regression that can be partly
1142 masked by careful scheduling of moves. */
1145 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1146 m_AMDFAM10,
1148 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1149 are resolved on SSE register parts instead of whole registers, so we may
1150 maintain just lower part of scalar values in proper format leaving the
1151 upper part undefined. */
1152 m_ATHLON_K8,
1154 /* X86_TUNE_SSE_TYPELESS_STORES */
1155 m_ATHLON_K8_AMDFAM10,
1157 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1160 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1163 /* X86_TUNE_PROLOGUE_USING_MOVE */
1166 /* X86_TUNE_EPILOGUE_USING_MOVE */
1169 /* X86_TUNE_SHIFT1 */
1172 /* X86_TUNE_USE_FFREEP */
1173 m_ATHLON_K8_AMDFAM10,
1175 /* X86_TUNE_INTER_UNIT_MOVES */
1178 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1179 than 4 branch instructions in the 16 byte window. */
1182 /* X86_TUNE_SCHEDULE */
1185 /* X86_TUNE_USE_BT */
1186 m_ATHLON_K8_AMDFAM10,
1188 /* X86_TUNE_USE_INCDEC */
1191 /* X86_TUNE_PAD_RETURNS */
1194 /* X86_TUNE_EXT_80387_CONSTANTS */
1197 /* X86_TUNE_SHORTEN_X87_SSE */
1200 /* X86_TUNE_AVOID_VECTOR_DECODE */
1203 /* X86_TUNE_SLOW_IMUL_IMM32_MEM (imul of 32-bit constant and memory is vector
1204 path on AMD machines) */
1207 /* X86_TUNE_SLOW_IMUL_IMM8 (imul of 8-bit constant is vector path on AMD
1208 machines) */
1211 /* X86_TUNE_MOVE_M1_VIA_OR (on pentiums, it is faster to load -1 via OR than
1212 a MOV) */
1213 m_PENT,
1215 /* X86_TUNE_NOT_UNPAIRABLE (NOT is not pairable on Pentium, while XOR is, but
1216 one byte longer). */
1217 m_PENT,
1219 /* X86_TUNE_NOT_VECTORMODE (On AMD K6, NOT is vector decoded with memory
1220 operand that cannot be represented using a modRM byte. The XOR
1221 replacement is long decoded, so this split helps here as well). */
1222 m_K6,
1223 };
1225 /* Feature tests against the various architecture variations. */
1227 /* X86_ARCH_CMOVE */
1230 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1233 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1236 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1239 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1241 };
1243 static const unsigned int x86_accumulate_outgoing_args
1246 static const unsigned int x86_arch_always_fancy_math_387
1252 /* In case the average insn count for single function invocation is
1253 lower than this constant, emit fast (but longer) prologue and
1254 epilogue code. */
1255 #define FAST_PROLOGUE_INSN_COUNT 20
1257 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1262 /* Array of the smallest class containing reg number REGNO, indexed by
1263 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1266 {
1267 /* ax, dx, cx, bx */
1269 /* si, di, bp, sp */
1271 /* FP registers */
1274 /* arg pointer */
1275 NON_Q_REGS,
1276 /* flags, fpsr, fpcr, frame */
1286 };
1288 /* The "default" register map used in 32bit mode. */
1291 {
1299 };
1302 {
1305 };
1308 {
1310 };
1312 /* The "default" register map used in 64bit mode. */
1314 {
1322 };
1324 /* Define the register numbers to be used in Dwarf debugging information.
1325 The SVR4 reference port C compiler uses the following register numbers
1326 in its Dwarf output code:
1327 0 for %eax (gcc regno = 0)
1328 1 for %ecx (gcc regno = 2)
1329 2 for %edx (gcc regno = 1)
1330 3 for %ebx (gcc regno = 3)
1331 4 for %esp (gcc regno = 7)
1332 5 for %ebp (gcc regno = 6)
1333 6 for %esi (gcc regno = 4)
1334 7 for %edi (gcc regno = 5)
1335 The following three DWARF register numbers are never generated by
1336 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1337 believes these numbers have these meanings.
1338 8 for %eip (no gcc equivalent)
1339 9 for %eflags (gcc regno = 17)
1340 10 for %trapno (no gcc equivalent)
1341 It is not at all clear how we should number the FP stack registers
1342 for the x86 architecture. If the version of SDB on x86/svr4 were
1343 a bit less brain dead with respect to floating-point then we would
1344 have a precedent to follow with respect to DWARF register numbers
1345 for x86 FP registers, but the SDB on x86/svr4 is so completely
1346 broken with respect to FP registers that it is hardly worth thinking
1347 of it as something to strive for compatibility with.
1348 The version of x86/svr4 SDB I have at the moment does (partially)
1349 seem to believe that DWARF register number 11 is associated with
1350 the x86 register %st(0), but that's about all. Higher DWARF
1351 register numbers don't seem to be associated with anything in
1352 particular, and even for DWARF regno 11, SDB only seems to under-
1353 stand that it should say that a variable lives in %st(0) (when
1354 asked via an `=' command) if we said it was in DWARF regno 11,
1355 but SDB still prints garbage when asked for the value of the
1356 variable in question (via a `/' command).
1357 (Also note that the labels SDB prints for various FP stack regs
1358 when doing an `x' command are all wrong.)
1359 Note that these problems generally don't affect the native SVR4
1360 C compiler because it doesn't allow the use of -O with -g and
1361 because when it is *not* optimizing, it allocates a memory
1362 location for each floating-point variable, and the memory
1363 location is what gets described in the DWARF AT_location
1364 attribute for the variable in question.
1365 Regardless of the severe mental illness of the x86/svr4 SDB, we
1366 do something sensible here and we use the following DWARF
1367 register numbers. Note that these are all stack-top-relative
1368 numbers.
1369 11 for %st(0) (gcc regno = 8)
1370 12 for %st(1) (gcc regno = 9)
1371 13 for %st(2) (gcc regno = 10)
1372 14 for %st(3) (gcc regno = 11)
1373 15 for %st(4) (gcc regno = 12)
1374 16 for %st(5) (gcc regno = 13)
1375 17 for %st(6) (gcc regno = 14)
1376 18 for %st(7) (gcc regno = 15)
1377 */
1379 {
1387 };
1389 /* Test and compare insns in i386.md store the information needed to
1390 generate branch and scc insns here. */
1396 /* Size of the register save area. */
1397 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1399 /* Define the structure for the machine field in struct function. */
1402 {
1405 rtx rtl;
1407 };
1409 /* Structure describing stack frame layout.
1410 Stack grows downward:
1412 [arguments]
1413 <- ARG_POINTER
1414 saved pc
1416 saved frame pointer if frame_pointer_needed
1417 <- HARD_FRAME_POINTER
1418 [saved regs]
1420 [padding1] \
1421 )
1422 [va_arg registers] (
1423 > to_allocate <- FRAME_POINTER
1424 [frame] (
1425 )
1426 [padding2] /
1427 */
1428 struct ix86_frame
1429 {
1433 HOST_WIDE_INT frame;
1438 HOST_WIDE_INT to_allocate;
1439 /* The offsets relative to ARG_POINTER. */
1440 HOST_WIDE_INT frame_pointer_offset;
1441 HOST_WIDE_INT hard_frame_pointer_offset;
1442 HOST_WIDE_INT stack_pointer_offset;
1444 /* When save_regs_using_mov is set, emit prologue using
1445 move instead of push instructions. */
1447 };
1449 /* Code model option. */
1451 /* Asm dialect. */
1453 /* TLS dialects. */
1456 /* Which unit we are generating floating point math for. */
1459 /* Which cpu are we scheduling for. */
1462 /* Which instruction set architecture to use. */
1465 /* true if sse prefetch instruction is not NOOP. */
1468 /* ix86_regparm_string as a number */
1471 /* -mstackrealign option */
1475 /* Preferred alignment for stack boundary in bits. */
1478 /* Values 1-5: see jump.c */
1481 /* Variables which are this size or smaller are put in the data/bss
1482 or ldata/lbss sections. */
1486 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1489 \f
1498 rtx *);
1588 /* This function is only used on Solaris. */
1590 ATTRIBUTE_UNUSED;
1592 /* Register class used for passing given 64bit part of the argument.
1593 These represent classes as documented by the PS ABI, with the exception
1594 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1595 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1597 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1598 whenever possible (upper half does contain padding).
1599 */
1600 enum x86_64_reg_class
1601 {
1602 X86_64_NO_CLASS,
1603 X86_64_INTEGER_CLASS,
1604 X86_64_INTEGERSI_CLASS,
1605 X86_64_SSE_CLASS,
1606 X86_64_SSESF_CLASS,
1607 X86_64_SSEDF_CLASS,
1608 X86_64_SSEUP_CLASS,
1609 X86_64_X87_CLASS,
1610 X86_64_X87UP_CLASS,
1611 X86_64_COMPLEX_X87_CLASS,
1612 X86_64_MEMORY_CLASS
1613 };
1617 };
1619 #define MAX_CLASSES 4
1621 /* Table of constants used by fldpi, fldln2, etc.... */
1630 ATTRIBUTE_UNUSED;
1631 \f
1632 /* Initialize the GCC target structure. */
1633 #undef TARGET_ATTRIBUTE_TABLE
1634 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
1635 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1636 # undef TARGET_MERGE_DECL_ATTRIBUTES
1637 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
1638 #endif
1640 #undef TARGET_COMP_TYPE_ATTRIBUTES
1641 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
1643 #undef TARGET_INIT_BUILTINS
1644 #define TARGET_INIT_BUILTINS ix86_init_builtins
1645 #undef TARGET_EXPAND_BUILTIN
1646 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
1648 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1649 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION ix86_builtin_vectorized_function
1650 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1651 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_builtin_conversion
1653 #undef TARGET_ASM_FUNCTION_EPILOGUE
1654 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
1656 #undef TARGET_ENCODE_SECTION_INFO
1657 #ifndef SUBTARGET_ENCODE_SECTION_INFO
1658 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
1659 #else
1660 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
1661 #endif
1663 #undef TARGET_ASM_OPEN_PAREN
1665 #undef TARGET_ASM_CLOSE_PAREN
1668 #undef TARGET_ASM_ALIGNED_HI_OP
1669 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
1670 #undef TARGET_ASM_ALIGNED_SI_OP
1671 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1672 #ifdef ASM_QUAD
1673 #undef TARGET_ASM_ALIGNED_DI_OP
1674 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1675 #endif
1677 #undef TARGET_ASM_UNALIGNED_HI_OP
1678 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1679 #undef TARGET_ASM_UNALIGNED_SI_OP
1680 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1681 #undef TARGET_ASM_UNALIGNED_DI_OP
1682 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1684 #undef TARGET_SCHED_ADJUST_COST
1685 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1686 #undef TARGET_SCHED_ISSUE_RATE
1687 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1688 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1689 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1690 ia32_multipass_dfa_lookahead
1692 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1693 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1695 #ifdef HAVE_AS_TLS
1696 #undef TARGET_HAVE_TLS
1697 #define TARGET_HAVE_TLS true
1698 #endif
1699 #undef TARGET_CANNOT_FORCE_CONST_MEM
1700 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1701 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1702 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
1704 #undef TARGET_DELEGITIMIZE_ADDRESS
1705 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1707 #undef TARGET_MS_BITFIELD_LAYOUT_P
1708 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1710 #if TARGET_MACHO
1711 #undef TARGET_BINDS_LOCAL_P
1712 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1713 #endif
1715 #undef TARGET_ASM_OUTPUT_MI_THUNK
1716 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1717 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1718 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1720 #undef TARGET_ASM_FILE_START
1721 #define TARGET_ASM_FILE_START x86_file_start
1723 #undef TARGET_DEFAULT_TARGET_FLAGS
1724 #define TARGET_DEFAULT_TARGET_FLAGS \
1725 (TARGET_DEFAULT \
1726 | TARGET_64BIT_DEFAULT \
1727 | TARGET_SUBTARGET_DEFAULT \
1728 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1730 #undef TARGET_HANDLE_OPTION
1731 #define TARGET_HANDLE_OPTION ix86_handle_option
1733 #undef TARGET_RTX_COSTS
1734 #define TARGET_RTX_COSTS ix86_rtx_costs
1735 #undef TARGET_ADDRESS_COST
1736 #define TARGET_ADDRESS_COST ix86_address_cost
1738 #undef TARGET_FIXED_CONDITION_CODE_REGS
1739 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1740 #undef TARGET_CC_MODES_COMPATIBLE
1741 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1743 #undef TARGET_MACHINE_DEPENDENT_REORG
1744 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1746 #undef TARGET_BUILD_BUILTIN_VA_LIST
1747 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1749 #undef TARGET_MD_ASM_CLOBBERS
1750 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1752 #undef TARGET_PROMOTE_PROTOTYPES
1753 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1754 #undef TARGET_STRUCT_VALUE_RTX
1755 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1758 #undef TARGET_MUST_PASS_IN_STACK
1759 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1760 #undef TARGET_PASS_BY_REFERENCE
1761 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1762 #undef TARGET_INTERNAL_ARG_POINTER
1763 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
1764 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1765 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
1767 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1768 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1770 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1771 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
1773 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1774 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1776 #ifdef HAVE_AS_TLS
1777 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1778 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1779 #endif
1781 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1782 #undef TARGET_INSERT_ATTRIBUTES
1783 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1784 #endif
1786 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1787 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1789 #undef TARGET_STACK_PROTECT_FAIL
1790 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1792 #undef TARGET_FUNCTION_VALUE
1793 #define TARGET_FUNCTION_VALUE ix86_function_value
1797 \f
1798 /* The svr4 ABI for the i386 says that records and unions are returned
1799 in memory. */
1800 #ifndef DEFAULT_PCC_STRUCT_RETURN
1801 #define DEFAULT_PCC_STRUCT_RETURN 1
1802 #endif
1804 /* Implement TARGET_HANDLE_OPTION. */
1806 static bool
1808 {
1810 {
1813 {
1816 }
1821 {
1824 }
1829 {
1832 }
1837 {
1840 }
1845 {
1848 }
1853 }
1854 }
1856 /* Sometimes certain combinations of command options do not make
1857 sense on a particular target machine. You can define a macro
1858 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1859 defined, is executed once just after all the command options have
1860 been parsed.
1862 Don't use this macro to turn on various extra optimizations for
1863 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1865 void
1867 {
1872 /* Comes from final.c -- no real reason to change it. */
1873 #define MAX_CODE_ALIGN 16
1875 static struct ptt
1876 {
1885 }
1887 {
1902 };
1905 static struct pta
1906 {
1909 const enum pta_flags
1910 {
1926 }
1928 {
1987 };
1991 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1992 SUBTARGET_OVERRIDE_OPTIONS;
1993 #endif
1995 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1996 SUBSUBTARGET_OVERRIDE_OPTIONS;
1997 #endif
1999 /* -fPIC is the default for x86_64. */
2003 /* Set the default values for switches whose default depends on TARGET_64BIT
2004 in case they weren't overwritten by command line options. */
2006 {
2007 /* Mach-O doesn't support omitting the frame pointer for now. */
2014 }
2015 else
2016 {
2023 }
2025 /* Need to check -mtune=generic first. */
2027 {
2030 /* As special support for cross compilers we read -mtune=native
2031 as -mtune=generic. With native compilers we won't see the
2032 -mtune=native, as it was changed by the driver. */
2034 {
2037 else
2039 }
2042 }
2043 else
2044 {
2048 {
2051 }
2053 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2054 need to use a sensible tune option. */
2058 {
2061 else
2063 }
2064 }
2066 {
2081 else
2083 }
2096 {
2109 else
2111 }
2112 else
2113 {
2117 }
2119 {
2125 else
2127 }
2137 {
2139 /* Default cpu tuning to the architecture. */
2181 }
2192 {
2195 {
2197 {
2204 }
2205 else
2208 }
2209 /* Intel CPUs have always interpreted SSE prefetch instructions as
2210 NOPs; so, we can enable SSE prefetch instructions even when
2211 -mtune (rather than -march) points us to a processor that has them.
2212 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2213 higher processors. */
2217 }
2227 else
2232 /* Arrange to set up i386_stack_locals for all functions. */
2235 /* Validate -mregparm= value. */
2237 {
2241 else
2243 }
2244 else
2248 /* If the user has provided any of the -malign-* options,
2249 warn and use that value only if -falign-* is not set.
2250 Remove this code in GCC 3.2 or later. */
2252 {
2255 {
2259 else
2261 }
2262 }
2265 {
2268 {
2272 else
2274 }
2275 }
2278 {
2281 {
2285 else
2287 }
2288 }
2290 /* Default align_* from the processor table. */
2292 {
2295 }
2297 {
2300 }
2302 {
2304 }
2306 /* Validate -mbranch-cost= value, or provide default. */
2309 {
2313 else
2315 }
2317 {
2321 else
2323 }
2326 {
2333 else
2335 ix86_tls_dialect_string);
2336 }
2338 /* Keep nonleaf frame pointers. */
2344 /* If we're doing fast math, we don't care about comparison order
2345 wrt NaNs. This lets us use a shorter comparison sequence. */
2349 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2350 since the insns won't need emulation. */
2354 /* Likewise, if the target doesn't have a 387, or we've specified
2355 software floating point, don't use 387 inline intrinsics. */
2359 /* Turn on SSE3 builtins for -mssse3. */
2363 /* Turn on SSE3 builtins for -msse4a. */
2367 /* Turn on SSE2 builtins for -msse3. */
2371 /* Turn on SSE builtins for -msse2. */
2375 /* Turn on MMX builtins for -msse. */
2377 {
2380 }
2382 /* Turn on MMX builtins for 3Dnow. */
2386 /* Turn on POPCNT builtins for -mabm. */
2391 {
2397 /* Enable by default the SSE and MMX builtins. Do allow the user to
2398 explicitly disable any of these. In particular, disabling SSE and
2399 MMX for kernel code is extremely useful. */
2400 target_flags
2403 }
2404 else
2405 {
2406 /* i386 ABI does not specify red zone. It still makes sense to use it
2407 when programmer takes care to stack from being destroyed. */
2410 }
2412 /* Validate -mpreferred-stack-boundary= value, or provide default.
2413 The default of 128 bits is for Pentium III's SSE __m128. We can't
2414 change it because of optimize_size. Otherwise, we can't mix object
2415 files compiled with -Os and -On. */
2418 {
2423 else
2425 }
2427 /* Accept -msseregparm only if at least SSE support is enabled. */
2434 {
2438 {
2440 {
2443 }
2444 else
2446 }
2449 {
2451 {
2454 }
2456 {
2459 }
2460 else
2462 }
2463 else
2465 }
2467 /* If the i387 is disabled, then do not return values in it. */
2476 /* ??? Unwind info is not correct around the CFG unless either a frame
2477 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2478 unwind info generation to be aware of the CFG and propagating states
2479 around edges. */
2482 && flag_omit_frame_pointer
2484 {
2489 }
2491 /* For sane SSE instruction set generation we need fcomi instruction.
2492 It is safe to enable all CMOVE instructions. */
2496 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2497 {
2503 }
2505 /* When scheduling description is not available, disable scheduler pass
2506 so it won't slow down the compilation and make x87 code slower. */
2515 }
2516 \f
2517 /* switch to the appropriate section for output of DECL.
2518 DECL is either a `VAR_DECL' node or a constant of some sort.
2519 RELOC indicates whether forming the initial value of DECL requires
2520 link-time relocations. */
2525 {
2528 {
2532 {
2566 /* We don't split these for medium model. Place them into
2567 default sections and hope for best. */
2569 }
2571 {
2572 /* We might get called with string constants, but get_named_section
2573 doesn't like them as they are not DECLs. Also, we need to set
2574 flags in that case. */
2578 }
2579 }
2581 }
2583 /* Build up a unique section name, expressed as a
2584 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2585 RELOC indicates whether the initial value of EXP requires
2586 link-time relocations. */
2588 static void
2590 {
2593 {
2595 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2599 {
2623 /* We don't split these for medium model. Place them into
2624 default sections and hope for best. */
2626 }
2628 {
2644 }
2645 }
2647 }
2649 #ifdef COMMON_ASM_OP
2650 /* This says how to output assembler code to declare an
2651 uninitialized external linkage data object.
2653 For medium model x86-64 we need to use .largecomm opcode for
2654 large objects. */
2655 void
2659 {
2663 else
2668 }
2669 #endif
2670 /* Utility function for targets to use in implementing
2671 ASM_OUTPUT_ALIGNED_BSS. */
2673 void
2677 {
2681 else
2684 #ifdef ASM_DECLARE_OBJECT_NAME
2687 #else
2688 /* Standard thing is just output label for the object. */
2692 }
2693 \f
2694 void
2696 {
2697 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2698 make the problem with not enough registers even worse. */
2699 #ifdef INSN_SCHEDULING
2702 #endif
2705 /* The Darwin libraries never set errno, so we might as well
2706 avoid calling them when that's the only reason we would. */
2709 /* The default values of these switches depend on the TARGET_64BIT
2710 that is not known at this moment. Mark these values with 2 and
2711 let user the to override these. In case there is no command line option
2712 specifying them, we will set the defaults in override_options. */
2717 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2718 SUBTARGET_OPTIMIZATION_OPTIONS;
2719 #endif
2720 }
2721 \f
2722 /* Table of valid machine attributes. */
2724 {
2725 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2726 /* Stdcall attribute says callee is responsible for popping arguments
2727 if they are not variable. */
2729 /* Fastcall attribute says callee is responsible for popping arguments
2730 if they are not variable. */
2732 /* Cdecl attribute says the callee is a normal C declaration */
2734 /* Regparm attribute specifies how many integer arguments are to be
2735 passed in registers. */
2737 /* Sseregparm attribute says we are using x86_64 calling conventions
2738 for FP arguments. */
2740 /* force_align_arg_pointer says this function realigns the stack at entry. */
2743 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2747 #endif
2750 #ifdef SUBTARGET_ATTRIBUTE_TABLE
2751 SUBTARGET_ATTRIBUTE_TABLE,
2752 #endif
2754 };
2756 /* Decide whether we can make a sibling call to a function. DECL is the
2757 declaration of the function being targeted by the call and EXP is the
2758 CALL_EXPR representing the call. */
2760 static bool
2762 {
2763 tree func;
2766 /* If we are generating position-independent code, we cannot sibcall
2767 optimize any indirect call, or a direct call to a global function,
2768 as the PLT requires %ebx be live. */
2774 else
2775 {
2779 }
2781 /* Check that the return value locations are the same. Like
2782 if we are returning floats on the 80387 register stack, we cannot
2783 make a sibcall from a function that doesn't return a float to a
2784 function that does or, conversely, from a function that does return
2785 a float to a function that doesn't; the necessary stack adjustment
2786 would not be executed. This is also the place we notice
2787 differences in the return value ABI. Note that it is ok for one
2788 of the functions to have void return type as long as the return
2789 value of the other is passed in a register. */
2794 {
2797 }
2799 ;
2803 /* If this call is indirect, we'll need to be able to use a call-clobbered
2804 register for the address of the target function. Make sure that all
2805 such registers are not used for passing parameters. */
2807 {
2808 tree type;
2810 /* We're looking at the CALL_EXPR, we need the type of the function. */
2816 {
2817 /* ??? Need to count the actual number of registers to be used,
2818 not the possible number of registers. Fix later. */
2820 }
2821 }
2823 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2824 /* Dllimport'd functions are also called indirectly. */
2828 #endif
2830 /* If we forced aligned the stack, then sibcalling would unalign the
2831 stack, which may break the called function. */
2835 /* Otherwise okay. That also includes certain types of indirect calls. */
2837 }
2839 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2840 calling convention attributes;
2841 arguments as in struct attribute_spec.handler. */
2843 static tree
2845 tree args,
2848 {
2853 {
2858 }
2860 /* Can combine regparm with all attributes but fastcall. */
2862 {
2863 tree cst;
2866 {
2868 }
2872 {
2877 }
2879 {
2883 }
2889 {
2892 }
2895 }
2898 {
2903 }
2905 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2907 {
2909 {
2911 }
2913 {
2915 }
2917 {
2919 }
2920 }
2922 /* Can combine stdcall with fastcall (redundant), regparm and
2923 sseregparm. */
2925 {
2927 {
2929 }
2931 {
2933 }
2934 }
2936 /* Can combine cdecl with regparm and sseregparm. */
2938 {
2940 {
2942 }
2944 {
2946 }
2947 }
2949 /* Can combine sseregparm with all attributes. */
2952 }
2954 /* Return 0 if the attributes for two types are incompatible, 1 if they
2955 are compatible, and 2 if they are nearly compatible (which causes a
2956 warning to be generated). */
2958 static int
2960 {
2961 /* Check for mismatch of non-default calling convention. */
2967 /* Check for mismatched fastcall/regparm types. */
2974 /* Check for mismatched sseregparm types. */
2979 /* Check for mismatched return types (cdecl vs stdcall). */
2985 }
2986 \f
2987 /* Return the regparm value for a function with the indicated TYPE and DECL.
2988 DECL may be NULL when calling function indirectly
2989 or considering a libcall. */
2991 static int
2993 {
2994 tree attr;
2999 {
3002 {
3005 }
3008 {
3011 }
3013 /* Use register calling convention for local functions when possible. */
3016 {
3019 {
3022 /* Make sure no regparm register is taken by a global register
3023 variable. */
3027 /* We can't use regparm(3) for nested functions as these use
3028 static chain pointer in third argument. */
3033 /* If the function realigns its stackpointer, the
3034 prologue will clobber %ecx. If we've already
3035 generated code for the callee, the callee
3036 DECL_STRUCT_FUNCTION is gone, so we fall back to
3037 scanning the attributes for the self-realigning
3038 property. */
3045 /* Each global register variable increases register preassure,
3046 so the more global reg vars there are, the smaller regparm
3047 optimization use, unless requested by the user explicitly. */
3050 globals++;
3051 local_regparm
3056 }
3057 }
3058 }
3060 }
3062 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3063 DFmode (2) arguments in SSE registers for a function with the
3064 indicated TYPE and DECL. DECL may be NULL when calling function
3065 indirectly or considering a libcall. Otherwise return 0. */
3067 static int
3069 {
3070 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3071 by the sseregparm attribute. */
3073 || (type
3075 {
3077 {
3081 else
3085 }
3088 }
3090 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3091 (and DFmode for SSE2) arguments in SSE registers,
3092 even for 32-bit targets. */
3095 {
3099 }
3102 }
3104 /* Return true if EAX is live at the start of the function. Used by
3105 ix86_expand_prologue to determine if we need special help before
3106 calling allocate_stack_worker. */
3108 static bool
3110 {
3111 /* Cheat. Don't bother working forward from ix86_function_regparm
3112 to the function type to whether an actual argument is located in
3113 eax. Instead just look at cfg info, which is still close enough
3114 to correct at this point. This gives false positives for broken
3115 functions that might use uninitialized data that happens to be
3116 allocated in eax, but who cares? */
3118 }
3120 /* Value is the number of bytes of arguments automatically
3121 popped when returning from a subroutine call.
3122 FUNDECL is the declaration node of the function (as a tree),
3123 FUNTYPE is the data type of the function (as a tree),
3124 or for a library call it is an identifier node for the subroutine name.
3125 SIZE is the number of bytes of arguments passed on the stack.
3127 On the 80386, the RTD insn may be used to pop them if the number
3128 of args is fixed, but if the number is variable then the caller
3129 must pop them all. RTD can't be used for library calls now
3130 because the library is compiled with the Unix compiler.
3131 Use of RTD is a selectable option, since it is incompatible with
3132 standard Unix calling sequences. If the option is not selected,
3133 the caller must always pop the args.
3135 The attribute stdcall is equivalent to RTD on a per module basis. */
3137 int
3139 {
3142 /* Cdecl functions override -mrtd, and never pop the stack. */
3145 /* Stdcall and fastcall functions will pop the stack if not
3146 variable args. */
3156 }
3158 /* Lose any fake structure return argument if it is passed on the stack. */
3160 && !TARGET_64BIT
3162 {
3167 }
3170 }
3171 \f
3172 /* Argument support functions. */
3174 /* Return true when register may be used to pass function parameters. */
3175 bool
3177 {
3180 {
3184 else
3190 }
3193 {
3196 }
3197 else
3198 {
3202 }
3203 /* RAX is used as hidden argument to va_arg functions. */
3210 }
3212 /* Return if we do not know how to pass TYPE solely in registers. */
3214 static bool
3216 {
3220 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3221 The layout_type routine is crafty and tries to trick us into passing
3222 currently unsupported vector types on the stack by using TImode. */
3225 }
3227 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3228 for a call to a function whose data type is FNTYPE.
3229 For a library call, FNTYPE is 0. */
3231 void
3235 tree fndecl)
3236 {
3241 {
3247 else
3252 }
3256 /* Set up the number of registers to use for passing arguments. */
3266 /* Use ecx and edx registers if function has fastcall attribute,
3267 else look for regparm information. */
3269 {
3271 {
3274 }
3275 else
3277 }
3279 /* Set up the number of SSE registers used for passing SFmode
3280 and DFmode arguments. Warn for mismatching ABI. */
3283 /* Determine if this function has variable arguments. This is
3284 indicated by the last argument being 'void_type_mode' if there
3285 are no variable arguments. If there are variable arguments, then
3286 we won't pass anything in registers in 32-bit mode. */
3289 {
3292 {
3295 {
3297 {
3305 }
3307 }
3308 }
3309 }
3318 }
3320 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3321 But in the case of vector types, it is some vector mode.
3323 When we have only some of our vector isa extensions enabled, then there
3324 are some modes for which vector_mode_supported_p is false. For these
3325 modes, the generic vector support in gcc will choose some non-vector mode
3326 in order to implement the type. By computing the natural mode, we'll
3327 select the proper ABI location for the operand and not depend on whatever
3328 the middle-end decides to do with these vector types. */
3330 static enum machine_mode
3332 {
3336 {
3339 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3341 {
3346 else
3349 /* Get the mode which has this inner mode and number of units. */
3356 }
3357 }
3360 }
3362 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3363 this may not agree with the mode that the type system has chosen for the
3364 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3365 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3367 static rtx
3370 {
3371 rtx tmp;
3375 else
3376 {
3380 }
3383 }
3385 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3386 of this code is to classify each 8bytes of incoming argument by the register
3387 class and assign registers accordingly. */
3389 /* Return the union class of CLASS1 and CLASS2.
3390 See the x86-64 PS ABI for details. */
3392 static enum x86_64_reg_class
3394 {
3395 /* Rule #1: If both classes are equal, this is the resulting class. */
3399 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3400 the other class. */
3406 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3410 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3418 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3419 MEMORY is used. */
3428 /* Rule #6: Otherwise class SSE is used. */
3430 }
3432 /* Classify the argument of type TYPE and mode MODE.
3433 CLASSES will be filled by the register class used to pass each word
3434 of the operand. The number of words is returned. In case the parameter
3435 should be passed in memory, 0 is returned. As a special case for zero
3436 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3438 BIT_OFFSET is used internally for handling records and specifies offset
3439 of the offset in bits modulo 256 to avoid overflow cases.
3441 See the x86-64 PS ABI for details.
3442 */
3444 static int
3447 {
3448 HOST_WIDE_INT bytes =
3452 /* Variable sized entities are always passed/returned in memory. */
3461 {
3463 tree field;
3466 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3473 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3474 signalize memory class, so handle it as special case. */
3476 {
3479 }
3481 /* Classify each field of record and merge classes. */
3483 {
3485 /* And now merge the fields of structure. */
3487 {
3489 {
3495 /* Bitfields are always classified as integer. Handle them
3496 early, since later code would consider them to be
3497 misaligned integers. */
3499 {
3507 }
3508 else
3509 {
3517 {
3522 }
3523 }
3524 }
3525 }
3529 /* Arrays are handled as small records. */
3530 {
3537 /* The partial classes are now full classes. */
3547 }
3550 /* Unions are similar to RECORD_TYPE but offset is always 0.
3551 */
3553 {
3555 {
3563 bit_offset);
3568 }
3569 }
3574 }
3576 /* Final merger cleanup. */
3578 {
3579 /* If one class is MEMORY, everything should be passed in
3580 memory. */
3584 /* The X86_64_SSEUP_CLASS should be always preceded by
3585 X86_64_SSE_CLASS. */
3590 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3594 }
3596 }
3598 /* Compute alignment needed. We align all types to natural boundaries with
3599 exception of XFmode that is aligned to 64bits. */
3601 {
3610 /* Misaligned fields are always returned in memory. */
3613 }
3615 /* for V1xx modes, just use the base mode */
3620 /* Classification of atomic types. */
3622 {
3640 else
3652 else
3677 /* This modes is larger than 16 bytes. */
3707 else
3711 }
3712 }
3714 /* Examine the argument and return set number of register required in each
3715 class. Return 0 iff parameter should be passed in memory. */
3716 static int
3719 {
3729 {
3751 }
3753 }
3755 /* Construct container for the argument used by GCC interface. See
3756 FUNCTION_ARG for the detailed description. */
3758 static rtx
3762 {
3763 /* The following variables hold the static issued_error state. */
3777 rtx ret;
3781 {
3784 else
3785 {
3788 {
3790 }
3792 }
3793 }
3802 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3803 some less clueful developer tries to use floating-point anyway. */
3805 {
3807 {
3809 {
3812 }
3813 }
3815 {
3818 }
3820 }
3822 /* Likewise, error if the ABI requires us to return values in the
3823 x87 registers and the user specified -mno-80387. */
3829 {
3831 {
3834 }
3836 }
3838 /* First construct simple cases. Avoid SCmode, since we want to use
3839 single register to pass this type. */
3842 {
3854 /* Zero sized array, struct or class. */
3858 }
3871 /* Otherwise figure out the entries of the PARALLEL. */
3873 {
3875 {
3880 /* Merge TImodes on aligned occasions here too. */
3885 else
3887 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3893 intreg++;
3900 sse_regno++;
3907 sse_regno++;
3912 else
3919 i++;
3920 sse_regno++;
3924 }
3925 }
3927 /* Empty aligned struct, union or class. */
3935 }
3937 /* Update the data in CUM to advance over an argument
3938 of mode MODE and data type TYPE.
3939 (TYPE is null for libcalls where that information may not be available.) */
3941 void
3944 {
3959 {
3964 {
3969 }
3970 else
3972 }
3973 else
3974 {
3976 {
3983 /* FALLTHRU */
3994 {
3997 }
4006 /* FALLTHRU */
4016 {
4021 {
4024 }
4025 }
4033 {
4038 {
4041 }
4042 }
4044 }
4045 }
4046 }
4048 /* Define where to put the arguments to a function.
4049 Value is zero to push the argument on the stack,
4050 or a hard register in which to store the argument.
4052 MODE is the argument's machine mode.
4053 TYPE is the data type of the argument (as a tree).
4054 This is null for libcalls where that information may
4055 not be available.
4056 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4057 the preceding args and about the function being called.
4058 NAMED is nonzero if this argument is a named parameter
4059 (otherwise it is an extra parameter matching an ellipsis). */
4061 rtx
4064 {
4072 /* To simplify the code below, represent vector types with a vector mode
4073 even if MMX/SSE are not active. */
4077 /* Handle a hidden AL argument containing number of registers for varargs
4078 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
4079 any AL settings. */
4081 {
4085 ? SSE_REGPARM_MAX
4088 else
4090 }
4096 else
4098 {
4099 /* For now, pass fp/complex values on the stack. */
4106 /* FALLTHRU */
4112 {
4115 /* Fastcall allocates the first two DWORD (SImode) or
4116 smaller arguments to ECX and EDX. */
4118 {
4122 /* ECX not EAX is the first allocated register. */
4125 }
4127 }
4135 /* FALLTHRU */
4144 {
4146 {
4150 }
4154 }
4161 {
4163 {
4167 }
4171 }
4173 }
4176 {
4183 else
4187 }
4190 }
4192 /* A C expression that indicates when an argument must be passed by
4193 reference. If nonzero for an argument, a copy of that argument is
4194 made in memory and a pointer to the argument is passed instead of
4195 the argument itself. The pointer is passed in whatever way is
4196 appropriate for passing a pointer to that type. */
4198 static bool
4202 {
4207 {
4211 }
4214 }
4216 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4217 ABI. Only called if TARGET_SSE. */
4218 static bool
4220 {
4229 {
4230 /* Walk the aggregates recursively. */
4232 {
4236 {
4237 tree field;
4239 /* Walk all the structure fields. */
4241 {
4245 }
4247 }
4250 /* Just for use if some languages passes arrays by value. */
4257 }
4258 }
4260 }
4262 /* Gives the alignment boundary, in bits, of an argument with the
4263 specified mode and type. */
4265 int
4267 {
4271 else
4276 {
4277 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4278 make an exception for SSE modes since these require 128bit
4279 alignment.
4281 The handling here differs from field_alignment. ICC aligns MMX
4282 arguments to 4 byte boundaries, while structure fields are aligned
4283 to 8 byte boundaries. */
4287 {
4290 }
4291 else
4292 {
4295 }
4296 }
4300 }
4302 /* Return true if N is a possible register number of function value. */
4303 bool
4305 {
4307 {
4309 {
4313 }
4317 }
4318 else
4319 {
4330 }
4331 }
4333 /* Define how to find the value returned by a function.
4334 VALTYPE is the data type of the value (as a tree).
4335 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4336 otherwise, FUNC is 0. */
4337 rtx
4340 {
4344 {
4348 /* For zero sized structures, construct_container return NULL, but we
4349 need to keep rest of compiler happy by returning meaningful value. */
4353 }
4354 else
4355 {
4363 }
4364 }
4366 /* Return true iff type is returned in memory. */
4367 int
4369 {
4385 {
4386 /* User-created vectors small enough to fit in EAX. */
4390 /* MMX/3dNow values are returned in MM0,
4391 except when it doesn't exits. */
4395 /* SSE values are returned in XMM0, except when it doesn't exist. */
4398 }
4409 }
4411 /* When returning SSE vector types, we have a choice of either
4412 (1) being abi incompatible with a -march switch, or
4413 (2) generating an error.
4414 Given no good solution, I think the safest thing is one warning.
4415 The user won't be able to use -Werror, but....
4417 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4418 called in response to actually generating a caller or callee that
4419 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4420 via aggregate_value_p for general type probing from tree-ssa. */
4422 static rtx
4424 {
4428 {
4429 /* Look at the return type of the function, not the function type. */
4433 {
4436 {
4440 }
4441 }
4444 {
4446 {
4450 }
4451 }
4452 }
4455 }
4457 /* Define how to find the value returned by a library function
4458 assuming the value has mode MODE. */
4459 rtx
4461 {
4463 {
4465 {
4482 }
4483 }
4484 else
4486 }
4488 /* Given a mode, return the register to use for a return value. */
4490 static int
4492 {
4495 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4496 we normally prevent this case when mmx is not available. However
4497 some ABIs may require the result to be returned like DImode. */
4501 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4502 we prevent this case when sse is not available. However some ABIs
4503 may require the result to be returned like integer TImode. */
4507 /* Decimal floating point values can go in %eax, unlike other float modes. */
4511 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
4515 /* Floating point return values in %st(0), except for local functions when
4516 SSE math is enabled or for functions with sseregparm attribute. */
4519 {
4524 }
4527 }
4528 \f
4529 /* Create the va_list data type. */
4531 static tree
4533 {
4536 /* For i386 we use plain pointer to argument area. */
4544 unsigned_type_node);
4546 unsigned_type_node);
4548 ptr_type_node);
4550 ptr_type_node);
4569 /* The correct type is an array type of one element. */
4571 }
4573 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4575 static void
4579 {
4580 CUMULATIVE_ARGS next_cum;
4582 rtx label;
4583 rtx label_ref;
4584 rtx tmp_reg;
4585 rtx nsse_reg;
4587 tree fntype;
4597 /* Indicate to allocate space on the stack for varargs save area. */
4607 /* For varargs, we do not want to skip the dummy va_dcl argument.
4608 For stdargs, we do want to skip the last named argument. */
4619 i < ix86_regparm
4621 i++)
4622 {
4629 }
4632 {
4633 /* Now emit code to save SSE registers. The AX parameter contains number
4634 of SSE parameter registers used to call this function. We use
4635 sse_prologue_save insn template that produces computed jump across
4636 SSE saves. We need some preparation work to get this working. */
4641 /* Compute address to jump to :
4642 label - 5*eax + nnamed_sse_arguments*5 */
4650 emit_move_insn
4654 label_ref,
4656 else
4660 /* Compute address of memory block we save into. We always use pointer
4661 pointing 127 bytes after first byte to store - this is needed to keep
4662 instruction size limited by 4 bytes. */
4672 /* And finally do the dirty job! */
4675 }
4677 }
4679 /* Implement va_start. */
4681 void
4683 {
4687 tree type;
4689 /* Only 64bit target needs something special. */
4691 {
4694 }
4707 /* Count number of gp and fp argument registers used. */
4717 {
4723 }
4726 {
4732 }
4734 /* Find the overflow area. */
4745 {
4746 /* Find the register save area.
4747 Prologue of the function save it right above stack frame. */
4753 }
4754 }
4756 /* Implement va_arg. */
4758 tree
4760 {
4767 rtx container;
4769 tree ptrtype;
4772 /* Only 64bit target needs something special. */
4797 /* Pull the value out of the saved registers. */
4803 {
4817 /* In case we are passing structure, verify that it is consecutive block
4818 on the register save area. If not we need to do moves. */
4820 {
4821 /* Verify that all registers are strictly consecutive */
4823 {
4827 {
4832 }
4833 }
4834 else
4835 {
4839 {
4844 }
4845 }
4846 }
4848 {
4851 }
4852 else
4853 {
4858 }
4860 /* First ensure that we fit completely in registers. */
4862 {
4869 }
4871 {
4879 }
4881 /* Compute index to start of area used for integer regs. */
4883 {
4884 /* int_addr = gpr + sav; */
4889 }
4891 {
4892 /* sse_addr = fpr + sav; */
4897 }
4899 {
4903 /* addr = &temp; */
4909 {
4920 {
4923 }
4924 else
4925 {
4928 }
4941 }
4942 }
4945 {
4950 }
4952 {
4957 }
4964 }
4966 /* ... otherwise out of the overflow area. */
4968 /* Care for on-stack alignment if needed. */
4972 else
4973 {
4979 }
4991 {
4994 }
5002 }
5003 \f
5004 /* Return nonzero if OPNUM's MEM should be matched
5005 in movabs* patterns. */
5007 int
5009 {
5021 }
5022 \f
5023 /* Initialize the table of extra 80387 mathematical constants. */
5025 static void
5027 {
5029 {
5035 };
5039 {
5041 /* Ensure each constant is rounded to XFmode precision. */
5044 }
5047 }
5049 /* Return true if the constant is something that can be loaded with
5050 a special instruction. */
5052 int
5054 {
5055 REAL_VALUE_TYPE r;
5067 /* For XFmode constants, try to find a special 80387 instruction when
5068 optimizing for size or on those CPUs that benefit from them. */
5071 {
5080 }
5082 /* Load of the constant -0.0 or -1.0 will be split as
5083 fldz;fchs or fld1;fchs sequence. */
5090 }
5092 /* Return the opcode of the special instruction to be used to load
5093 the constant X. */
5097 {
5099 {
5119 }
5120 }
5122 /* Return the CONST_DOUBLE representing the 80387 constant that is
5123 loaded by the specified special instruction. The argument IDX
5124 matches the return value from standard_80387_constant_p. */
5126 rtx
5128 {
5135 {
5146 }
5149 XFmode);
5150 }
5152 /* Return 1 if mode is a valid mode for sse. */
5153 static int
5155 {
5157 {
5168 }
5169 }
5171 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5172 */
5173 int
5175 {
5185 }
5187 /* Return the opcode of the special instruction to be used to load
5188 the constant X. */
5192 {
5194 {
5200 else
5204 }
5206 }
5208 /* Returns 1 if OP contains a symbol reference */
5210 int
5212 {
5221 {
5223 {
5229 }
5233 }
5236 }
5238 /* Return 1 if it is appropriate to emit `ret' instructions in the
5239 body of a function. Do this only if the epilogue is simple, needing a
5240 couple of insns. Prior to reloading, we can't tell how many registers
5241 must be saved, so return 0 then. Return 0 if there is no frame
5242 marker to de-allocate. */
5244 int
5246 {
5252 /* Don't allow more than 32 pop, since that's all we can do
5253 with one instruction. */
5260 }
5261 \f
5262 /* Value should be nonzero if functions must have frame pointers.
5263 Zero means the frame pointer need not be set up (and parms may
5264 be accessed via the stack pointer) in functions that seem suitable. */
5266 int
5268 {
5269 /* If we accessed previous frames, then the generated code expects
5270 to be able to access the saved ebp value in our frame. */
5274 /* Several x86 os'es need a frame pointer for other reasons,
5275 usually pertaining to setjmp. */
5279 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5280 the frame pointer by default. Turn it back on now if we've not
5281 got a leaf function. */
5283 && (!current_function_is_leaf
5291 }
5293 /* Record that the current function accesses previous call frames. */
5295 void
5297 {
5299 }
5300 \f
5301 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5302 # define USE_HIDDEN_LINKONCE 1
5303 #else
5304 # define USE_HIDDEN_LINKONCE 0
5305 #endif
5309 /* Fills in the label name that should be used for a pc thunk for
5310 the given register. */
5312 static void
5314 {
5319 else
5321 }
5324 /* This function generates code for -fpic that loads %ebx with
5325 the return address of the caller and then returns. */
5327 void
5329 {
5334 {
5342 #if TARGET_MACHO
5344 {
5352 }
5353 else
5354 #endif
5356 {
5357 tree decl;
5360 error_mark_node);
5373 }
5374 else
5375 {
5378 }
5384 }
5388 }
5390 /* Emit code for the SET_GOT patterns. */
5394 {
5400 {
5401 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5406 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5407 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5408 an unadorned address. */
5413 }
5418 {
5423 else
5426 #if TARGET_MACHO
5427 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5428 is what will be referenced by the Mach-O PIC subsystem. */
5431 #endif
5438 }
5439 else
5440 {
5448 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5449 is what will be referenced by the Mach-O PIC subsystem. */
5450 #if TARGET_MACHO
5453 else
5456 #endif
5457 }
5464 else
5468 }
5470 /* Generate an "push" pattern for input ARG. */
5472 static rtx
5474 {
5478 stack_pointer_rtx)),
5479 arg);
5480 }
5482 /* Return >= 0 if there is an unused call-clobbered register available
5483 for the entire function. */
5485 static unsigned int
5487 {
5490 {
5495 }
5498 }
5500 /* Return 1 if we need to save REGNO. */
5501 static int
5503 {
5507 || current_function_profile
5508 || current_function_calls_eh_return
5510 {
5514 }
5517 {
5520 {
5526 }
5527 }
5537 }
5539 /* Return number of registers to be saved on the stack. */
5541 static int
5543 {
5549 nregs++;
5551 }
5553 /* Return the offset between two registers, one to be eliminated, and the other
5554 its replacement, at the start of a routine. */
5556 HOST_WIDE_INT
5558 {
5567 else
5568 {
5576 }
5577 }
5579 /* Fill structure ix86_frame about frame of currently computed function. */
5581 static void
5583 {
5584 HOST_WIDE_INT total_size;
5586 HOST_WIDE_INT offset;
5596 /* During reload iteration the amount of registers saved can change.
5597 Recompute the value as needed. Do not recompute when amount of registers
5598 didn't change as reload does multiple calls to the function and does not
5599 expect the decision to change within single iteration. */
5602 {
5606 /* The fast prologue uses move instead of push to save registers. This
5607 is significantly longer, but also executes faster as modern hardware
5608 can execute the moves in parallel, but can't do that for push/pop.
5610 Be careful about choosing what prologue to emit: When function takes
5611 many instructions to execute we may use slow version as well as in
5612 case function is known to be outside hot spot (this is known with
5613 feedback only). Weight the size of function by number of registers
5614 to save as it is cheap to use one or two push instructions but very
5615 slow to use many of them. */
5619 || (flag_branch_probabilities
5622 else
5625 }
5629 else
5633 /* Skip return address and saved base pointer. */
5638 /* Do some sanity checking of stack_alignment_needed and
5639 preferred_alignment, since i386 port is the only using those features
5640 that may break easily. */
5651 /* Register save area */
5654 /* Va-arg area */
5656 {
5659 }
5660 else
5663 /* Align start of frame for local function. */
5669 /* Frame pointer points here. */
5674 /* Add outgoing arguments area. Can be skipped if we eliminated
5675 all the function calls as dead code.
5676 Skipping is however impossible when function calls alloca. Alloca
5677 expander assumes that last current_function_outgoing_args_size
5678 of stack frame are unused. */
5682 {
5685 }
5686 else
5689 /* Align stack boundary. Only needed if we're calling another function
5690 or using alloca. */
5695 else
5700 /* We've reached end of stack frame. */
5703 /* Size prologue needs to allocate. */
5713 && current_function_is_leaf
5715 {
5721 }
5722 else
5726 #if 0
5742 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
5743 #endif
5744 }
5746 /* Emit code to save registers in the prologue. */
5748 static void
5750 {
5752 rtx insn;
5756 {
5759 }
5760 }
5762 /* Emit code to save registers using MOV insns. First register
5763 is restored from POINTER + OFFSET. */
5764 static void
5766 {
5768 rtx insn;
5772 {
5778 }
5779 }
5781 /* Expand prologue or epilogue stack adjustment.
5782 The pattern exist to put a dependency on all ebp-based memory accesses.
5783 STYLE should be negative if instructions should be marked as frame related,
5784 zero if %r11 register is live and cannot be freely used and positive
5785 otherwise. */
5787 static void
5789 {
5790 rtx insn;
5796 else
5797 {
5798 rtx r11;
5799 /* r11 is used by indirect sibcall return as well, set before the
5800 epilogue and used after the epilogue. ATM indirect sibcall
5801 shouldn't be used together with huge frame sizes in one
5802 function because of the frame_size check in sibcall.c. */
5809 offset));
5810 }
5813 }
5815 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5817 static rtx
5819 {
5827 || ix86_force_align_arg_pointer
5829 {
5830 /* Nested functions can't realign the stack due to a register
5831 conflict. */
5834 {
5839 ix86_force_align_arg_pointer_string);
5841 }
5844 }
5845 else
5847 }
5849 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5850 This is called from dwarf2out.c to emit call frame instructions
5851 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5852 static void
5854 {
5859 {
5870 }
5871 }
5873 /* Expand the prologue into a bunch of separate insns. */
5875 void
5877 {
5878 rtx insn;
5881 HOST_WIDE_INT allocate;
5886 {
5889 /* Grab the argument pointer. */
5895 /* The unwind info consists of two parts: install the fafp as the cfa,
5896 and record the fafp as the "save register" of the stack pointer.
5897 The later is there in order that the unwinder can see where it
5898 should restore the stack pointer across the and insn. */
5903 UNSPEC_REG_SAVE);
5910 /* Align the stack. */
5914 /* And here we cheat like madmen with the unwind info. We force the
5915 cfa register back to sp+4, which is exactly what it was at the
5916 start of the function. Re-pushing the return address results in
5917 the return at the same spot relative to the cfa, and thus is
5918 correct wrt the unwind info. */
5929 }
5931 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5932 slower on all targets. Also sdb doesn't like it. */
5935 {
5941 }
5947 else
5950 /* When using red zone we may start register saving before allocating
5951 the stack frame saving one cycle of the prologue. */
5958 ;
5962 else
5963 {
5964 /* Only valid for Win32. */
5967 rtx t;
5972 {
5975 }
5987 {
5990 allocate
5993 else
5996 }
5997 }
6000 {
6003 else
6006 }
6012 {
6019 }
6022 {
6024 {
6026 {
6039 }
6040 else
6042 }
6043 else
6046 /* Even with accurate pre-reload life analysis, we can wind up
6047 deleting all references to the pic register after reload.
6048 Consider if cross-jumping unifies two sides of a branch
6049 controlled by a comparison vs the only read from a global.
6050 In which case, allow the set_got to be deleted, though we're
6051 too late to do anything about the ebx save in the prologue. */
6053 }
6055 /* Prevent function calls from be scheduled before the call to mcount.
6056 In the pic_reg_used case, make sure that the got load isn't deleted. */
6059 }
6061 /* Emit code to restore saved registers using MOV insns. First register
6062 is restored from POINTER + OFFSET. */
6063 static void
6066 {
6072 {
6073 /* Ensure that adjust_address won't be forced to produce pointer
6074 out of range allowed by x86-64 instruction set. */
6076 {
6077 rtx r11;
6084 }
6088 }
6089 }
6091 /* Restore function stack, frame, and registers. */
6093 void
6095 {
6099 HOST_WIDE_INT offset;
6103 /* Calculate start of saved registers relative to ebp. Special care
6104 must be taken for the normal return case of a function using
6105 eh_return: the eax and edx registers are marked as saved, but not
6106 restored along this path. */
6112 /* If we're only restoring one register and sp is not valid then
6113 using a move instruction to restore the register since it's
6114 less work than reloading sp and popping the register.
6116 The default code result in stack adjustment using add/lea instruction,
6117 while this code results in LEAVE instruction (or discrete equivalent),
6118 so it is profitable in some other cases as well. Especially when there
6119 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6120 and there is exactly one register to pop. This heuristic may need some
6121 tuning in future. */
6123 || (TARGET_EPILOGUE_USING_MOVE
6131 {
6132 /* Restore registers. We can use ebp or esp to address the memory
6133 locations. If both are available, default to ebp, since offsets
6134 are known to be small. Only exception is esp pointing directly to the
6135 end of block of saved registers, where we may simplify addressing
6136 mode. */
6141 else
6145 /* eh_return epilogues need %ecx added to the stack pointer. */
6147 {
6151 {
6161 }
6162 else
6163 {
6168 }
6169 }
6174 style);
6175 /* If not an i386, mov & pop is faster than "leave". */
6179 else
6180 {
6182 hard_frame_pointer_rtx,
6186 else
6188 }
6189 }
6190 else
6191 {
6192 /* First step is to deallocate the stack frame so that we can
6193 pop the registers. */
6195 {
6198 hard_frame_pointer_rtx,
6200 }
6207 {
6210 else
6212 }
6214 {
6215 /* Leave results in shorter dependency chains on CPUs that are
6216 able to grok it fast. */
6221 else
6223 }
6224 }
6227 {
6231 }
6233 /* Sibcall epilogues don't want a return instruction. */
6238 {
6241 /* i386 can only pop 64K bytes. If asked to pop more, pop
6242 return address, do explicit add, and jump indirectly to the
6243 caller. */
6246 {
6249 /* There is no "pascal" calling convention in 64bit ABI. */
6255 }
6256 else
6258 }
6259 else
6261 }
6263 /* Reset from the function's potential modifications. */
6265 static void
6267 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6268 {
6271 #if TARGET_MACHO
6272 /* Mach-O doesn't support labels at the end of objects, so if
6273 it looks like we might want one, insert a NOP. */
6274 {
6285 }
6286 #endif
6288 }
6289 \f
6290 /* Extract the parts of an RTL expression that is a valid memory address
6291 for an instruction. Return 0 if the structure of the address is
6292 grossly off. Return -1 if the address contains ASHIFT, so it is not
6293 strictly valid, but still used for computing length of lea instruction. */
6295 int
6297 {
6308 {
6313 do
6314 {
6319 }
6326 {
6329 {
6339 && TARGET_TLS_DIRECT_SEG_REFS
6342 else
6352 else
6367 }
6368 }
6369 }
6371 {
6374 }
6376 {
6377 rtx tmp;
6379 /* We're called for lea too, which implements ashift on occasion. */
6389 }
6390 else
6393 /* Extract the integral value of scale. */
6395 {
6399 }
6404 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6409 {
6410 rtx tmp;
6413 }
6415 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6421 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6422 Avoid this by transforming to [%esi+0]. */
6429 /* Special case: encode reg+reg instead of reg*2. */
6433 /* Special case: scaling cannot be encoded without base or displacement. */
6444 }
6445 \f
6446 /* Return cost of the memory address x.
6447 For i386, it is better to use a complex address than let gcc copy
6448 the address into a reg and make a new pseudo. But not if the address
6449 requires to two regs - that would mean more pseudos with longer
6450 lifetimes. */
6451 static int
6453 {
6465 /* More complex memory references are better. */
6467 cost--;
6469 cost--;
6471 /* Attempt to minimize number of registers in the address. */
6477 cost++;
6484 cost++;
6486 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6487 since it's predecode logic can't detect the length of instructions
6488 and it degenerates to vector decoded. Increase cost of such
6489 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6490 to split such addresses or even refuse such addresses at all.
6492 Following addressing modes are affected:
6493 [base+scale*index]
6494 [scale*index+disp]
6495 [base+index]
6497 The first and last case may be avoidable by explicitly coding the zero in
6498 memory address, but I don't have AMD-K6 machine handy to check this
6499 theory. */
6508 }
6509 \f
6510 /* If X is a machine specific address (i.e. a symbol or label being
6511 referenced as a displacement from the GOT implemented using an
6512 UNSPEC), then return the base term. Otherwise return X. */
6514 rtx
6516 {
6517 rtx term;
6520 {
6539 }
6548 }
6550 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6551 this is used for to form addresses to local data when -fPIC is in
6552 use. */
6554 static bool
6556 {
6558 {
6562 {
6566 }
6567 }
6570 }
6571 \f
6572 /* Determine if a given RTX is a valid constant. We already know this
6573 satisfies CONSTANT_P. */
6575 bool
6577 {
6579 {
6584 {
6588 }
6593 /* Only some unspecs are valid as "constants". */
6596 {
6612 }
6614 /* We must have drilled down to a symbol. */
6619 /* FALLTHRU */
6622 /* TLS symbols are never valid. */
6641 }
6643 /* Otherwise we handle everything else in the move patterns. */
6645 }
6647 /* Determine if it's legal to put X into the constant pool. This
6648 is not possible for the address of thread-local symbols, which
6649 is checked above. */
6651 static bool
6653 {
6654 /* We can always put integral constants and vectors in memory. */
6656 {
6664 }
6666 }
6668 /* Determine if a given RTX is a valid constant address. */
6670 bool
6672 {
6674 }
6676 /* Nonzero if the constant value X is a legitimate general operand
6677 when generating PIC code. It is given that flag_pic is on and
6678 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6680 bool
6682 {
6683 rtx inner;
6686 {
6693 /* Only some unspecs are valid as "constants". */
6696 {
6707 }
6708 /* FALLTHRU */
6716 }
6717 }
6719 /* Determine if a given CONST RTX is a valid memory displacement
6720 in PIC mode. */
6722 int
6724 {
6727 /* In 64bit mode we can allow direct addresses of symbols and labels
6728 when they are not dynamic symbols. */
6730 {
6734 {
6751 /* FALLTHRU */
6754 /* TLS references should always be enclosed in UNSPEC. */
6764 }
6765 }
6771 {
6772 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6773 of GOT tables. We should not need these anyway. */
6784 }
6788 {
6793 }
6802 {
6806 /* We need to check for both symbols and labels because VxWorks loads
6807 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
6808 details. */
6812 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6813 While ABI specify also 32bit relocation but we don't produce it in
6814 small PIC model at all. */
6836 }
6839 }
6841 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6842 memory address for an instruction. The MODE argument is the machine mode
6843 for the MEM expression that wants to use this address.
6845 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6846 convert common non-canonical forms to canonical form so that they will
6847 be recognized. */
6849 int
6851 {
6854 HOST_WIDE_INT scale;
6859 {
6864 }
6867 {
6870 }
6877 /* Validate base register.
6879 Don't allow SUBREG's that span more than a word here. It can lead to spill
6880 failures when the base is one word out of a two word structure, which is
6881 represented internally as a DImode int. */
6884 {
6885 rtx reg;
6895 else
6896 {
6899 }
6902 {
6905 }
6909 {
6912 }
6913 }
6915 /* Validate index register.
6917 Don't allow SUBREG's that span more than a word here -- same as above. */
6920 {
6921 rtx reg;
6931 else
6932 {
6935 }
6938 {
6941 }
6945 {
6948 }
6949 }
6951 /* Validate scale factor. */
6953 {
6956 {
6959 }
6962 {
6965 }
6966 }
6968 /* Validate displacement. */
6970 {
6976 {
6977 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6978 used. While ABI specify also 32bit relocations, we don't produce
6979 them at all and use IP relative instead. */
7002 }
7005 && (flag_pic
7006 || (TARGET_MACHO
7007 #if TARGET_MACHO
7008 && MACHOPIC_INDIRECT
7010 #endif
7011 )))
7012 {
7014 is_legitimate_pic:
7016 {
7017 /* foo@dtpoff(%rX) is ok. */
7024 {
7027 }
7028 }
7030 {
7033 }
7035 /* This code used to verify that a symbolic pic displacement
7036 includes the pic_offset_table_rtx register.
7038 While this is good idea, unfortunately these constructs may
7039 be created by "adds using lea" optimization for incorrect
7040 code like:
7042 int a;
7043 int foo(int i)
7044 {
7045 return *(&a+i);
7046 }
7048 This code is nonsensical, but results in addressing
7049 GOT table with pic_offset_table_rtx base. We can't
7050 just refuse it easily, since it gets matched by
7051 "addsi3" pattern, that later gets split to lea in the
7052 case output register differs from input. While this
7053 can be handled by separate addsi pattern for this case
7054 that never results in lea, this seems to be easier and
7055 correct fix for crash to disable this test. */
7056 }
7063 {
7066 }
7069 {
7072 }
7073 }
7075 /* Everything looks valid. */
7080 report_error:
7082 {
7085 }
7087 }
7088 \f
7089 /* Return a unique alias set for the GOT. */
7091 static HOST_WIDE_INT
7093 {
7098 }
7100 /* Return a legitimate reference for ORIG (an address) using the
7101 register REG. If REG is 0, a new pseudo is generated.
7103 There are two types of references that must be handled:
7105 1. Global data references must load the address from the GOT, via
7106 the PIC reg. An insn is emitted to do this load, and the reg is
7107 returned.
7109 2. Static data references, constant pool addresses, and code labels
7110 compute the address as an offset from the GOT, whose base is in
7111 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7112 differentiate them from global data objects. The returned
7113 address is the PIC reg + an unspec constant.
7115 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7116 reg also appears in the address. */
7118 static rtx
7120 {
7123 rtx base;
7125 #if TARGET_MACHO
7127 {
7130 /* Use the generic Mach-O PIC machinery. */
7132 }
7133 #endif
7140 {
7141 rtx tmpreg;
7142 /* This symbol may be referenced via a displacement from the PIC
7143 base address (@GOTOFF). */
7150 {
7153 }
7154 else
7159 else
7164 {
7168 }
7170 }
7172 {
7173 /* This symbol may be referenced via a displacement from the PIC
7174 base address (@GOTOFF). */
7181 {
7184 }
7185 else
7191 {
7194 }
7195 }
7197 /* We can't use @GOTOFF for text labels on VxWorks;
7198 see gotoff_operand. */
7200 {
7202 {
7210 /* Use directly gen_movsi, otherwise the address is loaded
7211 into register for CSE. We don't want to CSE this addresses,
7212 instead we CSE addresses from the GOT table, so skip this. */
7215 }
7216 else
7217 {
7218 /* This symbol must be referenced via a load from the
7219 Global Offset Table (@GOT). */
7235 }
7236 }
7237 else
7238 {
7241 {
7243 {
7246 }
7247 else
7249 }
7251 {
7254 /* We must match stuff we generate before. Assume the only
7255 unspecs that can get here are ours. Not that we could do
7256 anything with them anyway.... */
7262 }
7264 {
7267 /* Check first to see if this is a constant offset from a @GOTOFF
7268 symbol reference. */
7271 {
7273 {
7277 UNSPEC_GOTOFF);
7283 {
7286 }
7287 }
7288 else
7289 {
7292 {
7296 }
7297 }
7298 }
7299 else
7300 {
7307 else
7308 {
7310 {
7313 }
7315 }
7316 }
7317 }
7318 }
7320 }
7321 \f
7322 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7324 static rtx
7326 {
7338 }
7340 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7341 false if we expect this to be used for a memory address and true if
7342 we expect to load the address into a register. */
7344 static rtx
7346 {
7351 {
7357 {
7366 }
7369 else
7373 {
7377 }
7385 {
7396 }
7399 else
7403 {
7408 }
7416 {
7420 }
7426 {
7429 }
7431 {
7436 }
7438 {
7442 }
7443 else
7444 {
7447 }
7457 {
7461 }
7462 else
7463 {
7467 }
7477 {
7480 }
7481 else
7482 {
7486 }
7491 }
7494 }
7496 /* Try machine-dependent ways of modifying an illegitimate address
7497 to be legitimate. If we find one, return the new, valid address.
7498 This macro is used in only one place: `memory_address' in explow.c.
7500 OLDX is the address as it was before break_out_memory_refs was called.
7501 In some cases it is useful to look at this to decide what needs to be done.
7503 MODE and WIN are passed so that this macro can use
7504 GO_IF_LEGITIMATE_ADDRESS.
7506 It is always safe for this macro to do nothing. It exists to recognize
7507 opportunities to optimize the output.
7509 For the 80386, we handle X+REG by loading X into a register R and
7510 using R+REG. R will go in a general reg and indexing will be used.
7511 However, if REG is a broken-out memory address or multiplication,
7512 nothing needs to be done because REG can certainly go in a general reg.
7514 When -fpic is used, special handling is needed for symbolic references.
7515 See comments by legitimize_pic_address in i386.c for details. */
7517 rtx
7519 {
7524 {
7528 }
7537 {
7540 }
7545 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7549 {
7554 }
7557 {
7558 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7563 {
7569 }
7574 {
7580 }
7582 /* Put multiply first if it isn't already. */
7584 {
7589 }
7591 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7592 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7593 created by virtual register instantiation, register elimination, and
7594 similar optimizations. */
7596 {
7602 }
7604 /* Canonicalize
7605 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7606 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7611 {
7612 rtx constant;
7616 {
7619 }
7621 {
7624 }
7625 else
7629 {
7635 }
7636 }
7642 {
7645 }
7648 {
7651 }
7659 {
7662 }
7668 {
7676 }
7679 {
7687 }
7688 }
7691 }
7692 \f
7693 /* Print an integer constant expression in assembler syntax. Addition
7694 and subtraction are the only arithmetic that may appear in these
7695 expressions. FILE is the stdio stream to write to, X is the rtx, and
7696 CODE is the operand print code from the output string. */
7698 static void
7700 {
7704 {
7713 else
7714 {
7717 /* Mark the decl as referenced so that cgraph will output the function. */
7721 #if TARGET_MACHO
7725 #endif
7727 }
7734 /* FALLTHRU */
7745 /* This used to output parentheses around the expression,
7746 but that does not work on the 386 (either ATT or BSD assembler). */
7752 {
7753 /* We can use %d if the number is <32 bits and positive. */
7758 else
7760 }
7761 else
7762 /* We can't handle floating point constants;
7763 PRINT_OPERAND must handle them. */
7768 /* Some assemblers need integer constants to appear first. */
7770 {
7774 }
7775 else
7776 {
7781 }
7798 {
7812 /* FIXME: This might be @TPOFF in Sun ld too. */
7821 else
7830 else
7839 }
7844 }
7845 }
7847 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7848 We need to emit DTP-relative relocations. */
7850 static void
7852 {
7857 {
7865 }
7866 }
7868 /* In the name of slightly smaller debug output, and to cater to
7869 general assembler lossage, recognize PIC+GOTOFF and turn it back
7870 into a direct symbol reference.
7872 On Darwin, this is necessary to avoid a crash, because Darwin
7873 has a different PIC label for each routine but the DWARF debugging
7874 information is not associated with any particular routine, so it's
7875 necessary to remove references to the PIC label from RTL stored by
7876 the DWARF output code. */
7878 static rtx
7880 {
7882 /* reg_addend is NULL or a multiple of some register. */
7884 /* const_addend is NULL or a const_int. */
7886 /* This is the result, or NULL. */
7893 {
7900 }
7908 /* %ebx + GOT/GOTOFF */
7909 ;
7911 {
7912 /* %ebx + %reg * scale + GOT/GOTOFF */
7920 else
7926 }
7927 else
7933 {
7936 }
7955 }
7956 \f
7957 static void
7960 {
7964 {
7970 }
7975 {
7987 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
7988 Those same assemblers have the same but opposite lossage on cmov. */
7994 {
8007 }
8015 {
8028 }
8031 /* ??? As above. */
8051 }
8053 }
8055 /* Print the name of register X to FILE based on its machine mode and number.
8056 If CODE is 'w', pretend the mode is HImode.
8057 If CODE is 'b', pretend the mode is QImode.
8058 If CODE is 'k', pretend the mode is SImode.
8059 If CODE is 'q', pretend the mode is DImode.
8060 If CODE is 'h', pretend the reg is the 'high' byte register.
8061 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8063 void
8065 {
8087 else
8090 /* Irritatingly, AMD extended registers use different naming convention
8091 from the normal registers. */
8093 {
8096 {
8115 }
8117 }
8119 {
8122 {
8125 }
8126 /* FALLTHRU */
8132 /* FALLTHRU */
8135 normal:
8150 }
8151 }
8153 /* Locate some local-dynamic symbol still in use by this function
8154 so that we can print its name in some tls_local_dynamic_base
8155 pattern. */
8159 {
8160 rtx insn;
8171 }
8173 static int
8175 {
8180 {
8183 }
8186 }
8188 /* Meaning of CODE:
8189 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8190 C -- print opcode suffix for set/cmov insn.
8191 c -- like C, but print reversed condition
8192 F,f -- likewise, but for floating-point.
8193 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8194 otherwise nothing
8195 R -- print the prefix for register names.
8196 z -- print the opcode suffix for the size of the current operand.
8197 * -- print a star (in certain assembler syntax)
8198 A -- print an absolute memory reference.
8199 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8200 s -- print a shift double count, followed by the assemblers argument
8201 delimiter.
8202 b -- print the QImode name of the register for the indicated operand.
8203 %b0 would print %al if operands[0] is reg 0.
8204 w -- likewise, print the HImode name of the register.
8205 k -- likewise, print the SImode name of the register.
8206 q -- likewise, print the DImode name of the register.
8207 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8208 y -- print "st(0)" instead of "st" as a register.
8209 D -- print condition for SSE cmp instruction.
8210 P -- if PIC, print an @PLT suffix.
8211 X -- don't print any sort of PIC '@' suffix for a symbol.
8212 & -- print some in-use local-dynamic symbol name.
8213 H -- print a memory address offset by 8; used for sse high-parts
8214 */
8216 void
8218 {
8220 {
8222 {
8234 {
8240 /* Intel syntax. For absolute addresses, registers should not
8241 be surrounded by braces. */
8243 {
8248 }
8253 }
8290 /* 387 opcodes don't get size suffixes if the operands are
8291 registers. */
8295 /* Likewise if using Intel opcodes. */
8299 /* This is the size of op from size of operand. */
8301 {
8307 #ifdef HAVE_GAS_FILDS_FISTS
8309 #endif
8314 {
8317 }
8318 else
8329 {
8330 #ifdef GAS_MNEMONICS
8332 #else
8335 #endif
8336 }
8337 else
8343 }
8357 {
8360 }
8364 /* Little bit of braindamage here. The SSE compare instructions
8365 does use completely different names for the comparisons that the
8366 fp conditional moves. */
8368 {
8401 }
8404 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8406 {
8408 {
8415 }
8417 }
8418 #endif
8424 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8427 #endif
8431 /* Like above, but reverse condition */
8433 /* Check to see if argument to %c is really a constant
8434 and not a condition code which needs to be reversed. */
8436 {
8437 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8439 }
8443 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8446 #endif
8451 /* It doesn't actually matter what mode we use here, as we're
8452 only going to use this for printing. */
8457 {
8458 rtx x;
8465 {
8470 {
8474 /* Emit hints only in the case default branch prediction
8475 heuristics would fail. */
8477 {
8478 /* We use 3e (DS) prefix for taken branches and
8479 2e (CS) prefix for not taken branches. */
8482 else
8484 }
8485 }
8486 }
8488 }
8491 }
8492 }
8498 {
8499 /* No `byte ptr' prefix for call instructions. */
8501 {
8504 {
8513 }
8515 /* Check for explicit size override (codes 'b', 'w' and 'k') */
8525 }
8528 /* Avoid (%rip) for call operands. */
8534 else
8536 }
8539 {
8540 REAL_VALUE_TYPE r;
8549 }
8551 /* These float cases don't actually occur as immediate operands. */
8553 {
8558 }
8562 {
8567 }
8569 else
8570 {
8571 /* We have patterns that allow zero sets of memory, for instance.
8572 In 64-bit mode, we should probably support all 8-byte vectors,
8573 since we can in fact encode that into an immediate. */
8575 {
8578 }
8581 {
8583 {
8586 }
8589 {
8592 else
8594 }
8595 }
8600 else
8602 }
8603 }
8604 \f
8605 /* Print a memory operand whose address is ADDR. */
8607 void
8609 {
8623 {
8634 }
8637 {
8638 /* Displacement only requires special attention. */
8641 {
8643 {
8647 }
8649 }
8652 else
8655 /* Use one byte shorter RIP relative addressing for 64bit mode. */
8657 {
8666 }
8667 }
8668 else
8669 {
8671 {
8673 {
8678 else
8680 }
8686 {
8691 }
8693 }
8694 else
8695 {
8699 {
8700 /* Pull out the offset of a symbol; print any symbol itself. */
8704 {
8708 }
8716 else
8718 }
8722 {
8725 {
8729 }
8730 }
8733 else
8737 {
8742 }
8744 }
8745 }
8746 }
8748 bool
8750 {
8751 rtx op;
8758 {
8761 /* FIXME: This might be @TPOFF in Sun ld. */
8772 else
8783 else
8793 }
8796 }
8797 \f
8798 /* Split one or more DImode RTL references into pairs of SImode
8799 references. The RTL can be REG, offsettable MEM, integer constant, or
8800 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8801 split and "num" is its length. lo_half and hi_half are output arrays
8802 that parallel "operands". */
8804 void
8806 {
8808 {
8811 /* simplify_subreg refuse to split volatile memory addresses,
8812 but we still have to handle it. */
8814 {
8817 }
8818 else
8819 {
8826 }
8827 }
8828 }
8829 /* Split one or more TImode RTL references into pairs of DImode
8830 references. The RTL can be REG, offsettable MEM, integer constant, or
8831 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8832 split and "num" is its length. lo_half and hi_half are output arrays
8833 that parallel "operands". */
8835 void
8837 {
8839 {
8842 /* simplify_subreg refuse to split volatile memory addresses, but we
8843 still have to handle it. */
8845 {
8848 }
8849 else
8850 {
8853 }
8854 }
8855 }
8856 \f
8857 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8858 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8859 is the expression of the binary operation. The output may either be
8860 emitted here, or returned to the caller, like all output_* functions.
8862 There is no guarantee that the operands are the same mode, as they
8863 might be within FLOAT or FLOAT_EXTEND expressions. */
8865 #ifndef SYSV386_COMPAT
8866 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8867 wants to fix the assemblers because that causes incompatibility
8868 with gcc. No-one wants to fix gcc because that causes
8869 incompatibility with assemblers... You can use the option of
8870 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8871 #define SYSV386_COMPAT 1
8872 #endif
8876 {
8882 #ifdef ENABLE_CHECKING
8883 /* Even if we do not want to check the inputs, this documents input
8884 constraints. Which helps in understanding the following code. */
8894 else
8896 #endif
8899 {
8904 else
8913 else
8922 else
8931 else
8938 }
8941 {
8945 else
8948 }
8952 {
8956 {
8960 }
8962 /* know operands[0] == operands[1]. */
8965 {
8968 }
8971 {
8973 /* How is it that we are storing to a dead operand[2]?
8974 Well, presumably operands[1] is dead too. We can't
8975 store the result to st(0) as st(0) gets popped on this
8976 instruction. Instead store to operands[2] (which I
8977 think has to be st(1)). st(1) will be popped later.
8978 gcc <= 2.8.1 didn't have this check and generated
8979 assembly code that the Unixware assembler rejected. */
8981 else
8984 }
8988 else
8995 {
8998 }
9001 {
9004 }
9007 {
9008 #if SYSV386_COMPAT
9009 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9010 derived assemblers, confusingly reverse the direction of
9011 the operation for fsub{r} and fdiv{r} when the
9012 destination register is not st(0). The Intel assembler
9013 doesn't have this brain damage. Read !SYSV386_COMPAT to
9014 figure out what the hardware really does. */
9017 else
9019 #else
9021 /* As above for fmul/fadd, we can't store to st(0). */
9023 else
9025 #endif
9027 }
9030 {
9031 #if SYSV386_COMPAT
9034 else
9036 #else
9039 else
9041 #endif
9043 }
9046 {
9049 else
9052 }
9054 {
9055 #if SYSV386_COMPAT
9057 #else
9059 #endif
9060 }
9061 else
9062 {
9063 #if SYSV386_COMPAT
9065 #else
9067 #endif
9068 }
9073 }
9077 }
9079 /* Return needed mode for entity in optimize_mode_switching pass. */
9081 int
9083 {
9086 /* The mode UNINITIALIZED is used to store control word after a
9087 function call or ASM pattern. The mode ANY specify that function
9088 has no requirements on the control word and make no changes in the
9089 bits we are interested in. */
9103 {
9126 }
9129 }
9131 /* Output code to initialize control word copies used by trunc?f?i and
9132 rounding patterns. CURRENT_MODE is set to current control word,
9133 while NEW_MODE is set to new control word. */
9135 void
9137 {
9139 rtx new_mode;
9149 {
9151 {
9153 /* round toward zero (truncate) */
9159 /* round down toward -oo */
9166 /* round up toward +oo */
9173 /* mask precision exception for nearbyint() */
9180 }
9181 }
9182 else
9183 {
9185 {
9187 /* round toward zero (truncate) */
9193 /* round down toward -oo */
9199 /* round up toward +oo */
9205 /* mask precision exception for nearbyint() */
9212 }
9213 }
9219 }
9221 /* Output code for INSN to convert a float to a signed int. OPERANDS
9222 are the insn operands. The output may be [HSD]Imode and the input
9223 operand may be [SDX]Fmode. */
9227 {
9232 /* Jump through a hoop or two for DImode, since the hardware has no
9233 non-popping instruction. We used to do this a different way, but
9234 that was somewhat fragile and broke with post-reload splitters. */
9243 else
9244 {
9249 else
9253 }
9256 }
9258 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9259 have the values zero or one, indicates the ffreep insn's operand
9260 from the OPERANDS array. */
9264 {
9266 #if HAVE_AS_IX86_FFREEP
9268 #else
9269 {
9277 }
9278 #endif
9281 }
9284 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9285 should be used. UNORDERED_P is true when fucom should be used. */
9289 {
9295 {
9298 }
9299 else
9300 {
9303 }
9306 {
9310 else
9312 else
9315 else
9317 }
9324 {
9326 {
9329 }
9330 else
9332 }
9335 && stack_top_dies
9338 {
9339 /* If both the top of the 387 stack dies, and the other operand
9340 is also a stack register that dies, then this must be a
9341 `fcompp' float compare */
9344 {
9345 /* There is no double popping fcomi variant. Fortunately,
9346 eflags is immune from the fstp's cc clobbering. */
9349 else
9352 }
9353 else
9354 {
9357 else
9359 }
9360 }
9361 else
9362 {
9363 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9366 {
9374 NULL,
9375 NULL,
9382 NULL,
9383 NULL,
9384 NULL,
9385 NULL
9386 };
9401 }
9402 }
9404 void
9406 {
9409 #ifdef ASM_QUAD
9412 #else
9414 #endif
9417 }
9419 void
9421 {
9424 #ifdef ASM_QUAD
9427 #else
9429 #endif
9430 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
9436 #if TARGET_MACHO
9438 {
9442 }
9443 #endif
9444 else
9447 }
9448 \f
9449 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9450 for the target. */
9452 void
9454 {
9455 rtx tmp;
9457 /* We play register width games, which are only valid after reload. */
9460 /* Avoid HImode and its attendant prefix byte. */
9466 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
9468 {
9471 }
9474 }
9476 /* X is an unchanging MEM. If it is a constant pool reference, return
9477 the constant pool rtx, else NULL. */
9479 rtx
9481 {
9488 }
9490 void
9492 {
9501 {
9504 {
9509 }
9510 }
9514 {
9517 {
9525 }
9526 }
9529 {
9531 {
9532 #if TARGET_MACHO
9534 {
9535 rtx temp = ((reload_in_progress
9542 }
9547 #endif
9548 }
9549 else
9550 {
9554 {
9559 }
9560 }
9561 }
9562 else
9563 {
9574 /* Force large constants in 64bit compilation into register
9575 to get them CSEed. */
9584 {
9585 /* If we are loading a floating point constant to a register,
9586 force the value to memory now, since we'll get better code
9587 out the back end. */
9590 ;
9592 {
9595 {
9600 }
9601 }
9602 }
9603 }
9606 }
9608 void
9610 {
9613 /* Force constants other than zero into memory. We do not know how
9614 the instructions used to build constants modify the upper 64 bits
9615 of the register, once we have that information we may be able
9616 to handle some of them more efficiently. */
9623 /* Make operand1 a register if it isn't already. */
9627 {
9630 }
9633 }
9635 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
9636 straight to ix86_expand_vector_move. */
9637 /* Code generation for scalar reg-reg moves of single and double precision data:
9638 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
9639 movaps reg, reg
9640 else
9641 movss reg, reg
9642 if (x86_sse_partial_reg_dependency == true)
9643 movapd reg, reg
9644 else
9645 movsd reg, reg
9647 Code generation for scalar loads of double precision data:
9648 if (x86_sse_split_regs == true)
9649 movlpd mem, reg (gas syntax)
9650 else
9651 movsd mem, reg
9653 Code generation for unaligned packed loads of single precision data
9654 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
9655 if (x86_sse_unaligned_move_optimal)
9656 movups mem, reg
9658 if (x86_sse_partial_reg_dependency == true)
9659 {
9660 xorps reg, reg
9661 movlps mem, reg
9662 movhps mem+8, reg
9663 }
9664 else
9665 {
9666 movlps mem, reg
9667 movhps mem+8, reg
9668 }
9670 Code generation for unaligned packed loads of double precision data
9671 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
9672 if (x86_sse_unaligned_move_optimal)
9673 movupd mem, reg
9675 if (x86_sse_split_regs == true)
9676 {
9677 movlpd mem, reg
9678 movhpd mem+8, reg
9679 }
9680 else
9681 {
9682 movsd mem, reg
9683 movhpd mem+8, reg
9684 }
9685 */
9687 void
9689 {
9696 {
9697 /* If we're optimizing for size, movups is the smallest. */
9699 {
9704 }
9706 /* ??? If we have typed data, then it would appear that using
9707 movdqu is the only way to get unaligned data loaded with
9708 integer type. */
9710 {
9715 }
9718 {
9719 rtx zero;
9722 {
9727 }
9729 /* When SSE registers are split into halves, we can avoid
9730 writing to the top half twice. */
9732 {
9735 }
9736 else
9737 {
9738 /* ??? Not sure about the best option for the Intel chips.
9739 The following would seem to satisfy; the register is
9740 entirely cleared, breaking the dependency chain. We
9741 then store to the upper half, with a dependency depth
9742 of one. A rumor has it that Intel recommends two movsd
9743 followed by an unpacklpd, but this is unconfirmed. And
9744 given that the dependency depth of the unpacklpd would
9745 still be one, I'm not sure why this would be better. */
9747 }
9753 }
9754 else
9755 {
9757 {
9762 }
9766 else
9775 }
9776 }
9778 {
9779 /* If we're optimizing for size, movups is the smallest. */
9781 {
9786 }
9788 /* ??? Similar to above, only less clear because of quote
9789 typeless stores unquote. */
9792 {
9797 }
9800 {
9805 }
9806 else
9807 {
9814 }
9815 }
9816 else
9818 }
9820 /* Expand a push in MODE. This is some mode for which we do not support
9821 proper push instructions, at least from the registers that we expect
9822 the value to live in. */
9824 void
9826 {
9827 rtx tmp;
9837 }
9839 /* Helper function of ix86_fixup_binary_operands to canonicalize
9840 operand order. Returns true if the operands should be swapped. */
9842 static bool
9844 rtx operands[])
9845 {
9850 /* If the operation is not commutative, we can't do anything. */
9854 /* Highest priority is that src1 should match dst. */
9860 /* Next highest priority is that immediate constants come second. */
9866 /* Lowest priority is that memory references should come second. */
9873 }
9876 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
9877 destination to use for the operation. If different from the true
9878 destination in operands[0], a copy operation will be required. */
9880 rtx
9882 rtx operands[])
9883 {
9888 /* Canonicalize operand order. */
9890 {
9894 }
9896 /* Both source operands cannot be in memory. */
9898 {
9899 /* Optimization: Only read from memory once. */
9901 {
9904 }
9905 else
9907 }
9909 /* If the destination is memory, and we do not have matching source
9910 operands, do things in registers. */
9914 /* Source 1 cannot be a constant. */
9918 /* Source 1 cannot be a non-matching memory. */
9925 }
9927 /* Similarly, but assume that the destination has already been
9928 set up properly. */
9930 void
9933 {
9936 }
9938 /* Attempt to expand a binary operator. Make the expansion closer to the
9939 actual machine, then just general_operand, which will allow 3 separate
9940 memory references (one output, two input) in a single insn. */
9942 void
9944 rtx operands[])
9945 {
9952 /* Emit the instruction. */
9956 {
9957 /* Reload doesn't know about the flags register, and doesn't know that
9958 it doesn't want to clobber it. We can only do this with PLUS. */
9961 }
9962 else
9963 {
9966 }
9968 /* Fix up the destination if needed. */
9971 }
9973 /* Return TRUE or FALSE depending on whether the binary operator meets the
9974 appropriate constraints. */
9976 int
9979 {
9984 /* Both source operands cannot be in memory. */
9988 /* Canonicalize operand order for commutative operators. */
9990 {
9994 }
9996 /* If the destination is memory, we must have a matching source operand. */
10000 /* Source 1 cannot be a constant. */
10004 /* Source 1 cannot be a non-matching memory. */
10009 }
10011 /* Attempt to expand a unary operator. Make the expansion closer to the
10012 actual machine, then just general_operand, which will allow 2 separate
10013 memory references (one output, one input) in a single insn. */
10015 void
10017 rtx operands[])
10018 {
10025 /* If the destination is memory, and we do not have matching source
10026 operands, do things in registers. */
10029 {
10032 else
10034 }
10036 /* When source operand is memory, destination must match. */
10040 /* Emit the instruction. */
10044 {
10045 /* Reload doesn't know about the flags register, and doesn't know that
10046 it doesn't want to clobber it. */
10049 }
10050 else
10051 {
10054 }
10056 /* Fix up the destination if needed. */
10059 }
10061 /* Return TRUE or FALSE depending on whether the unary operator meets the
10062 appropriate constraints. */
10064 int
10068 {
10069 /* If one of operands is memory, source and destination must match. */
10075 }
10077 /* Post-reload splitter for converting an SF or DFmode value in an
10078 SSE register into an unsigned SImode. */
10080 void
10082 {
10093 /* Load up the value into the low element. We must ensure that the other
10094 elements are valid floats -- zero is the easiest such value. */
10096 {
10099 else
10101 }
10102 else
10103 {
10108 else
10110 }
10130 else
10135 }
10137 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10138 Expects the 64-bit DImode to be supplied in a pair of integral
10139 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10140 -mfpmath=sse, !optimize_size only. */
10142 void
10144 {
10148 rtx x;
10154 {
10157 }
10158 else
10159 {
10163 }
10171 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10174 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10175 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10176 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10177 (0x1.0p84 + double(fp_value_hi_xmm)).
10178 Note these exponents differ by 32. */
10182 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10183 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10192 /* Add the upper and lower DFmode values together. */
10195 else
10196 {
10200 }
10203 }
10205 /* Convert an unsigned SImode value into a DFmode. Only currently used
10206 for SSE, but applicable anywhere. */
10208 void
10210 {
10211 REAL_VALUE_TYPE TWO31r;
10226 }
10228 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10229 32-bit mode; otherwise we have a direct convert instruction. */
10231 void
10233 {
10234 REAL_VALUE_TYPE TWO32r;
10252 }
10254 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10255 For x86_32, -mfpmath=sse, !optimize_size only. */
10256 void
10258 {
10259 REAL_VALUE_TYPE ONE16r;
10278 }
10280 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10281 then replicate the value for all elements of the vector
10282 register. */
10284 rtx
10286 {
10287 rtvec v;
10289 {
10293 else
10301 else
10307 }
10308 }
10310 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
10311 Create a mask for the sign bit in MODE for an SSE register. If VECT is
10312 true, then replicate the mask for all elements of the vector register.
10313 If INVERT is true, then create a mask excluding the sign bit. */
10315 rtx
10317 {
10321 rtx v;
10322 rtx mask;
10324 /* Find the sign bit, sign extended to 2*HWI. */
10329 else
10335 /* Force this value into the low part of a fp vector constant. */
10342 }
10344 /* Generate code for floating point ABS or NEG. */
10346 void
10348 rtx operands[])
10349 {
10357 {
10360 }
10364 /* NEG and ABS performed with SSE use bitwise mask operations.
10365 Create the appropriate mask now. */
10368 else
10374 /* If the destination is memory, and we don't have matching source
10375 operands or we're using the x87, do things in registers. */
10378 {
10381 else
10383 }
10388 {
10392 }
10393 else
10394 {
10398 {
10403 }
10404 else
10406 }
10410 }
10412 /* Expand a copysign operation. Special case operand 0 being a constant. */
10414 void
10416 {
10428 {
10429 rtvec v;
10436 else
10437 {
10441 else
10444 }
10450 else
10452 }
10453 else
10454 {
10460 else
10462 }
10463 }
10465 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
10466 be a constant, and so has already been expanded into a vector constant. */
10468 void
10470 {
10487 {
10490 }
10491 }
10493 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
10494 so we have to do two masks. */
10496 void
10498 {
10513 {
10514 /* Shouldn't happen often (it's useless, obviously), but when it does
10515 we'd generate incorrect code if we continue below. */
10518 }
10521 {
10532 }
10533 else
10534 {
10536 {
10538 }
10540 {
10544 }
10548 {
10551 }
10553 {
10558 }
10560 }
10564 }
10566 /* Return TRUE or FALSE depending on whether the first SET in INSN
10567 has source and destination with matching CC modes, and that the
10568 CC mode is at least as constrained as REQ_MODE. */
10570 int
10572 {
10573 rtx set;
10584 {
10594 /* FALLTHRU */
10598 /* FALLTHRU */
10602 /* FALLTHRU */
10608 }
10611 }
10613 /* Generate insn patterns to do an integer compare of OPERANDS. */
10615 static rtx
10617 {
10624 /* This is very simple, but making the interface the same as in the
10625 FP case makes the rest of the code easier. */
10629 /* Return the test that should be put into the flags user, i.e.
10630 the bcc, scc, or cmov instruction. */
10632 }
10634 /* Figure out whether to use ordered or unordered fp comparisons.
10635 Return the appropriate mode to use. */
10637 enum machine_mode
10639 {
10640 /* ??? In order to make all comparisons reversible, we do all comparisons
10641 non-trapping when compiling for IEEE. Once gcc is able to distinguish
10642 all forms trapping and nontrapping comparisons, we can make inequality
10643 comparisons trapping again, since it results in better code when using
10644 FCOM based compares. */
10646 }
10648 enum machine_mode
10650 {
10654 {
10655 /* Only zero flag is needed. */
10659 /* Codes needing carry flag. */
10665 /* Codes possibly doable only with sign flag when
10666 comparing against zero. */
10671 else
10672 /* For other cases Carry flag is not required. */
10674 /* Codes doable only with sign flag when comparing
10675 against zero, but we miss jump instruction for it
10676 so we need to use relational tests against overflow
10677 that thus needs to be zero. */
10682 else
10684 /* strcmp pattern do (use flags) and combine may ask us for proper
10685 mode. */
10690 }
10691 }
10693 /* Return the fixed registers used for condition codes. */
10695 static bool
10697 {
10701 }
10703 /* If two condition code modes are compatible, return a condition code
10704 mode which is compatible with both. Otherwise, return
10705 VOIDmode. */
10707 static enum machine_mode
10709 {
10721 {
10731 {
10741 }
10745 /* These are only compatible with themselves, which we already
10746 checked above. */
10748 }
10749 }
10751 /* Return true if we should use an FCOMI instruction for this fp comparison. */
10753 int
10755 {
10760 }
10762 /* Swap, force into registers, or otherwise massage the two operands
10763 to a fp comparison. The operands are updated in place; the new
10764 comparison code is returned. */
10766 static enum rtx_code
10768 {
10774 /* All of the unordered compare instructions only work on registers.
10775 The same is true of the fcomi compare instructions. The XFmode
10776 compare instructions require registers except when comparing
10777 against zero or when converting operand 1 from fixed point to
10778 floating point. */
10787 {
10790 }
10791 else
10792 {
10793 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
10794 things around if they appear profitable, otherwise force op0
10795 into a register. */
10801 {
10802 rtx tmp;
10805 }
10811 {
10816 {
10819 }
10820 else
10822 }
10823 }
10825 /* Try to rearrange the comparison to make it cheaper. */
10829 {
10830 rtx tmp;
10835 }
10840 }
10842 /* Convert comparison codes we use to represent FP comparison to integer
10843 code that will result in proper branch. Return UNKNOWN if no such code
10844 is available. */
10846 enum rtx_code
10848 {
10850 {
10873 }
10874 }
10876 /* Split comparison code CODE into comparisons we can do using branch
10877 instructions. BYPASS_CODE is comparison code for branch that will
10878 branch around FIRST_CODE and SECOND_CODE. If some of branches
10879 is not required, set value to UNKNOWN.
10880 We never require more than two branches. */
10882 void
10886 {
10891 /* The fcomi comparison sets flags as follows:
10893 cmp ZF PF CF
10894 > 0 0 0
10895 < 0 0 1
10896 = 1 0 0
10897 un 1 1 1 */
10900 {
10936 }
10938 {
10941 }
10942 }
10944 /* Return cost of comparison done fcom + arithmetics operations on AX.
10945 All following functions do use number of instructions as a cost metrics.
10946 In future this should be tweaked to compute bytes for optimize_size and
10947 take into account performance of various instructions on various CPUs. */
10948 static int
10950 {
10953 /* The cost of code output by ix86_expand_fp_compare. */
10955 {
10978 }
10979 }
10981 /* Return cost of comparison done using fcomi operation.
10982 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10983 static int
10985 {
10987 /* Return arbitrarily high cost when instruction is not supported - this
10988 prevents gcc from using it. */
10993 }
10995 /* Return cost of comparison done using sahf operation.
10996 See ix86_fp_comparison_arithmetics_cost for the metrics. */
10997 static int
10999 {
11001 /* Return arbitrarily high cost when instruction is not preferred - this
11002 avoids gcc from using it. */
11007 }
11009 /* Compute cost of the comparison done using any method.
11010 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11011 static int
11013 {
11026 }
11028 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11030 static rtx
11033 {
11049 /* Do fcomi/sahf based test when profitable. */
11054 {
11056 {
11059 tmp);
11061 }
11062 else
11063 {
11070 }
11072 /* The FP codes work out to act like unsigned. */
11078 const0_rtx);
11082 const0_rtx);
11083 }
11084 else
11085 {
11086 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11093 /* In the unordered case, we have to check C2 for NaN's, which
11094 doesn't happen to work out to anything nice combination-wise.
11095 So do some bit twiddling on the value we've got in AH to come
11096 up with an appropriate set of condition codes. */
11100 {
11104 {
11107 }
11108 else
11109 {
11115 }
11120 {
11125 }
11126 else
11127 {
11130 }
11135 {
11138 }
11139 else
11140 {
11145 }
11150 {
11156 }
11157 else
11158 {
11161 }
11166 {
11171 }
11172 else
11173 {
11177 }
11182 {
11187 }
11188 else
11189 {
11192 }
11206 }
11207 }
11209 /* Return the test that should be put into the flags user, i.e.
11210 the bcc, scc, or cmov instruction. */
11213 const0_rtx);
11214 }
11216 rtx
11218 {
11229 {
11232 }
11236 else
11240 }
11242 /* Return true if the CODE will result in nontrivial jump sequence. */
11243 bool
11245 {
11251 }
11253 void
11255 {
11256 rtx tmp;
11258 /* If we have emitted a compare insn, go straight to simple.
11259 ix86_expand_compare won't emit anything if ix86_compare_emitted
11260 is non NULL. */
11265 {
11269 simple:
11273 pc_rtx);
11280 {
11281 rtvec vec;
11290 /* Check whether we will use the natural sequence with one jump. If
11291 so, we can expand jump early. Otherwise delay expansion by
11292 creating compound insn to not confuse optimizers. */
11295 {
11299 }
11300 else
11301 {
11306 pc_rtx);
11321 }
11323 }
11329 /* Expand DImode branch into multiple compare+branch. */
11330 {
11336 {
11341 }
11343 {
11347 }
11348 else
11349 {
11353 }
11355 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
11356 avoid two branches. This costs one extra insn, so disable when
11357 optimizing for size. */
11360 && (!optimize_size
11362 {
11382 }
11384 /* Otherwise, if we are doing less-than or greater-or-equal-than,
11385 op1 is a constant and the low word is zero, then we can just
11386 examine the high word. */
11390 {
11398 }
11400 /* Otherwise, we need two or three jumps. */
11409 {
11423 }
11425 /*
11426 * a < b =>
11427 * if (hi(a) < hi(b)) goto true;
11428 * if (hi(a) > hi(b)) goto false;
11429 * if (lo(a) < lo(b)) goto true;
11430 * false:
11431 */
11448 }
11452 }
11453 }
11455 /* Split branch based on floating point condition. */
11456 void
11459 {
11462 rtx condition;
11464 rtx i;
11467 {
11472 }
11477 /* Remove pushed operand from stack. */
11482 {
11483 /* Distribute the probabilities across the jumps.
11484 Assume the BYPASS and SECOND to be always test
11485 for UNORDERED. */
11488 /* Value of 1 is low enough to make no need for probability
11489 to be updated. Later we may run some experiments and see
11490 if unordered values are more frequent in practice. */
11495 }
11497 {
11502 bypass,
11504 label),
11505 pc_rtx)));
11511 }
11522 {
11526 target2)));
11532 }
11535 }
11537 int
11539 {
11556 {
11561 {
11566 }
11572 else
11574 }
11576 /* Attach a REG_EQUAL note describing the comparison result. */
11578 {
11583 }
11586 }
11588 /* Expand comparison setting or clearing carry flag. Return true when
11589 successful and set pop for the operation. */
11590 static bool
11592 {
11596 /* Do not handle DImode compares that go through special path. Also we can't
11597 deal with FP compares yet. This is possible to add. */
11601 {
11605 /* Shortcut: following common codes never translate into carry flag compares. */
11610 /* These comparisons require zero flag; swap operands so they won't. */
11613 {
11618 }
11620 /* Try to expand the comparison and verify that we end up with carry flag
11621 based comparison. This is fails to be true only when we decide to expand
11622 comparison using arithmetic that is not too common scenario. */
11634 else
11641 }
11645 {
11650 /* Convert a==0 into (unsigned)a<1. */
11659 /* Convert a>b into b<a or a>=b-1. */
11663 {
11665 /* Bail out on overflow. We still can swap operands but that
11666 would force loading of the constant into register. */
11671 }
11672 else
11673 {
11678 }
11681 /* Convert a>=0 into (unsigned)a<0x80000000. */
11699 }
11700 /* Swapping operands may cause constant to appear as first operand. */
11702 {
11706 }
11712 }
11714 int
11716 {
11734 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
11735 HImode insns, we'd be swallowed in word prefix ops. */
11741 {
11745 HOST_WIDE_INT diff;
11748 /* Sign bit compares are better done using shifts than we do by using
11749 sbb. */
11753 {
11754 /* Detect overlap between destination and compare sources. */
11758 {
11765 {
11768 }
11770 /* To simplify rest of code, restrict to the GEU case. */
11772 {
11778 }
11779 else
11780 {
11783 reverse_condition_maybe_unordered
11785 else
11787 }
11796 else
11798 }
11799 else
11800 {
11803 else
11804 {
11809 }
11812 }
11815 {
11816 /*
11817 * cmpl op0,op1
11818 * sbbl dest,dest
11819 * [addl dest, ct]
11820 *
11821 * Size 5 - 8.
11822 */
11827 }
11829 {
11830 /*
11831 * cmpl op0,op1
11832 * sbbl dest,dest
11833 * orl $ct, dest
11834 *
11835 * Size 8.
11836 */
11840 }
11842 {
11843 /*
11844 * cmpl op0,op1
11845 * sbbl dest,dest
11846 * notl dest
11847 * [addl dest, cf]
11848 *
11849 * Size 8 - 11.
11850 */
11856 }
11857 else
11858 {
11859 /*
11860 * cmpl op0,op1
11861 * sbbl dest,dest
11862 * [notl dest]
11863 * andl cf - ct, dest
11864 * [addl dest, ct]
11865 *
11866 * Size 8 - 11.
11867 */
11870 {
11874 }
11884 }
11890 }
11893 {
11894 HOST_WIDE_INT tmp;
11898 {
11899 /* We may be reversing unordered compare to normal compare, that
11900 is not valid in general (we may convert non-trapping condition
11901 to trapping one), however on i386 we currently emit all
11902 comparisons unordered. */
11905 }
11906 else
11907 {
11910 }
11911 }
11916 {
11921 {
11926 }
11927 }
11929 /* Optimize dest = (op0 < 0) ? -1 : cf. */
11933 {
11934 /* If lea code below could be used, only optimize
11935 if it results in a 2 insn sequence. */
11941 {
11942 /*
11943 * notl op1 (if necessary)
11944 * sarl $31, op1
11945 * orl cf, op1
11946 */
11948 {
11952 }
11964 }
11965 }
11973 {
11974 /*
11975 * xorl dest,dest
11976 * cmpl op1,op2
11977 * setcc dest
11978 * lea cf(dest*(ct-cf)),dest
11979 *
11980 * Size 14.
11981 *
11982 * This also catches the degenerate setcc-only case.
11983 */
11985 rtx tmp;
11992 /* On x86_64 the lea instruction operates on Pmode, so we need
11993 to get arithmetics done in proper mode to match. */
11996 else
11997 {
11998 rtx out1;
12001 nops++;
12003 {
12005 nops++;
12006 }
12007 }
12009 {
12011 nops++;
12012 }
12014 {
12017 else
12019 }
12024 }
12026 /*
12027 * General case: Jumpful:
12028 * xorl dest,dest cmpl op1, op2
12029 * cmpl op1, op2 movl ct, dest
12030 * setcc dest jcc 1f
12031 * decl dest movl cf, dest
12032 * andl (cf-ct),dest 1:
12033 * addl ct,dest
12034 *
12035 * Size 20. Size 14.
12036 *
12037 * This is reasonably steep, but branch mispredict costs are
12038 * high on modern cpus, so consider failing only if optimizing
12039 * for space.
12040 */
12044 {
12046 {
12050 /* We may be reversing unordered compare to normal compare,
12051 that is not valid in general (we may convert non-trapping
12052 condition to trapping one), however on i386 we currently
12053 emit all comparisons unordered. */
12055 else
12056 {
12060 }
12061 }
12064 {
12065 /* notl op1 (if needed)
12066 sarl $31, op1
12067 andl (cf-ct), op1
12068 addl ct, op1
12070 For x < 0 (resp. x <= -1) there will be no notl,
12071 so if possible swap the constants to get rid of the
12072 complement.
12073 True/false will be -1/0 while code below (store flag
12074 followed by decrement) is 0/-1, so the constants need
12075 to be exchanged once more. */
12078 {
12081 }
12082 else
12083 {
12087 }
12091 }
12092 else
12093 {
12099 }
12111 }
12112 }
12115 {
12116 /* Try a few things more with specific constants and a variable. */
12118 optab op;
12124 /* If one of the two operands is an interesting constant, load a
12125 constant with the above and mask it in with a logical operation. */
12128 {
12134 else
12136 }
12138 {
12144 else
12146 }
12147 else
12154 /* Recurse to get the constant loaded. */
12158 /* Mask in the interesting variable. */
12160 OPTAB_WIDEN);
12165 }
12167 /*
12168 * For comparison with above,
12169 *
12170 * movl cf,dest
12171 * movl ct,tmp
12172 * cmpl op1,op2
12173 * cmovcc tmp,dest
12174 *
12175 * Size 15.
12176 */
12184 {
12188 }
12190 {
12194 }
12213 bypass_test,
12219 second_test,
12224 }
12226 /* Swap, force into registers, or otherwise massage the two operands
12227 to an sse comparison with a mask result. Thus we differ a bit from
12228 ix86_prepare_fp_compare_args which expects to produce a flags result.
12230 The DEST operand exists to help determine whether to commute commutative
12231 operators. The POP0/POP1 operands are updated in place. The new
12232 comparison code is returned, or UNKNOWN if not implementable. */
12234 static enum rtx_code
12237 {
12238 rtx tmp;
12241 {
12244 /* We have no LTGT as an operator. We could implement it with
12245 NE & ORDERED, but this requires an extra temporary. It's
12246 not clear that it's worth it. */
12253 /* These are supported directly. */
12260 /* For commutative operators, try to canonicalize the destination
12261 operand to be first in the comparison - this helps reload to
12262 avoid extra moves. */
12265 /* FALLTHRU */
12271 /* These are not supported directly. Swap the comparison operands
12272 to transform into something that is supported. */
12281 }
12284 }
12286 /* Detect conditional moves that exactly match min/max operational
12287 semantics. Note that this is IEEE safe, as long as we don't
12288 interchange the operands.
12290 Returns FALSE if this conditional move doesn't match a MIN/MAX,
12291 and TRUE if the operation is successful and instructions are emitted. */
12293 static bool
12296 {
12299 rtx tmp;
12302 ;
12304 {
12308 }
12309 else
12316 else
12321 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
12322 but MODE may be a vector mode and thus not appropriate. */
12324 {
12326 rtvec v;
12331 }
12332 else
12333 {
12336 }
12340 }
12342 /* Expand an sse vector comparison. Return the register with the result. */
12344 static rtx
12347 {
12349 rtx x;
12364 }
12366 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
12367 operations. This is used for both scalar and vector conditional moves. */
12369 static void
12371 {
12376 {
12380 }
12382 {
12387 }
12388 else
12389 {
12396 else
12408 }
12409 }
12411 /* Expand a floating-point conditional move. Return true if successful. */
12413 int
12415 {
12421 {
12424 /* Since we've no cmove for sse registers, don't force bad register
12425 allocation just to gain access to it. Deny movcc when the
12426 comparison mode doesn't match the move mode. */
12448 }
12450 /* The floating point conditional move instructions don't directly
12451 support conditions resulting from a signed integer comparison. */
12455 /* The floating point conditional move instructions don't directly
12456 support signed integer comparisons. */
12459 {
12467 }
12469 {
12473 }
12475 {
12479 }
12494 }
12496 /* Expand a floating-point vector conditional move; a vcond operation
12497 rather than a movcc operation. */
12499 bool
12501 {
12503 rtx cmp;
12518 }
12520 /* Expand a signed integral vector conditional move. */
12522 bool
12524 {
12533 /* Canonicalize the comparison to EQ, GT, GTU. */
12535 {
12552 /* FALLTHRU */
12562 }
12564 /* Unsigned parallel compare is not supported by the hardware. Play some
12565 tricks to turn this into a signed comparison against 0. */
12567 {
12571 {
12573 {
12576 /* Perform a parallel modulo subtraction. */
12580 /* Extract the original sign bit of op0. */
12588 /* XOR it back into the result of the subtraction. This results
12589 in the sign bit set iff we saw unsigned underflow. */
12594 }
12599 /* Perform a parallel unsigned saturating subtraction. */
12610 }
12614 }
12622 }
12624 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
12625 true if we should do zero extension, else sign extension. HIGH_P is
12626 true if we want the N/2 high elements, else the low elements. */
12628 void
12630 {
12636 {
12640 else
12646 else
12652 else
12657 }
12663 else
12668 }
12670 /* Expand conditional increment or decrement using adb/sbb instructions.
12671 The default case using setcc followed by the conditional move can be
12672 done by generic code. */
12673 int
12675 {
12677 rtx compare_op;
12692 {
12695 }
12698 {
12702 reverse_condition_maybe_unordered
12704 else
12706 }
12709 /* Construct either adc or sbb insn. */
12711 {
12713 {
12728 }
12729 }
12730 else
12731 {
12733 {
12748 }
12749 }
12751 }
12754 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
12755 works for floating pointer parameters and nonoffsetable memories.
12756 For pushes, it returns just stack offsets; the values will be saved
12757 in the right order. Maximally three parts are generated. */
12759 static int
12761 {
12766 else
12772 /* Optimize constant pool reference to immediates. This is used by fp
12773 moves, that force all constants to memory to allow combining. */
12775 {
12779 }
12782 {
12783 /* The only non-offsetable memories we handle are pushes. */
12792 }
12795 {
12797 /* Caution: if we looked through a constant pool memory above,
12798 the operand may actually have a different mode now. That's
12799 ok, since we want to pun this all the way back to an integer. */
12803 }
12806 {
12809 else
12810 {
12812 {
12818 }
12820 {
12826 }
12828 {
12829 REAL_VALUE_TYPE r;
12834 {
12844 }
12847 }
12848 else
12850 }
12851 }
12852 else
12853 {
12857 {
12860 {
12864 }
12866 {
12870 }
12872 {
12873 REAL_VALUE_TYPE r;
12879 /* Do not use shift by 32 to avoid warning on 32bit systems. */
12882 = gen_int_mode
12885 DImode);
12886 else
12893 = gen_int_mode
12896 DImode);
12897 else
12899 }
12900 else
12902 }
12903 }
12906 }
12908 /* Emit insns to perform a move or push of DI, DF, and XF values.
12909 Return false when normal moves are needed; true when all required
12910 insns have been emitted. Operands 2-4 contain the input values
12911 int the correct order; operands 5-7 contain the output values. */
12913 void
12915 {
12922 /* The DFmode expanders may ask us to move double.
12923 For 64bit target this is single move. By hiding the fact
12924 here we simplify i386.md splitters. */
12926 {
12927 /* Optimize constant pool reference to immediates. This is used by
12928 fp moves, that force all constants to memory to allow combining. */
12935 {
12938 }
12939 else
12944 }
12946 /* The only non-offsettable memory we handle is push. */
12949 else
12956 /* When emitting push, take care for source operands on the stack. */
12959 {
12965 }
12967 /* We need to do copy in the right order in case an address register
12968 of the source overlaps the destination. */
12970 {
12972 collisions++;
12974 collisions++;
12977 collisions++;
12979 /* Collision in the middle part can be handled by reordering. */
12982 {
12983 rtx tmp;
12986 }
12988 /* If there are more collisions, we can't handle it by reordering.
12989 Do an lea to the last part and use only one colliding move. */
12991 {
12992 rtx base;
12998 /* Handle the case when the last part isn't valid for lea.
12999 Happens in 64-bit mode storing the 12-byte XFmode. */
13010 }
13011 }
13014 {
13016 {
13018 {
13022 }
13023 }
13024 else
13025 {
13026 /* In 64bit mode we don't have 32bit push available. In case this is
13027 register, it is OK - we will just use larger counterpart. We also
13028 retype memory - these comes from attempt to avoid REX prefix on
13029 moving of second half of TFmode value. */
13031 {
13033 {
13044 }
13048 }
13049 }
13053 }
13055 /* Choose correct order to not overwrite the source before it is copied. */
13063 {
13065 {
13072 }
13073 else
13074 {
13079 }
13080 }
13081 else
13082 {
13084 {
13091 }
13092 else
13093 {
13098 }
13099 }
13101 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
13103 {
13107 {
13116 }
13125 }
13133 }
13135 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
13136 left shift by a constant, either using a single shift or
13137 a sequence of add instructions. */
13139 static void
13141 {
13143 {
13145 ? gen_addsi3
13147 }
13150 {
13153 {
13155 ? gen_addsi3
13157 }
13158 }
13159 else
13161 ? gen_ashlsi3
13163 }
13165 void
13167 {
13173 {
13178 {
13184 }
13185 else
13186 {
13190 ? gen_x86_shld_1
13193 }
13195 }
13200 {
13201 /* Assuming we've chosen a QImode capable registers, then 1 << N
13202 can be done with two 32/64-bit shifts, no branches, no cmoves. */
13204 {
13220 }
13222 /* Otherwise, we can get the same results by manually performing
13223 a bit extract operation on bit 5/6, and then performing the two
13224 shifts. The two methods of getting 0/1 into low/high are exactly
13225 the same size. Avoiding the shift in the bit extract case helps
13226 pentium4 a bit; no one else seems to care much either way. */
13227 else
13228 {
13229 rtx x;
13233 else
13238 ? gen_lshrsi3
13241 ? gen_andsi3
13245 ? gen_xorsi3
13247 }
13250 ? gen_ashlsi3
13253 ? gen_ashlsi3
13256 }
13259 {
13260 /* For -1 << N, we can avoid the shld instruction, because we
13261 know that we're shifting 0...31/63 ones into a -1. */
13265 else
13267 }
13268 else
13269 {
13275 ? gen_x86_shld_1
13277 }
13282 {
13285 ? gen_x86_shift_adj_1
13287 }
13288 else
13290 }
13292 void
13294 {
13300 {
13305 {
13308 ? gen_ashrsi3
13313 }
13315 {
13319 ? gen_ashrsi3
13324 ? gen_ashrsi3
13327 }
13328 else
13329 {
13333 ? gen_x86_shrd_1
13336 ? gen_ashrsi3
13338 }
13339 }
13340 else
13341 {
13348 ? gen_x86_shrd_1
13351 ? gen_ashrsi3
13355 {
13358 ? gen_ashrsi3
13362 ? gen_x86_shift_adj_1
13364 scratch));
13365 }
13366 else
13368 }
13369 }
13371 void
13373 {
13379 {
13384 {
13390 ? gen_lshrsi3
13393 }
13394 else
13395 {
13399 ? gen_x86_shrd_1
13402 ? gen_lshrsi3
13404 }
13405 }
13406 else
13407 {
13414 ? gen_x86_shrd_1
13417 ? gen_lshrsi3
13420 /* Heh. By reversing the arguments, we can reuse this pattern. */
13422 {
13425 ? gen_x86_shift_adj_1
13427 scratch));
13428 }
13429 else
13431 }
13432 }
13434 /* Predict just emitted jump instruction to be taken with probability PROB. */
13435 static void
13437 {
13444 }
13446 /* Helper function for the string operations below. Dest VARIABLE whether
13447 it is aligned to VALUE bytes. If true, jump to the label. */
13448 static rtx
13450 {
13455 else
13461 else
13464 }
13466 /* Adjust COUNTER by the VALUE. */
13467 static void
13469 {
13472 else
13474 }
13476 /* Zero extend possibly SImode EXP to Pmode register. */
13477 rtx
13479 {
13480 rtx r;
13488 }
13490 /* Divide COUNTREG by SCALE. */
13491 static rtx
13493 {
13494 rtx sc;
13495 rtx piece_size_mask;
13508 }
13510 /* Return mode for the memcpy/memset loop counter. Preffer SImode over DImode
13511 for constant loop counts. */
13513 static enum machine_mode
13515 {
13523 }
13525 /* When SRCPTR is non-NULL, output simple loop to move memory
13526 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
13527 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
13528 equivalent loop to set memory by VALUE (supposed to be in MODE).
13530 The size is rounded down to whole number of chunk size moved at once.
13531 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
13534 static void
13539 {
13544 rtx size;
13545 rtx x_addr;
13546 rtx y_addr;
13555 /* Those two should combine. */
13557 {
13561 }
13571 {
13575 /* When unrolling for chips that reorder memory reads and writes,
13576 we can save registers by using single temporary.
13577 Also using 4 temporaries is overkill in 32bit mode. */
13579 {
13581 {
13583 {
13584 destmem =
13586 srcmem =
13588 }
13590 }
13591 }
13592 else
13593 {
13597 {
13600 {
13601 srcmem =
13603 }
13605 }
13607 {
13609 {
13610 destmem =
13612 }
13614 }
13615 }
13616 }
13617 else
13619 {
13621 destmem =
13624 }
13634 {
13640 else
13642 }
13643 else
13651 {
13656 }
13658 }
13660 /* Output "rep; mov" instruction.
13661 Arguments have same meaning as for previous function */
13662 static void
13665 rtx count,
13667 {
13668 rtx destexp;
13669 rtx srcexp;
13670 rtx countreg;
13672 /* If the size is known, it is shorter to use rep movs. */
13683 {
13690 }
13691 else
13692 {
13695 }
13698 }
13700 /* Output "rep; stos" instruction.
13701 Arguments have same meaning as for previous function */
13702 static void
13704 rtx count,
13706 {
13707 rtx destexp;
13708 rtx countreg;
13715 {
13719 }
13720 else
13723 }
13725 static void
13728 {
13732 }
13734 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
13735 static void
13738 {
13741 {
13746 {
13748 {
13751 }
13752 else
13755 }
13757 {
13760 else
13761 {
13764 }
13766 }
13768 {
13771 }
13773 {
13776 }
13778 {
13781 }
13783 }
13785 {
13791 }
13793 /* When there are stringops, we can cheaply increase dest and src pointers.
13794 Otherwise we save code size by maintaining offset (zero is readily
13795 available from preceding rep operation) and using x86 addressing modes.
13796 */
13798 {
13800 {
13807 }
13809 {
13816 }
13818 {
13825 }
13826 }
13827 else
13828 {
13830 rtx tmp;
13833 {
13844 }
13846 {
13859 }
13861 {
13870 }
13871 }
13872 }
13874 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
13875 static void
13878 {
13879 count =
13885 }
13887 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
13888 static void
13890 {
13891 rtx dest;
13894 {
13899 {
13901 {
13906 }
13907 else
13910 }
13912 {
13914 {
13917 }
13918 else
13919 {
13924 }
13926 }
13928 {
13932 }
13934 {
13938 }
13940 {
13944 }
13946 }
13948 {
13951 }
13953 {
13956 {
13960 }
13961 else
13962 {
13968 }
13971 }
13973 {
13976 {
13979 }
13980 else
13981 {
13985 }
13988 }
13990 {
13996 }
13998 {
14004 }
14006 {
14012 }
14013 }
14015 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
14016 DESIRED_ALIGNMENT. */
14017 static void
14021 {
14023 {
14031 }
14033 {
14041 }
14043 {
14051 }
14053 }
14055 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
14056 DESIRED_ALIGNMENT. */
14057 static void
14060 {
14062 {
14069 }
14071 {
14078 }
14080 {
14087 }
14089 }
14091 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
14092 static enum stringop_alg
14095 {
14101 else
14105 /* rep; movq or rep; movl is the smallest variant. */
14107 {
14110 else
14112 }
14113 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
14114 */
14118 {
14122 {
14125 {
14128 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
14129 last non-libcall inline algorithm. */
14131 {
14132 /* When the current size is best to be copied by a libcall,
14133 but we are still forced to inline, run the heuristic bellow
14134 that will pick code for medium sized blocks. */
14138 }
14139 else
14141 }
14142 }
14144 }
14145 /* When asked to inline the call anyway, try to pick meaningful choice.
14146 We look for maximal size of block that is faster to copy by hand and
14147 take blocks of at most of that size guessing that average size will
14148 be roughly half of the block.
14150 If this turns out to be bad, we might simply specify the preferred
14151 choice in ix86_costs. */
14154 {
14170 }
14172 }
14174 /* Decide on alignment. We know that the operand is already aligned to ALIGN
14175 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
14176 static int
14180 {
14183 {
14194 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14195 copying whole cacheline at once. */
14198 else
14202 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14203 copying whole cacheline at once. */
14206 else
14214 }
14223 }
14225 /* Return the smallest power of 2 greater than VAL. */
14226 static int
14228 {
14233 }
14235 /* Expand string move (memcpy) operation. Use i386 string operations when
14236 profitable. expand_clrmem contains similar code. The code depends upon
14237 architecture, block size and alignment, but always has the same
14238 overall structure:
14240 1) Prologue guard: Conditional that jumps up to epilogues for small
14241 blocks that can be handled by epilogue alone. This is faster but
14242 also needed for correctness, since prologue assume the block is larger
14243 than the desired alignment.
14245 Optional dynamic check for size and libcall for large
14246 blocks is emitted here too, with -minline-stringops-dynamically.
14248 2) Prologue: copy first few bytes in order to get destination aligned
14249 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
14250 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
14251 We emit either a jump tree on power of two sized blocks, or a byte loop.
14253 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
14254 with specified algorithm.
14256 4) Epilogue: code copying tail of the block that is too small to be
14257 handled by main body (or up to size guarded by prologue guard). */
14259 int
14262 {
14263 rtx destreg;
14264 rtx srcreg;
14266 rtx tmp;
14278 /* i386 can do misaligned access on reasonably increased cost. */
14287 /* Step 0: Decide on preferred algorithm, desired alignment and
14288 size of chunks to be copied by main loop. */
14304 {
14324 }
14328 /* Step 1: Prologue guard. */
14330 /* Alignment code needs count to be in register. */
14332 {
14337 }
14340 /* Ensure that alignment prologue won't copy past end of block. */
14342 {
14344 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14345 Make sure it is power of 2. */
14353 ;
14356 else
14358 }
14359 /* Emit code to decide on runtime whether library call or inline should be
14360 used. */
14362 {
14371 }
14373 /* Step 2: Alignment prologue. */
14376 {
14377 /* Except for the first move in epilogue, we no longer know
14378 constant offset in aliasing info. It don't seems to worth
14379 the pain to maintain it for the first move, so throw away
14380 the info early. */
14384 desired_align);
14385 }
14387 {
14391 }
14393 /* Step 3: Main loop. */
14396 {
14409 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
14410 registers for 4 temporaries anyway. */
14413 expected_size);
14417 DImode);
14421 SImode);
14425 QImode);
14427 }
14428 /* Adjust properly the offset of src and dest memory for aliasing. */
14430 {
14435 }
14436 else
14437 {
14440 }
14442 /* Step 4: Epilogue to copy the remaining bytes. */
14445 {
14446 /* When the main loop is done, COUNT_EXP might hold original count,
14447 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14448 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14449 bytes. Compensate if needed. */
14452 {
14453 tmp =
14456 OPTAB_DIRECT);
14459 }
14462 }
14466 epilogue_size_needed);
14470 }
14472 /* Helper function for memcpy. For QImode value 0xXY produce
14473 0xXYXYXYXY of wide specified by MODE. This is essentially
14474 a * 0x10101010, but we can do slightly better than
14475 synth_mult by unwinding the sequence by hand on CPUs with
14476 slow multiply. */
14477 static rtx
14479 {
14481 rtx tmp;
14488 {
14496 }
14505 nops--;
14510 {
14514 OPTAB_DIRECT);
14515 }
14516 else
14517 {
14523 else
14525 else
14526 {
14529 reg =
14531 }
14541 }
14542 }
14544 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
14545 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
14546 alignment from ALIGN to DESIRED_ALIGN. */
14547 static rtx
14549 {
14550 rtx promoted_val;
14559 else
14563 }
14565 /* Expand string clear operation (bzero). Use i386 string operations when
14566 profitable. See expand_movmem comment for explanation of individual
14567 steps performed. */
14568 int
14571 {
14572 rtx destreg;
14574 rtx tmp;
14588 /* i386 can do misaligned access on reasonably increased cost. */
14597 /* Step 0: Decide on preferred algorithm, desired alignment and
14598 size of chunks to be copied by main loop. */
14613 {
14633 }
14636 /* Step 1: Prologue guard. */
14638 /* Alignment code needs count to be in register. */
14640 {
14645 }
14646 /* Do the cheap promotion to allow better CSE across the
14647 main loop and epilogue (ie one load of the big constant in the
14648 front of all code. */
14652 /* Ensure that alignment prologue won't copy past end of block. */
14654 {
14656 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14657 Make sure it is power of 2. */
14660 /* To improve performance of small blocks, we jump around the VAL
14661 promoting mode. This mean that if the promoted VAL is not constant,
14662 we might not use it in the epilogue and have to use byte
14663 loop variant. */
14671 ;
14674 else
14676 }
14678 {
14687 }
14689 /* Step 2: Alignment prologue. */
14691 /* Do the expensive promotion once we branched off the small blocks. */
14698 {
14699 /* Except for the first move in epilogue, we no longer know
14700 constant offset in aliasing info. It don't seems to worth
14701 the pain to maintain it for the first move, so throw away
14702 the info early. */
14705 desired_align);
14706 }
14708 {
14712 }
14714 /* Step 3: Main loop. */
14717 {
14735 DImode);
14739 SImode);
14743 QImode);
14745 }
14746 /* Adjust properly the offset of src and dest memory for aliasing. */
14750 else
14753 /* Step 4: Epilogue to copy the remaining bytes. */
14756 {
14757 /* When the main loop is done, COUNT_EXP might hold original count,
14758 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14759 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14760 bytes. Compensate if needed. */
14763 {
14764 tmp =
14767 OPTAB_DIRECT);
14771 }
14774 }
14776 {
14779 size_needed);
14780 else
14782 size_needed);
14783 }
14787 }
14789 /* Expand strlen. */
14790 int
14792 {
14795 /* The generic case of strlen expander is long. Avoid it's
14796 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
14799 && !TARGET_INLINE_ALL_STRINGOPS
14800 && !optimize_size
14809 {
14810 /* Well it seems that some optimizer does not combine a call like
14811 foo(strlen(bar), strlen(bar));
14812 when the move and the subtraction is done here. It does calculate
14813 the length just once when these instructions are done inside of
14814 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
14815 often used and I use one fewer register for the lifetime of
14816 output_strlen_unroll() this is better. */
14822 /* strlensi_unroll_1 returns the address of the zero at the end of
14823 the string, like memchr(), so compute the length by subtracting
14824 the start address. */
14827 else
14829 }
14830 else
14831 {
14832 rtx unspec;
14842 /* If .md starts supporting :P, this can be done in .md. */
14847 {
14850 }
14851 else
14852 {
14855 }
14856 }
14858 }
14860 /* Expand the appropriate insns for doing strlen if not just doing
14861 repnz; scasb
14863 out = result, initialized with the start address
14864 align_rtx = alignment of the address.
14865 scratch = scratch register, initialized with the startaddress when
14866 not aligned, otherwise undefined
14868 This is just the body. It needs the initializations mentioned above and
14869 some address computing at the end. These things are done in i386.md. */
14871 static void
14873 {
14875 rtx tmp;
14880 rtx mem;
14883 rtx cmp;
14889 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
14891 /* Is there a known alignment and is it less than 4? */
14893 {
14896 /* Is there a known alignment and is it not 2? */
14898 {
14902 /* Leave just the 3 lower bits. */
14912 }
14913 else
14914 {
14915 /* Since the alignment is 2, we have to check 2 or 0 bytes;
14916 check if is aligned to 4 - byte. */
14923 }
14927 /* Now compare the bytes. */
14929 /* Compare the first n unaligned byte on a byte per byte basis. */
14933 /* Increment the address. */
14936 else
14939 /* Not needed with an alignment of 2 */
14941 {
14945 end_0_label);
14949 else
14953 }
14956 end_0_label);
14960 else
14962 }
14964 /* Generate loop to check 4 bytes at a time. It is not a good idea to
14965 align this loop. It gives only huge programs, but does not help to
14966 speed up. */
14973 else
14976 /* This formula yields a nonzero result iff one of the bytes is zero.
14977 This saves three branches inside loop and many cycles. */
14985 align_4_label);
14988 {
14994 /* If zero is not in the first two bytes, move two bytes forward. */
15000 reg,
15001 tmpreg)));
15002 /* Emit lea manually to avoid clobbering of flags. */
15010 reg2,
15011 out)));
15013 }
15014 else
15015 {
15017 /* Is zero in the first two bytes? */
15024 pc_rtx);
15028 /* Not in the first two. Move two bytes forward. */
15032 else
15037 }
15039 /* Avoid branch in fixing the byte. */
15045 else
15049 }
15051 /* For given symbol (function) construct code to compute address of it's PLT
15052 entry in large x86-64 PIC model. */
15053 rtx
15055 {
15065 }
15067 void
15069 rtx callarg2 ATTRIBUTE_UNUSED,
15071 {
15079 {
15080 #if TARGET_MACHO
15083 #endif
15084 }
15085 else
15086 {
15087 /* Static functions and indirect calls don't need the pic register. */
15092 }
15095 {
15099 }
15107 {
15110 }
15113 {
15114 rtx addr;
15119 }
15125 {
15129 }
15134 }
15136 \f
15137 /* Clear stack slot assignments remembered from previous functions.
15138 This is called from INIT_EXPANDERS once before RTL is emitted for each
15139 function. */
15143 {
15151 }
15153 /* Return a MEM corresponding to a stack slot with mode MODE.
15154 Allocate a new slot if necessary.
15156 The RTL for a function can have several slots available: N is
15157 which slot to use. */
15159 rtx
15161 {
15179 }
15181 /* Construct the SYMBOL_REF for the tls_get_addr function. */
15184 rtx
15186 {
15189 {
15191 (TARGET_ANY_GNU_TLS
15195 }
15198 }
15200 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
15203 rtx
15205 {
15208 {
15213 }
15216 }
15217 \f
15218 /* Calculate the length of the memory address in the instruction
15219 encoding. Does not include the one-byte modrm, opcode, or prefix. */
15221 int
15223 {
15248 /* Rule of thumb:
15249 - esp as the base always wants an index,
15250 - ebp as the base always wants a displacement. */
15252 /* Register Indirect. */
15254 {
15255 /* esp (for its index) and ebp (for its displacement) need
15256 the two-byte modrm form. */
15262 }
15264 /* Direct Addressing. */
15268 else
15269 {
15270 /* Find the length of the displacement constant. */
15272 {
15275 else
15277 }
15278 /* ebp always wants a displacement. */
15282 /* An index requires the two-byte modrm form.... */
15284 /* ...like esp, which always wants an index. */
15289 }
15292 }
15294 /* Compute default value for "length_immediate" attribute. When SHORTFORM
15295 is set, expect that insn have 8bit immediate alternative. */
15296 int
15298 {
15304 {
15308 else
15309 {
15311 {
15321 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
15327 }
15328 }
15329 }
15331 }
15332 /* Compute default value for "length_address" attribute. */
15333 int
15335 {
15339 {
15348 }
15353 {
15356 }
15358 }
15359 \f
15360 /* Return the maximum number of instructions a cpu can issue. */
15362 static int
15364 {
15366 {
15386 }
15387 }
15389 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
15390 by DEP_INSN and nothing set by DEP_INSN. */
15392 static int
15394 {
15397 /* Simplify the test for uninteresting insns. */
15405 {
15408 }
15413 {
15416 }
15417 else
15423 /* This test is true if the dependent insn reads the flags but
15424 not any other potentially set register. */
15432 }
15434 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
15435 address with operands set by DEP_INSN. */
15437 static int
15439 {
15440 rtx addr;
15444 {
15453 }
15454 else
15455 {
15460 {
15463 }
15465 found:;
15466 }
15469 }
15471 static int
15473 {
15479 /* Anti and output dependencies have zero cost on all CPUs. */
15485 /* If we can't recognize the insns, we can't really do anything. */
15493 {
15495 /* Address Generation Interlock adds a cycle of latency. */
15499 /* ??? Compares pair with jump/setcc. */
15503 /* Floating point stores require value to be ready one cycle earlier. */
15513 /* INT->FP conversion is expensive. */
15517 /* There is one cycle extra latency between an FP op and a store. */
15525 /* Show ability of reorder buffer to hide latency of load by executing
15526 in parallel with previous instruction in case
15527 previous instruction is not needed to compute the address. */
15530 {
15531 /* Claim moves to take one cycle, as core can issue one load
15532 at time and the next load can start cycle later. */
15537 cost--;
15538 }
15544 /* The esp dependency is resolved before the instruction is really
15545 finished. */
15550 /* INT->FP conversion is expensive. */
15554 /* Show ability of reorder buffer to hide latency of load by executing
15555 in parallel with previous instruction in case
15556 previous instruction is not needed to compute the address. */
15559 {
15560 /* Claim moves to take one cycle, as core can issue one load
15561 at time and the next load can start cycle later. */
15567 else
15569 }
15579 /* Show ability of reorder buffer to hide latency of load by executing
15580 in parallel with previous instruction in case
15581 previous instruction is not needed to compute the address. */
15584 {
15588 /* Because of the difference between the length of integer and
15589 floating unit pipeline preparation stages, the memory operands
15590 for floating point are cheaper.
15592 ??? For Athlon it the difference is most probably 2. */
15595 else
15600 else
15602 }
15606 }
15609 }
15611 /* How many alternative schedules to try. This should be as wide as the
15612 scheduling freedom in the DFA, but no wider. Making this value too
15613 large results extra work for the scheduler. */
15615 static int
15617 {
15625 else
15627 }
15629 \f
15630 /* Compute the alignment given to a constant that is being placed in memory.
15631 EXP is the constant and ALIGN is the alignment that the object would
15632 ordinarily have.
15633 The value of this function is used instead of that alignment to align
15634 the object. */
15636 int
15638 {
15640 {
15645 }
15651 }
15653 /* Compute the alignment for a static variable.
15654 TYPE is the data type, and ALIGN is the alignment that
15655 the object would ordinarily have. The value of this function is used
15656 instead of that alignment to align the object. */
15658 int
15660 {
15671 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15672 to 16byte boundary. */
15674 {
15681 }
15684 {
15689 }
15691 {
15697 }
15702 {
15707 }
15710 {
15715 }
15718 }
15720 /* Compute the alignment for a local variable.
15721 TYPE is the data type, and ALIGN is the alignment that
15722 the object would ordinarily have. The value of this macro is used
15723 instead of that alignment to align the object. */
15725 int
15727 {
15728 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15729 to 16byte boundary. */
15731 {
15738 }
15740 {
15745 }
15747 {
15752 }
15757 {
15762 }
15765 {
15771 }
15773 }
15774 \f
15775 /* Emit RTL insns to initialize the variable parts of a trampoline.
15776 FNADDR is an RTX for the address of the function's pure code.
15777 CXT is an RTX for the static chain value for the function. */
15778 void
15780 {
15782 {
15783 /* Compute offset from the end of the jmp to the target function. */
15793 }
15794 else
15795 {
15797 /* Try to load address using shorter movl instead of movabs.
15798 We may want to support movq for kernel mode, but kernel does not use
15799 trampolines at the moment. */
15801 {
15808 }
15809 else
15810 {
15814 fnaddr);
15816 }
15817 /* Load static chain using movabs to r10. */
15821 cxt);
15823 /* Jump to the r11 */
15830 }
15832 #ifdef ENABLE_EXECUTE_STACK
15835 #endif
15836 }
15837 \f
15838 /* Codes for all the SSE/MMX builtins. */
15839 enum ix86_builtins
15840 {
15841 IX86_BUILTIN_ADDPS,
15842 IX86_BUILTIN_ADDSS,
15843 IX86_BUILTIN_DIVPS,
15844 IX86_BUILTIN_DIVSS,
15845 IX86_BUILTIN_MULPS,
15846 IX86_BUILTIN_MULSS,
15847 IX86_BUILTIN_SUBPS,
15848 IX86_BUILTIN_SUBSS,
15850 IX86_BUILTIN_CMPEQPS,
15851 IX86_BUILTIN_CMPLTPS,
15852 IX86_BUILTIN_CMPLEPS,
15853 IX86_BUILTIN_CMPGTPS,
15854 IX86_BUILTIN_CMPGEPS,
15855 IX86_BUILTIN_CMPNEQPS,
15856 IX86_BUILTIN_CMPNLTPS,
15857 IX86_BUILTIN_CMPNLEPS,
15858 IX86_BUILTIN_CMPNGTPS,
15859 IX86_BUILTIN_CMPNGEPS,
15860 IX86_BUILTIN_CMPORDPS,
15861 IX86_BUILTIN_CMPUNORDPS,
15862 IX86_BUILTIN_CMPEQSS,
15863 IX86_BUILTIN_CMPLTSS,
15864 IX86_BUILTIN_CMPLESS,
15865 IX86_BUILTIN_CMPNEQSS,
15866 IX86_BUILTIN_CMPNLTSS,
15867 IX86_BUILTIN_CMPNLESS,
15868 IX86_BUILTIN_CMPNGTSS,
15869 IX86_BUILTIN_CMPNGESS,
15870 IX86_BUILTIN_CMPORDSS,
15871 IX86_BUILTIN_CMPUNORDSS,
15873 IX86_BUILTIN_COMIEQSS,
15874 IX86_BUILTIN_COMILTSS,
15875 IX86_BUILTIN_COMILESS,
15876 IX86_BUILTIN_COMIGTSS,
15877 IX86_BUILTIN_COMIGESS,
15878 IX86_BUILTIN_COMINEQSS,
15879 IX86_BUILTIN_UCOMIEQSS,
15880 IX86_BUILTIN_UCOMILTSS,
15881 IX86_BUILTIN_UCOMILESS,
15882 IX86_BUILTIN_UCOMIGTSS,
15883 IX86_BUILTIN_UCOMIGESS,
15884 IX86_BUILTIN_UCOMINEQSS,
15886 IX86_BUILTIN_CVTPI2PS,
15887 IX86_BUILTIN_CVTPS2PI,
15888 IX86_BUILTIN_CVTSI2SS,
15889 IX86_BUILTIN_CVTSI642SS,
15890 IX86_BUILTIN_CVTSS2SI,
15891 IX86_BUILTIN_CVTSS2SI64,
15892 IX86_BUILTIN_CVTTPS2PI,
15893 IX86_BUILTIN_CVTTSS2SI,
15894 IX86_BUILTIN_CVTTSS2SI64,
15896 IX86_BUILTIN_MAXPS,
15897 IX86_BUILTIN_MAXSS,
15898 IX86_BUILTIN_MINPS,
15899 IX86_BUILTIN_MINSS,
15901 IX86_BUILTIN_LOADUPS,
15902 IX86_BUILTIN_STOREUPS,
15903 IX86_BUILTIN_MOVSS,
15905 IX86_BUILTIN_MOVHLPS,
15906 IX86_BUILTIN_MOVLHPS,
15907 IX86_BUILTIN_LOADHPS,
15908 IX86_BUILTIN_LOADLPS,
15909 IX86_BUILTIN_STOREHPS,
15910 IX86_BUILTIN_STORELPS,
15912 IX86_BUILTIN_MASKMOVQ,
15913 IX86_BUILTIN_MOVMSKPS,
15914 IX86_BUILTIN_PMOVMSKB,
15916 IX86_BUILTIN_MOVNTPS,
15917 IX86_BUILTIN_MOVNTQ,
15919 IX86_BUILTIN_LOADDQU,
15920 IX86_BUILTIN_STOREDQU,
15922 IX86_BUILTIN_PACKSSWB,
15923 IX86_BUILTIN_PACKSSDW,
15924 IX86_BUILTIN_PACKUSWB,
15926 IX86_BUILTIN_PADDB,
15927 IX86_BUILTIN_PADDW,
15928 IX86_BUILTIN_PADDD,
15929 IX86_BUILTIN_PADDQ,
15930 IX86_BUILTIN_PADDSB,
15931 IX86_BUILTIN_PADDSW,
15932 IX86_BUILTIN_PADDUSB,
15933 IX86_BUILTIN_PADDUSW,
15934 IX86_BUILTIN_PSUBB,
15935 IX86_BUILTIN_PSUBW,
15936 IX86_BUILTIN_PSUBD,
15937 IX86_BUILTIN_PSUBQ,
15938 IX86_BUILTIN_PSUBSB,
15939 IX86_BUILTIN_PSUBSW,
15940 IX86_BUILTIN_PSUBUSB,
15941 IX86_BUILTIN_PSUBUSW,
15943 IX86_BUILTIN_PAND,
15944 IX86_BUILTIN_PANDN,
15945 IX86_BUILTIN_POR,
15946 IX86_BUILTIN_PXOR,
15948 IX86_BUILTIN_PAVGB,
15949 IX86_BUILTIN_PAVGW,
15951 IX86_BUILTIN_PCMPEQB,
15952 IX86_BUILTIN_PCMPEQW,
15953 IX86_BUILTIN_PCMPEQD,
15954 IX86_BUILTIN_PCMPGTB,
15955 IX86_BUILTIN_PCMPGTW,
15956 IX86_BUILTIN_PCMPGTD,
15958 IX86_BUILTIN_PMADDWD,
15960 IX86_BUILTIN_PMAXSW,
15961 IX86_BUILTIN_PMAXUB,
15962 IX86_BUILTIN_PMINSW,
15963 IX86_BUILTIN_PMINUB,
15965 IX86_BUILTIN_PMULHUW,
15966 IX86_BUILTIN_PMULHW,
15967 IX86_BUILTIN_PMULLW,
15969 IX86_BUILTIN_PSADBW,
15970 IX86_BUILTIN_PSHUFW,
15972 IX86_BUILTIN_PSLLW,
15973 IX86_BUILTIN_PSLLD,
15974 IX86_BUILTIN_PSLLQ,
15975 IX86_BUILTIN_PSRAW,
15976 IX86_BUILTIN_PSRAD,
15977 IX86_BUILTIN_PSRLW,
15978 IX86_BUILTIN_PSRLD,
15979 IX86_BUILTIN_PSRLQ,
15980 IX86_BUILTIN_PSLLWI,
15981 IX86_BUILTIN_PSLLDI,
15982 IX86_BUILTIN_PSLLQI,
15983 IX86_BUILTIN_PSRAWI,
15984 IX86_BUILTIN_PSRADI,
15985 IX86_BUILTIN_PSRLWI,
15986 IX86_BUILTIN_PSRLDI,
15987 IX86_BUILTIN_PSRLQI,
15989 IX86_BUILTIN_PUNPCKHBW,
15990 IX86_BUILTIN_PUNPCKHWD,
15991 IX86_BUILTIN_PUNPCKHDQ,
15992 IX86_BUILTIN_PUNPCKLBW,
15993 IX86_BUILTIN_PUNPCKLWD,
15994 IX86_BUILTIN_PUNPCKLDQ,
15996 IX86_BUILTIN_SHUFPS,
15998 IX86_BUILTIN_RCPPS,
15999 IX86_BUILTIN_RCPSS,
16000 IX86_BUILTIN_RSQRTPS,
16001 IX86_BUILTIN_RSQRTSS,
16002 IX86_BUILTIN_SQRTPS,
16003 IX86_BUILTIN_SQRTSS,
16005 IX86_BUILTIN_UNPCKHPS,
16006 IX86_BUILTIN_UNPCKLPS,
16008 IX86_BUILTIN_ANDPS,
16009 IX86_BUILTIN_ANDNPS,
16010 IX86_BUILTIN_ORPS,
16011 IX86_BUILTIN_XORPS,
16013 IX86_BUILTIN_EMMS,
16014 IX86_BUILTIN_LDMXCSR,
16015 IX86_BUILTIN_STMXCSR,
16016 IX86_BUILTIN_SFENCE,
16018 /* 3DNow! Original */
16019 IX86_BUILTIN_FEMMS,
16020 IX86_BUILTIN_PAVGUSB,
16021 IX86_BUILTIN_PF2ID,
16022 IX86_BUILTIN_PFACC,
16023 IX86_BUILTIN_PFADD,
16024 IX86_BUILTIN_PFCMPEQ,
16025 IX86_BUILTIN_PFCMPGE,
16026 IX86_BUILTIN_PFCMPGT,
16027 IX86_BUILTIN_PFMAX,
16028 IX86_BUILTIN_PFMIN,
16029 IX86_BUILTIN_PFMUL,
16030 IX86_BUILTIN_PFRCP,
16031 IX86_BUILTIN_PFRCPIT1,
16032 IX86_BUILTIN_PFRCPIT2,
16033 IX86_BUILTIN_PFRSQIT1,
16034 IX86_BUILTIN_PFRSQRT,
16035 IX86_BUILTIN_PFSUB,
16036 IX86_BUILTIN_PFSUBR,
16037 IX86_BUILTIN_PI2FD,
16038 IX86_BUILTIN_PMULHRW,
16040 /* 3DNow! Athlon Extensions */
16041 IX86_BUILTIN_PF2IW,
16042 IX86_BUILTIN_PFNACC,
16043 IX86_BUILTIN_PFPNACC,
16044 IX86_BUILTIN_PI2FW,
16045 IX86_BUILTIN_PSWAPDSI,
16046 IX86_BUILTIN_PSWAPDSF,
16048 /* SSE2 */
16049 IX86_BUILTIN_ADDPD,
16050 IX86_BUILTIN_ADDSD,
16051 IX86_BUILTIN_DIVPD,
16052 IX86_BUILTIN_DIVSD,
16053 IX86_BUILTIN_MULPD,
16054 IX86_BUILTIN_MULSD,
16055 IX86_BUILTIN_SUBPD,
16056 IX86_BUILTIN_SUBSD,
16058 IX86_BUILTIN_CMPEQPD,
16059 IX86_BUILTIN_CMPLTPD,
16060 IX86_BUILTIN_CMPLEPD,
16061 IX86_BUILTIN_CMPGTPD,
16062 IX86_BUILTIN_CMPGEPD,
16063 IX86_BUILTIN_CMPNEQPD,
16064 IX86_BUILTIN_CMPNLTPD,
16065 IX86_BUILTIN_CMPNLEPD,
16066 IX86_BUILTIN_CMPNGTPD,
16067 IX86_BUILTIN_CMPNGEPD,
16068 IX86_BUILTIN_CMPORDPD,
16069 IX86_BUILTIN_CMPUNORDPD,
16070 IX86_BUILTIN_CMPNEPD,
16071 IX86_BUILTIN_CMPEQSD,
16072 IX86_BUILTIN_CMPLTSD,
16073 IX86_BUILTIN_CMPLESD,
16074 IX86_BUILTIN_CMPNEQSD,
16075 IX86_BUILTIN_CMPNLTSD,
16076 IX86_BUILTIN_CMPNLESD,
16077 IX86_BUILTIN_CMPORDSD,
16078 IX86_BUILTIN_CMPUNORDSD,
16079 IX86_BUILTIN_CMPNESD,
16081 IX86_BUILTIN_COMIEQSD,
16082 IX86_BUILTIN_COMILTSD,
16083 IX86_BUILTIN_COMILESD,
16084 IX86_BUILTIN_COMIGTSD,
16085 IX86_BUILTIN_COMIGESD,
16086 IX86_BUILTIN_COMINEQSD,
16087 IX86_BUILTIN_UCOMIEQSD,
16088 IX86_BUILTIN_UCOMILTSD,
16089 IX86_BUILTIN_UCOMILESD,
16090 IX86_BUILTIN_UCOMIGTSD,
16091 IX86_BUILTIN_UCOMIGESD,
16092 IX86_BUILTIN_UCOMINEQSD,
16094 IX86_BUILTIN_MAXPD,
16095 IX86_BUILTIN_MAXSD,
16096 IX86_BUILTIN_MINPD,
16097 IX86_BUILTIN_MINSD,
16099 IX86_BUILTIN_ANDPD,
16100 IX86_BUILTIN_ANDNPD,
16101 IX86_BUILTIN_ORPD,
16102 IX86_BUILTIN_XORPD,
16104 IX86_BUILTIN_SQRTPD,
16105 IX86_BUILTIN_SQRTSD,
16107 IX86_BUILTIN_UNPCKHPD,
16108 IX86_BUILTIN_UNPCKLPD,
16110 IX86_BUILTIN_SHUFPD,
16112 IX86_BUILTIN_LOADUPD,
16113 IX86_BUILTIN_STOREUPD,
16114 IX86_BUILTIN_MOVSD,
16116 IX86_BUILTIN_LOADHPD,
16117 IX86_BUILTIN_LOADLPD,
16119 IX86_BUILTIN_CVTDQ2PD,
16120 IX86_BUILTIN_CVTDQ2PS,
16122 IX86_BUILTIN_CVTPD2DQ,
16123 IX86_BUILTIN_CVTPD2PI,
16124 IX86_BUILTIN_CVTPD2PS,
16125 IX86_BUILTIN_CVTTPD2DQ,
16126 IX86_BUILTIN_CVTTPD2PI,
16128 IX86_BUILTIN_CVTPI2PD,
16129 IX86_BUILTIN_CVTSI2SD,
16130 IX86_BUILTIN_CVTSI642SD,
16132 IX86_BUILTIN_CVTSD2SI,
16133 IX86_BUILTIN_CVTSD2SI64,
16134 IX86_BUILTIN_CVTSD2SS,
16135 IX86_BUILTIN_CVTSS2SD,
16136 IX86_BUILTIN_CVTTSD2SI,
16137 IX86_BUILTIN_CVTTSD2SI64,
16139 IX86_BUILTIN_CVTPS2DQ,
16140 IX86_BUILTIN_CVTPS2PD,
16141 IX86_BUILTIN_CVTTPS2DQ,
16143 IX86_BUILTIN_MOVNTI,
16144 IX86_BUILTIN_MOVNTPD,
16145 IX86_BUILTIN_MOVNTDQ,
16147 /* SSE2 MMX */
16148 IX86_BUILTIN_MASKMOVDQU,
16149 IX86_BUILTIN_MOVMSKPD,
16150 IX86_BUILTIN_PMOVMSKB128,
16152 IX86_BUILTIN_PACKSSWB128,
16153 IX86_BUILTIN_PACKSSDW128,
16154 IX86_BUILTIN_PACKUSWB128,
16156 IX86_BUILTIN_PADDB128,
16157 IX86_BUILTIN_PADDW128,
16158 IX86_BUILTIN_PADDD128,
16159 IX86_BUILTIN_PADDQ128,
16160 IX86_BUILTIN_PADDSB128,
16161 IX86_BUILTIN_PADDSW128,
16162 IX86_BUILTIN_PADDUSB128,
16163 IX86_BUILTIN_PADDUSW128,
16164 IX86_BUILTIN_PSUBB128,
16165 IX86_BUILTIN_PSUBW128,
16166 IX86_BUILTIN_PSUBD128,
16167 IX86_BUILTIN_PSUBQ128,
16168 IX86_BUILTIN_PSUBSB128,
16169 IX86_BUILTIN_PSUBSW128,
16170 IX86_BUILTIN_PSUBUSB128,
16171 IX86_BUILTIN_PSUBUSW128,
16173 IX86_BUILTIN_PAND128,
16174 IX86_BUILTIN_PANDN128,
16175 IX86_BUILTIN_POR128,
16176 IX86_BUILTIN_PXOR128,
16178 IX86_BUILTIN_PAVGB128,
16179 IX86_BUILTIN_PAVGW128,
16181 IX86_BUILTIN_PCMPEQB128,
16182 IX86_BUILTIN_PCMPEQW128,
16183 IX86_BUILTIN_PCMPEQD128,
16184 IX86_BUILTIN_PCMPGTB128,
16185 IX86_BUILTIN_PCMPGTW128,
16186 IX86_BUILTIN_PCMPGTD128,
16188 IX86_BUILTIN_PMADDWD128,
16190 IX86_BUILTIN_PMAXSW128,
16191 IX86_BUILTIN_PMAXUB128,
16192 IX86_BUILTIN_PMINSW128,
16193 IX86_BUILTIN_PMINUB128,
16195 IX86_BUILTIN_PMULUDQ,
16196 IX86_BUILTIN_PMULUDQ128,
16197 IX86_BUILTIN_PMULHUW128,
16198 IX86_BUILTIN_PMULHW128,
16199 IX86_BUILTIN_PMULLW128,
16201 IX86_BUILTIN_PSADBW128,
16202 IX86_BUILTIN_PSHUFHW,
16203 IX86_BUILTIN_PSHUFLW,
16204 IX86_BUILTIN_PSHUFD,
16206 IX86_BUILTIN_PSLLW128,
16207 IX86_BUILTIN_PSLLD128,
16208 IX86_BUILTIN_PSLLQ128,
16209 IX86_BUILTIN_PSRAW128,
16210 IX86_BUILTIN_PSRAD128,
16211 IX86_BUILTIN_PSRLW128,
16212 IX86_BUILTIN_PSRLD128,
16213 IX86_BUILTIN_PSRLQ128,
16214 IX86_BUILTIN_PSLLDQI128,
16215 IX86_BUILTIN_PSLLWI128,
16216 IX86_BUILTIN_PSLLDI128,
16217 IX86_BUILTIN_PSLLQI128,
16218 IX86_BUILTIN_PSRAWI128,
16219 IX86_BUILTIN_PSRADI128,
16220 IX86_BUILTIN_PSRLDQI128,
16221 IX86_BUILTIN_PSRLWI128,
16222 IX86_BUILTIN_PSRLDI128,
16223 IX86_BUILTIN_PSRLQI128,
16225 IX86_BUILTIN_PUNPCKHBW128,
16226 IX86_BUILTIN_PUNPCKHWD128,
16227 IX86_BUILTIN_PUNPCKHDQ128,
16228 IX86_BUILTIN_PUNPCKHQDQ128,
16229 IX86_BUILTIN_PUNPCKLBW128,
16230 IX86_BUILTIN_PUNPCKLWD128,
16231 IX86_BUILTIN_PUNPCKLDQ128,
16232 IX86_BUILTIN_PUNPCKLQDQ128,
16234 IX86_BUILTIN_CLFLUSH,
16235 IX86_BUILTIN_MFENCE,
16236 IX86_BUILTIN_LFENCE,
16238 /* Prescott New Instructions. */
16239 IX86_BUILTIN_ADDSUBPS,
16240 IX86_BUILTIN_HADDPS,
16241 IX86_BUILTIN_HSUBPS,
16242 IX86_BUILTIN_MOVSHDUP,
16243 IX86_BUILTIN_MOVSLDUP,
16244 IX86_BUILTIN_ADDSUBPD,
16245 IX86_BUILTIN_HADDPD,
16246 IX86_BUILTIN_HSUBPD,
16247 IX86_BUILTIN_LDDQU,
16249 IX86_BUILTIN_MONITOR,
16250 IX86_BUILTIN_MWAIT,
16252 /* SSSE3. */
16253 IX86_BUILTIN_PHADDW,
16254 IX86_BUILTIN_PHADDD,
16255 IX86_BUILTIN_PHADDSW,
16256 IX86_BUILTIN_PHSUBW,
16257 IX86_BUILTIN_PHSUBD,
16258 IX86_BUILTIN_PHSUBSW,
16259 IX86_BUILTIN_PMADDUBSW,
16260 IX86_BUILTIN_PMULHRSW,
16261 IX86_BUILTIN_PSHUFB,
16262 IX86_BUILTIN_PSIGNB,
16263 IX86_BUILTIN_PSIGNW,
16264 IX86_BUILTIN_PSIGND,
16265 IX86_BUILTIN_PALIGNR,
16266 IX86_BUILTIN_PABSB,
16267 IX86_BUILTIN_PABSW,
16268 IX86_BUILTIN_PABSD,
16270 IX86_BUILTIN_PHADDW128,
16271 IX86_BUILTIN_PHADDD128,
16272 IX86_BUILTIN_PHADDSW128,
16273 IX86_BUILTIN_PHSUBW128,
16274 IX86_BUILTIN_PHSUBD128,
16275 IX86_BUILTIN_PHSUBSW128,
16276 IX86_BUILTIN_PMADDUBSW128,
16277 IX86_BUILTIN_PMULHRSW128,
16278 IX86_BUILTIN_PSHUFB128,
16279 IX86_BUILTIN_PSIGNB128,
16280 IX86_BUILTIN_PSIGNW128,
16281 IX86_BUILTIN_PSIGND128,
16282 IX86_BUILTIN_PALIGNR128,
16283 IX86_BUILTIN_PABSB128,
16284 IX86_BUILTIN_PABSW128,
16285 IX86_BUILTIN_PABSD128,
16287 /* AMDFAM10 - SSE4A New Instructions. */
16288 IX86_BUILTIN_MOVNTSD,
16289 IX86_BUILTIN_MOVNTSS,
16290 IX86_BUILTIN_EXTRQI,
16291 IX86_BUILTIN_EXTRQ,
16292 IX86_BUILTIN_INSERTQI,
16293 IX86_BUILTIN_INSERTQ,
16295 IX86_BUILTIN_VEC_INIT_V2SI,
16296 IX86_BUILTIN_VEC_INIT_V4HI,
16297 IX86_BUILTIN_VEC_INIT_V8QI,
16298 IX86_BUILTIN_VEC_EXT_V2DF,
16299 IX86_BUILTIN_VEC_EXT_V2DI,
16300 IX86_BUILTIN_VEC_EXT_V4SF,
16301 IX86_BUILTIN_VEC_EXT_V4SI,
16302 IX86_BUILTIN_VEC_EXT_V8HI,
16303 IX86_BUILTIN_VEC_EXT_V2SI,
16304 IX86_BUILTIN_VEC_EXT_V4HI,
16305 IX86_BUILTIN_VEC_SET_V8HI,
16306 IX86_BUILTIN_VEC_SET_V4HI,
16308 IX86_BUILTIN_MAX
16309 };
16311 /* Table for the ix86 builtin decls. */
16314 /* Add a ix86 target builtin function with CODE, NAME and TYPE. Do so,
16315 * if the target_flags include one of MASK. Stores the function decl
16316 * in the ix86_builtins array.
16317 * Returns the function decl or NULL_TREE, if the builtin was not added. */
16321 {
16326 {
16330 }
16333 }
16335 /* Like def_builtin, but also marks the function decl "const". */
16340 {
16345 }
16347 /* Bits for builtin_description.flag. */
16349 /* Set when we don't support the comparison natively, and should
16350 swap_comparison in order to support it. */
16351 #define BUILTIN_DESC_SWAP_OPERANDS 1
16353 struct builtin_description
16354 {
16361 };
16364 {
16376 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
16382 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
16383 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
16384 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
16385 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
16386 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
16387 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
16388 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
16389 };
16392 {
16393 /* SSE */
16403 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
16404 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
16405 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
16407 BUILTIN_DESC_SWAP_OPERANDS },
16409 BUILTIN_DESC_SWAP_OPERANDS },
16410 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
16411 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
16412 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
16413 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
16414 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
16415 BUILTIN_DESC_SWAP_OPERANDS },
16416 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
16417 BUILTIN_DESC_SWAP_OPERANDS },
16418 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
16419 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
16420 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
16421 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
16422 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
16423 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
16424 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
16425 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
16426 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
16427 BUILTIN_DESC_SWAP_OPERANDS },
16428 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
16429 BUILTIN_DESC_SWAP_OPERANDS },
16430 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
16448 /* MMX */
16468 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
16469 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
16476 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
16477 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
16486 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
16487 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
16488 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
16489 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
16491 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
16492 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
16493 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
16494 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
16495 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
16496 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
16498 /* Special. */
16529 /* SSE2 */
16539 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
16540 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
16541 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
16543 BUILTIN_DESC_SWAP_OPERANDS },
16545 BUILTIN_DESC_SWAP_OPERANDS },
16546 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
16547 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
16548 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
16549 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
16550 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
16551 BUILTIN_DESC_SWAP_OPERANDS },
16552 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
16553 BUILTIN_DESC_SWAP_OPERANDS },
16554 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
16555 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
16556 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
16557 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
16558 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
16559 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
16560 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
16561 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
16562 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
16575 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
16576 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
16578 /* SSE2 MMX */
16588 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
16589 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
16590 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
16591 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
16592 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
16593 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
16594 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
16595 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
16598 { MASK_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
16601 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
16605 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
16606 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
16608 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
16609 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
16610 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
16611 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
16612 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
16613 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
16620 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
16621 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
16622 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
16623 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
16624 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
16625 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
16626 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
16627 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
16629 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
16630 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
16631 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
16633 { MASK_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
16657 /* SSE3 MMX */
16658 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
16659 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
16665 /* SSSE3 */
16666 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
16667 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
16668 { MASK_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
16669 { MASK_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
16670 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
16671 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
16672 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
16673 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
16674 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
16675 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
16676 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
16677 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
16678 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
16679 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
16680 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
16681 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
16682 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
16683 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
16684 { MASK_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
16685 { MASK_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
16686 { MASK_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
16687 { MASK_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
16688 { MASK_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
16690 };
16693 {
16733 /* SSE3 */
16734 { MASK_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, 0, 0 },
16735 { MASK_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, 0, 0 },
16737 /* SSSE3 */
16744 };
16746 static void
16748 {
16751 }
16753 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
16754 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
16755 builtins. */
16756 static void
16758 {
16765 tree V2DI_type_node
16784 /* Comparisons. */
16785 tree int_ftype_v4sf_v4sf
16788 tree v4si_ftype_v4sf_v4sf
16791 /* MMX/SSE/integer conversions. */
16792 tree int_ftype_v4sf
16795 tree int64_ftype_v4sf
16798 tree int_ftype_v8qi
16800 tree v4sf_ftype_v4sf_int
16803 tree v4sf_ftype_v4sf_int64
16806 NULL_TREE);
16807 tree v4sf_ftype_v4sf_v2si
16811 /* Miscellaneous. */
16812 tree v8qi_ftype_v4hi_v4hi
16815 tree v4hi_ftype_v2si_v2si
16818 tree v4sf_ftype_v4sf_v4sf_int
16822 tree v2si_ftype_v4hi_v4hi
16825 tree v4hi_ftype_v4hi_int
16828 tree v4hi_ftype_v4hi_di
16831 NULL_TREE);
16832 tree v2si_ftype_v2si_di
16835 NULL_TREE);
16836 tree void_ftype_void
16838 tree void_ftype_unsigned
16840 tree void_ftype_unsigned_unsigned
16843 tree void_ftype_pcvoid_unsigned_unsigned
16846 NULL_TREE);
16847 tree unsigned_ftype_void
16849 tree v2si_ftype_v4sf
16851 /* Loads/stores. */
16852 tree void_ftype_v8qi_v8qi_pchar
16856 tree v4sf_ftype_pcfloat
16858 /* @@@ the type is bogus */
16859 tree v4sf_ftype_v4sf_pv2si
16862 tree void_ftype_pv2si_v4sf
16865 tree void_ftype_pfloat_v4sf
16868 tree void_ftype_pdi_di
16871 NULL_TREE);
16872 tree void_ftype_pv2di_v2di
16875 /* Normal vector unops. */
16876 tree v4sf_ftype_v4sf
16878 tree v16qi_ftype_v16qi
16880 tree v8hi_ftype_v8hi
16882 tree v4si_ftype_v4si
16884 tree v8qi_ftype_v8qi
16886 tree v4hi_ftype_v4hi
16889 /* Normal vector binops. */
16890 tree v4sf_ftype_v4sf_v4sf
16893 tree v8qi_ftype_v8qi_v8qi
16896 tree v4hi_ftype_v4hi_v4hi
16899 tree v2si_ftype_v2si_v2si
16902 tree di_ftype_di_di
16904 long_long_unsigned_type_node,
16907 tree di_ftype_di_di_int
16909 long_long_unsigned_type_node,
16910 long_long_unsigned_type_node,
16913 tree v2si_ftype_v2sf
16915 tree v2sf_ftype_v2si
16917 tree v2si_ftype_v2si
16919 tree v2sf_ftype_v2sf
16921 tree v2sf_ftype_v2sf_v2sf
16924 tree v2si_ftype_v2sf_v2sf
16931 tree int_ftype_v2df_v2df
16935 tree void_ftype_pcvoid
16937 tree v4sf_ftype_v4si
16939 tree v4si_ftype_v4sf
16941 tree v2df_ftype_v4si
16943 tree v4si_ftype_v2df
16945 tree v2si_ftype_v2df
16947 tree v4sf_ftype_v2df
16949 tree v2df_ftype_v2si
16951 tree v2df_ftype_v4sf
16953 tree int_ftype_v2df
16955 tree int64_ftype_v2df
16958 tree v2df_ftype_v2df_int
16961 tree v2df_ftype_v2df_int64
16964 NULL_TREE);
16965 tree v4sf_ftype_v4sf_v2df
16968 tree v2df_ftype_v2df_v4sf
16971 tree v2df_ftype_v2df_v2df_int
16974 integer_type_node,
16975 NULL_TREE);
16976 tree v2df_ftype_v2df_pcdouble
16979 tree void_ftype_pdouble_v2df
16982 tree void_ftype_pint_int
16985 tree void_ftype_v16qi_v16qi_pchar
16989 tree v2df_ftype_pcdouble
16991 tree v2df_ftype_v2df_v2df
16994 tree v16qi_ftype_v16qi_v16qi
16997 tree v8hi_ftype_v8hi_v8hi
17000 tree v4si_ftype_v4si_v4si
17003 tree v2di_ftype_v2di_v2di
17006 tree v2di_ftype_v2df_v2df
17009 tree v2df_ftype_v2df
17011 tree v2di_ftype_v2di_int
17014 tree v2di_ftype_v2di_v2di_int
17017 tree v4si_ftype_v4si_int
17020 tree v8hi_ftype_v8hi_int
17023 tree v8hi_ftype_v8hi_v2di
17026 tree v4si_ftype_v4si_v2di
17029 tree v4si_ftype_v8hi_v8hi
17032 tree di_ftype_v8qi_v8qi
17035 tree di_ftype_v2si_v2si
17038 tree v2di_ftype_v16qi_v16qi
17041 tree v2di_ftype_v4si_v4si
17044 tree int_ftype_v16qi
17046 tree v16qi_ftype_pcchar
17048 tree void_ftype_pchar_v16qi
17052 tree v2di_ftype_v2di_unsigned_unsigned
17055 NULL_TREE);
17056 tree v2di_ftype_v2di_v2di_unsigned_unsigned
17059 NULL_TREE);
17060 tree v2di_ftype_v2di_v16qi
17062 NULL_TREE);
17064 tree float80_type;
17065 tree float128_type;
17066 tree ftype;
17068 /* The __float80 type. */
17072 else
17073 {
17074 /* The __float80 type. */
17079 }
17082 {
17087 }
17089 /* Add all builtins that are more or less simple operations on two
17090 operands. */
17092 {
17093 /* Use one of the operands; the target can have a different mode for
17094 mask-generating compares. */
17096 tree type;
17103 {
17137 }
17139 /* Override for comparisons. */
17149 }
17151 /* Add all builtins that are more or less simple operations on 1 operand. */
17153 {
17155 tree type;
17162 {
17190 }
17193 }
17195 /* Add the remaining MMX insns with somewhat more complicated types. */
17208 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
17211 /* comi/ucomi insns. */
17215 else
17218 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
17219 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
17220 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
17224 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
17225 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
17226 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
17227 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
17228 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
17229 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
17230 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
17231 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
17232 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
17234 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
17237 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
17239 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
17240 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
17241 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
17242 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
17245 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
17246 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
17247 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
17249 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
17251 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
17260 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
17262 /* Original 3DNow! */
17264 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
17268 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
17269 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
17270 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
17275 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
17276 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
17278 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
17282 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
17284 /* 3DNow! extension as used in the Athlon CPU. */
17286 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
17287 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
17289 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
17290 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
17292 /* SSE2 */
17293 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
17296 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
17298 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
17299 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
17302 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
17304 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
17305 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
17310 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
17315 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
17317 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
17318 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
17320 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
17321 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
17322 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
17323 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
17324 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
17326 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
17328 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
17329 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
17330 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
17331 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
17333 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
17334 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
17335 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
17337 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
17338 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
17339 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
17340 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
17347 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
17350 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
17352 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
17353 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
17354 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
17356 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
17357 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
17358 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
17360 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
17361 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
17363 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
17364 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
17365 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
17366 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
17368 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
17369 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
17370 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
17371 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
17373 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
17374 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
17376 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
17378 /* Prescott New Instructions. */
17380 void_ftype_pcvoid_unsigned_unsigned,
17381 IX86_BUILTIN_MONITOR);
17383 void_ftype_unsigned_unsigned,
17384 IX86_BUILTIN_MWAIT);
17388 /* SSSE3. */
17392 IX86_BUILTIN_PALIGNR);
17394 /* AMDFAM10 SSE4A New built-ins */
17408 /* Access to the vec_init patterns. */
17415 short_integer_type_node,
17416 short_integer_type_node,
17429 /* Access to the vec_extract patterns. */
17437 NULL_TREE);
17466 /* Access to the vec_set patterns. */
17468 intHI_type_node,
17474 intHI_type_node,
17478 }
17480 /* Errors in the source file can cause expand_expr to return const0_rtx
17481 where we expect a vector. To avoid crashing, use one of the vector
17482 clear instructions. */
17483 static rtx
17485 {
17489 }
17491 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
17493 static rtx
17495 {
17516 {
17520 }
17522 /* The insn must want input operands in the same modes as the
17523 result. */
17532 /* ??? Using ix86_fixup_binary_operands is problematic when
17533 we've got mismatched modes. Fake it. */
17540 {
17544 }
17546 {
17550 }
17557 }
17559 /* Subroutine of ix86_expand_builtin to take care of stores. */
17561 static rtx
17563 {
17564 rtx pat;
17582 }
17584 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
17586 static rtx
17589 {
17590 rtx pat;
17602 else
17603 {
17610 }
17617 }
17619 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
17620 sqrtss, rsqrtss, rcpss. */
17622 static rtx
17624 {
17625 rtx pat;
17652 }
17654 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
17656 static rtx
17658 rtx target)
17659 {
17660 rtx pat;
17665 rtx op2;
17676 /* Swap operands if we have a comparison that isn't available in
17677 hardware. */
17679 {
17684 }
17704 }
17706 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
17708 static rtx
17710 rtx target)
17711 {
17712 rtx pat;
17717 rtx op2;
17727 /* Swap operands if we have a comparison that isn't available in
17728 hardware. */
17730 {
17734 }
17756 const0_rtx)));
17759 }
17761 /* Return the integer constant in ARG. Constrain it to be in the range
17762 of the subparts of VEC_TYPE; issue an error if not. */
17764 static int
17766 {
17771 {
17774 }
17777 }
17779 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17780 ix86_expand_vector_init. We DO have language-level syntax for this, in
17781 the form of (type){ init-list }. Except that since we can't place emms
17782 instructions from inside the compiler, we can't allow the use of MMX
17783 registers unless the user explicitly asks for it. So we do *not* define
17784 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
17785 we have builtins invoked by mmintrin.h that gives us license to emit
17786 these sorts of instructions. */
17788 static rtx
17790 {
17800 {
17803 }
17810 }
17812 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17813 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
17814 had a language-level syntax for referencing vector elements. */
17816 static rtx
17818 {
17822 rtx op0;
17842 }
17844 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
17845 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
17846 a language-level syntax for referencing vector elements. */
17848 static rtx
17850 {
17877 }
17879 /* Expand an expression EXP that calls a built-in function,
17880 with result going to TARGET if that's convenient
17881 (and in mode MODE if that's convenient).
17882 SUBTARGET may be used as the target for computing one of EXP's operands.
17883 IGNORE is nonzero if the value is to be ignored. */
17885 static rtx
17889 {
17900 {
17912 ? CODE_FOR_mmx_maskmovq
17914 /* Note the arg order is different from the operand order. */
18021 ? CODE_FOR_sse_shufps
18040 {
18041 /* @@@ better error message */
18044 }
18074 {
18075 /* @@@ better error message */
18078 }
18102 {
18105 }
18107 {
18110 }
18248 else
18271 {
18274 }
18275 else
18276 {
18279 }
18292 {
18295 }
18297 {
18300 }
18302 {
18305 }
18323 ? CODE_FOR_sse4a_extrq
18361 {
18364 }
18366 {
18369 }
18403 {
18406 }
18408 {
18411 }
18442 }
18446 {
18447 /* Compares are treated specially. */
18455 }
18466 }
18468 /* Returns a function decl for a vectorized version of the builtin function
18469 with builtin function code FN and the result vector type TYPE, or NULL_TREE
18470 if it is not available. */
18472 static tree
18474 tree type_in)
18475 {
18489 {
18509 ;
18510 }
18513 }
18515 /* Returns a decl of a function that implements conversion of the
18516 input vector of type TYPE, or NULL_TREE if it is not available. */
18518 static tree
18520 {
18525 {
18528 {
18533 }
18537 {
18542 }
18546 }
18547 }
18549 /* Store OPERAND to the memory after reload is completed. This means
18550 that we can't easily use assign_stack_local. */
18551 rtx
18553 {
18554 rtx result;
18558 {
18561 stack_pointer_rtx,
18564 }
18566 {
18568 {
18572 /* FALLTHRU */
18578 stack_pointer_rtx)),
18579 operand));
18583 }
18585 }
18586 else
18587 {
18589 {
18591 {
18598 stack_pointer_rtx)),
18604 stack_pointer_rtx)),
18606 }
18609 /* Store HImodes as SImodes. */
18611 /* FALLTHRU */
18617 stack_pointer_rtx)),
18618 operand));
18622 }
18624 }
18626 }
18628 /* Free operand from the memory. */
18629 void
18631 {
18633 {
18638 else
18640 /* Use LEA to deallocate stack space. In peephole2 it will be converted
18641 to pop or add instruction if registers are available. */
18645 }
18646 }
18648 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
18649 QImode must go into class Q_REGS.
18650 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
18651 movdf to do mem-to-mem moves through integer regs. */
18652 enum reg_class
18654 {
18657 /* We're only allowed to return a subclass of CLASS. Many of the
18658 following checks fail for NO_REGS, so eliminate that early. */
18662 /* All classes can load zeros. */
18666 /* Force constants into memory if we are loading a (nonzero) constant into
18667 an MMX or SSE register. This is because there are no MMX/SSE instructions
18668 to load from a constant. */
18673 /* Prefer SSE regs only, if we can use them for math. */
18677 /* Floating-point constants need more complex checks. */
18679 {
18680 /* General regs can load everything. */
18684 /* Floats can load 0 and 1 plus some others. Note that we eliminated
18685 zero above. We only want to wind up preferring 80387 registers if
18686 we plan on doing computation with them. */
18689 {
18690 /* Limit class to non-sse. */
18699 }
18702 }
18704 /* Generally when we see PLUS here, it's the function invariant
18705 (plus soft-fp const_int). Which can only be computed into general
18706 regs. */
18710 /* QImode constants are easy to load, but non-constant QImode data
18711 must go into Q_REGS. */
18713 {
18719 }
18722 }
18724 /* Discourage putting floating-point values in SSE registers unless
18725 SSE math is being used, and likewise for the 387 registers. */
18726 enum reg_class
18728 {
18731 /* Restrict the output reload class to the register bank that we are doing
18732 math on. If we would like not to return a subset of CLASS, reject this
18733 alternative: if reload cannot do this, it will still use its choice. */
18739 {
18744 else
18746 }
18749 }
18751 /* If we are copying between general and FP registers, we need a memory
18752 location. The same is true for SSE and MMX registers.
18754 The macro can't work reliably when one of the CLASSES is class containing
18755 registers from multiple units (SSE, MMX, integer). We avoid this by never
18756 combining those units in single alternative in the machine description.
18757 Ensure that this constraint holds to avoid unexpected surprises.
18759 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
18760 enforce these sanity checks. */
18762 int
18765 {
18772 {
18775 }
18780 /* ??? This is a lie. We do have moves between mmx/general, and for
18781 mmx/sse2. But by saying we need secondary memory we discourage the
18782 register allocator from using the mmx registers unless needed. */
18787 {
18788 /* SSE1 doesn't have any direct moves from other classes. */
18792 /* If the target says that inter-unit moves are more expensive
18793 than moving through memory, then don't generate them. */
18797 /* Between SSE and general, we have moves no larger than word size. */
18800 }
18803 }
18805 /* Return true if the registers in CLASS cannot represent the change from
18806 modes FROM to TO. */
18808 bool
18811 {
18815 /* x87 registers can't do subreg at all, as all values are reformatted
18816 to extended precision. */
18821 {
18822 /* Vector registers do not support QI or HImode loads. If we don't
18823 disallow a change to these modes, reload will assume it's ok to
18824 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
18825 the vec_dupv4hi pattern. */
18829 /* Vector registers do not support subreg with nonzero offsets, which
18830 are otherwise valid for integer registers. Since we can't see
18831 whether we have a nonzero offset from here, prohibit all
18832 nonparadoxical subregs changing size. */
18835 }
18838 }
18840 /* Return the cost of moving data from a register in class CLASS1 to
18841 one in class CLASS2.
18843 It is not required that the cost always equal 2 when FROM is the same as TO;
18844 on some machines it is expensive to move between registers if they are not
18845 general registers. */
18847 int
18850 {
18851 /* In case we require secondary memory, compute cost of the store followed
18852 by load. In order to avoid bad register allocation choices, we need
18853 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
18856 {
18864 /* In case of copying from general_purpose_register we may emit multiple
18865 stores followed by single load causing memory size mismatch stall.
18866 Count this as arbitrarily high cost of 20. */
18870 /* In the case of FP/MMX moves, the registers actually overlap, and we
18871 have to switch modes in order to treat them differently. */
18877 }
18879 /* Moves between SSE/MMX and integer unit are expensive. */
18890 }
18892 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
18894 bool
18896 {
18897 /* Flags and only flags can only hold CCmode values. */
18907 {
18908 /* We implement the move patterns for all vector modes into and
18909 out of SSE registers, even when no operation instructions
18910 are available. */
18915 }
18917 {
18918 /* We implement the move patterns for 3DNOW modes even in MMX mode,
18919 so if the register is available at all, then we can move data of
18920 the given mode into or out of it. */
18923 }
18926 {
18927 /* Take care for QImode values - they can be in non-QI regs,
18928 but then they do cause partial register stalls. */
18934 }
18935 /* We handle both integer and floats in the general purpose registers. */
18940 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
18941 on to use that value in smaller contexts, this can easily force a
18942 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
18943 supporting DImode, allow it. */
18948 }
18950 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
18951 tieable integer mode. */
18953 static bool
18955 {
18957 {
18970 }
18971 }
18973 /* Return true if MODE1 is accessible in a register that can hold MODE2
18974 without copying. That is, all register classes that can hold MODE2
18975 can also hold MODE1. */
18977 bool
18979 {
18987 /* MODE2 being XFmode implies fp stack or general regs, which means we
18988 can tie any smaller floating point modes to it. Note that we do not
18989 tie this with TFmode. */
18993 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
18994 that we can tie it with SFmode. */
18998 /* If MODE2 is only appropriate for an SSE register, then tie with
18999 any other mode acceptable to SSE registers. */
19005 /* If MODE2 is appropriate for an MMX register, then tie
19006 with any other mode acceptable to MMX registers. */
19013 }
19015 /* Return the cost of moving data of mode M between a
19016 register and memory. A value of 2 is the default; this cost is
19017 relative to those in `REGISTER_MOVE_COST'.
19019 If moving between registers and memory is more expensive than
19020 between two registers, you should define this macro to express the
19021 relative cost.
19023 Model also increased moving costs of QImode registers in non
19024 Q_REGS classes.
19025 */
19026 int
19028 {
19030 {
19033 {
19045 }
19047 }
19049 {
19052 {
19064 }
19066 }
19068 {
19071 {
19080 }
19082 }
19084 {
19089 else
19096 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
19102 }
19103 }
19105 /* Compute a (partial) cost for rtx X. Return true if the complete
19106 cost has been computed, and false if subexpressions should be
19107 scanned. In either case, *TOTAL contains the cost result. */
19109 static bool
19111 {
19115 {
19125 && (!TARGET_64BIT
19130 else
19137 else
19139 {
19148 /* Start with (MEM (SYMBOL_REF)), since that's where
19149 it'll probably end up. Add a penalty for size. */
19154 }
19158 /* The zero extensions is often completely free on x86_64, so make
19159 it as cheap as possible. */
19165 else
19176 {
19179 {
19182 }
19185 {
19188 }
19189 }
19190 /* FALLTHRU */
19197 {
19199 {
19202 else
19204 }
19205 else
19206 {
19209 else
19211 }
19212 }
19213 else
19214 {
19217 else
19219 }
19224 {
19227 }
19228 else
19229 {
19234 {
19237 nbits++;
19238 }
19239 else
19240 /* This is arbitrary. */
19243 /* Compute costs correctly for widening multiplication. */
19247 {
19254 {
19258 else
19260 }
19264 }
19271 }
19279 else
19288 {
19293 {
19296 {
19300 outer_code);
19303 }
19304 }
19307 {
19310 {
19315 }
19316 }
19318 {
19324 }
19325 }
19326 /* FALLTHRU */
19330 {
19333 }
19334 /* FALLTHRU */
19340 {
19347 }
19348 /* FALLTHRU */
19352 {
19355 }
19356 /* FALLTHRU */
19361 else
19370 {
19371 /* This kind of construct is implemented using test[bwl].
19372 Treat it as if we had an AND. */
19377 }
19404 }
19405 }
19407 #if TARGET_MACHO
19411 /* Given a symbol name and its associated stub, write out the
19412 definition of the stub. */
19414 void
19416 {
19421 /* For 64-bit we shouldn't get here. */
19424 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19439 else
19446 {
19450 }
19451 else
19457 {
19460 }
19461 else
19470 }
19472 void
19474 {
19477 }
19480 /* Order the registers for register allocator. */
19482 void
19484 {
19488 /* First allocate the local general purpose registers. */
19493 /* Global general purpose registers. */
19498 /* x87 registers come first in case we are doing FP math
19499 using them. */
19504 /* SSE registers. */
19510 /* x87 registers. */
19518 /* Initialize the rest of array as we do not allocate some registers
19519 at all. */
19522 }
19524 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19525 struct attribute_spec.handler. */
19526 static tree
19528 tree args ATTRIBUTE_UNUSED,
19530 {
19533 {
19536 }
19537 else
19542 {
19546 }
19552 {
19556 }
19559 }
19561 static bool
19563 {
19567 }
19569 /* Returns an expression indicating where the this parameter is
19570 located on entry to the FUNCTION. */
19572 static rtx
19574 {
19578 {
19581 }
19584 {
19585 tree parm;
19588 /* Figure out whether or not the function has a variable number of
19589 arguments. */
19593 /* If not, the this parameter is in the first argument. */
19595 {
19600 }
19601 }
19605 else
19607 }
19609 /* Determine whether x86_output_mi_thunk can succeed. */
19611 static bool
19613 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
19615 {
19616 /* 64-bit can handle anything. */
19620 /* For 32-bit, everything's fine if we have one free register. */
19624 /* Need a free register for vcall_offset. */
19628 /* Need a free register for GOT references. */
19632 /* Otherwise ok. */
19634 }
19636 /* Output the assembler code for a thunk function. THUNK_DECL is the
19637 declaration for the thunk function itself, FUNCTION is the decl for
19638 the target function. DELTA is an immediate constant offset to be
19639 added to THIS. If VCALL_OFFSET is nonzero, the word at
19640 *(*this + vcall_offset) should be added to THIS. */
19642 static void
19646 {
19651 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
19652 pull it in now and let DELTA benefit. */
19656 {
19657 /* Put the this parameter into %eax. */
19661 }
19662 else
19665 /* Adjust the this parameter by a fixed constant. */
19667 {
19671 {
19673 {
19679 }
19681 }
19682 else
19684 }
19686 /* Adjust the this parameter by a value stored in the vtable. */
19688 {
19691 else
19692 {
19698 }
19704 else
19707 /* Adjust the this parameter. */
19710 {
19716 }
19720 else
19722 }
19724 /* If necessary, drop THIS back to its stack slot. */
19726 {
19730 }
19734 {
19737 else
19738 {
19744 }
19745 }
19746 else
19747 {
19750 else
19751 #if TARGET_MACHO
19753 {
19755 tmp = (gen_rtx_SYMBOL_REF
19761 }
19762 else
19764 {
19771 }
19772 }
19773 }
19775 static void
19777 {
19779 #if TARGET_MACHO
19781 #endif
19788 }
19790 int
19792 {
19805 }
19807 /* Output assembler code to FILE to increment profiler label # LABELNO
19808 for profiling a function entry. */
19809 void
19811 {
19814 {
19815 #ifndef NO_PROFILE_COUNTERS
19817 #endif
19819 }
19820 else
19821 {
19822 #ifndef NO_PROFILE_COUNTERS
19824 #endif
19826 }
19828 {
19829 #ifndef NO_PROFILE_COUNTERS
19832 #endif
19834 }
19835 else
19836 {
19837 #ifndef NO_PROFILE_COUNTERS
19839 PROFILE_COUNT_REGISTER);
19840 #endif
19842 }
19843 }
19845 /* We don't have exact information about the insn sizes, but we may assume
19846 quite safely that we are informed about all 1 byte insns and memory
19847 address sizes. This is enough to eliminate unnecessary padding in
19848 99% of cases. */
19850 static int
19852 {
19858 /* Discard alignments we've emit and jump instructions. */
19867 /* Important case - calls are always 5 bytes.
19868 It is common to have many calls in the row. */
19876 /* For normal instructions we may rely on the sizes of addresses
19877 and the presence of symbol to require 4 bytes of encoding.
19878 This is not the case for jumps where references are PC relative. */
19880 {
19884 }
19887 else
19889 }
19891 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
19892 window. */
19894 static void
19896 {
19901 /* Look for all minimal intervals of instructions containing 4 jumps.
19902 The intervals are bounded by START and INSN. NBYTES is the total
19903 size of instructions in the interval including INSN and not including
19904 START. When the NBYTES is smaller than 16 bytes, it is possible
19905 that the end of START and INSN ends up in the same 16byte page.
19907 The smallest offset in the page INSN can start is the case where START
19908 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
19909 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
19910 */
19912 {
19922 njumps++;
19923 else
19927 {
19934 else
19937 }
19944 {
19951 }
19952 }
19953 }
19955 /* AMD Athlon works faster
19956 when RET is not destination of conditional jump or directly preceded
19957 by other jump instruction. We avoid the penalty by inserting NOP just
19958 before the RET instructions in such cases. */
19959 static void
19961 {
19962 edge e;
19963 edge_iterator ei;
19966 {
19969 rtx prev;
19979 {
19980 edge e;
19981 edge_iterator ei;
19987 }
19989 {
19995 /* Empty functions get branch mispredict even when the jump destination
19996 is not visible to us. */
19999 }
20001 {
20004 }
20005 }
20006 }
20008 /* Implement machine specific optimizations. We implement padding of returns
20009 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
20010 static void
20012 {
20017 }
20019 /* Return nonzero when QImode register that must be represented via REX prefix
20020 is used. */
20021 bool
20023 {
20031 }
20033 /* Return nonzero when P points to register encoded via REX prefix.
20034 Called via for_each_rtx. */
20035 static int
20037 {
20043 }
20045 /* Return true when INSN mentions register that must be encoded using REX
20046 prefix. */
20047 bool
20049 {
20051 }
20053 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
20054 optabs would emit if we didn't have TFmode patterns. */
20056 void
20058 {
20092 }
20093 \f
20094 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20095 with all elements equal to VAR. Return true if successful. */
20097 static bool
20100 {
20102 rtx x;
20105 {
20110 /* FALLTHRU */
20125 {
20131 }
20132 else
20133 {
20138 }
20149 {
20151 /* Extend HImode to SImode using a paradoxical SUBREG. */
20154 /* Insert the SImode value as low element of V4SImode vector. */
20159 const1_rtx);
20161 /* Cast the V4SImode vector back to a V8HImode vector. */
20164 /* Duplicate the low short through the whole low SImode word. */
20166 /* Cast the V8HImode vector back to a V4SImode vector. */
20169 /* Replicate the low element of the V4SImode vector. */
20171 /* Cast the V2SImode back to V8HImode, and store in target. */
20174 }
20181 {
20183 /* Extend QImode to SImode using a paradoxical SUBREG. */
20186 /* Insert the SImode value as low element of V4SImode vector. */
20191 const1_rtx);
20193 /* Cast the V4SImode vector back to a V16QImode vector. */
20196 /* Duplicate the low byte through the whole low SImode word. */
20199 /* Cast the V16QImode vector back to a V4SImode vector. */
20202 /* Replicate the low element of the V4SImode vector. */
20204 /* Cast the V2SImode back to V16QImode, and store in target. */
20207 }
20212 widen:
20213 /* Replicate the value once into the next wider mode and recurse. */
20228 }
20229 }
20231 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20232 whose ONE_VAR element is VAR, and other elements are zero. Return true
20233 if successful. */
20235 static bool
20238 {
20240 rtx new_target;
20244 {
20249 /* FALLTHRU */
20264 else
20271 {
20272 /* We need to shuffle the value to the correct position, so
20273 create a new pseudo to store the intermediate result. */
20275 /* With SSE2, we can use the integer shuffle insns. */
20277 {
20286 }
20288 /* Otherwise convert the intermediate result to V4SFmode and
20289 use the SSE1 shuffle instructions. */
20291 {
20294 }
20295 else
20308 }
20323 widen:
20327 /* Zero extend the variable element to SImode and recurse. */
20340 }
20341 }
20343 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20344 consisting of the values in VALS. It is known that all elements
20345 except ONE_VAR are constants. Return true if successful. */
20347 static bool
20350 {
20360 {
20365 /* For the two element vectors, it's just as easy to use
20366 the general case. */
20381 widen:
20382 /* There's no way to set one QImode entry easily. Combine
20383 the variable value with its adjacent constant value, and
20384 promote to an HImode set. */
20387 {
20392 }
20393 else
20394 {
20397 }
20411 }
20416 }
20418 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
20419 all values variable, and none identical. */
20421 static void
20424 {
20430 {
20435 /* FALLTHRU */
20439 /* For the two element vectors, we always implement VEC_CONCAT. */
20451 half:
20452 {
20453 rtvec v;
20455 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
20456 Recurse to load the two halves. */
20467 }
20478 }
20481 {
20489 }
20490 else
20491 {
20503 {
20507 {
20513 else
20514 {
20519 }
20520 }
20523 }
20528 {
20534 }
20536 {
20541 }
20542 else
20544 }
20545 }
20547 /* Initialize vector TARGET via VALS. Suppress the use of MMX
20548 instructions unless MMX_OK is true. */
20550 void
20552 {
20559 rtx x;
20562 {
20570 }
20572 /* Constants are best loaded from the constant pool. */
20574 {
20577 }
20579 /* If all values are identical, broadcast the value. */
20585 /* Values where only one field is non-constant are best loaded from
20586 the pool and overwritten via move later. */
20588 {
20592 one_var))
20597 }
20600 }
20602 void
20604 {
20608 rtx tmp;
20611 {
20615 {
20620 else
20624 }
20629 {
20632 /* For the two element vectors, we implement a VEC_CONCAT with
20633 the extraction of the other element. */
20640 else
20645 }
20650 {
20656 /* tmp = target = A B C D */
20658 /* target = A A B B */
20660 /* target = X A B B */
20662 /* target = A X C D */
20669 /* tmp = target = A B C D */
20671 /* tmp = X B C D */
20673 /* target = A B X D */
20680 /* tmp = target = A B C D */
20682 /* tmp = X B C D */
20684 /* target = A B X D */
20692 }
20696 /* Element 0 handled by vec_merge below. */
20698 {
20701 }
20704 {
20705 /* With SSE2, use integer shuffles to swap element 0 and ELT,
20706 store into element 0, then shuffle them back. */
20723 }
20724 else
20725 {
20726 /* For SSE1, we have to reuse the V4SF code. */
20729 }
20743 }
20746 {
20750 }
20751 else
20752 {
20761 }
20762 }
20764 void
20766 {
20770 rtx tmp;
20773 {
20778 /* FALLTHRU */
20787 {
20807 }
20815 {
20817 {
20837 }
20841 }
20842 else
20843 {
20844 /* For SSE1, we have to reuse the V4SF code. */
20848 }
20860 /* ??? Could extract the appropriate HImode element and shift. */
20863 }
20866 {
20870 /* Let the rtl optimizers know about the zero extension performed. */
20872 {
20875 }
20878 }
20879 else
20880 {
20887 }
20888 }
20890 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
20891 pattern to reduce; DEST is the destination; IN is the input vector. */
20893 void
20895 {
20909 }
20910 \f
20911 /* Target hook for scalar_mode_supported_p. */
20912 static bool
20914 {
20917 else
20919 }
20921 /* Implements target hook vector_mode_supported_p. */
20922 static bool
20924 {
20934 }
20936 /* Worker function for TARGET_MD_ASM_CLOBBERS.
20938 We do this in the new i386 backend to maintain source compatibility
20939 with the old cc0-based compiler. */
20941 static tree
20943 tree inputs ATTRIBUTE_UNUSED,
20944 tree clobbers)
20945 {
20947 clobbers);
20949 clobbers);
20951 }
20953 /* Return true if this goes in small data/bss. */
20955 static bool
20957 {
20961 /* Functions are never large data. */
20966 {
20972 }
20973 else
20974 {
20977 /* If this is an incomplete type with size 0, then we can't put it
20978 in data because it might be too big when completed. */
20981 }
20984 }
20985 static void
20987 {
20994 }
20996 /* Worker function for REVERSE_CONDITION. */
20998 enum rtx_code
21000 {
21004 }
21006 /* Output code to perform an x87 FP register move, from OPERANDS[1]
21007 to OPERANDS[0]. */
21011 {
21014 {
21018 }
21022 }
21024 /* Output code to perform a conditional jump to LABEL, if C2 flag in
21025 FP status register is set. */
21027 void
21029 {
21031 rtx temp;
21036 {
21041 }
21042 else
21043 {
21048 }
21052 pc_rtx);
21057 }
21059 /* Output code to perform a log1p XFmode calculation. */
21062 {
21073 XFmode)));
21087 }
21089 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
21091 static void
21093 tree decl)
21094 {
21095 /* With Binutils 2.15, the "@unwind" marker must be specified on
21096 every occurrence of the ".eh_frame" section, not just the first
21097 one. */
21100 {
21104 }
21106 }
21108 /* Return the mangling of TYPE if it is an extended fundamental type. */
21112 {
21114 {
21116 /* __float128 is "g". */
21119 /* "long double" or __float80 is "e". */
21123 }
21124 }
21126 /* For 32-bit code we can save PIC register setup by using
21127 __stack_chk_fail_local hidden function instead of calling
21128 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
21129 register, so it is better to call __stack_chk_fail directly. */
21131 static tree
21133 {
21134 return TARGET_64BIT
21137 }
21139 /* Select a format to encode pointers in exception handling data. CODE
21140 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
21141 true if the symbol may be affected by dynamic relocations.
21143 ??? All x86 object file formats are capable of representing this.
21144 After all, the relocation needed is the same as for the call insn.
21145 Whether or not a particular assembler allows us to enter such, I
21146 guess we'll have to see. */
21147 int
21149 {
21151 {
21158 }
21163 }
21164 \f
21165 /* Expand copysign from SIGN to the positive value ABS_VALUE
21166 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
21167 the sign-bit. */
21168 static void
21170 {
21174 {
21177 {
21178 /* We need to generate a scalar mode mask in this case. */
21183 }
21184 }
21185 else
21191 }
21193 /* Expand fabs (OP0) and return a new rtx that holds the result. The
21194 mask for masking out the sign-bit is stored in *SMASK, if that is
21195 non-null. */
21196 static rtx
21198 {
21205 {
21206 /* We need to generate a scalar mode mask in this case. */
21211 }
21219 }
21221 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
21222 swapping the operands if SWAP_OPERANDS is true. The expanded
21223 code is a forward jump to a newly created label in case the
21224 comparison is true. The generated label rtx is returned. */
21225 static rtx
21228 {
21232 {
21236 }
21249 }
21251 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
21252 using comparison code CODE. Operands are swapped for the comparison if
21253 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
21254 static rtx
21257 {
21262 {
21266 }
21271 else
21276 }
21278 /* Generate and return a rtx of mode MODE for 2**n where n is the number
21279 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
21280 static rtx
21282 {
21283 REAL_VALUE_TYPE TWO52r;
21284 rtx TWO52;
21291 }
21293 /* Expand SSE sequence for computing lround from OP1 storing
21294 into OP0. */
21295 void
21297 {
21298 /* C code for the stuff we're doing below:
21299 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
21300 return (long)tmp;
21301 */
21305 rtx adj;
21307 /* load nextafter (0.5, 0.0) */
21312 /* adj = copysign (0.5, op1) */
21316 /* adj = op1 + adj */
21319 /* op0 = (imode)adj */
21321 }
21323 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
21324 into OPERAND0. */
21325 void
21327 {
21328 /* C code for the stuff we're doing below (for do_floor):
21329 xi = (long)op1;
21330 xi -= (double)xi > op1 ? 1 : 0;
21331 return xi;
21332 */
21337 /* reg = (long)op1 */
21341 /* freg = (double)reg */
21345 /* ireg = (freg > op1) ? ireg - 1 : ireg */
21356 }
21358 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
21359 result in OPERAND0. */
21360 void
21362 {
21363 /* C code for the stuff we're doing below:
21364 xa = fabs (operand1);
21365 if (!isless (xa, 2**52))
21366 return operand1;
21367 xa = xa + 2**52 - 2**52;
21368 return copysign (xa, operand1);
21369 */
21376 /* xa = abs (operand1) */
21379 /* if (!isless (xa, TWO52)) goto label; */
21392 }
21394 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
21395 into OPERAND0. */
21396 void
21398 {
21399 /* C code for the stuff we expand below.
21400 double xa = fabs (x), x2;
21401 if (!isless (xa, TWO52))
21402 return x;
21403 xa = xa + TWO52 - TWO52;
21404 x2 = copysign (xa, x);
21405 Compensate. Floor:
21406 if (x2 > x)
21407 x2 -= 1;
21408 Compensate. Ceil:
21409 if (x2 < x)
21410 x2 -= -1;
21411 return x2;
21412 */
21418 /* Temporary for holding the result, initialized to the input
21419 operand to ease control flow. */
21423 /* xa = abs (operand1) */
21426 /* if (!isless (xa, TWO52)) goto label; */
21429 /* xa = xa + TWO52 - TWO52; */
21433 /* xa = copysign (xa, operand1) */
21436 /* generate 1.0 or -1.0 */
21441 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
21445 /* We always need to subtract here to preserve signed zero. */
21454 }
21456 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
21457 into OPERAND0. */
21458 void
21460 {
21461 /* C code for the stuff we expand below.
21462 double xa = fabs (x), x2;
21463 if (!isless (xa, TWO52))
21464 return x;
21465 x2 = (double)(long)x;
21466 Compensate. Floor:
21467 if (x2 > x)
21468 x2 -= 1;
21469 Compensate. Ceil:
21470 if (x2 < x)
21471 x2 += 1;
21472 if (HONOR_SIGNED_ZEROS (mode))
21473 return copysign (x2, x);
21474 return x2;
21475 */
21481 /* Temporary for holding the result, initialized to the input
21482 operand to ease control flow. */
21486 /* xa = abs (operand1) */
21489 /* if (!isless (xa, TWO52)) goto label; */
21492 /* xa = (double)(long)x */
21497 /* generate 1.0 */
21500 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
21515 }
21517 /* Expand SSE sequence for computing round from OPERAND1 storing
21518 into OPERAND0. Sequence that works without relying on DImode truncation
21519 via cvttsd2siq that is only available on 64bit targets. */
21520 void
21522 {
21523 /* C code for the stuff we expand below.
21524 double xa = fabs (x), xa2, x2;
21525 if (!isless (xa, TWO52))
21526 return x;
21527 Using the absolute value and copying back sign makes
21528 -0.0 -> -0.0 correct.
21529 xa2 = xa + TWO52 - TWO52;
21530 Compensate.
21531 dxa = xa2 - xa;
21532 if (dxa <= -0.5)
21533 xa2 += 1;
21534 else if (dxa > 0.5)
21535 xa2 -= 1;
21536 x2 = copysign (xa2, x);
21537 return x2;
21538 */
21544 /* Temporary for holding the result, initialized to the input
21545 operand to ease control flow. */
21549 /* xa = abs (operand1) */
21552 /* if (!isless (xa, TWO52)) goto label; */
21555 /* xa2 = xa + TWO52 - TWO52; */
21559 /* dxa = xa2 - xa; */
21562 /* generate 0.5, 1.0 and -0.5 */
21568 /* Compensate. */
21570 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
21575 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
21581 /* res = copysign (xa2, operand1) */
21588 }
21590 /* Expand SSE sequence for computing trunc from OPERAND1 storing
21591 into OPERAND0. */
21592 void
21594 {
21595 /* C code for SSE variant we expand below.
21596 double xa = fabs (x), x2;
21597 if (!isless (xa, TWO52))
21598 return x;
21599 x2 = (double)(long)x;
21600 if (HONOR_SIGNED_ZEROS (mode))
21601 return copysign (x2, x);
21602 return x2;
21603 */
21609 /* Temporary for holding the result, initialized to the input
21610 operand to ease control flow. */
21614 /* xa = abs (operand1) */
21617 /* if (!isless (xa, TWO52)) goto label; */
21620 /* x = (double)(long)x */
21632 }
21634 /* Expand SSE sequence for computing trunc from OPERAND1 storing
21635 into OPERAND0. */
21636 void
21638 {
21642 /* C code for SSE variant we expand below.
21643 double xa = fabs (x), x2;
21644 if (!isless (xa, TWO52))
21645 return x;
21646 xa2 = xa + TWO52 - TWO52;
21647 Compensate:
21648 if (xa2 > xa)
21649 xa2 -= 1.0;
21650 x2 = copysign (xa2, x);
21651 return x2;
21652 */
21656 /* Temporary for holding the result, initialized to the input
21657 operand to ease control flow. */
21661 /* xa = abs (operand1) */
21664 /* if (!isless (xa, TWO52)) goto label; */
21667 /* res = xa + TWO52 - TWO52; */
21672 /* generate 1.0 */
21675 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
21683 /* res = copysign (res, operand1) */
21690 }
21692 /* Expand SSE sequence for computing round from OPERAND1 storing
21693 into OPERAND0. */
21694 void
21696 {
21697 /* C code for the stuff we're doing below:
21698 double xa = fabs (x);
21699 if (!isless (xa, TWO52))
21700 return x;
21701 xa = (double)(long)(xa + nextafter (0.5, 0.0));
21702 return copysign (xa, x);
21703 */
21709 /* Temporary for holding the result, initialized to the input
21710 operand to ease control flow. */
21718 /* load nextafter (0.5, 0.0) */
21723 /* xa = xa + 0.5 */
21727 /* xa = (double)(int64_t)xa */
21732 /* res = copysign (xa, operand1) */
21739 }