1 ;; Machine description for RISC-V atomic operations.
2 ;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
3 ;; Contributed by Andrew Waterman (andrew@sifive.com).
4 ;; Based on MIPS target for GNU compiler.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
24 (define_insn "mem_thread_fence_rvwmo"
25 [(set (match_operand:BLK 0 "" "")
26 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
27 (match_operand:SI 1 "const_int_operand" "")] ;; model
30 enum memmodel model = (enum memmodel) INTVAL (operands[1]);
31 model = memmodel_base (model);
33 if (model == MEMMODEL_SEQ_CST)
34 return "fence\trw,rw";
35 else if (model == MEMMODEL_ACQ_REL)
37 else if (model == MEMMODEL_ACQUIRE)
39 else if (model == MEMMODEL_RELEASE)
44 [(set_attr "type" "atomic")
45 (set (attr "length") (const_int 4))])
47 ;; Atomic memory operations.
49 (define_insn "atomic_load_rvwmo<mode>"
50 [(set (match_operand:GPR 0 "register_operand" "=r")
52 [(match_operand:GPR 1 "memory_operand" "A")
53 (match_operand:SI 2 "const_int_operand")] ;; model
57 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
58 model = memmodel_base (model);
60 if (model == MEMMODEL_SEQ_CST)
61 return "fence\trw,rw\;"
64 if (model == MEMMODEL_ACQUIRE)
65 return "l<amo>\t%0,%1\;"
68 return "l<amo>\t%0,%1";
70 [(set_attr "type" "multi")
71 (set (attr "length") (const_int 12))])
73 ;; Implement atomic stores with conservative fences.
74 ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7.
75 (define_insn "atomic_store_rvwmo<mode>"
76 [(set (match_operand:GPR 0 "memory_operand" "=A")
78 [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
79 (match_operand:SI 2 "const_int_operand")] ;; model
80 UNSPEC_ATOMIC_STORE))]
83 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
84 model = memmodel_base (model);
86 if (model == MEMMODEL_SEQ_CST)
87 return "fence\trw,w\;"
90 if (model == MEMMODEL_RELEASE)
91 return "fence\trw,w\;"
94 return "s<amo>\t%z1,%0";
96 [(set_attr "type" "multi")
97 (set (attr "length") (const_int 12))])