| blob | bc75f8ba3b858e7d8737e44e9b44f88d0d2de4c7 |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* The minimal number of prefetch blocks that a loop must consume to make
83 the emitting of prefetch instruction in the body of loop worthwhile. */
84 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
86 /* Parameterize some prefetch heuristics so they can be turned on and off
87 easily for performance testing on new architecures. These can be
88 defined in target-dependent files. */
90 /* Prefetch is worthwhile only when loads/stores are dense. */
91 #ifndef PREFETCH_ONLY_DENSE_MEM
92 #define PREFETCH_ONLY_DENSE_MEM 1
93 #endif
95 /* Define what we mean by "dense" loads and stores; This value divided by 256
96 is the minimum percentage of memory references that worth prefetching. */
97 #ifndef PREFETCH_DENSE_MEM
98 #define PREFETCH_DENSE_MEM 220
99 #endif
101 /* Do not prefetch for a loop whose iteration count is known to be low. */
102 #ifndef PREFETCH_NO_LOW_LOOPCNT
103 #define PREFETCH_NO_LOW_LOOPCNT 1
104 #endif
106 /* Define what we mean by a "low" iteration count. */
107 #ifndef PREFETCH_LOW_LOOPCNT
108 #define PREFETCH_LOW_LOOPCNT 32
109 #endif
111 /* Do not prefetch for a loop that contains a function call; such a loop is
112 probably not an internal loop. */
113 #ifndef PREFETCH_NO_CALL
114 #define PREFETCH_NO_CALL 1
115 #endif
117 /* Do not prefetch accesses with an extreme stride. */
118 #ifndef PREFETCH_NO_EXTREME_STRIDE
119 #define PREFETCH_NO_EXTREME_STRIDE 1
120 #endif
122 /* Define what we mean by an "extreme" stride. */
123 #ifndef PREFETCH_EXTREME_STRIDE
124 #define PREFETCH_EXTREME_STRIDE 4096
125 #endif
127 /* Define a limit to how far apart indices can be and still be merged
128 into a single prefetch. */
129 #ifndef PREFETCH_EXTREME_DIFFERENCE
130 #define PREFETCH_EXTREME_DIFFERENCE 4096
131 #endif
133 /* Issue prefetch instructions before the loop to fetch data to be used
134 in the first few loop iterations. */
135 #ifndef PREFETCH_BEFORE_LOOP
136 #define PREFETCH_BEFORE_LOOP 1
137 #endif
139 /* Do not handle reversed order prefetches (negative stride). */
140 #ifndef PREFETCH_NO_REVERSE_ORDER
141 #define PREFETCH_NO_REVERSE_ORDER 1
142 #endif
144 /* Prefetch even if the GIV is in conditional code. */
145 #ifndef PREFETCH_CONDITIONAL
146 #define PREFETCH_CONDITIONAL 1
147 #endif
149 /* If the loop requires more prefetches than the target can process in
150 parallel then don't prefetch anything in that loop. */
151 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
152 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
153 #endif
155 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
156 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
158 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
159 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
160 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
162 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
163 ((REGNO) < FIRST_PSEUDO_REGISTER \
164 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
167 /* Vector mapping INSN_UIDs to luids.
168 The luids are like uids but increase monotonically always.
169 We use them to see whether a jump comes from outside a given loop. */
173 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
174 number the insn is contained in. */
178 /* 1 + largest uid of any insn. */
182 /* 1 + luid of last insn. */
186 /* Number of loops detected in current function. Used as index to the
187 next few tables. */
191 /* Bound on pseudo register number before loop optimization.
192 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
195 /* The value to pass to the next call of reg_scan_update. */
198 #define obstack_chunk_alloc xmalloc
199 #define obstack_chunk_free free
200 \f
201 /* During the analysis of a loop, a chain of `struct movable's
202 is made to record all the movable insns found.
203 Then the entire chain can be scanned to decide which to move. */
205 struct movable
206 {
211 of any registers used within the LIBCALL. */
213 that must be moved with this one. */
216 may be adjusted when matching movables
217 that load the same value are found. */
219 including other movables that force this
220 or match this one. */
224 /* If PARTIAL is 1, GLOBAL means something different:
225 that the reg is live outside the range from where it is set
226 to the following label. */
230 In particular, moving it does not make it
231 invariant. */
233 load SRC, rather than copying INSN. */
235 first insn of a consecutive sets group. */
238 that we should avoid changing when clearing
239 the rest of the reg. */
243 };
248 /* Forward declarations. */
263 #if 0
265 #endif
295 rtx *));
378 {
379 rtx r1;
380 rtx r2;
384 {
385 rtx match;
386 rtx replacement;
387 rtx insn;
390 /* Nonzero iff INSN is between START and END, inclusive. */
391 #define INSN_IN_RANGE_P(INSN, START, END) \
392 (INSN_UID (INSN) < max_uid_for_loop \
393 && INSN_LUID (INSN) >= INSN_LUID (START) \
394 && INSN_LUID (INSN) <= INSN_LUID (END))
396 /* Indirect_jump_in_function is computed once per function. */
404 rtx));
405 \f
406 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
407 copy the value of the strength reduced giv to its original register. */
410 /* Cost of using a register, to normalize the benefits of a giv. */
413 void
415 {
421 }
422 \f
423 /* Compute the mapping from uids to luids.
424 LUIDs are numbers assigned to insns, like uids,
425 except that luids increase monotonically through the code.
426 Start at insn START and stop just before END. Assign LUIDs
427 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
428 static int
432 {
434 rtx insn;
437 {
440 /* Don't assign luids to line-number NOTEs, so that the distance in
441 luids between two insns is not affected by -g. */
445 else
446 /* Give a line number note the same luid as preceding insn. */
448 }
450 }
451 \f
452 /* Entry point of this file. Perform loop optimization
453 on the current function. F is the first insn of the function
454 and DUMPFILE is a stream for output of a trace of actions taken
455 (or 0 if none should be output). */
457 void
459 /* f is the first instruction of a chain of insns for one function */
460 rtx f;
463 {
464 rtx insn;
479 /* Count the number of loops. */
483 {
486 max_loop_num++;
487 }
489 /* Don't waste time if no loops. */
495 /* Get size to use for tables indexed by uids.
496 Leave some space for labels allocated by find_and_verify_loops. */
503 /* Allocate storage for array of loops. */
507 /* Find and process each loop.
508 First, find them, and record them in order of their beginnings. */
511 /* Allocate and initialize auxiliary loop information. */
516 /* Now find all register lifetimes. This must be done after
517 find_and_verify_loops, because it might reorder the insns in the
518 function. */
521 /* This must occur after reg_scan so that registers created by gcse
522 will have entries in the register tables.
524 We could have added a call to reg_scan after gcse_main in toplev.c,
525 but moving this call to init_alias_analysis is more efficient. */
528 /* See if we went too far. Note that get_max_uid already returns
529 one more that the maximum uid of all insn. */
532 /* Now reset it to the actual size we need. See above. */
535 /* find_and_verify_loops has already called compute_luids, but it
536 might have rearranged code afterwards, so we need to recompute
537 the luids now. */
540 /* Don't leave gaps in uid_luid for insns that have been
541 deleted. It is possible that the first or last insn
542 using some register has been deleted by cross-jumping.
543 Make sure that uid_luid for that former insn's uid
544 points to the general area where that insn used to be. */
546 {
550 }
555 /* Determine if the function has indirect jump. On some systems
556 this prevents low overhead loop instructions from being used. */
559 /* Now scan the loops, last ones first, since this means inner ones are done
560 before outer ones. */
562 {
567 }
571 /* Clean up. */
576 }
577 \f
578 /* Returns the next insn, in execution order, after INSN. START and
579 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
580 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
581 insn-stream; it is used with loops that are entered near the
582 bottom. */
584 static rtx
587 rtx insn;
588 {
592 {
594 /* Go to the top of the loop, and continue there. */
596 else
597 /* We're done. */
599 }
602 /* We're done. */
606 }
608 /* Optimize one loop described by LOOP. */
610 /* ??? Could also move memory writes out of loops if the destination address
611 is invariant, the source is invariant, the memory write is not volatile,
612 and if we can prove that no read inside the loop can read this address
613 before the write occurs. If there is a read of this address after the
614 write, then we can also mark the memory read as invariant. */
616 static void
620 {
626 rtx p;
627 /* 1 if we are scanning insns that could be executed zero times. */
629 /* 1 if we are scanning insns that might never be executed
630 due to a subroutine call which might exit before they are reached. */
632 /* Jump insn that enters the loop, or 0 if control drops in. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
647 /* Nonzero if we are scanning instructions in a sub-loop. */
655 /* Determine whether this loop starts with a jump down to a test at
656 the end. This will occur for a small number of loops with a test
657 that is too complex to duplicate in front of the loop.
659 We search for the first insn or label in the loop, skipping NOTEs.
660 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
661 (because we might have a loop executed only once that contains a
662 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
663 (in case we have a degenerate loop).
665 Note that if we mistakenly think that a loop is entered at the top
666 when, in fact, it is entered at the exit test, the only effect will be
667 slightly poorer optimization. Making the opposite error can generate
668 incorrect code. Since very few loops now start with a jump to the
669 exit test, the code here to detect that case is very conservative. */
672 p != loop_end
678 ;
682 /* If loop end is the end of the current function, then emit a
683 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
684 note insn. This is the position we use when sinking insns out of
685 the loop. */
688 else
691 /* Set up variables describing this loop. */
695 /* If loop has a jump before the first label,
696 the true entry is the target of that jump.
697 Start scan from there.
698 But record in LOOP->TOP the place where the end-test jumps
699 back to so we can scan that after the end of the loop. */
701 {
704 /* Loop entry must be unconditional jump (and not a RETURN) */
707 /* Check to see whether the jump actually
708 jumps out of the loop (meaning it's no loop).
709 This case can happen for things like
710 do {..} while (0). If this label was generated previously
711 by loop, we can't tell anything about it and have to reject
712 the loop. */
714 {
717 }
718 }
720 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
721 as required by loop_reg_used_before_p. So skip such loops. (This
722 test may never be true, but it's best to play it safe.)
724 Also, skip loops where we do not start scanning at a label. This
725 test also rejects loops starting with a JUMP_INSN that failed the
726 test above. */
730 {
735 }
737 /* Allocate extra space for REGs that might be created by load_mems.
738 We allocate a little extra slop as well, in the hopes that we
739 won't have to reallocate the regs array. */
744 {
750 }
752 /* Scan through the loop finding insns that are safe to move.
753 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
754 this reg will be considered invariant for subsequent insns.
755 We consider whether subsequent insns use the reg
756 in deciding whether it is worth actually moving.
758 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
759 and therefore it is possible that the insns we are scanning
760 would never be executed. At such times, we must make sure
761 that it is safe to execute the insn once instead of zero times.
762 When MAYBE_NEVER is 0, all insns will be executed at least once
763 so that is not a problem. */
768 {
772 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
774 #endif
776 {
783 /* Figure out what to use as a source of this insn. If a REG_EQUIV
784 note is given or if a REG_EQUAL note with a constant operand is
785 specified, use it as the source and mark that we should move
786 this insn by calling emit_move_insn rather that duplicating the
787 insn.
789 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
790 is present. */
794 else
795 {
800 {
802 /* A libcall block can use regs that don't appear in
803 the equivalent expression. To move the libcall,
804 we must move those regs too. */
806 }
807 }
809 /* For parallels, add any possible uses to the depencies, as we can't move
810 the insn without resolving them first. */
812 {
814 {
818 }
819 }
821 /* Don't try to optimize a register that was made
822 by loop-optimization for an inner loop.
823 We don't know its life-span, so we can't compute the benefit. */
825 ;
827 than the one where it is set (meaning that
828 something after this point in the loop might
829 depend on its value before the set). */
831 /* And the set is not guaranteed to be executed once
832 the loop starts, or the value before the set is
833 needed before the set occurs...
835 ??? Note we have quadratic behaviour here, mitigated
836 by the fact that the previous test will often fail for
837 large loops. Rather than re-scanning the entire loop
838 each time for register usage, we should build tables
839 of the register usage and use them here instead. */
840 && (maybe_never
842 /* It is unsafe to move the set.
844 This code used to consider it OK to move a set of a variable
845 which was not created by the user and not used in an exit test.
846 That behavior is incorrect and was removed. */
847 ;
852 || (tem1
853 = consec_sets_invariant_p
856 p)))
857 /* If the insn can cause a trap (such as divide by zero),
858 can't move it unless it's guaranteed to be executed
859 once loop is entered. Even a function call might
860 prevent the trap insn from being reached
861 (since it might exit!) */
864 {
868 /* A potential lossage is where we have a case where two insns
869 can be combined as long as they are both in the loop, but
870 we move one of them outside the loop. For large loops,
871 this can lose. The most common case of this is the address
872 of a function being called.
874 Therefore, if this register is marked as being used exactly
875 once if we are in a loop with calls (a "large loop"), see if
876 we can replace the usage of this register with the source
877 of this SET. If we can, delete this insn.
879 Don't do this if P has a REG_RETVAL note or if we have
880 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
892 && (! SMALL_REGISTER_CLASSES
895 /* This test is not redundant; SET_SRC (set) might be
896 a call-clobbered register and the life of REGNO
897 might span a call. */
903 {
904 /* Replace any usage in a REG_EQUAL note. Must copy the
905 new source, so that we don't get rtx sharing between the
906 SET_SOURCE and REG_NOTES of insn p. */
915 }
933 /* Set M->cond if either loop_invariant_p
934 or consec_sets_invariant_p returned 2
935 (only conditionally invariant). */
945 /* Add M to the end of the chain MOVABLES. */
949 {
950 /* It is possible for the first instruction to have a
951 REG_EQUAL note but a non-invariant SET_SRC, so we must
952 remember the status of the first instruction in case
953 the last instruction doesn't have a REG_EQUAL note. */
956 /* Skip this insn, not checking REG_LIBCALL notes. */
958 /* Skip the consecutive insns, if there are any. */
960 /* Back up to the last insn of the consecutive group. */
963 /* We must now reset m->move_insn, m->is_equiv, and possibly
964 m->set_src to correspond to the effects of all the
965 insns. */
969 else
970 {
974 else
977 }
979 }
980 }
981 /* If this register is always set within a STRICT_LOW_PART
982 or set to zero, then its high bytes are constant.
983 So clear them outside the loop and within the loop
984 just load the low bytes.
985 We must check that the machine has an instruction to do so.
986 Also, if the value loaded into the register
987 depends on the same register, this cannot be done. */
997 {
1000 {
1014 /* If the insn may not be executed on some cycles,
1015 we can't clear the whole reg; clear just high part.
1016 Not even if the reg is used only within this loop.
1017 Consider this:
1018 while (1)
1019 while (s != t) {
1020 if (foo ()) x = *s;
1021 use (x);
1022 }
1023 Clearing x before the inner loop could clobber a value
1024 being saved from the last time around the outer loop.
1025 However, if the reg is not used outside this loop
1026 and all uses of the register are in the same
1027 basic block as the store, there is no problem.
1029 If this insn was made by loop, we don't know its
1030 INSN_LUID and hence must make a conservative
1031 assumption. */
1034 || (labels_in_range_p
1038 else
1047 /* Add M to the end of the chain MOVABLES. */
1049 }
1050 }
1051 }
1052 /* Past a call insn, we get to insns which might not be executed
1053 because the call might exit. This matters for insns that trap.
1054 Constant and pure call insns always return, so they don't count. */
1057 /* Past a label or a jump, we get to insns for which we
1058 can't count on whether or how many times they will be
1059 executed during each iteration. Therefore, we can
1060 only move out sets of trivial variables
1061 (those not used after the loop). */
1062 /* Similar code appears twice in strength_reduce. */
1064 /* If we enter the loop in the middle, and scan around to the
1065 beginning, don't set maybe_never for that. This must be an
1066 unconditional jump, otherwise the code at the top of the
1067 loop might never be executed. Unconditional jumps are
1068 followed by a barrier then the loop_end. */
1074 {
1075 /* At the virtual top of a converted loop, insns are again known to
1076 be executed: logically, the loop begins here even though the exit
1077 code has been duplicated. */
1081 loop_depth++;
1083 loop_depth--;
1084 }
1085 }
1087 /* If one movable subsumes another, ignore that other. */
1091 /* For each movable insn, see if the reg that it loads
1092 leads when it dies right into another conditionally movable insn.
1093 If so, record that the second insn "forces" the first one,
1094 since the second can be moved only if the first is. */
1098 /* See if there are multiple movable insns that load the same value.
1099 If there are, make all but the first point at the first one
1100 through the `match' field, and add the priorities of them
1101 all together as the priority of the first. */
1105 /* Now consider each movable insn to decide whether it is worth moving.
1106 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1108 Generally this increases code size, so do not move moveables when
1109 optimizing for code size. */
1112 {
1115 /* Recalculate regs->array if move_movables has created new
1116 registers. */
1118 {
1124 ;
1129 }
1130 }
1132 /* Now candidates that still are negative are those not moved.
1133 Change regs->array[I].set_in_loop to indicate that those are not actually
1134 invariant. */
1139 /* Now that we've moved some things out of the loop, we might be able to
1140 hoist even more memory references. */
1143 /* Recalculate regs->array if load_mems has created new registers. */
1151 ;
1158 {
1160 /* Ensure our label doesn't go away. */
1171 }
1174 /* The movable information is required for strength reduction. */
1180 }
1181 \f
1182 /* Add elements to *OUTPUT to record all the pseudo-regs
1183 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1185 void
1189 {
1197 {
1215 }
1219 {
1223 {
1232 }
1233 }
1234 }
1235 \f
1236 /* Check what regs are referred to in the libcall block ending with INSN,
1237 aside from those mentioned in the equivalent value.
1238 If there are none, return 0.
1239 If there are one or more, return an EXPR_LIST containing all of them. */
1241 rtx
1244 {
1249 /* First, find all the regs used in the libcall block
1250 that are not mentioned as inputs to the result. */
1253 {
1258 }
1261 }
1262 \f
1263 /* Return 1 if all uses of REG
1264 are between INSN and the end of the basic block. */
1266 static int
1269 {
1271 rtx p;
1276 /* Search this basic block for the already recorded last use of the reg. */
1278 {
1280 {
1286 /* Ordinary insn: if this is the last use, we win. */
1292 /* Jump insn: if this is the last use, we win. */
1295 /* Otherwise, it's the end of the basic block, so we lose. */
1300 /* It's the end of the basic block, so we lose. */
1305 }
1306 }
1308 /* The "last use" that was recorded can't be found after the first
1309 use. This can happen when the last use was deleted while
1310 processing an inner loop, this inner loop was then completely
1311 unrolled, and the outer loop is always exited after the inner loop,
1312 so that everything after the first use becomes a single basic block. */
1314 }
1315 \f
1316 /* Compute the benefit of eliminating the insns in the block whose
1317 last insn is LAST. This may be a group of insns used to compute a
1318 value directly or can contain a library call. */
1320 static int
1322 rtx last;
1323 {
1324 rtx insn;
1329 {
1332 routine. */
1336 benefit++;
1337 }
1340 }
1341 \f
1342 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1344 static rtx
1346 rtx insn;
1348 {
1350 {
1351 rtx temp;
1353 /* If first insn of libcall sequence, skip to end. */
1354 /* Do this at start of loop, since INSN is guaranteed to
1355 be an insn here. */
1360 do
1363 }
1366 }
1368 /* Ignore any movable whose insn falls within a libcall
1369 which is part of another movable.
1370 We make use of the fact that the movable for the libcall value
1371 was made later and so appears later on the chain. */
1373 static void
1376 {
1380 {
1381 /* Is this a movable for the value of a libcall? */
1384 {
1385 rtx insn;
1386 /* Check for earlier movables inside that range,
1387 and mark them invalid. We cannot use LUIDs here because
1388 insns created by loop.c for prior loops don't have LUIDs.
1389 Rather than reject all such insns from movables, we just
1390 explicitly check each insn in the libcall (since invariant
1391 libcalls aren't that common). */
1396 }
1397 }
1398 }
1400 /* For each movable insn, see if the reg that it loads
1401 leads when it dies right into another conditionally movable insn.
1402 If so, record that the second insn "forces" the first one,
1403 since the second can be moved only if the first is. */
1405 static void
1408 {
1412 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1414 {
1417 /* ??? Could this be a bug? What if CSE caused the
1418 register of M1 to be used after this insn?
1419 Since CSE does not update regno_last_uid,
1420 this insn M->insn might not be where it dies.
1421 But very likely this doesn't matter; what matters is
1422 that M's reg is computed from M1's reg. */
1427 /* If m->consec, m->set_src isn't valid. */
1431 /* Increase the priority of the moving the first insn
1432 since it permits the second to be moved as well. */
1434 {
1438 }
1439 }
1440 }
1441 \f
1442 /* Find invariant expressions that are equal and can be combined into
1443 one register. */
1445 static void
1449 {
1454 /* Regs that are set more than once are not allowed to match
1455 or be matched. I'm no longer sure why not. */
1456 /* Only pseudo registers are allowed to match or be matched,
1457 since move_movables does not validate the change. */
1458 /* Perhaps testing m->consec_sets would be more appropriate here? */
1464 {
1471 /* We want later insns to match the first one. Don't make the first
1472 one match any later ones. So start this loop at m->next. */
1477 /* A reg used outside the loop mustn't be eliminated. */
1479 /* A reg used for zero-extending mustn't be eliminated. */
1482 ||
1483 (
1484 /* Can combine regs with different modes loaded from the
1485 same constant only if the modes are the same or
1486 if both are integer modes with M wider or the same
1487 width as M1. The check for integer is redundant, but
1488 safe, since the only case of differing destination
1489 modes with equal sources is when both sources are
1490 VOIDmode, i.e., CONST_INT. */
1496 /* See if the source of M1 says it matches M. */
1503 {
1509 }
1510 }
1512 /* Now combine the regs used for zero-extension.
1513 This can be done for those not marked `global'
1514 provided their lives don't overlap. */
1518 {
1521 /* Combine all the registers for extension from mode MODE.
1522 Don't combine any that are used outside this loop. */
1526 {
1533 {
1534 /* First one: don't check for overlap, just record it. */
1537 }
1539 /* Make sure they extend to the same mode.
1540 (Almost always true.) */
1544 /* We already have one: check for overlap with those
1545 already combined together. */
1552 /* No overlap: we can combine this with the others. */
1558 overlap:
1559 ;
1560 }
1561 }
1563 /* Clean up. */
1565 }
1567 /* Returns the number of movable instructions in LOOP that were not
1568 moved outside the loop. */
1570 static int
1573 {
1582 }
1584 \f
1585 /* Return 1 if regs X and Y will become the same if moved. */
1587 static int
1591 {
1608 }
1610 /* Return 1 if X and Y are identical-looking rtx's.
1611 This is the Lisp function EQUAL for rtx arguments.
1613 If two registers are matching movables or a movable register and an
1614 equivalent constant, consider them equal. */
1616 static int
1621 {
1635 /* If we have a register and a constant, they may sometimes be
1636 equal. */
1639 {
1644 }
1647 {
1652 }
1654 /* Otherwise, rtx's of different codes cannot be equal. */
1658 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1659 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1664 /* These three types of rtx's can be compared nonrecursively. */
1673 /* Compare the elements. If any pair of corresponding elements
1674 fail to match, return 0 for the whole things. */
1678 {
1680 {
1692 /* Two vectors must have the same length. */
1696 /* And the corresponding elements must match. */
1715 /* These are just backpointers, so they don't matter. */
1721 /* It is believed that rtx's at this level will never
1722 contain anything but integers and other rtx's,
1723 except for within LABEL_REFs and SYMBOL_REFs. */
1726 }
1727 }
1729 }
1730 \f
1731 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1732 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1733 references is incremented once for each added note. */
1735 static void
1737 rtx x;
1738 rtx insns;
1739 {
1743 rtx insn;
1746 {
1747 /* This code used to ignore labels that referred to dispatch tables to
1748 avoid flow generating (slighly) worse code.
1750 We no longer ignore such label references (see LABEL_REF handling in
1751 mark_jump_label for additional information). */
1754 {
1759 }
1760 }
1764 {
1770 }
1771 }
1772 \f
1773 /* Scan MOVABLES, and move the insns that deserve to be moved.
1774 If two matching movables are combined, replace one reg with the
1775 other throughout. */
1777 static void
1783 {
1788 rtx p;
1791 /* Map of pseudo-register replacements to handle combining
1792 when we move several insns that load the same value
1793 into different pseudo-registers. */
1798 {
1799 /* Describe this movable insn. */
1802 {
1823 }
1825 /* Ignore the insn if it's already done (it matched something else).
1826 Otherwise, see if it is now safe to move. */
1838 {
1840 rtx p;
1843 /* We have an insn that is safe to move.
1844 Compute its desirability. */
1855 /* An insn MUST be moved if we already moved something else
1856 which is safe only if this one is moved too: that is,
1857 if already_moved[REGNO] is nonzero. */
1859 /* An insn is desirable to move if the new lifetime of the
1860 register is no more than THRESHOLD times the old lifetime.
1861 If it's not desirable, it means the loop is so big
1862 that moving won't speed things up much,
1863 and it is liable to make register usage worse. */
1865 /* It is also desirable to move if it can be moved at no
1866 extra cost because something else was already moved. */
1869 || flag_move_all_movables
1874 {
1879 /* Now move the insns that set the reg. */
1882 {
1885 /* Find the end of this chain of matching regs.
1886 Thus, we load each reg in the chain from that one reg.
1887 And that reg is loaded with 0 directly,
1888 since it has ->match == 0. */
1894 /* Mark the moved, invariant reg as being allowed to
1895 share a hard reg with the other matching invariant. */
1899 regs_may_share
1902 regs_may_share));
1910 }
1911 /* If we are to re-generate the item being moved with a
1912 new move insn, first delete what we have and then emit
1913 the move insn before the loop. */
1915 {
1919 {
1920 /* If this is the first insn of a library call sequence,
1921 skip to the end. */
1926 /* If this is the last insn of a libcall sequence, then
1927 delete every insn in the sequence except the last.
1928 The last insn is handled in the normal manner. */
1931 {
1935 }
1940 /* simplify_giv_expr expects that it can walk the insns
1941 at m->insn forwards and see this old sequence we are
1942 tossing here. delete_insn does preserve the next
1943 pointers, but when we skip over a NOTE we must fix
1944 it up. Otherwise that code walks into the non-deleted
1945 insn stream. */
1948 }
1967 /* The more regs we move, the less we like moving them. */
1969 }
1970 else
1971 {
1973 {
1976 /* If first insn of libcall sequence, skip to end. */
1977 /* Do this at start of loop, since p is guaranteed to
1978 be an insn here. */
1983 /* If last insn of libcall sequence, move all
1984 insns except the last before the loop. The last
1985 insn is handled in the normal manner. */
1988 {
1996 {
1997 rtx body;
1998 rtx n;
1999 rtx next;
2006 /* Find the next insn after TEMP,
2007 not counting USE or NOTE insns. */
2015 /* If that is the call, this may be the insn
2016 that loads the function address.
2018 Extract the function address from the insn
2019 that loads it into a register.
2020 If this insn was cse'd, we get incorrect code.
2022 So emit a new move insn that copies the
2023 function address into the register that the
2024 call insn will use. flow.c will delete any
2025 redundant stores that we have created. */
2030 NULL_RTX)))
2031 {
2037 }
2038 /* We have the call insn.
2039 If it uses the register we suspect it might,
2040 load it with the correct address directly. */
2045 gen_move_insn
2049 {
2051 /* Because the USAGE information potentially
2052 contains objects other than hard registers
2053 we need to copy it. */
2057 }
2058 else
2067 }
2070 }
2072 {
2073 /* P sets REG to zero; but we should clear only
2074 the bits that are not covered by the mode
2075 m->savemode. */
2077 rtx sequence;
2078 rtx tem;
2081 tem = expand_simple_binop
2094 }
2096 {
2098 /* Because the USAGE information potentially
2099 contains objects other than hard registers
2100 we need to copy it. */
2104 }
2106 {
2107 rtx seq;
2108 /* The SET_SRC might not be invariant, so we must
2109 use the REG_EQUAL note. */
2122 }
2123 else
2127 {
2131 /* If there is a REG_EQUAL note present whose value
2132 is not loop invariant, then delete it, since it
2133 may cause problems with later optimization passes.
2134 It is possible for cse to create such notes
2135 like this as a result of record_jump_cond. */
2140 }
2149 /* If library call, now fix the REG_NOTES that contain
2150 insn pointers, namely REG_LIBCALL on FIRST
2151 and REG_RETVAL on I1. */
2153 {
2157 }
2163 /* simplify_giv_expr expects that it can walk the insns
2164 at m->insn forwards and see this old sequence we are
2165 tossing here. delete_insn does preserve the next
2166 pointers, but when we skip over a NOTE we must fix
2167 it up. Otherwise that code walks into the non-deleted
2168 insn stream. */
2171 }
2173 /* The more regs we move, the less we like moving them. */
2175 }
2177 /* Any other movable that loads the same register
2178 MUST be moved. */
2181 /* This reg has been moved out of one loop. */
2184 /* The reg set here is now invariant. */
2186 {
2190 }
2194 /* Change the length-of-life info for the register
2195 to say it lives at least the full length of this loop.
2196 This will help guide optimizations in outer loops. */
2199 /* This is the old insn before all the moved insns.
2200 We can't use the moved insn because it is out of range
2201 in uid_luid. Only the old insns have luids. */
2206 /* Combine with this moved insn any other matching movables. */
2211 {
2212 rtx temp;
2214 /* Schedule the reg loaded by M1
2215 for replacement so that shares the reg of M.
2216 If the modes differ (only possible in restricted
2217 circumstances, make a SUBREG.
2219 Note this assumes that the target dependent files
2220 treat REG and SUBREG equally, including within
2221 GO_IF_LEGITIMATE_ADDRESS and in all the
2222 predicates since we never verify that replacing the
2223 original register with a SUBREG results in a
2224 recognizable insn. */
2227 else
2232 /* Get rid of the matching insn
2233 and prevent further processing of it. */
2236 /* if library call, delete all insns. */
2238 NULL_RTX)))
2240 else
2243 /* Any other movable that loads the same register
2244 MUST be moved. */
2247 /* The reg merged here is now invariant,
2248 if the reg it matches is invariant. */
2250 {
2254 i++)
2256 }
2257 }
2258 }
2261 }
2267 }
2272 /* Go through all the instructions in the loop, making
2273 all the register substitutions scheduled in REG_MAP. */
2277 {
2281 }
2283 /* Clean up. */
2286 }
2289 static void
2293 {
2296 else
2299 }
2302 static void
2305 {
2310 {
2313 }
2314 }
2315 \f
2316 #if 0
2317 /* Scan X and replace the address of any MEM in it with ADDR.
2318 REG is the address that MEM should have before the replacement. */
2320 static void
2323 {
2332 {
2344 /* Short cut for very common case. */
2349 /* Short cut for very common case. */
2354 /* If this MEM uses a reg other than the one we expected,
2355 something is wrong. */
2363 }
2367 {
2371 {
2375 }
2376 }
2377 }
2378 #endif
2379 \f
2380 /* Return the number of memory refs to addresses that vary
2381 in the rtx X. */
2383 static int
2386 rtx x;
2387 {
2398 {
2415 }
2420 {
2424 {
2428 }
2429 }
2431 }
2432 \f
2433 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2434 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2435 `unknown_address_altered', `unknown_constant_address_altered', and
2436 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2437 list `store_mems' in LOOP. */
2439 static void
2442 {
2444 rtx insn;
2448 /* The label after END. Jumping here is just like falling off the
2449 end of the loop. We use next_nonnote_insn instead of next_label
2450 as a hedge against the (pathological) case where some actual insn
2451 might end up between the two. */
2474 {
2476 {
2479 }
2480 }
2484 {
2486 {
2489 {
2491 /* Count number of loops contained in this one. */
2493 }
2500 {
2503 }
2513 {
2517 {
2522 {
2525 }
2526 else
2527 {
2530 }
2532 do
2533 {
2535 {
2537 {
2538 /* Something tricky. */
2541 }
2544 {
2545 /* A jump outside the current loop. */
2548 }
2549 }
2553 }
2555 }
2556 else
2557 {
2558 /* A return, or something tricky. */
2560 }
2561 }
2562 /* FALLTHRU */
2583 }
2584 }
2586 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2588 anywhere. */
2590 /* We don't want loads for MEMs moved to a location before the
2591 one at which their stack memory becomes allocated. (Note
2592 that this is not a problem for malloc, etc., since those
2593 require actual function calls. */
2594 && ! current_function_calls_alloca
2595 /* There are ways to leave the loop other than falling off the
2596 end. */
2602 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2603 that loop_invariant_p and load_mems can use true_dependence
2604 to determine what is really clobbered. */
2606 {
2609 loop_info->store_mems
2611 }
2613 {
2617 loop_info->store_mems
2619 }
2620 }
2621 \f
2622 /* Invalidate all loops containing LABEL. */
2624 static void
2626 rtx label;
2627 {
2631 }
2633 /* Scan the function looking for loops. Record the start and end of each loop.
2634 Also mark as invalid loops any loops that contain a setjmp or are branched
2635 to from outside the loop. */
2637 static void
2639 rtx f;
2641 {
2642 rtx insn;
2643 rtx label;
2653 /* If there are jumps to undefined labels,
2654 treat them as jumps out of any/all loops.
2655 This also avoids writing past end of tables when there are no loops. */
2658 /* Find boundaries of loops, mark which loops are contained within
2659 loops, and invalidate loops that have setjmp. */
2664 {
2667 {
2671 num_loops++;
2695 }
2699 {
2700 /* In this case, we must invalidate our current loop and any
2701 enclosing loop. */
2703 {
2709 }
2710 }
2712 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2713 enclosing loop, but this doesn't matter. */
2715 }
2717 /* Any loop containing a label used in an initializer must be invalidated,
2718 because it can be jumped into from anywhere. */
2722 /* Any loop containing a label used for an exception handler must be
2723 invalidated, because it can be jumped into from anywhere. */
2726 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2727 loop that it is not contained within, that loop is marked invalid.
2728 If any INSN or CALL_INSN uses a label's address, then the loop containing
2729 that label is marked invalid, because it could be jumped into from
2730 anywhere.
2732 Also look for blocks of code ending in an unconditional branch that
2733 exits the loop. If such a block is surrounded by a conditional
2734 branch around the block, move the block elsewhere (see below) and
2735 invert the jump to point to the code block. This may eliminate a
2736 label in our loop and will simplify processing by both us and a
2737 possible second cse pass. */
2741 {
2745 {
2749 }
2756 /* See if this is an unconditional branch outside the loop. */
2764 {
2765 rtx p;
2771 /* Go backwards until we reach the start of the loop, a label,
2772 or a JUMP_INSN. */
2779 ;
2781 /* Check for the case where we have a jump to an inner nested
2782 loop, and do not perform the optimization in that case. */
2785 {
2788 {
2793 }
2794 }
2796 /* Make sure that the target of P is within the current loop. */
2802 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2803 we have a block of code to try to move.
2805 We look backward and then forward from the target of INSN
2806 to find a BARRIER at the same loop depth as the target.
2807 If we find such a BARRIER, we make a new label for the start
2808 of the block, invert the jump in P and point it to that label,
2809 and move the block of code to the spot we found. */
2814 /* Just ignore jumps to labels that were never emitted.
2815 These always indicate compilation errors. */
2819 /* If it's not safe to move the sequence, then we
2820 mustn't try. */
2823 {
2824 rtx target
2828 rtx tmp;
2830 /* Search for possible garbage past the conditional jumps
2831 and look for the last barrier. */
2839 /* Don't move things inside a tablejump. */
2852 /* Don't move things inside a tablejump. */
2863 {
2867 /* Ensure our label doesn't go away. */
2870 /* Verify that uid_loop is large enough and that
2871 we can invert P. */
2873 {
2876 /* If no suitable BARRIER was found, create a suitable
2877 one before TARGET. Since TARGET is a fall through
2878 path, we'll need to insert an jump around our block
2879 and add a BARRIER before TARGET.
2881 This creates an extra unconditional jump outside
2882 the loop. However, the benefits of removing rarely
2883 executed instructions from inside the loop usually
2884 outweighs the cost of the extra unconditional jump
2885 outside the loop. */
2887 {
2888 rtx temp;
2895 }
2897 /* Include the BARRIER after INSN and copy the
2898 block after LOC. */
2903 /* All those insns are now in TARGET_LOOP. */
2909 /* The label jumped to by INSN is no longer a loop
2910 exit. Unless INSN does not have a label (e.g.,
2911 it is a RETURN insn), search loop->exit_labels
2912 to find its label_ref, and remove it. Also turn
2913 off LABEL_OUTSIDE_LOOP_P bit. */
2915 {
2917 r;
2920 {
2924 else
2927 }
2933 /* If we didn't find it, then something is
2934 wrong. */
2937 }
2939 /* P is now a jump outside the loop, so it must be put
2940 in loop->exit_labels, and marked as such.
2941 The easiest way to do this is to just call
2942 mark_loop_jump again for P. */
2945 /* If INSN now jumps to the insn after it,
2946 delete INSN. */
2951 }
2953 /* Continue the loop after where the conditional
2954 branch used to jump, since the only branch insn
2955 in the block (if it still remains) is an inter-loop
2956 branch and hence needs no processing. */
2962 /* This loop will be continued with NEXT_INSN (insn). */
2964 }
2965 }
2966 }
2967 }
2968 }
2970 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2971 loops it is contained in, mark the target loop invalid.
2973 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2975 static void
2977 rtx x;
2979 {
2985 {
2997 /* There could be a label reference in here. */
3009 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3021 /* Link together all labels that branch outside the loop. This
3022 is used by final_[bg]iv_value and the loop unrolling code. Also
3023 mark this LABEL_REF so we know that this branch should predict
3024 false. */
3026 /* A check to make sure the label is not in an inner nested loop,
3027 since this does not count as a loop exit. */
3029 {
3034 }
3035 else
3039 {
3048 }
3050 /* If this is inside a loop, but not in the current loop or one enclosed
3051 by it, it invalidates at least one loop. */
3056 /* We must invalidate every nested loop containing the target of this
3057 label, except those that also contain the jump insn. */
3060 {
3061 /* Stop when we reach a loop that also contains the jump insn. */
3066 /* If we get here, we know we need to invalidate a loop. */
3073 }
3077 /* If this is not setting pc, ignore. */
3099 /* Strictly speaking this is not a jump into the loop, only a possible
3100 jump out of the loop. However, we have no way to link the destination
3101 of this jump onto the list of exit labels. To be safe we mark this
3102 loop and any containing loops as invalid. */
3104 {
3106 {
3112 }
3113 }
3115 }
3116 }
3117 \f
3118 /* Return nonzero if there is a label in the range from
3119 insn INSN to and including the insn whose luid is END
3120 INSN must have an assigned luid (i.e., it must not have
3121 been previously created by loop.c). */
3123 static int
3125 rtx insn;
3127 {
3129 {
3133 }
3136 }
3138 /* Record that a memory reference X is being set. */
3140 static void
3142 rtx x;
3143 rtx y ATTRIBUTE_UNUSED;
3145 {
3151 /* Count number of memory writes.
3152 This affects heuristics in strength_reduce. */
3155 /* BLKmode MEM means all memory is clobbered. */
3157 {
3160 else
3164 }
3168 }
3170 /* X is a value modified by an INSN that references a biv inside a loop
3171 exit test (ie, X is somehow related to the value of the biv). If X
3172 is a pseudo that is used more than once, then the biv is (effectively)
3173 used more than once. DATA is a pointer to a loop_regs structure. */
3175 static void
3177 rtx x;
3178 rtx y ATTRIBUTE_UNUSED;
3180 {
3195 /* If we do not have usage information, or if we know the register
3196 is used more than once, note that fact for check_dbra_loop. */
3201 }
3202 \f
3203 /* Return nonzero if the rtx X is invariant over the current loop.
3205 The value is 2 if we refer to something only conditionally invariant.
3207 A memory ref is invariant if it is not volatile and does not conflict
3208 with anything stored in `loop_info->store_mems'. */
3210 int
3213 rtx x;
3214 {
3221 rtx mem_list_entry;
3227 {
3235 /* A LABEL_REF is normally invariant, however, if we are unrolling
3236 loops, and this label is inside the loop, then it isn't invariant.
3237 This is because each unrolled copy of the loop body will have
3238 a copy of this label. If this was invariant, then an insn loading
3239 the address of this label into a register might get moved outside
3240 the loop, and then each loop body would end up using the same label.
3242 We don't know the loop bounds here though, so just fail for all
3243 labels. */
3246 else
3255 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3256 since the reg might be set by initialization within the loop. */
3273 /* Volatile memory references must be rejected. Do this before
3274 checking for read-only items, so that volatile read-only items
3275 will be rejected also. */
3279 /* See if there is any dependence between a store and this load. */
3282 {
3288 }
3290 /* It's not invalidated by a store in memory
3291 but we must still verify the address is invariant. */
3295 /* Don't mess with insns declared volatile. */
3302 }
3306 {
3308 {
3314 }
3316 {
3319 {
3325 }
3327 }
3328 }
3331 }
3332 \f
3333 /* Return nonzero if all the insns in the loop that set REG
3334 are INSN and the immediately following insns,
3335 and if each of those insns sets REG in an invariant way
3336 (not counting uses of REG in them).
3338 The value is 2 if some of these insns are only conditionally invariant.
3340 We assume that INSN itself is the first set of REG
3341 and that its source is invariant. */
3343 static int
3348 {
3352 rtx temp;
3353 /* Number of sets we have to insist on finding after INSN. */
3359 /* If N_SETS hit the limit, we can't rely on its value. */
3366 {
3368 rtx set;
3373 /* If library call, skip to end of it. */
3382 {
3387 {
3388 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3389 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3390 notes are OK. */
3396 }
3397 }
3399 count--;
3401 {
3404 }
3405 }
3408 /* If loop_invariant_p ever returned 2, we return 2. */
3410 }
3412 #if 0
3413 /* I don't think this condition is sufficient to allow INSN
3414 to be moved, so we no longer test it. */
3416 /* Return 1 if all insns in the basic block of INSN and following INSN
3417 that set REG are invariant according to TABLE. */
3419 static int
3423 {
3428 {
3437 {
3440 }
3441 }
3442 }
3444 \f
3445 /* Look at all uses (not sets) of registers in X. For each, if it is
3446 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3447 a different insn, set USAGE[REGNO] to const0_rtx. */
3449 static void
3452 rtx insn;
3453 rtx x;
3454 {
3466 {
3467 /* Don't count SET_DEST if it is a REG; otherwise count things
3468 in SET_DEST because if a register is partially modified, it won't
3469 show up as a potential movable so we don't care how USAGE is set
3470 for it. */
3474 }
3475 else
3477 {
3483 }
3484 }
3485 \f
3486 /* Count and record any set in X which is contained in INSN. Update
3487 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3488 in X. */
3490 static void
3495 {
3497 /* Don't move a reg that has an explicit clobber.
3498 It's not worth the pain to try to do it correctly. */
3502 {
3510 {
3514 {
3515 /* If this is the first setting of this reg
3516 in current basic block, and it was set before,
3517 it must be set in two basic blocks, so it cannot
3518 be moved out of the loop. */
3522 /* If this is not first setting in current basic block,
3523 see if reg was used in between previous one and this.
3524 If so, neither one can be moved. */
3531 }
3532 }
3533 }
3534 }
3535 \f
3536 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3537 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3538 contained in insn INSN is used by any insn that precedes INSN in
3539 cyclic order starting from the loop entry point.
3541 We don't want to use INSN_LUID here because if we restrict INSN to those
3542 that have a valid INSN_LUID, it means we cannot move an invariant out
3543 from an inner loop past two loops. */
3545 static int
3549 {
3551 rtx p;
3553 /* Scan forward checking for register usage. If we hit INSN, we
3554 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3556 {
3562 }
3565 }
3566 \f
3568 /* Information we collect about arrays that we might want to prefetch. */
3569 struct prefetch_info
3570 {
3574 index. */
3575 HOST_WIDE_INT index;
3577 iteration. */
3579 prefetch area in one iteration. */
3581 This is set only for loops with known
3582 iteration counts and is 0xffffffff
3583 otherwise. */
3587 };
3589 /* Data used by check_store function. */
3590 struct check_store_data
3591 {
3592 rtx mem_address;
3594 };
3600 /* Set mem_write when mem_address is found. Used as callback to
3601 note_stores. */
3602 static void
3606 {
3611 }
3612 \f
3613 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3614 important to get some addresses combined. Later more sophisticated
3615 transformations can be added when necesary.
3617 ??? Same trick with swapping operand is done at several other places.
3618 It can be nice to develop some common way to handle this. */
3620 static int
3623 {
3637 {
3642 }
3643 /* Compare the elements. If any pair of corresponding elements fails to
3644 match, return 0 for the whole thing. */
3648 {
3650 {
3662 /* Two vectors must have the same length. */
3666 /* And the corresponding elements must match. */
3684 /* These are just backpointers, so they don't matter. */
3690 /* It is believed that rtx's at this level will never
3691 contain anything but integers and other rtx's,
3692 except for within LABEL_REFs and SYMBOL_REFs. */
3695 }
3696 }
3698 }
3699 \f
3700 /* Remove constant addition value from the expression X (when present)
3701 and return it. */
3703 static HOST_WIDE_INT
3706 {
3710 /* Avoid clobbering a shared CONST expression. */
3712 {
3716 {
3719 }
3721 }
3724 {
3727 }
3729 /* For plus expression recurse on ourself. */
3731 {
3735 /* In case our parameter was constant, remove extra zero from the
3736 expression. */
3741 }
3744 }
3746 /* Attempt to identify accesses to arrays that are most likely to cause cache
3747 misses, and emit prefetch instructions a few prefetch blocks forward.
3749 To detect the arrays we use the GIV information that was collected by the
3750 strength reduction pass.
3752 The prefetch instructions are generated after the GIV information is done
3753 and before the strength reduction process. The new GIVs are injected into
3754 the strength reduction tables, so the prefetch addresses are optimized as
3755 well.
3757 GIVs are split into base address, stride, and constant addition values.
3758 GIVs with the same address, stride and close addition values are combined
3759 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3760 for write instructions can be used for the block we write to, on machines
3761 that support write prefetches.
3763 Several heuristics are used to determine when to prefetch. They are
3764 controlled by defined symbols that can be overridden for each target. */
3766 static void
3769 {
3785 /* Consider only loops w/o calls. When a call is done, the loop is probably
3786 slow enough to read the memory. */
3788 {
3793 }
3795 /* Don't prefetch in loops known to have few iterations. */
3799 {
3804 }
3806 /* Search all induction variables and pick those interesting for the prefetch
3807 machinery. */
3809 {
3815 /* Expect all BIVs to be executed in each iteration. This makes our
3816 analysis more conservative. */
3818 {
3819 /* Discard non-constant additions that we can't handle well yet, and
3820 BIVs that are executed multiple times; such BIVs ought to be
3821 handled in the nested loop. We accept not_every_iteration BIVs,
3822 since these only result in larger strides and make our
3823 heuristics more conservative. */
3825 {
3827 {
3833 }
3835 }
3838 {
3840 {
3846 }
3848 }
3852 }
3858 {
3859 rtx address;
3860 rtx temp;
3869 /* See whether an induction variable is interesting to us and if
3870 not, report the reason. */
3874 /* We are interested only in constant stride memory references
3875 in order to be able to compute density easily. */
3879 else
3880 {
3883 {
3886 }
3888 /* On some targets, reversed order prefetches are not
3889 worthwhile. */
3893 /* Prefetch of accesses with an extreme stride might not be
3894 worthwhile, either. */
3899 /* Ignore GIVs with varying add values; we can't predict the
3900 value for the next iteration. */
3904 /* Ignore GIVs in the nested loops; they ought to have been
3905 handled already. */
3908 }
3911 {
3917 }
3919 /* Determine the pointer to the basic array we are examining. It is
3920 the sum of the BIV's initial value and the GIV's add_val. */
3930 /* When the GIV is not always executed, we might be better off by
3931 not dirtying the cache pages. */
3934 else
3935 {
3940 }
3942 /* Attempt to find another prefetch to the same array and see if we
3943 can merge this one. */
3947 {
3948 /* In case both access same array (same location
3949 just with small difference in constant indexes), merge
3950 the prefetches. Just do the later and the earlier will
3951 get prefetched from previous iteration.
3952 The artificial threshold should not be too small,
3953 but also not bigger than small portion of memory usually
3954 traversed by single loop. */
3957 {
3966 }
3970 {
3975 }
3976 }
3978 /* Merging failed. */
3980 {
3988 num_prefetches++;
3990 {
3995 }
3996 }
3997 }
3998 }
4001 {
4004 /* Attempt to calculate the total number of bytes fetched by all
4005 iterations of the loop. Avoid overflow. */
4010 else
4015 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4020 {
4025 }
4026 else
4027 {
4033 }
4034 else
4037 /* Find how many prefetch instructions we'll use within the loop. */
4039 {
4045 }
4046 }
4048 /* Determine how many iterations ahead to prefetch within the loop, based
4049 on how many prefetches we currently expect to do within the loop. */
4051 {
4053 {
4059 }
4060 }
4061 /* We'll also use AHEAD to determine how many prefetch instructions to
4062 emit before a loop, so don't leave it zero. */
4067 {
4068 /* Update if we've decided not to prefetch anything within the loop. */
4072 /* Find how many prefetch instructions we'll use before the loop. */
4074 {
4082 }
4085 {
4107 }
4108 }
4111 {
4112 /* Record that this loop uses prefetch instructions. */
4116 {
4121 }
4122 }
4125 {
4129 {
4131 rtx insn;
4135 rtx seq;
4137 /* We can save some effort by offsetting the address on
4138 architectures with offsettable memory references. */
4141 else
4142 {
4148 }
4151 /* Make sure the address operand is valid for prefetch. */
4161 /* Check all insns emitted and record the new GIV
4162 information. */
4165 {
4170 }
4171 }
4174 {
4175 /* Emit insns before the loop to fetch the first cache lines or,
4176 if we're not prefetching within the loop, everything we expect
4177 to need. */
4179 {
4187 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4188 non-constant INIT_VAL to have the same mode as REG, which
4189 in this case we know to be Pmode. */
4197 loop_start);
4198 }
4199 }
4200 }
4203 }
4204 \f
4205 /* A "basic induction variable" or biv is a pseudo reg that is set
4206 (within this loop) only by incrementing or decrementing it. */
4207 /* A "general induction variable" or giv is a pseudo reg whose
4208 value is a linear function of a biv. */
4210 /* Bivs are recognized by `basic_induction_var';
4211 Givs by `general_induction_var'. */
4213 /* Communication with routines called via `note_stores'. */
4217 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4221 /* ??? Unfinished optimizations, and possible future optimizations,
4222 for the strength reduction code. */
4224 /* ??? The interaction of biv elimination, and recognition of 'constant'
4225 bivs, may cause problems. */
4227 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4228 performance problems.
4230 Perhaps don't eliminate things that can be combined with an addressing
4231 mode. Find all givs that have the same biv, mult_val, and add_val;
4232 then for each giv, check to see if its only use dies in a following
4233 memory address. If so, generate a new memory address and check to see
4234 if it is valid. If it is valid, then store the modified memory address,
4235 otherwise, mark the giv as not done so that it will get its own iv. */
4237 /* ??? Could try to optimize branches when it is known that a biv is always
4238 positive. */
4240 /* ??? When replace a biv in a compare insn, we should replace with closest
4241 giv so that an optimized branch can still be recognized by the combiner,
4242 e.g. the VAX acb insn. */
4244 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4245 was rerun in loop_optimize whenever a register was added or moved.
4246 Also, some of the optimizations could be a little less conservative. */
4247 \f
4248 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4249 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4250 callback.
4252 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4253 loop iteration except for the last one.
4255 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4256 loop iteration.
4257 */
4258 void
4261 loop_insn_callback fncall;
4262 {
4263 /* This is 1 if current insn is not executed at least once for every loop
4264 iteration. */
4269 rtx p;
4271 /* If loop_scan_start points to the loop exit test, we have to be wary of
4272 subversive use of gotos inside expression statements. */
4276 /* Scan through loop to find all possible bivs. */
4281 {
4284 /* Past CODE_LABEL, we get to insns that may be executed multiple
4285 times. The only way we can be sure that they can't is if every
4286 jump insn between here and the end of the loop either
4287 returns, exits the loop, is a jump to a location that is still
4288 behind the label, or is a jump to the loop start. */
4291 {
4297 {
4302 {
4305 else
4309 }
4317 {
4320 }
4321 }
4322 }
4324 /* Past a jump, we get to insns for which we can't count
4325 on whether they will be executed during each iteration. */
4326 /* This code appears twice in strength_reduce. There is also similar
4327 code in scan_loop. */
4329 /* If we enter the loop in the middle, and scan around to the
4330 beginning, don't set not_every_iteration for that.
4331 This can be any kind of jump, since we want to know if insns
4332 will be executed if the loop is executed. */
4337 {
4340 /* If this is a jump outside the loop, then it also doesn't
4341 matter. Check to see if the target of this branch is on the
4342 loop->exits_labels list. */
4350 }
4353 {
4354 /* At the virtual top of a converted loop, insns are again known to
4355 be executed each iteration: logically, the loop begins here
4356 even though the exit code has been duplicated.
4358 Insns are also again known to be executed each iteration at
4359 the LOOP_CONT note. */
4365 loop_depth++;
4367 loop_depth--;
4368 }
4370 /* Note if we pass a loop latch. If we do, then we can not clear
4371 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4372 a loop since a jump before the last CODE_LABEL may have started
4373 a new loop iteration.
4375 Note that LOOP_TOP is only set for rotated loops and we need
4376 this check for all loops, so compare against the CODE_LABEL
4377 which immediately follows LOOP_START. */
4382 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4383 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4384 or not an insn is known to be executed each iteration of the
4385 loop, whether or not any iterations are known to occur.
4387 Therefore, if we have just passed a label and have no more labels
4388 between here and the test insn of the loop, and we have not passed
4389 a jump to the top of the loop, then we know these insns will be
4390 executed each iteration. */
4393 && !past_loop_latch
4398 }
4399 }
4400 \f
4401 static void
4404 {
4407 /* Temporary list pointers for traversing ivs->list. */
4414 /* Scan ivs->list to remove all regs that proved not to be bivs.
4415 Make a sanity check against regs->n_times_set. */
4417 {
4419 /* Above happens if register modified by subreg, etc. */
4420 /* Make sure it is not recognized as a basic induction var: */
4422 /* If never incremented, it is invariant that we decided not to
4423 move. So leave it alone. */
4425 {
4436 }
4437 else
4438 {
4443 }
4444 }
4445 }
4448 /* Determine how BIVS are initialised by looking through pre-header
4449 extended basic block. */
4450 static void
4453 {
4455 /* Temporary list pointers for traversing ivs->list. */
4458 rtx p;
4460 /* Find initial value for each biv by searching backwards from loop_start,
4461 halting at first label. Also record any test condition. */
4465 {
4466 rtx test;
4476 /* Record any test of a biv that branches around the loop if no store
4477 between it and the start of loop. We only care about tests with
4478 constants and registers and only certain of those. */
4488 {
4489 /* If an NE test, we have an initial value! */
4491 {
4495 }
4496 else
4498 }
4499 }
4500 }
4503 /* Look at the each biv and see if we can say anything better about its
4504 initial value from any initializing insns set up above. (This is done
4505 in two passes to avoid missing SETs in a PARALLEL.) */
4506 static void
4509 {
4511 /* Temporary list pointers for traversing ivs->list. */
4516 {
4517 rtx src;
4518 rtx note;
4523 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4524 is a constant, use the value of that. */
4530 else
4543 {
4547 {
4550 }
4551 }
4552 /* If we can't make it a giv,
4553 let biv keep initial value of "itself". */
4556 }
4557 }
4560 /* Search the loop for general induction variables. */
4562 static void
4565 {
4567 }
4570 /* For each giv for which we still don't know whether or not it is
4571 replaceable, check to see if it is replaceable because its final value
4572 can be calculated. */
4574 static void
4577 {
4582 {
4588 }
4589 }
4592 /* Return non-zero if it is possible to eliminate the biv BL provided
4593 all givs are reduced. This is possible if either the reg is not
4594 used outside the loop, or we can compute what its final value will
4595 be. */
4597 static int
4603 {
4604 /* For architectures with a decrement_and_branch_until_zero insn,
4605 don't do this if we put a REG_NONNEG note on the endtest for this
4606 biv. */
4608 #ifdef HAVE_decrement_and_branch_until_zero
4610 {
4615 }
4616 #endif
4618 /* Check that biv is used outside loop or if it has a final value.
4619 Compare against bl->init_insn rather than loop->start. We aren't
4620 concerned with any uses of the biv between init_insn and
4621 loop->start since these won't be affected by the value of the biv
4622 elsewhere in the function, so long as init_insn doesn't use the
4623 biv itself. */
4634 {
4642 }
4644 }
4647 /* Reduce each giv of BL that we have decided to reduce. */
4649 static void
4653 {
4657 {
4660 {
4663 /* If the code for derived givs immediately below has already
4664 allocated a new_reg, we must keep it. */
4668 #ifdef AUTO_INC_DEC
4669 /* If the target has auto-increment addressing modes, and
4670 this is an address giv, then try to put the increment
4671 immediately after its use, so that flow can create an
4672 auto-increment addressing mode. */
4675 /* We don't handle reversed biv's because bl->biv->insn
4676 does not have a valid INSN_LUID. */
4680 {
4681 /* If other giv's have been combined with this one, then
4682 this will work only if all uses of the other giv's occur
4683 before this giv's insn. This is difficult to check.
4685 We simplify this by looking for the common case where
4686 there is one DEST_REG giv, and this giv's insn is the
4687 last use of the dest_reg of that DEST_REG giv. If the
4688 increment occurs after the address giv, then we can
4689 perform the optimization. (Otherwise, the increment
4690 would have to go before other_giv, and we would not be
4691 able to combine it with the address giv to get an
4692 auto-inc address.) */
4694 {
4699 {
4702 else
4704 }
4711 }
4712 /* Check for case where increment is before the address
4713 giv. Do this test in "loop order". */
4722 else
4725 #ifdef HAVE_cc0
4726 {
4727 rtx prev;
4729 /* We can't put an insn immediately after one setting
4730 cc0, or immediately before one using cc0. */
4737 }
4738 #endif
4742 }
4743 #endif
4745 /* For each place where the biv is incremented, add an insn
4746 to increment the new, reduced reg for the giv. */
4748 {
4749 rtx insert_before;
4755 else
4763 /* A multiply is acceptable here
4764 since this is presumed to be seldom executed. */
4768 }
4770 /* Add code at loop start to initialize giv's reduced reg. */
4775 }
4776 }
4777 }
4780 /* Check for givs whose first use is their definition and whose
4781 last use is the definition of another giv. If so, it is likely
4782 dead and should not be used to derive another giv nor to
4783 eliminate a biv. */
4785 static void
4789 {
4793 {
4800 {
4806 }
4807 }
4808 }
4811 static void
4816 {
4820 {
4827 /* Update expression if this was combined, in case other giv was
4828 replaced. */
4833 /* See if this register is known to be a pointer to something. If
4834 so, see if we can find the alignment. First see if there is a
4835 destination register that is a pointer. If so, this shares the
4836 alignment too. Next see if we can deduce anything from the
4837 computational information. If not, and this is a DEST_ADDR
4838 giv, at least we know that it's a pointer, though we don't know
4839 the alignment. */
4847 {
4856 }
4860 {
4868 }
4873 /* Store reduced reg as the address in the memref where we found
4874 this giv. */
4877 {
4879 }
4880 else
4881 {
4882 /* Not replaceable; emit an insn to set the original giv reg from
4883 the reduced giv, same as above. */
4886 }
4888 /* When a loop is reversed, givs which depend on the reversed
4889 biv, and which are live outside the loop, must be set to their
4890 correct final value. This insn is only needed if the giv is
4891 not replaceable. The correct final value is the same as the
4892 value that the giv starts the reversed loop with. */
4903 {
4908 }
4909 }
4910 }
4913 static int
4918 rtx test_reg;
4919 {
4928 /* Reduce benefit if not replaceable, since we will insert a
4929 move-insn to replace the insn that calculates this giv. Don't do
4930 this unless the giv is a user variable, since it will often be
4931 marked non-replaceable because of the duplication of the exit
4932 code outside the loop. In such a case, the copies we insert are
4933 dead and will be deleted. So they don't have a cost. Similar
4934 situations exist. */
4935 /* ??? The new final_[bg]iv_value code does a much better job of
4936 finding replaceable giv's, and hence this code may no longer be
4937 necessary. */
4942 /* Decrease the benefit to count the add-insns that we will insert
4943 to increment the reduced reg for the giv. ??? This can
4944 overestimate the run-time cost of the additional insns, e.g. if
4945 there are multiple basic blocks that increment the biv, but only
4946 one of these blocks is executed during each iteration. There is
4947 no good way to detect cases like this with the current structure
4948 of the loop optimizer. This code is more accurate for
4949 determining code size than run-time benefits. */
4952 /* Decide whether to strength-reduce this giv or to leave the code
4953 unchanged (recompute it from the biv each time it is used). This
4954 decision can be made independently for each giv. */
4956 #ifdef AUTO_INC_DEC
4957 /* Attempt to guess whether autoincrement will handle some of the
4958 new add insns; if so, increase BENEFIT (undo the subtraction of
4959 add_cost that was done above). */
4961 /* Increasing the benefit is risky, since this is only a guess.
4962 Avoid increasing register pressure in cases where there would
4963 be no other benefit from reducing this giv. */
4966 {
4981 }
4982 #endif
4985 }
4988 /* Free IV structures for LOOP. */
4990 static void
4993 {
5000 {
5006 {
5009 }
5011 {
5014 }
5018 }
5019 }
5022 /* Perform strength reduction and induction variable elimination.
5024 Pseudo registers created during this function will be beyond the
5025 last valid index in several tables including
5026 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5027 problem here, because the added registers cannot be givs outside of
5028 their loop, and hence will never be reconsidered. But scan_loop
5029 must check regnos to make sure they are in bounds. */
5031 static void
5035 {
5039 rtx p;
5040 /* Temporary list pointer for traversing ivs->list. */
5042 /* Ratio of extra register life span we can justify
5043 for saving an instruction. More if loop doesn't call subroutines
5044 since in that case saving an insn makes more difference
5045 and more registers are available. */
5046 /* ??? could set this to last value of threshold in move_movables */
5048 /* Map of pseudo-register replacements. */
5060 /* Find all BIVs in loop. */
5063 /* Exit if there are no bivs. */
5065 {
5066 /* Can still unroll the loop anyways, but indicate that there is no
5067 strength reduction info available. */
5073 }
5075 /* Determine how BIVS are initialised by looking through pre-header
5076 extended basic block. */
5079 /* Look at the each biv and see if we can say anything better about its
5080 initial value from any initializing insns set up above. */
5083 /* Search the loop for general induction variables. */
5086 /* Try to calculate and save the number of loop iterations. This is
5087 set to zero if the actual number can not be calculated. This must
5088 be called after all giv's have been identified, since otherwise it may
5089 fail if the iteration variable is a giv. */
5092 #ifdef HAVE_prefetch
5095 #endif
5097 /* Now for each giv for which we still don't know whether or not it is
5098 replaceable, check to see if it is replaceable because its final value
5099 can be calculated. This must be done after loop_iterations is called,
5100 so that final_giv_value will work correctly. */
5103 /* Try to prove that the loop counter variable (if any) is always
5104 nonnegative; if so, record that fact with a REG_NONNEG note
5105 so that "decrement and branch until zero" insn can be used. */
5108 /* Create reg_map to hold substitutions for replaceable giv regs.
5109 Some givs might have been made from biv increments, so look at
5110 ivs->reg_iv_type for a suitable size. */
5114 /* Examine each iv class for feasibility of strength reduction/induction
5115 variable elimination. */
5118 {
5122 /* Test whether it will be possible to eliminate this biv
5123 provided all givs are reduced. */
5126 /* This will be true at the end, if all givs which depend on this
5127 biv have been strength reduced.
5128 We can't (currently) eliminate the biv unless this is so. */
5131 /* Check each extension dependent giv in this class to see if its
5132 root biv is safe from wrapping in the interior mode. */
5135 /* Combine all giv's for this iv_class. */
5139 {
5147 /* If an insn is not to be strength reduced, then set its ignore
5148 flag, and clear bl->all_reduced. */
5150 /* A giv that depends on a reversed biv must be reduced if it is
5151 used after the loop exit, otherwise, it would have the wrong
5152 value after the loop exit. To make it simple, just reduce all
5153 of such giv's whether or not we know they are used after the loop
5154 exit. */
5159 {
5167 }
5168 else
5169 {
5170 /* Check that we can increment the reduced giv without a
5171 multiply insn. If not, reject it. */
5176 {
5184 }
5185 }
5186 }
5188 /* Check for givs whose first use is their definition and whose
5189 last use is the definition of another giv. If so, it is likely
5190 dead and should not be used to derive another giv nor to
5191 eliminate a biv. */
5194 /* Reduce each giv that we decided to reduce. */
5197 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5198 as not reduced.
5200 For each giv register that can be reduced now: if replaceable,
5201 substitute reduced reg wherever the old giv occurs;
5202 else add new move insn "giv_reg = reduced_reg". */
5205 /* All the givs based on the biv bl have been reduced if they
5206 merit it. */
5208 /* For each giv not marked as maybe dead that has been combined with a
5209 second giv, clear any "maybe dead" mark on that second giv.
5210 v->new_reg will either be or refer to the register of the giv it
5211 combined with.
5213 Doing this clearing avoids problems in biv elimination where
5214 a giv's new_reg is a complex value that can't be put in the
5215 insn but the giv combined with (with a reg as new_reg) is
5216 marked maybe_dead. Since the register will be used in either
5217 case, we'd prefer it be used from the simpler giv. */
5223 /* Try to eliminate the biv, if it is a candidate.
5224 This won't work if ! bl->all_reduced,
5225 since the givs we planned to use might not have been reduced.
5227 We have to be careful that we didn't initially think we could
5228 eliminate this biv because of a giv that we now think may be
5229 dead and shouldn't be used as a biv replacement.
5231 Also, there is the possibility that we may have a giv that looks
5232 like it can be used to eliminate a biv, but the resulting insn
5233 isn't valid. This can happen, for example, on the 88k, where a
5234 JUMP_INSN can compare a register only with zero. Attempts to
5235 replace it with a compare with a constant will fail.
5237 Note that in cases where this call fails, we may have replaced some
5238 of the occurrences of the biv with a giv, but no harm was done in
5239 doing so in the rare cases where it can occur. */
5243 {
5244 /* ?? If we created a new test to bypass the loop entirely,
5245 or otherwise drop straight in, based on this test, then
5246 we might want to rewrite it also. This way some later
5247 pass has more hope of removing the initialization of this
5248 biv entirely. */
5250 /* If final_value != 0, then the biv may be used after loop end
5251 and we must emit an insn to set it just in case.
5253 Reversed bivs already have an insn after the loop setting their
5254 value, so we don't need another one. We can't calculate the
5255 proper final value for such a biv here anyways. */
5264 }
5265 /* See above note wrt final_value. But since we couldn't eliminate
5266 the biv, we must set the value after the loop instead of before. */
5270 }
5272 /* Go through all the instructions in the loop, making all the
5273 register substitutions scheduled in REG_MAP. */
5278 {
5282 }
5285 {
5286 /* When we completely unroll a loop we will likely not need the increment
5287 of the loop BIV and we will not need the conditional branch at the
5288 end of the loop. */
5291 #ifdef HAVE_cc0
5292 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5293 need the comparison before the conditional branch at the end of the
5294 loop. */
5296 #endif
5298 /* We'll need one copy for each loop iteration. */
5301 /* A little slop to account for the ability to remove initialization
5302 code, better CSE, and other secondary benefits of completely
5303 unrolling some loops. */
5306 /* Clamp the value. */
5309 }
5311 /* Unroll loops from within strength reduction so that we can use the
5312 induction variable information that strength_reduce has already
5313 collected. Always unroll loops that would be as small or smaller
5314 unrolled than when rolled. */
5321 #ifdef HAVE_doloop_end
5326 /* In case number of iterations is known, drop branch prediction note
5327 in the branch. Do that only in second loop pass, as loop unrolling
5328 may change the number of iterations performed. */
5330 {
5331 unsigned HOST_WIDE_INT n
5336 }
5344 }
5345 \f
5346 /*Record all basic induction variables calculated in the insn. */
5347 static rtx
5350 rtx p;
5353 {
5355 rtx set;
5356 rtx dest_reg;
5357 rtx inc_val;
5358 rtx mult_val;
5364 {
5369 {
5374 {
5375 /* It is a possible basic induction variable.
5376 Create and initialize an induction structure for it. */
5384 }
5387 }
5388 }
5390 }
5391 \f
5392 /* Record all givs calculated in the insn.
5393 A register is a giv if: it is only set once, it is a function of a
5394 biv and a constant (or invariant), and it is not a biv. */
5395 static rtx
5398 rtx p;
5401 {
5404 rtx set;
5405 /* Look for a general induction variable in a register. */
5410 {
5411 rtx src_reg;
5412 rtx dest_reg;
5413 rtx add_val;
5414 rtx mult_val;
5415 rtx ext_val;
5418 rtx last_consec_insn;
5427 /* Equivalent expression is a giv. */
5432 /* Don't try to handle any regs made by loop optimization.
5433 We have nothing on them in regno_first_uid, etc. */
5435 /* Don't recognize a BASIC_INDUCT_VAR here. */
5437 /* This must be the only place where the register is set. */
5439 /* or all sets must be consecutive and make a giv. */
5444 {
5448 /* If this is a library call, increase benefit. */
5452 /* Skip the consecutive insns, if there are any. */
5460 }
5461 }
5463 #ifndef DONT_REDUCE_ADDR
5464 /* Look for givs which are memory addresses. */
5465 /* This resulted in worse code on a VAX 8600. I wonder if it
5466 still does. */
5469 maybe_multiple);
5470 #endif
5472 /* Update the status of whether giv can derive other givs. This can
5473 change when we pass a label or an insn that updates a biv. */
5478 }
5479 \f
5480 /* Return 1 if X is a valid source for an initial value (or as value being
5481 compared against in an initial test).
5483 X must be either a register or constant and must not be clobbered between
5484 the current insn and the start of the loop.
5486 INSN is the insn containing X. */
5488 static int
5490 rtx x;
5491 rtx insn;
5493 rtx loop_start;
5494 {
5498 /* Only consider pseudos we know about initialized in insns whose luids
5499 we know. */
5504 /* Don't use call-clobbered registers across a call which clobbers it. On
5505 some machines, don't use any hard registers at all. */
5507 && (SMALL_REGISTER_CLASSES
5511 /* Don't use registers that have been clobbered before the start of the
5512 loop. */
5517 }
5518 \f
5519 /* Scan X for memory refs and check each memory address
5520 as a possible giv. INSN is the insn whose pattern X comes from.
5521 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5522 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5523 more thanonce in each loop iteration. */
5525 static void
5528 rtx x;
5529 rtx insn;
5531 {
5541 {
5557 {
5558 rtx src_reg;
5559 rtx add_val;
5560 rtx mult_val;
5561 rtx ext_val;
5564 /* This code used to disable creating GIVs with mult_val == 1 and
5565 add_val == 0. However, this leads to lost optimizations when
5566 it comes time to combine a set of related DEST_ADDR GIVs, since
5567 this one would not be seen. */
5572 {
5573 /* Found one; record it. */
5582 }
5583 }
5588 }
5590 /* Recursively scan the subexpressions for other mem refs. */
5596 maybe_multiple);
5600 maybe_multiple);
5601 }
5602 \f
5603 /* Fill in the data about one biv update.
5604 V is the `struct induction' in which we record the biv. (It is
5605 allocated by the caller, with alloca.)
5606 INSN is the insn that sets it.
5607 DEST_REG is the biv's reg.
5609 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5610 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5611 being set to INC_VAL.
5613 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5614 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5615 can be executed more than once per iteration. If MAYBE_MULTIPLE
5616 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5617 executed exactly once per iteration. */
5619 static void
5624 rtx insn;
5625 rtx dest_reg;
5626 rtx inc_val;
5627 rtx mult_val;
5631 {
5647 /* Add this to the reg's iv_class, creating a class
5648 if this is the first incrementation of the reg. */
5652 {
5653 /* Create and initialize new iv_class. */
5663 /* Set initial value to the reg itself. */
5666 /* We haven't seen the initializing insn yet */
5676 /* Add this class to ivs->list. */
5680 /* Put it in the array of biv register classes. */
5682 }
5684 /* Update IV_CLASS entry for this biv. */
5693 }
5694 \f
5695 /* Fill in the data about one giv.
5696 V is the `struct induction' in which we record the giv. (It is
5697 allocated by the caller, with alloca.)
5698 INSN is the insn that sets it.
5699 BENEFIT estimates the savings from deleting this insn.
5700 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5701 into a register or is used as a memory address.
5703 SRC_REG is the biv reg which the giv is computed from.
5704 DEST_REG is the giv's reg (if the giv is stored in a reg).
5705 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5706 LOCATION points to the place where this giv's value appears in INSN. */
5708 static void
5713 rtx insn;
5714 rtx src_reg;
5715 rtx dest_reg;
5721 {
5726 rtx temp;
5728 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5729 undo the MULT canonicalization that we performed earlier. */
5759 /* The v->always_computable field is used in update_giv_derive, to
5760 determine whether a giv can be used to derive another giv. For a
5761 DEST_REG giv, INSN computes a new value for the giv, so its value
5762 isn't computable if INSN insn't executed every iteration.
5763 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5764 it does not compute a new value. Hence the value is always computable
5765 regardless of whether INSN is executed each iteration. */
5769 else
5775 {
5778 }
5780 {
5785 /* If the lifetime is zero, it means that this register is
5786 really a dead store. So mark this as a giv that can be
5787 ignored. This will not prevent the biv from being eliminated. */
5793 }
5795 /* Add the giv to the class of givs computed from one biv. */
5799 {
5802 /* Don't count DEST_ADDR. This is supposed to count the number of
5803 insns that calculate givs. */
5807 }
5808 else
5809 /* Fatal error, biv missing for this giv? */
5814 else
5815 {
5816 /* The giv can be replaced outright by the reduced register only if all
5817 of the following conditions are true:
5818 - the insn that sets the giv is always executed on any iteration
5819 on which the giv is used at all
5820 (there are two ways to deduce this:
5821 either the insn is executed on every iteration,
5822 or all uses follow that insn in the same basic block),
5823 - the giv is not used outside the loop
5824 - no assignments to the biv occur during the giv's lifetime. */
5827 /* Previous line always fails if INSN was moved by loop opt. */
5830 && (! not_every_iteration
5832 {
5833 /* Now check that there are no assignments to the biv within the
5834 giv's lifetime. This requires two separate checks. */
5836 /* Check each biv update, and fail if any are between the first
5837 and last use of the giv.
5839 If this loop contains an inner loop that was unrolled, then
5840 the insn modifying the biv may have been emitted by the loop
5841 unrolling code, and hence does not have a valid luid. Just
5842 mark the biv as not replaceable in this case. It is not very
5843 useful as a biv, because it is used in two different loops.
5844 It is very unlikely that we would be able to optimize the giv
5845 using this biv anyways. */
5849 {
5855 {
5859 }
5860 }
5862 /* If there are any backwards branches that go from after the
5863 biv update to before it, then this giv is not replaceable. */
5867 {
5871 }
5872 }
5873 else
5874 {
5875 /* May still be replaceable, we don't have enough info here to
5876 decide. */
5879 }
5880 }
5882 /* Record whether the add_val contains a const_int, for later use by
5883 combine_givs. */
5884 {
5889 ;
5893 {
5895 {
5900 else
5902 }
5905 }
5906 }
5910 }
5912 /* All this does is determine whether a giv can be made replaceable because
5913 its final value can be calculated. This code can not be part of record_giv
5914 above, because final_giv_value requires that the number of loop iterations
5915 be known, and that can not be accurately calculated until after all givs
5916 have been identified. */
5918 static void
5922 {
5929 /* DEST_ADDR givs will never reach here, because they are always marked
5930 replaceable above in record_giv. */
5932 /* The giv can be replaced outright by the reduced register only if all
5933 of the following conditions are true:
5934 - the insn that sets the giv is always executed on any iteration
5935 on which the giv is used at all
5936 (there are two ways to deduce this:
5937 either the insn is executed on every iteration,
5938 or all uses follow that insn in the same basic block),
5939 - its final value can be calculated (this condition is different
5940 than the one above in record_giv)
5941 - it's not used before the it's set
5942 - no assignments to the biv occur during the giv's lifetime. */
5944 #if 0
5945 /* This is only called now when replaceable is known to be false. */
5946 /* Clear replaceable, so that it won't confuse final_giv_value. */
5948 #endif
5952 {
5955 rtx last_giv_use;
5959 /* When trying to determine whether or not a biv increment occurs
5960 during the lifetime of the giv, we can ignore uses of the variable
5961 outside the loop because final_value is true. Hence we can not
5962 use regno_last_uid and regno_first_uid as above in record_giv. */
5964 /* Search the loop to determine whether any assignments to the
5965 biv occur during the giv's lifetime. Start with the insn
5966 that sets the giv, and search around the loop until we come
5967 back to that insn again.
5969 Also fail if there is a jump within the giv's lifetime that jumps
5970 to somewhere outside the lifetime but still within the loop. This
5971 catches spaghetti code where the execution order is not linear, and
5972 hence the above test fails. Here we assume that the giv lifetime
5973 does not extend from one iteration of the loop to the next, so as
5974 to make the test easier. Since the lifetime isn't known yet,
5975 this requires two loops. See also record_giv above. */
5980 {
5983 {
5986 }
5992 {
5993 /* It is possible for the BIV increment to use the GIV if we
5994 have a cycle. Thus we must be sure to check each insn for
5995 both BIV and GIV uses, and we must check for BIV uses
5996 first. */
6003 {
6005 {
6009 }
6011 }
6012 }
6013 }
6015 /* Now that the lifetime of the giv is known, check for branches
6016 from within the lifetime to outside the lifetime if it is still
6017 replaceable. */
6020 {
6023 {
6036 {
6045 }
6046 }
6047 }
6049 /* If it is replaceable, then save the final value. */
6052 }
6057 }
6058 \f
6059 /* Update the status of whether a giv can derive other givs.
6061 We need to do something special if there is or may be an update to the biv
6062 between the time the giv is defined and the time it is used to derive
6063 another giv.
6065 In addition, a giv that is only conditionally set is not allowed to
6066 derive another giv once a label has been passed.
6068 The cases we look at are when a label or an update to a biv is passed. */
6070 static void
6073 rtx p;
6074 {
6078 rtx tem;
6081 /* Search all IV classes, then all bivs, and finally all givs.
6083 There are three cases we are concerned with. First we have the situation
6084 of a giv that is only updated conditionally. In that case, it may not
6085 derive any givs after a label is passed.
6087 The second case is when a biv update occurs, or may occur, after the
6088 definition of a giv. For certain biv updates (see below) that are
6089 known to occur between the giv definition and use, we can adjust the
6090 giv definition. For others, or when the biv update is conditional,
6091 we must prevent the giv from deriving any other givs. There are two
6092 sub-cases within this case.
6094 If this is a label, we are concerned with any biv update that is done
6095 conditionally, since it may be done after the giv is defined followed by
6096 a branch here (actually, we need to pass both a jump and a label, but
6097 this extra tracking doesn't seem worth it).
6099 If this is a jump, we are concerned about any biv update that may be
6100 executed multiple times. We are actually only concerned about
6101 backward jumps, but it is probably not worth performing the test
6102 on the jump again here.
6104 If this is a biv update, we must adjust the giv status to show that a
6105 subsequent biv update was performed. If this adjustment cannot be done,
6106 the giv cannot derive further givs. */
6112 {
6114 {
6115 /* If cant_derive is already true, there is no point in
6116 checking all of these conditions again. */
6120 /* If this giv is conditionally set and we have passed a label,
6121 it cannot derive anything. */
6125 /* Skip givs that have mult_val == 0, since
6126 they are really invariants. Also skip those that are
6127 replaceable, since we know their lifetime doesn't contain
6128 any biv update. */
6132 /* The only way we can allow this giv to derive another
6133 is if this is a biv increment and we can form the product
6134 of biv->add_val and giv->mult_val. In this case, we will
6135 be able to compute a compensation. */
6137 {
6138 rtx ext_val_dummy;
6149 tem = simplify_giv_expr
6156 else
6158 }
6162 }
6163 }
6164 }
6165 \f
6166 /* Check whether an insn is an increment legitimate for a basic induction var.
6167 X is the source of insn P, or a part of it.
6168 MODE is the mode in which X should be interpreted.
6170 DEST_REG is the putative biv, also the destination of the insn.
6171 We accept patterns of these forms:
6172 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6173 REG = INVARIANT + REG
6175 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6176 store the additive term into *INC_VAL, and store the place where
6177 we found the additive term into *LOCATION.
6179 If X is an assignment of an invariant into DEST_REG, we set
6180 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6182 We also want to detect a BIV when it corresponds to a variable
6183 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6184 of the variable may be a PLUS that adds a SUBREG of that variable to
6185 an invariant and then sign- or zero-extends the result of the PLUS
6186 into the variable.
6188 Most GIVs in such cases will be in the promoted mode, since that is the
6189 probably the natural computation mode (and almost certainly the mode
6190 used for addresses) on the machine. So we view the pseudo-reg containing
6191 the variable as the BIV, as if it were simply incremented.
6193 Note that treating the entire pseudo as a BIV will result in making
6194 simple increments to any GIVs based on it. However, if the variable
6195 overflows in its declared mode but not its promoted mode, the result will
6196 be incorrect. This is acceptable if the variable is signed, since
6197 overflows in such cases are undefined, but not if it is unsigned, since
6198 those overflows are defined. So we only check for SIGN_EXTEND and
6199 not ZERO_EXTEND.
6201 If we cannot find a biv, we return 0. */
6203 static int
6206 rtx x;
6208 rtx dest_reg;
6209 rtx p;
6213 {
6221 {
6227 {
6229 }
6234 {
6236 }
6237 else
6250 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6251 handle addition of promoted variables.
6252 ??? The comment at the start of this function is wrong: promoted
6253 variable increments don't look like it says they do. */
6259 /* If this register is assigned in a previous insn, look at its
6260 source, but don't go outside the loop or past a label. */
6262 /* If this sets a register to itself, we would repeat any previous
6263 biv increment if we applied this strategy blindly. */
6269 {
6270 rtx dest;
6271 do
6272 {
6274 }
6303 }
6304 /* Fall through. */
6306 /* Can accept constant setting of biv only when inside inner most loop.
6307 Otherwise, a biv of an inner loop may be incorrectly recognized
6308 as a biv of the outer loop,
6309 causing code to be moved INTO the inner loop. */
6316 /* convert_modes aborts if we try to convert to or from CCmode, so just
6317 exclude that case. It is very unlikely that a condition code value
6318 would be a useful iterator anyways. convert_modes aborts if we try to
6319 convert a float mode to non-float or vice versa too. */
6323 {
6324 /* Possible bug here? Perhaps we don't know the mode of X. */
6328 }
6329 else
6337 /* Similar, since this can be a sign extension. */
6342 ;
6356 location);
6361 }
6362 }
6363 \f
6364 /* A general induction variable (giv) is any quantity that is a linear
6365 function of a basic induction variable,
6366 i.e. giv = biv * mult_val + add_val.
6367 The coefficients can be any loop invariant quantity.
6368 A giv need not be computed directly from the biv;
6369 it can be computed by way of other givs. */
6371 /* Determine whether X computes a giv.
6372 If it does, return a nonzero value
6373 which is the benefit from eliminating the computation of X;
6374 set *SRC_REG to the register of the biv that it is computed from;
6375 set *ADD_VAL and *MULT_VAL to the coefficients,
6376 such that the value of X is biv * mult + add; */
6378 static int
6382 rtx x;
6390 {
6394 /* If this is an invariant, forget it, it isn't a giv. */
6405 {
6408 /* Since this is now an invariant and wasn't before, it must be a giv
6409 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6410 with. */
6417 /* This is equivalent to a BIV. */
6424 /* Either (plus (biv) (invar)) or
6425 (plus (mult (biv) (invar_1)) (invar_2)). */
6427 {
6430 }
6431 else
6432 {
6435 }
6440 /* ADD_VAL is zero. */
6448 }
6450 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6451 unless they are CONST_INT). */
6459 else
6462 /* Always return true if this is a giv so it will be detected as such,
6463 even if the benefit is zero or negative. This allows elimination
6464 of bivs that might otherwise not be eliminated. */
6466 }
6467 \f
6468 /* Given an expression, X, try to form it as a linear function of a biv.
6469 We will canonicalize it to be of the form
6470 (plus (mult (BIV) (invar_1))
6471 (invar_2))
6472 with possible degeneracies.
6474 The invariant expressions must each be of a form that can be used as a
6475 machine operand. We surround then with a USE rtx (a hack, but localized
6476 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6477 routine; it is the caller's responsibility to strip them.
6479 If no such canonicalization is possible (i.e., two biv's are used or an
6480 expression that is neither invariant nor a biv or giv), this routine
6481 returns 0.
6483 For a non-zero return, the result will have a code of CONST_INT, USE,
6484 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6486 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6491 static rtx
6494 rtx x;
6497 {
6502 rtx tem;
6504 /* If this is not an integer mode, or if we cannot do arithmetic in this
6505 mode, this can't be a giv. */
6512 {
6519 /* Put constant last, CONST_INT last if both constant. */
6527 /* Handle addition of zero, then addition of an invariant. */
6532 {
6535 /* Adding two invariants must result in an invariant, so enclose
6536 addition operation inside a USE and return it. */
6546 else
6555 /* biv + invar or mult + invar. Return sum. */
6559 /* (a + invar_1) + invar_2. Associate. */
6560 return
6566 arg1)),
6571 }
6573 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6574 MULT to reduce cases. */
6580 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6581 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6582 Recurse to associate the second PLUS. */
6587 return
6595 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6611 /* Handle "a - b" as "a + b * (-1)". */
6617 constm1_rtx)),
6626 /* Put constant last, CONST_INT last if both constant. */
6631 /* If second argument is not now constant, not giv. */
6635 /* Handle multiply by 0 or 1. */
6643 {
6645 /* biv * invar. Done. */
6649 /* Product of two constants. */
6653 /* invar * invar is a giv, but attempt to simplify it somehow. */
6659 {
6660 /* (invar_0 * invar_1) * invar_2. Associate. */
6667 arg1)),
6669 }
6670 /* Porpagate the MULT expressions to the intermost nodes. */
6672 {
6673 /* (invar_0 + invar_1) * invar_2. Distribute. */
6679 arg1),
6683 arg1)),
6685 }
6689 /* (a * invar_1) * invar_2. Associate. */
6695 arg1)),
6699 /* (a + invar_1) * invar_2. Distribute. */
6704 arg1),
6707 arg1)),
6712 }
6715 /* Shift by constant is multiply by power of two. */
6719 return
6728 /* "-a" is "a * (-1)" */
6734 /* "~a" is "-a - 1". Silly, but easy. */
6738 const1_rtx),
6742 /* Already in proper form for invariant. */
6748 /* Conditionally recognize extensions of simple IVs. After we've
6749 computed loop traversal counts and verified the range of the
6750 source IV, we'll reevaluate this as a GIV. */
6752 {
6755 {
6758 }
6759 }
6763 /* If this is a new register, we can't deal with it. */
6767 /* Check for biv or giv. */
6769 {
6773 {
6776 /* Form expression from giv and add benefit. Ensure this giv
6777 can derive another and subtract any needed adjustment if so. */
6779 /* Increasing the benefit here is risky. The only case in which it
6780 is arguably correct is if this is the only use of V. In other
6781 cases, this will artificially inflate the benefit of the current
6782 giv, and lead to suboptimal code. Thus, it is disabled, since
6783 potentially not reducing an only marginally beneficial giv is
6784 less harmful than reducing many givs that are not really
6785 beneficial. */
6786 {
6790 }
6803 {
6806 }
6807 else
6808 {
6811 }
6813 }
6816 do_default:
6817 /* If it isn't an induction variable, and it is invariant, we
6818 may be able to simplify things further by looking through
6819 the bits we just moved outside the loop. */
6821 {
6827 {
6828 /* Ok, we found a match. Substitute and simplify. */
6830 /* If we match another movable, we must use that, as
6831 this one is going away. */
6836 /* If consec is non-zero, this is a member of a group of
6837 instructions that were moved together. We handle this
6838 case only to the point of seeking to the last insn and
6839 looking for a REG_EQUAL. Fail if we don't find one. */
6841 {
6844 do
6845 {
6847 }
6853 }
6854 else
6855 {
6859 }
6862 {
6863 /* What we are most interested in is pointer
6864 arithmetic on invariants -- only take
6865 patterns we may be able to do something with. */
6871 {
6873 benefit);
6876 }
6881 {
6886 }
6887 }
6889 }
6890 }
6892 }
6894 /* Fall through to general case. */
6896 /* If invariant, return as USE (unless CONST_INT).
6897 Otherwise, not giv. */
6902 {
6911 }
6912 else
6914 }
6915 }
6917 /* This routine folds invariants such that there is only ever one
6918 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6920 static rtx
6923 {
6929 {
6932 }
6935 {
6938 }
6939 else
6940 {
6943 }
6944 }
6946 static rtx
6950 {
6952 {
6956 else
6959 }
6962 else
6965 }
6966 \f
6967 /* Help detect a giv that is calculated by several consecutive insns;
6968 for example,
6969 giv = biv * M
6970 giv = giv + A
6971 The caller has already identified the first insn P as having a giv as dest;
6972 we check that all other insns that set the same register follow
6973 immediately after P, that they alter nothing else,
6974 and that the result of the last is still a giv.
6976 The value is 0 if the reg set in P is not really a giv.
6977 Otherwise, the value is the amount gained by eliminating
6978 all the consecutive insns that compute the value.
6980 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6981 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6983 The coefficients of the ultimate giv value are stored in
6984 *MULT_VAL and *ADD_VAL. */
6986 static int
6991 rtx p;
6992 rtx src_reg;
6993 rtx dest_reg;
6998 {
7004 rtx temp;
7005 rtx set;
7007 /* Indicate that this is a giv so that we can update the value produced in
7008 each insn of the multi-insn sequence.
7010 This induction structure will be used only by the call to
7011 general_induction_var below, so we can allocate it on our stack.
7012 If this is a giv, our caller will replace the induct var entry with
7013 a new induction structure. */
7034 {
7038 /* If libcall, skip to end of call sequence. */
7049 /* Giv created by equivalent expression. */
7055 {
7059 count--;
7063 }
7065 {
7066 /* Allow insns that set something other than this giv to a
7067 constant. Such insns are needed on machines which cannot
7068 include long constants and should not disqualify a giv. */
7077 }
7078 }
7083 }
7084 \f
7085 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7086 represented by G1. If no such expression can be found, or it is clear that
7087 it cannot possibly be a valid address, 0 is returned.
7089 To perform the computation, we note that
7090 G1 = x * v + a and
7091 G2 = y * v + b
7092 where `v' is the biv.
7094 So G2 = (y/b) * G1 + (b - a*y/x).
7096 Note that MULT = y/x.
7098 Update: A and B are now allowed to be additive expressions such that
7099 B contains all variables in A. That is, computing B-A will not require
7100 subtracting variables. */
7102 static rtx
7105 {
7106 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7111 /* If MULT is not 1, we cannot handle A with non-constants, since we
7112 would then be required to subtract multiples of the registers in A.
7113 This is theoretically possible, and may even apply to some Fortran
7114 constructs, but it is a lot of work and we do not attempt it here. */
7119 /* In general these structures are sorted top to bottom (down the PLUS
7120 chain), but not left to right across the PLUS. If B is a higher
7121 order giv than A, we can strip one level and recurse. If A is higher
7122 order, we'll eventually bail out, but won't know that until the end.
7123 If they are the same, we'll strip one level around this loop. */
7126 {
7138 /* We matched: remove one reg completely. */
7141 /* An alternate match. */
7144 /* An alternate match. */
7146 else
7147 {
7148 /* Indicates an extra register in B. Strip one level from B and
7149 recurse, hoping B was the higher order expression. */
7154 }
7155 }
7157 /* Here we are at the last level of A, go through the cases hoping to
7158 get rid of everything but a constant. */
7161 {
7174 }
7176 {
7178 }
7180 {
7185 }
7187 {
7192 else
7194 }
7199 }
7201 rtx
7204 {
7207 /* The value that G1 will be multiplied by must be a constant integer. Also,
7208 the only chance we have of getting a valid address is if b*c/a (see above
7209 for notation) is also an integer. */
7212 {
7217 }
7220 else
7221 {
7222 /* ??? Find out if the one is a multiple of the other? */
7224 }
7228 {
7229 /* Failed. If we've got a multiplication factor between G1 and G2,
7230 scale G1's addend and try again. */
7232 {
7236 {
7237 HOST_WIDE_INT m;
7241 }
7242 else
7243 {
7245 mult);
7246 }
7249 }
7250 }
7254 /* Form simplified final result. */
7259 else
7264 else
7265 {
7268 {
7272 }
7275 }
7276 }
7277 \f
7278 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7279 represented by G1. This indicates that G2 should be combined with G1 and
7280 that G2 can use (either directly or via an address expression) a register
7281 used to represent G1. */
7283 static rtx
7286 {
7289 /* With the introduction of ext dependent givs, we must care for modes.
7290 G2 must not use a wider mode than G1. */
7300 /* If these givs are identical, they can be combined. We use the results
7301 of express_from because the addends are not in a canonical form, so
7302 rtx_equal_p is a weaker test. */
7303 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7304 combination to be the other way round. */
7307 {
7309 }
7311 /* If G2 can be expressed as a function of G1 and that function is valid
7312 as an address and no more expensive than using a register for G2,
7313 the expression of G2 in terms of G1 can be used. */
7317 /* ??? Looses, especially with -fforce-addr, where *g2->location
7318 will always be a register, and so anything more complicated
7319 gets discarded. */
7320 #if 0
7321 #ifdef ADDRESS_COST
7323 #else
7325 #endif
7326 #endif
7327 )
7328 {
7330 }
7333 }
7334 \f
7335 /* Check each extension dependent giv in this class to see if its
7336 root biv is safe from wrapping in the interior mode, which would
7337 make the giv illegal. */
7339 static void
7343 {
7346 HOST_WIDE_INT start_val;
7352 /* Make sure the iteration data is available. We must have
7353 constants in order to be certain of no overflow. */
7354 /* ??? An unknown iteration count with an increment of +-1
7355 combined with friendly exit tests of against an invariant
7356 value is also ameanable to optimization. Not implemented. */
7362 /* Make sure the host can represent the arithmetic. */
7364 {
7366 HOST_WIDE_INT s_end_val;
7378 /* Check for host arithmatic overflow. */
7380 {
7382 HOST_WIDE_INT s_max;
7389 /* Check zero extension of biv ok. */
7391 /* Check for host arithmatic overflow. */
7392 && (neg_incr
7395 /* Check for target arithmetic overflow. */
7396 && (neg_incr
7399 {
7401 }
7403 /* Check sign extension of biv ok. */
7404 /* ??? While it is true that overflow with signed and pointer
7405 arithmetic is undefined, I fear too many programmers don't
7406 keep this fact in mind -- myself included on occasion.
7407 So leave alone with the signed overflow optimizations. */
7409 /* Check for host arithmatic overflow. */
7410 && (neg_incr
7413 /* Check for target arithmetic overflow. */
7414 && (neg_incr
7417 {
7419 }
7420 }
7421 }
7423 /* Invalidate givs that fail the tests. */
7426 {
7431 {
7440 /* We don't know whether this value is being used as either
7441 signed or unsigned, so to safely truncate we must satisfy
7442 both. The initial check here verifies the BIV itself;
7443 once that is successful we may check its range wrt the
7444 derived GIV. */
7446 {
7450 /* We know from the above that both endpoints are nonnegative,
7451 and that there is no wrapping. Verify that both endpoints
7452 are within the (signed) range of the outer mode. */
7455 }
7460 }
7463 {
7465 {
7469 }
7470 }
7471 else
7472 {
7474 {
7479 else
7480 {
7485 else
7487 }
7492 }
7495 }
7496 }
7497 }
7499 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7501 rtx
7504 rtx value;
7505 {
7511 /* Recall that check_ext_dependent_givs verified that the known bounds
7512 of a biv did not overflow or wrap with respect to the extension for
7513 the giv. Therefore, constants need no additional adjustment. */
7517 /* Otherwise, we must adjust the value to compensate for the
7518 differing modes of the biv and the giv. */
7520 }
7521 \f
7522 struct combine_givs_stats
7523 {
7526 };
7528 static int
7532 {
7539 /* Stabilize the sort. */
7543 }
7545 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7546 any other. If so, point SAME to the giv combined with and set NEW_REG to
7547 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7548 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7550 static void
7554 {
7555 /* Additional benefit to add for being combined multiple times. */
7563 /* Count givs, because bl->giv_count is incorrect here. */
7567 giv_count++;
7569 giv_array
7580 {
7582 rtx single_use;
7587 /* If a DEST_REG GIV is used only once, do not allow it to combine
7588 with anything, for in doing so we will gain nothing that cannot
7589 be had by simply letting the GIV with which we would have combined
7590 to be reduced on its own. The losage shows up in particular with
7591 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7592 be seen elsewhere as well. */
7599 /* Add an additional weight for zero addends. */
7604 {
7605 rtx this_combine;
7610 {
7613 }
7614 }
7616 }
7618 /* Iterate, combining until we can't. */
7619 restart:
7623 {
7626 {
7632 }
7634 }
7637 {
7643 /* If it has already been combined, skip. */
7648 {
7651 /* If it has already been combined, skip. */
7653 {
7658 /* For destination, we now may replace by mem expression instead
7659 of register. This changes the costs considerably, so add the
7660 compensation. */
7670 /* ??? The new final_[bg]iv_value code does a much better job
7671 of finding replaceable giv's, and hence this code may no
7672 longer be necessary. */
7676 /* To help optimize the next set of combinations, remove
7677 this giv from the benefits of other potential mates. */
7679 {
7683 }
7690 }
7691 }
7693 /* To help optimize the next set of combinations, remove
7694 this giv from the benefits of other potential mates. */
7696 {
7698 {
7702 }
7706 /* We've finished with this giv, and everything it touched.
7707 Restart the combination so that proper weights for the
7708 rest of the givs are properly taken into account. */
7709 /* ??? Ideally we would compact the arrays at this point, so
7710 as to not cover old ground. But sanely compacting
7711 can_combine is tricky. */
7713 }
7714 }
7716 /* Clean up. */
7719 }
7720 \f
7721 /* Generate sequence for REG = B * M + A. */
7723 static rtx
7729 {
7730 rtx seq;
7731 rtx result;
7734 /* Use unsigned arithmetic. */
7742 }
7745 /* Update registers created in insn sequence SEQ. */
7747 static void
7750 rtx seq;
7751 {
7752 /* Update register info for alias analysis. */
7755 {
7758 {
7762 }
7763 }
7764 else
7765 {
7769 }
7770 }
7773 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7775 void
7782 basic_block before_bb;
7783 rtx before_insn;
7784 {
7785 rtx seq;
7788 {
7791 }
7793 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7796 /* Increase the lifetime of any invariants moved further in code. */
7803 /* It is possible that the expansion created lots of new registers.
7804 Iterate over the sequence we just created and record them all. */
7806 }
7809 /* Emit insns in loop pre-header to set REG = B * M + A. */
7811 void
7818 {
7819 rtx seq;
7821 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7824 /* Increase the lifetime of any invariants moved further in code.
7825 ???? Is this really necessary? */
7832 /* It is possible that the expansion created lots of new registers.
7833 Iterate over the sequence we just created and record them all. */
7835 }
7838 /* Emit insns after loop to set REG = B * M + A. */
7840 void
7847 {
7848 rtx seq;
7850 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7855 /* It is possible that the expansion created lots of new registers.
7856 Iterate over the sequence we just created and record them all. */
7858 }
7862 /* Similar to gen_add_mult, but compute cost rather than generating
7863 sequence. */
7865 static int
7871 {
7881 {
7886 }
7889 }
7890 \f
7891 /* Test whether A * B can be computed without
7892 an actual multiply insn. Value is 1 if so. */
7894 static int
7896 rtx a;
7897 rtx b;
7898 {
7900 rtx tmp;
7903 /* If only one is constant, make it B. */
7907 /* If first constant, both constant, so don't need multiply. */
7911 /* If second not constant, neither is constant, so would need multiply. */
7915 /* One operand is constant, so might not need multiply insn. Generate the
7916 code for the multiply and see if a call or multiply, or long sequence
7917 of insns is generated. */
7925 {
7930 else
7932 {
7941 {
7944 }
7945 }
7946 }
7956 }
7957 \f
7958 /* Check to see if loop can be terminated by a "decrement and branch until
7959 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7960 Also try reversing an increment loop to a decrement loop
7961 to see if the optimization can be performed.
7962 Value is nonzero if optimization was performed. */
7964 /* This is useful even if the architecture doesn't have such an insn,
7965 because it might change a loops which increments from 0 to n to a loop
7966 which decrements from n to 0. A loop that decrements to zero is usually
7967 faster than one that increments from zero. */
7969 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7970 such as approx_final_value, biv_total_increment, loop_iterations, and
7971 final_[bg]iv_value. */
7973 static int
7977 {
7982 rtx reg;
7983 rtx jump_label;
7984 rtx final_value;
7985 rtx start_value;
7986 rtx new_add_val;
7987 rtx comparison;
7988 rtx before_comparison;
7989 rtx p;
7990 rtx jump;
7991 rtx first_compare;
7996 /* If last insn is a conditional branch, and the insn before tests a
7997 register value, try to optimize it. Otherwise, we can't do anything. */
8006 /* Try to compute whether the compare/branch at the loop end is one or
8007 two instructions. */
8013 else
8016 {
8017 /* If more than one condition is present to control the loop, then
8018 do not proceed, as this function does not know how to rewrite
8019 loop tests with more than one condition.
8021 Look backwards from the first insn in the last comparison
8022 sequence and see if we've got another comparison sequence. */
8024 rtx jump1;
8028 }
8030 /* Check all of the bivs to see if the compare uses one of them.
8031 Skip biv's set more than once because we can't guarantee that
8032 it will be zero on the last iteration. Also skip if the biv is
8033 used between its update and the test insn. */
8036 {
8041 first_compare))
8043 }
8048 /* Look for the case where the basic induction variable is always
8049 nonnegative, and equals zero on the last iteration.
8050 In this case, add a reg_note REG_NONNEG, which allows the
8051 m68k DBRA instruction to be used. */
8059 {
8060 /* Initial value must be greater than 0,
8061 init_val % -dec_value == 0 to ensure that it equals zero on
8062 the last iteration */
8068 {
8069 /* register always nonnegative, add REG_NOTE to branch */
8077 }
8079 /* If the decrement is 1 and the value was tested as >= 0 before
8080 the loop, then we can safely optimize. */
8082 {
8095 {
8103 }
8104 }
8105 }
8108 {
8109 /* Try to change inc to dec, so can apply above optimization. */
8110 /* Can do this if:
8111 all registers modified are induction variables or invariant,
8112 all memory references have non-overlapping addresses
8113 (obviously true if only one write)
8114 allow 2 insns for the compare/jump at the end of the loop. */
8115 /* Also, we must avoid any instructions which use both the reversed
8116 biv and another biv. Such instructions will fail if the loop is
8117 reversed. We meet this condition by requiring that either
8118 no_use_except_counting is true, or else that there is only
8119 one biv. */
8121 /* 1 if the iteration var is used only to count iterations. */
8123 /* 1 if the loop has no memory store, or it has a single memory store
8124 which is reversible. */
8130 {
8134 /* If there are no givs for this biv, and the only exit is the
8135 fall through at the end of the loop, then
8136 see if perhaps there are no uses except to count. */
8140 {
8145 /* An insn that sets the biv is okay. */
8146 ;
8150 {
8151 /* If either of these insns uses the biv and sets a pseudo
8152 that has more than one usage, then the biv has uses
8153 other than counting since it's used to derive a value
8154 that is used more than one time. */
8156 regs);
8158 {
8161 }
8162 }
8164 {
8167 }
8168 }
8170 /* A biv has uses besides counting if it is used to set
8171 another biv. */
8175 {
8178 }
8179 }
8182 /* No need to worry about MEMs. */
8183 ;
8185 {
8190 /* If the loop has a single store, and the destination address is
8191 invariant, then we can't reverse the loop, because this address
8192 might then have the wrong value at loop exit.
8193 This would work if the source was invariant also, however, in that
8194 case, the insn should have been moved out of the loop. */
8197 {
8200 /* If we could prove that each of the memory locations
8201 written to was different, then we could reverse the
8202 store -- but we don't presently have any way of
8203 knowing that. */
8206 /* If the store depends on a register that is set after the
8207 store, it depends on the initial value, and is thus not
8208 reversible. */
8210 {
8217 }
8218 }
8219 }
8220 else
8223 /* This code only acts for innermost loops. Also it simplifies
8224 the memory address check by only reversing loops with
8225 zero or one memory access.
8226 Two memory accesses could involve parts of the same array,
8227 and that can't be reversed.
8228 If the biv is used only for counting, than we don't need to worry
8229 about all these things. */
8235 && reversible_mem_store
8240 {
8241 rtx tem;
8243 /* Loop can be reversed. */
8247 /* Now check other conditions:
8249 The increment must be a constant, as must the initial value,
8250 and the comparison code must be LT.
8252 This test can probably be improved since +/- 1 in the constant
8253 can be obtained by changing LT to LE and vice versa; this is
8254 confusing. */
8257 /* for constants, LE gets turned into LT */
8261 {
8272 comparison_const_width
8274 else
8275 comparison_const_width
8279 comparison_sign_mask
8282 /* If the comparison value is not a loop invariant, then we
8283 can not reverse this loop.
8285 ??? If the insns which initialize the comparison value as
8286 a whole compute an invariant result, then we could move
8287 them out of the loop and proceed with loop reversal. */
8295 /* Normalize the initial value if it is an integer and
8296 has no other use except as a counter. This will allow
8297 a few more loops to be reversed. */
8301 {
8303 /* The code below requires comparison_val to be a multiple
8304 of add_val in order to do the loop reversal, so
8305 round up comparison_val to a multiple of add_val.
8306 Since comparison_value is constant, we know that the
8307 current comparison code is LT. */
8309 comparison_val
8311 /* We postpone overflow checks for COMPARISON_VAL here;
8312 even if there is an overflow, we might still be able to
8313 reverse the loop, if converting the loop exit test to
8314 NE is possible. */
8316 }
8318 /* First check if we can do a vanilla loop reversal. */
8320 /* If we have a decrement_and_branch_on_count,
8321 prefer the NE test, since this will allow that
8322 instruction to be generated. Note that we must
8323 use a vanilla loop reversal if the biv is used to
8324 calculate a giv or has a non-counting use. */
8325 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8326 && defined (HAVE_decrement_and_branch_on_count)
8330 #endif
8332 /* Now do postponed overflow checks on COMPARISON_VAL. */
8335 {
8336 /* Register will always be nonnegative, with value
8337 0 on last iteration */
8341 }
8345 {
8348 }
8349 else
8355 /* If the initial value is not zero, or if the comparison
8356 value is not an exact multiple of the increment, then we
8357 can not reverse this loop. */
8360 {
8363 }
8364 else
8365 {
8368 }
8372 /* Reset these in case we normalized the initial value
8373 and comparison value above. */
8376 {
8378 final_value
8380 }
8383 /* Save some info needed to produce the new insns. */
8388 /* Set start_value; if this is not a CONST_INT, we need
8389 to generate a SUB.
8390 Initialize biv to start_value before loop start.
8391 The old initializing insn will be deleted as a
8392 dead store by flow.c. */
8395 {
8398 }
8400 {
8408 start_value
8414 }
8416 {
8419 initial_value);
8423 start_value
8426 }
8427 else
8428 /* We could handle the other cases too, but it'll be
8429 better to have a testcase first. */
8432 /* We may not have a single insn which can increment a reg, so
8433 create a sequence to hold all the insns from expand_inc. */
8442 /* Update biv info to reflect its new status. */
8447 /* Update loop info. */
8456 /* Inc LABEL_NUSES so that delete_insn will
8457 not delete the label. */
8460 /* Emit an insn after the end of the loop to set the biv's
8461 proper exit value if it is used anywhere outside the loop. */
8467 /* Delete compare/branch at end of loop. */
8472 /* Add new compare/branch insn at end of loop. */
8484 ;
8490 {
8492 {
8493 /* Increment of LABEL_NUSES done above. */
8494 /* Register is now always nonnegative,
8495 so add REG_NONNEG note to the branch. */
8498 }
8500 }
8502 /* No insn may reference both the reversed and another biv or it
8503 will fail (see comment near the top of the loop reversal
8504 code).
8505 Earlier on, we have verified that the biv has no use except
8506 counting, or it is the only biv in this function.
8507 However, the code that computes no_use_except_counting does
8508 not verify reg notes. It's possible to have an insn that
8509 references another biv, and has a REG_EQUAL note with an
8510 expression based on the reversed biv. To avoid this case,
8511 remove all REG_EQUAL notes based on the reversed biv
8512 here. */
8515 {
8518 /* If this is a set of a GIV based on the reversed biv, any
8519 REG_EQUAL notes should still be correct. */
8526 {
8531 else
8533 }
8534 }
8536 /* Mark that this biv has been reversed. Each giv which depends
8537 on this biv, and which is also live past the end of the loop
8538 will have to be fixed up. */
8543 {
8547 else
8549 }
8552 }
8553 }
8554 }
8557 }
8558 \f
8559 /* Verify whether the biv BL appears to be eliminable,
8560 based on the insns in the loop that refer to it.
8562 If ELIMINATE_P is non-zero, actually do the elimination.
8564 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8565 determine whether invariant insns should be placed inside or at the
8566 start of the loop. */
8568 static int
8574 {
8577 rtx p;
8579 /* Scan all insns in the loop, stopping if we find one that uses the
8580 biv in a way that we cannot eliminate. */
8583 {
8588 /* If this is a libcall that sets a giv, skip ahead to its end. */
8590 {
8594 {
8599 {
8606 }
8607 }
8608 }
8613 {
8619 }
8620 }
8623 {
8628 }
8631 }
8632 \f
8633 /* INSN and REFERENCE are instructions in the same insn chain.
8634 Return non-zero if INSN is first. */
8636 int
8639 {
8643 {
8644 /* Start with test for not first so that INSN == REFERENCE yields not
8645 first. */
8651 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8652 previous insn, hence the <= comparison below does not work if
8653 P is a note. */
8664 }
8665 }
8667 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8668 the offset that we have to take into account due to auto-increment /
8669 div derivation is zero. */
8670 static int
8673 rtx insn;
8674 {
8675 /* If the giv V had the auto-inc address optimization applied
8676 to it, and INSN occurs between the giv insn and the biv
8677 insn, then we'd have to adjust the value used here.
8678 This is rare, so we don't bother to make this possible. */
8687 }
8689 /* If BL appears in X (part of the pattern of INSN), see if we can
8690 eliminate its use. If so, return 1. If not, return 0.
8692 If BIV does not appear in X, return 1.
8694 If ELIMINATE_P is non-zero, actually do the elimination.
8695 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8696 Depending on how many items have been moved out of the loop, it
8697 will either be before INSN (when WHERE_INSN is non-zero) or at the
8698 start of the loop (when WHERE_INSN is zero). */
8700 static int
8706 basic_block where_bb;
8707 rtx where_insn;
8708 {
8714 #ifdef HAVE_cc0
8716 #endif
8722 {
8724 /* If we haven't already been able to do something with this BIV,
8725 we can't eliminate it. */
8731 /* If this sets the BIV, it is not a problem. */
8735 /* If this is an insn that defines a giv, it is also ok because
8736 it will go away when the giv is reduced. */
8741 #ifdef HAVE_cc0
8743 {
8744 /* Can replace with any giv that was reduced and
8745 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8746 Require a constant for MULT_VAL, so we know it's nonzero.
8747 ??? We disable this optimization to avoid potential
8748 overflows. */
8756 {
8763 /* If the giv has the opposite direction of change,
8764 then reverse the comparison. */
8768 else
8771 /* We can probably test that giv's reduced reg. */
8774 }
8776 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8777 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8778 Require a constant for MULT_VAL, so we know it's nonzero.
8779 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8780 overflow problem. */
8792 {
8799 /* If the giv has the opposite direction of change,
8800 then reverse the comparison. */
8804 else
8808 /* Replace biv with the giv's reduced register. */
8813 /* Insn doesn't support that constant or invariant. Copy it
8814 into a register (it will be a loop invariant.) */
8821 /* Substitute the new register for its invariant value in
8822 the compare expression. */
8826 }
8827 }
8828 #endif
8835 /* See if either argument is the biv. */
8840 else
8844 {
8845 /* First try to replace with any giv that has constant positive
8846 mult_val and constant add_val. We might be able to support
8847 negative mult_val, but it seems complex to do it in general. */
8859 {
8863 /* Don't eliminate if the linear combination that makes up
8864 the giv overflows when it is applied to ARG. */
8866 {
8867 rtx add_val;
8871 else
8877 }
8882 /* Replace biv with the giv's reduced reg. */
8885 /* If all constants are actually constant integers and
8886 the derived constant can be directly placed in the COMPARE,
8887 do so. */
8890 {
8893 }
8894 else
8895 {
8896 /* Otherwise, load it into a register. */
8901 }
8907 }
8909 /* Look for giv with positive constant mult_val and nonconst add_val.
8910 Insert insns to calculate new compare value.
8911 ??? Turn this off due to possible overflow. */
8919 {
8920 rtx tem;
8930 /* Replace biv with giv's reduced register. */
8934 /* Compute value to compare against. */
8938 /* Use it in this insn. */
8942 }
8943 }
8945 {
8947 {
8948 /* Look for giv with constant positive mult_val and nonconst
8949 add_val. Insert insns to compute new compare value.
8950 ??? Turn this off due to possible overflow. */
8957 {
8958 rtx tem;
8968 /* Replace biv with giv's reduced register. */
8972 /* Compute value to compare against. */
8979 }
8980 }
8982 /* This code has problems. Basically, you can't know when
8983 seeing if we will eliminate BL, whether a particular giv
8984 of ARG will be reduced. If it isn't going to be reduced,
8985 we can't eliminate BL. We can try forcing it to be reduced,
8986 but that can generate poor code.
8988 The problem is that the benefit of reducing TV, below should
8989 be increased if BL can actually be eliminated, but this means
8990 we might have to do a topological sort of the order in which
8991 we try to process biv. It doesn't seem worthwhile to do
8992 this sort of thing now. */
8994 #if 0
8995 /* Otherwise the reg compared with had better be a biv. */
9000 /* Look for a pair of givs, one for each biv,
9001 with identical coefficients. */
9003 {
9015 {
9022 /* Replace biv with its giv's reduced reg. */
9024 /* Replace other operand with the other giv's
9025 reduced reg. */
9028 }
9029 }
9030 #endif
9031 }
9033 /* If we get here, the biv can't be eliminated. */
9037 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9038 biv is used in it, since it will be replaced. */
9046 }
9048 /* See if any subexpression fails elimination. */
9051 {
9053 {
9066 }
9067 }
9070 }
9071 \f
9072 /* Return nonzero if the last use of REG
9073 is in an insn following INSN in the same basic block. */
9075 static int
9077 rtx reg;
9078 rtx insn;
9079 {
9080 rtx n;
9084 {
9087 }
9089 }
9090 \f
9091 /* Called via `note_stores' to record the initial value of a biv. Here we
9092 just record the location of the set and process it later. */
9094 static void
9096 rtx dest;
9097 rtx set;
9099 {
9110 /* If this is the first set found, record it. */
9112 {
9115 }
9116 }
9117 \f
9118 /* If any of the registers in X are "old" and currently have a last use earlier
9119 than INSN, update them to have a last use of INSN. Their actual last use
9120 will be the previous insn but it will not have a valid uid_luid so we can't
9121 use it. X must be a source expression only. */
9123 static void
9125 rtx x;
9126 rtx insn;
9127 {
9128 /* Check for the case where INSN does not have a valid luid. In this case,
9129 there is no need to modify the regno_last_uid, as this can only happen
9130 when code is inserted after the loop_end to set a pseudo's final value,
9131 and hence this insn will never be the last use of x.
9132 ???? This comment is not correct. See for example loop_givs_reduce.
9133 This may insert an insn before another new insn. */
9137 {
9139 }
9140 else
9141 {
9145 {
9151 }
9152 }
9153 }
9154 \f
9155 /* Given an insn INSN and condition COND, return the condition in a
9156 canonical form to simplify testing by callers. Specifically:
9158 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9159 (2) Both operands will be machine operands; (cc0) will have been replaced.
9160 (3) If an operand is a constant, it will be the second operand.
9161 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9162 for GE, GEU, and LEU.
9164 If the condition cannot be understood, or is an inequality floating-point
9165 comparison which needs to be reversed, 0 will be returned.
9167 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9169 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9170 insn used in locating the condition was found. If a replacement test
9171 of the condition is desired, it should be placed in front of that
9172 insn and we will be sure that the inputs are still valid.
9174 If WANT_REG is non-zero, we wish the condition to be relative to that
9175 register, if possible. Therefore, do not canonicalize the condition
9176 further. */
9178 rtx
9180 rtx insn;
9181 rtx cond;
9184 rtx want_reg;
9185 {
9188 rtx set;
9189 rtx tem;
9207 /* If we are comparing a register with zero, see if the register is set
9208 in the previous insn to a COMPARE or a comparison operation. Perform
9209 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9210 in cse.c */
9215 {
9216 /* Set non-zero when we find something of interest. */
9219 #ifdef HAVE_cc0
9220 /* If comparison with cc0, import actual comparison from compare
9221 insn. */
9223 {
9234 }
9235 #endif
9237 /* If this is a COMPARE, pick up the two things being compared. */
9239 {
9243 }
9247 /* Go back to the previous insn. Stop if it is not an INSN. We also
9248 stop if it isn't a single set or if it has a REG_INC note because
9249 we don't want to bother dealing with it. */
9263 /* If this is setting OP0, get what it sets it to if it looks
9264 relevant. */
9266 {
9269 /* ??? We may not combine comparisons done in a CCmode with
9270 comparisons not done in a CCmode. This is to aid targets
9271 like Alpha that have an IEEE compliant EQ instruction, and
9272 a non-IEEE compliant BEQ instruction. The use of CCmode is
9273 actually artificial, simply to prevent the combination, but
9274 should not affect other platforms.
9276 However, we must allow VOIDmode comparisons to match either
9277 CCmode or non-CCmode comparison, because some ports have
9278 modeless comparisons inside branch patterns.
9280 ??? This mode check should perhaps look more like the mode check
9281 in simplify_comparison in combine. */
9289 && (STORE_FLAG_VALUE
9292 #ifdef FLOAT_STORE_FLAG_VALUE
9295 && (REAL_VALUE_NEGATIVE
9297 #endif
9298 ))
9309 && (STORE_FLAG_VALUE
9312 #ifdef FLOAT_STORE_FLAG_VALUE
9315 && (REAL_VALUE_NEGATIVE
9317 #endif
9318 ))
9324 {
9327 }
9328 else
9330 }
9333 /* If this sets OP0, but not directly, we have to give up. */
9337 {
9341 {
9346 }
9351 }
9352 }
9354 /* If constant is first, put it last. */
9358 /* If OP0 is the result of a comparison, we weren't able to find what
9359 was really being compared, so fail. */
9363 /* Canonicalize any ordered comparison with integers involving equality
9364 if we can do computations in the relevant mode and we do not
9365 overflow. */
9370 {
9373 unsigned HOST_WIDE_INT max_val
9377 {
9383 /* When cross-compiling, const_val might be sign-extended from
9384 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9404 }
9405 }
9407 #ifdef HAVE_cc0
9408 /* Never return CC0; return zero instead. */
9411 #endif
9414 }
9416 /* Given a jump insn JUMP, return the condition that will cause it to branch
9417 to its JUMP_LABEL. If the condition cannot be understood, or is an
9418 inequality floating-point comparison which needs to be reversed, 0 will
9419 be returned.
9421 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9422 insn used in locating the condition was found. If a replacement test
9423 of the condition is desired, it should be placed in front of that
9424 insn and we will be sure that the inputs are still valid. */
9426 rtx
9428 rtx jump;
9430 {
9431 rtx cond;
9433 rtx set;
9435 /* If this is not a standard conditional jump, we can't parse it. */
9443 /* If this branches to JUMP_LABEL when the condition is false, reverse
9444 the condition. */
9445 reverse
9450 }
9452 /* Similar to above routine, except that we also put an invariant last
9453 unless both operands are invariants. */
9455 rtx
9458 rtx x;
9459 {
9469 }
9471 /* Scan the function and determine whether it has indirect (computed) jumps.
9473 This is taken mostly from flow.c; similar code exists elsewhere
9474 in the compiler. It may be useful to put this into rtlanal.c. */
9475 static int
9477 rtx start;
9478 {
9479 rtx insn;
9486 }
9488 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9489 documentation for LOOP_MEMS for the definition of `appropriate'.
9490 This function is called from prescan_loop via for_each_rtx. */
9492 static int
9496 {
9505 {
9510 /* We're not interested in MEMs that are only clobbered. */
9514 /* We're not interested in the MEM associated with a
9515 CONST_DOUBLE, so there's no need to traverse into this. */
9519 /* We're not interested in any MEMs that only appear in notes. */
9523 /* This is not a MEM. */
9525 }
9527 /* See if we've already seen this MEM. */
9530 {
9532 /* The modes of the two memory accesses are different. If
9533 this happens, something tricky is going on, and we just
9534 don't optimize accesses to this MEM. */
9538 }
9540 /* Resize the array, if necessary. */
9542 {
9545 else
9551 }
9553 /* Actually insert the MEM. */
9555 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9556 because we can't put it in a register. We still store it in the
9557 table, though, so that if we see the same address later, but in a
9558 non-BLK mode, we'll not think we can optimize it at that point. */
9564 }
9567 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9569 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9570 register that is modified by an insn between FROM and TO. If the
9571 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9572 more, stop incrementing it, to avoid overflow.
9574 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9575 register I is used, if it is only used once. Otherwise, it is set
9576 to 0 (for no uses) or const0_rtx for more than one use. This
9577 parameter may be zero, in which case this processing is not done.
9579 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9580 optimize register I. */
9582 static void
9586 {
9589 /* last_set[n] is nonzero iff reg n has been set in the current
9590 basic block. In that case, it is the insn that last set reg n. */
9592 rtx insn;
9598 /* Grow the regs array if not allocated or too small. */
9600 {
9606 /* Zero the new elements. */
9609 }
9611 /* Clear previously scanned fields but do not clear n_times_set. */
9613 {
9617 }
9621 /* Scan the loop, recording register usage. */
9624 {
9626 {
9627 /* Record registers that have exactly one use. */
9630 /* Include uses in REG_EQUAL notes. */
9638 {
9642 last_set);
9643 }
9644 }
9648 }
9650 /* Invalidate all hard registers clobbered by calls. With one exception:
9651 a call-clobbered PIC register is still function-invariant for our
9652 purposes, since we can hoist any PIC calculations out of the loop.
9653 Thus the call to rtx_varies_p. */
9658 {
9661 }
9663 #ifdef AVOID_CCMODE_COPIES
9664 /* Don't try to move insns which set CC registers if we should not
9665 create CCmode register copies. */
9669 #endif
9671 /* Set regs->array[I].n_times_set for the new registers. */
9676 }
9678 /* Returns the number of real INSNs in the LOOP. */
9680 static int
9683 {
9685 rtx insn;
9693 }
9695 /* Move MEMs into registers for the duration of the loop. */
9697 static void
9700 {
9707 rtx end_label;
9708 /* Nonzero if the next instruction may never be executed. */
9715 /* We cannot use next_label here because it skips over normal insns. */
9720 /* Check to see if it's possible that some instructions in the loop are
9721 never executed. Also check if there is a goto out of the loop other
9722 than right after the end of the loop. */
9726 {
9730 /* If we enter the loop in the middle, and scan
9731 around to the beginning, don't set maybe_never
9732 for that. This must be an unconditional jump,
9733 otherwise the code at the top of the loop might
9734 never be executed. Unconditional jumps are
9735 followed a by barrier then loop end. */
9740 {
9741 /* If this is a jump outside of the loop but not right
9742 after the end of the loop, we would have to emit new fixup
9743 sequences for each such label. */
9745 JUMP_INSN is executed, we must be conservative. */
9754 /* Something complicated. */
9756 else
9757 /* If there are any more instructions in the loop, they
9758 might not be reached. */
9760 }
9763 }
9765 /* Find start of the extended basic block that enters the loop. */
9769 ;
9774 /* Build table of mems that get set to constant values before the
9775 loop. */
9779 /* Actually move the MEMs. */
9781 {
9782 regset_head load_copies;
9783 regset_head store_copies;
9785 rtx reg;
9787 rtx mem_list_entry;
9791 /* There's no telling whether or not MEM is modified. */
9794 /* Go through the MEMs written to in the loop to see if this
9795 one is aliased by one of them. */
9798 {
9803 {
9804 /* MEM is indeed aliased by this store. */
9807 }
9809 }
9815 /* If this MEM is written to, we must be sure that there
9816 are no reads from another MEM that aliases this one. */
9818 {
9822 {
9826 VOIDmode,
9828 rtx_varies_p))
9829 {
9830 /* It's not safe to hoist loop_info->mems[i] out of
9831 the loop because writes to it might not be
9832 seen by reads from loop_info->mems[j]. */
9835 }
9836 }
9837 }
9840 /* We can't access the MEM outside the loop; it might
9841 cause a trap that wouldn't have happened otherwise. */
9845 /* We thought we were going to lift this MEM out of the
9846 loop, but later discovered that we could not. */
9852 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9853 order to keep scan_loop from moving stores to this MEM
9854 out of the loop just because this REG is neither a
9855 user-variable nor used in the loop test. */
9860 /* Now, replace all references to the MEM with the
9861 corresponding pseudos. */
9866 {
9868 {
9869 rtx set;
9873 /* See if this copies the mem into a register that isn't
9874 modified afterwards. We'll try to do copy propagation
9875 a little further on. */
9877 /* @@@ This test is _way_ too conservative. */
9878 && ! maybe_never
9886 /* See if this copies the mem from a register that isn't
9887 modified afterwards. We'll try to remove the
9888 redundant copy later on by doing a little register
9889 renaming and copy propagation. This will help
9890 to untangle things for the BIV detection code. */
9892 && ! maybe_never
9900 /* If this is a call which uses / clobbers this memory
9901 location, we must not change the interface here. */
9905 {
9909 }
9910 else
9911 /* Replace the memory reference with the shadow register. */
9914 }
9919 }
9924 /* We couldn't replace all occurrences of the MEM. */
9926 else
9927 {
9928 /* Load the memory immediately before LOOP->START, which is
9929 the NOTE_LOOP_BEG. */
9931 rtx set;
9937 {
9941 {
9945 /* Extending hard register lifetimes causes crash
9946 on SRC targets. Doing so on non-SRC is
9947 probably also not good idea, since we most
9948 probably have pseudoregister equivalence as
9949 well. */
9952 }
9953 /* Use the constant equivalence if that is cheap enough. */
9959 {
9962 }
9964 /* If best_equiv is nonzero, we know that MEM is set to a
9965 constant or register before the loop. We will use this
9966 knowledge to initialize the shadow register with that
9967 constant or reg rather than by loading from MEM. */
9970 }
9975 {
9978 {
9981 }
9982 }
9988 {
9990 {
9993 }
9995 /* Store the memory immediately after END, which is
9996 the NOTE_LOOP_END. */
9999 }
10002 {
10007 }
10009 /* Attempt a bit of copy propagation. This helps untangle the
10010 data flow, and enables {basic,general}_induction_var to find
10011 more bivs/givs. */
10012 EXECUTE_IF_SET_IN_REG_SET
10014 {
10016 });
10019 EXECUTE_IF_SET_IN_REG_SET
10021 {
10023 });
10025 }
10026 }
10029 {
10030 /* Now, we need to replace all references to the previous exit
10031 label with the new one. */
10032 rtx_pair rr;
10037 {
10040 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10041 field. This is not handled by for_each_rtx because it doesn't
10042 handle unprinted ('0') fields. We need to update JUMP_LABEL
10043 because the immediately following unroll pass will use it.
10044 replace_label would not work anyways, because that only handles
10045 LABEL_REFs. */
10048 }
10049 }
10052 }
10054 /* For communication between note_reg_stored and its caller. */
10055 struct note_reg_stored_arg
10056 {
10058 rtx reg;
10059 };
10061 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10062 is equal to ARG. */
10063 static void
10067 {
10071 }
10073 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10074 There must be exactly one insn that sets this pseudo; it will be
10075 deleted if all replacements succeed and we can prove that the register
10076 is not used after the loop. */
10078 static void
10081 rtx replacement;
10083 {
10084 /* This is the reg that we are copying from. */
10087 rtx insn;
10088 /* These help keep track of whether we replaced all uses of the reg. */
10095 {
10096 rtx set;
10098 /* Only substitute within one extended basic block from the initializing
10099 insn. */
10106 /* Is this the initializing insn? */
10111 {
10118 }
10120 /* Only substitute after seeing the initializing insn. */
10122 {
10129 /* Stop replacing when REPLACEMENT is modified. */
10134 {
10137 /* It is possible that we've turned previously valid REG_EQUAL to
10138 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10139 REPLACEMENT is modified, we get different meaning. */
10143 }
10144 }
10145 }
10149 {
10153 {
10154 rtx first;
10155 rtx retval_note;
10157 /* Assume we're just deleting INIT_INSN. */
10159 /* Look for REG_RETVAL note. If we're deleting the end of
10160 the libcall sequence, the whole sequence can go. */
10162 /* If we found a REG_RETVAL note, find the first instruction
10163 in the sequence. */
10167 /* Delete the instructions. */
10169 }
10172 }
10173 }
10175 /* Replace all the instructions from FIRST up to and including LAST
10176 with NOTE_INSN_DELETED notes. */
10178 static void
10180 rtx first;
10181 rtx last;
10182 {
10184 {
10190 /* If this was the LAST instructions we're supposed to delete,
10191 we're done. */
10196 }
10197 }
10199 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10200 loop LOOP if the order of the sets of these registers can be
10201 swapped. There must be exactly one insn within the loop that sets
10202 this pseudo followed immediately by a move insn that sets
10203 REPLACEMENT with REGNO. */
10204 static void
10207 rtx replacement;
10209 {
10210 rtx insn;
10219 {
10220 /* Search for the insn that copies REGNO to NEW_REGNO? */
10228 }
10231 {
10232 rtx prev_insn;
10233 rtx prev_set;
10235 /* Some DEF-USE info would come in handy here to make this
10236 function more general. For now, just check the previous insn
10237 which is the most likely candidate for setting REGNO. */
10245 {
10246 /* We have:
10247 (set (reg regno) (expr))
10248 (set (reg new_regno) (reg regno))
10250 so try converting this to:
10251 (set (reg new_regno) (expr))
10252 (set (reg regno) (reg new_regno))
10254 The former construct is often generated when a global
10255 variable used for an induction variable is shadowed by a
10256 register (NEW_REGNO). The latter construct improves the
10257 chances of GIV replacement and BIV elimination. */
10267 {
10274 /* Update first use of REGNO. */
10278 /* Now perform copy propagation to hopefully
10279 remove all uses of REGNO within the loop. */
10281 }
10282 }
10283 }
10284 }
10286 /* Replace MEM with its associated pseudo register. This function is
10287 called from load_mems via for_each_rtx. DATA is actually a pointer
10288 to a structure describing the instruction currently being scanned
10289 and the MEM we are currently replacing. */
10291 static int
10295 {
10303 {
10308 /* We're not interested in the MEM associated with a
10309 CONST_DOUBLE, so there's no need to traverse into one. */
10313 /* This is not a MEM. */
10315 }
10318 /* This is not the MEM we are currently replacing. */
10321 /* Actually replace the MEM. */
10325 }
10327 static void
10329 rtx insn;
10330 rtx mem;
10331 rtx reg;
10332 {
10333 loop_replace_args args;
10340 }
10342 /* Replace one register with another. Called through for_each_rtx; PX points
10343 to the rtx being scanned. DATA is actually a pointer to
10344 a structure of arguments. */
10346 static int
10350 {
10361 }
10363 static void
10365 rtx insn;
10366 rtx reg;
10367 rtx replacement;
10368 {
10369 loop_replace_args args;
10376 }
10378 /* Replace occurrences of the old exit label for the loop with the new
10379 one. DATA is an rtx_pair containing the old and new labels,
10380 respectively. */
10382 static int
10386 {
10405 }
10406 \f
10407 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10408 (ignored in the interim). */
10410 static rtx
10413 basic_block where_bb ATTRIBUTE_UNUSED;
10414 rtx where_insn;
10415 rtx pattern;
10416 {
10418 }
10421 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10422 in basic block WHERE_BB (ignored in the interim) within the loop
10423 otherwise hoist PATTERN into the loop pre-header. */
10425 rtx
10428 basic_block where_bb ATTRIBUTE_UNUSED;
10429 rtx where_insn;
10430 rtx pattern;
10431 {
10435 }
10438 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10439 WHERE_BB (ignored in the interim) within the loop. */
10441 static rtx
10444 basic_block where_bb ATTRIBUTE_UNUSED;
10445 rtx where_insn;
10446 rtx pattern;
10447 {
10449 }
10452 /* Hoist insn for PATTERN into the loop pre-header. */
10454 rtx
10457 rtx pattern;
10458 {
10460 }
10463 /* Hoist call insn for PATTERN into the loop pre-header. */
10465 static rtx
10468 rtx pattern;
10469 {
10471 }
10474 /* Sink insn for PATTERN after the loop end. */
10476 rtx
10479 rtx pattern;
10480 {
10482 }
10484 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10485 and constant. Emit sequence of intructions to load it into REG */
10486 static rtx
10489 {
10490 rtx seq;
10498 }
10500 /* If the loop has multiple exits, emit insn for PATTERN before the
10501 loop to ensure that it will always be executed no matter how the
10502 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10503 since this is slightly more efficient. */
10505 static rtx
10508 rtx pattern;
10509 {
10512 else
10514 }
10515 \f
10516 static void
10521 {
10529 iv_num++;
10534 {
10537 }
10538 }
10541 static void
10546 {
10548 rtx incr;
10559 {
10562 }
10564 {
10567 }
10571 {
10575 }
10578 {
10582 }
10584 /* List the increments. */
10586 {
10590 }
10592 /* List the givs. */
10594 {
10599 else
10602 }
10603 }
10606 static void
10611 {
10622 {
10626 }
10629 }
10632 static void
10637 {
10644 else
10660 {
10662 {
10674 }
10675 }
10686 {
10690 }
10693 }
10696 void
10699 {
10701 }
10704 void
10707 {
10709 }
10712 void
10715 {
10717 }
10720 void
10723 {
10725 }
10728 #define LOOP_BLOCK_NUM_1(INSN) \
10729 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10731 /* The notes do not have an assigned block, so look at the next insn. */
10732 #define LOOP_BLOCK_NUM(INSN) \
10733 ((INSN) ? (GET_CODE (INSN) == NOTE \
10734 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10735 : LOOP_BLOCK_NUM_1 (INSN)) \
10736 : -1)
10738 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10740 static void
10745 {
10746 rtx label;
10751 /* Print diagnostics to compare our concept of a loop with
10752 what the loop notes say. */
10767 {
10787 {
10790 {
10793 }
10794 }
10797 /* This can happen when a marked loop appears as two nested loops,
10798 say from while (a || b) {}. The inner loop won't match
10799 the loop markers but the outer one will. */
10802 }
10803 }
10805 /* Call this function from the debugger to dump LOOP. */
10807 void
10810 {
10812 }
10814 /* Call this function from the debugger to dump LOOPS. */
10816 void
10819 {
10821 }