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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
68 #ifndef CHECK_STACK_LIMIT
69 #define CHECK_STACK_LIMIT (-1)
70 #endif
72 /* Return index of given mode in mult and division cost tables. */
73 #define MODE_INDEX(mode) \
74 ((mode) == QImode ? 0 \
75 : (mode) == HImode ? 1 \
76 : (mode) == SImode ? 2 \
77 : (mode) == DImode ? 3 \
78 : 4)
80 /* Processor costs (relative to an add) */
81 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
82 #define COSTS_N_BYTES(N) ((N) * 2)
84 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
86 const
109 in QImode, HImode and SImode.
110 Relative to reg-reg move (2). */
114 in SFmode, DFmode and XFmode */
116 in SFmode, DFmode and XFmode */
119 in SImode and DImode */
121 in SImode and DImode */
124 in SImode, DImode and TImode */
126 in SImode, DImode and TImode */
154 };
156 /* Processor costs (relative to an add) */
157 static const
180 in QImode, HImode and SImode.
181 Relative to reg-reg move (2). */
185 in SFmode, DFmode and XFmode */
187 in SFmode, DFmode and XFmode */
190 in SImode and DImode */
192 in SImode and DImode */
195 in SImode, DImode and TImode */
197 in SImode, DImode and TImode */
211 DUMMY_STRINGOP_ALGS},
213 DUMMY_STRINGOP_ALGS},
225 };
227 static const
250 in QImode, HImode and SImode.
251 Relative to reg-reg move (2). */
255 in SFmode, DFmode and XFmode */
257 in SFmode, DFmode and XFmode */
260 in SImode and DImode */
262 in SImode and DImode */
265 in SImode, DImode and TImode */
267 in SImode, DImode and TImode */
270 shared for code and data, so 4kB is
271 not really precise. */
283 DUMMY_STRINGOP_ALGS},
285 DUMMY_STRINGOP_ALGS},
297 };
299 static const
322 in QImode, HImode and SImode.
323 Relative to reg-reg move (2). */
327 in SFmode, DFmode and XFmode */
329 in SFmode, DFmode and XFmode */
332 in SImode and DImode */
334 in SImode and DImode */
337 in SImode, DImode and TImode */
339 in SImode, DImode and TImode */
353 DUMMY_STRINGOP_ALGS},
355 DUMMY_STRINGOP_ALGS},
367 };
369 static const
392 in QImode, HImode and SImode.
393 Relative to reg-reg move (2). */
397 in SFmode, DFmode and XFmode */
399 in SFmode, DFmode and XFmode */
402 in SImode and DImode */
404 in SImode and DImode */
407 in SImode, DImode and TImode */
409 in SImode, DImode and TImode */
422 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
423 (we ensure the alignment). For small blocks inline loop is still a
424 noticeable win, for bigger blocks either rep movsl or rep movsb is
425 way to go. Rep movsb has apparently more expensive startup time in CPU,
426 but after 4K the difference is down in the noise. */
430 DUMMY_STRINGOP_ALGS},
434 DUMMY_STRINGOP_ALGS},
446 };
448 static const
471 in QImode, HImode and SImode.
472 Relative to reg-reg move (2). */
476 in SFmode, DFmode and XFmode */
478 in SFmode, DFmode and XFmode */
482 in SImode and DImode */
484 in SImode and DImode */
487 in SImode, DImode and TImode */
489 in SImode, DImode and TImode */
503 DUMMY_STRINGOP_ALGS},
505 DUMMY_STRINGOP_ALGS},
517 };
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
563 have integrated l2 cache, but
564 optimizing for k6 is not important
565 enough to worry about that. */
576 DUMMY_STRINGOP_ALGS},
578 DUMMY_STRINGOP_ALGS},
590 };
592 static const
615 in QImode, HImode and SImode.
616 Relative to reg-reg move (2). */
620 in SFmode, DFmode and XFmode */
622 in SFmode, DFmode and XFmode */
625 in SImode and DImode */
627 in SImode and DImode */
630 in SImode, DImode and TImode */
632 in SImode, DImode and TImode */
645 /* For some reason, Athlon deals better with REP prefix (relative to loops)
646 compared to K8. Alignment becomes important after 8 bytes for memcpy and
647 128 bytes for memset. */
649 DUMMY_STRINGOP_ALGS},
651 DUMMY_STRINGOP_ALGS},
663 };
665 static const
688 in QImode, HImode and SImode.
689 Relative to reg-reg move (2). */
693 in SFmode, DFmode and XFmode */
695 in SFmode, DFmode and XFmode */
698 in SImode and DImode */
700 in SImode and DImode */
703 in SImode, DImode and TImode */
705 in SImode, DImode and TImode */
710 /* New AMD processors never drop prefetches; if they cannot be performed
711 immediately, they are queued. We set number of simultaneous prefetches
712 to a large constant to reflect this (it probably is not a good idea not
713 to limit number of prefetches at all, as their execution also takes some
714 time). */
723 /* K8 has optimized REP instruction for medium sized blocks, but for very
724 small blocks it is better to use loop. For large blocks, libcall can
725 do nontemporary accesses and beat inline considerably. */
745 };
769 in QImode, HImode and SImode.
770 Relative to reg-reg move (2). */
774 in SFmode, DFmode and XFmode */
776 in SFmode, DFmode and XFmode */
779 in SImode and DImode */
781 in SImode and DImode */
784 in SImode, DImode and TImode */
786 in SImode, DImode and TImode */
788 /* On K8:
789 MOVD reg64, xmmreg Double FSTORE 4
790 MOVD reg32, xmmreg Double FSTORE 4
791 On AMDFAM10:
792 MOVD reg64, xmmreg Double FADD 3
793 1/1 1/1
794 MOVD reg32, xmmreg Double FADD 3
795 1/1 1/1 */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
814 very small blocks it is better to use loop. For large blocks, libcall can
815 do nontemporary accesses and beat inline considerably. */
835 };
859 in QImode, HImode and SImode.
860 Relative to reg-reg move (2). */
864 in SFmode, DFmode and XFmode */
866 in SFmode, DFmode and XFmode */
869 in SImode and DImode */
871 in SImode and DImode */
874 in SImode, DImode and TImode */
876 in SImode, DImode and TImode */
878 /* On K8:
879 MOVD reg64, xmmreg Double FSTORE 4
880 MOVD reg32, xmmreg Double FSTORE 4
881 On AMDFAM10:
882 MOVD reg64, xmmreg Double FADD 3
883 1/1 1/1
884 MOVD reg32, xmmreg Double FADD 3
885 1/1 1/1 */
889 /* New AMD processors never drop prefetches; if they cannot be performed
890 immediately, they are queued. We set number of simultaneous prefetches
891 to a large constant to reflect this (it probably is not a good idea not
892 to limit number of prefetches at all, as their execution also takes some
893 time). */
903 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
904 very small blocks it is better to use loop. For large blocks, libcall
905 can do nontemporary accesses and beat inline considerably. */
925 };
949 in QImode, HImode and SImode.
950 Relative to reg-reg move (2). */
954 in SFmode, DFmode and XFmode */
956 in SFmode, DFmode and XFmode */
959 in SImode and DImode */
961 in SImode and DImode */
964 in SImode, DImode and TImode */
966 in SImode, DImode and TImode */
968 /* On K8:
969 MOVD reg64, xmmreg Double FSTORE 4
970 MOVD reg32, xmmreg Double FSTORE 4
971 On AMDFAM10:
972 MOVD reg64, xmmreg Double FADD 3
973 1/1 1/1
974 MOVD reg32, xmmreg Double FADD 3
975 1/1 1/1 */
979 /* New AMD processors never drop prefetches; if they cannot be performed
980 immediately, they are queued. We set number of simultaneous prefetches
981 to a large constant to reflect this (it probably is not a good idea not
982 to limit number of prefetches at all, as their execution also takes some
983 time). */
993 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
994 very small blocks it is better to use loop. For large blocks, libcall
995 can do nontemporary accesses and beat inline considerably. */
1015 };
1039 in QImode, HImode and SImode.
1040 Relative to reg-reg move (2). */
1044 in SFmode, DFmode and XFmode */
1046 in SFmode, DFmode and XFmode */
1049 in SImode and DImode */
1051 in SImode and DImode */
1054 in SImode, DImode and TImode */
1056 in SImode, DImode and TImode */
1061 /* New AMD processors never drop prefetches; if they cannot be performed
1062 immediately, they are queued. We set number of simultaneous prefetches
1063 to a large constant to reflect this (it probably is not a good idea not
1064 to limit number of prefetches at all, as their execution also takes some
1065 time). */
1075 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1097 };
1121 in QImode, HImode and SImode.
1122 Relative to reg-reg move (2). */
1126 in SFmode, DFmode and XFmode */
1128 in SFmode, DFmode and XFmode */
1131 in SImode and DImode */
1133 in SImode and DImode */
1136 in SImode, DImode and TImode */
1138 in SImode, DImode and TImode */
1140 /* On K8:
1141 MOVD reg64, xmmreg Double FSTORE 4
1142 MOVD reg32, xmmreg Double FSTORE 4
1143 On AMDFAM10:
1144 MOVD reg64, xmmreg Double FADD 3
1145 1/1 1/1
1146 MOVD reg32, xmmreg Double FADD 3
1147 1/1 1/1 */
1160 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1161 very small blocks it is better to use loop. For large blocks, libcall can
1162 do nontemporary accesses and beat inline considerably. */
1182 };
1206 in QImode, HImode and SImode.
1207 Relative to reg-reg move (2). */
1211 in SFmode, DFmode and XFmode */
1213 in SFmode, DFmode and XFmode */
1216 in SImode and DImode */
1218 in SImode and DImode */
1221 in SImode, DImode and TImode */
1223 in SImode, DImode and TImode */
1225 /* On K8:
1226 MOVD reg64, xmmreg Double FSTORE 4
1227 MOVD reg32, xmmreg Double FSTORE 4
1228 On AMDFAM10:
1229 MOVD reg64, xmmreg Double FADD 3
1230 1/1 1/1
1231 MOVD reg32, xmmreg Double FADD 3
1232 1/1 1/1 */
1264 };
1266 static const
1289 in QImode, HImode and SImode.
1290 Relative to reg-reg move (2). */
1294 in SFmode, DFmode and XFmode */
1296 in SFmode, DFmode and XFmode */
1299 in SImode and DImode */
1301 in SImode and DImode */
1304 in SImode, DImode and TImode */
1306 in SImode, DImode and TImode */
1320 DUMMY_STRINGOP_ALGS},
1323 DUMMY_STRINGOP_ALGS},
1335 };
1337 static const
1360 in QImode, HImode and SImode.
1361 Relative to reg-reg move (2). */
1365 in SFmode, DFmode and XFmode */
1367 in SFmode, DFmode and XFmode */
1370 in SImode and DImode */
1372 in SImode and DImode */
1375 in SImode, DImode and TImode */
1377 in SImode, DImode and TImode */
1408 };
1410 static const
1433 in QImode, HImode and SImode.
1434 Relative to reg-reg move (2). */
1438 in SFmode, DFmode and XFmode */
1440 in SFmode, DFmode and XFmode */
1443 in SImode and DImode */
1445 in SImode and DImode */
1448 in SImode, DImode and TImode */
1450 in SImode, DImode and TImode */
1481 };
1483 /* Generic64 should produce code tuned for Nocona and K8. */
1484 static const
1487 /* On all chips taken into consideration lea is 2 cycles and more. With
1488 this cost however our current implementation of synth_mult results in
1489 use of unnecessary temporary registers causing regression on several
1490 SPECfp benchmarks. */
1511 in QImode, HImode and SImode.
1512 Relative to reg-reg move (2). */
1516 in SFmode, DFmode and XFmode */
1518 in SFmode, DFmode and XFmode */
1521 in SImode and DImode */
1523 in SImode and DImode */
1526 in SImode, DImode and TImode */
1528 in SImode, DImode and TImode */
1534 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1535 value is increased to perhaps more appropriate value of 5. */
1560 };
1562 /* core_cost should produce code tuned for Core familly of CPUs. */
1563 static const
1566 /* On all chips taken into consideration lea is 2 cycles and more. With
1567 this cost however our current implementation of synth_mult results in
1568 use of unnecessary temporary registers causing regression on several
1569 SPECfp benchmarks. */
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1613 /* FIXME perhaps more appropriate value is 5. */
1641 };
1643 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1644 Athlon and K8. */
1645 static const
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1700 DUMMY_STRINGOP_ALGS},
1703 DUMMY_STRINGOP_ALGS},
1715 };
1717 /* Set by -mtune. */
1720 /* Set by -mtune or -Os. */
1723 /* Processor feature/optimization bitmasks. */
1724 #define m_386 (1<<PROCESSOR_I386)
1725 #define m_486 (1<<PROCESSOR_I486)
1726 #define m_PENT (1<<PROCESSOR_PENTIUM)
1727 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1728 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1729 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1730 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1731 #define m_CORE2 (1<<PROCESSOR_CORE2)
1732 #define m_COREI7 (1<<PROCESSOR_COREI7)
1733 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1734 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1735 #define m_ATOM (1<<PROCESSOR_ATOM)
1737 #define m_GEODE (1<<PROCESSOR_GEODE)
1738 #define m_K6 (1<<PROCESSOR_K6)
1739 #define m_K6_GEODE (m_K6 | m_GEODE)
1740 #define m_K8 (1<<PROCESSOR_K8)
1741 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1742 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1743 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1744 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1745 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1746 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1747 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1748 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1749 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1750 #define m_BTVER (m_BTVER1 | m_BTVER2)
1751 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1753 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1754 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1756 /* Generic instruction choice should be common subset of supported CPUs
1757 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1758 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1760 /* Feature tests against the various tunings. */
1763 /* Feature tests against the various tunings used to create ix86_tune_features
1764 based on the processor mask. */
1766 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1767 negatively, so enabling for Generic64 seems like good code size
1768 tradeoff. We can't enable it for 32bit generic because it does not
1769 work well with PPro base chips. */
1772 /* X86_TUNE_PUSH_MEMORY */
1775 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1778 /* X86_TUNE_UNROLL_STRLEN */
1781 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1782 on simulation result. But after P4 was made, no performance benefit
1783 was observed with branch hints. It also increases the code size.
1784 As a result, icc never generates branch hints. */
1787 /* X86_TUNE_DOUBLE_WITH_ADD */
1790 /* X86_TUNE_USE_SAHF */
1791 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1793 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1794 partial dependencies. */
1797 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1798 register stalls on Generic32 compilation setting as well. However
1799 in current implementation the partial register stalls are not eliminated
1800 very well - they can be introduced via subregs synthesized by combine
1801 and can happen in caller/callee saving sequences. Because this option
1802 pays back little on PPro based chips and is in conflict with partial reg
1803 dependencies used by Athlon/P4 based chips, it is better to leave it off
1804 for generic32 for now. */
1805 m_PPRO,
1807 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1810 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1811 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1814 /* X86_TUNE_USE_HIMODE_FIOP */
1817 /* X86_TUNE_USE_SIMODE_FIOP */
1820 /* X86_TUNE_USE_MOV0 */
1821 m_K6,
1823 /* X86_TUNE_USE_CLTD */
1826 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1827 m_PENT4,
1829 /* X86_TUNE_SPLIT_LONG_MOVES */
1830 m_PPRO,
1832 /* X86_TUNE_READ_MODIFY_WRITE */
1835 /* X86_TUNE_READ_MODIFY */
1838 /* X86_TUNE_PROMOTE_QIMODE */
1841 /* X86_TUNE_FAST_PREFIX */
1844 /* X86_TUNE_SINGLE_STRINGOP */
1847 /* X86_TUNE_QIMODE_MATH */
1850 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1851 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1852 might be considered for Generic32 if our scheme for avoiding partial
1853 stalls was more effective. */
1856 /* X86_TUNE_PROMOTE_QI_REGS */
1859 /* X86_TUNE_PROMOTE_HI_REGS */
1860 m_PPRO,
1862 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1863 over esp addition. */
1866 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1867 over esp addition. */
1868 m_PENT,
1870 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1871 over esp subtraction. */
1874 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1875 over esp subtraction. */
1878 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1879 for DFmode copies */
1882 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1885 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1886 conflict here in between PPro/Pentium4 based chips that thread 128bit
1887 SSE registers as single units versus K8 based chips that divide SSE
1888 registers to two 64bit halves. This knob promotes all store destinations
1889 to be 128bit to allow register renaming on 128bit SSE units, but usually
1890 results in one extra microop on 64bit SSE units. Experimental results
1891 shows that disabling this option on P4 brings over 20% SPECfp regression,
1892 while enabling it on K8 brings roughly 2.4% regression that can be partly
1893 masked by careful scheduling of moves. */
1896 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1899 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1902 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1903 m_BDVER ,
1905 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1906 are resolved on SSE register parts instead of whole registers, so we may
1907 maintain just lower part of scalar values in proper format leaving the
1908 upper part undefined. */
1909 m_ATHLON_K8,
1911 /* X86_TUNE_SSE_TYPELESS_STORES */
1912 m_AMD_MULTIPLE,
1914 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1917 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1920 /* X86_TUNE_PROLOGUE_USING_MOVE */
1923 /* X86_TUNE_EPILOGUE_USING_MOVE */
1926 /* X86_TUNE_SHIFT1 */
1929 /* X86_TUNE_USE_FFREEP */
1930 m_AMD_MULTIPLE,
1932 /* X86_TUNE_INTER_UNIT_MOVES */
1935 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1938 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1939 than 4 branch instructions in the 16 byte window. */
1942 /* X86_TUNE_SCHEDULE */
1945 /* X86_TUNE_USE_BT */
1948 /* X86_TUNE_USE_INCDEC */
1951 /* X86_TUNE_PAD_RETURNS */
1954 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1955 m_ATOM,
1957 /* X86_TUNE_EXT_80387_CONSTANTS */
1960 /* X86_TUNE_AVOID_VECTOR_DECODE */
1963 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1964 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1967 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1968 vector path on AMD machines. */
1971 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1972 machines. */
1975 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1976 than a MOV. */
1977 m_PENT,
1979 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1980 but one byte longer. */
1981 m_PENT,
1983 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1984 operand that cannot be represented using a modRM byte. The XOR
1985 replacement is long decoded, so this split helps here as well. */
1986 m_K6,
1988 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1989 from FP to FP. */
1992 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1993 from integer to FP. */
1994 m_AMDFAM10,
1996 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1997 with a subsequent conditional jump instruction into a single
1998 compare-and-branch uop. */
1999 m_BDVER,
2001 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2002 will impact LEA instruction selection. */
2003 m_ATOM,
2005 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2006 instructions. */
2009 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2010 at -O3. For the moment, the prefetching seems badly tuned for Intel
2011 chips. */
2014 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2015 the auto-vectorizer. */
2018 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2019 during reassociation of integer computation. */
2020 m_ATOM,
2022 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2023 during reassociation of fp computation. */
2024 m_ATOM,
2026 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2027 regs instead of memory. */
2028 m_CORE_ALL,
2030 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2031 a conditional move. */
2032 m_ATOM
2033 };
2035 /* Feature tests against the various architecture variations. */
2038 /* Feature tests against the various architecture variations, used to create
2039 ix86_arch_features based on the processor mask. */
2041 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2044 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2047 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2050 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2053 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2055 };
2057 static const unsigned int x86_accumulate_outgoing_args
2060 static const unsigned int x86_arch_always_fancy_math_387
2063 static const unsigned int x86_avx256_split_unaligned_load
2066 static const unsigned int x86_avx256_split_unaligned_store
2069 /* In case the average insn count for single function invocation is
2070 lower than this constant, emit fast (but longer) prologue and
2071 epilogue code. */
2072 #define FAST_PROLOGUE_INSN_COUNT 20
2074 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2079 /* Array of the smallest class containing reg number REGNO, indexed by
2080 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2083 {
2084 /* ax, dx, cx, bx */
2086 /* si, di, bp, sp */
2088 /* FP registers */
2091 /* arg pointer */
2092 NON_Q_REGS,
2093 /* flags, fpsr, fpcr, frame */
2095 /* SSE registers */
2098 /* MMX registers */
2101 /* REX registers */
2104 /* SSE REX registers */
2107 };
2109 /* The "default" register map used in 32bit mode. */
2112 {
2120 };
2122 /* The "default" register map used in 64bit mode. */
2125 {
2133 };
2135 /* Define the register numbers to be used in Dwarf debugging information.
2136 The SVR4 reference port C compiler uses the following register numbers
2137 in its Dwarf output code:
2138 0 for %eax (gcc regno = 0)
2139 1 for %ecx (gcc regno = 2)
2140 2 for %edx (gcc regno = 1)
2141 3 for %ebx (gcc regno = 3)
2142 4 for %esp (gcc regno = 7)
2143 5 for %ebp (gcc regno = 6)
2144 6 for %esi (gcc regno = 4)
2145 7 for %edi (gcc regno = 5)
2146 The following three DWARF register numbers are never generated by
2147 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2148 believes these numbers have these meanings.
2149 8 for %eip (no gcc equivalent)
2150 9 for %eflags (gcc regno = 17)
2151 10 for %trapno (no gcc equivalent)
2152 It is not at all clear how we should number the FP stack registers
2153 for the x86 architecture. If the version of SDB on x86/svr4 were
2154 a bit less brain dead with respect to floating-point then we would
2155 have a precedent to follow with respect to DWARF register numbers
2156 for x86 FP registers, but the SDB on x86/svr4 is so completely
2157 broken with respect to FP registers that it is hardly worth thinking
2158 of it as something to strive for compatibility with.
2159 The version of x86/svr4 SDB I have at the moment does (partially)
2160 seem to believe that DWARF register number 11 is associated with
2161 the x86 register %st(0), but that's about all. Higher DWARF
2162 register numbers don't seem to be associated with anything in
2163 particular, and even for DWARF regno 11, SDB only seems to under-
2164 stand that it should say that a variable lives in %st(0) (when
2165 asked via an `=' command) if we said it was in DWARF regno 11,
2166 but SDB still prints garbage when asked for the value of the
2167 variable in question (via a `/' command).
2168 (Also note that the labels SDB prints for various FP stack regs
2169 when doing an `x' command are all wrong.)
2170 Note that these problems generally don't affect the native SVR4
2171 C compiler because it doesn't allow the use of -O with -g and
2172 because when it is *not* optimizing, it allocates a memory
2173 location for each floating-point variable, and the memory
2174 location is what gets described in the DWARF AT_location
2175 attribute for the variable in question.
2176 Regardless of the severe mental illness of the x86/svr4 SDB, we
2177 do something sensible here and we use the following DWARF
2178 register numbers. Note that these are all stack-top-relative
2179 numbers.
2180 11 for %st(0) (gcc regno = 8)
2181 12 for %st(1) (gcc regno = 9)
2182 13 for %st(2) (gcc regno = 10)
2183 14 for %st(3) (gcc regno = 11)
2184 15 for %st(4) (gcc regno = 12)
2185 16 for %st(5) (gcc regno = 13)
2186 17 for %st(6) (gcc regno = 14)
2187 18 for %st(7) (gcc regno = 15)
2188 */
2190 {
2198 };
2200 /* Define parameter passing and return registers. */
2203 {
2205 };
2208 {
2210 };
2213 {
2215 };
2217 /* Define the structure for the machine field in struct function. */
2222 rtx rtl;
2224 };
2226 /* Structure describing stack frame layout.
2227 Stack grows downward:
2229 [arguments]
2230 <- ARG_POINTER
2231 saved pc
2233 saved static chain if ix86_static_chain_on_stack
2235 saved frame pointer if frame_pointer_needed
2236 <- HARD_FRAME_POINTER
2237 [saved regs]
2238 <- regs_save_offset
2239 [padding0]
2241 [saved SSE regs]
2242 <- sse_regs_save_offset
2243 [padding1] |
2244 | <- FRAME_POINTER
2245 [va_arg registers] |
2246 |
2247 [frame] |
2248 |
2249 [padding2] | = to_allocate
2250 <- STACK_POINTER
2251 */
2252 struct ix86_frame
2253 {
2260 /* The offsets relative to ARG_POINTER. */
2261 HOST_WIDE_INT frame_pointer_offset;
2262 HOST_WIDE_INT hard_frame_pointer_offset;
2263 HOST_WIDE_INT stack_pointer_offset;
2264 HOST_WIDE_INT hfp_save_offset;
2265 HOST_WIDE_INT reg_save_offset;
2266 HOST_WIDE_INT sse_reg_save_offset;
2268 /* When save_regs_using_mov is set, emit prologue using
2269 move instead of push instructions. */
2271 };
2273 /* Which cpu are we scheduling for. */
2276 /* Which cpu are we optimizing for. */
2279 /* Which instruction set architecture to use. */
2282 /* True if processor has SSE prefetch instruction. */
2285 /* -mstackrealign option */
2302 /* Preferred alignment for stack boundary in bits. */
2305 /* Alignment for incoming stack boundary in bits specified at
2306 command line. */
2309 /* Default alignment for incoming stack boundary in bits. */
2312 /* Alignment for incoming stack boundary in bits. */
2315 /* Calling abi specific va_list type nodes. */
2319 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2323 /* Fence to use after loop using movnt. */
2324 tree x86_mfence;
2326 /* Register class used for passing given 64bit part of the argument.
2327 These represent classes as documented by the PS ABI, with the exception
2328 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2329 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2331 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2332 whenever possible (upper half does contain padding). */
2333 enum x86_64_reg_class
2334 {
2335 X86_64_NO_CLASS,
2336 X86_64_INTEGER_CLASS,
2337 X86_64_INTEGERSI_CLASS,
2338 X86_64_SSE_CLASS,
2339 X86_64_SSESF_CLASS,
2340 X86_64_SSEDF_CLASS,
2341 X86_64_SSEUP_CLASS,
2342 X86_64_X87_CLASS,
2343 X86_64_X87UP_CLASS,
2344 X86_64_COMPLEX_X87_CLASS,
2345 X86_64_MEMORY_CLASS
2346 };
2348 #define MAX_CLASSES 4
2350 /* Table of constants used by fldpi, fldln2, etc.... */
2354 \f
2359 const_tree);
2371 enum ix86_function_specific_strings
2372 {
2373 IX86_FUNCTION_SPECIFIC_ARCH,
2374 IX86_FUNCTION_SPECIFIC_TUNE,
2375 IX86_FUNCTION_SPECIFIC_MAX
2376 };
2394 \f
2395 #ifndef SUBTARGET32_DEFAULT_CPU
2397 #endif
2399 /* Whether -mtune= or -march= were specified */
2403 /* Vectorization library interface and handlers. */
2409 /* Processor target table, indexed by processor number */
2410 struct ptt
2411 {
2418 };
2421 {
2432 /* Core 2 */
2434 /* Core i7 */
2436 /* Core avx2 */
2447 };
2450 {
2479 "btver2"
2480 };
2481 \f
2482 static bool
2484 {
2486 }
2488 static unsigned int
2490 {
2493 /* vzeroupper instructions are inserted immediately after reload to
2494 account for possible spills from 256bit registers. The pass
2495 reuses mode switching infrastructure by re-running mode insertion
2496 pass, so disable entities that have already been processed. */
2502 /* Call optimize_mode_switching. */
2505 }
2508 {
2509 {
2510 RTL_PASS,
2525 }
2526 };
2528 /* Return true if a red-zone is in use. */
2532 {
2534 }
2535 \f
2536 /* Return a string that documents the current -m options. The caller is
2537 responsible for freeing the string. */
2543 {
2544 struct ix86_target_opts
2545 {
2548 };
2550 /* This table is ordered so that options like -msse4.2 that imply
2551 preceding options while match those first. */
2553 {
2589 };
2591 /* Flag options. */
2593 {
2621 };
2638 /* Add -march= option. */
2640 {
2643 }
2645 /* Add -mtune= option. */
2647 {
2650 }
2652 /* Add -m32/-m64/-mx32. */
2654 {
2657 else
2659 isa &= ~ (OPTION_MASK_ISA_64BIT
2660 | OPTION_MASK_ABI_64
2662 }
2663 else
2667 /* Pick out the options in isa options. */
2669 {
2671 {
2674 }
2675 }
2678 {
2681 isa);
2682 }
2684 /* Add flag options. */
2686 {
2688 {
2691 }
2692 }
2695 {
2698 }
2700 /* Add -fpmath= option. */
2702 {
2705 {
2720 }
2721 }
2723 /* Any options? */
2729 /* Size the string. */
2733 {
2738 }
2740 /* Build the string. */
2745 {
2752 {
2754 line_len++;
2757 {
2761 }
2762 }
2766 {
2770 }
2771 }
2777 }
2779 /* Return true, if profiling code should be emitted before
2780 prologue. Otherwise it returns false.
2781 Note: For x86 with "hotfix" it is sorried. */
2782 static bool
2784 {
2786 }
2788 /* Function that is callable from the debugger to print the current
2789 options. */
2790 void
2792 {
2798 {
2801 }
2802 else
2806 }
2807 \f
2808 /* Override various settings based on options. If MAIN_ARGS_P, the
2809 options are from the command line, otherwise they are from
2810 attributes. */
2812 static void
2814 {
2822 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2823 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2824 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2825 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2826 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2827 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2828 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2829 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2830 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2831 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2832 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2833 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2834 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2835 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2836 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2837 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2838 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2839 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2840 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2841 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2842 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2843 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2844 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2845 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2846 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2847 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2848 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2849 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2850 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2851 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2852 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2853 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2854 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2855 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2856 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2857 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2858 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2859 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2860 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2861 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2863 /* if this reaches 64, need to widen struct pta flags below */
2865 static struct pta
2866 {
2871 }
2873 {
3003 PTA_64BIT
3005 };
3007 /* -mrecip options. */
3008 static struct
3009 {
3012 }
3014 {
3021 };
3025 /* Set up prefix/suffix so the error messages refer to either the command
3026 line argument, or the attribute(target). */
3028 {
3032 }
3033 else
3034 {
3038 }
3040 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3041 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3044 #ifdef TARGET_BI_ARCH
3045 else
3046 {
3047 #if TARGET_BI_ARCH == 1
3048 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3049 is on and OPTION_MASK_ABI_X32 is off. We turn off
3050 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3051 -mx32. */
3054 #else
3055 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3056 on and OPTION_MASK_ABI_64 is off. We turn off
3057 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3058 -m64. */
3061 #endif
3062 }
3063 #endif
3066 {
3067 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3068 OPTION_MASK_ABI_64 for TARGET_X32. */
3071 }
3073 {
3074 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3075 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3078 }
3080 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3081 SUBTARGET_OVERRIDE_OPTIONS;
3082 #endif
3084 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3085 SUBSUBTARGET_OVERRIDE_OPTIONS;
3086 #endif
3088 /* -fPIC is the default for x86_64. */
3092 /* Need to check -mtune=generic first. */
3094 {
3097 /* As special support for cross compilers we read -mtune=native
3098 as -mtune=generic. With native compilers we won't see the
3099 -mtune=native, as it was changed by the driver. */
3101 {
3104 else
3106 }
3107 /* If this call is for setting the option attribute, allow the
3108 generic32/generic64 that was previously set. */
3112 ;
3120 }
3121 else
3122 {
3126 {
3129 }
3131 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3132 need to use a sensible tune option. */
3136 {
3139 else
3141 }
3142 }
3145 {
3146 /* rep; movq isn't available in 32-bit code. */
3149 }
3153 else
3157 {
3163 }
3164 else
3171 {
3173 {
3217 {
3220 }
3228 }
3229 }
3230 else
3231 {
3232 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3233 use of rip-relative addressing. This eliminates fixups that
3234 would otherwise be needed if this object is to be placed in a
3235 DLL, and is essentially just as efficient as direct addressing. */
3242 else
3244 }
3246 {
3249 }
3256 {
3259 /* Default cpu tuning to the architecture. */
3384 }
3399 {
3403 {
3405 {
3407 {
3415 }
3416 else
3419 }
3420 }
3421 else
3422 {
3423 /* Adjust tuning when compiling for 32-bit ABI. */
3425 {
3433 }
3434 }
3435 /* Intel CPUs have always interpreted SSE prefetch instructions as
3436 NOPs; so, we can enable SSE prefetch instructions even when
3437 -mtune (rather than -march) points us to a processor that has them.
3438 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3439 higher processors. */
3444 }
3454 #ifndef USE_IX86_FRAME_POINTER
3455 #define USE_IX86_FRAME_POINTER 0
3456 #endif
3458 #ifndef USE_X86_64_FRAME_POINTER
3459 #define USE_X86_64_FRAME_POINTER 0
3460 #endif
3462 /* Set the default values for switches whose default depends on TARGET_64BIT
3463 in case they weren't overwritten by command line options. */
3465 {
3472 }
3473 else
3474 {
3481 }
3486 else
3489 /* Arrange to set up i386_stack_locals for all functions. */
3492 /* Validate -mregparm= value. */
3494 {
3498 {
3502 }
3503 }
3507 /* Default align_* from the processor table. */
3509 {
3512 }
3514 {
3517 }
3519 {
3521 }
3523 /* Provide default for -mbranch-cost= value. */
3528 {
3531 /* Enable by default the SSE and MMX builtins. Do allow the user to
3532 explicitly disable any of these. In particular, disabling SSE and
3533 MMX for kernel code is extremely useful. */
3535 ix86_isa_flags
3541 }
3542 else
3543 {
3547 ix86_isa_flags
3550 /* i386 ABI does not specify red zone. It still makes sense to use it
3551 when programmer takes care to stack from being destroyed. */
3554 }
3556 /* Keep nonleaf frame pointers. */
3562 /* If we're doing fast math, we don't care about comparison order
3563 wrt NaNs. This lets us use a shorter comparison sequence. */
3567 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3568 since the insns won't need emulation. */
3572 /* Likewise, if the target doesn't have a 387, or we've specified
3573 software floating point, don't use 387 inline intrinsics. */
3577 /* Turn on MMX builtins for -msse. */
3581 /* Enable SSE prefetch. */
3585 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3589 /* Turn on lzcnt instruction for -mabm. */
3593 /* Validate -mpreferred-stack-boundary= value or default it to
3594 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3597 {
3603 {
3607 else
3610 }
3611 else
3612 ix86_preferred_stack_boundary
3614 }
3616 /* Set the default value for -mstackrealign. */
3622 /* Validate -mincoming-stack-boundary= value or default it to
3623 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3626 {
3631 else
3632 {
3633 ix86_user_incoming_stack_boundary
3635 ix86_incoming_stack_boundary
3637 }
3638 }
3640 /* Accept -msseregparm only if at least SSE support is enabled. */
3646 {
3648 {
3650 {
3653 }
3655 {
3658 }
3659 }
3660 }
3661 else
3664 /* If the i387 is disabled, then do not return values in it. */
3668 /* Use external vectorized library in vectorizing intrinsics. */
3671 {
3682 }
3690 /* ??? Unwind info is not correct around the CFG unless either a frame
3691 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3692 unwind info generation to be aware of the CFG and propagating states
3693 around edges. */
3696 && flag_omit_frame_pointer
3698 {
3704 }
3706 /* If stack probes are required, the space used for large function
3707 arguments on the stack must also be probed, so enable
3708 -maccumulate-outgoing-args so this happens in the prologue. */
3711 {
3716 }
3718 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3719 {
3725 }
3727 /* When scheduling description is not available, disable scheduler pass
3728 so it won't slow down the compilation and make x87 code slower. */
3749 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3751 && HAVE_prefetch
3756 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3757 can be optimized to ap = __builtin_next_arg (0). */
3762 {
3765 {
3768 ix86_gen_tls_local_dynamic_base_64
3770 }
3771 else
3772 {
3775 ix86_gen_tls_local_dynamic_base_64
3777 }
3778 }
3779 else
3780 {
3783 }
3786 {
3795 }
3796 else
3797 {
3806 }
3808 #ifdef USE_IX86_CLD
3809 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3812 #endif
3815 {
3820 }
3822 {
3826 }
3828 {
3829 #if defined(PROFILE_BEFORE_PROLOGUE)
3831 #else
3833 #endif
3834 }
3837 {
3838 /* When not optimize for size, enable vzeroupper optimization for
3839 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3840 AVX unaligned load/store. */
3842 {
3852 /* Enable 128-bit AVX instruction generation
3853 for the auto-vectorizer. */
3857 }
3858 }
3859 else
3860 {
3861 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3863 }
3866 {
3873 {
3876 {
3878 q++;
3879 }
3880 else
3885 else
3886 {
3889 {
3892 }
3895 {
3899 }
3900 }
3905 else
3907 }
3908 }
3915 /* Default long double to 64-bit for Bionic. */
3920 /* Save the initial options in case the user does function specific
3921 options. */
3923 target_option_default_node = target_option_current_node
3925 }
3927 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3929 static void
3931 {
3932 static struct register_pass_info insert_vzeroupper_info
3935 };
3940 /* This needs to be done at start up. It's convenient to do it here. */
3942 }
3944 /* Update register usage after having seen the compiler flags. */
3946 static void
3948 {
3952 /* The PIC register, if it exists, is fixed. */
3957 /* For 32-bit targets, squash the REX registers. */
3959 {
3964 }
3966 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3974 {
3975 /* Set/reset conditionally defined registers from
3976 CALL_USED_REGISTERS initializer. */
3980 /* Calculate registers of CLOBBERED_REGS register set
3981 as call used registers from GENERAL_REGS register set. */
3985 }
3987 /* If MMX is disabled, squash the registers. */
3993 /* If SSE is disabled, squash the registers. */
3999 /* If the FPU is disabled, squash the registers. */
4004 }
4006 \f
4007 /* Save the current options */
4009 static void
4011 {
4022 /* The fields are char but the variables are not; make sure the
4023 values fit in the fields. */
4028 }
4030 /* Restore the current options */
4032 static void
4034 {
4050 /* Recreate the arch feature tests if the arch changed */
4052 {
4057 }
4059 /* Recreate the tune optimization tests */
4061 {
4066 }
4067 }
4069 /* Print the current options */
4071 static void
4074 {
4096 {
4099 }
4100 }
4102 \f
4103 /* Inner function to process the attribute((target(...))), take an argument and
4104 set the current options from the argument. If we have a list, recursively go
4105 over the list. */
4107 static bool
4110 {
4114 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4115 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4116 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4117 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4118 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4120 enum ix86_opt_type
4121 {
4122 ix86_opt_unknown,
4123 ix86_opt_yes,
4124 ix86_opt_no,
4125 ix86_opt_str,
4126 ix86_opt_enum,
4127 ix86_opt_isa
4128 };
4130 static const struct
4131 {
4138 /* isa options */
4175 /* enum options */
4178 /* string options */
4182 /* flag options */
4184 OPT_mcld,
4185 MASK_CLD),
4188 OPT_mfancy_math_387,
4189 MASK_NO_FANCY_MATH_387),
4192 OPT_mieee_fp,
4193 MASK_IEEE_FP),
4196 OPT_minline_all_stringops,
4197 MASK_INLINE_ALL_STRINGOPS),
4200 OPT_minline_stringops_dynamically,
4201 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4204 OPT_mno_align_stringops,
4205 MASK_NO_ALIGN_STRINGOPS),
4208 OPT_mrecip,
4209 MASK_RECIP),
4211 };
4213 /* If this is a list, recurse to get the options. */
4215 {
4225 }
4228 {
4231 }
4233 /* Handle multiple arguments separated by commas. */
4237 {
4251 {
4255 }
4256 else
4257 {
4260 }
4262 /* Recognize no-xxx. */
4264 {
4268 }
4269 else
4272 /* Find the option. */
4276 {
4284 {
4289 }
4290 }
4292 /* Process the option. */
4294 {
4297 }
4300 {
4306 }
4309 {
4315 else
4317 }
4320 {
4322 {
4325 }
4326 else
4328 }
4331 {
4339 global_dc);
4340 else
4341 {
4344 }
4345 }
4347 else
4349 }
4352 }
4354 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4356 tree
4358 {
4373 /* Process each of the options on the chain. */
4378 /* If the changed options are different from the default, rerun
4379 ix86_option_override_internal, and then save the options away.
4380 The string options are are attribute options, and will be undone
4381 when we copy the save structure. */
4387 {
4388 /* If we are using the default tune= or arch=, undo the string assigned,
4389 and use the default. */
4400 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4404 {
4407 }
4409 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4412 /* Add any builtin functions with the new isa if any. */
4415 /* Save the current options unless we are validating options for
4416 #pragma. */
4423 /* Free up memory allocated to hold the strings */
4426 }
4429 }
4431 /* Hook to validate attribute((target("string"))). */
4433 static bool
4436 tree args,
4438 {
4442 /* attribute((target("default"))) does nothing, beyond
4443 affecting multi-versioning. */
4454 /* If the function changed the optimization levels as well as setting target
4455 options, start with the optimizations specified. */
4460 /* The target attributes may also change some optimization flags, so update
4461 the optimization options if necessary. */
4470 {
4475 }
4484 }
4486 \f
4487 /* Hook to determine if one function can safely inline another. */
4489 static bool
4491 {
4496 /* If callee has no option attributes, then it is ok to inline. */
4500 /* If caller has no option attributes, but callee does then it is not ok to
4501 inline. */
4505 else
4506 {
4510 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4511 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4512 function. */
4517 /* See if we have the same non-isa options. */
4521 /* See if arch, tune, etc. are the same. */
4534 else
4536 }
4539 }
4541 \f
4542 /* Remember the last target of ix86_set_current_function. */
4545 /* Establish appropriate back-end context for processing the function
4546 FNDECL. The argument might be NULL to indicate processing at top
4547 level, outside of any function scope. */
4548 static void
4550 {
4551 /* Only change the context if the function changes. This hook is called
4552 several times in the course of compiling a function, and we don't want to
4553 slow things down too much or call target_reinit when it isn't safe. */
4555 {
4556 tree old_tree = (ix86_previous_fndecl
4560 tree new_tree = (fndecl
4566 ;
4569 {
4573 }
4576 {
4582 }
4583 }
4584 }
4586 \f
4587 /* Return true if this goes in large data/bss. */
4589 static bool
4591 {
4595 /* Functions are never large data. */
4600 {
4606 }
4607 else
4608 {
4611 /* If this is an incomplete type with size 0, then we can't put it
4612 in data because it might be too big when completed. */
4615 }
4618 }
4620 /* Switch to the appropriate section for output of DECL.
4621 DECL is either a `VAR_DECL' node or a constant of some sort.
4622 RELOC indicates whether forming the initial value of DECL requires
4623 link-time relocations. */
4626 ATTRIBUTE_UNUSED;
4631 {
4634 {
4638 {
4672 /* We don't split these for medium model. Place them into
4673 default sections and hope for best. */
4675 }
4677 {
4678 /* We might get called with string constants, but get_named_section
4679 doesn't like them as they are not DECLs. Also, we need to set
4680 flags in that case. */
4684 }
4685 }
4687 }
4689 /* Build up a unique section name, expressed as a
4690 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4691 RELOC indicates whether the initial value of EXP requires
4692 link-time relocations. */
4694 static void ATTRIBUTE_UNUSED
4696 {
4699 {
4701 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4705 {
4729 /* We don't split these for medium model. Place them into
4730 default sections and hope for best. */
4732 }
4734 {
4741 /* If we're using one_only, then there needs to be a .gnu.linkonce
4742 prefix to the section name. */
4749 }
4750 }
4752 }
4754 #ifdef COMMON_ASM_OP
4755 /* This says how to output assembler code to declare an
4756 uninitialized external linkage data object.
4758 For medium model x86-64 we need to use .largecomm opcode for
4759 large objects. */
4760 void
4764 {
4768 else
4773 }
4774 #endif
4776 /* Utility function for targets to use in implementing
4777 ASM_OUTPUT_ALIGNED_BSS. */
4779 void
4783 {
4787 else
4790 #ifdef ASM_DECLARE_OBJECT_NAME
4793 #else
4794 /* Standard thing is just output label for the object. */
4798 }
4799 \f
4800 /* Decide whether we must probe the stack before any space allocation
4801 on this target. It's essentially TARGET_STACK_PROBE except when
4802 -fstack-check causes the stack to be already probed differently. */
4804 bool
4806 {
4807 /* Do not probe the stack twice if static stack checking is enabled. */
4812 }
4813 \f
4814 /* Decide whether we can make a sibling call to a function. DECL is the
4815 declaration of the function being targeted by the call and EXP is the
4816 CALL_EXPR representing the call. */
4818 static bool
4820 {
4824 /* If we are generating position-independent code, we cannot sibcall
4825 optimize any indirect call, or a direct call to a global function,
4826 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4828 && !TARGET_64BIT
4829 && flag_pic
4833 /* If we need to align the outgoing stack, then sibcalling would
4834 unalign the stack, which may break the called function. */
4840 {
4843 }
4844 else
4845 {
4846 /* We're looking at the CALL_EXPR, we need the type of the function. */
4851 }
4853 /* Check that the return value locations are the same. Like
4854 if we are returning floats on the 80387 register stack, we cannot
4855 make a sibcall from a function that doesn't return a float to a
4856 function that does or, conversely, from a function that does return
4857 a float to a function that doesn't; the necessary stack adjustment
4858 would not be executed. This is also the place we notice
4859 differences in the return value ABI. Note that it is ok for one
4860 of the functions to have void return type as long as the return
4861 value of the other is passed in a register. */
4866 {
4869 }
4871 ;
4876 {
4877 /* The SYSV ABI has more call-clobbered registers;
4878 disallow sibcalls from MS to SYSV. */
4882 }
4883 else
4884 {
4885 /* If this call is indirect, we'll need to be able to use a
4886 call-clobbered register for the address of the target function.
4887 Make sure that all such registers are not used for passing
4888 parameters. Note that DLLIMPORT functions are indirect. */
4891 {
4893 {
4894 /* ??? Need to count the actual number of registers to be used,
4895 not the possible number of registers. Fix later. */
4897 }
4898 }
4899 }
4901 /* Otherwise okay. That also includes certain types of indirect calls. */
4903 }
4905 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4906 and "sseregparm" calling convention attributes;
4907 arguments as in struct attribute_spec.handler. */
4909 static tree
4911 tree args,
4914 {
4919 {
4921 name);
4924 }
4926 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4928 {
4929 tree cst;
4932 {
4934 }
4937 {
4939 }
4943 {
4946 name);
4948 }
4950 {
4954 }
4957 }
4960 {
4961 /* Do not warn when emulating the MS ABI. */
4966 name);
4969 }
4971 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4973 {
4975 {
4977 }
4979 {
4981 }
4983 {
4985 }
4987 {
4989 }
4990 }
4992 /* Can combine stdcall with fastcall (redundant), regparm and
4993 sseregparm. */
4995 {
4997 {
4999 }
5001 {
5003 }
5005 {
5007 }
5008 }
5010 /* Can combine cdecl with regparm and sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 {
5030 name);
5032 {
5034 }
5036 {
5038 }
5040 {
5042 }
5043 }
5045 /* Can combine sseregparm with all attributes. */
5048 }
5050 /* The transactional memory builtins are implicitly regparm or fastcall
5051 depending on the ABI. Override the generic do-nothing attribute that
5052 these builtins were declared with, and replace it with one of the two
5053 attributes that we expect elsewhere. */
5055 static tree
5057 tree args ATTRIBUTE_UNUSED,
5060 {
5061 tree alt;
5063 /* In no case do we want to add the placeholder attribute. */
5066 /* The 64-bit ABI is unchanged for transactional memory. */
5070 /* ??? Is there a better way to validate 32-bit windows? We have
5071 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5074 else
5075 {
5078 }
5082 }
5084 /* This function determines from TYPE the calling-convention. */
5086 unsigned int
5088 {
5091 tree attrs;
5098 {
5108 /* Regparam isn't allowed for thiscall and fastcall. */
5110 {
5115 }
5119 }
5126 || is_stdarg
5132 }
5134 /* Return 0 if the attributes for two types are incompatible, 1 if they
5135 are compatible, and 2 if they are nearly compatible (which causes a
5136 warning to be generated). */
5138 static int
5140 {
5156 }
5157 \f
5158 /* Return the regparm value for a function with the indicated TYPE and DECL.
5159 DECL may be NULL when calling function indirectly
5160 or considering a libcall. */
5162 static int
5164 {
5165 tree attr;
5176 {
5179 {
5182 }
5183 }
5189 /* Use register calling convention for local functions when possible. */
5192 && optimize
5194 {
5195 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5198 {
5201 /* Make sure no regparm register is taken by a
5202 fixed register variable. */
5207 /* We don't want to use regparm(3) for nested functions as
5208 these use a static chain pointer in the third argument. */
5212 /* In 32-bit mode save a register for the split stack. */
5216 /* Each fixed register usage increases register pressure,
5217 so less registers should be used for argument passing.
5218 This functionality can be overriden by an explicit
5219 regparm value. */
5222 globals++;
5224 local_regparm
5229 }
5230 }
5233 }
5235 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5236 DFmode (2) arguments in SSE registers for a function with the
5237 indicated TYPE and DECL. DECL may be NULL when calling function
5238 indirectly or considering a libcall. Otherwise return 0. */
5240 static int
5242 {
5245 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5246 by the sseregparm attribute. */
5249 {
5251 {
5253 {
5257 else
5260 }
5262 }
5265 }
5267 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5268 (and DFmode for SSE2) arguments in SSE registers. */
5271 {
5272 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5276 }
5279 }
5281 /* Return true if EAX is live at the start of the function. Used by
5282 ix86_expand_prologue to determine if we need special help before
5283 calling allocate_stack_worker. */
5285 static bool
5287 {
5288 /* Cheat. Don't bother working forward from ix86_function_regparm
5289 to the function type to whether an actual argument is located in
5290 eax. Instead just look at cfg info, which is still close enough
5291 to correct at this point. This gives false positives for broken
5292 functions that might use uninitialized data that happens to be
5293 allocated in eax, but who cares? */
5295 }
5297 static bool
5299 {
5300 tree attr;
5303 {
5309 /* For 32-bit MS-ABI the default is to keep aggregate
5310 return pointer. */
5313 }
5315 }
5317 /* Value is the number of bytes of arguments automatically
5318 popped when returning from a subroutine call.
5319 FUNDECL is the declaration node of the function (as a tree),
5320 FUNTYPE is the data type of the function (as a tree),
5321 or for a library call it is an identifier node for the subroutine name.
5322 SIZE is the number of bytes of arguments passed on the stack.
5324 On the 80386, the RTD insn may be used to pop them if the number
5325 of args is fixed, but if the number is variable then the caller
5326 must pop them all. RTD can't be used for library calls now
5327 because the library is compiled with the Unix compiler.
5328 Use of RTD is a selectable option, since it is incompatible with
5329 standard Unix calling sequences. If the option is not selected,
5330 the caller must always pop the args.
5332 The attribute stdcall is equivalent to RTD on a per module basis. */
5334 static int
5336 {
5339 /* None of the 64-bit ABIs pop arguments. */
5350 /* Lose any fake structure return argument if it is passed on the stack. */
5353 {
5357 }
5360 }
5362 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5364 static bool
5366 {
5367 /* Check operand constraints in case hard registers were propagated
5368 into insn pattern. This check prevents combine pass from
5369 generating insn patterns with invalid hard register operands.
5370 These invalid insns can eventually confuse reload to error out
5371 with a spill failure. See also PRs 46829 and 46843. */
5373 {
5380 {
5388 /* A unary operator may be accepted by the predicate, but it
5389 is irrelevant for matching constraints. */
5394 {
5402 }
5409 /* Operand has no constraints, anything is OK. */
5413 {
5416 && operands_match_p
5420 {
5423 }
5424 }
5428 }
5429 }
5432 }
5433 \f
5434 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5436 static unsigned HOST_WIDE_INT
5438 {
5440 }
5441 \f
5442 /* Argument support functions. */
5444 /* Return true when register may be used to pass function parameters. */
5445 bool
5447 {
5452 {
5456 else
5462 }
5465 {
5468 }
5469 else
5470 {
5474 }
5476 /* TODO: The function should depend on current function ABI but
5477 builtins.c would need updating then. Therefore we use the
5478 default ABI. */
5480 /* RAX is used as hidden argument to va_arg functions. */
5486 else
5493 }
5495 /* Return if we do not know how to pass TYPE solely in registers. */
5497 static bool
5499 {
5503 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5504 The layout_type routine is crafty and tries to trick us into passing
5505 currently unsupported vector types on the stack by using TImode. */
5508 }
5510 /* It returns the size, in bytes, of the area reserved for arguments passed
5511 in registers for the function represented by fndecl dependent to the used
5512 abi format. */
5513 int
5515 {
5519 else
5524 }
5526 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5527 call abi used. */
5528 enum calling_abi
5530 {
5532 {
5535 {
5538 }
5542 }
5544 }
5546 static bool
5548 {
5550 {
5554 else
5556 }
5558 }
5560 static enum calling_abi
5562 {
5566 }
5568 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5569 call abi used. */
5570 enum calling_abi
5572 {
5576 }
5578 /* Write the extra assembler code needed to declare a function properly. */
5580 void
5582 tree decl)
5583 {
5587 {
5593 }
5595 #ifdef SUBTARGET_ASM_UNWIND_INIT
5597 #endif
5601 /* Output magic byte marker, if hot-patch attribute is set. */
5603 {
5605 {
5606 /* leaq [%rsp + 0], %rsp */
5609 }
5610 else
5611 {
5612 /* movl.s %edi, %edi
5613 push %ebp
5614 movl.s %esp, %ebp */
5617 }
5618 }
5619 }
5621 /* regclass.c */
5624 /* Implementation of call abi switching target hook. Specific to FNDECL
5625 the specific call register sets are set. See also
5626 ix86_conditional_register_usage for more details. */
5627 void
5629 {
5632 else
5634 }
5636 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5637 expensive re-initialization of init_regs each time we switch function context
5638 since this is needed only during RTL expansion. */
5639 static void
5641 {
5645 }
5647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5648 for a call to a function whose data type is FNTYPE.
5649 For a library call, FNTYPE is 0. */
5651 void
5655 tree fndecl,
5657 {
5663 {
5666 }
5667 else
5668 {
5671 }
5675 /* Set up the number of registers to use for passing arguments. */
5682 {
5684 ? X86_64_REGPARM_MAX
5686 }
5688 {
5691 {
5693 ? X86_64_SSE_REGPARM_MAX
5695 }
5696 }
5703 /* Because type might mismatch in between caller and callee, we need to
5704 use actual type of function for local calls.
5705 FIXME: cgraph_analyze can be told to actually record if function uses
5706 va_start so for local functions maybe_vaarg can be made aggressive
5707 helping K&R code.
5708 FIXME: once typesytem is fixed, we won't need this code anymore. */
5716 {
5717 /* If there are variable arguments, then we won't pass anything
5718 in registers in 32-bit mode. */
5720 {
5728 }
5730 /* Use ecx and edx registers if function has fastcall attribute,
5731 else look for regparm information. */
5733 {
5736 {
5739 }
5741 {
5744 }
5745 else
5747 }
5749 /* Set up the number of SSE registers used for passing SFmode
5750 and DFmode arguments. Warn for mismatching ABI. */
5752 }
5753 }
5755 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5756 But in the case of vector types, it is some vector mode.
5758 When we have only some of our vector isa extensions enabled, then there
5759 are some modes for which vector_mode_supported_p is false. For these
5760 modes, the generic vector support in gcc will choose some non-vector mode
5761 in order to implement the type. By computing the natural mode, we'll
5762 select the proper ABI location for the operand and not depend on whatever
5763 the middle-end decides to do with these vector types.
5765 The midde-end can't deal with the vector types > 16 bytes. In this
5766 case, we return the original mode and warn ABI change if CUM isn't
5767 NULL. */
5769 static enum machine_mode
5771 {
5775 {
5778 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5780 {
5785 else
5788 /* Get the mode which has this inner mode and number of units. */
5792 {
5794 {
5798 && !warnedavx
5800 {
5804 }
5806 }
5808 {
5812 && !warnedsse
5814 {
5818 }
5820 }
5821 else
5823 }
5826 }
5827 }
5830 }
5832 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5833 this may not agree with the mode that the type system has chosen for the
5834 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5835 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5837 static rtx
5840 {
5841 rtx tmp;
5845 else
5846 {
5850 }
5853 }
5855 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5856 of this code is to classify each 8bytes of incoming argument by the register
5857 class and assign registers accordingly. */
5859 /* Return the union class of CLASS1 and CLASS2.
5860 See the x86-64 PS ABI for details. */
5862 static enum x86_64_reg_class
5864 {
5865 /* Rule #1: If both classes are equal, this is the resulting class. */
5869 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5870 the other class. */
5876 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5880 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5888 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5889 MEMORY is used. */
5898 /* Rule #6: Otherwise class SSE is used. */
5900 }
5902 /* Classify the argument of type TYPE and mode MODE.
5903 CLASSES will be filled by the register class used to pass each word
5904 of the operand. The number of words is returned. In case the parameter
5905 should be passed in memory, 0 is returned. As a special case for zero
5906 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5908 BIT_OFFSET is used internally for handling records and specifies offset
5909 of the offset in bits modulo 256 to avoid overflow cases.
5911 See the x86-64 PS ABI for details.
5912 */
5914 static int
5917 {
5918 HOST_WIDE_INT bytes =
5920 int words
5923 /* Variable sized entities are always passed/returned in memory. */
5931 /* Special case check for pointer to shared, on 64-bit target. */
5935 {
5938 }
5941 {
5943 tree field;
5946 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5953 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5954 signalize memory class, so handle it as special case. */
5956 {
5959 }
5961 /* Classify each field of record and merge classes. */
5963 {
5965 /* And now merge the fields of structure. */
5967 {
5969 {
5975 /* Bitfields are always classified as integer. Handle them
5976 early, since later code would consider them to be
5977 misaligned integers. */
5979 {
5988 }
5989 else
5990 {
5995 /* Flexible array member is ignored. */
6002 {
6006 {
6009 "the ABI of passing struct with"
6010 " a flexible array member has"
6012 }
6014 }
6016 subclasses,
6026 }
6027 }
6028 }
6032 /* Arrays are handled as small records. */
6033 {
6040 /* The partial classes are now full classes. */
6051 }
6054 /* Unions are similar to RECORD_TYPE but offset is always 0.
6055 */
6057 {
6059 {
6067 bit_offset);
6072 }
6073 }
6078 }
6081 {
6082 /* When size > 16 bytes, if the first one isn't
6083 X86_64_SSE_CLASS or any other ones aren't
6084 X86_64_SSEUP_CLASS, everything should be passed in
6085 memory. */
6092 }
6094 /* Final merger cleanup. */
6096 {
6097 /* If one class is MEMORY, everything should be passed in
6098 memory. */
6102 /* The X86_64_SSEUP_CLASS should be always preceded by
6103 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6107 {
6108 /* The first one should never be X86_64_SSEUP_CLASS. */
6111 }
6113 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6114 everything should be passed in memory. */
6117 {
6120 /* The first one should never be X86_64_X87UP_CLASS. */
6123 {
6126 "the ABI of passing union with long double"
6128 }
6130 }
6131 }
6133 }
6135 /* Compute alignment needed. We align all types to natural boundaries with
6136 exception of XFmode that is aligned to 64bits. */
6138 {
6147 /* Misaligned fields are always returned in memory. */
6150 }
6152 /* for V1xx modes, just use the base mode */
6157 /* Classification of atomic types. */
6159 {
6175 {
6179 {
6182 }
6184 {
6187 }
6189 {
6193 }
6195 {
6198 }
6199 else
6201 }
6208 /* OImode shouldn't be used directly. */
6215 else
6233 else
6234 {
6238 {
6241 "the ABI of passing structure with complex float"
6243 }
6246 }
6255 /* This modes is larger than 16 bytes. */
6298 else
6302 }
6303 }
6305 /* Examine the argument and return set number of register required in each
6306 class. Return 0 iff parameter should be passed in memory. */
6307 static int
6310 {
6320 {
6342 }
6344 }
6346 /* Construct container for the argument used by GCC interface. See
6347 FUNCTION_ARG for the detailed description. */
6349 static rtx
6353 {
6354 /* The following variables hold the static issued_error state. */
6368 rtx ret;
6379 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6380 some less clueful developer tries to use floating-point anyway. */
6382 {
6384 {
6386 {
6389 }
6390 }
6392 {
6395 }
6397 }
6399 /* Likewise, error if the ABI requires us to return values in the
6400 x87 registers and the user specified -mno-80387. */
6406 {
6408 {
6411 }
6413 }
6415 /* First construct simple cases. Avoid SCmode, since we want to use
6416 single register to pass this type. */
6419 {
6434 /* Zero sized array, struct or class. */
6438 }
6465 /* Otherwise figure out the entries of the PARALLEL. */
6467 {
6471 {
6476 /* Merge TImodes on aligned occasions here too. */
6478 tmpmode
6482 else
6484 /* We've requested 24 bytes we
6485 don't have mode for. Use DImode. */
6492 intreg++;
6500 sse_regno++;
6508 sse_regno++;
6513 {
6519 {
6521 i++;
6522 }
6523 else
6536 }
6542 sse_regno++;
6546 }
6547 }
6549 /* Empty aligned struct, union or class. */
6557 }
6559 /* Update the data in CUM to advance over an argument of mode MODE
6560 and data type TYPE. (TYPE is null for libcalls where that information
6561 may not be available.) */
6563 static void
6566 HOST_WIDE_INT words)
6567 {
6569 {
6576 /* FALLTHRU */
6587 {
6590 }
6594 /* OImode shouldn't be used directly. */
6603 /* FALLTHRU */
6619 {
6624 {
6627 }
6628 }
6638 {
6643 {
6646 }
6647 }
6649 }
6650 }
6652 static void
6655 {
6658 /* Unnamed 256bit vector mode parameters are passed on stack. */
6664 {
6669 }
6670 else
6671 {
6675 }
6676 }
6678 static void
6680 HOST_WIDE_INT words)
6681 {
6682 /* Otherwise, this should be passed indirect. */
6687 {
6690 }
6691 }
6693 /* Update the data in CUM to advance over an argument of mode MODE and
6694 data type TYPE. (TYPE is null for libcalls where that information
6695 may not be available.) */
6697 static void
6700 {
6706 else
6717 else
6719 }
6721 /* Define where to put the arguments to a function.
6722 Value is zero to push the argument on the stack,
6723 or a hard register in which to store the argument.
6725 MODE is the argument's machine mode.
6726 TYPE is the data type of the argument (as a tree).
6727 This is null for libcalls where that information may
6728 not be available.
6729 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6730 the preceding args and about the function being called.
6731 NAMED is nonzero if this argument is a named parameter
6732 (otherwise it is an extra parameter matching an ellipsis). */
6734 static rtx
6738 {
6741 /* Avoid the AL settings for the Unix64 ABI. */
6746 {
6753 /* FALLTHRU */
6759 {
6762 /* Fastcall allocates the first two DWORD (SImode) or
6763 smaller arguments to ECX and EDX if it isn't an
6764 aggregate type . */
6766 {
6772 /* ECX not EAX is the first allocated register. */
6775 }
6777 }
6786 /* FALLTHRU */
6788 /* In 32bit, we pass TImode in xmm registers. */
6796 {
6798 {
6802 }
6806 }
6810 /* OImode shouldn't be used directly. */
6820 {
6824 }
6834 {
6836 {
6840 }
6844 }
6846 }
6849 }
6851 static rtx
6854 {
6855 /* Handle a hidden AL argument containing number of registers
6856 for varargs x86-64 functions. */
6860 ? X86_64_SSE_REGPARM_MAX
6865 {
6875 /* Unnamed 256bit vector mode parameters are passed on stack. */
6879 }
6885 }
6887 static rtx
6890 HOST_WIDE_INT bytes)
6891 {
6894 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6895 We use value of -2 to specify that current function call is MSABI. */
6899 /* If we've run out of registers, it goes on the stack. */
6905 /* Only floating point modes are passed in anything but integer regs. */
6907 {
6910 else
6911 {
6914 /* Unnamed floating parameters are passed in both the
6915 SSE and integer registers. */
6921 }
6922 }
6923 /* Handle aggregated types passed in register. */
6925 {
6930 }
6933 }
6935 /* Return where to put the arguments to a function.
6936 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6938 MODE is the argument's machine mode. TYPE is the data type of the
6939 argument. It is null for libcalls where that information may not be
6940 available. CUM gives information about the preceding args and about
6941 the function being called. NAMED is nonzero if this argument is a
6942 named parameter (otherwise it is an extra parameter matching an
6943 ellipsis). */
6945 static rtx
6948 {
6952 rtx arg;
6956 else
6960 /* To simplify the code below, represent vector types with a vector mode
6961 even if MMX/SSE are not active. */
6969 else
6973 }
6975 /* A C expression that indicates when an argument must be passed by
6976 reference. If nonzero for an argument, a copy of that argument is
6977 made in memory and a pointer to the argument is passed instead of
6978 the argument itself. The pointer is passed in whatever way is
6979 appropriate for passing a pointer to that type. */
6981 static bool
6985 {
6988 /* See Windows x64 Software Convention. */
6990 {
6993 {
6994 /* Arrays are passed by reference. */
6999 {
7000 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7001 are passed by reference. */
7003 }
7004 }
7006 /* __m128 is passed by reference. */
7012 }
7013 }
7018 }
7020 /* Return true when TYPE should be 128bit aligned for 32bit argument
7021 passing ABI. XXX: This function is obsolete and is only used for
7022 checking psABI compatibility with previous versions of GCC. */
7024 static bool
7026 {
7038 {
7039 /* Walk the aggregates recursively. */
7041 {
7045 {
7046 tree field;
7048 /* Walk all the structure fields. */
7050 {
7054 }
7056 }
7059 /* Just for use if some languages passes arrays by value. */
7066 }
7067 }
7069 }
7071 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7072 XXX: This function is obsolete and is only used for checking psABI
7073 compatibility with previous versions of GCC. */
7075 static unsigned int
7078 {
7079 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7080 natural boundaries. */
7082 {
7083 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7084 make an exception for SSE modes since these require 128bit
7085 alignment.
7087 The handling here differs from field_alignment. ICC aligns MMX
7088 arguments to 4 byte boundaries, while structure fields are aligned
7089 to 8 byte boundaries. */
7091 {
7094 }
7095 else
7096 {
7099 }
7100 }
7104 }
7106 /* Return true when TYPE should be 128bit aligned for 32bit argument
7107 passing ABI. */
7109 static bool
7111 {
7121 {
7122 /* Walk the aggregates recursively. */
7124 {
7128 {
7129 tree field;
7131 /* Walk all the structure fields. */
7133 field;
7135 {
7139 }
7141 }
7144 /* Just for use if some languages passes arrays by value. */
7151 }
7152 }
7153 else
7157 }
7159 /* Gives the alignment boundary, in bits, of an argument with the
7160 specified mode and type. */
7162 static unsigned int
7164 {
7167 {
7168 /* Since the main variant type is used for call, we convert it to
7169 the main variant type. */
7172 }
7173 else
7177 else
7178 {
7183 {
7184 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7186 {
7189 }
7195 }
7198 && !warned
7200 saved_align))
7201 {
7204 "The ABI for passing parameters with %d-byte"
7207 }
7208 }
7211 }
7213 /* Return true if N is a possible register number of function value. */
7215 static bool
7217 {
7219 {
7224 /* TODO: The function should depend on current function ABI but
7225 builtins.c would need updating then. Therefore we use the
7226 default ABI. */
7238 }
7241 }
7243 /* Define how to find the value returned by a function.
7244 VALTYPE is the data type of the value (as a tree).
7245 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7246 otherwise, FUNC is 0. */
7248 static rtx
7251 {
7254 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7255 we normally prevent this case when mmx is not available. However
7256 some ABIs may require the result to be returned like DImode. */
7260 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7261 we prevent this case when sse is not available. However some ABIs
7262 may require the result to be returned like integer TImode. */
7267 /* 32-byte vector modes in %ymm0. */
7271 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7274 else
7275 /* Most things go in %eax. */
7278 /* Override FP return register with %xmm0 for local functions when
7279 SSE math is enabled or for functions with sseregparm attribute. */
7281 {
7286 }
7288 /* OImode shouldn't be used directly. */
7292 }
7294 static rtx
7296 const_tree valtype)
7297 {
7298 rtx ret;
7300 /* Handle libcalls, which don't provide a type node. */
7302 {
7306 {
7325 }
7328 }
7331 {
7332 /* Pointers are always returned in word_mode. */
7334 }
7340 /* For zero sized structures, construct_container returns NULL, but we
7341 need to keep rest of compiler happy by returning meaningful value. */
7346 }
7348 static rtx
7350 {
7354 {
7356 {
7369 }
7370 }
7372 }
7374 static rtx
7377 {
7389 else
7391 }
7393 static rtx
7396 {
7402 }
7404 /* Pointer function arguments and return values are promoted to
7405 word_mode. */
7407 static enum machine_mode
7411 {
7413 {
7415 {
7418 }
7421 }
7423 for_return);
7424 }
7426 /* Return true if a structure, union or array with MODE containing FIELD
7427 should be accessed using BLKmode. */
7429 static bool
7431 {
7432 /* Union with XFmode must be in BLKmode. */
7436 }
7438 rtx
7440 {
7442 }
7444 /* Return true iff type is returned in memory. */
7446 static bool ATTRIBUTE_UNUSED
7448 {
7449 HOST_WIDE_INT size;
7460 {
7461 /* User-created vectors small enough to fit in EAX. */
7465 /* MMX/3dNow values are returned in MM0,
7466 except when it doesn't exits or the ABI prescribes otherwise. */
7470 /* SSE values are returned in XMM0, except when it doesn't exist. */
7474 /* AVX values are returned in YMM0, except when it doesn't exist. */
7477 }
7485 /* OImode shouldn't be used directly. */
7489 }
7491 static bool ATTRIBUTE_UNUSED
7493 {
7496 }
7498 static bool ATTRIBUTE_UNUSED
7500 {
7503 /* __m128 is returned in xmm0. */
7508 /* Otherwise, the size must be exactly in [1248]. */
7510 }
7512 static bool
7514 {
7515 #ifdef SUBTARGET_RETURN_IN_MEMORY
7517 #else
7521 {
7524 else
7526 }
7527 else
7529 #endif
7530 }
7532 /* When returning SSE vector types, we have a choice of either
7533 (1) being abi incompatible with a -march switch, or
7534 (2) generating an error.
7535 Given no good solution, I think the safest thing is one warning.
7536 The user won't be able to use -Werror, but....
7538 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7539 called in response to actually generating a caller or callee that
7540 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7541 via aggregate_value_p for general type probing from tree-ssa. */
7543 static rtx
7545 {
7549 {
7550 /* Look at the return type of the function, not the function type. */
7554 {
7557 {
7561 }
7562 }
7565 {
7567 {
7571 }
7572 }
7573 }
7576 }
7578 \f
7579 /* Create the va_list data type. */
7581 /* Returns the calling convention specific va_list date type.
7582 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7584 static tree
7586 {
7589 /* For i386 we use plain pointer to argument area. */
7599 unsigned_type_node);
7602 unsigned_type_node);
7605 ptr_type_node);
7608 ptr_type_node);
7627 /* The correct type is an array type of one element. */
7629 }
7631 /* Setup the builtin va_list data type and for 64-bit the additional
7632 calling convention specific va_list data types. */
7634 static tree
7636 {
7639 /* Initialize abi specific va_list builtin types. */
7641 {
7642 tree t;
7644 {
7649 }
7650 else
7651 {
7656 }
7658 {
7663 }
7664 else
7665 {
7670 }
7671 }
7674 }
7676 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7678 static void
7680 {
7682 alias_set_type set;
7685 /* GPR size of varargs save area. */
7688 else
7691 /* FPR size of varargs save area. We don't need it if we don't pass
7692 anything in SSE registers. */
7695 else
7709 {
7717 }
7720 {
7724 /* Now emit code to save SSE registers. The AX parameter contains number
7725 of SSE parameter registers used to call this function, though all we
7726 actually check here is the zero/non-zero status. */
7731 label));
7733 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7734 we used movdqa (i.e. TImode) instead? Perhaps even better would
7735 be if we could determine the real mode of the data, via a hook
7736 into pass_stdarg. Ignore all that for now. */
7746 {
7755 }
7758 }
7759 }
7761 static void
7763 {
7767 /* Reset to zero, as there might be a sysv vaarg used
7768 before. */
7773 {
7784 }
7785 }
7787 static void
7791 {
7793 CUMULATIVE_ARGS next_cum;
7794 tree fntype;
7796 /* This argument doesn't appear to be used anymore. Which is good,
7797 because the old code here didn't suppress rtl generation. */
7805 /* For varargs, we do not want to skip the dummy va_dcl argument.
7806 For stdargs, we do want to skip the last named argument. */
7814 else
7816 }
7818 /* Checks if TYPE is of kind va_list char *. */
7820 static bool
7822 {
7823 tree canonic;
7825 /* For 32-bit it is always true. */
7831 }
7833 /* Implement va_start. */
7835 static void
7837 {
7841 tree type;
7842 rtx ovf_rtx;
7846 {
7849 /* When we are splitting the stack, we can't refer to the stack
7850 arguments using internal_arg_pointer, because they may be on
7851 the old stack. The split stack prologue will arrange to
7852 leave a pointer to the old stack arguments in a scratch
7853 register, which we here copy to a pseudo-register. The split
7854 stack prologue can't set the pseudo-register directly because
7855 it (the prologue) runs before any registers have been saved. */
7859 {
7873 }
7874 }
7876 /* Only 64bit target needs something special. */
7878 {
7881 else
7882 {
7891 }
7893 }
7902 /* The following should be folded into the MEM_REF offset. */
7912 /* Count number of gp and fp argument registers used. */
7918 {
7924 }
7927 {
7933 }
7935 /* Find the overflow area. */
7939 else
7949 {
7950 /* Find the register save area.
7951 Prologue of the function save it right above stack frame. */
7959 }
7960 }
7962 /* Implement va_arg. */
7964 static tree
7967 {
7974 rtx container;
7976 tree ptrtype;
7980 /* Only 64bit target needs something special. */
8004 {
8011 /* Unnamed 256bit vector mode parameters are passed on stack. */
8013 {
8016 }
8024 }
8026 /* Pull the value out of the saved registers. */
8031 {
8045 /* In case we are passing structure, verify that it is consecutive block
8046 on the register save area. If not we need to do moves. */
8048 {
8049 /* Verify that all registers are strictly consecutive */
8051 {
8055 {
8060 }
8061 }
8062 else
8063 {
8067 {
8072 }
8073 }
8074 }
8076 {
8079 }
8080 else
8081 {
8084 }
8086 /* First ensure that we fit completely in registers. */
8088 {
8095 }
8097 {
8105 }
8107 /* Compute index to start of area used for integer regs. */
8109 {
8110 /* int_addr = gpr + sav; */
8113 }
8115 {
8116 /* sse_addr = fpr + sav; */
8119 }
8121 {
8125 /* addr = &temp; */
8130 {
8134 tree piece_type;
8135 tree addr_type;
8136 tree daddr_type;
8145 {
8150 }
8154 else
8161 {
8164 }
8165 else
8166 {
8169 }
8176 {
8181 }
8182 else
8183 {
8184 tree copy
8189 }
8191 }
8192 }
8195 {
8199 }
8202 {
8206 }
8211 }
8213 /* ... otherwise out of the overflow area. */
8215 /* When we align parameter on stack for caller, if the parameter
8216 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8217 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8218 here with caller. */
8223 /* Care for on-stack alignment if needed. */
8226 else
8227 {
8232 }
8249 }
8250 \f
8251 /* Return true if OPNUM's MEM should be matched
8252 in movabs* patterns. */
8254 bool
8256 {
8268 }
8269 \f
8270 /* Initialize the table of extra 80387 mathematical constants. */
8272 static void
8274 {
8276 {
8282 };
8286 {
8288 /* Ensure each constant is rounded to XFmode precision. */
8291 }
8294 }
8296 /* Return non-zero if the constant is something that
8297 can be loaded with a special instruction. */
8299 int
8301 {
8304 REAL_VALUE_TYPE r;
8316 /* For XFmode constants, try to find a special 80387 instruction when
8317 optimizing for size or on those CPUs that benefit from them. */
8320 {
8329 }
8331 /* Load of the constant -0.0 or -1.0 will be split as
8332 fldz;fchs or fld1;fchs sequence. */
8339 }
8341 /* Return the opcode of the special instruction to be used to load
8342 the constant X. */
8346 {
8348 {
8368 }
8369 }
8371 /* Return the CONST_DOUBLE representing the 80387 constant that is
8372 loaded by the specified special instruction. The argument IDX
8373 matches the return value from standard_80387_constant_p. */
8375 rtx
8377 {
8384 {
8395 }
8398 XFmode);
8399 }
8401 /* Return 1 if X is all 0s and 2 if x is all 1s
8402 in supported SSE/AVX vector mode. */
8404 int
8406 {
8413 {
8428 }
8431 }
8433 /* Return the opcode of the special instruction to be used to load
8434 the constant X. */
8438 {
8440 {
8443 {
8460 }
8465 else
8470 }
8472 }
8474 /* Returns true if OP contains a symbol reference */
8476 bool
8478 {
8487 {
8489 {
8495 }
8499 }
8502 }
8504 /* Return true if it is appropriate to emit `ret' instructions in the
8505 body of a function. Do this only if the epilogue is simple, needing a
8506 couple of insns. Prior to reloading, we can't tell how many registers
8507 must be saved, so return false then. Return false if there is no frame
8508 marker to de-allocate. */
8510 bool
8512 {
8518 /* Don't allow more than 32k pop, since that's all we can do
8519 with one instruction. */
8526 }
8527 \f
8528 /* Value should be nonzero if functions must have frame pointers.
8529 Zero means the frame pointer need not be set up (and parms may
8530 be accessed via the stack pointer) in functions that seem suitable. */
8532 static bool
8534 {
8535 /* If we accessed previous frames, then the generated code expects
8536 to be able to access the saved ebp value in our frame. */
8540 /* Several x86 os'es need a frame pointer for other reasons,
8541 usually pertaining to setjmp. */
8545 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8549 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8550 allocation is 4GB. */
8554 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8555 turns off the frame pointer by default. Turn it back on now if
8556 we've not got a leaf function. */
8566 }
8568 /* Record that the current function accesses previous call frames. */
8570 void
8572 {
8574 }
8575 \f
8576 #ifndef USE_HIDDEN_LINKONCE
8577 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8578 # define USE_HIDDEN_LINKONCE 1
8579 # else
8580 # define USE_HIDDEN_LINKONCE 0
8581 # endif
8582 #endif
8586 /* Fills in the label name that should be used for a pc thunk for
8587 the given register. */
8589 static void
8591 {
8596 else
8598 }
8601 /* This function generates code for -fpic that loads %ebx with
8602 the return address of the caller and then returns. */
8604 static void
8606 {
8611 {
8613 tree decl;
8629 #if TARGET_MACHO
8631 {
8640 }
8641 else
8642 #endif
8644 {
8655 }
8656 else
8657 {
8660 }
8666 /* Make sure unwind info is emitted for the thunk if needed. */
8669 /* Pad stack IP move with 4 instructions (two NOPs count
8670 as one instruction). */
8672 {
8677 }
8688 }
8692 }
8694 /* Emit code for the SET_GOT patterns. */
8698 {
8704 {
8705 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8710 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8711 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8712 an unadorned address. */
8717 }
8722 {
8727 #if TARGET_MACHO
8728 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8729 is what will be referenced by the Mach-O PIC subsystem. */
8732 #endif
8736 }
8737 else
8738 {
8746 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8747 is what will be referenced by the Mach-O PIC subsystem. */
8748 #if TARGET_MACHO
8751 else
8754 #endif
8755 }
8761 }
8763 /* Generate an "push" pattern for input ARG. */
8765 static rtx
8767 {
8780 stack_pointer_rtx)),
8781 arg);
8782 }
8784 /* Generate an "pop" pattern for input ARG. */
8786 static rtx
8788 {
8793 arg,
8796 stack_pointer_rtx)));
8797 }
8799 /* Return >= 0 if there is an unused call-clobbered register available
8800 for the entire function. */
8802 static unsigned int
8804 {
8808 {
8810 /* Can't use the same register for both PIC and DRAP. */
8813 else
8818 }
8821 }
8823 /* Return TRUE if we need to save REGNO. */
8825 static bool
8827 {
8837 {
8840 {
8846 }
8847 }
8856 }
8858 /* Return number of saved general prupose registers. */
8860 static int
8862 {
8868 nregs ++;
8870 }
8872 /* Return number of saved SSE registrers. */
8874 static int
8876 {
8884 nregs ++;
8886 }
8888 /* Given FROM and TO register numbers, say whether this elimination is
8889 allowed. If stack alignment is needed, we can only replace argument
8890 pointer with hard frame pointer, or replace frame pointer with stack
8891 pointer. Otherwise, frame pointer elimination is automatically
8892 handled and all other eliminations are valid. */
8894 static bool
8896 {
8902 else
8904 }
8906 /* Return the offset between two registers, one to be eliminated, and the other
8907 its replacement, at the start of a routine. */
8909 HOST_WIDE_INT
8911 {
8920 else
8921 {
8929 }
8930 }
8932 /* In a dynamically-aligned function, we can't know the offset from
8933 stack pointer to frame pointer, so we must ensure that setjmp
8934 eliminates fp against the hard fp (%ebp) rather than trying to
8935 index from %esp up to the top of the frame across a gap that is
8936 of unknown (at compile-time) size. */
8937 static rtx
8939 {
8941 }
8943 /* When using -fsplit-stack, the allocation routines set a field in
8944 the TCB to the bottom of the stack plus this much space, measured
8945 in bytes. */
8947 #define SPLIT_STACK_AVAILABLE 256
8949 /* Fill structure ix86_frame about frame of currently computed function. */
8951 static void
8953 {
8955 HOST_WIDE_INT offset;
8958 HOST_WIDE_INT to_allocate;
8966 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8967 function prologues and leaf. */
8971 {
8976 }
8982 /* For SEH we have to limit the amount of code movement into the prologue.
8983 At present we do this via a BLOCKAGE, at which point there's very little
8984 scheduling that can be done, which means that there's very little point
8985 in doing anything except PUSHs. */
8989 /* During reload iteration the amount of registers saved can change.
8990 Recompute the value as needed. Do not recompute when amount of registers
8991 didn't change as reload does multiple calls to the function and does not
8992 expect the decision to change within single iteration. */
8995 {
9001 /* The fast prologue uses move instead of push to save registers. This
9002 is significantly longer, but also executes faster as modern hardware
9003 can execute the moves in parallel, but can't do that for push/pop.
9005 Be careful about choosing what prologue to emit: When function takes
9006 many instructions to execute we may use slow version as well as in
9007 case function is known to be outside hot spot (this is known with
9008 feedback only). Weight the size of function by number of registers
9009 to save as it is cheap to use one or two push instructions but very
9010 slow to use many of them. */
9014 || (flag_branch_probabilities
9017 else
9020 }
9022 frame->save_regs_using_mov
9024 /* If static stack checking is enabled and done with probes,
9025 the registers need to be saved before allocating the frame. */
9028 /* Skip return address. */
9031 /* Skip pushed static chain. */
9035 /* Skip saved base pointer. */
9040 /* The traditional frame pointer location is at the top of the frame. */
9043 /* Register save area */
9047 /* On SEH target, registers are pushed just before the frame pointer
9048 location. */
9052 /* Align and set SSE register save area. */
9054 {
9055 /* The only ABI that has saved SSE registers (Win64) also has a
9056 16-byte aligned default stack, and thus we don't need to be
9057 within the re-aligned local stack frame to save them. */
9061 }
9064 /* The re-aligned stack starts here. Values before this point are not
9065 directly comparable with values below this point. In order to make
9066 sure that no value happens to be the same before and after, force
9067 the alignment computation below to add a non-zero value. */
9071 /* Va-arg area */
9075 /* Align start of frame for local function. */
9084 /* Frame pointer points here. */
9089 /* Add outgoing arguments area. Can be skipped if we eliminated
9090 all the function calls as dead code.
9091 Skipping is however impossible when function calls alloca. Alloca
9092 expander assumes that last crtl->outgoing_args_size
9093 of stack frame are unused. */
9097 {
9100 }
9101 else
9104 /* Align stack boundary. Only needed if we're calling another function
9105 or using alloca. */
9110 /* We've reached end of stack frame. */
9113 /* Size prologue needs to allocate. */
9124 {
9130 }
9131 else
9135 /* The SEH frame pointer location is near the bottom of the frame.
9136 This is enforced by the fact that the difference between the
9137 stack pointer and the frame pointer is limited to 240 bytes in
9138 the unwind data structure. */
9140 {
9141 HOST_WIDE_INT diff;
9143 /* If we can leave the frame pointer where it is, do so. Also, returns
9144 the establisher frame for __builtin_frame_address (0). */
9149 {
9150 /* Ideally we'd determine what portion of the local stack frame
9151 (within the constraint of the lowest 240) is most heavily used.
9152 But without that complication, simply bias the frame pointer
9153 by 128 bytes so as to maximize the amount of the local stack
9154 frame that is addressable with 8-bit offsets. */
9156 }
9157 }
9158 }
9160 /* This is semi-inlined memory_address_length, but simplified
9161 since we know that we're always dealing with reg+offset, and
9162 to avoid having to create and discard all that rtl. */
9166 {
9170 {
9171 /* EBP and R13 cannot be encoded without an offset. */
9173 }
9177 /* ESP and R12 must be encoded with a SIB byte. */
9179 len++;
9182 }
9184 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9185 The valid base registers are taken from CFUN->MACHINE->FS. */
9187 static rtx
9189 {
9195 {
9196 /* Choose the base register most likely to allow the most scheduling
9197 opportunities. Generally FP is valid throughout the function,
9198 while DRAP must be reloaded within the epilogue. But choose either
9199 over the SP due to increased encoding size. */
9202 {
9205 }
9207 {
9210 }
9212 {
9215 }
9216 }
9217 else
9218 {
9219 HOST_WIDE_INT toffset;
9222 /* Choose the base register with the smallest address encoding.
9223 With a tie, choose FP > DRAP > SP. */
9225 {
9229 }
9231 {
9235 {
9239 }
9240 }
9242 {
9246 {
9250 }
9251 }
9252 }
9256 }
9258 /* Emit code to save registers in the prologue. */
9260 static void
9262 {
9264 rtx insn;
9268 {
9271 }
9272 }
9274 /* Emit a single register save at CFA - CFA_OFFSET. */
9276 static void
9278 HOST_WIDE_INT cfa_offset)
9279 {
9287 /* For SSE saves, we need to indicate the 128-bit alignment. */
9298 /* When saving registers into a re-aligned local stack frame, avoid
9299 any tricky guessing by dwarf2out. */
9301 {
9305 {
9306 /* A bit of a hack. We force the DRAP register to be saved in
9307 the re-aligned stack frame, which provides us with a copy
9308 of the CFA that will last past the prologue. Install it. */
9314 }
9315 else
9316 {
9317 /* The frame pointer is a stable reference within the
9318 aligned frame. Use it. */
9325 }
9326 }
9328 /* The memory may not be relative to the current CFA register,
9329 which means that we may need to generate a new pattern for
9330 use by the unwind info. */
9332 {
9337 }
9338 }
9340 /* Emit code to save registers using MOV insns.
9341 First register is stored at CFA - CFA_OFFSET. */
9342 static void
9344 {
9349 {
9352 }
9353 }
9355 /* Emit code to save SSE registers using MOV insns.
9356 First register is stored at CFA - CFA_OFFSET. */
9357 static void
9359 {
9364 {
9367 }
9368 }
9372 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9373 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9374 Don't add the note if the previously saved value will be left untouched
9375 within stack red-zone till return, as unwinders can find the same value
9376 in the register and on the stack. */
9378 static void
9380 {
9386 {
9389 }
9390 else
9391 queued_cfa_restores
9393 }
9395 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9397 static void
9399 {
9400 rtx last;
9404 ;
9409 }
9411 /* Expand prologue or epilogue stack adjustment.
9412 The pattern exist to put a dependency on all ebp-based memory accesses.
9413 STYLE should be negative if instructions should be marked as frame related,
9414 zero if %r11 register is live and cannot be freely used and positive
9415 otherwise. */
9417 static void
9420 {
9422 rtx insn;
9429 else
9430 {
9431 rtx tmp;
9432 /* r11 is used by indirect sibcall return as well, set before the
9433 epilogue and used after the epilogue. */
9436 else
9437 {
9441 }
9447 }
9454 {
9455 rtx r;
9465 }
9467 {
9470 {
9474 }
9475 }
9478 {
9483 {
9486 }
9488 {
9491 }
9492 else
9493 {
9494 /* Else there are two possibilities: SP itself, which we set
9495 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9496 taken care of this by hand along the eh_return path. */
9499 }
9503 }
9504 }
9506 /* Find an available register to be used as dynamic realign argument
9507 pointer regsiter. Such a register will be written in prologue and
9508 used in begin of body, so it must not be
9509 1. parameter passing register.
9510 2. GOT pointer.
9511 We reuse static-chain register if it is available. Otherwise, we
9512 use DI for i386 and R13 for x86-64. We chose R13 since it has
9513 shorter encoding.
9515 Return: the regno of chosen register. */
9517 static unsigned int
9519 {
9523 {
9524 /* Use R13 for nested function or function need static chain.
9525 Since function with tail call may use any caller-saved
9526 registers in epilogue, DRAP must not use caller-saved
9527 register in such case. */
9532 }
9533 else
9534 {
9535 /* Use DI for nested function or function need static chain.
9536 Since function with tail call may use any caller-saved
9537 registers in epilogue, DRAP must not use caller-saved
9538 register in such case. */
9542 /* Reuse static chain register if it isn't used for parameter
9543 passing. */
9545 {
9549 }
9551 }
9552 }
9554 /* Return minimum incoming stack alignment. */
9556 static unsigned int
9558 {
9561 /* Prefer the one specified at command line. */
9564 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9565 if -mstackrealign is used, it isn't used for sibcall check and
9566 estimated stack alignment is 128bit. */
9568 && !TARGET_64BIT
9569 && ix86_force_align_arg_pointer
9572 else
9575 /* Incoming stack alignment can be changed on individual functions
9576 via force_align_arg_pointer attribute. We use the smallest
9577 incoming stack boundary. */
9583 /* The incoming stack frame has to be aligned at least at
9584 parm_stack_boundary. */
9588 /* Stack at entrance of main is aligned by runtime. We use the
9589 smallest incoming stack boundary. */
9597 }
9599 /* Update incoming stack boundary and estimated stack alignment. */
9601 static void
9603 {
9604 ix86_incoming_stack_boundary
9607 /* x86_64 vararg needs 16byte stack alignment for register save
9608 area. */
9613 }
9615 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9616 needed or an rtx for DRAP otherwise. */
9618 static rtx
9620 {
9625 {
9626 /* Assign DRAP to vDRAP and returns vDRAP */
9628 rtx drap_vreg;
9629 rtx arg_ptr;
9642 {
9645 }
9647 }
9648 else
9650 }
9652 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9654 static rtx
9656 {
9658 }
9661 rtx reg;
9663 };
9665 /* Return a short-lived scratch register for use on function entry.
9666 In 32-bit mode, it is valid only after the registers are saved
9667 in the prologue. This register must be released by means of
9668 release_scratch_register_on_entry once it is dead. */
9670 static void
9672 {
9678 {
9679 /* We always use R11 in 64-bit mode. */
9681 }
9682 else
9683 {
9685 bool fastcall_p
9687 bool thiscall_p
9691 int drap_regno
9694 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9695 for the static chain register. */
9699 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9700 for the static chain register. */
9705 /* ecx is the static chain register. */
9707 && !static_chain_p
9712 /* esi is the static chain register. */
9718 else
9719 {
9722 }
9723 }
9727 {
9730 }
9731 }
9733 /* Release a scratch register obtained from the preceding function. */
9735 static void
9737 {
9739 {
9743 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9749 }
9750 }
9752 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9754 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9756 static void
9758 {
9759 /* We skip the probe for the first interval + a small dope of 4 words and
9760 probe that many bytes past the specified size to maintain a protection
9761 area at the botton of the stack. */
9765 /* See if we have a constant small number of probes to generate. If so,
9766 that's the easy case. The run-time loop is made up of 11 insns in the
9767 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9768 for n # of intervals. */
9770 {
9774 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9775 values of N from 1 until it exceeds SIZE. If only one probe is
9776 needed, this will not generate any code. Then adjust and probe
9777 to PROBE_INTERVAL + SIZE. */
9779 {
9781 {
9784 }
9785 else
9792 }
9796 else
9804 /* Adjust back to account for the additional first interval. */
9808 }
9810 /* Otherwise, do the same as above, but in a loop. Note that we must be
9811 extra careful with variables wrapping around because we might be at
9812 the very top (or the very bottom) of the address space and we have
9813 to be able to handle this case properly; in particular, we use an
9814 equality test for the loop condition. */
9815 else
9816 {
9817 HOST_WIDE_INT rounded_size;
9823 /* Step 1: round SIZE to the previous multiple of the interval. */
9828 /* Step 2: compute initial and final value of the loop counter. */
9830 /* SP = SP_0 + PROBE_INTERVAL. */
9835 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9839 stack_pointer_rtx)));
9842 /* Step 3: the loop
9844 while (SP != LAST_ADDR)
9845 {
9846 SP = SP + PROBE_INTERVAL
9847 probe at SP
9848 }
9850 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9851 values of N from 1 until it is equal to ROUNDED_SIZE. */
9856 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9857 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9860 {
9865 }
9867 /* Adjust back to account for the additional first interval. */
9873 }
9877 /* Even if the stack pointer isn't the CFA register, we need to correctly
9878 describe the adjustments made to it, in particular differentiate the
9879 frame-related ones from the frame-unrelated ones. */
9881 {
9894 }
9896 /* Make sure nothing is scheduled before we are done. */
9898 }
9900 /* Adjust the stack pointer up to REG while probing it. */
9904 {
9914 /* Jump to END_LAB if SP == LAST_ADDR. */
9922 /* SP = SP + PROBE_INTERVAL. */
9926 /* Probe at SP. */
9937 }
9939 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9940 inclusive. These are offsets from the current stack pointer. */
9942 static void
9944 {
9945 /* See if we have a constant small number of probes to generate. If so,
9946 that's the easy case. The run-time loop is made up of 7 insns in the
9947 generic case while the compile-time loop is made up of n insns for n #
9948 of intervals. */
9950 {
9951 HOST_WIDE_INT i;
9953 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9954 it exceeds SIZE. If only one probe is needed, this will not
9955 generate any code. Then probe at FIRST + SIZE. */
9962 }
9964 /* Otherwise, do the same as above, but in a loop. Note that we must be
9965 extra careful with variables wrapping around because we might be at
9966 the very top (or the very bottom) of the address space and we have
9967 to be able to handle this case properly; in particular, we use an
9968 equality test for the loop condition. */
9969 else
9970 {
9977 /* Step 1: round SIZE to the previous multiple of the interval. */
9982 /* Step 2: compute initial and final value of the loop counter. */
9984 /* TEST_OFFSET = FIRST. */
9987 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
9991 /* Step 3: the loop
9993 while (TEST_ADDR != LAST_ADDR)
9994 {
9995 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
9996 probe at TEST_ADDR
9997 }
9999 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10000 until it is equal to ROUNDED_SIZE. */
10005 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10006 that SIZE is equal to ROUNDED_SIZE. */
10011 stack_pointer_rtx,
10016 }
10018 /* Make sure nothing is scheduled before we are done. */
10020 }
10022 /* Probe a range of stack addresses from REG to END, inclusive. These are
10023 offsets from the current stack pointer. */
10027 {
10037 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10045 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10049 /* Probe at TEST_ADDR. */
10062 }
10064 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10065 to be generated in correct form. */
10066 static void
10068 {
10069 /* Check if stack realign is really needed after reload, and
10070 stores result in cfun */
10071 unsigned int incoming_stack_boundary
10080 {
10081 /* After stack_realign_needed is finalized, we can't no longer
10082 change it. */
10085 }
10087 /* If the only reason for frame_pointer_needed is that we conservatively
10088 assumed stack realignment might be needed, but in the end nothing that
10089 needed the stack alignment had been spilled, clear frame_pointer_needed
10090 and say we don't need stack realignment. */
10093 && frame_pointer_needed
10095 && flag_omit_frame_pointer
10097 && !ix86_current_function_calls_tls_descriptor
10106 {
10108 basic_block bb;
10115 HARD_FRAME_POINTER_REGNUM);
10117 {
10118 rtx insn;
10122 set_up_by_prologue))
10123 {
10127 }
10128 }
10142 }
10146 }
10148 /* Expand the prologue into a bunch of separate insns. */
10150 void
10152 {
10157 HOST_WIDE_INT allocate;
10163 /* DRAP should not coexist with stack_realign_fp */
10168 /* Initialize CFA state for before the prologue. */
10172 /* Track SP offset to the CFA. We continue tracking this after we've
10173 swapped the CFA register away from SP. In the case of re-alignment
10174 this is fudged; we're interested to offsets within the local frame. */
10181 {
10182 /* We should have already generated an error for any use of
10183 ms_hook on a nested function. */
10186 /* Check if profiling is active and we shall use profiling before
10187 prologue variant. If so sorry. */
10192 /* In ix86_asm_output_function_label we emitted:
10193 8b ff movl.s %edi,%edi
10194 55 push %ebp
10195 8b ec movl.s %esp,%ebp
10197 This matches the hookable function prologue in Win32 API
10198 functions in Microsoft Windows XP Service Pack 2 and newer.
10199 Wine uses this to enable Windows apps to hook the Win32 API
10200 functions provided by Wine.
10202 What that means is that we've already set up the frame pointer. */
10206 {
10209 /* We've decided to use the frame pointer already set up.
10210 Describe this to the unwinder by pretending that both
10211 push and mov insns happen right here.
10213 Putting the unwind info here at the end of the ms_hook
10214 is done so that we can make absolutely certain we get
10215 the required byte sequence at the start of the function,
10216 rather than relying on an assembler that can produce
10217 the exact encoding required.
10219 However it does mean (in the unpatched case) that we have
10220 a 1 insn window where the asynchronous unwind info is
10221 incorrect. However, if we placed the unwind info at
10222 its correct location we would have incorrect unwind info
10223 in the patched case. Which is probably all moot since
10224 I don't expect Wine generates dwarf2 unwind info for the
10225 system libraries that use this feature. */
10231 stack_pointer_rtx);
10239 /* Note that gen_push incremented m->fs.cfa_offset, even
10240 though we didn't emit the push insn here. */
10244 }
10245 else
10246 {
10247 /* The frame pointer is not needed so pop %ebp again.
10248 This leaves us with a pristine state. */
10250 }
10251 }
10253 /* The first insn of a function that accepts its static chain on the
10254 stack is to push the register that would be filled in by a direct
10255 call. This insn will be skipped by the trampoline. */
10257 {
10261 /* We don't want to interpret this push insn as a register save,
10262 only as a stack adjustment. The real copy of the register as
10263 a save will be done later, if needed. */
10268 }
10270 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10271 of DRAP is needed and stack realignment is really needed after reload */
10273 {
10276 /* Only need to push parameter pointer reg if it is caller saved. */
10278 {
10279 /* Push arg pointer reg */
10282 }
10284 /* Grab the argument pointer. */
10291 /* Align the stack. */
10293 stack_pointer_rtx,
10297 /* Replicate the return address on the stack so that return
10298 address can be reached via (argp - 1) slot. This is needed
10299 to implement macro RETURN_ADDR_RTX and intrinsic function
10300 expand_builtin_return_addr etc. */
10306 /* For the purposes of frame and register save area addressing,
10307 we've started over with a new frame. */
10310 }
10316 {
10317 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10318 slower on all targets. Also sdb doesn't like it. */
10322 /* Push registers now, before setting the frame pointer
10323 on SEH target. */
10325 && TARGET_SEH
10327 {
10331 }
10334 {
10342 }
10343 }
10346 {
10347 /* If saving registers via PUSH, do so now. */
10349 {
10353 }
10355 /* When using red zone we may start register saving before allocating
10356 the stack frame saving one cycle of the prologue. However, avoid
10357 doing this if we have to probe the stack; at least on x86_64 the
10358 stack probe can turn into a call that clobbers a red zone location. */
10360 && (! TARGET_STACK_PROBE
10362 {
10365 }
10366 }
10369 {
10373 /* The computation of the size of the re-aligned stack frame means
10374 that we must allocate the size of the register save area before
10375 performing the actual alignment. Otherwise we cannot guarantee
10376 that there's enough storage above the realignment point. */
10383 /* Align the stack. */
10385 stack_pointer_rtx,
10388 /* For the purposes of register save area addressing, the stack
10389 pointer is no longer valid. As for the value of sp_offset,
10390 see ix86_compute_frame_layout, which we need to match in order
10391 to pass verification of stack_pointer_offset at the end. */
10394 }
10399 {
10400 /* We start to count from ARG_POINTER. */
10403 /* If it was realigned, take into account the fake frame. */
10405 {
10412 /* This over-estimates by 1 minimal-stack-alignment-unit but
10413 mitigates that by counting in the new return address slot. */
10414 current_function_dynamic_stack_size
10416 }
10419 }
10421 /* On SEH target with very large frame size, allocate an area to save
10422 SSE registers (as the very large allocation won't be described). */
10426 {
10427 HOST_WIDE_INT sse_size =
10432 /* No need to do stack checking as the area will be immediately
10433 written. */
10440 }
10442 /* The stack has already been decremented by the instruction calling us
10443 so probe if the size is non-negative to preserve the protection area. */
10445 {
10446 /* We expect the registers to be saved when probes are used. */
10450 {
10453 }
10454 else
10455 {
10463 else
10465 }
10466 }
10469 ;
10472 {
10476 }
10477 else
10478 {
10491 /* Note that SEH directives need to continue tracking the stack
10492 pointer even after the frame pointer has been set up. */
10494 {
10498 {
10502 }
10503 }
10506 {
10511 {
10515 }
10516 }
10521 /* Use the fact that AX still contains ALLOCATE. */
10523 ? gen_pro_epilogue_adjust_stack_di_sub
10530 {
10538 }
10542 {
10549 }
10551 {
10556 }
10557 }
10560 /* If we havn't already set up the frame pointer, do so now. */
10562 {
10574 }
10585 {
10592 }
10595 {
10597 {
10599 {
10609 label));
10613 }
10614 else
10616 }
10617 else
10618 {
10622 }
10623 }
10625 /* In the pic_reg_used case, make sure that the got load isn't deleted
10626 when mcount needs it. Blockage to avoid call movement across mcount
10627 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10628 note. */
10633 {
10634 /* vDRAP is setup but after reload it turns out stack realign
10635 isn't necessary, here we will emit prologue to setup DRAP
10636 without stack realign adjustment */
10639 }
10641 /* Prevent instructions from being scheduled into register save push
10642 sequence when access to the redzone area is done through frame pointer.
10643 The offset between the frame pointer and the stack pointer is calculated
10644 relative to the value of the stack pointer at the end of the function
10645 prologue, and moving instructions that access redzone area via frame
10646 pointer inside push sequence violates this assumption. */
10650 /* Emit cld instruction if stringops are used in the function. */
10654 /* SEH requires that the prologue end within 256 bytes of the start of
10655 the function. Prevent instruction schedules that would extend that.
10656 Further, prevent alloca modifications to the stack pointer from being
10657 combined with prologue modifications. */
10660 }
10662 /* Emit code to restore REG using a POP insn. */
10664 static void
10666 {
10675 {
10676 /* Previously we'd represented the CFA as an expression
10677 like *(%ebp - 8). We've just popped that value from
10678 the stack, which means we need to reset the CFA to
10679 the drap register. This will remain until we restore
10680 the stack pointer. */
10684 /* This means that the DRAP register is valid for addressing too. */
10687 }
10690 {
10697 }
10699 /* When the frame pointer is the CFA, and we pop it, we are
10700 swapping back to the stack pointer as the CFA. This happens
10701 for stack frames that don't allocate other data, so we assume
10702 the stack pointer is now pointing at the return address, i.e.
10703 the function entry state, which makes the offset be 1 word. */
10705 {
10708 {
10716 }
10717 }
10718 }
10720 /* Emit code to restore saved registers using POP insns. */
10722 static void
10724 {
10730 }
10732 /* Emit code and notes for the LEAVE instruction. */
10734 static void
10736 {
10748 {
10756 }
10759 }
10761 /* Emit code to restore saved registers using MOV insns.
10762 First register is restored from CFA - CFA_OFFSET. */
10763 static void
10766 {
10772 {
10781 {
10782 /* Previously we'd represented the CFA as an expression
10783 like *(%ebp - 8). We've just popped that value from
10784 the stack, which means we need to reset the CFA to
10785 the drap register. This will remain until we restore
10786 the stack pointer. */
10790 /* This means that the DRAP register is valid for addressing. */
10792 }
10793 else
10797 }
10798 }
10800 /* Emit code to restore saved registers using MOV insns.
10801 First register is restored from CFA - CFA_OFFSET. */
10802 static void
10805 {
10810 {
10812 rtx mem;
10822 }
10823 }
10825 /* Restore function stack, frame, and registers. */
10827 void
10829 {
10845 /* The FP must be valid if the frame pointer is present. */
10850 /* We must have *some* valid pointer to the stack frame. */
10853 /* The DRAP is never valid at this point. */
10856 /* See the comment about red zone and frame
10857 pointer usage in ix86_expand_prologue. */
10864 /* Determine the CFA offset of the end of the red-zone. */
10867 {
10868 /* The red-zone begins below the return address. */
10871 /* When the register save area is in the aligned portion of
10872 the stack, determine the maximum runtime displacement that
10873 matches up with the aligned frame. */
10877 }
10879 /* Special care must be taken for the normal return case of a function
10880 using eh_return: the eax and edx registers are marked as saved, but
10881 not restored along this path. Adjust the save location to match. */
10885 /* EH_RETURN requires the use of moves to function properly. */
10888 /* SEH requires the use of pops to identify the epilogue. */
10891 /* If we're only restoring one register and sp is not valid then
10892 using a move instruction to restore the register since it's
10893 less work than reloading sp and popping the register. */
10906 && TARGET_USE_LEAVE
10910 else
10914 {
10915 /* Ensure that the entire register save area is addressable via
10916 the stack pointer, if we will restore via sp. */
10921 {
10925 style,
10927 }
10928 }
10930 /* If there are any SSE registers to restore, then we have to do it
10931 via moves, since there's obviously no pop for SSE regs. */
10937 {
10938 rtx t;
10943 /* eh_return epilogues need %ecx added to the stack pointer. */
10945 {
10948 /* Stack align doesn't work with eh_return. */
10950 /* Neither does regparm nested functions. */
10954 {
10962 /* Note that we use SA as a temporary CFA, as the return
10963 address is at the proper place relative to it. We
10964 pretend this happens at the FP restore insn because
10965 prior to this insn the FP would be stored at the wrong
10966 offset relative to SA, and after this insn we have no
10967 other reasonable register to use for the CFA. We don't
10968 bother resetting the CFA to the SP for the duration of
10969 the return insn. */
10982 }
10983 else
10984 {
10992 {
10996 UNITS_PER_WORD));
10998 }
10999 }
11002 }
11003 }
11004 else
11005 {
11006 /* SEH requires that the function end with (1) a stack adjustment
11007 if necessary, (2) a sequence of pops, and (3) a return or
11008 jump instruction. Prevent insns from the function body from
11009 being scheduled into this sequence. */
11011 {
11012 /* Prevent a catch region from being adjacent to the standard
11013 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11014 several other flags that would be interesting to test are
11015 not yet set up. */
11018 else
11020 }
11022 /* First step is to deallocate the stack frame so that we can
11023 pop the registers. Also do it on SEH target for very large
11024 frame as the emitted instructions aren't allowed by the ABI in
11025 epilogues. */
11027 || (TARGET_SEH
11030 {
11035 }
11037 {
11041 style,
11043 }
11046 }
11048 /* If we used a stack pointer and haven't already got rid of it,
11049 then do so now. */
11051 {
11052 /* If the stack pointer is valid and pointing at the frame
11053 pointer store address, then we only need a pop. */
11056 /* Leave results in shorter dependency chains on CPUs that are
11057 able to grok it fast. */
11062 else
11063 {
11065 hard_frame_pointer_rtx,
11068 }
11069 }
11072 {
11074 rtx insn;
11100 }
11102 /* At this point the stack pointer must be valid, and we must have
11103 restored all of the registers. We may not have deallocated the
11104 entire stack frame. We've delayed this until now because it may
11105 be possible to merge the local stack deallocation with the
11106 deallocation forced by ix86_static_chain_on_stack. */
11111 {
11115 }
11116 else
11119 /* Sibcall epilogues don't want a return instruction. */
11121 {
11124 }
11127 {
11130 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11131 address, do explicit add, and jump indirectly to the caller. */
11134 {
11136 rtx insn;
11138 /* There is no "pascal" calling convention in any 64bit ABI. */
11154 }
11155 else
11157 }
11158 else
11161 /* Restore the state back to the state from the prologue,
11162 so that it's correct for the next epilogue. */
11164 }
11166 /* Reset from the function's potential modifications. */
11168 static void
11170 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11171 {
11174 #if TARGET_MACHO
11175 /* Mach-O doesn't support labels at the end of objects, so if
11176 it looks like we might want one, insert a NOP. */
11177 {
11183 {
11184 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11185 notes only, instead set their CODE_LABEL_NUMBER to -1,
11186 otherwise there would be code generation differences
11187 in between -g and -g0. */
11191 }
11201 }
11202 #endif
11204 }
11206 /* Return a scratch register to use in the split stack prologue. The
11207 split stack prologue is used for -fsplit-stack. It is the first
11208 instructions in the function, even before the regular prologue.
11209 The scratch register can be any caller-saved register which is not
11210 used for parameters or for the static chain. */
11212 static unsigned int
11214 {
11217 else
11218 {
11231 {
11233 {
11237 }
11239 }
11241 {
11245 }
11247 {
11250 else
11251 {
11253 {
11257 }
11259 }
11260 }
11261 else
11262 {
11263 /* FIXME: We could make this work by pushing a register
11264 around the addition and comparison. */
11267 }
11268 }
11269 }
11271 /* A SYMBOL_REF for the function which allocates new stackspace for
11272 -fsplit-stack. */
11276 /* A SYMBOL_REF for the more stack function when using the large
11277 model. */
11281 /* Handle -fsplit-stack. These are the first instructions in the
11282 function, even before the regular prologue. */
11284 void
11286 {
11288 HOST_WIDE_INT allocate;
11293 rtx fn;
11301 /* This is the label we will branch to if we have enough stack
11302 space. We expect the basic block reordering pass to reverse this
11303 branch if optimizing, so that we branch in the unlikely case. */
11306 /* We need to compare the stack pointer minus the frame size with
11307 the stack boundary in the TCB. The stack boundary always gives
11308 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11309 can compare directly. Otherwise we need to do an addition. */
11312 UNSPEC_STACK_CHECK);
11317 else
11318 {
11320 rtx offset;
11322 /* We need a scratch register to hold the stack pointer minus
11323 the required frame size. Since this is the very start of the
11324 function, the scratch register can be any caller-saved
11325 register which is not used for parameters. */
11332 {
11333 /* We don't use ix86_gen_add3 in this case because it will
11334 want to split to lea, but when not optimizing the insn
11335 will not be split after this point. */
11338 offset)));
11339 }
11340 else
11341 {
11344 stack_pointer_rtx));
11345 }
11347 }
11353 /* Mark the jump as very likely to be taken. */
11361 /* Get more stack space. We pass in the desired stack space and the
11362 size of the arguments to copy to the new stack. In 32-bit mode
11363 we push the parameters; __morestack will return on a new stack
11364 anyhow. In 64-bit mode we pass the parameters in r10 and
11365 r11. */
11370 {
11376 /* If this function uses a static chain, it will be in %r10.
11377 Preserve it across the call to __morestack. */
11379 {
11380 rtx rax;
11385 }
11388 {
11389 HOST_WIDE_INT argval;
11392 /* When using the large model we need to load the address
11393 into a register, and we've run out of registers. So we
11394 switch to a different calling convention, and we call a
11395 different function: __morestack_large. We pass the
11396 argument size in the upper 32 bits of r10 and pass the
11397 frame size in the lower 32 bits. */
11402 split_stack_fn_large =
11406 {
11416 UNSPEC_GOT);
11422 }
11423 else
11430 }
11431 else
11432 {
11436 }
11439 }
11440 else
11441 {
11444 }
11450 /* In order to make call/return prediction work right, we now need
11451 to execute a return instruction. See
11452 libgcc/config/i386/morestack.S for the details on how this works.
11454 For flow purposes gcc must not see this as a return
11455 instruction--we need control flow to continue at the subsequent
11456 label. Therefore, we use an unspec. */
11460 /* If we are in 64-bit mode and this function uses a static chain,
11461 we saved %r10 in %rax before calling _morestack. */
11466 /* If this function calls va_start, we need to store a pointer to
11467 the arguments on the old stack, because they may not have been
11468 all copied to the new stack. At this point the old stack can be
11469 found at the frame pointer value used by __morestack, because
11470 __morestack has set that up before calling back to us. Here we
11471 store that pointer in a scratch register, and in
11472 ix86_expand_prologue we store the scratch register in a stack
11473 slot. */
11475 {
11477 rtx frame_reg;
11484 /* 64-bit:
11485 fp -> old fp value
11486 return address within this function
11487 return address of caller of this function
11488 stack arguments
11489 So we add three words to get to the stack arguments.
11491 32-bit:
11492 fp -> old fp value
11493 return address within this function
11494 first argument to __morestack
11495 second argument to __morestack
11496 return address of caller of this function
11497 stack arguments
11498 So we add five words to get to the stack arguments.
11499 */
11510 }
11515 /* If this function calls va_start, we now have to set the scratch
11516 register for the case where we do not call __morestack. In this
11517 case we need to set it based on the stack pointer. */
11519 {
11526 }
11527 }
11529 /* We may have to tell the dataflow pass that the split stack prologue
11530 is initializing a scratch register. */
11532 static void
11534 {
11536 {
11539 }
11540 }
11541 \f
11542 /* Determine if op is suitable SUBREG RTX for address. */
11544 static bool
11546 {
11557 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11558 failures when the register is one word out of a two word structure. */
11562 /* Allow only SUBREGs of non-eliminable hard registers. */
11564 }
11566 /* Extract the parts of an RTL expression that is a valid memory address
11567 for an instruction. Return 0 if the structure of the address is
11568 grossly off. Return -1 if the address contains ASHIFT, so it is not
11569 strictly valid, but still used for computing length of lea instruction. */
11571 int
11573 {
11578 rtx tmp;
11582 /* Allow zero-extended SImode addresses,
11583 they will be emitted with addr32 prefix. */
11585 {
11588 {
11592 }
11595 {
11602 }
11603 }
11605 /* Allow SImode subregs of DImode addresses,
11606 they will be emitted with addr32 prefix. */
11608 {
11611 {
11615 }
11616 }
11621 {
11624 else
11626 }
11628 {
11633 do
11634 {
11639 }
11646 {
11649 {
11674 /* FALLTHRU */
11678 && TARGET_TLS_DIRECT_SEG_REFS
11681 else
11688 /* FALLTHRU */
11695 else
11710 }
11711 }
11712 }
11714 {
11717 }
11719 {
11720 /* We're called for lea too, which implements ashift on occasion. */
11730 }
11732 {
11736 /* Constant addresses are sign extended to 64bit, we have to
11737 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11743 }
11744 else
11748 {
11750 ;
11753 ;
11754 else
11756 }
11758 /* Address override works only on the (%reg) part of %fs:(%reg). */
11764 /* Extract the integral value of scale. */
11766 {
11770 }
11775 /* Avoid useless 0 displacement. */
11779 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11784 {
11785 rtx tmp;
11788 }
11790 /* Special case: %ebp cannot be encoded as a base without a displacement.
11791 Similarly %r13. */
11793 && base_reg
11802 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11803 Avoid this by transforming to [%esi+0].
11804 Reload calls address legitimization without cfun defined, so we need
11805 to test cfun for being non-NULL. */
11811 /* Special case: encode reg+reg instead of reg*2. */
11815 /* Special case: scaling cannot be encoded without base or displacement. */
11826 }
11827 \f
11828 /* Return cost of the memory address x.
11829 For i386, it is better to use a complex address than let gcc copy
11830 the address into a reg and make a new pseudo. But not if the address
11831 requires to two regs - that would mean more pseudos with longer
11832 lifetimes. */
11833 static int
11835 addr_space_t as ATTRIBUTE_UNUSED,
11837 {
11849 /* Attempt to minimize number of registers in the address. */
11855 cost++;
11862 cost++;
11864 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11865 since it's predecode logic can't detect the length of instructions
11866 and it degenerates to vector decoded. Increase cost of such
11867 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11868 to split such addresses or even refuse such addresses at all.
11870 Following addressing modes are affected:
11871 [base+scale*index]
11872 [scale*index+disp]
11873 [base+index]
11875 The first and last case may be avoidable by explicitly coding the zero in
11876 memory address, but I don't have AMD-K6 machine handy to check this
11877 theory. */
11886 }
11887 \f
11888 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11889 this is used for to form addresses to local data when -fPIC is in
11890 use. */
11892 static bool
11894 {
11897 }
11899 /* Determine if a given RTX is a valid constant. We already know this
11900 satisfies CONSTANT_P. */
11902 static bool
11904 {
11906 {
11911 {
11915 }
11920 /* Only some unspecs are valid as "constants". */
11923 {
11939 }
11941 /* We must have drilled down to a symbol. */
11946 /* FALLTHRU */
11949 /* TLS symbols are never valid. */
11953 /* DLLIMPORT symbols are never valid. */
11958 #if TARGET_MACHO
11959 /* mdynamic-no-pic */
11962 #endif
11978 }
11980 /* Otherwise we handle everything else in the move patterns. */
11982 }
11984 /* Determine if it's legal to put X into the constant pool. This
11985 is not possible for the address of thread-local symbols, which
11986 is checked above. */
11988 static bool
11990 {
11991 /* We can always put integral constants and vectors in memory. */
11993 {
12001 }
12003 }
12006 /* Nonzero if the constant value X is a legitimate general operand
12007 when generating PIC code. It is given that flag_pic is on and
12008 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12010 bool
12012 {
12013 rtx inner;
12016 {
12023 /* Only some unspecs are valid as "constants". */
12026 {
12039 }
12040 /* FALLTHRU */
12048 }
12049 }
12051 /* Determine if a given CONST RTX is a valid memory displacement
12052 in PIC mode. */
12054 bool
12056 {
12059 /* In 64bit mode we can allow direct addresses of symbols and labels
12060 when they are not dynamic symbols. */
12062 {
12066 {
12090 /* FALLTHRU */
12093 /* TLS references should always be enclosed in UNSPEC. */
12103 }
12104 }
12110 {
12111 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12112 of GOT tables. We should not need these anyway. */
12124 }
12128 {
12133 }
12142 {
12146 /* We need to check for both symbols and labels because VxWorks loads
12147 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12148 details. */
12152 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12153 While ABI specify also 32bit relocation but we don't produce it in
12154 small PIC model at all. */
12176 }
12179 }
12181 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12182 replace the input X, or the original X if no replacement is called for.
12183 The output parameter *WIN is 1 if the calling macro should goto WIN,
12184 0 if it should not. */
12186 bool
12191 {
12192 /* Reload can generate:
12194 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12195 (reg:DI 97))
12196 (reg:DI 2 cx))
12198 This RTX is rejected from ix86_legitimate_address_p due to
12199 non-strictness of base register 97. Following this rejection,
12200 reload pushes all three components into separate registers,
12201 creating invalid memory address RTX.
12203 Following code reloads only the invalid part of the
12204 memory address RTX. */
12210 {
12216 {
12221 }
12225 {
12230 }
12234 }
12237 }
12239 /* Recognizes RTL expressions that are valid memory addresses for an
12240 instruction. The MODE argument is the machine mode for the MEM
12241 expression that wants to use this address.
12243 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12244 convert common non-canonical forms to canonical form so that they will
12245 be recognized. */
12247 static bool
12250 {
12253 HOST_WIDE_INT scale;
12256 /* Decomposition failed. */
12264 /* Validate base register. */
12266 {
12267 rtx reg;
12273 else
12274 /* Base is not a register. */
12282 /* Base is not valid. */
12284 }
12286 /* Validate index register. */
12288 {
12289 rtx reg;
12295 else
12296 /* Index is not a register. */
12304 /* Index is not valid. */
12306 }
12308 /* Index and base should have the same mode. */
12313 /* Validate scale factor. */
12315 {
12317 /* Scale without index. */
12321 /* Scale is not a valid multiplier. */
12323 }
12325 /* Validate displacement. */
12327 {
12332 {
12333 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12334 used. While ABI specify also 32bit relocations, we don't produce
12335 them at all and use IP relative instead. */
12342 /* 64bit address unspec. */
12362 /* Invalid address unspec. */
12364 }
12367 && (flag_pic
12368 || (TARGET_MACHO
12369 #if TARGET_MACHO
12370 && MACHOPIC_INDIRECT
12372 #endif
12373 )))
12374 {
12376 is_legitimate_pic:
12378 {
12379 /* foo@dtpoff(%rX) is ok. */
12386 /* Non-constant pic memory reference. */
12388 }
12391 /* Displacement is an invalid pic construct. */
12393 #if TARGET_MACHO
12396 /* displacment must be referenced via non_lazy_pointer */
12398 #endif
12400 /* This code used to verify that a symbolic pic displacement
12401 includes the pic_offset_table_rtx register.
12403 While this is good idea, unfortunately these constructs may
12404 be created by "adds using lea" optimization for incorrect
12405 code like:
12407 int a;
12408 int foo(int i)
12409 {
12410 return *(&a+i);
12411 }
12413 This code is nonsensical, but results in addressing
12414 GOT table with pic_offset_table_rtx base. We can't
12415 just refuse it easily, since it gets matched by
12416 "addsi3" pattern, that later gets split to lea in the
12417 case output register differs from input. While this
12418 can be handled by separate addsi pattern for this case
12419 that never results in lea, this seems to be easier and
12420 correct fix for crash to disable this test. */
12421 }
12428 /* Displacement is not constant. */
12432 /* Displacement is out of range. */
12434 }
12436 /* Everything looks valid. */
12438 }
12440 /* Determine if a given RTX is a valid constant address. */
12442 bool
12444 {
12446 }
12447 \f
12448 /* Return a unique alias set for the GOT. */
12450 static alias_set_type
12452 {
12457 }
12459 /* Return a legitimate reference for ORIG (an address) using the
12460 register REG. If REG is 0, a new pseudo is generated.
12462 There are two types of references that must be handled:
12464 1. Global data references must load the address from the GOT, via
12465 the PIC reg. An insn is emitted to do this load, and the reg is
12466 returned.
12468 2. Static data references, constant pool addresses, and code labels
12469 compute the address as an offset from the GOT, whose base is in
12470 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12471 differentiate them from global data objects. The returned
12472 address is the PIC reg + an unspec constant.
12474 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12475 reg also appears in the address. */
12477 static rtx
12479 {
12483 #if TARGET_MACHO
12485 {
12488 /* Use the generic Mach-O PIC machinery. */
12490 }
12491 #endif
12498 {
12499 rtx tmpreg;
12500 /* This symbol may be referenced via a displacement from the PIC
12501 base address (@GOTOFF). */
12508 {
12510 UNSPEC_GOTOFF);
12512 }
12513 else
12518 else
12523 {
12527 }
12529 }
12531 {
12532 /* This symbol may be referenced via a displacement from the PIC
12533 base address (@GOTOFF). */
12540 {
12542 UNSPEC_GOTOFF);
12544 }
12545 else
12551 {
12554 }
12555 }
12557 /* We can't use @GOTOFF for text labels on VxWorks;
12558 see gotoff_operand. */
12560 {
12562 {
12568 {
12571 }
12572 }
12574 /* For x64 PE-COFF there is no GOT table. So we use address
12575 directly. */
12577 {
12585 }
12587 {
12595 /* Use directly gen_movsi, otherwise the address is loaded
12596 into register for CSE. We don't want to CSE this addresses,
12597 instead we CSE addresses from the GOT table, so skip this. */
12600 }
12601 else
12602 {
12603 /* This symbol must be referenced via a load from the
12604 Global Offset Table (@GOT). */
12620 }
12621 }
12622 else
12623 {
12626 {
12628 {
12631 }
12632 else
12634 }
12636 {
12639 /* We must match stuff we generate before. Assume the only
12640 unspecs that can get here are ours. Not that we could do
12641 anything with them anyway.... */
12647 }
12649 {
12652 /* Check first to see if this is a constant offset from a @GOTOFF
12653 symbol reference. */
12656 {
12658 {
12662 UNSPEC_GOTOFF);
12668 {
12671 }
12672 }
12673 else
12674 {
12677 {
12681 }
12682 }
12683 }
12684 else
12685 {
12688 new_rtx
12692 {
12695 {
12698 new_rtx
12700 }
12701 else
12703 }
12704 else
12705 {
12708 {
12711 }
12713 }
12714 }
12715 }
12716 }
12718 }
12719 \f
12720 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12722 static rtx
12724 {
12728 {
12733 }
12739 }
12741 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12745 static rtx
12747 {
12749 {
12755 }
12758 }
12760 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12764 rtx
12766 {
12768 {
12769 ix86_tls_module_base_symbol
12774 }
12777 }
12779 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12780 false if we expect this to be used for a memory address and true if
12781 we expect to load the address into a register. */
12783 static rtx
12785 {
12792 {
12797 {
12800 else
12801 {
12804 }
12805 }
12808 {
12811 else
12821 }
12822 else
12823 {
12827 {
12829 rtx insns;
12832 emit_call_insn
12842 }
12843 else
12845 }
12852 {
12855 else
12856 {
12859 }
12860 }
12863 {
12868 else
12874 }
12875 else
12876 {
12880 {
12885 emit_call_insn
12890 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12891 share the LD_BASE result with other LD model accesses. */
12893 UNSPEC_TLS_LD_BASE);
12897 }
12898 else
12900 }
12908 {
12915 }
12920 {
12922 {
12923 /* The Sun linker took the AMD64 TLS spec literally
12924 and can only handle %rax as destination of the
12925 initial executable code sequence. */
12930 }
12932 /* Generate DImode references to avoid %fs:(%reg32)
12933 problems and linker IE->LE relaxation bug. */
12937 }
12939 {
12944 }
12946 {
12950 }
12951 else
12952 {
12955 }
12965 {
12970 }
12971 else
12972 {
12976 }
12986 {
12990 }
12991 else
12992 {
12996 }
13001 }
13004 }
13006 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13007 to symbol DECL. */
13010 htab_t dllimport_map;
13012 static tree
13014 {
13021 tree to;
13022 rtx rtl;
13066 }
13068 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13069 true if we require the result be a register. */
13071 static rtx
13073 {
13074 tree imp_decl;
13075 rtx x;
13084 }
13086 /* Try machine-dependent ways of modifying an illegitimate address
13087 to be legitimate. If we find one, return the new, valid address.
13088 This macro is used in only one place: `memory_address' in explow.c.
13090 OLDX is the address as it was before break_out_memory_refs was called.
13091 In some cases it is useful to look at this to decide what needs to be done.
13093 It is always safe for this macro to do nothing. It exists to recognize
13094 opportunities to optimize the output.
13096 For the 80386, we handle X+REG by loading X into a register R and
13097 using R+REG. R will go in a general reg and indexing will be used.
13098 However, if REG is a broken-out memory address or multiplication,
13099 nothing needs to be done because REG can certainly go in a general reg.
13101 When -fpic is used, special handling is needed for symbolic references.
13102 See comments by legitimize_pic_address in i386.c for details. */
13104 static rtx
13107 {
13118 {
13122 }
13125 {
13132 {
13135 }
13136 }
13141 #if TARGET_MACHO
13144 #endif
13146 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13150 {
13155 }
13158 {
13159 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13164 {
13170 }
13175 {
13181 }
13183 /* Put multiply first if it isn't already. */
13185 {
13190 }
13192 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13193 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13194 created by virtual register instantiation, register elimination, and
13195 similar optimizations. */
13197 {
13203 }
13205 /* Canonicalize
13206 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13207 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13212 {
13213 rtx constant;
13217 {
13220 }
13222 {
13225 }
13226 else
13230 {
13237 }
13238 }
13244 {
13247 }
13250 {
13253 }
13261 {
13264 }
13270 {
13274 {
13277 }
13281 }
13284 {
13288 {
13291 }
13295 }
13296 }
13299 }
13300 \f
13301 /* Print an integer constant expression in assembler syntax. Addition
13302 and subtraction are the only arithmetic that may appear in these
13303 expressions. FILE is the stdio stream to write to, X is the rtx, and
13304 CODE is the operand print code from the output string. */
13306 static void
13308 {
13312 {
13321 else
13322 {
13325 /* Mark the decl as referenced so that cgraph will
13326 output the function. */
13330 #if TARGET_MACHO
13334 #endif
13336 }
13344 /* FALLTHRU */
13355 /* This used to output parentheses around the expression,
13356 but that does not work on the 386 (either ATT or BSD assembler). */
13362 {
13363 /* We can use %d if the number is <32 bits and positive. */
13368 else
13370 }
13371 else
13372 /* We can't handle floating point constants;
13373 TARGET_PRINT_OPERAND must handle them. */
13378 /* Some assemblers need integer constants to appear first. */
13380 {
13384 }
13385 else
13386 {
13391 }
13406 {
13410 }
13415 {
13434 /* FIXME: This might be @TPOFF in Sun ld too. */
13443 else
13453 else
13459 #if TARGET_MACHO
13464 #endif
13468 }
13473 }
13474 }
13476 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13477 We need to emit DTP-relative relocations. */
13479 static void ATTRIBUTE_UNUSED
13481 {
13486 {
13494 }
13495 }
13497 /* Return true if X is a representation of the PIC register. This copes
13498 with calls from ix86_find_base_term, where the register might have
13499 been replaced by a cselib value. */
13501 static bool
13503 {
13507 else
13509 }
13511 /* Helper function for ix86_delegitimize_address.
13512 Attempt to delegitimize TLS local-exec accesses. */
13514 static rtx
13516 {
13541 {
13546 }
13552 }
13554 /* In the name of slightly smaller debug output, and to cater to
13555 general assembler lossage, recognize PIC+GOTOFF and turn it back
13556 into a direct symbol reference.
13558 On Darwin, this is necessary to avoid a crash, because Darwin
13559 has a different PIC label for each routine but the DWARF debugging
13560 information is not associated with any particular routine, so it's
13561 necessary to remove references to the PIC label from RTL stored by
13562 the DWARF output code. */
13564 static rtx
13566 {
13568 /* addend is NULL or some rtx if x is something+GOTOFF where
13569 something doesn't include the PIC register. */
13571 /* reg_addend is NULL or a multiple of some register. */
13573 /* const_addend is NULL or a const_int. */
13575 /* This is the result, or NULL. */
13584 {
13591 {
13597 }
13606 {
13611 }
13613 }
13620 /* %ebx + GOT/GOTOFF */
13621 ;
13623 {
13624 /* %ebx + %reg * scale + GOT/GOTOFF */
13630 else
13631 {
13634 }
13635 }
13636 else
13642 {
13645 }
13664 {
13665 /* If the rest of original X doesn't involve the PIC register, add
13666 addend and subtract pic_offset_table_rtx. This can happen e.g.
13667 for code like:
13668 leal (%ebx, %ecx, 4), %ecx
13669 ...
13670 movl foo@GOTOFF(%ecx), %edx
13671 in which case we return (%ecx - %ebx) + foo. */
13674 pic_offset_table_rtx),
13675 result);
13676 else
13678 }
13680 {
13684 }
13686 }
13688 /* If X is a machine specific address (i.e. a symbol or label being
13689 referenced as a displacement from the GOT implemented using an
13690 UNSPEC), then return the base term. Otherwise return X. */
13692 rtx
13694 {
13695 rtx term;
13698 {
13712 }
13715 }
13716 \f
13717 static void
13720 {
13724 {
13727 }
13732 {
13735 {
13754 }
13758 {
13777 }
13784 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13785 Those same assemblers have the same but opposite lossage on cmov. */
13790 else
13795 {
13808 }
13816 {
13829 }
13832 /* ??? As above. */
13841 /* ??? As above. */
13846 else
13857 }
13859 }
13861 /* Print the name of register X to FILE based on its machine mode and number.
13862 If CODE is 'w', pretend the mode is HImode.
13863 If CODE is 'b', pretend the mode is QImode.
13864 If CODE is 'k', pretend the mode is SImode.
13865 If CODE is 'q', pretend the mode is DImode.
13866 If CODE is 'x', pretend the mode is V4SFmode.
13867 If CODE is 't', pretend the mode is V8SFmode.
13868 If CODE is 'h', pretend the reg is the 'high' byte register.
13869 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13870 If CODE is 'd', duplicate the operand for AVX instruction.
13871 */
13873 void
13875 {
13884 {
13888 }
13913 else
13916 /* Irritatingly, AMD extended registers use different naming convention
13917 from the normal registers: "r%d[bwd]" */
13919 {
13924 {
13938 /* no suffix */
13943 }
13945 }
13949 {
13952 {
13955 }
13956 /* FALLTHRU */
13962 /* FALLTHRU */
13965 normal:
13980 {
13985 }
13989 }
13993 {
13996 else
13998 }
13999 }
14001 /* Locate some local-dynamic symbol still in use by this function
14002 so that we can print its name in some tls_local_dynamic_base
14003 pattern. */
14005 static int
14007 {
14012 {
14015 }
14018 }
14022 {
14023 rtx insn;
14034 }
14036 /* Meaning of CODE:
14037 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14038 C -- print opcode suffix for set/cmov insn.
14039 c -- like C, but print reversed condition
14040 F,f -- likewise, but for floating-point.
14041 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14042 otherwise nothing
14043 R -- print the prefix for register names.
14044 z -- print the opcode suffix for the size of the current operand.
14045 Z -- likewise, with special suffixes for x87 instructions.
14046 * -- print a star (in certain assembler syntax)
14047 A -- print an absolute memory reference.
14048 E -- print address with DImode register names if TARGET_64BIT.
14049 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14050 s -- print a shift double count, followed by the assemblers argument
14051 delimiter.
14052 b -- print the QImode name of the register for the indicated operand.
14053 %b0 would print %al if operands[0] is reg 0.
14054 w -- likewise, print the HImode name of the register.
14055 k -- likewise, print the SImode name of the register.
14056 q -- likewise, print the DImode name of the register.
14057 x -- likewise, print the V4SFmode name of the register.
14058 t -- likewise, print the V8SFmode name of the register.
14059 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14060 y -- print "st(0)" instead of "st" as a register.
14061 d -- print duplicated register operand for AVX instruction.
14062 D -- print condition for SSE cmp instruction.
14063 P -- if PIC, print an @PLT suffix.
14064 p -- print raw symbol name.
14065 X -- don't print any sort of PIC '@' suffix for a symbol.
14066 & -- print some in-use local-dynamic symbol name.
14067 H -- print a memory address offset by 8; used for sse high-parts
14068 Y -- print condition for XOP pcom* instruction.
14069 + -- print a branch hint as 'cs' or 'ds' prefix
14070 ; -- print a semicolon (after prefixes due to bug in older gas).
14071 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14072 @ -- print a segment register of thread base pointer load
14073 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14074 */
14076 void
14078 {
14080 {
14082 {
14085 {
14091 /* Intel syntax. For absolute addresses, registers should not
14092 be surrounded by braces. */
14094 {
14099 }
14104 }
14110 /* Wrap address in an UNSPEC to declare special handling. */
14148 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14153 {
14167 output_operand_lossage
14170 }
14173 #endif
14178 {
14179 /* Opcodes don't get size suffixes if using Intel opcodes. */
14184 {
14202 output_operand_lossage
14205 }
14206 }
14209 warning
14211 /* FALLTHRU */
14214 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14219 {
14221 {
14223 #ifdef HAVE_AS_IX86_FILDS
14225 #endif
14233 #ifdef HAVE_AS_IX86_FILDQ
14235 #else
14237 #endif
14242 }
14243 }
14245 {
14246 /* 387 opcodes don't get size suffixes
14247 if the operands are registers. */
14252 {
14268 }
14269 }
14270 else
14271 {
14272 output_operand_lossage
14275 }
14277 output_operand_lossage
14297 {
14300 }
14305 {
14356 }
14360 /* Little bit of braindamage here. The SSE compare instructions
14361 does use completely different names for the comparisons that the
14362 fp conditional moves. */
14364 {
14367 {
14370 }
14376 {
14379 }
14385 {
14388 }
14397 {
14400 }
14406 {
14409 }
14415 {
14418 }
14429 }
14434 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14437 #endif
14442 {
14446 }
14450 file);
14455 {
14459 }
14460 /* It doesn't actually matter what mode we use here, as we're
14461 only going to use this for printing. */
14469 #ifdef HAVE_AS_IX86_HLE
14471 #else
14473 #endif
14475 #ifdef HAVE_AS_IX86_HLE
14477 #else
14479 #endif
14480 /* We do not want to print value of the operand. */
14489 {
14494 else
14497 }
14500 {
14501 rtx x;
14510 {
14515 {
14517 bool cputaken
14520 /* Emit hints only in the case default branch prediction
14521 heuristics would fail. */
14523 {
14524 /* We use 3e (DS) prefix for taken branches and
14525 2e (CS) prefix for not taken branches. */
14528 else
14530 }
14531 }
14532 }
14534 }
14537 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14539 #endif
14546 /* The kernel uses a different segment register for performance
14547 reasons; a system call would not have to trash the userspace
14548 segment register, which would be expensive. */
14551 else
14566 }
14567 }
14573 {
14574 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14577 {
14580 {
14589 else
14595 }
14597 /* Check for explicit size override (codes 'b', 'w', 'k',
14598 'q' and 'x') */
14612 }
14615 /* Avoid (%rip) for call operands. */
14621 else
14623 }
14626 {
14627 REAL_VALUE_TYPE r;
14635 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14638 else
14640 }
14643 {
14644 REAL_VALUE_TYPE r;
14653 }
14655 /* These float cases don't actually occur as immediate operands. */
14657 {
14662 }
14664 else
14665 {
14666 /* We have patterns that allow zero sets of memory, for instance.
14667 In 64-bit mode, we should probably support all 8-byte vectors,
14668 since we can in fact encode that into an immediate. */
14670 {
14673 }
14676 {
14678 {
14681 }
14684 {
14687 else
14689 }
14690 }
14695 else
14697 }
14698 }
14700 static bool
14702 {
14705 }
14706 \f
14707 /* Print a memory operand whose address is ADDR. */
14709 static void
14711 {
14720 {
14727 }
14729 {
14733 }
14734 else
14745 {
14756 }
14758 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14760 {
14772 }
14774 {
14775 /* Displacement only requires special attention. */
14778 {
14782 }
14785 else
14787 }
14788 else
14789 {
14790 /* Print SImode register names to force addr32 prefix. */
14792 {
14793 #ifdef ENABLE_CHECKING
14796 {
14807 }
14808 #endif
14811 }
14813 && TARGET_X32
14814 && disp
14817 {
14818 /* X32 runs in 64-bit mode, where displacement, DISP, in
14819 address DISP(%r64), is encoded as 32-bit immediate sign-
14820 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14821 address is %r64 + 0xffffffffbffffd00. When %r64 <
14822 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14823 which is invalid for x32. The correct address is %r64
14824 - 0x40000300 == 0xf7ffdd64. To properly encode
14825 -0x40000300(%r64) for x32, we zero-extend negative
14826 displacement by forcing addr32 prefix which truncates
14827 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14828 zero-extend all negative displacements, including -1(%rsp).
14829 However, for small negative displacements, sign-extension
14830 won't cause overflow. We only zero-extend negative
14831 displacements if they < -16*1024*1024, which is also used
14832 to check legitimate address displacements for PIC. */
14834 }
14837 {
14839 {
14844 else
14846 }
14852 {
14857 }
14859 }
14860 else
14861 {
14865 {
14866 /* Pull out the offset of a symbol; print any symbol itself. */
14870 {
14874 }
14882 else
14884 }
14888 {
14891 {
14895 }
14896 }
14899 else
14903 {
14908 }
14910 }
14911 }
14912 }
14914 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14916 static bool
14918 {
14919 rtx op;
14926 {
14929 /* FIXME: This might be @TPOFF in Sun ld. */
14940 else
14952 else
14959 #if TARGET_MACHO
14965 #endif
14968 {
14973 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14975 #else
14977 #endif
14980 }
14985 }
14988 }
14989 \f
14990 /* Split one or more double-mode RTL references into pairs of half-mode
14991 references. The RTL can be REG, offsettable MEM, integer constant, or
14992 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14993 split and "num" is its length. lo_half and hi_half are output arrays
14994 that parallel "operands". */
14996 void
14999 {
15004 {
15013 }
15018 {
15021 /* simplify_subreg refuse to split volatile memory addresses,
15022 but we still have to handle it. */
15024 {
15027 }
15028 else
15029 {
15036 }
15037 }
15038 }
15039 \f
15040 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15041 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15042 is the expression of the binary operation. The output may either be
15043 emitted here, or returned to the caller, like all output_* functions.
15045 There is no guarantee that the operands are the same mode, as they
15046 might be within FLOAT or FLOAT_EXTEND expressions. */
15048 #ifndef SYSV386_COMPAT
15049 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15050 wants to fix the assemblers because that causes incompatibility
15051 with gcc. No-one wants to fix gcc because that causes
15052 incompatibility with assemblers... You can use the option of
15053 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15054 #define SYSV386_COMPAT 1
15055 #endif
15059 {
15065 #ifdef ENABLE_CHECKING
15066 /* Even if we do not want to check the inputs, this documents input
15067 constraints. Which helps in understanding the following code. */
15077 else
15079 #endif
15082 {
15087 else
15096 else
15105 else
15114 else
15121 }
15124 {
15126 {
15130 else
15132 }
15133 else
15134 {
15138 else
15140 }
15142 }
15146 {
15150 {
15154 }
15156 /* know operands[0] == operands[1]. */
15159 {
15162 }
15165 {
15167 /* How is it that we are storing to a dead operand[2]?
15168 Well, presumably operands[1] is dead too. We can't
15169 store the result to st(0) as st(0) gets popped on this
15170 instruction. Instead store to operands[2] (which I
15171 think has to be st(1)). st(1) will be popped later.
15172 gcc <= 2.8.1 didn't have this check and generated
15173 assembly code that the Unixware assembler rejected. */
15175 else
15178 }
15182 else
15189 {
15192 }
15195 {
15198 }
15201 {
15202 #if SYSV386_COMPAT
15203 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15204 derived assemblers, confusingly reverse the direction of
15205 the operation for fsub{r} and fdiv{r} when the
15206 destination register is not st(0). The Intel assembler
15207 doesn't have this brain damage. Read !SYSV386_COMPAT to
15208 figure out what the hardware really does. */
15211 else
15213 #else
15215 /* As above for fmul/fadd, we can't store to st(0). */
15217 else
15219 #endif
15221 }
15224 {
15225 #if SYSV386_COMPAT
15228 else
15230 #else
15233 else
15235 #endif
15237 }
15240 {
15243 else
15246 }
15248 {
15249 #if SYSV386_COMPAT
15251 #else
15253 #endif
15254 }
15255 else
15256 {
15257 #if SYSV386_COMPAT
15259 #else
15261 #endif
15262 }
15267 }
15271 }
15273 /* Check if a 256bit AVX register is referenced inside of EXP. */
15275 static int
15277 {
15288 }
15290 /* Return needed mode for entity in optimize_mode_switching pass. */
15292 static int
15294 {
15296 {
15297 rtx link;
15299 /* Needed mode is set to AVX_U128_CLEAN if there are
15300 no 256bit modes used in function arguments. */
15302 link;
15304 {
15306 {
15311 }
15312 }
15315 }
15317 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15318 changes state only when a 256bit register is written to, but we need
15319 to prevent the compiler from moving optimal insertion point above
15320 eventual read from 256bit register. */
15325 }
15327 /* Return mode that i387 must be switched into
15328 prior to the execution of insn. */
15330 static int
15332 {
15335 /* The mode UNINITIALIZED is used to store control word after a
15336 function call or ASM pattern. The mode ANY specify that function
15337 has no requirements on the control word and make no changes in the
15338 bits we are interested in. */
15352 {
15375 }
15378 }
15380 /* Return mode that entity must be switched into
15381 prior to the execution of insn. */
15383 int
15385 {
15387 {
15397 }
15399 }
15401 /* Check if a 256bit AVX register is referenced in stores. */
15403 static void
15405 {
15407 {
15410 }
15411 }
15413 /* Calculate mode of upper 128bit AVX registers after the insn. */
15415 static int
15417 {
15424 /* We know that state is clean after CALL insn if there are no
15425 256bit registers used in the function return register. */
15427 {
15432 }
15434 /* Otherwise, return current mode. Remember that if insn
15435 references AVX 256bit registers, the mode was already changed
15436 to DIRTY from MODE_NEEDED. */
15438 }
15440 /* Return the mode that an insn results in. */
15442 int
15444 {
15446 {
15456 }
15457 }
15459 static int
15461 {
15462 tree arg;
15464 /* Entry mode is set to AVX_U128_DIRTY if there are
15465 256bit modes used in function arguments. */
15468 {
15473 }
15476 }
15478 /* Return a mode that ENTITY is assumed to be
15479 switched to at function entry. */
15481 int
15483 {
15485 {
15495 }
15496 }
15498 static int
15500 {
15503 /* Exit mode is set to AVX_U128_DIRTY if there are
15504 256bit modes used in the function return register. */
15509 }
15511 /* Return a mode that ENTITY is assumed to be
15512 switched to at function exit. */
15514 int
15516 {
15518 {
15528 }
15529 }
15531 /* Output code to initialize control word copies used by trunc?f?i and
15532 rounding patterns. CURRENT_MODE is set to current control word,
15533 while NEW_MODE is set to new control word. */
15535 static void
15537 {
15539 rtx new_mode;
15550 {
15552 {
15554 /* round toward zero (truncate) */
15560 /* round down toward -oo */
15567 /* round up toward +oo */
15574 /* mask precision exception for nearbyint() */
15581 }
15582 }
15583 else
15584 {
15586 {
15588 /* round toward zero (truncate) */
15594 /* round down toward -oo */
15600 /* round up toward +oo */
15606 /* mask precision exception for nearbyint() */
15613 }
15614 }
15620 }
15622 /* Emit vzeroupper. */
15624 void
15626 {
15629 /* Cancel automatic vzeroupper insertion if there are
15630 live call-saved SSE registers at the insertion point. */
15642 }
15644 /* Generate one or more insns to set ENTITY to MODE. */
15646 void
15648 {
15650 {
15665 }
15666 }
15668 /* Output code for INSN to convert a float to a signed int. OPERANDS
15669 are the insn operands. The output may be [HSD]Imode and the input
15670 operand may be [SDX]Fmode. */
15674 {
15679 /* Jump through a hoop or two for DImode, since the hardware has no
15680 non-popping instruction. We used to do this a different way, but
15681 that was somewhat fragile and broke with post-reload splitters. */
15691 else
15692 {
15697 else
15701 }
15704 }
15706 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15707 have the values zero or one, indicates the ffreep insn's operand
15708 from the OPERANDS array. */
15712 {
15714 #ifdef HAVE_AS_IX86_FFREEP
15716 #else
15717 {
15727 }
15728 #endif
15731 }
15734 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15735 should be used. UNORDERED_P is true when fucom should be used. */
15739 {
15745 {
15748 }
15749 else
15750 {
15753 }
15756 {
15760 else
15762 else
15765 else
15767 }
15774 {
15776 {
15779 }
15780 else
15782 }
15785 && stack_top_dies
15788 {
15789 /* If both the top of the 387 stack dies, and the other operand
15790 is also a stack register that dies, then this must be a
15791 `fcompp' float compare */
15794 {
15795 /* There is no double popping fcomi variant. Fortunately,
15796 eflags is immune from the fstp's cc clobbering. */
15799 else
15802 }
15803 else
15804 {
15807 else
15809 }
15810 }
15811 else
15812 {
15813 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15816 {
15824 NULL,
15825 NULL,
15832 NULL,
15833 NULL,
15834 NULL,
15835 NULL
15836 };
15851 }
15852 }
15854 void
15856 {
15859 #ifdef ASM_QUAD
15862 #else
15864 #endif
15867 }
15869 void
15871 {
15874 #ifdef ASM_QUAD
15877 #else
15879 #endif
15880 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15886 #if TARGET_MACHO
15888 {
15892 }
15893 #endif
15894 else
15897 }
15898 \f
15899 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15900 for the target. */
15902 void
15904 {
15905 rtx tmp;
15907 /* We play register width games, which are only valid after reload. */
15910 /* Avoid HImode and its attendant prefix byte. */
15915 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15917 {
15920 }
15923 }
15925 /* X is an unchanging MEM. If it is a constant pool reference, return
15926 the constant pool rtx, else NULL. */
15928 rtx
15930 {
15937 }
15939 void
15941 {
15949 {
15952 {
15958 }
15962 }
15966 {
15979 {
15986 }
15987 }
15991 {
15993 {
15994 #if TARGET_MACHO
15995 /* dynamic-no-pic */
15997 {
15998 rtx temp = ((reload_in_progress
16006 }
16008 {
16012 }
16015 else
16016 {
16024 }
16025 /* dynamic-no-pic */
16026 #endif
16027 }
16028 else
16029 {
16033 {
16039 }
16040 }
16041 }
16042 else
16043 {
16054 /* Force large constants in 64bit compilation into register
16055 to get them CSEed. */
16067 {
16068 /* If we are loading a floating point constant to a register,
16069 force the value to memory now, since we'll get better code
16070 out the back end. */
16074 {
16079 }
16080 }
16081 }
16084 }
16086 void
16088 {
16092 /* Force constants other than zero into memory. We do not know how
16093 the instructions used to build constants modify the upper 64 bits
16094 of the register, once we have that information we may be able
16095 to handle some of them more efficiently. */
16104 /* We need to check memory alignment for SSE mode since attribute
16105 can make operands unaligned. */
16110 {
16113 /* ix86_expand_vector_move_misalign() does not like constants ... */
16119 /* ... nor both arguments in memory. */
16127 }
16129 /* Make operand1 a register if it isn't already. */
16133 {
16136 }
16139 }
16141 /* Split 32-byte AVX unaligned load and store if needed. */
16143 static void
16145 {
16146 rtx m;
16153 {
16174 }
16177 {
16179 {
16186 }
16187 else
16189 }
16191 {
16193 {
16198 }
16199 else
16201 }
16202 else
16204 }
16206 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16207 straight to ix86_expand_vector_move. */
16208 /* Code generation for scalar reg-reg moves of single and double precision data:
16209 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16210 movaps reg, reg
16211 else
16212 movss reg, reg
16213 if (x86_sse_partial_reg_dependency == true)
16214 movapd reg, reg
16215 else
16216 movsd reg, reg
16218 Code generation for scalar loads of double precision data:
16219 if (x86_sse_split_regs == true)
16220 movlpd mem, reg (gas syntax)
16221 else
16222 movsd mem, reg
16224 Code generation for unaligned packed loads of single precision data
16225 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16226 if (x86_sse_unaligned_move_optimal)
16227 movups mem, reg
16229 if (x86_sse_partial_reg_dependency == true)
16230 {
16231 xorps reg, reg
16232 movlps mem, reg
16233 movhps mem+8, reg
16234 }
16235 else
16236 {
16237 movlps mem, reg
16238 movhps mem+8, reg
16239 }
16241 Code generation for unaligned packed loads of double precision data
16242 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16243 if (x86_sse_unaligned_move_optimal)
16244 movupd mem, reg
16246 if (x86_sse_split_regs == true)
16247 {
16248 movlpd mem, reg
16249 movhpd mem+8, reg
16250 }
16251 else
16252 {
16253 movsd mem, reg
16254 movhpd mem+8, reg
16255 }
16256 */
16258 void
16260 {
16268 {
16270 {
16275 /* FALLTHRU */
16283 }
16286 }
16289 {
16290 /* ??? If we have typed data, then it would appear that using
16291 movdqu is the only way to get unaligned data loaded with
16292 integer type. */
16294 {
16297 /* We will eventually emit movups based on insn attributes. */
16299 }
16301 {
16302 rtx zero;
16305 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16306 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16308 {
16309 /* We will eventually emit movups based on insn attributes. */
16312 }
16314 /* When SSE registers are split into halves, we can avoid
16315 writing to the top half twice. */
16317 {
16320 }
16321 else
16322 {
16323 /* ??? Not sure about the best option for the Intel chips.
16324 The following would seem to satisfy; the register is
16325 entirely cleared, breaking the dependency chain. We
16326 then store to the upper half, with a dependency depth
16327 of one. A rumor has it that Intel recommends two movsd
16328 followed by an unpacklpd, but this is unconfirmed. And
16329 given that the dependency depth of the unpacklpd would
16330 still be one, I'm not sure why this would be better. */
16332 }
16338 }
16339 else
16340 {
16342 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16343 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16345 {
16350 }
16354 else
16364 }
16365 }
16367 {
16369 {
16372 /* We will eventually emit movups based on insn attributes. */
16374 }
16376 {
16378 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16379 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16381 /* We will eventually emit movups based on insn attributes. */
16383 else
16384 {
16389 }
16390 }
16391 else
16392 {
16397 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16398 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16400 {
16403 }
16404 else
16405 {
16410 }
16411 }
16412 }
16413 else
16415 }
16417 /* Expand a push in MODE. This is some mode for which we do not support
16418 proper push instructions, at least from the registers that we expect
16419 the value to live in. */
16421 void
16423 {
16424 rtx tmp;
16434 /* When we push an operand onto stack, it has to be aligned at least
16435 at the function argument boundary. However since we don't have
16436 the argument type, we can't determine the actual argument
16437 boundary. */
16439 }
16441 /* Helper function of ix86_fixup_binary_operands to canonicalize
16442 operand order. Returns true if the operands should be swapped. */
16444 static bool
16446 rtx operands[])
16447 {
16452 /* If the operation is not commutative, we can't do anything. */
16456 /* Highest priority is that src1 should match dst. */
16462 /* Next highest priority is that immediate constants come second. */
16468 /* Lowest priority is that memory references should come second. */
16475 }
16478 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16479 destination to use for the operation. If different from the true
16480 destination in operands[0], a copy operation will be required. */
16482 rtx
16484 rtx operands[])
16485 {
16490 /* Canonicalize operand order. */
16492 {
16493 rtx temp;
16495 /* It is invalid to swap operands of different modes. */
16501 }
16503 /* Both source operands cannot be in memory. */
16505 {
16506 /* Optimization: Only read from memory once. */
16508 {
16511 }
16512 else
16514 }
16516 /* If the destination is memory, and we do not have matching source
16517 operands, do things in registers. */
16521 /* Source 1 cannot be a constant. */
16525 /* Source 1 cannot be a non-matching memory. */
16529 /* Improve address combine. */
16538 }
16540 /* Similarly, but assume that the destination has already been
16541 set up properly. */
16543 void
16546 {
16549 }
16551 /* Attempt to expand a binary operator. Make the expansion closer to the
16552 actual machine, then just general_operand, which will allow 3 separate
16553 memory references (one output, two input) in a single insn. */
16555 void
16557 rtx operands[])
16558 {
16565 /* Emit the instruction. */
16569 {
16570 /* Reload doesn't know about the flags register, and doesn't know that
16571 it doesn't want to clobber it. We can only do this with PLUS. */
16574 }
16578 {
16579 /* This is going to be an LEA; avoid splitting it later. */
16581 }
16582 else
16583 {
16586 }
16588 /* Fix up the destination if needed. */
16591 }
16593 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16594 the given OPERANDS. */
16596 void
16598 rtx operands[])
16599 {
16602 {
16605 }
16607 {
16610 }
16611 /* Optimize (__m128i) d | (__m128i) e and similar code
16612 when d and e are float vectors into float vector logical
16613 insn. In C/C++ without using intrinsics there is no other way
16614 to express vector logical operation on float vectors than
16615 to cast them temporarily to integer vectors. */
16617 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16626 {
16627 rtx dst;
16629 {
16636 {
16639 }
16640 else
16641 {
16646 }
16657 }
16658 }
16667 }
16669 /* Return TRUE or FALSE depending on whether the binary operator meets the
16670 appropriate constraints. */
16672 bool
16675 {
16680 /* Both source operands cannot be in memory. */
16684 /* Canonicalize operand order for commutative operators. */
16686 {
16690 }
16692 /* If the destination is memory, we must have a matching source operand. */
16696 /* Source 1 cannot be a constant. */
16700 /* Source 1 cannot be a non-matching memory. */
16702 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16710 }
16712 /* Attempt to expand a unary operator. Make the expansion closer to the
16713 actual machine, then just general_operand, which will allow 2 separate
16714 memory references (one output, one input) in a single insn. */
16716 void
16718 rtx operands[])
16719 {
16726 /* If the destination is memory, and we do not have matching source
16727 operands, do things in registers. */
16730 {
16733 else
16735 }
16737 /* When source operand is memory, destination must match. */
16741 /* Emit the instruction. */
16745 {
16746 /* Reload doesn't know about the flags register, and doesn't know that
16747 it doesn't want to clobber it. */
16750 }
16751 else
16752 {
16755 }
16757 /* Fix up the destination if needed. */
16760 }
16762 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16763 divisor are within the range [0-255]. */
16765 void
16768 {
16777 {
16790 }
16797 /* Use 8bit unsigned divimod if dividend and divisor are within
16798 the range [0-255]. */
16807 pc_rtx);
16812 /* Generate original signed/unsigned divimod. */
16817 /* Branch to the end. */
16821 /* Generate 8bit unsigned divide. */
16823 /* Don't use operands[0] for result of 8bit divide since not all
16824 registers support QImode ZERO_EXTRACT. */
16831 {
16834 }
16835 else
16836 {
16839 }
16841 /* Extract remainder from AH. */
16845 else
16846 {
16847 /* Need a new scratch register since the old one has result
16848 of 8bit divide. */
16852 }
16855 /* Zero extend quotient from AL. */
16861 }
16863 #define LEA_MAX_STALL (3)
16864 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16866 /* Increase given DISTANCE in half-cycles according to
16867 dependencies between PREV and NEXT instructions.
16868 Add 1 half-cycle if there is no dependency and
16869 go to next cycle if there is some dependecy. */
16871 static unsigned int
16873 {
16890 }
16892 /* Function checks if instruction INSN defines register number
16893 REGNO1 or REGNO2. */
16895 static bool
16897 rtx insn)
16898 {
16906 {
16908 }
16911 }
16913 /* Function checks if instruction INSN uses register number
16914 REGNO as a part of address expression. */
16916 static bool
16918 {
16926 }
16928 /* Search backward for non-agu definition of register number REGNO1
16929 or register number REGNO2 in basic block starting from instruction
16930 START up to head of basic block or instruction INSN.
16932 Function puts true value into *FOUND var if definition was found
16933 and false otherwise.
16935 Distance in half-cycles between START and found instruction or head
16936 of BB is added to DISTANCE and returned. */
16938 static int
16942 {
16952 {
16954 {
16957 {
16960 {
16963 }
16964 }
16967 }
16972 }
16975 }
16977 /* Search backward for non-agu definition of register number REGNO1
16978 or register number REGNO2 in INSN's basic block until
16979 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16980 2. Reach neighbour BBs boundary, or
16981 3. Reach agu definition.
16982 Returns the distance between the non-agu definition point and INSN.
16983 If no definition point, returns -1. */
16985 static int
16987 rtx insn)
16988 {
16999 {
17000 edge e;
17001 edge_iterator ei;
17006 {
17009 }
17015 else
17016 {
17021 {
17022 int bb_dist
17028 {
17035 }
17036 }
17039 }
17040 }
17042 /* get_attr_type may modify recog data. We want to make sure
17043 that recog data is valid for instruction INSN, on which
17044 distance_non_agu_define is called. INSN is unchanged here. */
17051 }
17053 /* Return the distance in half-cycles between INSN and the next
17054 insn that uses register number REGNO in memory address added
17055 to DISTANCE. Return -1 if REGNO0 is set.
17057 Put true value into *FOUND if register usage was found and
17058 false otherwise.
17059 Put true value into *REDEFINED if register redefinition was
17060 found and false otherwise. */
17062 static int
17066 {
17077 {
17079 {
17082 {
17083 /* Return DISTANCE if OP0 is used in memory
17084 address in NEXT. */
17087 }
17090 {
17091 /* Return -1 if OP0 is set in NEXT. */
17094 }
17097 }
17103 }
17106 }
17108 /* Return the distance between INSN and the next insn that uses
17109 register number REGNO0 in memory address. Return -1 if no such
17110 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17112 static int
17114 {
17126 {
17127 edge e;
17128 edge_iterator ei;
17133 {
17136 }
17142 else
17143 {
17149 {
17150 int bb_dist
17155 {
17162 }
17163 }
17166 }
17167 }
17173 }
17175 /* Define this macro to tune LEA priority vs ADD, it take effect when
17176 there is a dilemma of choicing LEA or ADD
17177 Negative value: ADD is more preferred than LEA
17178 Zero: Netrual
17179 Positive value: LEA is more preferred than ADD*/
17180 #define IX86_LEA_PRIORITY 0
17182 /* Return true if usage of lea INSN has performance advantage
17183 over a sequence of instructions. Instructions sequence has
17184 SPLIT_COST cycles higher latency than lea latency. */
17186 static bool
17189 {
17196 {
17197 /* If there is no non AGU operand definition, no AGU
17198 operand usage and split cost is 0 then both lea
17199 and non lea variants have same priority. Currently
17200 we prefer lea for 64 bit code and non lea on 32 bit
17201 code. */
17204 else
17206 }
17208 /* With longer definitions distance lea is more preferable.
17209 Here we change it to take into account splitting cost and
17210 lea priority. */
17213 /* If there is no use in memory addess then we just check
17214 that split cost exceeds AGU stall. */
17218 /* If this insn has both backward non-agu dependence and forward
17219 agu dependence, the one with short distance takes effect. */
17221 }
17223 /* Return true if it is legal to clobber flags by INSN and
17224 false otherwise. */
17226 static bool
17228 {
17231 bitmap live;
17234 {
17236 {
17243 }
17249 }
17253 }
17255 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17256 move and add to avoid AGU stalls. */
17258 bool
17260 {
17263 /* Check if we need to optimize. */
17267 /* Check it is correct to split here. */
17275 /* We need to split only adds with non destructive
17276 destination operand. */
17279 else
17281 }
17283 /* Return true if we should emit lea instruction instead of mov
17284 instruction. */
17286 bool
17288 {
17291 /* Check if we need to optimize. */
17295 /* Use lea for reg to reg moves only. */
17303 }
17305 /* Return true if we need to split lea into a sequence of
17306 instructions to avoid AGU stalls. */
17308 bool
17310 {
17316 /* Check we need to optimize. */
17320 /* Check it is correct to split here. */
17327 /* There should be at least two components in the address. */
17332 /* We should not split into add if non legitimate pic
17333 operand is used as displacement. */
17348 /* Compute how many cycles we will add to execution time
17349 if split lea into a sequence of instructions. */
17351 {
17352 /* Have to use mov instruction if non desctructive
17353 destination form is used. */
17357 /* Have to add index to base if both exist. */
17361 /* Have to use shift and adds if scale is 2 or greater. */
17363 {
17368 else
17370 }
17372 /* Have to use add instruction with immediate if
17373 disp is non zero. */
17377 /* Subtract the price of lea. */
17379 }
17382 }
17384 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17385 matches destination. RTX includes clobber of FLAGS_REG. */
17387 static void
17390 {
17397 }
17399 /* Return true if regno1 def is nearest to the insn. */
17401 static bool
17403 {
17410 {
17412 {
17415 }
17421 }
17423 /* None of the regs is defined in the bb. */
17425 }
17427 /* Split lea instructions into a sequence of instructions
17428 which are executed on ALU to avoid AGU stalls.
17429 It is assumed that it is allowed to clobber flags register
17430 at lea position. */
17432 void
17434 {
17450 {
17453 }
17456 {
17459 }
17465 {
17466 /* Case r1 = r1 + ... */
17468 {
17469 /* If we have a case r1 = r1 + C * r1 then we
17470 should use multiplication which is very
17471 expensive. Assume cost model is wrong if we
17472 have such case here. */
17477 }
17478 else
17479 {
17480 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17484 /* Use shift for scaling. */
17493 }
17494 }
17496 {
17499 }
17500 else
17501 {
17503 {
17506 }
17508 {
17511 }
17512 else
17513 {
17518 else
17519 {
17520 rtx tmp1;
17522 /* Find better operand for SET instruction, depending
17523 on which definition is farther from the insn. */
17526 else
17536 }
17539 }
17543 }
17544 }
17546 /* Return true if it is ok to optimize an ADD operation to LEA
17547 operation to avoid flag register consumation. For most processors,
17548 ADD is faster than LEA. For the processors like ATOM, if the
17549 destination register of LEA holds an actual address which will be
17550 used soon, LEA is better and otherwise ADD is better. */
17552 bool
17554 {
17559 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17567 }
17569 /* Return true if destination reg of SET_BODY is shift count of
17570 USE_BODY. */
17572 static bool
17574 {
17575 rtx set_dest;
17576 rtx shift_rtx;
17579 /* Retrieve destination of SET_BODY. */
17581 {
17590 use_body))
17595 }
17597 /* Retrieve shift count of USE_BODY. */
17599 {
17611 }
17619 {
17622 /* Return true if shift count is dest of SET_BODY. */
17624 {
17625 /* Add check since it can be invoked before register
17626 allocation in pre-reload schedule. */
17632 }
17633 }
17636 }
17638 /* Return true if destination reg of SET_INSN is shift count of
17639 USE_INSN. */
17641 bool
17643 {
17646 }
17648 /* Return TRUE or FALSE depending on whether the unary operator meets the
17649 appropriate constraints. */
17651 bool
17655 {
17656 /* If one of operands is memory, source and destination must match. */
17662 }
17664 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17665 are ok, keeping in mind the possible movddup alternative. */
17667 bool
17669 {
17675 }
17677 /* Post-reload splitter for converting an SF or DFmode value in an
17678 SSE register into an unsigned SImode. */
17680 void
17682 {
17693 /* Load up the value into the low element. We must ensure that the other
17694 elements are valid floats -- zero is the easiest such value. */
17696 {
17699 else
17701 }
17702 else
17703 {
17708 else
17710 }
17730 else
17735 }
17737 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17738 Expects the 64-bit DImode to be supplied in a pair of integral
17739 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17740 -mfpmath=sse, !optimize_size only. */
17742 void
17744 {
17748 rtx x;
17754 {
17757 }
17758 else
17759 {
17763 }
17771 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17774 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17775 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17776 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17777 (0x1.0p84 + double(fp_value_hi_xmm)).
17778 Note these exponents differ by 32. */
17782 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17783 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17792 /* Add the upper and lower DFmode values together. */
17795 else
17796 {
17800 }
17803 }
17805 /* Not used, but eases macroization of patterns. */
17806 void
17808 rtx input ATTRIBUTE_UNUSED)
17809 {
17811 }
17813 /* Convert an unsigned SImode value into a DFmode. Only currently used
17814 for SSE, but applicable anywhere. */
17816 void
17818 {
17819 REAL_VALUE_TYPE TWO31r;
17834 }
17836 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17837 32-bit mode; otherwise we have a direct convert instruction. */
17839 void
17841 {
17842 REAL_VALUE_TYPE TWO32r;
17860 }
17862 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17863 For x86_32, -mfpmath=sse, !optimize_size only. */
17864 void
17866 {
17867 REAL_VALUE_TYPE ONE16r;
17886 }
17888 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
17889 a vector of unsigned ints VAL to vector of floats TARGET. */
17891 void
17893 {
17895 REAL_VALUE_TYPE TWO16r;
17902 else
17907 OPTAB_DIRECT);
17918 OPTAB_DIRECT);
17920 OPTAB_DIRECT);
17923 }
17925 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
17926 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
17927 This is done by doing just signed conversion if < 0x1p31, and otherwise by
17928 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
17930 rtx
17932 {
17933 REAL_VALUE_TYPE TWO31r;
17948 {
17954 }
17963 OPTAB_DIRECT);
17964 else
17965 {
17971 OPTAB_DIRECT);
17972 }
17975 }
17977 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
17978 then replicate the value for all elements of the vector
17979 register. */
17981 rtx
17983 {
17985 rtvec v;
17989 {
18016 }
18017 }
18019 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18020 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18021 for an SSE register. If VECT is true, then replicate the mask for
18022 all elements of the vector register. If INVERT is true, then create
18023 a mask excluding the sign bit. */
18025 rtx
18027 {
18031 rtx v;
18032 rtx mask;
18034 /* Find the sign bit, sign extended to 2*HWI. */
18036 {
18056 else
18064 {
18067 }
18068 else
18069 {
18070 rtvec vec;
18076 {
18079 }
18080 else
18090 }
18095 }
18100 /* Force this value into the low part of a fp vector constant. */
18109 }
18111 /* Generate code for floating point ABS or NEG. */
18113 void
18115 rtx operands[])
18116 {
18127 {
18133 }
18135 /* NEG and ABS performed with SSE use bitwise mask operations.
18136 Create the appropriate mask now. */
18139 else
18149 {
18151 rtvec par;
18156 else
18157 {
18160 }
18162 }
18163 else
18165 }
18167 /* Expand a copysign operation. Special case operand 0 being a constant. */
18169 void
18171 {
18185 else
18189 {
18196 {
18199 else
18200 {
18204 }
18205 }
18215 else
18219 }
18220 else
18221 {
18231 else
18235 }
18236 }
18238 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18239 be a constant, and so has already been expanded into a vector constant. */
18241 void
18243 {
18259 {
18262 }
18263 }
18265 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18266 so we have to do two masks. */
18268 void
18270 {
18285 {
18286 /* Shouldn't happen often (it's useless, obviously), but when it does
18287 we'd generate incorrect code if we continue below. */
18290 }
18293 {
18304 }
18305 else
18306 {
18308 {
18310 }
18312 {
18316 }
18320 {
18323 }
18325 {
18330 }
18332 }
18336 }
18338 /* Return TRUE or FALSE depending on whether the first SET in INSN
18339 has source and destination with matching CC modes, and that the
18340 CC mode is at least as constrained as REQ_MODE. */
18342 bool
18344 {
18345 rtx set;
18356 {
18366 /* FALLTHRU */
18370 /* FALLTHRU */
18374 /* FALLTHRU */
18388 }
18391 }
18393 /* Generate insn patterns to do an integer compare of OPERANDS. */
18395 static rtx
18397 {
18404 /* This is very simple, but making the interface the same as in the
18405 FP case makes the rest of the code easier. */
18409 /* Return the test that should be put into the flags user, i.e.
18410 the bcc, scc, or cmov instruction. */
18412 }
18414 /* Figure out whether to use ordered or unordered fp comparisons.
18415 Return the appropriate mode to use. */
18417 enum machine_mode
18419 {
18420 /* ??? In order to make all comparisons reversible, we do all comparisons
18421 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18422 all forms trapping and nontrapping comparisons, we can make inequality
18423 comparisons trapping again, since it results in better code when using
18424 FCOM based compares. */
18426 }
18428 enum machine_mode
18430 {
18434 {
18437 }
18440 {
18441 /* Only zero flag is needed. */
18445 /* Codes needing carry flag. */
18448 /* Detect overflow checks. They need just the carry flag. */
18452 else
18456 /* Detect overflow checks. They need just the carry flag. */
18460 else
18462 /* Codes possibly doable only with sign flag when
18463 comparing against zero. */
18468 else
18469 /* For other cases Carry flag is not required. */
18471 /* Codes doable only with sign flag when comparing
18472 against zero, but we miss jump instruction for it
18473 so we need to use relational tests against overflow
18474 that thus needs to be zero. */
18479 else
18481 /* strcmp pattern do (use flags) and combine may ask us for proper
18482 mode. */
18487 }
18488 }
18490 /* Return the fixed registers used for condition codes. */
18492 static bool
18494 {
18498 }
18500 /* If two condition code modes are compatible, return a condition code
18501 mode which is compatible with both. Otherwise, return
18502 VOIDmode. */
18504 static enum machine_mode
18506 {
18523 {
18537 {
18551 }
18555 /* These are only compatible with themselves, which we already
18556 checked above. */
18558 }
18559 }
18562 /* Return a comparison we can do and that it is equivalent to
18563 swap_condition (code) apart possibly from orderedness.
18564 But, never change orderedness if TARGET_IEEE_FP, returning
18565 UNKNOWN in that case if necessary. */
18567 static enum rtx_code
18569 {
18571 {
18582 }
18583 }
18585 /* Return cost of comparison CODE using the best strategy for performance.
18586 All following functions do use number of instructions as a cost metrics.
18587 In future this should be tweaked to compute bytes for optimize_size and
18588 take into account performance of various instructions on various CPUs. */
18590 static int
18592 {
18595 /* The cost of code using bit-twiddling on %ah. */
18597 {
18620 }
18623 {
18630 }
18631 }
18633 /* Return strategy to use for floating-point. We assume that fcomi is always
18634 preferrable where available, since that is also true when looking at size
18635 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18637 enum ix86_fpcmp_strategy
18639 {
18640 /* Do fcomi/sahf based test when profitable. */
18649 }
18651 /* Swap, force into registers, or otherwise massage the two operands
18652 to a fp comparison. The operands are updated in place; the new
18653 comparison code is returned. */
18655 static enum rtx_code
18657 {
18663 /* All of the unordered compare instructions only work on registers.
18664 The same is true of the fcomi compare instructions. The XFmode
18665 compare instructions require registers except when comparing
18666 against zero or when converting operand 1 from fixed point to
18667 floating point. */
18676 {
18679 }
18680 else
18681 {
18682 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18683 things around if they appear profitable, otherwise force op0
18684 into a register. */
18690 {
18693 {
18694 rtx tmp;
18697 }
18698 }
18704 {
18709 {
18712 }
18713 else
18715 }
18716 }
18718 /* Try to rearrange the comparison to make it cheaper. */
18722 {
18723 rtx tmp;
18728 }
18733 }
18735 /* Convert comparison codes we use to represent FP comparison to integer
18736 code that will result in proper branch. Return UNKNOWN if no such code
18737 is available. */
18739 enum rtx_code
18741 {
18743 {
18766 }
18767 }
18769 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18771 static rtx
18773 {
18780 /* Do fcomi/sahf based test when profitable. */
18782 {
18787 tmp);
18795 tmp);
18804 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18811 /* In the unordered case, we have to check C2 for NaN's, which
18812 doesn't happen to work out to anything nice combination-wise.
18813 So do some bit twiddling on the value we've got in AH to come
18814 up with an appropriate set of condition codes. */
18818 {
18822 {
18825 }
18826 else
18827 {
18833 }
18838 {
18843 }
18844 else
18845 {
18848 }
18853 {
18856 }
18857 else
18858 {
18862 }
18867 {
18873 }
18874 else
18875 {
18878 }
18883 {
18888 }
18889 else
18890 {
18893 }
18898 {
18903 }
18904 else
18905 {
18908 }
18922 }
18927 }
18929 /* Return the test that should be put into the flags user, i.e.
18930 the bcc, scc, or cmov instruction. */
18933 const0_rtx);
18934 }
18936 static rtx
18938 {
18939 rtx ret;
18945 {
18948 }
18949 else
18953 }
18955 void
18957 {
18959 rtx tmp;
18962 {
18969 simple:
18973 pc_rtx);
18981 /* Expand DImode branch into multiple compare+branch. */
18982 {
18988 {
18991 }
18998 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
18999 avoid two branches. This costs one extra insn, so disable when
19000 optimizing for size. */
19005 {
19023 }
19025 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19026 op1 is a constant and the low word is zero, then we can just
19027 examine the high word. Similarly for low word -1 and
19028 less-or-equal-than or greater-than. */
19032 {
19035 {
19038 }
19042 {
19045 }
19049 }
19051 /* Otherwise, we need two or three jumps. */
19060 {
19074 }
19076 /*
19077 * a < b =>
19078 * if (hi(a) < hi(b)) goto true;
19079 * if (hi(a) > hi(b)) goto false;
19080 * if (lo(a) < lo(b)) goto true;
19081 * false:
19082 */
19094 }
19099 }
19100 }
19102 /* Split branch based on floating point condition. */
19103 void
19106 {
19107 rtx condition;
19108 rtx i;
19111 {
19116 }
19119 tmp);
19121 /* Remove pushed operand from stack. */
19131 }
19133 void
19135 {
19136 rtx ret;
19143 }
19145 /* Expand comparison setting or clearing carry flag. Return true when
19146 successful and set pop for the operation. */
19147 static bool
19149 {
19153 /* Do not handle double-mode compares that go through special path. */
19158 {
19163 /* Shortcut: following common codes never translate
19164 into carry flag compares. */
19169 /* These comparisons require zero flag; swap operands so they won't. */
19172 {
19177 }
19179 /* Try to expand the comparison and verify that we end up with
19180 carry flag based comparison. This fails to be true only when
19181 we decide to expand comparison using arithmetic that is not
19182 too common scenario. */
19191 else
19200 }
19206 {
19211 /* Convert a==0 into (unsigned)a<1. */
19220 /* Convert a>b into b<a or a>=b-1. */
19224 {
19226 /* Bail out on overflow. We still can swap operands but that
19227 would force loading of the constant into register. */
19232 }
19233 else
19234 {
19239 }
19242 /* Convert a>=0 into (unsigned)a<0x80000000. */
19260 }
19261 /* Swapping operands may cause constant to appear as first operand. */
19263 {
19267 }
19271 }
19273 bool
19275 {
19299 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19300 HImode insns, we'd be swallowed in word prefix ops. */
19306 {
19310 HOST_WIDE_INT diff;
19313 /* Sign bit compares are better done using shifts than we do by using
19314 sbb. */
19317 {
19318 /* Detect overlap between destination and compare sources. */
19322 {
19323 rtx flags;
19332 {
19334 compare_code
19336 }
19338 /* To simplify rest of code, restrict to the GEU case. */
19340 {
19346 }
19347 else
19348 {
19351 reverse_condition_maybe_unordered
19353 else
19356 }
19365 else
19368 }
19369 else
19370 {
19373 else
19374 {
19379 }
19381 }
19384 {
19385 /*
19386 * cmpl op0,op1
19387 * sbbl dest,dest
19388 * [addl dest, ct]
19389 *
19390 * Size 5 - 8.
19391 */
19396 }
19398 {
19399 /*
19400 * cmpl op0,op1
19401 * sbbl dest,dest
19402 * orl $ct, dest
19403 *
19404 * Size 8.
19405 */
19409 }
19411 {
19412 /*
19413 * cmpl op0,op1
19414 * sbbl dest,dest
19415 * notl dest
19416 * [addl dest, cf]
19417 *
19418 * Size 8 - 11.
19419 */
19425 }
19426 else
19427 {
19428 /*
19429 * cmpl op0,op1
19430 * sbbl dest,dest
19431 * [notl dest]
19432 * andl cf - ct, dest
19433 * [addl dest, ct]
19434 *
19435 * Size 8 - 11.
19436 */
19439 {
19443 }
19453 }
19459 }
19462 {
19465 HOST_WIDE_INT tmp;
19470 {
19473 /* We may be reversing unordered compare to normal compare, that
19474 is not valid in general (we may convert non-trapping condition
19475 to trapping one), however on i386 we currently emit all
19476 comparisons unordered. */
19479 }
19480 else
19481 {
19484 }
19485 }
19490 {
19495 {
19500 }
19501 }
19503 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19507 {
19508 /* If lea code below could be used, only optimize
19509 if it results in a 2 insn sequence. */
19515 {
19516 /*
19517 * notl op1 (if necessary)
19518 * sarl $31, op1
19519 * orl cf, op1
19520 */
19522 {
19526 }
19537 }
19538 }
19546 {
19547 /*
19548 * xorl dest,dest
19549 * cmpl op1,op2
19550 * setcc dest
19551 * lea cf(dest*(ct-cf)),dest
19552 *
19553 * Size 14.
19554 *
19555 * This also catches the degenerate setcc-only case.
19556 */
19558 rtx tmp;
19564 /* On x86_64 the lea instruction operates on Pmode, so we need
19565 to get arithmetics done in proper mode to match. */
19568 else
19569 {
19570 rtx out1;
19573 nops++;
19575 {
19577 nops++;
19578 }
19579 }
19581 {
19583 nops++;
19584 }
19586 {
19589 else
19591 }
19596 }
19598 /*
19599 * General case: Jumpful:
19600 * xorl dest,dest cmpl op1, op2
19601 * cmpl op1, op2 movl ct, dest
19602 * setcc dest jcc 1f
19603 * decl dest movl cf, dest
19604 * andl (cf-ct),dest 1:
19605 * addl ct,dest
19606 *
19607 * Size 20. Size 14.
19608 *
19609 * This is reasonably steep, but branch mispredict costs are
19610 * high on modern cpus, so consider failing only if optimizing
19611 * for space.
19612 */
19617 {
19619 {
19626 {
19629 /* We may be reversing unordered compare to normal compare,
19630 that is not valid in general (we may convert non-trapping
19631 condition to trapping one), however on i386 we currently
19632 emit all comparisons unordered. */
19634 }
19635 else
19636 {
19640 }
19641 }
19644 {
19645 /* notl op1 (if needed)
19646 sarl $31, op1
19647 andl (cf-ct), op1
19648 addl ct, op1
19650 For x < 0 (resp. x <= -1) there will be no notl,
19651 so if possible swap the constants to get rid of the
19652 complement.
19653 True/false will be -1/0 while code below (store flag
19654 followed by decrement) is 0/-1, so the constants need
19655 to be exchanged once more. */
19658 {
19661 }
19662 else
19663 {
19667 }
19670 }
19671 else
19672 {
19676 constm1_rtx,
19678 }
19690 }
19691 }
19694 {
19695 /* Try a few things more with specific constants and a variable. */
19697 optab op;
19703 /* If one of the two operands is an interesting constant, load a
19704 constant with the above and mask it in with a logical operation. */
19707 {
19713 else
19715 }
19717 {
19723 else
19725 }
19726 else
19733 /* Recurse to get the constant loaded. */
19737 /* Mask in the interesting variable. */
19739 OPTAB_WIDEN);
19744 }
19746 /*
19747 * For comparison with above,
19748 *
19749 * movl cf,dest
19750 * movl ct,tmp
19751 * cmpl op1,op2
19752 * cmovcc tmp,dest
19753 *
19754 * Size 15.
19755 */
19777 }
19779 /* Swap, force into registers, or otherwise massage the two operands
19780 to an sse comparison with a mask result. Thus we differ a bit from
19781 ix86_prepare_fp_compare_args which expects to produce a flags result.
19783 The DEST operand exists to help determine whether to commute commutative
19784 operators. The POP0/POP1 operands are updated in place. The new
19785 comparison code is returned, or UNKNOWN if not implementable. */
19787 static enum rtx_code
19790 {
19791 rtx tmp;
19794 {
19797 /* AVX supports all the needed comparisons. */
19800 /* We have no LTGT as an operator. We could implement it with
19801 NE & ORDERED, but this requires an extra temporary. It's
19802 not clear that it's worth it. */
19809 /* These are supported directly. */
19816 /* AVX has 3 operand comparisons, no need to swap anything. */
19819 /* For commutative operators, try to canonicalize the destination
19820 operand to be first in the comparison - this helps reload to
19821 avoid extra moves. */
19824 /* FALLTHRU */
19830 /* These are not supported directly before AVX, and furthermore
19831 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19832 comparison operands to transform into something that is
19833 supported. */
19842 }
19845 }
19847 /* Detect conditional moves that exactly match min/max operational
19848 semantics. Note that this is IEEE safe, as long as we don't
19849 interchange the operands.
19851 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19852 and TRUE if the operation is successful and instructions are emitted. */
19854 static bool
19857 {
19860 rtx tmp;
19863 ;
19865 {
19869 }
19870 else
19877 else
19882 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
19883 but MODE may be a vector mode and thus not appropriate. */
19885 {
19887 rtvec v;
19892 }
19893 else
19894 {
19897 }
19901 }
19903 /* Expand an sse vector comparison. Return the register with the result. */
19905 static rtx
19908 {
19911 rtx x;
19924 {
19927 }
19928 else
19932 }
19934 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
19935 operations. This is used for both scalar and vector conditional moves. */
19937 static void
19939 {
19945 {
19947 }
19949 {
19953 }
19955 {
19960 }
19962 {
19966 }
19968 {
19976 op_true,
19977 op_false)));
19978 }
19979 else
19980 {
19989 {
20003 {
20009 }
20024 {
20030 }
20034 }
20038 else
20039 {
20045 else
20057 }
20058 }
20059 }
20061 /* Expand a floating-point conditional move. Return true if successful. */
20063 bool
20065 {
20073 {
20076 /* Since we've no cmove for sse registers, don't force bad register
20077 allocation just to gain access to it. Deny movcc when the
20078 comparison mode doesn't match the move mode. */
20097 }
20104 /* The floating point conditional move instructions don't directly
20105 support conditions resulting from a signed integer comparison. */
20109 {
20114 }
20121 }
20123 /* Expand a floating-point vector conditional move; a vcond operation
20124 rather than a movcc operation. */
20126 bool
20128 {
20130 rtx cmp;
20135 {
20136 rtx temp;
20138 {
20155 }
20157 OPTAB_DIRECT);
20160 }
20170 }
20172 /* Expand a signed/unsigned integral vector conditional move. */
20174 bool
20176 {
20186 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20187 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20196 {
20200 {
20206 }
20209 {
20215 }
20216 }
20225 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20229 ;
20230 else
20231 {
20232 /* Canonicalize the comparison to EQ, GT, GTU. */
20234 {
20251 /* FALLTHRU */
20261 }
20263 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20265 {
20267 {
20269 /* SSE4.1 supports EQ. */
20276 /* SSE4.2 supports GT/GTU. */
20283 }
20284 }
20286 /* Unsigned parallel compare is not supported by the hardware.
20287 Play some tricks to turn this into a signed comparison
20288 against 0. */
20290 {
20294 {
20299 {
20304 {
20311 }
20312 /* Subtract (-(INT MAX) - 1) from both operands to make
20313 them signed. */
20324 }
20331 /* Perform a parallel unsigned saturating subtraction. */
20344 }
20345 }
20346 }
20348 /* Allow the comparison to be done in one mode, but the movcc to
20349 happen in another mode. */
20351 {
20354 }
20355 else
20356 {
20362 }
20367 }
20369 /* Expand a variable vector permutation. */
20371 void
20373 {
20384 /* Number of elements in the vector. */
20390 {
20392 {
20393 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20394 an constant shuffle operand. With a tiny bit of effort we can
20395 use VPERMD instead. A re-interpretation stall for V4DFmode is
20396 unfortunate but there's no avoiding it.
20397 Similarly for V16HImode we don't have instructions for variable
20398 shuffling, while for V32QImode we can use after preparing suitable
20399 masks vpshufb; vpshufb; vpermq; vpor. */
20402 {
20406 }
20407 else
20408 {
20412 }
20415 /* Replicate the low bits of the V4DImode mask into V8SImode:
20416 mask = { A B C D }
20417 t1 = { A A B B C C D D }. */
20425 else
20428 /* Multiply the shuffle indicies by two. */
20430 OPTAB_DIRECT);
20432 /* Add one to the odd shuffle indicies:
20433 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20435 {
20438 }
20442 OPTAB_DIRECT);
20444 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20449 }
20452 {
20454 /* The VPERMD and VPERMPS instructions already properly ignore
20455 the high bits of the shuffle elements. No need for us to
20456 perform an AND ourselves. */
20459 else
20460 {
20466 }
20473 else
20474 {
20480 }
20484 /* By combining the two 128-bit input vectors into one 256-bit
20485 input vector, we can use VPERMD and VPERMPS for the full
20486 two-operand shuffle. */
20518 /* From mask create two adjusted masks, which contain the same
20519 bits as mask in the low 7 bits of each vector element.
20520 The first mask will have the most significant bit clear
20521 if it requests element from the same 128-bit lane
20522 and MSB set if it requests element from the other 128-bit lane.
20523 The second mask will have the opposite values of the MSB,
20524 and additionally will have its 128-bit lanes swapped.
20525 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20526 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20527 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20528 stands for other 12 bytes. */
20529 /* The bit whether element is from the same lane or the other
20530 lane is bit 4, so shift it up by 3 to the MSB position. */
20534 /* Clear MSB bits from the mask just in case it had them set. */
20536 /* After this t1 will have MSB set for elements from other lane. */
20538 /* Clear bits other than MSB. */
20540 /* Or in the lower bits from mask into t3. */
20542 /* And invert MSB bits in t1, so MSB is set for elements from the same
20543 lane. */
20545 /* Swap 128-bit lanes in t3. */
20550 /* And or in the lower bits from mask into t1. */
20553 {
20554 /* Each of these shuffles will put 0s in places where
20555 element from the other 128-bit lane is needed, otherwise
20556 will shuffle in the requested value. */
20559 /* For t3 the 128-bit lanes are swapped again. */
20564 /* And oring both together leads to the result. */
20567 }
20570 /* Similarly to the above one_operand_shuffle code,
20571 just for repeated twice for each operand. merge_two:
20572 code will merge the two results together. */
20594 }
20595 }
20598 {
20599 /* The XOP VPPERM insn supports three inputs. By ignoring the
20600 one_operand_shuffle special case, we avoid creating another
20601 set of constant vectors in memory. */
20604 /* mask = mask & {2*w-1, ...} */
20606 }
20607 else
20608 {
20609 /* mask = mask & {w-1, ...} */
20611 }
20619 /* For non-QImode operations, convert the word permutation control
20620 into a byte permutation control. */
20622 {
20627 /* Convert mask to vector of chars. */
20630 /* Replicate each of the input bytes into byte positions:
20631 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20632 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20633 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20640 else
20643 /* Convert it into the byte positions by doing
20644 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20650 }
20652 /* The actual shuffle operations all operate on V16QImode. */
20658 {
20660 }
20662 {
20664 }
20665 else
20666 {
20670 /* Shuffle the two input vectors independently. */
20676 merge_two:
20677 /* Then merge them together. The key is whether any given control
20678 element contained a bit set that indicates the second word. */
20682 {
20683 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20684 more shuffle to convert the V2DI input mask into a V4SI
20685 input mask. At which point the masking that expand_int_vcond
20686 will work as desired. */
20694 }
20711 }
20712 }
20714 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20715 true if we should do zero extension, else sign extension. HIGH_P is
20716 true if we want the N/2 high elements, else the low elements. */
20718 void
20720 {
20722 rtx tmp;
20725 {
20731 {
20735 else
20738 extract
20744 else
20747 extract
20753 else
20756 extract
20762 else
20768 else
20774 else
20779 }
20782 {
20785 }
20787 {
20788 /* Shift higher 8 bytes to lower 8 bytes. */
20793 }
20794 else
20798 }
20799 else
20800 {
20804 {
20808 else
20814 else
20820 else
20825 }
20829 else
20834 }
20835 }
20837 /* Expand conditional increment or decrement using adb/sbb instructions.
20838 The default case using setcc followed by the conditional move can be
20839 done by generic code. */
20840 bool
20842 {
20844 rtx flags;
20846 rtx compare_op;
20864 {
20867 }
20870 {
20874 reverse_condition_maybe_unordered
20876 else
20878 }
20882 /* Construct either adc or sbb insn. */
20884 {
20886 {
20901 }
20902 }
20903 else
20904 {
20906 {
20921 }
20922 }
20926 }
20929 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
20930 but works for floating pointer parameters and nonoffsetable memories.
20931 For pushes, it returns just stack offsets; the values will be saved
20932 in the right order. Maximally three parts are generated. */
20934 static int
20936 {
20941 else
20947 /* Optimize constant pool reference to immediates. This is used by fp
20948 moves, that force all constants to memory to allow combining. */
20950 {
20954 }
20957 {
20958 /* The only non-offsetable memories we handle are pushes. */
20967 }
20970 {
20972 /* Caution: if we looked through a constant pool memory above,
20973 the operand may actually have a different mode now. That's
20974 ok, since we want to pun this all the way back to an integer. */
20978 }
20981 {
20984 else
20985 {
20989 {
20993 }
20995 {
21000 }
21002 {
21003 REAL_VALUE_TYPE r;
21008 {
21015 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21016 long double may not be 80-bit. */
21025 }
21028 }
21029 else
21031 }
21032 }
21033 else
21034 {
21038 {
21041 {
21045 }
21047 {
21051 }
21053 {
21054 REAL_VALUE_TYPE r;
21060 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21063 = gen_int_mode
21066 DImode);
21067 else
21074 = gen_int_mode
21077 DImode);
21078 else
21080 }
21081 else
21083 }
21084 }
21087 }
21089 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21090 Return false when normal moves are needed; true when all required
21091 insns have been emitted. Operands 2-4 contain the input values
21092 int the correct order; operands 5-7 contain the output values. */
21094 void
21096 {
21104 /* The DFmode expanders may ask us to move double.
21105 For 64bit target this is single move. By hiding the fact
21106 here we simplify i386.md splitters. */
21108 {
21109 /* Optimize constant pool reference to immediates. This is used by
21110 fp moves, that force all constants to memory to allow combining. */
21117 {
21120 }
21121 else
21126 }
21128 /* The only non-offsettable memory we handle is push. */
21131 else
21138 /* When emitting push, take care for source operands on the stack. */
21141 {
21144 /* Compensate for the stack decrement by 4. */
21149 /* src_base refers to the stack pointer and is
21150 automatically decreased by emitted push. */
21154 }
21156 /* We need to do copy in the right order in case an address register
21157 of the source overlaps the destination. */
21159 {
21160 rtx tmp;
21163 {
21167 collisions++;
21168 }
21170 /* Collision in the middle part can be handled by reordering. */
21172 {
21175 }
21179 {
21181 {
21184 }
21185 else
21186 {
21189 }
21190 }
21192 /* If there are more collisions, we can't handle it by reordering.
21193 Do an lea to the last part and use only one colliding move. */
21195 {
21196 rtx base;
21202 /* Handle the case when the last part isn't valid for lea.
21203 Happens in 64-bit mode storing the 12-byte XFmode. */
21210 {
21213 }
21214 }
21215 }
21218 {
21220 {
21222 {
21227 }
21229 {
21232 }
21233 }
21234 else
21235 {
21236 /* In 64bit mode we don't have 32bit push available. In case this is
21237 register, it is OK - we will just use larger counterpart. We also
21238 retype memory - these comes from attempt to avoid REX prefix on
21239 moving of second half of TFmode value. */
21241 {
21243 {
21254 }
21258 }
21259 }
21263 }
21265 /* Choose correct order to not overwrite the source before it is copied. */
21275 {
21277 {
21280 }
21281 }
21282 else
21283 {
21285 {
21288 }
21289 }
21291 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21293 {
21302 }
21308 }
21310 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21311 left shift by a constant, either using a single shift or
21312 a sequence of add instructions. */
21314 static void
21316 {
21322 {
21326 }
21327 else
21328 {
21331 }
21332 }
21334 void
21336 {
21345 {
21350 {
21356 }
21357 else
21358 {
21366 }
21368 }
21375 {
21376 /* Assuming we've chosen a QImode capable registers, then 1 << N
21377 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21379 {
21395 }
21397 /* Otherwise, we can get the same results by manually performing
21398 a bit extract operation on bit 5/6, and then performing the two
21399 shifts. The two methods of getting 0/1 into low/high are exactly
21400 the same size. Avoiding the shift in the bit extract case helps
21401 pentium4 a bit; no one else seems to care much either way. */
21402 else
21403 {
21408 HOST_WIDE_INT bits;
21409 rtx x;
21412 {
21418 }
21419 else
21420 {
21426 }
21430 else
21438 }
21443 }
21446 {
21447 /* For -1 << N, we can avoid the shld instruction, because we
21448 know that we're shifting 0...31/63 ones into a -1. */
21452 else
21454 }
21455 else
21456 {
21464 }
21469 {
21475 }
21476 else
21477 {
21482 }
21483 }
21485 void
21487 {
21497 {
21502 {
21508 }
21510 {
21519 }
21520 else
21521 {
21529 }
21530 }
21531 else
21532 {
21544 {
21552 scratch));
21553 }
21554 else
21555 {
21560 }
21561 }
21562 }
21564 void
21566 {
21576 {
21581 {
21588 }
21589 else
21590 {
21598 }
21599 }
21600 else
21601 {
21613 {
21619 scratch));
21620 }
21621 else
21622 {
21627 }
21628 }
21629 }
21631 /* Predict just emitted jump instruction to be taken with probability PROB. */
21632 static void
21634 {
21638 }
21640 /* Helper function for the string operations below. Dest VARIABLE whether
21641 it is aligned to VALUE bytes. If true, jump to the label. */
21642 static rtx
21644 {
21649 else
21655 else
21658 }
21660 /* Adjust COUNTER by the VALUE. */
21661 static void
21663 {
21668 }
21670 /* Zero extend possibly SImode EXP to Pmode register. */
21671 rtx
21673 {
21675 }
21677 /* Divide COUNTREG by SCALE. */
21678 static rtx
21680 {
21681 rtx sc;
21693 }
21695 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21696 DImode for constant loop counts. */
21698 static enum machine_mode
21700 {
21708 }
21710 /* When SRCPTR is non-NULL, output simple loop to move memory
21711 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21712 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21713 equivalent loop to set memory by VALUE (supposed to be in MODE).
21715 The size is rounded down to whole number of chunk size moved at once.
21716 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21719 static void
21724 {
21729 rtx size;
21730 rtx x_addr;
21731 rtx y_addr;
21740 /* Those two should combine. */
21742 {
21746 }
21756 {
21760 /* When unrolling for chips that reorder memory reads and writes,
21761 we can save registers by using single temporary.
21762 Also using 4 temporaries is overkill in 32bit mode. */
21764 {
21766 {
21768 {
21769 destmem =
21771 srcmem =
21773 }
21775 }
21776 }
21777 else
21778 {
21782 {
21785 {
21786 srcmem =
21788 }
21790 }
21792 {
21794 {
21795 destmem =
21797 }
21799 }
21800 }
21801 }
21802 else
21804 {
21806 destmem =
21809 }
21819 {
21825 else
21827 }
21828 else
21836 {
21841 }
21843 }
21845 /* Output "rep; mov" instruction.
21846 Arguments have same meaning as for previous function */
21847 static void
21850 rtx count,
21852 {
21853 rtx destexp;
21854 rtx srcexp;
21855 rtx countreg;
21856 HOST_WIDE_INT rounded_count;
21858 /* If the size is known, it is shorter to use rep movs. */
21869 {
21876 }
21877 else
21878 {
21881 }
21883 {
21890 }
21891 else
21892 {
21897 }
21900 }
21902 /* Output "rep; stos" instruction.
21903 Arguments have same meaning as for previous function */
21904 static void
21907 rtx orig_value)
21908 {
21909 rtx destexp;
21910 rtx countreg;
21911 HOST_WIDE_INT rounded_count;
21918 {
21922 }
21923 else
21926 {
21931 }
21935 }
21937 static void
21940 {
21944 }
21946 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
21947 static void
21950 {
21953 {
21958 {
21960 {
21963 }
21964 else
21967 }
21969 {
21972 else
21973 {
21976 }
21978 }
21980 {
21983 }
21985 {
21988 }
21990 {
21993 }
21995 }
21997 {
22003 }
22005 /* When there are stringops, we can cheaply increase dest and src pointers.
22006 Otherwise we save code size by maintaining offset (zero is readily
22007 available from preceding rep operation) and using x86 addressing modes.
22008 */
22010 {
22012 {
22019 }
22021 {
22028 }
22030 {
22037 }
22038 }
22039 else
22040 {
22042 rtx tmp;
22045 {
22056 }
22058 {
22071 }
22073 {
22082 }
22083 }
22084 }
22086 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22087 static void
22090 {
22091 count =
22097 }
22099 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22100 static void
22102 {
22103 rtx dest;
22106 {
22111 {
22113 {
22118 }
22119 else
22122 }
22124 {
22126 {
22129 }
22130 else
22131 {
22136 }
22138 }
22140 {
22144 }
22146 {
22150 }
22152 {
22156 }
22158 }
22160 {
22163 }
22165 {
22168 {
22172 }
22173 else
22174 {
22180 }
22183 }
22185 {
22188 {
22191 }
22192 else
22193 {
22197 }
22200 }
22202 {
22208 }
22210 {
22216 }
22218 {
22224 }
22225 }
22227 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22228 DESIRED_ALIGNMENT. */
22229 static void
22233 {
22235 {
22243 }
22245 {
22253 }
22255 {
22263 }
22265 }
22267 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22268 ALIGN_BYTES is how many bytes need to be copied. */
22269 static rtx
22272 {
22281 {
22286 }
22288 {
22299 }
22301 {
22307 {
22315 }
22318 }
22324 {
22336 }
22343 }
22345 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22346 DESIRED_ALIGNMENT. */
22347 static void
22350 {
22352 {
22359 }
22361 {
22368 }
22370 {
22377 }
22379 }
22381 /* Set enough from DST to align DST known to by aligned by ALIGN to
22382 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22383 static rtx
22386 {
22390 {
22395 }
22397 {
22404 }
22406 {
22413 }
22420 }
22422 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22423 static enum stringop_alg
22426 {
22429 /* Algorithms using the rep prefix want at least edi and ecx;
22430 additionally, memset wants eax and memcpy wants esi. Don't
22431 consider such algorithms if the user has appropriated those
22432 registers for their own purposes. */
22434 || (memset
22438 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22439 || (alg != rep_prefix_1_byte \
22440 && alg != rep_prefix_4_byte \
22441 && alg != rep_prefix_8_byte))
22444 /* Even if the string operation call is cold, we still might spend a lot
22445 of time processing large blocks. */
22450 else
22458 else
22462 /* rep; movq or rep; movl is the smallest variant. */
22464 {
22467 else
22469 }
22470 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22471 */
22475 {
22479 {
22480 /* We get here if the algorithms that were not libcall-based
22481 were rep-prefix based and we are unable to use rep prefixes
22482 based on global register usage. Break out of the loop and
22483 use the heuristic below. */
22487 {
22492 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22493 last non-libcall inline algorithm. */
22495 {
22496 /* When the current size is best to be copied by a libcall,
22497 but we are still forced to inline, run the heuristic below
22498 that will pick code for medium sized blocks. */
22502 }
22504 {
22507 }
22508 }
22509 }
22511 }
22512 /* When asked to inline the call anyway, try to pick meaningful choice.
22513 We look for maximal size of block that is faster to copy by hand and
22514 take blocks of at most of that size guessing that average size will
22515 be roughly half of the block.
22517 If this turns out to be bad, we might simply specify the preferred
22518 choice in ix86_costs. */
22521 {
22528 {
22535 }
22536 /* If there aren't any usable algorithms, then recursing on
22537 smaller sizes isn't going to find anything. Just return the
22538 simple byte-at-a-time copy loop. */
22540 {
22541 /* Pick something reasonable. */
22545 }
22554 }
22556 #undef ALG_USABLE_P
22557 }
22559 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22560 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22561 static int
22565 {
22568 {
22579 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22580 copying whole cacheline at once. */
22583 else
22587 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22588 copying whole cacheline at once. */
22591 else
22599 }
22608 }
22610 /* Return the smallest power of 2 greater than VAL. */
22611 static int
22613 {
22618 }
22620 /* Expand string move (memcpy) operation. Use i386 string operations
22621 when profitable. expand_setmem contains similar code. The code
22622 depends upon architecture, block size and alignment, but always has
22623 the same overall structure:
22625 1) Prologue guard: Conditional that jumps up to epilogues for small
22626 blocks that can be handled by epilogue alone. This is faster
22627 but also needed for correctness, since prologue assume the block
22628 is larger than the desired alignment.
22630 Optional dynamic check for size and libcall for large
22631 blocks is emitted here too, with -minline-stringops-dynamically.
22633 2) Prologue: copy first few bytes in order to get destination
22634 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22635 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22636 copied. We emit either a jump tree on power of two sized
22637 blocks, or a byte loop.
22639 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22640 with specified algorithm.
22642 4) Epilogue: code copying tail of the block that is too small to be
22643 handled by main body (or up to size guarded by prologue guard). */
22645 bool
22648 {
22649 rtx destreg;
22650 rtx srcreg;
22652 rtx tmp;
22666 /* i386 can do misaligned access on reasonably increased cost. */
22670 /* ALIGN is the minimum of destination and source alignment, but we care here
22671 just about destination alignment. */
22680 /* Make sure we don't need to care about overflow later on. */
22684 /* Step 0: Decide on preferred algorithm, desired alignment and
22685 size of chunks to be copied by main loop. */
22701 {
22726 }
22730 /* Step 1: Prologue guard. */
22732 /* Alignment code needs count to be in register. */
22734 {
22737 {
22738 align_bytes
22742 else
22744 }
22747 }
22750 /* Ensure that alignment prologue won't copy past end of block. */
22752 {
22754 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22755 Make sure it is power of 2. */
22759 {
22761 {
22762 /* If main algorithm works on QImode, no epilogue is needed.
22763 For small sizes just don't align anything. */
22766 else
22768 }
22769 }
22770 else
22771 {
22778 else
22780 }
22781 }
22783 /* Emit code to decide on runtime whether library call or inline should be
22784 used. */
22786 {
22788 {
22790 {
22794 }
22795 }
22796 else
22797 {
22806 }
22807 }
22809 /* Step 2: Alignment prologue. */
22812 {
22814 {
22815 /* Except for the first move in epilogue, we no longer know
22816 constant offset in aliasing info. It don't seems to worth
22817 the pain to maintain it for the first move, so throw away
22818 the info early. */
22822 desired_align);
22823 }
22824 else
22825 {
22826 /* If we know how many bytes need to be stored before dst is
22827 sufficiently aligned, maintain aliasing info accurately. */
22833 }
22839 {
22840 /* It is possible that we copied enough so the main loop will not
22841 execute. */
22851 else
22853 }
22854 }
22856 {
22861 }
22865 /* Step 3: Main loop. */
22868 {
22881 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
22882 registers for 4 temporaries anyway. */
22885 expected_size);
22889 DImode);
22893 SImode);
22897 QImode);
22899 }
22900 /* Adjust properly the offset of src and dest memory for aliasing. */
22902 {
22907 }
22908 else
22909 {
22912 }
22914 /* Step 4: Epilogue to copy the remaining bytes. */
22915 epilogue:
22917 {
22918 /* When the main loop is done, COUNT_EXP might hold original count,
22919 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
22920 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
22921 bytes. Compensate if needed. */
22924 {
22925 tmp =
22928 OPTAB_DIRECT);
22931 }
22934 }
22938 epilogue_size_needed);
22942 }
22944 /* Helper function for memcpy. For QImode value 0xXY produce
22945 0xXYXYXYXY of wide specified by MODE. This is essentially
22946 a * 0x10101010, but we can do slightly better than
22947 synth_mult by unwinding the sequence by hand on CPUs with
22948 slow multiply. */
22949 static rtx
22951 {
22953 rtx tmp;
22960 {
22968 }
22977 nops--;
22982 {
22986 OPTAB_DIRECT);
22987 }
22988 else
22989 {
22995 else
22997 else
22998 {
23001 reg =
23003 }
23013 }
23014 }
23016 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23017 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23018 alignment from ALIGN to DESIRED_ALIGN. */
23019 static rtx
23021 {
23022 rtx promoted_val;
23031 else
23035 }
23037 /* Expand string clear operation (bzero). Use i386 string operations when
23038 profitable. See expand_movmem comment for explanation of individual
23039 steps performed. */
23040 bool
23043 {
23044 rtx destreg;
23046 rtx tmp;
23062 /* i386 can do misaligned access on reasonably increased cost. */
23071 /* Make sure we don't need to care about overflow later on. */
23075 /* Step 0: Decide on preferred algorithm, desired alignment and
23076 size of chunks to be copied by main loop. */
23091 {
23116 }
23119 /* Step 1: Prologue guard. */
23121 /* Alignment code needs count to be in register. */
23123 {
23126 {
23127 align_bytes
23131 else
23133 }
23135 {
23140 }
23141 }
23142 /* Do the cheap promotion to allow better CSE across the
23143 main loop and epilogue (ie one load of the big constant in the
23144 front of all code. */
23148 /* Ensure that alignment prologue won't copy past end of block. */
23150 {
23152 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23153 Make sure it is power of 2. */
23156 /* To improve performance of small blocks, we jump around the VAL
23157 promoting mode. This mean that if the promoted VAL is not constant,
23158 we might not use it in the epilogue and have to use byte
23159 loop variant. */
23163 {
23165 {
23166 /* If main algorithm works on QImode, no epilogue is needed.
23167 For small sizes just don't align anything. */
23170 else
23172 }
23173 }
23174 else
23175 {
23182 else
23184 }
23185 }
23187 {
23196 }
23198 /* Step 2: Alignment prologue. */
23200 /* Do the expensive promotion once we branched off the small blocks. */
23207 {
23209 {
23210 /* Except for the first move in epilogue, we no longer know
23211 constant offset in aliasing info. It don't seems to worth
23212 the pain to maintain it for the first move, so throw away
23213 the info early. */
23216 desired_align);
23217 }
23218 else
23219 {
23220 /* If we know how many bytes need to be stored before dst is
23221 sufficiently aligned, maintain aliasing info accurately. */
23227 }
23233 {
23234 /* It is possible that we copied enough so the main loop will not
23235 execute. */
23245 else
23247 }
23248 }
23250 {
23256 }
23260 /* Step 3: Main loop. */
23263 {
23291 }
23292 /* Adjust properly the offset of src and dest memory for aliasing. */
23296 else
23299 /* Step 4: Epilogue to copy the remaining bytes. */
23302 {
23303 /* When the main loop is done, COUNT_EXP might hold original count,
23304 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23305 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23306 bytes. Compensate if needed. */
23309 {
23310 tmp =
23313 OPTAB_DIRECT);
23316 }
23319 }
23320 epilogue:
23322 {
23325 epilogue_size_needed);
23326 else
23328 epilogue_size_needed);
23329 }
23333 }
23335 /* Expand the appropriate insns for doing strlen if not just doing
23336 repnz; scasb
23338 out = result, initialized with the start address
23339 align_rtx = alignment of the address.
23340 scratch = scratch register, initialized with the startaddress when
23341 not aligned, otherwise undefined
23343 This is just the body. It needs the initializations mentioned above and
23344 some address computing at the end. These things are done in i386.md. */
23346 static void
23348 {
23350 rtx tmp;
23355 rtx mem;
23358 rtx cmp;
23364 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23366 /* Is there a known alignment and is it less than 4? */
23368 {
23371 /* Is there a known alignment and is it not 2? */
23373 {
23377 /* Leave just the 3 lower bits. */
23387 }
23388 else
23389 {
23390 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23391 check if is aligned to 4 - byte. */
23398 }
23402 /* Now compare the bytes. */
23404 /* Compare the first n unaligned byte on a byte per byte basis. */
23408 /* Increment the address. */
23411 /* Not needed with an alignment of 2 */
23413 {
23417 end_0_label);
23422 }
23425 end_0_label);
23428 }
23430 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23431 align this loop. It gives only huge programs, but does not help to
23432 speed up. */
23439 /* This formula yields a nonzero result iff one of the bytes is zero.
23440 This saves three branches inside loop and many cycles. */
23448 align_4_label);
23451 {
23457 /* If zero is not in the first two bytes, move two bytes forward. */
23463 reg,
23464 tmpreg)));
23465 /* Emit lea manually to avoid clobbering of flags. */
23473 reg2,
23474 out)));
23475 }
23476 else
23477 {
23479 /* Is zero in the first two bytes? */
23486 pc_rtx);
23490 /* Not in the first two. Move two bytes forward. */
23496 }
23498 /* Avoid branch in fixing the byte. */
23506 }
23508 /* Expand strlen. */
23510 bool
23512 {
23515 /* The generic case of strlen expander is long. Avoid it's
23516 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23519 && !TARGET_INLINE_ALL_STRINGOPS
23529 {
23530 /* Well it seems that some optimizer does not combine a call like
23531 foo(strlen(bar), strlen(bar));
23532 when the move and the subtraction is done here. It does calculate
23533 the length just once when these instructions are done inside of
23534 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23535 often used and I use one fewer register for the lifetime of
23536 output_strlen_unroll() this is better. */
23542 /* strlensi_unroll_1 returns the address of the zero at the end of
23543 the string, like memchr(), so compute the length by subtracting
23544 the start address. */
23546 }
23547 else
23548 {
23549 rtx unspec;
23551 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23564 /* If .md starts supporting :P, this can be done in .md. */
23570 }
23572 }
23574 /* For given symbol (function) construct code to compute address of it's PLT
23575 entry in large x86-64 PIC model. */
23576 static rtx
23578 {
23591 }
23593 rtx
23595 rtx callarg2,
23597 {
23598 /* We need to represent that SI and DI registers are clobbered
23599 by SYSV calls. */
23605 };
23615 {
23616 #if TARGET_MACHO
23619 #endif
23620 }
23621 else
23622 {
23623 /* Static functions and indirect calls don't need the pic register. */
23628 }
23631 {
23635 }
23645 {
23648 }
23657 {
23661 }
23665 {
23669 UNSPEC_MS_TO_SYSV_CALL);
23677 }
23686 }
23688 /* Output the assembly for a call instruction. */
23692 {
23698 {
23701 /* SEH epilogue detection requires the indirect branch case
23702 to include REX.W. */
23705 else
23710 }
23712 /* SEH unwinding can require an extra nop to be emitted in several
23713 circumstances. Determine if we have one of those. */
23715 {
23716 rtx i;
23719 {
23720 /* If we get to another real insn, we don't need the nop. */
23724 /* If we get to the epilogue note, prevent a catch region from
23725 being adjacent to the standard epilogue sequence. If non-
23726 call-exceptions, we'll have done this during epilogue emission. */
23728 && !flag_non_call_exceptions
23730 {
23733 }
23734 }
23736 /* If we didn't find a real insn following the call, prevent the
23737 unwinder from looking into the next function. */
23740 }
23744 else
23753 }
23754 \f
23755 /* Clear stack slot assignments remembered from previous functions.
23756 This is called from INIT_EXPANDERS once before RTL is emitted for each
23757 function. */
23761 {
23769 }
23771 /* Return a MEM corresponding to a stack slot with mode MODE.
23772 Allocate a new slot if necessary.
23774 The RTL for a function can have several slots available: N is
23775 which slot to use. */
23777 rtx
23779 {
23796 }
23798 static void
23800 {
23806 }
23807 \f
23808 /* Calculate the length of the memory address in the instruction encoding.
23809 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23810 or other prefixes. We never generate addr32 prefix for LEA insn. */
23812 int
23814 {
23831 /* If this is not LEA instruction, add the length of addr32 prefix. */
23836 len++;
23850 /* Rule of thumb:
23851 - esp as the base always wants an index,
23852 - ebp as the base always wants a displacement,
23853 - r12 as the base always wants an index,
23854 - r13 as the base always wants a displacement. */
23856 /* Register Indirect. */
23858 {
23859 /* esp (for its index) and ebp (for its displacement) need
23860 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23861 code. */
23868 len++;
23869 }
23871 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23872 is not disp32, but disp32(%rip), so for disp32
23873 SIB byte is needed, unless print_operand_address
23874 optimizes it into disp32(%rip) or (%rip) is implied
23875 by UNSPEC. */
23877 {
23880 {
23896 len++;
23897 }
23898 }
23899 else
23900 {
23901 /* Find the length of the displacement constant. */
23903 {
23906 else
23908 }
23909 /* ebp always wants a displacement. Similarly r13. */
23911 len++;
23913 /* An index requires the two-byte modrm form.... */
23915 /* ...like esp (or r12), which always wants an index. */
23919 len++;
23920 }
23923 }
23925 /* Compute default value for "length_immediate" attribute. When SHORTFORM
23926 is set, expect that insn have 8bit immediate alternative. */
23927 int
23929 {
23935 {
23940 {
23943 {
23955 }
23957 {
23960 }
23961 }
23963 {
23973 /* Immediates for DImode instructions are encoded
23974 as 32bit sign extended values. */
23980 }
23981 }
23983 }
23985 /* Compute default value for "length_address" attribute. */
23986 int
23988 {
23992 {
24003 }
24008 {
24011 {
24016 constraints++;
24019 ;
24020 /* Skip ignored operands. */
24023 }
24025 }
24027 }
24029 /* Compute default value for "length_vex" attribute. It includes
24030 2 or 3 byte VEX prefix and 1 opcode byte. */
24032 int
24034 {
24037 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24038 byte VEX prefix. */
24042 /* We can always use 2 byte VEX prefix in 32bit. */
24050 {
24051 /* REX.W bit uses 3 byte VEX prefix. */
24055 }
24056 else
24057 {
24058 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24062 }
24065 }
24066 \f
24067 /* Return the maximum number of instructions a cpu can issue. */
24069 static int
24071 {
24073 {
24099 }
24100 }
24102 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24103 by DEP_INSN and nothing set by DEP_INSN. */
24105 static bool
24107 {
24110 /* Simplify the test for uninteresting insns. */
24118 {
24121 }
24126 {
24129 }
24130 else
24136 /* This test is true if the dependent insn reads the flags but
24137 not any other potentially set register. */
24145 }
24147 /* Return true iff USE_INSN has a memory address with operands set by
24148 SET_INSN. */
24150 bool
24152 {
24157 {
24160 }
24162 }
24164 static int
24166 {
24172 /* Anti and output dependencies have zero cost on all CPUs. */
24178 /* If we can't recognize the insns, we can't really do anything. */
24186 {
24188 /* Address Generation Interlock adds a cycle of latency. */
24190 {
24201 }
24205 /* ??? Compares pair with jump/setcc. */
24209 /* Floating point stores require value to be ready one cycle earlier. */
24219 /* INT->FP conversion is expensive. */
24223 /* There is one cycle extra latency between an FP op and a store. */
24231 /* Show ability of reorder buffer to hide latency of load by executing
24232 in parallel with previous instruction in case
24233 previous instruction is not needed to compute the address. */
24236 {
24237 /* Claim moves to take one cycle, as core can issue one load
24238 at time and the next load can start cycle later. */
24243 cost--;
24244 }
24250 /* The esp dependency is resolved before the instruction is really
24251 finished. */
24256 /* INT->FP conversion is expensive. */
24260 /* Show ability of reorder buffer to hide latency of load by executing
24261 in parallel with previous instruction in case
24262 previous instruction is not needed to compute the address. */
24265 {
24266 /* Claim moves to take one cycle, as core can issue one load
24267 at time and the next load can start cycle later. */
24273 else
24275 }
24291 /* Show ability of reorder buffer to hide latency of load by executing
24292 in parallel with previous instruction in case
24293 previous instruction is not needed to compute the address. */
24296 {
24300 /* Because of the difference between the length of integer and
24301 floating unit pipeline preparation stages, the memory operands
24302 for floating point are cheaper.
24304 ??? For Athlon it the difference is most probably 2. */
24307 else
24312 else
24314 }
24318 }
24321 }
24323 /* How many alternative schedules to try. This should be as wide as the
24324 scheduling freedom in the DFA, but no wider. Making this value too
24325 large results extra work for the scheduler. */
24327 static int
24329 {
24331 {
24343 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24344 as many instructions can be executed on a cycle, i.e.,
24345 issue_rate. I wonder why tuning for many CPUs does not do this. */
24348 /* Don't use lookahead for pre-reload schedule to save compile time. */
24353 }
24354 }
24356 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24357 execution. It is applied if
24358 (1) IMUL instruction is on the top of list;
24359 (2) There exists the only producer of independent IMUL instruction in
24360 ready list;
24361 (3) Put found producer on the top of ready list.
24362 Returns issue rate. */
24364 static int
24367 {
24372 sd_iterator_def sd_it;
24373 dep_t dep;
24376 /* Set up issue rate. */
24379 /* Do reodering for Atom only. */
24382 /* Do not perform ready list reodering for pre-reload schedule pass. */
24385 /* Nothing to do if ready list contains only 1 instruction. */
24389 /* Check that IMUL instruction is on the top of ready list. */
24402 /* Search for producer of independent IMUL instruction. */
24404 {
24408 /* Skip IMUL instruction. */
24418 {
24419 rtx con;
24430 {
24431 sd_iterator_def sd_it1;
24432 dep_t dep1;
24433 /* Check if there is no other dependee for IMUL. */
24436 {
24437 rtx pro;
24443 }
24446 }
24447 }
24450 }
24458 /* Put IMUL producer (ready[index]) at the top of ready list. */
24465 }
24467 static bool
24470 /* Returns true if lhs of insn is HW function argument register and set up
24471 is_spilled to true if it is likely spilled HW register. */
24472 static bool
24474 {
24475 rtx dst;
24479 /* Call instructions are not movable, ignore it. */
24490 {
24491 /* Is it likely spilled HW register? */
24496 }
24498 }
24500 /* Add output dependencies for chain of function adjacent arguments if only
24501 there is a move to likely spilled HW register. Return first argument
24502 if at least one dependence was added or NULL otherwise. */
24503 static rtx
24505 {
24506 rtx insn;
24513 /* Find nearest to call argument passing instruction. */
24515 {
24524 }
24528 {
24535 {
24538 }
24540 {
24541 /* Add output depdendence between two function arguments if chain
24542 of output arguments contains likely spilled HW registers. */
24546 }
24547 else
24549 }
24553 }
24555 /* Add output or anti dependency from insn to first_arg to restrict its code
24556 motion. */
24557 static void
24559 {
24560 rtx set;
24561 rtx tmp;
24568 {
24569 /* Add output dependency to the first function argument. */
24572 }
24573 /* Add anti dependency. */
24575 }
24577 /* Avoid cross block motion of function argument through adding dependency
24578 from the first non-jump instruction in bb. */
24579 static void
24581 {
24585 {
24587 {
24590 {
24593 }
24594 }
24598 }
24599 }
24601 /* Hook for pre-reload schedule - avoid motion of function arguments
24602 passed in likely spilled HW registers. */
24603 static void
24605 {
24606 rtx insn;
24614 {
24617 {
24618 /* Add dependee for first argument to predecessors if only
24619 region contains more than one block. */
24623 /* Skip trivial regions and region head blocks that can have
24624 predecessors outside of region. */
24626 {
24627 edge e;
24628 edge_iterator ei;
24629 /* Assume that region is SCC, i.e. all immediate predecessors
24630 of non-head block are in the same region. */
24632 {
24633 /* Avoid creating of loop-carried dependencies through
24634 using topological odering in region. */
24637 }
24638 }
24642 }
24643 }
24646 }
24648 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24649 HW registers to maximum, to schedule them at soon as possible. These are
24650 moves from function argument registers at the top of the function entry
24651 and moves from function return value registers after call. */
24652 static int
24654 {
24655 rtx set;
24665 {
24672 }
24675 }
24677 /* Model decoder of Core 2/i7.
24678 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24679 track the instruction fetch block boundaries and make sure that long
24680 (9+ bytes) instructions are assigned to D0. */
24682 /* Maximum length of an insn that can be handled by
24683 a secondary decoder unit. '8' for Core 2/i7. */
24686 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24687 '16' for Core 2/i7. */
24690 /* Maximum number of instructions decoder can handle per cycle.
24691 '6' for Core 2/i7. */
24695 ix86_first_cycle_multipass_data_t;
24697 const_ix86_first_cycle_multipass_data_t;
24699 /* A variable to store target state across calls to max_issue within
24700 one cycle. */
24704 /* Initialize DATA. */
24705 static void
24707 {
24708 ix86_first_cycle_multipass_data_t data
24715 }
24717 /* Advancing the cycle; reset ifetch block counts. */
24718 static void
24720 {
24727 }
24731 /* Filter out insns from ready_try that the core will not be able to issue
24732 on current cycle due to decoder. */
24733 static void
24734 core2i7_first_cycle_multipass_filter_ready_try
24737 {
24739 {
24740 rtx insn;
24750 (!first_cycle_insn_p
24752 /* ... or it would not fit into the ifetch block ... */
24754 /* ... or the decoder is full already ... */
24756 /* ... mask the insn out. */
24757 {
24762 }
24763 }
24764 }
24766 /* Prepare for a new round of multipass lookahead scheduling. */
24767 static void
24770 {
24771 ix86_first_cycle_multipass_data_t data
24773 const_ix86_first_cycle_multipass_data_t prev_data
24776 /* Restore the state from the end of the previous round. */
24780 /* Filter instructions that cannot be issued on current cycle due to
24781 decoder restrictions. */
24783 first_cycle_insn_p);
24784 }
24786 /* INSN is being issued in current solution. Account for its impact on
24787 the decoder model. */
24788 static void
24791 {
24792 ix86_first_cycle_multipass_data_t data
24794 const_ix86_first_cycle_multipass_data_t prev_data
24804 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24806 {
24809 }
24811 {
24815 }
24818 /* Filter out insns from ready_try that the core will not be able to issue
24819 on current cycle due to decoder. */
24822 }
24824 /* Revert the effect on ready_try. */
24825 static void
24829 {
24830 const_ix86_first_cycle_multipass_data_t data
24833 sbitmap_iterator sbi;
24837 {
24839 }
24840 }
24842 /* Save the result of multipass lookahead scheduling for the next round. */
24843 static void
24845 {
24846 const_ix86_first_cycle_multipass_data_t data
24848 ix86_first_cycle_multipass_data_t next_data
24852 {
24855 }
24856 }
24858 /* Deallocate target data. */
24859 static void
24861 {
24862 ix86_first_cycle_multipass_data_t data
24866 {
24870 }
24871 }
24873 /* Prepare for scheduling pass. */
24874 static void
24878 {
24879 /* Install scheduling hooks for current CPU. Some of these hooks are used
24880 in time-critical parts of the scheduler, so we only set them up when
24881 they are actually used. */
24883 {
24887 /* Do not perform multipass scheduling for pre-reload schedule
24888 to save compile time. */
24890 {
24906 /* Set decoder parameters. */
24911 }
24912 /* ... Fall through ... */
24922 }
24923 }
24925 \f
24926 /* Compute the alignment given to a constant that is being placed in memory.
24927 EXP is the constant and ALIGN is the alignment that the object would
24928 ordinarily have.
24929 The value of this function is used instead of that alignment to align
24930 the object. */
24932 int
24934 {
24937 {
24942 }
24948 }
24950 /* Compute the alignment for a static variable.
24951 TYPE is the data type, and ALIGN is the alignment that
24952 the object would ordinarily have. The value of this function is used
24953 instead of that alignment to align the object. */
24955 int
24957 {
24968 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
24969 to 16byte boundary. */
24971 {
24978 }
24981 {
24986 }
24988 {
24995 }
25000 {
25005 }
25008 {
25013 }
25016 }
25018 /* Compute the alignment for a local variable or a stack slot. EXP is
25019 the data type or decl itself, MODE is the widest mode available and
25020 ALIGN is the alignment that the object would ordinarily have. The
25021 value of this macro is used instead of that alignment to align the
25022 object. */
25024 unsigned int
25027 {
25031 {
25034 }
25035 else
25036 {
25039 }
25041 /* Don't do dynamic stack realignment for long long objects with
25042 -mpreferred-stack-boundary=2. */
25051 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25052 register in MODE. We will return the largest alignment of XF
25053 and DF. */
25055 {
25059 }
25061 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25062 to 16byte boundary. Exact wording is:
25064 An array uses the same alignment as its elements, except that a local or
25065 global array variable of length at least 16 bytes or
25066 a C99 variable-length array variable always has alignment of at least 16 bytes.
25068 This was added to allow use of aligned SSE instructions at arrays. This
25069 rule is meant for static storage (where compiler can not do the analysis
25070 by itself). We follow it for automatic variables only when convenient.
25071 We fully control everything in the function compiled and functions from
25072 other unit can not rely on the alignment.
25074 Exclude va_list type. It is the common case of local array where
25075 we can not benefit from the alignment. */
25078 {
25088 }
25090 {
25095 }
25097 {
25103 }
25108 {
25113 }
25116 {
25122 }
25124 }
25126 /* Compute the minimum required alignment for dynamic stack realignment
25127 purposes for a local variable, parameter or a stack slot. EXP is
25128 the data type or decl itself, MODE is its mode and ALIGN is the
25129 alignment that the object would ordinarily have. */
25131 unsigned int
25134 {
25138 {
25141 }
25142 else
25143 {
25146 }
25151 /* Don't do dynamic stack realignment for long long objects with
25152 -mpreferred-stack-boundary=2. */
25159 }
25160 \f
25161 /* Find a location for the static chain incoming to a nested function.
25162 This is a register, unless all free registers are used by arguments. */
25164 static rtx
25166 {
25173 {
25174 /* We always use R10 in 64-bit mode. */
25176 }
25177 else
25178 {
25179 tree fntype;
25182 /* By default in 32-bit mode we use ECX to pass the static chain. */
25188 {
25189 /* Fastcall functions use ecx/edx for arguments, which leaves
25190 us with EAX for the static chain.
25191 Thiscall functions use ecx for arguments, which also
25192 leaves us with EAX for the static chain. */
25194 }
25196 {
25197 /* Thiscall functions use ecx for arguments, which leaves
25198 us with EAX and EDX for the static chain.
25199 We are using for abi-compatibility EAX. */
25201 }
25203 {
25204 /* For regparm 3, we have no free call-clobbered registers in
25205 which to store the static chain. In order to implement this,
25206 we have the trampoline push the static chain to the stack.
25207 However, we can't push a value below the return address when
25208 we call the nested function directly, so we have to use an
25209 alternate entry point. For this we use ESI, and have the
25210 alternate entry point push ESI, so that things appear the
25211 same once we're executing the nested function. */
25213 {
25219 }
25221 }
25222 }
25225 }
25227 /* Emit RTL insns to initialize the variable parts of a trampoline.
25228 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25229 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25230 to be passed to the target function. */
25232 static void
25234 {
25242 {
25245 /* Load the function address to r11. Try to load address using
25246 the shorter movl instead of movabs. We may want to support
25247 movq for kernel mode, but kernel does not use trampolines at
25248 the moment. FNADDR is a 32bit address and may not be in
25249 DImode when ptr_mode == SImode. Always use movl in this
25250 case. */
25253 {
25262 }
25263 else
25264 {
25271 }
25273 /* Load static chain using movabs to r10. Use the shorter movl
25274 instead of movabs when ptr_mode == SImode. */
25276 {
25279 }
25280 else
25281 {
25284 }
25293 /* Jump to r11; the last (unused) byte is a nop, only there to
25294 pad the write out to a single 32-bit store. */
25298 }
25299 else
25300 {
25303 /* Depending on the static chain location, either load a register
25304 with a constant, or push the constant to the stack. All of the
25305 instructions are the same size. */
25308 {
25310 {
25317 }
25318 }
25319 else
25334 /* Compute offset from the end of the jmp to the target function.
25335 In the case in which the trampoline stores the static chain on
25336 the stack, we need to skip the first insn which pushes the
25337 (call-saved) register static chain; this push is 1 byte. */
25344 }
25348 #ifdef HAVE_ENABLE_EXECUTE_STACK
25349 #ifdef CHECK_EXECUTE_STACK_ENABLED
25351 #endif
25354 #endif
25355 }
25356 \f
25357 /* The following file contains several enumerations and data structures
25358 built from the definitions in i386-builtin-types.def. */
25362 /* Table for the ix86 builtin non-function types. */
25365 /* Retrieve an element from the above table, building some of
25366 the types lazily. */
25368 static tree
25370 {
25382 {
25390 }
25391 else
25392 {
25398 else
25406 }
25410 }
25412 /* Table for the ix86 builtin function types. */
25415 /* Retrieve an element from the above table, building some of
25416 the types lazily. */
25418 static tree
25420 {
25421 tree type;
25430 {
25438 {
25441 }
25444 }
25445 else
25446 {
25452 }
25456 }
25459 /* Codes for all the SSE/MMX builtins. */
25460 enum ix86_builtins
25461 {
25462 IX86_BUILTIN_ADDPS,
25463 IX86_BUILTIN_ADDSS,
25464 IX86_BUILTIN_DIVPS,
25465 IX86_BUILTIN_DIVSS,
25466 IX86_BUILTIN_MULPS,
25467 IX86_BUILTIN_MULSS,
25468 IX86_BUILTIN_SUBPS,
25469 IX86_BUILTIN_SUBSS,
25471 IX86_BUILTIN_CMPEQPS,
25472 IX86_BUILTIN_CMPLTPS,
25473 IX86_BUILTIN_CMPLEPS,
25474 IX86_BUILTIN_CMPGTPS,
25475 IX86_BUILTIN_CMPGEPS,
25476 IX86_BUILTIN_CMPNEQPS,
25477 IX86_BUILTIN_CMPNLTPS,
25478 IX86_BUILTIN_CMPNLEPS,
25479 IX86_BUILTIN_CMPNGTPS,
25480 IX86_BUILTIN_CMPNGEPS,
25481 IX86_BUILTIN_CMPORDPS,
25482 IX86_BUILTIN_CMPUNORDPS,
25483 IX86_BUILTIN_CMPEQSS,
25484 IX86_BUILTIN_CMPLTSS,
25485 IX86_BUILTIN_CMPLESS,
25486 IX86_BUILTIN_CMPNEQSS,
25487 IX86_BUILTIN_CMPNLTSS,
25488 IX86_BUILTIN_CMPNLESS,
25489 IX86_BUILTIN_CMPNGTSS,
25490 IX86_BUILTIN_CMPNGESS,
25491 IX86_BUILTIN_CMPORDSS,
25492 IX86_BUILTIN_CMPUNORDSS,
25494 IX86_BUILTIN_COMIEQSS,
25495 IX86_BUILTIN_COMILTSS,
25496 IX86_BUILTIN_COMILESS,
25497 IX86_BUILTIN_COMIGTSS,
25498 IX86_BUILTIN_COMIGESS,
25499 IX86_BUILTIN_COMINEQSS,
25500 IX86_BUILTIN_UCOMIEQSS,
25501 IX86_BUILTIN_UCOMILTSS,
25502 IX86_BUILTIN_UCOMILESS,
25503 IX86_BUILTIN_UCOMIGTSS,
25504 IX86_BUILTIN_UCOMIGESS,
25505 IX86_BUILTIN_UCOMINEQSS,
25507 IX86_BUILTIN_CVTPI2PS,
25508 IX86_BUILTIN_CVTPS2PI,
25509 IX86_BUILTIN_CVTSI2SS,
25510 IX86_BUILTIN_CVTSI642SS,
25511 IX86_BUILTIN_CVTSS2SI,
25512 IX86_BUILTIN_CVTSS2SI64,
25513 IX86_BUILTIN_CVTTPS2PI,
25514 IX86_BUILTIN_CVTTSS2SI,
25515 IX86_BUILTIN_CVTTSS2SI64,
25517 IX86_BUILTIN_MAXPS,
25518 IX86_BUILTIN_MAXSS,
25519 IX86_BUILTIN_MINPS,
25520 IX86_BUILTIN_MINSS,
25522 IX86_BUILTIN_LOADUPS,
25523 IX86_BUILTIN_STOREUPS,
25524 IX86_BUILTIN_MOVSS,
25526 IX86_BUILTIN_MOVHLPS,
25527 IX86_BUILTIN_MOVLHPS,
25528 IX86_BUILTIN_LOADHPS,
25529 IX86_BUILTIN_LOADLPS,
25530 IX86_BUILTIN_STOREHPS,
25531 IX86_BUILTIN_STORELPS,
25533 IX86_BUILTIN_MASKMOVQ,
25534 IX86_BUILTIN_MOVMSKPS,
25535 IX86_BUILTIN_PMOVMSKB,
25537 IX86_BUILTIN_MOVNTPS,
25538 IX86_BUILTIN_MOVNTQ,
25540 IX86_BUILTIN_LOADDQU,
25541 IX86_BUILTIN_STOREDQU,
25543 IX86_BUILTIN_PACKSSWB,
25544 IX86_BUILTIN_PACKSSDW,
25545 IX86_BUILTIN_PACKUSWB,
25547 IX86_BUILTIN_PADDB,
25548 IX86_BUILTIN_PADDW,
25549 IX86_BUILTIN_PADDD,
25550 IX86_BUILTIN_PADDQ,
25551 IX86_BUILTIN_PADDSB,
25552 IX86_BUILTIN_PADDSW,
25553 IX86_BUILTIN_PADDUSB,
25554 IX86_BUILTIN_PADDUSW,
25555 IX86_BUILTIN_PSUBB,
25556 IX86_BUILTIN_PSUBW,
25557 IX86_BUILTIN_PSUBD,
25558 IX86_BUILTIN_PSUBQ,
25559 IX86_BUILTIN_PSUBSB,
25560 IX86_BUILTIN_PSUBSW,
25561 IX86_BUILTIN_PSUBUSB,
25562 IX86_BUILTIN_PSUBUSW,
25564 IX86_BUILTIN_PAND,
25565 IX86_BUILTIN_PANDN,
25566 IX86_BUILTIN_POR,
25567 IX86_BUILTIN_PXOR,
25569 IX86_BUILTIN_PAVGB,
25570 IX86_BUILTIN_PAVGW,
25572 IX86_BUILTIN_PCMPEQB,
25573 IX86_BUILTIN_PCMPEQW,
25574 IX86_BUILTIN_PCMPEQD,
25575 IX86_BUILTIN_PCMPGTB,
25576 IX86_BUILTIN_PCMPGTW,
25577 IX86_BUILTIN_PCMPGTD,
25579 IX86_BUILTIN_PMADDWD,
25581 IX86_BUILTIN_PMAXSW,
25582 IX86_BUILTIN_PMAXUB,
25583 IX86_BUILTIN_PMINSW,
25584 IX86_BUILTIN_PMINUB,
25586 IX86_BUILTIN_PMULHUW,
25587 IX86_BUILTIN_PMULHW,
25588 IX86_BUILTIN_PMULLW,
25590 IX86_BUILTIN_PSADBW,
25591 IX86_BUILTIN_PSHUFW,
25593 IX86_BUILTIN_PSLLW,
25594 IX86_BUILTIN_PSLLD,
25595 IX86_BUILTIN_PSLLQ,
25596 IX86_BUILTIN_PSRAW,
25597 IX86_BUILTIN_PSRAD,
25598 IX86_BUILTIN_PSRLW,
25599 IX86_BUILTIN_PSRLD,
25600 IX86_BUILTIN_PSRLQ,
25601 IX86_BUILTIN_PSLLWI,
25602 IX86_BUILTIN_PSLLDI,
25603 IX86_BUILTIN_PSLLQI,
25604 IX86_BUILTIN_PSRAWI,
25605 IX86_BUILTIN_PSRADI,
25606 IX86_BUILTIN_PSRLWI,
25607 IX86_BUILTIN_PSRLDI,
25608 IX86_BUILTIN_PSRLQI,
25610 IX86_BUILTIN_PUNPCKHBW,
25611 IX86_BUILTIN_PUNPCKHWD,
25612 IX86_BUILTIN_PUNPCKHDQ,
25613 IX86_BUILTIN_PUNPCKLBW,
25614 IX86_BUILTIN_PUNPCKLWD,
25615 IX86_BUILTIN_PUNPCKLDQ,
25617 IX86_BUILTIN_SHUFPS,
25619 IX86_BUILTIN_RCPPS,
25620 IX86_BUILTIN_RCPSS,
25621 IX86_BUILTIN_RSQRTPS,
25622 IX86_BUILTIN_RSQRTPS_NR,
25623 IX86_BUILTIN_RSQRTSS,
25624 IX86_BUILTIN_RSQRTF,
25625 IX86_BUILTIN_SQRTPS,
25626 IX86_BUILTIN_SQRTPS_NR,
25627 IX86_BUILTIN_SQRTSS,
25629 IX86_BUILTIN_UNPCKHPS,
25630 IX86_BUILTIN_UNPCKLPS,
25632 IX86_BUILTIN_ANDPS,
25633 IX86_BUILTIN_ANDNPS,
25634 IX86_BUILTIN_ORPS,
25635 IX86_BUILTIN_XORPS,
25637 IX86_BUILTIN_EMMS,
25638 IX86_BUILTIN_LDMXCSR,
25639 IX86_BUILTIN_STMXCSR,
25640 IX86_BUILTIN_SFENCE,
25642 IX86_BUILTIN_FXSAVE,
25643 IX86_BUILTIN_FXRSTOR,
25644 IX86_BUILTIN_FXSAVE64,
25645 IX86_BUILTIN_FXRSTOR64,
25647 IX86_BUILTIN_XSAVE,
25648 IX86_BUILTIN_XRSTOR,
25649 IX86_BUILTIN_XSAVE64,
25650 IX86_BUILTIN_XRSTOR64,
25652 IX86_BUILTIN_XSAVEOPT,
25653 IX86_BUILTIN_XSAVEOPT64,
25655 /* 3DNow! Original */
25656 IX86_BUILTIN_FEMMS,
25657 IX86_BUILTIN_PAVGUSB,
25658 IX86_BUILTIN_PF2ID,
25659 IX86_BUILTIN_PFACC,
25660 IX86_BUILTIN_PFADD,
25661 IX86_BUILTIN_PFCMPEQ,
25662 IX86_BUILTIN_PFCMPGE,
25663 IX86_BUILTIN_PFCMPGT,
25664 IX86_BUILTIN_PFMAX,
25665 IX86_BUILTIN_PFMIN,
25666 IX86_BUILTIN_PFMUL,
25667 IX86_BUILTIN_PFRCP,
25668 IX86_BUILTIN_PFRCPIT1,
25669 IX86_BUILTIN_PFRCPIT2,
25670 IX86_BUILTIN_PFRSQIT1,
25671 IX86_BUILTIN_PFRSQRT,
25672 IX86_BUILTIN_PFSUB,
25673 IX86_BUILTIN_PFSUBR,
25674 IX86_BUILTIN_PI2FD,
25675 IX86_BUILTIN_PMULHRW,
25677 /* 3DNow! Athlon Extensions */
25678 IX86_BUILTIN_PF2IW,
25679 IX86_BUILTIN_PFNACC,
25680 IX86_BUILTIN_PFPNACC,
25681 IX86_BUILTIN_PI2FW,
25682 IX86_BUILTIN_PSWAPDSI,
25683 IX86_BUILTIN_PSWAPDSF,
25685 /* SSE2 */
25686 IX86_BUILTIN_ADDPD,
25687 IX86_BUILTIN_ADDSD,
25688 IX86_BUILTIN_DIVPD,
25689 IX86_BUILTIN_DIVSD,
25690 IX86_BUILTIN_MULPD,
25691 IX86_BUILTIN_MULSD,
25692 IX86_BUILTIN_SUBPD,
25693 IX86_BUILTIN_SUBSD,
25695 IX86_BUILTIN_CMPEQPD,
25696 IX86_BUILTIN_CMPLTPD,
25697 IX86_BUILTIN_CMPLEPD,
25698 IX86_BUILTIN_CMPGTPD,
25699 IX86_BUILTIN_CMPGEPD,
25700 IX86_BUILTIN_CMPNEQPD,
25701 IX86_BUILTIN_CMPNLTPD,
25702 IX86_BUILTIN_CMPNLEPD,
25703 IX86_BUILTIN_CMPNGTPD,
25704 IX86_BUILTIN_CMPNGEPD,
25705 IX86_BUILTIN_CMPORDPD,
25706 IX86_BUILTIN_CMPUNORDPD,
25707 IX86_BUILTIN_CMPEQSD,
25708 IX86_BUILTIN_CMPLTSD,
25709 IX86_BUILTIN_CMPLESD,
25710 IX86_BUILTIN_CMPNEQSD,
25711 IX86_BUILTIN_CMPNLTSD,
25712 IX86_BUILTIN_CMPNLESD,
25713 IX86_BUILTIN_CMPORDSD,
25714 IX86_BUILTIN_CMPUNORDSD,
25716 IX86_BUILTIN_COMIEQSD,
25717 IX86_BUILTIN_COMILTSD,
25718 IX86_BUILTIN_COMILESD,
25719 IX86_BUILTIN_COMIGTSD,
25720 IX86_BUILTIN_COMIGESD,
25721 IX86_BUILTIN_COMINEQSD,
25722 IX86_BUILTIN_UCOMIEQSD,
25723 IX86_BUILTIN_UCOMILTSD,
25724 IX86_BUILTIN_UCOMILESD,
25725 IX86_BUILTIN_UCOMIGTSD,
25726 IX86_BUILTIN_UCOMIGESD,
25727 IX86_BUILTIN_UCOMINEQSD,
25729 IX86_BUILTIN_MAXPD,
25730 IX86_BUILTIN_MAXSD,
25731 IX86_BUILTIN_MINPD,
25732 IX86_BUILTIN_MINSD,
25734 IX86_BUILTIN_ANDPD,
25735 IX86_BUILTIN_ANDNPD,
25736 IX86_BUILTIN_ORPD,
25737 IX86_BUILTIN_XORPD,
25739 IX86_BUILTIN_SQRTPD,
25740 IX86_BUILTIN_SQRTSD,
25742 IX86_BUILTIN_UNPCKHPD,
25743 IX86_BUILTIN_UNPCKLPD,
25745 IX86_BUILTIN_SHUFPD,
25747 IX86_BUILTIN_LOADUPD,
25748 IX86_BUILTIN_STOREUPD,
25749 IX86_BUILTIN_MOVSD,
25751 IX86_BUILTIN_LOADHPD,
25752 IX86_BUILTIN_LOADLPD,
25754 IX86_BUILTIN_CVTDQ2PD,
25755 IX86_BUILTIN_CVTDQ2PS,
25757 IX86_BUILTIN_CVTPD2DQ,
25758 IX86_BUILTIN_CVTPD2PI,
25759 IX86_BUILTIN_CVTPD2PS,
25760 IX86_BUILTIN_CVTTPD2DQ,
25761 IX86_BUILTIN_CVTTPD2PI,
25763 IX86_BUILTIN_CVTPI2PD,
25764 IX86_BUILTIN_CVTSI2SD,
25765 IX86_BUILTIN_CVTSI642SD,
25767 IX86_BUILTIN_CVTSD2SI,
25768 IX86_BUILTIN_CVTSD2SI64,
25769 IX86_BUILTIN_CVTSD2SS,
25770 IX86_BUILTIN_CVTSS2SD,
25771 IX86_BUILTIN_CVTTSD2SI,
25772 IX86_BUILTIN_CVTTSD2SI64,
25774 IX86_BUILTIN_CVTPS2DQ,
25775 IX86_BUILTIN_CVTPS2PD,
25776 IX86_BUILTIN_CVTTPS2DQ,
25778 IX86_BUILTIN_MOVNTI,
25779 IX86_BUILTIN_MOVNTI64,
25780 IX86_BUILTIN_MOVNTPD,
25781 IX86_BUILTIN_MOVNTDQ,
25783 IX86_BUILTIN_MOVQ128,
25785 /* SSE2 MMX */
25786 IX86_BUILTIN_MASKMOVDQU,
25787 IX86_BUILTIN_MOVMSKPD,
25788 IX86_BUILTIN_PMOVMSKB128,
25790 IX86_BUILTIN_PACKSSWB128,
25791 IX86_BUILTIN_PACKSSDW128,
25792 IX86_BUILTIN_PACKUSWB128,
25794 IX86_BUILTIN_PADDB128,
25795 IX86_BUILTIN_PADDW128,
25796 IX86_BUILTIN_PADDD128,
25797 IX86_BUILTIN_PADDQ128,
25798 IX86_BUILTIN_PADDSB128,
25799 IX86_BUILTIN_PADDSW128,
25800 IX86_BUILTIN_PADDUSB128,
25801 IX86_BUILTIN_PADDUSW128,
25802 IX86_BUILTIN_PSUBB128,
25803 IX86_BUILTIN_PSUBW128,
25804 IX86_BUILTIN_PSUBD128,
25805 IX86_BUILTIN_PSUBQ128,
25806 IX86_BUILTIN_PSUBSB128,
25807 IX86_BUILTIN_PSUBSW128,
25808 IX86_BUILTIN_PSUBUSB128,
25809 IX86_BUILTIN_PSUBUSW128,
25811 IX86_BUILTIN_PAND128,
25812 IX86_BUILTIN_PANDN128,
25813 IX86_BUILTIN_POR128,
25814 IX86_BUILTIN_PXOR128,
25816 IX86_BUILTIN_PAVGB128,
25817 IX86_BUILTIN_PAVGW128,
25819 IX86_BUILTIN_PCMPEQB128,
25820 IX86_BUILTIN_PCMPEQW128,
25821 IX86_BUILTIN_PCMPEQD128,
25822 IX86_BUILTIN_PCMPGTB128,
25823 IX86_BUILTIN_PCMPGTW128,
25824 IX86_BUILTIN_PCMPGTD128,
25826 IX86_BUILTIN_PMADDWD128,
25828 IX86_BUILTIN_PMAXSW128,
25829 IX86_BUILTIN_PMAXUB128,
25830 IX86_BUILTIN_PMINSW128,
25831 IX86_BUILTIN_PMINUB128,
25833 IX86_BUILTIN_PMULUDQ,
25834 IX86_BUILTIN_PMULUDQ128,
25835 IX86_BUILTIN_PMULHUW128,
25836 IX86_BUILTIN_PMULHW128,
25837 IX86_BUILTIN_PMULLW128,
25839 IX86_BUILTIN_PSADBW128,
25840 IX86_BUILTIN_PSHUFHW,
25841 IX86_BUILTIN_PSHUFLW,
25842 IX86_BUILTIN_PSHUFD,
25844 IX86_BUILTIN_PSLLDQI128,
25845 IX86_BUILTIN_PSLLWI128,
25846 IX86_BUILTIN_PSLLDI128,
25847 IX86_BUILTIN_PSLLQI128,
25848 IX86_BUILTIN_PSRAWI128,
25849 IX86_BUILTIN_PSRADI128,
25850 IX86_BUILTIN_PSRLDQI128,
25851 IX86_BUILTIN_PSRLWI128,
25852 IX86_BUILTIN_PSRLDI128,
25853 IX86_BUILTIN_PSRLQI128,
25855 IX86_BUILTIN_PSLLDQ128,
25856 IX86_BUILTIN_PSLLW128,
25857 IX86_BUILTIN_PSLLD128,
25858 IX86_BUILTIN_PSLLQ128,
25859 IX86_BUILTIN_PSRAW128,
25860 IX86_BUILTIN_PSRAD128,
25861 IX86_BUILTIN_PSRLW128,
25862 IX86_BUILTIN_PSRLD128,
25863 IX86_BUILTIN_PSRLQ128,
25865 IX86_BUILTIN_PUNPCKHBW128,
25866 IX86_BUILTIN_PUNPCKHWD128,
25867 IX86_BUILTIN_PUNPCKHDQ128,
25868 IX86_BUILTIN_PUNPCKHQDQ128,
25869 IX86_BUILTIN_PUNPCKLBW128,
25870 IX86_BUILTIN_PUNPCKLWD128,
25871 IX86_BUILTIN_PUNPCKLDQ128,
25872 IX86_BUILTIN_PUNPCKLQDQ128,
25874 IX86_BUILTIN_CLFLUSH,
25875 IX86_BUILTIN_MFENCE,
25876 IX86_BUILTIN_LFENCE,
25877 IX86_BUILTIN_PAUSE,
25879 IX86_BUILTIN_BSRSI,
25880 IX86_BUILTIN_BSRDI,
25881 IX86_BUILTIN_RDPMC,
25882 IX86_BUILTIN_RDTSC,
25883 IX86_BUILTIN_RDTSCP,
25884 IX86_BUILTIN_ROLQI,
25885 IX86_BUILTIN_ROLHI,
25886 IX86_BUILTIN_RORQI,
25887 IX86_BUILTIN_RORHI,
25889 /* SSE3. */
25890 IX86_BUILTIN_ADDSUBPS,
25891 IX86_BUILTIN_HADDPS,
25892 IX86_BUILTIN_HSUBPS,
25893 IX86_BUILTIN_MOVSHDUP,
25894 IX86_BUILTIN_MOVSLDUP,
25895 IX86_BUILTIN_ADDSUBPD,
25896 IX86_BUILTIN_HADDPD,
25897 IX86_BUILTIN_HSUBPD,
25898 IX86_BUILTIN_LDDQU,
25900 IX86_BUILTIN_MONITOR,
25901 IX86_BUILTIN_MWAIT,
25903 /* SSSE3. */
25904 IX86_BUILTIN_PHADDW,
25905 IX86_BUILTIN_PHADDD,
25906 IX86_BUILTIN_PHADDSW,
25907 IX86_BUILTIN_PHSUBW,
25908 IX86_BUILTIN_PHSUBD,
25909 IX86_BUILTIN_PHSUBSW,
25910 IX86_BUILTIN_PMADDUBSW,
25911 IX86_BUILTIN_PMULHRSW,
25912 IX86_BUILTIN_PSHUFB,
25913 IX86_BUILTIN_PSIGNB,
25914 IX86_BUILTIN_PSIGNW,
25915 IX86_BUILTIN_PSIGND,
25916 IX86_BUILTIN_PALIGNR,
25917 IX86_BUILTIN_PABSB,
25918 IX86_BUILTIN_PABSW,
25919 IX86_BUILTIN_PABSD,
25921 IX86_BUILTIN_PHADDW128,
25922 IX86_BUILTIN_PHADDD128,
25923 IX86_BUILTIN_PHADDSW128,
25924 IX86_BUILTIN_PHSUBW128,
25925 IX86_BUILTIN_PHSUBD128,
25926 IX86_BUILTIN_PHSUBSW128,
25927 IX86_BUILTIN_PMADDUBSW128,
25928 IX86_BUILTIN_PMULHRSW128,
25929 IX86_BUILTIN_PSHUFB128,
25930 IX86_BUILTIN_PSIGNB128,
25931 IX86_BUILTIN_PSIGNW128,
25932 IX86_BUILTIN_PSIGND128,
25933 IX86_BUILTIN_PALIGNR128,
25934 IX86_BUILTIN_PABSB128,
25935 IX86_BUILTIN_PABSW128,
25936 IX86_BUILTIN_PABSD128,
25938 /* AMDFAM10 - SSE4A New Instructions. */
25939 IX86_BUILTIN_MOVNTSD,
25940 IX86_BUILTIN_MOVNTSS,
25941 IX86_BUILTIN_EXTRQI,
25942 IX86_BUILTIN_EXTRQ,
25943 IX86_BUILTIN_INSERTQI,
25944 IX86_BUILTIN_INSERTQ,
25946 /* SSE4.1. */
25947 IX86_BUILTIN_BLENDPD,
25948 IX86_BUILTIN_BLENDPS,
25949 IX86_BUILTIN_BLENDVPD,
25950 IX86_BUILTIN_BLENDVPS,
25951 IX86_BUILTIN_PBLENDVB128,
25952 IX86_BUILTIN_PBLENDW128,
25954 IX86_BUILTIN_DPPD,
25955 IX86_BUILTIN_DPPS,
25957 IX86_BUILTIN_INSERTPS128,
25959 IX86_BUILTIN_MOVNTDQA,
25960 IX86_BUILTIN_MPSADBW128,
25961 IX86_BUILTIN_PACKUSDW128,
25962 IX86_BUILTIN_PCMPEQQ,
25963 IX86_BUILTIN_PHMINPOSUW128,
25965 IX86_BUILTIN_PMAXSB128,
25966 IX86_BUILTIN_PMAXSD128,
25967 IX86_BUILTIN_PMAXUD128,
25968 IX86_BUILTIN_PMAXUW128,
25970 IX86_BUILTIN_PMINSB128,
25971 IX86_BUILTIN_PMINSD128,
25972 IX86_BUILTIN_PMINUD128,
25973 IX86_BUILTIN_PMINUW128,
25975 IX86_BUILTIN_PMOVSXBW128,
25976 IX86_BUILTIN_PMOVSXBD128,
25977 IX86_BUILTIN_PMOVSXBQ128,
25978 IX86_BUILTIN_PMOVSXWD128,
25979 IX86_BUILTIN_PMOVSXWQ128,
25980 IX86_BUILTIN_PMOVSXDQ128,
25982 IX86_BUILTIN_PMOVZXBW128,
25983 IX86_BUILTIN_PMOVZXBD128,
25984 IX86_BUILTIN_PMOVZXBQ128,
25985 IX86_BUILTIN_PMOVZXWD128,
25986 IX86_BUILTIN_PMOVZXWQ128,
25987 IX86_BUILTIN_PMOVZXDQ128,
25989 IX86_BUILTIN_PMULDQ128,
25990 IX86_BUILTIN_PMULLD128,
25992 IX86_BUILTIN_ROUNDSD,
25993 IX86_BUILTIN_ROUNDSS,
25995 IX86_BUILTIN_ROUNDPD,
25996 IX86_BUILTIN_ROUNDPS,
25998 IX86_BUILTIN_FLOORPD,
25999 IX86_BUILTIN_CEILPD,
26000 IX86_BUILTIN_TRUNCPD,
26001 IX86_BUILTIN_RINTPD,
26002 IX86_BUILTIN_ROUNDPD_AZ,
26004 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26005 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26006 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26008 IX86_BUILTIN_FLOORPS,
26009 IX86_BUILTIN_CEILPS,
26010 IX86_BUILTIN_TRUNCPS,
26011 IX86_BUILTIN_RINTPS,
26012 IX86_BUILTIN_ROUNDPS_AZ,
26014 IX86_BUILTIN_FLOORPS_SFIX,
26015 IX86_BUILTIN_CEILPS_SFIX,
26016 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26018 IX86_BUILTIN_PTESTZ,
26019 IX86_BUILTIN_PTESTC,
26020 IX86_BUILTIN_PTESTNZC,
26022 IX86_BUILTIN_VEC_INIT_V2SI,
26023 IX86_BUILTIN_VEC_INIT_V4HI,
26024 IX86_BUILTIN_VEC_INIT_V8QI,
26025 IX86_BUILTIN_VEC_EXT_V2DF,
26026 IX86_BUILTIN_VEC_EXT_V2DI,
26027 IX86_BUILTIN_VEC_EXT_V4SF,
26028 IX86_BUILTIN_VEC_EXT_V4SI,
26029 IX86_BUILTIN_VEC_EXT_V8HI,
26030 IX86_BUILTIN_VEC_EXT_V2SI,
26031 IX86_BUILTIN_VEC_EXT_V4HI,
26032 IX86_BUILTIN_VEC_EXT_V16QI,
26033 IX86_BUILTIN_VEC_SET_V2DI,
26034 IX86_BUILTIN_VEC_SET_V4SF,
26035 IX86_BUILTIN_VEC_SET_V4SI,
26036 IX86_BUILTIN_VEC_SET_V8HI,
26037 IX86_BUILTIN_VEC_SET_V4HI,
26038 IX86_BUILTIN_VEC_SET_V16QI,
26040 IX86_BUILTIN_VEC_PACK_SFIX,
26041 IX86_BUILTIN_VEC_PACK_SFIX256,
26043 /* SSE4.2. */
26044 IX86_BUILTIN_CRC32QI,
26045 IX86_BUILTIN_CRC32HI,
26046 IX86_BUILTIN_CRC32SI,
26047 IX86_BUILTIN_CRC32DI,
26049 IX86_BUILTIN_PCMPESTRI128,
26050 IX86_BUILTIN_PCMPESTRM128,
26051 IX86_BUILTIN_PCMPESTRA128,
26052 IX86_BUILTIN_PCMPESTRC128,
26053 IX86_BUILTIN_PCMPESTRO128,
26054 IX86_BUILTIN_PCMPESTRS128,
26055 IX86_BUILTIN_PCMPESTRZ128,
26056 IX86_BUILTIN_PCMPISTRI128,
26057 IX86_BUILTIN_PCMPISTRM128,
26058 IX86_BUILTIN_PCMPISTRA128,
26059 IX86_BUILTIN_PCMPISTRC128,
26060 IX86_BUILTIN_PCMPISTRO128,
26061 IX86_BUILTIN_PCMPISTRS128,
26062 IX86_BUILTIN_PCMPISTRZ128,
26064 IX86_BUILTIN_PCMPGTQ,
26066 /* AES instructions */
26067 IX86_BUILTIN_AESENC128,
26068 IX86_BUILTIN_AESENCLAST128,
26069 IX86_BUILTIN_AESDEC128,
26070 IX86_BUILTIN_AESDECLAST128,
26071 IX86_BUILTIN_AESIMC128,
26072 IX86_BUILTIN_AESKEYGENASSIST128,
26074 /* PCLMUL instruction */
26075 IX86_BUILTIN_PCLMULQDQ128,
26077 /* AVX */
26078 IX86_BUILTIN_ADDPD256,
26079 IX86_BUILTIN_ADDPS256,
26080 IX86_BUILTIN_ADDSUBPD256,
26081 IX86_BUILTIN_ADDSUBPS256,
26082 IX86_BUILTIN_ANDPD256,
26083 IX86_BUILTIN_ANDPS256,
26084 IX86_BUILTIN_ANDNPD256,
26085 IX86_BUILTIN_ANDNPS256,
26086 IX86_BUILTIN_BLENDPD256,
26087 IX86_BUILTIN_BLENDPS256,
26088 IX86_BUILTIN_BLENDVPD256,
26089 IX86_BUILTIN_BLENDVPS256,
26090 IX86_BUILTIN_DIVPD256,
26091 IX86_BUILTIN_DIVPS256,
26092 IX86_BUILTIN_DPPS256,
26093 IX86_BUILTIN_HADDPD256,
26094 IX86_BUILTIN_HADDPS256,
26095 IX86_BUILTIN_HSUBPD256,
26096 IX86_BUILTIN_HSUBPS256,
26097 IX86_BUILTIN_MAXPD256,
26098 IX86_BUILTIN_MAXPS256,
26099 IX86_BUILTIN_MINPD256,
26100 IX86_BUILTIN_MINPS256,
26101 IX86_BUILTIN_MULPD256,
26102 IX86_BUILTIN_MULPS256,
26103 IX86_BUILTIN_ORPD256,
26104 IX86_BUILTIN_ORPS256,
26105 IX86_BUILTIN_SHUFPD256,
26106 IX86_BUILTIN_SHUFPS256,
26107 IX86_BUILTIN_SUBPD256,
26108 IX86_BUILTIN_SUBPS256,
26109 IX86_BUILTIN_XORPD256,
26110 IX86_BUILTIN_XORPS256,
26111 IX86_BUILTIN_CMPSD,
26112 IX86_BUILTIN_CMPSS,
26113 IX86_BUILTIN_CMPPD,
26114 IX86_BUILTIN_CMPPS,
26115 IX86_BUILTIN_CMPPD256,
26116 IX86_BUILTIN_CMPPS256,
26117 IX86_BUILTIN_CVTDQ2PD256,
26118 IX86_BUILTIN_CVTDQ2PS256,
26119 IX86_BUILTIN_CVTPD2PS256,
26120 IX86_BUILTIN_CVTPS2DQ256,
26121 IX86_BUILTIN_CVTPS2PD256,
26122 IX86_BUILTIN_CVTTPD2DQ256,
26123 IX86_BUILTIN_CVTPD2DQ256,
26124 IX86_BUILTIN_CVTTPS2DQ256,
26125 IX86_BUILTIN_EXTRACTF128PD256,
26126 IX86_BUILTIN_EXTRACTF128PS256,
26127 IX86_BUILTIN_EXTRACTF128SI256,
26128 IX86_BUILTIN_VZEROALL,
26129 IX86_BUILTIN_VZEROUPPER,
26130 IX86_BUILTIN_VPERMILVARPD,
26131 IX86_BUILTIN_VPERMILVARPS,
26132 IX86_BUILTIN_VPERMILVARPD256,
26133 IX86_BUILTIN_VPERMILVARPS256,
26134 IX86_BUILTIN_VPERMILPD,
26135 IX86_BUILTIN_VPERMILPS,
26136 IX86_BUILTIN_VPERMILPD256,
26137 IX86_BUILTIN_VPERMILPS256,
26138 IX86_BUILTIN_VPERMIL2PD,
26139 IX86_BUILTIN_VPERMIL2PS,
26140 IX86_BUILTIN_VPERMIL2PD256,
26141 IX86_BUILTIN_VPERMIL2PS256,
26142 IX86_BUILTIN_VPERM2F128PD256,
26143 IX86_BUILTIN_VPERM2F128PS256,
26144 IX86_BUILTIN_VPERM2F128SI256,
26145 IX86_BUILTIN_VBROADCASTSS,
26146 IX86_BUILTIN_VBROADCASTSD256,
26147 IX86_BUILTIN_VBROADCASTSS256,
26148 IX86_BUILTIN_VBROADCASTPD256,
26149 IX86_BUILTIN_VBROADCASTPS256,
26150 IX86_BUILTIN_VINSERTF128PD256,
26151 IX86_BUILTIN_VINSERTF128PS256,
26152 IX86_BUILTIN_VINSERTF128SI256,
26153 IX86_BUILTIN_LOADUPD256,
26154 IX86_BUILTIN_LOADUPS256,
26155 IX86_BUILTIN_STOREUPD256,
26156 IX86_BUILTIN_STOREUPS256,
26157 IX86_BUILTIN_LDDQU256,
26158 IX86_BUILTIN_MOVNTDQ256,
26159 IX86_BUILTIN_MOVNTPD256,
26160 IX86_BUILTIN_MOVNTPS256,
26161 IX86_BUILTIN_LOADDQU256,
26162 IX86_BUILTIN_STOREDQU256,
26163 IX86_BUILTIN_MASKLOADPD,
26164 IX86_BUILTIN_MASKLOADPS,
26165 IX86_BUILTIN_MASKSTOREPD,
26166 IX86_BUILTIN_MASKSTOREPS,
26167 IX86_BUILTIN_MASKLOADPD256,
26168 IX86_BUILTIN_MASKLOADPS256,
26169 IX86_BUILTIN_MASKSTOREPD256,
26170 IX86_BUILTIN_MASKSTOREPS256,
26171 IX86_BUILTIN_MOVSHDUP256,
26172 IX86_BUILTIN_MOVSLDUP256,
26173 IX86_BUILTIN_MOVDDUP256,
26175 IX86_BUILTIN_SQRTPD256,
26176 IX86_BUILTIN_SQRTPS256,
26177 IX86_BUILTIN_SQRTPS_NR256,
26178 IX86_BUILTIN_RSQRTPS256,
26179 IX86_BUILTIN_RSQRTPS_NR256,
26181 IX86_BUILTIN_RCPPS256,
26183 IX86_BUILTIN_ROUNDPD256,
26184 IX86_BUILTIN_ROUNDPS256,
26186 IX86_BUILTIN_FLOORPD256,
26187 IX86_BUILTIN_CEILPD256,
26188 IX86_BUILTIN_TRUNCPD256,
26189 IX86_BUILTIN_RINTPD256,
26190 IX86_BUILTIN_ROUNDPD_AZ256,
26192 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26193 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26194 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26196 IX86_BUILTIN_FLOORPS256,
26197 IX86_BUILTIN_CEILPS256,
26198 IX86_BUILTIN_TRUNCPS256,
26199 IX86_BUILTIN_RINTPS256,
26200 IX86_BUILTIN_ROUNDPS_AZ256,
26202 IX86_BUILTIN_FLOORPS_SFIX256,
26203 IX86_BUILTIN_CEILPS_SFIX256,
26204 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26206 IX86_BUILTIN_UNPCKHPD256,
26207 IX86_BUILTIN_UNPCKLPD256,
26208 IX86_BUILTIN_UNPCKHPS256,
26209 IX86_BUILTIN_UNPCKLPS256,
26211 IX86_BUILTIN_SI256_SI,
26212 IX86_BUILTIN_PS256_PS,
26213 IX86_BUILTIN_PD256_PD,
26214 IX86_BUILTIN_SI_SI256,
26215 IX86_BUILTIN_PS_PS256,
26216 IX86_BUILTIN_PD_PD256,
26218 IX86_BUILTIN_VTESTZPD,
26219 IX86_BUILTIN_VTESTCPD,
26220 IX86_BUILTIN_VTESTNZCPD,
26221 IX86_BUILTIN_VTESTZPS,
26222 IX86_BUILTIN_VTESTCPS,
26223 IX86_BUILTIN_VTESTNZCPS,
26224 IX86_BUILTIN_VTESTZPD256,
26225 IX86_BUILTIN_VTESTCPD256,
26226 IX86_BUILTIN_VTESTNZCPD256,
26227 IX86_BUILTIN_VTESTZPS256,
26228 IX86_BUILTIN_VTESTCPS256,
26229 IX86_BUILTIN_VTESTNZCPS256,
26230 IX86_BUILTIN_PTESTZ256,
26231 IX86_BUILTIN_PTESTC256,
26232 IX86_BUILTIN_PTESTNZC256,
26234 IX86_BUILTIN_MOVMSKPD256,
26235 IX86_BUILTIN_MOVMSKPS256,
26237 /* AVX2 */
26238 IX86_BUILTIN_MPSADBW256,
26239 IX86_BUILTIN_PABSB256,
26240 IX86_BUILTIN_PABSW256,
26241 IX86_BUILTIN_PABSD256,
26242 IX86_BUILTIN_PACKSSDW256,
26243 IX86_BUILTIN_PACKSSWB256,
26244 IX86_BUILTIN_PACKUSDW256,
26245 IX86_BUILTIN_PACKUSWB256,
26246 IX86_BUILTIN_PADDB256,
26247 IX86_BUILTIN_PADDW256,
26248 IX86_BUILTIN_PADDD256,
26249 IX86_BUILTIN_PADDQ256,
26250 IX86_BUILTIN_PADDSB256,
26251 IX86_BUILTIN_PADDSW256,
26252 IX86_BUILTIN_PADDUSB256,
26253 IX86_BUILTIN_PADDUSW256,
26254 IX86_BUILTIN_PALIGNR256,
26255 IX86_BUILTIN_AND256I,
26256 IX86_BUILTIN_ANDNOT256I,
26257 IX86_BUILTIN_PAVGB256,
26258 IX86_BUILTIN_PAVGW256,
26259 IX86_BUILTIN_PBLENDVB256,
26260 IX86_BUILTIN_PBLENDVW256,
26261 IX86_BUILTIN_PCMPEQB256,
26262 IX86_BUILTIN_PCMPEQW256,
26263 IX86_BUILTIN_PCMPEQD256,
26264 IX86_BUILTIN_PCMPEQQ256,
26265 IX86_BUILTIN_PCMPGTB256,
26266 IX86_BUILTIN_PCMPGTW256,
26267 IX86_BUILTIN_PCMPGTD256,
26268 IX86_BUILTIN_PCMPGTQ256,
26269 IX86_BUILTIN_PHADDW256,
26270 IX86_BUILTIN_PHADDD256,
26271 IX86_BUILTIN_PHADDSW256,
26272 IX86_BUILTIN_PHSUBW256,
26273 IX86_BUILTIN_PHSUBD256,
26274 IX86_BUILTIN_PHSUBSW256,
26275 IX86_BUILTIN_PMADDUBSW256,
26276 IX86_BUILTIN_PMADDWD256,
26277 IX86_BUILTIN_PMAXSB256,
26278 IX86_BUILTIN_PMAXSW256,
26279 IX86_BUILTIN_PMAXSD256,
26280 IX86_BUILTIN_PMAXUB256,
26281 IX86_BUILTIN_PMAXUW256,
26282 IX86_BUILTIN_PMAXUD256,
26283 IX86_BUILTIN_PMINSB256,
26284 IX86_BUILTIN_PMINSW256,
26285 IX86_BUILTIN_PMINSD256,
26286 IX86_BUILTIN_PMINUB256,
26287 IX86_BUILTIN_PMINUW256,
26288 IX86_BUILTIN_PMINUD256,
26289 IX86_BUILTIN_PMOVMSKB256,
26290 IX86_BUILTIN_PMOVSXBW256,
26291 IX86_BUILTIN_PMOVSXBD256,
26292 IX86_BUILTIN_PMOVSXBQ256,
26293 IX86_BUILTIN_PMOVSXWD256,
26294 IX86_BUILTIN_PMOVSXWQ256,
26295 IX86_BUILTIN_PMOVSXDQ256,
26296 IX86_BUILTIN_PMOVZXBW256,
26297 IX86_BUILTIN_PMOVZXBD256,
26298 IX86_BUILTIN_PMOVZXBQ256,
26299 IX86_BUILTIN_PMOVZXWD256,
26300 IX86_BUILTIN_PMOVZXWQ256,
26301 IX86_BUILTIN_PMOVZXDQ256,
26302 IX86_BUILTIN_PMULDQ256,
26303 IX86_BUILTIN_PMULHRSW256,
26304 IX86_BUILTIN_PMULHUW256,
26305 IX86_BUILTIN_PMULHW256,
26306 IX86_BUILTIN_PMULLW256,
26307 IX86_BUILTIN_PMULLD256,
26308 IX86_BUILTIN_PMULUDQ256,
26309 IX86_BUILTIN_POR256,
26310 IX86_BUILTIN_PSADBW256,
26311 IX86_BUILTIN_PSHUFB256,
26312 IX86_BUILTIN_PSHUFD256,
26313 IX86_BUILTIN_PSHUFHW256,
26314 IX86_BUILTIN_PSHUFLW256,
26315 IX86_BUILTIN_PSIGNB256,
26316 IX86_BUILTIN_PSIGNW256,
26317 IX86_BUILTIN_PSIGND256,
26318 IX86_BUILTIN_PSLLDQI256,
26319 IX86_BUILTIN_PSLLWI256,
26320 IX86_BUILTIN_PSLLW256,
26321 IX86_BUILTIN_PSLLDI256,
26322 IX86_BUILTIN_PSLLD256,
26323 IX86_BUILTIN_PSLLQI256,
26324 IX86_BUILTIN_PSLLQ256,
26325 IX86_BUILTIN_PSRAWI256,
26326 IX86_BUILTIN_PSRAW256,
26327 IX86_BUILTIN_PSRADI256,
26328 IX86_BUILTIN_PSRAD256,
26329 IX86_BUILTIN_PSRLDQI256,
26330 IX86_BUILTIN_PSRLWI256,
26331 IX86_BUILTIN_PSRLW256,
26332 IX86_BUILTIN_PSRLDI256,
26333 IX86_BUILTIN_PSRLD256,
26334 IX86_BUILTIN_PSRLQI256,
26335 IX86_BUILTIN_PSRLQ256,
26336 IX86_BUILTIN_PSUBB256,
26337 IX86_BUILTIN_PSUBW256,
26338 IX86_BUILTIN_PSUBD256,
26339 IX86_BUILTIN_PSUBQ256,
26340 IX86_BUILTIN_PSUBSB256,
26341 IX86_BUILTIN_PSUBSW256,
26342 IX86_BUILTIN_PSUBUSB256,
26343 IX86_BUILTIN_PSUBUSW256,
26344 IX86_BUILTIN_PUNPCKHBW256,
26345 IX86_BUILTIN_PUNPCKHWD256,
26346 IX86_BUILTIN_PUNPCKHDQ256,
26347 IX86_BUILTIN_PUNPCKHQDQ256,
26348 IX86_BUILTIN_PUNPCKLBW256,
26349 IX86_BUILTIN_PUNPCKLWD256,
26350 IX86_BUILTIN_PUNPCKLDQ256,
26351 IX86_BUILTIN_PUNPCKLQDQ256,
26352 IX86_BUILTIN_PXOR256,
26353 IX86_BUILTIN_MOVNTDQA256,
26354 IX86_BUILTIN_VBROADCASTSS_PS,
26355 IX86_BUILTIN_VBROADCASTSS_PS256,
26356 IX86_BUILTIN_VBROADCASTSD_PD256,
26357 IX86_BUILTIN_VBROADCASTSI256,
26358 IX86_BUILTIN_PBLENDD256,
26359 IX86_BUILTIN_PBLENDD128,
26360 IX86_BUILTIN_PBROADCASTB256,
26361 IX86_BUILTIN_PBROADCASTW256,
26362 IX86_BUILTIN_PBROADCASTD256,
26363 IX86_BUILTIN_PBROADCASTQ256,
26364 IX86_BUILTIN_PBROADCASTB128,
26365 IX86_BUILTIN_PBROADCASTW128,
26366 IX86_BUILTIN_PBROADCASTD128,
26367 IX86_BUILTIN_PBROADCASTQ128,
26368 IX86_BUILTIN_VPERMVARSI256,
26369 IX86_BUILTIN_VPERMDF256,
26370 IX86_BUILTIN_VPERMVARSF256,
26371 IX86_BUILTIN_VPERMDI256,
26372 IX86_BUILTIN_VPERMTI256,
26373 IX86_BUILTIN_VEXTRACT128I256,
26374 IX86_BUILTIN_VINSERT128I256,
26375 IX86_BUILTIN_MASKLOADD,
26376 IX86_BUILTIN_MASKLOADQ,
26377 IX86_BUILTIN_MASKLOADD256,
26378 IX86_BUILTIN_MASKLOADQ256,
26379 IX86_BUILTIN_MASKSTORED,
26380 IX86_BUILTIN_MASKSTOREQ,
26381 IX86_BUILTIN_MASKSTORED256,
26382 IX86_BUILTIN_MASKSTOREQ256,
26383 IX86_BUILTIN_PSLLVV4DI,
26384 IX86_BUILTIN_PSLLVV2DI,
26385 IX86_BUILTIN_PSLLVV8SI,
26386 IX86_BUILTIN_PSLLVV4SI,
26387 IX86_BUILTIN_PSRAVV8SI,
26388 IX86_BUILTIN_PSRAVV4SI,
26389 IX86_BUILTIN_PSRLVV4DI,
26390 IX86_BUILTIN_PSRLVV2DI,
26391 IX86_BUILTIN_PSRLVV8SI,
26392 IX86_BUILTIN_PSRLVV4SI,
26394 IX86_BUILTIN_GATHERSIV2DF,
26395 IX86_BUILTIN_GATHERSIV4DF,
26396 IX86_BUILTIN_GATHERDIV2DF,
26397 IX86_BUILTIN_GATHERDIV4DF,
26398 IX86_BUILTIN_GATHERSIV4SF,
26399 IX86_BUILTIN_GATHERSIV8SF,
26400 IX86_BUILTIN_GATHERDIV4SF,
26401 IX86_BUILTIN_GATHERDIV8SF,
26402 IX86_BUILTIN_GATHERSIV2DI,
26403 IX86_BUILTIN_GATHERSIV4DI,
26404 IX86_BUILTIN_GATHERDIV2DI,
26405 IX86_BUILTIN_GATHERDIV4DI,
26406 IX86_BUILTIN_GATHERSIV4SI,
26407 IX86_BUILTIN_GATHERSIV8SI,
26408 IX86_BUILTIN_GATHERDIV4SI,
26409 IX86_BUILTIN_GATHERDIV8SI,
26411 /* Alternate 4 element gather for the vectorizer where
26412 all operands are 32-byte wide. */
26413 IX86_BUILTIN_GATHERALTSIV4DF,
26414 IX86_BUILTIN_GATHERALTDIV8SF,
26415 IX86_BUILTIN_GATHERALTSIV4DI,
26416 IX86_BUILTIN_GATHERALTDIV8SI,
26418 /* TFmode support builtins. */
26419 IX86_BUILTIN_INFQ,
26420 IX86_BUILTIN_HUGE_VALQ,
26421 IX86_BUILTIN_FABSQ,
26422 IX86_BUILTIN_COPYSIGNQ,
26424 /* Vectorizer support builtins. */
26425 IX86_BUILTIN_CPYSGNPS,
26426 IX86_BUILTIN_CPYSGNPD,
26427 IX86_BUILTIN_CPYSGNPS256,
26428 IX86_BUILTIN_CPYSGNPD256,
26430 /* FMA4 instructions. */
26431 IX86_BUILTIN_VFMADDSS,
26432 IX86_BUILTIN_VFMADDSD,
26433 IX86_BUILTIN_VFMADDPS,
26434 IX86_BUILTIN_VFMADDPD,
26435 IX86_BUILTIN_VFMADDPS256,
26436 IX86_BUILTIN_VFMADDPD256,
26437 IX86_BUILTIN_VFMADDSUBPS,
26438 IX86_BUILTIN_VFMADDSUBPD,
26439 IX86_BUILTIN_VFMADDSUBPS256,
26440 IX86_BUILTIN_VFMADDSUBPD256,
26442 /* FMA3 instructions. */
26443 IX86_BUILTIN_VFMADDSS3,
26444 IX86_BUILTIN_VFMADDSD3,
26446 /* XOP instructions. */
26447 IX86_BUILTIN_VPCMOV,
26448 IX86_BUILTIN_VPCMOV_V2DI,
26449 IX86_BUILTIN_VPCMOV_V4SI,
26450 IX86_BUILTIN_VPCMOV_V8HI,
26451 IX86_BUILTIN_VPCMOV_V16QI,
26452 IX86_BUILTIN_VPCMOV_V4SF,
26453 IX86_BUILTIN_VPCMOV_V2DF,
26454 IX86_BUILTIN_VPCMOV256,
26455 IX86_BUILTIN_VPCMOV_V4DI256,
26456 IX86_BUILTIN_VPCMOV_V8SI256,
26457 IX86_BUILTIN_VPCMOV_V16HI256,
26458 IX86_BUILTIN_VPCMOV_V32QI256,
26459 IX86_BUILTIN_VPCMOV_V8SF256,
26460 IX86_BUILTIN_VPCMOV_V4DF256,
26462 IX86_BUILTIN_VPPERM,
26464 IX86_BUILTIN_VPMACSSWW,
26465 IX86_BUILTIN_VPMACSWW,
26466 IX86_BUILTIN_VPMACSSWD,
26467 IX86_BUILTIN_VPMACSWD,
26468 IX86_BUILTIN_VPMACSSDD,
26469 IX86_BUILTIN_VPMACSDD,
26470 IX86_BUILTIN_VPMACSSDQL,
26471 IX86_BUILTIN_VPMACSSDQH,
26472 IX86_BUILTIN_VPMACSDQL,
26473 IX86_BUILTIN_VPMACSDQH,
26474 IX86_BUILTIN_VPMADCSSWD,
26475 IX86_BUILTIN_VPMADCSWD,
26477 IX86_BUILTIN_VPHADDBW,
26478 IX86_BUILTIN_VPHADDBD,
26479 IX86_BUILTIN_VPHADDBQ,
26480 IX86_BUILTIN_VPHADDWD,
26481 IX86_BUILTIN_VPHADDWQ,
26482 IX86_BUILTIN_VPHADDDQ,
26483 IX86_BUILTIN_VPHADDUBW,
26484 IX86_BUILTIN_VPHADDUBD,
26485 IX86_BUILTIN_VPHADDUBQ,
26486 IX86_BUILTIN_VPHADDUWD,
26487 IX86_BUILTIN_VPHADDUWQ,
26488 IX86_BUILTIN_VPHADDUDQ,
26489 IX86_BUILTIN_VPHSUBBW,
26490 IX86_BUILTIN_VPHSUBWD,
26491 IX86_BUILTIN_VPHSUBDQ,
26493 IX86_BUILTIN_VPROTB,
26494 IX86_BUILTIN_VPROTW,
26495 IX86_BUILTIN_VPROTD,
26496 IX86_BUILTIN_VPROTQ,
26497 IX86_BUILTIN_VPROTB_IMM,
26498 IX86_BUILTIN_VPROTW_IMM,
26499 IX86_BUILTIN_VPROTD_IMM,
26500 IX86_BUILTIN_VPROTQ_IMM,
26502 IX86_BUILTIN_VPSHLB,
26503 IX86_BUILTIN_VPSHLW,
26504 IX86_BUILTIN_VPSHLD,
26505 IX86_BUILTIN_VPSHLQ,
26506 IX86_BUILTIN_VPSHAB,
26507 IX86_BUILTIN_VPSHAW,
26508 IX86_BUILTIN_VPSHAD,
26509 IX86_BUILTIN_VPSHAQ,
26511 IX86_BUILTIN_VFRCZSS,
26512 IX86_BUILTIN_VFRCZSD,
26513 IX86_BUILTIN_VFRCZPS,
26514 IX86_BUILTIN_VFRCZPD,
26515 IX86_BUILTIN_VFRCZPS256,
26516 IX86_BUILTIN_VFRCZPD256,
26518 IX86_BUILTIN_VPCOMEQUB,
26519 IX86_BUILTIN_VPCOMNEUB,
26520 IX86_BUILTIN_VPCOMLTUB,
26521 IX86_BUILTIN_VPCOMLEUB,
26522 IX86_BUILTIN_VPCOMGTUB,
26523 IX86_BUILTIN_VPCOMGEUB,
26524 IX86_BUILTIN_VPCOMFALSEUB,
26525 IX86_BUILTIN_VPCOMTRUEUB,
26527 IX86_BUILTIN_VPCOMEQUW,
26528 IX86_BUILTIN_VPCOMNEUW,
26529 IX86_BUILTIN_VPCOMLTUW,
26530 IX86_BUILTIN_VPCOMLEUW,
26531 IX86_BUILTIN_VPCOMGTUW,
26532 IX86_BUILTIN_VPCOMGEUW,
26533 IX86_BUILTIN_VPCOMFALSEUW,
26534 IX86_BUILTIN_VPCOMTRUEUW,
26536 IX86_BUILTIN_VPCOMEQUD,
26537 IX86_BUILTIN_VPCOMNEUD,
26538 IX86_BUILTIN_VPCOMLTUD,
26539 IX86_BUILTIN_VPCOMLEUD,
26540 IX86_BUILTIN_VPCOMGTUD,
26541 IX86_BUILTIN_VPCOMGEUD,
26542 IX86_BUILTIN_VPCOMFALSEUD,
26543 IX86_BUILTIN_VPCOMTRUEUD,
26545 IX86_BUILTIN_VPCOMEQUQ,
26546 IX86_BUILTIN_VPCOMNEUQ,
26547 IX86_BUILTIN_VPCOMLTUQ,
26548 IX86_BUILTIN_VPCOMLEUQ,
26549 IX86_BUILTIN_VPCOMGTUQ,
26550 IX86_BUILTIN_VPCOMGEUQ,
26551 IX86_BUILTIN_VPCOMFALSEUQ,
26552 IX86_BUILTIN_VPCOMTRUEUQ,
26554 IX86_BUILTIN_VPCOMEQB,
26555 IX86_BUILTIN_VPCOMNEB,
26556 IX86_BUILTIN_VPCOMLTB,
26557 IX86_BUILTIN_VPCOMLEB,
26558 IX86_BUILTIN_VPCOMGTB,
26559 IX86_BUILTIN_VPCOMGEB,
26560 IX86_BUILTIN_VPCOMFALSEB,
26561 IX86_BUILTIN_VPCOMTRUEB,
26563 IX86_BUILTIN_VPCOMEQW,
26564 IX86_BUILTIN_VPCOMNEW,
26565 IX86_BUILTIN_VPCOMLTW,
26566 IX86_BUILTIN_VPCOMLEW,
26567 IX86_BUILTIN_VPCOMGTW,
26568 IX86_BUILTIN_VPCOMGEW,
26569 IX86_BUILTIN_VPCOMFALSEW,
26570 IX86_BUILTIN_VPCOMTRUEW,
26572 IX86_BUILTIN_VPCOMEQD,
26573 IX86_BUILTIN_VPCOMNED,
26574 IX86_BUILTIN_VPCOMLTD,
26575 IX86_BUILTIN_VPCOMLED,
26576 IX86_BUILTIN_VPCOMGTD,
26577 IX86_BUILTIN_VPCOMGED,
26578 IX86_BUILTIN_VPCOMFALSED,
26579 IX86_BUILTIN_VPCOMTRUED,
26581 IX86_BUILTIN_VPCOMEQQ,
26582 IX86_BUILTIN_VPCOMNEQ,
26583 IX86_BUILTIN_VPCOMLTQ,
26584 IX86_BUILTIN_VPCOMLEQ,
26585 IX86_BUILTIN_VPCOMGTQ,
26586 IX86_BUILTIN_VPCOMGEQ,
26587 IX86_BUILTIN_VPCOMFALSEQ,
26588 IX86_BUILTIN_VPCOMTRUEQ,
26590 /* LWP instructions. */
26591 IX86_BUILTIN_LLWPCB,
26592 IX86_BUILTIN_SLWPCB,
26593 IX86_BUILTIN_LWPVAL32,
26594 IX86_BUILTIN_LWPVAL64,
26595 IX86_BUILTIN_LWPINS32,
26596 IX86_BUILTIN_LWPINS64,
26598 IX86_BUILTIN_CLZS,
26600 /* RTM */
26601 IX86_BUILTIN_XBEGIN,
26602 IX86_BUILTIN_XEND,
26603 IX86_BUILTIN_XABORT,
26604 IX86_BUILTIN_XTEST,
26606 /* BMI instructions. */
26607 IX86_BUILTIN_BEXTR32,
26608 IX86_BUILTIN_BEXTR64,
26609 IX86_BUILTIN_CTZS,
26611 /* TBM instructions. */
26612 IX86_BUILTIN_BEXTRI32,
26613 IX86_BUILTIN_BEXTRI64,
26615 /* BMI2 instructions. */
26616 IX86_BUILTIN_BZHI32,
26617 IX86_BUILTIN_BZHI64,
26618 IX86_BUILTIN_PDEP32,
26619 IX86_BUILTIN_PDEP64,
26620 IX86_BUILTIN_PEXT32,
26621 IX86_BUILTIN_PEXT64,
26623 /* ADX instructions. */
26624 IX86_BUILTIN_ADDCARRYX32,
26625 IX86_BUILTIN_ADDCARRYX64,
26627 /* FSGSBASE instructions. */
26628 IX86_BUILTIN_RDFSBASE32,
26629 IX86_BUILTIN_RDFSBASE64,
26630 IX86_BUILTIN_RDGSBASE32,
26631 IX86_BUILTIN_RDGSBASE64,
26632 IX86_BUILTIN_WRFSBASE32,
26633 IX86_BUILTIN_WRFSBASE64,
26634 IX86_BUILTIN_WRGSBASE32,
26635 IX86_BUILTIN_WRGSBASE64,
26637 /* RDRND instructions. */
26638 IX86_BUILTIN_RDRAND16_STEP,
26639 IX86_BUILTIN_RDRAND32_STEP,
26640 IX86_BUILTIN_RDRAND64_STEP,
26642 /* RDSEED instructions. */
26643 IX86_BUILTIN_RDSEED16_STEP,
26644 IX86_BUILTIN_RDSEED32_STEP,
26645 IX86_BUILTIN_RDSEED64_STEP,
26647 /* F16C instructions. */
26648 IX86_BUILTIN_CVTPH2PS,
26649 IX86_BUILTIN_CVTPH2PS256,
26650 IX86_BUILTIN_CVTPS2PH,
26651 IX86_BUILTIN_CVTPS2PH256,
26653 /* CFString built-in for darwin */
26654 IX86_BUILTIN_CFSTRING,
26656 /* Builtins to get CPU type and supported features. */
26657 IX86_BUILTIN_CPU_INIT,
26658 IX86_BUILTIN_CPU_IS,
26659 IX86_BUILTIN_CPU_SUPPORTS,
26661 IX86_BUILTIN_MAX
26662 };
26664 /* Table for the ix86 builtin decls. */
26667 /* Table of all of the builtin functions that are possible with different ISA's
26668 but are waiting to be built until a function is declared to use that
26669 ISA. */
26676 };
26681 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26682 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26683 function decl in the ix86_builtins array. Returns the function decl or
26684 NULL_TREE, if the builtin was not added.
26686 If the front end has a special hook for builtin functions, delay adding
26687 builtin functions that aren't in the current ISA until the ISA is changed
26688 with function specific optimization. Doing so, can save about 300K for the
26689 default compiler. When the builtin is expanded, check at that time whether
26690 it is valid.
26692 If the front end doesn't have a special hook, record all builtins, even if
26693 it isn't an instruction set in the current ISA in case the user uses
26694 function specific options for a different ISA, so that we don't get scope
26695 errors if a builtin is added in the middle of a function scope. */
26701 {
26705 {
26714 {
26720 }
26721 else
26722 {
26728 }
26729 }
26732 }
26734 /* Like def_builtin, but also marks the function decl "const". */
26739 {
26743 else
26747 }
26749 /* Add any new builtin functions for a given ISA that may not have been
26750 declared. This saves a bit of space compared to adding all of the
26751 declarations to the tree, even if we didn't use them. */
26753 static void
26755 {
26759 {
26762 {
26765 /* Don't define the builtin again. */
26771 NULL_TREE);
26776 }
26777 }
26778 }
26780 /* Bits for builtin_description.flag. */
26782 /* Set when we don't support the comparison natively, and should
26783 swap_comparison in order to support it. */
26784 #define BUILTIN_DESC_SWAP_OPERANDS 1
26786 struct builtin_description
26787 {
26794 };
26797 {
26798 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26800 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26801 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26802 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26807 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26808 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26809 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26813 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26822 };
26825 {
26826 /* SSE4.2 */
26827 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26828 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26829 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26830 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26831 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26832 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26833 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26834 };
26837 {
26838 /* SSE4.2 */
26839 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26840 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26841 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26842 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26843 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26844 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26845 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26846 };
26848 /* Special builtins with variable number of arguments. */
26850 {
26851 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26852 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26853 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26855 /* MMX */
26856 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26858 /* 3DNow! */
26859 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26861 /* FXSR, XSAVE and XSAVEOPT */
26862 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26863 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26864 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26865 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26866 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26868 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26869 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26870 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26871 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26872 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26874 /* SSE */
26875 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26876 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26879 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26880 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
26881 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26882 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
26884 /* SSE or 3DNow!A */
26885 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26886 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
26888 /* SSE2 */
26889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26890 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
26891 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26892 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
26893 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26894 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
26895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
26896 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
26897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
26898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
26903 /* SSE3 */
26904 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
26906 /* SSE4.1 */
26907 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
26909 /* SSE4A */
26910 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
26911 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26913 /* AVX */
26914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
26915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
26917 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
26918 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26919 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
26921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
26923 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
26924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
26925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26926 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26927 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
26929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
26931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
26932 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
26933 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
26935 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
26936 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
26937 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
26938 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
26939 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
26940 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
26941 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
26942 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
26944 /* AVX2 */
26945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
26946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
26947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
26948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
26949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
26950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
26951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
26952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
26953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
26955 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
26956 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
26957 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
26958 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
26959 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
26960 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
26962 /* FSGSBASE */
26963 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26964 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26965 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26966 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
26967 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26968 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26969 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
26970 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
26972 /* RTM */
26973 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
26974 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
26975 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
26976 };
26978 /* Builtins with variable number of arguments. */
26980 {
26981 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
26982 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
26983 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
26984 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26985 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26986 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
26987 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
26989 /* MMX */
26990 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26992 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26993 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26994 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26995 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
26997 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
26998 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
26999 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27000 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27001 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27002 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27003 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27004 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27006 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27007 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27009 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27010 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27012 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27014 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27015 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27016 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27017 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27018 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27019 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27021 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27022 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27023 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27024 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27025 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27026 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27028 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27029 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27030 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27032 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27034 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27035 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27042 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27051 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27053 /* 3DNow! */
27054 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27055 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27056 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27057 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27059 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27060 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27061 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27062 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27063 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27064 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27065 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27066 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27067 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27068 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27069 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27070 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27071 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27072 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27073 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27075 /* 3DNow!A */
27076 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27077 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27078 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27079 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27080 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27081 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27083 /* SSE */
27084 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27085 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27086 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27088 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27090 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27092 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27095 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27097 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27099 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27100 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27101 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27102 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27103 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27104 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27105 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27106 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27108 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27109 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27110 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27111 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27112 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27113 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27114 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27115 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27116 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27117 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27118 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27119 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27120 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27121 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27122 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27123 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27124 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27125 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27126 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27127 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27128 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27129 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27131 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27132 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27134 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27136 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27138 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27139 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27141 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27144 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27145 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27146 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27147 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27151 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27153 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27155 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27156 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27157 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27159 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27160 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27162 /* SSE MMX or 3Dnow!A */
27163 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27164 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27165 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27167 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27168 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27169 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27170 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27172 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27173 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27175 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27177 /* SSE2 */
27178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27184 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27195 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27196 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27197 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27200 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27201 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27203 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27204 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27205 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27206 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27208 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27209 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27210 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27212 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27213 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27214 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27215 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27216 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27217 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27218 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27234 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27238 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27239 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27240 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27241 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27243 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27245 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27246 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27247 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27249 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27251 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27252 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27253 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27254 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27255 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27256 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27257 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27258 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27269 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27270 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27272 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27274 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27275 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27278 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27287 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27288 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27289 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27292 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27293 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27294 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27295 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27296 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27297 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27298 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27314 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27319 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27323 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27332 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27335 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27345 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27347 /* SSE2 MMX */
27348 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27349 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27351 /* SSE3 */
27352 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27353 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27355 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27356 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27357 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27358 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27359 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27360 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27362 /* SSSE3 */
27363 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27364 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27365 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27366 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27367 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27368 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27370 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27371 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27372 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27373 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27374 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27375 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27376 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27377 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27378 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27379 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27380 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27381 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27382 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27383 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27384 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27385 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27386 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27387 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27388 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27389 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27390 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27391 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27392 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27393 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27395 /* SSSE3. */
27396 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27397 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27399 /* SSE4.1 */
27400 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27401 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27402 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27403 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27404 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27405 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27406 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27407 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27408 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27409 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27411 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27412 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27413 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27414 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27415 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27416 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27417 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27418 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27419 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27420 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27421 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27422 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27423 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27425 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27438 /* SSE4.1 */
27439 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27440 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27441 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27442 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27444 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27445 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27446 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27447 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27449 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27450 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27452 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27453 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27455 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27456 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27457 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27458 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27460 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27461 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27463 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27464 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27466 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27467 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27468 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27470 /* SSE4.2 */
27471 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27472 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27473 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27474 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27475 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27477 /* SSE4A */
27478 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27479 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27480 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27481 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27483 /* AES */
27484 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27485 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27487 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27488 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27489 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27490 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27492 /* PCLMUL */
27493 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27495 /* AVX */
27496 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27497 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27498 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27499 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27500 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27501 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27502 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27503 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27504 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27505 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27506 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27507 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27508 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27509 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27510 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27511 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27512 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27513 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27514 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27515 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27516 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27517 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27518 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27519 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27520 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27521 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27524 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27530 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27531 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27532 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27533 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27534 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27535 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27536 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27537 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27538 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27539 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27540 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27541 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27542 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27544 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27545 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27547 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27549 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27551 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27567 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27569 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27571 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27583 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27584 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27589 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27592 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27597 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27598 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27602 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27608 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27609 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27610 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27631 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27632 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27634 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27636 /* AVX2 */
27637 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27638 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27639 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27640 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27641 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27642 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27643 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27644 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27645 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27646 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27647 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27648 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27649 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27650 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27651 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27652 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27653 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27654 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27655 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27656 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27657 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27658 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27659 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27660 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27661 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27662 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27663 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27664 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27665 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27666 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27667 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27668 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27669 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27670 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27671 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27672 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27673 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27674 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27675 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27676 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27677 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27678 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27679 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27680 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27681 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27682 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27683 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27684 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27685 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27686 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27687 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27688 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27689 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27690 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27691 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27692 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27693 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27694 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27695 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27696 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27697 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27698 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27699 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27700 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27701 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27702 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27703 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27704 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27705 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27706 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27707 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27708 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27709 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27710 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27711 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27712 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27713 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27714 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27715 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27716 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27717 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27718 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27719 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27720 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27721 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27722 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27723 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27724 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27725 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27726 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27727 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27728 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27729 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27730 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27731 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27732 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27733 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27734 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27735 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27736 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27737 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27738 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27739 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27740 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27741 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27742 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27743 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27744 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27745 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27746 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27747 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27748 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27749 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27750 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27751 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27752 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27753 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27754 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27755 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27756 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27757 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27784 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27786 /* BMI */
27787 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27788 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27789 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27791 /* TBM */
27792 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27793 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27795 /* F16C */
27796 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27797 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27798 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27799 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27801 /* BMI2 */
27802 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27803 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27804 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27805 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27806 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27807 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27808 };
27810 /* FMA4 and XOP. */
27811 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27812 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27813 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27814 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27815 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27816 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27817 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27818 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27819 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27820 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27821 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27822 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27823 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27824 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27825 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27826 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27827 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27828 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27829 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27830 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27831 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27832 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27833 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27834 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27835 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27836 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27837 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27838 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27839 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27840 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27841 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27842 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27843 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27844 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27845 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27846 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27847 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27848 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27849 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27850 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27851 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27852 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27853 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27854 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27855 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27856 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27857 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27858 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27859 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27860 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27861 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27862 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27865 {
27906 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
27907 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
27908 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
27909 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
27910 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
27911 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
27912 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
27914 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27915 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
27916 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
27917 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
27918 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
27919 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
27920 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
27922 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
27924 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27925 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
27926 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27927 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27928 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27929 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
27930 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27931 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27932 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27933 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
27934 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27935 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
27937 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27938 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
27939 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
27940 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
27941 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
27942 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
27943 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
27944 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
27945 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27946 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
27947 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
27948 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
27949 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
27950 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
27951 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
27952 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
27954 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
27955 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
27956 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
27957 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
27958 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
27959 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
27961 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27962 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27963 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27964 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27965 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27966 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27967 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27968 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
27969 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
27970 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27971 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
27972 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27973 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
27974 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
27975 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
27977 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
27978 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27979 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
27980 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
27981 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
27982 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
27983 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
27985 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
27986 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27987 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
27988 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
27989 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
27990 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
27991 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
27993 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
27994 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27995 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
27996 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
27997 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
27998 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
27999 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28001 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28002 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28003 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28004 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28005 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28006 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28007 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28009 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28010 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28011 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28012 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28013 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28014 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28015 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28017 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28018 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28019 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28020 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28021 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28022 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28023 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28025 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28026 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28034 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28042 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28044 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28057 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28064 };
28065 \f
28066 /* TM vector builtins. */
28068 /* Reuse the existing x86-specific `struct builtin_description' cause
28069 we're lazy. Add casts to make them fit. */
28071 {
28072 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28073 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28074 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28075 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28076 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28077 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28078 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28080 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28081 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28082 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28083 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28084 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28085 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28086 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28088 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28089 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28090 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28091 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28092 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28093 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28094 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28096 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28097 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28098 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28099 };
28101 /* TM callbacks. */
28103 /* Return the builtin decl needed to load a vector of TYPE. */
28105 static tree
28107 {
28109 {
28111 {
28118 }
28119 }
28121 }
28123 /* Return the builtin decl needed to store a vector of TYPE. */
28125 static tree
28127 {
28129 {
28131 {
28138 }
28139 }
28141 }
28142 \f
28143 /* Initialize the transactional memory vector load/store builtins. */
28145 static void
28147 {
28151 tree decl;
28158 /* If there are no builtins defined, we must be compiling in a
28159 language without trans-mem support. */
28163 /* Use whatever attributes a normal TM load has. */
28167 /* Use whatever attributes a normal TM store has. */
28171 /* Use whatever attributes a normal TM log has. */
28179 {
28183 {
28191 {
28194 }
28196 {
28199 }
28200 else
28201 {
28204 }
28206 /* The builtin without the prefix for
28207 calling it directly. */
28209 attrs);
28210 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28211 set the TYPE_ATTRIBUTES. */
28215 }
28216 }
28217 }
28219 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28220 in the current target ISA to allow the user to compile particular modules
28221 with different target specific options that differ from the command line
28222 options. */
28223 static void
28225 {
28230 /* Add all special builtins with variable number of operands. */
28234 {
28240 }
28242 /* Add all builtins with variable number of operands. */
28246 {
28252 }
28254 /* pcmpestr[im] insns. */
28258 {
28261 else
28264 }
28266 /* pcmpistr[im] insns. */
28270 {
28273 else
28276 }
28278 /* comi/ucomi insns. */
28280 {
28283 else
28286 }
28288 /* SSE */
28294 /* SSE or 3DNow!A */
28297 IX86_BUILTIN_MASKMOVQ);
28299 /* SSE2 */
28308 /* SSE3. */
28314 /* AES */
28328 /* PCLMUL */
28332 /* RDRND */
28339 IX86_BUILTIN_RDRAND64_STEP);
28341 /* AVX2 */
28343 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28344 IX86_BUILTIN_GATHERSIV2DF);
28347 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28348 IX86_BUILTIN_GATHERSIV4DF);
28351 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28352 IX86_BUILTIN_GATHERDIV2DF);
28355 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28356 IX86_BUILTIN_GATHERDIV4DF);
28359 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28360 IX86_BUILTIN_GATHERSIV4SF);
28363 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28364 IX86_BUILTIN_GATHERSIV8SF);
28367 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28368 IX86_BUILTIN_GATHERDIV4SF);
28371 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28372 IX86_BUILTIN_GATHERDIV8SF);
28375 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28376 IX86_BUILTIN_GATHERSIV2DI);
28379 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28380 IX86_BUILTIN_GATHERSIV4DI);
28383 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28384 IX86_BUILTIN_GATHERDIV2DI);
28387 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28388 IX86_BUILTIN_GATHERDIV4DI);
28391 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28392 IX86_BUILTIN_GATHERSIV4SI);
28395 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28396 IX86_BUILTIN_GATHERSIV8SI);
28399 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28400 IX86_BUILTIN_GATHERDIV4SI);
28403 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28404 IX86_BUILTIN_GATHERDIV8SI);
28407 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28408 IX86_BUILTIN_GATHERALTSIV4DF);
28411 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28412 IX86_BUILTIN_GATHERALTDIV8SF);
28415 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28416 IX86_BUILTIN_GATHERALTSIV4DI);
28419 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28420 IX86_BUILTIN_GATHERALTDIV8SI);
28422 /* RTM. */
28426 /* MMX access to the vec_init patterns. */
28431 V4HI_FTYPE_HI_HI_HI_HI,
28432 IX86_BUILTIN_VEC_INIT_V4HI);
28435 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28436 IX86_BUILTIN_VEC_INIT_V8QI);
28438 /* Access to the vec_extract patterns. */
28460 /* Access to the vec_set patterns. */
28481 /* RDSEED */
28490 /* ADCX */
28495 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28496 IX86_BUILTIN_ADDCARRYX64);
28498 /* Add FMA4 multi-arg argument instructions */
28500 {
28506 }
28507 }
28509 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28510 to return a pointer to VERSION_DECL if the outcome of the expression
28511 formed by PREDICATE_CHAIN is true. This function will be called during
28512 version dispatch to decide which function version to execute. It returns
28513 the basic block at the end, to which more conditions can be added. */
28515 static basic_block
28518 {
28519 gimple return_stmt;
28521 gimple convert_stmt;
28522 gimple call_cond_stmt;
28523 gimple if_else_stmt;
28529 gimple_seq gseq;
28546 {
28554 }
28557 {
28572 else
28573 {
28574 gimple assign_stmt;
28575 /* Use MIN_EXPR to check if any integer is zero?.
28576 and_expr_var = min_expr <cond_var, and_expr_var> */
28584 }
28585 }
28588 integer_zero_node,
28618 }
28620 /* This parses the attribute arguments to target in DECL and determines
28621 the right builtin to use to match the platform specification.
28622 It returns the priority value for this version decl. If PREDICATE_LIST
28623 is not NULL, it stores the list of cpu features that need to be checked
28624 before dispatching this function. */
28626 static unsigned int
28628 {
28629 tree attrs;
28631 tree target_node;
28638 /* Priority of i386 features, greater value is higher priority. This is
28639 used to decide the order in which function dispatch must happen. For
28640 instance, a version specialized for SSE4.2 should be checked for dispatch
28641 before a version for SSE3, as SSE4.2 implies SSE3. */
28642 enum feature_priority
28643 {
28645 P_MMX,
28646 P_SSE,
28647 P_SSE2,
28648 P_SSE3,
28649 P_SSSE3,
28650 P_PROC_SSSE3,
28651 P_SSE4_a,
28652 P_PROC_SSE4_a,
28653 P_SSE4_1,
28654 P_SSE4_2,
28655 P_PROC_SSE4_2,
28656 P_POPCNT,
28657 P_AVX,
28658 P_AVX2,
28659 P_FMA,
28660 P_PROC_FMA
28661 };
28665 /* These are the target attribute strings for which a dispatcher is
28666 available, from fold_builtin_cpu. */
28668 static struct _feature_list
28669 {
28672 }
28674 {
28685 };
28688 static unsigned int NUM_FEATURES
28705 /* Handle arch= if specified. For priority, set it to be 1 more than
28706 the best instruction set the processor can handle. For instance, if
28707 there is a version for atom and a version for ssse3 (the highest ISA
28708 priority for atom), the atom version must be checked for dispatch
28709 before the ssse3 version. */
28711 {
28720 {
28722 {
28747 }
28748 }
28753 {
28757 }
28760 {
28762 /* For a C string literal the length includes the trailing NULL. */
28765 predicate_chain);
28766 }
28767 }
28769 /* Process feature name. */
28776 {
28777 /* Do not process "arch=" */
28779 {
28782 }
28784 {
28786 {
28788 {
28793 predicate_chain);
28794 }
28795 /* Find the maximum priority feature. */
28800 }
28801 }
28803 {
28807 }
28809 }
28813 {
28816 attrs_str);
28818 }
28820 {
28823 }
28826 }
28828 /* This compares the priority of target features in function DECL1
28829 and DECL2. It returns positive value if DECL1 is higher priority,
28830 negative value if DECL2 is higher priority and 0 if they are the
28831 same. */
28833 static int
28835 {
28846 }
28848 /* V1 and V2 point to function versions with different priorities
28849 based on the target ISA. This function compares their priorities. */
28851 static int
28853 {
28855 {
28856 tree version_decl;
28857 tree predicate_chain;
28864 }
28866 /* This function generates the dispatch function for
28867 multi-versioned functions. DISPATCH_DECL is the function which will
28868 contain the dispatch logic. FNDECLS are the function choices for
28869 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28870 in DISPATCH_DECL in which the dispatch code is generated. */
28872 static int
28876 {
28877 tree default_decl;
28878 gimple ifunc_cpu_init_stmt;
28879 gimple_seq gseq;
28881 tree ele;
28887 struct _function_version_info
28888 {
28889 tree version_decl;
28890 tree predicate_chain;
28898 /*fndecls_p is actually a vector. */
28901 /* At least one more version other than the default. */
28908 /* The first version in the vector is the default decl. */
28914 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
28915 constructors, so explicity call __builtin_cpu_init here. */
28926 {
28930 /* Get attribute string, parse it and find the right predicate decl.
28931 The predicate function could be a lengthy combination of many
28932 features, like arch-type and various isa-variants. */
28939 actual_versions++;
28943 }
28945 /* Sort the versions according to descending order of dispatch priority. The
28946 priority is based on the ISA. This is not a perfect solution. There
28947 could still be ambiguity. If more than one function version is suitable
28948 to execute, which one should be dispatched? In future, allow the user
28949 to specify a dispatch priority next to the version. */
28959 /* dispatch default version at the end. */
28965 }
28967 /* Comparator function to be used in qsort routine to sort attribute
28968 specification strings to "target". */
28970 static int
28972 {
28976 }
28978 /* ARGLIST is the argument to target attribute. This function tokenizes
28979 the comma separated arguments, sorts them and returns a string which
28980 is a unique identifier for the comma separated arguments. It also
28981 replaces non-identifier characters "=,-" with "_". */
28985 {
28986 tree arg;
28995 {
29000 argnum++;
29003 argnum++;
29004 }
29009 {
29015 }
29017 /* Replace "=,-" with "_". */
29030 {
29032 i++;
29034 }
29041 {
29046 }
29051 }
29053 /* This function changes the assembler name for functions that are
29054 versions. If DECL is a function version and has a "target"
29055 attribute, it appends the attribute string to its assembler name. */
29057 static tree
29059 {
29060 tree version_attr;
29068 "Function versions cannot be marked as gnu_inline,"
29078 /* target attribute string is NULL for default functions. */
29083 version_string
29094 /* Allow assembler name to be modified if already set. */
29102 }
29104 /* This function returns true if FN1 and FN2 are versions of the same function,
29105 that is, the target strings of the function decls are different. This assumes
29106 that FN1 and FN2 have the same signature. */
29108 static bool
29110 {
29122 /* At least one function decl should have the target attribute specified. */
29126 /* Diagnose missing target attribute if one of the decls is already
29127 multi-versioned. */
29129 {
29131 {
29133 {
29138 }
29141 fn2);
29144 /* Prevent diagnosing of the same error multiple times. */
29149 }
29151 }
29156 /* The sorted target strings must be different for fn1 and fn2
29157 to be versions. */
29160 else
29167 }
29169 static tree
29171 {
29172 /* For function version, add the target suffix to the assembler name. */
29176 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29178 #endif
29181 }
29183 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29184 is true, append the full path name of the source file. */
29188 {
29196 /* Get a unique name that can be used globally without any chances
29197 of collision at link time. */
29207 /* Use '.' to concatenate names as it is demangler friendly. */
29210 suffix);
29211 else
29215 }
29217 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29219 /* Make a dispatcher declaration for the multi-versioned function DECL.
29220 Calls to DECL function will be replaced with calls to the dispatcher
29221 by the front-end. Return the decl created. */
29223 static tree
29225 {
29226 tree func_decl;
29246 /* Mark this func as external, the resolver will flip it again if
29247 it gets generated. */
29249 /* This will be of type IFUNCs have to be externally visible. */
29253 }
29255 #endif
29257 /* Returns true if decl is multi-versioned and DECL is the default function,
29258 that is it is not tagged with target specific optimization. */
29260 static bool
29262 {
29271 }
29273 /* Make a dispatcher declaration for the multi-versioned function DECL.
29274 Calls to DECL function will be replaced with calls to the dispatcher
29275 by the front-end. Returns the decl of the dispatcher function. */
29277 static tree
29279 {
29288 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29292 #endif
29307 /* Find the default version and make it the first node. */
29309 /* Go to the beginnig of the chain. */
29314 {
29319 }
29321 /* If there is no default node, just return NULL. */
29325 /* Make default info the first node. */
29327 {
29334 }
29338 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE) && HAVE_GNU_INDIRECT_FUNCTION
29339 /* Right now, the dispatching is done via ifunc. */
29345 dispatcher_version_info
29350 /* Set the dispatcher for all the versions. */
29353 {
29356 }
29357 #else
29359 "multiversioning needs ifunc which is not supported "
29361 #endif
29363 }
29365 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29366 it to CHAIN. */
29368 static tree
29370 {
29371 tree attr_name;
29372 tree attr_arg_name;
29373 tree attr_args;
29374 tree attr;
29381 }
29383 /* Make the resolver function decl to dispatch the versions of
29384 a multi-versioned function, DEFAULT_DECL. Create an
29385 empty basic block in the resolver and store the pointer in
29386 EMPTY_BB. Return the decl of the resolver function. */
29388 static tree
29392 {
29397 /* IFUNC's have to be globally visible. So, if the default_decl is
29398 not, then the name of the IFUNC should be made unique. */
29402 /* Append the filename to the resolver function if the versions are
29403 not externally visible. This is because the resolver function has
29404 to be externally visible for the loader to find it. So, appending
29405 the filename will prevent conflicts with a resolver function from
29406 another module which is based on the same version name. */
29409 /* The resolver function should return a (void *). */
29420 /* IFUNC resolvers have to be externally visible. */
29424 /* Resolver is not external, body is generated. */
29434 {
29435 /* In this case, each translation unit with a call to this
29436 versioned function will put out a resolver. Ensure it
29437 is comdat to keep just one copy. */
29440 }
29441 /* Build result decl and add to function_decl. */
29457 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29461 /* Create the alias for dispatch to resolver here. */
29462 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29466 }
29468 /* Generate the dispatching code body to dispatch multi-versioned function
29469 DECL. The target hook is called to process the "target" attributes and
29470 provide the code to dispatch the right function at run-time. NODE points
29471 to the dispatcher decl whose body will be created. */
29473 static tree
29475 {
29476 tree resolver_decl;
29477 basic_block empty_bb;
29479 tree default_ver_decl;
29495 /* The first version in the chain corresponds to the default version. */
29498 /* node is going to be an alias, so remove the finalized bit. */
29512 {
29514 /* Check for virtual functions here again, as by this time it should
29515 have been determined if this function needs a vtable index or
29516 not. This happens for methods in derived classes that override
29517 virtual methods in base classes but are not explicitly marked as
29518 virtual. */
29523 }
29530 }
29531 /* This builds the processor_model struct type defined in
29532 libgcc/config/i386/cpuinfo.c */
29534 static tree
29536 {
29543 /* The first 3 fields are unsigned int. */
29545 {
29551 }
29553 /* The last field is an array of unsigned integers of size one. */
29564 }
29566 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29568 static tree
29570 {
29571 tree new_decl;
29574 VAR_DECL,
29576 type);
29589 }
29591 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29592 into an integer defined in libgcc/config/i386/cpuinfo.c */
29594 static tree
29596 {
29602 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29603 enum processor_features
29604 {
29606 F_MMX,
29607 F_POPCNT,
29608 F_SSE,
29609 F_SSE2,
29610 F_SSE3,
29611 F_SSSE3,
29612 F_SSE4_1,
29613 F_SSE4_2,
29614 F_AVX,
29615 F_AVX2,
29616 F_MAX
29617 };
29619 /* These are the values for vendor types and cpu types and subtypes
29620 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29621 the corresponding start value. */
29622 enum processor_model
29623 {
29625 M_AMD,
29626 M_CPU_TYPE_START,
29627 M_INTEL_ATOM,
29628 M_INTEL_CORE2,
29629 M_INTEL_COREI7,
29630 M_AMDFAM10H,
29631 M_AMDFAM15H,
29632 M_CPU_SUBTYPE_START,
29633 M_INTEL_COREI7_NEHALEM,
29634 M_INTEL_COREI7_WESTMERE,
29635 M_INTEL_COREI7_SANDYBRIDGE,
29636 M_AMDFAM10H_BARCELONA,
29637 M_AMDFAM10H_SHANGHAI,
29638 M_AMDFAM10H_ISTANBUL,
29639 M_AMDFAM15H_BDVER1,
29640 M_AMDFAM15H_BDVER2,
29641 M_AMDFAM15H_BDVER3
29642 };
29644 static struct _arch_names_table
29645 {
29648 }
29650 {
29667 };
29669 static struct _isa_names_table
29670 {
29673 }
29675 {
29687 };
29698 {
29699 /* *args must be a expr that can contain other EXPRS leading to a
29700 STRING_CST. */
29702 {
29705 }
29707 }
29712 {
29713 tree ref;
29714 tree field;
29715 tree final;
29718 unsigned int NUM_ARCH_NAMES
29727 {
29731 }
29736 /* CPU types are stored in the next field. */
29739 {
29742 }
29744 /* CPU subtypes are stored in the next field. */
29746 {
29749 }
29751 /* Get the appropriate field in __cpu_model. */
29755 /* Check the value. */
29759 }
29761 {
29762 tree ref;
29763 tree array_elt;
29764 tree field;
29765 tree final;
29768 unsigned int NUM_ISA_NAMES
29777 {
29781 }
29784 /* Get the last field, which is __cpu_features. */
29788 /* Get the appropriate field: __cpu_model.__cpu_features */
29792 /* Access the 0th element of __cpu_features array. */
29797 /* Return __cpu_model.__cpu_features[0] & field_val */
29801 }
29803 }
29805 static tree
29808 {
29810 {
29815 {
29818 }
29819 }
29821 #ifdef SUBTARGET_FOLD_BUILTIN
29823 #endif
29826 }
29828 /* Make builtins to detect cpu type and features supported. NAME is
29829 the builtin name, CODE is the builtin code, and FTYPE is the function
29830 type of the builtin. */
29832 static void
29835 {
29836 tree decl;
29837 tree type;
29845 }
29847 /* Make builtins to get CPU type and features supported. The created
29848 builtins are :
29850 __builtin_cpu_init (), to detect cpu type and features,
29851 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29852 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29853 */
29855 static void
29857 {
29864 }
29866 /* Internal method for ix86_init_builtins. */
29868 static void
29870 {
29882 sysv_va_ref =
29885 fnvoid_va_end_ms =
29887 fnvoid_va_start_ms =
29889 fnvoid_va_end_sysv =
29891 fnvoid_va_start_sysv =
29893 NULL_TREE);
29894 fnvoid_va_copy_ms =
29896 NULL_TREE);
29897 fnvoid_va_copy_sysv =
29913 }
29915 static void
29917 {
29920 /* The __float80 type. */
29923 {
29924 /* The __float80 type. */
29929 }
29932 /* The __float128 type. */
29938 /* This macro is built by i386-builtin-types.awk. */
29939 DEFINE_BUILTIN_PRIMITIVE_TYPES;
29940 }
29942 static void
29944 {
29945 tree t;
29949 /* Builtins to get CPU type and features. */
29952 /* TFmode support builtins. */
29958 /* We will expand them to normal call if SSE isn't available since
29959 they are used by libgcc. */
29978 #ifdef SUBTARGET_INIT_BUILTINS
29979 SUBTARGET_INIT_BUILTINS;
29980 #endif
29981 }
29983 /* Return the ix86 builtin for CODE. */
29985 static tree
29987 {
29992 }
29994 /* Errors in the source file can cause expand_expr to return const0_rtx
29995 where we expect a vector. To avoid crashing, use one of the vector
29996 clear instructions. */
29997 static rtx
29999 {
30003 }
30005 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30007 static rtx
30009 {
30010 rtx pat;
30030 {
30034 }
30048 }
30050 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30052 static rtx
30056 {
30057 rtx pat;
30065 rtx op;
30072 {
30152 }
30162 {
30169 {
30171 {
30174 {
30192 xop_rotl:
30194 {
30197 gcc_checking_assert
30199 }
30200 else
30201 {
30202 gcc_checking_assert
30213 }
30217 }
30218 }
30219 }
30220 else
30221 {
30222 non_constant:
30226 /* If we aren't optimizing, only allow one memory operand to be
30227 generated. */
30229 num_memory++;
30237 }
30241 }
30244 {
30255 else
30256 {
30262 }
30275 }
30282 }
30284 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30285 insns with vec_merge. */
30287 static rtx
30289 rtx target)
30290 {
30291 rtx pat;
30318 }
30320 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30322 static rtx
30325 {
30326 rtx pat;
30331 rtx op2;
30342 /* Swap operands if we have a comparison that isn't available in
30343 hardware. */
30345 {
30350 }
30370 }
30372 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30374 static rtx
30376 rtx target)
30377 {
30378 rtx pat;
30392 /* Swap operands if we have a comparison that isn't available in
30393 hardware. */
30395 {
30399 }
30420 const0_rtx)));
30423 }
30425 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30427 static rtx
30429 rtx target)
30430 {
30431 rtx pat;
30456 }
30458 static rtx
30461 {
30462 rtx pat;
30467 rtx op2;
30494 }
30496 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30498 static rtx
30500 rtx target)
30501 {
30502 rtx pat;
30535 const0_rtx)));
30538 }
30540 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30542 static rtx
30545 {
30546 rtx pat;
30584 {
30587 }
30590 {
30599 }
30601 {
30610 }
30611 else
30612 {
30619 }
30627 {
30632 emit_insn
30636 FLAGS_REG),
30637 const0_rtx)));
30639 }
30640 else
30642 }
30645 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30647 static rtx
30650 {
30651 rtx pat;
30679 {
30682 }
30685 {
30694 }
30696 {
30705 }
30706 else
30707 {
30714 }
30722 {
30727 emit_insn
30731 FLAGS_REG),
30732 const0_rtx)));
30734 }
30735 else
30737 }
30739 /* Subroutine of ix86_expand_builtin to take care of insns with
30740 variable number of operands. */
30742 static rtx
30745 {
30750 struct
30751 {
30752 rtx op;
30764 {
31043 }
31048 {
31051 }
31054 {
31061 }
31062 else
31063 {
31066 }
31069 {
31076 {
31077 /* SIMD shift insns take either an 8-bit immediate or
31078 register as count. But builtin functions take int as
31079 count. If count doesn't match, we put it in register. */
31081 {
31085 }
31086 }
31088 {
31091 {
31145 {
31148 {
31151 }
31157 }
31159 }
31160 }
31161 else
31162 {
31166 /* If we aren't optimizing, only allow one memory operand to
31167 be generated. */
31169 num_memory++;
31172 {
31175 }
31176 else
31177 {
31180 }
31181 }
31185 }
31188 {
31205 }
31212 }
31214 /* Subroutine of ix86_expand_builtin to take care of special insns
31215 with variable number of operands. */
31217 static rtx
31220 {
31221 tree arg;
31224 struct
31225 {
31226 rtx op;
31236 {
31284 /* Reserve memory operand for target. */
31315 /* Reserve memory operand for target. */
31329 }
31334 {
31339 {
31342 }
31343 else
31346 }
31347 else
31348 {
31355 }
31358 {
31367 {
31369 {
31375 else
31378 }
31379 }
31380 else
31381 {
31383 {
31384 /* This must be the memory operand. */
31389 }
31390 else
31391 {
31392 /* This must be register. */
31399 }
31400 }
31404 }
31407 {
31422 }
31428 }
31430 /* Return the integer constant in ARG. Constrain it to be in the range
31431 of the subparts of VEC_TYPE; issue an error if not. */
31433 static int
31435 {
31440 {
31443 }
31446 }
31448 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31449 ix86_expand_vector_init. We DO have language-level syntax for this, in
31450 the form of (type){ init-list }. Except that since we can't place emms
31451 instructions from inside the compiler, we can't allow the use of MMX
31452 registers unless the user explicitly asks for it. So we do *not* define
31453 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31454 we have builtins invoked by mmintrin.h that gives us license to emit
31455 these sorts of instructions. */
31457 static rtx
31459 {
31469 {
31472 }
31479 }
31481 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31482 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31483 had a language-level syntax for referencing vector elements. */
31485 static rtx
31487 {
31491 rtx op0;
31511 }
31513 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31514 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31515 a language-level syntax for referencing vector elements. */
31517 static rtx
31519 {
31543 /* OP0 is the source of these builtin functions and shouldn't be
31544 modified. Create a copy, use it and return it as target. */
31550 }
31552 /* Expand an expression EXP that calls a built-in function,
31553 with result going to TARGET if that's convenient
31554 (and in mode MODE if that's convenient).
31555 SUBTARGET may be used as the target for computing one of EXP's operands.
31556 IGNORE is nonzero if the value is to be ignored. */
31558 static rtx
31562 {
31572 /* For CPU builtins that can be folded, fold first and expand the fold. */
31574 {
31576 {
31577 /* Make it call __cpu_indicator_init in libgcc. */
31583 }
31586 {
31591 }
31592 }
31594 /* Determine whether the builtin function is available under the current ISA.
31595 Originally the builtin was not created if it wasn't applicable to the
31596 current ISA based on the command line switches. With function specific
31597 options, we need to check in the context of the function making the call
31598 whether it is supported. */
31601 {
31607 else
31608 {
31612 }
31614 }
31617 {
31621 ? CODE_FOR_mmx_maskmovq
31623 /* Note the arg order is different from the operand order. */
31724 {
31725 REAL_VALUE_TYPE inf;
31726 rtx tmp;
31738 }
31748 {
31754 insn = (TARGET_64BIT
31758 }
31760 {
31761 insn = (TARGET_64BIT
31765 }
31766 else
31767 {
31770 insn = (TARGET_64BIT
31778 {
31781 }
31783 }
31789 {
31794 }
31804 {
31819 }
31825 {
31828 }
31848 {
31851 }
31857 {
31861 {
31882 }
31887 }
31888 else
31889 {
31891 {
31903 }
31905 }
31935 ? CODE_FOR_tbm_bextri_si
31938 {
31941 }
31942 else
31943 {
31952 }
31968 rdrand_step:
31975 {
31978 }
31984 /* Emit SImode conditional move. */
31986 {
31989 }
31992 else
31999 const0_rtx);
32018 rdseed_step:
32025 {
32028 }
32034 const0_rtx);
32052 addcarryx:
32060 /* Generate CF from input operand. */
32065 /* Gen ADCX instruction to compute X+Y+CF. */
32080 /* Store the result. */
32083 {
32086 }
32089 /* Return current CF value. */
32158 gather_gen:
32169 /* Note the arg order is different from the operand order. */
32178 else
32183 {
32189 }
32192 {
32197 else
32207 }
32209 /* Force memory operand only with base register here. But we
32210 don't want to do it on memory operand for other builtin
32211 functions. */
32223 {
32226 }
32228 /* Optimize. If mask is known to have all high bits set,
32229 replace op0 with pc_rtx to signal that the instruction
32230 overwrites the whole destination and doesn't use its
32231 previous contents. */
32233 {
32235 {
32238 {
32242 negative++;
32245 negative++;
32246 }
32249 }
32251 {
32252 /* Recognize also when mask is like:
32253 __v2df src = _mm_setzero_pd ();
32254 __v2df mask = _mm_cmpeq_pd (src, src);
32255 or
32256 __v8sf src = _mm256_setzero_ps ();
32257 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32258 as that is a cheaper way to load all ones into
32259 a register than having to load a constant from
32260 memory. */
32263 {
32268 {
32275 /* FALLTHRU */
32285 }
32286 }
32287 }
32288 }
32297 {
32304 else
32306 }
32307 else
32318 {
32321 }
32327 }
32340 {
32344 /* Emit a normal call if SSE isn't available. */
32348 }
32373 }
32375 /* Returns a function decl for a vectorized version of the builtin function
32376 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32377 if it is not available. */
32379 static tree
32381 tree type_in)
32382 {
32398 {
32401 {
32406 }
32411 {
32416 }
32422 /* The round insn does not trap on denormals. */
32427 {
32432 }
32438 /* The round insn does not trap on denormals. */
32443 {
32448 }
32454 /* The round insn does not trap on denormals. */
32459 {
32464 }
32470 /* The round insn does not trap on denormals. */
32475 {
32480 }
32487 {
32492 }
32499 {
32504 }
32510 /* The round insn does not trap on denormals. */
32515 {
32520 }
32526 /* The round insn does not trap on denormals. */
32531 {
32536 }
32541 {
32546 }
32551 {
32556 }
32560 /* The round insn does not trap on denormals. */
32565 {
32570 }
32574 /* The round insn does not trap on denormals. */
32579 {
32584 }
32588 /* The round insn does not trap on denormals. */
32593 {
32598 }
32602 /* The round insn does not trap on denormals. */
32607 {
32612 }
32616 /* The round insn does not trap on denormals. */
32621 {
32626 }
32630 /* The round insn does not trap on denormals. */
32635 {
32640 }
32644 /* The round insn does not trap on denormals. */
32649 {
32654 }
32658 /* The round insn does not trap on denormals. */
32663 {
32668 }
32672 /* The round insn does not trap on denormals. */
32677 {
32682 }
32686 /* The round insn does not trap on denormals. */
32691 {
32696 }
32701 {
32706 }
32711 {
32716 }
32721 }
32723 /* Dispatch to a handler for a vectorization library. */
32726 type_in);
32729 }
32731 /* Handler for an SVML-style interface to
32732 a library with vectorized intrinsics. */
32734 static tree
32736 {
32744 /* The SVML is suitable for unsafe math only. */
32757 {
32804 }
32813 {
32816 }
32817 else
32820 /* Convert to uppercase. */
32825 args;
32827 arity++;
32831 else
32834 /* Build a function declaration for the vectorized function. */
32843 }
32845 /* Handler for an ACML-style interface to
32846 a library with vectorized intrinsics. */
32848 static tree
32850 {
32858 /* The ACML is 64bits only and suitable for unsafe math only as
32859 it does not correctly support parts of IEEE with the required
32860 precision such as denormals. */
32874 {
32904 }
32911 args;
32913 arity++;
32917 else
32920 /* Build a function declaration for the vectorized function. */
32929 }
32931 /* Returns a decl of a function that implements gather load with
32932 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
32933 Return NULL_TREE if it is not available. */
32935 static tree
32938 {
32954 /* v*gather* insn sign extends index to pointer mode. */
32966 {
32993 }
32996 }
32998 /* Returns a code for a target-specific builtin that implements
32999 reciprocal of the function, or NULL_TREE if not available. */
33001 static tree
33004 {
33011 /* Machine dependent builtins. */
33013 {
33014 /* Vectorized version of sqrt to rsqrt conversion. */
33023 }
33024 else
33025 /* Normal builtins. */
33027 {
33028 /* Sqrt to rsqrt conversion. */
33034 }
33035 }
33036 \f
33037 /* Helper for avx_vpermilps256_operand et al. This is also used by
33038 the expansion functions to turn the parallel back into a mask.
33039 The return value is 0 for no match and the imm8+1 for a match. */
33041 int
33043 {
33051 /* Validate that all of the elements are constants, and not totally
33052 out of range. Copy the data into an integral array to make the
33053 subsequent checks easier. */
33055 {
33065 }
33068 {
33070 /* In the 256-bit DFmode case, we can only move elements within
33071 a 128-bit lane. */
33073 {
33077 }
33079 {
33083 }
33087 /* In the 256-bit SFmode case, we have full freedom of movement
33088 within the low 128-bit lane, but the high 128-bit lane must
33089 mirror the exact same pattern. */
33094 /* FALLTHRU */
33098 /* In the 128-bit case, we've full freedom in the placement of
33099 the elements from the source operand. */
33106 }
33108 /* Make sure success has a non-zero value by adding one. */
33110 }
33112 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33113 the expansion functions to turn the parallel back into a mask.
33114 The return value is 0 for no match and the imm8+1 for a match. */
33116 int
33118 {
33126 /* Validate that all of the elements are constants, and not totally
33127 out of range. Copy the data into an integral array to make the
33128 subsequent checks easier. */
33130 {
33140 }
33142 /* Validate that the halves of the permute are halves. */
33150 /* Reconstruct the mask. */
33152 {
33158 }
33160 /* Make sure success has a non-zero value by adding one. */
33162 }
33163 \f
33164 /* Store OPERAND to the memory after reload is completed. This means
33165 that we can't easily use assign_stack_local. */
33166 rtx
33168 {
33169 rtx result;
33173 {
33176 stack_pointer_rtx,
33179 }
33181 {
33183 {
33187 /* FALLTHRU */
33193 stack_pointer_rtx)),
33194 operand));
33198 }
33200 }
33201 else
33202 {
33204 {
33206 {
33213 stack_pointer_rtx)),
33219 stack_pointer_rtx)),
33221 }
33224 /* Store HImodes as SImodes. */
33226 /* FALLTHRU */
33232 stack_pointer_rtx)),
33233 operand));
33237 }
33239 }
33241 }
33243 /* Free operand from the memory. */
33244 void
33246 {
33248 {
33253 else
33255 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33256 to pop or add instruction if registers are available. */
33260 }
33261 }
33263 /* Return a register priority for hard reg REGNO. */
33264 static int
33266 {
33267 /* ebp and r13 as the base always wants a displacement, r12 as the
33268 base always wants an index. So discourage their usage in an
33269 address. */
33274 /* New x86-64 int registers result in bigger code size. Discourage
33275 them. */
33278 /* New x86-64 SSE registers result in bigger code size. Discourage
33279 them. */
33282 /* Usage of AX register results in smaller code. Prefer it. */
33286 }
33288 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33290 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33291 QImode must go into class Q_REGS.
33292 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33293 movdf to do mem-to-mem moves through integer regs. */
33295 static reg_class_t
33297 {
33300 /* We're only allowed to return a subclass of CLASS. Many of the
33301 following checks fail for NO_REGS, so eliminate that early. */
33305 /* All classes can load zeros. */
33309 /* Force constants into memory if we are loading a (nonzero) constant into
33310 an MMX or SSE register. This is because there are no MMX/SSE instructions
33311 to load from a constant. */
33316 /* Prefer SSE regs only, if we can use them for math. */
33320 /* Floating-point constants need more complex checks. */
33322 {
33323 /* General regs can load everything. */
33327 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33328 zero above. We only want to wind up preferring 80387 registers if
33329 we plan on doing computation with them. */
33332 {
33333 /* Limit class to non-sse. */
33342 }
33345 }
33347 /* Generally when we see PLUS here, it's the function invariant
33348 (plus soft-fp const_int). Which can only be computed into general
33349 regs. */
33353 /* QImode constants are easy to load, but non-constant QImode data
33354 must go into Q_REGS. */
33356 {
33362 }
33365 }
33367 /* Discourage putting floating-point values in SSE registers unless
33368 SSE math is being used, and likewise for the 387 registers. */
33369 static reg_class_t
33371 {
33374 /* Restrict the output reload class to the register bank that we are doing
33375 math on. If we would like not to return a subset of CLASS, reject this
33376 alternative: if reload cannot do this, it will still use its choice. */
33382 {
33387 else
33389 }
33392 }
33394 static reg_class_t
33397 {
33398 /* Double-word spills from general registers to non-offsettable memory
33399 references (zero-extended addresses) require special handling. */
33405 {
33407 ? CODE_FOR_reload_noff_load
33409 /* Add the cost of moving address to a temporary. */
33413 }
33415 /* QImode spills from non-QI registers require
33416 intermediate register on 32bit targets. */
33425 {
33430 else
33436 /* Return Q_REGS if the operand is in memory. */
33439 }
33441 /* This condition handles corner case where an expression involving
33442 pointers gets vectorized. We're trying to use the address of a
33443 stack slot as a vector initializer.
33445 (set (reg:V2DI 74 [ vect_cst_.2 ])
33446 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33448 Eventually frame gets turned into sp+offset like this:
33450 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33451 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33452 (const_int 392 [0x188]))))
33454 That later gets turned into:
33456 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33457 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33458 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33460 We'll have the following reload recorded:
33462 Reload 0: reload_in (DI) =
33463 (plus:DI (reg/f:DI 7 sp)
33464 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33465 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33466 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33467 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33468 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33469 reload_reg_rtx: (reg:V2DI 22 xmm1)
33471 Which isn't going to work since SSE instructions can't handle scalar
33472 additions. Returning GENERAL_REGS forces the addition into integer
33473 register and reload can handle subsequent reloads without problems. */
33481 }
33483 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33485 static bool
33487 {
33489 {
33504 }
33507 }
33509 /* If we are copying between general and FP registers, we need a memory
33510 location. The same is true for SSE and MMX registers.
33512 To optimize register_move_cost performance, allow inline variant.
33514 The macro can't work reliably when one of the CLASSES is class containing
33515 registers from multiple units (SSE, MMX, integer). We avoid this by never
33516 combining those units in single alternative in the machine description.
33517 Ensure that this constraint holds to avoid unexpected surprises.
33519 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33520 enforce these sanity checks. */
33525 {
33532 {
33535 }
33540 /* ??? This is a lie. We do have moves between mmx/general, and for
33541 mmx/sse2. But by saying we need secondary memory we discourage the
33542 register allocator from using the mmx registers unless needed. */
33547 {
33548 /* SSE1 doesn't have any direct moves from other classes. */
33552 /* If the target says that inter-unit moves are more expensive
33553 than moving through memory, then don't generate them. */
33557 /* Between SSE and general, we have moves no larger than word size. */
33560 }
33563 }
33565 bool
33568 {
33570 }
33572 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33574 On the 80386, this is the size of MODE in words,
33575 except in the FP regs, where a single reg is always enough. */
33577 static unsigned char
33579 {
33581 {
33586 else
33588 }
33589 else
33590 {
33593 else
33595 }
33596 }
33598 /* Return true if the registers in CLASS cannot represent the change from
33599 modes FROM to TO. */
33601 bool
33604 {
33608 /* x87 registers can't do subreg at all, as all values are reformatted
33609 to extended precision. */
33614 {
33615 /* Vector registers do not support QI or HImode loads. If we don't
33616 disallow a change to these modes, reload will assume it's ok to
33617 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33618 the vec_dupv4hi pattern. */
33622 /* Vector registers do not support subreg with nonzero offsets, which
33623 are otherwise valid for integer registers. Since we can't see
33624 whether we have a nonzero offset from here, prohibit all
33625 nonparadoxical subregs changing size. */
33628 }
33631 }
33633 /* Return the cost of moving data of mode M between a
33634 register and memory. A value of 2 is the default; this cost is
33635 relative to those in `REGISTER_MOVE_COST'.
33637 This function is used extensively by register_move_cost that is used to
33638 build tables at startup. Make it inline in this case.
33639 When IN is 2, return maximum of in and out move cost.
33641 If moving between registers and memory is more expensive than
33642 between two registers, you should define this macro to express the
33643 relative cost.
33645 Model also increased moving costs of QImode registers in non
33646 Q_REGS classes.
33647 */
33651 {
33654 {
33657 {
33669 }
33673 }
33675 {
33678 {
33690 }
33694 }
33696 {
33699 {
33708 }
33712 }
33714 {
33717 {
33723 else
33728 }
33729 else
33730 {
33735 else
33737 }
33744 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33751 else
33755 }
33756 }
33758 static int
33761 {
33763 }
33766 /* Return the cost of moving data from a register in class CLASS1 to
33767 one in class CLASS2.
33769 It is not required that the cost always equal 2 when FROM is the same as TO;
33770 on some machines it is expensive to move between registers if they are not
33771 general registers. */
33773 static int
33775 reg_class_t class2_i)
33776 {
33780 /* In case we require secondary memory, compute cost of the store followed
33781 by load. In order to avoid bad register allocation choices, we need
33782 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33785 {
33791 /* In case of copying from general_purpose_register we may emit multiple
33792 stores followed by single load causing memory size mismatch stall.
33793 Count this as arbitrarily high cost of 20. */
33798 /* In the case of FP/MMX moves, the registers actually overlap, and we
33799 have to switch modes in order to treat them differently. */
33805 }
33807 /* Moves between SSE/MMX and integer unit are expensive. */
33811 /* ??? By keeping returned value relatively high, we limit the number
33812 of moves between integer and MMX/SSE registers for all targets.
33813 Additionally, high value prevents problem with x86_modes_tieable_p(),
33814 where integer modes in MMX/SSE registers are not tieable
33815 because of missing QImode and HImode moves to, from or between
33816 MMX/SSE registers. */
33826 }
33828 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33829 MODE. */
33831 bool
33833 {
33834 /* Flags and only flags can only hold CCmode values. */
33844 {
33845 /* We implement the move patterns for all vector modes into and
33846 out of SSE registers, even when no operation instructions
33847 are available. OImode move is available only when AVX is
33848 enabled. */
33855 }
33857 {
33858 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33859 so if the register is available at all, then we can move data of
33860 the given mode into or out of it. */
33863 }
33866 {
33867 /* Take care for QImode values - they can be in non-QI regs,
33868 but then they do cause partial register stalls. */
33874 }
33875 /* We handle both integer and floats in the general purpose registers. */
33882 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
33883 on to use that value in smaller contexts, this can easily force a
33884 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
33885 supporting DImode, allow it. */
33890 }
33892 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
33893 tieable integer mode. */
33895 static bool
33897 {
33899 {
33912 }
33913 }
33915 /* Return true if MODE1 is accessible in a register that can hold MODE2
33916 without copying. That is, all register classes that can hold MODE2
33917 can also hold MODE1. */
33919 bool
33921 {
33929 /* MODE2 being XFmode implies fp stack or general regs, which means we
33930 can tie any smaller floating point modes to it. Note that we do not
33931 tie this with TFmode. */
33935 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
33936 that we can tie it with SFmode. */
33940 /* If MODE2 is only appropriate for an SSE register, then tie with
33941 any other mode acceptable to SSE registers. */
33951 /* If MODE2 is appropriate for an MMX register, then tie
33952 with any other mode acceptable to MMX registers. */
33959 }
33961 /* Return the cost of moving between two registers of mode MODE. */
33963 static int
33965 {
33969 {
34000 }
34002 /* Return the cost of moving between two registers of mode MODE,
34003 assuming that the move will be in pieces of at most UNITS bytes. */
34005 }
34007 /* Compute a (partial) cost for rtx X. Return true if the complete
34008 cost has been computed, and false if subexpressions should be
34009 scanned. In either case, *TOTAL contains the cost result. */
34011 static bool
34014 {
34021 {
34025 {
34028 }
34040 && (!TARGET_64BIT
34045 else
34051 {
34054 }
34056 {
34066 }
34068 {
34071 {
34080 }
34081 }
34082 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34083 it'll probably end up. Add a penalty for size. */
34090 /* The zero extensions is often completely free on x86_64, so make
34091 it as cheap as possible. */
34097 else
34109 {
34112 {
34115 }
34118 {
34121 }
34122 }
34123 /* FALLTHRU */
34130 {
34131 /* ??? Should be SSE vector operation cost. */
34132 /* At least for published AMD latencies, this really is the same
34133 as the latency for a simple fpu operation like fabs. */
34134 /* V*QImode is emulated with 1-11 insns. */
34136 {
34139 {
34140 /* For XOP we use vpshab, which requires a broadcast of the
34141 value to the variable shift insn. For constants this
34142 means a V16Q const in mem; even when we can perform the
34143 shift with one insn set the cost to prefer paddb. */
34145 {
34150 }
34152 }
34156 }
34157 else
34159 }
34161 {
34163 {
34166 else
34168 }
34169 else
34170 {
34173 else
34175 }
34176 }
34177 else
34178 {
34181 else
34183 }
34187 {
34188 rtx sub;
34193 /* ??? SSE scalar/vector cost should be used here. */
34194 /* ??? Bald assumption that fma has the same cost as fmul. */
34198 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34209 }
34213 {
34214 /* ??? SSE scalar cost should be used here. */
34217 }
34219 {
34222 }
34224 {
34225 /* ??? SSE vector cost should be used here. */
34228 }
34230 {
34231 /* V*QImode is emulated with 7-13 insns. */
34233 {
34240 }
34241 /* V*DImode is emulated with 5-8 insns. */
34243 {
34246 else
34248 }
34249 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34250 insns, including two PMULUDQ. */
34253 else
34256 }
34257 else
34258 {
34263 {
34266 nbits++;
34267 }
34268 else
34269 /* This is arbitrary. */
34272 /* Compute costs correctly for widening multiplication. */
34276 {
34283 {
34287 else
34289 }
34293 }
34301 }
34308 /* ??? SSE cost should be used here. */
34313 /* ??? SSE vector cost should be used here. */
34315 else
34322 {
34327 {
34330 {
34338 }
34339 }
34342 {
34345 {
34351 }
34352 }
34354 {
34362 }
34363 }
34364 /* FALLTHRU */
34368 {
34369 /* ??? SSE cost should be used here. */
34372 }
34374 {
34377 }
34379 {
34380 /* ??? SSE vector cost should be used here. */
34383 }
34384 /* FALLTHRU */
34391 {
34398 }
34399 /* FALLTHRU */
34403 {
34404 /* ??? SSE cost should be used here. */
34407 }
34409 {
34412 }
34414 {
34415 /* ??? SSE vector cost should be used here. */
34418 }
34419 /* FALLTHRU */
34423 {
34424 /* ??? Should be SSE vector operation cost. */
34425 /* At least for published AMD latencies, this really is the same
34426 as the latency for a simple fpu operation like fabs. */
34428 }
34431 else
34440 {
34441 /* This kind of construct is implemented using test[bwl].
34442 Treat it as if we had an AND. */
34447 }
34457 /* ??? SSE cost should be used here. */
34462 /* ??? SSE vector cost should be used here. */
34468 /* ??? SSE cost should be used here. */
34473 /* ??? SSE vector cost should be used here. */
34486 /* ??? Assume all of these vector manipulation patterns are
34487 recognizable. In which case they all pretty much have the
34488 same cost. */
34494 }
34495 }
34497 #if TARGET_MACHO
34501 /* Given a symbol name and its associated stub, write out the
34502 definition of the stub. */
34504 void
34506 {
34511 /* For 64-bit we shouldn't get here. */
34514 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34531 else
34538 {
34540 }
34542 {
34543 /* PIC stub. */
34544 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34550 }
34551 else
34554 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34555 it needs no stub-binding-helper. */
34562 {
34565 }
34566 else
34571 /* N.B. Keep the correspondence of these
34572 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34573 old-pic/new-pic/non-pic stubs; altering this will break
34574 compatibility with existing dylibs. */
34576 {
34577 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34579 }
34580 else
34581 /* 16-byte -mdynamic-no-pic stub. */
34587 }
34590 /* Order the registers for register allocator. */
34592 void
34594 {
34598 /* First allocate the local general purpose registers. */
34603 /* Global general purpose registers. */
34608 /* x87 registers come first in case we are doing FP math
34609 using them. */
34614 /* SSE registers. */
34620 /* x87 registers. */
34628 /* Initialize the rest of array as we do not allocate some registers
34629 at all. */
34632 }
34634 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34635 in struct attribute_spec handler. */
34636 static tree
34638 tree args,
34641 {
34646 {
34648 name);
34651 }
34653 {
34655 name);
34658 }
34660 {
34661 tree cst;
34665 {
34668 name);
34670 }
34673 {
34676 name);
34678 }
34681 }
34684 }
34686 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34687 struct attribute_spec.handler. */
34688 static tree
34690 tree args ATTRIBUTE_UNUSED,
34692 {
34697 {
34699 name);
34702 }
34704 /* Can combine regparm with all attributes but fastcall. */
34706 {
34708 {
34710 }
34713 }
34715 {
34717 {
34719 }
34722 }
34725 }
34727 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34728 struct attribute_spec.handler. */
34729 static tree
34731 tree args ATTRIBUTE_UNUSED,
34733 {
34736 {
34739 }
34740 else
34744 {
34746 name);
34748 }
34754 {
34756 name);
34758 }
34761 }
34763 static tree
34765 tree args ATTRIBUTE_UNUSED,
34767 {
34769 {
34771 name);
34773 }
34775 }
34777 static bool
34779 {
34783 }
34785 /* Returns an expression indicating where the this parameter is
34786 located on entry to the FUNCTION. */
34788 static rtx
34790 {
34796 {
34801 else
34804 }
34809 {
34816 {
34821 }
34822 else
34823 {
34826 {
34832 }
34833 }
34835 }
34839 }
34841 /* Determine whether x86_output_mi_thunk can succeed. */
34843 static bool
34845 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34847 {
34848 /* 64-bit can handle anything. */
34852 /* For 32-bit, everything's fine if we have one free register. */
34856 /* Need a free register for vcall_offset. */
34860 /* Need a free register for GOT references. */
34864 /* Otherwise ok. */
34866 }
34868 /* Output the assembler code for a thunk function. THUNK_DECL is the
34869 declaration for the thunk function itself, FUNCTION is the decl for
34870 the target function. DELTA is an immediate constant offset to be
34871 added to THIS. If VCALL_OFFSET is nonzero, the word at
34872 *(*this + vcall_offset) should be added to THIS. */
34874 static void
34878 {
34885 else
34886 {
34892 else
34894 }
34898 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
34899 pull it in now and let DELTA benefit. */
34903 {
34904 /* Put the this parameter into %eax. */
34907 }
34908 else
34911 /* Adjust the this parameter by a fixed constant. */
34913 {
34918 {
34920 {
34924 }
34925 }
34928 }
34930 /* Adjust the this parameter by a value stored in the vtable. */
34932 {
34942 /* Adjust the this parameter. */
34946 {
34950 }
34957 vcall_mem));
34958 else
34960 }
34962 /* If necessary, drop THIS back to its stack slot. */
34968 {
34971 ;
34972 else
34973 {
34977 }
34978 }
34979 else
34980 {
34982 ;
34983 #if TARGET_MACHO
34985 {
34988 }
34990 else
34991 {
34998 }
34999 }
35001 /* Our sibling call patterns do not allow memories, because we have no
35002 predicate that can distinguish between frame and non-frame memory.
35003 For our purposes here, we can get away with (ab)using a jump pattern,
35004 because we're going to do no optimization. */
35007 else
35008 {
35014 {
35020 }
35026 }
35029 /* Emit just enough of rest_of_compilation to get the insns emitted.
35030 Note that use_thunk calls assemble_start_function et al. */
35036 }
35038 static void
35040 {
35042 #if TARGET_MACHO
35044 #endif
35051 }
35053 int
35055 {
35067 }
35069 /* Output assembler code to FILE to increment profiler label # LABELNO
35070 for profiling a function entry. */
35071 void
35073 {
35078 {
35079 #ifndef NO_PROFILE_COUNTERS
35081 #endif
35085 else
35087 }
35089 {
35090 #ifndef NO_PROFILE_COUNTERS
35093 #endif
35095 }
35096 else
35097 {
35098 #ifndef NO_PROFILE_COUNTERS
35101 #endif
35103 }
35104 }
35106 /* We don't have exact information about the insn sizes, but we may assume
35107 quite safely that we are informed about all 1 byte insns and memory
35108 address sizes. This is enough to eliminate unnecessary padding in
35109 99% of cases. */
35111 static int
35113 {
35119 /* Discard alignments we've emit and jump instructions. */
35126 /* Important case - calls are always 5 bytes.
35127 It is common to have many calls in the row. */
35136 /* For normal instructions we rely on get_attr_length being exact,
35137 with a few exceptions. */
35139 {
35143 {
35153 /* Otherwise trust get_attr_length. */
35155 }
35160 }
35163 else
35165 }
35167 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35169 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35170 window. */
35172 static void
35174 {
35179 /* Look for all minimal intervals of instructions containing 4 jumps.
35180 The intervals are bounded by START and INSN. NBYTES is the total
35181 size of instructions in the interval including INSN and not including
35182 START. When the NBYTES is smaller than 16 bytes, it is possible
35183 that the end of START and INSN ends up in the same 16byte page.
35185 The smallest offset in the page INSN can start is the case where START
35186 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35187 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35188 */
35190 {
35194 {
35200 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35201 already in the current 16 byte page, because otherwise
35202 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35203 bytes to reach 16 byte boundary. */
35211 {
35213 {
35220 else
35223 }
35224 }
35226 }
35237 njumps++;
35238 else
35242 {
35249 else
35252 }
35259 {
35266 }
35267 }
35268 }
35269 #endif
35271 /* AMD Athlon works faster
35272 when RET is not destination of conditional jump or directly preceded
35273 by other jump instruction. We avoid the penalty by inserting NOP just
35274 before the RET instructions in such cases. */
35275 static void
35277 {
35278 edge e;
35279 edge_iterator ei;
35282 {
35285 rtx prev;
35295 {
35296 edge e;
35297 edge_iterator ei;
35303 }
35305 {
35311 /* Empty functions get branch mispredict even when
35312 the jump destination is not visible to us. */
35315 }
35317 {
35320 }
35321 }
35322 }
35324 /* Count the minimum number of instructions in BB. Return 4 if the
35325 number of instructions >= 4. */
35327 static int
35329 {
35330 rtx insn;
35333 /* Count number of instructions in this block. Return 4 if the number
35334 of instructions >= 4. */
35336 {
35337 /* Only happen in exit blocks. */
35345 {
35346 insn_count++;
35349 }
35350 }
35353 }
35356 /* Count the minimum number of instructions in code path in BB.
35357 Return 4 if the number of instructions >= 4. */
35359 static int
35361 {
35362 edge e;
35363 edge_iterator ei;
35366 /* Only bother counting instructions along paths with no
35367 more than 2 basic blocks between entry and exit. Given
35368 that BB has an edge to exit, determine if a predecessor
35369 of BB has an edge from entry. If so, compute the number
35370 of instructions in the predecessor block. If there
35371 happen to be multiple such blocks, compute the minimum. */
35374 {
35375 edge prev_e;
35376 edge_iterator prev_ei;
35379 {
35382 }
35384 {
35386 {
35391 }
35392 }
35393 }
35399 }
35401 /* Pad short function to 4 instructions. */
35403 static void
35405 {
35406 edge e;
35407 edge_iterator ei;
35410 {
35413 {
35416 /* Pad short function. */
35418 {
35421 /* Find epilogue. */
35430 /* Two NOPs count as one instruction. */
35433 }
35434 }
35435 }
35436 }
35438 /* Implement machine specific optimizations. We implement padding of returns
35439 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35440 static void
35442 {
35443 /* We are freeing block_for_insn in the toplev to keep compatibility
35444 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35448 {
35453 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35456 #endif
35457 }
35458 }
35460 /* Return nonzero when QImode register that must be represented via REX prefix
35461 is used. */
35462 bool
35464 {
35472 }
35474 /* Return nonzero when P points to register encoded via REX prefix.
35475 Called via for_each_rtx. */
35476 static int
35478 {
35484 }
35486 /* Return true when INSN mentions register that must be encoded using REX
35487 prefix. */
35488 bool
35490 {
35493 }
35495 /* If profitable, negate (without causing overflow) integer constant
35496 of mode MODE at location LOC. Return true in this case. */
35497 bool
35499 {
35500 HOST_WIDE_INT val;
35506 {
35508 /* DImode x86_64 constants must fit in 32 bits. */
35521 }
35523 /* Avoid overflows. */
35529 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35530 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35533 {
35536 }
35539 }
35541 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35542 optabs would emit if we didn't have TFmode patterns. */
35544 void
35546 {
35580 }
35581 \f
35582 /* AVX2 does support 32-byte integer vector operations,
35583 thus the longest vector we are faced with is V32QImode. */
35584 #define MAX_VECT_LEN 32
35586 struct expand_vec_perm_d
35587 {
35594 };
35600 /* Get a vector mode of the same size as the original but with elements
35601 twice as wide. This is only guaranteed to apply to integral vectors. */
35605 {
35606 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35611 }
35613 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35614 with all elements equal to VAR. Return true if successful. */
35616 static bool
35619 {
35623 {
35628 /* FALLTHRU */
35638 {
35641 /* First attempt to recognize VAL as-is. */
35645 {
35646 rtx seq;
35647 /* If that fails, force VAL into a register. */
35658 }
35659 }
35666 {
35667 rtx x;
35674 }
35684 {
35688 permute:
35696 /* Extend to SImode using a paradoxical SUBREG. */
35700 /* Insert the SImode value as low element of a V4SImode vector. */
35708 }
35716 widen:
35717 /* Replicate the value once into the next wider mode and recurse. */
35718 {
35720 rtx x;
35736 }
35740 {
35749 }
35754 }
35755 }
35757 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35758 whose ONE_VAR element is VAR, and other elements are zero. Return true
35759 if successful. */
35761 static bool
35764 {
35766 rtx new_target;
35771 {
35773 /* For SSE4.1, we normally use vector set. But if the second
35774 element is zero and inter-unit moves are OK, we use movq
35775 instead. */
35776 use_vector_set = (TARGET_64BIT
35777 && TARGET_SSE4_1
35778 && !(TARGET_INTER_UNIT_MOVES
35800 /* Use ix86_expand_vector_set in 64bit mode only. */
35805 }
35808 {
35813 }
35816 {
35821 /* FALLTHRU */
35836 else
35843 {
35844 /* We need to shuffle the value to the correct position, so
35845 create a new pseudo to store the intermediate result. */
35847 /* With SSE2, we can use the integer shuffle insns. */
35849 {
35851 const1_rtx,
35858 }
35860 /* Otherwise convert the intermediate result to V4SFmode and
35861 use the SSE1 shuffle instructions. */
35863 {
35866 }
35867 else
35871 const1_rtx,
35880 }
35895 widen:
35899 /* Zero extend the variable element to SImode and recurse. */
35912 }
35913 }
35915 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35916 consisting of the values in VALS. It is known that all elements
35917 except ONE_VAR are constants. Return true if successful. */
35919 static bool
35922 {
35932 {
35937 /* For the two element vectors, it's just as easy to use
35938 the general case. */
35942 /* Use ix86_expand_vector_set in 64bit mode only. */
35964 widen:
35965 /* There's no way to set one QImode entry easily. Combine
35966 the variable value with its adjacent constant value, and
35967 promote to an HImode set. */
35970 {
35975 }
35976 else
35977 {
35980 }
35994 }
35999 }
36001 /* A subroutine of ix86_expand_vector_init_general. Use vector
36002 concatenate to handle the most general case: all values variable,
36003 and none identical. */
36005 static void
36008 {
36011 rtvec v;
36015 {
36018 {
36051 }
36064 {
36079 }
36084 {
36095 }
36098 half:
36099 /* FIXME: We process inputs backward to help RA. PR 36222. */
36103 {
36108 }
36112 {
36115 {
36119 }
36122 }
36123 else
36129 }
36130 }
36132 /* A subroutine of ix86_expand_vector_init_general. Use vector
36133 interleave to handle the most general case: all values variable,
36134 and none identical. */
36136 static void
36139 {
36148 {
36169 }
36172 {
36173 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36177 /* Insert the SImode value as low element of V4SImode vector. */
36181 op0),
36183 const1_rtx);
36186 /* Cast the V4SImode vector back to a vector in orignal mode. */
36190 /* Load even elements into the second positon. */
36194 const1_rtx));
36196 /* Cast vector to FIRST_IMODE vector. */
36199 }
36201 /* Interleave low FIRST_IMODE vectors. */
36203 {
36207 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36210 }
36212 /* Interleave low SECOND_IMODE vectors. */
36214 {
36217 {
36222 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36223 vector. */
36226 }
36229 /* FALLTHRU */
36236 /* Cast the SECOND_IMODE vector back to a vector on original
36237 mode. */
36244 }
36245 }
36247 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36248 all values variable, and none identical. */
36250 static void
36253 {
36259 {
36264 /* FALLTHRU */
36288 half:
36305 /* FALLTHRU */
36311 /* Don't use ix86_expand_vector_init_interleave if we can't
36312 move from GPR to SSE register directly. */
36328 }
36330 {
36342 {
36346 {
36352 else
36353 {
36358 }
36359 }
36362 }
36367 {
36373 }
36375 {
36381 }
36382 else
36384 }
36385 }
36387 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36388 instructions unless MMX_OK is true. */
36390 void
36392 {
36399 rtx x;
36402 {
36412 }
36414 /* Constants are best loaded from the constant pool. */
36416 {
36419 }
36421 /* If all values are identical, broadcast the value. */
36427 /* Values where only one field is non-constant are best loaded from
36428 the pool and overwritten via move later. */
36430 {
36434 one_var))
36439 }
36442 }
36444 void
36446 {
36451 rtx tmp;
36453 = {
36460 };
36462 = {
36469 };
36473 {
36477 {
36482 else
36486 }
36498 else
36504 {
36507 /* For the two element vectors, we implement a VEC_CONCAT with
36508 the extraction of the other element. */
36515 else
36520 }
36529 {
36535 /* tmp = target = A B C D */
36537 /* target = A A B B */
36539 /* target = X A B B */
36541 /* target = A X C D */
36548 /* tmp = target = A B C D */
36550 /* tmp = X B C D */
36552 /* target = A B X D */
36559 /* tmp = target = A B C D */
36561 /* tmp = X B C D */
36563 /* target = A B X D */
36571 }
36579 /* Element 0 handled by vec_merge below. */
36581 {
36584 }
36587 {
36588 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36589 store into element 0, then shuffle them back. */
36606 }
36607 else
36608 {
36609 /* For SSE1, we have to reuse the V4SF code. */
36612 }
36665 half:
36666 /* Compute offset. */
36672 /* Extract the half. */
36676 /* Put val in tmp at elt. */
36679 /* Put it back. */
36685 }
36688 {
36692 }
36693 else
36694 {
36703 }
36704 }
36706 void
36708 {
36712 rtx tmp;
36715 {
36720 /* FALLTHRU */
36733 {
36753 }
36765 {
36767 {
36787 }
36791 }
36792 else
36793 {
36794 /* For SSE1, we have to reuse the V4SF code. */
36798 }
36814 {
36818 else
36822 }
36827 {
36831 else
36835 }
36840 {
36844 else
36848 }
36853 {
36857 else
36861 }
36866 {
36870 else
36874 }
36879 {
36883 else
36887 }
36891 /* ??? Could extract the appropriate HImode element and shift. */
36894 }
36897 {
36901 /* Let the rtl optimizers know about the zero extension performed. */
36903 {
36906 }
36909 }
36910 else
36911 {
36918 }
36919 }
36921 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
36922 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
36923 The upper bits of DEST are undefined, though they shouldn't cause
36924 exceptions (some bits from src or all zeros are ok). */
36926 static void
36928 {
36929 rtx tem;
36931 {
36935 else
36953 else
36960 else
36971 const1_rtx);
36972 else
36979 }
36981 }
36983 /* Expand a vector reduction. FN is the binary pattern to reduce;
36984 DEST is the destination; IN is the input vector. */
36986 void
36988 {
36993 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
36997 {
37000 }
37005 {
37010 else
37014 }
37015 }
37016 \f
37017 /* Target hook for scalar_mode_supported_p. */
37018 static bool
37020 {
37025 else
37027 }
37029 /* Implements target hook vector_mode_supported_p. */
37030 static bool
37032 {
37044 }
37046 /* Target hook for c_mode_for_suffix. */
37047 static enum machine_mode
37049 {
37056 }
37058 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37060 We do this in the new i386 backend to maintain source compatibility
37061 with the old cc0-based compiler. */
37063 static tree
37065 tree inputs ATTRIBUTE_UNUSED,
37066 tree clobbers)
37067 {
37069 clobbers);
37071 clobbers);
37073 }
37075 /* Implements target vector targetm.asm.encode_section_info. */
37077 static void ATTRIBUTE_UNUSED
37079 {
37086 }
37088 /* Worker function for REVERSE_CONDITION. */
37090 enum rtx_code
37092 {
37096 }
37098 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37099 to OPERANDS[0]. */
37103 {
37105 {
37108 {
37112 }
37116 }
37118 {
37122 else
37123 {
37124 /* There is no non-popping store to memory for XFmode.
37125 So if we need one, follow the store with a load. */
37128 else
37130 }
37131 }
37132 else
37134 }
37136 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37137 FP status register is set. */
37139 void
37141 {
37143 rtx temp;
37148 {
37153 }
37154 else
37155 {
37160 }
37164 pc_rtx);
37169 }
37171 /* Output code to perform a log1p XFmode calculation. */
37174 {
37180 rtx test;
37186 XFmode));
37200 }
37202 /* Emit code for round calculation. */
37204 {
37211 rtx insn;
37216 {
37228 }
37231 {
37252 }
37260 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37262 /* scratch = fxam(op1) */
37265 UNSPEC_FXAM)));
37266 /* e1 = fabs(op1) */
37269 /* e2 = e1 + 0.5 */
37274 /* res = floor(e2) */
37276 {
37281 }
37282 else
37286 {
37289 {
37296 UNSPEC_TRUNC_NOOP)));
37297 }
37313 }
37315 /* flags = signbit(a) */
37318 /* if (flags) then res = -res */
37322 pc_rtx);
37333 }
37335 /* Output code to perform a Newton-Rhapson approximation of a single precision
37336 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37339 {
37347 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37351 /* x0 = rcp(b) estimate */
37354 UNSPEC_RCP)));
37355 /* e0 = x0 * b */
37359 /* e0 = x0 * e0 */
37363 /* e1 = x0 + x0 */
37367 /* x1 = e1 - e0 */
37371 /* res = a * x1 */
37374 }
37376 /* Output code to perform a Newton-Rhapson approximation of a
37377 single precision floating point [reciprocal] square root. */
37381 {
37383 REAL_VALUE_TYPE r;
37398 {
37401 }
37403 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37404 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37408 /* x0 = rsqrt(a) estimate */
37411 UNSPEC_RSQRT)));
37413 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37415 {
37427 }
37429 /* e0 = x0 * a */
37432 /* e1 = e0 * x0 */
37436 /* e2 = e1 - 3. */
37443 /* e3 = -.5 * x0 */
37446 else
37447 /* e3 = -.5 * e0 */
37450 /* ret = e2 * e3 */
37453 }
37455 #ifdef TARGET_SOLARIS
37456 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37458 static void
37460 tree decl)
37461 {
37462 /* With Binutils 2.15, the "@unwind" marker must be specified on
37463 every occurrence of the ".eh_frame" section, not just the first
37464 one. */
37467 {
37471 }
37473 #ifndef USE_GAS
37475 {
37478 }
37479 #endif
37482 }
37485 /* Return the mangling of TYPE if it is an extended fundamental type. */
37489 {
37497 {
37499 /* __float128 is "g". */
37502 /* "long double" or __float80 is "e". */
37506 }
37507 }
37509 /* For 32-bit code we can save PIC register setup by using
37510 __stack_chk_fail_local hidden function instead of calling
37511 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37512 register, so it is better to call __stack_chk_fail directly. */
37514 static tree ATTRIBUTE_UNUSED
37516 {
37517 return TARGET_64BIT
37520 }
37522 /* Select a format to encode pointers in exception handling data. CODE
37523 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37524 true if the symbol may be affected by dynamic relocations.
37526 ??? All x86 object file formats are capable of representing this.
37527 After all, the relocation needed is the same as for the call insn.
37528 Whether or not a particular assembler allows us to enter such, I
37529 guess we'll have to see. */
37530 int
37532 {
37534 {
37541 }
37546 }
37547 \f
37548 /* Expand copysign from SIGN to the positive value ABS_VALUE
37549 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37550 the sign-bit. */
37551 static void
37553 {
37557 {
37564 else
37569 {
37570 /* We need to generate a scalar mode mask in this case. */
37575 }
37576 }
37577 else
37583 }
37585 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37586 mask for masking out the sign-bit is stored in *SMASK, if that is
37587 non-null. */
37588 static rtx
37590 {
37599 else
37603 {
37604 /* We need to generate a scalar mode mask in this case. */
37609 }
37617 }
37619 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37620 swapping the operands if SWAP_OPERANDS is true. The expanded
37621 code is a forward jump to a newly created label in case the
37622 comparison is true. The generated label rtx is returned. */
37623 static rtx
37626 {
37630 {
37634 }
37647 }
37649 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37650 using comparison code CODE. Operands are swapped for the comparison if
37651 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37652 static rtx
37655 {
37661 {
37665 }
37672 }
37674 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37675 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37676 static rtx
37678 {
37679 REAL_VALUE_TYPE TWO52r;
37680 rtx TWO52;
37687 }
37689 /* Expand SSE sequence for computing lround from OP1 storing
37690 into OP0. */
37691 void
37693 {
37694 /* C code for the stuff we're doing below:
37695 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37696 return (long)tmp;
37697 */
37701 rtx adj;
37703 /* load nextafter (0.5, 0.0) */
37708 /* adj = copysign (0.5, op1) */
37712 /* adj = op1 + adj */
37715 /* op0 = (imode)adj */
37717 }
37719 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37720 into OPERAND0. */
37721 void
37723 {
37724 /* C code for the stuff we're doing below (for do_floor):
37725 xi = (long)op1;
37726 xi -= (double)xi > op1 ? 1 : 0;
37727 return xi;
37728 */
37733 /* reg = (long)op1 */
37737 /* freg = (double)reg */
37741 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37752 }
37754 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37755 result in OPERAND0. */
37756 void
37758 {
37759 /* C code for the stuff we're doing below:
37760 xa = fabs (operand1);
37761 if (!isless (xa, 2**52))
37762 return operand1;
37763 xa = xa + 2**52 - 2**52;
37764 return copysign (xa, operand1);
37765 */
37772 /* xa = abs (operand1) */
37775 /* if (!isless (xa, TWO52)) goto label; */
37788 }
37790 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37791 into OPERAND0. */
37792 void
37794 {
37795 /* C code for the stuff we expand below.
37796 double xa = fabs (x), x2;
37797 if (!isless (xa, TWO52))
37798 return x;
37799 xa = xa + TWO52 - TWO52;
37800 x2 = copysign (xa, x);
37801 Compensate. Floor:
37802 if (x2 > x)
37803 x2 -= 1;
37804 Compensate. Ceil:
37805 if (x2 < x)
37806 x2 -= -1;
37807 return x2;
37808 */
37814 /* Temporary for holding the result, initialized to the input
37815 operand to ease control flow. */
37819 /* xa = abs (operand1) */
37822 /* if (!isless (xa, TWO52)) goto label; */
37825 /* xa = xa + TWO52 - TWO52; */
37829 /* xa = copysign (xa, operand1) */
37832 /* generate 1.0 or -1.0 */
37837 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37841 /* We always need to subtract here to preserve signed zero. */
37850 }
37852 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37853 into OPERAND0. */
37854 void
37856 {
37857 /* C code for the stuff we expand below.
37858 double xa = fabs (x), x2;
37859 if (!isless (xa, TWO52))
37860 return x;
37861 x2 = (double)(long)x;
37862 Compensate. Floor:
37863 if (x2 > x)
37864 x2 -= 1;
37865 Compensate. Ceil:
37866 if (x2 < x)
37867 x2 += 1;
37868 if (HONOR_SIGNED_ZEROS (mode))
37869 return copysign (x2, x);
37870 return x2;
37871 */
37877 /* Temporary for holding the result, initialized to the input
37878 operand to ease control flow. */
37882 /* xa = abs (operand1) */
37885 /* if (!isless (xa, TWO52)) goto label; */
37888 /* xa = (double)(long)x */
37893 /* generate 1.0 */
37896 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37911 }
37913 /* Expand SSE sequence for computing round from OPERAND1 storing
37914 into OPERAND0. Sequence that works without relying on DImode truncation
37915 via cvttsd2siq that is only available on 64bit targets. */
37916 void
37918 {
37919 /* C code for the stuff we expand below.
37920 double xa = fabs (x), xa2, x2;
37921 if (!isless (xa, TWO52))
37922 return x;
37923 Using the absolute value and copying back sign makes
37924 -0.0 -> -0.0 correct.
37925 xa2 = xa + TWO52 - TWO52;
37926 Compensate.
37927 dxa = xa2 - xa;
37928 if (dxa <= -0.5)
37929 xa2 += 1;
37930 else if (dxa > 0.5)
37931 xa2 -= 1;
37932 x2 = copysign (xa2, x);
37933 return x2;
37934 */
37940 /* Temporary for holding the result, initialized to the input
37941 operand to ease control flow. */
37945 /* xa = abs (operand1) */
37948 /* if (!isless (xa, TWO52)) goto label; */
37951 /* xa2 = xa + TWO52 - TWO52; */
37955 /* dxa = xa2 - xa; */
37958 /* generate 0.5, 1.0 and -0.5 */
37964 /* Compensate. */
37966 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
37971 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
37977 /* res = copysign (xa2, operand1) */
37984 }
37986 /* Expand SSE sequence for computing trunc from OPERAND1 storing
37987 into OPERAND0. */
37988 void
37990 {
37991 /* C code for SSE variant we expand below.
37992 double xa = fabs (x), x2;
37993 if (!isless (xa, TWO52))
37994 return x;
37995 x2 = (double)(long)x;
37996 if (HONOR_SIGNED_ZEROS (mode))
37997 return copysign (x2, x);
37998 return x2;
37999 */
38005 /* Temporary for holding the result, initialized to the input
38006 operand to ease control flow. */
38010 /* xa = abs (operand1) */
38013 /* if (!isless (xa, TWO52)) goto label; */
38016 /* x = (double)(long)x */
38028 }
38030 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38031 into OPERAND0. */
38032 void
38034 {
38038 /* C code for SSE variant we expand below.
38039 double xa = fabs (x), x2;
38040 if (!isless (xa, TWO52))
38041 return x;
38042 xa2 = xa + TWO52 - TWO52;
38043 Compensate:
38044 if (xa2 > xa)
38045 xa2 -= 1.0;
38046 x2 = copysign (xa2, x);
38047 return x2;
38048 */
38052 /* Temporary for holding the result, initialized to the input
38053 operand to ease control flow. */
38057 /* xa = abs (operand1) */
38060 /* if (!isless (xa, TWO52)) goto label; */
38063 /* res = xa + TWO52 - TWO52; */
38068 /* generate 1.0 */
38071 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38079 /* res = copysign (res, operand1) */
38086 }
38088 /* Expand SSE sequence for computing round from OPERAND1 storing
38089 into OPERAND0. */
38090 void
38092 {
38093 /* C code for the stuff we're doing below:
38094 double xa = fabs (x);
38095 if (!isless (xa, TWO52))
38096 return x;
38097 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38098 return copysign (xa, x);
38099 */
38105 /* Temporary for holding the result, initialized to the input
38106 operand to ease control flow. */
38114 /* load nextafter (0.5, 0.0) */
38119 /* xa = xa + 0.5 */
38123 /* xa = (double)(int64_t)xa */
38128 /* res = copysign (xa, operand1) */
38135 }
38137 /* Expand SSE sequence for computing round
38138 from OP1 storing into OP0 using sse4 round insn. */
38139 void
38141 {
38150 {
38161 }
38163 /* round (a) = trunc (a + copysign (0.5, a)) */
38165 /* load nextafter (0.5, 0.0) */
38171 /* e1 = copysign (0.5, op1) */
38175 /* e2 = op1 + e1 */
38178 /* res = trunc (e2) */
38183 }
38184 \f
38186 /* Table of valid machine attributes. */
38188 {
38189 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38190 affects_type_identity } */
38191 /* Stdcall attribute says callee is responsible for popping arguments
38192 if they are not variable. */
38195 /* Fastcall attribute says callee is responsible for popping arguments
38196 if they are not variable. */
38199 /* Thiscall attribute says callee is responsible for popping arguments
38200 if they are not variable. */
38203 /* Cdecl attribute says the callee is a normal C declaration */
38206 /* Regparm attribute specifies how many integer arguments are to be
38207 passed in registers. */
38210 /* Sseregparm attribute says we are using x86_64 calling conventions
38211 for FP arguments. */
38214 /* The transactional memory builtins are implicitly regparm or fastcall
38215 depending on the ABI. Override the generic do-nothing attribute that
38216 these builtins were declared with. */
38219 /* force_align_arg_pointer says this function realigns the stack at entry. */
38222 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38227 #endif
38232 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38233 SUBTARGET_ATTRIBUTE_TABLE,
38234 #endif
38235 /* ms_abi and sysv_abi calling convention function attributes. */
38242 /* End element. */
38244 };
38246 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38247 static int
38249 tree vectype,
38251 {
38255 {
38300 }
38301 }
38303 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38304 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38305 insn every time. */
38309 /* Initialize vselect_insn. */
38311 static void
38313 {
38315 rtx x;
38326 }
38328 /* Construct (set target (vec_select op0 (parallel perm))) and
38329 return true if that's a valid instruction in the active ISA. */
38331 static bool
38334 {
38360 }
38362 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38364 static bool
38368 {
38370 rtx x;
38385 }
38387 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38388 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38390 static bool
38392 {
38401 ;
38403 ;
38405 ;
38406 else
38409 /* This is a blend, not a permute. Elements must stay in their
38410 respective lanes. */
38412 {
38416 }
38421 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38422 decision should be extracted elsewhere, so that we only try that
38423 sequence once all budget==3 options have been tried. */
38430 {
38454 /* See if bytes move in pairs so we can use pblendw with
38455 an immediate argument, rather than pblendvb with a vector
38456 argument. */
38459 {
38460 use_pblendvb:
38464 finish_pblendvb:
38470 else
38473 }
38478 /* FALLTHRU */
38480 do_subreg:
38487 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38491 /* See if bytes move in quadruplets. If yes, vpblendd
38492 with immediate can be used. */
38497 {
38498 /* See if bytes move the same in both lanes. If yes,
38499 vpblendw with immediate can be used. */
38504 /* Use vpblendw. */
38509 }
38511 /* Use vpblendd. */
38518 /* See if words move in pairs. If yes, vpblendd can be used. */
38523 {
38524 /* See if words move the same in both lanes. If not,
38525 vpblendvb must be used. */
38528 {
38529 /* Use vpblendvb. */
38539 }
38541 /* Use vpblendw. */
38545 }
38547 /* Use vpblendd. */
38554 /* Use vpblendd. */
38562 }
38564 /* This matches five different patterns with the different modes. */
38570 }
38572 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38573 in terms of the variable form of vpermilps.
38575 Note that we will have already failed the immediate input vpermilps,
38576 which requires that the high and low part shuffle be identical; the
38577 variable form doesn't require that. */
38579 static bool
38581 {
38588 /* We can only permute within the 128-bit lane. */
38590 {
38594 }
38600 {
38603 /* Within each 128-bit lane, the elements of op0 are numbered
38604 from 0 and the elements of op1 are numbered from 4. */
38611 }
38618 }
38620 /* Return true if permutation D can be performed as VMODE permutation
38621 instead. */
38623 static bool
38625 {
38640 else
38646 }
38648 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38649 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38651 static bool
38653 {
38662 {
38664 {
38667 {
38671 /* Use vperm2i128 insn. The pattern uses
38672 V4DImode instead of V2TImode. */
38681 }
38683 }
38684 }
38685 else
38686 {
38688 {
38691 }
38693 {
38697 /* V4DImode should be already handled through
38698 expand_vselect by vpermq instruction. */
38705 {
38706 /* First see if vpermq can be used for
38707 V8SImode/V16HImode/V32QImode. */
38709 {
38717 }
38719 /* Next see if vpermd can be used. */
38722 }
38723 /* Or if vpermps can be used. */
38728 {
38729 /* vpshufb only works intra lanes, it is not
38730 possible to shuffle bytes in between the lanes. */
38734 }
38735 }
38736 else
38738 }
38746 else
38747 {
38753 else
38757 {
38761 }
38762 }
38771 {
38778 else
38780 }
38781 else
38782 {
38785 }
38788 }
38790 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38791 in a single instruction. */
38793 static bool
38795 {
38799 /* Check plain VEC_SELECT first, because AVX has instructions that could
38800 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38801 input where SEL+CONCAT may not. */
38803 {
38809 {
38815 }
38818 {
38822 }
38824 {
38825 /* Use vpbroadcast{b,w,d}. */
38828 {
38847 /* For other modes prefer other shuffles this function creates. */
38849 }
38851 {
38855 }
38856 }
38861 /* There are plenty of patterns in sse.md that are written for
38862 SEL+CONCAT and are not replicated for a single op. Perhaps
38863 that should be changed, to avoid the nastiness here. */
38865 /* Recognize interleave style patterns, which means incrementing
38866 every other permutation operand. */
38868 {
38871 }
38876 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38878 {
38880 {
38885 }
38890 }
38891 }
38893 /* Finally, try the fully general two operand permute. */
38898 /* Recognize interleave style patterns with reversed operands. */
38900 {
38902 {
38906 else
38909 }
38914 }
38916 /* Try the SSE4.1 blend variable merge instructions. */
38920 /* Try one of the AVX vpermil variable permutations. */
38924 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
38925 vpshufb, vpermd, vpermps or vpermq variable permutation. */
38930 }
38932 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38933 in terms of a pair of pshuflw + pshufhw instructions. */
38935 static bool
38937 {
38945 /* The two permutations only operate in 64-bit lanes. */
38956 /* Emit the pshuflw. */
38963 /* Emit the pshufhw. */
38971 }
38973 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
38974 the permutation using the SSSE3 palignr instruction. This succeeds
38975 when all of the elements in PERM fit within one vector and we merely
38976 need to shift them down so that a single vector permutation has a
38977 chance to succeed. */
38979 static bool
38981 {
38985 rtx shift;
38987 /* Even with AVX, palignr only operates on 128-bit vectors. */
38993 {
38999 }
39003 /* Given that we have SSSE3, we know we'll be able to implement the
39004 single operand permutation after the palignr with pshufb. */
39018 {
39023 }
39025 /* Test for the degenerate case where the alignment by itself
39026 produces the desired permutation. */
39034 }
39038 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39039 a two vector permutation into a single vector permutation by using
39040 an interleave operation to merge the vectors. */
39042 static bool
39044 {
39049 rtx seq;
39053 {
39056 }
39058 {
39061 /* For 32-byte modes allow even d->one_operand_p.
39062 The lack of cross-lane shuffling in some instructions
39063 might prevent a single insn shuffle. */
39066 /* If expand_vec_perm_interleave3 can expand this into
39067 a 3 insn sequence, give up and let it be expanded as
39068 3 insn sequence. While that is one insn longer,
39069 it doesn't need a memory operand and in the common
39070 case that both interleave low and high permutations
39071 with the same operands are adjacent needs 4 insns
39072 for both after CSE. */
39075 }
39076 else
39079 /* Examine from whence the elements come. */
39088 {
39091 /* Split the two input vectors into 4 halves. */
39097 /* If the elements from the low halves use interleave low, and similarly
39098 for interleave high. If the elements are from mis-matched halves, we
39099 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39101 {
39102 /* punpckl* */
39104 {
39109 }
39112 }
39114 {
39115 /* punpckh* */
39117 {
39122 }
39125 }
39127 {
39128 /* shufps */
39130 {
39135 }
39137 {
39138 /* shufpd */
39143 }
39144 }
39146 {
39147 /* shufps */
39149 {
39154 }
39156 {
39157 /* shufpd */
39162 }
39163 }
39164 else
39166 }
39167 else
39168 {
39173 /* Split the two input vectors into 8 quarters. */
39179 {
39182 }
39185 {
39189 }
39191 {
39194 }
39197 {
39199 {
39200 /* Attempt to increase the likelihood that dfinal
39201 shuffle will be intra-lane. */
39205 }
39207 /* vperm2f128 or vperm2i128. */
39209 {
39214 }
39219 {
39223 {
39226 }
39227 }
39228 }
39233 {
39234 /* vpunpckl* */
39236 {
39245 }
39246 }
39249 {
39250 /* vpunpckh* */
39252 {
39261 }
39262 }
39263 else
39265 }
39267 /* Use the remapping array set up above to move the elements from their
39268 swizzled locations into their final destinations. */
39271 {
39274 /* If same_halves is true, both halves of the remapped vector are the
39275 same. Avoid cross-lane accesses if possible. */
39277 {
39280 }
39281 else
39283 }
39289 /* Test if the final remap can be done with a single insn. For V4SFmode or
39290 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39303 {
39307 }
39314 }
39316 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39317 a single vector cross-lane permutation into vpermq followed
39318 by any of the single insn permutations. */
39320 static bool
39322 {
39336 {
39339 }
39342 {
39347 }
39360 {
39367 }
39374 {
39379 ;
39382 else
39384 }
39393 }
39395 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39396 a vector permutation using two instructions, vperm2f128 resp.
39397 vperm2i128 followed by any single in-lane permutation. */
39399 static bool
39401 {
39415 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39416 immediate. For perm < 16 the second permutation uses
39417 d->op0 as first operand, for perm >= 16 it uses d->op1
39418 as first operand. The second operand is the result of
39419 vperm2[fi]128. */
39421 {
39422 /* Ignore permutations which do not move anything cross-lane. */
39424 {
39425 /* The second shuffle for e.g. V4DFmode has
39426 0123 and ABCD operands.
39427 Ignore AB23, as 23 is already in the second lane
39428 of the first operand. */
39430 /* And 01CD, as 01 is in the first lane of the first
39431 operand. */
39433 /* And 4567, as then the vperm2[fi]128 doesn't change
39434 anything on the original 4567 second operand. */
39436 }
39437 else
39438 {
39439 /* The second shuffle for e.g. V4DFmode has
39440 4567 and ABCD operands.
39441 Ignore AB67, as 67 is already in the second lane
39442 of the first operand. */
39444 /* And 45CD, as 45 is in the first lane of the first
39445 operand. */
39447 /* And 0123, as then the vperm2[fi]128 doesn't change
39448 anything on the original 0123 first operand. */
39450 }
39453 {
39459 else
39461 }
39464 {
39468 }
39469 else
39473 {
39477 /* Found a usable second shuffle. dfirst will be
39478 vperm2f128 on d->op0 and d->op1. */
39489 /* And dsecond is some single insn shuffle, taking
39490 d->op0 and result of vperm2f128 (if perm < 16) or
39491 d->op1 and result of vperm2f128 (otherwise). */
39500 }
39502 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39505 }
39508 }
39510 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39511 a two vector permutation using 2 intra-lane interleave insns
39512 and cross-lane shuffle for 32-byte vectors. */
39514 static bool
39516 {
39523 ;
39525 ;
39526 else
39541 {
39545 else
39551 else
39557 else
39563 else
39569 else
39575 else
39580 }
39584 }
39586 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39587 a single vector permutation using a single intra-lane vector
39588 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39589 the non-swapped and swapped vectors together. */
39591 static bool
39593 {
39596 rtx seq;
39601 || TARGET_AVX2
39610 {
39617 }
39652 }
39654 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39655 permutation using two vperm2f128, followed by a vshufpd insn blending
39656 the two vectors together. */
39658 static bool
39660 {
39703 }
39705 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39706 permutation with two pshufb insns and an ior. We should have already
39707 failed all two instruction sequences. */
39709 static bool
39711 {
39722 /* Generate two permutation masks. If the required element is within
39723 the given vector it is shuffled into the proper lane. If the required
39724 element is in the other vector, force a zero into the lane by setting
39725 bit 7 in the permutation mask. */
39728 {
39735 {
39738 }
39739 }
39759 }
39761 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39762 with two vpshufb insns, vpermq and vpor. We should have already failed
39763 all two or three instruction sequences. */
39765 static bool
39767 {
39782 /* Generate two permutation masks. If the required element is within
39783 the same lane, it is shuffled in. If the required element from the
39784 other lane, force a zero by setting bit 7 in the permutation mask.
39785 In the other mask the mask has non-negative elements if element
39786 is requested from the other lane, but also moved to the other lane,
39787 so that the result of vpshufb can have the two V2TImode halves
39788 swapped. */
39791 {
39796 {
39799 }
39800 }
39809 /* Swap the 128-byte lanes of h into hp. */
39813 const1_rtx));
39826 }
39828 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39829 and extract-odd permutations of two V32QImode and V16QImode operand
39830 with two vpshufb insns, vpor and vpermq. We should have already
39831 failed all two or three instruction sequences. */
39833 static bool
39835 {
39854 /* Generate two permutation masks. In the first permutation mask
39855 the first quarter will contain indexes for the first half
39856 of the op0, the second quarter will contain bit 7 set, third quarter
39857 will contain indexes for the second half of the op0 and the
39858 last quarter bit 7 set. In the second permutation mask
39859 the first quarter will contain bit 7 set, the second quarter
39860 indexes for the first half of the op1, the third quarter bit 7 set
39861 and last quarter indexes for the second half of the op1.
39862 I.e. the first mask e.g. for V32QImode extract even will be:
39863 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39864 (all values masked with 0xf except for -128) and second mask
39865 for extract even will be
39866 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39869 {
39875 {
39878 }
39879 }
39898 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
39905 }
39907 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
39908 and extract-odd permutations. */
39910 static bool
39912 {
39916 {
39921 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
39925 /* Now an unpck[lh]pd will produce the result required. */
39928 else
39934 {
39941 /* Shuffle within the 128-bit lanes to produce:
39942 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
39946 /* Shuffle the lanes around to produce:
39947 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
39951 /* Shuffle within the 128-bit lanes to produce:
39952 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
39955 /* Shuffle within the 128-bit lanes to produce:
39956 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
39959 /* Shuffle the lanes around to produce:
39960 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
39963 }
39970 /* These are always directly implementable by expand_vec_perm_1. */
39976 else
39977 {
39978 /* We need 2*log2(N)-1 operations to achieve odd/even
39979 with interleave. */
39988 else
39991 }
39997 else
39998 {
40010 else
40013 }
40022 {
40029 }
40034 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40038 /* Now an vpunpck[lh]qdq will produce the result required. */
40041 else
40048 {
40055 }
40060 /* Shuffle the lanes around into
40061 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40071 /* Swap the 2nd and 3rd position in each lane into
40072 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40078 /* Now an vpunpck[lh]qdq will produce
40079 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40084 else
40093 }
40096 }
40098 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40099 extract-even and extract-odd permutations. */
40101 static bool
40103 {
40115 }
40117 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40118 permutations. We assume that expand_vec_perm_1 has already failed. */
40120 static bool
40122 {
40130 {
40133 /* These are special-cased in sse.md so that we can optionally
40134 use the vbroadcast instruction. They expand to two insns
40135 if the input happens to be in a register. */
40142 /* These are always implementable using standard shuffle patterns. */
40147 /* These can be implemented via interleave. We save one insn by
40148 stopping once we have promoted to V4SImode and then use pshufd. */
40149 do
40150 {
40151 rtx dest;
40157 {
40161 }
40168 }
40181 /* For AVX2 broadcasts of the first element vpbroadcast* or
40182 vpermq should be used by expand_vec_perm_1. */
40188 }
40189 }
40191 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40192 broadcast permutations. */
40194 static bool
40196 {
40208 }
40210 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40211 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40212 all the shorter instruction sequences. */
40214 static bool
40216 {
40232 /* Generate 4 permutation masks. If the required element is within
40233 the same lane, it is shuffled in. If the required element from the
40234 other lane, force a zero by setting bit 7 in the permutation mask.
40235 In the other mask the mask has non-negative elements if element
40236 is requested from the other lane, but also moved to the other lane,
40237 so that the result of vpshufb can have the two V2TImode halves
40238 swapped. */
40241 {
40246 }
40252 {
40260 }
40263 {
40265 {
40268 }
40275 }
40277 /* Swap the 128-byte lanes of h[X]. */
40279 {
40285 const1_rtx));
40287 }
40290 {
40292 {
40295 }
40301 }
40304 {
40306 {
40310 }
40313 }
40319 }
40321 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40322 With all of the interface bits taken care of, perform the expansion
40323 in D and return true on success. */
40325 static bool
40327 {
40328 /* Try a single instruction expansion. */
40332 /* Try sequences of two instructions. */
40352 /* Try sequences of three instructions. */
40366 /* Try sequences of four instructions. */
40374 /* ??? Look for narrow permutations whose element orderings would
40375 allow the promotion to a wider mode. */
40377 /* ??? Look for sequences of interleave or a wider permute that place
40378 the data into the correct lanes for a half-vector shuffle like
40379 pshuf[lh]w or vpermilps. */
40381 /* ??? Look for sequences of interleave that produce the desired results.
40382 The combinatorics of punpck[lh] get pretty ugly... */
40387 /* Even longer sequences. */
40392 }
40394 /* If a permutation only uses one operand, make it clear. Returns true
40395 if the permutation references both operands. */
40397 static bool
40399 {
40407 {
40413 {
40416 }
40417 /* The elements of PERM do not suggest that only the first operand
40418 is used, but both operands are identical. Allow easier matching
40419 of the permutation by folding the permutation into the single
40420 input vector. */
40421 /* FALLTHRU */
40432 }
40435 }
40437 bool
40439 {
40444 rtx sel;
40461 {
40466 }
40473 /* If the selector says both arguments are needed, but the operands are the
40474 same, the above tried to expand with one_operand_p and flattened selector.
40475 If that didn't work, retry without one_operand_p; we succeeded with that
40476 during testing. */
40478 {
40482 }
40485 }
40487 /* Implement targetm.vectorize.vec_perm_const_ok. */
40489 static bool
40492 {
40501 /* Given sufficient ISA support we can just return true here
40502 for selected vector modes. */
40504 {
40505 /* All implementable with a single vpperm insn. */
40508 /* All implementable with 2 pshufb + 1 ior. */
40511 /* All implementable with shufpd or unpck[lh]pd. */
40514 }
40516 /* Extract the values from the vector CST into the permutation
40517 array in D. */
40520 {
40524 }
40526 /* For all elements from second vector, fold the elements to first. */
40531 /* Check whether the mask can be applied to the vector type. */
40534 /* Implementable with shufps or pshufd. */
40538 /* Otherwise we have to go through the motions and see if we can
40539 figure out how to generate the requested permutation. */
40550 }
40552 void
40554 {
40569 /* We'll either be able to implement the permutation directly... */
40573 /* ... or we use the special-case patterns. */
40575 }
40577 static void
40579 {
40594 {
40597 }
40599 /* Note that for AVX this isn't one instruction. */
40602 }
40605 /* Expand a vector operation CODE for a V*QImode in terms of the
40606 same operation on V*HImode. */
40608 void
40610 {
40622 {
40635 }
40639 {
40641 /* Unpack data such that we've got a source byte in each low byte of
40642 each word. We don't care what goes into the high byte of each word.
40643 Rather than trying to get zero in there, most convenient is to let
40644 it be a copy of the low byte. */
40649 /* FALLTHRU */
40661 /* FALLTHRU */
40671 }
40673 /* Perform the operation. */
40680 /* Merge the data back into the right place. */
40690 {
40691 /* For SSE2, we used an full interleave, so the desired
40692 results are in the even elements. */
40695 }
40696 else
40697 {
40698 /* For AVX, the interleave used above was not cross-lane. So the
40699 extraction is evens but with the second and third quarter swapped.
40700 Happily, that is even one insn shorter than even extraction. */
40703 }
40710 }
40712 void
40715 {
40718 rtx x;
40720 /* We only play even/odd games with vectors of SImode. */
40723 /* If we're looking for the odd results, shift those members down to
40724 the even slots. For some cpus this is faster than a PSHUFD. */
40726 {
40728 {
40732 }
40741 }
40744 {
40747 else
40749 }
40754 else
40755 {
40758 /* The easiest way to implement this without PMULDQ is to go through
40759 the motions as if we are performing a full 64-bit multiply. With
40760 the exception that we need to do less shuffling of the elements. */
40762 /* Compute the sign-extension, aka highparts, of the two operands. */
40768 /* Multiply LO(A) * HI(B), and vice-versa. */
40774 /* Multiply LO(A) * LO(B). */
40778 /* Combine and shift the highparts into place. */
40783 /* Combine high and low parts. */
40786 }
40788 }
40790 void
40793 {
40799 {
40804 {
40805 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40806 shuffle the elements once so that all elements are in the right
40807 place for immediate use: { A C B D }. */
40812 }
40813 else
40814 {
40815 /* Put the elements into place for the multiply. */
40819 }
40824 /* Shuffle the elements between the lanes. After this we
40825 have { A B E F | C D G H } for each operand. */
40835 /* Shuffle the elements within the lanes. After this we
40836 have { A A B B | C C D D } or { E E F F | G G H H }. */
40872 }
40873 }
40875 void
40877 {
40887 /* Move the results in element 2 down to element 1; we don't care
40888 what goes in elements 2 and 3. Then we can merge the parts
40889 back together with an interleave.
40891 Note that two other sequences were tried:
40892 (1) Use interleaves at the start instead of psrldq, which allows
40893 us to use a single shufps to merge things back at the end.
40894 (2) Use shufps here to combine the two vectors, then pshufd to
40895 put the elements in the correct order.
40896 In both cases the cost of the reformatting stall was too high
40897 and the overall sequence slower. */
40906 }
40908 void
40910 {
40915 {
40916 /* op1: A,B,C,D, op2: E,F,G,H */
40925 /* t1: B,A,D,C */
40932 /* t2: (B*E),(A*F),(D*G),(C*H) */
40935 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
40938 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
40941 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
40943 }
40944 else
40945 {
40950 {
40953 }
40955 {
40958 }
40959 else
40963 /* Multiply low parts. */
40967 /* Shift input vectors right 32 bits so we can multiply high parts. */
40972 /* Multiply high parts by low parts. */
40978 /* Combine and shift the highparts back. */
40982 /* Combine high and low parts. */
40984 }
40988 }
40990 /* Expand an insert into a vector register through pinsr insn.
40991 Return true if successful. */
40993 bool
40995 {
41003 {
41006 }
41012 {
41017 {
41024 {
41056 }
41065 }
41069 }
41070 }
41071 \f
41072 /* This function returns the calling abi specific va_list type node.
41073 It returns the FNDECL specific va_list type. */
41075 static tree
41077 {
41084 else
41086 }
41088 /* Returns the canonical va_list type specified by TYPE. If there
41089 is no valid TYPE provided, it return NULL_TREE. */
41091 static tree
41093 {
41096 /* Resolve references and pointers to va_list type. */
41105 {
41110 {
41111 /* If va_list is an array type, the argument may have decayed
41112 to a pointer type, e.g. by being passed to another function.
41113 In that case, unwrap both types so that we can compare the
41114 underlying records. */
41117 {
41120 }
41121 }
41128 {
41129 /* If va_list is an array type, the argument may have decayed
41130 to a pointer type, e.g. by being passed to another function.
41131 In that case, unwrap both types so that we can compare the
41132 underlying records. */
41135 {
41138 }
41139 }
41146 {
41147 /* If va_list is an array type, the argument may have decayed
41148 to a pointer type, e.g. by being passed to another function.
41149 In that case, unwrap both types so that we can compare the
41150 underlying records. */
41153 {
41156 }
41157 }
41161 }
41163 }
41165 /* Iterate through the target-specific builtin types for va_list.
41166 IDX denotes the iterator, *PTREE is set to the result type of
41167 the va_list builtin, and *PNAME to its internal type.
41168 Returns zero if there is no element for this index, otherwise
41169 IDX should be increased upon the next call.
41170 Note, do not iterate a base builtin's name like __builtin_va_list.
41171 Used from c_common_nodes_and_builtins. */
41173 static int
41175 {
41177 {
41179 {
41192 }
41193 }
41196 }
41198 #undef TARGET_SCHED_DISPATCH
41199 #define TARGET_SCHED_DISPATCH has_dispatch
41200 #undef TARGET_SCHED_DISPATCH_DO
41201 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41202 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41203 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41204 #undef TARGET_SCHED_REORDER
41205 #define TARGET_SCHED_REORDER ix86_sched_reorder
41206 #undef TARGET_SCHED_ADJUST_PRIORITY
41207 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41208 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41209 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41211 /* The size of the dispatch window is the total number of bytes of
41212 object code allowed in a window. */
41213 #define DISPATCH_WINDOW_SIZE 16
41215 /* Number of dispatch windows considered for scheduling. */
41216 #define MAX_DISPATCH_WINDOWS 3
41218 /* Maximum number of instructions in a window. */
41219 #define MAX_INSN 4
41221 /* Maximum number of immediate operands in a window. */
41222 #define MAX_IMM 4
41224 /* Maximum number of immediate bits allowed in a window. */
41225 #define MAX_IMM_SIZE 128
41227 /* Maximum number of 32 bit immediates allowed in a window. */
41228 #define MAX_IMM_32 4
41230 /* Maximum number of 64 bit immediates allowed in a window. */
41231 #define MAX_IMM_64 2
41233 /* Maximum total of loads or prefetches allowed in a window. */
41234 #define MAX_LOAD 2
41236 /* Maximum total of stores allowed in a window. */
41237 #define MAX_STORE 1
41239 #undef BIG
41240 #define BIG 100
41243 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41246 disp_load,
41247 disp_store,
41248 disp_load_store,
41249 disp_prefetch,
41250 disp_imm,
41251 disp_imm_32,
41252 disp_imm_64,
41253 disp_branch,
41254 disp_cmp,
41255 disp_jcc,
41256 disp_last
41257 };
41259 /* Number of allowable groups in a dispatch window. It is an array
41260 indexed by dispatch_group enum. 100 is used as a big number,
41261 because the number of these kind of operations does not have any
41262 effect in dispatch window, but we need them for other reasons in
41263 the table. */
41266 };
41272 };
41274 /* Instruction path. */
41280 last_path
41281 };
41283 /* sched_insn_info defines a window to the instructions scheduled in
41284 the basic block. It contains a pointer to the insn_info table and
41285 the instruction scheduled.
41287 Windows are allocated for each basic block and are linked
41288 together. */
41290 rtx insn;
41297 /* Linked list of dispatch windows. This is a two way list of
41298 dispatch windows of a basic block. It contains information about
41299 the number of uops in the window and the total number of
41300 instructions and of bytes in the object code for this dispatch
41301 window. */
41319 /* Immediate valuse used in an insn. */
41321 {
41330 /* Get dispatch group of insn. */
41332 static enum dispatch_group
41334 {
41350 }
41352 /* Return true if insn is a compare instruction. */
41354 static bool
41356 {
41364 }
41366 /* Return true if a dispatch violation encountered. */
41368 static bool
41370 {
41374 }
41376 /* Return true if insn is a branch instruction. */
41378 static bool
41380 {
41382 }
41384 /* Return true if insn is a prefetch instruction. */
41386 static bool
41388 {
41390 }
41392 /* This function initializes a dispatch window and the list container holding a
41393 pointer to the window. */
41395 static void
41397 {
41403 else
41421 {
41427 }
41429 }
41431 /* This function allocates and initializes a dispatch window and the
41432 list container holding a pointer to the window. */
41436 {
41441 }
41443 /* This routine initializes the dispatch scheduling information. It
41444 initiates building dispatch scheduler tables and constructs the
41445 first dispatch window. */
41447 static void
41449 {
41450 /* Allocate a dispatch list and a window. */
41455 }
41457 /* This function returns true if a branch is detected. End of a basic block
41458 does not have to be a branch, but here we assume only branches end a
41459 window. */
41461 static bool
41463 {
41465 }
41467 /* This function is called when the end of a window processing is reached. */
41469 static void
41471 {
41474 {
41479 }
41481 }
41483 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41484 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41485 for 48 bytes of instructions. Note that these windows are not dispatch
41486 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41490 {
41492 {
41497 }
41503 }
41505 /* Increment the number of immediate operands of an instruction. */
41507 static int
41509 {
41514 {
41521 else
41532 {
41535 }
41540 }
41543 }
41545 /* Compute number of immediate operands of an instruction. */
41547 static void
41549 {
41552 }
41554 /* Return total size of immediate operands of an instruction along with number
41555 of corresponding immediate-operands. It initializes its parameters to zero
41556 befor calling FIND_CONSTANT.
41557 INSN is the input instruction. IMM is the total of immediates.
41558 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41559 bit immediates. */
41561 static int
41563 {
41571 }
41573 /* This function indicates if an operand of an instruction is an
41574 immediate. */
41576 static bool
41578 {
41587 }
41589 /* Return single or double path for instructions. */
41591 static enum insn_path
41593 {
41603 }
41605 /* Return insn dispatch group. */
41607 static enum dispatch_group
41609 {
41627 }
41629 /* Count number of GROUP restricted instructions in a dispatch
41630 window WINDOW_LIST. */
41632 static int
41634 {
41645 {
41664 }
41677 }
41679 /* This function returns true if insn satisfies dispatch rules on the
41680 last window scheduled. */
41682 static bool
41684 {
41692 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41693 instructions should be given the lowest priority in the
41694 scheduling process in Haifa scheduler to make sure they will be
41695 scheduled in the same dispatch window as the reference to them. */
41699 /* Check nonrestricted. */
41703 /* Get last dispatch window. */
41708 {
41713 /* Window 1 is full. Go for next window. */
41715 }
41722 /* See if it fits in the first window. */
41724 {
41725 /* The first widow should have only single and double path
41726 uops. */
41732 }
41734 }
41736 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41737 dispatch window WINDOW_LIST. */
41739 static void
41741 {
41759 /* Initialize window with new instruction. */
41780 {
41783 }
41784 }
41786 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41787 If the total bytes of instructions or the number of instructions in
41788 the window exceed allowable, it allocates a new window. */
41790 static void
41792 {
41815 /* Get the last dispatch window. */
41823 else
41826 /* If current window is full, get a new window.
41827 Window number zero is full, if MAX_INSN uops are scheduled in it.
41828 Window number one is full, if window zero's bytes plus window
41829 one's bytes is 32, or if the bytes of the new instruction added
41830 to the total makes it greater than 48, or it has already MAX_INSN
41831 instructions in it. */
41840 {
41843 }
41846 {
41850 {
41853 }
41854 }
41856 {
41861 {
41864 }
41867 }
41868 else
41872 {
41873 /* End of basic block is reached do end-basic-block process. */
41876 }
41877 }
41879 /* Print the dispatch window, WINDOW_NUM, to FILE. */
41881 DEBUG_FUNCTION static void
41883 {
41889 else
41903 {
41906 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
41912 }
41913 }
41915 /* Print to stdout a dispatch window. */
41917 DEBUG_FUNCTION void
41919 {
41921 }
41923 /* Print INSN dispatch information to FILE. */
41925 DEBUG_FUNCTION static void
41927 {
41950 }
41952 /* Print to STDERR the status of the ready list with respect to
41953 dispatch windows. */
41955 DEBUG_FUNCTION void
41957 {
41965 }
41967 /* This routine is the driver of the dispatch scheduler. */
41969 static void
41971 {
41976 }
41978 /* Return TRUE if Dispatch Scheduling is supported. */
41980 static bool
41982 {
41986 {
42002 }
42005 }
42007 /* Implementation of reassociation_width target hook used by
42008 reassoc phase to identify parallelism level in reassociated
42009 tree. Statements tree_code is passed in OPC. Arguments type
42010 is passed in MODE.
42012 Currently parallel reassociation is enabled for Atom
42013 processors only and we set reassociation width to be 2
42014 because Atom may issue up to 2 instructions per cycle.
42016 Return value should be fixed if parallel reassociation is
42017 enabled for other processors. */
42019 static int
42022 {
42031 }
42033 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42034 place emms and femms instructions. */
42036 static enum machine_mode
42038 {
42043 {
42056 else
42066 /* FALLTHRU */
42070 }
42071 }
42073 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42074 vectors. */
42076 static unsigned int
42078 {
42080 }
42082 \f
42084 /* Return class of registers which could be used for pseudo of MODE
42085 and of class RCLASS for spilling instead of memory. Return NO_REGS
42086 if it is not possible or non-profitable. */
42087 static reg_class_t
42089 {
42096 }
42098 /* Implement targetm.vectorize.init_cost. */
42102 {
42106 }
42108 /* Implement targetm.vectorize.add_stmt_cost. */
42110 static unsigned
42114 {
42119 {
42123 /* Statements in an inner loop relative to the loop being
42124 vectorized are weighted more heavily. The value here is
42125 arbitrary and could potentially be improved with analysis. */
42131 }
42134 }
42136 /* Implement targetm.vectorize.finish_cost. */
42138 static void
42141 {
42146 }
42148 /* Implement targetm.vectorize.destroy_cost_data. */
42150 static void
42152 {
42154 }
42156 /* Validate target specific memory model bits in VAL. */
42158 static unsigned HOST_WIDE_INT
42160 {
42167 {
42171 }
42174 {
42178 }
42180 {
42184 }
42186 }
42188 /* Initialize the GCC target structure. */
42189 #undef TARGET_RETURN_IN_MEMORY
42190 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42192 #undef TARGET_LEGITIMIZE_ADDRESS
42193 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42195 #undef TARGET_ATTRIBUTE_TABLE
42196 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42197 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42198 # undef TARGET_MERGE_DECL_ATTRIBUTES
42199 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42200 #endif
42202 #undef TARGET_COMP_TYPE_ATTRIBUTES
42203 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42205 #undef TARGET_INIT_BUILTINS
42206 #define TARGET_INIT_BUILTINS ix86_init_builtins
42207 #undef TARGET_BUILTIN_DECL
42208 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42209 #undef TARGET_EXPAND_BUILTIN
42210 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42212 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42213 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42214 ix86_builtin_vectorized_function
42216 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42217 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42219 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42220 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42222 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42223 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42225 #undef TARGET_BUILTIN_RECIPROCAL
42226 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42228 #undef TARGET_ASM_FUNCTION_EPILOGUE
42229 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42231 #undef TARGET_ENCODE_SECTION_INFO
42232 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42233 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42234 #else
42235 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42236 #endif
42238 #undef TARGET_ASM_OPEN_PAREN
42240 #undef TARGET_ASM_CLOSE_PAREN
42243 #undef TARGET_ASM_BYTE_OP
42244 #define TARGET_ASM_BYTE_OP ASM_BYTE
42246 #undef TARGET_ASM_ALIGNED_HI_OP
42247 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42248 #undef TARGET_ASM_ALIGNED_SI_OP
42249 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42250 #ifdef ASM_QUAD
42251 #undef TARGET_ASM_ALIGNED_DI_OP
42252 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42253 #endif
42255 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42256 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42258 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42259 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42261 #undef TARGET_ASM_UNALIGNED_HI_OP
42262 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42263 #undef TARGET_ASM_UNALIGNED_SI_OP
42264 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42265 #undef TARGET_ASM_UNALIGNED_DI_OP
42266 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42268 #undef TARGET_PRINT_OPERAND
42269 #define TARGET_PRINT_OPERAND ix86_print_operand
42270 #undef TARGET_PRINT_OPERAND_ADDRESS
42271 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42272 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42273 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42274 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42275 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42277 #undef TARGET_SCHED_INIT_GLOBAL
42278 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42279 #undef TARGET_SCHED_ADJUST_COST
42280 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42281 #undef TARGET_SCHED_ISSUE_RATE
42282 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42283 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42284 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42285 ia32_multipass_dfa_lookahead
42287 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42288 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42290 #undef TARGET_MEMMODEL_CHECK
42291 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42293 #ifdef HAVE_AS_TLS
42294 #undef TARGET_HAVE_TLS
42295 #define TARGET_HAVE_TLS true
42296 #endif
42297 #undef TARGET_CANNOT_FORCE_CONST_MEM
42298 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42299 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42300 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42302 #undef TARGET_DELEGITIMIZE_ADDRESS
42303 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42305 #undef TARGET_MS_BITFIELD_LAYOUT_P
42306 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42308 #if TARGET_MACHO
42309 #undef TARGET_BINDS_LOCAL_P
42310 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42311 #endif
42312 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42313 #undef TARGET_BINDS_LOCAL_P
42314 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42315 #endif
42317 #undef TARGET_ASM_OUTPUT_MI_THUNK
42318 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42319 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42320 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42322 #undef TARGET_ASM_FILE_START
42323 #define TARGET_ASM_FILE_START x86_file_start
42325 #undef TARGET_OPTION_OVERRIDE
42326 #define TARGET_OPTION_OVERRIDE ix86_option_override
42328 #undef TARGET_REGISTER_MOVE_COST
42329 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42330 #undef TARGET_MEMORY_MOVE_COST
42331 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42332 #undef TARGET_RTX_COSTS
42333 #define TARGET_RTX_COSTS ix86_rtx_costs
42334 #undef TARGET_ADDRESS_COST
42335 #define TARGET_ADDRESS_COST ix86_address_cost
42337 #undef TARGET_FIXED_CONDITION_CODE_REGS
42338 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42339 #undef TARGET_CC_MODES_COMPATIBLE
42340 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42342 #undef TARGET_MACHINE_DEPENDENT_REORG
42343 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42345 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42346 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42348 #undef TARGET_BUILD_BUILTIN_VA_LIST
42349 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42351 #undef TARGET_FOLD_BUILTIN
42352 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42354 #undef TARGET_COMPARE_VERSION_PRIORITY
42355 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42357 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42358 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42359 ix86_generate_version_dispatcher_body
42361 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42362 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42363 ix86_get_function_versions_dispatcher
42365 #undef TARGET_ENUM_VA_LIST_P
42366 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42368 #undef TARGET_FN_ABI_VA_LIST
42369 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42371 #undef TARGET_CANONICAL_VA_LIST_TYPE
42372 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42374 #undef TARGET_EXPAND_BUILTIN_VA_START
42375 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42377 #undef TARGET_MD_ASM_CLOBBERS
42378 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42380 #undef TARGET_PROMOTE_PROTOTYPES
42381 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42382 #undef TARGET_STRUCT_VALUE_RTX
42383 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42384 #undef TARGET_SETUP_INCOMING_VARARGS
42385 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42386 #undef TARGET_MUST_PASS_IN_STACK
42387 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42388 #undef TARGET_FUNCTION_ARG_ADVANCE
42389 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42390 #undef TARGET_FUNCTION_ARG
42391 #define TARGET_FUNCTION_ARG ix86_function_arg
42392 #undef TARGET_FUNCTION_ARG_BOUNDARY
42393 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42394 #undef TARGET_PASS_BY_REFERENCE
42395 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42396 #undef TARGET_INTERNAL_ARG_POINTER
42397 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42398 #undef TARGET_UPDATE_STACK_BOUNDARY
42399 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42400 #undef TARGET_GET_DRAP_RTX
42401 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42402 #undef TARGET_STRICT_ARGUMENT_NAMING
42403 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42404 #undef TARGET_STATIC_CHAIN
42405 #define TARGET_STATIC_CHAIN ix86_static_chain
42406 #undef TARGET_TRAMPOLINE_INIT
42407 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42408 #undef TARGET_RETURN_POPS_ARGS
42409 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42411 #undef TARGET_LEGITIMATE_COMBINED_INSN
42412 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42414 #undef TARGET_ASAN_SHADOW_OFFSET
42415 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42417 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42418 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42420 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42421 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42423 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42424 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42426 #undef TARGET_C_MODE_FOR_SUFFIX
42427 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42429 #ifdef HAVE_AS_TLS
42430 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42431 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42432 #endif
42434 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42435 #undef TARGET_INSERT_ATTRIBUTES
42436 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42437 #endif
42439 #undef TARGET_MANGLE_TYPE
42440 #define TARGET_MANGLE_TYPE ix86_mangle_type
42442 #if !TARGET_MACHO
42443 #undef TARGET_STACK_PROTECT_FAIL
42444 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42445 #endif
42447 #undef TARGET_FUNCTION_VALUE
42448 #define TARGET_FUNCTION_VALUE ix86_function_value
42450 #undef TARGET_FUNCTION_VALUE_REGNO_P
42451 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42453 #undef TARGET_PROMOTE_FUNCTION_MODE
42454 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42456 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42457 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42459 #undef TARGET_INSTANTIATE_DECLS
42460 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42462 #undef TARGET_SECONDARY_RELOAD
42463 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42465 #undef TARGET_CLASS_MAX_NREGS
42466 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42468 #undef TARGET_PREFERRED_RELOAD_CLASS
42469 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42470 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42471 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42472 #undef TARGET_CLASS_LIKELY_SPILLED_P
42473 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42475 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42476 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42477 ix86_builtin_vectorization_cost
42478 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42479 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42480 ix86_vectorize_vec_perm_const_ok
42481 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42482 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42483 ix86_preferred_simd_mode
42484 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42485 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42486 ix86_autovectorize_vector_sizes
42487 #undef TARGET_VECTORIZE_INIT_COST
42488 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42489 #undef TARGET_VECTORIZE_ADD_STMT_COST
42490 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42491 #undef TARGET_VECTORIZE_FINISH_COST
42492 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42493 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42494 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42496 #undef TARGET_SET_CURRENT_FUNCTION
42497 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42499 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42500 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42502 #undef TARGET_OPTION_SAVE
42503 #define TARGET_OPTION_SAVE ix86_function_specific_save
42505 #undef TARGET_OPTION_RESTORE
42506 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42508 #undef TARGET_OPTION_PRINT
42509 #define TARGET_OPTION_PRINT ix86_function_specific_print
42511 #undef TARGET_OPTION_FUNCTION_VERSIONS
42512 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42514 #undef TARGET_CAN_INLINE_P
42515 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42517 #undef TARGET_EXPAND_TO_RTL_HOOK
42518 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42520 #undef TARGET_LEGITIMATE_ADDRESS_P
42521 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42523 #undef TARGET_LRA_P
42524 #define TARGET_LRA_P hook_bool_void_true
42526 #undef TARGET_REGISTER_PRIORITY
42527 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42529 #undef TARGET_LEGITIMATE_CONSTANT_P
42530 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42532 #undef TARGET_FRAME_POINTER_REQUIRED
42533 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42535 #undef TARGET_CAN_ELIMINATE
42536 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42538 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42539 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42541 #undef TARGET_ASM_CODE_END
42542 #define TARGET_ASM_CODE_END ix86_code_end
42544 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42545 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42547 #if TARGET_MACHO
42548 #undef TARGET_INIT_LIBFUNCS
42549 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42550 #endif
42552 #undef TARGET_SPILL_CLASS
42553 #define TARGET_SPILL_CLASS ix86_spill_class
42556 \f