| blob | 71b1656ba33c52fafc7c5f302d94a7683425bea6 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
96 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
106 #ifndef LOAD_EXTEND_OP
107 #define LOAD_EXTEND_OP(M) UNKNOWN
108 #endif
110 /* Number of attempts to combine instructions in this function. */
114 /* Number of attempts that got as far as substitution in this function. */
118 /* Number of instructions combined with added SETs in this function. */
122 /* Number of instructions combined in this function. */
126 /* Totals over entire compilation. */
130 /* combine_instructions may try to replace the right hand side of the
131 second instruction with the value of an associated REG_EQUAL note
132 before throwing it at try_combine. That is problematic when there
133 is a REG_DEAD note for a register used in the old right hand side
134 and can cause distribute_notes to do wrong things. This is the
135 second instruction if it has been so modified, null otherwise. */
139 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
143 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 \f
148 /* Record last point of death of (hard or pseudo) register n. */
151 /* Record last point of modification of (hard or pseudo) register n. */
154 /* The next group of fields allows the recording of the last value assigned
155 to (hard or pseudo) register n. We use this information to see if an
156 operation being processed is redundant given a prior operation performed
157 on the register. For example, an `and' with a constant is redundant if
158 all the zero bits are already known to be turned off.
160 We use an approach similar to that used by cse, but change it in the
161 following ways:
163 (1) We do not want to reinitialize at each label.
164 (2) It is useful, but not critical, to know the actual value assigned
165 to a register. Often just its form is helpful.
167 Therefore, we maintain the following fields:
169 last_set_value the last value assigned
170 last_set_label records the value of label_tick when the
171 register was assigned
172 last_set_table_tick records the value of label_tick when a
173 value using the register is assigned
174 last_set_invalid set to nonzero when it is not valid
175 to use the value of this register in some
176 register's value
178 To understand the usage of these tables, it is important to understand
179 the distinction between the value in last_set_value being valid and
180 the register being validly contained in some other expression in the
181 table.
183 (The next two parameters are out of date).
185 reg_stat[i].last_set_value is valid if it is nonzero, and either
186 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
188 Register I may validly appear in any expression returned for the value
189 of another register if reg_n_sets[i] is 1. It may also appear in the
190 value for register J if reg_stat[j].last_set_invalid is zero, or
191 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
193 If an expression is found in the table containing a register which may
194 not validly appear in an expression, the register is replaced by
195 something that won't match, (clobber (const_int 0)). */
197 /* Record last value assigned to (hard or pseudo) register n. */
199 rtx last_set_value;
201 /* Record the value of label_tick when an expression involving register n
202 is placed in last_set_value. */
206 /* Record the value of label_tick when the value for register n is placed in
207 last_set_value. */
211 /* These fields are maintained in parallel with last_set_value and are
212 used to store the mode in which the register was last set, the bits
213 that were known to be zero when it was last set, and the number of
214 sign bits copies it was known to have when it was last set. */
220 /* Set nonzero if references to register n in expressions should not be
221 used. last_set_invalid is set nonzero when this register is being
222 assigned to and last_set_table_tick == label_tick. */
226 /* Some registers that are set more than once and used in more than one
227 basic block are nevertheless always set in similar ways. For example,
228 a QImode register may be loaded from memory in two places on a machine
229 where byte loads zero extend.
231 We record in the following fields if a register has some leading bits
232 that are always equal to the sign bit, and what we know about the
233 nonzero bits of a register, specifically which bits are known to be
234 zero.
236 If an entry is zero, it means that we don't know anything special. */
242 /* Record the value of the label_tick when the last truncation
243 happened. The field truncated_to_mode is only valid if
244 truncation_label == label_tick. */
248 /* Record the last truncation seen for this register. If truncation
249 is not a nop to this mode we might be able to save an explicit
250 truncation if we know that value already contains a truncated
251 value. */
254 };
259 /* One plus the highest pseudo for which we track REG_N_SETS.
260 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
261 but during combine_split_insns new pseudos can be created. As we don't have
262 updated DF information in that case, it is hard to initialize the array
263 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
264 so instead of growing the arrays, just assume all newly created pseudos
265 during combine might be set multiple times. */
269 /* Record the luid of the last insn that invalidated memory
270 (anything that writes memory, and subroutine calls, but not pushes). */
274 /* Record the luid of the last CALL_INSN
275 so we can tell whether a potential combination crosses any calls. */
279 /* When `subst' is called, this is the insn that is being modified
280 (by combining in a previous insn). The PATTERN of this insn
281 is still the old pattern partially modified and it should not be
282 looked at, but this may be used to examine the successors of the insn
283 to judge whether a simplification is valid. */
287 /* This is the lowest LUID that `subst' is currently dealing with.
288 get_last_value will not return a value if the register was set at or
289 after this LUID. If not for this mechanism, we could get confused if
290 I2 or I1 in try_combine were an insn that used the old value of a register
291 to obtain a new value. In that case, we might erroneously get the
292 new value of the register when we wanted the old one. */
296 /* This contains any hard registers that are used in newpat; reg_dead_at_p
297 must consider all these registers to be always live. */
301 /* This is an insn to which a LOG_LINKS entry has been added. If this
302 insn is the earlier than I2 or I3, combine should rescan starting at
303 that location. */
307 /* Basic block in which we are performing combines. */
311 \f
312 /* Length of the currently allocated uid_insn_cost array. */
316 /* The following array records the insn_rtx_cost for every insn
317 in the instruction stream. */
321 /* The following array records the LOG_LINKS for every insn in the
322 instruction stream as struct insn_link pointers. */
328 };
332 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
333 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
335 #define FOR_EACH_LOG_LINK(L, INSN) \
336 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
338 /* Links for LOG_LINKS are allocated from this obstack. */
342 /* Allocate a link. */
346 {
354 }
356 /* Incremented for each basic block. */
360 /* Reset to label_tick for each extended basic block in scanning order. */
364 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
365 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
369 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
370 be safely used. It is zero while computing them and after combine has
371 completed. This former test prevents propagating values based on
372 previously set values, which can be incorrect if a variable is modified
373 in a loop. */
377 \f
378 /* Record one modification to rtl structure
379 to be undone by storing old_contents into *where. */
383 struct undo
384 {
389 };
391 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
392 num_undo says how many are currently recorded.
394 other_insn is nonzero if we have modified some other insn in the process
395 of working on subst_insn. It must be verified too. */
397 struct undobuf
398 {
402 };
406 /* Number of times the pseudo being substituted for
407 was found and replaced. */
412 machine_mode,
416 machine_mode,
488 \f
490 /* It is not safe to use ordinary gen_lowpart in combine.
491 See comments in gen_lowpart_for_combine. */
492 #undef RTL_HOOKS_GEN_LOWPART
493 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
495 /* Our implementation of gen_lowpart never emits a new pseudo. */
496 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
497 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
499 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
500 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
502 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
503 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
505 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
506 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
510 \f
511 /* Convenience wrapper for the canonicalize_comparison target hook.
512 Target hooks cannot use enum rtx_code. */
516 {
520 }
522 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
523 PATTERN can not be split. Otherwise, it returns an insn sequence.
524 This is a wrapper around split_insns which ensures that the
525 reg_stat vector is made larger if the splitter creates a new
526 register. */
530 {
539 }
541 /* This is used by find_single_use to locate an rtx in LOC that
542 contains exactly one use of DEST, which is typically either a REG
543 or CC0. It returns a pointer to the innermost rtx expression
544 containing DEST. Appearances of DEST that are being used to
545 totally replace it are not counted. */
549 {
558 {
562 CASE_CONST_ANY:
567 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
568 of a REG that occupies all of the REG, the insn uses DEST if
569 it is mentioned in the destination or the source. Otherwise, we
570 need just check the source. */
590 }
592 /* If it wasn't one of the common cases above, check each expression and
593 vector of this code. Look for a unique usage of DEST. */
597 {
599 {
604 else
610 /* Duplicate usage. */
612 }
614 {
618 {
624 else
631 }
632 }
633 }
636 }
639 /* See if DEST, produced in INSN, is used only a single time in the
640 sequel. If so, return a pointer to the innermost rtx expression in which
641 it is used.
643 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
645 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
646 care about REG_DEAD notes or LOG_LINKS.
648 Otherwise, we find the single use by finding an insn that has a
649 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
650 only referenced once in that insn, we know that it must be the first
651 and last insn referencing DEST. */
655 {
656 basic_block bb;
662 {
672 }
682 {
688 {
693 }
694 }
697 }
698 \f
699 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
700 insn. The substitution can be undone by undo_all. If INTO is already
701 set to NEWVAL, do not record this change. Because computing NEWVAL might
702 also call SUBST, we have to compute it before we put anything into
703 the undo table. */
705 static void
707 {
714 /* We'd like to catch as many invalid transformations here as
715 possible. Unfortunately, there are way too many mode changes
716 that are perfectly valid, so we'd waste too much effort for
717 little gain doing the checks here. Focus on catching invalid
718 transformations involving integer constants. */
721 {
722 /* Sanity check that we're replacing oldval with a CONST_INT
723 that is a valid sign-extension for the original mode. */
727 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
728 CONST_INT is not valid, because after the replacement, the
729 original mode would be gone. Unfortunately, we can't tell
730 when do_SUBST is called to replace the operand thereof, so we
731 perform this test on oldval instead, checking whether an
732 invalid replacement took place before we got here. */
737 }
741 else
750 }
752 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
754 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
755 for the value of a HOST_WIDE_INT value (including CONST_INT) is
756 not safe. */
758 static void
760 {
769 else
778 }
780 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
782 /* Similar to SUBST, but just substitute the mode. This is used when
783 changing the mode of a pseudo-register, so that any other
784 references to the entry in the regno_reg_rtx array will change as
785 well. */
787 static void
789 {
798 else
807 }
809 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
811 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
813 static void
815 {
824 else
833 }
835 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
836 \f
837 /* Subroutine of try_combine. Determine whether the replacement patterns
838 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
839 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
840 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
841 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
842 of all the instructions can be estimated and the replacements are more
843 expensive than the original sequence. */
845 static bool
848 {
853 /* Lookup the original insn_rtx_costs. */
858 {
861 {
865 }
866 else
867 {
871 }
872 }
873 else
874 {
877 }
879 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
880 correct that. */
885 /* Calculate the replacement insn_rtx_costs. */
888 {
892 }
893 else
894 {
897 }
900 {
906 {
909 }
910 else
912 }
914 /* Disallow this combination if both new_cost and old_cost are greater than
915 zero, and new_cost is greater than old cost. */
919 {
938 else
940 }
945 /* Update the uid_insn_cost array with the replacement costs. */
949 {
953 }
956 }
959 /* Delete any insns that copy a register to itself. */
961 static void
963 {
965 basic_block bb;
968 {
970 {
973 {
978 }
979 }
980 }
981 }
983 \f
984 /* Return false if we do not want to (or cannot) combine DEF. */
985 static bool
987 {
988 /* Do not consider if it is pre/post modification in MEM. */
994 /* Do not combine frame pointer adjustments. */
997 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1005 }
1007 /* Return false if we do not want to (or cannot) combine USE. */
1008 static bool
1010 {
1011 /* Do not consider the usage of the stack pointer by function call. */
1016 }
1018 /* Fill in log links field for all insns. */
1020 static void
1022 {
1023 basic_block bb;
1030 /* Pass through each block from the end, recording the uses of each
1031 register and establishing log links when def is encountered.
1032 Note that we do not clear next_use array in order to save time,
1033 so we have to test whether the use is in the same basic block as def.
1035 There are a few cases below when we do not consider the definition or
1036 usage -- these are taken from original flow.c did. Don't ask me why it is
1037 done this way; I don't know and if it works, I don't want to know. */
1040 {
1042 {
1046 /* Log links are created only once. */
1050 {
1066 /* flow.c claimed:
1068 We don't build a LOG_LINK for hard registers contained
1069 in ASM_OPERANDs. If these registers get replaced,
1070 we might wind up changing the semantics of the insn,
1071 even if reload can make what appear to be valid
1072 assignments later. */
1077 /* Don't add duplicate links between instructions. */
1086 }
1091 }
1092 }
1095 }
1097 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1098 true if we found a LOG_LINK that proves that A feeds B. This only works
1099 if there are no instructions between A and B which could have a link
1100 depending on A, since in that case we would not record a link for B.
1101 We also check the implicit dependency created by a cc0 setter/user
1102 pair. */
1104 static bool
1106 {
1114 }
1115 \f
1116 /* Main entry point for combiner. F is the first insn of the function.
1117 NREGS is the first unused pseudo-reg number.
1119 Return nonzero if the combiner has turned an indirect jump
1120 instruction into a direct jump. */
1121 static int
1123 {
1128 basic_block last_bb;
1148 /* Allocate array for insn info. */
1156 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1157 problems when, for example, we have j <<= 1 in a loop. */
1162 /* Scan all SETs and see if we can deduce anything about what
1163 bits are known to be zero for some registers and how many copies
1164 of the sign bit are known to exist for those registers.
1166 Also set any known values so that we can use it while searching
1167 for what bits are known to be set. */
1170 /* Allow the entry block and the first block to fall into the same EBB.
1171 Conceptually the incoming promotions are assigned to the entry block. */
1176 {
1181 label_tick++;
1189 {
1190 rtx links;
1196 insn);
1203 insn);
1205 /* Record the current insn_rtx_cost of this instruction. */
1208 optimize_this_for_speed_p);
1212 }
1213 }
1217 /* Now scan all the insns in forward order. */
1225 {
1231 label_tick++;
1241 {
1255 /* See if we know about function return values before this
1256 insn based upon SUBREG flags. */
1259 /* See if we can find hardregs and subreg of pseudos in
1260 narrower modes. This could help turning TRUNCATEs
1261 into SUBREGs. */
1264 /* Try this insn with each insn it links back to. */
1270 {
1273 }
1275 /* Try each sequence of three linked insns ending with this one. */
1279 {
1282 /* If the linked insn has been replaced by a note, then there
1283 is no point in pursuing this chain any further. */
1291 {
1294 }
1295 }
1297 /* Try to combine a jump insn that uses CC0
1298 with a preceding insn that sets CC0, and maybe with its
1299 logical predecessor as well.
1300 This is how we make decrement-and-branch insns.
1301 We need this special code because data flow connections
1302 via CC0 do not get entered in LOG_LINKS. */
1309 {
1320 }
1322 /* Do the same for an insn that explicitly references CC0. */
1329 {
1340 }
1342 /* Finally, see if any of the insns that this insn links to
1343 explicitly references CC0. If so, try this insn, that insn,
1344 and its predecessor if it sets CC0. */
1346 {
1358 }
1360 /* Try combining an insn with two different insns whose results it
1361 uses. */
1371 {
1374 }
1376 /* Try four-instruction combinations. */
1379 {
1383 /* If the linked insn has been replaced by a note, then there
1384 is no point in pursuing this chain any further. */
1389 {
1393 /* I0 -> I1 -> I2 -> I3. */
1399 {
1402 }
1403 /* I0, I1 -> I2, I2 -> I3. */
1410 {
1413 }
1414 }
1417 {
1421 /* I0 -> I2; I1, I2 -> I3. */
1427 {
1430 }
1431 /* I0 -> I1; I1, I2 -> I3. */
1437 {
1440 }
1441 }
1442 }
1444 /* Try this insn with each REG_EQUAL note it links back to. */
1446 {
1452 /* Avoid using a register that may already been marked
1453 dead by an earlier instruction. */
1458 {
1459 /* Temporarily replace the set's source with the
1460 contents of the REG_EQUAL note. The insn will
1461 be deleted or recognized by try_combine. */
1469 last_combined_insn);
1472 {
1475 }
1477 }
1478 }
1483 retry:
1484 ;
1485 }
1486 }
1493 /* Clean up. */
1499 {
1502 {
1505 }
1507 }
1517 /* Make recognizer allow volatile MEMs again. */
1521 }
1523 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1525 static void
1527 {
1533 }
1534 \f
1535 /* Set up any promoted values for incoming argument registers. */
1537 static void
1539 {
1540 tree arg;
1545 {
1550 /* Only continue if the incoming argument is in a register. */
1554 /* Determine, if possible, whether all call sites of the current
1555 function lie within the current compilation unit. (This does
1556 take into account the exporting of a function via taking its
1557 address, and so forth.) */
1560 /* The mode and signedness of the argument before any promotions happen
1561 (equal to the mode of the pseudo holding it at that stage). */
1565 /* The mode and signedness of the argument after any source language and
1566 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1570 /* The mode and signedness of the argument as it is actually passed,
1571 see assign_parm_setup_reg in function.c. */
1575 /* The mode of the register in which the argument is being passed. */
1578 /* Eliminate sign extensions in the callee when:
1579 (a) A mode promotion has occurred; */
1582 /* (b) The mode of the register is the same as the mode of
1583 the argument as it is passed; */
1586 /* (c) There's no language level extension; */
1588 ;
1589 /* (c.1) All callers are from the current compilation unit. If that's
1590 the case we don't have to rely on an ABI, we only have to know
1591 what we're generating right now, and we know that we will do the
1592 mode1 to mode2 promotion with the given sign. */
1595 /* (c.2) The combination of the two promotions is useful. This is
1596 true when the signs match, or if the first promotion is unsigned.
1597 In the later case, (sign_extend (zero_extend x)) is the same as
1598 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1604 /* Record that the value was promoted from mode1 to mode3,
1605 so that any sign extension at the head of the current
1606 function may be eliminated. */
1610 }
1611 }
1613 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1614 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1615 because some machines (maybe most) will actually do the sign-extension and
1616 this is the conservative approach.
1618 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1619 kludge. */
1621 static rtx
1623 {
1631 }
1633 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1634 and SET. */
1636 static void
1638 rtx x)
1639 {
1649 {
1653 }
1655 /* Don't call nonzero_bits if it cannot change anything. */
1657 {
1662 }
1664 /* Don't call num_sign_bit_copies if it cannot change anything. */
1666 {
1669 {
1673 }
1676 }
1677 }
1679 /* Called via note_stores. If X is a pseudo that is narrower than
1680 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1682 If we are setting only a portion of X and we can't figure out what
1683 portion, assume all bits will be used since we don't know what will
1684 be happening.
1686 Similarly, set how many bits of X are known to be copies of the sign bit
1687 at all locations in the function. This is the smallest number implied
1688 by any set of X. */
1690 static void
1692 {
1697 /* If this register is undefined at the start of the file, we can't
1698 say what its contents were. */
1699 && ! REGNO_REG_SET_P
1702 {
1706 {
1710 }
1712 /* If this register is being initialized using itself, and the
1713 register is uninitialized in this basic block, and there are
1714 no LOG_LINKS which set the register, then part of the
1715 register is uninitialized. In that case we can't assume
1716 anything about the number of nonzero bits.
1718 ??? We could do better if we checked this in
1719 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1720 could avoid making assumptions about the insn which initially
1721 sets the register, while still using the information in other
1722 insns. We would have to be careful to check every insn
1723 involved in the combination. */
1729 {
1736 {
1740 }
1741 }
1743 /* If this is a complex assignment, see if we can convert it into a
1744 simple assignment. */
1747 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1748 set what we know about X. */
1754 else
1755 {
1758 }
1759 }
1760 }
1761 \f
1762 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1763 optionally insns that were previously combined into I3 or that will be
1764 combined into the merger of INSN and I3. The order is PRED, PRED2,
1765 INSN, SUCC, SUCC2, I3.
1767 Return 0 if the combination is not allowed for any reason.
1769 If the combination is allowed, *PDEST will be set to the single
1770 destination of INSN and *PSRC to the single source, and this function
1771 will return 1. */
1773 static int
1777 {
1782 rtx link;
1787 {
1789 {
1794 }
1799 }
1803 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1804 or a PARALLEL consisting of such a SET and CLOBBERs.
1806 If INSN has CLOBBER parallel parts, ignore them for our processing.
1807 By definition, these happen during the execution of the insn. When it
1808 is merged with another insn, all bets are off. If they are, in fact,
1809 needed and aren't also supplied in I3, they may be added by
1810 recog_for_combine. Otherwise, it won't match.
1812 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1813 note.
1815 Get the source and destination of INSN. If more than one, can't
1816 combine. */
1822 {
1824 {
1828 {
1829 /* This is important to combine floating point insns
1830 for the SH4 port. */
1832 /* Combining an isolated USE doesn't make sense.
1833 We depend here on combinable_i3pat to reject them. */
1834 /* The code below this loop only verifies that the inputs of
1835 the SET in INSN do not change. We call reg_set_between_p
1836 to verify that the REG in the USE does not change between
1837 I3 and INSN.
1838 If the USE in INSN was for a pseudo register, the matching
1839 insn pattern will likely match any register; combining this
1840 with any other USE would only be safe if we knew that the
1841 used registers have identical values, or if there was
1842 something to tell them apart, e.g. different modes. For
1843 now, we forgo such complicated tests and simply disallow
1844 combining of USES of pseudo registers with any other USE. */
1847 {
1852 do
1853 {
1863 }
1865 }
1868 /* We can ignore CLOBBERs. */
1873 /* Ignore SETs whose result isn't used but not those that
1874 have side-effects. */
1880 /* If we have already found a SET, this is a second one and
1881 so we cannot combine with this insn. */
1889 /* Anything else means we can't combine. */
1891 }
1892 }
1895 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1896 so don't do anything with it. */
1899 }
1900 else
1906 /* The simplification in expand_field_assignment may call back to
1907 get_last_value, so set safe guard here. */
1913 /* Do not eliminate user-specified register if it is in an
1914 asm input because we may break the register asm usage defined
1915 in GCC manual if allow to do so.
1916 Be aware that this may cover more cases than we expect but this
1917 should be harmless. */
1922 /* Don't eliminate a store in the stack pointer. */
1924 /* Don't combine with an insn that sets a register to itself if it has
1925 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1927 /* Can't merge an ASM_OPERANDS. */
1929 /* Can't merge a function call. */
1931 /* Don't eliminate a function call argument. */
1937 /* Don't substitute into an incremented register. */
1941 /* Don't substitute into a non-local goto, this confuses CFG. */
1943 /* Make sure that DEST is not used after SUCC but before I3. */
1944 || (!all_adjacent
1945 && ((succ2
1949 /* Make sure that the value that is to be substituted for the register
1950 does not use any registers whose values alter in between. However,
1951 If the insns are adjacent, a use can't cross a set even though we
1952 think it might (this can happen for a sequence of insns each setting
1953 the same destination; last_set of that register might point to
1954 a NOTE). If INSN has a REG_EQUIV note, the register is always
1955 equivalent to the memory so the substitution is valid even if there
1956 are intervening stores. Also, don't move a volatile asm or
1957 UNSPEC_VOLATILE across any other insns. */
1958 || (! all_adjacent
1964 /* Don't combine across a CALL_INSN, because that would possibly
1965 change whether the life span of some REGs crosses calls or not,
1966 and it is a pain to update that information.
1967 Exception: if source is a constant, moving it later can't hurt.
1968 Accept that as a special case. */
1972 /* DEST must either be a REG or CC0. */
1974 {
1975 /* If register alignment is being enforced for multi-word items in all
1976 cases except for parameters, it is possible to have a register copy
1977 insn referencing a hard register that is not allowed to contain the
1978 mode being copied and which would not be valid as an operand of most
1979 insns. Eliminate this problem by not combining with such an insn.
1981 Also, on some machines we don't want to extend the life of a hard
1982 register. */
1987 /* Don't extend the life of a hard register unless it is
1988 user variable (if we have few registers) or it can't
1989 fit into the desired register (meaning something special
1990 is going on).
1991 Also avoid substituting a return register into I3, because
1992 reload can't handle a conflict with constraints of other
1993 inputs. */
1997 }
2005 {
2008 /* If the clobber represents an earlyclobber operand, we must not
2009 substitute an expression containing the clobbered register.
2010 As we do not analyze the constraint strings here, we have to
2011 make the conservative assumption. However, if the register is
2012 a fixed hard reg, the clobber cannot represent any operand;
2013 we leave it up to the machine description to either accept or
2014 reject use-and-clobber patterns. */
2020 }
2022 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2023 or not), reject, unless nothing volatile comes between it and I3 */
2026 {
2027 /* Make sure neither succ nor succ2 contains a volatile reference. */
2032 /* We'll check insns between INSN and I3 below. */
2033 }
2035 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2036 to be an explicit register variable, and was chosen for a reason. */
2042 /* If INSN contains volatile references (specifically volatile MEMs),
2043 we cannot combine across any other volatile references.
2044 Even if INSN doesn't contain volatile references, any intervening
2045 volatile insn might affect machine state. */
2048 ? volatile_refs_p
2055 /* If INSN contains an autoincrement or autodecrement, make sure that
2056 register is not used between there and I3, and not already used in
2057 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2058 Also insist that I3 not be a jump; if it were one
2059 and the incremented register were spilled, we would lose. */
2077 /* Don't combine an insn that follows a CC0-setting insn.
2078 An insn that uses CC0 must not be separated from the one that sets it.
2079 We do, however, allow I2 to follow a CC0-setting insn if that insn
2080 is passed as I1; in that case it will be deleted also.
2081 We also allow combining in this case if all the insns are adjacent
2082 because that would leave the two CC0 insns adjacent as well.
2083 It would be more logical to test whether CC0 occurs inside I1 or I2,
2084 but that would be much slower, and this ought to be equivalent. */
2087 {
2092 }
2094 /* If we get here, we have passed all the tests and the combination is
2095 to be allowed. */
2101 }
2102 \f
2103 /* LOC is the location within I3 that contains its pattern or the component
2104 of a PARALLEL of the pattern. We validate that it is valid for combining.
2106 One problem is if I3 modifies its output, as opposed to replacing it
2107 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2108 doing so would produce an insn that is not equivalent to the original insns.
2110 Consider:
2112 (set (reg:DI 101) (reg:DI 100))
2113 (set (subreg:SI (reg:DI 101) 0) <foo>)
2115 This is NOT equivalent to:
2117 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2118 (set (reg:DI 101) (reg:DI 100))])
2120 Not only does this modify 100 (in which case it might still be valid
2121 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2123 We can also run into a problem if I2 sets a register that I1
2124 uses and I1 gets directly substituted into I3 (not via I2). In that
2125 case, we would be getting the wrong value of I2DEST into I3, so we
2126 must reject the combination. This case occurs when I2 and I1 both
2127 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2128 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2129 of a SET must prevent combination from occurring. The same situation
2130 can occur for I0, in which case I0_NOT_IN_SRC is set.
2132 Before doing the above check, we first try to expand a field assignment
2133 into a set of logical operations.
2135 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2136 we place a register that is both set and used within I3. If more than one
2137 such register is detected, we fail.
2139 Return 1 if the combination is valid, zero otherwise. */
2141 static int
2144 {
2148 {
2153 rtx subdest;
2160 /* Check for the case where I3 modifies its output, as discussed
2161 above. We don't want to prevent pseudos from being combined
2162 into the address of a MEM, so only prevent the combination if
2163 i1 or i2 set the same MEM. */
2173 /* This is the same test done in can_combine_p except we can't test
2174 all_adjacent; we don't have to, since this instruction will stay
2175 in place, thus we are not considering increasing the lifetime of
2176 INNER_DEST.
2178 Also, if this insn sets a function argument, combining it with
2179 something that might need a spill could clobber a previous
2180 function argument; the all_adjacent test in can_combine_p also
2181 checks this; here, we do a more specific test for this case. */
2191 /* If DEST is used in I3, it is being killed in this insn, so
2192 record that for later. We have to consider paradoxical
2193 subregs here, since they kill the whole register, but we
2194 ignore partial subregs, STRICT_LOW_PART, etc.
2195 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2196 STACK_POINTER_REGNUM, since these are always considered to be
2197 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2207 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2213 {
2218 }
2219 }
2222 {
2229 }
2232 }
2233 \f
2234 /* Return 1 if X is an arithmetic expression that contains a multiplication
2235 and division. We don't count multiplications by powers of two here. */
2237 static int
2239 {
2241 {
2257 }
2258 }
2259 \f
2260 /* Determine whether INSN can be used in a combination. Return nonzero if
2261 not. This is used in try_combine to detect early some cases where we
2262 can't perform combinations. */
2264 static int
2266 {
2267 rtx set;
2270 /* If this isn't really an insn, we can't do anything.
2271 This can occur when flow deletes an insn that it has merged into an
2272 auto-increment address. */
2276 /* Never combine loads and stores involving hard regs that are likely
2277 to be spilled. The register allocator can usually handle such
2278 reg-reg moves by tying. If we allow the combiner to make
2279 substitutions of likely-spilled regs, reload might die.
2280 As an exception, we allow combinations involving fixed regs; these are
2281 not available to the register allocator so there's no risk involved. */
2302 }
2304 struct likely_spilled_retval_info
2305 {
2308 };
2310 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2311 hard registers that are known to be written to / clobbered in full. */
2312 static void
2314 {
2331 else
2334 }
2336 /* Return nonzero iff part of the return value is live during INSN, and
2337 it is likely spilled. This can happen when more than one insn is needed
2338 to copy the return value, e.g. when we consider to combine into the
2339 second copy insn for a complex value. */
2341 static int
2343 {
2345 rtx reg;
2348 /* We assume here that no machine mode needs more than
2349 32 hard registers when the value overlaps with a register
2350 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2365 /* Disregard parts of the return value that are set later. */
2374 /* Check if any of the (probably) live return value registers is
2375 likely spilled. */
2376 nregs --;
2377 do
2378 {
2384 }
2386 /* Adjust INSN after we made a change to its destination.
2388 Changing the destination can invalidate notes that say something about
2389 the results of the insn and a LOG_LINK pointing to the insn. */
2391 static void
2393 {
2394 /* For notes, be conservative and simply remove them. */
2397 /* The new insn will have a destination that was previously the destination
2398 of an insn just above it. Call distribute_links to make a LOG_LINK from
2399 the next use of that destination. */
2415 }
2417 /* Return TRUE if combine can reuse reg X in mode MODE.
2418 ADDED_SETS is nonzero if the original set is still required. */
2419 static bool
2421 {
2428 /* Allow hard registers if the new mode is legal, and occupies no more
2429 registers than the old mode. */
2434 /* Or a pseudo that is only used once. */
2437 && !added_sets
2439 }
2442 /* Check whether X, the destination of a set, refers to part of
2443 the register specified by REG. */
2445 static bool
2447 {
2448 /* Check that reg is an integer mode register. */
2459 }
2461 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2462 Note that the INSN should be deleted *after* removing dead edges, so
2463 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2464 but not for a (set (pc) (label_ref FOO)). */
2466 static void
2468 {
2476 {
2481 /* Remove barriers from the footer if there are any. */
2484 {
2487 else
2491 }
2494 }
2495 }
2497 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2498 by an arbitrary number of CLOBBERs. */
2499 static bool
2501 {
2520 }
2522 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2523 CLOBBERs), can be split into individual SETs in that order, without
2524 changing semantics. */
2525 static bool
2527 {
2535 {
2544 }
2547 }
2549 /* Try to combine the insns I0, I1 and I2 into I3.
2550 Here I0, I1 and I2 appear earlier than I3.
2551 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2552 I3.
2554 If we are combining more than two insns and the resulting insn is not
2555 recognized, try splitting it into two insns. If that happens, I2 and I3
2556 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2557 Otherwise, I0, I1 and I2 are pseudo-deleted.
2559 Return 0 if the combination does not work. Then nothing is changed.
2560 If we did the combination, return the insn at which combine should
2561 resume scanning.
2563 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2564 new direct jump instruction.
2566 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2567 been I3 passed to an earlier try_combine within the same basic
2568 block. */
2573 {
2574 /* New patterns for I3 and I2, respectively. */
2578 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2579 dead. */
2581 /* Total number of SETs to put into I3. */
2583 /* Nonzero if I2's or I1's body now appears in I3. */
2585 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2587 /* Contains I3 if the destination of I3 is used in its source, which means
2588 that the old life of I3 is being killed. If that usage is placed into
2589 I2 and not in I3, a REG_DEAD note must be made. */
2591 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2593 /* Copy of SET_SRC of I1 and I0, if needed. */
2595 /* Set if I2DEST was reused as a scratch register. */
2597 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2599 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2604 /* Notes that must be added to REG_NOTES in I3 and I2. */
2606 /* Notes that we substituted I3 into I2 instead of the normal case. */
2608 /* Notes that I1, I2 or I3 is a MULT operation. */
2615 rtx temp_expr;
2618 rtx new_other_notes;
2621 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2622 never be). */
2626 /* Only try four-insn combinations when there's high likelihood of
2627 success. Look for simple insns, such as loads of constants or
2628 binary operations involving a constant. */
2630 {
2640 {
2643 rtx src;
2648 {
2651 }
2653 ngood++;
2656 nshift++;
2657 }
2659 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2660 are likely manipulating its value. Ideally we'll be able to combine
2661 all four insns into a bitfield insertion of some kind.
2663 Note the source in I0 might be inside a sign/zero extension and the
2664 memory modes in I0 and I3 might be different. So extract the address
2665 from the destination of I3 and search for it in the source of I0.
2667 In the event that there's a match but the source/dest do not actually
2668 refer to the same memory, the worst that happens is we try some
2669 combinations that we wouldn't have otherwise. */
2671 /* Ensure the source of SET0 is a MEM, possibly buried inside
2672 an extension. */
2678 /* Ensure the destination of SET3 is a MEM. */
2680 /* Would it be better to extract the base address for the MEM
2681 in SET3 and look for that? I don't have cases where it matters
2682 but I could envision such cases. */
2688 }
2690 /* Exit early if one of the insns involved can't be used for
2691 combinations. */
2702 combine_attempts++;
2705 /* Reset the hard register usage information. */
2709 {
2716 else
2719 }
2721 /* If multiple insns feed into one of I2 or I3, they can be in any
2722 order. To simplify the code below, reorder them in sequence. */
2732 /* First check for one important special case that the code below will
2733 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2734 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2735 we may be able to replace that destination with the destination of I3.
2736 This occurs in the common code where we compute both a quotient and
2737 remainder into a structure, in which case we want to do the computation
2738 directly into the structure to avoid register-register copies.
2740 Note that this case handles both multiple sets in I2 and also cases
2741 where I2 has a number of CLOBBERs inside the PARALLEL.
2743 We make very conservative checks below and only try to handle the
2744 most common cases of this. For example, we only handle the case
2745 where I2 and I3 are adjacent to avoid making difficult register
2746 usage tests. */
2754 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2755 below would need to check what is inside (and reg_overlap_mentioned_p
2756 doesn't support those codes anyway). Don't allow those destinations;
2757 the resulting insn isn't likely to be recognized anyway. */
2763 {
2766 /* Make sure that the destination of I3,
2767 which we are going to substitute into one output of I2,
2768 is not used within another output of I2. We must avoid making this:
2769 (parallel [(set (mem (reg 69)) ...)
2770 (set (reg 69) ...)])
2771 which is not well-defined as to order of actions.
2772 (Besides, reload can't handle output reloads for this.)
2774 The problem can also happen if the dest of I3 is a memory ref,
2775 if another dest in I2 is an indirect memory ref. */
2783 /* Make sure this PARALLEL is not an asm. We do not allow combining
2784 that usually (see can_combine_p), so do not here either. */
2794 {
2795 combine_merges++;
2805 /* Replace the dest in I2 with our dest and make the resulting
2806 insn the new pattern for I3. Then skip to where we validate
2807 the pattern. Everything was set up above. */
2812 }
2813 }
2815 /* If I2 is setting a pseudo to a constant and I3 is setting some
2816 sub-part of it to another constant, merge them by making a new
2817 constant. */
2824 {
2830 {
2833 {
2839 }
2840 }
2841 else
2842 {
2847 }
2850 {
2851 /* If this is the low part, we're done. */
2853 ;
2854 /* Handle the case where inner is twice the size of outer. */
2858 /* Otherwise give up for now. */
2859 else
2861 }
2864 {
2868 wide_int o
2873 combine_merges++;
2880 /* Replace the source in I2 with the new constant and make the
2881 resulting insn the new pattern for I3. Then skip to where we
2882 validate the pattern. Everything was set up above. */
2888 /* The dest of I3 has been replaced with the dest of I2. */
2891 }
2892 }
2894 /* If we have no I1 and I2 looks like:
2895 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2896 (set Y OP)])
2897 make up a dummy I1 that is
2898 (set Y OP)
2899 and change I2 to be
2900 (set (reg:CC X) (compare:CC Y (const_int 0)))
2902 (We can ignore any trailing CLOBBERs.)
2904 This undoes a previous combination and allows us to match a branch-and-
2905 decrement insn. */
2917 {
2918 /* We make I1 with the same INSN_UID as I2. This gives it
2919 the same DF_INSN_LUID for value tracking. Our fake I1 will
2920 never appear in the insn stream so giving it the same INSN_UID
2921 as I2 will not cause a problem. */
2934 }
2936 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2937 make those two SETs separate I1 and I2 insns, and make an I0 that is
2938 the original I1. */
2944 {
2945 /* If there is no I1, there is no I0 either. */
2948 /* We make I1 with the same INSN_UID as I2. This gives it
2949 the same DF_INSN_LUID for value tracking. Our fake I1 will
2950 never appear in the insn stream so giving it the same INSN_UID
2951 as I2 will not cause a problem. */
2959 }
2961 /* Verify that I2 and I1 are valid for combining. */
2967 {
2970 }
2972 /* Record whether I2DEST is used in I2SRC and similarly for the other
2973 cases. Knowing this will help in register status updating below. */
2984 /* For the earlier insns, determine which of the subsequent ones they
2985 feed. */
2992 /* Ensure that I3's pattern can be the destination of combines. */
2998 {
3001 }
3003 /* See if any of the insns is a MULT operation. Unless one is, we will
3004 reject a combination that is, since it must be slower. Be conservative
3005 here. */
3013 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3014 We used to do this EXCEPT in one case: I3 has a post-inc in an
3015 output operand. However, that exception can give rise to insns like
3016 mov r3,(r3)+
3017 which is a famous insn on the PDP-11 where the value of r3 used as the
3018 source was model-dependent. Avoid this sort of thing. */
3020 #if 0
3026 /* It's not the exception. */
3027 #endif
3029 {
3030 rtx link;
3036 {
3039 }
3040 }
3042 /* See if the SETs in I1 or I2 need to be kept around in the merged
3043 instruction: whenever the value set there is still needed past I3.
3044 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3046 For the SET in I1, we have two cases: if I1 and I2 independently feed
3047 into I3, the set in I1 needs to be kept around unless I1DEST dies
3048 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3049 in I1 needs to be kept around unless I1DEST dies or is set in either
3050 I2 or I3. The same considerations apply to I0. */
3057 else
3065 else
3068 /* We are about to copy insns for the case where they need to be kept
3069 around. Check that they can be copied in the merged instruction. */
3075 {
3078 }
3080 /* If the set in I2 needs to be kept around, we must make a copy of
3081 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3082 PATTERN (I2), we are only substituting for the original I1DEST, not into
3083 an already-substituted copy. This also prevents making self-referential
3084 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3085 I2DEST. */
3088 {
3091 else
3093 }
3096 {
3099 else
3101 }
3104 {
3107 else
3109 }
3111 combine_merges++;
3113 /* Substitute in the latest insn for the regs set by the earlier ones. */
3119 /* Many machines that don't use CC0 have insns that can both perform an
3120 arithmetic operation and set the condition code. These operations will
3121 be represented as a PARALLEL with the first element of the vector
3122 being a COMPARE of an arithmetic operation with the constant zero.
3123 The second element of the vector will set some pseudo to the result
3124 of the same arithmetic operation. If we simplify the COMPARE, we won't
3125 match such a pattern and so will generate an extra insn. Here we test
3126 for this case, where both the comparison and the operation result are
3127 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3128 I2SRC. Later we will make the PARALLEL that contains I2. */
3134 {
3135 rtx newpat_dest;
3149 {
3154 }
3156 /* Do the rest only if op1 is const0_rtx, which may be the
3157 result of simplification. */
3159 {
3160 /* If a single use of the CC is found, prepare to modify it
3161 when SELECT_CC_MODE returns a new CC-class mode, or when
3162 the above simplify_compare_const() returned a new comparison
3163 operator. undobuf.other_insn is assigned the CC use insn
3164 when modifying it. */
3166 {
3167 #ifdef SELECT_CC_MODE
3168 machine_mode new_mode
3173 {
3178 else
3179 {
3182 }
3183 }
3184 #endif
3185 /* Cases for modifying the CC-using comparison. */
3187 /* ??? Do we need to verify the zero rtx? */
3189 {
3190 /* Replace cc_use_loc with entire new RTX. */
3195 }
3197 {
3198 /* Just replace the CC reg with a new mode. */
3201 }
3202 }
3204 /* Now we modify the current newpat:
3205 First, SET_DEST(newpat) is updated if the CC mode has been
3206 altered. For targets without SELECT_CC_MODE, this should be
3207 optimized away. */
3210 /* This is always done to propagate i2src into newpat. */
3213 /* Create new version of i2pat if needed; the below PARALLEL
3214 creation needs this to work correctly. */
3218 }
3219 }
3222 {
3223 /* It is possible that the source of I2 or I1 may be performing
3224 an unneeded operation, such as a ZERO_EXTEND of something
3225 that is known to have the high part zero. Handle that case
3226 by letting subst look at the inner insns.
3228 Another way to do this would be to have a function that tries
3229 to simplify a single insn instead of merging two or more
3230 insns. We don't do this because of the potential of infinite
3231 loops and because of the potential extra memory required.
3232 However, doing it the way we are is a bit of a kludge and
3233 doesn't catch all cases.
3235 But only do this if -fexpensive-optimizations since it slows
3236 things down and doesn't usually win.
3238 This is not done in the COMPARE case above because the
3239 unmodified I2PAT is used in the PARALLEL and so a pattern
3240 with a modified I2SRC would not match. */
3243 {
3244 /* Pass pc_rtx so no substitutions are done, just
3245 simplifications. */
3247 {
3250 }
3254 }
3259 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3260 copy of I2SRC each time we substitute it, in order to avoid creating
3261 self-referential RTL when we will be substituting I1SRC for I1DEST
3262 later. Likewise if I0 feeds into I2, either directly or indirectly
3263 through I1, and I0DEST is in I0SRC. */
3270 /* Record whether I2's body now appears within I3's body. */
3272 }
3274 /* If we already got a failure, don't try to do more. Otherwise, try to
3275 substitute I1 if we have it. */
3278 {
3279 /* Check that an autoincrement side-effect on I1 has not been lost.
3280 This happens if I1DEST is mentioned in I2 and dies there, and
3281 has disappeared from the new pattern. */
3283 && i1_feeds_i2_n
3286 /* Before we can do this substitution, we must redo the test done
3287 above (see detailed comments there) that ensures I1DEST isn't
3288 mentioned in any SETs in NEWPAT that are field assignments. */
3291 {
3294 }
3299 /* If the following substitution will modify I1SRC, make a copy of it
3300 for the case where it is substituted for I1DEST in I2PAT later. */
3304 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3305 copy of I1SRC each time we substitute it, in order to avoid creating
3306 self-referential RTL when we will be substituting I0SRC for I0DEST
3307 later. */
3312 /* Record whether I1's body now appears within I3's body. */
3314 }
3316 /* Likewise for I0 if we have it. */
3319 {
3326 {
3329 }
3331 /* If the following substitution will modify I0SRC, make a copy of it
3332 for the case where it is substituted for I0DEST in I1PAT later. */
3335 /* And a copy for I0DEST in I2PAT substitution. */
3344 }
3346 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3347 to count all the ways that I2SRC and I1SRC can be used. */
3358 /* Fail if we tried to make a new register. */
3360 /* Fail if we couldn't do something and have a CLOBBER. */
3362 /* Fail if this new pattern is a MULT and we didn't have one before
3363 at the outer level. */
3366 {
3369 }
3371 /* If the actions of the earlier insns must be kept
3372 in addition to substituting them into the latest one,
3373 we must make a new PARALLEL for the latest insn
3374 to hold additional the SETs. */
3377 {
3379 combine_extras++;
3382 {
3388 }
3389 else
3390 {
3395 }
3401 {
3407 }
3409 {
3418 }
3419 }
3421 validate_replacement:
3423 /* Note which hard regs this insn has as inputs. */
3426 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3427 consider splitting this pattern, we might need these clobbers. */
3430 {
3436 }
3438 /* We have recognized nothing yet. */
3441 /* See if this is a PARALLEL of two SETs where one SET's destination is
3442 a register that is unused and this isn't marked as an instruction that
3443 might trap in an EH region. In that case, we just need the other SET.
3444 We prefer this over the PARALLEL.
3446 This can occur when simplifying a divmod insn. We *must* test for this
3447 case here because the code below that splits two independent SETs doesn't
3448 handle this case correctly when it updates the register status.
3450 It's pointless doing this if we originally had two sets, one from
3451 i3, and one from i2. Combining then splitting the parallel results
3452 in the original i2 again plus an invalid insn (which we delete).
3453 The net effect is only to move instructions around, which makes
3454 debug info less accurate. */
3459 {
3470 {
3473 }
3482 {
3488 }
3492 }
3494 /* Is the result of combination a valid instruction? */
3498 /* If we were combining three insns and the result is a simple SET
3499 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3500 insns. There are two ways to do this. It can be split using a
3501 machine-specific method (like when you have an addition of a large
3502 constant) or by combine in the function find_split_point. */
3506 {
3510 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3511 use I2DEST as a scratch register will help. In the latter case,
3512 convert I2DEST to the mode of the source of NEWPAT if we can. */
3516 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3517 inputs of NEWPAT. */
3519 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3520 possible to try that as a scratch reg. This would require adding
3521 more code to make it work though. */
3524 {
3527 /* First try to split using the original register as a
3528 scratch register. */
3532 i2dest)));
3535 /* If that didn't work, try changing the mode of I2DEST if
3536 we can. */
3541 {
3543 rtx ni2dest;
3547 else
3548 {
3551 }
3553 parallel = (gen_rtx_PARALLEL
3557 ni2dest))));
3562 {
3570 }
3571 }
3574 }
3576 /* If recog_for_combine has discarded clobbers, try to use them
3577 again for the split. */
3579 {
3582 }
3585 {
3590 }
3594 {
3604 /* If I2 or I3 has multiple SETs, we won't know how to track
3605 register status, so don't use these insns. If I2's destination
3606 is used between I2 and I3, we also can't use these insns. */
3616 /* It is possible that both insns now set the destination of I3.
3617 If so, we must show an extra use of it. */
3620 {
3639 }
3640 }
3642 /* If we can split it and use I2DEST, go ahead and see if that
3643 helps things be recognized. Verify that none of the registers
3644 are set between I2 and I3. */
3648 /* We need I2DEST in the proper mode. If it is a hard register
3649 or the only use of a pseudo, we can change its mode.
3650 Make sure we don't change a hard register to have a mode that
3651 isn't valid for it, or change the number of registers. */
3658 /* We can't overwrite I2DEST if its value is still used by
3659 NEWPAT. */
3661 {
3670 /* *SPLIT may be part of I2SRC, so make sure we have the
3671 original expression around for later debug processing.
3672 We should not need I2SRC any more in other cases. */
3675 else
3678 /* Get NEWDEST as a register in the proper mode. We have already
3679 validated that we can do this. */
3681 {
3684 else
3685 {
3688 }
3689 }
3691 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3692 an ASHIFT. This can occur if it was inside a PLUS and hence
3693 appeared to be a memory address. This is a kludge. */
3698 {
3701 /* Update split_code because we may not have a multiply
3702 anymore. */
3704 }
3706 /* Similarly for (plus (mult FOO (const_int pow2))). */
3712 {
3716 /* Update split_code because we may not have a multiply
3717 anymore. */
3719 }
3721 #ifdef INSN_SCHEDULING
3722 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3723 be written as a ZERO_EXTEND. */
3725 {
3726 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3727 what it really is. */
3732 else
3735 }
3736 #endif
3738 /* Attempt to split binary operators using arithmetic identities. */
3742 {
3749 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3751 {
3756 }
3757 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3764 {
3770 /* Split both "((X op Y) op X) op Y" and
3771 "((X op Y) op Y) op X" as "T op T" where T is
3772 "X op Y". */
3775 {
3780 }
3781 /* Split "((X op X) op Y) op Y)" as "T op T" where
3782 T is "X op Y". */
3784 {
3790 }
3791 }
3792 }
3795 {
3798 }
3802 /* recog_for_combine might have added CLOBBERs to newi2pat.
3803 Make sure NEWPAT does not depend on the clobbered regs. */
3807 {
3810 {
3813 }
3814 }
3816 /* If the split point was a MULT and we didn't have one before,
3817 don't use one now. */
3820 }
3821 }
3823 /* Check for a case where we loaded from memory in a narrow mode and
3824 then sign extended it, but we need both registers. In that case,
3825 we have a PARALLEL with both loads from the same memory location.
3826 We can split this into a load from memory followed by a register-register
3827 copy. This saves at least one insn, more if register allocation can
3828 eliminate the copy.
3830 We cannot do this if the destination of the first assignment is a
3831 condition code register or cc0. We eliminate this case by making sure
3832 the SET_DEST and SET_SRC have the same mode.
3834 We cannot do this if the destination of the second assignment is
3835 a register that we have already assumed is zero-extended. Similarly
3836 for a SUBREG of such a register. */
3871 {
3872 rtx ni2dest;
3886 }
3888 /* Similarly, check for a case where we have a PARALLEL of two independent
3889 SETs but we started with three insns. In this case, we can do the sets
3890 as two separate insns. This case occurs when some SET allows two
3891 other insns to combine, but the destination of that SET is still live.
3893 Also do this if we started with two insns and (at least) one of the
3894 resulting sets is a noop; this noop will be deleted later. */
3913 {
3917 /* Normally, it doesn't matter which of the two is done first,
3918 but the one that references cc0 can't be the second, and
3919 one which uses any regs/memory set in between i2 and i3 can't
3920 be first. The PARALLEL might also have been pre-existing in i3,
3921 so we need to make sure that we won't wrongly hoist a SET to i2
3922 that would conflict with a death note present in there. */
3930 /* If I3 is a jump, ensure that set0 is a jump so that
3931 we do not create invalid RTL. */
3933 )
3934 {
3937 }
3945 /* If I3 is a jump, ensure that set1 is a jump so that
3946 we do not create invalid RTL. */
3948 )
3949 {
3952 }
3953 else
3954 {
3957 }
3962 {
3963 /* recog_for_combine might have added CLOBBERs to newi2pat.
3964 Make sure NEWPAT does not depend on the clobbered regs. */
3966 {
3969 {
3972 {
3975 }
3976 }
3977 }
3980 }
3981 }
3983 /* If it still isn't recognized, fail and change things back the way they
3984 were. */
3986 /* Is the result a reasonable ASM_OPERANDS? */
3988 {
3991 }
3993 /* If we had to change another insn, make sure it is valid also. */
3995 {
4003 {
4006 }
4007 }
4009 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4010 they are adjacent to each other or not. */
4012 {
4016 {
4019 }
4020 }
4022 /* Only allow this combination if insn_rtx_costs reports that the
4023 replacement instructions are cheaper than the originals. */
4025 {
4028 }
4031 {
4036 {
4041 /* Temporarily revert mode back. */
4045 {
4046 /* If we used i2dest as a scratch register with a
4047 different mode, substitute it for the original
4048 i2src while its original mode is temporarily
4049 restored, and then clear i2scratch so that we don't
4050 do it again later. */
4052 this_basic_block);
4054 /* Put back the new mode. */
4056 }
4057 else
4058 {
4063 {
4066 }
4067 else
4068 {
4075 }
4077 /* We're dealing with a reg that changed mode but not
4078 meaning, so we want to turn it into a subreg for
4079 the new mode. However, because of REG sharing and
4080 because its mode had already changed, we have to do
4081 it in two steps. First, replace any debug uses of
4082 reg, with its original mode temporarily restored,
4083 with this copy we have created; then, replace the
4084 copy with the SUBREG of the original shared reg,
4085 once again changed to the new mode. */
4087 this_basic_block);
4091 this_basic_block);
4092 }
4093 }
4094 }
4096 /* If we will be able to accept this, we have made a
4097 change to the destination of I3. This requires us to
4098 do a few adjustments. */
4101 {
4104 }
4106 /* We now know that we can do this combination. Merge the insns and
4107 update the status of registers and LOG_LINKS. */
4110 {
4115 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4116 ensure that they are still valid. Then add any non-duplicate
4117 notes added by recog_for_combine. */
4119 {
4129 }
4133 NULL_RTX);
4134 }
4137 {
4140 rtx ni2dest;
4142 /* I3 now uses what used to be its destination and which is now
4143 I2's destination. This requires us to do a few adjustments. */
4147 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4148 so we still will.
4150 However, some later insn might be using I2's dest and have
4151 a LOG_LINK pointing at I3. We must remove this link.
4152 The simplest way to remove the link is to point it at I1,
4153 which we know will be a NOTE. */
4155 /* newi2pat is usually a SET here; however, recog_for_combine might
4156 have added some clobbers. */
4159 else
4166 {
4168 {
4174 }
4175 }
4176 }
4178 {
4183 /* Compute which registers we expect to eliminate. newi2pat may be setting
4184 either i3dest or i2dest, so we must check it. */
4187 || !i2dest_killed
4189 /* For i1, we need to compute both local elimination and global
4190 elimination information with respect to newi2pat because i1dest
4191 may be the same as i3dest, in which case newi2pat may be setting
4192 i1dest. Global information is used when distributing REG_DEAD
4193 note for i2 and i3, in which case it does matter if newi2pat sets
4194 i1dest or not.
4196 Local information is used when distributing REG_DEAD note for i1,
4197 in which case it doesn't matter if newi2pat sets i1dest or not.
4198 See PR62151, if we have four insns combination:
4199 i0: r0 <- i0src
4200 i1: r1 <- i1src (using r0)
4201 REG_DEAD (r0)
4202 i2: r0 <- i2src (using r1)
4203 i3: r3 <- i3src (using r0)
4204 ix: using r0
4205 From i1's point of view, r0 is eliminated, no matter if it is set
4206 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4207 should be discarded.
4209 Note local information only affects cases in forms like "I1->I2->I3",
4210 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4211 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4212 i0dest anyway. */
4214 || !i1dest_killed
4219 /* Same case as i1. */
4226 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4227 clear them. */
4235 /* Ensure that we do not have something that should not be shared but
4236 occurs multiple times in the new insns. Check this by first
4237 resetting all the `used' flags and then copying anything is shared. */
4261 {
4268 {
4269 /* I2SRC must still be meaningful at this point. Some splitting
4270 operations can invalidate I2SRC, but those operations do not
4271 apply to calls. */
4274 }
4282 }
4287 /* We had one special case above where I2 had more than one set and
4288 we replaced a destination of one of those sets with the destination
4289 of I3. In that case, we have to update LOG_LINKS of insns later
4290 in this basic block. Note that this (expensive) case is rare.
4292 Also, in this case, we must pretend that all REG_NOTEs for I2
4293 actually came from I3, so that REG_UNUSED notes from I2 will be
4294 properly handled. */
4297 {
4306 temp_insn
4316 {
4321 }
4322 else
4325 }
4333 {
4336 this_basic_block);
4339 }
4340 else
4341 {
4344 this_basic_block);
4346 }
4349 {
4354 this_basic_block);
4356 }
4359 {
4364 this_basic_block);
4366 }
4368 /* Get death notes for everything that is now used in either I3 or
4369 I2 and used to die in a previous insn. If we built two new
4370 patterns, move from I1 to I2 then I2 to I3 so that we get the
4371 proper movement on registers that I2 modifies. */
4377 else
4383 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4400 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4401 know these are REG_UNUSED and want them to go to the desired insn,
4402 so we always pass it as i3. */
4406 NULL_RTX);
4410 NULL_RTX);
4412 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4413 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4414 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4415 in that case, it might delete I2. Similarly for I2 and I1.
4416 Show an additional death due to the REG_DEAD note we make here. If
4417 we discard it in distribute_notes, we will decrement it again. */
4420 {
4425 else
4428 }
4431 {
4436 else
4439 }
4442 {
4447 else
4450 }
4453 {
4458 else
4461 }
4469 {
4474 /* The insn that used to set this register doesn't exist, and
4475 this life of the register may not exist either. See if one of
4476 I3's links points to an insn that sets I2DEST. If it does,
4477 that is now the last known value for I2DEST. If we don't update
4478 this and I2 set the register to a value that depended on its old
4479 contents, we will get confused. If this insn is used, thing
4480 will be set correctly in combine_instructions. */
4488 /* If the reg formerly set in I2 died only once and that was in I3,
4489 zero its use count so it won't make `reload' do any work. */
4492 && ! i2dest_in_i2src
4495 }
4498 {
4511 && ! i1dest_in_i1src
4514 }
4517 {
4530 && ! i0dest_in_i0src
4533 }
4535 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4536 been made to this insn. The order is important, because newi2pat
4537 can affect nonzero_bits of newpat. */
4541 }
4544 {
4546 {
4549 }
4551 }
4554 {
4556 {
4559 }
4561 }
4564 {
4566 {
4569 }
4571 }
4574 {
4576 {
4579 }
4581 }
4584 {
4586 {
4589 }
4591 }
4593 /* Set new_direct_jump_p if a new return or simple jump instruction
4594 has been created. Adjust the CFG accordingly. */
4596 {
4600 }
4605 {
4608 }
4610 /* A noop might also need cleaning up of CFG, if it comes from the
4611 simplification of a jump. */
4616 {
4619 }
4626 {
4629 }
4631 combine_successes++;
4638 else
4640 }
4641 \f
4642 /* Get a marker for undoing to the current state. */
4646 {
4648 }
4650 /* Undo the modifications up to the marker. */
4652 static void
4654 {
4658 {
4663 {
4678 }
4682 }
4685 }
4687 /* Undo all the modifications recorded in undobuf. */
4689 static void
4691 {
4693 }
4695 /* We've committed to accepting the changes we made. Move all
4696 of the undos to the free list. */
4698 static void
4700 {
4704 {
4708 }
4710 }
4711 \f
4712 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4713 where we have an arithmetic expression and return that point. LOC will
4714 be inside INSN.
4716 try_combine will call this function to see if an insn can be split into
4717 two insns. */
4721 {
4730 /* First special-case some codes. */
4732 {
4734 #ifdef INSN_SCHEDULING
4735 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4736 point. */
4739 #endif
4743 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4744 using LO_SUM and HIGH. */
4747 {
4755 }
4757 /* If we have a PLUS whose second operand is a constant and the
4758 address is not valid, perhaps will can split it up using
4759 the machine-specific way to split large constants. We use
4760 the first pseudo-reg (one of the virtual regs) as a placeholder;
4761 it will not remain in the result. */
4766 {
4769 subst_insn);
4771 /* This should have produced two insns, each of which sets our
4772 placeholder. If the source of the second is a valid address,
4773 we can make put both sources together and make a split point
4774 in the middle. */
4787 && memory_address_addr_space_p
4790 {
4794 /* Replace the placeholder in SRC2 with SRC1. If we can
4795 find where in SRC2 it was placed, that can become our
4796 split point and we can replace this address with SRC2.
4797 Just try two obvious places. */
4808 {
4811 }
4812 }
4814 /* If that didn't work, perhaps the first operand is complex and
4815 needs to be computed separately, so make a split point there.
4816 This will occur on machines that just support REG + CONST
4817 and have a constant moved through some previous computation. */
4823 }
4825 /* If we have a PLUS whose first operand is complex, try computing it
4826 separately by making a split there. */
4837 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4838 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4839 we need to put the operand into a register. So split at that
4840 point. */
4850 /* See if we can split SET_SRC as it stands. */
4855 /* See if we can split SET_DEST as it stands. */
4860 /* See if this is a bitfield assignment with everything constant. If
4861 so, this is an IOR of an AND, so split it into that. */
4871 {
4877 unsigned HOST_WIDE_INT mask
4879 rtx or_mask;
4888 else
4889 {
4895 or_mask));
4896 }
4903 }
4905 /* Otherwise, see if this is an operation that we can split into two.
4906 If so, try to split that. */
4910 {
4912 /* If we are AND'ing with a large constant that is only a single
4913 bit and the result is only being used in a context where we
4914 need to know if it is zero or nonzero, replace it with a bit
4915 extraction. This will avoid the large constant, which might
4916 have taken more than one insn to make. If the constant were
4917 not a valid argument to the AND but took only one insn to make,
4918 this is no worse, but if it took more than one insn, it will
4919 be better. */
4929 {
4934 {
4937 }
4938 }
4942 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4943 is known to be on, this can be converted into a NEG of a shift. */
4949 {
4961 }
4967 /* We can't optimize if either mode is a partial integer
4968 mode as we don't know how many bits are significant
4969 in those modes. */
4983 {
4991 }
4996 }
5000 {
5003 /* For unsigned, we have a choice of a shift followed by an
5004 AND or two shifts. Use two shifts for field sizes where the
5005 constant might be too large. We assume here that we can
5006 always at least get 8-bit constants in an AND insn, which is
5007 true for every current RISC. */
5010 {
5011 unsigned HOST_WIDE_INT mask
5015 gen_rtx_LSHIFTRT
5023 }
5024 else
5025 {
5027 gen_rtx_fmt_ee
5038 }
5039 }
5041 /* See if this is a simple operation with a constant as the second
5042 operand. It might be that this constant is out of range and hence
5043 could be used as a split point. */
5051 /* Finally, see if this is a simple operation with its first operand
5052 not in a register. The operation might require this operand in a
5053 register, so return it as a split point. We can always do this
5054 because if the first operand were another operation, we would have
5055 already found it as a split point. */
5064 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5065 it is better to write this as (not (ior A B)) so we can split it.
5066 Similarly for IOR. */
5068 {
5076 }
5078 /* Many RISC machines have a large set of logical insns. If the
5079 second operand is a NOT, put it first so we will try to split the
5080 other operand first. */
5082 {
5086 }
5091 /* Canonicalization can produce (minus A (mult B C)), where C is a
5092 constant. It may be better to try splitting (plus (mult B -C) A)
5093 instead if this isn't a multiply by a power of two. */
5097 {
5105 mode)),
5108 }
5110 /* Split at a multiply-accumulate instruction. However if this is
5111 the SET_SRC, we likely do not have such an instruction and it's
5112 worthless to try this split. */
5121 }
5123 /* Otherwise, select our actions depending on our rtx class. */
5125 {
5131 /* ... fall through ... */
5139 /* ... fall through ... */
5141 /* Some machines have (and (shift ...) ...) insns. If X is not
5142 an AND, but XEXP (X, 0) is, use it as our split point. */
5152 /* Otherwise, we don't have a split point. */
5154 }
5155 }
5156 \f
5157 /* Throughout X, replace FROM with TO, and return the result.
5158 The result is TO if X is FROM;
5159 otherwise the result is X, but its contents may have been modified.
5160 If they were modified, a record was made in undobuf so that
5161 undo_all will (among other things) return X to its original state.
5163 If the number of changes necessary is too much to record to undo,
5164 the excess changes are not made, so the result is invalid.
5165 The changes already made can still be undone.
5166 undobuf.num_undo is incremented for such changes, so by testing that
5167 the caller can tell whether the result is valid.
5169 `n_occurrences' is incremented each time FROM is replaced.
5171 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5173 IN_COND is nonzero if we are at the top level of a condition.
5175 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5176 by copying if `n_occurrences' is nonzero. */
5178 static rtx
5180 {
5185 rtx new_rtx;
5187 /* Two expressions are equal if they are identical copies of a shared
5188 RTX or if they are both registers with the same register number
5189 and mode. */
5191 #define COMBINE_RTX_EQUAL_P(X,Y) \
5192 ((X) == (Y) \
5193 || (REG_P (X) && REG_P (Y) \
5194 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5196 /* Do not substitute into clobbers of regs -- this will never result in
5197 valid RTL. */
5202 {
5203 n_occurrences++;
5205 }
5207 /* If X and FROM are the same register but different modes, they
5208 will not have been seen as equal above. However, the log links code
5209 will make a LOG_LINKS entry for that case. If we do nothing, we
5210 will try to rerecognize our original insn and, when it succeeds,
5211 we will delete the feeding insn, which is incorrect.
5213 So force this insn not to match in this (rare) case. */
5218 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5219 of which may contain things that can be combined. */
5223 /* It is possible to have a subexpression appear twice in the insn.
5224 Suppose that FROM is a register that appears within TO.
5225 Then, after that subexpression has been scanned once by `subst',
5226 the second time it is scanned, TO may be found. If we were
5227 to scan TO here, we would find FROM within it and create a
5228 self-referent rtl structure which is completely wrong. */
5232 /* Parallel asm_operands need special attention because all of the
5233 inputs are shared across the arms. Furthermore, unsharing the
5234 rtl results in recognition failures. Failure to handle this case
5235 specially can result in circular rtl.
5237 Solve this by doing a normal pass across the first entry of the
5238 parallel, and only processing the SET_DESTs of the subsequent
5239 entries. Ug. */
5244 {
5247 /* If this substitution failed, this whole thing fails. */
5255 {
5261 {
5264 /* If this substitution failed, this whole thing fails. */
5270 }
5271 }
5272 }
5273 else
5274 {
5278 /* We don't need to process a SET_DEST that is a register, CC0,
5279 or PC, so set up to skip this common case. All other cases
5280 where we want to suppress replacing something inside a
5281 SET_SRC are handled via the IN_DEST operand. */
5288 /* Trying to simplify the operands of a widening MULT is not likely
5289 to create RTL matching a machine insn. */
5301 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5302 constant. */
5307 {
5309 {
5312 {
5314 {
5317 n_occurrences++;
5318 }
5319 else
5320 {
5322 unique_copy);
5324 /* If this substitution failed, this whole thing
5325 fails. */
5329 }
5332 }
5333 }
5335 {
5336 /* If this is a register being set, ignore it. */
5343 ;
5346 {
5347 /* In general, don't install a subreg involving two
5348 modes not tieable. It can worsen register
5349 allocation, and can even make invalid reload
5350 insns, since the reg inside may need to be copied
5351 from in the outside mode, and that may be invalid
5352 if it is an fp reg copied in integer mode.
5354 We allow two exceptions to this: It is valid if
5355 it is inside another SUBREG and the mode of that
5356 SUBREG and the mode of the inside of TO is
5357 tieable and it is valid if X is a SET that copies
5358 FROM to CC0. */
5366 && (!HAVE_cc0
5381 n_occurrences++;
5382 }
5383 else
5384 /* If we are in a SET_DEST, suppress most cases unless we
5385 have gone inside a MEM, in which case we want to
5386 simplify the address. We assume here that things that
5387 are actually part of the destination have their inner
5388 parts in the first expression. This is true for SUBREG,
5389 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5390 things aside from REG and MEM that should appear in a
5391 SET_DEST. */
5393 (((in_dest
5399 unique_copy);
5401 /* If we found that we will have to reject this combination,
5402 indicate that by returning the CLOBBER ourselves, rather than
5403 an expression containing it. This will speed things up as
5404 well as prevent accidents where two CLOBBERs are considered
5405 to be equal, thus producing an incorrect simplification. */
5411 {
5419 }
5422 {
5426 }
5427 else
5429 }
5430 }
5431 }
5433 /* Check if we are loading something from the constant pool via float
5434 extension; in this case we would undo compress_float_constant
5435 optimization and degenerate constant load to an immediate value. */
5439 {
5443 }
5445 /* Try to simplify X. If the simplification changed the code, it is likely
5446 that further simplification will help, so loop, but limit the number
5447 of repetitions that will be performed. */
5450 {
5451 /* If X is sufficiently simple, don't bother trying to do anything
5452 with it. */
5461 /* We no longer know the original mode of operand 0 since we
5462 have changed the form of X) */
5464 }
5467 }
5468 \f
5469 /* Simplify X, a piece of RTL. We just operate on the expression at the
5470 outer level; call `subst' to simplify recursively. Return the new
5471 expression.
5473 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5474 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5475 of a condition. */
5477 static rtx
5480 {
5483 rtx temp;
5486 /* If this is a commutative operation, put a constant last and a complex
5487 expression first. We don't need to do this for comparisons here. */
5490 {
5494 }
5496 /* Try to fold this expression in case we have constants that weren't
5497 present before. */
5500 {
5508 {
5511 {
5515 }
5518 }
5531 }
5534 {
5539 }
5541 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5542 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5543 things. Check for cases where both arms are testing the same
5544 condition.
5546 Don't do anything if all operands are very simple. */
5559 {
5564 /* If everything is a comparison, what we have is highly unlikely
5565 to be simpler, so don't use it. */
5568 {
5575 /* Simplify the alternative arms; this may collapse the true and
5576 false arms to store-flag values. Be careful to use copy_rtx
5577 here since true_rtx or false_rtx might share RTL with x as a
5578 result of the if_then_else_cond call above. */
5582 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5583 is unlikely to be simpler. */
5586 {
5589 /* Restarting if we generate a store-flag expression will cause
5590 us to loop. Just drop through in this case. */
5592 /* If the result values are STORE_FLAG_VALUE and zero, we can
5593 just make the comparison operation. */
5604 /* Likewise, we can make the negate of a comparison operation
5605 if the result values are - STORE_FLAG_VALUE and zero. */
5613 mode);
5624 mode);
5625 else
5628 mode,
5629 VOIDmode,
5630 cond,
5631 cop1),
5636 }
5637 }
5638 }
5640 /* First see if we can apply the inverse distributive law. */
5643 {
5647 }
5649 /* If CODE is an associative operation not otherwise handled, see if we
5650 can associate some operands. This can win if they are constants or
5651 if they are logically related (i.e. (a & b) & a). */
5657 {
5659 {
5663 rtx inner;
5665 /* Make sure we pass the constant operand if any as the second
5666 one if this is a commutative operation. */
5674 /* For commutative operations, try the other pair if that one
5675 didn't simplify. */
5677 {
5682 }
5686 }
5687 }
5689 /* A little bit of algebraic simplification here. */
5691 {
5693 /* Ensure that our address has any ASHIFTs converted to MULT in case
5694 address-recognizing predicates are called later. */
5703 /* See if this can be moved to simplify_subreg. */
5706 /* Don't call gen_lowpart if the inner mode
5707 is VOIDmode and we cannot simplify it, as SUBREG without
5708 inner mode is invalid. */
5715 {
5716 rtx temp;
5722 /* If op is known to have all lower bits zero, the result is zero. */
5732 }
5734 /* Don't change the mode of the MEM if that would change the meaning
5735 of the address. */
5742 /* Note that we cannot do any narrowing for non-constants since
5743 we might have been counting on using the fact that some bits were
5744 zero. We now do this in the SET. */
5751 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5752 replaced by (lshiftrt X C). This will convert
5753 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5761 /* If X has only a single bit that might be nonzero, say, bit I, convert
5762 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5763 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5764 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5765 or a SUBREG of one since we'd be making the expression more
5766 complex if it was just a register. */
5772 {
5773 rtx temp1 = simplify_shift_const
5779 /* If all we did was surround TEMP with the two shifts, we
5780 haven't improved anything, so don't use it. Otherwise,
5781 we are better off with TEMP1. */
5786 }
5790 /* We can't handle truncation to a partial integer mode here
5791 because we don't know the real bitsize of the partial
5792 integer mode. */
5801 /* We can truncate a constant value and return it. */
5805 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5806 whose value is a comparison can be replaced with a subreg if
5807 STORE_FLAG_VALUE permits. */
5816 /* (const (const X)) can become (const X). Do it this way rather than
5817 returning the inner CONST since CONST can be shared with a
5818 REG_EQUAL note. */
5824 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5825 can add in an offset. find_split_point will split this address up
5826 again if it doesn't match. */
5833 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5834 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5835 bit-field and can be replaced by either a sign_extend or a
5836 sign_extract. The `and' may be a zero_extend and the two
5837 <c>, -<c> constants may be reversed. */
5852 return simplify_shift_const
5859 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5860 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5861 the bitsize of the mode - 1. This allows simplification of
5862 "a = (b & 8) == 0;" */
5874 /* If we are adding two things that have no bits in common, convert
5875 the addition into an IOR. This will often be further simplified,
5876 for example in cases like ((a & 1) + (a & 2)), which can
5877 become a & 3. */
5882 {
5883 /* Try to simplify the expression further. */
5887 /* If we could, great. If not, do not go ahead with the IOR
5888 replacement, since PLUS appears in many special purpose
5889 address arithmetic instructions. */
5897 }
5901 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5902 (and <foo> (const_int pow2-1)) */
5912 /* If we have (mult (plus A B) C), apply the distributive law and then
5913 the inverse distributive law to see if things simplify. This
5914 occurs mostly in addresses, often when unrolling loops. */
5917 {
5921 }
5923 /* Try simplify a*(b/c) as (a*b)/c. */
5926 {
5932 }
5936 /* If this is a divide by a power of two, treat it as a shift if
5937 its first operand is a shift. */
5955 /* If the first operand is a condition code, we can't do anything
5956 with it. */
5960 {
5968 /* Simplify our comparison, if possible. */
5971 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5972 if only the low-order bit is possibly nonzero in X (such as when
5973 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5974 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5975 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5976 (plus X 1).
5978 Remove any ZERO_EXTRACT we made when thinking this was a
5979 comparison. It may now be simpler to use, e.g., an AND. If a
5980 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5981 the call to make_compound_operation in the SET case.
5983 Don't apply these optimizations if the caller would
5984 prefer a comparison rather than a value.
5985 E.g., for the condition in an IF_THEN_ELSE most targets need
5986 an explicit comparison. */
5989 ;
6005 {
6009 mode);
6010 }
6017 {
6021 const1_rtx);
6022 }
6030 {
6033 }
6035 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6036 those above. */
6038 ;
6054 {
6058 mode);
6059 }
6067 {
6071 mode);
6072 }
6074 /* If X is 0/1, (eq X 0) is X-1. */
6080 {
6083 }
6085 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6086 one bit that might be nonzero, we can convert (ne x 0) to
6087 (ashift x c) where C puts the bit in the sign bit. Remove any
6088 AND with STORE_FLAG_VALUE when we are done, since we are only
6089 going to test the sign bit. */
6096 {
6102 else
6104 }
6106 /* If the code changed, return a whole new comparison.
6107 We also need to avoid using SUBST in cases where
6108 simplify_comparison has widened a comparison with a CONST_INT,
6109 since in that case the wider CONST_INT may fail the sanity
6110 checks in do_SUBST. */
6117 /* Otherwise, keep this operation, but maybe change its operands.
6118 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6121 }
6131 /* If we are processing SET_DEST, we are done. */
6149 /* If this is a shift by a constant amount, simplify it. */
6165 }
6168 }
6169 \f
6170 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6172 static rtx
6174 {
6181 rtx temp;
6184 rtx reversed;
6186 /* Simplify storing of the truth value. */
6191 /* Also when the truth value has to be reversed. */
6197 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6198 in it is being compared against certain values. Get the true and false
6199 comparisons and see if that says anything about the value of each arm. */
6205 {
6206 HOST_WIDE_INT nzb;
6212 /* If FALSE_CODE is EQ, swap the codes and arms. */
6215 {
6218 }
6220 /* If we are comparing against zero and the expression being tested has
6221 only a single bit that might be nonzero, that is its value when it is
6222 not equal to zero. Similarly if it is known to be -1 or 0. */
6226 {
6229 }
6233 {
6236 }
6238 /* Now simplify an arm if we know the value of the register in the
6239 branch and it is used in the arm. Be careful due to the potential
6240 of locally-shared RTL. */
6257 }
6259 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6260 reversed, do so to avoid needing two sets of patterns for
6261 subtract-and-branch insns. Similarly if we have a constant in the true
6262 arm, the false arm is the same as the first operand of the comparison, or
6263 the false arm is more complicated than the true arm. */
6276 {
6285 /* It is possible that the conditional has been simplified out. */
6288 }
6290 /* If the two arms are identical, we don't need the comparison. */
6295 /* Convert a == b ? b : a to "a". */
6307 /* Look for cases where we have (abs x) or (neg (abs X)). */
6310 && comparison_p
6317 {
6323 return
6326 mode);
6329 }
6331 /* Look for MIN or MAX. */
6334 && comparison_p
6339 {
6354 }
6356 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6357 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6358 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6359 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6360 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6361 neither 1 or -1, but it isn't worth checking for. */
6364 && comparison_p
6367 {
6383 /* If an identity-zero op is commutative, check whether there
6384 would be a match if we swapped the operands. */
6404 {
6408 }
6420 {
6424 }
6440 {
6444 }
6456 {
6460 }
6463 {
6469 const_true_rtx));
6477 }
6478 }
6480 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6481 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6482 negation of a single bit, we can convert this operation to a shift. We
6483 can actually do this more generally, but it doesn't seem worth it. */
6492 return
6496 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6506 }
6507 \f
6508 /* Simplify X, a SET expression. Return the new expression. */
6510 static rtx
6512 {
6515 machine_mode mode
6520 /* (set (pc) (return)) gets written as (return). */
6524 /* Now that we know for sure which bits of SRC we are using, see if we can
6525 simplify the expression for the object knowing that we only need the
6526 low-order bits. */
6529 {
6532 }
6534 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6535 the comparison result and try to simplify it unless we already have used
6536 undobuf.other_insn. */
6544 {
6553 {
6556 {
6559 }
6560 }
6561 else
6569 {
6573 }
6574 else
6575 {
6580 /* Attempt to simplify CC user. */
6582 {
6586 }
6588 /* Convert X into a no-op move. */
6592 }
6594 /* Simplify our comparison, if possible. */
6597 #ifdef SELECT_CC_MODE
6598 /* If this machine has CC modes other than CCmode, check to see if we
6599 need to use a different CC mode here. */
6608 else
6611 /* If the mode changed, we have to change SET_DEST, the mode in the
6612 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6613 a hard register, just build new versions with the proper mode. If it
6614 is a pseudo, we lose unless it is only time we set the pseudo, in
6615 which case we can safely change its mode. */
6617 {
6619 {
6621 rtx new_dest;
6625 else
6626 {
6629 }
6636 }
6637 }
6640 /* If the code changed, we have to build a new comparison in
6641 undobuf.other_insn. */
6643 {
6652 /* If the only change we made was to change an EQ into an NE or
6653 vice versa, OP0 has only one bit that might be nonzero, and OP1
6654 is zero, check if changing the user of the condition code will
6655 produce a valid insn. If it won't, we can keep the original code
6656 in that insn by surrounding our operation with an XOR. */
6663 {
6668 {
6675 }
6676 }
6677 }
6682 /* Don't generate a compare of a CC with 0, just use that CC. */
6684 {
6687 }
6688 /* Otherwise, if we didn't previously have the same COMPARE we
6689 want, create it from scratch. */
6692 {
6695 }
6696 }
6697 else
6698 {
6699 /* Get SET_SRC in a form where we have placed back any
6700 compound expressions. Then do the checks below. */
6703 }
6705 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6706 and X being a REG or (subreg (reg)), we may be able to convert this to
6707 (set (subreg:m2 x) (op)).
6709 We can always do this if M1 is narrower than M2 because that means that
6710 we only care about the low bits of the result.
6712 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6713 perform a narrower operation than requested since the high-order bits will
6714 be undefined. On machine where it is defined, this transformation is safe
6715 as long as M1 and M2 have the same number of words. */
6723 && (WORD_REGISTER_OPERATIONS
6726 #ifdef CANNOT_CHANGE_MODE_CLASS
6731 #endif
6735 {
6738 dest));
6742 }
6744 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6745 in SRC. */
6751 {
6755 /* Here we make sure that we don't have a sign bit on. */
6758 {
6761 }
6762 }
6764 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6765 would require a paradoxical subreg. Replace the subreg with a
6766 zero_extend to avoid the reload that would otherwise be required. */
6774 {
6780 }
6782 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6783 are comparing an item known to be 0 or -1 against 0, use a logical
6784 operation instead. Check for one of the arms being an IOR of the other
6785 arm with some value. We compute three terms to be IOR'ed together. In
6786 practice, at most two will be nonzero. Then we do the IOR's. */
6794 && (!HAVE_conditional_move
6800 {
6826 false_rtx);
6832 term3));
6835 }
6837 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6838 whole thing fail. */
6843 else
6844 /* Convert this into a field assignment operation, if possible. */
6846 }
6847 \f
6848 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6849 result. */
6851 static rtx
6853 {
6859 {
6861 /* We can call simplify_and_const_int only if we don't lose
6862 any (sign) bits when converting INTVAL (op1) to
6863 "unsigned HOST_WIDE_INT". */
6867 {
6874 }
6876 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6877 apply the distributive law and then the inverse distributive
6878 law to see if things simplify. */
6880 {
6884 }
6886 {
6890 }
6894 /* If we have (ior (and A B) C), apply the distributive law and then
6895 the inverse distributive law to see if things simplify. */
6898 {
6902 }
6905 {
6909 }
6914 }
6917 }
6918 \f
6919 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6920 operations" because they can be replaced with two more basic operations.
6921 ZERO_EXTEND is also considered "compound" because it can be replaced with
6922 an AND operation, which is simpler, though only one operation.
6924 The function expand_compound_operation is called with an rtx expression
6925 and will convert it to the appropriate shifts and AND operations,
6926 simplifying at each stage.
6928 The function make_compound_operation is called to convert an expression
6929 consisting of shifts and ANDs into the equivalent compound expression.
6930 It is the inverse of this function, loosely speaking. */
6932 static rtx
6934 {
6938 rtx tem;
6941 {
6945 /* We can't necessarily use a const_int for a multiword mode;
6946 it depends on implicitly extending the value.
6947 Since we don't know the right way to extend it,
6948 we can't tell whether the implicit way is right.
6950 Even for a mode that is no wider than a const_int,
6951 we can't win, because we need to sign extend one of its bits through
6952 the rest of it, and we don't know which bit. */
6956 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6957 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6958 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6959 reloaded. If not for that, MEM's would very rarely be safe.
6961 Reject MODEs bigger than a word, because we might not be able
6962 to reference a two-register group starting with an arbitrary register
6963 (and currently gen_lowpart might crash for a SUBREG). */
6968 /* Reject MODEs that aren't scalar integers because turning vector
6969 or complex modes into shifts causes problems. */
6975 /* If the inner object has VOIDmode (the only way this can happen
6976 is if it is an ASM_OPERANDS), we can't do anything since we don't
6977 know how much masking to do. */
6986 /* ... fall through ... */
6989 /* If the operand is a CLOBBER, just return it. */
6998 /* Reject MODEs that aren't scalar integers because turning vector
6999 or complex modes into shifts causes problems. */
7007 /* This should stay within the object being extracted, fail otherwise. */
7018 }
7019 /* Convert sign extension to zero extension, if we know that the high
7020 bit is not set, as this is easier to optimize. It will be converted
7021 back to cheaper alternative in make_extraction. */
7029 {
7034 /* Make sure this is a profitable operation. */
7041 else
7043 }
7045 /* We can optimize some special cases of ZERO_EXTEND. */
7047 {
7048 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7049 know that the last value didn't have any inappropriate bits
7050 set. */
7058 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7067 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7068 is a comparison and STORE_FLAG_VALUE permits. This is like
7069 the first case, but it works even when GET_MODE (x) is larger
7070 than HOST_WIDE_INT. */
7079 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7089 }
7091 /* If we reach here, we want to return a pair of shifts. The inner
7092 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7093 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7094 logical depending on the value of UNSIGNEDP.
7096 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7097 converted into an AND of a shift.
7099 We must check for the case where the left shift would have a negative
7100 count. This can happen in a case like (x >> 31) & 255 on machines
7101 that can't shift by a constant. On those machines, we would first
7102 combine the shift with the AND to produce a variable-position
7103 extraction. Then the constant of 31 would be substituted in
7104 to produce such a position. */
7108 {
7117 }
7124 else
7125 /* Any other cases we can't handle. */
7128 /* If we couldn't do this for some reason, return the original
7129 expression. */
7134 }
7135 \f
7136 /* X is a SET which contains an assignment of one object into
7137 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7138 or certain SUBREGS). If possible, convert it into a series of
7139 logical operations.
7141 We half-heartedly support variable positions, but do not at all
7142 support variable lengths. */
7144 static const_rtx
7146 {
7147 rtx inner;
7151 machine_mode compute_mode;
7153 /* Loop until we find something we can't simplify. */
7155 {
7158 {
7162 }
7165 {
7170 /* A constant position should stay within the width of INNER. */
7176 {
7184 /* If position is ADJUST - X, new position is X. */
7186 else
7187 {
7192 pos);
7193 }
7194 }
7195 }
7197 /* A SUBREG between two modes that occupy the same numbers of words
7198 can be done by moving the SUBREG to the source. */
7200 /* We need SUBREGs to compute nonzero_bits properly. */
7201 && nonzero_sign_valid
7206 {
7208 gen_lowpart
7212 }
7213 else
7221 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7223 {
7224 machine_mode imode;
7226 /* Don't do anything for vector or complex integral types. */
7230 /* Try to find an integral mode to pun with. */
7237 }
7239 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7243 /* Now compute the equivalent expression. Make a copy of INNER
7244 for the SET_DEST in case it is a MEM into which we will substitute;
7245 we don't want shared RTL in that case. */
7247 compute_mode);
7251 compute_mode,
7253 compute_mode),
7254 inner);
7259 mask),
7260 pos);
7265 }
7268 }
7269 \f
7270 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7271 it is an RTX that represents the (variable) starting position; otherwise,
7272 POS is the (constant) starting bit position. Both are counted from the LSB.
7274 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7276 IN_DEST is nonzero if this is a reference in the destination of a SET.
7277 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7278 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7279 be used.
7281 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7282 ZERO_EXTRACT should be built even for bits starting at bit 0.
7284 MODE is the desired mode of the result (if IN_DEST == 0).
7286 The result is an RTX for the extraction or NULL_RTX if the target
7287 can't handle it. */
7289 static rtx
7293 {
7294 /* This mode describes the size of the storage area
7295 to fetch the overall value from. Within that, we
7296 ignore the POS lowest bits, etc. */
7298 machine_mode inner_mode;
7299 machine_mode wanted_inner_mode;
7306 HOST_WIDE_INT orig_pos;
7312 {
7313 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7314 consider just the QI as the memory to extract from.
7315 The subreg adds or removes high bits; its mode is
7316 irrelevant to the meaning of this extraction,
7317 since POS and LEN count from the lsb. */
7321 }
7326 {
7327 /* We're extracting the least significant bits of an rtx
7328 (ashift X (const_int C)), where LEN > C. Extract the
7329 least significant (LEN - C) bits of X, giving an rtx
7330 whose mode is MODE, then shift it left C times. */
7336 }
7342 /* See if this can be done without an extraction. We never can if the
7343 width of the field is not the same as that of some integer mode. For
7344 registers, we can only avoid the extraction if the position is at the
7345 low-order bit and this is either not in the destination or we have the
7346 appropriate STRICT_LOW_PART operation available.
7348 For MEM, we can avoid an extract if the field starts on an appropriate
7349 boundary and we can change the mode of the memory reference. */
7358 && (! in_dest
7362 && (pos
7365 /* We can't do this if we are widening INNER_MODE (it
7366 may not be aligned, for one thing). */
7372 {
7373 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7374 field. If the original and current mode are the same, we need not
7375 adjust the offset. Otherwise, we do if bytes big endian.
7377 If INNER is not a MEM, get a piece consisting of just the field
7378 of interest (in this case POS % BITS_PER_WORD must be 0). */
7381 {
7382 HOST_WIDE_INT offset;
7384 /* POS counts from lsb, but make OFFSET count in memory order. */
7387 else
7391 }
7393 {
7395 {
7396 /* We can't call gen_lowpart in a DEST since we
7397 always want a SUBREG (see below) and it would sometimes
7398 return a new hard register. */
7400 {
7415 /* Avoid creating invalid subregs, for example when
7416 simplifying (x>>32)&255. */
7421 }
7422 else
7424 }
7425 else
7427 }
7428 else
7430 len >= HOST_BITS_PER_WIDE_INT
7435 /* If this extraction is going into the destination of a SET,
7436 make a STRICT_LOW_PART unless we made a MEM. */
7451 /* If we know that no extraneous bits are set, and that the high
7452 bit is not set, convert the extraction to the cheaper of
7453 sign and zero extension, that are equivalent in these cases. */
7459 {
7463 /* Prefer ZERO_EXTENSION, since it gives more information to
7464 backends. */
7469 }
7471 /* Otherwise, sign- or zero-extend unless we already are in the
7472 proper mode. */
7476 }
7478 /* Unless this is a COMPARE or we have a funny memory reference,
7479 don't do anything with zero-extending field extracts starting at
7480 the low-order bit since they are simple AND operations. */
7485 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7486 if the position is not a constant and the length is not 1. In all
7487 other cases, we would only be going outside our object in cases when
7488 an original shift would have been undefined. */
7497 /* If INNER is not from memory, we want it to have the mode of a register
7498 extraction pattern's structure operand, or word_mode if there is no
7499 such pattern. The same applies to extraction_mode and pos_mode
7500 and their respective operands.
7502 For memory, assume that the desired extraction_mode and pos_mode
7503 are the same as for a register operation, since at present we don't
7504 have named patterns for aligned memory structures. */
7508 {
7512 }
7514 /* Never narrow an object, since that might not be safe. */
7522 else
7523 {
7524 /* Be careful not to go beyond the extracted object and maintain the
7525 natural alignment of the memory. */
7529 {
7532 }
7533 }
7538 {
7539 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7540 BITS_BIG_ENDIAN style. If position is constant, compute new
7541 position. Otherwise, build subtraction.
7542 Note that POS is relative to the mode of the original argument.
7543 If it's a MEM we need to recompute POS relative to that.
7544 However, if we're extracting from (or inserting into) a register,
7545 we want to recompute POS relative to wanted_inner_mode. */
7552 else
7553 pos_rtx
7556 pos_rtx);
7557 /* POS may be less than 0 now, but we check for that below.
7558 Note that it can only be less than 0 if !MEM_P (inner). */
7559 }
7561 /* If INNER has a wider mode, and this is a constant extraction, try to
7562 make it smaller and adjust the byte to point to the byte containing
7563 the value. */
7566 && ! pos_rtx
7571 {
7574 /* The computations below will be correct if the machine is big
7575 endian in both bits and bytes or little endian in bits and bytes.
7576 If it is mixed, we must adjust. */
7578 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7579 adjust OFFSET to compensate. */
7584 /* We can now move to the desired byte. */
7595 }
7597 /* If INNER is not memory, get it into the proper mode. If we are changing
7598 its mode, POS must be a constant and smaller than the size of the new
7599 mode. */
7601 {
7602 /* On the LHS, don't create paradoxical subregs implicitely truncating
7603 the register unless TRULY_NOOP_TRUNCATION. */
7606 wanted_inner_mode))
7618 pos_rtx
7624 }
7626 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7627 have to zero extend. Otherwise, we can just use a SUBREG. */
7630 {
7634 /* If we know that no extraneous bits are set, and that the high
7635 bit is not set, convert extraction to cheaper one - either
7636 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7637 cases. */
7645 {
7649 /* Prefer ZERO_EXTENSION, since it gives more information to
7650 backends. */
7654 }
7656 }
7658 /* Make POS_RTX unless we already have it and it is correct. If we don't
7659 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7660 be a CONST_INT. */
7667 /* Make the required operation. See if we can use existing rtx. */
7674 }
7675 \f
7676 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7677 with any other operations in X. Return X without that shift if so. */
7679 static rtx
7681 {
7684 rtx tem;
7687 {
7689 /* This is the shift itself. If it is wide enough, we will return
7690 either the value being shifted if the shift count is equal to
7691 COUNT or a shift for the difference. */
7705 /* If we can safely shift this constant and we find the inner shift,
7706 make a new operation. */
7711 {
7715 }
7720 }
7723 }
7724 \f
7725 /* Look at the expression rooted at X. Look for expressions
7726 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7727 Form these expressions.
7729 Return the new rtx, usually just X.
7731 Also, for machines like the VAX that don't have logical shift insns,
7732 try to convert logical to arithmetic shift operations in cases where
7733 they are equivalent. This undoes the canonicalizations to logical
7734 shifts done elsewhere.
7736 We try, as much as possible, to re-use rtl expressions to save memory.
7738 IN_CODE says what kind of expression we are processing. Normally, it is
7739 SET. In a memory address it is MEM. When processing the arguments of
7740 a comparison or a COMPARE against zero, it is COMPARE. */
7742 rtx
7744 {
7752 rtx tem;
7755 /* Select the code to be used in recursive calls. Once we are inside an
7756 address, we stay there. If we have a comparison, set to COMPARE,
7757 but once inside, go back to our default of SET. */
7764 /* Process depending on the code of this operation. If NEW is set
7765 nonzero, it will be returned. */
7768 {
7770 /* Convert shifts by constants into multiplications if inside
7771 an address. */
7776 {
7782 {
7785 }
7788 }
7798 {
7802 }
7805 {
7809 mode));
7811 }
7812 else
7813 {
7817 }
7828 {
7832 }
7835 {
7839 mode));
7841 }
7842 else
7843 {
7847 }
7851 /* If the second operand is not a constant, we can't do anything
7852 with it. */
7856 /* If the constant is a power of two minus one and the first operand
7857 is a logical right shift, make an extraction. */
7860 {
7864 }
7866 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7871 {
7873 next_code);
7878 /* If that didn't give anything, see if the AND simplifies on
7879 its own. */
7881 {
7885 }
7886 }
7887 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7893 {
7894 /* Apply the distributive law, and then try to make extractions. */
7901 }
7903 /* If we are have (and (rotate X C) M) and C is larger than the number
7904 of bits in M, this is an extraction. */
7910 {
7916 }
7918 /* On machines without logical shifts, if the operand of the AND is
7919 a logical shift and our mask turns off all the propagated sign
7920 bits, we can replace the logical shift with an arithmetic shift. */
7928 {
7935 make_compound_operation
7938 }
7940 /* If the constant is one less than a power of two, this might be
7941 representable by an extraction even if no shift is present.
7942 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7943 we are in a COMPARE. */
7947 next_code),
7950 /* If we are in a comparison and this is an AND with a power of two,
7951 convert this into the appropriate bit extract. */
7956 next_code),
7962 /* If the sign bit is known to be zero, replace this with an
7963 arithmetic shift. */
7968 {
7971 next_code),
7974 }
7976 /* ... fall through ... */
7982 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7983 this is a SIGN_EXTRACT. */
7990 {
7997 }
7999 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8000 If so, try to merge the shifts into a SIGN_EXTEND. We could
8001 also do this for some cases of SIGN_EXTRACT, but it doesn't
8002 seem worth the effort; the case checked for occurs on Alpha. */
8018 /* Call ourselves recursively on the inner expression. If we are
8019 narrowing the object and it has a different RTL code from
8020 what it originally did, do this SUBREG as a force_to_mode. */
8021 {
8025 /* If in_code is COMPARE, it isn't always safe to pass it through
8026 to the recursive make_compound_operation call. */
8030 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8031 is (const_int 0), rather than
8032 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8042 simplified
8050 {
8051 rtx newer
8054 /* If we have something other than a SUBREG, we might have
8055 done an expansion, so rerun ourselves. */
8059 /* force_to_mode can expand compounds. If it just re-expanded the
8060 compound, use gen_lowpart to convert to the desired mode. */
8062 /* Likewise if it re-expanded the compound only partially.
8063 This happens for SUBREG of ZERO_EXTRACT if they extract
8064 the same number of bits. */
8073 }
8077 }
8082 }
8085 {
8088 }
8090 /* Now recursively process each operand of this operation. We need to
8091 handle ZERO_EXTEND specially so that we don't lose track of the
8092 inner mode. */
8094 {
8102 }
8107 {
8110 }
8113 {
8116 }
8118 maybe_swap:
8119 /* If this is a commutative operation, the changes to the operands
8120 may have made it noncanonical. */
8123 {
8127 }
8130 }
8131 \f
8132 /* Given M see if it is a value that would select a field of bits
8133 within an item, but not the entire word. Return -1 if not.
8134 Otherwise, return the starting position of the field, where 0 is the
8135 low-order bit.
8137 *PLEN is set to the length of the field. */
8139 static int
8141 {
8142 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8147 /* Now shift off the low-order zero bits and see if we have a
8148 power of two minus 1. */
8156 }
8157 \f
8158 /* If X refers to a register that equals REG in value, replace these
8159 references with REG. */
8160 static rtx
8162 {
8170 {
8206 {
8210 else
8212 }
8214 /* fall through */
8221 {
8224 {
8226 {
8229 }
8231 }
8232 }
8234 {
8237 {
8240 {
8242 {
8245 }
8247 }
8248 }
8249 }
8252 }
8255 }
8257 /* Return X converted to MODE. If the value is already truncated to
8258 MODE we can just return a subreg even though in the general case we
8259 would need an explicit truncation. */
8261 static rtx
8263 {
8268 {
8269 /* Bit-cast X into an integer mode. */
8274 }
8277 }
8279 /* See if X can be simplified knowing that we will only refer to it in
8280 MODE and will only refer to those bits that are nonzero in MASK.
8281 If other bits are being computed or if masking operations are done
8282 that select a superset of the bits in MASK, they can sometimes be
8283 ignored.
8285 Return a possibly simplified expression, but always convert X to
8286 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8288 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8289 are all off in X. This is used when X will be complemented, by either
8290 NOT, NEG, or XOR. */
8292 static rtx
8295 {
8298 machine_mode op_mode;
8302 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8303 code below will do the wrong thing since the mode of such an
8304 expression is VOIDmode.
8306 Also do nothing if X is a CLOBBER; this can happen if X was
8307 the return value from a call to gen_lowpart. */
8311 /* We want to perform the operation in its present mode unless we know
8312 that the operation is valid in MODE, in which case we do the operation
8313 in MODE. */
8318 /* It is not valid to do a right-shift in a narrower mode
8319 than the one it came in with. */
8324 /* Truncate MASK to fit OP_MODE. */
8328 /* When we have an arithmetic operation, or a shift whose count we
8329 do not know, we need to assume that all bits up to the highest-order
8330 bit in MASK will be needed. This is how we form such a mask. */
8333 else
8337 /* Determine what bits of X are guaranteed to be (non)zero. */
8340 /* If none of the bits in X are needed, return a zero. */
8344 /* If X is a CONST_INT, return a new one. Do this here since the
8345 test below will fail. */
8347 {
8350 else
8351 {
8354 }
8355 }
8357 /* If X is narrower than MODE and we want all the bits in X's mode, just
8358 get X in the proper mode. */
8363 /* We can ignore the effect of a SUBREG if it narrows the mode or
8364 if the constant masks to zero all the bits the mode doesn't have. */
8374 /* The arithmetic simplifications here only work for scalar integer modes. */
8379 {
8381 /* If X is a (clobber (const_int)), return it since we know we are
8382 generating something that won't match. */
8395 /* Similarly for a truncate. */
8399 /* If this is an AND with a constant, convert it into an AND
8400 whose constant is the AND of that constant with MASK. If it
8401 remains an AND of MASK, delete it since it is redundant. */
8404 {
8408 /* If X is still an AND, see if it is an AND with a mask that
8409 is just some low-order bits. If so, and it is MASK, we don't
8410 need it. */
8417 /* If it remains an AND, try making another AND with the bits
8418 in the mode mask that aren't in MASK turned on. If the
8419 constant in the AND is wide enough, this might make a
8420 cheaper constant. */
8425 {
8426 unsigned HOST_WIDE_INT cval
8429 rtx y;
8436 }
8439 }
8444 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8445 low-order bits (as in an alignment operation) and FOO is already
8446 aligned to that boundary, mask C1 to that boundary as well.
8447 This may eliminate that PLUS and, later, the AND. */
8449 {
8453 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8454 number, sign extend it. */
8467 }
8469 /* ... fall through ... */
8472 /* Substituting into the operands of a widening MULT is not likely to
8473 create RTL matching a machine insn. */
8483 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8484 most significant bit in MASK since carries from those bits will
8485 affect the bits we are interested in. */
8490 /* If X is (minus C Y) where C's least set bit is larger than any bit
8491 in the mask, then we may replace with (neg Y). */
8494 {
8498 }
8500 /* Similarly, if C contains every bit in the fuller_mask, then we may
8501 replace with (not Y). */
8504 {
8508 }
8515 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8516 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8517 operation which may be a bitfield extraction. Ensure that the
8518 constant we form is not wider than the mode of X. */
8530 {
8539 }
8541 binop:
8542 /* For most binary operations, just propagate into the operation and
8543 change the mode if we have an operation of that mode. */
8548 /* If we ended up truncating both operands, truncate the result of the
8549 operation instead. */
8552 {
8555 }
8565 /* For left shifts, do the same, but just for the first operand.
8566 However, we cannot do anything with shifts where we cannot
8567 guarantee that the counts are smaller than the size of the mode
8568 because such a count will have a different meaning in a
8569 wider mode. */
8579 /* If the shift count is a constant and we can do arithmetic in
8580 the mode of the shift, refine which bits we need. Otherwise, use the
8581 conservative form of the mask. */
8587 else
8599 /* Here we can only do something if the shift count is a constant,
8600 this shift constant is valid for the host, and we can do arithmetic
8601 in OP_MODE. */
8607 {
8611 /* Select the mask of the bits we need for the shift operand. */
8614 /* We can only change the mode of the shift if we can do arithmetic
8615 in the mode of the shift and INNER_MASK is no wider than the
8616 width of X's mode. */
8624 }
8626 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8627 shift and AND produces only copies of the sign bit (C2 is one less
8628 than a power of two), we can do this with just a shift. */
8632 /* The shift puts one of the sign bit copies in the least significant
8633 bit. */
8638 /* Number of bits left after the shift must be more than the mask
8639 needs. */
8642 /* Must be more sign bit copies than the mask needs. */
8652 /* If we are just looking for the sign bit, we don't need this shift at
8653 all, even if it has a variable count. */
8657 /* If this is a shift by a constant, get a mask that contains those bits
8658 that are not copies of the sign bit. We then have two cases: If
8659 MASK only includes those bits, this can be a logical shift, which may
8660 allow simplifications. If MASK is a single-bit field not within
8661 those bits, we are requesting a copy of the sign bit and hence can
8662 shift the sign bit to the appropriate location. */
8666 {
8669 /* If the considered data is wider than HOST_WIDE_INT, we can't
8670 represent a mask for all its bits in a single scalar.
8671 But we only care about the lower bits, so calculate these. */
8674 {
8677 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8678 is the number of bits a full-width mask would have set.
8679 We need only shift if these are fewer than nonzero can
8680 hold. If not, we must keep all bits set in nonzero. */
8685 + HOST_BITS_PER_WIDE_INT
8687 }
8688 else
8689 {
8692 }
8695 {
8700 }
8703 {
8704 x = simplify_shift_const
8710 }
8711 }
8713 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8714 even if the shift count isn't a constant. */
8719 shiftrt:
8721 /* If this is a zero- or sign-extension operation that just affects bits
8722 we don't care about, remove it. Be sure the call above returned
8723 something that is still a shift. */
8733 next_select);
8739 /* If the shift count is constant and we can do computations
8740 in the mode of X, compute where the bits we care about are.
8741 Otherwise, we can't do anything. Don't change the mode of
8742 the shift or propagate MODE into the shift, though. */
8745 {
8755 }
8759 /* If we just want the low-order bit, the NEG isn't needed since it
8760 won't change the low-order bit. */
8764 /* We need any bits less significant than the most significant bit in
8765 MASK since carries from those bits will affect the bits we are
8766 interested in. */
8771 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8772 same as the XOR case above. Ensure that the constant we form is not
8773 wider than the mode of X. */
8781 {
8790 }
8792 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8793 use the full mask inside the NOT. */
8796 unop:
8799 next_select));
8805 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8806 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8807 which is equal to STORE_FLAG_VALUE. */
8819 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8820 written in a narrower mode. We play it safe and do not do so. */
8836 }
8838 /* Ensure we return a value of the proper mode. */
8840 }
8841 \f
8842 /* Return nonzero if X is an expression that has one of two values depending on
8843 whether some other value is zero or nonzero. In that case, we return the
8844 value that is being tested, *PTRUE is set to the value if the rtx being
8845 returned has a nonzero value, and *PFALSE is set to the other alternative.
8847 If we return zero, we set *PTRUE and *PFALSE to X. */
8849 static rtx
8851 {
8857 /* If we are comparing a value against zero, we are done. */
8860 {
8864 }
8866 /* If this is a unary operation whose operand has one of two values, apply
8867 our opcode to compute those values. */
8870 {
8875 }
8877 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8878 make can't possibly match and would suppress other optimizations. */
8880 ;
8882 /* If this is a binary operation, see if either side has only one of two
8883 values. If either one does or if both do and they are conditional on
8884 the same value, compute the new true and false values. */
8886 {
8892 {
8893 /* If if_then_else_cond returned zero, then true/false are the
8894 same rtl. We must copy one of them to prevent invalid rtl
8895 sharing. */
8902 {
8907 }
8908 else
8909 {
8912 }
8915 }
8917 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8918 operands is zero when the other is nonzero, and vice-versa,
8919 and STORE_FLAG_VALUE is 1 or -1. */
8925 {
8942 {
8949 const_true_rtx);
8951 }
8952 }
8954 /* Similarly for MULT, AND and UMIN, except that for these the result
8955 is always zero. */
8959 {
8973 {
8976 }
8977 }
8978 }
8981 {
8982 /* If we have IF_THEN_ELSE already, extract the condition and
8983 canonicalize it if it is NE or EQ. */
8989 {
8992 }
8993 else
8995 }
8997 /* If X is a SUBREG, we can narrow both the true and false values
8998 if the inner expression, if there is a condition. */
9002 {
9008 {
9012 }
9013 }
9015 /* If X is a constant, this isn't special and will cause confusions
9016 if we treat it as such. Likewise if it is equivalent to a constant. */
9019 ;
9021 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9022 will be least confusing to the rest of the compiler. */
9024 {
9027 }
9029 /* If X is known to be either 0 or -1, those are the true and
9030 false values when testing X. */
9034 {
9037 }
9039 /* Likewise for 0 or a single bit. */
9042 {
9045 }
9047 /* Otherwise fail; show no condition with true and false values the same. */
9050 }
9051 \f
9052 /* Return the value of expression X given the fact that condition COND
9053 is known to be true when applied to REG as its first operand and VAL
9054 as its second. X is known to not be shared and so can be modified in
9055 place.
9057 We only handle the simplest cases, and specifically those cases that
9058 arise with IF_THEN_ELSE expressions. */
9060 static rtx
9062 {
9070 /* If either operand of the condition is a floating point value,
9071 then we have to avoid collapsing an EQ comparison. */
9081 /* If X is (abs REG) and we know something about REG's relationship
9082 with zero, we may be able to simplify this. */
9086 {
9095 }
9097 /* The only other cases we handle are MIN, MAX, and comparisons if the
9098 operands are the same as REG and VAL. */
9101 {
9103 {
9106 }
9109 {
9111 {
9119 else
9121 }
9124 {
9127 /* Do not reverse the condition when it is NE or EQ.
9128 This is because we cannot conclude anything about
9129 the value of 'SMAX (x, y)' when x is not equal to y,
9130 but we can when x equals y. */
9136 {
9147 }
9148 }
9149 }
9150 }
9152 {
9157 {
9158 /* We must simplify subreg here, before we lose track of the
9159 original inner_mode. */
9164 else
9166 }
9169 }
9170 /* We don't have to handle SIGN_EXTEND here, because even in the
9171 case of replacing something with a modeless CONST_INT, a
9172 CONST_INT is already (supposed to be) a valid sign extension for
9173 its narrower mode, which implies it's already properly
9174 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9175 story is different. */
9177 {
9182 {
9183 /* We must simplify the zero_extend here, before we lose
9184 track of the original inner_mode. */
9189 else
9191 }
9194 }
9198 {
9205 }
9208 }
9209 \f
9210 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9211 assignment as a field assignment. */
9213 static int
9215 {
9217 {
9222 /* For big endian, adjust the memory offset. */
9227 else
9229 }
9237 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9238 Note that all SUBREGs of MEM are paradoxical; otherwise they
9239 would have been rewritten. */
9252 /* We used to see if get_last_value of X and Y were the same but that's
9253 not correct. In one direction, we'll cause the assignment to have
9254 the wrong destination and in the case, we'll import a register into this
9255 insn that might have already have been dead. So fail if none of the
9256 above cases are true. */
9258 }
9259 \f
9260 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9261 Return that assignment if so.
9263 We only handle the most common cases. */
9265 static rtx
9267 {
9270 rtx assign;
9272 HOST_WIDE_INT c1;
9273 HOST_WIDE_INT pos;
9275 rtx other;
9276 machine_mode mode;
9278 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9279 a clear of a one-bit field. We will have changed it to
9280 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9281 for a SUBREG. */
9287 {
9293 }
9303 {
9310 }
9312 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9313 one-bit field. */
9317 {
9323 }
9325 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9326 SRC is an AND with all bits of that field set, then we can discard
9327 the AND. */
9332 {
9339 else
9342 /* Complete overlap. We can remove the source AND. */
9346 /* Partial overlap. We can reduce the source AND. */
9348 {
9353 }
9354 }
9356 /* The other case we handle is assignments into a constant-position
9357 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9358 a mask that has all one bits except for a group of zero bits and
9359 OTHER is known to have zeros where C1 has ones, this is such an
9360 assignment. Compute the position and length from C1. Shift OTHER
9361 to the appropriate position, force it to the required mode, and
9362 make the extraction. Check for the AND in both operands. */
9364 /* One or more SUBREGs might obscure the constant-position field
9365 assignment. The first one we are likely to encounter is an outer
9366 narrowing SUBREG, which we can just strip for the purposes of
9367 identifying the constant-field assignment. */
9381 /* The second SUBREG that might get in the way is a paradoxical
9382 SUBREG around the first operand of the AND. We want to
9383 pretend the operand is as wide as the destination here. We
9384 do this by adjusting the MEM to wider mode for the sole
9385 purpose of the call to rtx_equal_for_field_assignment_p. Also
9386 note this trick only works for MEMs. */
9398 /* The second SUBREG that might get in the way is a paradoxical
9399 SUBREG around the first operand of the AND. We want to
9400 pretend the operand is as wide as the destination here. We
9401 do this by adjusting the MEM to wider mode for the sole
9402 purpose of the call to rtx_equal_for_field_assignment_p. Also
9403 note this trick only works for MEMs. */
9411 else
9424 /* The mode to use for the source is the mode of the assignment, or of
9425 what is inside a possible STRICT_LOW_PART. */
9429 /* Shift OTHER right POS places and make it the source, restricting it
9430 to the proper length and mode. */
9435 dest);
9442 /* If SRC is masked by an AND that does not make a difference in
9443 the value being stored, strip it. */
9454 }
9455 \f
9456 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9457 if so. */
9459 static rtx
9461 {
9465 rtx tem;
9467 /* Distributivity is not true for floating point as it can change the
9468 value. So we don't do it unless -funsafe-math-optimizations. */
9473 /* The outer operation can only be one of the following: */
9481 /* If either operand is a primitive we can't do anything, so get out
9482 fast. */
9492 /* See if the inner and outer operations distribute. */
9494 {
9499 /* These all distribute except over PLUS. */
9510 /* This is also a multiply, so it distributes over everything. */
9513 /* This used to handle SUBREG, but this turned out to be counter-
9514 productive, since (subreg (op ...)) usually is not handled by
9515 insn patterns, and this "optimization" therefore transformed
9516 recognizable patterns into unrecognizable ones. Therefore the
9517 SUBREG case was removed from here.
9519 It is possible that distributing SUBREG over arithmetic operations
9520 leads to an intermediate result than can then be optimized further,
9521 e.g. by moving the outer SUBREG to the other side of a SET as done
9522 in simplify_set. This seems to have been the original intent of
9523 handling SUBREGs here.
9525 However, with current GCC this does not appear to actually happen,
9526 at least on major platforms. If some case is found where removing
9527 the SUBREG case here prevents follow-on optimizations, distributing
9528 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9532 }
9534 /* Set LHS and RHS to the inner operands (A and B in the example
9535 above) and set OTHER to the common operand (C in the example).
9536 There is only one way to do this unless the inner operation is
9537 commutative. */
9549 else
9552 /* Form the new inner operation, seeing if it simplifies first. */
9555 /* There is one exception to the general way of distributing:
9556 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9558 {
9561 }
9563 /* We may be able to continuing distributing the result, so call
9564 ourselves recursively on the inner operation before forming the
9565 outer operation, which we return. */
9568 }
9570 /* See if X is of the form (* (+ A B) C), and if so convert to
9571 (+ (* A C) (* B C)) and try to simplify.
9573 Most of the time, this results in no change. However, if some of
9574 the operands are the same or inverses of each other, simplifications
9575 will result.
9577 For example, (and (ior A B) (not B)) can occur as the result of
9578 expanding a bit field assignment. When we apply the distributive
9579 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9580 which then simplifies to (and (A (not B))).
9582 Note that no checks happen on the validity of applying the inverse
9583 distributive law. This is pointless since we can do it in the
9584 few places where this routine is called.
9586 N is the index of the term that is decomposed (the arithmetic operation,
9587 i.e. (+ A B) in the first example above). !N is the index of the term that
9588 is distributed, i.e. of C in the first example above. */
9589 static rtx
9591 {
9592 machine_mode mode;
9596 /* Distributivity is not true for floating point as it can change the
9597 value. So we don't do it unless -funsafe-math-optimizations. */
9614 /* Special case (and (xor B C) (not A)), which is equivalent to
9615 (xor (ior A B) (ior A C)) */
9617 {
9620 }
9623 {
9624 /* Distribute the second term. */
9627 }
9628 else
9629 {
9630 /* Distribute the first term. */
9633 }
9643 }
9644 \f
9645 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9646 in MODE. Return an equivalent form, if different from (and VAROP
9647 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9649 static rtx
9652 {
9655 rtx orig_varop;
9663 /* Simplify VAROP knowing that we will be only looking at some of the
9664 bits in it.
9666 Note by passing in CONSTOP, we guarantee that the bits not set in
9667 CONSTOP are not significant and will never be examined. We must
9668 ensure that is the case by explicitly masking out those bits
9669 before returning. */
9672 /* If VAROP is a CLOBBER, we will fail so return it. */
9676 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9677 to VAROP and return the new constant. */
9681 /* See what bits may be nonzero in VAROP. Unlike the general case of
9682 a call to nonzero_bits, here we don't care about bits outside
9683 MODE. */
9687 /* Turn off all bits in the constant that are known to already be zero.
9688 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9689 which is tested below. */
9693 /* If we don't have any bits left, return zero. */
9697 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9698 a power of two, we can replace this with an ASHIFT. */
9703 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9704 or XOR, then try to apply the distributive law. This may eliminate
9705 operations if either branch can be simplified because of the AND.
9706 It may also make some cases more complex, but those cases probably
9707 won't match a pattern either with or without this. */
9710 return
9711 gen_lowpart
9713 apply_distributive_law
9718 constop),
9722 constop))));
9724 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9725 the AND and see if one of the operands simplifies to zero. If so, we
9726 may eliminate it. */
9730 {
9739 }
9741 /* Make a SUBREG if necessary. If we can't make it, fail. */
9746 /* If we are only masking insignificant bits, return VAROP. */
9753 /* Otherwise, return an AND. */
9755 }
9758 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9759 in MODE.
9761 Return an equivalent form, if different from X. Otherwise, return X. If
9762 X is zero, we are to always construct the equivalent form. */
9764 static rtx
9767 {
9778 }
9779 \f
9780 /* Given a REG, X, compute which bits in X can be nonzero.
9781 We don't care about bits outside of those defined in MODE.
9783 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9784 a shift, AND, or zero_extract, we can do better. */
9786 static rtx
9788 const_rtx known_x ATTRIBUTE_UNUSED,
9789 machine_mode known_mode ATTRIBUTE_UNUSED,
9792 {
9793 rtx tem;
9796 /* If X is a register whose nonzero bits value is current, use it.
9797 Otherwise, if X is a register whose value we can find, use that
9798 value. Otherwise, use the previously-computed global nonzero bits
9799 for this register. */
9813 && !REGNO_REG_SET_P
9816 {
9820 /* We don't know anything about the upper bits. */
9825 }
9830 {
9836 }
9838 {
9842 /* We don't know anything about the upper bits. */
9846 }
9849 }
9851 /* Return the number of bits at the high-order end of X that are known to
9852 be equal to the sign bit. X will be used in mode MODE; if MODE is
9853 VOIDmode, X will be used in its own mode. The returned value will always
9854 be between 1 and the number of bits in MODE. */
9856 static rtx
9858 const_rtx known_x ATTRIBUTE_UNUSED,
9859 machine_mode known_mode
9860 ATTRIBUTE_UNUSED,
9863 {
9864 rtx tem;
9877 && !REGNO_REG_SET_P
9880 {
9883 }
9894 }
9895 \f
9896 /* Return the number of "extended" bits there are in X, when interpreted
9897 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9898 unsigned quantities, this is the number of high-order zero bits.
9899 For signed quantities, this is the number of copies of the sign bit
9900 minus 1. In both case, this function returns the number of "spare"
9901 bits. For example, if two quantities for which this function returns
9902 at least 1 are added, the addition is known not to overflow.
9904 This function will always return 0 unless called during combine, which
9905 implies that it must be called from a define_split. */
9907 unsigned int
9909 {
9919 }
9921 /* This function is called from `simplify_shift_const' to merge two
9922 outer operations. Specifically, we have already found that we need
9923 to perform operation *POP0 with constant *PCONST0 at the outermost
9924 position. We would now like to also perform OP1 with constant CONST1
9925 (with *POP0 being done last).
9927 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9928 the resulting operation. *PCOMP_P is set to 1 if we would need to
9929 complement the innermost operand, otherwise it is unchanged.
9931 MODE is the mode in which the operation will be done. No bits outside
9932 the width of this mode matter. It is assumed that the width of this mode
9933 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9935 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9936 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9937 result is simply *PCONST0.
9939 If the resulting operation cannot be expressed as one operation, we
9940 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9942 static int
9943 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9944 {
9951 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9955 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9956 if OP0 is SET. */
9965 {
9967 {
9985 }
9986 }
9988 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9992 /* If the two constants aren't the same, we can't do anything. The
9993 remaining six cases can all be done. */
9997 else
9999 {
10002 /* (a & b) | b == b */
10005 /* (a ^ b) | b == a | b */
10006 {;}
10011 /* (a & b) ^ b == (~a) & b */
10014 /* (a | b) ^ b == a & ~b */
10020 /* (a | b) & b == b */
10023 /* (a ^ b) & b) == (~a) & b */
10028 }
10030 /* Check for NO-OP cases. */
10043 /* ??? Slightly redundant with the above mask, but not entirely.
10044 Moving this above means we'd have to sign-extend the mode mask
10045 for the final test. */
10050 }
10051 \f
10052 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10053 the shift in. The original shift operation CODE is performed on OP in
10054 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10055 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10056 result of the shift is subject to operation OUTER_CODE with operand
10057 OUTER_CONST. */
10059 static machine_mode
10063 {
10068 /* In general we can't perform in wider mode for right shift and rotate. */
10070 {
10072 /* We can still widen if the bits brought in from the left are identical
10073 to the sign bit of ORIG_MODE. */
10081 /* Similarly here but with zero bits. */
10086 /* We can also widen if the bits brought in will be masked off. This
10087 operation is performed in ORIG_MODE. */
10089 {
10095 }
10096 /* fall through */
10106 }
10107 }
10109 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10110 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10111 if we cannot simplify it. Otherwise, return a simplified value.
10113 The shift is normally computed in the widest mode we find in VAROP, as
10114 long as it isn't a different number of words than RESULT_MODE. Exceptions
10115 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10117 static rtx
10120 {
10126 unsigned int mode_words
10128 /* We form (outer_op (code varop count) (outer_const)). */
10134 /* Make sure and truncate the "natural" shift on the way in. We don't
10135 want to do this inside the loop as it makes it more difficult to
10136 combine shifts. */
10140 /* If we were given an invalid count, don't do anything except exactly
10141 what was requested. */
10148 /* Unless one of the branches of the `if' in this loop does a `continue',
10149 we will `break' the loop after the `if'. */
10152 {
10153 /* If we have an operand of (clobber (const_int 0)), fail. */
10157 /* Convert ROTATERT to ROTATE. */
10159 {
10164 else
10166 }
10171 /* Handle cases where the count is greater than the size of the mode
10172 minus 1. For ASHIFT, use the size minus one as the count (this can
10173 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10174 take the count modulo the size. For other shifts, the result is
10175 zero.
10177 Since these shifts are being produced by the compiler by combining
10178 multiple operations, each of which are defined, we know what the
10179 result is supposed to be. */
10182 {
10187 else
10188 {
10189 /* We can't simply return zero because there may be an
10190 outer op. */
10194 }
10195 }
10197 /* If we discovered we had to complement VAROP, leave. Making a NOT
10198 here would cause an infinite loop. */
10202 /* An arithmetic right shift of a quantity known to be -1 or 0
10203 is a no-op. */
10207 {
10210 }
10212 /* If we are doing an arithmetic right shift and discarding all but
10213 the sign bit copies, this is equivalent to doing a shift by the
10214 bitsize minus one. Convert it into that shift because it will often
10215 allow other simplifications. */
10222 /* We simplify the tests below and elsewhere by converting
10223 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10224 `make_compound_operation' will convert it to an ASHIFTRT for
10225 those machines (such as VAX) that don't have an LSHIFTRT. */
10242 {
10249 {
10252 }
10256 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10257 minus the width of a smaller mode, we can do this with a
10258 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10265 {
10274 }
10278 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10279 the same number of words as what we've seen so far. Then store
10280 the widest mode in MODE. */
10286 == mode_words
10289 {
10294 }
10298 /* Some machines use MULT instead of ASHIFT because MULT
10299 is cheaper. But it is still better on those machines to
10300 merge two shifts into one. */
10303 {
10304 varop
10310 }
10314 /* Similar, for when divides are cheaper. */
10317 {
10318 varop
10324 }
10328 /* If we are extracting just the sign bit of an arithmetic
10329 right shift, that shift is not needed. However, the sign
10330 bit of a wider mode may be different from what would be
10331 interpreted as the sign bit in a narrower mode, so, if
10332 the result is narrower, don't discard the shift. */
10337 {
10340 }
10342 /* ... fall through ... */
10347 /* Here we have two nested shifts. The result is usually the
10348 AND of a new shift with a mask. We compute the result below. */
10355 {
10359 rtx mask_rtx;
10361 /* We have one common special case. We can't do any merging if
10362 the inner code is an ASHIFTRT of a smaller mode. However, if
10363 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10364 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10365 we can convert it to
10366 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10367 This simplifies certain SIGN_EXTEND operations. */
10371 {
10372 /* C3 has the low-order C1 bits zero. */
10384 }
10386 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10387 than C1 high-order bits equal to the sign bit, we can convert
10388 this to either an ASHIFT or an ASHIFTRT depending on the
10389 two counts.
10391 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10397 {
10401 {
10404 }
10407 }
10409 /* There are some cases we can't do. If CODE is ASHIFTRT,
10410 we can only do this if FIRST_CODE is also ASHIFTRT.
10412 We can't do the case when CODE is ROTATE and FIRST_CODE is
10413 ASHIFTRT.
10415 If the mode of this shift is not the mode of the outer shift,
10416 we can't do this if either shift is a right shift or ROTATE.
10418 Finally, we can't do any of these if the mode is too wide
10419 unless the codes are the same.
10421 Handle the case where the shift codes are the same
10422 first. */
10425 {
10434 }
10445 /* To compute the mask to apply after the shift, shift the
10446 nonzero bits of the inner shift the same way the
10447 outer shift will. */
10450 result_mode);
10452 mask_rtx
10456 /* Give up if we can't compute an outer operation to use. */
10464 /* If the shifts are in the same direction, we add the
10465 counts. Otherwise, we subtract them. */
10469 else
10472 /* If COUNT is positive, the new shift is usually CODE,
10473 except for the two exceptions below, in which case it is
10474 FIRST_CODE. If the count is negative, FIRST_CODE should
10475 always be used */
10485 }
10487 /* If we have (A << B << C) for any shift, we can convert this to
10488 (A << C << B). This wins if A is a constant. Only try this if
10489 B is not a constant. */
10494 {
10501 }
10508 /* Make this fit the case below. */
10515 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10516 with C the size of VAROP - 1 and the shift is logical if
10517 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10518 we have an (le X 0) operation. If we have an arithmetic shift
10519 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10520 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10528 {
10531 const0_rtx);
10537 }
10539 /* If we have (shift (logical)), move the logical to the outside
10540 to allow it to possibly combine with another logical and the
10541 shift to combine with another shift. This also canonicalizes to
10542 what a ZERO_EXTRACT looks like. Also, some machines have
10543 (and (shift)) insns. */
10546 /* We can't do this if we have (ashiftrt (xor)) and the
10547 constant has its sign bit set in shift_mode with shift_mode
10548 wider than result_mode. */
10552 shift_mode))
10560 {
10563 }
10565 /* If we can't do that, try to simplify the shift in each arm of the
10566 logical expression, make a new logical expression, and apply
10567 the inverse distributive law. This also can't be done for
10568 (ashiftrt (xor)) where we've widened the shift and the constant
10569 changes the sign bit. */
10574 shift_mode)))
10575 {
10587 }
10591 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10592 says that the sign bit can be tested, FOO has mode MODE, C is
10593 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10594 that may be nonzero. */
10604 {
10608 }
10612 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10613 than the number of bits in the mode is equivalent to A. */
10617 {
10621 }
10623 /* NEG commutes with ASHIFT since it is multiplication. Move the
10624 NEG outside to allow shifts to combine. */
10628 {
10631 }
10635 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10636 is one less than the number of bits in the mode is
10637 equivalent to (xor A 1). */
10644 {
10648 }
10650 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10651 that might be nonzero in BAR are those being shifted out and those
10652 bits are known zero in FOO, we can replace the PLUS with FOO.
10653 Similarly in the other operand order. This code occurs when
10654 we are computing the size of a variable-size array. */
10661 {
10664 }
10672 result_mode)))
10673 {
10676 }
10678 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10688 {
10691 }
10693 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10694 signbit', and attempt to change the PLUS to an XOR and move it to
10695 the outer operation as is done above in the AND/IOR/XOR case
10696 leg for shift(logical). See details in logical handling above
10697 for reasoning in doing so. */
10708 {
10711 }
10716 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10717 with C the size of VAROP - 1 and the shift is logical if
10718 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10719 we have a (gt X 0) operation. If the shift is arithmetic with
10720 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10721 we have a (neg (gt X 0)) operation. */
10730 {
10733 const0_rtx);
10739 }
10743 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10744 if the truncate does not affect the value. */
10751 {
10754 varop_inner
10757 GEN_INT
10762 }
10767 }
10770 }
10775 /* We have now finished analyzing the shift. The result should be
10776 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10777 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10778 to the result of the shift. OUTER_CONST is the relevant constant,
10779 but we must turn off all bits turned off in the shift. */
10787 /* Make a SUBREG if necessary. If we can't make it, fail. */
10792 /* If we have an outer operation and we just made a shift, it is
10793 possible that we could have simplified the shift were it not
10794 for the outer operation. So try to do the simplification
10795 recursively. */
10799 else
10805 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10806 turn off all the bits that the shift would have turned off. */
10811 /* Do the remainder of the processing in RESULT_MODE. */
10814 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10815 operation. */
10820 {
10828 {
10829 /* This means that we have determined that the result is
10830 equivalent to a constant. This should be rare. */
10833 }
10836 else
10839 }
10842 }
10844 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10845 The result of the shift is RESULT_MODE. If we cannot simplify it,
10846 return X or, if it is NULL, synthesize the expression with
10847 simplify_gen_binary. Otherwise, return a simplified value.
10849 The shift is normally computed in the widest mode we find in VAROP, as
10850 long as it isn't a different number of words than RESULT_MODE. Exceptions
10851 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10853 static rtx
10856 {
10866 }
10868 \f
10869 /* A subroutine of recog_for_combine. See there for arguments and
10870 return value. */
10872 static int
10874 {
10876 rtx pat_without_clobbers;
10884 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10885 we use to indicate that something didn't match. If we find such a
10886 thing, force rejection. */
10900 {
10903 else
10906 }
10908 /* If it isn't, there is the possibility that we previously had an insn
10909 that clobbered some register as a side effect, but the combined
10910 insn doesn't need to do that. So try once more without the clobbers
10911 unless this represents an ASM insn. */
10915 {
10920 {
10923 pos++;
10924 }
10934 {
10937 else
10940 }
10941 }
10948 /* Recognize all noop sets, these will be killed by followup pass. */
10952 /* If we had any clobbers to add, make a new pattern than contains
10953 them. Then check to make sure that all of them are dead. */
10955 {
10965 else
10972 {
10977 {
10981 }
10982 }
10984 }
10988 {
10995 /* Allow targets to reject combined insn. */
10997 {
11000 dump_file);
11002 /* Callers expect recog_for_combine to strip
11003 clobbers from the pattern on failure. */
11008 }
11013 }
11019 }
11021 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11022 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11023 Return whether anything was so changed. */
11025 static bool
11027 {
11032 {
11041 {
11049 }
11054 {
11057 }
11058 else
11063 mask--;
11069 }
11072 }
11074 /* Like recog, but we receive the address of a pointer to a new pattern.
11075 We try to match the rtx that the pointer points to.
11076 If that fails, we may try to modify or replace the pattern,
11077 storing the replacement into the same pointer object.
11079 Modifications include deletion or addition of CLOBBERs. If the
11080 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11081 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11082 (and undo if that fails).
11084 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11085 the CLOBBERs are placed.
11087 The value is the final insn code from the pattern ultimately matched,
11088 or -1. */
11090 static int
11092 {
11104 {
11107 {
11111 }
11112 }
11115 {
11120 }
11123 }
11124 \f
11125 /* Like gen_lowpart_general but for use by combine. In combine it
11126 is not possible to create any new pseudoregs. However, it is
11127 safe to create invalid memory addresses, because combine will
11128 try to recognize them and all they will do is make the combine
11129 attempt fail.
11131 If for some reason this cannot do its job, an rtx
11132 (clobber (const_int 0)) is returned.
11133 An insn containing that will not be recognized. */
11135 static rtx
11137 {
11141 rtx result;
11146 /* We can only support MODE being wider than a word if X is a
11147 constant integer or has a mode the same size. */
11152 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11153 won't know what to do. So we will strip off the SUBREG here and
11154 process normally. */
11156 {
11159 /* For use in case we fall down into the address adjustments
11160 further below, we need to adjust the known mode and size of
11161 x; imode and isize, since we just adjusted x. */
11168 }
11176 {
11179 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11180 address. */
11185 /* If we want to refer to something bigger than the original memref,
11186 generate a paradoxical subreg instead. That will force a reload
11187 of the original memref X. */
11194 /* Adjust the address so that the address-after-the-data is
11195 unchanged. */
11200 }
11202 /* If X is a comparison operator, rewrite it in a new mode. This
11203 probably won't match, but may allow further simplifications. */
11207 /* If we couldn't simplify X any other way, just enclose it in a
11208 SUBREG. Normally, this SUBREG won't match, but some patterns may
11209 include an explicit SUBREG or we may simplify it further in combine. */
11210 else
11211 {
11212 rtx res;
11215 {
11220 }
11224 }
11226 fail:
11228 }
11229 \f
11230 /* Try to simplify a comparison between OP0 and a constant OP1,
11231 where CODE is the comparison code that will be tested, into a
11232 (CODE OP0 const0_rtx) form.
11234 The result is a possibly different comparison code to use.
11235 *POP1 may be updated. */
11237 static enum rtx_code
11240 {
11244 /* Get the constant we are comparing against and turn off all bits
11245 not on in our mode. */
11249 /* If we are comparing against a constant power of two and the value
11250 being compared can only have that single bit nonzero (e.g., it was
11251 `and'ed with that bit), we can replace this with a comparison
11252 with zero. */
11260 {
11263 }
11265 /* Similarly, if we are comparing a value known to be either -1 or
11266 0 with -1, change it to the opposite comparison against zero. */
11271 {
11274 }
11276 /* Do some canonicalizations based on the comparison code. We prefer
11277 comparisons against zero and then prefer equality comparisons.
11278 If we can reduce the size of a constant, we will do that too. */
11280 {
11282 /* < C is equivalent to <= (C - 1) */
11284 {
11287 /* ... fall through to LE case below. */
11288 }
11289 else
11293 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11295 {
11298 }
11300 /* If we are doing a <= 0 comparison on a value known to have
11301 a zero sign bit, we can replace this with == 0. */
11311 /* >= C is equivalent to > (C - 1). */
11313 {
11316 /* ... fall through to GT below. */
11317 }
11318 else
11322 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11324 {
11327 }
11329 /* If we are doing a > 0 comparison on a value known to have
11330 a zero sign bit, we can replace this with != 0. */
11340 /* < C is equivalent to <= (C - 1). */
11342 {
11345 /* ... fall through ... */
11346 }
11347 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11351 {
11355 }
11356 else
11360 /* unsigned <= 0 is equivalent to == 0 */
11363 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11367 {
11370 }
11374 /* >= C is equivalent to > (C - 1). */
11376 {
11379 /* ... fall through ... */
11380 }
11382 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11386 {
11390 }
11391 else
11395 /* unsigned > 0 is equivalent to != 0 */
11398 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11402 {
11405 }
11410 }
11414 }
11415 \f
11416 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11417 comparison code that will be tested.
11419 The result is a possibly different comparison code to use. *POP0 and
11420 *POP1 may be updated.
11422 It is possible that we might detect that a comparison is either always
11423 true or always false. However, we do not perform general constant
11424 folding in combine, so this knowledge isn't useful. Such tautologies
11425 should have been detected earlier. Hence we ignore all such cases. */
11427 static enum rtx_code
11429 {
11436 /* Try a few ways of applying the same transformation to both operands. */
11438 {
11439 #if !WORD_REGISTER_OPERATIONS
11440 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11441 so check specially. */
11456 - (GET_MODE_PRECISION
11458 {
11461 }
11462 #endif
11464 /* If both operands are the same constant shift, see if we can ignore the
11465 shift. We can if the shift is a rotate or if the bits shifted out of
11466 this shift are known to be zero for both inputs and if the type of
11467 comparison is compatible with the shift. */
11480 {
11493 else
11495 }
11497 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11498 SUBREGs are of the same mode, and, in both cases, the AND would
11499 be redundant if the comparison was done in the narrower mode,
11500 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11501 and the operand's possibly nonzero bits are 0xffffff01; in that case
11502 if we only care about QImode, we don't need the AND). This case
11503 occurs if the output mode of an scc insn is not SImode and
11504 STORE_FLAG_VALUE == 1 (e.g., the 386).
11506 Similarly, check for a case where the AND's are ZERO_EXTEND
11507 operations from some narrower mode even though a SUBREG is not
11508 present. */
11513 {
11530 {
11534 /* The resulting comparison is always unsigned since we masked
11535 off the original sign bit. */
11539 }
11546 {
11552 }
11556 }
11558 /* If both operands are NOT, we can strip off the outer operation
11559 and adjust the comparison code for swapped operands; similarly for
11560 NEG, except that this must be an equality comparison. */
11566 else
11568 }
11570 /* If the first operand is a constant, swap the operands and adjust the
11571 comparison code appropriately, but don't do this if the second operand
11572 is already a constant integer. */
11574 {
11577 }
11579 /* We now enter a loop during which we will try to simplify the comparison.
11580 For the most part, we only are concerned with comparisons with zero,
11581 but some things may really be comparisons with zero but not start
11582 out looking that way. */
11585 {
11592 HOST_WIDE_INT const_op;
11594 /* We only want to handle integral modes. This catches VOIDmode,
11595 CCmode, and the floating-point modes. An exception is that we
11596 can handle VOIDmode if OP0 is a COMPARE or a comparison
11597 operation. */
11604 /* Try to simplify the compare to constant, possibly changing the
11605 comparison op, and/or changing op1 to zero. */
11609 /* Compute some predicates to simplify code below. */
11616 /* If this is a sign bit comparison and we can do arithmetic in
11617 MODE, say that we will only be needing the sign bit of OP0. */
11624 /* Now try cases based on the opcode of OP0. If none of the cases
11625 does a "continue", we exit this loop immediately after the
11626 switch. */
11629 {
11631 /* If we are extracting a single bit from a variable position in
11632 a constant that has only a single bit set and are comparing it
11633 with zero, we can convert this into an equality comparison
11634 between the position and the location of the single bit. */
11635 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11636 have already reduced the shift count modulo the word size. */
11642 {
11650 /* Result is nonzero iff shift count is equal to I. */
11653 }
11655 /* ... fall through ... */
11660 {
11663 }
11667 /* If testing for equality, we can take the NOT of the constant. */
11670 {
11674 }
11676 /* If just looking at the sign bit, reverse the sense of the
11677 comparison. */
11679 {
11683 }
11687 /* If testing for equality, we can take the NEG of the constant. */
11690 {
11694 }
11696 /* The remaining cases only apply to comparisons with zero. */
11700 /* When X is ABS or is known positive,
11701 (neg X) is < 0 if and only if X != 0. */
11709 {
11713 }
11715 /* If we have NEG of something whose two high-order bits are the
11716 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11718 {
11722 }
11726 /* If we are testing equality and our count is a constant, we
11727 can perform the inverse operation on our RHS. */
11731 {
11735 }
11737 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11738 a particular bit. Convert it to an AND of a constant of that
11739 bit. This will be converted into a ZERO_EXTRACT. */
11743 {
11750 }
11752 /* Fall through. */
11755 /* ABS is ignorable inside an equality comparison with zero. */
11757 {
11760 }
11764 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11765 (compare FOO CONST) if CONST fits in FOO's mode and we
11766 are either testing inequality or have an unsigned
11767 comparison with ZERO_EXTEND or a signed comparison with
11768 SIGN_EXTEND. But don't do it if we don't have a compare
11769 insn of the given mode, since we'd have to revert it
11770 later on, and then we wouldn't know whether to sign- or
11771 zero-extend. */
11774 && ! unsigned_comparison_p
11778 {
11781 }
11785 /* Check for the case where we are comparing A - C1 with C2, that is
11787 (subreg:MODE (plus (A) (-C1))) op (C2)
11789 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11790 comparison in the wider mode. One of the following two conditions
11791 must be true in order for this to be valid:
11793 1. The mode extension results in the same bit pattern being added
11794 on both sides and the comparison is equality or unsigned. As
11795 C2 has been truncated to fit in MODE, the pattern can only be
11796 all 0s or all 1s.
11798 2. The mode extension results in the sign bit being copied on
11799 each side.
11801 The difficulty here is that we have predicates for A but not for
11802 (A - C1) so we need to check that C1 is within proper bounds so
11803 as to perturbate A as little as possible. */
11810 {
11819 /* (A - C1) zero-extends if it is positive and sign-extends
11820 if it is negative, C2 both zero- and sign-extends. */
11824 /* (A - C1) sign-extends if it is positive and 1-extends
11825 if it is negative, C2 both sign- and 1-extends. */
11832 /* (A - C1) always sign-extends, like C2. */
11836 {
11839 }
11840 }
11842 /* If the inner mode is narrower and we are extracting the low part,
11843 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11847 else
11850 /* ... fall through ... */
11860 {
11863 }
11867 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11868 this for equality comparisons due to pathological cases involving
11869 overflows. */
11873 {
11877 }
11879 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11882 {
11886 }
11890 /* We used to optimize signed comparisons against zero, but that
11891 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11892 arrive here as equality comparisons, or (GEU, LTU) are
11893 optimized away. No need to special-case them. */
11895 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11896 (eq B (minus A C)), whichever simplifies. We can only do
11897 this for equality comparisons due to pathological cases involving
11898 overflows. */
11902 {
11906 }
11911 {
11915 }
11917 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11918 of bits in X minus 1, is one iff X > 0. */
11923 {
11927 }
11931 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11932 if C is zero or B is a constant. */
11936 {
11940 }
11948 /* We can't do anything if OP0 is a condition code value, rather
11949 than an actual data value. */
11955 /* Get the two operands being compared. */
11958 else
11961 /* Check for the cases where we simply want the result of the
11962 earlier test or the opposite of that result. */
11966 {
11970 else
11974 {
11979 }
11980 }
11984 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11985 iff X <= 0. */
11989 {
11993 }
11997 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11998 will be converted to a ZERO_EXTRACT later. */
12002 {
12007 }
12009 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12010 zero and X is a comparison and C1 and C2 describe only bits set
12011 in STORE_FLAG_VALUE, we can compare with X. */
12019 {
12026 {
12029 }
12030 }
12032 /* If we are doing an equality comparison of an AND of a bit equal
12033 to the sign bit, replace this with a LT or GE comparison of
12034 the underlying value. */
12041 {
12045 }
12047 /* If this AND operation is really a ZERO_EXTEND from a narrower
12048 mode, the constant fits within that mode, and this is either an
12049 equality or unsigned comparison, try to do this comparison in
12050 the narrower mode.
12052 Note that in:
12054 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12055 -> (ne:DI (reg:SI 4) (const_int 0))
12057 unless TRULY_NOOP_TRUNCATION allows it or the register is
12058 known to hold a value of the required mode the
12059 transformation is invalid. */
12067 {
12070 }
12072 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12073 fits in both M1 and M2 and the SUBREG is either paradoxical
12074 or represents the low part, permute the SUBREG and the AND
12075 and try again. */
12078 {
12081 /* Require an integral mode, to avoid creating something like
12082 (AND:SF ...). */
12084 /* It is unsafe to commute the AND into the SUBREG if the
12085 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12086 not defined. As originally written the upper bits
12087 have a defined value due to the AND operation.
12088 However, if we commute the AND inside the SUBREG then
12089 they no longer have defined values and the meaning of
12090 the code has been changed.
12091 Also C1 should not change value in the smaller mode,
12092 see PR67028 (a positive C1 can become negative in the
12093 smaller mode, so that the AND does no longer mask the
12094 upper bits). */
12095 && ((WORD_REGISTER_OPERATIONS
12107 {
12113 }
12114 }
12116 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12120 {
12125 }
12127 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12128 (eq (and (lshiftrt X) 1) 0).
12129 Also handle the case where (not X) is expressed using xor. */
12133 {
12145 {
12146 op0
12151 }
12152 }
12156 /* If we have (compare (ashift FOO N) (const_int C)) and
12157 the high order N bits of FOO (N+1 if an inequality comparison)
12158 are known to be zero, we can do this by comparing FOO with C
12159 shifted right N bits so long as the low-order N bits of C are
12160 zero. */
12172 {
12173 /* We must perform a logical shift, not an arithmetic one,
12174 as we want the top N bits of C to be zero. */
12181 }
12183 /* If we are doing a sign bit comparison, it means we are testing
12184 a particular bit. Convert it to the appropriate AND. */
12187 {
12194 }
12196 /* If this an equality comparison with zero and we are shifting
12197 the low bit to the sign bit, we can convert this to an AND of the
12198 low-order bit. */
12202 {
12205 }
12209 /* If this is an equality comparison with zero, we can do this
12210 as a logical shift, which might be much simpler. */
12213 {
12218 }
12220 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12221 do the comparison in a narrower mode. */
12231 {
12234 }
12236 /* Likewise if OP0 is a PLUS of a sign extension with a
12237 constant, which is usually represented with the PLUS
12238 between the shifts. */
12250 {
12258 new_const);
12260 }
12262 /* ... fall through ... */
12264 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12265 the low order N bits of FOO are known to be zero, we can do this
12266 by comparing FOO with C shifted left N bits so long as no
12267 overflow occurs. Even if the low order N bits of FOO aren't known
12268 to be zero, if the comparison is >= or < we can use the same
12269 optimization and for > or <= by setting all the low
12270 order N bits in the comparison constant. */
12281 {
12282 unsigned HOST_WIDE_INT low_bits
12287 {
12288 /* If the shift was logical, then we must make the condition
12289 unsigned. */
12297 const_op
12302 }
12303 }
12305 /* If we are using this shift to extract just the sign bit, we
12306 can replace this with an LT or GE comparison. */
12311 {
12315 }
12320 }
12323 }
12325 /* Now make any compound operations involved in this comparison. Then,
12326 check for an outmost SUBREG on OP0 that is not doing anything or is
12327 paradoxical. The latter transformation must only be performed when
12328 it is known that the "extra" bits will be the same in op0 and op1 or
12329 that they don't matter. There are three cases to consider:
12331 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12332 care bits and we can assume they have any convenient value. So
12333 making the transformation is safe.
12335 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12336 In this case the upper bits of op0 are undefined. We should not make
12337 the simplification in that case as we do not know the contents of
12338 those bits.
12340 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12341 UNKNOWN. In that case we know those bits are zeros or ones. We must
12342 also be sure that they are the same as the upper bits of op1.
12344 We can never remove a SUBREG for a non-equality comparison because
12345 the sign bit is in a different place in the underlying object. */
12354 {
12356 {
12357 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12358 implemented. */
12360 {
12363 }
12364 }
12370 {
12376 }
12377 }
12379 /* We now do the opposite procedure: Some machines don't have compare
12380 insns in all modes. If OP0's mode is an integer mode smaller than a
12381 word and we can't do a compare in that mode, see if there is a larger
12382 mode for which we can do the compare. There are a number of cases in
12383 which we can use the wider mode. */
12393 {
12396 /* If this is a test for negative, we can make an explicit
12397 test of the sign bit. Test this first so we can use
12398 a paradoxical subreg to extend OP0. */
12402 {
12403 unsigned HOST_WIDE_INT sign
12410 }
12412 /* If the only nonzero bits in OP0 and OP1 are those in the
12413 narrower mode and this is an equality or unsigned comparison,
12414 we can use the wider mode. Similarly for sign-extended
12415 values, in which case it is true for all comparisons. */
12432 {
12433 /* If OP0 is an AND and we don't have an AND in MODE either,
12434 make a new AND in the proper mode. */
12442 else
12443 {
12445 {
12448 }
12449 else
12450 {
12453 }
12455 }
12456 }
12457 }
12459 /* We may have changed the comparison operands. Re-canonicalize. */
12461 {
12464 }
12466 /* If this machine only supports a subset of valid comparisons, see if we
12467 can convert an unsupported one into a supported one. */
12474 }
12475 \f
12476 /* Utility function for record_value_for_reg. Count number of
12477 rtxs in X. */
12478 static int
12480 {
12487 {
12507 }
12518 }
12519 \f
12520 /* Utility function for following routine. Called when X is part of a value
12521 being stored into last_set_value. Sets last_set_table_tick
12522 for each register mentioned. Similar to mention_regs in cse.c */
12524 static void
12526 {
12532 {
12538 {
12541 }
12544 }
12548 {
12549 /* Check for identical subexpressions. If x contains
12550 identical subexpression we only have to traverse one of
12551 them. */
12553 {
12554 /* Note that at this point x1 has already been
12555 processed. */
12559 /* If x0 and x1 are identical then there is no need to
12560 process x0. */
12564 /* If x0 is identical to a subexpression of x1 then while
12565 processing x1, x0 has already been processed. Thus we
12566 are done with x. */
12571 /* If x1 is identical to a subexpression of x0 then we
12572 still have to process the rest of x0. */
12575 {
12578 }
12579 }
12582 }
12586 }
12588 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12589 are saying that the register is clobbered and we no longer know its
12590 value. If INSN is zero, don't update reg_stat[].last_set; this is
12591 only permitted with VALUE also zero and is used to invalidate the
12592 register. */
12594 static void
12596 {
12602 /* If VALUE contains REG and we have a previous value for REG, substitute
12603 the previous value. */
12605 {
12606 rtx tem;
12608 /* Set things up so get_last_value is allowed to see anything set up to
12609 our insn. */
12613 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12614 it isn't going to be useful and will take a lot of time to process,
12615 so just use the CLOBBER. */
12618 {
12624 {
12625 /* If there are two or more occurrences of REG in VALUE,
12626 prevent the value from growing too much. */
12629 }
12632 }
12633 }
12635 /* For each register modified, show we don't know its value, that
12636 we don't know about its bitwise content, that its value has been
12637 updated, and that we don't know the location of the death of the
12638 register. */
12640 {
12652 }
12654 /* Mark registers that are being referenced in this value. */
12658 /* Now update the status of each register being set.
12659 If someone is using this register in this block, set this register
12660 to invalid since we will get confused between the two lives in this
12661 basic block. This makes using this register always invalid. In cse, we
12662 scan the table to invalidate all entries using this register, but this
12663 is too much work for us. */
12666 {
12672 else
12674 }
12676 /* The value being assigned might refer to X (like in "x++;"). In that
12677 case, we must replace it with (clobber (const_int 0)) to prevent
12678 infinite loops. */
12681 {
12685 }
12687 /* For the main register being modified, update the value, the mode, the
12688 nonzero bits, and the number of sign bit copies. */
12693 {
12701 rsp->last_set_sign_bit_copies
12703 }
12704 }
12706 /* Called via note_stores from record_dead_and_set_regs to handle one
12707 SET or CLOBBER in an insn. DATA is the instruction in which the
12708 set is occurring. */
12710 static void
12712 {
12719 {
12723 }
12726 {
12727 /* If we are setting the whole register, we know its value. Otherwise
12728 show that we don't know the value. We can handle SUBREG in
12729 some cases. */
12740 else
12742 }
12744 /* Ignore pushes, they clobber nothing. */
12747 }
12749 /* Update the records of when each REG was most recently set or killed
12750 for the things done by INSN. This is the last thing done in processing
12751 INSN in the combiner loop.
12753 We update reg_stat[], in particular fields last_set, last_set_value,
12754 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12755 last_death, and also the similar information mem_last_set (which insn
12756 most recently modified memory) and last_call_luid (which insn was the
12757 most recent subroutine call). */
12759 static void
12761 {
12762 rtx link;
12766 {
12769 {
12774 {
12779 }
12780 }
12783 }
12786 {
12787 hard_reg_set_iterator hrsi;
12789 {
12801 }
12805 /* We can't combine into a call pattern. Remember, though, that
12806 the return value register is set at this LUID. We could
12807 still replace a register with the return value from the
12808 wrong subroutine call! */
12810 }
12811 else
12813 }
12815 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12816 register present in the SUBREG, so for each such SUBREG go back and
12817 adjust nonzero and sign bit information of the registers that are
12818 known to have some zero/sign bits set.
12820 This is needed because when combine blows the SUBREGs away, the
12821 information on zero/sign bits is lost and further combines can be
12822 missed because of that. */
12824 static void
12826 {
12828 rtx set;
12836 {
12845 {
12848 }
12852 {
12855 }
12858 {
12861 }
12862 else
12864 }
12865 }
12867 /* Check if X, a register, is known to contain a value already
12868 truncated to MODE. In this case we can use a subreg to refer to
12869 the truncated value even though in the generic case we would need
12870 an explicit truncation. */
12872 static bool
12874 {
12886 }
12888 /* If X is a hard reg or a subreg record the mode that the register is
12889 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12890 to turn a truncate into a subreg using this information. Return true
12891 if traversing X is complete. */
12893 static bool
12895 {
12896 machine_mode truncated_mode;
12900 {
12911 }
12912 /* ??? For hard-regs we now record everything. We might be able to
12913 optimize this using last_set_mode. */
12916 else
12924 {
12927 }
12930 }
12932 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12933 the modes they are used in. This can help truning TRUNCATEs into
12934 SUBREGs. */
12936 static void
12938 {
12943 }
12945 /* Scan X for promoted SUBREGs. For each one found,
12946 note what it implies to the registers used in it. */
12948 static void
12950 {
12955 else
12956 {
12962 {
12972 }
12973 }
12974 }
12975 \f
12976 /* Verify that all the registers and memory references mentioned in *LOC are
12977 still valid. *LOC was part of a value set in INSN when label_tick was
12978 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12979 the invalid references with (clobber (const_int 0)) and return 1. This
12980 replacement is useful because we often can get useful information about
12981 the form of a value (e.g., if it was produced by a shift that always
12982 produces -1 or 0) even though we don't know exactly what registers it
12983 was produced from. */
12985 static int
12987 {
12994 {
13000 {
13003 /* If this is a pseudo-register that was only set once and not
13004 live at the beginning of the function, it is always valid. */
13008 && (!REGNO_REG_SET_P
13010 regno)))
13012 {
13016 }
13017 }
13020 }
13021 /* If this is a memory reference, make sure that there were no stores after
13022 it that might have clobbered the value. We don't have alias info, so we
13023 assume any store invalidates it. Moreover, we only have local UIDs, so
13024 we also assume that there were stores in the intervening basic blocks. */
13027 {
13031 }
13034 {
13036 {
13037 /* Check for identical subexpressions. If x contains
13038 identical subexpression we only have to traverse one of
13039 them. */
13041 {
13042 /* Note that at this point x0 has already been checked
13043 and found valid. */
13047 /* If x0 and x1 are identical then x is also valid. */
13051 /* If x1 is identical to a subexpression of x0 then
13052 while checking x0, x1 has already been checked. Thus
13053 it is valid and so as x. */
13058 /* If x0 is identical to a subexpression of x1 then x is
13059 valid iff the rest of x1 is valid. */
13062 return
13066 }
13071 }
13077 }
13079 /* If we haven't found a reason for it to be invalid, it is valid. */
13081 }
13083 /* Get the last value assigned to X, if known. Some registers
13084 in the value may be replaced with (clobber (const_int 0)) if their value
13085 is known longer known reliably. */
13087 static rtx
13089 {
13091 rtx value;
13094 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13095 then convert it to the desired mode. If this is a paradoxical SUBREG,
13096 we cannot predict what values the "extra" bits might have. */
13110 /* If we don't have a value, or if it isn't for this basic block and
13111 it's either a hard register, set more than once, or it's a live
13112 at the beginning of the function, return 0.
13114 Because if it's not live at the beginning of the function then the reg
13115 is always set before being used (is never used without being set).
13116 And, if it's set only once, and it's always set before use, then all
13117 uses must have the same last value, even if it's not from this basic
13118 block. */
13125 || REGNO_REG_SET_P
13129 /* If the value was set in a later insn than the ones we are processing,
13130 we can't use it even if the register was only set once. */
13135 /* If the value has all its registers valid, return it. */
13139 /* Otherwise, make a copy and replace any invalid register with
13140 (clobber (const_int 0)). If that fails for some reason, return 0. */
13147 }
13148 \f
13149 /* Return nonzero if expression X refers to a REG or to memory
13150 that is set in an instruction more recent than FROM_LUID. */
13152 static int
13154 {
13160 {
13164 #ifdef PUSH_ROUNDING
13165 /* Don't allow uses of the stack pointer to be moved,
13166 because we don't know whether the move crosses a push insn. */
13169 #endif
13171 {
13177 }
13179 }
13187 {
13189 {
13194 }
13198 }
13200 }
13201 \f
13202 /* Define three variables used for communication between the following
13203 routines. */
13208 /* Function called via note_stores from reg_dead_at_p.
13210 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13211 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13213 static void
13215 {
13225 }
13227 /* Return nonzero if REG is known to be dead at INSN.
13229 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13230 referencing REG, it is dead. If we hit a SET referencing REG, it is
13231 live. Otherwise, see if it is live or dead at the start of the basic
13232 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13233 must be assumed to be always live. */
13235 static int
13237 {
13238 basic_block block;
13241 /* Set variables for reg_dead_at_p_1. */
13247 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13248 we allow the machine description to decide whether use-and-clobber
13249 patterns are OK. */
13251 {
13255 }
13257 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13258 beginning of basic block. */
13261 {
13263 {
13273 }
13279 }
13281 /* Look at live-in sets for the basic block that we were in. */
13287 }
13288 \f
13289 /* Note hard registers in X that are used. */
13291 static void
13293 {
13299 {
13303 CASE_CONST_ANY:
13308 /* CC0 must die in the insn after it is set, so we don't need to take
13309 special note of it here. */
13314 /* If we are clobbering a MEM, mark any hard registers inside the
13315 address as used. */
13322 /* A hard reg in a wide mode may really be multiple registers.
13323 If so, mark all of them just like the first. */
13325 {
13326 /* None of this applies to the stack, frame or arg pointers. */
13328 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13336 }
13340 {
13341 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13342 the address. */
13354 }
13359 }
13361 /* Recursively scan the operands of this expression. */
13363 {
13367 {
13371 {
13376 }
13377 }
13378 }
13379 }
13380 \f
13381 /* Remove register number REGNO from the dead registers list of INSN.
13383 Return the note used to record the death, if there was one. */
13385 rtx
13387 {
13394 }
13396 /* For each register (hardware or pseudo) used within expression X, if its
13397 death is in an instruction with luid between FROM_LUID (inclusive) and
13398 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13399 list headed by PNOTES.
13401 That said, don't move registers killed by maybe_kill_insn.
13403 This is done when X is being merged by combination into TO_INSN. These
13404 notes will then be distributed as needed. */
13406 static void
13409 {
13415 {
13419 /* Don't move the register if it gets killed in between from and to. */
13428 {
13431 /* It is possible for the call above to return 0. This can occur
13432 when last_death points to I2 or I1 that we combined with.
13433 In that case make a new note.
13435 We must also check for the case where X is a hard register
13436 and NOTE is a death note for a range of hard registers
13437 including X. In that case, we must put REG_DEAD notes for
13438 the remaining registers in place of NOTE. */
13443 {
13452 }
13454 /* If we didn't find any note, or if we found a REG_DEAD note that
13455 covers only part of the given reg, and we have a multi-reg hard
13456 register, then to be safe we must check for REG_DEAD notes
13457 for each register other than the first. They could have
13458 their own REG_DEAD notes lying around. */
13465 {
13472 else
13478 }
13481 {
13484 }
13485 else
13487 }
13490 }
13493 {
13498 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13499 that accesses one word of a multi-word item, some
13500 piece of everything register in the expression is used by
13501 this insn, so remove any old death. */
13502 /* ??? So why do we test for equality of the sizes? */
13511 {
13514 }
13516 /* If this is some other SUBREG, we know it replaces the entire
13517 value, so use that as the destination. */
13521 /* If this is a MEM, adjust deaths of anything used in the address.
13522 For a REG (the only other possibility), the entire value is
13523 being replaced so the old value is not used in this insn. */
13529 }
13538 {
13540 {
13545 }
13548 }
13549 }
13550 \f
13551 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13552 pattern of an insn. X must be a REG. */
13554 static int
13556 {
13560 {
13562 rtx target;
13569 else
13586 }
13594 }
13595 \f
13596 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13597 as appropriate. I3 and I2 are the insns resulting from the combination
13598 insns including FROM (I2 may be zero).
13600 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13601 not need REG_DEAD notes because they are being substituted for. This
13602 saves searching in the most common cases.
13604 Each note in the list is either ignored or placed on some insns, depending
13605 on the type of note. */
13607 static void
13610 {
13612 rtx tem_note;
13616 {
13621 {
13624 /* Doesn't matter much where we put this, as long as it's somewhere.
13625 It is preferable to keep these notes on branches, which is most
13626 likely to be i3. */
13633 else
13634 {
13637 }
13641 /* These notes must remain with the call or trapping instruction. */
13646 else
13647 {
13653 /* ??? Otherwise assume we've combined things such that we
13654 can now prove that the instructions can't trap. Drop the
13655 note in this case. */
13656 }
13660 /* ??? How to distribute between i3-i1. Assume i3 contains the
13661 entire adjustment. Assert i3 contains at least some adjust. */
13663 {
13665 /* fixup_args_size_notes looks at REG_NORETURN note,
13666 so ensure the note is placed there first. */
13668 {
13672 {
13678 }
13679 }
13681 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13682 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13685 && !ACCUMULATE_OUTGOING_ARGS
13687 }
13694 /* These notes must remain with the call. It should not be
13695 possible for both I2 and I3 to be a call. */
13698 else
13699 {
13702 }
13706 /* Any clobbers for i3 may still exist, and so we must process
13707 REG_UNUSED notes from that insn.
13709 Any clobbers from i2 or i1 can only exist if they were added by
13710 recog_for_combine. In that case, recog_for_combine created the
13711 necessary REG_UNUSED notes. Trying to keep any original
13712 REG_UNUSED notes from these insns can cause incorrect output
13713 if it is for the same register as the original i3 dest.
13714 In that case, we will notice that the register is set in i3,
13715 and then add a REG_UNUSED note for the destination of i3, which
13716 is wrong. However, it is possible to have REG_UNUSED notes from
13717 i2 or i1 for register which were both used and clobbered, so
13718 we keep notes from i2 or i1 if they will turn into REG_DEAD
13719 notes. */
13721 /* If this register is set or clobbered in I3, put the note there
13722 unless there is one already. */
13724 {
13732 }
13733 /* Otherwise, if this register is used by I3, then this register
13734 now dies here, so we must put a REG_DEAD note here unless there
13735 is one already. */
13741 {
13744 }
13750 /* These notes say something about results of an insn. We can
13751 only support them if they used to be on I3 in which case they
13752 remain on I3. Otherwise they are ignored.
13754 If the note refers to an expression that is not a constant, we
13755 must also ignore the note since we cannot tell whether the
13756 equivalence is still true. It might be possible to do
13757 slightly better than this (we only have a problem if I2DEST
13758 or I1DEST is present in the expression), but it doesn't
13759 seem worth the trouble. */
13767 /* These notes say something about how a register is used. They must
13768 be present on any use of the register in I2 or I3. */
13773 {
13776 else
13778 }
13783 /* This can show up in several ways -- either directly in the
13784 pattern, or hidden off in the constant pool with (or without?)
13785 a REG_EQUAL note. */
13786 /* ??? Ignore the without-reg_equal-note problem for now. */
13798 {
13801 else
13803 }
13805 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13806 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13807 there. */
13812 {
13819 }
13825 {
13833 }
13837 /* This note says something about the value of a register prior
13838 to the execution of an insn. It is too much trouble to see
13839 if the note is still correct in all situations. It is better
13840 to simply delete it. */
13844 /* If we replaced the right hand side of FROM_INSN with a
13845 REG_EQUAL note, the original use of the dying register
13846 will not have been combined into I3 and I2. In such cases,
13847 FROM_INSN is guaranteed to be the first of the combined
13848 instructions, so we simply need to search back before
13849 FROM_INSN for the previous use or set of this register,
13850 then alter the notes there appropriately.
13852 If the register is used as an input in I3, it dies there.
13853 Similarly for I2, if it is nonzero and adjacent to I3.
13855 If the register is not used as an input in either I3 or I2
13856 and it is not one of the registers we were supposed to eliminate,
13857 there are two possibilities. We might have a non-adjacent I2
13858 or we might have somehow eliminated an additional register
13859 from a computation. For example, we might have had A & B where
13860 we discover that B will always be zero. In this case we will
13861 eliminate the reference to A.
13863 In both cases, we must search to see if we can find a previous
13864 use of A and put the death note there. */
13870 else
13871 {
13882 && !(i2mod
13884 i2mod_old_rhs)))
13889 /* If the new I2 sets the same register that is marked dead
13890 in the note, the note now should not be put on I2, as the
13891 note refers to a previous incarnation of the reg. */
13894 }
13897 {
13901 {
13903 {
13907 }
13909 /* If the register is being set at TEM_INSN, see if that is all
13910 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13911 into a REG_UNUSED note instead. Don't delete sets to
13912 global register vars. */
13916 {
13927 ;
13929 /* Verify that it was the set, and not a clobber that
13930 modified the register.
13932 CC0 targets must be careful to maintain setter/user
13933 pairs. If we cannot delete the setter due to side
13934 effects, mark the user with an UNUSED note instead
13935 of deleting it. */
13939 && (!HAVE_cc0
13943 {
13944 /* Move the notes and links of TEM_INSN elsewhere.
13945 This might delete other dead insns recursively.
13946 First set the pattern to something that won't use
13947 any register. */
13961 /* Delete the setter too. */
13963 {
13976 }
13977 }
13978 else
13979 {
13982 /* If there isn't already a REG_UNUSED note, put one
13983 here. Do not place a REG_DEAD note, even if
13984 the register is also used here; that would not
13985 match the algorithm used in lifetime analysis
13986 and can cause the consistency check in the
13987 scheduler to fail. */
13992 }
13993 }
13997 {
14000 /* If we are doing a 3->2 combination, and we have a
14001 register which formerly died in i3 and was not used
14002 by i2, which now no longer dies in i3 and is used in
14003 i2 but does not die in i2, and place is between i2
14004 and i3, then we may need to move a link from place to
14005 i2. */
14007 && from_insn
14010 {
14014 }
14016 }
14020 }
14022 }
14024 /* If the register is set or already dead at PLACE, we needn't do
14025 anything with this note if it is still a REG_DEAD note.
14026 We check here if it is set at all, not if is it totally replaced,
14027 which is what `dead_or_set_p' checks, so also check for it being
14028 set partially. */
14031 {
14037 {
14038 /* Unless the register previously died in PLACE, clear
14039 last_death. [I no longer understand why this is
14040 being done.] */
14044 }
14045 else
14048 /* If this is a death note for a hard reg that is occupying
14049 multiple registers, ensure that we are still using all
14050 parts of the object. If we find a piece of the object
14051 that is unused, we must arrange for an appropriate REG_DEAD
14052 note to be added for it. However, we can't just emit a USE
14053 and tag the note to it, since the register might actually
14054 be dead; so we recourse, and the recursive call then finds
14055 the previous insn that used this register. */
14058 {
14067 {
14070 }
14073 {
14074 /* Put only REG_DEAD notes for pieces that are
14075 not already dead or set. */
14079 {
14086 {
14088 NULL_RTX);
14092 NULL_RTX);
14093 }
14098 {
14100 {
14104 }
14108 {
14111 }
14112 }
14113 }
14116 }
14117 }
14118 }
14122 /* Any other notes should not be present at this point in the
14123 compilation. */
14125 }
14128 {
14131 }
14135 }
14136 }
14137 \f
14138 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14139 I3, I2, and I1 to new locations. This is also called to add a link
14140 pointing at I3 when I3's destination is changed. */
14142 static void
14144 {
14148 {
14155 /* If the insn that this link points to is a NOTE, ignore it. */
14164 {
14167 {
14183 }
14186 }
14187 else
14197 /* A LOG_LINK is defined as being placed on the first insn that uses
14198 a register and points to the insn that sets the register. Start
14199 searching at the next insn after the target of the link and stop
14200 when we reach a set of the register or the end of the basic block.
14202 Note that this correctly handles the link that used to point from
14203 I3 to I2. Also note that not much searching is typically done here
14204 since most links don't point very far away. */
14213 {
14217 }
14220 {
14223 }
14227 /* If we found a place to put the link, place it there unless there
14228 is already a link to the same insn as LINK at that point. */
14231 {
14239 {
14243 /* Set added_links_insn to the earliest insn we added a
14244 link to. */
14248 }
14249 }
14250 }
14251 }
14252 \f
14253 /* Check for any register or memory mentioned in EQUIV that is not
14254 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14255 of EXPR where some registers may have been replaced by constants. */
14257 static bool
14259 {
14262 {
14267 }
14269 }
14270 \f
14271 DEBUG_FUNCTION void
14273 {
14274 fprintf
14276 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14278 }
14280 void
14282 {
14283 fprintf
14285 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14287 }
14288 \f
14289 /* Try combining insns through substitution. */
14290 static unsigned int
14292 {
14302 rebuild_jump_labels_after_combine
14305 /* Combining insns may have turned an indirect jump into a
14306 direct jump. Rebuild the JUMP_LABEL fields of jumping
14307 instructions. */
14309 {
14314 }
14318 }
14323 {
14333 };
14336 {
14340 {}
14342 /* opt_pass methods: */
14345 {
14347 }
14353 rtl_opt_pass *
14355 {
14357 }