| blob | c4f0b9dea0e7f3e04eff33a4b6699b0b76f3f86c |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
64 enum upper_128bits_state
65 {
67 unused,
68 used
69 };
72 {
73 /* State of the upper 128bits of AVX registers at exit. */
75 /* TRUE if state of the upper 128bits of AVX registers is unchanged
76 in this block. */
78 /* TRUE if block has been processed. */
80 /* TRUE if block has been scanned. */
82 /* Previous state of the upper 128bits of AVX registers at entry. */
86 #define BLOCK_INFO(B) ((block_info) (B)->aux)
88 enum call_avx256_state
89 {
90 /* Callee returns 256bit AVX register. */
92 /* Callee returns and passes 256bit AVX register. */
93 callee_return_pass_avx256,
94 /* Callee passes 256bit AVX register. */
95 callee_pass_avx256,
96 /* Callee doesn't return nor passe 256bit AVX register, or no
97 256bit AVX register in function return. */
98 call_no_avx256,
99 /* vzeroupper intrinsic. */
100 vzeroupper_intrinsic
101 };
103 /* Check if a 256bit AVX register is referenced in stores. */
105 static void
107 {
113 {
117 }
118 }
120 /* Helper function for move_or_delete_vzeroupper_1. Look for vzeroupper
121 in basic block BB. Delete it if upper 128bit AVX registers are
122 unused. If it isn't deleted, move it to just before a jump insn.
124 STATE is state of the upper 128bits of AVX registers at entry. */
126 static void
129 {
132 rtx pat;
137 {
144 }
147 {
152 }
162 /* BB_END changes when it is deleted. */
166 {
172 /* Move vzeroupper before jump/call. */
174 {
179 {
181 {
186 }
189 }
192 }
196 /* Check insn for vzeroupper intrinsic. */
199 {
201 {
202 /* Found vzeroupper intrinsic. */
205 }
206 }
207 else
208 {
209 /* Check insn for vzeroall intrinsic. */
213 {
217 /* Delete pending vzeroupper insertion. */
219 {
222 }
223 }
225 {
229 }
231 }
233 /* Process vzeroupper intrinsic. */
237 {
238 /* Since the upper 128bits are cleared, callee must not pass
239 256bit AVX register. We only need to check if callee
240 returns 256bit AVX register. */
242 {
245 }
247 /* Remove unnecessary vzeroupper since upper 128bits are
248 cleared. */
250 {
253 }
255 }
256 else
257 {
258 /* Set state to UNUSED if callee doesn't return 256bit AVX
259 register. */
265 {
266 /* Must remove vzeroupper since callee passes in 256bit
267 AVX register. */
269 {
272 }
274 }
275 else
276 {
279 }
280 }
281 }
290 state);
291 }
293 /* Helper function for move_or_delete_vzeroupper. Process vzeroupper
294 in BLOCK and check its predecessor blocks. Treat UNKNOWN state
295 as USED if UNKNOWN_IS_UNUSED is true. Return TRUE if the exit
296 state is changed. */
298 static bool
300 {
301 edge e;
302 edge_iterator ei;
315 /* Check all predecessor edges of this block. */
318 {
322 {
331 }
332 }
337 done:
345 /* Need to rescan if the upper 128bits of AVX registers are changed
346 to USED at exit. */
348 {
352 }
353 else
355 }
357 /* Go through the instruction stream looking for vzeroupper. Delete
358 it if upper 128bit AVX registers are unused. If it isn't deleted,
359 move it to just before a jump insn. */
361 static void
363 {
364 edge e;
365 edge_iterator ei;
366 basic_block bb;
373 /* Set up block info for each basic block. */
376 /* Process outgoing edges of entry point. */
381 {
386 }
388 /* Compute reverse completion order of depth first search of the CFG
389 so that the data-flow runs faster. */
404 /* Don't check outgoing edges of entry point. */
409 else
410 {
413 }
419 {
432 {
437 {
438 edge_iterator ei;
444 {
450 {
452 {
453 /* Send E->DEST to next round. */
458 }
459 }
461 {
462 /* Add E->DEST to current round. */
466 }
467 }
468 }
469 }
473 }
489 }
493 #ifndef CHECK_STACK_LIMIT
494 #define CHECK_STACK_LIMIT (-1)
495 #endif
497 /* Return index of given mode in mult and division cost tables. */
498 #define MODE_INDEX(mode) \
499 ((mode) == QImode ? 0 \
500 : (mode) == HImode ? 1 \
501 : (mode) == SImode ? 2 \
502 : (mode) == DImode ? 3 \
503 : 4)
505 /* Processor costs (relative to an add) */
506 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
507 #define COSTS_N_BYTES(N) ((N) * 2)
509 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
511 const
534 in QImode, HImode and SImode.
535 Relative to reg-reg move (2). */
539 in SFmode, DFmode and XFmode */
541 in SFmode, DFmode and XFmode */
544 in SImode and DImode */
546 in SImode and DImode */
549 in SImode, DImode and TImode */
551 in SImode, DImode and TImode */
579 };
581 /* Processor costs (relative to an add) */
582 static const
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
610 in SFmode, DFmode and XFmode */
612 in SFmode, DFmode and XFmode */
615 in SImode and DImode */
617 in SImode and DImode */
620 in SImode, DImode and TImode */
622 in SImode, DImode and TImode */
636 DUMMY_STRINGOP_ALGS},
638 DUMMY_STRINGOP_ALGS},
650 };
652 static const
675 in QImode, HImode and SImode.
676 Relative to reg-reg move (2). */
680 in SFmode, DFmode and XFmode */
682 in SFmode, DFmode and XFmode */
685 in SImode and DImode */
687 in SImode and DImode */
690 in SImode, DImode and TImode */
692 in SImode, DImode and TImode */
695 shared for code and data, so 4kB is
696 not really precise. */
708 DUMMY_STRINGOP_ALGS},
710 DUMMY_STRINGOP_ALGS},
722 };
724 static const
747 in QImode, HImode and SImode.
748 Relative to reg-reg move (2). */
752 in SFmode, DFmode and XFmode */
754 in SFmode, DFmode and XFmode */
757 in SImode and DImode */
759 in SImode and DImode */
762 in SImode, DImode and TImode */
764 in SImode, DImode and TImode */
778 DUMMY_STRINGOP_ALGS},
780 DUMMY_STRINGOP_ALGS},
792 };
794 static const
817 in QImode, HImode and SImode.
818 Relative to reg-reg move (2). */
822 in SFmode, DFmode and XFmode */
824 in SFmode, DFmode and XFmode */
827 in SImode and DImode */
829 in SImode and DImode */
832 in SImode, DImode and TImode */
834 in SImode, DImode and TImode */
847 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
848 (we ensure the alignment). For small blocks inline loop is still a
849 noticeable win, for bigger blocks either rep movsl or rep movsb is
850 way to go. Rep movsb has apparently more expensive startup time in CPU,
851 but after 4K the difference is down in the noise. */
854 DUMMY_STRINGOP_ALGS},
857 DUMMY_STRINGOP_ALGS},
869 };
871 static const
894 in QImode, HImode and SImode.
895 Relative to reg-reg move (2). */
899 in SFmode, DFmode and XFmode */
901 in SFmode, DFmode and XFmode */
905 in SImode and DImode */
907 in SImode and DImode */
910 in SImode, DImode and TImode */
912 in SImode, DImode and TImode */
926 DUMMY_STRINGOP_ALGS},
928 DUMMY_STRINGOP_ALGS},
940 };
942 static const
965 in QImode, HImode and SImode.
966 Relative to reg-reg move (2). */
970 in SFmode, DFmode and XFmode */
972 in SFmode, DFmode and XFmode */
975 in SImode and DImode */
977 in SImode and DImode */
980 in SImode, DImode and TImode */
982 in SImode, DImode and TImode */
986 have integrated l2 cache, but
987 optimizing for k6 is not important
988 enough to worry about that. */
999 DUMMY_STRINGOP_ALGS},
1001 DUMMY_STRINGOP_ALGS},
1013 };
1015 static const
1038 in QImode, HImode and SImode.
1039 Relative to reg-reg move (2). */
1043 in SFmode, DFmode and XFmode */
1045 in SFmode, DFmode and XFmode */
1048 in SImode and DImode */
1050 in SImode and DImode */
1053 in SImode, DImode and TImode */
1055 in SImode, DImode and TImode */
1068 /* For some reason, Athlon deals better with REP prefix (relative to loops)
1069 compared to K8. Alignment becomes important after 8 bytes for memcpy and
1070 128 bytes for memset. */
1072 DUMMY_STRINGOP_ALGS},
1074 DUMMY_STRINGOP_ALGS},
1086 };
1088 static const
1111 in QImode, HImode and SImode.
1112 Relative to reg-reg move (2). */
1116 in SFmode, DFmode and XFmode */
1118 in SFmode, DFmode and XFmode */
1121 in SImode and DImode */
1123 in SImode and DImode */
1126 in SImode, DImode and TImode */
1128 in SImode, DImode and TImode */
1133 /* New AMD processors never drop prefetches; if they cannot be performed
1134 immediately, they are queued. We set number of simultaneous prefetches
1135 to a large constant to reflect this (it probably is not a good idea not
1136 to limit number of prefetches at all, as their execution also takes some
1137 time). */
1146 /* K8 has optimized REP instruction for medium sized blocks, but for very
1147 small blocks it is better to use loop. For large blocks, libcall can
1148 do nontemporary accesses and beat inline considerably. */
1165 };
1189 in QImode, HImode and SImode.
1190 Relative to reg-reg move (2). */
1194 in SFmode, DFmode and XFmode */
1196 in SFmode, DFmode and XFmode */
1199 in SImode and DImode */
1201 in SImode and DImode */
1204 in SImode, DImode and TImode */
1206 in SImode, DImode and TImode */
1208 /* On K8:
1209 MOVD reg64, xmmreg Double FSTORE 4
1210 MOVD reg32, xmmreg Double FSTORE 4
1211 On AMDFAM10:
1212 MOVD reg64, xmmreg Double FADD 3
1213 1/1 1/1
1214 MOVD reg32, xmmreg Double FADD 3
1215 1/1 1/1 */
1219 /* New AMD processors never drop prefetches; if they cannot be performed
1220 immediately, they are queued. We set number of simultaneous prefetches
1221 to a large constant to reflect this (it probably is not a good idea not
1222 to limit number of prefetches at all, as their execution also takes some
1223 time). */
1233 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
1234 very small blocks it is better to use loop. For large blocks, libcall can
1235 do nontemporary accesses and beat inline considerably. */
1252 };
1276 in QImode, HImode and SImode.
1277 Relative to reg-reg move (2). */
1281 in SFmode, DFmode and XFmode */
1283 in SFmode, DFmode and XFmode */
1286 in SImode and DImode */
1288 in SImode and DImode */
1291 in SImode, DImode and TImode */
1293 in SImode, DImode and TImode */
1295 /* On K8:
1296 MOVD reg64, xmmreg Double FSTORE 4
1297 MOVD reg32, xmmreg Double FSTORE 4
1298 On AMDFAM10:
1299 MOVD reg64, xmmreg Double FADD 3
1300 1/1 1/1
1301 MOVD reg32, xmmreg Double FADD 3
1302 1/1 1/1 */
1306 /* New AMD processors never drop prefetches; if they cannot be performed
1307 immediately, they are queued. We set number of simultaneous prefetches
1308 to a large constant to reflect this (it probably is not a good idea not
1309 to limit number of prefetches at all, as their execution also takes some
1310 time). */
1320 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
1321 very small blocks it is better to use loop. For large blocks, libcall
1322 can do nontemporary accesses and beat inline considerably. */
1339 };
1363 in QImode, HImode and SImode.
1364 Relative to reg-reg move (2). */
1368 in SFmode, DFmode and XFmode */
1370 in SFmode, DFmode and XFmode */
1373 in SImode and DImode */
1375 in SImode and DImode */
1378 in SImode, DImode and TImode */
1380 in SImode, DImode and TImode */
1382 /* On K8:
1383 MOVD reg64, xmmreg Double FSTORE 4
1384 MOVD reg32, xmmreg Double FSTORE 4
1385 On AMDFAM10:
1386 MOVD reg64, xmmreg Double FADD 3
1387 1/1 1/1
1388 MOVD reg32, xmmreg Double FADD 3
1389 1/1 1/1 */
1402 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1403 very small blocks it is better to use loop. For large blocks, libcall can
1404 do nontemporary accesses and beat inline considerably. */
1421 };
1423 static const
1446 in QImode, HImode and SImode.
1447 Relative to reg-reg move (2). */
1451 in SFmode, DFmode and XFmode */
1453 in SFmode, DFmode and XFmode */
1456 in SImode and DImode */
1458 in SImode and DImode */
1461 in SImode, DImode and TImode */
1463 in SImode, DImode and TImode */
1477 DUMMY_STRINGOP_ALGS},
1480 DUMMY_STRINGOP_ALGS},
1492 };
1494 static const
1517 in QImode, HImode and SImode.
1518 Relative to reg-reg move (2). */
1522 in SFmode, DFmode and XFmode */
1524 in SFmode, DFmode and XFmode */
1527 in SImode and DImode */
1529 in SImode and DImode */
1532 in SImode, DImode and TImode */
1534 in SImode, DImode and TImode */
1565 };
1567 static const
1590 in QImode, HImode and SImode.
1591 Relative to reg-reg move (2). */
1595 in SFmode, DFmode and XFmode */
1597 in SFmode, DFmode and XFmode */
1600 in SImode and DImode */
1602 in SImode and DImode */
1605 in SImode, DImode and TImode */
1607 in SImode, DImode and TImode */
1638 };
1640 /* Generic64 should produce code tuned for Nocona and K8. */
1641 static const
1644 /* On all chips taken into consideration lea is 2 cycles and more. With
1645 this cost however our current implementation of synth_mult results in
1646 use of unnecessary temporary registers causing regression on several
1647 SPECfp benchmarks. */
1668 in QImode, HImode and SImode.
1669 Relative to reg-reg move (2). */
1673 in SFmode, DFmode and XFmode */
1675 in SFmode, DFmode and XFmode */
1678 in SImode and DImode */
1680 in SImode and DImode */
1683 in SImode, DImode and TImode */
1685 in SImode, DImode and TImode */
1691 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1692 value is increased to perhaps more appropriate value of 5. */
1715 };
1717 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1718 Athlon and K8. */
1719 static const
1742 in QImode, HImode and SImode.
1743 Relative to reg-reg move (2). */
1747 in SFmode, DFmode and XFmode */
1749 in SFmode, DFmode and XFmode */
1752 in SImode and DImode */
1754 in SImode and DImode */
1757 in SImode, DImode and TImode */
1759 in SImode, DImode and TImode */
1773 DUMMY_STRINGOP_ALGS},
1775 DUMMY_STRINGOP_ALGS},
1787 };
1791 /* Processor feature/optimization bitmasks. */
1792 #define m_386 (1<<PROCESSOR_I386)
1793 #define m_486 (1<<PROCESSOR_I486)
1794 #define m_PENT (1<<PROCESSOR_PENTIUM)
1795 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1796 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1797 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1798 #define m_CORE2_32 (1<<PROCESSOR_CORE2_32)
1799 #define m_CORE2_64 (1<<PROCESSOR_CORE2_64)
1800 #define m_COREI7_32 (1<<PROCESSOR_COREI7_32)
1801 #define m_COREI7_64 (1<<PROCESSOR_COREI7_64)
1802 #define m_COREI7 (m_COREI7_32 | m_COREI7_64)
1803 #define m_CORE2I7_32 (m_CORE2_32 | m_COREI7_32)
1804 #define m_CORE2I7_64 (m_CORE2_64 | m_COREI7_64)
1805 #define m_CORE2I7 (m_CORE2I7_32 | m_CORE2I7_64)
1806 #define m_ATOM (1<<PROCESSOR_ATOM)
1808 #define m_GEODE (1<<PROCESSOR_GEODE)
1809 #define m_K6 (1<<PROCESSOR_K6)
1810 #define m_K6_GEODE (m_K6 | m_GEODE)
1811 #define m_K8 (1<<PROCESSOR_K8)
1812 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1813 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1814 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1815 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1816 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1817 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1 | m_BTVER1)
1819 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1820 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1822 /* Generic instruction choice should be common subset of supported CPUs
1823 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1824 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1826 /* Feature tests against the various tunings. */
1829 /* Feature tests against the various tunings used to create ix86_tune_features
1830 based on the processor mask. */
1832 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1833 negatively, so enabling for Generic64 seems like good code size
1834 tradeoff. We can't enable it for 32bit generic because it does not
1835 work well with PPro base chips. */
1838 /* X86_TUNE_PUSH_MEMORY */
1842 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1845 /* X86_TUNE_UNROLL_STRLEN */
1849 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1853 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1854 on simulation result. But after P4 was made, no performance benefit
1855 was observed with branch hints. It also increases the code size.
1856 As a result, icc never generates branch hints. */
1859 /* X86_TUNE_DOUBLE_WITH_ADD */
1862 /* X86_TUNE_USE_SAHF */
1866 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1867 partial dependencies. */
1871 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1872 register stalls on Generic32 compilation setting as well. However
1873 in current implementation the partial register stalls are not eliminated
1874 very well - they can be introduced via subregs synthesized by combine
1875 and can happen in caller/callee saving sequences. Because this option
1876 pays back little on PPro based chips and is in conflict with partial reg
1877 dependencies used by Athlon/P4 based chips, it is better to leave it off
1878 for generic32 for now. */
1879 m_PPRO,
1881 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1884 /* X86_TUNE_USE_HIMODE_FIOP */
1887 /* X86_TUNE_USE_SIMODE_FIOP */
1890 /* X86_TUNE_USE_MOV0 */
1891 m_K6,
1893 /* X86_TUNE_USE_CLTD */
1896 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1897 m_PENT4,
1899 /* X86_TUNE_SPLIT_LONG_MOVES */
1900 m_PPRO,
1902 /* X86_TUNE_READ_MODIFY_WRITE */
1905 /* X86_TUNE_READ_MODIFY */
1908 /* X86_TUNE_PROMOTE_QIMODE */
1912 /* X86_TUNE_FAST_PREFIX */
1915 /* X86_TUNE_SINGLE_STRINGOP */
1918 /* X86_TUNE_QIMODE_MATH */
1921 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1922 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1923 might be considered for Generic32 if our scheme for avoiding partial
1924 stalls was more effective. */
1927 /* X86_TUNE_PROMOTE_QI_REGS */
1930 /* X86_TUNE_PROMOTE_HI_REGS */
1931 m_PPRO,
1933 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1934 over esp addition. */
1937 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1938 over esp addition. */
1939 m_PENT,
1941 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1942 over esp subtraction. */
1945 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1946 over esp subtraction. */
1949 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1950 for DFmode copies */
1954 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1957 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1958 conflict here in between PPro/Pentium4 based chips that thread 128bit
1959 SSE registers as single units versus K8 based chips that divide SSE
1960 registers to two 64bit halves. This knob promotes all store destinations
1961 to be 128bit to allow register renaming on 128bit SSE units, but usually
1962 results in one extra microop on 64bit SSE units. Experimental results
1963 shows that disabling this option on P4 brings over 20% SPECfp regression,
1964 while enabling it on K8 brings roughly 2.4% regression that can be partly
1965 masked by careful scheduling of moves. */
1969 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1972 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1975 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1976 m_BDVER1,
1978 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1979 are resolved on SSE register parts instead of whole registers, so we may
1980 maintain just lower part of scalar values in proper format leaving the
1981 upper part undefined. */
1982 m_ATHLON_K8,
1984 /* X86_TUNE_SSE_TYPELESS_STORES */
1985 m_AMD_MULTIPLE,
1987 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1990 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1993 /* X86_TUNE_PROLOGUE_USING_MOVE */
1996 /* X86_TUNE_EPILOGUE_USING_MOVE */
1999 /* X86_TUNE_SHIFT1 */
2002 /* X86_TUNE_USE_FFREEP */
2003 m_AMD_MULTIPLE,
2005 /* X86_TUNE_INTER_UNIT_MOVES */
2008 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
2011 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
2012 than 4 branch instructions in the 16 byte window. */
2016 /* X86_TUNE_SCHEDULE */
2020 /* X86_TUNE_USE_BT */
2023 /* X86_TUNE_USE_INCDEC */
2026 /* X86_TUNE_PAD_RETURNS */
2029 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
2030 m_ATOM,
2032 /* X86_TUNE_EXT_80387_CONSTANTS */
2036 /* X86_TUNE_SHORTEN_X87_SSE */
2039 /* X86_TUNE_AVOID_VECTOR_DECODE */
2042 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
2043 and SImode multiply, but 386 and 486 do HImode multiply faster. */
2046 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
2047 vector path on AMD machines. */
2050 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
2051 machines. */
2054 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
2055 than a MOV. */
2056 m_PENT,
2058 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
2059 but one byte longer. */
2060 m_PENT,
2062 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
2063 operand that cannot be represented using a modRM byte. The XOR
2064 replacement is long decoded, so this split helps here as well. */
2065 m_K6,
2067 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
2068 from FP to FP. */
2071 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
2072 from integer to FP. */
2073 m_AMDFAM10,
2075 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
2076 with a subsequent conditional jump instruction into a single
2077 compare-and-branch uop. */
2078 m_BDVER1,
2080 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2081 will impact LEA instruction selection. */
2082 m_ATOM,
2084 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2085 instructions. */
2088 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2089 at -O3. For the moment, the prefetching seems badly tuned for Intel
2090 chips. */
2091 m_K6_GEODE | m_AMD_MULTIPLE
2092 };
2094 /* Feature tests against the various architecture variations. */
2097 /* Feature tests against the various architecture variations, used to create
2098 ix86_arch_features based on the processor mask. */
2100 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
2103 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2106 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2109 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2112 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2114 };
2116 static const unsigned int x86_accumulate_outgoing_args
2120 static const unsigned int x86_arch_always_fancy_math_387
2124 /* In case the average insn count for single function invocation is
2125 lower than this constant, emit fast (but longer) prologue and
2126 epilogue code. */
2127 #define FAST_PROLOGUE_INSN_COUNT 20
2129 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2134 /* Array of the smallest class containing reg number REGNO, indexed by
2135 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2138 {
2139 /* ax, dx, cx, bx */
2141 /* si, di, bp, sp */
2143 /* FP registers */
2146 /* arg pointer */
2147 NON_Q_REGS,
2148 /* flags, fpsr, fpcr, frame */
2150 /* SSE registers */
2153 /* MMX registers */
2156 /* REX registers */
2159 /* SSE REX registers */
2162 };
2164 /* The "default" register map used in 32bit mode. */
2167 {
2175 };
2177 /* The "default" register map used in 64bit mode. */
2180 {
2188 };
2190 /* Define the register numbers to be used in Dwarf debugging information.
2191 The SVR4 reference port C compiler uses the following register numbers
2192 in its Dwarf output code:
2193 0 for %eax (gcc regno = 0)
2194 1 for %ecx (gcc regno = 2)
2195 2 for %edx (gcc regno = 1)
2196 3 for %ebx (gcc regno = 3)
2197 4 for %esp (gcc regno = 7)
2198 5 for %ebp (gcc regno = 6)
2199 6 for %esi (gcc regno = 4)
2200 7 for %edi (gcc regno = 5)
2201 The following three DWARF register numbers are never generated by
2202 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2203 believes these numbers have these meanings.
2204 8 for %eip (no gcc equivalent)
2205 9 for %eflags (gcc regno = 17)
2206 10 for %trapno (no gcc equivalent)
2207 It is not at all clear how we should number the FP stack registers
2208 for the x86 architecture. If the version of SDB on x86/svr4 were
2209 a bit less brain dead with respect to floating-point then we would
2210 have a precedent to follow with respect to DWARF register numbers
2211 for x86 FP registers, but the SDB on x86/svr4 is so completely
2212 broken with respect to FP registers that it is hardly worth thinking
2213 of it as something to strive for compatibility with.
2214 The version of x86/svr4 SDB I have at the moment does (partially)
2215 seem to believe that DWARF register number 11 is associated with
2216 the x86 register %st(0), but that's about all. Higher DWARF
2217 register numbers don't seem to be associated with anything in
2218 particular, and even for DWARF regno 11, SDB only seems to under-
2219 stand that it should say that a variable lives in %st(0) (when
2220 asked via an `=' command) if we said it was in DWARF regno 11,
2221 but SDB still prints garbage when asked for the value of the
2222 variable in question (via a `/' command).
2223 (Also note that the labels SDB prints for various FP stack regs
2224 when doing an `x' command are all wrong.)
2225 Note that these problems generally don't affect the native SVR4
2226 C compiler because it doesn't allow the use of -O with -g and
2227 because when it is *not* optimizing, it allocates a memory
2228 location for each floating-point variable, and the memory
2229 location is what gets described in the DWARF AT_location
2230 attribute for the variable in question.
2231 Regardless of the severe mental illness of the x86/svr4 SDB, we
2232 do something sensible here and we use the following DWARF
2233 register numbers. Note that these are all stack-top-relative
2234 numbers.
2235 11 for %st(0) (gcc regno = 8)
2236 12 for %st(1) (gcc regno = 9)
2237 13 for %st(2) (gcc regno = 10)
2238 14 for %st(3) (gcc regno = 11)
2239 15 for %st(4) (gcc regno = 12)
2240 16 for %st(5) (gcc regno = 13)
2241 17 for %st(6) (gcc regno = 14)
2242 18 for %st(7) (gcc regno = 15)
2243 */
2245 {
2253 };
2255 /* Define parameter passing and return registers. */
2258 {
2260 };
2263 {
2265 };
2268 {
2270 };
2272 /* Define the structure for the machine field in struct function. */
2277 rtx rtl;
2279 };
2281 /* Structure describing stack frame layout.
2282 Stack grows downward:
2284 [arguments]
2285 <- ARG_POINTER
2286 saved pc
2288 saved static chain if ix86_static_chain_on_stack
2290 saved frame pointer if frame_pointer_needed
2291 <- HARD_FRAME_POINTER
2292 [saved regs]
2293 <- regs_save_offset
2294 [padding0]
2296 [saved SSE regs]
2297 <- sse_regs_save_offset
2298 [padding1] |
2299 | <- FRAME_POINTER
2300 [va_arg registers] |
2301 |
2302 [frame] |
2303 |
2304 [padding2] | = to_allocate
2305 <- STACK_POINTER
2306 */
2307 struct ix86_frame
2308 {
2314 HOST_WIDE_INT frame;
2316 /* The offsets relative to ARG_POINTER. */
2317 HOST_WIDE_INT frame_pointer_offset;
2318 HOST_WIDE_INT hard_frame_pointer_offset;
2319 HOST_WIDE_INT stack_pointer_offset;
2320 HOST_WIDE_INT hfp_save_offset;
2321 HOST_WIDE_INT reg_save_offset;
2322 HOST_WIDE_INT sse_reg_save_offset;
2324 /* When save_regs_using_mov is set, emit prologue using
2325 move instead of push instructions. */
2327 };
2329 /* Which cpu are we scheduling for. */
2332 /* Which cpu are we optimizing for. */
2335 /* Which instruction set architecture to use. */
2338 /* true if sse prefetch instruction is not NOOP. */
2341 /* -mstackrealign option */
2356 /* Preferred alignment for stack boundary in bits. */
2359 /* Alignment for incoming stack boundary in bits specified at
2360 command line. */
2363 /* Default alignment for incoming stack boundary in bits. */
2366 /* Alignment for incoming stack boundary in bits. */
2369 /* Calling abi specific va_list type nodes. */
2373 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2377 /* Fence to use after loop using movnt. */
2378 tree x86_mfence;
2380 /* Register class used for passing given 64bit part of the argument.
2381 These represent classes as documented by the PS ABI, with the exception
2382 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2383 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2385 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2386 whenever possible (upper half does contain padding). */
2387 enum x86_64_reg_class
2388 {
2389 X86_64_NO_CLASS,
2390 X86_64_INTEGER_CLASS,
2391 X86_64_INTEGERSI_CLASS,
2392 X86_64_SSE_CLASS,
2393 X86_64_SSESF_CLASS,
2394 X86_64_SSEDF_CLASS,
2395 X86_64_SSEUP_CLASS,
2396 X86_64_X87_CLASS,
2397 X86_64_X87UP_CLASS,
2398 X86_64_COMPLEX_X87_CLASS,
2399 X86_64_MEMORY_CLASS
2400 };
2402 #define MAX_CLASSES 4
2404 /* Table of constants used by fldpi, fldln2, etc.... */
2408 \f
2413 const_tree);
2426 enum ix86_function_specific_strings
2427 {
2428 IX86_FUNCTION_SPECIFIC_ARCH,
2429 IX86_FUNCTION_SPECIFIC_TUNE,
2430 IX86_FUNCTION_SPECIFIC_MAX
2431 };
2449 \f
2450 #ifndef SUBTARGET32_DEFAULT_CPU
2452 #endif
2454 /* The svr4 ABI for the i386 says that records and unions are returned
2455 in memory. */
2456 #ifndef DEFAULT_PCC_STRUCT_RETURN
2457 #define DEFAULT_PCC_STRUCT_RETURN 1
2458 #endif
2460 /* Whether -mtune= or -march= were specified */
2464 /* Define a set of ISAs which are available when a given ISA is
2465 enabled. MMX and SSE ISAs are handled separately. */
2467 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
2468 #define OPTION_MASK_ISA_3DNOW_SET \
2469 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
2471 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
2472 #define OPTION_MASK_ISA_SSE2_SET \
2473 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
2474 #define OPTION_MASK_ISA_SSE3_SET \
2475 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
2476 #define OPTION_MASK_ISA_SSSE3_SET \
2477 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
2478 #define OPTION_MASK_ISA_SSE4_1_SET \
2479 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
2480 #define OPTION_MASK_ISA_SSE4_2_SET \
2481 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
2482 #define OPTION_MASK_ISA_AVX_SET \
2483 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
2484 #define OPTION_MASK_ISA_FMA_SET \
2485 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
2487 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
2488 as -msse4.2. */
2489 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
2491 #define OPTION_MASK_ISA_SSE4A_SET \
2492 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
2493 #define OPTION_MASK_ISA_FMA4_SET \
2494 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
2495 | OPTION_MASK_ISA_AVX_SET)
2496 #define OPTION_MASK_ISA_XOP_SET \
2497 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
2498 #define OPTION_MASK_ISA_LWP_SET \
2499 OPTION_MASK_ISA_LWP
2501 /* AES and PCLMUL need SSE2 because they use xmm registers */
2502 #define OPTION_MASK_ISA_AES_SET \
2503 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
2504 #define OPTION_MASK_ISA_PCLMUL_SET \
2505 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
2507 #define OPTION_MASK_ISA_ABM_SET \
2508 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
2510 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
2511 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
2512 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
2513 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
2514 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
2515 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
2516 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
2518 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
2519 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
2520 #define OPTION_MASK_ISA_F16C_SET \
2521 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
2523 /* Define a set of ISAs which aren't available when a given ISA is
2524 disabled. MMX and SSE ISAs are handled separately. */
2526 #define OPTION_MASK_ISA_MMX_UNSET \
2527 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
2528 #define OPTION_MASK_ISA_3DNOW_UNSET \
2529 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
2530 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
2532 #define OPTION_MASK_ISA_SSE_UNSET \
2533 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
2534 #define OPTION_MASK_ISA_SSE2_UNSET \
2535 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
2536 #define OPTION_MASK_ISA_SSE3_UNSET \
2537 (OPTION_MASK_ISA_SSE3 \
2538 | OPTION_MASK_ISA_SSSE3_UNSET \
2539 | OPTION_MASK_ISA_SSE4A_UNSET )
2540 #define OPTION_MASK_ISA_SSSE3_UNSET \
2541 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2542 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2543 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2544 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2545 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2546 #define OPTION_MASK_ISA_AVX_UNSET \
2547 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2548 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET)
2549 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2551 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2552 as -mno-sse4.1. */
2553 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2555 #define OPTION_MASK_ISA_SSE4A_UNSET \
2556 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2558 #define OPTION_MASK_ISA_FMA4_UNSET \
2559 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2560 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2561 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2563 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2564 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2565 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2566 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
2567 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
2568 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2569 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2570 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2571 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2572 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2574 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
2575 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
2576 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
2578 /* Vectorization library interface and handlers. */
2584 /* Processor target table, indexed by processor number */
2585 struct ptt
2586 {
2593 };
2596 {
2607 /* Core 2 32-bit. */
2609 /* Core 2 64-bit. */
2611 /* Core i7 32-bit. */
2613 /* Core i7 64-bit. */
2621 };
2624 {
2649 "btver1"
2650 };
2651 \f
2652 /* Return true if a red-zone is in use. */
2656 {
2658 }
2660 /* Implement TARGET_HANDLE_OPTION. */
2662 static bool
2666 location_t loc)
2667 {
2672 {
2675 {
2678 }
2679 else
2680 {
2683 }
2688 {
2691 }
2692 else
2693 {
2696 }
2704 {
2707 }
2708 else
2709 {
2712 }
2717 {
2720 }
2721 else
2722 {
2725 }
2730 {
2733 }
2734 else
2735 {
2738 }
2743 {
2746 }
2747 else
2748 {
2751 }
2756 {
2759 }
2760 else
2761 {
2764 }
2769 {
2772 }
2773 else
2774 {
2777 }
2782 {
2785 }
2786 else
2787 {
2790 }
2795 {
2798 }
2799 else
2800 {
2803 }
2818 {
2821 }
2822 else
2823 {
2826 }
2831 {
2834 }
2835 else
2836 {
2839 }
2844 {
2847 }
2848 else
2849 {
2852 }
2857 {
2860 }
2861 else
2862 {
2865 }
2870 {
2873 }
2874 else
2875 {
2878 }
2883 {
2886 }
2887 else
2888 {
2891 }
2896 {
2899 }
2900 else
2901 {
2904 }
2909 {
2912 }
2913 else
2914 {
2917 }
2922 {
2925 }
2926 else
2927 {
2930 }
2935 {
2938 }
2939 else
2940 {
2943 }
2948 {
2951 }
2952 else
2953 {
2956 }
2961 {
2964 }
2965 else
2966 {
2969 }
2974 {
2977 }
2978 else
2979 {
2982 }
2987 {
2990 }
2991 else
2992 {
2995 }
3000 {
3003 }
3004 else
3005 {
3008 }
3013 {
3016 }
3017 else
3018 {
3021 }
3026 {
3029 }
3030 else
3031 {
3034 }
3037 /* Comes from final.c -- no real reason to change it. */
3038 #define MAX_CODE_ALIGN 16
3045 else
3054 else
3064 else
3070 {
3073 }
3078 }
3079 }
3080 \f
3081 /* Return a string that documents the current -m options. The caller is
3082 responsible for freeing the string. */
3087 {
3088 struct ix86_target_opts
3089 {
3092 };
3094 /* This table is ordered so that options like -msse4.2 that imply
3095 preceding options while match those first. */
3097 {
3124 };
3126 /* Flag options. */
3128 {
3154 };
3170 /* Add -march= option. */
3172 {
3175 }
3177 /* Add -mtune= option. */
3179 {
3182 }
3184 /* Pick out the options in isa options. */
3186 {
3188 {
3191 }
3192 }
3195 {
3198 }
3200 /* Add flag options. */
3202 {
3204 {
3207 }
3208 }
3211 {
3214 }
3216 /* Add -fpmath= option. */
3218 {
3221 {
3236 }
3237 }
3239 /* Any options? */
3245 /* Size the string. */
3249 {
3254 }
3256 /* Build the string. */
3261 {
3268 {
3270 line_len++;
3273 {
3277 }
3278 }
3282 {
3286 }
3287 }
3293 }
3295 /* Return true, if profiling code should be emitted before
3296 prologue. Otherwise it returns false.
3297 Note: For x86 with "hotfix" it is sorried. */
3298 static bool
3300 {
3302 }
3304 /* Function that is callable from the debugger to print the current
3305 options. */
3306 void
3308 {
3314 {
3317 }
3318 else
3322 }
3323 \f
3324 /* Override various settings based on options. If MAIN_ARGS_P, the
3325 options are from the command line, otherwise they are from
3326 attributes. */
3328 static void
3330 {
3338 enum pta_flags
3339 {
3369 /* if this reaches 32, need to widen struct pta flags below */
3370 };
3372 static struct pta
3373 {
3378 }
3380 {
3477 };
3481 /* Set up prefix/suffix so the error messages refer to either the command
3482 line argument, or the attribute(target). */
3484 {
3488 }
3489 else
3490 {
3494 }
3496 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3497 SUBTARGET_OVERRIDE_OPTIONS;
3498 #endif
3500 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3501 SUBSUBTARGET_OVERRIDE_OPTIONS;
3502 #endif
3504 /* -fPIC is the default for x86_64. */
3508 /* Need to check -mtune=generic first. */
3510 {
3513 /* As special support for cross compilers we read -mtune=native
3514 as -mtune=generic. With native compilers we won't see the
3515 -mtune=native, as it was changed by the driver. */
3517 {
3520 else
3522 }
3523 /* If this call is for setting the option attribute, allow the
3524 generic32/generic64 that was previously set. */
3528 ;
3536 }
3537 else
3538 {
3542 {
3545 }
3547 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3548 need to use a sensible tune option. */
3552 {
3555 else
3557 }
3558 }
3561 {
3562 /* rep; movq isn't available in 32-bit code. */
3565 }
3569 else
3576 {
3578 {
3616 {
3619 }
3627 }
3628 }
3629 else
3630 {
3631 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3632 use of rip-relative addressing. This eliminates fixups that
3633 would otherwise be needed if this object is to be placed in a
3634 DLL, and is essentially just as efficient as direct addressing. */
3639 else
3641 }
3643 {
3646 }
3653 {
3656 /* Default cpu tuning to the architecture. */
3748 }
3763 {
3767 {
3769 {
3771 {
3779 }
3780 else
3783 }
3784 }
3785 else
3786 {
3787 /* Adjust tuning when compiling for 32-bit ABI. */
3789 {
3805 }
3806 }
3807 /* Intel CPUs have always interpreted SSE prefetch instructions as
3808 NOPs; so, we can enable SSE prefetch instructions even when
3809 -mtune (rather than -march) points us to a processor that has them.
3810 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3811 higher processors. */
3816 }
3826 #ifndef USE_IX86_FRAME_POINTER
3827 #define USE_IX86_FRAME_POINTER 0
3828 #endif
3830 #ifndef USE_X86_64_FRAME_POINTER
3831 #define USE_X86_64_FRAME_POINTER 0
3832 #endif
3834 /* Set the default values for switches whose default depends on TARGET_64BIT
3835 in case they weren't overwritten by command line options. */
3837 {
3846 }
3847 else
3848 {
3855 }
3859 else
3862 /* Arrange to set up i386_stack_locals for all functions. */
3865 /* Validate -mregparm= value. */
3867 {
3871 {
3875 }
3876 }
3880 /* Default align_* from the processor table. */
3882 {
3885 }
3887 {
3890 }
3892 {
3894 }
3896 /* Provide default for -mbranch-cost= value. */
3901 {
3904 /* Enable by default the SSE and MMX builtins. Do allow the user to
3905 explicitly disable any of these. In particular, disabling SSE and
3906 MMX for kernel code is extremely useful. */
3908 ix86_isa_flags
3914 }
3915 else
3916 {
3920 ix86_isa_flags
3923 /* i386 ABI does not specify red zone. It still makes sense to use it
3924 when programmer takes care to stack from being destroyed. */
3927 }
3929 /* Keep nonleaf frame pointers. */
3935 /* If we're doing fast math, we don't care about comparison order
3936 wrt NaNs. This lets us use a shorter comparison sequence. */
3940 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3941 since the insns won't need emulation. */
3945 /* Likewise, if the target doesn't have a 387, or we've specified
3946 software floating point, don't use 387 inline intrinsics. */
3950 /* Turn on MMX builtins for -msse. */
3952 {
3955 }
3957 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3961 /* Validate -mpreferred-stack-boundary= value or default it to
3962 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3965 {
3971 {
3975 else
3978 }
3979 else
3980 ix86_preferred_stack_boundary
3982 }
3984 /* Set the default value for -mstackrealign. */
3990 /* Validate -mincoming-stack-boundary= value or default it to
3991 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3994 {
3999 else
4000 {
4001 ix86_user_incoming_stack_boundary
4003 ix86_incoming_stack_boundary
4005 }
4006 }
4008 /* Accept -msseregparm only if at least SSE support is enabled. */
4014 {
4016 {
4018 {
4021 }
4023 {
4026 }
4027 }
4028 }
4029 else
4032 /* If the i387 is disabled, then do not return values in it. */
4036 /* Use external vectorized library in vectorizing intrinsics. */
4039 {
4050 }
4058 /* ??? Unwind info is not correct around the CFG unless either a frame
4059 pointer is present or M_A_O_A is set. Fixing this requires rewriting
4060 unwind info generation to be aware of the CFG and propagating states
4061 around edges. */
4064 && flag_omit_frame_pointer
4066 {
4072 }
4074 /* If stack probes are required, the space used for large function
4075 arguments on the stack must also be probed, so enable
4076 -maccumulate-outgoing-args so this happens in the prologue. */
4079 {
4084 }
4086 /* For sane SSE instruction set generation we need fcomi instruction.
4087 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
4088 expands to a sequence that includes conditional move. */
4092 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4093 {
4099 }
4101 /* When scheduling description is not available, disable scheduler pass
4102 so it won't slow down the compilation and make x87 code slower. */
4120 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4122 && HAVE_prefetch
4127 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4128 can be optimized to ap = __builtin_next_arg (0). */
4133 {
4144 }
4145 else
4146 {
4157 }
4159 #ifdef USE_IX86_CLD
4160 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4163 #endif
4166 {
4171 }
4173 {
4177 }
4179 {
4180 #if defined(PROFILE_BEFORE_PROLOGUE)
4182 #else
4184 #endif
4185 }
4188 {
4189 /* When not optimize for size, enable vzeroupper optimization for
4190 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4191 AVX unaligned load/store. */
4193 {
4201 }
4202 }
4203 else
4204 {
4205 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
4207 }
4209 /* Save the initial options in case the user does function specific
4210 options. */
4212 target_option_default_node = target_option_current_node
4214 }
4216 /* Return TRUE if VAL is passed in register with 256bit AVX modes. */
4218 static bool
4220 {
4228 {
4230 rtx r;
4233 {
4241 }
4242 }
4245 }
4247 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4249 static void
4251 {
4253 }
4255 /* Update register usage after having seen the compiler flags. */
4257 static void
4259 {
4264 {
4269 }
4271 /* The PIC register, if it exists, is fixed. */
4276 /* The 64-bit MS_ABI changes the set of call-used registers. */
4278 {
4285 }
4287 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
4288 other call-clobbered regs for 64-bit. */
4290 {
4297 }
4299 /* If MMX is disabled, squash the registers. */
4305 /* If SSE is disabled, squash the registers. */
4311 /* If the FPU is disabled, squash the registers. */
4317 /* If 32-bit, squash the 64-bit registers. */
4319 {
4324 }
4325 }
4327 \f
4328 /* Save the current options */
4330 static void
4332 {
4342 /* The fields are char but the variables are not; make sure the
4343 values fit in the fields. */
4348 }
4350 /* Restore the current options */
4352 static void
4354 {
4369 /* Recreate the arch feature tests if the arch changed */
4371 {
4376 }
4378 /* Recreate the tune optimization tests */
4380 {
4385 }
4386 }
4388 /* Print the current options */
4390 static void
4393 {
4415 {
4418 }
4419 }
4421 \f
4422 /* Inner function to process the attribute((target(...))), take an argument and
4423 set the current options from the argument. If we have a list, recursively go
4424 over the list. */
4426 static bool
4429 {
4433 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4434 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4435 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4436 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4437 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4439 enum ix86_opt_type
4440 {
4441 ix86_opt_unknown,
4442 ix86_opt_yes,
4443 ix86_opt_no,
4444 ix86_opt_str,
4445 ix86_opt_enum,
4446 ix86_opt_isa
4447 };
4449 static const struct
4450 {
4457 /* isa options */
4482 /* enum options */
4485 /* string options */
4489 /* flag options */
4491 OPT_mcld,
4492 MASK_CLD),
4495 OPT_mfancy_math_387,
4496 MASK_NO_FANCY_MATH_387),
4499 OPT_mieee_fp,
4500 MASK_IEEE_FP),
4503 OPT_minline_all_stringops,
4504 MASK_INLINE_ALL_STRINGOPS),
4507 OPT_minline_stringops_dynamically,
4508 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4511 OPT_mno_align_stringops,
4512 MASK_NO_ALIGN_STRINGOPS),
4515 OPT_mrecip,
4516 MASK_RECIP),
4518 };
4520 /* If this is a list, recurse to get the options. */
4522 {
4532 }
4537 /* Handle multiple arguments separated by commas. */
4541 {
4555 {
4559 }
4560 else
4561 {
4564 }
4566 /* Recognize no-xxx. */
4568 {
4572 }
4573 else
4576 /* Find the option. */
4580 {
4588 {
4593 }
4594 }
4596 /* Process the option. */
4598 {
4601 }
4604 {
4610 }
4613 {
4619 else
4621 }
4624 {
4626 {
4629 }
4630 else
4632 }
4635 {
4643 global_dc);
4644 else
4645 {
4648 }
4649 }
4651 else
4653 }
4656 }
4658 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4660 tree
4662 {
4677 /* Process each of the options on the chain. */
4682 /* If the changed options are different from the default, rerun
4683 ix86_option_override_internal, and then save the options away.
4684 The string options are are attribute options, and will be undone
4685 when we copy the save structure. */
4691 {
4692 /* If we are using the default tune= or arch=, undo the string assigned,
4693 and use the default. */
4704 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4708 {
4711 }
4713 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4716 /* Add any builtin functions with the new isa if any. */
4719 /* Save the current options unless we are validating options for
4720 #pragma. */
4727 /* Free up memory allocated to hold the strings */
4730 }
4733 }
4735 /* Hook to validate attribute((target("string"))). */
4737 static bool
4740 tree args,
4742 {
4749 /* If the function changed the optimization levels as well as setting target
4750 options, start with the optimizations specified. */
4755 /* The target attributes may also change some optimization flags, so update
4756 the optimization options if necessary. */
4765 {
4770 }
4779 }
4781 \f
4782 /* Hook to determine if one function can safely inline another. */
4784 static bool
4786 {
4791 /* If callee has no option attributes, then it is ok to inline. */
4795 /* If caller has no option attributes, but callee does then it is not ok to
4796 inline. */
4800 else
4801 {
4805 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4806 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4807 function. */
4812 /* See if we have the same non-isa options. */
4816 /* See if arch, tune, etc. are the same. */
4829 else
4831 }
4834 }
4836 \f
4837 /* Remember the last target of ix86_set_current_function. */
4840 /* Establish appropriate back-end context for processing the function
4841 FNDECL. The argument might be NULL to indicate processing at top
4842 level, outside of any function scope. */
4843 static void
4845 {
4846 /* Only change the context if the function changes. This hook is called
4847 several times in the course of compiling a function, and we don't want to
4848 slow things down too much or call target_reinit when it isn't safe. */
4850 {
4851 tree old_tree = (ix86_previous_fndecl
4855 tree new_tree = (fndecl
4861 ;
4864 {
4868 }
4871 {
4877 }
4878 }
4879 }
4881 \f
4882 /* Return true if this goes in large data/bss. */
4884 static bool
4886 {
4890 /* Functions are never large data. */
4895 {
4901 }
4902 else
4903 {
4906 /* If this is an incomplete type with size 0, then we can't put it
4907 in data because it might be too big when completed. */
4910 }
4913 }
4915 /* Switch to the appropriate section for output of DECL.
4916 DECL is either a `VAR_DECL' node or a constant of some sort.
4917 RELOC indicates whether forming the initial value of DECL requires
4918 link-time relocations. */
4921 ATTRIBUTE_UNUSED;
4926 {
4929 {
4933 {
4967 /* We don't split these for medium model. Place them into
4968 default sections and hope for best. */
4970 }
4972 {
4973 /* We might get called with string constants, but get_named_section
4974 doesn't like them as they are not DECLs. Also, we need to set
4975 flags in that case. */
4979 }
4980 }
4982 }
4984 /* Build up a unique section name, expressed as a
4985 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4986 RELOC indicates whether the initial value of EXP requires
4987 link-time relocations. */
4989 static void ATTRIBUTE_UNUSED
4991 {
4994 {
4996 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5000 {
5024 /* We don't split these for medium model. Place them into
5025 default sections and hope for best. */
5027 }
5029 {
5036 /* If we're using one_only, then there needs to be a .gnu.linkonce
5037 prefix to the section name. */
5044 }
5045 }
5047 }
5049 #ifdef COMMON_ASM_OP
5050 /* This says how to output assembler code to declare an
5051 uninitialized external linkage data object.
5053 For medium model x86-64 we need to use .largecomm opcode for
5054 large objects. */
5055 void
5059 {
5063 else
5068 }
5069 #endif
5071 /* Utility function for targets to use in implementing
5072 ASM_OUTPUT_ALIGNED_BSS. */
5074 void
5078 {
5082 else
5085 #ifdef ASM_DECLARE_OBJECT_NAME
5088 #else
5089 /* Standard thing is just output label for the object. */
5093 }
5094 \f
5096 {
5097 /* Turn off -fschedule-insns by default. It tends to make the
5098 problem with not enough registers even worse. */
5099 #ifdef INSN_SCHEDULING
5101 #endif
5103 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
5104 SUBTARGET_OPTIMIZATION_OPTIONS,
5105 #endif
5107 };
5109 /* Implement TARGET_OPTION_INIT_STRUCT. */
5111 static void
5113 {
5115 /* The Darwin libraries never set errno, so we might as well
5116 avoid calling them when that's the only reason we would. */
5122 }
5124 /* Decide whether we must probe the stack before any space allocation
5125 on this target. It's essentially TARGET_STACK_PROBE except when
5126 -fstack-check causes the stack to be already probed differently. */
5128 bool
5130 {
5131 /* Do not probe the stack twice if static stack checking is enabled. */
5136 }
5137 \f
5138 /* Decide whether we can make a sibling call to a function. DECL is the
5139 declaration of the function being targeted by the call and EXP is the
5140 CALL_EXPR representing the call. */
5142 static bool
5144 {
5148 /* If we are generating position-independent code, we cannot sibcall
5149 optimize any indirect call, or a direct call to a global function,
5150 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5152 && !TARGET_64BIT
5153 && flag_pic
5157 /* If we need to align the outgoing stack, then sibcalling would
5158 unalign the stack, which may break the called function. */
5164 {
5167 }
5168 else
5169 {
5170 /* We're looking at the CALL_EXPR, we need the type of the function. */
5175 }
5177 /* Check that the return value locations are the same. Like
5178 if we are returning floats on the 80387 register stack, we cannot
5179 make a sibcall from a function that doesn't return a float to a
5180 function that does or, conversely, from a function that does return
5181 a float to a function that doesn't; the necessary stack adjustment
5182 would not be executed. This is also the place we notice
5183 differences in the return value ABI. Note that it is ok for one
5184 of the functions to have void return type as long as the return
5185 value of the other is passed in a register. */
5190 {
5193 }
5195 {
5196 /* Disable sibcall if we need to generate vzeroupper after
5197 callee returns. */
5202 }
5207 {
5208 /* The SYSV ABI has more call-clobbered registers;
5209 disallow sibcalls from MS to SYSV. */
5213 }
5214 else
5215 {
5216 /* If this call is indirect, we'll need to be able to use a
5217 call-clobbered register for the address of the target function.
5218 Make sure that all such registers are not used for passing
5219 parameters. Note that DLLIMPORT functions are indirect. */
5222 {
5224 {
5225 /* ??? Need to count the actual number of registers to be used,
5226 not the possible number of registers. Fix later. */
5228 }
5229 }
5230 }
5232 /* Otherwise okay. That also includes certain types of indirect calls. */
5234 }
5236 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5237 and "sseregparm" calling convention attributes;
5238 arguments as in struct attribute_spec.handler. */
5240 static tree
5242 tree args,
5245 {
5250 {
5252 name);
5255 }
5257 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5259 {
5260 tree cst;
5263 {
5265 }
5268 {
5270 }
5274 {
5277 name);
5279 }
5281 {
5285 }
5288 }
5291 {
5292 /* Do not warn when emulating the MS ABI. */
5297 name);
5300 }
5302 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5304 {
5306 {
5308 }
5310 {
5312 }
5314 {
5316 }
5318 {
5320 }
5321 }
5323 /* Can combine stdcall with fastcall (redundant), regparm and
5324 sseregparm. */
5326 {
5328 {
5330 }
5332 {
5334 }
5336 {
5338 }
5339 }
5341 /* Can combine cdecl with regparm and sseregparm. */
5343 {
5345 {
5347 }
5349 {
5351 }
5353 {
5355 }
5356 }
5358 {
5361 name);
5363 {
5365 }
5367 {
5369 }
5371 {
5373 }
5374 }
5376 /* Can combine sseregparm with all attributes. */
5379 }
5381 /* This function determines from TYPE the calling-convention. */
5383 unsigned int
5385 {
5388 tree attrs;
5395 {
5405 /* Regparam isn't allowed for thiscall and fastcall. */
5407 {
5412 }
5416 }
5423 || is_stdarg
5429 }
5431 /* Return 0 if the attributes for two types are incompatible, 1 if they
5432 are compatible, and 2 if they are nearly compatible (which causes a
5433 warning to be generated). */
5435 static int
5437 {
5453 }
5454 \f
5455 /* Return the regparm value for a function with the indicated TYPE and DECL.
5456 DECL may be NULL when calling function indirectly
5457 or considering a libcall. */
5459 static int
5461 {
5462 tree attr;
5473 {
5476 {
5479 }
5480 }
5486 /* Use register calling convention for local functions when possible. */
5489 && optimize
5491 {
5492 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5495 {
5498 /* Make sure no regparm register is taken by a
5499 fixed register variable. */
5504 /* We don't want to use regparm(3) for nested functions as
5505 these use a static chain pointer in the third argument. */
5509 /* In 32-bit mode save a register for the split stack. */
5513 /* Each fixed register usage increases register pressure,
5514 so less registers should be used for argument passing.
5515 This functionality can be overriden by an explicit
5516 regparm value. */
5519 globals++;
5521 local_regparm
5526 }
5527 }
5530 }
5532 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5533 DFmode (2) arguments in SSE registers for a function with the
5534 indicated TYPE and DECL. DECL may be NULL when calling function
5535 indirectly or considering a libcall. Otherwise return 0. */
5537 static int
5539 {
5542 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5543 by the sseregparm attribute. */
5546 {
5548 {
5550 {
5554 else
5557 }
5559 }
5562 }
5564 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5565 (and DFmode for SSE2) arguments in SSE registers. */
5568 {
5569 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5573 }
5576 }
5578 /* Return true if EAX is live at the start of the function. Used by
5579 ix86_expand_prologue to determine if we need special help before
5580 calling allocate_stack_worker. */
5582 static bool
5584 {
5585 /* Cheat. Don't bother working forward from ix86_function_regparm
5586 to the function type to whether an actual argument is located in
5587 eax. Instead just look at cfg info, which is still close enough
5588 to correct at this point. This gives false positives for broken
5589 functions that might use uninitialized data that happens to be
5590 allocated in eax, but who cares? */
5592 }
5594 static bool
5596 {
5597 tree attr;
5600 {
5606 /* For 32-bit MS-ABI the default is to keep aggregate
5607 return pointer. */
5610 }
5612 }
5614 /* Value is the number of bytes of arguments automatically
5615 popped when returning from a subroutine call.
5616 FUNDECL is the declaration node of the function (as a tree),
5617 FUNTYPE is the data type of the function (as a tree),
5618 or for a library call it is an identifier node for the subroutine name.
5619 SIZE is the number of bytes of arguments passed on the stack.
5621 On the 80386, the RTD insn may be used to pop them if the number
5622 of args is fixed, but if the number is variable then the caller
5623 must pop them all. RTD can't be used for library calls now
5624 because the library is compiled with the Unix compiler.
5625 Use of RTD is a selectable option, since it is incompatible with
5626 standard Unix calling sequences. If the option is not selected,
5627 the caller must always pop the args.
5629 The attribute stdcall is equivalent to RTD on a per module basis. */
5631 static int
5633 {
5636 /* None of the 64-bit ABIs pop arguments. */
5647 /* Lose any fake structure return argument if it is passed on the stack. */
5650 {
5654 }
5657 }
5658 \f
5659 /* Argument support functions. */
5661 /* Return true when register may be used to pass function parameters. */
5662 bool
5664 {
5669 {
5673 else
5679 }
5682 {
5685 }
5686 else
5687 {
5691 }
5693 /* TODO: The function should depend on current function ABI but
5694 builtins.c would need updating then. Therefore we use the
5695 default ABI. */
5697 /* RAX is used as hidden argument to va_arg functions. */
5703 else
5710 }
5712 /* Return if we do not know how to pass TYPE solely in registers. */
5714 static bool
5716 {
5720 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5721 The layout_type routine is crafty and tries to trick us into passing
5722 currently unsupported vector types on the stack by using TImode. */
5725 }
5727 /* It returns the size, in bytes, of the area reserved for arguments passed
5728 in registers for the function represented by fndecl dependent to the used
5729 abi format. */
5730 int
5732 {
5736 else
5741 }
5743 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5744 call abi used. */
5745 enum calling_abi
5747 {
5749 {
5752 {
5755 }
5759 }
5761 }
5763 static bool
5765 {
5767 {
5771 else
5773 }
5775 }
5777 static enum calling_abi
5779 {
5783 }
5785 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5786 call abi used. */
5787 enum calling_abi
5789 {
5793 }
5795 /* Write the extra assembler code needed to declare a function properly. */
5797 void
5799 tree decl)
5800 {
5804 {
5810 }
5812 #ifdef SUBTARGET_ASM_UNWIND_INIT
5814 #endif
5818 /* Output magic byte marker, if hot-patch attribute is set. */
5820 {
5822 {
5823 /* leaq [%rsp + 0], %rsp */
5826 }
5827 else
5828 {
5829 /* movl.s %edi, %edi
5830 push %ebp
5831 movl.s %esp, %ebp */
5834 }
5835 }
5836 }
5838 /* regclass.c */
5841 /* Implementation of call abi switching target hook. Specific to FNDECL
5842 the specific call register sets are set. See also
5843 ix86_conditional_register_usage for more details. */
5844 void
5846 {
5849 else
5851 }
5853 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5854 expensive re-initialization of init_regs each time we switch function context
5855 since this is needed only during RTL expansion. */
5856 static void
5858 {
5862 }
5864 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5865 for a call to a function whose data type is FNTYPE.
5866 For a library call, FNTYPE is 0. */
5868 void
5872 tree fndecl,
5874 {
5876 tree fnret_type;
5880 /* Initialize for the current callee. */
5882 {
5885 }
5888 {
5892 }
5893 else
5894 {
5899 else
5901 }
5904 {
5908 {
5909 /* The return value of this function uses 256bit AVX modes. */
5912 else
5914 }
5915 }
5919 /* Set up the number of registers to use for passing arguments. */
5926 {
5928 ? X86_64_REGPARM_MAX
5930 }
5932 {
5935 {
5937 ? X86_64_SSE_REGPARM_MAX
5939 }
5940 }
5947 /* Because type might mismatch in between caller and callee, we need to
5948 use actual type of function for local calls.
5949 FIXME: cgraph_analyze can be told to actually record if function uses
5950 va_start so for local functions maybe_vaarg can be made aggressive
5951 helping K&R code.
5952 FIXME: once typesytem is fixed, we won't need this code anymore. */
5960 {
5961 /* If there are variable arguments, then we won't pass anything
5962 in registers in 32-bit mode. */
5964 {
5972 }
5974 /* Use ecx and edx registers if function has fastcall attribute,
5975 else look for regparm information. */
5977 {
5980 {
5983 }
5985 {
5988 }
5989 else
5991 }
5993 /* Set up the number of SSE registers used for passing SFmode
5994 and DFmode arguments. Warn for mismatching ABI. */
5996 }
5997 }
5999 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6000 But in the case of vector types, it is some vector mode.
6002 When we have only some of our vector isa extensions enabled, then there
6003 are some modes for which vector_mode_supported_p is false. For these
6004 modes, the generic vector support in gcc will choose some non-vector mode
6005 in order to implement the type. By computing the natural mode, we'll
6006 select the proper ABI location for the operand and not depend on whatever
6007 the middle-end decides to do with these vector types.
6009 The midde-end can't deal with the vector types > 16 bytes. In this
6010 case, we return the original mode and warn ABI change if CUM isn't
6011 NULL. */
6013 static enum machine_mode
6015 {
6019 {
6022 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6024 {
6029 else
6032 /* Get the mode which has this inner mode and number of units. */
6036 {
6038 {
6042 && !warnedavx
6044 {
6048 }
6050 }
6051 else
6053 }
6056 }
6057 }
6060 }
6062 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6063 this may not agree with the mode that the type system has chosen for the
6064 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6065 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6067 static rtx
6070 {
6071 rtx tmp;
6075 else
6076 {
6080 }
6083 }
6085 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6086 of this code is to classify each 8bytes of incoming argument by the register
6087 class and assign registers accordingly. */
6089 /* Return the union class of CLASS1 and CLASS2.
6090 See the x86-64 PS ABI for details. */
6092 static enum x86_64_reg_class
6094 {
6095 /* Rule #1: If both classes are equal, this is the resulting class. */
6099 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6100 the other class. */
6106 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6110 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6118 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6119 MEMORY is used. */
6128 /* Rule #6: Otherwise class SSE is used. */
6130 }
6132 /* Classify the argument of type TYPE and mode MODE.
6133 CLASSES will be filled by the register class used to pass each word
6134 of the operand. The number of words is returned. In case the parameter
6135 should be passed in memory, 0 is returned. As a special case for zero
6136 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6138 BIT_OFFSET is used internally for handling records and specifies offset
6139 of the offset in bits modulo 256 to avoid overflow cases.
6141 See the x86-64 PS ABI for details.
6142 */
6144 static int
6147 {
6148 HOST_WIDE_INT bytes =
6152 /* Variable sized entities are always passed/returned in memory. */
6161 {
6163 tree field;
6166 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
6173 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6174 signalize memory class, so handle it as special case. */
6176 {
6179 }
6181 /* Classify each field of record and merge classes. */
6183 {
6185 /* And now merge the fields of structure. */
6187 {
6189 {
6195 /* Bitfields are always classified as integer. Handle them
6196 early, since later code would consider them to be
6197 misaligned integers. */
6199 {
6207 }
6208 else
6209 {
6214 /* Flexible array member is ignored. */
6221 {
6225 {
6228 "the ABI of passing struct with"
6229 " a flexible array member has"
6231 }
6233 }
6235 subclasses,
6244 }
6245 }
6246 }
6250 /* Arrays are handled as small records. */
6251 {
6258 /* The partial classes are now full classes. */
6269 }
6272 /* Unions are similar to RECORD_TYPE but offset is always 0.
6273 */
6275 {
6277 {
6285 bit_offset);
6290 }
6291 }
6296 }
6299 {
6300 /* When size > 16 bytes, if the first one isn't
6301 X86_64_SSE_CLASS or any other ones aren't
6302 X86_64_SSEUP_CLASS, everything should be passed in
6303 memory. */
6310 }
6312 /* Final merger cleanup. */
6314 {
6315 /* If one class is MEMORY, everything should be passed in
6316 memory. */
6320 /* The X86_64_SSEUP_CLASS should be always preceded by
6321 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6325 {
6326 /* The first one should never be X86_64_SSEUP_CLASS. */
6329 }
6331 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6332 everything should be passed in memory. */
6335 {
6338 /* The first one should never be X86_64_X87UP_CLASS. */
6341 {
6344 "the ABI of passing union with long double"
6346 }
6348 }
6349 }
6351 }
6353 /* Compute alignment needed. We align all types to natural boundaries with
6354 exception of XFmode that is aligned to 64bits. */
6356 {
6365 /* Misaligned fields are always returned in memory. */
6368 }
6370 /* for V1xx modes, just use the base mode */
6375 /* Classification of atomic types. */
6377 {
6393 {
6397 {
6400 }
6402 {
6405 }
6407 {
6411 }
6413 {
6416 }
6417 else
6419 }
6426 /* OImode shouldn't be used directly. */
6433 else
6451 else
6452 {
6456 {
6459 "the ABI of passing structure with complex float"
6461 }
6464 }
6473 /* This modes is larger than 16 bytes. */
6516 else
6520 }
6521 }
6523 /* Examine the argument and return set number of register required in each
6524 class. Return 0 iff parameter should be passed in memory. */
6525 static int
6528 {
6538 {
6560 }
6562 }
6564 /* Construct container for the argument used by GCC interface. See
6565 FUNCTION_ARG for the detailed description. */
6567 static rtx
6571 {
6572 /* The following variables hold the static issued_error state. */
6586 rtx ret;
6597 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6598 some less clueful developer tries to use floating-point anyway. */
6600 {
6602 {
6604 {
6607 }
6608 }
6610 {
6613 }
6615 }
6617 /* Likewise, error if the ABI requires us to return values in the
6618 x87 registers and the user specified -mno-80387. */
6624 {
6626 {
6629 }
6631 }
6633 /* First construct simple cases. Avoid SCmode, since we want to use
6634 single register to pass this type. */
6637 {
6652 /* Zero sized array, struct or class. */
6656 }
6677 /* Otherwise figure out the entries of the PARALLEL. */
6679 {
6683 {
6688 /* Merge TImodes on aligned occasions here too. */
6693 else
6695 /* We've requested 24 bytes we don't have mode for. Use DImode. */
6701 intreg++;
6708 sse_regno++;
6715 sse_regno++;
6720 {
6726 {
6728 i++;
6729 }
6730 else
6743 }
6748 sse_regno++;
6752 }
6753 }
6755 /* Empty aligned struct, union or class. */
6763 }
6765 /* Update the data in CUM to advance over an argument of mode MODE
6766 and data type TYPE. (TYPE is null for libcalls where that information
6767 may not be available.) */
6769 static void
6772 HOST_WIDE_INT words)
6773 {
6775 {
6782 /* FALLTHRU */
6793 {
6796 }
6800 /* OImode shouldn't be used directly. */
6809 /* FALLTHRU */
6825 {
6830 {
6833 }
6834 }
6844 {
6849 {
6852 }
6853 }
6855 }
6856 }
6858 static void
6861 {
6864 /* Unnamed 256bit vector mode parameters are passed on stack. */
6870 {
6875 }
6876 else
6877 {
6881 }
6882 }
6884 static void
6886 HOST_WIDE_INT words)
6887 {
6888 /* Otherwise, this should be passed indirect. */
6893 {
6896 }
6897 }
6899 /* Update the data in CUM to advance over an argument of mode MODE and
6900 data type TYPE. (TYPE is null for libcalls where that information
6901 may not be available.) */
6903 static void
6906 {
6911 else
6922 else
6924 }
6926 /* Define where to put the arguments to a function.
6927 Value is zero to push the argument on the stack,
6928 or a hard register in which to store the argument.
6930 MODE is the argument's machine mode.
6931 TYPE is the data type of the argument (as a tree).
6932 This is null for libcalls where that information may
6933 not be available.
6934 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6935 the preceding args and about the function being called.
6936 NAMED is nonzero if this argument is a named parameter
6937 (otherwise it is an extra parameter matching an ellipsis). */
6939 static rtx
6943 {
6946 /* Avoid the AL settings for the Unix64 ABI. */
6951 {
6958 /* FALLTHRU */
6964 {
6967 /* Fastcall allocates the first two DWORD (SImode) or
6968 smaller arguments to ECX and EDX if it isn't an
6969 aggregate type . */
6971 {
6977 /* ECX not EAX is the first allocated register. */
6980 }
6982 }
6991 /* FALLTHRU */
6993 /* In 32bit, we pass TImode in xmm registers. */
7001 {
7003 {
7007 }
7011 }
7015 /* OImode shouldn't be used directly. */
7025 {
7029 }
7039 {
7041 {
7045 }
7049 }
7051 }
7054 }
7056 static rtx
7059 {
7060 /* Handle a hidden AL argument containing number of registers
7061 for varargs x86-64 functions. */
7065 ? X86_64_SSE_REGPARM_MAX
7070 {
7080 /* Unnamed 256bit vector mode parameters are passed on stack. */
7084 }
7090 }
7092 static rtx
7095 HOST_WIDE_INT bytes)
7096 {
7099 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7100 We use value of -2 to specify that current function call is MSABI. */
7104 /* If we've run out of registers, it goes on the stack. */
7110 /* Only floating point modes are passed in anything but integer regs. */
7112 {
7115 else
7116 {
7119 /* Unnamed floating parameters are passed in both the
7120 SSE and integer registers. */
7126 }
7127 }
7128 /* Handle aggregated types passed in register. */
7130 {
7135 }
7138 }
7140 /* Return where to put the arguments to a function.
7141 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7143 MODE is the argument's machine mode. TYPE is the data type of the
7144 argument. It is null for libcalls where that information may not be
7145 available. CUM gives information about the preceding args and about
7146 the function being called. NAMED is nonzero if this argument is a
7147 named parameter (otherwise it is an extra parameter matching an
7148 ellipsis). */
7150 static rtx
7153 {
7156 rtx arg;
7160 else
7164 /* To simplify the code below, represent vector types with a vector mode
7165 even if MMX/SSE are not active. */
7173 else
7177 {
7178 /* This argument uses 256bit AVX modes. */
7181 else
7183 }
7186 }
7188 /* A C expression that indicates when an argument must be passed by
7189 reference. If nonzero for an argument, a copy of that argument is
7190 made in memory and a pointer to the argument is passed instead of
7191 the argument itself. The pointer is passed in whatever way is
7192 appropriate for passing a pointer to that type. */
7194 static bool
7198 {
7199 /* See Windows x64 Software Convention. */
7201 {
7204 {
7205 /* Arrays are passed by reference. */
7210 {
7211 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7212 are passed by reference. */
7214 }
7215 }
7217 /* __m128 is passed by reference. */
7223 }
7224 }
7229 }
7231 /* Return true when TYPE should be 128bit aligned for 32bit argument
7232 passing ABI. XXX: This function is obsolete and is only used for
7233 checking psABI compatibility with previous versions of GCC. */
7235 static bool
7237 {
7249 {
7250 /* Walk the aggregates recursively. */
7252 {
7256 {
7257 tree field;
7259 /* Walk all the structure fields. */
7261 {
7265 }
7267 }
7270 /* Just for use if some languages passes arrays by value. */
7277 }
7278 }
7280 }
7282 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7283 XXX: This function is obsolete and is only used for checking psABI
7284 compatibility with previous versions of GCC. */
7286 static unsigned int
7289 {
7290 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7291 natural boundaries. */
7293 {
7294 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7295 make an exception for SSE modes since these require 128bit
7296 alignment.
7298 The handling here differs from field_alignment. ICC aligns MMX
7299 arguments to 4 byte boundaries, while structure fields are aligned
7300 to 8 byte boundaries. */
7302 {
7305 }
7306 else
7307 {
7310 }
7311 }
7315 }
7317 /* Return true when TYPE should be 128bit aligned for 32bit argument
7318 passing ABI. */
7320 static bool
7322 {
7332 {
7333 /* Walk the aggregates recursively. */
7335 {
7339 {
7340 tree field;
7342 /* Walk all the structure fields. */
7344 field;
7346 {
7350 }
7352 }
7355 /* Just for use if some languages passes arrays by value. */
7362 }
7363 }
7364 else
7368 }
7370 /* Gives the alignment boundary, in bits, of an argument with the
7371 specified mode and type. */
7373 static unsigned int
7375 {
7378 {
7379 /* Since the main variant type is used for call, we convert it to
7380 the main variant type. */
7383 }
7384 else
7388 else
7389 {
7394 {
7395 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7397 {
7400 }
7406 }
7409 && !warned
7411 saved_align))
7412 {
7415 "The ABI for passing parameters with %d-byte"
7418 }
7419 }
7422 }
7424 /* Return true if N is a possible register number of function value. */
7426 static bool
7428 {
7430 {
7435 /* TODO: The function should depend on current function ABI but
7436 builtins.c would need updating then. Therefore we use the
7437 default ABI. */
7449 }
7452 }
7454 /* Define how to find the value returned by a function.
7455 VALTYPE is the data type of the value (as a tree).
7456 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7457 otherwise, FUNC is 0. */
7459 static rtx
7462 {
7465 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7466 we normally prevent this case when mmx is not available. However
7467 some ABIs may require the result to be returned like DImode. */
7471 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7472 we prevent this case when sse is not available. However some ABIs
7473 may require the result to be returned like integer TImode. */
7478 /* 32-byte vector modes in %ymm0. */
7482 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7485 else
7486 /* Most things go in %eax. */
7489 /* Override FP return register with %xmm0 for local functions when
7490 SSE math is enabled or for functions with sseregparm attribute. */
7492 {
7497 }
7499 /* OImode shouldn't be used directly. */
7503 }
7505 static rtx
7507 const_tree valtype)
7508 {
7509 rtx ret;
7511 /* Handle libcalls, which don't provide a type node. */
7513 {
7515 {
7532 }
7533 }
7539 /* For zero sized structures, construct_container returns NULL, but we
7540 need to keep rest of compiler happy by returning meaningful value. */
7545 }
7547 static rtx
7549 {
7553 {
7555 {
7568 }
7569 }
7571 }
7573 static rtx
7576 {
7588 else
7590 }
7592 static rtx
7595 {
7601 }
7603 rtx
7605 {
7607 }
7609 /* Return true iff type is returned in memory. */
7611 static bool ATTRIBUTE_UNUSED
7613 {
7614 HOST_WIDE_INT size;
7625 {
7626 /* User-created vectors small enough to fit in EAX. */
7630 /* MMX/3dNow values are returned in MM0,
7631 except when it doesn't exits or the ABI prescribes otherwise. */
7635 /* SSE values are returned in XMM0, except when it doesn't exist. */
7639 /* AVX values are returned in YMM0, except when it doesn't exist. */
7642 }
7650 /* OImode shouldn't be used directly. */
7654 }
7656 static bool ATTRIBUTE_UNUSED
7658 {
7661 }
7663 static bool ATTRIBUTE_UNUSED
7665 {
7668 /* __m128 is returned in xmm0. */
7673 /* Otherwise, the size must be exactly in [1248]. */
7675 }
7677 static bool
7679 {
7680 #ifdef SUBTARGET_RETURN_IN_MEMORY
7682 #else
7686 {
7689 else
7691 }
7692 else
7694 #endif
7695 }
7697 /* When returning SSE vector types, we have a choice of either
7698 (1) being abi incompatible with a -march switch, or
7699 (2) generating an error.
7700 Given no good solution, I think the safest thing is one warning.
7701 The user won't be able to use -Werror, but....
7703 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7704 called in response to actually generating a caller or callee that
7705 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7706 via aggregate_value_p for general type probing from tree-ssa. */
7708 static rtx
7710 {
7714 {
7715 /* Look at the return type of the function, not the function type. */
7719 {
7722 {
7726 }
7727 }
7730 {
7732 {
7736 }
7737 }
7738 }
7741 }
7743 \f
7744 /* Create the va_list data type. */
7746 /* Returns the calling convention specific va_list date type.
7747 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7749 static tree
7751 {
7754 /* For i386 we use plain pointer to argument area. */
7764 unsigned_type_node);
7767 unsigned_type_node);
7770 ptr_type_node);
7773 ptr_type_node);
7792 /* The correct type is an array type of one element. */
7794 }
7796 /* Setup the builtin va_list data type and for 64-bit the additional
7797 calling convention specific va_list data types. */
7799 static tree
7801 {
7804 /* Initialize abi specific va_list builtin types. */
7806 {
7807 tree t;
7809 {
7814 }
7815 else
7816 {
7821 }
7823 {
7828 }
7829 else
7830 {
7835 }
7836 }
7839 }
7841 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7843 static void
7845 {
7847 alias_set_type set;
7850 /* GPR size of varargs save area. */
7853 else
7856 /* FPR size of varargs save area. We don't need it if we don't pass
7857 anything in SSE registers. */
7860 else
7874 {
7881 }
7884 {
7888 /* Now emit code to save SSE registers. The AX parameter contains number
7889 of SSE parameter registers used to call this function, though all we
7890 actually check here is the zero/non-zero status. */
7895 label));
7897 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7898 we used movdqa (i.e. TImode) instead? Perhaps even better would
7899 be if we could determine the real mode of the data, via a hook
7900 into pass_stdarg. Ignore all that for now. */
7910 {
7918 }
7921 }
7922 }
7924 static void
7926 {
7931 {
7942 }
7943 }
7945 static void
7949 {
7950 CUMULATIVE_ARGS next_cum;
7951 tree fntype;
7953 /* This argument doesn't appear to be used anymore. Which is good,
7954 because the old code here didn't suppress rtl generation. */
7962 /* For varargs, we do not want to skip the dummy va_dcl argument.
7963 For stdargs, we do want to skip the last named argument. */
7970 else
7972 }
7974 /* Checks if TYPE is of kind va_list char *. */
7976 static bool
7978 {
7979 tree canonic;
7981 /* For 32-bit it is always true. */
7987 }
7989 /* Implement va_start. */
7991 static void
7993 {
7997 tree type;
7998 rtx ovf_rtx;
8002 {
8005 /* When we are splitting the stack, we can't refer to the stack
8006 arguments using internal_arg_pointer, because they may be on
8007 the old stack. The split stack prologue will arrange to
8008 leave a pointer to the old stack arguments in a scratch
8009 register, which we here copy to a pseudo-register. The split
8010 stack prologue can't set the pseudo-register directly because
8011 it (the prologue) runs before any registers have been saved. */
8015 {
8029 }
8030 }
8032 /* Only 64bit target needs something special. */
8034 {
8037 else
8038 {
8047 }
8049 }
8058 /* The following should be folded into the MEM_REF offset. */
8068 /* Count number of gp and fp argument registers used. */
8074 {
8080 }
8083 {
8089 }
8091 /* Find the overflow area. */
8095 else
8106 {
8107 /* Find the register save area.
8108 Prologue of the function save it right above stack frame. */
8117 }
8118 }
8120 /* Implement va_arg. */
8122 static tree
8125 {
8132 rtx container;
8134 tree ptrtype;
8138 /* Only 64bit target needs something special. */
8162 {
8169 /* Unnamed 256bit vector mode parameters are passed on stack. */
8171 {
8174 }
8182 }
8184 /* Pull the value out of the saved registers. */
8189 {
8203 /* In case we are passing structure, verify that it is consecutive block
8204 on the register save area. If not we need to do moves. */
8206 {
8207 /* Verify that all registers are strictly consecutive */
8209 {
8213 {
8218 }
8219 }
8220 else
8221 {
8225 {
8230 }
8231 }
8232 }
8234 {
8237 }
8238 else
8239 {
8242 }
8244 /* First ensure that we fit completely in registers. */
8246 {
8253 }
8255 {
8263 }
8265 /* Compute index to start of area used for integer regs. */
8267 {
8268 /* int_addr = gpr + sav; */
8272 }
8274 {
8275 /* sse_addr = fpr + sav; */
8279 }
8281 {
8285 /* addr = &temp; */
8290 {
8294 tree piece_type;
8295 tree addr_type;
8296 tree daddr_type;
8305 {
8310 }
8314 else
8321 {
8324 }
8325 else
8326 {
8329 }
8338 {
8343 }
8344 else
8345 {
8346 tree copy
8351 }
8353 }
8354 }
8357 {
8361 }
8364 {
8368 }
8373 }
8375 /* ... otherwise out of the overflow area. */
8377 /* When we align parameter on stack for caller, if the parameter
8378 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8379 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8380 here with caller. */
8385 /* Care for on-stack alignment if needed. */
8388 else
8389 {
8397 }
8415 }
8416 \f
8417 /* Return true if OPNUM's MEM should be matched
8418 in movabs* patterns. */
8420 bool
8422 {
8434 }
8435 \f
8436 /* Initialize the table of extra 80387 mathematical constants. */
8438 static void
8440 {
8442 {
8448 };
8452 {
8454 /* Ensure each constant is rounded to XFmode precision. */
8457 }
8460 }
8462 /* Return non-zero if the constant is something that
8463 can be loaded with a special instruction. */
8465 int
8467 {
8470 REAL_VALUE_TYPE r;
8482 /* For XFmode constants, try to find a special 80387 instruction when
8483 optimizing for size or on those CPUs that benefit from them. */
8486 {
8495 }
8497 /* Load of the constant -0.0 or -1.0 will be split as
8498 fldz;fchs or fld1;fchs sequence. */
8505 }
8507 /* Return the opcode of the special instruction to be used to load
8508 the constant X. */
8512 {
8514 {
8534 }
8535 }
8537 /* Return the CONST_DOUBLE representing the 80387 constant that is
8538 loaded by the specified special instruction. The argument IDX
8539 matches the return value from standard_80387_constant_p. */
8541 rtx
8543 {
8550 {
8561 }
8564 XFmode);
8565 }
8567 /* Return 1 if X is all 0s and 2 if x is all 1s
8568 in supported SSE vector mode. */
8570 int
8572 {
8579 {
8588 }
8591 }
8593 /* Return the opcode of the special instruction to be used to load
8594 the constant X. */
8598 {
8600 {
8603 {
8609 else
8614 else
8621 else
8626 else
8630 }
8635 }
8637 }
8639 /* Returns true if OP contains a symbol reference */
8641 bool
8643 {
8652 {
8654 {
8660 }
8664 }
8667 }
8669 /* Return true if it is appropriate to emit `ret' instructions in the
8670 body of a function. Do this only if the epilogue is simple, needing a
8671 couple of insns. Prior to reloading, we can't tell how many registers
8672 must be saved, so return false then. Return false if there is no frame
8673 marker to de-allocate. */
8675 bool
8677 {
8683 /* Don't allow more than 32k pop, since that's all we can do
8684 with one instruction. */
8691 }
8692 \f
8693 /* Value should be nonzero if functions must have frame pointers.
8694 Zero means the frame pointer need not be set up (and parms may
8695 be accessed via the stack pointer) in functions that seem suitable. */
8697 static bool
8699 {
8700 /* If we accessed previous frames, then the generated code expects
8701 to be able to access the saved ebp value in our frame. */
8705 /* Several x86 os'es need a frame pointer for other reasons,
8706 usually pertaining to setjmp. */
8710 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8711 turns off the frame pointer by default. Turn it back on now if
8712 we've not got a leaf function. */
8714 && (!current_function_is_leaf
8722 }
8724 /* Record that the current function accesses previous call frames. */
8726 void
8728 {
8730 }
8731 \f
8732 #ifndef USE_HIDDEN_LINKONCE
8733 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
8734 # define USE_HIDDEN_LINKONCE 1
8735 # else
8736 # define USE_HIDDEN_LINKONCE 0
8737 # endif
8738 #endif
8742 /* Fills in the label name that should be used for a pc thunk for
8743 the given register. */
8745 static void
8747 {
8752 else
8754 }
8757 /* This function generates code for -fpic that loads %ebx with
8758 the return address of the caller and then returns. */
8760 static void
8762 {
8766 #ifdef TARGET_SOLARIS
8768 #endif
8771 {
8773 tree decl;
8788 #if TARGET_MACHO
8790 {
8799 }
8800 else
8801 #endif
8803 {
8814 }
8815 else
8816 {
8819 }
8825 /* Make sure unwind info is emitted for the thunk if needed. */
8828 /* Pad stack IP move with 4 instructions (two NOPs count
8829 as one instruction). */
8831 {
8836 }
8847 }
8851 }
8853 /* Emit code for the SET_GOT patterns. */
8857 {
8863 {
8864 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8869 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8870 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8871 an unadorned address. */
8876 }
8881 {
8886 else
8887 {
8889 #ifdef DWARF2_UNWIND_INFO
8890 /* The call to next label acts as a push. */
8892 {
8893 rtx insn;
8897 stack_pointer_rtx,
8902 }
8903 #endif
8904 }
8906 #if TARGET_MACHO
8907 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8908 is what will be referenced by the Mach-O PIC subsystem. */
8911 #endif
8917 {
8919 #ifdef DWARF2_UNWIND_INFO
8920 /* The pop is a pop and clobbers dest, but doesn't restore it
8921 for unwind info purposes. */
8923 {
8924 rtx insn;
8930 stack_pointer_rtx,
8935 }
8936 #endif
8937 }
8938 }
8939 else
8940 {
8945 #ifdef DWARF2_UNWIND_INFO
8946 /* Ensure all queued register saves are flushed before the
8947 call. */
8950 #endif
8954 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8955 is what will be referenced by the Mach-O PIC subsystem. */
8956 #if TARGET_MACHO
8959 else
8962 #endif
8963 }
8970 else
8974 }
8976 /* Generate an "push" pattern for input ARG. */
8978 static rtx
8980 {
8990 stack_pointer_rtx)),
8991 arg);
8992 }
8994 /* Generate an "pop" pattern for input ARG. */
8996 static rtx
8998 {
9000 arg,
9003 stack_pointer_rtx)));
9004 }
9006 /* Return >= 0 if there is an unused call-clobbered register available
9007 for the entire function. */
9009 static unsigned int
9011 {
9015 {
9017 /* Can't use the same register for both PIC and DRAP. */
9020 else
9025 }
9028 }
9030 /* Return TRUE if we need to save REGNO. */
9032 static bool
9034 {
9044 {
9047 {
9053 }
9054 }
9063 }
9065 /* Return number of saved general prupose registers. */
9067 static int
9069 {
9075 nregs ++;
9077 }
9079 /* Return number of saved SSE registrers. */
9081 static int
9083 {
9091 nregs ++;
9093 }
9095 /* Given FROM and TO register numbers, say whether this elimination is
9096 allowed. If stack alignment is needed, we can only replace argument
9097 pointer with hard frame pointer, or replace frame pointer with stack
9098 pointer. Otherwise, frame pointer elimination is automatically
9099 handled and all other eliminations are valid. */
9101 static bool
9103 {
9109 else
9111 }
9113 /* Return the offset between two registers, one to be eliminated, and the other
9114 its replacement, at the start of a routine. */
9116 HOST_WIDE_INT
9118 {
9127 else
9128 {
9136 }
9137 }
9139 /* In a dynamically-aligned function, we can't know the offset from
9140 stack pointer to frame pointer, so we must ensure that setjmp
9141 eliminates fp against the hard fp (%ebp) rather than trying to
9142 index from %esp up to the top of the frame across a gap that is
9143 of unknown (at compile-time) size. */
9144 static rtx
9146 {
9148 }
9150 /* On the x86 -fsplit-stack and -fstack-protector both use the same
9151 field in the TCB, so they can not be used together. */
9153 static bool
9156 {
9159 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
9163 #else
9165 {
9170 }
9171 #endif
9174 }
9176 /* When using -fsplit-stack, the allocation routines set a field in
9177 the TCB to the bottom of the stack plus this much space, measured
9178 in bytes. */
9180 #define SPLIT_STACK_AVAILABLE 256
9182 /* Fill structure ix86_frame about frame of currently computed function. */
9184 static void
9186 {
9188 HOST_WIDE_INT offset;
9191 HOST_WIDE_INT to_allocate;
9199 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9200 function prologues and leaf. */
9204 {
9209 }
9215 /* For SEH we have to limit the amount of code movement into the prologue.
9216 At present we do this via a BLOCKAGE, at which point there's very little
9217 scheduling that can be done, which means that there's very little point
9218 in doing anything except PUSHs. */
9222 /* During reload iteration the amount of registers saved can change.
9223 Recompute the value as needed. Do not recompute when amount of registers
9224 didn't change as reload does multiple calls to the function and does not
9225 expect the decision to change within single iteration. */
9228 {
9234 /* The fast prologue uses move instead of push to save registers. This
9235 is significantly longer, but also executes faster as modern hardware
9236 can execute the moves in parallel, but can't do that for push/pop.
9238 Be careful about choosing what prologue to emit: When function takes
9239 many instructions to execute we may use slow version as well as in
9240 case function is known to be outside hot spot (this is known with
9241 feedback only). Weight the size of function by number of registers
9242 to save as it is cheap to use one or two push instructions but very
9243 slow to use many of them. */
9247 || (flag_branch_probabilities
9250 else
9253 }
9257 else
9260 /* If static stack checking is enabled and done with probes, the registers
9261 need to be saved before allocating the frame. */
9265 /* Skip return address. */
9268 /* Skip pushed static chain. */
9272 /* Skip saved base pointer. */
9277 /* The traditional frame pointer location is at the top of the frame. */
9280 /* Register save area */
9284 /* Align and set SSE register save area. */
9286 {
9287 /* The only ABI that has saved SSE registers (Win64) also has a
9288 16-byte aligned default stack, and thus we don't need to be
9289 within the re-aligned local stack frame to save them. */
9293 }
9296 /* The re-aligned stack starts here. Values before this point are not
9297 directly comparable with values below this point. In order to make
9298 sure that no value happens to be the same before and after, force
9299 the alignment computation below to add a non-zero value. */
9303 /* Va-arg area */
9307 /* Align start of frame for local function. */
9311 || !current_function_is_leaf
9316 /* Frame pointer points here. */
9321 /* Add outgoing arguments area. Can be skipped if we eliminated
9322 all the function calls as dead code.
9323 Skipping is however impossible when function calls alloca. Alloca
9324 expander assumes that last crtl->outgoing_args_size
9325 of stack frame are unused. */
9329 {
9332 }
9333 else
9336 /* Align stack boundary. Only needed if we're calling another function
9337 or using alloca. */
9342 /* We've reached end of stack frame. */
9345 /* Size prologue needs to allocate. */
9353 && current_function_sp_is_unchanging
9354 && current_function_is_leaf
9356 {
9362 }
9363 else
9367 /* The SEH frame pointer location is near the bottom of the frame.
9368 This is enforced by the fact that the difference between the
9369 stack pointer and the frame pointer is limited to 240 bytes in
9370 the unwind data structure. */
9372 {
9373 HOST_WIDE_INT diff;
9375 /* If we can leave the frame pointer where it is, do so. */
9378 {
9379 /* Ideally we'd determine what portion of the local stack frame
9380 (within the constraint of the lowest 240) is most heavily used.
9381 But without that complication, simply bias the frame pointer
9382 by 128 bytes so as to maximize the amount of the local stack
9383 frame that is addressable with 8-bit offsets. */
9385 }
9386 }
9387 }
9389 /* This is semi-inlined memory_address_length, but simplified
9390 since we know that we're always dealing with reg+offset, and
9391 to avoid having to create and discard all that rtl. */
9395 {
9399 {
9400 /* EBP and R13 cannot be encoded without an offset. */
9402 }
9406 /* ESP and R12 must be encoded with a SIB byte. */
9408 len++;
9411 }
9413 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9414 The valid base registers are taken from CFUN->MACHINE->FS. */
9416 static rtx
9418 {
9424 {
9425 /* Choose the base register most likely to allow the most scheduling
9426 opportunities. Generally FP is valid througout the function,
9427 while DRAP must be reloaded within the epilogue. But choose either
9428 over the SP due to increased encoding size. */
9431 {
9434 }
9436 {
9439 }
9441 {
9444 }
9445 }
9446 else
9447 {
9448 HOST_WIDE_INT toffset;
9451 /* Choose the base register with the smallest address encoding.
9452 With a tie, choose FP > DRAP > SP. */
9454 {
9458 }
9460 {
9464 {
9468 }
9469 }
9471 {
9475 {
9479 }
9480 }
9481 }
9485 }
9487 /* Emit code to save registers in the prologue. */
9489 static void
9491 {
9493 rtx insn;
9497 {
9500 }
9501 }
9503 /* Emit a single register save at CFA - CFA_OFFSET. */
9505 static void
9507 HOST_WIDE_INT cfa_offset)
9508 {
9516 /* For SSE saves, we need to indicate the 128-bit alignment. */
9527 /* When saving registers into a re-aligned local stack frame, avoid
9528 any tricky guessing by dwarf2out. */
9530 {
9534 {
9535 /* A bit of a hack. We force the DRAP register to be saved in
9536 the re-aligned stack frame, which provides us with a copy
9537 of the CFA that will last past the prologue. Install it. */
9543 }
9544 else
9545 {
9546 /* The frame pointer is a stable reference within the
9547 aligned frame. Use it. */
9554 }
9555 }
9557 /* The memory may not be relative to the current CFA register,
9558 which means that we may need to generate a new pattern for
9559 use by the unwind info. */
9561 {
9565 }
9566 }
9568 /* Emit code to save registers using MOV insns.
9569 First register is stored at CFA - CFA_OFFSET. */
9570 static void
9572 {
9577 {
9580 }
9581 }
9583 /* Emit code to save SSE registers using MOV insns.
9584 First register is stored at CFA - CFA_OFFSET. */
9585 static void
9587 {
9592 {
9595 }
9596 }
9600 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9601 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9602 Don't add the note if the previously saved value will be left untouched
9603 within stack red-zone till return, as unwinders can find the same value
9604 in the register and on the stack. */
9606 static void
9608 {
9613 {
9616 }
9617 else
9618 queued_cfa_restores
9620 }
9622 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9624 static void
9626 {
9627 rtx last;
9631 ;
9636 }
9638 /* Expand prologue or epilogue stack adjustment.
9639 The pattern exist to put a dependency on all ebp-based memory accesses.
9640 STYLE should be negative if instructions should be marked as frame related,
9641 zero if %r11 register is live and cannot be freely used and positive
9642 otherwise. */
9644 static void
9647 {
9649 rtx insn;
9656 else
9657 {
9658 rtx tmp;
9659 /* r11 is used by indirect sibcall return as well, set before the
9660 epilogue and used after the epilogue. */
9663 else
9664 {
9668 }
9674 }
9681 {
9682 rtx r;
9692 }
9694 {
9697 {
9701 }
9702 }
9705 {
9710 {
9713 }
9715 {
9718 }
9719 else
9720 {
9721 /* Else there are two possibilities: SP itself, which we set
9722 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9723 taken care of this by hand along the eh_return path. */
9726 }
9730 }
9731 }
9733 /* Find an available register to be used as dynamic realign argument
9734 pointer regsiter. Such a register will be written in prologue and
9735 used in begin of body, so it must not be
9736 1. parameter passing register.
9737 2. GOT pointer.
9738 We reuse static-chain register if it is available. Otherwise, we
9739 use DI for i386 and R13 for x86-64. We chose R13 since it has
9740 shorter encoding.
9742 Return: the regno of chosen register. */
9744 static unsigned int
9746 {
9750 {
9751 /* Use R13 for nested function or function need static chain.
9752 Since function with tail call may use any caller-saved
9753 registers in epilogue, DRAP must not use caller-saved
9754 register in such case. */
9759 }
9760 else
9761 {
9762 /* Use DI for nested function or function need static chain.
9763 Since function with tail call may use any caller-saved
9764 registers in epilogue, DRAP must not use caller-saved
9765 register in such case. */
9769 /* Reuse static chain register if it isn't used for parameter
9770 passing. */
9772 {
9776 }
9778 }
9779 }
9781 /* Return minimum incoming stack alignment. */
9783 static unsigned int
9785 {
9788 /* Prefer the one specified at command line. */
9791 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9792 if -mstackrealign is used, it isn't used for sibcall check and
9793 estimated stack alignment is 128bit. */
9795 && !TARGET_64BIT
9796 && ix86_force_align_arg_pointer
9799 else
9802 /* Incoming stack alignment can be changed on individual functions
9803 via force_align_arg_pointer attribute. We use the smallest
9804 incoming stack boundary. */
9810 /* The incoming stack frame has to be aligned at least at
9811 parm_stack_boundary. */
9815 /* Stack at entrance of main is aligned by runtime. We use the
9816 smallest incoming stack boundary. */
9824 }
9826 /* Update incoming stack boundary and estimated stack alignment. */
9828 static void
9830 {
9831 ix86_incoming_stack_boundary
9834 /* x86_64 vararg needs 16byte stack alignment for register save
9835 area. */
9840 }
9842 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9843 needed or an rtx for DRAP otherwise. */
9845 static rtx
9847 {
9852 {
9853 /* Assign DRAP to vDRAP and returns vDRAP */
9855 rtx drap_vreg;
9856 rtx arg_ptr;
9869 {
9872 }
9874 }
9875 else
9877 }
9879 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9881 static rtx
9883 {
9885 }
9888 rtx reg;
9890 };
9892 /* Return a short-lived scratch register for use on function entry.
9893 In 32-bit mode, it is valid only after the registers are saved
9894 in the prologue. This register must be released by means of
9895 release_scratch_register_on_entry once it is dead. */
9897 static void
9899 {
9905 {
9906 /* We always use R11 in 64-bit mode. */
9908 }
9909 else
9910 {
9912 bool fastcall_p
9916 int drap_regno
9919 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9920 for the static chain register. */
9926 /* ecx is the static chain register. */
9932 /* esi is the static chain register. */
9938 else
9939 {
9942 }
9943 }
9947 {
9950 }
9951 }
9953 /* Release a scratch register obtained from the preceding function. */
9955 static void
9957 {
9959 {
9962 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9967 }
9968 }
9970 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9972 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9974 static void
9976 {
9977 /* We skip the probe for the first interval + a small dope of 4 words and
9978 probe that many bytes past the specified size to maintain a protection
9979 area at the botton of the stack. */
9983 /* See if we have a constant small number of probes to generate. If so,
9984 that's the easy case. The run-time loop is made up of 11 insns in the
9985 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9986 for n # of intervals. */
9988 {
9992 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9993 values of N from 1 until it exceeds SIZE. If only one probe is
9994 needed, this will not generate any code. Then adjust and probe
9995 to PROBE_INTERVAL + SIZE. */
9997 {
9999 {
10002 }
10003 else
10009 }
10013 else
10020 /* Adjust back to account for the additional first interval. */
10024 }
10026 /* Otherwise, do the same as above, but in a loop. Note that we must be
10027 extra careful with variables wrapping around because we might be at
10028 the very top (or the very bottom) of the address space and we have
10029 to be able to handle this case properly; in particular, we use an
10030 equality test for the loop condition. */
10031 else
10032 {
10033 HOST_WIDE_INT rounded_size;
10039 /* Step 1: round SIZE to the previous multiple of the interval. */
10044 /* Step 2: compute initial and final value of the loop counter. */
10046 /* SP = SP_0 + PROBE_INTERVAL. */
10051 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10055 stack_pointer_rtx)));
10058 /* Step 3: the loop
10060 while (SP != LAST_ADDR)
10061 {
10062 SP = SP + PROBE_INTERVAL
10063 probe at SP
10064 }
10066 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10067 values of N from 1 until it is equal to ROUNDED_SIZE. */
10072 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10073 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10076 {
10081 }
10083 /* Adjust back to account for the additional first interval. */
10089 }
10093 /* Even if the stack pointer isn't the CFA register, we need to correctly
10094 describe the adjustments made to it, in particular differentiate the
10095 frame-related ones from the frame-unrelated ones. */
10097 {
10110 }
10112 /* Make sure nothing is scheduled before we are done. */
10114 }
10116 /* Adjust the stack pointer up to REG while probing it. */
10120 {
10130 /* Jump to END_LAB if SP == LAST_ADDR. */
10138 /* SP = SP + PROBE_INTERVAL. */
10142 /* Probe at SP. */
10153 }
10155 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10156 inclusive. These are offsets from the current stack pointer. */
10158 static void
10160 {
10161 /* See if we have a constant small number of probes to generate. If so,
10162 that's the easy case. The run-time loop is made up of 7 insns in the
10163 generic case while the compile-time loop is made up of n insns for n #
10164 of intervals. */
10166 {
10167 HOST_WIDE_INT i;
10169 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10170 it exceeds SIZE. If only one probe is needed, this will not
10171 generate any code. Then probe at FIRST + SIZE. */
10176 }
10178 /* Otherwise, do the same as above, but in a loop. Note that we must be
10179 extra careful with variables wrapping around because we might be at
10180 the very top (or the very bottom) of the address space and we have
10181 to be able to handle this case properly; in particular, we use an
10182 equality test for the loop condition. */
10183 else
10184 {
10191 /* Step 1: round SIZE to the previous multiple of the interval. */
10196 /* Step 2: compute initial and final value of the loop counter. */
10198 /* TEST_OFFSET = FIRST. */
10201 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10205 /* Step 3: the loop
10207 while (TEST_ADDR != LAST_ADDR)
10208 {
10209 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10210 probe at TEST_ADDR
10211 }
10213 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10214 until it is equal to ROUNDED_SIZE. */
10219 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10220 that SIZE is equal to ROUNDED_SIZE. */
10224 stack_pointer_rtx,
10229 }
10231 /* Make sure nothing is scheduled before we are done. */
10233 }
10235 /* Probe a range of stack addresses from REG to END, inclusive. These are
10236 offsets from the current stack pointer. */
10240 {
10250 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10258 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10262 /* Probe at TEST_ADDR. */
10275 }
10277 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10278 to be generated in correct form. */
10279 static void
10281 {
10282 /* Check if stack realign is really needed after reload, and
10283 stores result in cfun */
10284 unsigned int incoming_stack_boundary
10288 < (current_function_is_leaf
10293 {
10294 /* After stack_realign_needed is finalized, we can't no longer
10295 change it. */
10297 }
10298 else
10299 {
10302 }
10303 }
10305 /* Expand the prologue into a bunch of separate insns. */
10307 void
10309 {
10314 HOST_WIDE_INT allocate;
10319 /* DRAP should not coexist with stack_realign_fp */
10324 /* Initialize CFA state for before the prologue. */
10328 /* Track SP offset to the CFA. We continue tracking this after we've
10329 swapped the CFA register away from SP. In the case of re-alignment
10330 this is fudged; we're interested to offsets within the local frame. */
10337 {
10338 /* We should have already generated an error for any use of
10339 ms_hook on a nested function. */
10342 /* Check if profiling is active and we shall use profiling before
10343 prologue variant. If so sorry. */
10348 /* In ix86_asm_output_function_label we emitted:
10349 8b ff movl.s %edi,%edi
10350 55 push %ebp
10351 8b ec movl.s %esp,%ebp
10353 This matches the hookable function prologue in Win32 API
10354 functions in Microsoft Windows XP Service Pack 2 and newer.
10355 Wine uses this to enable Windows apps to hook the Win32 API
10356 functions provided by Wine.
10358 What that means is that we've already set up the frame pointer. */
10362 {
10365 /* We've decided to use the frame pointer already set up.
10366 Describe this to the unwinder by pretending that both
10367 push and mov insns happen right here.
10369 Putting the unwind info here at the end of the ms_hook
10370 is done so that we can make absolutely certain we get
10371 the required byte sequence at the start of the function,
10372 rather than relying on an assembler that can produce
10373 the exact encoding required.
10375 However it does mean (in the unpatched case) that we have
10376 a 1 insn window where the asynchronous unwind info is
10377 incorrect. However, if we placed the unwind info at
10378 its correct location we would have incorrect unwind info
10379 in the patched case. Which is probably all moot since
10380 I don't expect Wine generates dwarf2 unwind info for the
10381 system libraries that use this feature. */
10387 stack_pointer_rtx);
10395 /* Note that gen_push incremented m->fs.cfa_offset, even
10396 though we didn't emit the push insn here. */
10400 }
10401 else
10402 {
10403 /* The frame pointer is not needed so pop %ebp again.
10404 This leaves us with a pristine state. */
10406 }
10407 }
10409 /* The first insn of a function that accepts its static chain on the
10410 stack is to push the register that would be filled in by a direct
10411 call. This insn will be skipped by the trampoline. */
10413 {
10417 /* We don't want to interpret this push insn as a register save,
10418 only as a stack adjustment. The real copy of the register as
10419 a save will be done later, if needed. */
10424 }
10426 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10427 of DRAP is needed and stack realignment is really needed after reload */
10429 {
10432 /* Only need to push parameter pointer reg if it is caller saved. */
10434 {
10435 /* Push arg pointer reg */
10438 }
10440 /* Grab the argument pointer. */
10447 /* Align the stack. */
10449 stack_pointer_rtx,
10453 /* Replicate the return address on the stack so that return
10454 address can be reached via (argp - 1) slot. This is needed
10455 to implement macro RETURN_ADDR_RTX and intrinsic function
10456 expand_builtin_return_addr etc. */
10462 /* For the purposes of frame and register save area addressing,
10463 we've started over with a new frame. */
10466 }
10469 {
10470 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10471 slower on all targets. Also sdb doesn't like it. */
10476 {
10484 }
10485 }
10490 {
10491 /* If saving registers via PUSH, do so now. */
10493 {
10497 }
10499 /* When using red zone we may start register saving before allocating
10500 the stack frame saving one cycle of the prologue. However, avoid
10501 doing this if we have to probe the stack; at least on x86_64 the
10502 stack probe can turn into a call that clobbers a red zone location. */
10504 && (! TARGET_STACK_PROBE
10506 {
10509 }
10510 }
10513 {
10517 /* The computation of the size of the re-aligned stack frame means
10518 that we must allocate the size of the register save area before
10519 performing the actual alignment. Otherwise we cannot guarantee
10520 that there's enough storage above the realignment point. */
10527 /* Align the stack. */
10529 stack_pointer_rtx,
10532 /* For the purposes of register save area addressing, the stack
10533 pointer is no longer valid. As for the value of sp_offset,
10534 see ix86_compute_frame_layout, which we need to match in order
10535 to pass verification of stack_pointer_offset at the end. */
10538 }
10543 {
10544 /* We start to count from ARG_POINTER. */
10547 /* If it was realigned, take into account the fake frame. */
10549 {
10556 /* This over-estimates by 1 minimal-stack-alignment-unit but
10557 mitigates that by counting in the new return address slot. */
10558 current_function_dynamic_stack_size
10560 }
10563 }
10565 /* The stack has already been decremented by the instruction calling us
10566 so probe if the size is non-negative to preserve the protection area. */
10568 {
10569 /* We expect the registers to be saved when probes are used. */
10573 {
10576 }
10577 else
10578 {
10586 else
10588 }
10589 }
10592 ;
10595 {
10599 }
10600 else
10601 {
10615 {
10618 }
10620 {
10624 }
10629 /* Use the fact that AX still contains ALLOCATE. */
10630 adjust_stack_insn = (TARGET_64BIT
10631 ? gen_pro_epilogue_adjust_stack_di_sub
10637 /* Note that SEH directives need to continue tracking the stack
10638 pointer even after the frame pointer has been set up. */
10640 {
10649 }
10653 {
10658 }
10660 {
10663 }
10664 }
10667 /* If we havn't already set up the frame pointer, do so now. */
10669 {
10681 }
10692 {
10699 }
10702 {
10704 {
10706 {
10716 }
10717 else
10719 }
10720 else
10722 }
10724 /* In the pic_reg_used case, make sure that the got load isn't deleted
10725 when mcount needs it. Blockage to avoid call movement across mcount
10726 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10727 note. */
10732 {
10733 /* vDRAP is setup but after reload it turns out stack realign
10734 isn't necessary, here we will emit prologue to setup DRAP
10735 without stack realign adjustment */
10738 }
10740 /* Prevent instructions from being scheduled into register save push
10741 sequence when access to the redzone area is done through frame pointer.
10742 The offset between the frame pointer and the stack pointer is calculated
10743 relative to the value of the stack pointer at the end of the function
10744 prologue, and moving instructions that access redzone area via frame
10745 pointer inside push sequence violates this assumption. */
10749 /* Emit cld instruction if stringops are used in the function. */
10753 /* SEH requires that the prologue end within 256 bytes of the start of
10754 the function. Prevent instruction schedules that would extend that. */
10757 }
10759 /* Emit code to restore REG using a POP insn. */
10761 static void
10763 {
10772 {
10773 /* Previously we'd represented the CFA as an expression
10774 like *(%ebp - 8). We've just popped that value from
10775 the stack, which means we need to reset the CFA to
10776 the drap register. This will remain until we restore
10777 the stack pointer. */
10781 /* This means that the DRAP register is valid for addressing too. */
10784 }
10787 {
10794 }
10796 /* When the frame pointer is the CFA, and we pop it, we are
10797 swapping back to the stack pointer as the CFA. This happens
10798 for stack frames that don't allocate other data, so we assume
10799 the stack pointer is now pointing at the return address, i.e.
10800 the function entry state, which makes the offset be 1 word. */
10802 {
10805 {
10813 }
10814 }
10815 }
10817 /* Emit code to restore saved registers using POP insns. */
10819 static void
10821 {
10827 }
10829 /* Emit code and notes for the LEAVE instruction. */
10831 static void
10833 {
10845 {
10854 }
10855 }
10857 /* Emit code to restore saved registers using MOV insns.
10858 First register is restored from CFA - CFA_OFFSET. */
10859 static void
10862 {
10868 {
10877 {
10878 /* Previously we'd represented the CFA as an expression
10879 like *(%ebp - 8). We've just popped that value from
10880 the stack, which means we need to reset the CFA to
10881 the drap register. This will remain until we restore
10882 the stack pointer. */
10886 /* This means that the DRAP register is valid for addressing. */
10888 }
10889 else
10893 }
10894 }
10896 /* Emit code to restore saved registers using MOV insns.
10897 First register is restored from CFA - CFA_OFFSET. */
10898 static void
10901 {
10906 {
10908 rtx mem;
10918 }
10919 }
10921 /* Restore function stack, frame, and registers. */
10923 void
10925 {
10936 || (current_function_sp_is_unchanging
10941 /* The FP must be valid if the frame pointer is present. */
10946 /* We must have *some* valid pointer to the stack frame. */
10949 /* The DRAP is never valid at this point. */
10952 /* See the comment about red zone and frame
10953 pointer usage in ix86_expand_prologue. */
10960 /* Determine the CFA offset of the end of the red-zone. */
10963 {
10964 /* The red-zone begins below the return address. */
10967 /* When the register save area is in the aligned portion of
10968 the stack, determine the maximum runtime displacement that
10969 matches up with the aligned frame. */
10973 }
10975 /* Special care must be taken for the normal return case of a function
10976 using eh_return: the eax and edx registers are marked as saved, but
10977 not restored along this path. Adjust the save location to match. */
10981 /* EH_RETURN requires the use of moves to function properly. */
10984 /* SEH requires the use of pops to identify the epilogue. */
10987 /* If we're only restoring one register and sp is not valid then
10988 using a move instruction to restore the register since it's
10989 less work than reloading sp and popping the register. */
11002 && TARGET_USE_LEAVE
11006 else
11010 {
11011 /* Ensure that the entire register save area is addressable via
11012 the stack pointer, if we will restore via sp. */
11017 {
11021 style,
11023 }
11024 }
11026 /* If there are any SSE registers to restore, then we have to do it
11027 via moves, since there's obviously no pop for SSE regs. */
11033 {
11034 rtx t;
11039 /* eh_return epilogues need %ecx added to the stack pointer. */
11041 {
11044 /* Stack align doesn't work with eh_return. */
11046 /* Neither does regparm nested functions. */
11050 {
11058 /* Note that we use SA as a temporary CFA, as the return
11059 address is at the proper place relative to it. We
11060 pretend this happens at the FP restore insn because
11061 prior to this insn the FP would be stored at the wrong
11062 offset relative to SA, and after this insn we have no
11063 other reasonable register to use for the CFA. We don't
11064 bother resetting the CFA to the SP for the duration of
11065 the return insn. */
11078 }
11079 else
11080 {
11088 {
11092 UNITS_PER_WORD));
11094 }
11095 }
11098 }
11099 }
11100 else
11101 {
11102 /* SEH requires that the function end with (1) a stack adjustment
11103 if necessary, (2) a sequence of pops, and (3) a return or
11104 jump instruction. Prevent insns from the function body from
11105 being scheduled into this sequence. */
11107 {
11108 /* Prevent a catch region from being adjacent to the standard
11109 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11110 several other flags that would be interesting to test are
11111 not yet set up. */
11114 else
11116 }
11118 /* First step is to deallocate the stack frame so that we can
11119 pop the registers. */
11121 {
11126 }
11128 {
11132 style,
11134 }
11137 }
11139 /* If we used a stack pointer and haven't already got rid of it,
11140 then do so now. */
11142 {
11143 /* If the stack pointer is valid and pointing at the frame
11144 pointer store address, then we only need a pop. */
11147 /* Leave results in shorter dependency chains on CPUs that are
11148 able to grok it fast. */
11153 else
11154 {
11156 hard_frame_pointer_rtx,
11159 }
11160 }
11163 {
11165 rtx insn;
11191 }
11193 /* At this point the stack pointer must be valid, and we must have
11194 restored all of the registers. We may not have deallocated the
11195 entire stack frame. We've delayed this until now because it may
11196 be possible to merge the local stack deallocation with the
11197 deallocation forced by ix86_static_chain_on_stack. */
11202 {
11206 }
11208 /* Sibcall epilogues don't want a return instruction. */
11210 {
11213 }
11215 /* Emit vzeroupper if needed. */
11222 {
11225 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11226 address, do explicit add, and jump indirectly to the caller. */
11229 {
11231 rtx insn;
11233 /* There is no "pascal" calling convention in any 64bit ABI. */
11249 }
11250 else
11252 }
11253 else
11256 /* Restore the state back to the state from the prologue,
11257 so that it's correct for the next epilogue. */
11259 }
11261 /* Reset from the function's potential modifications. */
11263 static void
11265 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11266 {
11269 #if TARGET_MACHO
11270 /* Mach-O doesn't support labels at the end of objects, so if
11271 it looks like we might want one, insert a NOP. */
11272 {
11283 }
11284 #endif
11286 }
11288 /* Return a scratch register to use in the split stack prologue. The
11289 split stack prologue is used for -fsplit-stack. It is the first
11290 instructions in the function, even before the regular prologue.
11291 The scratch register can be any caller-saved register which is not
11292 used for parameters or for the static chain. */
11294 static unsigned int
11296 {
11299 else
11300 {
11310 {
11312 {
11316 }
11318 }
11320 {
11323 else
11324 {
11326 {
11330 }
11332 }
11333 }
11334 else
11335 {
11336 /* FIXME: We could make this work by pushing a register
11337 around the addition and comparison. */
11340 }
11341 }
11342 }
11344 /* A SYMBOL_REF for the function which allocates new stackspace for
11345 -fsplit-stack. */
11349 /* A SYMBOL_REF for the more stack function when using the large
11350 model. */
11354 /* Handle -fsplit-stack. These are the first instructions in the
11355 function, even before the regular prologue. */
11357 void
11359 {
11361 HOST_WIDE_INT allocate;
11366 rtx fn;
11374 /* This is the label we will branch to if we have enough stack
11375 space. We expect the basic block reordering pass to reverse this
11376 branch if optimizing, so that we branch in the unlikely case. */
11379 /* We need to compare the stack pointer minus the frame size with
11380 the stack boundary in the TCB. The stack boundary always gives
11381 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11382 can compare directly. Otherwise we need to do an addition. */
11385 UNSPEC_STACK_CHECK);
11390 else
11391 {
11393 rtx offset;
11395 /* We need a scratch register to hold the stack pointer minus
11396 the required frame size. Since this is the very start of the
11397 function, the scratch register can be any caller-saved
11398 register which is not used for parameters. */
11405 {
11406 /* We don't use ix86_gen_add3 in this case because it will
11407 want to split to lea, but when not optimizing the insn
11408 will not be split after this point. */
11411 offset)));
11412 }
11413 else
11414 {
11417 stack_pointer_rtx));
11418 }
11420 }
11426 /* Mark the jump as very likely to be taken. */
11434 /* Get more stack space. We pass in the desired stack space and the
11435 size of the arguments to copy to the new stack. In 32-bit mode
11436 we push the parameters; __morestack will return on a new stack
11437 anyhow. In 64-bit mode we pass the parameters in r10 and
11438 r11. */
11443 {
11449 /* If this function uses a static chain, it will be in %r10.
11450 Preserve it across the call to __morestack. */
11452 {
11453 rtx rax;
11458 }
11461 {
11462 HOST_WIDE_INT argval;
11464 /* When using the large model we need to load the address
11465 into a register, and we've run out of registers. So we
11466 switch to a different calling convention, and we call a
11467 different function: __morestack_large. We pass the
11468 argument size in the upper 32 bits of r10 and pass the
11469 frame size in the lower 32 bits. */
11474 split_stack_fn_large =
11478 {
11488 UNSPEC_GOT);
11494 }
11495 else
11502 }
11503 else
11504 {
11508 }
11511 }
11512 else
11513 {
11516 }
11522 /* In order to make call/return prediction work right, we now need
11523 to execute a return instruction. See
11524 libgcc/config/i386/morestack.S for the details on how this works.
11526 For flow purposes gcc must not see this as a return
11527 instruction--we need control flow to continue at the subsequent
11528 label. Therefore, we use an unspec. */
11532 /* If we are in 64-bit mode and this function uses a static chain,
11533 we saved %r10 in %rax before calling _morestack. */
11538 /* If this function calls va_start, we need to store a pointer to
11539 the arguments on the old stack, because they may not have been
11540 all copied to the new stack. At this point the old stack can be
11541 found at the frame pointer value used by __morestack, because
11542 __morestack has set that up before calling back to us. Here we
11543 store that pointer in a scratch register, and in
11544 ix86_expand_prologue we store the scratch register in a stack
11545 slot. */
11547 {
11549 rtx frame_reg;
11556 /* 64-bit:
11557 fp -> old fp value
11558 return address within this function
11559 return address of caller of this function
11560 stack arguments
11561 So we add three words to get to the stack arguments.
11563 32-bit:
11564 fp -> old fp value
11565 return address within this function
11566 first argument to __morestack
11567 second argument to __morestack
11568 return address of caller of this function
11569 stack arguments
11570 So we add five words to get to the stack arguments.
11571 */
11582 }
11587 /* If this function calls va_start, we now have to set the scratch
11588 register for the case where we do not call __morestack. In this
11589 case we need to set it based on the stack pointer. */
11591 {
11598 }
11599 }
11601 /* We may have to tell the dataflow pass that the split stack prologue
11602 is initializing a scratch register. */
11604 static void
11606 {
11608 {
11611 }
11612 }
11613 \f
11614 /* Extract the parts of an RTL expression that is a valid memory address
11615 for an instruction. Return 0 if the structure of the address is
11616 grossly off. Return -1 if the address contains ASHIFT, so it is not
11617 strictly valid, but still used for computing length of lea instruction. */
11619 int
11621 {
11626 rtx tmp;
11633 {
11638 do
11639 {
11644 }
11651 {
11654 {
11677 && TARGET_TLS_DIRECT_SEG_REFS
11680 else
11690 else
11705 }
11706 }
11707 }
11709 {
11712 }
11714 {
11715 /* We're called for lea too, which implements ashift on occasion. */
11725 }
11726 else
11729 /* Extract the integral value of scale. */
11731 {
11735 }
11740 /* Avoid useless 0 displacement. */
11744 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11749 {
11750 rtx tmp;
11753 }
11755 /* Special case: %ebp cannot be encoded as a base without a displacement.
11756 Similarly %r13. */
11758 && base_reg
11767 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11768 Avoid this by transforming to [%esi+0].
11769 Reload calls address legitimization without cfun defined, so we need
11770 to test cfun for being non-NULL. */
11776 /* Special case: encode reg+reg instead of reg*2. */
11780 /* Special case: scaling cannot be encoded without base or displacement. */
11791 }
11792 \f
11793 /* Return cost of the memory address x.
11794 For i386, it is better to use a complex address than let gcc copy
11795 the address into a reg and make a new pseudo. But not if the address
11796 requires to two regs - that would mean more pseudos with longer
11797 lifetimes. */
11798 static int
11800 {
11812 /* Attempt to minimize number of registers in the address. */
11818 cost++;
11825 cost++;
11827 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11828 since it's predecode logic can't detect the length of instructions
11829 and it degenerates to vector decoded. Increase cost of such
11830 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11831 to split such addresses or even refuse such addresses at all.
11833 Following addressing modes are affected:
11834 [base+scale*index]
11835 [scale*index+disp]
11836 [base+index]
11838 The first and last case may be avoidable by explicitly coding the zero in
11839 memory address, but I don't have AMD-K6 machine handy to check this
11840 theory. */
11849 }
11850 \f
11851 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11852 this is used for to form addresses to local data when -fPIC is in
11853 use. */
11855 static bool
11857 {
11860 }
11862 /* Determine if a given RTX is a valid constant. We already know this
11863 satisfies CONSTANT_P. */
11865 static bool
11867 {
11869 {
11874 {
11878 }
11883 /* Only some unspecs are valid as "constants". */
11886 {
11902 }
11904 /* We must have drilled down to a symbol. */
11909 /* FALLTHRU */
11912 /* TLS symbols are never valid. */
11916 /* DLLIMPORT symbols are never valid. */
11921 #if TARGET_MACHO
11922 /* mdynamic-no-pic */
11925 #endif
11941 }
11943 /* Otherwise we handle everything else in the move patterns. */
11945 }
11947 /* Determine if it's legal to put X into the constant pool. This
11948 is not possible for the address of thread-local symbols, which
11949 is checked above. */
11951 static bool
11953 {
11954 /* We can always put integral constants and vectors in memory. */
11956 {
11964 }
11966 }
11969 /* Nonzero if the constant value X is a legitimate general operand
11970 when generating PIC code. It is given that flag_pic is on and
11971 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
11973 bool
11975 {
11976 rtx inner;
11979 {
11986 /* Only some unspecs are valid as "constants". */
11989 {
12002 }
12003 /* FALLTHRU */
12011 }
12012 }
12014 /* Determine if a given CONST RTX is a valid memory displacement
12015 in PIC mode. */
12017 bool
12019 {
12022 /* In 64bit mode we can allow direct addresses of symbols and labels
12023 when they are not dynamic symbols. */
12025 {
12029 {
12046 /* FALLTHRU */
12049 /* TLS references should always be enclosed in UNSPEC. */
12059 }
12060 }
12066 {
12067 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12068 of GOT tables. We should not need these anyway. */
12080 }
12084 {
12089 }
12098 {
12102 /* We need to check for both symbols and labels because VxWorks loads
12103 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12104 details. */
12108 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12109 While ABI specify also 32bit relocation but we don't produce it in
12110 small PIC model at all. */
12132 }
12135 }
12137 /* Recognizes RTL expressions that are valid memory addresses for an
12138 instruction. The MODE argument is the machine mode for the MEM
12139 expression that wants to use this address.
12141 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12142 convert common non-canonical forms to canonical form so that they will
12143 be recognized. */
12145 static bool
12148 {
12151 HOST_WIDE_INT scale;
12154 /* Decomposition failed. */
12162 /* Validate base register.
12164 Don't allow SUBREG's that span more than a word here. It can lead to spill
12165 failures when the base is one word out of a two word structure, which is
12166 represented internally as a DImode int. */
12169 {
12170 rtx reg;
12179 else
12180 /* Base is not a register. */
12184 /* Base is not in Pmode. */
12189 /* Base is not valid. */
12191 }
12193 /* Validate index register.
12195 Don't allow SUBREG's that span more than a word here -- same as above. */
12198 {
12199 rtx reg;
12208 else
12209 /* Index is not a register. */
12213 /* Index is not in Pmode. */
12218 /* Index is not valid. */
12220 }
12222 /* Validate scale factor. */
12224 {
12226 /* Scale without index. */
12230 /* Scale is not a valid multiplier. */
12232 }
12234 /* Validate displacement. */
12236 {
12241 {
12242 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12243 used. While ABI specify also 32bit relocations, we don't produce
12244 them at all and use IP relative instead. */
12251 /* 64bit address unspec. */
12271 /* Invalid address unspec. */
12273 }
12276 && (flag_pic
12277 || (TARGET_MACHO
12278 #if TARGET_MACHO
12279 && MACHOPIC_INDIRECT
12281 #endif
12282 )))
12283 {
12285 is_legitimate_pic:
12287 {
12288 /* foo@dtpoff(%rX) is ok. */
12295 /* Non-constant pic memory reference. */
12297 }
12300 /* Displacement is an invalid pic construct. */
12302 #if TARGET_MACHO
12305 /* displacment must be referenced via non_lazy_pointer */
12307 #endif
12309 /* This code used to verify that a symbolic pic displacement
12310 includes the pic_offset_table_rtx register.
12312 While this is good idea, unfortunately these constructs may
12313 be created by "adds using lea" optimization for incorrect
12314 code like:
12316 int a;
12317 int foo(int i)
12318 {
12319 return *(&a+i);
12320 }
12322 This code is nonsensical, but results in addressing
12323 GOT table with pic_offset_table_rtx base. We can't
12324 just refuse it easily, since it gets matched by
12325 "addsi3" pattern, that later gets split to lea in the
12326 case output register differs from input. While this
12327 can be handled by separate addsi pattern for this case
12328 that never results in lea, this seems to be easier and
12329 correct fix for crash to disable this test. */
12330 }
12337 /* Displacement is not constant. */
12341 /* Displacement is out of range. */
12343 }
12345 /* Everything looks valid. */
12347 }
12349 /* Determine if a given RTX is a valid constant address. */
12351 bool
12353 {
12355 }
12356 \f
12357 /* Return a unique alias set for the GOT. */
12359 static alias_set_type
12361 {
12366 }
12368 /* Return a legitimate reference for ORIG (an address) using the
12369 register REG. If REG is 0, a new pseudo is generated.
12371 There are two types of references that must be handled:
12373 1. Global data references must load the address from the GOT, via
12374 the PIC reg. An insn is emitted to do this load, and the reg is
12375 returned.
12377 2. Static data references, constant pool addresses, and code labels
12378 compute the address as an offset from the GOT, whose base is in
12379 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12380 differentiate them from global data objects. The returned
12381 address is the PIC reg + an unspec constant.
12383 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12384 reg also appears in the address. */
12386 static rtx
12388 {
12391 rtx base;
12393 #if TARGET_MACHO
12395 {
12398 /* Use the generic Mach-O PIC machinery. */
12400 }
12401 #endif
12408 {
12409 rtx tmpreg;
12410 /* This symbol may be referenced via a displacement from the PIC
12411 base address (@GOTOFF). */
12418 {
12420 UNSPEC_GOTOFF);
12422 }
12423 else
12428 else
12433 {
12437 }
12439 }
12441 {
12442 /* This symbol may be referenced via a displacement from the PIC
12443 base address (@GOTOFF). */
12450 {
12452 UNSPEC_GOTOFF);
12454 }
12455 else
12461 {
12464 }
12465 }
12467 /* We can't use @GOTOFF for text labels on VxWorks;
12468 see gotoff_operand. */
12470 {
12472 {
12478 {
12481 }
12482 }
12484 /* For x64 PE-COFF there is no GOT table. So we use address
12485 directly. */
12487 {
12495 }
12497 {
12505 /* Use directly gen_movsi, otherwise the address is loaded
12506 into register for CSE. We don't want to CSE this addresses,
12507 instead we CSE addresses from the GOT table, so skip this. */
12510 }
12511 else
12512 {
12513 /* This symbol must be referenced via a load from the
12514 Global Offset Table (@GOT). */
12530 }
12531 }
12532 else
12533 {
12536 {
12538 {
12541 }
12542 else
12544 }
12546 {
12549 /* We must match stuff we generate before. Assume the only
12550 unspecs that can get here are ours. Not that we could do
12551 anything with them anyway.... */
12557 }
12559 {
12562 /* Check first to see if this is a constant offset from a @GOTOFF
12563 symbol reference. */
12566 {
12568 {
12572 UNSPEC_GOTOFF);
12578 {
12581 }
12582 }
12583 else
12584 {
12587 {
12591 }
12592 }
12593 }
12594 else
12595 {
12602 else
12603 {
12605 {
12608 }
12610 }
12611 }
12612 }
12613 }
12615 }
12616 \f
12617 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12619 static rtx
12621 {
12633 }
12635 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12639 static rtx
12641 {
12643 {
12649 }
12652 }
12654 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12658 rtx
12660 {
12662 {
12663 ix86_tls_module_base_symbol
12668 }
12671 }
12673 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12674 false if we expect this to be used for a memory address and true if
12675 we expect to load the address into a register. */
12677 static rtx
12679 {
12685 {
12690 {
12693 else
12694 {
12697 }
12698 }
12701 {
12704 else
12711 }
12712 else
12713 {
12717 {
12727 }
12728 else
12730 }
12737 {
12740 else
12741 {
12744 }
12745 }
12748 {
12753 else
12759 }
12760 else
12761 {
12765 {
12773 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
12774 share the LD_BASE result with other LD model accesses. */
12776 UNSPEC_TLS_LD_BASE);
12780 }
12781 else
12783 }
12791 {
12795 }
12800 {
12802 {
12803 /* The Sun linker took the AMD64 TLS spec literally
12804 and can only handle %rax as destination of the
12805 initial executable code sequence. */
12810 }
12814 }
12816 {
12821 }
12823 {
12827 }
12828 else
12829 {
12832 }
12842 {
12846 }
12847 else
12848 {
12852 }
12862 {
12865 }
12866 else
12867 {
12871 }
12876 }
12879 }
12881 /* Create or return the unique __imp_DECL dllimport symbol corresponding
12882 to symbol DECL. */
12885 htab_t dllimport_map;
12887 static tree
12889 {
12896 tree to;
12897 rtx rtl;
12941 }
12943 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
12944 true if we require the result be a register. */
12946 static rtx
12948 {
12949 tree imp_decl;
12950 rtx x;
12959 }
12961 /* Try machine-dependent ways of modifying an illegitimate address
12962 to be legitimate. If we find one, return the new, valid address.
12963 This macro is used in only one place: `memory_address' in explow.c.
12965 OLDX is the address as it was before break_out_memory_refs was called.
12966 In some cases it is useful to look at this to decide what needs to be done.
12968 It is always safe for this macro to do nothing. It exists to recognize
12969 opportunities to optimize the output.
12971 For the 80386, we handle X+REG by loading X into a register R and
12972 using R+REG. R will go in a general reg and indexing will be used.
12973 However, if REG is a broken-out memory address or multiplication,
12974 nothing needs to be done because REG can certainly go in a general reg.
12976 When -fpic is used, special handling is needed for symbolic references.
12977 See comments by legitimize_pic_address in i386.c for details. */
12979 static rtx
12982 {
12993 {
12997 }
13000 {
13007 {
13010 }
13011 }
13016 #if TARGET_MACHO
13019 #endif
13021 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13025 {
13030 }
13033 {
13034 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13039 {
13045 }
13050 {
13056 }
13058 /* Put multiply first if it isn't already. */
13060 {
13065 }
13067 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13068 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13069 created by virtual register instantiation, register elimination, and
13070 similar optimizations. */
13072 {
13078 }
13080 /* Canonicalize
13081 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13082 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13087 {
13088 rtx constant;
13092 {
13095 }
13097 {
13100 }
13101 else
13105 {
13111 }
13112 }
13118 {
13121 }
13124 {
13127 }
13135 {
13138 }
13144 {
13152 }
13155 {
13163 }
13164 }
13167 }
13168 \f
13169 /* Print an integer constant expression in assembler syntax. Addition
13170 and subtraction are the only arithmetic that may appear in these
13171 expressions. FILE is the stdio stream to write to, X is the rtx, and
13172 CODE is the operand print code from the output string. */
13174 static void
13176 {
13180 {
13189 else
13190 {
13193 /* Mark the decl as referenced so that cgraph will
13194 output the function. */
13198 #if TARGET_MACHO
13202 #endif
13204 }
13212 /* FALLTHRU */
13223 /* This used to output parentheses around the expression,
13224 but that does not work on the 386 (either ATT or BSD assembler). */
13230 {
13231 /* We can use %d if the number is <32 bits and positive. */
13236 else
13238 }
13239 else
13240 /* We can't handle floating point constants;
13241 TARGET_PRINT_OPERAND must handle them. */
13246 /* Some assemblers need integer constants to appear first. */
13248 {
13252 }
13253 else
13254 {
13259 }
13274 {
13278 }
13283 {
13302 /* FIXME: This might be @TPOFF in Sun ld too. */
13311 else
13321 else
13327 #if TARGET_MACHO
13332 #endif
13336 }
13341 }
13342 }
13344 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13345 We need to emit DTP-relative relocations. */
13347 static void ATTRIBUTE_UNUSED
13349 {
13354 {
13362 }
13363 }
13365 /* Return true if X is a representation of the PIC register. This copes
13366 with calls from ix86_find_base_term, where the register might have
13367 been replaced by a cselib value. */
13369 static bool
13371 {
13375 else
13377 }
13379 /* Helper function for ix86_delegitimize_address.
13380 Attempt to delegitimize TLS local-exec accesses. */
13382 static rtx
13384 {
13409 {
13414 }
13420 }
13422 /* In the name of slightly smaller debug output, and to cater to
13423 general assembler lossage, recognize PIC+GOTOFF and turn it back
13424 into a direct symbol reference.
13426 On Darwin, this is necessary to avoid a crash, because Darwin
13427 has a different PIC label for each routine but the DWARF debugging
13428 information is not associated with any particular routine, so it's
13429 necessary to remove references to the PIC label from RTL stored by
13430 the DWARF output code. */
13432 static rtx
13434 {
13436 /* addend is NULL or some rtx if x is something+GOTOFF where
13437 something doesn't include the PIC register. */
13439 /* reg_addend is NULL or a multiple of some register. */
13441 /* const_addend is NULL or a const_int. */
13443 /* This is the result, or NULL. */
13452 {
13461 {
13465 }
13467 }
13474 /* %ebx + GOT/GOTOFF */
13475 ;
13477 {
13478 /* %ebx + %reg * scale + GOT/GOTOFF */
13484 else
13485 {
13488 }
13489 }
13490 else
13496 {
13499 }
13518 {
13519 /* If the rest of original X doesn't involve the PIC register, add
13520 addend and subtract pic_offset_table_rtx. This can happen e.g.
13521 for code like:
13522 leal (%ebx, %ecx, 4), %ecx
13523 ...
13524 movl foo@GOTOFF(%ecx), %edx
13525 in which case we return (%ecx - %ebx) + foo. */
13528 pic_offset_table_rtx),
13529 result);
13530 else
13532 }
13534 {
13538 }
13540 }
13542 /* If X is a machine specific address (i.e. a symbol or label being
13543 referenced as a displacement from the GOT implemented using an
13544 UNSPEC), then return the base term. Otherwise return X. */
13546 rtx
13548 {
13549 rtx term;
13552 {
13566 }
13569 }
13570 \f
13571 static void
13574 {
13578 {
13581 }
13586 {
13589 {
13608 }
13612 {
13631 }
13638 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13639 Those same assemblers have the same but opposite lossage on cmov. */
13644 else
13649 {
13662 }
13670 {
13683 }
13686 /* ??? As above. */
13695 /* ??? As above. */
13700 else
13711 }
13713 }
13715 /* Print the name of register X to FILE based on its machine mode and number.
13716 If CODE is 'w', pretend the mode is HImode.
13717 If CODE is 'b', pretend the mode is QImode.
13718 If CODE is 'k', pretend the mode is SImode.
13719 If CODE is 'q', pretend the mode is DImode.
13720 If CODE is 'x', pretend the mode is V4SFmode.
13721 If CODE is 't', pretend the mode is V8SFmode.
13722 If CODE is 'h', pretend the reg is the 'high' byte register.
13723 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13724 If CODE is 'd', duplicate the operand for AVX instruction.
13725 */
13727 void
13729 {
13744 {
13748 }
13766 else
13769 /* Irritatingly, AMD extended registers use different naming convention
13770 from the normal registers. */
13772 {
13775 {
13794 }
13796 }
13800 {
13803 {
13806 }
13807 /* FALLTHRU */
13813 /* FALLTHRU */
13816 normal:
13831 {
13836 }
13840 }
13844 {
13847 else
13849 }
13850 }
13852 /* Locate some local-dynamic symbol still in use by this function
13853 so that we can print its name in some tls_local_dynamic_base
13854 pattern. */
13856 static int
13858 {
13863 {
13866 }
13869 }
13873 {
13874 rtx insn;
13885 }
13887 /* Meaning of CODE:
13888 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
13889 C -- print opcode suffix for set/cmov insn.
13890 c -- like C, but print reversed condition
13891 F,f -- likewise, but for floating-point.
13892 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
13893 otherwise nothing
13894 R -- print the prefix for register names.
13895 z -- print the opcode suffix for the size of the current operand.
13896 Z -- likewise, with special suffixes for x87 instructions.
13897 * -- print a star (in certain assembler syntax)
13898 A -- print an absolute memory reference.
13899 w -- print the operand as if it's a "word" (HImode) even if it isn't.
13900 s -- print a shift double count, followed by the assemblers argument
13901 delimiter.
13902 b -- print the QImode name of the register for the indicated operand.
13903 %b0 would print %al if operands[0] is reg 0.
13904 w -- likewise, print the HImode name of the register.
13905 k -- likewise, print the SImode name of the register.
13906 q -- likewise, print the DImode name of the register.
13907 x -- likewise, print the V4SFmode name of the register.
13908 t -- likewise, print the V8SFmode name of the register.
13909 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
13910 y -- print "st(0)" instead of "st" as a register.
13911 d -- print duplicated register operand for AVX instruction.
13912 D -- print condition for SSE cmp instruction.
13913 P -- if PIC, print an @PLT suffix.
13914 p -- print raw symbol name.
13915 X -- don't print any sort of PIC '@' suffix for a symbol.
13916 & -- print some in-use local-dynamic symbol name.
13917 H -- print a memory address offset by 8; used for sse high-parts
13918 Y -- print condition for XOP pcom* instruction.
13919 + -- print a branch hint as 'cs' or 'ds' prefix
13920 ; -- print a semicolon (after prefixes due to bug in older gas).
13921 @ -- print a segment register of thread base pointer load
13922 */
13924 void
13926 {
13928 {
13930 {
13937 {
13942 else
13945 }
13949 {
13955 /* Intel syntax. For absolute addresses, registers should not
13956 be surrounded by braces. */
13958 {
13963 }
13968 }
14006 {
14007 /* Opcodes don't get size suffixes if using Intel opcodes. */
14012 {
14030 output_operand_lossage
14033 }
14034 }
14037 warning
14039 /* FALLTHRU */
14042 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14047 {
14049 {
14051 #ifdef HAVE_AS_IX86_FILDS
14053 #endif
14061 #ifdef HAVE_AS_IX86_FILDQ
14063 #else
14065 #endif
14070 }
14071 }
14073 {
14074 /* 387 opcodes don't get size suffixes
14075 if the operands are registers. */
14080 {
14096 }
14097 }
14098 else
14099 {
14100 output_operand_lossage
14103 }
14105 output_operand_lossage
14125 {
14128 }
14132 /* Little bit of braindamage here. The SSE compare instructions
14133 does use completely different names for the comparisons that the
14134 fp conditional moves. */
14136 {
14138 {
14185 }
14186 }
14187 else
14188 {
14190 {
14225 }
14226 }
14229 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14231 {
14233 {
14240 }
14242 }
14243 #endif
14247 {
14249 "condition code, invalid operand code "
14252 }
14257 {
14259 "condition code, invalid operand code "
14262 }
14263 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14266 #endif
14270 /* Like above, but reverse condition */
14272 /* Check to see if argument to %c is really a constant
14273 and not a condition code which needs to be reversed. */
14275 {
14277 "condition code, invalid operand "
14280 }
14285 {
14287 "condition code, invalid operand "
14290 }
14291 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14294 #endif
14299 /* It doesn't actually matter what mode we use here, as we're
14300 only going to use this for printing. */
14305 {
14306 rtx x;
14314 {
14319 {
14323 /* Emit hints only in the case default branch prediction
14324 heuristics would fail. */
14326 {
14327 /* We use 3e (DS) prefix for taken branches and
14328 2e (CS) prefix for not taken branches. */
14331 else
14333 }
14334 }
14335 }
14337 }
14341 {
14392 }
14396 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14398 #endif
14405 /* The kernel uses a different segment register for performance
14406 reasons; a system call would not have to trash the userspace
14407 segment register, which would be expensive. */
14410 else
14416 }
14417 }
14423 {
14424 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14427 {
14430 {
14439 else
14445 }
14447 /* Check for explicit size override (codes 'b', 'w' and 'k') */
14457 }
14460 /* Avoid (%rip) for call operands. */
14466 else
14468 }
14471 {
14472 REAL_VALUE_TYPE r;
14480 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14483 else
14485 }
14488 {
14489 REAL_VALUE_TYPE r;
14498 }
14500 /* These float cases don't actually occur as immediate operands. */
14502 {
14507 }
14509 else
14510 {
14511 /* We have patterns that allow zero sets of memory, for instance.
14512 In 64-bit mode, we should probably support all 8-byte vectors,
14513 since we can in fact encode that into an immediate. */
14515 {
14518 }
14521 {
14523 {
14526 }
14529 {
14532 else
14534 }
14535 }
14540 else
14542 }
14543 }
14545 static bool
14547 {
14550 }
14551 \f
14552 /* Print a memory operand whose address is ADDR. */
14554 static void
14556 {
14570 {
14581 }
14583 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14585 {
14597 }
14599 {
14600 /* Displacement only requires special attention. */
14603 {
14607 }
14610 else
14612 }
14613 else
14614 {
14616 {
14618 {
14623 else
14625 }
14631 {
14636 }
14638 }
14639 else
14640 {
14644 {
14645 /* Pull out the offset of a symbol; print any symbol itself. */
14649 {
14653 }
14661 else
14663 }
14667 {
14670 {
14674 }
14675 }
14678 else
14682 {
14687 }
14689 }
14690 }
14691 }
14693 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
14695 static bool
14697 {
14698 rtx op;
14705 {
14708 /* FIXME: This might be @TPOFF in Sun ld. */
14719 else
14731 else
14738 #if TARGET_MACHO
14744 #endif
14747 {
14752 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
14754 #else
14756 #endif
14759 }
14764 }
14767 }
14768 \f
14769 /* Split one or more double-mode RTL references into pairs of half-mode
14770 references. The RTL can be REG, offsettable MEM, integer constant, or
14771 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
14772 split and "num" is its length. lo_half and hi_half are output arrays
14773 that parallel "operands". */
14775 void
14778 {
14783 {
14792 }
14797 {
14800 /* simplify_subreg refuse to split volatile memory addresses,
14801 but we still have to handle it. */
14803 {
14806 }
14807 else
14808 {
14815 }
14816 }
14817 }
14818 \f
14819 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
14820 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
14821 is the expression of the binary operation. The output may either be
14822 emitted here, or returned to the caller, like all output_* functions.
14824 There is no guarantee that the operands are the same mode, as they
14825 might be within FLOAT or FLOAT_EXTEND expressions. */
14827 #ifndef SYSV386_COMPAT
14828 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
14829 wants to fix the assemblers because that causes incompatibility
14830 with gcc. No-one wants to fix gcc because that causes
14831 incompatibility with assemblers... You can use the option of
14832 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
14833 #define SYSV386_COMPAT 1
14834 #endif
14838 {
14844 #ifdef ENABLE_CHECKING
14845 /* Even if we do not want to check the inputs, this documents input
14846 constraints. Which helps in understanding the following code. */
14856 else
14858 #endif
14861 {
14866 else
14875 else
14884 else
14893 else
14900 }
14903 {
14905 {
14909 else
14911 }
14912 else
14913 {
14917 else
14919 }
14921 }
14925 {
14929 {
14933 }
14935 /* know operands[0] == operands[1]. */
14938 {
14941 }
14944 {
14946 /* How is it that we are storing to a dead operand[2]?
14947 Well, presumably operands[1] is dead too. We can't
14948 store the result to st(0) as st(0) gets popped on this
14949 instruction. Instead store to operands[2] (which I
14950 think has to be st(1)). st(1) will be popped later.
14951 gcc <= 2.8.1 didn't have this check and generated
14952 assembly code that the Unixware assembler rejected. */
14954 else
14957 }
14961 else
14968 {
14971 }
14974 {
14977 }
14980 {
14981 #if SYSV386_COMPAT
14982 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
14983 derived assemblers, confusingly reverse the direction of
14984 the operation for fsub{r} and fdiv{r} when the
14985 destination register is not st(0). The Intel assembler
14986 doesn't have this brain damage. Read !SYSV386_COMPAT to
14987 figure out what the hardware really does. */
14990 else
14992 #else
14994 /* As above for fmul/fadd, we can't store to st(0). */
14996 else
14998 #endif
15000 }
15003 {
15004 #if SYSV386_COMPAT
15007 else
15009 #else
15012 else
15014 #endif
15016 }
15019 {
15022 else
15025 }
15027 {
15028 #if SYSV386_COMPAT
15030 #else
15032 #endif
15033 }
15034 else
15035 {
15036 #if SYSV386_COMPAT
15038 #else
15040 #endif
15041 }
15046 }
15050 }
15052 /* Return needed mode for entity in optimize_mode_switching pass. */
15054 int
15056 {
15059 /* The mode UNINITIALIZED is used to store control word after a
15060 function call or ASM pattern. The mode ANY specify that function
15061 has no requirements on the control word and make no changes in the
15062 bits we are interested in. */
15076 {
15099 }
15102 }
15104 /* Output code to initialize control word copies used by trunc?f?i and
15105 rounding patterns. CURRENT_MODE is set to current control word,
15106 while NEW_MODE is set to new control word. */
15108 void
15110 {
15112 rtx new_mode;
15123 {
15125 {
15127 /* round toward zero (truncate) */
15133 /* round down toward -oo */
15140 /* round up toward +oo */
15147 /* mask precision exception for nearbyint() */
15154 }
15155 }
15156 else
15157 {
15159 {
15161 /* round toward zero (truncate) */
15167 /* round down toward -oo */
15173 /* round up toward +oo */
15179 /* mask precision exception for nearbyint() */
15186 }
15187 }
15193 }
15195 /* Output code for INSN to convert a float to a signed int. OPERANDS
15196 are the insn operands. The output may be [HSD]Imode and the input
15197 operand may be [SDX]Fmode. */
15201 {
15206 /* Jump through a hoop or two for DImode, since the hardware has no
15207 non-popping instruction. We used to do this a different way, but
15208 that was somewhat fragile and broke with post-reload splitters. */
15218 else
15219 {
15224 else
15228 }
15231 }
15233 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15234 have the values zero or one, indicates the ffreep insn's operand
15235 from the OPERANDS array. */
15239 {
15241 #ifdef HAVE_AS_IX86_FFREEP
15243 #else
15244 {
15254 }
15255 #endif
15258 }
15261 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15262 should be used. UNORDERED_P is true when fucom should be used. */
15266 {
15272 {
15275 }
15276 else
15277 {
15280 }
15283 {
15292 else
15294 else
15297 else
15299 }
15306 {
15308 {
15311 }
15312 else
15314 }
15317 && stack_top_dies
15320 {
15321 /* If both the top of the 387 stack dies, and the other operand
15322 is also a stack register that dies, then this must be a
15323 `fcompp' float compare */
15326 {
15327 /* There is no double popping fcomi variant. Fortunately,
15328 eflags is immune from the fstp's cc clobbering. */
15331 else
15334 }
15335 else
15336 {
15339 else
15341 }
15342 }
15343 else
15344 {
15345 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15348 {
15356 NULL,
15357 NULL,
15364 NULL,
15365 NULL,
15366 NULL,
15367 NULL
15368 };
15383 }
15384 }
15386 void
15388 {
15391 #ifdef ASM_QUAD
15394 #else
15396 #endif
15399 }
15401 void
15403 {
15406 #ifdef ASM_QUAD
15409 #else
15411 #endif
15412 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
15418 #if TARGET_MACHO
15420 {
15424 }
15425 #endif
15426 else
15429 }
15430 \f
15431 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
15432 for the target. */
15434 void
15436 {
15437 rtx tmp;
15439 /* We play register width games, which are only valid after reload. */
15442 /* Avoid HImode and its attendant prefix byte. */
15447 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
15449 {
15452 }
15455 }
15457 /* X is an unchanging MEM. If it is a constant pool reference, return
15458 the constant pool rtx, else NULL. */
15460 rtx
15462 {
15469 }
15471 void
15473 {
15481 {
15484 {
15489 }
15493 }
15497 {
15510 {
15516 }
15517 }
15521 {
15523 {
15524 #if TARGET_MACHO
15525 /* dynamic-no-pic */
15527 {
15528 rtx temp = ((reload_in_progress
15536 }
15538 {
15542 }
15545 else
15546 {
15554 }
15555 /* dynamic-no-pic */
15556 #endif
15557 }
15558 else
15559 {
15563 {
15568 }
15569 }
15570 }
15571 else
15572 {
15583 /* Force large constants in 64bit compilation into register
15584 to get them CSEed. */
15596 {
15597 /* If we are loading a floating point constant to a register,
15598 force the value to memory now, since we'll get better code
15599 out the back end. */
15603 {
15608 }
15609 }
15610 }
15613 }
15615 void
15617 {
15621 /* Force constants other than zero into memory. We do not know how
15622 the instructions used to build constants modify the upper 64 bits
15623 of the register, once we have that information we may be able
15624 to handle some of them more efficiently. */
15633 /* We need to check memory alignment for SSE mode since attribute
15634 can make operands unaligned. */
15639 {
15642 /* ix86_expand_vector_move_misalign() does not like constants ... */
15648 /* ... nor both arguments in memory. */
15656 }
15658 /* Make operand1 a register if it isn't already. */
15662 {
15665 }
15668 }
15670 /* Split 32-byte AVX unaligned load and store if needed. */
15672 static void
15674 {
15675 rtx m;
15681 {
15699 }
15702 {
15709 }
15711 {
15716 }
15717 else
15719 }
15721 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
15722 straight to ix86_expand_vector_move. */
15723 /* Code generation for scalar reg-reg moves of single and double precision data:
15724 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
15725 movaps reg, reg
15726 else
15727 movss reg, reg
15728 if (x86_sse_partial_reg_dependency == true)
15729 movapd reg, reg
15730 else
15731 movsd reg, reg
15733 Code generation for scalar loads of double precision data:
15734 if (x86_sse_split_regs == true)
15735 movlpd mem, reg (gas syntax)
15736 else
15737 movsd mem, reg
15739 Code generation for unaligned packed loads of single precision data
15740 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
15741 if (x86_sse_unaligned_move_optimal)
15742 movups mem, reg
15744 if (x86_sse_partial_reg_dependency == true)
15745 {
15746 xorps reg, reg
15747 movlps mem, reg
15748 movhps mem+8, reg
15749 }
15750 else
15751 {
15752 movlps mem, reg
15753 movhps mem+8, reg
15754 }
15756 Code generation for unaligned packed loads of double precision data
15757 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
15758 if (x86_sse_unaligned_move_optimal)
15759 movupd mem, reg
15761 if (x86_sse_split_regs == true)
15762 {
15763 movlpd mem, reg
15764 movhpd mem+8, reg
15765 }
15766 else
15767 {
15768 movsd mem, reg
15769 movhpd mem+8, reg
15770 }
15771 */
15773 void
15775 {
15782 {
15784 {
15788 {
15790 /* If we're optimizing for size, movups is the smallest. */
15792 {
15797 }
15809 }
15816 {
15825 {
15830 }
15838 }
15843 }
15846 }
15849 {
15850 /* If we're optimizing for size, movups is the smallest. */
15853 {
15858 }
15860 /* ??? If we have typed data, then it would appear that using
15861 movdqu is the only way to get unaligned data loaded with
15862 integer type. */
15864 {
15869 }
15872 {
15873 rtx zero;
15876 {
15881 }
15883 /* When SSE registers are split into halves, we can avoid
15884 writing to the top half twice. */
15886 {
15889 }
15890 else
15891 {
15892 /* ??? Not sure about the best option for the Intel chips.
15893 The following would seem to satisfy; the register is
15894 entirely cleared, breaking the dependency chain. We
15895 then store to the upper half, with a dependency depth
15896 of one. A rumor has it that Intel recommends two movsd
15897 followed by an unpacklpd, but this is unconfirmed. And
15898 given that the dependency depth of the unpacklpd would
15899 still be one, I'm not sure why this would be better. */
15901 }
15907 }
15908 else
15909 {
15911 {
15916 }
15920 else
15929 }
15930 }
15932 {
15933 /* If we're optimizing for size, movups is the smallest. */
15936 {
15941 }
15943 /* ??? Similar to above, only less clear because of quote
15944 typeless stores unquote. */
15947 {
15952 }
15955 {
15957 {
15961 }
15962 else
15963 {
15968 }
15969 }
15970 else
15971 {
15976 {
15979 }
15980 else
15981 {
15986 }
15987 }
15988 }
15989 else
15991 }
15993 /* Expand a push in MODE. This is some mode for which we do not support
15994 proper push instructions, at least from the registers that we expect
15995 the value to live in. */
15997 void
15999 {
16000 rtx tmp;
16010 /* When we push an operand onto stack, it has to be aligned at least
16011 at the function argument boundary. However since we don't have
16012 the argument type, we can't determine the actual argument
16013 boundary. */
16015 }
16017 /* Helper function of ix86_fixup_binary_operands to canonicalize
16018 operand order. Returns true if the operands should be swapped. */
16020 static bool
16022 rtx operands[])
16023 {
16028 /* If the operation is not commutative, we can't do anything. */
16032 /* Highest priority is that src1 should match dst. */
16038 /* Next highest priority is that immediate constants come second. */
16044 /* Lowest priority is that memory references should come second. */
16051 }
16054 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16055 destination to use for the operation. If different from the true
16056 destination in operands[0], a copy operation will be required. */
16058 rtx
16060 rtx operands[])
16061 {
16066 /* Canonicalize operand order. */
16068 {
16069 rtx temp;
16071 /* It is invalid to swap operands of different modes. */
16077 }
16079 /* Both source operands cannot be in memory. */
16081 {
16082 /* Optimization: Only read from memory once. */
16084 {
16087 }
16088 else
16090 }
16092 /* If the destination is memory, and we do not have matching source
16093 operands, do things in registers. */
16097 /* Source 1 cannot be a constant. */
16101 /* Source 1 cannot be a non-matching memory. */
16108 }
16110 /* Similarly, but assume that the destination has already been
16111 set up properly. */
16113 void
16116 {
16119 }
16121 /* Attempt to expand a binary operator. Make the expansion closer to the
16122 actual machine, then just general_operand, which will allow 3 separate
16123 memory references (one output, two input) in a single insn. */
16125 void
16127 rtx operands[])
16128 {
16135 /* Emit the instruction. */
16139 {
16140 /* Reload doesn't know about the flags register, and doesn't know that
16141 it doesn't want to clobber it. We can only do this with PLUS. */
16144 }
16148 {
16149 /* This is going to be an LEA; avoid splitting it later. */
16151 }
16152 else
16153 {
16156 }
16158 /* Fix up the destination if needed. */
16161 }
16163 /* Return TRUE or FALSE depending on whether the binary operator meets the
16164 appropriate constraints. */
16166 bool
16169 {
16174 /* Both source operands cannot be in memory. */
16178 /* Canonicalize operand order for commutative operators. */
16180 {
16184 }
16186 /* If the destination is memory, we must have a matching source operand. */
16190 /* Source 1 cannot be a constant. */
16194 /* Source 1 cannot be a non-matching memory. */
16196 {
16197 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16205 }
16208 }
16210 /* Attempt to expand a unary operator. Make the expansion closer to the
16211 actual machine, then just general_operand, which will allow 2 separate
16212 memory references (one output, one input) in a single insn. */
16214 void
16216 rtx operands[])
16217 {
16224 /* If the destination is memory, and we do not have matching source
16225 operands, do things in registers. */
16228 {
16231 else
16233 }
16235 /* When source operand is memory, destination must match. */
16239 /* Emit the instruction. */
16243 {
16244 /* Reload doesn't know about the flags register, and doesn't know that
16245 it doesn't want to clobber it. */
16248 }
16249 else
16250 {
16253 }
16255 /* Fix up the destination if needed. */
16258 }
16260 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16261 divisor are within the range [0-255]. */
16263 void
16266 {
16275 {
16288 }
16295 /* Use 8bit unsigned divimod if dividend and divisor are within
16296 the range [0-255]. */
16305 pc_rtx);
16310 /* Generate original signed/unsigned divimod. */
16315 /* Branch to the end. */
16319 /* Generate 8bit unsigned divide. */
16321 /* Don't use operands[0] for result of 8bit divide since not all
16322 registers support QImode ZERO_EXTRACT. */
16329 {
16332 }
16333 else
16334 {
16337 }
16339 /* Extract remainder from AH. */
16343 else
16344 {
16345 /* Need a new scratch register since the old one has result
16346 of 8bit divide. */
16350 }
16353 /* Zero extend quotient from AL. */
16359 }
16361 #define LEA_SEARCH_THRESHOLD 12
16363 /* Search backward for non-agu definition of register number REGNO1
16364 or register number REGNO2 in INSN's basic block until
16365 1. Pass LEA_SEARCH_THRESHOLD instructions, or
16366 2. Reach BB boundary, or
16367 3. Reach agu definition.
16368 Returns the distance between the non-agu definition point and INSN.
16369 If no definition point, returns -1. */
16371 static int
16373 rtx insn)
16374 {
16381 {
16384 {
16386 {
16387 distance++;
16393 {
16397 }
16398 }
16402 }
16403 }
16406 {
16407 edge e;
16408 edge_iterator ei;
16413 {
16416 }
16419 {
16424 {
16426 {
16427 distance++;
16433 {
16437 }
16438 }
16440 }
16441 }
16442 }
16446 done:
16447 /* get_attr_type may modify recog data. We want to make sure
16448 that recog data is valid for instruction INSN, on which
16449 distance_non_agu_define is called. INSN is unchanged here. */
16452 }
16454 /* Return the distance between INSN and the next insn that uses
16455 register number REGNO0 in memory address. Return -1 if no such
16456 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
16458 static int
16460 {
16467 {
16470 {
16472 {
16473 distance++;
16479 {
16480 /* Return DISTANCE if OP0 is used in memory
16481 address in NEXT. */
16483 }
16489 {
16490 /* Return -1 if OP0 is set in NEXT. */
16492 }
16493 }
16497 }
16498 }
16501 {
16502 edge e;
16503 edge_iterator ei;
16508 {
16511 }
16514 {
16519 {
16521 {
16522 distance++;
16528 {
16529 /* Return DISTANCE if OP0 is used in memory
16530 address in NEXT. */
16532 }
16538 {
16539 /* Return -1 if OP0 is set in NEXT. */
16541 }
16543 }
16545 }
16546 }
16547 }
16550 }
16552 /* Define this macro to tune LEA priority vs ADD, it take effect when
16553 there is a dilemma of choicing LEA or ADD
16554 Negative value: ADD is more preferred than LEA
16555 Zero: Netrual
16556 Positive value: LEA is more preferred than ADD*/
16557 #define IX86_LEA_PRIORITY 2
16559 /* Return true if it is ok to optimize an ADD operation to LEA
16560 operation to avoid flag register consumation. For most processors,
16561 ADD is faster than LEA. For the processors like ATOM, if the
16562 destination register of LEA holds an actual address which will be
16563 used soon, LEA is better and otherwise ADD is better. */
16565 bool
16567 {
16572 /* If a = b + c, (a!=b && a!=c), must use lea form. */
16578 else
16579 {
16582 /* Return false if REGNO0 isn't used in memory address. */
16591 /* If this insn has both backward non-agu dependence and forward
16592 agu dependence, the one with short distance take effect. */
16597 }
16598 }
16600 /* Return true if destination reg of SET_BODY is shift count of
16601 USE_BODY. */
16603 static bool
16605 {
16606 rtx set_dest;
16607 rtx shift_rtx;
16610 /* Retrieve destination of SET_BODY. */
16612 {
16621 use_body))
16626 }
16628 /* Retrieve shift count of USE_BODY. */
16630 {
16642 }
16650 {
16653 /* Return true if shift count is dest of SET_BODY. */
16657 }
16660 }
16662 /* Return true if destination reg of SET_INSN is shift count of
16663 USE_INSN. */
16665 bool
16667 {
16670 }
16672 /* Return TRUE or FALSE depending on whether the unary operator meets the
16673 appropriate constraints. */
16675 bool
16679 {
16680 /* If one of operands is memory, source and destination must match. */
16686 }
16688 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
16689 are ok, keeping in mind the possible movddup alternative. */
16691 bool
16693 {
16699 }
16701 /* Post-reload splitter for converting an SF or DFmode value in an
16702 SSE register into an unsigned SImode. */
16704 void
16706 {
16717 /* Load up the value into the low element. We must ensure that the other
16718 elements are valid floats -- zero is the easiest such value. */
16720 {
16723 else
16725 }
16726 else
16727 {
16732 else
16734 }
16754 else
16759 }
16761 /* Convert an unsigned DImode value into a DFmode, using only SSE.
16762 Expects the 64-bit DImode to be supplied in a pair of integral
16763 registers. Requires SSE2; will use SSE3 if available. For x86_32,
16764 -mfpmath=sse, !optimize_size only. */
16766 void
16768 {
16772 rtx x;
16778 {
16781 }
16782 else
16783 {
16787 }
16795 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
16798 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
16799 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
16800 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
16801 (0x1.0p84 + double(fp_value_hi_xmm)).
16802 Note these exponents differ by 32. */
16806 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
16807 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
16816 /* Add the upper and lower DFmode values together. */
16819 else
16820 {
16824 }
16827 }
16829 /* Not used, but eases macroization of patterns. */
16830 void
16832 rtx input ATTRIBUTE_UNUSED)
16833 {
16835 }
16837 /* Convert an unsigned SImode value into a DFmode. Only currently used
16838 for SSE, but applicable anywhere. */
16840 void
16842 {
16843 REAL_VALUE_TYPE TWO31r;
16858 }
16860 /* Convert a signed DImode value into a DFmode. Only used for SSE in
16861 32-bit mode; otherwise we have a direct convert instruction. */
16863 void
16865 {
16866 REAL_VALUE_TYPE TWO32r;
16884 }
16886 /* Convert an unsigned SImode value into a SFmode, using only SSE.
16887 For x86_32, -mfpmath=sse, !optimize_size only. */
16888 void
16890 {
16891 REAL_VALUE_TYPE ONE16r;
16910 }
16912 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
16913 then replicate the value for all elements of the vector
16914 register. */
16916 rtx
16918 {
16919 rtvec v;
16921 {
16936 else
16946 else
16954 else
16962 else
16968 }
16969 }
16971 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
16972 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
16973 for an SSE register. If VECT is true, then replicate the mask for
16974 all elements of the vector register. If INVERT is true, then create
16975 a mask excluding the sign bit. */
16977 rtx
16979 {
16983 rtx v;
16984 rtx mask;
16986 /* Find the sign bit, sign extended to 2*HWI. */
16988 {
17006 else
17014 {
17017 }
17018 else
17019 {
17020 rtvec vec;
17026 {
17029 }
17030 else
17040 }
17045 }
17050 /* Force this value into the low part of a fp vector constant. */
17059 }
17061 /* Generate code for floating point ABS or NEG. */
17063 void
17065 rtx operands[])
17066 {
17077 {
17083 }
17085 /* NEG and ABS performed with SSE use bitwise mask operations.
17086 Create the appropriate mask now. */
17089 else
17099 {
17101 rtvec par;
17106 else
17107 {
17110 }
17112 }
17113 else
17115 }
17117 /* Expand a copysign operation. Special case operand 0 being a constant. */
17119 void
17121 {
17135 else
17139 {
17146 {
17149 else
17150 {
17154 }
17155 }
17165 else
17169 }
17170 else
17171 {
17181 else
17185 }
17186 }
17188 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
17189 be a constant, and so has already been expanded into a vector constant. */
17191 void
17193 {
17209 {
17212 }
17213 }
17215 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
17216 so we have to do two masks. */
17218 void
17220 {
17235 {
17236 /* Shouldn't happen often (it's useless, obviously), but when it does
17237 we'd generate incorrect code if we continue below. */
17240 }
17243 {
17254 }
17255 else
17256 {
17258 {
17260 }
17262 {
17266 }
17270 {
17273 }
17275 {
17280 }
17282 }
17286 }
17288 /* Return TRUE or FALSE depending on whether the first SET in INSN
17289 has source and destination with matching CC modes, and that the
17290 CC mode is at least as constrained as REQ_MODE. */
17292 bool
17294 {
17295 rtx set;
17306 {
17316 /* FALLTHRU */
17320 /* FALLTHRU */
17324 /* FALLTHRU */
17338 }
17341 }
17343 /* Generate insn patterns to do an integer compare of OPERANDS. */
17345 static rtx
17347 {
17354 /* This is very simple, but making the interface the same as in the
17355 FP case makes the rest of the code easier. */
17359 /* Return the test that should be put into the flags user, i.e.
17360 the bcc, scc, or cmov instruction. */
17362 }
17364 /* Figure out whether to use ordered or unordered fp comparisons.
17365 Return the appropriate mode to use. */
17367 enum machine_mode
17369 {
17370 /* ??? In order to make all comparisons reversible, we do all comparisons
17371 non-trapping when compiling for IEEE. Once gcc is able to distinguish
17372 all forms trapping and nontrapping comparisons, we can make inequality
17373 comparisons trapping again, since it results in better code when using
17374 FCOM based compares. */
17376 }
17378 enum machine_mode
17380 {
17384 {
17387 }
17390 {
17391 /* Only zero flag is needed. */
17395 /* Codes needing carry flag. */
17398 /* Detect overflow checks. They need just the carry flag. */
17402 else
17406 /* Detect overflow checks. They need just the carry flag. */
17410 else
17412 /* Codes possibly doable only with sign flag when
17413 comparing against zero. */
17418 else
17419 /* For other cases Carry flag is not required. */
17421 /* Codes doable only with sign flag when comparing
17422 against zero, but we miss jump instruction for it
17423 so we need to use relational tests against overflow
17424 that thus needs to be zero. */
17429 else
17431 /* strcmp pattern do (use flags) and combine may ask us for proper
17432 mode. */
17437 }
17438 }
17440 /* Return the fixed registers used for condition codes. */
17442 static bool
17444 {
17448 }
17450 /* If two condition code modes are compatible, return a condition code
17451 mode which is compatible with both. Otherwise, return
17452 VOIDmode. */
17454 static enum machine_mode
17456 {
17468 {
17482 {
17496 }
17500 /* These are only compatible with themselves, which we already
17501 checked above. */
17503 }
17504 }
17507 /* Return a comparison we can do and that it is equivalent to
17508 swap_condition (code) apart possibly from orderedness.
17509 But, never change orderedness if TARGET_IEEE_FP, returning
17510 UNKNOWN in that case if necessary. */
17512 static enum rtx_code
17514 {
17516 {
17527 }
17528 }
17530 /* Return cost of comparison CODE using the best strategy for performance.
17531 All following functions do use number of instructions as a cost metrics.
17532 In future this should be tweaked to compute bytes for optimize_size and
17533 take into account performance of various instructions on various CPUs. */
17535 static int
17537 {
17540 /* The cost of code using bit-twiddling on %ah. */
17542 {
17565 }
17568 {
17575 }
17576 }
17578 /* Return strategy to use for floating-point. We assume that fcomi is always
17579 preferrable where available, since that is also true when looking at size
17580 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
17582 enum ix86_fpcmp_strategy
17584 {
17585 /* Do fcomi/sahf based test when profitable. */
17594 }
17596 /* Swap, force into registers, or otherwise massage the two operands
17597 to a fp comparison. The operands are updated in place; the new
17598 comparison code is returned. */
17600 static enum rtx_code
17602 {
17608 /* All of the unordered compare instructions only work on registers.
17609 The same is true of the fcomi compare instructions. The XFmode
17610 compare instructions require registers except when comparing
17611 against zero or when converting operand 1 from fixed point to
17612 floating point. */
17621 {
17624 }
17625 else
17626 {
17627 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
17628 things around if they appear profitable, otherwise force op0
17629 into a register. */
17635 {
17638 {
17639 rtx tmp;
17642 }
17643 }
17649 {
17654 {
17657 }
17658 else
17660 }
17661 }
17663 /* Try to rearrange the comparison to make it cheaper. */
17667 {
17668 rtx tmp;
17673 }
17678 }
17680 /* Convert comparison codes we use to represent FP comparison to integer
17681 code that will result in proper branch. Return UNKNOWN if no such code
17682 is available. */
17684 enum rtx_code
17686 {
17688 {
17711 }
17712 }
17714 /* Generate insn patterns to do a floating point compare of OPERANDS. */
17716 static rtx
17718 {
17725 /* Do fcomi/sahf based test when profitable. */
17727 {
17732 tmp);
17740 tmp);
17749 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
17756 /* In the unordered case, we have to check C2 for NaN's, which
17757 doesn't happen to work out to anything nice combination-wise.
17758 So do some bit twiddling on the value we've got in AH to come
17759 up with an appropriate set of condition codes. */
17763 {
17767 {
17770 }
17771 else
17772 {
17778 }
17783 {
17788 }
17789 else
17790 {
17793 }
17798 {
17801 }
17802 else
17803 {
17807 }
17812 {
17818 }
17819 else
17820 {
17823 }
17828 {
17833 }
17834 else
17835 {
17838 }
17843 {
17848 }
17849 else
17850 {
17853 }
17867 }
17872 }
17874 /* Return the test that should be put into the flags user, i.e.
17875 the bcc, scc, or cmov instruction. */
17878 const0_rtx);
17879 }
17881 static rtx
17883 {
17884 rtx ret;
17890 {
17893 }
17894 else
17898 }
17900 void
17902 {
17904 rtx tmp;
17907 {
17914 simple:
17918 pc_rtx);
17926 /* Expand DImode branch into multiple compare+branch. */
17927 {
17933 {
17936 }
17943 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
17944 avoid two branches. This costs one extra insn, so disable when
17945 optimizing for size. */
17950 {
17968 }
17970 /* Otherwise, if we are doing less-than or greater-or-equal-than,
17971 op1 is a constant and the low word is zero, then we can just
17972 examine the high word. Similarly for low word -1 and
17973 less-or-equal-than or greater-than. */
17977 {
17980 {
17983 }
17987 {
17990 }
17994 }
17996 /* Otherwise, we need two or three jumps. */
18005 {
18019 }
18021 /*
18022 * a < b =>
18023 * if (hi(a) < hi(b)) goto true;
18024 * if (hi(a) > hi(b)) goto false;
18025 * if (lo(a) < lo(b)) goto true;
18026 * false:
18027 */
18039 }
18044 }
18045 }
18047 /* Split branch based on floating point condition. */
18048 void
18051 {
18052 rtx condition;
18053 rtx i;
18056 {
18061 }
18064 tmp);
18066 /* Remove pushed operand from stack. */
18076 }
18078 void
18080 {
18081 rtx ret;
18088 }
18090 /* Expand comparison setting or clearing carry flag. Return true when
18091 successful and set pop for the operation. */
18092 static bool
18094 {
18098 /* Do not handle double-mode compares that go through special path. */
18103 {
18108 /* Shortcut: following common codes never translate
18109 into carry flag compares. */
18114 /* These comparisons require zero flag; swap operands so they won't. */
18117 {
18122 }
18124 /* Try to expand the comparison and verify that we end up with
18125 carry flag based comparison. This fails to be true only when
18126 we decide to expand comparison using arithmetic that is not
18127 too common scenario. */
18136 else
18145 }
18151 {
18156 /* Convert a==0 into (unsigned)a<1. */
18165 /* Convert a>b into b<a or a>=b-1. */
18169 {
18171 /* Bail out on overflow. We still can swap operands but that
18172 would force loading of the constant into register. */
18177 }
18178 else
18179 {
18184 }
18187 /* Convert a>=0 into (unsigned)a<0x80000000. */
18205 }
18206 /* Swapping operands may cause constant to appear as first operand. */
18208 {
18212 }
18216 }
18218 bool
18220 {
18239 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
18240 HImode insns, we'd be swallowed in word prefix ops. */
18246 {
18250 HOST_WIDE_INT diff;
18253 /* Sign bit compares are better done using shifts than we do by using
18254 sbb. */
18257 {
18258 /* Detect overlap between destination and compare sources. */
18262 {
18263 rtx flags;
18272 {
18274 compare_code
18276 }
18278 /* To simplify rest of code, restrict to the GEU case. */
18280 {
18286 }
18287 else
18288 {
18291 reverse_condition_maybe_unordered
18293 else
18296 }
18305 else
18308 }
18309 else
18310 {
18313 else
18314 {
18319 }
18321 }
18324 {
18325 /*
18326 * cmpl op0,op1
18327 * sbbl dest,dest
18328 * [addl dest, ct]
18329 *
18330 * Size 5 - 8.
18331 */
18336 }
18338 {
18339 /*
18340 * cmpl op0,op1
18341 * sbbl dest,dest
18342 * orl $ct, dest
18343 *
18344 * Size 8.
18345 */
18349 }
18351 {
18352 /*
18353 * cmpl op0,op1
18354 * sbbl dest,dest
18355 * notl dest
18356 * [addl dest, cf]
18357 *
18358 * Size 8 - 11.
18359 */
18365 }
18366 else
18367 {
18368 /*
18369 * cmpl op0,op1
18370 * sbbl dest,dest
18371 * [notl dest]
18372 * andl cf - ct, dest
18373 * [addl dest, ct]
18374 *
18375 * Size 8 - 11.
18376 */
18379 {
18383 }
18393 }
18399 }
18402 {
18405 HOST_WIDE_INT tmp;
18410 {
18413 /* We may be reversing unordered compare to normal compare, that
18414 is not valid in general (we may convert non-trapping condition
18415 to trapping one), however on i386 we currently emit all
18416 comparisons unordered. */
18419 }
18420 else
18421 {
18424 }
18425 }
18430 {
18435 {
18440 }
18441 }
18443 /* Optimize dest = (op0 < 0) ? -1 : cf. */
18447 {
18448 /* If lea code below could be used, only optimize
18449 if it results in a 2 insn sequence. */
18455 {
18456 /*
18457 * notl op1 (if necessary)
18458 * sarl $31, op1
18459 * orl cf, op1
18460 */
18462 {
18466 }
18477 }
18478 }
18486 {
18487 /*
18488 * xorl dest,dest
18489 * cmpl op1,op2
18490 * setcc dest
18491 * lea cf(dest*(ct-cf)),dest
18492 *
18493 * Size 14.
18494 *
18495 * This also catches the degenerate setcc-only case.
18496 */
18498 rtx tmp;
18504 /* On x86_64 the lea instruction operates on Pmode, so we need
18505 to get arithmetics done in proper mode to match. */
18508 else
18509 {
18510 rtx out1;
18513 nops++;
18515 {
18517 nops++;
18518 }
18519 }
18521 {
18523 nops++;
18524 }
18526 {
18529 else
18531 }
18536 }
18538 /*
18539 * General case: Jumpful:
18540 * xorl dest,dest cmpl op1, op2
18541 * cmpl op1, op2 movl ct, dest
18542 * setcc dest jcc 1f
18543 * decl dest movl cf, dest
18544 * andl (cf-ct),dest 1:
18545 * addl ct,dest
18546 *
18547 * Size 20. Size 14.
18548 *
18549 * This is reasonably steep, but branch mispredict costs are
18550 * high on modern cpus, so consider failing only if optimizing
18551 * for space.
18552 */
18557 {
18559 {
18566 {
18569 /* We may be reversing unordered compare to normal compare,
18570 that is not valid in general (we may convert non-trapping
18571 condition to trapping one), however on i386 we currently
18572 emit all comparisons unordered. */
18574 }
18575 else
18576 {
18580 }
18581 }
18584 {
18585 /* notl op1 (if needed)
18586 sarl $31, op1
18587 andl (cf-ct), op1
18588 addl ct, op1
18590 For x < 0 (resp. x <= -1) there will be no notl,
18591 so if possible swap the constants to get rid of the
18592 complement.
18593 True/false will be -1/0 while code below (store flag
18594 followed by decrement) is 0/-1, so the constants need
18595 to be exchanged once more. */
18598 {
18601 }
18602 else
18603 {
18607 }
18610 }
18611 else
18612 {
18616 constm1_rtx,
18618 }
18630 }
18631 }
18634 {
18635 /* Try a few things more with specific constants and a variable. */
18637 optab op;
18643 /* If one of the two operands is an interesting constant, load a
18644 constant with the above and mask it in with a logical operation. */
18647 {
18653 else
18655 }
18657 {
18663 else
18665 }
18666 else
18673 /* Recurse to get the constant loaded. */
18677 /* Mask in the interesting variable. */
18679 OPTAB_WIDEN);
18684 }
18686 /*
18687 * For comparison with above,
18688 *
18689 * movl cf,dest
18690 * movl ct,tmp
18691 * cmpl op1,op2
18692 * cmovcc tmp,dest
18693 *
18694 * Size 15.
18695 */
18717 }
18719 /* Swap, force into registers, or otherwise massage the two operands
18720 to an sse comparison with a mask result. Thus we differ a bit from
18721 ix86_prepare_fp_compare_args which expects to produce a flags result.
18723 The DEST operand exists to help determine whether to commute commutative
18724 operators. The POP0/POP1 operands are updated in place. The new
18725 comparison code is returned, or UNKNOWN if not implementable. */
18727 static enum rtx_code
18730 {
18731 rtx tmp;
18734 {
18737 /* We have no LTGT as an operator. We could implement it with
18738 NE & ORDERED, but this requires an extra temporary. It's
18739 not clear that it's worth it. */
18746 /* These are supported directly. */
18753 /* For commutative operators, try to canonicalize the destination
18754 operand to be first in the comparison - this helps reload to
18755 avoid extra moves. */
18758 /* FALLTHRU */
18764 /* These are not supported directly. Swap the comparison operands
18765 to transform into something that is supported. */
18774 }
18777 }
18779 /* Detect conditional moves that exactly match min/max operational
18780 semantics. Note that this is IEEE safe, as long as we don't
18781 interchange the operands.
18783 Returns FALSE if this conditional move doesn't match a MIN/MAX,
18784 and TRUE if the operation is successful and instructions are emitted. */
18786 static bool
18789 {
18792 rtx tmp;
18795 ;
18797 {
18801 }
18802 else
18809 else
18814 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
18815 but MODE may be a vector mode and thus not appropriate. */
18817 {
18819 rtvec v;
18824 }
18825 else
18826 {
18829 }
18833 }
18835 /* Expand an sse vector comparison. Return the register with the result. */
18837 static rtx
18840 {
18842 rtx x;
18857 }
18859 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
18860 operations. This is used for both scalar and vector conditional moves. */
18862 static void
18864 {
18869 {
18873 }
18875 {
18880 }
18882 {
18885 op_true,
18886 op_false));
18888 }
18889 else
18890 {
18897 else
18909 }
18910 }
18912 /* Expand a floating-point conditional move. Return true if successful. */
18914 bool
18916 {
18924 {
18927 /* Since we've no cmove for sse registers, don't force bad register
18928 allocation just to gain access to it. Deny movcc when the
18929 comparison mode doesn't match the move mode. */
18948 }
18950 /* The floating point conditional move instructions don't directly
18951 support conditions resulting from a signed integer comparison. */
18955 {
18960 }
18967 }
18969 /* Expand a floating-point vector conditional move; a vcond operation
18970 rather than a movcc operation. */
18972 bool
18974 {
18976 rtx cmp;
18991 }
18993 /* Expand a signed/unsigned integral vector conditional move. */
18995 bool
18997 {
19006 /* XOP supports all of the comparisons on all vector int types. */
19008 {
19009 /* Canonicalize the comparison to EQ, GT, GTU. */
19011 {
19028 /* FALLTHRU */
19038 }
19040 /* Only SSE4.1/SSE4.2 supports V2DImode. */
19042 {
19044 {
19046 /* SSE4.1 supports EQ. */
19053 /* SSE4.2 supports GT/GTU. */
19060 }
19061 }
19063 /* Unsigned parallel compare is not supported by the hardware.
19064 Play some tricks to turn this into a signed comparison
19065 against 0. */
19067 {
19071 {
19074 {
19078 /* Subtract (-(INT MAX) - 1) from both operands to make
19079 them signed. */
19092 }
19097 /* Perform a parallel unsigned saturating subtraction. */
19110 }
19111 }
19112 }
19120 }
19122 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
19123 true if we should do zero extension, else sign extension. HIGH_P is
19124 true if we want the N/2 high elements, else the low elements. */
19126 void
19128 {
19133 {
19137 {
19141 else
19147 else
19153 else
19158 }
19161 {
19162 /* Shift higher 8 bytes to lower 8 bytes. */
19167 }
19168 else
19172 }
19173 else
19174 {
19178 {
19182 else
19188 else
19194 else
19199 }
19205 else
19210 }
19211 }
19213 /* Expand conditional increment or decrement using adb/sbb instructions.
19214 The default case using setcc followed by the conditional move can be
19215 done by generic code. */
19216 bool
19218 {
19220 rtx flags;
19222 rtx compare_op;
19240 {
19243 }
19246 {
19250 reverse_condition_maybe_unordered
19252 else
19254 }
19258 /* Construct either adc or sbb insn. */
19260 {
19262 {
19277 }
19278 }
19279 else
19280 {
19282 {
19297 }
19298 }
19302 }
19305 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
19306 but works for floating pointer parameters and nonoffsetable memories.
19307 For pushes, it returns just stack offsets; the values will be saved
19308 in the right order. Maximally three parts are generated. */
19310 static int
19312 {
19317 else
19323 /* Optimize constant pool reference to immediates. This is used by fp
19324 moves, that force all constants to memory to allow combining. */
19326 {
19330 }
19333 {
19334 /* The only non-offsetable memories we handle are pushes. */
19343 }
19346 {
19348 /* Caution: if we looked through a constant pool memory above,
19349 the operand may actually have a different mode now. That's
19350 ok, since we want to pun this all the way back to an integer. */
19354 }
19357 {
19360 else
19361 {
19365 {
19369 }
19371 {
19376 }
19378 {
19379 REAL_VALUE_TYPE r;
19384 {
19399 }
19402 }
19403 else
19405 }
19406 }
19407 else
19408 {
19412 {
19415 {
19419 }
19421 {
19425 }
19427 {
19428 REAL_VALUE_TYPE r;
19434 /* Do not use shift by 32 to avoid warning on 32bit systems. */
19437 = gen_int_mode
19440 DImode);
19441 else
19448 = gen_int_mode
19451 DImode);
19452 else
19454 }
19455 else
19457 }
19458 }
19461 }
19463 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
19464 Return false when normal moves are needed; true when all required
19465 insns have been emitted. Operands 2-4 contain the input values
19466 int the correct order; operands 5-7 contain the output values. */
19468 void
19470 {
19478 /* The DFmode expanders may ask us to move double.
19479 For 64bit target this is single move. By hiding the fact
19480 here we simplify i386.md splitters. */
19482 {
19483 /* Optimize constant pool reference to immediates. This is used by
19484 fp moves, that force all constants to memory to allow combining. */
19491 {
19494 }
19495 else
19500 }
19502 /* The only non-offsettable memory we handle is push. */
19505 else
19512 /* When emitting push, take care for source operands on the stack. */
19515 {
19518 /* Compensate for the stack decrement by 4. */
19523 /* src_base refers to the stack pointer and is
19524 automatically decreased by emitted push. */
19528 }
19530 /* We need to do copy in the right order in case an address register
19531 of the source overlaps the destination. */
19533 {
19534 rtx tmp;
19537 {
19541 collisions++;
19542 }
19544 /* Collision in the middle part can be handled by reordering. */
19546 {
19549 }
19553 {
19555 {
19558 }
19559 else
19560 {
19563 }
19564 }
19566 /* If there are more collisions, we can't handle it by reordering.
19567 Do an lea to the last part and use only one colliding move. */
19569 {
19570 rtx base;
19576 /* Handle the case when the last part isn't valid for lea.
19577 Happens in 64-bit mode storing the 12-byte XFmode. */
19584 {
19587 }
19588 }
19589 }
19592 {
19594 {
19596 {
19601 }
19603 {
19606 }
19607 }
19608 else
19609 {
19610 /* In 64bit mode we don't have 32bit push available. In case this is
19611 register, it is OK - we will just use larger counterpart. We also
19612 retype memory - these comes from attempt to avoid REX prefix on
19613 moving of second half of TFmode value. */
19615 {
19617 {
19628 }
19632 }
19633 }
19637 }
19639 /* Choose correct order to not overwrite the source before it is copied. */
19649 {
19651 {
19654 }
19655 }
19656 else
19657 {
19659 {
19662 }
19663 }
19665 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
19667 {
19676 }
19682 }
19684 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
19685 left shift by a constant, either using a single shift or
19686 a sequence of add instructions. */
19688 static void
19690 {
19696 {
19700 }
19701 else
19702 {
19705 }
19706 }
19708 void
19710 {
19719 {
19724 {
19730 }
19731 else
19732 {
19740 }
19742 }
19749 {
19750 /* Assuming we've chosen a QImode capable registers, then 1 << N
19751 can be done with two 32/64-bit shifts, no branches, no cmoves. */
19753 {
19769 }
19771 /* Otherwise, we can get the same results by manually performing
19772 a bit extract operation on bit 5/6, and then performing the two
19773 shifts. The two methods of getting 0/1 into low/high are exactly
19774 the same size. Avoiding the shift in the bit extract case helps
19775 pentium4 a bit; no one else seems to care much either way. */
19776 else
19777 {
19782 HOST_WIDE_INT bits;
19783 rtx x;
19786 {
19792 }
19793 else
19794 {
19800 }
19804 else
19812 }
19817 }
19820 {
19821 /* For -1 << N, we can avoid the shld instruction, because we
19822 know that we're shifting 0...31/63 ones into a -1. */
19826 else
19828 }
19829 else
19830 {
19838 }
19843 {
19849 }
19850 else
19851 {
19856 }
19857 }
19859 void
19861 {
19871 {
19876 {
19882 }
19884 {
19893 }
19894 else
19895 {
19903 }
19904 }
19905 else
19906 {
19918 {
19926 scratch));
19927 }
19928 else
19929 {
19934 }
19935 }
19936 }
19938 void
19940 {
19950 {
19955 {
19962 }
19963 else
19964 {
19972 }
19973 }
19974 else
19975 {
19987 {
19993 scratch));
19994 }
19995 else
19996 {
20001 }
20002 }
20003 }
20005 /* Predict just emitted jump instruction to be taken with probability PROB. */
20006 static void
20008 {
20012 }
20014 /* Helper function for the string operations below. Dest VARIABLE whether
20015 it is aligned to VALUE bytes. If true, jump to the label. */
20016 static rtx
20018 {
20023 else
20029 else
20032 }
20034 /* Adjust COUNTER by the VALUE. */
20035 static void
20037 {
20042 }
20044 /* Zero extend possibly SImode EXP to Pmode register. */
20045 rtx
20047 {
20048 rtx r;
20056 }
20058 /* Divide COUNTREG by SCALE. */
20059 static rtx
20061 {
20062 rtx sc;
20074 }
20076 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
20077 DImode for constant loop counts. */
20079 static enum machine_mode
20081 {
20089 }
20091 /* When SRCPTR is non-NULL, output simple loop to move memory
20092 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
20093 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
20094 equivalent loop to set memory by VALUE (supposed to be in MODE).
20096 The size is rounded down to whole number of chunk size moved at once.
20097 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
20100 static void
20105 {
20110 rtx size;
20111 rtx x_addr;
20112 rtx y_addr;
20121 /* Those two should combine. */
20123 {
20127 }
20137 {
20141 /* When unrolling for chips that reorder memory reads and writes,
20142 we can save registers by using single temporary.
20143 Also using 4 temporaries is overkill in 32bit mode. */
20145 {
20147 {
20149 {
20150 destmem =
20152 srcmem =
20154 }
20156 }
20157 }
20158 else
20159 {
20163 {
20166 {
20167 srcmem =
20169 }
20171 }
20173 {
20175 {
20176 destmem =
20178 }
20180 }
20181 }
20182 }
20183 else
20185 {
20187 destmem =
20190 }
20200 {
20206 else
20208 }
20209 else
20217 {
20222 }
20224 }
20226 /* Output "rep; mov" instruction.
20227 Arguments have same meaning as for previous function */
20228 static void
20231 rtx count,
20233 {
20234 rtx destexp;
20235 rtx srcexp;
20236 rtx countreg;
20238 /* If the size is known, it is shorter to use rep movs. */
20249 {
20256 }
20257 else
20258 {
20261 }
20263 {
20270 }
20271 else
20272 {
20277 }
20280 }
20282 /* Output "rep; stos" instruction.
20283 Arguments have same meaning as for previous function */
20284 static void
20287 rtx orig_value)
20288 {
20289 rtx destexp;
20290 rtx countreg;
20297 {
20301 }
20302 else
20305 {
20310 }
20314 }
20316 static void
20319 {
20323 }
20325 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
20326 static void
20329 {
20332 {
20337 {
20339 {
20342 }
20343 else
20346 }
20348 {
20351 else
20352 {
20355 }
20357 }
20359 {
20362 }
20364 {
20367 }
20369 {
20372 }
20374 }
20376 {
20382 }
20384 /* When there are stringops, we can cheaply increase dest and src pointers.
20385 Otherwise we save code size by maintaining offset (zero is readily
20386 available from preceding rep operation) and using x86 addressing modes.
20387 */
20389 {
20391 {
20398 }
20400 {
20407 }
20409 {
20416 }
20417 }
20418 else
20419 {
20421 rtx tmp;
20424 {
20435 }
20437 {
20450 }
20452 {
20461 }
20462 }
20463 }
20465 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20466 static void
20469 {
20470 count =
20476 }
20478 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
20479 static void
20481 {
20482 rtx dest;
20485 {
20490 {
20492 {
20497 }
20498 else
20501 }
20503 {
20505 {
20508 }
20509 else
20510 {
20515 }
20517 }
20519 {
20523 }
20525 {
20529 }
20531 {
20535 }
20537 }
20539 {
20542 }
20544 {
20547 {
20551 }
20552 else
20553 {
20559 }
20562 }
20564 {
20567 {
20570 }
20571 else
20572 {
20576 }
20579 }
20581 {
20587 }
20589 {
20595 }
20597 {
20603 }
20604 }
20606 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
20607 DESIRED_ALIGNMENT. */
20608 static void
20612 {
20614 {
20622 }
20624 {
20632 }
20634 {
20642 }
20644 }
20646 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
20647 ALIGN_BYTES is how many bytes need to be copied. */
20648 static rtx
20651 {
20661 {
20666 }
20668 {
20679 }
20681 {
20687 {
20695 }
20698 }
20704 {
20716 }
20723 }
20725 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
20726 DESIRED_ALIGNMENT. */
20727 static void
20730 {
20732 {
20739 }
20741 {
20748 }
20750 {
20757 }
20759 }
20761 /* Set enough from DST to align DST known to by aligned by ALIGN to
20762 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
20763 static rtx
20766 {
20770 {
20775 }
20777 {
20784 }
20786 {
20793 }
20800 }
20802 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
20803 static enum stringop_alg
20806 {
20809 /* Algorithms using the rep prefix want at least edi and ecx;
20810 additionally, memset wants eax and memcpy wants esi. Don't
20811 consider such algorithms if the user has appropriated those
20812 registers for their own purposes. */
20814 || (memset
20817 #define ALG_USABLE_P(alg) (rep_prefix_usable \
20818 || (alg != rep_prefix_1_byte \
20819 && alg != rep_prefix_4_byte \
20820 && alg != rep_prefix_8_byte))
20823 /* Even if the string operation call is cold, we still might spend a lot
20824 of time processing large blocks. */
20829 else
20837 else
20841 /* rep; movq or rep; movl is the smallest variant. */
20843 {
20846 else
20848 }
20849 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
20850 */
20854 {
20858 {
20859 /* We get here if the algorithms that were not libcall-based
20860 were rep-prefix based and we are unable to use rep prefixes
20861 based on global register usage. Break out of the loop and
20862 use the heuristic below. */
20866 {
20871 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
20872 last non-libcall inline algorithm. */
20874 {
20875 /* When the current size is best to be copied by a libcall,
20876 but we are still forced to inline, run the heuristic below
20877 that will pick code for medium sized blocks. */
20881 }
20884 }
20885 }
20887 }
20888 /* When asked to inline the call anyway, try to pick meaningful choice.
20889 We look for maximal size of block that is faster to copy by hand and
20890 take blocks of at most of that size guessing that average size will
20891 be roughly half of the block.
20893 If this turns out to be bad, we might simply specify the preferred
20894 choice in ix86_costs. */
20897 {
20904 {
20911 }
20912 /* If there aren't any usable algorithms, then recursing on
20913 smaller sizes isn't going to find anything. Just return the
20914 simple byte-at-a-time copy loop. */
20916 {
20917 /* Pick something reasonable. */
20921 }
20930 }
20932 #undef ALG_USABLE_P
20933 }
20935 /* Decide on alignment. We know that the operand is already aligned to ALIGN
20936 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
20937 static int
20941 {
20944 {
20955 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20956 copying whole cacheline at once. */
20959 else
20963 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
20964 copying whole cacheline at once. */
20967 else
20975 }
20984 }
20986 /* Return the smallest power of 2 greater than VAL. */
20987 static int
20989 {
20994 }
20996 /* Expand string move (memcpy) operation. Use i386 string operations
20997 when profitable. expand_setmem contains similar code. The code
20998 depends upon architecture, block size and alignment, but always has
20999 the same overall structure:
21001 1) Prologue guard: Conditional that jumps up to epilogues for small
21002 blocks that can be handled by epilogue alone. This is faster
21003 but also needed for correctness, since prologue assume the block
21004 is larger than the desired alignment.
21006 Optional dynamic check for size and libcall for large
21007 blocks is emitted here too, with -minline-stringops-dynamically.
21009 2) Prologue: copy first few bytes in order to get destination
21010 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
21011 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
21012 copied. We emit either a jump tree on power of two sized
21013 blocks, or a byte loop.
21015 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
21016 with specified algorithm.
21018 4) Epilogue: code copying tail of the block that is too small to be
21019 handled by main body (or up to size guarded by prologue guard). */
21021 bool
21024 {
21025 rtx destreg;
21026 rtx srcreg;
21028 rtx tmp;
21041 /* i386 can do misaligned access on reasonably increased cost. */
21045 /* ALIGN is the minimum of destination and source alignment, but we care here
21046 just about destination alignment. */
21055 /* Make sure we don't need to care about overflow later on. */
21059 /* Step 0: Decide on preferred algorithm, desired alignment and
21060 size of chunks to be copied by main loop. */
21076 {
21101 }
21105 /* Step 1: Prologue guard. */
21107 /* Alignment code needs count to be in register. */
21109 {
21112 {
21113 align_bytes
21117 else
21119 }
21122 }
21125 /* Ensure that alignment prologue won't copy past end of block. */
21127 {
21129 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
21130 Make sure it is power of 2. */
21134 {
21136 {
21137 /* If main algorithm works on QImode, no epilogue is needed.
21138 For small sizes just don't align anything. */
21141 else
21143 }
21144 }
21145 else
21146 {
21153 else
21155 }
21156 }
21158 /* Emit code to decide on runtime whether library call or inline should be
21159 used. */
21161 {
21163 {
21165 {
21169 }
21170 }
21171 else
21172 {
21181 }
21182 }
21184 /* Step 2: Alignment prologue. */
21187 {
21189 {
21190 /* Except for the first move in epilogue, we no longer know
21191 constant offset in aliasing info. It don't seems to worth
21192 the pain to maintain it for the first move, so throw away
21193 the info early. */
21197 desired_align);
21198 }
21199 else
21200 {
21201 /* If we know how many bytes need to be stored before dst is
21202 sufficiently aligned, maintain aliasing info accurately. */
21207 }
21213 {
21214 /* It is possible that we copied enough so the main loop will not
21215 execute. */
21225 else
21227 }
21228 }
21230 {
21235 }
21239 /* Step 3: Main loop. */
21242 {
21255 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
21256 registers for 4 temporaries anyway. */
21259 expected_size);
21263 DImode);
21267 SImode);
21271 QImode);
21273 }
21274 /* Adjust properly the offset of src and dest memory for aliasing. */
21276 {
21281 }
21282 else
21283 {
21286 }
21288 /* Step 4: Epilogue to copy the remaining bytes. */
21289 epilogue:
21291 {
21292 /* When the main loop is done, COUNT_EXP might hold original count,
21293 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
21294 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
21295 bytes. Compensate if needed. */
21298 {
21299 tmp =
21302 OPTAB_DIRECT);
21305 }
21308 }
21312 epilogue_size_needed);
21316 }
21318 /* Helper function for memcpy. For QImode value 0xXY produce
21319 0xXYXYXYXY of wide specified by MODE. This is essentially
21320 a * 0x10101010, but we can do slightly better than
21321 synth_mult by unwinding the sequence by hand on CPUs with
21322 slow multiply. */
21323 static rtx
21325 {
21327 rtx tmp;
21334 {
21342 }
21351 nops--;
21356 {
21360 OPTAB_DIRECT);
21361 }
21362 else
21363 {
21369 else
21371 else
21372 {
21375 reg =
21377 }
21387 }
21388 }
21390 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
21391 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
21392 alignment from ALIGN to DESIRED_ALIGN. */
21393 static rtx
21395 {
21396 rtx promoted_val;
21405 else
21409 }
21411 /* Expand string clear operation (bzero). Use i386 string operations when
21412 profitable. See expand_movmem comment for explanation of individual
21413 steps performed. */
21414 bool
21417 {
21418 rtx destreg;
21420 rtx tmp;
21435 /* i386 can do misaligned access on reasonably increased cost. */
21444 /* Make sure we don't need to care about overflow later on. */
21448 /* Step 0: Decide on preferred algorithm, desired alignment and
21449 size of chunks to be copied by main loop. */
21464 {
21489 }
21492 /* Step 1: Prologue guard. */
21494 /* Alignment code needs count to be in register. */
21496 {
21499 {
21500 align_bytes
21504 else
21506 }
21508 {
21513 }
21514 }
21515 /* Do the cheap promotion to allow better CSE across the
21516 main loop and epilogue (ie one load of the big constant in the
21517 front of all code. */
21521 /* Ensure that alignment prologue won't copy past end of block. */
21523 {
21525 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
21526 Make sure it is power of 2. */
21529 /* To improve performance of small blocks, we jump around the VAL
21530 promoting mode. This mean that if the promoted VAL is not constant,
21531 we might not use it in the epilogue and have to use byte
21532 loop variant. */
21536 {
21538 {
21539 /* If main algorithm works on QImode, no epilogue is needed.
21540 For small sizes just don't align anything. */
21543 else
21545 }
21546 }
21547 else
21548 {
21555 else
21557 }
21558 }
21560 {
21569 }
21571 /* Step 2: Alignment prologue. */
21573 /* Do the expensive promotion once we branched off the small blocks. */
21580 {
21582 {
21583 /* Except for the first move in epilogue, we no longer know
21584 constant offset in aliasing info. It don't seems to worth
21585 the pain to maintain it for the first move, so throw away
21586 the info early. */
21589 desired_align);
21590 }
21591 else
21592 {
21593 /* If we know how many bytes need to be stored before dst is
21594 sufficiently aligned, maintain aliasing info accurately. */
21599 }
21605 {
21606 /* It is possible that we copied enough so the main loop will not
21607 execute. */
21617 else
21619 }
21620 }
21622 {
21628 }
21632 /* Step 3: Main loop. */
21635 {
21663 }
21664 /* Adjust properly the offset of src and dest memory for aliasing. */
21668 else
21671 /* Step 4: Epilogue to copy the remaining bytes. */
21674 {
21675 /* When the main loop is done, COUNT_EXP might hold original count,
21676 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
21677 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
21678 bytes. Compensate if needed. */
21681 {
21682 tmp =
21685 OPTAB_DIRECT);
21688 }
21691 }
21692 epilogue:
21694 {
21697 epilogue_size_needed);
21698 else
21700 epilogue_size_needed);
21701 }
21705 }
21707 /* Expand the appropriate insns for doing strlen if not just doing
21708 repnz; scasb
21710 out = result, initialized with the start address
21711 align_rtx = alignment of the address.
21712 scratch = scratch register, initialized with the startaddress when
21713 not aligned, otherwise undefined
21715 This is just the body. It needs the initializations mentioned above and
21716 some address computing at the end. These things are done in i386.md. */
21718 static void
21720 {
21722 rtx tmp;
21727 rtx mem;
21730 rtx cmp;
21736 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
21738 /* Is there a known alignment and is it less than 4? */
21740 {
21743 /* Is there a known alignment and is it not 2? */
21745 {
21749 /* Leave just the 3 lower bits. */
21759 }
21760 else
21761 {
21762 /* Since the alignment is 2, we have to check 2 or 0 bytes;
21763 check if is aligned to 4 - byte. */
21770 }
21774 /* Now compare the bytes. */
21776 /* Compare the first n unaligned byte on a byte per byte basis. */
21780 /* Increment the address. */
21783 /* Not needed with an alignment of 2 */
21785 {
21789 end_0_label);
21794 }
21797 end_0_label);
21800 }
21802 /* Generate loop to check 4 bytes at a time. It is not a good idea to
21803 align this loop. It gives only huge programs, but does not help to
21804 speed up. */
21811 /* This formula yields a nonzero result iff one of the bytes is zero.
21812 This saves three branches inside loop and many cycles. */
21820 align_4_label);
21823 {
21829 /* If zero is not in the first two bytes, move two bytes forward. */
21835 reg,
21836 tmpreg)));
21837 /* Emit lea manually to avoid clobbering of flags. */
21845 reg2,
21846 out)));
21847 }
21848 else
21849 {
21851 /* Is zero in the first two bytes? */
21858 pc_rtx);
21862 /* Not in the first two. Move two bytes forward. */
21868 }
21870 /* Avoid branch in fixing the byte. */
21878 }
21880 /* Expand strlen. */
21882 bool
21884 {
21887 /* The generic case of strlen expander is long. Avoid it's
21888 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
21891 && !TARGET_INLINE_ALL_STRINGOPS
21901 {
21902 /* Well it seems that some optimizer does not combine a call like
21903 foo(strlen(bar), strlen(bar));
21904 when the move and the subtraction is done here. It does calculate
21905 the length just once when these instructions are done inside of
21906 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
21907 often used and I use one fewer register for the lifetime of
21908 output_strlen_unroll() this is better. */
21914 /* strlensi_unroll_1 returns the address of the zero at the end of
21915 the string, like memchr(), so compute the length by subtracting
21916 the start address. */
21918 }
21919 else
21920 {
21921 rtx unspec;
21923 /* Can't use this if the user has appropriated eax, ecx, or edi. */
21936 /* If .md starts supporting :P, this can be done in .md. */
21942 }
21944 }
21946 /* For given symbol (function) construct code to compute address of it's PLT
21947 entry in large x86-64 PIC model. */
21948 rtx
21950 {
21960 }
21962 rtx
21964 rtx callarg2,
21966 {
21974 {
21975 #if TARGET_MACHO
21978 #endif
21979 }
21980 else
21981 {
21982 /* Static functions and indirect calls don't need the pic register. */
21987 }
21990 {
21994 }
22004 {
22007 }
22013 {
22017 }
22020 {
22021 /* We need to represent that SI and DI registers are clobbered
22022 by SYSV calls. */
22028 };
22032 UNSPEC_MS_TO_SYSV_CALL);
22039 gen_rtx_REG
22047 }
22049 /* Add UNSPEC_CALL_NEEDS_VZEROUPPER decoration. */
22051 {
22052 rtx unspec;
22056 {
22059 else
22061 }
22064 else
22069 else
22070 {
22073 UNSPEC_CALL_NEEDS_VZEROUPPER);
22076 }
22077 }
22084 }
22086 void
22088 {
22092 }
22094 /* Output the assembly for a call instruction. */
22098 {
22104 {
22107 /* SEH epilogue detection requires the indirect branch case
22108 to include REX.W. */
22111 else
22116 }
22118 /* SEH unwinding can require an extra nop to be emitted in several
22119 circumstances. Determine if we have one of those. */
22121 {
22122 rtx i;
22125 {
22126 /* If we get to another real insn, we don't need the nop. */
22130 /* If we get to the epilogue note, prevent a catch region from
22131 being adjacent to the standard epilogue sequence. If non-
22132 call-exceptions, we'll have done this during epilogue emission. */
22134 && !flag_non_call_exceptions
22136 {
22139 }
22140 }
22142 /* If we didn't find a real insn following the call, prevent the
22143 unwinder from looking into the next function. */
22146 }
22150 else
22159 }
22160 \f
22161 /* Clear stack slot assignments remembered from previous functions.
22162 This is called from INIT_EXPANDERS once before RTL is emitted for each
22163 function. */
22167 {
22176 }
22178 /* Return a MEM corresponding to a stack slot with mode MODE.
22179 Allocate a new slot if necessary.
22181 The RTL for a function can have several slots available: N is
22182 which slot to use. */
22184 rtx
22186 {
22191 /* Virtual slot is valid only before vregs are instantiated. */
22206 }
22207 \f
22208 /* Calculate the length of the memory address in the instruction
22209 encoding. Does not include the one-byte modrm, opcode, or prefix. */
22211 int
22213 {
22238 /* Rule of thumb:
22239 - esp as the base always wants an index,
22240 - ebp as the base always wants a displacement,
22241 - r12 as the base always wants an index,
22242 - r13 as the base always wants a displacement. */
22244 /* Register Indirect. */
22246 {
22247 /* esp (for its index) and ebp (for its displacement) need
22248 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
22249 code. */
22258 }
22260 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
22261 is not disp32, but disp32(%rip), so for disp32
22262 SIB byte is needed, unless print_operand_address
22263 optimizes it into disp32(%rip) or (%rip) is implied
22264 by UNSPEC. */
22266 {
22269 {
22286 }
22287 }
22289 else
22290 {
22291 /* Find the length of the displacement constant. */
22293 {
22296 else
22298 }
22299 /* ebp always wants a displacement. Similarly r13. */
22304 /* An index requires the two-byte modrm form.... */
22306 /* ...like esp (or r12), which always wants an index. */
22312 }
22315 {
22322 }
22325 }
22327 /* Compute default value for "length_immediate" attribute. When SHORTFORM
22328 is set, expect that insn have 8bit immediate alternative. */
22329 int
22331 {
22337 {
22342 {
22345 {
22357 }
22359 {
22362 }
22363 }
22365 {
22375 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
22381 }
22382 }
22384 }
22385 /* Compute default value for "length_address" attribute. */
22386 int
22388 {
22392 {
22402 {
22407 }
22410 }
22415 {
22418 {
22423 constraints++;
22426 ;
22427 /* Skip ignored operands. */
22430 }
22432 }
22434 }
22436 /* Compute default value for "length_vex" attribute. It includes
22437 2 or 3 byte VEX prefix and 1 opcode byte. */
22439 int
22441 {
22444 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
22445 byte VEX prefix. */
22449 /* We can always use 2 byte VEX prefix in 32bit. */
22457 {
22458 /* REX.W bit uses 3 byte VEX prefix. */
22462 }
22463 else
22464 {
22465 /* REX.X or REX.B bits use 3 byte VEX prefix. */
22469 }
22472 }
22473 \f
22474 /* Return the maximum number of instructions a cpu can issue. */
22476 static int
22478 {
22480 {
22504 }
22505 }
22507 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
22508 by DEP_INSN and nothing set by DEP_INSN. */
22510 static bool
22512 {
22515 /* Simplify the test for uninteresting insns. */
22523 {
22526 }
22531 {
22534 }
22535 else
22541 /* This test is true if the dependent insn reads the flags but
22542 not any other potentially set register. */
22550 }
22552 /* Return true iff USE_INSN has a memory address with operands set by
22553 SET_INSN. */
22555 bool
22557 {
22562 {
22565 }
22567 }
22569 static int
22571 {
22577 /* Anti and output dependencies have zero cost on all CPUs. */
22583 /* If we can't recognize the insns, we can't really do anything. */
22591 {
22593 /* Address Generation Interlock adds a cycle of latency. */
22595 {
22606 }
22610 /* ??? Compares pair with jump/setcc. */
22614 /* Floating point stores require value to be ready one cycle earlier. */
22624 /* INT->FP conversion is expensive. */
22628 /* There is one cycle extra latency between an FP op and a store. */
22636 /* Show ability of reorder buffer to hide latency of load by executing
22637 in parallel with previous instruction in case
22638 previous instruction is not needed to compute the address. */
22641 {
22642 /* Claim moves to take one cycle, as core can issue one load
22643 at time and the next load can start cycle later. */
22648 cost--;
22649 }
22655 /* The esp dependency is resolved before the instruction is really
22656 finished. */
22661 /* INT->FP conversion is expensive. */
22665 /* Show ability of reorder buffer to hide latency of load by executing
22666 in parallel with previous instruction in case
22667 previous instruction is not needed to compute the address. */
22670 {
22671 /* Claim moves to take one cycle, as core can issue one load
22672 at time and the next load can start cycle later. */
22678 else
22680 }
22693 /* Show ability of reorder buffer to hide latency of load by executing
22694 in parallel with previous instruction in case
22695 previous instruction is not needed to compute the address. */
22698 {
22702 /* Because of the difference between the length of integer and
22703 floating unit pipeline preparation stages, the memory operands
22704 for floating point are cheaper.
22706 ??? For Athlon it the difference is most probably 2. */
22709 else
22714 else
22716 }
22720 }
22723 }
22725 /* How many alternative schedules to try. This should be as wide as the
22726 scheduling freedom in the DFA, but no wider. Making this value too
22727 large results extra work for the scheduler. */
22729 static int
22731 {
22733 {
22745 /* Generally, we want haifa-sched:max_issue() to look ahead as far
22746 as many instructions can be executed on a cycle, i.e.,
22747 issue_rate. I wonder why tuning for many CPUs does not do this. */
22752 }
22753 }
22755 \f
22757 /* Model decoder of Core 2/i7.
22758 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
22759 track the instruction fetch block boundaries and make sure that long
22760 (9+ bytes) instructions are assigned to D0. */
22762 /* Maximum length of an insn that can be handled by
22763 a secondary decoder unit. '8' for Core 2/i7. */
22766 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
22767 '16' for Core 2/i7. */
22770 /* Maximum number of instructions decoder can handle per cycle.
22771 '6' for Core 2/i7. */
22775 ix86_first_cycle_multipass_data_t;
22777 const_ix86_first_cycle_multipass_data_t;
22779 /* A variable to store target state across calls to max_issue within
22780 one cycle. */
22784 /* Initialize DATA. */
22785 static void
22787 {
22788 ix86_first_cycle_multipass_data_t data
22795 }
22797 /* Advancing the cycle; reset ifetch block counts. */
22798 static void
22800 {
22807 }
22811 /* Filter out insns from ready_try that the core will not be able to issue
22812 on current cycle due to decoder. */
22813 static void
22814 core2i7_first_cycle_multipass_filter_ready_try
22817 {
22819 {
22820 rtx insn;
22830 (!first_cycle_insn_p
22832 /* ... or it would not fit into the ifetch block ... */
22834 /* ... or the decoder is full already ... */
22836 /* ... mask the insn out. */
22837 {
22842 }
22843 }
22844 }
22846 /* Prepare for a new round of multipass lookahead scheduling. */
22847 static void
22850 {
22851 ix86_first_cycle_multipass_data_t data
22853 const_ix86_first_cycle_multipass_data_t prev_data
22856 /* Restore the state from the end of the previous round. */
22860 /* Filter instructions that cannot be issued on current cycle due to
22861 decoder restrictions. */
22863 first_cycle_insn_p);
22864 }
22866 /* INSN is being issued in current solution. Account for its impact on
22867 the decoder model. */
22868 static void
22871 {
22872 ix86_first_cycle_multipass_data_t data
22874 const_ix86_first_cycle_multipass_data_t prev_data
22884 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
22886 {
22889 }
22891 {
22895 }
22898 /* Filter out insns from ready_try that the core will not be able to issue
22899 on current cycle due to decoder. */
22902 }
22904 /* Revert the effect on ready_try. */
22905 static void
22909 {
22910 const_ix86_first_cycle_multipass_data_t data
22913 sbitmap_iterator sbi;
22917 {
22919 }
22920 }
22922 /* Save the result of multipass lookahead scheduling for the next round. */
22923 static void
22925 {
22926 const_ix86_first_cycle_multipass_data_t data
22928 ix86_first_cycle_multipass_data_t next_data
22932 {
22935 }
22936 }
22938 /* Deallocate target data. */
22939 static void
22941 {
22942 ix86_first_cycle_multipass_data_t data
22946 {
22950 }
22951 }
22953 /* Prepare for scheduling pass. */
22954 static void
22958 {
22959 /* Install scheduling hooks for current CPU. Some of these hooks are used
22960 in time-critical parts of the scheduler, so we only set them up when
22961 they are actually used. */
22963 {
22983 /* Set decoder parameters. */
22998 }
22999 }
23001 \f
23002 /* Compute the alignment given to a constant that is being placed in memory.
23003 EXP is the constant and ALIGN is the alignment that the object would
23004 ordinarily have.
23005 The value of this function is used instead of that alignment to align
23006 the object. */
23008 int
23010 {
23013 {
23018 }
23024 }
23026 /* Compute the alignment for a static variable.
23027 TYPE is the data type, and ALIGN is the alignment that
23028 the object would ordinarily have. The value of this function is used
23029 instead of that alignment to align the object. */
23031 int
23033 {
23044 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
23045 to 16byte boundary. */
23047 {
23054 }
23057 {
23062 }
23064 {
23071 }
23076 {
23081 }
23084 {
23089 }
23092 }
23094 /* Compute the alignment for a local variable or a stack slot. EXP is
23095 the data type or decl itself, MODE is the widest mode available and
23096 ALIGN is the alignment that the object would ordinarily have. The
23097 value of this macro is used instead of that alignment to align the
23098 object. */
23100 unsigned int
23103 {
23107 {
23110 }
23111 else
23112 {
23115 }
23117 /* Don't do dynamic stack realignment for long long objects with
23118 -mpreferred-stack-boundary=2. */
23127 /* If TYPE is NULL, we are allocating a stack slot for caller-save
23128 register in MODE. We will return the largest alignment of XF
23129 and DF. */
23131 {
23135 }
23137 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
23138 to 16byte boundary. Exact wording is:
23140 An array uses the same alignment as its elements, except that a local or
23141 global array variable of length at least 16 bytes or
23142 a C99 variable-length array variable always has alignment of at least 16 bytes.
23144 This was added to allow use of aligned SSE instructions at arrays. This
23145 rule is meant for static storage (where compiler can not do the analysis
23146 by itself). We follow it for automatic variables only when convenient.
23147 We fully control everything in the function compiled and functions from
23148 other unit can not rely on the alignment.
23150 Exclude va_list type. It is the common case of local array where
23151 we can not benefit from the alignment. */
23154 {
23164 }
23166 {
23171 }
23173 {
23179 }
23184 {
23189 }
23192 {
23198 }
23200 }
23202 /* Compute the minimum required alignment for dynamic stack realignment
23203 purposes for a local variable, parameter or a stack slot. EXP is
23204 the data type or decl itself, MODE is its mode and ALIGN is the
23205 alignment that the object would ordinarily have. */
23207 unsigned int
23210 {
23214 {
23217 }
23218 else
23219 {
23222 }
23227 /* Don't do dynamic stack realignment for long long objects with
23228 -mpreferred-stack-boundary=2. */
23235 }
23236 \f
23237 /* Find a location for the static chain incoming to a nested function.
23238 This is a register, unless all free registers are used by arguments. */
23240 static rtx
23242 {
23249 {
23250 /* We always use R10 in 64-bit mode. */
23252 }
23253 else
23254 {
23255 tree fntype;
23258 /* By default in 32-bit mode we use ECX to pass the static chain. */
23264 {
23265 /* Fastcall functions use ecx/edx for arguments, which leaves
23266 us with EAX for the static chain.
23267 Thiscall functions use ecx for arguments, which also
23268 leaves us with EAX for the static chain. */
23270 }
23272 {
23273 /* For regparm 3, we have no free call-clobbered registers in
23274 which to store the static chain. In order to implement this,
23275 we have the trampoline push the static chain to the stack.
23276 However, we can't push a value below the return address when
23277 we call the nested function directly, so we have to use an
23278 alternate entry point. For this we use ESI, and have the
23279 alternate entry point push ESI, so that things appear the
23280 same once we're executing the nested function. */
23282 {
23287 }
23289 }
23290 }
23293 }
23295 /* Emit RTL insns to initialize the variable parts of a trampoline.
23296 FNDECL is the decl of the target address; M_TRAMP is a MEM for
23297 the trampoline, and CHAIN_VALUE is an RTX for the static chain
23298 to be passed to the target function. */
23300 static void
23302 {
23308 {
23312 /* Depending on the static chain location, either load a register
23313 with a constant, or push the constant to the stack. All of the
23314 instructions are the same size. */
23317 {
23322 else
23324 }
23325 else
23334 /* Compute offset from the end of the jmp to the target function.
23335 In the case in which the trampoline stores the static chain on
23336 the stack, we need to skip the first insn which pushes the
23337 (call-saved) register static chain; this push is 1 byte. */
23348 }
23349 else
23350 {
23353 /* Load the function address to r11. Try to load address using
23354 the shorter movl instead of movabs. We may want to support
23355 movq for kernel mode, but kernel does not use trampolines at
23356 the moment. */
23358 {
23367 }
23368 else
23369 {
23376 }
23378 /* Load static chain using movabs to r10. */
23386 /* Jump to r11; the last (unused) byte is a nop, only there to
23387 pad the write out to a single 32-bit store. */
23393 }
23395 #ifdef ENABLE_EXECUTE_STACK
23396 #ifdef CHECK_EXECUTE_STACK_ENABLED
23398 #endif
23401 #endif
23402 }
23403 \f
23404 /* The following file contains several enumerations and data structures
23405 built from the definitions in i386-builtin-types.def. */
23409 /* Table for the ix86 builtin non-function types. */
23412 /* Retrieve an element from the above table, building some of
23413 the types lazily. */
23415 static tree
23417 {
23429 {
23437 }
23438 else
23439 {
23445 else
23453 }
23457 }
23459 /* Table for the ix86 builtin function types. */
23462 /* Retrieve an element from the above table, building some of
23463 the types lazily. */
23465 static tree
23467 {
23468 tree type;
23477 {
23485 {
23488 }
23491 }
23492 else
23493 {
23499 }
23503 }
23506 /* Codes for all the SSE/MMX builtins. */
23507 enum ix86_builtins
23508 {
23509 IX86_BUILTIN_ADDPS,
23510 IX86_BUILTIN_ADDSS,
23511 IX86_BUILTIN_DIVPS,
23512 IX86_BUILTIN_DIVSS,
23513 IX86_BUILTIN_MULPS,
23514 IX86_BUILTIN_MULSS,
23515 IX86_BUILTIN_SUBPS,
23516 IX86_BUILTIN_SUBSS,
23518 IX86_BUILTIN_CMPEQPS,
23519 IX86_BUILTIN_CMPLTPS,
23520 IX86_BUILTIN_CMPLEPS,
23521 IX86_BUILTIN_CMPGTPS,
23522 IX86_BUILTIN_CMPGEPS,
23523 IX86_BUILTIN_CMPNEQPS,
23524 IX86_BUILTIN_CMPNLTPS,
23525 IX86_BUILTIN_CMPNLEPS,
23526 IX86_BUILTIN_CMPNGTPS,
23527 IX86_BUILTIN_CMPNGEPS,
23528 IX86_BUILTIN_CMPORDPS,
23529 IX86_BUILTIN_CMPUNORDPS,
23530 IX86_BUILTIN_CMPEQSS,
23531 IX86_BUILTIN_CMPLTSS,
23532 IX86_BUILTIN_CMPLESS,
23533 IX86_BUILTIN_CMPNEQSS,
23534 IX86_BUILTIN_CMPNLTSS,
23535 IX86_BUILTIN_CMPNLESS,
23536 IX86_BUILTIN_CMPNGTSS,
23537 IX86_BUILTIN_CMPNGESS,
23538 IX86_BUILTIN_CMPORDSS,
23539 IX86_BUILTIN_CMPUNORDSS,
23541 IX86_BUILTIN_COMIEQSS,
23542 IX86_BUILTIN_COMILTSS,
23543 IX86_BUILTIN_COMILESS,
23544 IX86_BUILTIN_COMIGTSS,
23545 IX86_BUILTIN_COMIGESS,
23546 IX86_BUILTIN_COMINEQSS,
23547 IX86_BUILTIN_UCOMIEQSS,
23548 IX86_BUILTIN_UCOMILTSS,
23549 IX86_BUILTIN_UCOMILESS,
23550 IX86_BUILTIN_UCOMIGTSS,
23551 IX86_BUILTIN_UCOMIGESS,
23552 IX86_BUILTIN_UCOMINEQSS,
23554 IX86_BUILTIN_CVTPI2PS,
23555 IX86_BUILTIN_CVTPS2PI,
23556 IX86_BUILTIN_CVTSI2SS,
23557 IX86_BUILTIN_CVTSI642SS,
23558 IX86_BUILTIN_CVTSS2SI,
23559 IX86_BUILTIN_CVTSS2SI64,
23560 IX86_BUILTIN_CVTTPS2PI,
23561 IX86_BUILTIN_CVTTSS2SI,
23562 IX86_BUILTIN_CVTTSS2SI64,
23564 IX86_BUILTIN_MAXPS,
23565 IX86_BUILTIN_MAXSS,
23566 IX86_BUILTIN_MINPS,
23567 IX86_BUILTIN_MINSS,
23569 IX86_BUILTIN_LOADUPS,
23570 IX86_BUILTIN_STOREUPS,
23571 IX86_BUILTIN_MOVSS,
23573 IX86_BUILTIN_MOVHLPS,
23574 IX86_BUILTIN_MOVLHPS,
23575 IX86_BUILTIN_LOADHPS,
23576 IX86_BUILTIN_LOADLPS,
23577 IX86_BUILTIN_STOREHPS,
23578 IX86_BUILTIN_STORELPS,
23580 IX86_BUILTIN_MASKMOVQ,
23581 IX86_BUILTIN_MOVMSKPS,
23582 IX86_BUILTIN_PMOVMSKB,
23584 IX86_BUILTIN_MOVNTPS,
23585 IX86_BUILTIN_MOVNTQ,
23587 IX86_BUILTIN_LOADDQU,
23588 IX86_BUILTIN_STOREDQU,
23590 IX86_BUILTIN_PACKSSWB,
23591 IX86_BUILTIN_PACKSSDW,
23592 IX86_BUILTIN_PACKUSWB,
23594 IX86_BUILTIN_PADDB,
23595 IX86_BUILTIN_PADDW,
23596 IX86_BUILTIN_PADDD,
23597 IX86_BUILTIN_PADDQ,
23598 IX86_BUILTIN_PADDSB,
23599 IX86_BUILTIN_PADDSW,
23600 IX86_BUILTIN_PADDUSB,
23601 IX86_BUILTIN_PADDUSW,
23602 IX86_BUILTIN_PSUBB,
23603 IX86_BUILTIN_PSUBW,
23604 IX86_BUILTIN_PSUBD,
23605 IX86_BUILTIN_PSUBQ,
23606 IX86_BUILTIN_PSUBSB,
23607 IX86_BUILTIN_PSUBSW,
23608 IX86_BUILTIN_PSUBUSB,
23609 IX86_BUILTIN_PSUBUSW,
23611 IX86_BUILTIN_PAND,
23612 IX86_BUILTIN_PANDN,
23613 IX86_BUILTIN_POR,
23614 IX86_BUILTIN_PXOR,
23616 IX86_BUILTIN_PAVGB,
23617 IX86_BUILTIN_PAVGW,
23619 IX86_BUILTIN_PCMPEQB,
23620 IX86_BUILTIN_PCMPEQW,
23621 IX86_BUILTIN_PCMPEQD,
23622 IX86_BUILTIN_PCMPGTB,
23623 IX86_BUILTIN_PCMPGTW,
23624 IX86_BUILTIN_PCMPGTD,
23626 IX86_BUILTIN_PMADDWD,
23628 IX86_BUILTIN_PMAXSW,
23629 IX86_BUILTIN_PMAXUB,
23630 IX86_BUILTIN_PMINSW,
23631 IX86_BUILTIN_PMINUB,
23633 IX86_BUILTIN_PMULHUW,
23634 IX86_BUILTIN_PMULHW,
23635 IX86_BUILTIN_PMULLW,
23637 IX86_BUILTIN_PSADBW,
23638 IX86_BUILTIN_PSHUFW,
23640 IX86_BUILTIN_PSLLW,
23641 IX86_BUILTIN_PSLLD,
23642 IX86_BUILTIN_PSLLQ,
23643 IX86_BUILTIN_PSRAW,
23644 IX86_BUILTIN_PSRAD,
23645 IX86_BUILTIN_PSRLW,
23646 IX86_BUILTIN_PSRLD,
23647 IX86_BUILTIN_PSRLQ,
23648 IX86_BUILTIN_PSLLWI,
23649 IX86_BUILTIN_PSLLDI,
23650 IX86_BUILTIN_PSLLQI,
23651 IX86_BUILTIN_PSRAWI,
23652 IX86_BUILTIN_PSRADI,
23653 IX86_BUILTIN_PSRLWI,
23654 IX86_BUILTIN_PSRLDI,
23655 IX86_BUILTIN_PSRLQI,
23657 IX86_BUILTIN_PUNPCKHBW,
23658 IX86_BUILTIN_PUNPCKHWD,
23659 IX86_BUILTIN_PUNPCKHDQ,
23660 IX86_BUILTIN_PUNPCKLBW,
23661 IX86_BUILTIN_PUNPCKLWD,
23662 IX86_BUILTIN_PUNPCKLDQ,
23664 IX86_BUILTIN_SHUFPS,
23666 IX86_BUILTIN_RCPPS,
23667 IX86_BUILTIN_RCPSS,
23668 IX86_BUILTIN_RSQRTPS,
23669 IX86_BUILTIN_RSQRTPS_NR,
23670 IX86_BUILTIN_RSQRTSS,
23671 IX86_BUILTIN_RSQRTF,
23672 IX86_BUILTIN_SQRTPS,
23673 IX86_BUILTIN_SQRTPS_NR,
23674 IX86_BUILTIN_SQRTSS,
23676 IX86_BUILTIN_UNPCKHPS,
23677 IX86_BUILTIN_UNPCKLPS,
23679 IX86_BUILTIN_ANDPS,
23680 IX86_BUILTIN_ANDNPS,
23681 IX86_BUILTIN_ORPS,
23682 IX86_BUILTIN_XORPS,
23684 IX86_BUILTIN_EMMS,
23685 IX86_BUILTIN_LDMXCSR,
23686 IX86_BUILTIN_STMXCSR,
23687 IX86_BUILTIN_SFENCE,
23689 /* 3DNow! Original */
23690 IX86_BUILTIN_FEMMS,
23691 IX86_BUILTIN_PAVGUSB,
23692 IX86_BUILTIN_PF2ID,
23693 IX86_BUILTIN_PFACC,
23694 IX86_BUILTIN_PFADD,
23695 IX86_BUILTIN_PFCMPEQ,
23696 IX86_BUILTIN_PFCMPGE,
23697 IX86_BUILTIN_PFCMPGT,
23698 IX86_BUILTIN_PFMAX,
23699 IX86_BUILTIN_PFMIN,
23700 IX86_BUILTIN_PFMUL,
23701 IX86_BUILTIN_PFRCP,
23702 IX86_BUILTIN_PFRCPIT1,
23703 IX86_BUILTIN_PFRCPIT2,
23704 IX86_BUILTIN_PFRSQIT1,
23705 IX86_BUILTIN_PFRSQRT,
23706 IX86_BUILTIN_PFSUB,
23707 IX86_BUILTIN_PFSUBR,
23708 IX86_BUILTIN_PI2FD,
23709 IX86_BUILTIN_PMULHRW,
23711 /* 3DNow! Athlon Extensions */
23712 IX86_BUILTIN_PF2IW,
23713 IX86_BUILTIN_PFNACC,
23714 IX86_BUILTIN_PFPNACC,
23715 IX86_BUILTIN_PI2FW,
23716 IX86_BUILTIN_PSWAPDSI,
23717 IX86_BUILTIN_PSWAPDSF,
23719 /* SSE2 */
23720 IX86_BUILTIN_ADDPD,
23721 IX86_BUILTIN_ADDSD,
23722 IX86_BUILTIN_DIVPD,
23723 IX86_BUILTIN_DIVSD,
23724 IX86_BUILTIN_MULPD,
23725 IX86_BUILTIN_MULSD,
23726 IX86_BUILTIN_SUBPD,
23727 IX86_BUILTIN_SUBSD,
23729 IX86_BUILTIN_CMPEQPD,
23730 IX86_BUILTIN_CMPLTPD,
23731 IX86_BUILTIN_CMPLEPD,
23732 IX86_BUILTIN_CMPGTPD,
23733 IX86_BUILTIN_CMPGEPD,
23734 IX86_BUILTIN_CMPNEQPD,
23735 IX86_BUILTIN_CMPNLTPD,
23736 IX86_BUILTIN_CMPNLEPD,
23737 IX86_BUILTIN_CMPNGTPD,
23738 IX86_BUILTIN_CMPNGEPD,
23739 IX86_BUILTIN_CMPORDPD,
23740 IX86_BUILTIN_CMPUNORDPD,
23741 IX86_BUILTIN_CMPEQSD,
23742 IX86_BUILTIN_CMPLTSD,
23743 IX86_BUILTIN_CMPLESD,
23744 IX86_BUILTIN_CMPNEQSD,
23745 IX86_BUILTIN_CMPNLTSD,
23746 IX86_BUILTIN_CMPNLESD,
23747 IX86_BUILTIN_CMPORDSD,
23748 IX86_BUILTIN_CMPUNORDSD,
23750 IX86_BUILTIN_COMIEQSD,
23751 IX86_BUILTIN_COMILTSD,
23752 IX86_BUILTIN_COMILESD,
23753 IX86_BUILTIN_COMIGTSD,
23754 IX86_BUILTIN_COMIGESD,
23755 IX86_BUILTIN_COMINEQSD,
23756 IX86_BUILTIN_UCOMIEQSD,
23757 IX86_BUILTIN_UCOMILTSD,
23758 IX86_BUILTIN_UCOMILESD,
23759 IX86_BUILTIN_UCOMIGTSD,
23760 IX86_BUILTIN_UCOMIGESD,
23761 IX86_BUILTIN_UCOMINEQSD,
23763 IX86_BUILTIN_MAXPD,
23764 IX86_BUILTIN_MAXSD,
23765 IX86_BUILTIN_MINPD,
23766 IX86_BUILTIN_MINSD,
23768 IX86_BUILTIN_ANDPD,
23769 IX86_BUILTIN_ANDNPD,
23770 IX86_BUILTIN_ORPD,
23771 IX86_BUILTIN_XORPD,
23773 IX86_BUILTIN_SQRTPD,
23774 IX86_BUILTIN_SQRTSD,
23776 IX86_BUILTIN_UNPCKHPD,
23777 IX86_BUILTIN_UNPCKLPD,
23779 IX86_BUILTIN_SHUFPD,
23781 IX86_BUILTIN_LOADUPD,
23782 IX86_BUILTIN_STOREUPD,
23783 IX86_BUILTIN_MOVSD,
23785 IX86_BUILTIN_LOADHPD,
23786 IX86_BUILTIN_LOADLPD,
23788 IX86_BUILTIN_CVTDQ2PD,
23789 IX86_BUILTIN_CVTDQ2PS,
23791 IX86_BUILTIN_CVTPD2DQ,
23792 IX86_BUILTIN_CVTPD2PI,
23793 IX86_BUILTIN_CVTPD2PS,
23794 IX86_BUILTIN_CVTTPD2DQ,
23795 IX86_BUILTIN_CVTTPD2PI,
23797 IX86_BUILTIN_CVTPI2PD,
23798 IX86_BUILTIN_CVTSI2SD,
23799 IX86_BUILTIN_CVTSI642SD,
23801 IX86_BUILTIN_CVTSD2SI,
23802 IX86_BUILTIN_CVTSD2SI64,
23803 IX86_BUILTIN_CVTSD2SS,
23804 IX86_BUILTIN_CVTSS2SD,
23805 IX86_BUILTIN_CVTTSD2SI,
23806 IX86_BUILTIN_CVTTSD2SI64,
23808 IX86_BUILTIN_CVTPS2DQ,
23809 IX86_BUILTIN_CVTPS2PD,
23810 IX86_BUILTIN_CVTTPS2DQ,
23812 IX86_BUILTIN_MOVNTI,
23813 IX86_BUILTIN_MOVNTPD,
23814 IX86_BUILTIN_MOVNTDQ,
23816 IX86_BUILTIN_MOVQ128,
23818 /* SSE2 MMX */
23819 IX86_BUILTIN_MASKMOVDQU,
23820 IX86_BUILTIN_MOVMSKPD,
23821 IX86_BUILTIN_PMOVMSKB128,
23823 IX86_BUILTIN_PACKSSWB128,
23824 IX86_BUILTIN_PACKSSDW128,
23825 IX86_BUILTIN_PACKUSWB128,
23827 IX86_BUILTIN_PADDB128,
23828 IX86_BUILTIN_PADDW128,
23829 IX86_BUILTIN_PADDD128,
23830 IX86_BUILTIN_PADDQ128,
23831 IX86_BUILTIN_PADDSB128,
23832 IX86_BUILTIN_PADDSW128,
23833 IX86_BUILTIN_PADDUSB128,
23834 IX86_BUILTIN_PADDUSW128,
23835 IX86_BUILTIN_PSUBB128,
23836 IX86_BUILTIN_PSUBW128,
23837 IX86_BUILTIN_PSUBD128,
23838 IX86_BUILTIN_PSUBQ128,
23839 IX86_BUILTIN_PSUBSB128,
23840 IX86_BUILTIN_PSUBSW128,
23841 IX86_BUILTIN_PSUBUSB128,
23842 IX86_BUILTIN_PSUBUSW128,
23844 IX86_BUILTIN_PAND128,
23845 IX86_BUILTIN_PANDN128,
23846 IX86_BUILTIN_POR128,
23847 IX86_BUILTIN_PXOR128,
23849 IX86_BUILTIN_PAVGB128,
23850 IX86_BUILTIN_PAVGW128,
23852 IX86_BUILTIN_PCMPEQB128,
23853 IX86_BUILTIN_PCMPEQW128,
23854 IX86_BUILTIN_PCMPEQD128,
23855 IX86_BUILTIN_PCMPGTB128,
23856 IX86_BUILTIN_PCMPGTW128,
23857 IX86_BUILTIN_PCMPGTD128,
23859 IX86_BUILTIN_PMADDWD128,
23861 IX86_BUILTIN_PMAXSW128,
23862 IX86_BUILTIN_PMAXUB128,
23863 IX86_BUILTIN_PMINSW128,
23864 IX86_BUILTIN_PMINUB128,
23866 IX86_BUILTIN_PMULUDQ,
23867 IX86_BUILTIN_PMULUDQ128,
23868 IX86_BUILTIN_PMULHUW128,
23869 IX86_BUILTIN_PMULHW128,
23870 IX86_BUILTIN_PMULLW128,
23872 IX86_BUILTIN_PSADBW128,
23873 IX86_BUILTIN_PSHUFHW,
23874 IX86_BUILTIN_PSHUFLW,
23875 IX86_BUILTIN_PSHUFD,
23877 IX86_BUILTIN_PSLLDQI128,
23878 IX86_BUILTIN_PSLLWI128,
23879 IX86_BUILTIN_PSLLDI128,
23880 IX86_BUILTIN_PSLLQI128,
23881 IX86_BUILTIN_PSRAWI128,
23882 IX86_BUILTIN_PSRADI128,
23883 IX86_BUILTIN_PSRLDQI128,
23884 IX86_BUILTIN_PSRLWI128,
23885 IX86_BUILTIN_PSRLDI128,
23886 IX86_BUILTIN_PSRLQI128,
23888 IX86_BUILTIN_PSLLDQ128,
23889 IX86_BUILTIN_PSLLW128,
23890 IX86_BUILTIN_PSLLD128,
23891 IX86_BUILTIN_PSLLQ128,
23892 IX86_BUILTIN_PSRAW128,
23893 IX86_BUILTIN_PSRAD128,
23894 IX86_BUILTIN_PSRLW128,
23895 IX86_BUILTIN_PSRLD128,
23896 IX86_BUILTIN_PSRLQ128,
23898 IX86_BUILTIN_PUNPCKHBW128,
23899 IX86_BUILTIN_PUNPCKHWD128,
23900 IX86_BUILTIN_PUNPCKHDQ128,
23901 IX86_BUILTIN_PUNPCKHQDQ128,
23902 IX86_BUILTIN_PUNPCKLBW128,
23903 IX86_BUILTIN_PUNPCKLWD128,
23904 IX86_BUILTIN_PUNPCKLDQ128,
23905 IX86_BUILTIN_PUNPCKLQDQ128,
23907 IX86_BUILTIN_CLFLUSH,
23908 IX86_BUILTIN_MFENCE,
23909 IX86_BUILTIN_LFENCE,
23910 IX86_BUILTIN_PAUSE,
23912 IX86_BUILTIN_BSRSI,
23913 IX86_BUILTIN_BSRDI,
23914 IX86_BUILTIN_RDPMC,
23915 IX86_BUILTIN_RDTSC,
23916 IX86_BUILTIN_RDTSCP,
23917 IX86_BUILTIN_ROLQI,
23918 IX86_BUILTIN_ROLHI,
23919 IX86_BUILTIN_RORQI,
23920 IX86_BUILTIN_RORHI,
23922 /* SSE3. */
23923 IX86_BUILTIN_ADDSUBPS,
23924 IX86_BUILTIN_HADDPS,
23925 IX86_BUILTIN_HSUBPS,
23926 IX86_BUILTIN_MOVSHDUP,
23927 IX86_BUILTIN_MOVSLDUP,
23928 IX86_BUILTIN_ADDSUBPD,
23929 IX86_BUILTIN_HADDPD,
23930 IX86_BUILTIN_HSUBPD,
23931 IX86_BUILTIN_LDDQU,
23933 IX86_BUILTIN_MONITOR,
23934 IX86_BUILTIN_MWAIT,
23936 /* SSSE3. */
23937 IX86_BUILTIN_PHADDW,
23938 IX86_BUILTIN_PHADDD,
23939 IX86_BUILTIN_PHADDSW,
23940 IX86_BUILTIN_PHSUBW,
23941 IX86_BUILTIN_PHSUBD,
23942 IX86_BUILTIN_PHSUBSW,
23943 IX86_BUILTIN_PMADDUBSW,
23944 IX86_BUILTIN_PMULHRSW,
23945 IX86_BUILTIN_PSHUFB,
23946 IX86_BUILTIN_PSIGNB,
23947 IX86_BUILTIN_PSIGNW,
23948 IX86_BUILTIN_PSIGND,
23949 IX86_BUILTIN_PALIGNR,
23950 IX86_BUILTIN_PABSB,
23951 IX86_BUILTIN_PABSW,
23952 IX86_BUILTIN_PABSD,
23954 IX86_BUILTIN_PHADDW128,
23955 IX86_BUILTIN_PHADDD128,
23956 IX86_BUILTIN_PHADDSW128,
23957 IX86_BUILTIN_PHSUBW128,
23958 IX86_BUILTIN_PHSUBD128,
23959 IX86_BUILTIN_PHSUBSW128,
23960 IX86_BUILTIN_PMADDUBSW128,
23961 IX86_BUILTIN_PMULHRSW128,
23962 IX86_BUILTIN_PSHUFB128,
23963 IX86_BUILTIN_PSIGNB128,
23964 IX86_BUILTIN_PSIGNW128,
23965 IX86_BUILTIN_PSIGND128,
23966 IX86_BUILTIN_PALIGNR128,
23967 IX86_BUILTIN_PABSB128,
23968 IX86_BUILTIN_PABSW128,
23969 IX86_BUILTIN_PABSD128,
23971 /* AMDFAM10 - SSE4A New Instructions. */
23972 IX86_BUILTIN_MOVNTSD,
23973 IX86_BUILTIN_MOVNTSS,
23974 IX86_BUILTIN_EXTRQI,
23975 IX86_BUILTIN_EXTRQ,
23976 IX86_BUILTIN_INSERTQI,
23977 IX86_BUILTIN_INSERTQ,
23979 /* SSE4.1. */
23980 IX86_BUILTIN_BLENDPD,
23981 IX86_BUILTIN_BLENDPS,
23982 IX86_BUILTIN_BLENDVPD,
23983 IX86_BUILTIN_BLENDVPS,
23984 IX86_BUILTIN_PBLENDVB128,
23985 IX86_BUILTIN_PBLENDW128,
23987 IX86_BUILTIN_DPPD,
23988 IX86_BUILTIN_DPPS,
23990 IX86_BUILTIN_INSERTPS128,
23992 IX86_BUILTIN_MOVNTDQA,
23993 IX86_BUILTIN_MPSADBW128,
23994 IX86_BUILTIN_PACKUSDW128,
23995 IX86_BUILTIN_PCMPEQQ,
23996 IX86_BUILTIN_PHMINPOSUW128,
23998 IX86_BUILTIN_PMAXSB128,
23999 IX86_BUILTIN_PMAXSD128,
24000 IX86_BUILTIN_PMAXUD128,
24001 IX86_BUILTIN_PMAXUW128,
24003 IX86_BUILTIN_PMINSB128,
24004 IX86_BUILTIN_PMINSD128,
24005 IX86_BUILTIN_PMINUD128,
24006 IX86_BUILTIN_PMINUW128,
24008 IX86_BUILTIN_PMOVSXBW128,
24009 IX86_BUILTIN_PMOVSXBD128,
24010 IX86_BUILTIN_PMOVSXBQ128,
24011 IX86_BUILTIN_PMOVSXWD128,
24012 IX86_BUILTIN_PMOVSXWQ128,
24013 IX86_BUILTIN_PMOVSXDQ128,
24015 IX86_BUILTIN_PMOVZXBW128,
24016 IX86_BUILTIN_PMOVZXBD128,
24017 IX86_BUILTIN_PMOVZXBQ128,
24018 IX86_BUILTIN_PMOVZXWD128,
24019 IX86_BUILTIN_PMOVZXWQ128,
24020 IX86_BUILTIN_PMOVZXDQ128,
24022 IX86_BUILTIN_PMULDQ128,
24023 IX86_BUILTIN_PMULLD128,
24025 IX86_BUILTIN_ROUNDPD,
24026 IX86_BUILTIN_ROUNDPS,
24027 IX86_BUILTIN_ROUNDSD,
24028 IX86_BUILTIN_ROUNDSS,
24030 IX86_BUILTIN_FLOORPD,
24031 IX86_BUILTIN_CEILPD,
24032 IX86_BUILTIN_TRUNCPD,
24033 IX86_BUILTIN_RINTPD,
24034 IX86_BUILTIN_FLOORPS,
24035 IX86_BUILTIN_CEILPS,
24036 IX86_BUILTIN_TRUNCPS,
24037 IX86_BUILTIN_RINTPS,
24039 IX86_BUILTIN_PTESTZ,
24040 IX86_BUILTIN_PTESTC,
24041 IX86_BUILTIN_PTESTNZC,
24043 IX86_BUILTIN_VEC_INIT_V2SI,
24044 IX86_BUILTIN_VEC_INIT_V4HI,
24045 IX86_BUILTIN_VEC_INIT_V8QI,
24046 IX86_BUILTIN_VEC_EXT_V2DF,
24047 IX86_BUILTIN_VEC_EXT_V2DI,
24048 IX86_BUILTIN_VEC_EXT_V4SF,
24049 IX86_BUILTIN_VEC_EXT_V4SI,
24050 IX86_BUILTIN_VEC_EXT_V8HI,
24051 IX86_BUILTIN_VEC_EXT_V2SI,
24052 IX86_BUILTIN_VEC_EXT_V4HI,
24053 IX86_BUILTIN_VEC_EXT_V16QI,
24054 IX86_BUILTIN_VEC_SET_V2DI,
24055 IX86_BUILTIN_VEC_SET_V4SF,
24056 IX86_BUILTIN_VEC_SET_V4SI,
24057 IX86_BUILTIN_VEC_SET_V8HI,
24058 IX86_BUILTIN_VEC_SET_V4HI,
24059 IX86_BUILTIN_VEC_SET_V16QI,
24061 IX86_BUILTIN_VEC_PACK_SFIX,
24063 /* SSE4.2. */
24064 IX86_BUILTIN_CRC32QI,
24065 IX86_BUILTIN_CRC32HI,
24066 IX86_BUILTIN_CRC32SI,
24067 IX86_BUILTIN_CRC32DI,
24069 IX86_BUILTIN_PCMPESTRI128,
24070 IX86_BUILTIN_PCMPESTRM128,
24071 IX86_BUILTIN_PCMPESTRA128,
24072 IX86_BUILTIN_PCMPESTRC128,
24073 IX86_BUILTIN_PCMPESTRO128,
24074 IX86_BUILTIN_PCMPESTRS128,
24075 IX86_BUILTIN_PCMPESTRZ128,
24076 IX86_BUILTIN_PCMPISTRI128,
24077 IX86_BUILTIN_PCMPISTRM128,
24078 IX86_BUILTIN_PCMPISTRA128,
24079 IX86_BUILTIN_PCMPISTRC128,
24080 IX86_BUILTIN_PCMPISTRO128,
24081 IX86_BUILTIN_PCMPISTRS128,
24082 IX86_BUILTIN_PCMPISTRZ128,
24084 IX86_BUILTIN_PCMPGTQ,
24086 /* AES instructions */
24087 IX86_BUILTIN_AESENC128,
24088 IX86_BUILTIN_AESENCLAST128,
24089 IX86_BUILTIN_AESDEC128,
24090 IX86_BUILTIN_AESDECLAST128,
24091 IX86_BUILTIN_AESIMC128,
24092 IX86_BUILTIN_AESKEYGENASSIST128,
24094 /* PCLMUL instruction */
24095 IX86_BUILTIN_PCLMULQDQ128,
24097 /* AVX */
24098 IX86_BUILTIN_ADDPD256,
24099 IX86_BUILTIN_ADDPS256,
24100 IX86_BUILTIN_ADDSUBPD256,
24101 IX86_BUILTIN_ADDSUBPS256,
24102 IX86_BUILTIN_ANDPD256,
24103 IX86_BUILTIN_ANDPS256,
24104 IX86_BUILTIN_ANDNPD256,
24105 IX86_BUILTIN_ANDNPS256,
24106 IX86_BUILTIN_BLENDPD256,
24107 IX86_BUILTIN_BLENDPS256,
24108 IX86_BUILTIN_BLENDVPD256,
24109 IX86_BUILTIN_BLENDVPS256,
24110 IX86_BUILTIN_DIVPD256,
24111 IX86_BUILTIN_DIVPS256,
24112 IX86_BUILTIN_DPPS256,
24113 IX86_BUILTIN_HADDPD256,
24114 IX86_BUILTIN_HADDPS256,
24115 IX86_BUILTIN_HSUBPD256,
24116 IX86_BUILTIN_HSUBPS256,
24117 IX86_BUILTIN_MAXPD256,
24118 IX86_BUILTIN_MAXPS256,
24119 IX86_BUILTIN_MINPD256,
24120 IX86_BUILTIN_MINPS256,
24121 IX86_BUILTIN_MULPD256,
24122 IX86_BUILTIN_MULPS256,
24123 IX86_BUILTIN_ORPD256,
24124 IX86_BUILTIN_ORPS256,
24125 IX86_BUILTIN_SHUFPD256,
24126 IX86_BUILTIN_SHUFPS256,
24127 IX86_BUILTIN_SUBPD256,
24128 IX86_BUILTIN_SUBPS256,
24129 IX86_BUILTIN_XORPD256,
24130 IX86_BUILTIN_XORPS256,
24131 IX86_BUILTIN_CMPSD,
24132 IX86_BUILTIN_CMPSS,
24133 IX86_BUILTIN_CMPPD,
24134 IX86_BUILTIN_CMPPS,
24135 IX86_BUILTIN_CMPPD256,
24136 IX86_BUILTIN_CMPPS256,
24137 IX86_BUILTIN_CVTDQ2PD256,
24138 IX86_BUILTIN_CVTDQ2PS256,
24139 IX86_BUILTIN_CVTPD2PS256,
24140 IX86_BUILTIN_CVTPS2DQ256,
24141 IX86_BUILTIN_CVTPS2PD256,
24142 IX86_BUILTIN_CVTTPD2DQ256,
24143 IX86_BUILTIN_CVTPD2DQ256,
24144 IX86_BUILTIN_CVTTPS2DQ256,
24145 IX86_BUILTIN_EXTRACTF128PD256,
24146 IX86_BUILTIN_EXTRACTF128PS256,
24147 IX86_BUILTIN_EXTRACTF128SI256,
24148 IX86_BUILTIN_VZEROALL,
24149 IX86_BUILTIN_VZEROUPPER,
24150 IX86_BUILTIN_VPERMILVARPD,
24151 IX86_BUILTIN_VPERMILVARPS,
24152 IX86_BUILTIN_VPERMILVARPD256,
24153 IX86_BUILTIN_VPERMILVARPS256,
24154 IX86_BUILTIN_VPERMILPD,
24155 IX86_BUILTIN_VPERMILPS,
24156 IX86_BUILTIN_VPERMILPD256,
24157 IX86_BUILTIN_VPERMILPS256,
24158 IX86_BUILTIN_VPERMIL2PD,
24159 IX86_BUILTIN_VPERMIL2PS,
24160 IX86_BUILTIN_VPERMIL2PD256,
24161 IX86_BUILTIN_VPERMIL2PS256,
24162 IX86_BUILTIN_VPERM2F128PD256,
24163 IX86_BUILTIN_VPERM2F128PS256,
24164 IX86_BUILTIN_VPERM2F128SI256,
24165 IX86_BUILTIN_VBROADCASTSS,
24166 IX86_BUILTIN_VBROADCASTSD256,
24167 IX86_BUILTIN_VBROADCASTSS256,
24168 IX86_BUILTIN_VBROADCASTPD256,
24169 IX86_BUILTIN_VBROADCASTPS256,
24170 IX86_BUILTIN_VINSERTF128PD256,
24171 IX86_BUILTIN_VINSERTF128PS256,
24172 IX86_BUILTIN_VINSERTF128SI256,
24173 IX86_BUILTIN_LOADUPD256,
24174 IX86_BUILTIN_LOADUPS256,
24175 IX86_BUILTIN_STOREUPD256,
24176 IX86_BUILTIN_STOREUPS256,
24177 IX86_BUILTIN_LDDQU256,
24178 IX86_BUILTIN_MOVNTDQ256,
24179 IX86_BUILTIN_MOVNTPD256,
24180 IX86_BUILTIN_MOVNTPS256,
24181 IX86_BUILTIN_LOADDQU256,
24182 IX86_BUILTIN_STOREDQU256,
24183 IX86_BUILTIN_MASKLOADPD,
24184 IX86_BUILTIN_MASKLOADPS,
24185 IX86_BUILTIN_MASKSTOREPD,
24186 IX86_BUILTIN_MASKSTOREPS,
24187 IX86_BUILTIN_MASKLOADPD256,
24188 IX86_BUILTIN_MASKLOADPS256,
24189 IX86_BUILTIN_MASKSTOREPD256,
24190 IX86_BUILTIN_MASKSTOREPS256,
24191 IX86_BUILTIN_MOVSHDUP256,
24192 IX86_BUILTIN_MOVSLDUP256,
24193 IX86_BUILTIN_MOVDDUP256,
24195 IX86_BUILTIN_SQRTPD256,
24196 IX86_BUILTIN_SQRTPS256,
24197 IX86_BUILTIN_SQRTPS_NR256,
24198 IX86_BUILTIN_RSQRTPS256,
24199 IX86_BUILTIN_RSQRTPS_NR256,
24201 IX86_BUILTIN_RCPPS256,
24203 IX86_BUILTIN_ROUNDPD256,
24204 IX86_BUILTIN_ROUNDPS256,
24206 IX86_BUILTIN_FLOORPD256,
24207 IX86_BUILTIN_CEILPD256,
24208 IX86_BUILTIN_TRUNCPD256,
24209 IX86_BUILTIN_RINTPD256,
24210 IX86_BUILTIN_FLOORPS256,
24211 IX86_BUILTIN_CEILPS256,
24212 IX86_BUILTIN_TRUNCPS256,
24213 IX86_BUILTIN_RINTPS256,
24215 IX86_BUILTIN_UNPCKHPD256,
24216 IX86_BUILTIN_UNPCKLPD256,
24217 IX86_BUILTIN_UNPCKHPS256,
24218 IX86_BUILTIN_UNPCKLPS256,
24220 IX86_BUILTIN_SI256_SI,
24221 IX86_BUILTIN_PS256_PS,
24222 IX86_BUILTIN_PD256_PD,
24223 IX86_BUILTIN_SI_SI256,
24224 IX86_BUILTIN_PS_PS256,
24225 IX86_BUILTIN_PD_PD256,
24227 IX86_BUILTIN_VTESTZPD,
24228 IX86_BUILTIN_VTESTCPD,
24229 IX86_BUILTIN_VTESTNZCPD,
24230 IX86_BUILTIN_VTESTZPS,
24231 IX86_BUILTIN_VTESTCPS,
24232 IX86_BUILTIN_VTESTNZCPS,
24233 IX86_BUILTIN_VTESTZPD256,
24234 IX86_BUILTIN_VTESTCPD256,
24235 IX86_BUILTIN_VTESTNZCPD256,
24236 IX86_BUILTIN_VTESTZPS256,
24237 IX86_BUILTIN_VTESTCPS256,
24238 IX86_BUILTIN_VTESTNZCPS256,
24239 IX86_BUILTIN_PTESTZ256,
24240 IX86_BUILTIN_PTESTC256,
24241 IX86_BUILTIN_PTESTNZC256,
24243 IX86_BUILTIN_MOVMSKPD256,
24244 IX86_BUILTIN_MOVMSKPS256,
24246 /* TFmode support builtins. */
24247 IX86_BUILTIN_INFQ,
24248 IX86_BUILTIN_HUGE_VALQ,
24249 IX86_BUILTIN_FABSQ,
24250 IX86_BUILTIN_COPYSIGNQ,
24252 /* Vectorizer support builtins. */
24253 IX86_BUILTIN_CPYSGNPS,
24254 IX86_BUILTIN_CPYSGNPD,
24255 IX86_BUILTIN_CPYSGNPS256,
24256 IX86_BUILTIN_CPYSGNPD256,
24258 IX86_BUILTIN_CVTUDQ2PS,
24260 IX86_BUILTIN_VEC_PERM_V2DF,
24261 IX86_BUILTIN_VEC_PERM_V4SF,
24262 IX86_BUILTIN_VEC_PERM_V2DI,
24263 IX86_BUILTIN_VEC_PERM_V4SI,
24264 IX86_BUILTIN_VEC_PERM_V8HI,
24265 IX86_BUILTIN_VEC_PERM_V16QI,
24266 IX86_BUILTIN_VEC_PERM_V2DI_U,
24267 IX86_BUILTIN_VEC_PERM_V4SI_U,
24268 IX86_BUILTIN_VEC_PERM_V8HI_U,
24269 IX86_BUILTIN_VEC_PERM_V16QI_U,
24270 IX86_BUILTIN_VEC_PERM_V4DF,
24271 IX86_BUILTIN_VEC_PERM_V8SF,
24273 /* FMA4 and XOP instructions. */
24274 IX86_BUILTIN_VFMADDSS,
24275 IX86_BUILTIN_VFMADDSD,
24276 IX86_BUILTIN_VFMADDPS,
24277 IX86_BUILTIN_VFMADDPD,
24278 IX86_BUILTIN_VFMADDPS256,
24279 IX86_BUILTIN_VFMADDPD256,
24280 IX86_BUILTIN_VFMADDSUBPS,
24281 IX86_BUILTIN_VFMADDSUBPD,
24282 IX86_BUILTIN_VFMADDSUBPS256,
24283 IX86_BUILTIN_VFMADDSUBPD256,
24285 IX86_BUILTIN_VPCMOV,
24286 IX86_BUILTIN_VPCMOV_V2DI,
24287 IX86_BUILTIN_VPCMOV_V4SI,
24288 IX86_BUILTIN_VPCMOV_V8HI,
24289 IX86_BUILTIN_VPCMOV_V16QI,
24290 IX86_BUILTIN_VPCMOV_V4SF,
24291 IX86_BUILTIN_VPCMOV_V2DF,
24292 IX86_BUILTIN_VPCMOV256,
24293 IX86_BUILTIN_VPCMOV_V4DI256,
24294 IX86_BUILTIN_VPCMOV_V8SI256,
24295 IX86_BUILTIN_VPCMOV_V16HI256,
24296 IX86_BUILTIN_VPCMOV_V32QI256,
24297 IX86_BUILTIN_VPCMOV_V8SF256,
24298 IX86_BUILTIN_VPCMOV_V4DF256,
24300 IX86_BUILTIN_VPPERM,
24302 IX86_BUILTIN_VPMACSSWW,
24303 IX86_BUILTIN_VPMACSWW,
24304 IX86_BUILTIN_VPMACSSWD,
24305 IX86_BUILTIN_VPMACSWD,
24306 IX86_BUILTIN_VPMACSSDD,
24307 IX86_BUILTIN_VPMACSDD,
24308 IX86_BUILTIN_VPMACSSDQL,
24309 IX86_BUILTIN_VPMACSSDQH,
24310 IX86_BUILTIN_VPMACSDQL,
24311 IX86_BUILTIN_VPMACSDQH,
24312 IX86_BUILTIN_VPMADCSSWD,
24313 IX86_BUILTIN_VPMADCSWD,
24315 IX86_BUILTIN_VPHADDBW,
24316 IX86_BUILTIN_VPHADDBD,
24317 IX86_BUILTIN_VPHADDBQ,
24318 IX86_BUILTIN_VPHADDWD,
24319 IX86_BUILTIN_VPHADDWQ,
24320 IX86_BUILTIN_VPHADDDQ,
24321 IX86_BUILTIN_VPHADDUBW,
24322 IX86_BUILTIN_VPHADDUBD,
24323 IX86_BUILTIN_VPHADDUBQ,
24324 IX86_BUILTIN_VPHADDUWD,
24325 IX86_BUILTIN_VPHADDUWQ,
24326 IX86_BUILTIN_VPHADDUDQ,
24327 IX86_BUILTIN_VPHSUBBW,
24328 IX86_BUILTIN_VPHSUBWD,
24329 IX86_BUILTIN_VPHSUBDQ,
24331 IX86_BUILTIN_VPROTB,
24332 IX86_BUILTIN_VPROTW,
24333 IX86_BUILTIN_VPROTD,
24334 IX86_BUILTIN_VPROTQ,
24335 IX86_BUILTIN_VPROTB_IMM,
24336 IX86_BUILTIN_VPROTW_IMM,
24337 IX86_BUILTIN_VPROTD_IMM,
24338 IX86_BUILTIN_VPROTQ_IMM,
24340 IX86_BUILTIN_VPSHLB,
24341 IX86_BUILTIN_VPSHLW,
24342 IX86_BUILTIN_VPSHLD,
24343 IX86_BUILTIN_VPSHLQ,
24344 IX86_BUILTIN_VPSHAB,
24345 IX86_BUILTIN_VPSHAW,
24346 IX86_BUILTIN_VPSHAD,
24347 IX86_BUILTIN_VPSHAQ,
24349 IX86_BUILTIN_VFRCZSS,
24350 IX86_BUILTIN_VFRCZSD,
24351 IX86_BUILTIN_VFRCZPS,
24352 IX86_BUILTIN_VFRCZPD,
24353 IX86_BUILTIN_VFRCZPS256,
24354 IX86_BUILTIN_VFRCZPD256,
24356 IX86_BUILTIN_VPCOMEQUB,
24357 IX86_BUILTIN_VPCOMNEUB,
24358 IX86_BUILTIN_VPCOMLTUB,
24359 IX86_BUILTIN_VPCOMLEUB,
24360 IX86_BUILTIN_VPCOMGTUB,
24361 IX86_BUILTIN_VPCOMGEUB,
24362 IX86_BUILTIN_VPCOMFALSEUB,
24363 IX86_BUILTIN_VPCOMTRUEUB,
24365 IX86_BUILTIN_VPCOMEQUW,
24366 IX86_BUILTIN_VPCOMNEUW,
24367 IX86_BUILTIN_VPCOMLTUW,
24368 IX86_BUILTIN_VPCOMLEUW,
24369 IX86_BUILTIN_VPCOMGTUW,
24370 IX86_BUILTIN_VPCOMGEUW,
24371 IX86_BUILTIN_VPCOMFALSEUW,
24372 IX86_BUILTIN_VPCOMTRUEUW,
24374 IX86_BUILTIN_VPCOMEQUD,
24375 IX86_BUILTIN_VPCOMNEUD,
24376 IX86_BUILTIN_VPCOMLTUD,
24377 IX86_BUILTIN_VPCOMLEUD,
24378 IX86_BUILTIN_VPCOMGTUD,
24379 IX86_BUILTIN_VPCOMGEUD,
24380 IX86_BUILTIN_VPCOMFALSEUD,
24381 IX86_BUILTIN_VPCOMTRUEUD,
24383 IX86_BUILTIN_VPCOMEQUQ,
24384 IX86_BUILTIN_VPCOMNEUQ,
24385 IX86_BUILTIN_VPCOMLTUQ,
24386 IX86_BUILTIN_VPCOMLEUQ,
24387 IX86_BUILTIN_VPCOMGTUQ,
24388 IX86_BUILTIN_VPCOMGEUQ,
24389 IX86_BUILTIN_VPCOMFALSEUQ,
24390 IX86_BUILTIN_VPCOMTRUEUQ,
24392 IX86_BUILTIN_VPCOMEQB,
24393 IX86_BUILTIN_VPCOMNEB,
24394 IX86_BUILTIN_VPCOMLTB,
24395 IX86_BUILTIN_VPCOMLEB,
24396 IX86_BUILTIN_VPCOMGTB,
24397 IX86_BUILTIN_VPCOMGEB,
24398 IX86_BUILTIN_VPCOMFALSEB,
24399 IX86_BUILTIN_VPCOMTRUEB,
24401 IX86_BUILTIN_VPCOMEQW,
24402 IX86_BUILTIN_VPCOMNEW,
24403 IX86_BUILTIN_VPCOMLTW,
24404 IX86_BUILTIN_VPCOMLEW,
24405 IX86_BUILTIN_VPCOMGTW,
24406 IX86_BUILTIN_VPCOMGEW,
24407 IX86_BUILTIN_VPCOMFALSEW,
24408 IX86_BUILTIN_VPCOMTRUEW,
24410 IX86_BUILTIN_VPCOMEQD,
24411 IX86_BUILTIN_VPCOMNED,
24412 IX86_BUILTIN_VPCOMLTD,
24413 IX86_BUILTIN_VPCOMLED,
24414 IX86_BUILTIN_VPCOMGTD,
24415 IX86_BUILTIN_VPCOMGED,
24416 IX86_BUILTIN_VPCOMFALSED,
24417 IX86_BUILTIN_VPCOMTRUED,
24419 IX86_BUILTIN_VPCOMEQQ,
24420 IX86_BUILTIN_VPCOMNEQ,
24421 IX86_BUILTIN_VPCOMLTQ,
24422 IX86_BUILTIN_VPCOMLEQ,
24423 IX86_BUILTIN_VPCOMGTQ,
24424 IX86_BUILTIN_VPCOMGEQ,
24425 IX86_BUILTIN_VPCOMFALSEQ,
24426 IX86_BUILTIN_VPCOMTRUEQ,
24428 /* LWP instructions. */
24429 IX86_BUILTIN_LLWPCB,
24430 IX86_BUILTIN_SLWPCB,
24431 IX86_BUILTIN_LWPVAL32,
24432 IX86_BUILTIN_LWPVAL64,
24433 IX86_BUILTIN_LWPINS32,
24434 IX86_BUILTIN_LWPINS64,
24436 IX86_BUILTIN_CLZS,
24438 /* BMI instructions. */
24439 IX86_BUILTIN_BEXTR32,
24440 IX86_BUILTIN_BEXTR64,
24441 IX86_BUILTIN_CTZS,
24443 /* TBM instructions. */
24444 IX86_BUILTIN_BEXTRI32,
24445 IX86_BUILTIN_BEXTRI64,
24448 /* FSGSBASE instructions. */
24449 IX86_BUILTIN_RDFSBASE32,
24450 IX86_BUILTIN_RDFSBASE64,
24451 IX86_BUILTIN_RDGSBASE32,
24452 IX86_BUILTIN_RDGSBASE64,
24453 IX86_BUILTIN_WRFSBASE32,
24454 IX86_BUILTIN_WRFSBASE64,
24455 IX86_BUILTIN_WRGSBASE32,
24456 IX86_BUILTIN_WRGSBASE64,
24458 /* RDRND instructions. */
24459 IX86_BUILTIN_RDRAND16_STEP,
24460 IX86_BUILTIN_RDRAND32_STEP,
24461 IX86_BUILTIN_RDRAND64_STEP,
24463 /* F16C instructions. */
24464 IX86_BUILTIN_CVTPH2PS,
24465 IX86_BUILTIN_CVTPH2PS256,
24466 IX86_BUILTIN_CVTPS2PH,
24467 IX86_BUILTIN_CVTPS2PH256,
24469 /* CFString built-in for darwin */
24470 IX86_BUILTIN_CFSTRING,
24472 IX86_BUILTIN_MAX
24473 };
24475 /* Table for the ix86 builtin decls. */
24478 /* Table of all of the builtin functions that are possible with different ISA's
24479 but are waiting to be built until a function is declared to use that
24480 ISA. */
24487 };
24492 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
24493 of which isa_flags to use in the ix86_builtins_isa array. Stores the
24494 function decl in the ix86_builtins array. Returns the function decl or
24495 NULL_TREE, if the builtin was not added.
24497 If the front end has a special hook for builtin functions, delay adding
24498 builtin functions that aren't in the current ISA until the ISA is changed
24499 with function specific optimization. Doing so, can save about 300K for the
24500 default compiler. When the builtin is expanded, check at that time whether
24501 it is valid.
24503 If the front end doesn't have a special hook, record all builtins, even if
24504 it isn't an instruction set in the current ISA in case the user uses
24505 function specific options for a different ISA, so that we don't get scope
24506 errors if a builtin is added in the middle of a function scope. */
24511 {
24515 {
24524 {
24530 }
24531 else
24532 {
24538 }
24539 }
24542 }
24544 /* Like def_builtin, but also marks the function decl "const". */
24549 {
24553 else
24557 }
24559 /* Add any new builtin functions for a given ISA that may not have been
24560 declared. This saves a bit of space compared to adding all of the
24561 declarations to the tree, even if we didn't use them. */
24563 static void
24565 {
24569 {
24572 {
24575 /* Don't define the builtin again. */
24581 NULL_TREE);
24586 }
24587 }
24588 }
24590 /* Bits for builtin_description.flag. */
24592 /* Set when we don't support the comparison natively, and should
24593 swap_comparison in order to support it. */
24594 #define BUILTIN_DESC_SWAP_OPERANDS 1
24596 struct builtin_description
24597 {
24604 };
24607 {
24608 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
24609 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
24610 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
24611 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
24612 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
24613 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
24614 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
24615 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
24616 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
24617 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
24618 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
24619 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
24620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
24621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
24622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
24623 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
24624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
24625 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
24626 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
24627 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
24628 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
24629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
24630 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
24631 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
24632 };
24635 {
24636 /* SSE4.2 */
24637 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
24638 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
24639 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
24640 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
24641 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
24642 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
24643 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
24644 };
24647 {
24648 /* SSE4.2 */
24649 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
24650 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
24651 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
24652 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
24653 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
24654 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
24655 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
24656 };
24658 /* Special builtins with variable number of arguments. */
24660 {
24661 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
24662 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
24663 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
24665 /* MMX */
24666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24668 /* 3DNow! */
24669 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
24671 /* SSE */
24672 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24673 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24674 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24676 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24677 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
24678 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24679 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
24681 /* SSE or 3DNow!A */
24682 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24683 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
24685 /* SSE2 */
24686 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24687 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
24688 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
24690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
24692 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
24693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
24694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
24699 /* SSE3 */
24700 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
24702 /* SSE4.1 */
24703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
24705 /* SSE4A */
24706 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
24707 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
24709 /* AVX */
24710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
24711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
24713 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
24714 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24715 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
24717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
24719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
24720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
24721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
24725 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
24727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
24728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
24729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
24731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
24732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
24733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
24734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
24735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
24736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
24737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
24738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
24740 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
24741 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
24742 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
24743 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
24744 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
24745 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
24747 /* FSGSBASE */
24748 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24749 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24750 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
24751 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
24752 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24753 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24754 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
24755 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
24756 };
24758 /* Builtins with variable number of arguments. */
24760 {
24761 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
24762 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
24763 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
24764 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24765 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24766 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
24767 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
24769 /* MMX */
24770 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24771 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24772 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24773 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24774 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24775 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24777 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24778 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24779 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24780 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24781 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24782 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24783 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24784 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24786 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24787 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24789 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24790 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24791 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24792 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24794 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24795 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24796 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24797 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24798 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24799 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24801 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24802 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24803 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
24804 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24805 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
24806 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
24808 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24809 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
24810 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
24812 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
24814 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24815 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24816 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24817 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24818 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24819 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24821 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24822 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24823 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
24824 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24825 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24826 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
24828 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
24829 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
24830 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
24831 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
24833 /* 3DNow! */
24834 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24835 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24836 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24837 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24839 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24840 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24841 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24842 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24843 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24844 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
24845 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24846 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24847 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24848 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24849 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24850 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24851 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24852 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24853 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24855 /* 3DNow!A */
24856 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
24857 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
24858 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
24859 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
24860 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24861 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
24863 /* SSE */
24864 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
24865 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24866 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24867 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24868 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24869 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
24870 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24871 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24872 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24873 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
24874 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
24875 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
24877 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
24879 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24880 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24881 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24882 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24883 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24884 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24885 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24886 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24888 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24889 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24890 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24891 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24892 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24893 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24894 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24895 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24896 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24897 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24898 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
24899 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24900 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
24901 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
24902 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
24903 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24904 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
24905 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
24906 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
24907 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24908 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
24909 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
24911 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24912 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24916 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24918 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24919 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24921 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24926 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24927 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
24929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
24930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
24931 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
24933 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
24935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
24939 /* SSE MMX or 3Dnow!A */
24940 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24941 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24942 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24944 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24945 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24946 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
24947 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
24949 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
24950 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
24952 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
24954 /* SSE2 */
24955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
24957 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2df", IX86_BUILTIN_VEC_PERM_V2DF, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI },
24958 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4sf", IX86_BUILTIN_VEC_PERM_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI },
24959 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di", IX86_BUILTIN_VEC_PERM_V2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI },
24960 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si", IX86_BUILTIN_VEC_PERM_V4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
24961 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi", IX86_BUILTIN_VEC_PERM_V8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI },
24962 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi", IX86_BUILTIN_VEC_PERM_V16QI, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
24963 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v2di_u", IX86_BUILTIN_VEC_PERM_V2DI_U, UNKNOWN, (int) V2UDI_FTYPE_V2UDI_V2UDI_V2UDI },
24964 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4si_u", IX86_BUILTIN_VEC_PERM_V4SI_U, UNKNOWN, (int) V4USI_FTYPE_V4USI_V4USI_V4USI },
24965 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8hi_u", IX86_BUILTIN_VEC_PERM_V8HI_U, UNKNOWN, (int) V8UHI_FTYPE_V8UHI_V8UHI_V8UHI },
24966 { OPTION_MASK_ISA_SSE2, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v16qi_u", IX86_BUILTIN_VEC_PERM_V16QI_U, UNKNOWN, (int) V16UQI_FTYPE_V16UQI_V16UQI_V16UQI },
24967 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v4df", IX86_BUILTIN_VEC_PERM_V4DF, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI },
24968 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin_ia32_vec_perm_v8sf", IX86_BUILTIN_VEC_PERM_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI },
24970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
24971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
24972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
24973 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
24974 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24975 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
24977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
24980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
24981 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
24983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
24985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
24987 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24988 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
24990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24991 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
24992 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
24994 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24995 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24996 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24997 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24998 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
24999 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25000 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25001 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25003 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
25004 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
25005 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
25006 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
25007 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
25008 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
25009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
25010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
25011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
25012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
25013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
25014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
25015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
25016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
25017 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
25018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
25019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
25020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
25021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
25022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
25024 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25025 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25027 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25029 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25031 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25032 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25034 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25037 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25038 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25040 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
25042 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25043 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25044 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25045 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25046 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25047 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25048 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25049 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25051 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25052 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25053 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25054 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25055 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25056 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25057 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25058 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25060 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25061 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
25063 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25065 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25066 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25068 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25074 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25076 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25078 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25079 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25080 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25081 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25083 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25084 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25085 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25086 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25087 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25088 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25089 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25090 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
25093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
25094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
25096 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
25099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
25100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
25102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
25104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
25105 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
25106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
25107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
25109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
25110 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
25111 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
25112 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
25113 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
25114 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
25115 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
25117 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
25118 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
25119 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
25120 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
25121 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
25122 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
25123 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
25125 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
25126 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
25127 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
25128 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
25130 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
25131 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
25132 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
25134 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
25136 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
25137 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
25139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
25141 /* SSE2 MMX */
25142 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
25143 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
25145 /* SSE3 */
25146 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
25147 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
25149 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25150 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25151 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25152 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25153 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
25154 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
25156 /* SSSE3 */
25157 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
25158 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
25159 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
25160 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
25161 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
25162 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
25164 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25165 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25166 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25167 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25168 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25169 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25170 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25171 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25172 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25173 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25174 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25175 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25176 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
25177 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
25178 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25179 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25180 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25181 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
25182 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25183 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
25184 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25185 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
25186 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25187 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
25189 /* SSSE3. */
25190 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
25191 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
25193 /* SSE4.1 */
25194 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25195 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25196 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
25197 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
25198 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25199 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25200 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25201 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
25202 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
25203 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
25205 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
25206 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
25207 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
25208 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
25209 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
25210 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
25211 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
25212 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
25213 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
25214 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
25215 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
25216 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
25217 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
25219 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
25220 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25221 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25222 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25223 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25224 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25225 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
25226 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25227 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25228 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
25229 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
25230 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
25232 /* SSE4.1 */
25233 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
25234 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
25235 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25236 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25238 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
25239 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
25240 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
25241 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
25243 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
25244 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
25245 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
25246 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
25248 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25249 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25250 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
25252 /* SSE4.2 */
25253 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25254 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
25255 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
25256 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25257 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25259 /* SSE4A */
25260 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
25261 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
25262 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
25263 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25265 /* AES */
25266 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
25267 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
25269 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25270 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25271 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25272 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
25274 /* PCLMUL */
25275 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
25277 /* AVX */
25278 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25279 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25280 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25281 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25282 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25283 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25284 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25285 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25286 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25287 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25288 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25289 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25290 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25291 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25292 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25293 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25294 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25295 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25296 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25297 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25298 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25299 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25300 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25301 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25302 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25303 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25305 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
25306 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
25307 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
25308 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
25310 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25311 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25312 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
25313 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
25314 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25315 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25316 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25317 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25318 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25319 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
25320 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
25321 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25322 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25323 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
25324 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
25325 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
25326 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
25327 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
25328 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
25329 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25330 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
25331 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25332 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
25333 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
25334 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
25335 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
25336 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
25337 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
25338 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
25339 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25340 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25341 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
25342 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
25343 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
25345 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25346 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25347 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25349 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
25350 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25351 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25352 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25353 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25355 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
25357 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
25358 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
25360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
25361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
25362 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
25363 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
25365 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
25366 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
25367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
25368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
25370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25372 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25373 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25375 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
25376 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
25377 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
25378 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
25379 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
25380 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
25382 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25383 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25384 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
25385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
25388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25389 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
25391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
25394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25395 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
25398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
25399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
25401 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
25402 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
25404 { OPTION_MASK_ISA_ABM, CODE_FOR_clzhi2_abm, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25406 /* BMI */
25407 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25408 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25409 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
25411 /* TBM */
25412 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
25413 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
25415 /* F16C */
25416 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
25417 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
25418 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
25419 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
25420 };
25422 /* FMA4 and XOP. */
25423 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
25424 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
25425 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
25426 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
25427 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
25428 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
25429 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
25430 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
25431 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
25432 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
25433 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
25434 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
25435 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
25436 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
25437 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
25438 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
25439 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
25440 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
25441 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
25442 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
25443 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
25444 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
25445 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
25446 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
25447 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
25448 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
25449 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
25450 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
25451 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
25452 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
25453 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
25454 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
25455 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
25456 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
25457 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
25458 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
25459 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
25460 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
25461 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
25462 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
25463 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
25464 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
25465 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
25466 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
25467 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
25468 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
25469 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
25470 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
25471 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
25472 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
25473 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
25474 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
25477 {
25511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
25512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
25513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
25514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
25515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
25516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
25517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
25519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
25521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
25522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
25523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
25524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
25525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
25527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
25529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
25531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
25535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
25539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
25542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
25544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
25545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
25546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
25547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
25548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
25549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
25550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
25552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
25553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
25554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
25555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
25556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
25557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
25559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
25560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
25561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
25562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
25563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
25564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
25566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
25574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
25575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
25577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
25579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
25580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
25582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
25583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
25585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
25586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
25587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
25588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
25590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
25591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
25593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
25594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
25595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
25596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
25598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
25599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
25601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
25602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
25603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
25604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
25606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
25609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
25610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
25611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
25612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
25614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
25615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
25617 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
25618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
25619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
25620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
25622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
25623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
25625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
25626 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
25627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
25628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
25630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
25631 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25632 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
25633 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
25634 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
25635 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
25636 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
25638 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
25639 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25640 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
25641 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
25642 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
25643 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
25644 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
25646 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25647 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25648 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25649 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25650 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
25651 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
25652 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
25653 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
25655 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25656 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25657 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25658 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25659 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
25660 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
25661 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
25662 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
25664 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
25665 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
25666 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
25667 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
25669 };
25671 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
25672 in the current target ISA to allow the user to compile particular modules
25673 with different target specific options that differ from the command line
25674 options. */
25675 static void
25677 {
25682 /* Add all special builtins with variable number of operands. */
25686 {
25692 }
25694 /* Add all builtins with variable number of operands. */
25698 {
25704 }
25706 /* pcmpestr[im] insns. */
25710 {
25713 else
25716 }
25718 /* pcmpistr[im] insns. */
25722 {
25725 else
25728 }
25730 /* comi/ucomi insns. */
25732 {
25735 else
25738 }
25740 /* SSE */
25746 /* SSE or 3DNow!A */
25749 IX86_BUILTIN_MASKMOVQ);
25751 /* SSE2 */
25760 /* SSE3. */
25766 /* AES */
25780 /* PCLMUL */
25784 /* RDRND */
25791 IX86_BUILTIN_RDRAND64_STEP);
25793 /* MMX access to the vec_init patterns. */
25798 V4HI_FTYPE_HI_HI_HI_HI,
25799 IX86_BUILTIN_VEC_INIT_V4HI);
25802 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
25803 IX86_BUILTIN_VEC_INIT_V8QI);
25805 /* Access to the vec_extract patterns. */
25827 /* Access to the vec_set patterns. */
25848 /* Add FMA4 multi-arg argument instructions */
25850 {
25856 }
25857 }
25859 /* Internal method for ix86_init_builtins. */
25861 static void
25863 {
25875 sysv_va_ref =
25878 fnvoid_va_end_ms =
25880 fnvoid_va_start_ms =
25882 fnvoid_va_end_sysv =
25884 fnvoid_va_start_sysv =
25886 NULL_TREE);
25887 fnvoid_va_copy_ms =
25889 NULL_TREE);
25890 fnvoid_va_copy_sysv =
25906 }
25908 static void
25910 {
25913 /* The __float80 type. */
25916 {
25917 /* The __float80 type. */
25922 }
25925 /* The __float128 type. */
25931 /* This macro is built by i386-builtin-types.awk. */
25932 DEFINE_BUILTIN_PRIMITIVE_TYPES;
25933 }
25935 static void
25937 {
25938 tree t;
25942 /* TFmode support builtins. */
25948 /* We will expand them to normal call if SSE2 isn't available since
25949 they are used by libgcc. */
25967 #ifdef SUBTARGET_INIT_BUILTINS
25968 SUBTARGET_INIT_BUILTINS;
25969 #endif
25970 }
25972 /* Return the ix86 builtin for CODE. */
25974 static tree
25976 {
25981 }
25983 /* Errors in the source file can cause expand_expr to return const0_rtx
25984 where we expect a vector. To avoid crashing, use one of the vector
25985 clear instructions. */
25986 static rtx
25988 {
25992 }
25994 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
25996 static rtx
25998 {
25999 rtx pat;
26019 {
26023 }
26037 }
26039 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
26041 static rtx
26045 {
26046 rtx pat;
26054 rtx op;
26061 {
26141 }
26151 {
26158 {
26160 {
26163 }
26164 }
26165 else
26166 {
26170 /* If we aren't optimizing, only allow one memory operand to be
26171 generated. */
26173 num_memory++;
26181 }
26185 }
26188 {
26199 else
26200 {
26206 }
26219 }
26226 }
26228 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
26229 insns with vec_merge. */
26231 static rtx
26233 rtx target)
26234 {
26235 rtx pat;
26262 }
26264 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
26266 static rtx
26269 {
26270 rtx pat;
26275 rtx op2;
26286 /* Swap operands if we have a comparison that isn't available in
26287 hardware. */
26289 {
26294 }
26314 }
26316 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
26318 static rtx
26320 rtx target)
26321 {
26322 rtx pat;
26336 /* Swap operands if we have a comparison that isn't available in
26337 hardware. */
26339 {
26343 }
26364 const0_rtx)));
26367 }
26369 /* Subroutine of ix86_expand_args_builtin to take care of round insns. */
26371 static rtx
26373 rtx target)
26374 {
26375 rtx pat;
26400 }
26402 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
26404 static rtx
26406 rtx target)
26407 {
26408 rtx pat;
26441 const0_rtx)));
26444 }
26446 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
26448 static rtx
26451 {
26452 rtx pat;
26490 {
26493 }
26496 {
26505 }
26507 {
26516 }
26517 else
26518 {
26525 }
26533 {
26538 emit_insn
26542 FLAGS_REG),
26543 const0_rtx)));
26545 }
26546 else
26548 }
26551 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
26553 static rtx
26556 {
26557 rtx pat;
26585 {
26588 }
26591 {
26600 }
26602 {
26611 }
26612 else
26613 {
26620 }
26628 {
26633 emit_insn
26637 FLAGS_REG),
26638 const0_rtx)));
26640 }
26641 else
26643 }
26645 /* Subroutine of ix86_expand_builtin to take care of insns with
26646 variable number of operands. */
26648 static rtx
26651 {
26656 struct
26657 {
26658 rtx op;
26670 {
26890 }
26895 {
26898 }
26901 {
26908 }
26909 else
26910 {
26913 }
26916 {
26923 {
26924 /* SIMD shift insns take either an 8-bit immediate or
26925 register as count. But builtin functions take int as
26926 count. If count doesn't match, we put it in register. */
26928 {
26932 }
26933 }
26935 {
26938 {
26980 {
26983 {
26986 }
26992 }
26994 }
26995 }
26996 else
26997 {
27001 /* If we aren't optimizing, only allow one memory operand to
27002 be generated. */
27004 num_memory++;
27007 {
27010 }
27011 else
27012 {
27015 }
27016 }
27020 }
27023 {
27040 }
27047 }
27049 /* Subroutine of ix86_expand_builtin to take care of special insns
27050 with variable number of operands. */
27052 static rtx
27055 {
27056 tree arg;
27059 struct
27060 {
27061 rtx op;
27071 {
27118 /* Reserve memory operand for target. */
27141 /* Reserve memory operand for target. */
27155 }
27160 {
27166 else
27169 }
27170 else
27171 {
27178 }
27181 {
27190 {
27192 {
27198 else
27201 }
27202 }
27203 else
27204 {
27206 {
27207 /* This must be the memory operand. */
27211 }
27212 else
27213 {
27214 /* This must be register. */
27221 }
27222 }
27226 }
27229 {
27244 }
27250 }
27252 /* Return the integer constant in ARG. Constrain it to be in the range
27253 of the subparts of VEC_TYPE; issue an error if not. */
27255 static int
27257 {
27262 {
27265 }
27268 }
27270 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27271 ix86_expand_vector_init. We DO have language-level syntax for this, in
27272 the form of (type){ init-list }. Except that since we can't place emms
27273 instructions from inside the compiler, we can't allow the use of MMX
27274 registers unless the user explicitly asks for it. So we do *not* define
27275 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
27276 we have builtins invoked by mmintrin.h that gives us license to emit
27277 these sorts of instructions. */
27279 static rtx
27281 {
27291 {
27294 }
27301 }
27303 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27304 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
27305 had a language-level syntax for referencing vector elements. */
27307 static rtx
27309 {
27313 rtx op0;
27333 }
27335 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
27336 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
27337 a language-level syntax for referencing vector elements. */
27339 static rtx
27341 {
27365 /* OP0 is the source of these builtin functions and shouldn't be
27366 modified. Create a copy, use it and return it as target. */
27372 }
27374 /* Expand an expression EXP that calls a built-in function,
27375 with result going to TARGET if that's convenient
27376 (and in mode MODE if that's convenient).
27377 SUBTARGET may be used as the target for computing one of EXP's operands.
27378 IGNORE is nonzero if the value is to be ignored. */
27380 static rtx
27384 {
27394 /* Determine whether the builtin function is available under the current ISA.
27395 Originally the builtin was not created if it wasn't applicable to the
27396 current ISA based on the command line switches. With function specific
27397 options, we need to check in the context of the function making the call
27398 whether it is supported. */
27401 {
27407 else
27408 {
27412 }
27414 }
27417 {
27421 ? CODE_FOR_mmx_maskmovq
27423 /* Note the arg order is different from the operand order. */
27538 {
27539 REAL_VALUE_TYPE inf;
27540 rtx tmp;
27552 }
27578 ? CODE_FOR_tbm_bextri_si
27581 {
27584 }
27585 else
27586 {
27595 }
27611 rdrand_step:
27624 /* Emit SImode conditional move. */
27626 {
27629 }
27632 else
27639 const0_rtx);
27646 }
27659 {
27663 /* Emit a normal call if SSE2 isn't available. */
27667 }
27692 }
27694 /* Returns a function decl for a vectorized version of the builtin function
27695 with builtin function code FN and the result vector type TYPE, or NULL_TREE
27696 if it is not available. */
27698 static tree
27700 tree type_in)
27701 {
27717 {
27720 {
27725 }
27730 {
27735 }
27746 {
27751 }
27756 {
27761 }
27766 {
27771 }
27775 /* The round insn does not trap on denormals. */
27780 {
27785 }
27789 /* The round insn does not trap on denormals. */
27794 {
27799 }
27803 /* The round insn does not trap on denormals. */
27808 {
27813 }
27817 /* The round insn does not trap on denormals. */
27822 {
27827 }
27831 /* The round insn does not trap on denormals. */
27836 {
27841 }
27845 /* The round insn does not trap on denormals. */
27850 {
27855 }
27859 /* The round insn does not trap on denormals. */
27864 {
27869 }
27873 /* The round insn does not trap on denormals. */
27878 {
27883 }
27888 {
27893 }
27898 {
27903 }
27908 }
27910 /* Dispatch to a handler for a vectorization library. */
27913 type_in);
27916 }
27918 /* Handler for an SVML-style interface to
27919 a library with vectorized intrinsics. */
27921 static tree
27923 {
27931 /* The SVML is suitable for unsafe math only. */
27944 {
27991 }
28000 {
28003 }
28004 else
28007 /* Convert to uppercase. */
28013 arity++;
28017 else
28020 /* Build a function declaration for the vectorized function. */
28029 }
28031 /* Handler for an ACML-style interface to
28032 a library with vectorized intrinsics. */
28034 static tree
28036 {
28044 /* The ACML is 64bits only and suitable for unsafe math only as
28045 it does not correctly support parts of IEEE with the required
28046 precision such as denormals. */
28060 {
28090 }
28098 arity++;
28102 else
28105 /* Build a function declaration for the vectorized function. */
28114 }
28117 /* Returns a decl of a function that implements conversion of an integer vector
28118 into a floating-point vector, or vice-versa. DEST_TYPE and SRC_TYPE
28119 are the types involved when converting according to CODE.
28120 Return NULL_TREE if it is not available. */
28122 static tree
28125 {
28130 {
28133 {
28136 {
28143 ? NULL_TREE
28147 }
28151 {
28154 ? NULL_TREE
28158 }
28162 }
28166 {
28169 {
28172 ? NULL_TREE
28176 ? NULL_TREE
28180 }
28185 {
28188 ? NULL_TREE
28192 }
28197 }
28201 }
28204 }
28206 /* Returns a code for a target-specific builtin that implements
28207 reciprocal of the function, or NULL_TREE if not available. */
28209 static tree
28212 {
28219 /* Machine dependent builtins. */
28221 {
28222 /* Vectorized version of sqrt to rsqrt conversion. */
28231 }
28232 else
28233 /* Normal builtins. */
28235 {
28236 /* Sqrt to rsqrt conversion. */
28242 }
28243 }
28244 \f
28245 /* Helper for avx_vpermilps256_operand et al. This is also used by
28246 the expansion functions to turn the parallel back into a mask.
28247 The return value is 0 for no match and the imm8+1 for a match. */
28249 int
28251 {
28259 /* Validate that all of the elements are constants, and not totally
28260 out of range. Copy the data into an integral array to make the
28261 subsequent checks easier. */
28263 {
28273 }
28276 {
28278 /* In the 256-bit DFmode case, we can only move elements within
28279 a 128-bit lane. */
28281 {
28285 }
28287 {
28291 }
28295 /* In the 256-bit SFmode case, we have full freedom of movement
28296 within the low 128-bit lane, but the high 128-bit lane must
28297 mirror the exact same pattern. */
28302 /* FALLTHRU */
28306 /* In the 128-bit case, we've full freedom in the placement of
28307 the elements from the source operand. */
28314 }
28316 /* Make sure success has a non-zero value by adding one. */
28318 }
28320 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
28321 the expansion functions to turn the parallel back into a mask.
28322 The return value is 0 for no match and the imm8+1 for a match. */
28324 int
28326 {
28334 /* Validate that all of the elements are constants, and not totally
28335 out of range. Copy the data into an integral array to make the
28336 subsequent checks easier. */
28338 {
28348 }
28350 /* Validate that the halves of the permute are halves. */
28358 /* Reconstruct the mask. */
28360 {
28366 }
28368 /* Make sure success has a non-zero value by adding one. */
28370 }
28371 \f
28373 /* Store OPERAND to the memory after reload is completed. This means
28374 that we can't easily use assign_stack_local. */
28375 rtx
28377 {
28378 rtx result;
28382 {
28385 stack_pointer_rtx,
28388 }
28390 {
28392 {
28396 /* FALLTHRU */
28402 stack_pointer_rtx)),
28403 operand));
28407 }
28409 }
28410 else
28411 {
28413 {
28415 {
28422 stack_pointer_rtx)),
28428 stack_pointer_rtx)),
28430 }
28433 /* Store HImodes as SImodes. */
28435 /* FALLTHRU */
28441 stack_pointer_rtx)),
28442 operand));
28446 }
28448 }
28450 }
28452 /* Free operand from the memory. */
28453 void
28455 {
28457 {
28462 else
28464 /* Use LEA to deallocate stack space. In peephole2 it will be converted
28465 to pop or add instruction if registers are available. */
28469 }
28470 }
28472 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
28474 Put float CONST_DOUBLE in the constant pool instead of fp regs.
28475 QImode must go into class Q_REGS.
28476 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
28477 movdf to do mem-to-mem moves through integer regs. */
28479 static reg_class_t
28481 {
28484 /* We're only allowed to return a subclass of CLASS. Many of the
28485 following checks fail for NO_REGS, so eliminate that early. */
28489 /* All classes can load zeros. */
28493 /* Force constants into memory if we are loading a (nonzero) constant into
28494 an MMX or SSE register. This is because there are no MMX/SSE instructions
28495 to load from a constant. */
28500 /* Prefer SSE regs only, if we can use them for math. */
28504 /* Floating-point constants need more complex checks. */
28506 {
28507 /* General regs can load everything. */
28511 /* Floats can load 0 and 1 plus some others. Note that we eliminated
28512 zero above. We only want to wind up preferring 80387 registers if
28513 we plan on doing computation with them. */
28516 {
28517 /* Limit class to non-sse. */
28526 }
28529 }
28531 /* Generally when we see PLUS here, it's the function invariant
28532 (plus soft-fp const_int). Which can only be computed into general
28533 regs. */
28537 /* QImode constants are easy to load, but non-constant QImode data
28538 must go into Q_REGS. */
28540 {
28546 }
28549 }
28551 /* Discourage putting floating-point values in SSE registers unless
28552 SSE math is being used, and likewise for the 387 registers. */
28553 static reg_class_t
28555 {
28558 /* Restrict the output reload class to the register bank that we are doing
28559 math on. If we would like not to return a subset of CLASS, reject this
28560 alternative: if reload cannot do this, it will still use its choice. */
28566 {
28571 else
28573 }
28576 }
28578 static reg_class_t
28582 {
28583 /* QImode spills from non-QI registers require
28584 intermediate register on 32bit targets. */
28590 {
28595 else
28601 /* Return Q_REGS if the operand is in memory. */
28604 }
28606 /* This condition handles corner case where an expression involving
28607 pointers gets vectorized. We're trying to use the address of a
28608 stack slot as a vector initializer.
28610 (set (reg:V2DI 74 [ vect_cst_.2 ])
28611 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
28613 Eventually frame gets turned into sp+offset like this:
28615 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
28616 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
28617 (const_int 392 [0x188]))))
28619 That later gets turned into:
28621 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
28622 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
28623 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
28625 We'll have the following reload recorded:
28627 Reload 0: reload_in (DI) =
28628 (plus:DI (reg/f:DI 7 sp)
28629 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
28630 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
28631 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
28632 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
28633 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
28634 reload_reg_rtx: (reg:V2DI 22 xmm1)
28636 Which isn't going to work since SSE instructions can't handle scalar
28637 additions. Returning GENERAL_REGS forces the addition into integer
28638 register and reload can handle subsequent reloads without problems. */
28646 }
28648 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
28650 static bool
28652 {
28654 {
28669 }
28672 }
28674 /* If we are copying between general and FP registers, we need a memory
28675 location. The same is true for SSE and MMX registers.
28677 To optimize register_move_cost performance, allow inline variant.
28679 The macro can't work reliably when one of the CLASSES is class containing
28680 registers from multiple units (SSE, MMX, integer). We avoid this by never
28681 combining those units in single alternative in the machine description.
28682 Ensure that this constraint holds to avoid unexpected surprises.
28684 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
28685 enforce these sanity checks. */
28690 {
28697 {
28700 }
28705 /* ??? This is a lie. We do have moves between mmx/general, and for
28706 mmx/sse2. But by saying we need secondary memory we discourage the
28707 register allocator from using the mmx registers unless needed. */
28712 {
28713 /* SSE1 doesn't have any direct moves from other classes. */
28717 /* If the target says that inter-unit moves are more expensive
28718 than moving through memory, then don't generate them. */
28722 /* Between SSE and general, we have moves no larger than word size. */
28725 }
28728 }
28730 bool
28733 {
28735 }
28737 /* Return true if the registers in CLASS cannot represent the change from
28738 modes FROM to TO. */
28740 bool
28743 {
28747 /* x87 registers can't do subreg at all, as all values are reformatted
28748 to extended precision. */
28753 {
28754 /* Vector registers do not support QI or HImode loads. If we don't
28755 disallow a change to these modes, reload will assume it's ok to
28756 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
28757 the vec_dupv4hi pattern. */
28761 /* Vector registers do not support subreg with nonzero offsets, which
28762 are otherwise valid for integer registers. Since we can't see
28763 whether we have a nonzero offset from here, prohibit all
28764 nonparadoxical subregs changing size. */
28767 }
28770 }
28772 /* Return the cost of moving data of mode M between a
28773 register and memory. A value of 2 is the default; this cost is
28774 relative to those in `REGISTER_MOVE_COST'.
28776 This function is used extensively by register_move_cost that is used to
28777 build tables at startup. Make it inline in this case.
28778 When IN is 2, return maximum of in and out move cost.
28780 If moving between registers and memory is more expensive than
28781 between two registers, you should define this macro to express the
28782 relative cost.
28784 Model also increased moving costs of QImode registers in non
28785 Q_REGS classes.
28786 */
28790 {
28793 {
28796 {
28808 }
28812 }
28814 {
28817 {
28829 }
28833 }
28835 {
28838 {
28847 }
28851 }
28853 {
28856 {
28862 else
28867 }
28868 else
28869 {
28874 else
28876 }
28883 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
28890 else
28894 }
28895 }
28897 static int
28900 {
28902 }
28905 /* Return the cost of moving data from a register in class CLASS1 to
28906 one in class CLASS2.
28908 It is not required that the cost always equal 2 when FROM is the same as TO;
28909 on some machines it is expensive to move between registers if they are not
28910 general registers. */
28912 static int
28914 reg_class_t class2_i)
28915 {
28919 /* In case we require secondary memory, compute cost of the store followed
28920 by load. In order to avoid bad register allocation choices, we need
28921 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
28924 {
28930 /* In case of copying from general_purpose_register we may emit multiple
28931 stores followed by single load causing memory size mismatch stall.
28932 Count this as arbitrarily high cost of 20. */
28936 /* In the case of FP/MMX moves, the registers actually overlap, and we
28937 have to switch modes in order to treat them differently. */
28943 }
28945 /* Moves between SSE/MMX and integer unit are expensive. */
28949 /* ??? By keeping returned value relatively high, we limit the number
28950 of moves between integer and MMX/SSE registers for all targets.
28951 Additionally, high value prevents problem with x86_modes_tieable_p(),
28952 where integer modes in MMX/SSE registers are not tieable
28953 because of missing QImode and HImode moves to, from or between
28954 MMX/SSE registers. */
28964 }
28966 /* Return TRUE if hard register REGNO can hold a value of machine-mode
28967 MODE. */
28969 bool
28971 {
28972 /* Flags and only flags can only hold CCmode values. */
28982 {
28983 /* We implement the move patterns for all vector modes into and
28984 out of SSE registers, even when no operation instructions
28985 are available. OImode move is available only when AVX is
28986 enabled. */
28993 }
28995 {
28996 /* We implement the move patterns for 3DNOW modes even in MMX mode,
28997 so if the register is available at all, then we can move data of
28998 the given mode into or out of it. */
29001 }
29004 {
29005 /* Take care for QImode values - they can be in non-QI regs,
29006 but then they do cause partial register stalls. */
29012 }
29013 /* We handle both integer and floats in the general purpose registers. */
29020 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
29021 on to use that value in smaller contexts, this can easily force a
29022 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
29023 supporting DImode, allow it. */
29028 }
29030 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
29031 tieable integer mode. */
29033 static bool
29035 {
29037 {
29050 }
29051 }
29053 /* Return true if MODE1 is accessible in a register that can hold MODE2
29054 without copying. That is, all register classes that can hold MODE2
29055 can also hold MODE1. */
29057 bool
29059 {
29067 /* MODE2 being XFmode implies fp stack or general regs, which means we
29068 can tie any smaller floating point modes to it. Note that we do not
29069 tie this with TFmode. */
29073 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
29074 that we can tie it with SFmode. */
29078 /* If MODE2 is only appropriate for an SSE register, then tie with
29079 any other mode acceptable to SSE registers. */
29085 /* If MODE2 is appropriate for an MMX register, then tie
29086 with any other mode acceptable to MMX registers. */
29093 }
29095 /* Compute a (partial) cost for rtx X. Return true if the complete
29096 cost has been computed, and false if subexpressions should be
29097 scanned. In either case, *TOTAL contains the cost result. */
29099 static bool
29101 {
29107 {
29117 && (!TARGET_64BIT
29122 else
29129 else
29131 {
29140 /* Start with (MEM (SYMBOL_REF)), since that's where
29141 it'll probably end up. Add a penalty for size. */
29146 }
29150 /* The zero extensions is often completely free on x86_64, so make
29151 it as cheap as possible. */
29157 else
29168 {
29171 {
29174 }
29177 {
29180 }
29181 }
29182 /* FALLTHRU */
29189 {
29191 {
29194 else
29196 }
29197 else
29198 {
29201 else
29203 }
29204 }
29205 else
29206 {
29209 else
29211 }
29215 {
29216 rtx sub;
29221 /* ??? SSE scalar/vector cost should be used here. */
29222 /* ??? Bald assumption that fma has the same cost as fmul. */
29226 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
29237 }
29241 {
29242 /* ??? SSE scalar cost should be used here. */
29245 }
29247 {
29250 }
29252 {
29253 /* ??? SSE vector cost should be used here. */
29256 }
29257 else
29258 {
29263 {
29266 nbits++;
29267 }
29268 else
29269 /* This is arbitrary. */
29272 /* Compute costs correctly for widening multiplication. */
29276 {
29283 {
29287 else
29289 }
29293 }
29300 }
29307 /* ??? SSE cost should be used here. */
29312 /* ??? SSE vector cost should be used here. */
29314 else
29321 {
29326 {
29329 {
29336 }
29337 }
29340 {
29343 {
29348 }
29349 }
29351 {
29357 }
29358 }
29359 /* FALLTHRU */
29363 {
29364 /* ??? SSE cost should be used here. */
29367 }
29369 {
29372 }
29374 {
29375 /* ??? SSE vector cost should be used here. */
29378 }
29379 /* FALLTHRU */
29385 {
29392 }
29393 /* FALLTHRU */
29397 {
29398 /* ??? SSE cost should be used here. */
29401 }
29403 {
29406 }
29408 {
29409 /* ??? SSE vector cost should be used here. */
29412 }
29413 /* FALLTHRU */
29418 else
29427 {
29428 /* This kind of construct is implemented using test[bwl].
29429 Treat it as if we had an AND. */
29434 }
29444 /* ??? SSE cost should be used here. */
29449 /* ??? SSE vector cost should be used here. */
29455 /* ??? SSE cost should be used here. */
29460 /* ??? SSE vector cost should be used here. */
29473 /* ??? Assume all of these vector manipulation patterns are
29474 recognizable. In which case they all pretty much have the
29475 same cost. */
29481 }
29482 }
29484 #if TARGET_MACHO
29488 /* Given a symbol name and its associated stub, write out the
29489 definition of the stub. */
29491 void
29493 {
29498 /* For 64-bit we shouldn't get here. */
29501 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
29517 {
29520 else
29522 }
29523 else
29530 {
29532 }
29534 {
29535 /* PIC stub. */
29537 {
29538 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29542 }
29543 else
29544 {
29545 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %eax". */
29548 }
29550 }
29551 else
29554 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
29555 it needs no stub-binding-helper. */
29562 {
29565 }
29566 else
29571 /* N.B. Keep the correspondence of these
29572 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
29573 old-pic/new-pic/non-pic stubs; altering this will break
29574 compatibility with existing dylibs. */
29576 {
29577 /* PIC stubs. */
29579 /* 25-byte PIC stub using "CALL get_pc_thunk". */
29581 else
29582 /* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %ebx". */
29584 }
29585 else
29586 /* 16-byte -mdynamic-no-pic stub. */
29592 }
29595 /* Order the registers for register allocator. */
29597 void
29599 {
29603 /* First allocate the local general purpose registers. */
29608 /* Global general purpose registers. */
29613 /* x87 registers come first in case we are doing FP math
29614 using them. */
29619 /* SSE registers. */
29625 /* x87 registers. */
29633 /* Initialize the rest of array as we do not allocate some registers
29634 at all. */
29637 }
29639 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
29640 in struct attribute_spec handler. */
29641 static tree
29643 tree args,
29646 {
29651 {
29653 name);
29656 }
29658 {
29660 name);
29663 }
29665 {
29666 tree cst;
29670 {
29673 name);
29675 }
29678 {
29681 name);
29683 }
29686 }
29689 }
29691 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
29692 struct attribute_spec.handler. */
29693 static tree
29695 tree args ATTRIBUTE_UNUSED,
29697 {
29702 {
29704 name);
29707 }
29709 {
29711 name);
29714 }
29716 /* Can combine regparm with all attributes but fastcall. */
29718 {
29720 {
29722 }
29725 }
29727 {
29729 {
29731 }
29734 }
29737 }
29739 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29740 struct attribute_spec.handler. */
29741 static tree
29743 tree args ATTRIBUTE_UNUSED,
29745 {
29748 {
29751 }
29752 else
29757 {
29759 name);
29761 }
29767 {
29769 name);
29771 }
29774 }
29776 static tree
29778 tree args ATTRIBUTE_UNUSED,
29780 {
29782 {
29784 name);
29786 }
29788 }
29790 static bool
29792 {
29796 }
29798 /* Returns an expression indicating where the this parameter is
29799 located on entry to the FUNCTION. */
29801 static rtx
29803 {
29809 {
29814 else
29817 }
29822 {
29829 {
29834 }
29835 else
29836 {
29839 {
29844 }
29845 }
29847 }
29850 }
29852 /* Determine whether x86_output_mi_thunk can succeed. */
29854 static bool
29856 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
29858 {
29859 /* 64-bit can handle anything. */
29863 /* For 32-bit, everything's fine if we have one free register. */
29867 /* Need a free register for vcall_offset. */
29871 /* Need a free register for GOT references. */
29875 /* Otherwise ok. */
29877 }
29879 /* Output the assembler code for a thunk function. THUNK_DECL is the
29880 declaration for the thunk function itself, FUNCTION is the decl for
29881 the target function. DELTA is an immediate constant offset to be
29882 added to THIS. If VCALL_OFFSET is nonzero, the word at
29883 *(*this + vcall_offset) should be added to THIS. */
29885 static void
29889 {
29894 /* Make sure unwind info is emitted for the thunk if needed. */
29897 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
29898 pull it in now and let DELTA benefit. */
29902 {
29903 /* Put the this parameter into %eax. */
29907 }
29908 else
29911 /* Adjust the this parameter by a fixed constant. */
29913 {
29917 {
29919 {
29925 }
29928 else
29930 }
29933 else
29935 }
29937 /* Adjust the this parameter by a value stored in the vtable. */
29939 {
29942 else
29943 {
29949 }
29955 /* Adjust the this parameter. */
29958 {
29964 }
29967 }
29969 /* If necessary, drop THIS back to its stack slot. */
29971 {
29975 }
29979 {
29983 /* All thunks should be in the same object as their target,
29984 and thus binds_local_p should be true. */
29987 else
29988 {
29994 }
29995 }
29996 else
29997 {
30000 else
30001 #if TARGET_MACHO
30003 {
30006 sym_ref = (gen_rtx_SYMBOL_REF
30012 }
30013 else
30015 {
30022 }
30023 }
30025 }
30027 static void
30029 {
30031 #if TARGET_MACHO
30033 #endif
30040 }
30042 int
30044 {
30056 }
30058 /* Output assembler code to FILE to increment profiler label # LABELNO
30059 for profiling a function entry. */
30060 void
30062 {
30067 {
30068 #ifndef NO_PROFILE_COUNTERS
30070 #endif
30074 else
30076 }
30078 {
30079 #ifndef NO_PROFILE_COUNTERS
30082 #endif
30084 }
30085 else
30086 {
30087 #ifndef NO_PROFILE_COUNTERS
30090 #endif
30092 }
30093 }
30095 /* We don't have exact information about the insn sizes, but we may assume
30096 quite safely that we are informed about all 1 byte insns and memory
30097 address sizes. This is enough to eliminate unnecessary padding in
30098 99% of cases. */
30100 static int
30102 {
30108 /* Discard alignments we've emit and jump instructions. */
30115 /* Important case - calls are always 5 bytes.
30116 It is common to have many calls in the row. */
30125 /* For normal instructions we rely on get_attr_length being exact,
30126 with a few exceptions. */
30128 {
30132 {
30142 /* Otherwise trust get_attr_length. */
30144 }
30149 }
30152 else
30154 }
30156 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
30158 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
30159 window. */
30161 static void
30163 {
30168 /* Look for all minimal intervals of instructions containing 4 jumps.
30169 The intervals are bounded by START and INSN. NBYTES is the total
30170 size of instructions in the interval including INSN and not including
30171 START. When the NBYTES is smaller than 16 bytes, it is possible
30172 that the end of START and INSN ends up in the same 16byte page.
30174 The smallest offset in the page INSN can start is the case where START
30175 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
30176 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
30177 */
30179 {
30183 {
30189 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
30190 already in the current 16 byte page, because otherwise
30191 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
30192 bytes to reach 16 byte boundary. */
30200 {
30202 {
30209 else
30212 }
30213 }
30215 }
30226 njumps++;
30227 else
30231 {
30238 else
30241 }
30248 {
30255 }
30256 }
30257 }
30258 #endif
30260 /* AMD Athlon works faster
30261 when RET is not destination of conditional jump or directly preceded
30262 by other jump instruction. We avoid the penalty by inserting NOP just
30263 before the RET instructions in such cases. */
30264 static void
30266 {
30267 edge e;
30268 edge_iterator ei;
30271 {
30274 rtx prev;
30284 {
30285 edge e;
30286 edge_iterator ei;
30292 }
30294 {
30300 /* Empty functions get branch mispredict even when
30301 the jump destination is not visible to us. */
30304 }
30306 {
30309 }
30310 }
30311 }
30313 /* Count the minimum number of instructions in BB. Return 4 if the
30314 number of instructions >= 4. */
30316 static int
30318 {
30319 rtx insn;
30322 /* Count number of instructions in this block. Return 4 if the number
30323 of instructions >= 4. */
30325 {
30326 /* Only happen in exit blocks. */
30334 {
30335 insn_count++;
30338 }
30339 }
30342 }
30345 /* Count the minimum number of instructions in code path in BB.
30346 Return 4 if the number of instructions >= 4. */
30348 static int
30350 {
30351 edge e;
30352 edge_iterator ei;
30355 /* Only bother counting instructions along paths with no
30356 more than 2 basic blocks between entry and exit. Given
30357 that BB has an edge to exit, determine if a predecessor
30358 of BB has an edge from entry. If so, compute the number
30359 of instructions in the predecessor block. If there
30360 happen to be multiple such blocks, compute the minimum. */
30363 {
30364 edge prev_e;
30365 edge_iterator prev_ei;
30368 {
30371 }
30373 {
30375 {
30380 }
30381 }
30382 }
30388 }
30390 /* Pad short funtion to 4 instructions. */
30392 static void
30394 {
30395 edge e;
30396 edge_iterator ei;
30399 {
30402 {
30405 /* Pad short function. */
30407 {
30410 /* Find epilogue. */
30419 /* Two NOPs count as one instruction. */
30422 }
30423 }
30424 }
30425 }
30427 /* Implement machine specific optimizations. We implement padding of returns
30428 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
30429 static void
30431 {
30432 /* We are freeing block_for_insn in the toplev to keep compatibility
30433 with old MDEP_REORGS that are not CFG based. Recompute it now. */
30436 /* Run the vzeroupper optimization if needed. */
30441 {
30446 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
30449 #endif
30450 }
30451 }
30453 /* Return nonzero when QImode register that must be represented via REX prefix
30454 is used. */
30455 bool
30457 {
30465 }
30467 /* Return nonzero when P points to register encoded via REX prefix.
30468 Called via for_each_rtx. */
30469 static int
30471 {
30477 }
30479 /* Return true when INSN mentions register that must be encoded using REX
30480 prefix. */
30481 bool
30483 {
30486 }
30488 /* If profitable, negate (without causing overflow) integer constant
30489 of mode MODE at location LOC. Return true in this case. */
30490 bool
30492 {
30493 HOST_WIDE_INT val;
30499 {
30501 /* DImode x86_64 constants must fit in 32 bits. */
30514 }
30516 /* Avoid overflows. */
30522 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
30523 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
30526 {
30529 }
30532 }
30534 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
30535 optabs would emit if we didn't have TFmode patterns. */
30537 void
30539 {
30573 }
30574 \f
30575 /* AVX does not support 32-byte integer vector operations,
30576 thus the longest vector we are faced with is V16QImode. */
30577 #define MAX_VECT_LEN 16
30579 struct expand_vec_perm_d
30580 {
30586 };
30591 /* Get a vector mode of the same size as the original but with elements
30592 twice as wide. This is only guaranteed to apply to integral vectors. */
30596 {
30597 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
30602 }
30604 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30605 with all elements equal to VAR. Return true if successful. */
30607 static bool
30610 {
30614 {
30619 /* FALLTHRU */
30629 {
30632 /* First attempt to recognize VAL as-is. */
30636 {
30637 rtx seq;
30638 /* If that fails, force VAL into a register. */
30649 }
30650 }
30657 {
30658 rtx x;
30665 }
30675 {
30679 permute:
30686 /* Extend to SImode using a paradoxical SUBREG. */
30690 /* Insert the SImode value as low element of a V4SImode vector. */
30698 }
30706 widen:
30707 /* Replicate the value once into the next wider mode and recurse. */
30708 {
30710 rtx x;
30726 }
30730 {
30739 }
30744 }
30745 }
30747 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30748 whose ONE_VAR element is VAR, and other elements are zero. Return true
30749 if successful. */
30751 static bool
30754 {
30756 rtx new_target;
30761 {
30763 /* For SSE4.1, we normally use vector set. But if the second
30764 element is zero and inter-unit moves are OK, we use movq
30765 instead. */
30766 use_vector_set = (TARGET_64BIT
30767 && TARGET_SSE4_1
30768 && !(TARGET_INTER_UNIT_MOVES
30790 /* Use ix86_expand_vector_set in 64bit mode only. */
30795 }
30798 {
30803 }
30806 {
30811 /* FALLTHRU */
30826 else
30833 {
30834 /* We need to shuffle the value to the correct position, so
30835 create a new pseudo to store the intermediate result. */
30837 /* With SSE2, we can use the integer shuffle insns. */
30839 {
30841 const1_rtx,
30848 }
30850 /* Otherwise convert the intermediate result to V4SFmode and
30851 use the SSE1 shuffle instructions. */
30853 {
30856 }
30857 else
30861 const1_rtx,
30870 }
30885 widen:
30889 /* Zero extend the variable element to SImode and recurse. */
30902 }
30903 }
30905 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
30906 consisting of the values in VALS. It is known that all elements
30907 except ONE_VAR are constants. Return true if successful. */
30909 static bool
30912 {
30922 {
30927 /* For the two element vectors, it's just as easy to use
30928 the general case. */
30932 /* Use ix86_expand_vector_set in 64bit mode only. */
30954 widen:
30955 /* There's no way to set one QImode entry easily. Combine
30956 the variable value with its adjacent constant value, and
30957 promote to an HImode set. */
30960 {
30965 }
30966 else
30967 {
30970 }
30984 }
30989 }
30991 /* A subroutine of ix86_expand_vector_init_general. Use vector
30992 concatenate to handle the most general case: all values variable,
30993 and none identical. */
30995 static void
30998 {
31001 rtvec v;
31005 {
31008 {
31041 }
31054 {
31069 }
31074 {
31085 }
31088 half:
31089 /* FIXME: We process inputs backward to help RA. PR 36222. */
31093 {
31098 }
31102 {
31105 {
31109 }
31112 }
31113 else
31119 }
31120 }
31122 /* A subroutine of ix86_expand_vector_init_general. Use vector
31123 interleave to handle the most general case: all values variable,
31124 and none identical. */
31126 static void
31129 {
31138 {
31159 }
31162 {
31163 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
31167 /* Insert the SImode value as low element of V4SImode vector. */
31171 op0),
31173 const1_rtx);
31176 /* Cast the V4SImode vector back to a vector in orignal mode. */
31180 /* Load even elements into the second positon. */
31184 const1_rtx));
31186 /* Cast vector to FIRST_IMODE vector. */
31189 }
31191 /* Interleave low FIRST_IMODE vectors. */
31193 {
31197 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
31200 }
31202 /* Interleave low SECOND_IMODE vectors. */
31204 {
31207 {
31212 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
31213 vector. */
31216 }
31219 /* FALLTHRU */
31226 /* Cast the SECOND_IMODE vector back to a vector on original
31227 mode. */
31234 }
31235 }
31237 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
31238 all values variable, and none identical. */
31240 static void
31243 {
31249 {
31254 /* FALLTHRU */
31278 half:
31295 /* FALLTHRU */
31301 /* Don't use ix86_expand_vector_init_interleave if we can't
31302 move from GPR to SSE register directly. */
31318 }
31320 {
31332 {
31336 {
31342 else
31343 {
31348 }
31349 }
31352 }
31357 {
31363 }
31365 {
31371 }
31372 else
31374 }
31375 }
31377 /* Initialize vector TARGET via VALS. Suppress the use of MMX
31378 instructions unless MMX_OK is true. */
31380 void
31382 {
31389 rtx x;
31392 {
31402 }
31404 /* Constants are best loaded from the constant pool. */
31406 {
31409 }
31411 /* If all values are identical, broadcast the value. */
31417 /* Values where only one field is non-constant are best loaded from
31418 the pool and overwritten via move later. */
31420 {
31424 one_var))
31429 }
31432 }
31434 void
31436 {
31441 rtx tmp;
31443 = {
31450 };
31452 = {
31459 };
31463 {
31467 {
31472 else
31476 }
31488 else
31494 {
31497 /* For the two element vectors, we implement a VEC_CONCAT with
31498 the extraction of the other element. */
31505 else
31510 }
31519 {
31525 /* tmp = target = A B C D */
31527 /* target = A A B B */
31529 /* target = X A B B */
31531 /* target = A X C D */
31538 /* tmp = target = A B C D */
31540 /* tmp = X B C D */
31542 /* target = A B X D */
31549 /* tmp = target = A B C D */
31551 /* tmp = X B C D */
31553 /* target = A B X D */
31561 }
31569 /* Element 0 handled by vec_merge below. */
31571 {
31574 }
31577 {
31578 /* With SSE2, use integer shuffles to swap element 0 and ELT,
31579 store into element 0, then shuffle them back. */
31596 }
31597 else
31598 {
31599 /* For SSE1, we have to reuse the V4SF code. */
31602 }
31655 half:
31656 /* Compute offset. */
31662 /* Extract the half. */
31666 /* Put val in tmp at elt. */
31669 /* Put it back. */
31675 }
31678 {
31682 }
31683 else
31684 {
31693 }
31694 }
31696 void
31698 {
31702 rtx tmp;
31705 {
31710 /* FALLTHRU */
31723 {
31743 }
31755 {
31757 {
31777 }
31781 }
31782 else
31783 {
31784 /* For SSE1, we have to reuse the V4SF code. */
31788 }
31803 /* ??? Could extract the appropriate HImode element and shift. */
31806 }
31809 {
31813 /* Let the rtl optimizers know about the zero extension performed. */
31815 {
31818 }
31821 }
31822 else
31823 {
31830 }
31831 }
31833 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
31834 pattern to reduce; DEST is the destination; IN is the input vector. */
31836 void
31838 {
31852 }
31853 \f
31854 /* Target hook for scalar_mode_supported_p. */
31855 static bool
31857 {
31862 else
31864 }
31866 /* Implements target hook vector_mode_supported_p. */
31867 static bool
31869 {
31881 }
31883 /* Target hook for c_mode_for_suffix. */
31884 static enum machine_mode
31886 {
31893 }
31895 /* Worker function for TARGET_MD_ASM_CLOBBERS.
31897 We do this in the new i386 backend to maintain source compatibility
31898 with the old cc0-based compiler. */
31900 static tree
31902 tree inputs ATTRIBUTE_UNUSED,
31903 tree clobbers)
31904 {
31906 clobbers);
31908 clobbers);
31910 }
31912 /* Implements target vector targetm.asm.encode_section_info. This
31913 is not used by netware. */
31915 static void ATTRIBUTE_UNUSED
31917 {
31924 }
31926 /* Worker function for REVERSE_CONDITION. */
31928 enum rtx_code
31930 {
31934 }
31936 /* Output code to perform an x87 FP register move, from OPERANDS[1]
31937 to OPERANDS[0]. */
31941 {
31943 {
31946 {
31950 }
31954 }
31956 {
31960 else
31961 {
31962 /* There is no non-popping store to memory for XFmode.
31963 So if we need one, follow the store with a load. */
31966 else
31968 }
31969 }
31970 else
31972 }
31974 /* Output code to perform a conditional jump to LABEL, if C2 flag in
31975 FP status register is set. */
31977 void
31979 {
31981 rtx temp;
31986 {
31991 }
31992 else
31993 {
31998 }
32002 pc_rtx);
32007 }
32009 /* Output code to perform a log1p XFmode calculation. */
32012 {
32018 rtx test;
32024 XFmode));
32038 }
32040 /* Output code to perform a Newton-Rhapson approximation of a single precision
32041 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
32044 {
32052 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
32054 /* x0 = rcp(b) estimate */
32057 UNSPEC_RCP)));
32058 /* e0 = x0 * b */
32062 /* e0 = x0 * e0 */
32066 /* e1 = x0 + x0 */
32070 /* x1 = e1 - e0 */
32074 /* res = a * x1 */
32077 }
32079 /* Output code to perform a Newton-Rhapson approximation of a
32080 single precision floating point [reciprocal] square root. */
32084 {
32086 REAL_VALUE_TYPE r;
32101 {
32104 }
32106 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
32107 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
32109 /* x0 = rsqrt(a) estimate */
32112 UNSPEC_RSQRT)));
32114 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
32116 {
32128 }
32130 /* e0 = x0 * a */
32133 /* e1 = e0 * x0 */
32137 /* e2 = e1 - 3. */
32144 /* e3 = -.5 * x0 */
32147 else
32148 /* e3 = -.5 * e0 */
32151 /* ret = e2 * e3 */
32154 }
32156 #ifdef TARGET_SOLARIS
32157 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
32159 static void
32161 tree decl)
32162 {
32163 /* With Binutils 2.15, the "@unwind" marker must be specified on
32164 every occurrence of the ".eh_frame" section, not just the first
32165 one. */
32168 {
32172 }
32174 #ifndef USE_GAS
32176 {
32179 }
32180 #endif
32183 }
32186 /* Return the mangling of TYPE if it is an extended fundamental type. */
32190 {
32198 {
32200 /* __float128 is "g". */
32203 /* "long double" or __float80 is "e". */
32207 }
32208 }
32210 /* For 32-bit code we can save PIC register setup by using
32211 __stack_chk_fail_local hidden function instead of calling
32212 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
32213 register, so it is better to call __stack_chk_fail directly. */
32215 static tree
32217 {
32218 return TARGET_64BIT
32221 }
32223 /* Select a format to encode pointers in exception handling data. CODE
32224 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
32225 true if the symbol may be affected by dynamic relocations.
32227 ??? All x86 object file formats are capable of representing this.
32228 After all, the relocation needed is the same as for the call insn.
32229 Whether or not a particular assembler allows us to enter such, I
32230 guess we'll have to see. */
32231 int
32233 {
32235 {
32242 }
32247 }
32248 \f
32249 /* Expand copysign from SIGN to the positive value ABS_VALUE
32250 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
32251 the sign-bit. */
32252 static void
32254 {
32258 {
32265 else
32270 {
32271 /* We need to generate a scalar mode mask in this case. */
32276 }
32277 }
32278 else
32284 }
32286 /* Expand fabs (OP0) and return a new rtx that holds the result. The
32287 mask for masking out the sign-bit is stored in *SMASK, if that is
32288 non-null. */
32289 static rtx
32291 {
32300 else
32304 {
32305 /* We need to generate a scalar mode mask in this case. */
32310 }
32318 }
32320 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
32321 swapping the operands if SWAP_OPERANDS is true. The expanded
32322 code is a forward jump to a newly created label in case the
32323 comparison is true. The generated label rtx is returned. */
32324 static rtx
32327 {
32331 {
32335 }
32348 }
32350 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
32351 using comparison code CODE. Operands are swapped for the comparison if
32352 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
32353 static rtx
32356 {
32362 {
32366 }
32373 }
32375 /* Generate and return a rtx of mode MODE for 2**n where n is the number
32376 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
32377 static rtx
32379 {
32380 REAL_VALUE_TYPE TWO52r;
32381 rtx TWO52;
32388 }
32390 /* Expand SSE sequence for computing lround from OP1 storing
32391 into OP0. */
32392 void
32394 {
32395 /* C code for the stuff we're doing below:
32396 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
32397 return (long)tmp;
32398 */
32402 rtx adj;
32404 /* load nextafter (0.5, 0.0) */
32409 /* adj = copysign (0.5, op1) */
32413 /* adj = op1 + adj */
32416 /* op0 = (imode)adj */
32418 }
32420 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
32421 into OPERAND0. */
32422 void
32424 {
32425 /* C code for the stuff we're doing below (for do_floor):
32426 xi = (long)op1;
32427 xi -= (double)xi > op1 ? 1 : 0;
32428 return xi;
32429 */
32434 /* reg = (long)op1 */
32438 /* freg = (double)reg */
32442 /* ireg = (freg > op1) ? ireg - 1 : ireg */
32453 }
32455 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
32456 result in OPERAND0. */
32457 void
32459 {
32460 /* C code for the stuff we're doing below:
32461 xa = fabs (operand1);
32462 if (!isless (xa, 2**52))
32463 return operand1;
32464 xa = xa + 2**52 - 2**52;
32465 return copysign (xa, operand1);
32466 */
32473 /* xa = abs (operand1) */
32476 /* if (!isless (xa, TWO52)) goto label; */
32489 }
32491 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
32492 into OPERAND0. */
32493 void
32495 {
32496 /* C code for the stuff we expand below.
32497 double xa = fabs (x), x2;
32498 if (!isless (xa, TWO52))
32499 return x;
32500 xa = xa + TWO52 - TWO52;
32501 x2 = copysign (xa, x);
32502 Compensate. Floor:
32503 if (x2 > x)
32504 x2 -= 1;
32505 Compensate. Ceil:
32506 if (x2 < x)
32507 x2 -= -1;
32508 return x2;
32509 */
32515 /* Temporary for holding the result, initialized to the input
32516 operand to ease control flow. */
32520 /* xa = abs (operand1) */
32523 /* if (!isless (xa, TWO52)) goto label; */
32526 /* xa = xa + TWO52 - TWO52; */
32530 /* xa = copysign (xa, operand1) */
32533 /* generate 1.0 or -1.0 */
32538 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32542 /* We always need to subtract here to preserve signed zero. */
32551 }
32553 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
32554 into OPERAND0. */
32555 void
32557 {
32558 /* C code for the stuff we expand below.
32559 double xa = fabs (x), x2;
32560 if (!isless (xa, TWO52))
32561 return x;
32562 x2 = (double)(long)x;
32563 Compensate. Floor:
32564 if (x2 > x)
32565 x2 -= 1;
32566 Compensate. Ceil:
32567 if (x2 < x)
32568 x2 += 1;
32569 if (HONOR_SIGNED_ZEROS (mode))
32570 return copysign (x2, x);
32571 return x2;
32572 */
32578 /* Temporary for holding the result, initialized to the input
32579 operand to ease control flow. */
32583 /* xa = abs (operand1) */
32586 /* if (!isless (xa, TWO52)) goto label; */
32589 /* xa = (double)(long)x */
32594 /* generate 1.0 */
32597 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
32612 }
32614 /* Expand SSE sequence for computing round from OPERAND1 storing
32615 into OPERAND0. Sequence that works without relying on DImode truncation
32616 via cvttsd2siq that is only available on 64bit targets. */
32617 void
32619 {
32620 /* C code for the stuff we expand below.
32621 double xa = fabs (x), xa2, x2;
32622 if (!isless (xa, TWO52))
32623 return x;
32624 Using the absolute value and copying back sign makes
32625 -0.0 -> -0.0 correct.
32626 xa2 = xa + TWO52 - TWO52;
32627 Compensate.
32628 dxa = xa2 - xa;
32629 if (dxa <= -0.5)
32630 xa2 += 1;
32631 else if (dxa > 0.5)
32632 xa2 -= 1;
32633 x2 = copysign (xa2, x);
32634 return x2;
32635 */
32641 /* Temporary for holding the result, initialized to the input
32642 operand to ease control flow. */
32646 /* xa = abs (operand1) */
32649 /* if (!isless (xa, TWO52)) goto label; */
32652 /* xa2 = xa + TWO52 - TWO52; */
32656 /* dxa = xa2 - xa; */
32659 /* generate 0.5, 1.0 and -0.5 */
32665 /* Compensate. */
32667 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
32672 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
32678 /* res = copysign (xa2, operand1) */
32685 }
32687 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32688 into OPERAND0. */
32689 void
32691 {
32692 /* C code for SSE variant we expand below.
32693 double xa = fabs (x), x2;
32694 if (!isless (xa, TWO52))
32695 return x;
32696 x2 = (double)(long)x;
32697 if (HONOR_SIGNED_ZEROS (mode))
32698 return copysign (x2, x);
32699 return x2;
32700 */
32706 /* Temporary for holding the result, initialized to the input
32707 operand to ease control flow. */
32711 /* xa = abs (operand1) */
32714 /* if (!isless (xa, TWO52)) goto label; */
32717 /* x = (double)(long)x */
32729 }
32731 /* Expand SSE sequence for computing trunc from OPERAND1 storing
32732 into OPERAND0. */
32733 void
32735 {
32739 /* C code for SSE variant we expand below.
32740 double xa = fabs (x), x2;
32741 if (!isless (xa, TWO52))
32742 return x;
32743 xa2 = xa + TWO52 - TWO52;
32744 Compensate:
32745 if (xa2 > xa)
32746 xa2 -= 1.0;
32747 x2 = copysign (xa2, x);
32748 return x2;
32749 */
32753 /* Temporary for holding the result, initialized to the input
32754 operand to ease control flow. */
32758 /* xa = abs (operand1) */
32761 /* if (!isless (xa, TWO52)) goto label; */
32764 /* res = xa + TWO52 - TWO52; */
32769 /* generate 1.0 */
32772 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
32780 /* res = copysign (res, operand1) */
32787 }
32789 /* Expand SSE sequence for computing round from OPERAND1 storing
32790 into OPERAND0. */
32791 void
32793 {
32794 /* C code for the stuff we're doing below:
32795 double xa = fabs (x);
32796 if (!isless (xa, TWO52))
32797 return x;
32798 xa = (double)(long)(xa + nextafter (0.5, 0.0));
32799 return copysign (xa, x);
32800 */
32806 /* Temporary for holding the result, initialized to the input
32807 operand to ease control flow. */
32815 /* load nextafter (0.5, 0.0) */
32820 /* xa = xa + 0.5 */
32824 /* xa = (double)(int64_t)xa */
32829 /* res = copysign (xa, operand1) */
32836 }
32837 \f
32839 /* Table of valid machine attributes. */
32841 {
32842 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
32843 affects_type_identity } */
32844 /* Stdcall attribute says callee is responsible for popping arguments
32845 if they are not variable. */
32848 /* Fastcall attribute says callee is responsible for popping arguments
32849 if they are not variable. */
32852 /* Thiscall attribute says callee is responsible for popping arguments
32853 if they are not variable. */
32856 /* Cdecl attribute says the callee is a normal C declaration */
32859 /* Regparm attribute specifies how many integer arguments are to be
32860 passed in registers. */
32863 /* Sseregparm attribute says we are using x86_64 calling conventions
32864 for FP arguments. */
32867 /* force_align_arg_pointer says this function realigns the stack at entry. */
32870 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
32875 #endif
32880 #ifdef SUBTARGET_ATTRIBUTE_TABLE
32881 SUBTARGET_ATTRIBUTE_TABLE,
32882 #endif
32883 /* ms_abi and sysv_abi calling convention function attributes. */
32890 /* End element. */
32892 };
32894 /* Implement targetm.vectorize.builtin_vectorization_cost. */
32895 static int
32897 tree vectype ATTRIBUTE_UNUSED,
32899 {
32901 {
32941 }
32942 }
32945 /* Implement targetm.vectorize.builtin_vec_perm. */
32947 static tree
32949 {
32957 {
32964 get_di:
32975 get_si:
32994 }
33001 }
33003 /* Return a vector mode with twice as many elements as VMODE. */
33004 /* ??? Consider moving this to a table generated by genmodes.c. */
33006 static enum machine_mode
33008 {
33010 {
33033 }
33034 }
33036 /* Construct (set target (vec_select op0 (parallel perm))) and
33037 return true if that's a valid instruction in the active ISA. */
33039 static bool
33041 {
33054 {
33057 }
33059 }
33061 /* Similar, but generate a vec_concat from op0 and op1 as well. */
33063 static bool
33066 {
33068 rtx x;
33073 }
33075 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
33076 in terms of blendp[sd] / pblendw / pblendvb. */
33078 static bool
33080 {
33090 /* This is a blend, not a permute. Elements must stay in their
33091 respective lanes. */
33093 {
33097 }
33102 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
33103 decision should be extracted elsewhere, so that we only try that
33104 sequence once all budget==3 options have been tried. */
33106 /* For bytes, see if bytes move in pairs so we can use pblendw with
33107 an immediate argument, rather than pblendvb with a vector argument. */
33109 {
33115 {
33126 }
33127 }
33135 {
33159 do_subreg:
33168 }
33170 /* This matches five different patterns with the different modes. */
33176 }
33178 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
33179 in terms of the variable form of vpermilps.
33181 Note that we will have already failed the immediate input vpermilps,
33182 which requires that the high and low part shuffle be identical; the
33183 variable form doesn't require that. */
33185 static bool
33187 {
33194 /* We can only permute within the 128-bit lane. */
33196 {
33200 }
33206 {
33209 /* Within each 128-bit lane, the elements of op0 are numbered
33210 from 0 and the elements of op1 are numbered from 4. */
33217 }
33224 }
33226 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
33227 in terms of pshufb or vpperm. */
33229 static bool
33231 {
33247 {
33251 }
33260 else
33261 {
33264 }
33267 }
33269 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
33270 in a single instruction. */
33272 static bool
33274 {
33278 /* Check plain VEC_SELECT first, because AVX has instructions that could
33279 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
33280 input where SEL+CONCAT may not. */
33282 {
33291 /* There are plenty of patterns in sse.md that are written for
33292 SEL+CONCAT and are not replicated for a single op. Perhaps
33293 that should be changed, to avoid the nastiness here. */
33295 /* Recognize interleave style patterns, which means incrementing
33296 every other permutation operand. */
33298 {
33301 }
33305 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
33307 {
33309 {
33314 }
33318 }
33319 }
33321 /* Finally, try the fully general two operand permute. */
33325 /* Recognize interleave style patterns with reversed operands. */
33327 {
33329 {
33333 else
33336 }
33340 }
33342 /* Try the SSE4.1 blend variable merge instructions. */
33346 /* Try one of the AVX vpermil variable permutations. */
33350 /* Try the SSSE3 pshufb or XOP vpperm variable permutation. */
33355 }
33357 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
33358 in terms of a pair of pshuflw + pshufhw instructions. */
33360 static bool
33362 {
33370 /* The two permutations only operate in 64-bit lanes. */
33381 /* Emit the pshuflw. */
33388 /* Emit the pshufhw. */
33396 }
33398 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
33399 the permutation using the SSSE3 palignr instruction. This succeeds
33400 when all of the elements in PERM fit within one vector and we merely
33401 need to shift them down so that a single vector permutation has a
33402 chance to succeed. */
33404 static bool
33406 {
33410 rtx shift;
33412 /* Even with AVX, palignr only operates on 128-bit vectors. */
33418 {
33424 }
33428 /* Given that we have SSSE3, we know we'll be able to implement the
33429 single operand permutation after the palignr with pshufb. */
33442 {
33447 }
33449 /* Test for the degenerate case where the alignment by itself
33450 produces the desired permutation. */
33458 }
33460 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
33461 a two vector permutation into a single vector permutation by using
33462 an interleave operation to merge the vectors. */
33464 static bool
33466 {
33471 rtx seq;
33477 /* The 256-bit unpck[lh]p[sd] instructions only operate within the 128-bit
33478 lanes. We can use similar techniques with the vperm2f128 instruction,
33479 but it requires slightly different logic. */
33483 /* Examine from whence the elements come. */
33488 /* Split the two input vectors into 4 halves. */
33497 /* If the elements from the low halves use interleave low, and similarly
33498 for interleave high. If the elements are from mis-matched halves, we
33499 can use shufps for V4SF/V4SI or do a DImode shuffle. */
33501 {
33503 {
33508 }
33509 }
33511 {
33513 {
33518 }
33519 }
33521 {
33523 {
33528 }
33530 {
33535 }
33536 }
33538 {
33540 {
33545 }
33547 {
33552 }
33553 }
33554 else
33557 /* Use the remapping array set up above to move the elements from their
33558 swizzled locations into their final destinations. */
33561 {
33565 }
33570 /* Test if the final remap can be done with a single insn. For V4SFmode or
33571 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
33581 {
33585 }
33592 }
33594 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
33595 permutation with two pshufb insns and an ior. We should have already
33596 failed all two instruction sequences. */
33598 static bool
33600 {
33611 /* Generate two permutation masks. If the required element is within
33612 the given vector it is shuffled into the proper lane. If the required
33613 element is in the other vector, force a zero into the lane by setting
33614 bit 7 in the permutation mask. */
33617 {
33624 {
33627 }
33628 }
33648 }
33650 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
33651 and extract-odd permutations. */
33653 static bool
33655 {
33659 {
33664 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
33668 /* Now an unpck[lh]pd will produce the result required. */
33671 else
33677 {
33684 /* Shuffle within the 128-bit lanes to produce:
33685 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
33689 /* Shuffle the lanes around to produce:
33690 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
33694 /* Shuffle within the 128-bit lanes to produce:
33695 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
33698 /* Shuffle within the 128-bit lanes to produce:
33699 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
33702 /* Shuffle the lanes around to produce:
33703 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
33706 }
33713 /* These are always directly implementable by expand_vec_perm_1. */
33719 else
33720 {
33721 /* We need 2*log2(N)-1 operations to achieve odd/even
33722 with interleave. */
33731 else
33734 }
33740 else
33741 {
33753 else
33756 }
33761 }
33764 }
33766 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33767 extract-even and extract-odd permutations. */
33769 static bool
33771 {
33783 }
33785 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
33786 permutations. We assume that expand_vec_perm_1 has already failed. */
33788 static bool
33790 {
33798 {
33801 /* These are special-cased in sse.md so that we can optionally
33802 use the vbroadcast instruction. They expand to two insns
33803 if the input happens to be in a register. */
33810 /* These are always implementable using standard shuffle patterns. */
33815 /* These can be implemented via interleave. We save one insn by
33816 stopping once we have promoted to V4SImode and then use pshufd. */
33817 do
33818 {
33822 {
33825 }
33831 }
33841 }
33842 }
33844 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
33845 broadcast permutations. */
33847 static bool
33849 {
33861 }
33863 /* The guts of ix86_expand_vec_perm_builtin, also used by the ok hook.
33864 With all of the interface bits taken care of, perform the expansion
33865 in D and return true on success. */
33867 static bool
33869 {
33870 /* Try a single instruction expansion. */
33874 /* Try sequences of two instructions. */
33888 /* Try sequences of three instructions. */
33893 /* ??? Look for narrow permutations whose element orderings would
33894 allow the promotion to a wider mode. */
33896 /* ??? Look for sequences of interleave or a wider permute that place
33897 the data into the correct lanes for a half-vector shuffle like
33898 pshuf[lh]w or vpermilps. */
33900 /* ??? Look for sequences of interleave that produce the desired results.
33901 The combinatorics of punpck[lh] get pretty ugly... */
33907 }
33909 /* Extract the values from the vector CST into the permutation array in D.
33910 Return 0 on error, 1 if all values from the permutation come from the
33911 first vector, 2 if all values from the second vector, and 3 otherwise. */
33913 static int
33915 {
33921 {
33932 }
33935 /* For all elements from second vector, fold the elements to first. */
33941 }
33943 static rtx
33945 {
33959 {
33963 }
33966 {
33976 {
33982 }
33984 /* The elements of PERM do not suggest that only the first operand
33985 is used, but both operands are identical. Allow easier matching
33986 of the permutation by folding the permutation into the single
33987 input vector. */
33988 {
33993 }
33994 /* FALLTHRU */
34007 }
34013 /* For compiler generated permutations, we should never got here, because
34014 the compiler should also be checking the ok hook. But since this is a
34015 builtin the user has access too, so don't abort. */
34017 {
34040 }
34041 exit_error:
34043 }
34045 /* Implement targetm.vectorize.builtin_vec_perm_ok. */
34047 static bool
34049 {
34058 /* Given sufficient ISA support we can just return true here
34059 for selected vector modes. */
34061 {
34062 /* All implementable with a single vpperm insn. */
34065 /* All implementable with 2 pshufb + 1 ior. */
34068 /* All implementable with shufpd or unpck[lh]pd. */
34071 }
34075 /* This hook is cannot be called in response to something that the
34076 user does (unlike the builtin expander) so we shouldn't ever see
34077 an error generated from the extract. */
34081 /* Implementable with shufps or pshufd. */
34085 /* Otherwise we have to go through the motions and see if we can
34086 figure out how to generate the requested permutation. */
34097 }
34099 void
34101 {
34115 /* We'll either be able to implement the permutation directly... */
34119 /* ... or we use the special-case patterns. */
34121 }
34123 /* Expand an insert into a vector register through pinsr insn.
34124 Return true if successful. */
34126 bool
34128 {
34136 {
34139 }
34145 {
34150 {
34157 {
34189 }
34198 }
34202 }
34203 }
34204 \f
34205 /* This function returns the calling abi specific va_list type node.
34206 It returns the FNDECL specific va_list type. */
34208 static tree
34210 {
34217 else
34219 }
34221 /* Returns the canonical va_list type specified by TYPE. If there
34222 is no valid TYPE provided, it return NULL_TREE. */
34224 static tree
34226 {
34229 /* Resolve references and pointers to va_list type. */
34238 {
34243 {
34244 /* If va_list is an array type, the argument may have decayed
34245 to a pointer type, e.g. by being passed to another function.
34246 In that case, unwrap both types so that we can compare the
34247 underlying records. */
34250 {
34253 }
34254 }
34261 {
34262 /* If va_list is an array type, the argument may have decayed
34263 to a pointer type, e.g. by being passed to another function.
34264 In that case, unwrap both types so that we can compare the
34265 underlying records. */
34268 {
34271 }
34272 }
34279 {
34280 /* If va_list is an array type, the argument may have decayed
34281 to a pointer type, e.g. by being passed to another function.
34282 In that case, unwrap both types so that we can compare the
34283 underlying records. */
34286 {
34289 }
34290 }
34294 }
34296 }
34298 /* Iterate through the target-specific builtin types for va_list.
34299 IDX denotes the iterator, *PTREE is set to the result type of
34300 the va_list builtin, and *PNAME to its internal type.
34301 Returns zero if there is no element for this index, otherwise
34302 IDX should be increased upon the next call.
34303 Note, do not iterate a base builtin's name like __builtin_va_list.
34304 Used from c_common_nodes_and_builtins. */
34306 static int
34308 {
34310 {
34312 {
34325 }
34326 }
34329 }
34331 #undef TARGET_SCHED_DISPATCH
34332 #define TARGET_SCHED_DISPATCH has_dispatch
34333 #undef TARGET_SCHED_DISPATCH_DO
34334 #define TARGET_SCHED_DISPATCH_DO do_dispatch
34336 /* The size of the dispatch window is the total number of bytes of
34337 object code allowed in a window. */
34338 #define DISPATCH_WINDOW_SIZE 16
34340 /* Number of dispatch windows considered for scheduling. */
34341 #define MAX_DISPATCH_WINDOWS 3
34343 /* Maximum number of instructions in a window. */
34344 #define MAX_INSN 4
34346 /* Maximum number of immediate operands in a window. */
34347 #define MAX_IMM 4
34349 /* Maximum number of immediate bits allowed in a window. */
34350 #define MAX_IMM_SIZE 128
34352 /* Maximum number of 32 bit immediates allowed in a window. */
34353 #define MAX_IMM_32 4
34355 /* Maximum number of 64 bit immediates allowed in a window. */
34356 #define MAX_IMM_64 2
34358 /* Maximum total of loads or prefetches allowed in a window. */
34359 #define MAX_LOAD 2
34361 /* Maximum total of stores allowed in a window. */
34362 #define MAX_STORE 1
34364 #undef BIG
34365 #define BIG 100
34368 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
34371 disp_load,
34372 disp_store,
34373 disp_load_store,
34374 disp_prefetch,
34375 disp_imm,
34376 disp_imm_32,
34377 disp_imm_64,
34378 disp_branch,
34379 disp_cmp,
34380 disp_jcc,
34381 disp_last
34382 };
34384 /* Number of allowable groups in a dispatch window. It is an array
34385 indexed by dispatch_group enum. 100 is used as a big number,
34386 because the number of these kind of operations does not have any
34387 effect in dispatch window, but we need them for other reasons in
34388 the table. */
34391 };
34397 };
34399 /* Instruction path. */
34405 last_path
34406 };
34408 /* sched_insn_info defines a window to the instructions scheduled in
34409 the basic block. It contains a pointer to the insn_info table and
34410 the instruction scheduled.
34412 Windows are allocated for each basic block and are linked
34413 together. */
34415 rtx insn;
34422 /* Linked list of dispatch windows. This is a two way list of
34423 dispatch windows of a basic block. It contains information about
34424 the number of uops in the window and the total number of
34425 instructions and of bytes in the object code for this dispatch
34426 window. */
34444 /* Immediate valuse used in an insn. */
34446 {
34455 /* Get dispatch group of insn. */
34457 static enum dispatch_group
34459 {
34475 }
34477 /* Return true if insn is a compare instruction. */
34479 static bool
34481 {
34489 }
34491 /* Return true if a dispatch violation encountered. */
34493 static bool
34495 {
34499 }
34501 /* Return true if insn is a branch instruction. */
34503 static bool
34505 {
34507 }
34509 /* Return true if insn is a prefetch instruction. */
34511 static bool
34513 {
34515 }
34517 /* This function initializes a dispatch window and the list container holding a
34518 pointer to the window. */
34520 static void
34522 {
34528 else
34546 {
34552 }
34554 }
34556 /* This function allocates and initializes a dispatch window and the
34557 list container holding a pointer to the window. */
34561 {
34566 }
34568 /* This routine initializes the dispatch scheduling information. It
34569 initiates building dispatch scheduler tables and constructs the
34570 first dispatch window. */
34572 static void
34574 {
34575 /* Allocate a dispatch list and a window. */
34580 }
34582 /* This function returns true if a branch is detected. End of a basic block
34583 does not have to be a branch, but here we assume only branches end a
34584 window. */
34586 static bool
34588 {
34590 }
34592 /* This function is called when the end of a window processing is reached. */
34594 static void
34596 {
34599 {
34604 }
34606 }
34608 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
34609 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
34610 for 48 bytes of instructions. Note that these windows are not dispatch
34611 windows that their sizes are DISPATCH_WINDOW_SIZE. */
34615 {
34617 {
34622 }
34628 }
34630 /* Increment the number of immediate operands of an instruction. */
34632 static int
34634 {
34639 {
34646 else
34657 {
34660 }
34665 }
34668 }
34670 /* Compute number of immediate operands of an instruction. */
34672 static void
34674 {
34677 }
34679 /* Return total size of immediate operands of an instruction along with number
34680 of corresponding immediate-operands. It initializes its parameters to zero
34681 befor calling FIND_CONSTANT.
34682 INSN is the input instruction. IMM is the total of immediates.
34683 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
34684 bit immediates. */
34686 static int
34688 {
34696 }
34698 /* This function indicates if an operand of an instruction is an
34699 immediate. */
34701 static bool
34703 {
34712 }
34714 /* Return single or double path for instructions. */
34716 static enum insn_path
34718 {
34728 }
34730 /* Return insn dispatch group. */
34732 static enum dispatch_group
34734 {
34752 }
34754 /* Count number of GROUP restricted instructions in a dispatch
34755 window WINDOW_LIST. */
34757 static int
34759 {
34770 {
34789 }
34802 }
34804 /* This function returns true if insn satisfies dispatch rules on the
34805 last window scheduled. */
34807 static bool
34809 {
34817 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
34818 instructions should be given the lowest priority in the
34819 scheduling process in Haifa scheduler to make sure they will be
34820 scheduled in the same dispatch window as the refrence to them. */
34824 /* Check nonrestricted. */
34828 /* Get last dispatch window. */
34833 {
34838 /* Window 1 is full. Go for next window. */
34840 }
34847 /* See if it fits in the first window. */
34849 {
34850 /* The first widow should have only single and double path
34851 uops. */
34857 }
34859 }
34861 /* Add an instruction INSN with NUM_UOPS micro-operations to the
34862 dispatch window WINDOW_LIST. */
34864 static void
34866 {
34884 /* Initialize window with new instruction. */
34905 {
34908 }
34909 }
34911 /* Adds a scheduled instruction, INSN, to the current dispatch window.
34912 If the total bytes of instructions or the number of instructions in
34913 the window exceed allowable, it allocates a new window. */
34915 static void
34917 {
34940 /* Get the last dispatch window. */
34948 else
34951 /* If current window is full, get a new window.
34952 Window number zero is full, if MAX_INSN uops are scheduled in it.
34953 Window number one is full, if window zero's bytes plus window
34954 one's bytes is 32, or if the bytes of the new instruction added
34955 to the total makes it greater than 48, or it has already MAX_INSN
34956 instructions in it. */
34965 {
34968 }
34971 {
34975 {
34978 }
34979 }
34981 {
34986 {
34989 }
34992 }
34993 else
34997 {
34998 /* End of basic block is reached do end-basic-block process. */
35001 }
35002 }
35004 /* Print the dispatch window, WINDOW_NUM, to FILE. */
35006 DEBUG_FUNCTION static void
35008 {
35014 else
35028 {
35031 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
35037 }
35038 }
35040 /* Print to stdout a dispatch window. */
35042 DEBUG_FUNCTION void
35044 {
35046 }
35048 /* Print INSN dispatch information to FILE. */
35050 DEBUG_FUNCTION static void
35052 {
35075 }
35077 /* Print to STDERR the status of the ready list with respect to
35078 dispatch windows. */
35080 DEBUG_FUNCTION void
35082 {
35090 }
35092 /* This routine is the driver of the dispatch scheduler. */
35094 static void
35096 {
35101 }
35103 /* Return TRUE if Dispatch Scheduling is supported. */
35105 static bool
35107 {
35110 {
35126 }
35129 }
35131 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
35132 place emms and femms instructions. */
35134 static enum machine_mode
35136 {
35141 {
35154 else
35164 /* FALLTHRU */
35168 }
35169 }
35171 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
35172 vectors. */
35174 static unsigned int
35176 {
35178 }
35180 /* Initialize the GCC target structure. */
35181 #undef TARGET_RETURN_IN_MEMORY
35182 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
35184 #undef TARGET_LEGITIMIZE_ADDRESS
35185 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
35187 #undef TARGET_ATTRIBUTE_TABLE
35188 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
35189 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
35190 # undef TARGET_MERGE_DECL_ATTRIBUTES
35191 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
35192 #endif
35194 #undef TARGET_COMP_TYPE_ATTRIBUTES
35195 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
35197 #undef TARGET_INIT_BUILTINS
35198 #define TARGET_INIT_BUILTINS ix86_init_builtins
35199 #undef TARGET_BUILTIN_DECL
35200 #define TARGET_BUILTIN_DECL ix86_builtin_decl
35201 #undef TARGET_EXPAND_BUILTIN
35202 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
35204 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
35205 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
35206 ix86_builtin_vectorized_function
35208 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
35209 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
35211 #undef TARGET_BUILTIN_RECIPROCAL
35212 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
35214 #undef TARGET_ASM_FUNCTION_EPILOGUE
35215 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
35217 #undef TARGET_ENCODE_SECTION_INFO
35218 #ifndef SUBTARGET_ENCODE_SECTION_INFO
35219 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
35220 #else
35221 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
35222 #endif
35224 #undef TARGET_ASM_OPEN_PAREN
35226 #undef TARGET_ASM_CLOSE_PAREN
35229 #undef TARGET_ASM_BYTE_OP
35230 #define TARGET_ASM_BYTE_OP ASM_BYTE
35232 #undef TARGET_ASM_ALIGNED_HI_OP
35233 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
35234 #undef TARGET_ASM_ALIGNED_SI_OP
35235 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
35236 #ifdef ASM_QUAD
35237 #undef TARGET_ASM_ALIGNED_DI_OP
35238 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
35239 #endif
35241 #undef TARGET_PROFILE_BEFORE_PROLOGUE
35242 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
35244 #undef TARGET_ASM_UNALIGNED_HI_OP
35245 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
35246 #undef TARGET_ASM_UNALIGNED_SI_OP
35247 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
35248 #undef TARGET_ASM_UNALIGNED_DI_OP
35249 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
35251 #undef TARGET_PRINT_OPERAND
35252 #define TARGET_PRINT_OPERAND ix86_print_operand
35253 #undef TARGET_PRINT_OPERAND_ADDRESS
35254 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
35255 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
35256 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
35257 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
35258 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
35260 #undef TARGET_SCHED_INIT_GLOBAL
35261 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
35262 #undef TARGET_SCHED_ADJUST_COST
35263 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
35264 #undef TARGET_SCHED_ISSUE_RATE
35265 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
35266 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
35267 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
35268 ia32_multipass_dfa_lookahead
35270 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
35271 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
35273 #ifdef HAVE_AS_TLS
35274 #undef TARGET_HAVE_TLS
35275 #define TARGET_HAVE_TLS true
35276 #endif
35277 #undef TARGET_CANNOT_FORCE_CONST_MEM
35278 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
35279 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
35280 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
35282 #undef TARGET_DELEGITIMIZE_ADDRESS
35283 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
35285 #undef TARGET_MS_BITFIELD_LAYOUT_P
35286 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
35288 #if TARGET_MACHO
35289 #undef TARGET_BINDS_LOCAL_P
35290 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
35291 #endif
35292 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
35293 #undef TARGET_BINDS_LOCAL_P
35294 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
35295 #endif
35297 #undef TARGET_ASM_OUTPUT_MI_THUNK
35298 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
35299 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
35300 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
35302 #undef TARGET_ASM_FILE_START
35303 #define TARGET_ASM_FILE_START x86_file_start
35305 #undef TARGET_DEFAULT_TARGET_FLAGS
35306 #define TARGET_DEFAULT_TARGET_FLAGS \
35307 (TARGET_DEFAULT \
35308 | TARGET_SUBTARGET_DEFAULT \
35309 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
35311 #undef TARGET_HANDLE_OPTION
35312 #define TARGET_HANDLE_OPTION ix86_handle_option
35314 #undef TARGET_OPTION_OVERRIDE
35315 #define TARGET_OPTION_OVERRIDE ix86_option_override
35316 #undef TARGET_OPTION_OPTIMIZATION_TABLE
35317 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
35318 #undef TARGET_OPTION_INIT_STRUCT
35319 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
35321 #undef TARGET_REGISTER_MOVE_COST
35322 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
35323 #undef TARGET_MEMORY_MOVE_COST
35324 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
35325 #undef TARGET_RTX_COSTS
35326 #define TARGET_RTX_COSTS ix86_rtx_costs
35327 #undef TARGET_ADDRESS_COST
35328 #define TARGET_ADDRESS_COST ix86_address_cost
35330 #undef TARGET_FIXED_CONDITION_CODE_REGS
35331 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
35332 #undef TARGET_CC_MODES_COMPATIBLE
35333 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
35335 #undef TARGET_MACHINE_DEPENDENT_REORG
35336 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
35338 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
35339 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
35341 #undef TARGET_BUILD_BUILTIN_VA_LIST
35342 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
35344 #undef TARGET_ENUM_VA_LIST_P
35345 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
35347 #undef TARGET_FN_ABI_VA_LIST
35348 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
35350 #undef TARGET_CANONICAL_VA_LIST_TYPE
35351 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
35353 #undef TARGET_EXPAND_BUILTIN_VA_START
35354 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
35356 #undef TARGET_MD_ASM_CLOBBERS
35357 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
35359 #undef TARGET_PROMOTE_PROTOTYPES
35360 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
35361 #undef TARGET_STRUCT_VALUE_RTX
35362 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
35363 #undef TARGET_SETUP_INCOMING_VARARGS
35364 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
35365 #undef TARGET_MUST_PASS_IN_STACK
35366 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
35367 #undef TARGET_FUNCTION_ARG_ADVANCE
35368 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
35369 #undef TARGET_FUNCTION_ARG
35370 #define TARGET_FUNCTION_ARG ix86_function_arg
35371 #undef TARGET_FUNCTION_ARG_BOUNDARY
35372 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
35373 #undef TARGET_PASS_BY_REFERENCE
35374 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
35375 #undef TARGET_INTERNAL_ARG_POINTER
35376 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
35377 #undef TARGET_UPDATE_STACK_BOUNDARY
35378 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
35379 #undef TARGET_GET_DRAP_RTX
35380 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
35381 #undef TARGET_STRICT_ARGUMENT_NAMING
35382 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
35383 #undef TARGET_STATIC_CHAIN
35384 #define TARGET_STATIC_CHAIN ix86_static_chain
35385 #undef TARGET_TRAMPOLINE_INIT
35386 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
35387 #undef TARGET_RETURN_POPS_ARGS
35388 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
35390 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
35391 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
35393 #undef TARGET_SCALAR_MODE_SUPPORTED_P
35394 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
35396 #undef TARGET_VECTOR_MODE_SUPPORTED_P
35397 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
35399 #undef TARGET_C_MODE_FOR_SUFFIX
35400 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
35402 #ifdef HAVE_AS_TLS
35403 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
35404 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
35405 #endif
35407 #ifdef SUBTARGET_INSERT_ATTRIBUTES
35408 #undef TARGET_INSERT_ATTRIBUTES
35409 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
35410 #endif
35412 #undef TARGET_MANGLE_TYPE
35413 #define TARGET_MANGLE_TYPE ix86_mangle_type
35415 #undef TARGET_STACK_PROTECT_FAIL
35416 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
35418 #undef TARGET_SUPPORTS_SPLIT_STACK
35419 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
35421 #undef TARGET_FUNCTION_VALUE
35422 #define TARGET_FUNCTION_VALUE ix86_function_value
35424 #undef TARGET_FUNCTION_VALUE_REGNO_P
35425 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
35427 #undef TARGET_SECONDARY_RELOAD
35428 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
35430 #undef TARGET_PREFERRED_RELOAD_CLASS
35431 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
35432 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
35433 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
35434 #undef TARGET_CLASS_LIKELY_SPILLED_P
35435 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
35437 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
35438 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
35439 ix86_builtin_vectorization_cost
35440 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM
35441 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM \
35442 ix86_vectorize_builtin_vec_perm
35443 #undef TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK
35444 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM_OK \
35445 ix86_vectorize_builtin_vec_perm_ok
35446 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
35447 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
35448 ix86_preferred_simd_mode
35449 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
35450 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
35451 ix86_autovectorize_vector_sizes
35453 #undef TARGET_SET_CURRENT_FUNCTION
35454 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
35456 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
35457 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
35459 #undef TARGET_OPTION_SAVE
35460 #define TARGET_OPTION_SAVE ix86_function_specific_save
35462 #undef TARGET_OPTION_RESTORE
35463 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
35465 #undef TARGET_OPTION_PRINT
35466 #define TARGET_OPTION_PRINT ix86_function_specific_print
35468 #undef TARGET_CAN_INLINE_P
35469 #define TARGET_CAN_INLINE_P ix86_can_inline_p
35471 #undef TARGET_EXPAND_TO_RTL_HOOK
35472 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
35474 #undef TARGET_LEGITIMATE_ADDRESS_P
35475 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
35477 #undef TARGET_LEGITIMATE_CONSTANT_P
35478 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
35480 #undef TARGET_FRAME_POINTER_REQUIRED
35481 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
35483 #undef TARGET_CAN_ELIMINATE
35484 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
35486 #undef TARGET_EXTRA_LIVE_ON_ENTRY
35487 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
35489 #undef TARGET_ASM_CODE_END
35490 #define TARGET_ASM_CODE_END ix86_code_end
35492 #undef TARGET_CONDITIONAL_REGISTER_USAGE
35493 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
35495 #if TARGET_MACHO
35496 #undef TARGET_INIT_LIBFUNCS
35497 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
35498 #endif
35501 \f