gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "stor-layout.h"
  85 #include "tm_p.h"
  86 #include "flags.h"
  87 #include "regs.h"
  88 #include "hard-reg-set.h"
  89 #include "basic-block.h"
  90 #include "insn-config.h"
  91 #include "function.h"
  92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  93 #include "expr.h"
  94 #include "insn-attr.h"
  95 #include "recog.h"
  96 #include "diagnostic-core.h"
  97 #include "target.h"
  98 #include "optabs.h"
  99 #include "insn-codes.h"
 100 #include "rtlhooks-def.h"
 101 #include "params.h"
 102 #include "tree-pass.h"
 103 #include "df.h"
 104 #include "valtrack.h"
 105 #include "cgraph.h"
 106 #include "obstack.h"
 107
 108 /* Number of attempts to combine instructions in this function.  */
 109
 110 static int combine_attempts;
 111
 112 /* Number of attempts that got as far as substitution in this function.  */
 113
 114 static int combine_merges;
 115
 116 /* Number of instructions combined with added SETs in this function.  */
 117
 118 static int combine_extras;
 119
 120 /* Number of instructions combined in this function.  */
 121
 122 static int combine_successes;
 123
 124 /* Totals over entire compilation.  */
 125
 126 static int total_attempts, total_merges, total_extras, total_successes;
 127
 128 /* combine_instructions may try to replace the right hand side of the
 129    second instruction with the value of an associated REG_EQUAL note
 130    before throwing it at try_combine.  That is problematic when there
 131    is a REG_DEAD note for a register used in the old right hand side
 132    and can cause distribute_notes to do wrong things.  This is the
 133    second instruction if it has been so modified, null otherwise.  */
 134
 135 static rtx i2mod;
 136
 137 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 138
 139 static rtx i2mod_old_rhs;
 140
 141 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 142
 143 static rtx i2mod_new_rhs;
 144 \f
 145 typedef struct reg_stat_struct {
 146   /* Record last point of death of (hard or pseudo) register n.  */
 147   rtx                           last_death;
 148
 149   /* Record last point of modification of (hard or pseudo) register n.  */
 150   rtx                           last_set;
 151
 152   /* The next group of fields allows the recording of the last value assigned
 153      to (hard or pseudo) register n.  We use this information to see if an
 154      operation being processed is redundant given a prior operation performed
 155      on the register.  For example, an `and' with a constant is redundant if
 156      all the zero bits are already known to be turned off.
 157
 158      We use an approach similar to that used by cse, but change it in the
 159      following ways:
 160
 161      (1) We do not want to reinitialize at each label.
 162      (2) It is useful, but not critical, to know the actual value assigned
 163          to a register.  Often just its form is helpful.
 164
 165      Therefore, we maintain the following fields:
 166
 167      last_set_value             the last value assigned
 168      last_set_label             records the value of label_tick when the
 169                                 register was assigned
 170      last_set_table_tick        records the value of label_tick when a
 171                                 value using the register is assigned
 172      last_set_invalid           set to nonzero when it is not valid
 173                                 to use the value of this register in some
 174                                 register's value
 175
 176      To understand the usage of these tables, it is important to understand
 177      the distinction between the value in last_set_value being valid and
 178      the register being validly contained in some other expression in the
 179      table.
 180
 181      (The next two parameters are out of date).
 182
 183      reg_stat[i].last_set_value is valid if it is nonzero, and either
 184      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 185
 186      Register I may validly appear in any expression returned for the value
 187      of another register if reg_n_sets[i] is 1.  It may also appear in the
 188      value for register J if reg_stat[j].last_set_invalid is zero, or
 189      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 190
 191      If an expression is found in the table containing a register which may
 192      not validly appear in an expression, the register is replaced by
 193      something that won't match, (clobber (const_int 0)).  */
 194
 195   /* Record last value assigned to (hard or pseudo) register n.  */
 196
 197   rtx                           last_set_value;
 198
 199   /* Record the value of label_tick when an expression involving register n
 200      is placed in last_set_value.  */
 201
 202   int                           last_set_table_tick;
 203
 204   /* Record the value of label_tick when the value for register n is placed in
 205      last_set_value.  */
 206
 207   int                           last_set_label;
 208
 209   /* These fields are maintained in parallel with last_set_value and are
 210      used to store the mode in which the register was last set, the bits
 211      that were known to be zero when it was last set, and the number of
 212      sign bits copies it was known to have when it was last set.  */
 213
 214   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 215   char                          last_set_sign_bit_copies;
 216   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 217
 218   /* Set nonzero if references to register n in expressions should not be
 219      used.  last_set_invalid is set nonzero when this register is being
 220      assigned to and last_set_table_tick == label_tick.  */
 221
 222   char                          last_set_invalid;
 223
 224   /* Some registers that are set more than once and used in more than one
 225      basic block are nevertheless always set in similar ways.  For example,
 226      a QImode register may be loaded from memory in two places on a machine
 227      where byte loads zero extend.
 228
 229      We record in the following fields if a register has some leading bits
 230      that are always equal to the sign bit, and what we know about the
 231      nonzero bits of a register, specifically which bits are known to be
 232      zero.
 233
 234      If an entry is zero, it means that we don't know anything special.  */
 235
 236   unsigned char                 sign_bit_copies;
 237
 238   unsigned HOST_WIDE_INT        nonzero_bits;
 239
 240   /* Record the value of the label_tick when the last truncation
 241      happened.  The field truncated_to_mode is only valid if
 242      truncation_label == label_tick.  */
 243
 244   int                           truncation_label;
 245
 246   /* Record the last truncation seen for this register.  If truncation
 247      is not a nop to this mode we might be able to save an explicit
 248      truncation if we know that value already contains a truncated
 249      value.  */
 250
 251   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 252 } reg_stat_type;
 253
 254
 255 static vec<reg_stat_type> reg_stat;
 256
 257 /* Record the luid of the last insn that invalidated memory
 258    (anything that writes memory, and subroutine calls, but not pushes).  */
 259
 260 static int mem_last_set;
 261
 262 /* Record the luid of the last CALL_INSN
 263    so we can tell whether a potential combination crosses any calls.  */
 264
 265 static int last_call_luid;
 266
 267 /* When `subst' is called, this is the insn that is being modified
 268    (by combining in a previous insn).  The PATTERN of this insn
 269    is still the old pattern partially modified and it should not be
 270    looked at, but this may be used to examine the successors of the insn
 271    to judge whether a simplification is valid.  */
 272
 273 static rtx subst_insn;
 274
 275 /* This is the lowest LUID that `subst' is currently dealing with.
 276    get_last_value will not return a value if the register was set at or
 277    after this LUID.  If not for this mechanism, we could get confused if
 278    I2 or I1 in try_combine were an insn that used the old value of a register
 279    to obtain a new value.  In that case, we might erroneously get the
 280    new value of the register when we wanted the old one.  */
 281
 282 static int subst_low_luid;
 283
 284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 285    must consider all these registers to be always live.  */
 286
 287 static HARD_REG_SET newpat_used_regs;
 288
 289 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 290    insn is the earlier than I2 or I3, combine should rescan starting at
 291    that location.  */
 292
 293 static rtx added_links_insn;
 294
 295 /* Basic block in which we are performing combines.  */
 296 static basic_block this_basic_block;
 297 static bool optimize_this_for_speed_p;
 298
 299 \f
 300 /* Length of the currently allocated uid_insn_cost array.  */
 301
 302 static int max_uid_known;
 303
 304 /* The following array records the insn_rtx_cost for every insn
 305    in the instruction stream.  */
 306
 307 static int *uid_insn_cost;
 308
 309 /* The following array records the LOG_LINKS for every insn in the
 310    instruction stream as struct insn_link pointers.  */
 311
 312 struct insn_link {
 313   rtx insn;
 314   struct insn_link *next;
 315 };
 316
 317 static struct insn_link **uid_log_links;
 318
 319 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 320 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 321
 322 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 323   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 324
 325 /* Links for LOG_LINKS are allocated from this obstack.  */
 326
 327 static struct obstack insn_link_obstack;
 328
 329 /* Allocate a link.  */
 330
 331 static inline struct insn_link *
 332 alloc_insn_link (rtx insn, struct insn_link *next)
 333 {
 334   struct insn_link *l
 335     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 336                                           sizeof (struct insn_link));
 337   l->insn = insn;
 338   l->next = next;
 339   return l;
 340 }
 341
 342 /* Incremented for each basic block.  */
 343
 344 static int label_tick;
 345
 346 /* Reset to label_tick for each extended basic block in scanning order.  */
 347
 348 static int label_tick_ebb_start;
 349
 350 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 351    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 352
 353 static enum machine_mode nonzero_bits_mode;
 354
 355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 356    be safely used.  It is zero while computing them and after combine has
 357    completed.  This former test prevents propagating values based on
 358    previously set values, which can be incorrect if a variable is modified
 359    in a loop.  */
 360
 361 static int nonzero_sign_valid;
 362
 363 \f
 364 /* Record one modification to rtl structure
 365    to be undone by storing old_contents into *where.  */
 366
 367 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 368
 369 struct undo
 370 {
 371   struct undo *next;
 372   enum undo_kind kind;
 373   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 374   union { rtx *r; int *i; struct insn_link **l; } where;
 375 };
 376
 377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 378    num_undo says how many are currently recorded.
 379
 380    other_insn is nonzero if we have modified some other insn in the process
 381    of working on subst_insn.  It must be verified too.  */
 382
 383 struct undobuf
 384 {
 385   struct undo *undos;
 386   struct undo *frees;
 387   rtx other_insn;
 388 };
 389
 390 static struct undobuf undobuf;
 391
 392 /* Number of times the pseudo being substituted for
 393    was found and replaced.  */
 394
 395 static int n_occurrences;
 396
 397 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 398                                          enum machine_mode,
 399                                          unsigned HOST_WIDE_INT,
 400                                          unsigned HOST_WIDE_INT *);
 401 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 402                                                 enum machine_mode,
 403                                                 unsigned int, unsigned int *);
 404 static void do_SUBST (rtx *, rtx);
 405 static void do_SUBST_INT (int *, int);
 406 static void init_reg_last (void);
 407 static void setup_incoming_promotions (rtx);
 408 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 409 static int cant_combine_insn_p (rtx);
 410 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 411 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 412 static int contains_muldiv (rtx);
 413 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 414 static void undo_all (void);
 415 static void undo_commit (void);
 416 static rtx *find_split_point (rtx *, rtx, bool);
 417 static rtx subst (rtx, rtx, rtx, int, int, int);
 418 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 419 static rtx simplify_if_then_else (rtx);
 420 static rtx simplify_set (rtx);
 421 static rtx simplify_logical (rtx);
 422 static rtx expand_compound_operation (rtx);
 423 static const_rtx expand_field_assignment (const_rtx);
 424 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 425                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 426 static rtx extract_left_shift (rtx, int);
 427 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 428                               unsigned HOST_WIDE_INT *);
 429 static rtx canon_reg_for_combine (rtx, rtx);
 430 static rtx force_to_mode (rtx, enum machine_mode,
 431                           unsigned HOST_WIDE_INT, int);
 432 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 433 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 434 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 435 static rtx make_field_assignment (rtx);
 436 static rtx apply_distributive_law (rtx);
 437 static rtx distribute_and_simplify_rtx (rtx, int);
 438 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 439                                      unsigned HOST_WIDE_INT);
 440 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 441                                    unsigned HOST_WIDE_INT);
 442 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 443                             HOST_WIDE_INT, enum machine_mode, int *);
 444 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 445 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 446                                  int);
 447 static int recog_for_combine (rtx *, rtx, rtx *);
 448 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 449 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 450 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 451 static void update_table_tick (rtx);
 452 static void record_value_for_reg (rtx, rtx, rtx);
 453 static void check_promoted_subreg (rtx, rtx);
 454 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 455 static void record_dead_and_set_regs (rtx);
 456 static int get_last_value_validate (rtx *, rtx, int, int);
 457 static rtx get_last_value (const_rtx);
 458 static int use_crosses_set_p (const_rtx, int);
 459 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 460 static int reg_dead_at_p (rtx, rtx);
 461 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 462 static int reg_bitfield_target_p (rtx, rtx);
 463 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 464 static void distribute_links (struct insn_link *);
 465 static void mark_used_regs_combine (rtx);
 466 static void record_promoted_value (rtx, rtx);
 467 static int unmentioned_reg_p_1 (rtx *, void *);
 468 static bool unmentioned_reg_p (rtx, rtx);
 469 static int record_truncated_value (rtx *, void *);
 470 static void record_truncated_values (rtx *, void *);
 471 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 472 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 473 \f
 474
 475 /* It is not safe to use ordinary gen_lowpart in combine.
 476    See comments in gen_lowpart_for_combine.  */
 477 #undef RTL_HOOKS_GEN_LOWPART
 478 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 479
 480 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 481 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 482 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 483
 484 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 485 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 486
 487 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 488 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 489
 490 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 491 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 492
 493 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 494
 495 \f
 496 /* Convenience wrapper for the canonicalize_comparison target hook.
 497    Target hooks cannot use enum rtx_code.  */
 498 static inline void
 499 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 500                                 bool op0_preserve_value)
 501 {
 502   int code_int = (int)*code;
 503   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 504   *code = (enum rtx_code)code_int;
 505 }
 506
 507 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 508    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 509    This is a wrapper around split_insns which ensures that the
 510    reg_stat vector is made larger if the splitter creates a new
 511    register.  */
 512
 513 static rtx
 514 combine_split_insns (rtx pattern, rtx insn)
 515 {
 516   rtx ret;
 517   unsigned int nregs;
 518
 519   ret = split_insns (pattern, insn);
 520   nregs = max_reg_num ();
 521   if (nregs > reg_stat.length ())
 522     reg_stat.safe_grow_cleared (nregs);
 523   return ret;
 524 }
 525
 526 /* This is used by find_single_use to locate an rtx in LOC that
 527    contains exactly one use of DEST, which is typically either a REG
 528    or CC0.  It returns a pointer to the innermost rtx expression
 529    containing DEST.  Appearances of DEST that are being used to
 530    totally replace it are not counted.  */
 531
 532 static rtx *
 533 find_single_use_1 (rtx dest, rtx *loc)
 534 {
 535   rtx x = *loc;
 536   enum rtx_code code = GET_CODE (x);
 537   rtx *result = NULL;
 538   rtx *this_result;
 539   int i;
 540   const char *fmt;
 541
 542   switch (code)
 543     {
 544     case CONST:
 545     case LABEL_REF:
 546     case SYMBOL_REF:
 547     CASE_CONST_ANY:
 548     case CLOBBER:
 549       return 0;
 550
 551     case SET:
 552       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 553          of a REG that occupies all of the REG, the insn uses DEST if
 554          it is mentioned in the destination or the source.  Otherwise, we
 555          need just check the source.  */
 556       if (GET_CODE (SET_DEST (x)) != CC0
 557           && GET_CODE (SET_DEST (x)) != PC
 558           && !REG_P (SET_DEST (x))
 559           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 560                 && REG_P (SUBREG_REG (SET_DEST (x)))
 561                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 562                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 563                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 564                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 565         break;
 566
 567       return find_single_use_1 (dest, &SET_SRC (x));
 568
 569     case MEM:
 570     case SUBREG:
 571       return find_single_use_1 (dest, &XEXP (x, 0));
 572
 573     default:
 574       break;
 575     }
 576
 577   /* If it wasn't one of the common cases above, check each expression and
 578      vector of this code.  Look for a unique usage of DEST.  */
 579
 580   fmt = GET_RTX_FORMAT (code);
 581   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 582     {
 583       if (fmt[i] == 'e')
 584         {
 585           if (dest == XEXP (x, i)
 586               || (REG_P (dest) && REG_P (XEXP (x, i))
 587                   && REGNO (dest) == REGNO (XEXP (x, i))))
 588             this_result = loc;
 589           else
 590             this_result = find_single_use_1 (dest, &XEXP (x, i));
 591
 592           if (result == NULL)
 593             result = this_result;
 594           else if (this_result)
 595             /* Duplicate usage.  */
 596             return NULL;
 597         }
 598       else if (fmt[i] == 'E')
 599         {
 600           int j;
 601
 602           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 603             {
 604               if (XVECEXP (x, i, j) == dest
 605                   || (REG_P (dest)
 606                       && REG_P (XVECEXP (x, i, j))
 607                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 608                 this_result = loc;
 609               else
 610                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 611
 612               if (result == NULL)
 613                 result = this_result;
 614               else if (this_result)
 615                 return NULL;
 616             }
 617         }
 618     }
 619
 620   return result;
 621 }
 622
 623
 624 /* See if DEST, produced in INSN, is used only a single time in the
 625    sequel.  If so, return a pointer to the innermost rtx expression in which
 626    it is used.
 627
 628    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 629
 630    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 631    care about REG_DEAD notes or LOG_LINKS.
 632
 633    Otherwise, we find the single use by finding an insn that has a
 634    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 635    only referenced once in that insn, we know that it must be the first
 636    and last insn referencing DEST.  */
 637
 638 static rtx *
 639 find_single_use (rtx dest, rtx insn, rtx *ploc)
 640 {
 641   basic_block bb;
 642   rtx next;
 643   rtx *result;
 644   struct insn_link *link;
 645
 646 #ifdef HAVE_cc0
 647   if (dest == cc0_rtx)
 648     {
 649       next = NEXT_INSN (insn);
 650       if (next == 0
 651           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 652         return 0;
 653
 654       result = find_single_use_1 (dest, &PATTERN (next));
 655       if (result && ploc)
 656         *ploc = next;
 657       return result;
 658     }
 659 #endif
 660
 661   if (!REG_P (dest))
 662     return 0;
 663
 664   bb = BLOCK_FOR_INSN (insn);
 665   for (next = NEXT_INSN (insn);
 666        next && BLOCK_FOR_INSN (next) == bb;
 667        next = NEXT_INSN (next))
 668     if (INSN_P (next) && dead_or_set_p (next, dest))
 669       {
 670         FOR_EACH_LOG_LINK (link, next)
 671           if (link->insn == insn)
 672             break;
 673
 674         if (link)
 675           {
 676             result = find_single_use_1 (dest, &PATTERN (next));
 677             if (ploc)
 678               *ploc = next;
 679             return result;
 680           }
 681       }
 682
 683   return 0;
 684 }
 685 \f
 686 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 687    insn.  The substitution can be undone by undo_all.  If INTO is already
 688    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 689    also call SUBST, we have to compute it before we put anything into
 690    the undo table.  */
 691
 692 static void
 693 do_SUBST (rtx *into, rtx newval)
 694 {
 695   struct undo *buf;
 696   rtx oldval = *into;
 697
 698   if (oldval == newval)
 699     return;
 700
 701   /* We'd like to catch as many invalid transformations here as
 702      possible.  Unfortunately, there are way too many mode changes
 703      that are perfectly valid, so we'd waste too much effort for
 704      little gain doing the checks here.  Focus on catching invalid
 705      transformations involving integer constants.  */
 706   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 707       && CONST_INT_P (newval))
 708     {
 709       /* Sanity check that we're replacing oldval with a CONST_INT
 710          that is a valid sign-extension for the original mode.  */
 711       gcc_assert (INTVAL (newval)
 712                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 713
 714       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 715          CONST_INT is not valid, because after the replacement, the
 716          original mode would be gone.  Unfortunately, we can't tell
 717          when do_SUBST is called to replace the operand thereof, so we
 718          perform this test on oldval instead, checking whether an
 719          invalid replacement took place before we got here.  */
 720       gcc_assert (!(GET_CODE (oldval) == SUBREG
 721                     && CONST_INT_P (SUBREG_REG (oldval))));
 722       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 723                     && CONST_INT_P (XEXP (oldval, 0))));
 724     }
 725
 726   if (undobuf.frees)
 727     buf = undobuf.frees, undobuf.frees = buf->next;
 728   else
 729     buf = XNEW (struct undo);
 730
 731   buf->kind = UNDO_RTX;
 732   buf->where.r = into;
 733   buf->old_contents.r = oldval;
 734   *into = newval;
 735
 736   buf->next = undobuf.undos, undobuf.undos = buf;
 737 }
 738
 739 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 740
 741 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 742    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 743    not safe.  */
 744
 745 static void
 746 do_SUBST_INT (int *into, int newval)
 747 {
 748   struct undo *buf;
 749   int oldval = *into;
 750
 751   if (oldval == newval)
 752     return;
 753
 754   if (undobuf.frees)
 755     buf = undobuf.frees, undobuf.frees = buf->next;
 756   else
 757     buf = XNEW (struct undo);
 758
 759   buf->kind = UNDO_INT;
 760   buf->where.i = into;
 761   buf->old_contents.i = oldval;
 762   *into = newval;
 763
 764   buf->next = undobuf.undos, undobuf.undos = buf;
 765 }
 766
 767 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 768
 769 /* Similar to SUBST, but just substitute the mode.  This is used when
 770    changing the mode of a pseudo-register, so that any other
 771    references to the entry in the regno_reg_rtx array will change as
 772    well.  */
 773
 774 static void
 775 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 776 {
 777   struct undo *buf;
 778   enum machine_mode oldval = GET_MODE (*into);
 779
 780   if (oldval == newval)
 781     return;
 782
 783   if (undobuf.frees)
 784     buf = undobuf.frees, undobuf.frees = buf->next;
 785   else
 786     buf = XNEW (struct undo);
 787
 788   buf->kind = UNDO_MODE;
 789   buf->where.r = into;
 790   buf->old_contents.m = oldval;
 791   adjust_reg_mode (*into, newval);
 792
 793   buf->next = undobuf.undos, undobuf.undos = buf;
 794 }
 795
 796 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 797
 798 #ifndef HAVE_cc0
 799 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 800
 801 static void
 802 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 803 {
 804   struct undo *buf;
 805   struct insn_link * oldval = *into;
 806
 807   if (oldval == newval)
 808     return;
 809
 810   if (undobuf.frees)
 811     buf = undobuf.frees, undobuf.frees = buf->next;
 812   else
 813     buf = XNEW (struct undo);
 814
 815   buf->kind = UNDO_LINKS;
 816   buf->where.l = into;
 817   buf->old_contents.l = oldval;
 818   *into = newval;
 819
 820   buf->next = undobuf.undos, undobuf.undos = buf;
 821 }
 822
 823 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 824 #endif
 825 \f
 826 /* Subroutine of try_combine.  Determine whether the replacement patterns
 827    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 828    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 829    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 830    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 831    of all the instructions can be estimated and the replacements are more
 832    expensive than the original sequence.  */
 833
 834 static bool
 835 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 836                        rtx newi2pat, rtx newotherpat)
 837 {
 838   int i0_cost, i1_cost, i2_cost, i3_cost;
 839   int new_i2_cost, new_i3_cost;
 840   int old_cost, new_cost;
 841
 842   /* Lookup the original insn_rtx_costs.  */
 843   i2_cost = INSN_COST (i2);
 844   i3_cost = INSN_COST (i3);
 845
 846   if (i1)
 847     {
 848       i1_cost = INSN_COST (i1);
 849       if (i0)
 850         {
 851           i0_cost = INSN_COST (i0);
 852           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 853                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 854         }
 855       else
 856         {
 857           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 858                       ? i1_cost + i2_cost + i3_cost : 0);
 859           i0_cost = 0;
 860         }
 861     }
 862   else
 863     {
 864       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 865       i1_cost = i0_cost = 0;
 866     }
 867
 868   /* Calculate the replacement insn_rtx_costs.  */
 869   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 870   if (newi2pat)
 871     {
 872       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 873       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 874                  ? new_i2_cost + new_i3_cost : 0;
 875     }
 876   else
 877     {
 878       new_cost = new_i3_cost;
 879       new_i2_cost = 0;
 880     }
 881
 882   if (undobuf.other_insn)
 883     {
 884       int old_other_cost, new_other_cost;
 885
 886       old_other_cost = INSN_COST (undobuf.other_insn);
 887       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 888       if (old_other_cost > 0 && new_other_cost > 0)
 889         {
 890           old_cost += old_other_cost;
 891           new_cost += new_other_cost;
 892         }
 893       else
 894         old_cost = 0;
 895     }
 896
 897   /* Disallow this combination if both new_cost and old_cost are greater than
 898      zero, and new_cost is greater than old cost.  */
 899   if (old_cost > 0 && new_cost > old_cost)
 900     {
 901       if (dump_file)
 902         {
 903           if (i0)
 904             {
 905               fprintf (dump_file,
 906                        "rejecting combination of insns %d, %d, %d and %d\n",
 907                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 908                        INSN_UID (i3));
 909               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 910                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 911             }
 912           else if (i1)
 913             {
 914               fprintf (dump_file,
 915                        "rejecting combination of insns %d, %d and %d\n",
 916                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 917               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 918                        i1_cost, i2_cost, i3_cost, old_cost);
 919             }
 920           else
 921             {
 922               fprintf (dump_file,
 923                        "rejecting combination of insns %d and %d\n",
 924                        INSN_UID (i2), INSN_UID (i3));
 925               fprintf (dump_file, "original costs %d + %d = %d\n",
 926                        i2_cost, i3_cost, old_cost);
 927             }
 928
 929           if (newi2pat)
 930             {
 931               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 932                        new_i2_cost, new_i3_cost, new_cost);
 933             }
 934           else
 935             fprintf (dump_file, "replacement cost %d\n", new_cost);
 936         }
 937
 938       return false;
 939     }
 940
 941   /* Update the uid_insn_cost array with the replacement costs.  */
 942   INSN_COST (i2) = new_i2_cost;
 943   INSN_COST (i3) = new_i3_cost;
 944   if (i1)
 945     {
 946       INSN_COST (i1) = 0;
 947       if (i0)
 948         INSN_COST (i0) = 0;
 949     }
 950
 951   return true;
 952 }
 953
 954
 955 /* Delete any insns that copy a register to itself.  */
 956
 957 static void
 958 delete_noop_moves (void)
 959 {
 960   rtx insn, next;
 961   basic_block bb;
 962
 963   FOR_EACH_BB (bb)
 964     {
 965       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 966         {
 967           next = NEXT_INSN (insn);
 968           if (INSN_P (insn) && noop_move_p (insn))
 969             {
 970               if (dump_file)
 971                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 972
 973               delete_insn_and_edges (insn);
 974             }
 975         }
 976     }
 977 }
 978
 979 \f
 980 /* Fill in log links field for all insns.  */
 981
 982 static void
 983 create_log_links (void)
 984 {
 985   basic_block bb;
 986   rtx *next_use, insn;
 987   df_ref *def_vec, *use_vec;
 988
 989   next_use = XCNEWVEC (rtx, max_reg_num ());
 990
 991   /* Pass through each block from the end, recording the uses of each
 992      register and establishing log links when def is encountered.
 993      Note that we do not clear next_use array in order to save time,
 994      so we have to test whether the use is in the same basic block as def.
 995
 996      There are a few cases below when we do not consider the definition or
 997      usage -- these are taken from original flow.c did. Don't ask me why it is
 998      done this way; I don't know and if it works, I don't want to know.  */
 999
1000   FOR_EACH_BB (bb)
1001     {
1002       FOR_BB_INSNS_REVERSE (bb, insn)
1003         {
1004           if (!NONDEBUG_INSN_P (insn))
1005             continue;
1006
1007           /* Log links are created only once.  */
1008           gcc_assert (!LOG_LINKS (insn));
1009
1010           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1011             {
1012               df_ref def = *def_vec;
1013               int regno = DF_REF_REGNO (def);
1014               rtx use_insn;
1015
1016               if (!next_use[regno])
1017                 continue;
1018
1019               /* Do not consider if it is pre/post modification in MEM.  */
1020               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1021                 continue;
1022
1023               /* Do not make the log link for frame pointer.  */
1024               if ((regno == FRAME_POINTER_REGNUM
1025                    && (! reload_completed || frame_pointer_needed))
1026 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1027                   || (regno == HARD_FRAME_POINTER_REGNUM
1028                       && (! reload_completed || frame_pointer_needed))
1029 #endif
1030 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1031                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1032 #endif
1033                   )
1034                 continue;
1035
1036               use_insn = next_use[regno];
1037               if (BLOCK_FOR_INSN (use_insn) == bb)
1038                 {
1039                   /* flow.c claimed:
1040
1041                      We don't build a LOG_LINK for hard registers contained
1042                      in ASM_OPERANDs.  If these registers get replaced,
1043                      we might wind up changing the semantics of the insn,
1044                      even if reload can make what appear to be valid
1045                      assignments later.  */
1046                   if (regno >= FIRST_PSEUDO_REGISTER
1047                       || asm_noperands (PATTERN (use_insn)) < 0)
1048                     {
1049                       /* Don't add duplicate links between instructions.  */
1050                       struct insn_link *links;
1051                       FOR_EACH_LOG_LINK (links, use_insn)
1052                         if (insn == links->insn)
1053                           break;
1054
1055                       if (!links)
1056                         LOG_LINKS (use_insn)
1057                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1058                     }
1059                 }
1060               next_use[regno] = NULL_RTX;
1061             }
1062
1063           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1064             {
1065               df_ref use = *use_vec;
1066               int regno = DF_REF_REGNO (use);
1067
1068               /* Do not consider the usage of the stack pointer
1069                  by function call.  */
1070               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1071                 continue;
1072
1073               next_use[regno] = insn;
1074             }
1075         }
1076     }
1077
1078   free (next_use);
1079 }
1080
1081 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1082    true if we found a LOG_LINK that proves that A feeds B.  This only works
1083    if there are no instructions between A and B which could have a link
1084    depending on A, since in that case we would not record a link for B.
1085    We also check the implicit dependency created by a cc0 setter/user
1086    pair.  */
1087
1088 static bool
1089 insn_a_feeds_b (rtx a, rtx b)
1090 {
1091   struct insn_link *links;
1092   FOR_EACH_LOG_LINK (links, b)
1093     if (links->insn == a)
1094       return true;
1095 #ifdef HAVE_cc0
1096   if (sets_cc0_p (a))
1097     return true;
1098 #endif
1099   return false;
1100 }
1101 \f
1102 /* Main entry point for combiner.  F is the first insn of the function.
1103    NREGS is the first unused pseudo-reg number.
1104
1105    Return nonzero if the combiner has turned an indirect jump
1106    instruction into a direct jump.  */
1107 static int
1108 combine_instructions (rtx f, unsigned int nregs)
1109 {
1110   rtx insn, next;
1111 #ifdef HAVE_cc0
1112   rtx prev;
1113 #endif
1114   struct insn_link *links, *nextlinks;
1115   rtx first;
1116   basic_block last_bb;
1117
1118   int new_direct_jump_p = 0;
1119
1120   for (first = f; first && !INSN_P (first); )
1121     first = NEXT_INSN (first);
1122   if (!first)
1123     return 0;
1124
1125   combine_attempts = 0;
1126   combine_merges = 0;
1127   combine_extras = 0;
1128   combine_successes = 0;
1129
1130   rtl_hooks = combine_rtl_hooks;
1131
1132   reg_stat.safe_grow_cleared (nregs);
1133
1134   init_recog_no_volatile ();
1135
1136   /* Allocate array for insn info.  */
1137   max_uid_known = get_max_uid ();
1138   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1139   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1140   gcc_obstack_init (&insn_link_obstack);
1141
1142   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1143
1144   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1145      problems when, for example, we have j <<= 1 in a loop.  */
1146
1147   nonzero_sign_valid = 0;
1148   label_tick = label_tick_ebb_start = 1;
1149
1150   /* Scan all SETs and see if we can deduce anything about what
1151      bits are known to be zero for some registers and how many copies
1152      of the sign bit are known to exist for those registers.
1153
1154      Also set any known values so that we can use it while searching
1155      for what bits are known to be set.  */
1156
1157   setup_incoming_promotions (first);
1158   /* Allow the entry block and the first block to fall into the same EBB.
1159      Conceptually the incoming promotions are assigned to the entry block.  */
1160   last_bb = ENTRY_BLOCK_PTR;
1161
1162   create_log_links ();
1163   FOR_EACH_BB (this_basic_block)
1164     {
1165       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1166       last_call_luid = 0;
1167       mem_last_set = -1;
1168
1169       label_tick++;
1170       if (!single_pred_p (this_basic_block)
1171           || single_pred (this_basic_block) != last_bb)
1172         label_tick_ebb_start = label_tick;
1173       last_bb = this_basic_block;
1174
1175       FOR_BB_INSNS (this_basic_block, insn)
1176         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1177           {
1178 #ifdef AUTO_INC_DEC
1179             rtx links;
1180 #endif
1181
1182             subst_low_luid = DF_INSN_LUID (insn);
1183             subst_insn = insn;
1184
1185             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1186                          insn);
1187             record_dead_and_set_regs (insn);
1188
1189 #ifdef AUTO_INC_DEC
1190             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1191               if (REG_NOTE_KIND (links) == REG_INC)
1192                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1193                                                   insn);
1194 #endif
1195
1196             /* Record the current insn_rtx_cost of this instruction.  */
1197             if (NONJUMP_INSN_P (insn))
1198               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1199                                                 optimize_this_for_speed_p);
1200             if (dump_file)
1201               fprintf (dump_file, "insn_cost %d: %d\n",
1202                        INSN_UID (insn), INSN_COST (insn));
1203           }
1204     }
1205
1206   nonzero_sign_valid = 1;
1207
1208   /* Now scan all the insns in forward order.  */
1209   label_tick = label_tick_ebb_start = 1;
1210   init_reg_last ();
1211   setup_incoming_promotions (first);
1212   last_bb = ENTRY_BLOCK_PTR;
1213
1214   FOR_EACH_BB (this_basic_block)
1215     {
1216       rtx last_combined_insn = NULL_RTX;
1217       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1218       last_call_luid = 0;
1219       mem_last_set = -1;
1220
1221       label_tick++;
1222       if (!single_pred_p (this_basic_block)
1223           || single_pred (this_basic_block) != last_bb)
1224         label_tick_ebb_start = label_tick;
1225       last_bb = this_basic_block;
1226
1227       rtl_profile_for_bb (this_basic_block);
1228       for (insn = BB_HEAD (this_basic_block);
1229            insn != NEXT_INSN (BB_END (this_basic_block));
1230            insn = next ? next : NEXT_INSN (insn))
1231         {
1232           next = 0;
1233           if (NONDEBUG_INSN_P (insn))
1234             {
1235               while (last_combined_insn
1236                      && INSN_DELETED_P (last_combined_insn))
1237                 last_combined_insn = PREV_INSN (last_combined_insn);
1238               if (last_combined_insn == NULL_RTX
1239                   || BARRIER_P (last_combined_insn)
1240                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1241                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1242                 last_combined_insn = insn;
1243
1244               /* See if we know about function return values before this
1245                  insn based upon SUBREG flags.  */
1246               check_promoted_subreg (insn, PATTERN (insn));
1247
1248               /* See if we can find hardregs and subreg of pseudos in
1249                  narrower modes.  This could help turning TRUNCATEs
1250                  into SUBREGs.  */
1251               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1252
1253               /* Try this insn with each insn it links back to.  */
1254
1255               FOR_EACH_LOG_LINK (links, insn)
1256                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1257                                          NULL_RTX, &new_direct_jump_p,
1258                                          last_combined_insn)) != 0)
1259                   goto retry;
1260
1261               /* Try each sequence of three linked insns ending with this one.  */
1262
1263               FOR_EACH_LOG_LINK (links, insn)
1264                 {
1265                   rtx link = links->insn;
1266
1267                   /* If the linked insn has been replaced by a note, then there
1268                      is no point in pursuing this chain any further.  */
1269                   if (NOTE_P (link))
1270                     continue;
1271
1272                   FOR_EACH_LOG_LINK (nextlinks, link)
1273                     if ((next = try_combine (insn, link, nextlinks->insn,
1274                                              NULL_RTX, &new_direct_jump_p,
1275                                              last_combined_insn)) != 0)
1276                       goto retry;
1277                 }
1278
1279 #ifdef HAVE_cc0
1280               /* Try to combine a jump insn that uses CC0
1281                  with a preceding insn that sets CC0, and maybe with its
1282                  logical predecessor as well.
1283                  This is how we make decrement-and-branch insns.
1284                  We need this special code because data flow connections
1285                  via CC0 do not get entered in LOG_LINKS.  */
1286
1287               if (JUMP_P (insn)
1288                   && (prev = prev_nonnote_insn (insn)) != 0
1289                   && NONJUMP_INSN_P (prev)
1290                   && sets_cc0_p (PATTERN (prev)))
1291                 {
1292                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1293                                            &new_direct_jump_p,
1294                                            last_combined_insn)) != 0)
1295                     goto retry;
1296
1297                   FOR_EACH_LOG_LINK (nextlinks, prev)
1298                     if ((next = try_combine (insn, prev, nextlinks->insn,
1299                                              NULL_RTX, &new_direct_jump_p,
1300                                              last_combined_insn)) != 0)
1301                       goto retry;
1302                 }
1303
1304               /* Do the same for an insn that explicitly references CC0.  */
1305               if (NONJUMP_INSN_P (insn)
1306                   && (prev = prev_nonnote_insn (insn)) != 0
1307                   && NONJUMP_INSN_P (prev)
1308                   && sets_cc0_p (PATTERN (prev))
1309                   && GET_CODE (PATTERN (insn)) == SET
1310                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1311                 {
1312                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1313                                            &new_direct_jump_p,
1314                                            last_combined_insn)) != 0)
1315                     goto retry;
1316
1317                   FOR_EACH_LOG_LINK (nextlinks, prev)
1318                     if ((next = try_combine (insn, prev, nextlinks->insn,
1319                                              NULL_RTX, &new_direct_jump_p,
1320                                              last_combined_insn)) != 0)
1321                       goto retry;
1322                 }
1323
1324               /* Finally, see if any of the insns that this insn links to
1325                  explicitly references CC0.  If so, try this insn, that insn,
1326                  and its predecessor if it sets CC0.  */
1327               FOR_EACH_LOG_LINK (links, insn)
1328                 if (NONJUMP_INSN_P (links->insn)
1329                     && GET_CODE (PATTERN (links->insn)) == SET
1330                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1331                     && (prev = prev_nonnote_insn (links->insn)) != 0
1332                     && NONJUMP_INSN_P (prev)
1333                     && sets_cc0_p (PATTERN (prev))
1334                     && (next = try_combine (insn, links->insn,
1335                                             prev, NULL_RTX, &new_direct_jump_p,
1336                                             last_combined_insn)) != 0)
1337                   goto retry;
1338 #endif
1339
1340               /* Try combining an insn with two different insns whose results it
1341                  uses.  */
1342               FOR_EACH_LOG_LINK (links, insn)
1343                 for (nextlinks = links->next; nextlinks;
1344                      nextlinks = nextlinks->next)
1345                   if ((next = try_combine (insn, links->insn,
1346                                            nextlinks->insn, NULL_RTX,
1347                                            &new_direct_jump_p,
1348                                            last_combined_insn)) != 0)
1349                     goto retry;
1350
1351               /* Try four-instruction combinations.  */
1352               FOR_EACH_LOG_LINK (links, insn)
1353                 {
1354                   struct insn_link *next1;
1355                   rtx link = links->insn;
1356
1357                   /* If the linked insn has been replaced by a note, then there
1358                      is no point in pursuing this chain any further.  */
1359                   if (NOTE_P (link))
1360                     continue;
1361
1362                   FOR_EACH_LOG_LINK (next1, link)
1363                     {
1364                       rtx link1 = next1->insn;
1365                       if (NOTE_P (link1))
1366                         continue;
1367                       /* I0 -> I1 -> I2 -> I3.  */
1368                       FOR_EACH_LOG_LINK (nextlinks, link1)
1369                         if ((next = try_combine (insn, link, link1,
1370                                                  nextlinks->insn,
1371                                                  &new_direct_jump_p,
1372                                                  last_combined_insn)) != 0)
1373                           goto retry;
1374                       /* I0, I1 -> I2, I2 -> I3.  */
1375                       for (nextlinks = next1->next; nextlinks;
1376                            nextlinks = nextlinks->next)
1377                         if ((next = try_combine (insn, link, link1,
1378                                                  nextlinks->insn,
1379                                                  &new_direct_jump_p,
1380                                                  last_combined_insn)) != 0)
1381                           goto retry;
1382                     }
1383
1384                   for (next1 = links->next; next1; next1 = next1->next)
1385                     {
1386                       rtx link1 = next1->insn;
1387                       if (NOTE_P (link1))
1388                         continue;
1389                       /* I0 -> I2; I1, I2 -> I3.  */
1390                       FOR_EACH_LOG_LINK (nextlinks, link)
1391                         if ((next = try_combine (insn, link, link1,
1392                                                  nextlinks->insn,
1393                                                  &new_direct_jump_p,
1394                                                  last_combined_insn)) != 0)
1395                           goto retry;
1396                       /* I0 -> I1; I1, I2 -> I3.  */
1397                       FOR_EACH_LOG_LINK (nextlinks, link1)
1398                         if ((next = try_combine (insn, link, link1,
1399                                                  nextlinks->insn,
1400                                                  &new_direct_jump_p,
1401                                                  last_combined_insn)) != 0)
1402                           goto retry;
1403                     }
1404                 }
1405
1406               /* Try this insn with each REG_EQUAL note it links back to.  */
1407               FOR_EACH_LOG_LINK (links, insn)
1408                 {
1409                   rtx set, note;
1410                   rtx temp = links->insn;
1411                   if ((set = single_set (temp)) != 0
1412                       && (note = find_reg_equal_equiv_note (temp)) != 0
1413                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1414                       /* Avoid using a register that may already been marked
1415                          dead by an earlier instruction.  */
1416                       && ! unmentioned_reg_p (note, SET_SRC (set))
1417                       && (GET_MODE (note) == VOIDmode
1418                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1419                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1420                     {
1421                       /* Temporarily replace the set's source with the
1422                          contents of the REG_EQUAL note.  The insn will
1423                          be deleted or recognized by try_combine.  */
1424                       rtx orig = SET_SRC (set);
1425                       SET_SRC (set) = note;
1426                       i2mod = temp;
1427                       i2mod_old_rhs = copy_rtx (orig);
1428                       i2mod_new_rhs = copy_rtx (note);
1429                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1430                                           &new_direct_jump_p,
1431                                           last_combined_insn);
1432                       i2mod = NULL_RTX;
1433                       if (next)
1434                         goto retry;
1435                       SET_SRC (set) = orig;
1436                     }
1437                 }
1438
1439               if (!NOTE_P (insn))
1440                 record_dead_and_set_regs (insn);
1441
1442             retry:
1443               ;
1444             }
1445         }
1446     }
1447
1448   default_rtl_profile ();
1449   clear_bb_flags ();
1450   new_direct_jump_p |= purge_all_dead_edges ();
1451   delete_noop_moves ();
1452
1453   /* Clean up.  */
1454   obstack_free (&insn_link_obstack, NULL);
1455   free (uid_log_links);
1456   free (uid_insn_cost);
1457   reg_stat.release ();
1458
1459   {
1460     struct undo *undo, *next;
1461     for (undo = undobuf.frees; undo; undo = next)
1462       {
1463         next = undo->next;
1464         free (undo);
1465       }
1466     undobuf.frees = 0;
1467   }
1468
1469   total_attempts += combine_attempts;
1470   total_merges += combine_merges;
1471   total_extras += combine_extras;
1472   total_successes += combine_successes;
1473
1474   nonzero_sign_valid = 0;
1475   rtl_hooks = general_rtl_hooks;
1476
1477   /* Make recognizer allow volatile MEMs again.  */
1478   init_recog ();
1479
1480   return new_direct_jump_p;
1481 }
1482
1483 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1484
1485 static void
1486 init_reg_last (void)
1487 {
1488   unsigned int i;
1489   reg_stat_type *p;
1490
1491   FOR_EACH_VEC_ELT (reg_stat, i, p)
1492     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1493 }
1494 \f
1495 /* Set up any promoted values for incoming argument registers.  */
1496
1497 static void
1498 setup_incoming_promotions (rtx first)
1499 {
1500   tree arg;
1501   bool strictly_local = false;
1502
1503   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1504        arg = DECL_CHAIN (arg))
1505     {
1506       rtx x, reg = DECL_INCOMING_RTL (arg);
1507       int uns1, uns3;
1508       enum machine_mode mode1, mode2, mode3, mode4;
1509
1510       /* Only continue if the incoming argument is in a register.  */
1511       if (!REG_P (reg))
1512         continue;
1513
1514       /* Determine, if possible, whether all call sites of the current
1515          function lie within the current compilation unit.  (This does
1516          take into account the exporting of a function via taking its
1517          address, and so forth.)  */
1518       strictly_local = cgraph_local_info (current_function_decl)->local;
1519
1520       /* The mode and signedness of the argument before any promotions happen
1521          (equal to the mode of the pseudo holding it at that stage).  */
1522       mode1 = TYPE_MODE (TREE_TYPE (arg));
1523       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1524
1525       /* The mode and signedness of the argument after any source language and
1526          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1527       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1528       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1529
1530       /* The mode and signedness of the argument as it is actually passed,
1531          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1532       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1533                                      TREE_TYPE (cfun->decl), 0);
1534
1535       /* The mode of the register in which the argument is being passed.  */
1536       mode4 = GET_MODE (reg);
1537
1538       /* Eliminate sign extensions in the callee when:
1539          (a) A mode promotion has occurred;  */
1540       if (mode1 == mode3)
1541         continue;
1542       /* (b) The mode of the register is the same as the mode of
1543              the argument as it is passed; */
1544       if (mode3 != mode4)
1545         continue;
1546       /* (c) There's no language level extension;  */
1547       if (mode1 == mode2)
1548         ;
1549       /* (c.1) All callers are from the current compilation unit.  If that's
1550          the case we don't have to rely on an ABI, we only have to know
1551          what we're generating right now, and we know that we will do the
1552          mode1 to mode2 promotion with the given sign.  */
1553       else if (!strictly_local)
1554         continue;
1555       /* (c.2) The combination of the two promotions is useful.  This is
1556          true when the signs match, or if the first promotion is unsigned.
1557          In the later case, (sign_extend (zero_extend x)) is the same as
1558          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1559       else if (uns1)
1560         uns3 = true;
1561       else if (uns3)
1562         continue;
1563
1564       /* Record that the value was promoted from mode1 to mode3,
1565          so that any sign extension at the head of the current
1566          function may be eliminated.  */
1567       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1568       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1569       record_value_for_reg (reg, first, x);
1570     }
1571 }
1572
1573 /* Called via note_stores.  If X is a pseudo that is narrower than
1574    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575
1576    If we are setting only a portion of X and we can't figure out what
1577    portion, assume all bits will be used since we don't know what will
1578    be happening.
1579
1580    Similarly, set how many bits of X are known to be copies of the sign bit
1581    at all locations in the function.  This is the smallest number implied
1582    by any set of X.  */
1583
1584 static void
1585 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1586 {
1587   rtx insn = (rtx) data;
1588   unsigned int num;
1589
1590   if (REG_P (x)
1591       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1592       /* If this register is undefined at the start of the file, we can't
1593          say what its contents were.  */
1594       && ! REGNO_REG_SET_P
1595            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1596       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1597     {
1598       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1599
1600       if (set == 0 || GET_CODE (set) == CLOBBER)
1601         {
1602           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1603           rsp->sign_bit_copies = 1;
1604           return;
1605         }
1606
1607       /* If this register is being initialized using itself, and the
1608          register is uninitialized in this basic block, and there are
1609          no LOG_LINKS which set the register, then part of the
1610          register is uninitialized.  In that case we can't assume
1611          anything about the number of nonzero bits.
1612
1613          ??? We could do better if we checked this in
1614          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1615          could avoid making assumptions about the insn which initially
1616          sets the register, while still using the information in other
1617          insns.  We would have to be careful to check every insn
1618          involved in the combination.  */
1619
1620       if (insn
1621           && reg_referenced_p (x, PATTERN (insn))
1622           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1623                                REGNO (x)))
1624         {
1625           struct insn_link *link;
1626
1627           FOR_EACH_LOG_LINK (link, insn)
1628             if (dead_or_set_p (link->insn, x))
1629               break;
1630           if (!link)
1631             {
1632               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1633               rsp->sign_bit_copies = 1;
1634               return;
1635             }
1636         }
1637
1638       /* If this is a complex assignment, see if we can convert it into a
1639          simple assignment.  */
1640       set = expand_field_assignment (set);
1641
1642       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1643          set what we know about X.  */
1644
1645       if (SET_DEST (set) == x
1646           || (paradoxical_subreg_p (SET_DEST (set))
1647               && SUBREG_REG (SET_DEST (set)) == x))
1648         {
1649           rtx src = SET_SRC (set);
1650
1651 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1652           /* If X is narrower than a word and SRC is a non-negative
1653              constant that would appear negative in the mode of X,
1654              sign-extend it for use in reg_stat[].nonzero_bits because some
1655              machines (maybe most) will actually do the sign-extension
1656              and this is the conservative approach.
1657
1658              ??? For 2.5, try to tighten up the MD files in this regard
1659              instead of this kludge.  */
1660
1661           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1662               && CONST_INT_P (src)
1663               && INTVAL (src) > 0
1664               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1665             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1666 #endif
1667
1668           /* Don't call nonzero_bits if it cannot change anything.  */
1669           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1670             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1671           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1672           if (rsp->sign_bit_copies == 0
1673               || rsp->sign_bit_copies > num)
1674             rsp->sign_bit_copies = num;
1675         }
1676       else
1677         {
1678           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1679           rsp->sign_bit_copies = 1;
1680         }
1681     }
1682 }
1683 \f
1684 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1685    optionally insns that were previously combined into I3 or that will be
1686    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1687    INSN, SUCC, SUCC2, I3.
1688
1689    Return 0 if the combination is not allowed for any reason.
1690
1691    If the combination is allowed, *PDEST will be set to the single
1692    destination of INSN and *PSRC to the single source, and this function
1693    will return 1.  */
1694
1695 static int
1696 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1697                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1698                rtx *pdest, rtx *psrc)
1699 {
1700   int i;
1701   const_rtx set = 0;
1702   rtx src, dest;
1703   rtx p;
1704 #ifdef AUTO_INC_DEC
1705   rtx link;
1706 #endif
1707   bool all_adjacent = true;
1708   int (*is_volatile_p) (const_rtx);
1709
1710   if (succ)
1711     {
1712       if (succ2)
1713         {
1714           if (next_active_insn (succ2) != i3)
1715             all_adjacent = false;
1716           if (next_active_insn (succ) != succ2)
1717             all_adjacent = false;
1718         }
1719       else if (next_active_insn (succ) != i3)
1720         all_adjacent = false;
1721       if (next_active_insn (insn) != succ)
1722         all_adjacent = false;
1723     }
1724   else if (next_active_insn (insn) != i3)
1725     all_adjacent = false;
1726
1727   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1728      or a PARALLEL consisting of such a SET and CLOBBERs.
1729
1730      If INSN has CLOBBER parallel parts, ignore them for our processing.
1731      By definition, these happen during the execution of the insn.  When it
1732      is merged with another insn, all bets are off.  If they are, in fact,
1733      needed and aren't also supplied in I3, they may be added by
1734      recog_for_combine.  Otherwise, it won't match.
1735
1736      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1737      note.
1738
1739      Get the source and destination of INSN.  If more than one, can't
1740      combine.  */
1741
1742   if (GET_CODE (PATTERN (insn)) == SET)
1743     set = PATTERN (insn);
1744   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1745            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1746     {
1747       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1748         {
1749           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1750
1751           switch (GET_CODE (elt))
1752             {
1753             /* This is important to combine floating point insns
1754                for the SH4 port.  */
1755             case USE:
1756               /* Combining an isolated USE doesn't make sense.
1757                  We depend here on combinable_i3pat to reject them.  */
1758               /* The code below this loop only verifies that the inputs of
1759                  the SET in INSN do not change.  We call reg_set_between_p
1760                  to verify that the REG in the USE does not change between
1761                  I3 and INSN.
1762                  If the USE in INSN was for a pseudo register, the matching
1763                  insn pattern will likely match any register; combining this
1764                  with any other USE would only be safe if we knew that the
1765                  used registers have identical values, or if there was
1766                  something to tell them apart, e.g. different modes.  For
1767                  now, we forgo such complicated tests and simply disallow
1768                  combining of USES of pseudo registers with any other USE.  */
1769               if (REG_P (XEXP (elt, 0))
1770                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1771                 {
1772                   rtx i3pat = PATTERN (i3);
1773                   int i = XVECLEN (i3pat, 0) - 1;
1774                   unsigned int regno = REGNO (XEXP (elt, 0));
1775
1776                   do
1777                     {
1778                       rtx i3elt = XVECEXP (i3pat, 0, i);
1779
1780                       if (GET_CODE (i3elt) == USE
1781                           && REG_P (XEXP (i3elt, 0))
1782                           && (REGNO (XEXP (i3elt, 0)) == regno
1783                               ? reg_set_between_p (XEXP (elt, 0),
1784                                                    PREV_INSN (insn), i3)
1785                               : regno >= FIRST_PSEUDO_REGISTER))
1786                         return 0;
1787                     }
1788                   while (--i >= 0);
1789                 }
1790               break;
1791
1792               /* We can ignore CLOBBERs.  */
1793             case CLOBBER:
1794               break;
1795
1796             case SET:
1797               /* Ignore SETs whose result isn't used but not those that
1798                  have side-effects.  */
1799               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1800                   && insn_nothrow_p (insn)
1801                   && !side_effects_p (elt))
1802                 break;
1803
1804               /* If we have already found a SET, this is a second one and
1805                  so we cannot combine with this insn.  */
1806               if (set)
1807                 return 0;
1808
1809               set = elt;
1810               break;
1811
1812             default:
1813               /* Anything else means we can't combine.  */
1814               return 0;
1815             }
1816         }
1817
1818       if (set == 0
1819           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1820              so don't do anything with it.  */
1821           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1822         return 0;
1823     }
1824   else
1825     return 0;
1826
1827   if (set == 0)
1828     return 0;
1829
1830   /* The simplification in expand_field_assignment may call back to
1831      get_last_value, so set safe guard here.  */
1832   subst_low_luid = DF_INSN_LUID (insn);
1833
1834   set = expand_field_assignment (set);
1835   src = SET_SRC (set), dest = SET_DEST (set);
1836
1837   /* Don't eliminate a store in the stack pointer.  */
1838   if (dest == stack_pointer_rtx
1839       /* Don't combine with an insn that sets a register to itself if it has
1840          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1841       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1842       /* Can't merge an ASM_OPERANDS.  */
1843       || GET_CODE (src) == ASM_OPERANDS
1844       /* Can't merge a function call.  */
1845       || GET_CODE (src) == CALL
1846       /* Don't eliminate a function call argument.  */
1847       || (CALL_P (i3)
1848           && (find_reg_fusage (i3, USE, dest)
1849               || (REG_P (dest)
1850                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1851                   && global_regs[REGNO (dest)])))
1852       /* Don't substitute into an incremented register.  */
1853       || FIND_REG_INC_NOTE (i3, dest)
1854       || (succ && FIND_REG_INC_NOTE (succ, dest))
1855       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1856       /* Don't substitute into a non-local goto, this confuses CFG.  */
1857       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1858       /* Make sure that DEST is not used after SUCC but before I3.  */
1859       || (!all_adjacent
1860           && ((succ2
1861                && (reg_used_between_p (dest, succ2, i3)
1862                    || reg_used_between_p (dest, succ, succ2)))
1863               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1864       /* Make sure that the value that is to be substituted for the register
1865          does not use any registers whose values alter in between.  However,
1866          If the insns are adjacent, a use can't cross a set even though we
1867          think it might (this can happen for a sequence of insns each setting
1868          the same destination; last_set of that register might point to
1869          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1870          equivalent to the memory so the substitution is valid even if there
1871          are intervening stores.  Also, don't move a volatile asm or
1872          UNSPEC_VOLATILE across any other insns.  */
1873       || (! all_adjacent
1874           && (((!MEM_P (src)
1875                 || ! find_reg_note (insn, REG_EQUIV, src))
1876                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1877               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1878               || GET_CODE (src) == UNSPEC_VOLATILE))
1879       /* Don't combine across a CALL_INSN, because that would possibly
1880          change whether the life span of some REGs crosses calls or not,
1881          and it is a pain to update that information.
1882          Exception: if source is a constant, moving it later can't hurt.
1883          Accept that as a special case.  */
1884       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1885     return 0;
1886
1887   /* DEST must either be a REG or CC0.  */
1888   if (REG_P (dest))
1889     {
1890       /* If register alignment is being enforced for multi-word items in all
1891          cases except for parameters, it is possible to have a register copy
1892          insn referencing a hard register that is not allowed to contain the
1893          mode being copied and which would not be valid as an operand of most
1894          insns.  Eliminate this problem by not combining with such an insn.
1895
1896          Also, on some machines we don't want to extend the life of a hard
1897          register.  */
1898
1899       if (REG_P (src)
1900           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1901                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1902               /* Don't extend the life of a hard register unless it is
1903                  user variable (if we have few registers) or it can't
1904                  fit into the desired register (meaning something special
1905                  is going on).
1906                  Also avoid substituting a return register into I3, because
1907                  reload can't handle a conflict with constraints of other
1908                  inputs.  */
1909               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1910                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1911         return 0;
1912     }
1913   else if (GET_CODE (dest) != CC0)
1914     return 0;
1915
1916
1917   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1918     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1919       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1920         {
1921           /* Don't substitute for a register intended as a clobberable
1922              operand.  */
1923           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1924           if (rtx_equal_p (reg, dest))
1925             return 0;
1926
1927           /* If the clobber represents an earlyclobber operand, we must not
1928              substitute an expression containing the clobbered register.
1929              As we do not analyze the constraint strings here, we have to
1930              make the conservative assumption.  However, if the register is
1931              a fixed hard reg, the clobber cannot represent any operand;
1932              we leave it up to the machine description to either accept or
1933              reject use-and-clobber patterns.  */
1934           if (!REG_P (reg)
1935               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1936               || !fixed_regs[REGNO (reg)])
1937             if (reg_overlap_mentioned_p (reg, src))
1938               return 0;
1939         }
1940
1941   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1942      or not), reject, unless nothing volatile comes between it and I3 */
1943
1944   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1945     {
1946       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1947       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1948         return 0;
1949       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1950         return 0;
1951       /* We'll check insns between INSN and I3 below.  */
1952     }
1953
1954   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1955      to be an explicit register variable, and was chosen for a reason.  */
1956
1957   if (GET_CODE (src) == ASM_OPERANDS
1958       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1959     return 0;
1960
1961   /* If INSN contains volatile references (specifically volatile MEMs),
1962      we cannot combine across any other volatile references.
1963      Even if INSN doesn't contain volatile references, any intervening
1964      volatile insn might affect machine state.  */
1965
1966   is_volatile_p = volatile_refs_p (PATTERN (insn))
1967     ? volatile_refs_p
1968     : volatile_insn_p;
1969
1970   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1971     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1972       return 0;
1973
1974   /* If INSN contains an autoincrement or autodecrement, make sure that
1975      register is not used between there and I3, and not already used in
1976      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1977      Also insist that I3 not be a jump; if it were one
1978      and the incremented register were spilled, we would lose.  */
1979
1980 #ifdef AUTO_INC_DEC
1981   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1982     if (REG_NOTE_KIND (link) == REG_INC
1983         && (JUMP_P (i3)
1984             || reg_used_between_p (XEXP (link, 0), insn, i3)
1985             || (pred != NULL_RTX
1986                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1987             || (pred2 != NULL_RTX
1988                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1989             || (succ != NULL_RTX
1990                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1991             || (succ2 != NULL_RTX
1992                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1993             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1994       return 0;
1995 #endif
1996
1997 #ifdef HAVE_cc0
1998   /* Don't combine an insn that follows a CC0-setting insn.
1999      An insn that uses CC0 must not be separated from the one that sets it.
2000      We do, however, allow I2 to follow a CC0-setting insn if that insn
2001      is passed as I1; in that case it will be deleted also.
2002      We also allow combining in this case if all the insns are adjacent
2003      because that would leave the two CC0 insns adjacent as well.
2004      It would be more logical to test whether CC0 occurs inside I1 or I2,
2005      but that would be much slower, and this ought to be equivalent.  */
2006
2007   p = prev_nonnote_insn (insn);
2008   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2009       && ! all_adjacent)
2010     return 0;
2011 #endif
2012
2013   /* If we get here, we have passed all the tests and the combination is
2014      to be allowed.  */
2015
2016   *pdest = dest;
2017   *psrc = src;
2018
2019   return 1;
2020 }
2021 \f
2022 /* LOC is the location within I3 that contains its pattern or the component
2023    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2024
2025    One problem is if I3 modifies its output, as opposed to replacing it
2026    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2027    doing so would produce an insn that is not equivalent to the original insns.
2028
2029    Consider:
2030
2031          (set (reg:DI 101) (reg:DI 100))
2032          (set (subreg:SI (reg:DI 101) 0) <foo>)
2033
2034    This is NOT equivalent to:
2035
2036          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2037                     (set (reg:DI 101) (reg:DI 100))])
2038
2039    Not only does this modify 100 (in which case it might still be valid
2040    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041
2042    We can also run into a problem if I2 sets a register that I1
2043    uses and I1 gets directly substituted into I3 (not via I2).  In that
2044    case, we would be getting the wrong value of I2DEST into I3, so we
2045    must reject the combination.  This case occurs when I2 and I1 both
2046    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2047    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2048    of a SET must prevent combination from occurring.  The same situation
2049    can occur for I0, in which case I0_NOT_IN_SRC is set.
2050
2051    Before doing the above check, we first try to expand a field assignment
2052    into a set of logical operations.
2053
2054    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2055    we place a register that is both set and used within I3.  If more than one
2056    such register is detected, we fail.
2057
2058    Return 1 if the combination is valid, zero otherwise.  */
2059
2060 static int
2061 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2062                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2063 {
2064   rtx x = *loc;
2065
2066   if (GET_CODE (x) == SET)
2067     {
2068       rtx set = x ;
2069       rtx dest = SET_DEST (set);
2070       rtx src = SET_SRC (set);
2071       rtx inner_dest = dest;
2072       rtx subdest;
2073
2074       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2075              || GET_CODE (inner_dest) == SUBREG
2076              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2077         inner_dest = XEXP (inner_dest, 0);
2078
2079       /* Check for the case where I3 modifies its output, as discussed
2080          above.  We don't want to prevent pseudos from being combined
2081          into the address of a MEM, so only prevent the combination if
2082          i1 or i2 set the same MEM.  */
2083       if ((inner_dest != dest &&
2084            (!MEM_P (inner_dest)
2085             || rtx_equal_p (i2dest, inner_dest)
2086             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2087             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2088            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2089                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2090                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2091
2092           /* This is the same test done in can_combine_p except we can't test
2093              all_adjacent; we don't have to, since this instruction will stay
2094              in place, thus we are not considering increasing the lifetime of
2095              INNER_DEST.
2096
2097              Also, if this insn sets a function argument, combining it with
2098              something that might need a spill could clobber a previous
2099              function argument; the all_adjacent test in can_combine_p also
2100              checks this; here, we do a more specific test for this case.  */
2101
2102           || (REG_P (inner_dest)
2103               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2104               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2105                                         GET_MODE (inner_dest))))
2106           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2107           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2108         return 0;
2109
2110       /* If DEST is used in I3, it is being killed in this insn, so
2111          record that for later.  We have to consider paradoxical
2112          subregs here, since they kill the whole register, but we
2113          ignore partial subregs, STRICT_LOW_PART, etc.
2114          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2115          STACK_POINTER_REGNUM, since these are always considered to be
2116          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2117       subdest = dest;
2118       if (GET_CODE (subdest) == SUBREG
2119           && (GET_MODE_SIZE (GET_MODE (subdest))
2120               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2121         subdest = SUBREG_REG (subdest);
2122       if (pi3dest_killed
2123           && REG_P (subdest)
2124           && reg_referenced_p (subdest, PATTERN (i3))
2125           && REGNO (subdest) != FRAME_POINTER_REGNUM
2126 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2127           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2128 #endif
2129 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2130           && (REGNO (subdest) != ARG_POINTER_REGNUM
2131               || ! fixed_regs [REGNO (subdest)])
2132 #endif
2133           && REGNO (subdest) != STACK_POINTER_REGNUM)
2134         {
2135           if (*pi3dest_killed)
2136             return 0;
2137
2138           *pi3dest_killed = subdest;
2139         }
2140     }
2141
2142   else if (GET_CODE (x) == PARALLEL)
2143     {
2144       int i;
2145
2146       for (i = 0; i < XVECLEN (x, 0); i++)
2147         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2148                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2149           return 0;
2150     }
2151
2152   return 1;
2153 }
2154 \f
2155 /* Return 1 if X is an arithmetic expression that contains a multiplication
2156    and division.  We don't count multiplications by powers of two here.  */
2157
2158 static int
2159 contains_muldiv (rtx x)
2160 {
2161   switch (GET_CODE (x))
2162     {
2163     case MOD:  case DIV:  case UMOD:  case UDIV:
2164       return 1;
2165
2166     case MULT:
2167       return ! (CONST_INT_P (XEXP (x, 1))
2168                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2169     default:
2170       if (BINARY_P (x))
2171         return contains_muldiv (XEXP (x, 0))
2172             || contains_muldiv (XEXP (x, 1));
2173
2174       if (UNARY_P (x))
2175         return contains_muldiv (XEXP (x, 0));
2176
2177       return 0;
2178     }
2179 }
2180 \f
2181 /* Determine whether INSN can be used in a combination.  Return nonzero if
2182    not.  This is used in try_combine to detect early some cases where we
2183    can't perform combinations.  */
2184
2185 static int
2186 cant_combine_insn_p (rtx insn)
2187 {
2188   rtx set;
2189   rtx src, dest;
2190
2191   /* If this isn't really an insn, we can't do anything.
2192      This can occur when flow deletes an insn that it has merged into an
2193      auto-increment address.  */
2194   if (! INSN_P (insn))
2195     return 1;
2196
2197   /* Never combine loads and stores involving hard regs that are likely
2198      to be spilled.  The register allocator can usually handle such
2199      reg-reg moves by tying.  If we allow the combiner to make
2200      substitutions of likely-spilled regs, reload might die.
2201      As an exception, we allow combinations involving fixed regs; these are
2202      not available to the register allocator so there's no risk involved.  */
2203
2204   set = single_set (insn);
2205   if (! set)
2206     return 0;
2207   src = SET_SRC (set);
2208   dest = SET_DEST (set);
2209   if (GET_CODE (src) == SUBREG)
2210     src = SUBREG_REG (src);
2211   if (GET_CODE (dest) == SUBREG)
2212     dest = SUBREG_REG (dest);
2213   if (REG_P (src) && REG_P (dest)
2214       && ((HARD_REGISTER_P (src)
2215            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2216            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2217           || (HARD_REGISTER_P (dest)
2218               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2219               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2220     return 1;
2221
2222   return 0;
2223 }
2224
2225 struct likely_spilled_retval_info
2226 {
2227   unsigned regno, nregs;
2228   unsigned mask;
2229 };
2230
2231 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2232    hard registers that are known to be written to / clobbered in full.  */
2233 static void
2234 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2235 {
2236   struct likely_spilled_retval_info *const info =
2237     (struct likely_spilled_retval_info *) data;
2238   unsigned regno, nregs;
2239   unsigned new_mask;
2240
2241   if (!REG_P (XEXP (set, 0)))
2242     return;
2243   regno = REGNO (x);
2244   if (regno >= info->regno + info->nregs)
2245     return;
2246   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2247   if (regno + nregs <= info->regno)
2248     return;
2249   new_mask = (2U << (nregs - 1)) - 1;
2250   if (regno < info->regno)
2251     new_mask >>= info->regno - regno;
2252   else
2253     new_mask <<= regno - info->regno;
2254   info->mask &= ~new_mask;
2255 }
2256
2257 /* Return nonzero iff part of the return value is live during INSN, and
2258    it is likely spilled.  This can happen when more than one insn is needed
2259    to copy the return value, e.g. when we consider to combine into the
2260    second copy insn for a complex value.  */
2261
2262 static int
2263 likely_spilled_retval_p (rtx insn)
2264 {
2265   rtx use = BB_END (this_basic_block);
2266   rtx reg, p;
2267   unsigned regno, nregs;
2268   /* We assume here that no machine mode needs more than
2269      32 hard registers when the value overlaps with a register
2270      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2271   unsigned mask;
2272   struct likely_spilled_retval_info info;
2273
2274   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2275     return 0;
2276   reg = XEXP (PATTERN (use), 0);
2277   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2278     return 0;
2279   regno = REGNO (reg);
2280   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2281   if (nregs == 1)
2282     return 0;
2283   mask = (2U << (nregs - 1)) - 1;
2284
2285   /* Disregard parts of the return value that are set later.  */
2286   info.regno = regno;
2287   info.nregs = nregs;
2288   info.mask = mask;
2289   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2290     if (INSN_P (p))
2291       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2292   mask = info.mask;
2293
2294   /* Check if any of the (probably) live return value registers is
2295      likely spilled.  */
2296   nregs --;
2297   do
2298     {
2299       if ((mask & 1 << nregs)
2300           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2301         return 1;
2302     } while (nregs--);
2303   return 0;
2304 }
2305
2306 /* Adjust INSN after we made a change to its destination.
2307
2308    Changing the destination can invalidate notes that say something about
2309    the results of the insn and a LOG_LINK pointing to the insn.  */
2310
2311 static void
2312 adjust_for_new_dest (rtx insn)
2313 {
2314   /* For notes, be conservative and simply remove them.  */
2315   remove_reg_equal_equiv_notes (insn);
2316
2317   /* The new insn will have a destination that was previously the destination
2318      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2319      the next use of that destination.  */
2320   distribute_links (alloc_insn_link (insn, NULL));
2321
2322   df_insn_rescan (insn);
2323 }
2324
2325 /* Return TRUE if combine can reuse reg X in mode MODE.
2326    ADDED_SETS is nonzero if the original set is still required.  */
2327 static bool
2328 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2329 {
2330   unsigned int regno;
2331
2332   if (!REG_P (x))
2333     return false;
2334
2335   regno = REGNO (x);
2336   /* Allow hard registers if the new mode is legal, and occupies no more
2337      registers than the old mode.  */
2338   if (regno < FIRST_PSEUDO_REGISTER)
2339     return (HARD_REGNO_MODE_OK (regno, mode)
2340             && (hard_regno_nregs[regno][GET_MODE (x)]
2341                 >= hard_regno_nregs[regno][mode]));
2342
2343   /* Or a pseudo that is only used once.  */
2344   return (REG_N_SETS (regno) == 1 && !added_sets
2345           && !REG_USERVAR_P (x));
2346 }
2347
2348
2349 /* Check whether X, the destination of a set, refers to part of
2350    the register specified by REG.  */
2351
2352 static bool
2353 reg_subword_p (rtx x, rtx reg)
2354 {
2355   /* Check that reg is an integer mode register.  */
2356   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2357     return false;
2358
2359   if (GET_CODE (x) == STRICT_LOW_PART
2360       || GET_CODE (x) == ZERO_EXTRACT)
2361     x = XEXP (x, 0);
2362
2363   return GET_CODE (x) == SUBREG
2364          && SUBREG_REG (x) == reg
2365          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2366 }
2367
2368 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2369    Note that the INSN should be deleted *after* removing dead edges, so
2370    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2371    but not for a (set (pc) (label_ref FOO)).  */
2372
2373 static void
2374 update_cfg_for_uncondjump (rtx insn)
2375 {
2376   basic_block bb = BLOCK_FOR_INSN (insn);
2377   gcc_assert (BB_END (bb) == insn);
2378
2379   purge_dead_edges (bb);
2380
2381   delete_insn (insn);
2382   if (EDGE_COUNT (bb->succs) == 1)
2383     {
2384       rtx insn;
2385
2386       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2387
2388       /* Remove barriers from the footer if there are any.  */
2389       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2390         if (BARRIER_P (insn))
2391           {
2392             if (PREV_INSN (insn))
2393               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2394             else
2395               BB_FOOTER (bb) = NEXT_INSN (insn);
2396             if (NEXT_INSN (insn))
2397               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2398           }
2399         else if (LABEL_P (insn))
2400           break;
2401     }
2402 }
2403
2404 /* Try to combine the insns I0, I1 and I2 into I3.
2405    Here I0, I1 and I2 appear earlier than I3.
2406    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2407    I3.
2408
2409    If we are combining more than two insns and the resulting insn is not
2410    recognized, try splitting it into two insns.  If that happens, I2 and I3
2411    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2412    Otherwise, I0, I1 and I2 are pseudo-deleted.
2413
2414    Return 0 if the combination does not work.  Then nothing is changed.
2415    If we did the combination, return the insn at which combine should
2416    resume scanning.
2417
2418    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2419    new direct jump instruction.
2420
2421    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2422    been I3 passed to an earlier try_combine within the same basic
2423    block.  */
2424
2425 static rtx
2426 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2427              rtx last_combined_insn)
2428 {
2429   /* New patterns for I3 and I2, respectively.  */
2430   rtx newpat, newi2pat = 0;
2431   rtvec newpat_vec_with_clobbers = 0;
2432   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2433   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434      dead.  */
2435   int added_sets_0, added_sets_1, added_sets_2;
2436   /* Total number of SETs to put into I3.  */
2437   int total_sets;
2438   /* Nonzero if I2's or I1's body now appears in I3.  */
2439   int i2_is_used = 0, i1_is_used = 0;
2440   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2441   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2442   /* Contains I3 if the destination of I3 is used in its source, which means
2443      that the old life of I3 is being killed.  If that usage is placed into
2444      I2 and not in I3, a REG_DEAD note must be made.  */
2445   rtx i3dest_killed = 0;
2446   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2447   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2448   /* Copy of SET_SRC of I1 and I0, if needed.  */
2449   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2450   /* Set if I2DEST was reused as a scratch register.  */
2451   bool i2scratch = false;
2452   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2453   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2454   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2455   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2456   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2457   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2458   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2459   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2460   rtx new_i3_notes, new_i2_notes;
2461   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2462   int i3_subst_into_i2 = 0;
2463   /* Notes that I1, I2 or I3 is a MULT operation.  */
2464   int have_mult = 0;
2465   int swap_i2i3 = 0;
2466   int changed_i3_dest = 0;
2467
2468   int maxreg;
2469   rtx temp;
2470   struct insn_link *link;
2471   rtx other_pat = 0;
2472   rtx new_other_notes;
2473   int i;
2474
2475   /* Only try four-insn combinations when there's high likelihood of
2476      success.  Look for simple insns, such as loads of constants or
2477      binary operations involving a constant.  */
2478   if (i0)
2479     {
2480       int i;
2481       int ngood = 0;
2482       int nshift = 0;
2483
2484       if (!flag_expensive_optimizations)
2485         return 0;
2486
2487       for (i = 0; i < 4; i++)
2488         {
2489           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2490           rtx set = single_set (insn);
2491           rtx src;
2492           if (!set)
2493             continue;
2494           src = SET_SRC (set);
2495           if (CONSTANT_P (src))
2496             {
2497               ngood += 2;
2498               break;
2499             }
2500           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2501             ngood++;
2502           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2503                    || GET_CODE (src) == LSHIFTRT)
2504             nshift++;
2505         }
2506       if (ngood < 2 && nshift < 2)
2507         return 0;
2508     }
2509
2510   /* Exit early if one of the insns involved can't be used for
2511      combinations.  */
2512   if (cant_combine_insn_p (i3)
2513       || cant_combine_insn_p (i2)
2514       || (i1 && cant_combine_insn_p (i1))
2515       || (i0 && cant_combine_insn_p (i0))
2516       || likely_spilled_retval_p (i3))
2517     return 0;
2518
2519   combine_attempts++;
2520   undobuf.other_insn = 0;
2521
2522   /* Reset the hard register usage information.  */
2523   CLEAR_HARD_REG_SET (newpat_used_regs);
2524
2525   if (dump_file && (dump_flags & TDF_DETAILS))
2526     {
2527       if (i0)
2528         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2529                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2530       else if (i1)
2531         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2532                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2533       else
2534         fprintf (dump_file, "\nTrying %d -> %d:\n",
2535                  INSN_UID (i2), INSN_UID (i3));
2536     }
2537
2538   /* If multiple insns feed into one of I2 or I3, they can be in any
2539      order.  To simplify the code below, reorder them in sequence.  */
2540   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2541     temp = i2, i2 = i0, i0 = temp;
2542   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2543     temp = i1, i1 = i0, i0 = temp;
2544   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2545     temp = i1, i1 = i2, i2 = temp;
2546
2547   added_links_insn = 0;
2548
2549   /* First check for one important special case that the code below will
2550      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2551      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2552      we may be able to replace that destination with the destination of I3.
2553      This occurs in the common code where we compute both a quotient and
2554      remainder into a structure, in which case we want to do the computation
2555      directly into the structure to avoid register-register copies.
2556
2557      Note that this case handles both multiple sets in I2 and also cases
2558      where I2 has a number of CLOBBERs inside the PARALLEL.
2559
2560      We make very conservative checks below and only try to handle the
2561      most common cases of this.  For example, we only handle the case
2562      where I2 and I3 are adjacent to avoid making difficult register
2563      usage tests.  */
2564
2565   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2566       && REG_P (SET_SRC (PATTERN (i3)))
2567       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2568       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2569       && GET_CODE (PATTERN (i2)) == PARALLEL
2570       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2571       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2572          below would need to check what is inside (and reg_overlap_mentioned_p
2573          doesn't support those codes anyway).  Don't allow those destinations;
2574          the resulting insn isn't likely to be recognized anyway.  */
2575       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2576       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2577       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2578                                     SET_DEST (PATTERN (i3)))
2579       && next_active_insn (i2) == i3)
2580     {
2581       rtx p2 = PATTERN (i2);
2582
2583       /* Make sure that the destination of I3,
2584          which we are going to substitute into one output of I2,
2585          is not used within another output of I2.  We must avoid making this:
2586          (parallel [(set (mem (reg 69)) ...)
2587                     (set (reg 69) ...)])
2588          which is not well-defined as to order of actions.
2589          (Besides, reload can't handle output reloads for this.)
2590
2591          The problem can also happen if the dest of I3 is a memory ref,
2592          if another dest in I2 is an indirect memory ref.  */
2593       for (i = 0; i < XVECLEN (p2, 0); i++)
2594         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2595              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2596             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2597                                         SET_DEST (XVECEXP (p2, 0, i))))
2598           break;
2599
2600       if (i == XVECLEN (p2, 0))
2601         for (i = 0; i < XVECLEN (p2, 0); i++)
2602           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2603               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2604             {
2605               combine_merges++;
2606
2607               subst_insn = i3;
2608               subst_low_luid = DF_INSN_LUID (i2);
2609
2610               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2611               i2src = SET_SRC (XVECEXP (p2, 0, i));
2612               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2613               i2dest_killed = dead_or_set_p (i2, i2dest);
2614
2615               /* Replace the dest in I2 with our dest and make the resulting
2616                  insn the new pattern for I3.  Then skip to where we validate
2617                  the pattern.  Everything was set up above.  */
2618               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2619               newpat = p2;
2620               i3_subst_into_i2 = 1;
2621               goto validate_replacement;
2622             }
2623     }
2624
2625   /* If I2 is setting a pseudo to a constant and I3 is setting some
2626      sub-part of it to another constant, merge them by making a new
2627      constant.  */
2628   if (i1 == 0
2629       && (temp = single_set (i2)) != 0
2630       && CONST_SCALAR_INT_P (SET_SRC (temp))
2631       && GET_CODE (PATTERN (i3)) == SET
2632       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2633       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2634     {
2635       rtx dest = SET_DEST (PATTERN (i3));
2636       int offset = -1;
2637       int width = 0;
2638
2639       if (GET_CODE (dest) == ZERO_EXTRACT)
2640         {
2641           if (CONST_INT_P (XEXP (dest, 1))
2642               && CONST_INT_P (XEXP (dest, 2)))
2643             {
2644               width = INTVAL (XEXP (dest, 1));
2645               offset = INTVAL (XEXP (dest, 2));
2646               dest = XEXP (dest, 0);
2647               if (BITS_BIG_ENDIAN)
2648                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2649             }
2650         }
2651       else
2652         {
2653           if (GET_CODE (dest) == STRICT_LOW_PART)
2654             dest = XEXP (dest, 0);
2655           width = GET_MODE_PRECISION (GET_MODE (dest));
2656           offset = 0;
2657         }
2658
2659       if (offset >= 0)
2660         {
2661           /* If this is the low part, we're done.  */
2662           if (subreg_lowpart_p (dest))
2663             ;
2664           /* Handle the case where inner is twice the size of outer.  */
2665           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2666                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2667             offset += GET_MODE_PRECISION (GET_MODE (dest));
2668           /* Otherwise give up for now.  */
2669           else
2670             offset = -1;
2671         }
2672
2673       if (offset >= 0
2674           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2675               <= HOST_BITS_PER_DOUBLE_INT))
2676         {
2677           double_int m, o, i;
2678           rtx inner = SET_SRC (PATTERN (i3));
2679           rtx outer = SET_SRC (temp);
2680
2681           o = rtx_to_double_int (outer);
2682           i = rtx_to_double_int (inner);
2683
2684           m = double_int::mask (width);
2685           i &= m;
2686           m = m.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2687           i = i.llshift (offset, HOST_BITS_PER_DOUBLE_INT);
2688           o = o.and_not (m) | i;
2689
2690           combine_merges++;
2691           subst_insn = i3;
2692           subst_low_luid = DF_INSN_LUID (i2);
2693           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2694           i2dest = SET_DEST (temp);
2695           i2dest_killed = dead_or_set_p (i2, i2dest);
2696
2697           /* Replace the source in I2 with the new constant and make the
2698              resulting insn the new pattern for I3.  Then skip to where we
2699              validate the pattern.  Everything was set up above.  */
2700           SUBST (SET_SRC (temp),
2701                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2702
2703           newpat = PATTERN (i2);
2704
2705           /* The dest of I3 has been replaced with the dest of I2.  */
2706           changed_i3_dest = 1;
2707           goto validate_replacement;
2708         }
2709     }
2710
2711 #ifndef HAVE_cc0
2712   /* If we have no I1 and I2 looks like:
2713         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2714                    (set Y OP)])
2715      make up a dummy I1 that is
2716         (set Y OP)
2717      and change I2 to be
2718         (set (reg:CC X) (compare:CC Y (const_int 0)))
2719
2720      (We can ignore any trailing CLOBBERs.)
2721
2722      This undoes a previous combination and allows us to match a branch-and-
2723      decrement insn.  */
2724
2725   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2726       && XVECLEN (PATTERN (i2), 0) >= 2
2727       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2728       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2729           == MODE_CC)
2730       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2731       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2732       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2733       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2734       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2735                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2736     {
2737       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2738         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2739           break;
2740
2741       if (i == 1)
2742         {
2743           /* We make I1 with the same INSN_UID as I2.  This gives it
2744              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2745              never appear in the insn stream so giving it the same INSN_UID
2746              as I2 will not cause a problem.  */
2747
2748           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2749                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2750                              INSN_LOCATION (i2), -1, NULL_RTX);
2751
2752           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2753           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2754                  SET_DEST (PATTERN (i1)));
2755           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2756         }
2757     }
2758 #endif
2759
2760   /* Verify that I2 and I1 are valid for combining.  */
2761   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2762       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2763                                  &i1dest, &i1src))
2764       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2765                                  &i0dest, &i0src)))
2766     {
2767       undo_all ();
2768       return 0;
2769     }
2770
2771   /* Record whether I2DEST is used in I2SRC and similarly for the other
2772      cases.  Knowing this will help in register status updating below.  */
2773   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2774   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2775   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2776   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2777   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2778   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2779   i2dest_killed = dead_or_set_p (i2, i2dest);
2780   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2781   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2782
2783   /* For the earlier insns, determine which of the subsequent ones they
2784      feed.  */
2785   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2786   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2787   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2788                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2789                              && reg_overlap_mentioned_p (i0dest, i2src))));
2790
2791   /* Ensure that I3's pattern can be the destination of combines.  */
2792   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2793                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2794                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2795                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2796                           &i3dest_killed))
2797     {
2798       undo_all ();
2799       return 0;
2800     }
2801
2802   /* See if any of the insns is a MULT operation.  Unless one is, we will
2803      reject a combination that is, since it must be slower.  Be conservative
2804      here.  */
2805   if (GET_CODE (i2src) == MULT
2806       || (i1 != 0 && GET_CODE (i1src) == MULT)
2807       || (i0 != 0 && GET_CODE (i0src) == MULT)
2808       || (GET_CODE (PATTERN (i3)) == SET
2809           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2810     have_mult = 1;
2811
2812   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2813      We used to do this EXCEPT in one case: I3 has a post-inc in an
2814      output operand.  However, that exception can give rise to insns like
2815         mov r3,(r3)+
2816      which is a famous insn on the PDP-11 where the value of r3 used as the
2817      source was model-dependent.  Avoid this sort of thing.  */
2818
2819 #if 0
2820   if (!(GET_CODE (PATTERN (i3)) == SET
2821         && REG_P (SET_SRC (PATTERN (i3)))
2822         && MEM_P (SET_DEST (PATTERN (i3)))
2823         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2824             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2825     /* It's not the exception.  */
2826 #endif
2827 #ifdef AUTO_INC_DEC
2828     {
2829       rtx link;
2830       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2831         if (REG_NOTE_KIND (link) == REG_INC
2832             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2833                 || (i1 != 0
2834                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2835           {
2836             undo_all ();
2837             return 0;
2838           }
2839     }
2840 #endif
2841
2842   /* See if the SETs in I1 or I2 need to be kept around in the merged
2843      instruction: whenever the value set there is still needed past I3.
2844      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2845
2846      For the SET in I1, we have two cases: if I1 and I2 independently feed
2847      into I3, the set in I1 needs to be kept around unless I1DEST dies
2848      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2849      in I1 needs to be kept around unless I1DEST dies or is set in either
2850      I2 or I3.  The same considerations apply to I0.  */
2851
2852   added_sets_2 = !dead_or_set_p (i3, i2dest);
2853
2854   if (i1)
2855     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2856                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2857   else
2858     added_sets_1 = 0;
2859
2860   if (i0)
2861     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2862                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2863                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2864                           && dead_or_set_p (i2, i0dest)));
2865   else
2866     added_sets_0 = 0;
2867
2868   /* We are about to copy insns for the case where they need to be kept
2869      around.  Check that they can be copied in the merged instruction.  */
2870
2871   if (targetm.cannot_copy_insn_p
2872       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2873           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2874           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2875     {
2876       undo_all ();
2877       return 0;
2878     }
2879
2880   /* If the set in I2 needs to be kept around, we must make a copy of
2881      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2882      PATTERN (I2), we are only substituting for the original I1DEST, not into
2883      an already-substituted copy.  This also prevents making self-referential
2884      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2885      I2DEST.  */
2886
2887   if (added_sets_2)
2888     {
2889       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2890         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2891       else
2892         i2pat = copy_rtx (PATTERN (i2));
2893     }
2894
2895   if (added_sets_1)
2896     {
2897       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2898         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2899       else
2900         i1pat = copy_rtx (PATTERN (i1));
2901     }
2902
2903   if (added_sets_0)
2904     {
2905       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2906         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2907       else
2908         i0pat = copy_rtx (PATTERN (i0));
2909     }
2910
2911   combine_merges++;
2912
2913   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2914
2915   maxreg = max_reg_num ();
2916
2917   subst_insn = i3;
2918
2919 #ifndef HAVE_cc0
2920   /* Many machines that don't use CC0 have insns that can both perform an
2921      arithmetic operation and set the condition code.  These operations will
2922      be represented as a PARALLEL with the first element of the vector
2923      being a COMPARE of an arithmetic operation with the constant zero.
2924      The second element of the vector will set some pseudo to the result
2925      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2926      match such a pattern and so will generate an extra insn.   Here we test
2927      for this case, where both the comparison and the operation result are
2928      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2929      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2930
2931   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2932       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2933       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2934       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2935     {
2936       rtx newpat_dest;
2937       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
2938       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2939       enum machine_mode compare_mode, orig_compare_mode;
2940       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2941
2942       newpat = PATTERN (i3);
2943       newpat_dest = SET_DEST (newpat);
2944       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2945
2946       if (undobuf.other_insn == 0
2947           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2948                                             &cc_use_insn)))
2949         {
2950           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2951           compare_code = simplify_compare_const (compare_code,
2952                                                  op0, &op1);
2953           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2954         }
2955
2956       /* Do the rest only if op1 is const0_rtx, which may be the
2957          result of simplification.  */
2958       if (op1 == const0_rtx)
2959         {
2960           /* If a single use of the CC is found, prepare to modify it
2961              when SELECT_CC_MODE returns a new CC-class mode, or when
2962              the above simplify_compare_const() returned a new comparison
2963              operator.  undobuf.other_insn is assigned the CC use insn
2964              when modifying it.  */
2965           if (cc_use_loc)
2966             {
2967 #ifdef SELECT_CC_MODE
2968               enum machine_mode new_mode
2969                 = SELECT_CC_MODE (compare_code, op0, op1);
2970               if (new_mode != orig_compare_mode
2971                   && can_change_dest_mode (SET_DEST (newpat),
2972                                            added_sets_2, new_mode))
2973                 {
2974                   unsigned int regno = REGNO (newpat_dest);
2975                   compare_mode = new_mode;
2976                   if (regno < FIRST_PSEUDO_REGISTER)
2977                     newpat_dest = gen_rtx_REG (compare_mode, regno);
2978                   else
2979                     {
2980                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2981                       newpat_dest = regno_reg_rtx[regno];
2982                     }
2983                 }
2984 #endif
2985               /* Cases for modifying the CC-using comparison.  */
2986               if (compare_code != orig_compare_code
2987                   /* ??? Do we need to verify the zero rtx?  */
2988                   && XEXP (*cc_use_loc, 1) == const0_rtx)
2989                 {
2990                   /* Replace cc_use_loc with entire new RTX.  */
2991                   SUBST (*cc_use_loc,
2992                          gen_rtx_fmt_ee (compare_code, compare_mode,
2993                                          newpat_dest, const0_rtx));
2994                   undobuf.other_insn = cc_use_insn;
2995                 }
2996               else if (compare_mode != orig_compare_mode)
2997                 {
2998                   /* Just replace the CC reg with a new mode.  */
2999                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3000                   undobuf.other_insn = cc_use_insn;
3001                 }
3002             }
3003
3004           /* Now we modify the current newpat:
3005              First, SET_DEST(newpat) is updated if the CC mode has been
3006              altered. For targets without SELECT_CC_MODE, this should be
3007              optimized away.  */
3008           if (compare_mode != orig_compare_mode)
3009             SUBST (SET_DEST (newpat), newpat_dest);
3010           /* This is always done to propagate i2src into newpat.  */
3011           SUBST (SET_SRC (newpat),
3012                  gen_rtx_COMPARE (compare_mode, op0, op1));
3013           /* Create new version of i2pat if needed; the below PARALLEL
3014              creation needs this to work correctly.  */
3015           if (! rtx_equal_p (i2src, op0))
3016             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3017           i2_is_used = 1;
3018         }
3019     }
3020 #endif
3021
3022   if (i2_is_used == 0)
3023     {
3024       /* It is possible that the source of I2 or I1 may be performing
3025          an unneeded operation, such as a ZERO_EXTEND of something
3026          that is known to have the high part zero.  Handle that case
3027          by letting subst look at the inner insns.
3028
3029          Another way to do this would be to have a function that tries
3030          to simplify a single insn instead of merging two or more
3031          insns.  We don't do this because of the potential of infinite
3032          loops and because of the potential extra memory required.
3033          However, doing it the way we are is a bit of a kludge and
3034          doesn't catch all cases.
3035
3036          But only do this if -fexpensive-optimizations since it slows
3037          things down and doesn't usually win.
3038
3039          This is not done in the COMPARE case above because the
3040          unmodified I2PAT is used in the PARALLEL and so a pattern
3041          with a modified I2SRC would not match.  */
3042
3043       if (flag_expensive_optimizations)
3044         {
3045           /* Pass pc_rtx so no substitutions are done, just
3046              simplifications.  */
3047           if (i1)
3048             {
3049               subst_low_luid = DF_INSN_LUID (i1);
3050               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3051             }
3052
3053           subst_low_luid = DF_INSN_LUID (i2);
3054           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3055         }
3056
3057       n_occurrences = 0;                /* `subst' counts here */
3058       subst_low_luid = DF_INSN_LUID (i2);
3059
3060       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3061          copy of I2SRC each time we substitute it, in order to avoid creating
3062          self-referential RTL when we will be substituting I1SRC for I1DEST
3063          later.  Likewise if I0 feeds into I2, either directly or indirectly
3064          through I1, and I0DEST is in I0SRC.  */
3065       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3066                       (i1_feeds_i2_n && i1dest_in_i1src)
3067                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3068                           && i0dest_in_i0src));
3069       substed_i2 = 1;
3070
3071       /* Record whether I2's body now appears within I3's body.  */
3072       i2_is_used = n_occurrences;
3073     }
3074
3075   /* If we already got a failure, don't try to do more.  Otherwise, try to
3076      substitute I1 if we have it.  */
3077
3078   if (i1 && GET_CODE (newpat) != CLOBBER)
3079     {
3080       /* Check that an autoincrement side-effect on I1 has not been lost.
3081          This happens if I1DEST is mentioned in I2 and dies there, and
3082          has disappeared from the new pattern.  */
3083       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3084            && i1_feeds_i2_n
3085            && dead_or_set_p (i2, i1dest)
3086            && !reg_overlap_mentioned_p (i1dest, newpat))
3087            /* Before we can do this substitution, we must redo the test done
3088               above (see detailed comments there) that ensures I1DEST isn't
3089               mentioned in any SETs in NEWPAT that are field assignments.  */
3090           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3091                                 0, 0, 0))
3092         {
3093           undo_all ();
3094           return 0;
3095         }
3096
3097       n_occurrences = 0;
3098       subst_low_luid = DF_INSN_LUID (i1);
3099
3100       /* If the following substitution will modify I1SRC, make a copy of it
3101          for the case where it is substituted for I1DEST in I2PAT later.  */
3102       if (added_sets_2 && i1_feeds_i2_n)
3103         i1src_copy = copy_rtx (i1src);
3104
3105       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3106          copy of I1SRC each time we substitute it, in order to avoid creating
3107          self-referential RTL when we will be substituting I0SRC for I0DEST
3108          later.  */
3109       newpat = subst (newpat, i1dest, i1src, 0, 0,
3110                       i0_feeds_i1_n && i0dest_in_i0src);
3111       substed_i1 = 1;
3112
3113       /* Record whether I1's body now appears within I3's body.  */
3114       i1_is_used = n_occurrences;
3115     }
3116
3117   /* Likewise for I0 if we have it.  */
3118
3119   if (i0 && GET_CODE (newpat) != CLOBBER)
3120     {
3121       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3122            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3123                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3124            && !reg_overlap_mentioned_p (i0dest, newpat))
3125           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3126                                 0, 0, 0))
3127         {
3128           undo_all ();
3129           return 0;
3130         }
3131
3132       /* If the following substitution will modify I0SRC, make a copy of it
3133          for the case where it is substituted for I0DEST in I1PAT later.  */
3134       if (added_sets_1 && i0_feeds_i1_n)
3135         i0src_copy = copy_rtx (i0src);
3136       /* And a copy for I0DEST in I2PAT substitution.  */
3137       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3138                            || (i0_feeds_i2_n)))
3139         i0src_copy2 = copy_rtx (i0src);
3140
3141       n_occurrences = 0;
3142       subst_low_luid = DF_INSN_LUID (i0);
3143       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3144       substed_i0 = 1;
3145     }
3146
3147   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3148      to count all the ways that I2SRC and I1SRC can be used.  */
3149   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3150        && i2_is_used + added_sets_2 > 1)
3151       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3152           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3153               > 1))
3154       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3155           && (n_occurrences + added_sets_0
3156               + (added_sets_1 && i0_feeds_i1_n)
3157               + (added_sets_2 && i0_feeds_i2_n)
3158               > 1))
3159       /* Fail if we tried to make a new register.  */
3160       || max_reg_num () != maxreg
3161       /* Fail if we couldn't do something and have a CLOBBER.  */
3162       || GET_CODE (newpat) == CLOBBER
3163       /* Fail if this new pattern is a MULT and we didn't have one before
3164          at the outer level.  */
3165       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3166           && ! have_mult))
3167     {
3168       undo_all ();
3169       return 0;
3170     }
3171
3172   /* If the actions of the earlier insns must be kept
3173      in addition to substituting them into the latest one,
3174      we must make a new PARALLEL for the latest insn
3175      to hold additional the SETs.  */
3176
3177   if (added_sets_0 || added_sets_1 || added_sets_2)
3178     {
3179       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3180       combine_extras++;
3181
3182       if (GET_CODE (newpat) == PARALLEL)
3183         {
3184           rtvec old = XVEC (newpat, 0);
3185           total_sets = XVECLEN (newpat, 0) + extra_sets;
3186           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3187           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3188                   sizeof (old->elem[0]) * old->num_elem);
3189         }
3190       else
3191         {
3192           rtx old = newpat;
3193           total_sets = 1 + extra_sets;
3194           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3195           XVECEXP (newpat, 0, 0) = old;
3196         }
3197
3198       if (added_sets_0)
3199         XVECEXP (newpat, 0, --total_sets) = i0pat;
3200
3201       if (added_sets_1)
3202         {
3203           rtx t = i1pat;
3204           if (i0_feeds_i1_n)
3205             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3206
3207           XVECEXP (newpat, 0, --total_sets) = t;
3208         }
3209       if (added_sets_2)
3210         {
3211           rtx t = i2pat;
3212           if (i1_feeds_i2_n)
3213             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3214                        i0_feeds_i1_n && i0dest_in_i0src);
3215           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3216             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3217
3218           XVECEXP (newpat, 0, --total_sets) = t;
3219         }
3220     }
3221
3222  validate_replacement:
3223
3224   /* Note which hard regs this insn has as inputs.  */
3225   mark_used_regs_combine (newpat);
3226
3227   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3228      consider splitting this pattern, we might need these clobbers.  */
3229   if (i1 && GET_CODE (newpat) == PARALLEL
3230       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3231     {
3232       int len = XVECLEN (newpat, 0);
3233
3234       newpat_vec_with_clobbers = rtvec_alloc (len);
3235       for (i = 0; i < len; i++)
3236         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3237     }
3238
3239   /* Is the result of combination a valid instruction?  */
3240   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3241
3242   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3243      the second SET's destination is a register that is unused and isn't
3244      marked as an instruction that might trap in an EH region.  In that case,
3245      we just need the first SET.   This can occur when simplifying a divmod
3246      insn.  We *must* test for this case here because the code below that
3247      splits two independent SETs doesn't handle this case correctly when it
3248      updates the register status.
3249
3250      It's pointless doing this if we originally had two sets, one from
3251      i3, and one from i2.  Combining then splitting the parallel results
3252      in the original i2 again plus an invalid insn (which we delete).
3253      The net effect is only to move instructions around, which makes
3254      debug info less accurate.
3255
3256      Also check the case where the first SET's destination is unused.
3257      That would not cause incorrect code, but does cause an unneeded
3258      insn to remain.  */
3259
3260   if (insn_code_number < 0
3261       && !(added_sets_2 && i1 == 0)
3262       && GET_CODE (newpat) == PARALLEL
3263       && XVECLEN (newpat, 0) == 2
3264       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3265       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3266       && asm_noperands (newpat) < 0)
3267     {
3268       rtx set0 = XVECEXP (newpat, 0, 0);
3269       rtx set1 = XVECEXP (newpat, 0, 1);
3270
3271       if (((REG_P (SET_DEST (set1))
3272             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3273            || (GET_CODE (SET_DEST (set1)) == SUBREG
3274                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3275           && insn_nothrow_p (i3)
3276           && !side_effects_p (SET_SRC (set1)))
3277         {
3278           newpat = set0;
3279           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3280         }
3281
3282       else if (((REG_P (SET_DEST (set0))
3283                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3284                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3285                     && find_reg_note (i3, REG_UNUSED,
3286                                       SUBREG_REG (SET_DEST (set0)))))
3287                && insn_nothrow_p (i3)
3288                && !side_effects_p (SET_SRC (set0)))
3289         {
3290           newpat = set1;
3291           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3292
3293           if (insn_code_number >= 0)
3294             changed_i3_dest = 1;
3295         }
3296     }
3297
3298   /* If we were combining three insns and the result is a simple SET
3299      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3300      insns.  There are two ways to do this.  It can be split using a
3301      machine-specific method (like when you have an addition of a large
3302      constant) or by combine in the function find_split_point.  */
3303
3304   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3305       && asm_noperands (newpat) < 0)
3306     {
3307       rtx parallel, m_split, *split;
3308
3309       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3310          use I2DEST as a scratch register will help.  In the latter case,
3311          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3312
3313       m_split = combine_split_insns (newpat, i3);
3314
3315       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3316          inputs of NEWPAT.  */
3317
3318       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3319          possible to try that as a scratch reg.  This would require adding
3320          more code to make it work though.  */
3321
3322       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3323         {
3324           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3325
3326           /* First try to split using the original register as a
3327              scratch register.  */
3328           parallel = gen_rtx_PARALLEL (VOIDmode,
3329                                        gen_rtvec (2, newpat,
3330                                                   gen_rtx_CLOBBER (VOIDmode,
3331                                                                    i2dest)));
3332           m_split = combine_split_insns (parallel, i3);
3333
3334           /* If that didn't work, try changing the mode of I2DEST if
3335              we can.  */
3336           if (m_split == 0
3337               && new_mode != GET_MODE (i2dest)
3338               && new_mode != VOIDmode
3339               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3340             {
3341               enum machine_mode old_mode = GET_MODE (i2dest);
3342               rtx ni2dest;
3343
3344               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3345                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3346               else
3347                 {
3348                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3349                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3350                 }
3351
3352               parallel = (gen_rtx_PARALLEL
3353                           (VOIDmode,
3354                            gen_rtvec (2, newpat,
3355                                       gen_rtx_CLOBBER (VOIDmode,
3356                                                        ni2dest))));
3357               m_split = combine_split_insns (parallel, i3);
3358
3359               if (m_split == 0
3360                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3361                 {
3362                   struct undo *buf;
3363
3364                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3365                   buf = undobuf.undos;
3366                   undobuf.undos = buf->next;
3367                   buf->next = undobuf.frees;
3368                   undobuf.frees = buf;
3369                 }
3370             }
3371
3372           i2scratch = m_split != 0;
3373         }
3374
3375       /* If recog_for_combine has discarded clobbers, try to use them
3376          again for the split.  */
3377       if (m_split == 0 && newpat_vec_with_clobbers)
3378         {
3379           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3380           m_split = combine_split_insns (parallel, i3);
3381         }
3382
3383       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3384         {
3385           m_split = PATTERN (m_split);
3386           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3387           if (insn_code_number >= 0)
3388             newpat = m_split;
3389         }
3390       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3391                && (next_nonnote_nondebug_insn (i2) == i3
3392                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3393         {
3394           rtx i2set, i3set;
3395           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3396           newi2pat = PATTERN (m_split);
3397
3398           i3set = single_set (NEXT_INSN (m_split));
3399           i2set = single_set (m_split);
3400
3401           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3402
3403           /* If I2 or I3 has multiple SETs, we won't know how to track
3404              register status, so don't use these insns.  If I2's destination
3405              is used between I2 and I3, we also can't use these insns.  */
3406
3407           if (i2_code_number >= 0 && i2set && i3set
3408               && (next_nonnote_nondebug_insn (i2) == i3
3409                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3410             insn_code_number = recog_for_combine (&newi3pat, i3,
3411                                                   &new_i3_notes);
3412           if (insn_code_number >= 0)
3413             newpat = newi3pat;
3414
3415           /* It is possible that both insns now set the destination of I3.
3416              If so, we must show an extra use of it.  */
3417
3418           if (insn_code_number >= 0)
3419             {
3420               rtx new_i3_dest = SET_DEST (i3set);
3421               rtx new_i2_dest = SET_DEST (i2set);
3422
3423               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3424                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3425                      || GET_CODE (new_i3_dest) == SUBREG)
3426                 new_i3_dest = XEXP (new_i3_dest, 0);
3427
3428               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3429                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3430                      || GET_CODE (new_i2_dest) == SUBREG)
3431                 new_i2_dest = XEXP (new_i2_dest, 0);
3432
3433               if (REG_P (new_i3_dest)
3434                   && REG_P (new_i2_dest)
3435                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3436                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3437             }
3438         }
3439
3440       /* If we can split it and use I2DEST, go ahead and see if that
3441          helps things be recognized.  Verify that none of the registers
3442          are set between I2 and I3.  */
3443       if (insn_code_number < 0
3444           && (split = find_split_point (&newpat, i3, false)) != 0
3445 #ifdef HAVE_cc0
3446           && REG_P (i2dest)
3447 #endif
3448           /* We need I2DEST in the proper mode.  If it is a hard register
3449              or the only use of a pseudo, we can change its mode.
3450              Make sure we don't change a hard register to have a mode that
3451              isn't valid for it, or change the number of registers.  */
3452           && (GET_MODE (*split) == GET_MODE (i2dest)
3453               || GET_MODE (*split) == VOIDmode
3454               || can_change_dest_mode (i2dest, added_sets_2,
3455                                        GET_MODE (*split)))
3456           && (next_nonnote_nondebug_insn (i2) == i3
3457               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3458           /* We can't overwrite I2DEST if its value is still used by
3459              NEWPAT.  */
3460           && ! reg_referenced_p (i2dest, newpat))
3461         {
3462           rtx newdest = i2dest;
3463           enum rtx_code split_code = GET_CODE (*split);
3464           enum machine_mode split_mode = GET_MODE (*split);
3465           bool subst_done = false;
3466           newi2pat = NULL_RTX;
3467
3468           i2scratch = true;
3469
3470           /* *SPLIT may be part of I2SRC, so make sure we have the
3471              original expression around for later debug processing.
3472              We should not need I2SRC any more in other cases.  */
3473           if (MAY_HAVE_DEBUG_INSNS)
3474             i2src = copy_rtx (i2src);
3475           else
3476             i2src = NULL;
3477
3478           /* Get NEWDEST as a register in the proper mode.  We have already
3479              validated that we can do this.  */
3480           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3481             {
3482               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3483                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3484               else
3485                 {
3486                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3487                   newdest = regno_reg_rtx[REGNO (i2dest)];
3488                 }
3489             }
3490
3491           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3492              an ASHIFT.  This can occur if it was inside a PLUS and hence
3493              appeared to be a memory address.  This is a kludge.  */
3494           if (split_code == MULT
3495               && CONST_INT_P (XEXP (*split, 1))
3496               && INTVAL (XEXP (*split, 1)) > 0
3497               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3498             {
3499               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3500                                              XEXP (*split, 0), GEN_INT (i)));
3501               /* Update split_code because we may not have a multiply
3502                  anymore.  */
3503               split_code = GET_CODE (*split);
3504             }
3505
3506 #ifdef INSN_SCHEDULING
3507           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3508              be written as a ZERO_EXTEND.  */
3509           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3510             {
3511 #ifdef LOAD_EXTEND_OP
3512               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3513                  what it really is.  */
3514               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3515                   == SIGN_EXTEND)
3516                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3517                                                     SUBREG_REG (*split)));
3518               else
3519 #endif
3520                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3521                                                     SUBREG_REG (*split)));
3522             }
3523 #endif
3524
3525           /* Attempt to split binary operators using arithmetic identities.  */
3526           if (BINARY_P (SET_SRC (newpat))
3527               && split_mode == GET_MODE (SET_SRC (newpat))
3528               && ! side_effects_p (SET_SRC (newpat)))
3529             {
3530               rtx setsrc = SET_SRC (newpat);
3531               enum machine_mode mode = GET_MODE (setsrc);
3532               enum rtx_code code = GET_CODE (setsrc);
3533               rtx src_op0 = XEXP (setsrc, 0);
3534               rtx src_op1 = XEXP (setsrc, 1);
3535
3536               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3537               if (rtx_equal_p (src_op0, src_op1))
3538                 {
3539                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3540                   SUBST (XEXP (setsrc, 0), newdest);
3541                   SUBST (XEXP (setsrc, 1), newdest);
3542                   subst_done = true;
3543                 }
3544               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3545               else if ((code == PLUS || code == MULT)
3546                        && GET_CODE (src_op0) == code
3547                        && GET_CODE (XEXP (src_op0, 0)) == code
3548                        && (INTEGRAL_MODE_P (mode)
3549                            || (FLOAT_MODE_P (mode)
3550                                && flag_unsafe_math_optimizations)))
3551                 {
3552                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3553                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3554                   rtx r = XEXP (src_op0, 1);
3555                   rtx s = src_op1;
3556
3557                   /* Split both "((X op Y) op X) op Y" and
3558                      "((X op Y) op Y) op X" as "T op T" where T is
3559                      "X op Y".  */
3560                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3561                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3562                     {
3563                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3564                                               XEXP (src_op0, 0));
3565                       SUBST (XEXP (setsrc, 0), newdest);
3566                       SUBST (XEXP (setsrc, 1), newdest);
3567                       subst_done = true;
3568                     }
3569                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3570                      T is "X op Y".  */
3571                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3572                     {
3573                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3574                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3575                       SUBST (XEXP (setsrc, 0), newdest);
3576                       SUBST (XEXP (setsrc, 1), newdest);
3577                       subst_done = true;
3578                     }
3579                 }
3580             }
3581
3582           if (!subst_done)
3583             {
3584               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3585               SUBST (*split, newdest);
3586             }
3587
3588           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3589
3590           /* recog_for_combine might have added CLOBBERs to newi2pat.
3591              Make sure NEWPAT does not depend on the clobbered regs.  */
3592           if (GET_CODE (newi2pat) == PARALLEL)
3593             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3594               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3595                 {
3596                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3597                   if (reg_overlap_mentioned_p (reg, newpat))
3598                     {
3599                       undo_all ();
3600                       return 0;
3601                     }
3602                 }
3603
3604           /* If the split point was a MULT and we didn't have one before,
3605              don't use one now.  */
3606           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3607             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3608         }
3609     }
3610
3611   /* Check for a case where we loaded from memory in a narrow mode and
3612      then sign extended it, but we need both registers.  In that case,
3613      we have a PARALLEL with both loads from the same memory location.
3614      We can split this into a load from memory followed by a register-register
3615      copy.  This saves at least one insn, more if register allocation can
3616      eliminate the copy.
3617
3618      We cannot do this if the destination of the first assignment is a
3619      condition code register or cc0.  We eliminate this case by making sure
3620      the SET_DEST and SET_SRC have the same mode.
3621
3622      We cannot do this if the destination of the second assignment is
3623      a register that we have already assumed is zero-extended.  Similarly
3624      for a SUBREG of such a register.  */
3625
3626   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3627            && GET_CODE (newpat) == PARALLEL
3628            && XVECLEN (newpat, 0) == 2
3629            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3630            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3631            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3632                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3633            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3634            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3635                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3636            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3637                                    DF_INSN_LUID (i2))
3638            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3639            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3640            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3641                  (REG_P (temp)
3642                   && reg_stat[REGNO (temp)].nonzero_bits != 0
3643                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3644                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3645                   && (reg_stat[REGNO (temp)].nonzero_bits
3646                       != GET_MODE_MASK (word_mode))))
3647            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3648                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3649                      (REG_P (temp)
3650                       && reg_stat[REGNO (temp)].nonzero_bits != 0
3651                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3652                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3653                       && (reg_stat[REGNO (temp)].nonzero_bits
3654                           != GET_MODE_MASK (word_mode)))))
3655            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3656                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3657            && ! find_reg_note (i3, REG_UNUSED,
3658                                SET_DEST (XVECEXP (newpat, 0, 0))))
3659     {
3660       rtx ni2dest;
3661
3662       newi2pat = XVECEXP (newpat, 0, 0);
3663       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3664       newpat = XVECEXP (newpat, 0, 1);
3665       SUBST (SET_SRC (newpat),
3666              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3667       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3668
3669       if (i2_code_number >= 0)
3670         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3671
3672       if (insn_code_number >= 0)
3673         swap_i2i3 = 1;
3674     }
3675
3676   /* Similarly, check for a case where we have a PARALLEL of two independent
3677      SETs but we started with three insns.  In this case, we can do the sets
3678      as two separate insns.  This case occurs when some SET allows two
3679      other insns to combine, but the destination of that SET is still live.  */
3680
3681   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3682            && GET_CODE (newpat) == PARALLEL
3683            && XVECLEN (newpat, 0) == 2
3684            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3685            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3686            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3687            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3688            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3689            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3690            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3691                                   XVECEXP (newpat, 0, 0))
3692            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3693                                   XVECEXP (newpat, 0, 1))
3694            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3695                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3696     {
3697       rtx set0 = XVECEXP (newpat, 0, 0);
3698       rtx set1 = XVECEXP (newpat, 0, 1);
3699
3700       /* Normally, it doesn't matter which of the two is done first,
3701          but the one that references cc0 can't be the second, and
3702          one which uses any regs/memory set in between i2 and i3 can't
3703          be first.  The PARALLEL might also have been pre-existing in i3,
3704          so we need to make sure that we won't wrongly hoist a SET to i2
3705          that would conflict with a death note present in there.  */
3706       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3707           && !(REG_P (SET_DEST (set1))
3708                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3709           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3710                && find_reg_note (i2, REG_DEAD,
3711                                  SUBREG_REG (SET_DEST (set1))))
3712 #ifdef HAVE_cc0
3713           && !reg_referenced_p (cc0_rtx, set0)
3714 #endif
3715          )
3716         {
3717           newi2pat = set1;
3718           newpat = set0;
3719         }
3720       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3721                && !(REG_P (SET_DEST (set0))
3722                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3723                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3724                     && find_reg_note (i2, REG_DEAD,
3725                                       SUBREG_REG (SET_DEST (set0))))
3726 #ifdef HAVE_cc0
3727                && !reg_referenced_p (cc0_rtx, set1)
3728 #endif
3729               )
3730         {
3731           newi2pat = set0;
3732           newpat = set1;
3733         }
3734       else
3735         {
3736           undo_all ();
3737           return 0;
3738         }
3739
3740       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3741
3742       if (i2_code_number >= 0)
3743         {
3744           /* recog_for_combine might have added CLOBBERs to newi2pat.
3745              Make sure NEWPAT does not depend on the clobbered regs.  */
3746           if (GET_CODE (newi2pat) == PARALLEL)
3747             {
3748               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3749                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3750                   {
3751                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3752                     if (reg_overlap_mentioned_p (reg, newpat))
3753                       {
3754                         undo_all ();
3755                         return 0;
3756                       }
3757                   }
3758             }
3759
3760           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3761         }
3762     }
3763
3764   /* If it still isn't recognized, fail and change things back the way they
3765      were.  */
3766   if ((insn_code_number < 0
3767        /* Is the result a reasonable ASM_OPERANDS?  */
3768        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3769     {
3770       undo_all ();
3771       return 0;
3772     }
3773
3774   /* If we had to change another insn, make sure it is valid also.  */
3775   if (undobuf.other_insn)
3776     {
3777       CLEAR_HARD_REG_SET (newpat_used_regs);
3778
3779       other_pat = PATTERN (undobuf.other_insn);
3780       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3781                                              &new_other_notes);
3782
3783       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3784         {
3785           undo_all ();
3786           return 0;
3787         }
3788     }
3789
3790 #ifdef HAVE_cc0
3791   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3792      they are adjacent to each other or not.  */
3793   {
3794     rtx p = prev_nonnote_insn (i3);
3795     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3796         && sets_cc0_p (newi2pat))
3797       {
3798         undo_all ();
3799         return 0;
3800       }
3801   }
3802 #endif
3803
3804   /* Only allow this combination if insn_rtx_costs reports that the
3805      replacement instructions are cheaper than the originals.  */
3806   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3807     {
3808       undo_all ();
3809       return 0;
3810     }
3811
3812   if (MAY_HAVE_DEBUG_INSNS)
3813     {
3814       struct undo *undo;
3815
3816       for (undo = undobuf.undos; undo; undo = undo->next)
3817         if (undo->kind == UNDO_MODE)
3818           {
3819             rtx reg = *undo->where.r;
3820             enum machine_mode new_mode = GET_MODE (reg);
3821             enum machine_mode old_mode = undo->old_contents.m;
3822
3823             /* Temporarily revert mode back.  */
3824             adjust_reg_mode (reg, old_mode);
3825
3826             if (reg == i2dest && i2scratch)
3827               {
3828                 /* If we used i2dest as a scratch register with a
3829                    different mode, substitute it for the original
3830                    i2src while its original mode is temporarily
3831                    restored, and then clear i2scratch so that we don't
3832                    do it again later.  */
3833                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3834                                      this_basic_block);
3835                 i2scratch = false;
3836                 /* Put back the new mode.  */
3837                 adjust_reg_mode (reg, new_mode);
3838               }
3839             else
3840               {
3841                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3842                 rtx first, last;
3843
3844                 if (reg == i2dest)
3845                   {
3846                     first = i2;
3847                     last = last_combined_insn;
3848                   }
3849                 else
3850                   {
3851                     first = i3;
3852                     last = undobuf.other_insn;
3853                     gcc_assert (last);
3854                     if (DF_INSN_LUID (last)
3855                         < DF_INSN_LUID (last_combined_insn))
3856                       last = last_combined_insn;
3857                   }
3858
3859                 /* We're dealing with a reg that changed mode but not
3860                    meaning, so we want to turn it into a subreg for
3861                    the new mode.  However, because of REG sharing and
3862                    because its mode had already changed, we have to do
3863                    it in two steps.  First, replace any debug uses of
3864                    reg, with its original mode temporarily restored,
3865                    with this copy we have created; then, replace the
3866                    copy with the SUBREG of the original shared reg,
3867                    once again changed to the new mode.  */
3868                 propagate_for_debug (first, last, reg, tempreg,
3869                                      this_basic_block);
3870                 adjust_reg_mode (reg, new_mode);
3871                 propagate_for_debug (first, last, tempreg,
3872                                      lowpart_subreg (old_mode, reg, new_mode),
3873                                      this_basic_block);
3874               }
3875           }
3876     }
3877
3878   /* If we will be able to accept this, we have made a
3879      change to the destination of I3.  This requires us to
3880      do a few adjustments.  */
3881
3882   if (changed_i3_dest)
3883     {
3884       PATTERN (i3) = newpat;
3885       adjust_for_new_dest (i3);
3886     }
3887
3888   /* We now know that we can do this combination.  Merge the insns and
3889      update the status of registers and LOG_LINKS.  */
3890
3891   if (undobuf.other_insn)
3892     {
3893       rtx note, next;
3894
3895       PATTERN (undobuf.other_insn) = other_pat;
3896
3897       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3898          are still valid.  Then add any non-duplicate notes added by
3899          recog_for_combine.  */
3900       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3901         {
3902           next = XEXP (note, 1);
3903
3904           if (REG_NOTE_KIND (note) == REG_UNUSED
3905               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3906             remove_note (undobuf.other_insn, note);
3907         }
3908
3909       distribute_notes (new_other_notes, undobuf.other_insn,
3910                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3911                         NULL_RTX);
3912     }
3913
3914   if (swap_i2i3)
3915     {
3916       rtx insn;
3917       struct insn_link *link;
3918       rtx ni2dest;
3919
3920       /* I3 now uses what used to be its destination and which is now
3921          I2's destination.  This requires us to do a few adjustments.  */
3922       PATTERN (i3) = newpat;
3923       adjust_for_new_dest (i3);
3924
3925       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3926          so we still will.
3927
3928          However, some later insn might be using I2's dest and have
3929          a LOG_LINK pointing at I3.  We must remove this link.
3930          The simplest way to remove the link is to point it at I1,
3931          which we know will be a NOTE.  */
3932
3933       /* newi2pat is usually a SET here; however, recog_for_combine might
3934          have added some clobbers.  */
3935       if (GET_CODE (newi2pat) == PARALLEL)
3936         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3937       else
3938         ni2dest = SET_DEST (newi2pat);
3939
3940       for (insn = NEXT_INSN (i3);
3941            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3942                     || insn != BB_HEAD (this_basic_block->next_bb));
3943            insn = NEXT_INSN (insn))
3944         {
3945           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3946             {
3947               FOR_EACH_LOG_LINK (link, insn)
3948                 if (link->insn == i3)
3949                   link->insn = i1;
3950
3951               break;
3952             }
3953         }
3954     }
3955
3956   {
3957     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3958     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3959     rtx midnotes = 0;
3960     int from_luid;
3961     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3962        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3963        same as i3dest, in which case newi2pat may be setting i1dest.  */
3964     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3965                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3966                    || !i2dest_killed
3967                    ? 0 : i2dest);
3968     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3969                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3970                    || !i1dest_killed
3971                    ? 0 : i1dest);
3972     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3973                    || (newi2pat && reg_set_p (i0dest, newi2pat))
3974                    || !i0dest_killed
3975                    ? 0 : i0dest);
3976
3977     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3978        clear them.  */
3979     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3980     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3981     if (i1)
3982       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3983     if (i0)
3984       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
3985
3986     /* Ensure that we do not have something that should not be shared but
3987        occurs multiple times in the new insns.  Check this by first
3988        resetting all the `used' flags and then copying anything is shared.  */
3989
3990     reset_used_flags (i3notes);
3991     reset_used_flags (i2notes);
3992     reset_used_flags (i1notes);
3993     reset_used_flags (i0notes);
3994     reset_used_flags (newpat);
3995     reset_used_flags (newi2pat);
3996     if (undobuf.other_insn)
3997       reset_used_flags (PATTERN (undobuf.other_insn));
3998
3999     i3notes = copy_rtx_if_shared (i3notes);
4000     i2notes = copy_rtx_if_shared (i2notes);
4001     i1notes = copy_rtx_if_shared (i1notes);
4002     i0notes = copy_rtx_if_shared (i0notes);
4003     newpat = copy_rtx_if_shared (newpat);
4004     newi2pat = copy_rtx_if_shared (newi2pat);
4005     if (undobuf.other_insn)
4006       reset_used_flags (PATTERN (undobuf.other_insn));
4007
4008     INSN_CODE (i3) = insn_code_number;
4009     PATTERN (i3) = newpat;
4010
4011     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4012       {
4013         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4014
4015         reset_used_flags (call_usage);
4016         call_usage = copy_rtx (call_usage);
4017
4018         if (substed_i2)
4019           {
4020             /* I2SRC must still be meaningful at this point.  Some splitting
4021                operations can invalidate I2SRC, but those operations do not
4022                apply to calls.  */
4023             gcc_assert (i2src);
4024             replace_rtx (call_usage, i2dest, i2src);
4025           }
4026
4027         if (substed_i1)
4028           replace_rtx (call_usage, i1dest, i1src);
4029         if (substed_i0)
4030           replace_rtx (call_usage, i0dest, i0src);
4031
4032         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4033       }
4034
4035     if (undobuf.other_insn)
4036       INSN_CODE (undobuf.other_insn) = other_code_number;
4037
4038     /* We had one special case above where I2 had more than one set and
4039        we replaced a destination of one of those sets with the destination
4040        of I3.  In that case, we have to update LOG_LINKS of insns later
4041        in this basic block.  Note that this (expensive) case is rare.
4042
4043        Also, in this case, we must pretend that all REG_NOTEs for I2
4044        actually came from I3, so that REG_UNUSED notes from I2 will be
4045        properly handled.  */
4046
4047     if (i3_subst_into_i2)
4048       {
4049         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4050           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4051                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4052               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4053               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4054               && ! find_reg_note (i2, REG_UNUSED,
4055                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4056             for (temp = NEXT_INSN (i2);
4057                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4058                           || BB_HEAD (this_basic_block) != temp);
4059                  temp = NEXT_INSN (temp))
4060               if (temp != i3 && INSN_P (temp))
4061                 FOR_EACH_LOG_LINK (link, temp)
4062                   if (link->insn == i2)
4063                     link->insn = i3;
4064
4065         if (i3notes)
4066           {
4067             rtx link = i3notes;
4068             while (XEXP (link, 1))
4069               link = XEXP (link, 1);
4070             XEXP (link, 1) = i2notes;
4071           }
4072         else
4073           i3notes = i2notes;
4074         i2notes = 0;
4075       }
4076
4077     LOG_LINKS (i3) = NULL;
4078     REG_NOTES (i3) = 0;
4079     LOG_LINKS (i2) = NULL;
4080     REG_NOTES (i2) = 0;
4081
4082     if (newi2pat)
4083       {
4084         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4085           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4086                                this_basic_block);
4087         INSN_CODE (i2) = i2_code_number;
4088         PATTERN (i2) = newi2pat;
4089       }
4090     else
4091       {
4092         if (MAY_HAVE_DEBUG_INSNS && i2src)
4093           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4094                                this_basic_block);
4095         SET_INSN_DELETED (i2);
4096       }
4097
4098     if (i1)
4099       {
4100         LOG_LINKS (i1) = NULL;
4101         REG_NOTES (i1) = 0;
4102         if (MAY_HAVE_DEBUG_INSNS)
4103           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4104                                this_basic_block);
4105         SET_INSN_DELETED (i1);
4106       }
4107
4108     if (i0)
4109       {
4110         LOG_LINKS (i0) = NULL;
4111         REG_NOTES (i0) = 0;
4112         if (MAY_HAVE_DEBUG_INSNS)
4113           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4114                                this_basic_block);
4115         SET_INSN_DELETED (i0);
4116       }
4117
4118     /* Get death notes for everything that is now used in either I3 or
4119        I2 and used to die in a previous insn.  If we built two new
4120        patterns, move from I1 to I2 then I2 to I3 so that we get the
4121        proper movement on registers that I2 modifies.  */
4122
4123     if (i0)
4124       from_luid = DF_INSN_LUID (i0);
4125     else if (i1)
4126       from_luid = DF_INSN_LUID (i1);
4127     else
4128       from_luid = DF_INSN_LUID (i2);
4129     if (newi2pat)
4130       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4131     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4132
4133     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4134     if (i3notes)
4135       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4136                         elim_i2, elim_i1, elim_i0);
4137     if (i2notes)
4138       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4139                         elim_i2, elim_i1, elim_i0);
4140     if (i1notes)
4141       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4142                         elim_i2, elim_i1, elim_i0);
4143     if (i0notes)
4144       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4145                         elim_i2, elim_i1, elim_i0);
4146     if (midnotes)
4147       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4148                         elim_i2, elim_i1, elim_i0);
4149
4150     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4151        know these are REG_UNUSED and want them to go to the desired insn,
4152        so we always pass it as i3.  */
4153
4154     if (newi2pat && new_i2_notes)
4155       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4156                         NULL_RTX);
4157
4158     if (new_i3_notes)
4159       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4160                         NULL_RTX);
4161
4162     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4163        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4164        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4165        in that case, it might delete I2.  Similarly for I2 and I1.
4166        Show an additional death due to the REG_DEAD note we make here.  If
4167        we discard it in distribute_notes, we will decrement it again.  */
4168
4169     if (i3dest_killed)
4170       {
4171         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4172         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4173           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, elim_i2,
4174                             elim_i1, elim_i0);
4175         else
4176           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4177                             elim_i2, elim_i1, elim_i0);
4178       }
4179
4180     if (i2dest_in_i2src)
4181       {
4182         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4183         if (newi2pat && reg_set_p (i2dest, newi2pat))
4184           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4185                             NULL_RTX, NULL_RTX);
4186         else
4187           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4188                             NULL_RTX, NULL_RTX, NULL_RTX);
4189       }
4190
4191     if (i1dest_in_i1src)
4192       {
4193         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4194         if (newi2pat && reg_set_p (i1dest, newi2pat))
4195           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4196                             NULL_RTX, NULL_RTX);
4197         else
4198           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4199                             NULL_RTX, NULL_RTX, NULL_RTX);
4200       }
4201
4202     if (i0dest_in_i0src)
4203       {
4204         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4205         if (newi2pat && reg_set_p (i0dest, newi2pat))
4206           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4207                             NULL_RTX, NULL_RTX);
4208         else
4209           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4210                             NULL_RTX, NULL_RTX, NULL_RTX);
4211       }
4212
4213     distribute_links (i3links);
4214     distribute_links (i2links);
4215     distribute_links (i1links);
4216     distribute_links (i0links);
4217
4218     if (REG_P (i2dest))
4219       {
4220         struct insn_link *link;
4221         rtx i2_insn = 0, i2_val = 0, set;
4222
4223         /* The insn that used to set this register doesn't exist, and
4224            this life of the register may not exist either.  See if one of
4225            I3's links points to an insn that sets I2DEST.  If it does,
4226            that is now the last known value for I2DEST. If we don't update
4227            this and I2 set the register to a value that depended on its old
4228            contents, we will get confused.  If this insn is used, thing
4229            will be set correctly in combine_instructions.  */
4230         FOR_EACH_LOG_LINK (link, i3)
4231           if ((set = single_set (link->insn)) != 0
4232               && rtx_equal_p (i2dest, SET_DEST (set)))
4233             i2_insn = link->insn, i2_val = SET_SRC (set);
4234
4235         record_value_for_reg (i2dest, i2_insn, i2_val);
4236
4237         /* If the reg formerly set in I2 died only once and that was in I3,
4238            zero its use count so it won't make `reload' do any work.  */
4239         if (! added_sets_2
4240             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4241             && ! i2dest_in_i2src)
4242           INC_REG_N_SETS (REGNO (i2dest), -1);
4243       }
4244
4245     if (i1 && REG_P (i1dest))
4246       {
4247         struct insn_link *link;
4248         rtx i1_insn = 0, i1_val = 0, set;
4249
4250         FOR_EACH_LOG_LINK (link, i3)
4251           if ((set = single_set (link->insn)) != 0
4252               && rtx_equal_p (i1dest, SET_DEST (set)))
4253             i1_insn = link->insn, i1_val = SET_SRC (set);
4254
4255         record_value_for_reg (i1dest, i1_insn, i1_val);
4256
4257         if (! added_sets_1 && ! i1dest_in_i1src)
4258           INC_REG_N_SETS (REGNO (i1dest), -1);
4259       }
4260
4261     if (i0 && REG_P (i0dest))
4262       {
4263         struct insn_link *link;
4264         rtx i0_insn = 0, i0_val = 0, set;
4265
4266         FOR_EACH_LOG_LINK (link, i3)
4267           if ((set = single_set (link->insn)) != 0
4268               && rtx_equal_p (i0dest, SET_DEST (set)))
4269             i0_insn = link->insn, i0_val = SET_SRC (set);
4270
4271         record_value_for_reg (i0dest, i0_insn, i0_val);
4272
4273         if (! added_sets_0 && ! i0dest_in_i0src)
4274           INC_REG_N_SETS (REGNO (i0dest), -1);
4275       }
4276
4277     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4278        been made to this insn.  The order is important, because newi2pat
4279        can affect nonzero_bits of newpat.  */
4280     if (newi2pat)
4281       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4282     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4283   }
4284
4285   if (undobuf.other_insn != NULL_RTX)
4286     {
4287       if (dump_file)
4288         {
4289           fprintf (dump_file, "modifying other_insn ");
4290           dump_insn_slim (dump_file, undobuf.other_insn);
4291         }
4292       df_insn_rescan (undobuf.other_insn);
4293     }
4294
4295   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4296     {
4297       if (dump_file)
4298         {
4299           fprintf (dump_file, "modifying insn i0 ");
4300           dump_insn_slim (dump_file, i0);
4301         }
4302       df_insn_rescan (i0);
4303     }
4304
4305   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4306     {
4307       if (dump_file)
4308         {
4309           fprintf (dump_file, "modifying insn i1 ");
4310           dump_insn_slim (dump_file, i1);
4311         }
4312       df_insn_rescan (i1);
4313     }
4314
4315   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4316     {
4317       if (dump_file)
4318         {
4319           fprintf (dump_file, "modifying insn i2 ");
4320           dump_insn_slim (dump_file, i2);
4321         }
4322       df_insn_rescan (i2);
4323     }
4324
4325   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4326     {
4327       if (dump_file)
4328         {
4329           fprintf (dump_file, "modifying insn i3 ");
4330           dump_insn_slim (dump_file, i3);
4331         }
4332       df_insn_rescan (i3);
4333     }
4334
4335   /* Set new_direct_jump_p if a new return or simple jump instruction
4336      has been created.  Adjust the CFG accordingly.  */
4337   if (returnjump_p (i3) || any_uncondjump_p (i3))
4338     {
4339       *new_direct_jump_p = 1;
4340       mark_jump_label (PATTERN (i3), i3, 0);
4341       update_cfg_for_uncondjump (i3);
4342     }
4343
4344   if (undobuf.other_insn != NULL_RTX
4345       && (returnjump_p (undobuf.other_insn)
4346           || any_uncondjump_p (undobuf.other_insn)))
4347     {
4348       *new_direct_jump_p = 1;
4349       update_cfg_for_uncondjump (undobuf.other_insn);
4350     }
4351
4352   /* A noop might also need cleaning up of CFG, if it comes from the
4353      simplification of a jump.  */
4354   if (JUMP_P (i3)
4355       && GET_CODE (newpat) == SET
4356       && SET_SRC (newpat) == pc_rtx
4357       && SET_DEST (newpat) == pc_rtx)
4358     {
4359       *new_direct_jump_p = 1;
4360       update_cfg_for_uncondjump (i3);
4361     }
4362
4363   if (undobuf.other_insn != NULL_RTX
4364       && JUMP_P (undobuf.other_insn)
4365       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4366       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4367       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4368     {
4369       *new_direct_jump_p = 1;
4370       update_cfg_for_uncondjump (undobuf.other_insn);
4371     }
4372
4373   combine_successes++;
4374   undo_commit ();
4375
4376   if (added_links_insn
4377       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4378       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4379     return added_links_insn;
4380   else
4381     return newi2pat ? i2 : i3;
4382 }
4383 \f
4384 /* Undo all the modifications recorded in undobuf.  */
4385
4386 static void
4387 undo_all (void)
4388 {
4389   struct undo *undo, *next;
4390
4391   for (undo = undobuf.undos; undo; undo = next)
4392     {
4393       next = undo->next;
4394       switch (undo->kind)
4395         {
4396         case UNDO_RTX:
4397           *undo->where.r = undo->old_contents.r;
4398           break;
4399         case UNDO_INT:
4400           *undo->where.i = undo->old_contents.i;
4401           break;
4402         case UNDO_MODE:
4403           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4404           break;
4405         case UNDO_LINKS:
4406           *undo->where.l = undo->old_contents.l;
4407           break;
4408         default:
4409           gcc_unreachable ();
4410         }
4411
4412       undo->next = undobuf.frees;
4413       undobuf.frees = undo;
4414     }
4415
4416   undobuf.undos = 0;
4417 }
4418
4419 /* We've committed to accepting the changes we made.  Move all
4420    of the undos to the free list.  */
4421
4422 static void
4423 undo_commit (void)
4424 {
4425   struct undo *undo, *next;
4426
4427   for (undo = undobuf.undos; undo; undo = next)
4428     {
4429       next = undo->next;
4430       undo->next = undobuf.frees;
4431       undobuf.frees = undo;
4432     }
4433   undobuf.undos = 0;
4434 }
4435 \f
4436 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4437    where we have an arithmetic expression and return that point.  LOC will
4438    be inside INSN.
4439
4440    try_combine will call this function to see if an insn can be split into
4441    two insns.  */
4442
4443 static rtx *
4444 find_split_point (rtx *loc, rtx insn, bool set_src)
4445 {
4446   rtx x = *loc;
4447   enum rtx_code code = GET_CODE (x);
4448   rtx *split;
4449   unsigned HOST_WIDE_INT len = 0;
4450   HOST_WIDE_INT pos = 0;
4451   int unsignedp = 0;
4452   rtx inner = NULL_RTX;
4453
4454   /* First special-case some codes.  */
4455   switch (code)
4456     {
4457     case SUBREG:
4458 #ifdef INSN_SCHEDULING
4459       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4460          point.  */
4461       if (MEM_P (SUBREG_REG (x)))
4462         return loc;
4463 #endif
4464       return find_split_point (&SUBREG_REG (x), insn, false);
4465
4466     case MEM:
4467 #ifdef HAVE_lo_sum
4468       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4469          using LO_SUM and HIGH.  */
4470       if (GET_CODE (XEXP (x, 0)) == CONST
4471           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4472         {
4473           enum machine_mode address_mode = get_address_mode (x);
4474
4475           SUBST (XEXP (x, 0),
4476                  gen_rtx_LO_SUM (address_mode,
4477                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4478                                  XEXP (x, 0)));
4479           return &XEXP (XEXP (x, 0), 0);
4480         }
4481 #endif
4482
4483       /* If we have a PLUS whose second operand is a constant and the
4484          address is not valid, perhaps will can split it up using
4485          the machine-specific way to split large constants.  We use
4486          the first pseudo-reg (one of the virtual regs) as a placeholder;
4487          it will not remain in the result.  */
4488       if (GET_CODE (XEXP (x, 0)) == PLUS
4489           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4490           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4491                                             MEM_ADDR_SPACE (x)))
4492         {
4493           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4494           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4495                                                       XEXP (x, 0)),
4496                                          subst_insn);
4497
4498           /* This should have produced two insns, each of which sets our
4499              placeholder.  If the source of the second is a valid address,
4500              we can make put both sources together and make a split point
4501              in the middle.  */
4502
4503           if (seq
4504               && NEXT_INSN (seq) != NULL_RTX
4505               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4506               && NONJUMP_INSN_P (seq)
4507               && GET_CODE (PATTERN (seq)) == SET
4508               && SET_DEST (PATTERN (seq)) == reg
4509               && ! reg_mentioned_p (reg,
4510                                     SET_SRC (PATTERN (seq)))
4511               && NONJUMP_INSN_P (NEXT_INSN (seq))
4512               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4513               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4514               && memory_address_addr_space_p
4515                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4516                     MEM_ADDR_SPACE (x)))
4517             {
4518               rtx src1 = SET_SRC (PATTERN (seq));
4519               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4520
4521               /* Replace the placeholder in SRC2 with SRC1.  If we can
4522                  find where in SRC2 it was placed, that can become our
4523                  split point and we can replace this address with SRC2.
4524                  Just try two obvious places.  */
4525
4526               src2 = replace_rtx (src2, reg, src1);
4527               split = 0;
4528               if (XEXP (src2, 0) == src1)
4529                 split = &XEXP (src2, 0);
4530               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4531                        && XEXP (XEXP (src2, 0), 0) == src1)
4532                 split = &XEXP (XEXP (src2, 0), 0);
4533
4534               if (split)
4535                 {
4536                   SUBST (XEXP (x, 0), src2);
4537                   return split;
4538                 }
4539             }
4540
4541           /* If that didn't work, perhaps the first operand is complex and
4542              needs to be computed separately, so make a split point there.
4543              This will occur on machines that just support REG + CONST
4544              and have a constant moved through some previous computation.  */
4545
4546           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4547                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4548                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4549             return &XEXP (XEXP (x, 0), 0);
4550         }
4551
4552       /* If we have a PLUS whose first operand is complex, try computing it
4553          separately by making a split there.  */
4554       if (GET_CODE (XEXP (x, 0)) == PLUS
4555           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4556                                             MEM_ADDR_SPACE (x))
4557           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4558           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4559                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4560         return &XEXP (XEXP (x, 0), 0);
4561       break;
4562
4563     case SET:
4564 #ifdef HAVE_cc0
4565       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4566          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4567          we need to put the operand into a register.  So split at that
4568          point.  */
4569
4570       if (SET_DEST (x) == cc0_rtx
4571           && GET_CODE (SET_SRC (x)) != COMPARE
4572           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4573           && !OBJECT_P (SET_SRC (x))
4574           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4575                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4576         return &SET_SRC (x);
4577 #endif
4578
4579       /* See if we can split SET_SRC as it stands.  */
4580       split = find_split_point (&SET_SRC (x), insn, true);
4581       if (split && split != &SET_SRC (x))
4582         return split;
4583
4584       /* See if we can split SET_DEST as it stands.  */
4585       split = find_split_point (&SET_DEST (x), insn, false);
4586       if (split && split != &SET_DEST (x))
4587         return split;
4588
4589       /* See if this is a bitfield assignment with everything constant.  If
4590          so, this is an IOR of an AND, so split it into that.  */
4591       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4592           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4593           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4594           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4595           && CONST_INT_P (SET_SRC (x))
4596           && ((INTVAL (XEXP (SET_DEST (x), 1))
4597                + INTVAL (XEXP (SET_DEST (x), 2)))
4598               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4599           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4600         {
4601           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4602           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4603           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4604           rtx dest = XEXP (SET_DEST (x), 0);
4605           enum machine_mode mode = GET_MODE (dest);
4606           unsigned HOST_WIDE_INT mask
4607             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4608           rtx or_mask;
4609
4610           if (BITS_BIG_ENDIAN)
4611             pos = GET_MODE_PRECISION (mode) - len - pos;
4612
4613           or_mask = gen_int_mode (src << pos, mode);
4614           if (src == mask)
4615             SUBST (SET_SRC (x),
4616                    simplify_gen_binary (IOR, mode, dest, or_mask));
4617           else
4618             {
4619               rtx negmask = gen_int_mode (~(mask << pos), mode);
4620               SUBST (SET_SRC (x),
4621                      simplify_gen_binary (IOR, mode,
4622                                           simplify_gen_binary (AND, mode,
4623                                                                dest, negmask),
4624                                           or_mask));
4625             }
4626
4627           SUBST (SET_DEST (x), dest);
4628
4629           split = find_split_point (&SET_SRC (x), insn, true);
4630           if (split && split != &SET_SRC (x))
4631             return split;
4632         }
4633
4634       /* Otherwise, see if this is an operation that we can split into two.
4635          If so, try to split that.  */
4636       code = GET_CODE (SET_SRC (x));
4637
4638       switch (code)
4639         {
4640         case AND:
4641           /* If we are AND'ing with a large constant that is only a single
4642              bit and the result is only being used in a context where we
4643              need to know if it is zero or nonzero, replace it with a bit
4644              extraction.  This will avoid the large constant, which might
4645              have taken more than one insn to make.  If the constant were
4646              not a valid argument to the AND but took only one insn to make,
4647              this is no worse, but if it took more than one insn, it will
4648              be better.  */
4649
4650           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4651               && REG_P (XEXP (SET_SRC (x), 0))
4652               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4653               && REG_P (SET_DEST (x))
4654               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4655               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4656               && XEXP (*split, 0) == SET_DEST (x)
4657               && XEXP (*split, 1) == const0_rtx)
4658             {
4659               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4660                                                 XEXP (SET_SRC (x), 0),
4661                                                 pos, NULL_RTX, 1, 1, 0, 0);
4662               if (extraction != 0)
4663                 {
4664                   SUBST (SET_SRC (x), extraction);
4665                   return find_split_point (loc, insn, false);
4666                 }
4667             }
4668           break;
4669
4670         case NE:
4671           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4672              is known to be on, this can be converted into a NEG of a shift.  */
4673           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4674               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4675               && 1 <= (pos = exact_log2
4676                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4677                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4678             {
4679               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4680
4681               SUBST (SET_SRC (x),
4682                      gen_rtx_NEG (mode,
4683                                   gen_rtx_LSHIFTRT (mode,
4684                                                     XEXP (SET_SRC (x), 0),
4685                                                     GEN_INT (pos))));
4686
4687               split = find_split_point (&SET_SRC (x), insn, true);
4688               if (split && split != &SET_SRC (x))
4689                 return split;
4690             }
4691           break;
4692
4693         case SIGN_EXTEND:
4694           inner = XEXP (SET_SRC (x), 0);
4695
4696           /* We can't optimize if either mode is a partial integer
4697              mode as we don't know how many bits are significant
4698              in those modes.  */
4699           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4700               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4701             break;
4702
4703           pos = 0;
4704           len = GET_MODE_PRECISION (GET_MODE (inner));
4705           unsignedp = 0;
4706           break;
4707
4708         case SIGN_EXTRACT:
4709         case ZERO_EXTRACT:
4710           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4711               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4712             {
4713               inner = XEXP (SET_SRC (x), 0);
4714               len = INTVAL (XEXP (SET_SRC (x), 1));
4715               pos = INTVAL (XEXP (SET_SRC (x), 2));
4716
4717               if (BITS_BIG_ENDIAN)
4718                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4719               unsignedp = (code == ZERO_EXTRACT);
4720             }
4721           break;
4722
4723         default:
4724           break;
4725         }
4726
4727       if (len && pos >= 0
4728           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4729         {
4730           enum machine_mode mode = GET_MODE (SET_SRC (x));
4731
4732           /* For unsigned, we have a choice of a shift followed by an
4733              AND or two shifts.  Use two shifts for field sizes where the
4734              constant might be too large.  We assume here that we can
4735              always at least get 8-bit constants in an AND insn, which is
4736              true for every current RISC.  */
4737
4738           if (unsignedp && len <= 8)
4739             {
4740               unsigned HOST_WIDE_INT mask
4741                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4742               SUBST (SET_SRC (x),
4743                      gen_rtx_AND (mode,
4744                                   gen_rtx_LSHIFTRT
4745                                   (mode, gen_lowpart (mode, inner),
4746                                    GEN_INT (pos)),
4747                                   gen_int_mode (mask, mode)));
4748
4749               split = find_split_point (&SET_SRC (x), insn, true);
4750               if (split && split != &SET_SRC (x))
4751                 return split;
4752             }
4753           else
4754             {
4755               SUBST (SET_SRC (x),
4756                      gen_rtx_fmt_ee
4757                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4758                       gen_rtx_ASHIFT (mode,
4759                                       gen_lowpart (mode, inner),
4760                                       GEN_INT (GET_MODE_PRECISION (mode)
4761                                                - len - pos)),
4762                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4763
4764               split = find_split_point (&SET_SRC (x), insn, true);
4765               if (split && split != &SET_SRC (x))
4766                 return split;
4767             }
4768         }
4769
4770       /* See if this is a simple operation with a constant as the second
4771          operand.  It might be that this constant is out of range and hence
4772          could be used as a split point.  */
4773       if (BINARY_P (SET_SRC (x))
4774           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4775           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4776               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4777                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4778         return &XEXP (SET_SRC (x), 1);
4779
4780       /* Finally, see if this is a simple operation with its first operand
4781          not in a register.  The operation might require this operand in a
4782          register, so return it as a split point.  We can always do this
4783          because if the first operand were another operation, we would have
4784          already found it as a split point.  */
4785       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4786           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4787         return &XEXP (SET_SRC (x), 0);
4788
4789       return 0;
4790
4791     case AND:
4792     case IOR:
4793       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4794          it is better to write this as (not (ior A B)) so we can split it.
4795          Similarly for IOR.  */
4796       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4797         {
4798           SUBST (*loc,
4799                  gen_rtx_NOT (GET_MODE (x),
4800                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4801                                               GET_MODE (x),
4802                                               XEXP (XEXP (x, 0), 0),
4803                                               XEXP (XEXP (x, 1), 0))));
4804           return find_split_point (loc, insn, set_src);
4805         }
4806
4807       /* Many RISC machines have a large set of logical insns.  If the
4808          second operand is a NOT, put it first so we will try to split the
4809          other operand first.  */
4810       if (GET_CODE (XEXP (x, 1)) == NOT)
4811         {
4812           rtx tem = XEXP (x, 0);
4813           SUBST (XEXP (x, 0), XEXP (x, 1));
4814           SUBST (XEXP (x, 1), tem);
4815         }
4816       break;
4817
4818     case PLUS:
4819     case MINUS:
4820       /* Canonicalization can produce (minus A (mult B C)), where C is a
4821          constant.  It may be better to try splitting (plus (mult B -C) A)
4822          instead if this isn't a multiply by a power of two.  */
4823       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4824           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4825           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4826         {
4827           enum machine_mode mode = GET_MODE (x);
4828           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4829           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4830           SUBST (*loc, gen_rtx_PLUS (mode,
4831                                      gen_rtx_MULT (mode,
4832                                                    XEXP (XEXP (x, 1), 0),
4833                                                    gen_int_mode (other_int,
4834                                                                  mode)),
4835                                      XEXP (x, 0)));
4836           return find_split_point (loc, insn, set_src);
4837         }
4838
4839       /* Split at a multiply-accumulate instruction.  However if this is
4840          the SET_SRC, we likely do not have such an instruction and it's
4841          worthless to try this split.  */
4842       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4843         return loc;
4844
4845     default:
4846       break;
4847     }
4848
4849   /* Otherwise, select our actions depending on our rtx class.  */
4850   switch (GET_RTX_CLASS (code))
4851     {
4852     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4853     case RTX_TERNARY:
4854       split = find_split_point (&XEXP (x, 2), insn, false);
4855       if (split)
4856         return split;
4857       /* ... fall through ...  */
4858     case RTX_BIN_ARITH:
4859     case RTX_COMM_ARITH:
4860     case RTX_COMPARE:
4861     case RTX_COMM_COMPARE:
4862       split = find_split_point (&XEXP (x, 1), insn, false);
4863       if (split)
4864         return split;
4865       /* ... fall through ...  */
4866     case RTX_UNARY:
4867       /* Some machines have (and (shift ...) ...) insns.  If X is not
4868          an AND, but XEXP (X, 0) is, use it as our split point.  */
4869       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4870         return &XEXP (x, 0);
4871
4872       split = find_split_point (&XEXP (x, 0), insn, false);
4873       if (split)
4874         return split;
4875       return loc;
4876
4877     default:
4878       /* Otherwise, we don't have a split point.  */
4879       return 0;
4880     }
4881 }
4882 \f
4883 /* Throughout X, replace FROM with TO, and return the result.
4884    The result is TO if X is FROM;
4885    otherwise the result is X, but its contents may have been modified.
4886    If they were modified, a record was made in undobuf so that
4887    undo_all will (among other things) return X to its original state.
4888
4889    If the number of changes necessary is too much to record to undo,
4890    the excess changes are not made, so the result is invalid.
4891    The changes already made can still be undone.
4892    undobuf.num_undo is incremented for such changes, so by testing that
4893    the caller can tell whether the result is valid.
4894
4895    `n_occurrences' is incremented each time FROM is replaced.
4896
4897    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4898
4899    IN_COND is nonzero if we are at the top level of a condition.
4900
4901    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4902    by copying if `n_occurrences' is nonzero.  */
4903
4904 static rtx
4905 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4906 {
4907   enum rtx_code code = GET_CODE (x);
4908   enum machine_mode op0_mode = VOIDmode;
4909   const char *fmt;
4910   int len, i;
4911   rtx new_rtx;
4912
4913 /* Two expressions are equal if they are identical copies of a shared
4914    RTX or if they are both registers with the same register number
4915    and mode.  */
4916
4917 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4918   ((X) == (Y)                                           \
4919    || (REG_P (X) && REG_P (Y)   \
4920        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4921
4922   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4923     {
4924       n_occurrences++;
4925       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4926     }
4927
4928   /* If X and FROM are the same register but different modes, they
4929      will not have been seen as equal above.  However, the log links code
4930      will make a LOG_LINKS entry for that case.  If we do nothing, we
4931      will try to rerecognize our original insn and, when it succeeds,
4932      we will delete the feeding insn, which is incorrect.
4933
4934      So force this insn not to match in this (rare) case.  */
4935   if (! in_dest && code == REG && REG_P (from)
4936       && reg_overlap_mentioned_p (x, from))
4937     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4938
4939   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4940      of which may contain things that can be combined.  */
4941   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4942     return x;
4943
4944   /* It is possible to have a subexpression appear twice in the insn.
4945      Suppose that FROM is a register that appears within TO.
4946      Then, after that subexpression has been scanned once by `subst',
4947      the second time it is scanned, TO may be found.  If we were
4948      to scan TO here, we would find FROM within it and create a
4949      self-referent rtl structure which is completely wrong.  */
4950   if (COMBINE_RTX_EQUAL_P (x, to))
4951     return to;
4952
4953   /* Parallel asm_operands need special attention because all of the
4954      inputs are shared across the arms.  Furthermore, unsharing the
4955      rtl results in recognition failures.  Failure to handle this case
4956      specially can result in circular rtl.
4957
4958      Solve this by doing a normal pass across the first entry of the
4959      parallel, and only processing the SET_DESTs of the subsequent
4960      entries.  Ug.  */
4961
4962   if (code == PARALLEL
4963       && GET_CODE (XVECEXP (x, 0, 0)) == SET
4964       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4965     {
4966       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
4967
4968       /* If this substitution failed, this whole thing fails.  */
4969       if (GET_CODE (new_rtx) == CLOBBER
4970           && XEXP (new_rtx, 0) == const0_rtx)
4971         return new_rtx;
4972
4973       SUBST (XVECEXP (x, 0, 0), new_rtx);
4974
4975       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4976         {
4977           rtx dest = SET_DEST (XVECEXP (x, 0, i));
4978
4979           if (!REG_P (dest)
4980               && GET_CODE (dest) != CC0
4981               && GET_CODE (dest) != PC)
4982             {
4983               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
4984
4985               /* If this substitution failed, this whole thing fails.  */
4986               if (GET_CODE (new_rtx) == CLOBBER
4987                   && XEXP (new_rtx, 0) == const0_rtx)
4988                 return new_rtx;
4989
4990               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4991             }
4992         }
4993     }
4994   else
4995     {
4996       len = GET_RTX_LENGTH (code);
4997       fmt = GET_RTX_FORMAT (code);
4998
4999       /* We don't need to process a SET_DEST that is a register, CC0,
5000          or PC, so set up to skip this common case.  All other cases
5001          where we want to suppress replacing something inside a
5002          SET_SRC are handled via the IN_DEST operand.  */
5003       if (code == SET
5004           && (REG_P (SET_DEST (x))
5005               || GET_CODE (SET_DEST (x)) == CC0
5006               || GET_CODE (SET_DEST (x)) == PC))
5007         fmt = "ie";
5008
5009       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5010          constant.  */
5011       if (fmt[0] == 'e')
5012         op0_mode = GET_MODE (XEXP (x, 0));
5013
5014       for (i = 0; i < len; i++)
5015         {
5016           if (fmt[i] == 'E')
5017             {
5018               int j;
5019               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5020                 {
5021                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5022                     {
5023                       new_rtx = (unique_copy && n_occurrences
5024                              ? copy_rtx (to) : to);
5025                       n_occurrences++;
5026                     }
5027                   else
5028                     {
5029                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5030                                        unique_copy);
5031
5032                       /* If this substitution failed, this whole thing
5033                          fails.  */
5034                       if (GET_CODE (new_rtx) == CLOBBER
5035                           && XEXP (new_rtx, 0) == const0_rtx)
5036                         return new_rtx;
5037                     }
5038
5039                   SUBST (XVECEXP (x, i, j), new_rtx);
5040                 }
5041             }
5042           else if (fmt[i] == 'e')
5043             {
5044               /* If this is a register being set, ignore it.  */
5045               new_rtx = XEXP (x, i);
5046               if (in_dest
5047                   && i == 0
5048                   && (((code == SUBREG || code == ZERO_EXTRACT)
5049                        && REG_P (new_rtx))
5050                       || code == STRICT_LOW_PART))
5051                 ;
5052
5053               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5054                 {
5055                   /* In general, don't install a subreg involving two
5056                      modes not tieable.  It can worsen register
5057                      allocation, and can even make invalid reload
5058                      insns, since the reg inside may need to be copied
5059                      from in the outside mode, and that may be invalid
5060                      if it is an fp reg copied in integer mode.
5061
5062                      We allow two exceptions to this: It is valid if
5063                      it is inside another SUBREG and the mode of that
5064                      SUBREG and the mode of the inside of TO is
5065                      tieable and it is valid if X is a SET that copies
5066                      FROM to CC0.  */
5067
5068                   if (GET_CODE (to) == SUBREG
5069                       && ! MODES_TIEABLE_P (GET_MODE (to),
5070                                             GET_MODE (SUBREG_REG (to)))
5071                       && ! (code == SUBREG
5072                             && MODES_TIEABLE_P (GET_MODE (x),
5073                                                 GET_MODE (SUBREG_REG (to))))
5074 #ifdef HAVE_cc0
5075                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5076 #endif
5077                       )
5078                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5079
5080 #ifdef CANNOT_CHANGE_MODE_CLASS
5081                   if (code == SUBREG
5082                       && REG_P (to)
5083                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5084                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5085                                                    GET_MODE (to),
5086                                                    GET_MODE (x)))
5087                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5088 #endif
5089
5090                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5091                   n_occurrences++;
5092                 }
5093               else
5094                 /* If we are in a SET_DEST, suppress most cases unless we
5095                    have gone inside a MEM, in which case we want to
5096                    simplify the address.  We assume here that things that
5097                    are actually part of the destination have their inner
5098                    parts in the first expression.  This is true for SUBREG,
5099                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5100                    things aside from REG and MEM that should appear in a
5101                    SET_DEST.  */
5102                 new_rtx = subst (XEXP (x, i), from, to,
5103                              (((in_dest
5104                                 && (code == SUBREG || code == STRICT_LOW_PART
5105                                     || code == ZERO_EXTRACT))
5106                                || code == SET)
5107                               && i == 0),
5108                                  code == IF_THEN_ELSE && i == 0,
5109                                  unique_copy);
5110
5111               /* If we found that we will have to reject this combination,
5112                  indicate that by returning the CLOBBER ourselves, rather than
5113                  an expression containing it.  This will speed things up as
5114                  well as prevent accidents where two CLOBBERs are considered
5115                  to be equal, thus producing an incorrect simplification.  */
5116
5117               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5118                 return new_rtx;
5119
5120               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5121                 {
5122                   enum machine_mode mode = GET_MODE (x);
5123
5124                   x = simplify_subreg (GET_MODE (x), new_rtx,
5125                                        GET_MODE (SUBREG_REG (x)),
5126                                        SUBREG_BYTE (x));
5127                   if (! x)
5128                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5129                 }
5130               else if (CONST_INT_P (new_rtx)
5131                        && GET_CODE (x) == ZERO_EXTEND)
5132                 {
5133                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5134                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5135                   gcc_assert (x);
5136                 }
5137               else
5138                 SUBST (XEXP (x, i), new_rtx);
5139             }
5140         }
5141     }
5142
5143   /* Check if we are loading something from the constant pool via float
5144      extension; in this case we would undo compress_float_constant
5145      optimization and degenerate constant load to an immediate value.  */
5146   if (GET_CODE (x) == FLOAT_EXTEND
5147       && MEM_P (XEXP (x, 0))
5148       && MEM_READONLY_P (XEXP (x, 0)))
5149     {
5150       rtx tmp = avoid_constant_pool_reference (x);
5151       if (x != tmp)
5152         return x;
5153     }
5154
5155   /* Try to simplify X.  If the simplification changed the code, it is likely
5156      that further simplification will help, so loop, but limit the number
5157      of repetitions that will be performed.  */
5158
5159   for (i = 0; i < 4; i++)
5160     {
5161       /* If X is sufficiently simple, don't bother trying to do anything
5162          with it.  */
5163       if (code != CONST_INT && code != REG && code != CLOBBER)
5164         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5165
5166       if (GET_CODE (x) == code)
5167         break;
5168
5169       code = GET_CODE (x);
5170
5171       /* We no longer know the original mode of operand 0 since we
5172          have changed the form of X)  */
5173       op0_mode = VOIDmode;
5174     }
5175
5176   return x;
5177 }
5178 \f
5179 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5180    outer level; call `subst' to simplify recursively.  Return the new
5181    expression.
5182
5183    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5184    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5185    of a condition.  */
5186
5187 static rtx
5188 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5189                       int in_cond)
5190 {
5191   enum rtx_code code = GET_CODE (x);
5192   enum machine_mode mode = GET_MODE (x);
5193   rtx temp;
5194   int i;
5195
5196   /* If this is a commutative operation, put a constant last and a complex
5197      expression first.  We don't need to do this for comparisons here.  */
5198   if (COMMUTATIVE_ARITH_P (x)
5199       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5200     {
5201       temp = XEXP (x, 0);
5202       SUBST (XEXP (x, 0), XEXP (x, 1));
5203       SUBST (XEXP (x, 1), temp);
5204     }
5205
5206   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5207      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5208      things.  Check for cases where both arms are testing the same
5209      condition.
5210
5211      Don't do anything if all operands are very simple.  */
5212
5213   if ((BINARY_P (x)
5214        && ((!OBJECT_P (XEXP (x, 0))
5215             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5216                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5217            || (!OBJECT_P (XEXP (x, 1))
5218                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5219                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5220       || (UNARY_P (x)
5221           && (!OBJECT_P (XEXP (x, 0))
5222                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5223                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5224     {
5225       rtx cond, true_rtx, false_rtx;
5226
5227       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5228       if (cond != 0
5229           /* If everything is a comparison, what we have is highly unlikely
5230              to be simpler, so don't use it.  */
5231           && ! (COMPARISON_P (x)
5232                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5233         {
5234           rtx cop1 = const0_rtx;
5235           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5236
5237           if (cond_code == NE && COMPARISON_P (cond))
5238             return x;
5239
5240           /* Simplify the alternative arms; this may collapse the true and
5241              false arms to store-flag values.  Be careful to use copy_rtx
5242              here since true_rtx or false_rtx might share RTL with x as a
5243              result of the if_then_else_cond call above.  */
5244           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5245           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5246
5247           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5248              is unlikely to be simpler.  */
5249           if (general_operand (true_rtx, VOIDmode)
5250               && general_operand (false_rtx, VOIDmode))
5251             {
5252               enum rtx_code reversed;
5253
5254               /* Restarting if we generate a store-flag expression will cause
5255                  us to loop.  Just drop through in this case.  */
5256
5257               /* If the result values are STORE_FLAG_VALUE and zero, we can
5258                  just make the comparison operation.  */
5259               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5260                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5261                                              cond, cop1);
5262               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5263                        && ((reversed = reversed_comparison_code_parts
5264                                         (cond_code, cond, cop1, NULL))
5265                            != UNKNOWN))
5266                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5267                                              cond, cop1);
5268
5269               /* Likewise, we can make the negate of a comparison operation
5270                  if the result values are - STORE_FLAG_VALUE and zero.  */
5271               else if (CONST_INT_P (true_rtx)
5272                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5273                        && false_rtx == const0_rtx)
5274                 x = simplify_gen_unary (NEG, mode,
5275                                         simplify_gen_relational (cond_code,
5276                                                                  mode, VOIDmode,
5277                                                                  cond, cop1),
5278                                         mode);
5279               else if (CONST_INT_P (false_rtx)
5280                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5281                        && true_rtx == const0_rtx
5282                        && ((reversed = reversed_comparison_code_parts
5283                                         (cond_code, cond, cop1, NULL))
5284                            != UNKNOWN))
5285                 x = simplify_gen_unary (NEG, mode,
5286                                         simplify_gen_relational (reversed,
5287                                                                  mode, VOIDmode,
5288                                                                  cond, cop1),
5289                                         mode);
5290               else
5291                 return gen_rtx_IF_THEN_ELSE (mode,
5292                                              simplify_gen_relational (cond_code,
5293                                                                       mode,
5294                                                                       VOIDmode,
5295                                                                       cond,
5296                                                                       cop1),
5297                                              true_rtx, false_rtx);
5298
5299               code = GET_CODE (x);
5300               op0_mode = VOIDmode;
5301             }
5302         }
5303     }
5304
5305   /* Try to fold this expression in case we have constants that weren't
5306      present before.  */
5307   temp = 0;
5308   switch (GET_RTX_CLASS (code))
5309     {
5310     case RTX_UNARY:
5311       if (op0_mode == VOIDmode)
5312         op0_mode = GET_MODE (XEXP (x, 0));
5313       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5314       break;
5315     case RTX_COMPARE:
5316     case RTX_COMM_COMPARE:
5317       {
5318         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5319         if (cmp_mode == VOIDmode)
5320           {
5321             cmp_mode = GET_MODE (XEXP (x, 1));
5322             if (cmp_mode == VOIDmode)
5323               cmp_mode = op0_mode;
5324           }
5325         temp = simplify_relational_operation (code, mode, cmp_mode,
5326                                               XEXP (x, 0), XEXP (x, 1));
5327       }
5328       break;
5329     case RTX_COMM_ARITH:
5330     case RTX_BIN_ARITH:
5331       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5332       break;
5333     case RTX_BITFIELD_OPS:
5334     case RTX_TERNARY:
5335       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5336                                          XEXP (x, 1), XEXP (x, 2));
5337       break;
5338     default:
5339       break;
5340     }
5341
5342   if (temp)
5343     {
5344       x = temp;
5345       code = GET_CODE (temp);
5346       op0_mode = VOIDmode;
5347       mode = GET_MODE (temp);
5348     }
5349
5350   /* First see if we can apply the inverse distributive law.  */
5351   if (code == PLUS || code == MINUS
5352       || code == AND || code == IOR || code == XOR)
5353     {
5354       x = apply_distributive_law (x);
5355       code = GET_CODE (x);
5356       op0_mode = VOIDmode;
5357     }
5358
5359   /* If CODE is an associative operation not otherwise handled, see if we
5360      can associate some operands.  This can win if they are constants or
5361      if they are logically related (i.e. (a & b) & a).  */
5362   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5363        || code == AND || code == IOR || code == XOR
5364        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5365       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5366           || (flag_associative_math && FLOAT_MODE_P (mode))))
5367     {
5368       if (GET_CODE (XEXP (x, 0)) == code)
5369         {
5370           rtx other = XEXP (XEXP (x, 0), 0);
5371           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5372           rtx inner_op1 = XEXP (x, 1);
5373           rtx inner;
5374
5375           /* Make sure we pass the constant operand if any as the second
5376              one if this is a commutative operation.  */
5377           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5378             {
5379               rtx tem = inner_op0;
5380               inner_op0 = inner_op1;
5381               inner_op1 = tem;
5382             }
5383           inner = simplify_binary_operation (code == MINUS ? PLUS
5384                                              : code == DIV ? MULT
5385                                              : code,
5386                                              mode, inner_op0, inner_op1);
5387
5388           /* For commutative operations, try the other pair if that one
5389              didn't simplify.  */
5390           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5391             {
5392               other = XEXP (XEXP (x, 0), 1);
5393               inner = simplify_binary_operation (code, mode,
5394                                                  XEXP (XEXP (x, 0), 0),
5395                                                  XEXP (x, 1));
5396             }
5397
5398           if (inner)
5399             return simplify_gen_binary (code, mode, other, inner);
5400         }
5401     }
5402
5403   /* A little bit of algebraic simplification here.  */
5404   switch (code)
5405     {
5406     case MEM:
5407       /* Ensure that our address has any ASHIFTs converted to MULT in case
5408          address-recognizing predicates are called later.  */
5409       temp = make_compound_operation (XEXP (x, 0), MEM);
5410       SUBST (XEXP (x, 0), temp);
5411       break;
5412
5413     case SUBREG:
5414       if (op0_mode == VOIDmode)
5415         op0_mode = GET_MODE (SUBREG_REG (x));
5416
5417       /* See if this can be moved to simplify_subreg.  */
5418       if (CONSTANT_P (SUBREG_REG (x))
5419           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5420              /* Don't call gen_lowpart if the inner mode
5421                 is VOIDmode and we cannot simplify it, as SUBREG without
5422                 inner mode is invalid.  */
5423           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5424               || gen_lowpart_common (mode, SUBREG_REG (x))))
5425         return gen_lowpart (mode, SUBREG_REG (x));
5426
5427       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5428         break;
5429       {
5430         rtx temp;
5431         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5432                                 SUBREG_BYTE (x));
5433         if (temp)
5434           return temp;
5435
5436         /* If op is known to have all lower bits zero, the result is zero.  */
5437         if (!in_dest
5438             && SCALAR_INT_MODE_P (mode)
5439             && SCALAR_INT_MODE_P (op0_mode)
5440             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5441             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5442             && HWI_COMPUTABLE_MODE_P (op0_mode)
5443             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5444                 & GET_MODE_MASK (mode)) == 0)
5445           return CONST0_RTX (mode);
5446       }
5447
5448       /* Don't change the mode of the MEM if that would change the meaning
5449          of the address.  */
5450       if (MEM_P (SUBREG_REG (x))
5451           && (MEM_VOLATILE_P (SUBREG_REG (x))
5452               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5453                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5454         return gen_rtx_CLOBBER (mode, const0_rtx);
5455
5456       /* Note that we cannot do any narrowing for non-constants since
5457          we might have been counting on using the fact that some bits were
5458          zero.  We now do this in the SET.  */
5459
5460       break;
5461
5462     case NEG:
5463       temp = expand_compound_operation (XEXP (x, 0));
5464
5465       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5466          replaced by (lshiftrt X C).  This will convert
5467          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5468
5469       if (GET_CODE (temp) == ASHIFTRT
5470           && CONST_INT_P (XEXP (temp, 1))
5471           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5472         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5473                                      INTVAL (XEXP (temp, 1)));
5474
5475       /* If X has only a single bit that might be nonzero, say, bit I, convert
5476          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5477          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5478          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5479          or a SUBREG of one since we'd be making the expression more
5480          complex if it was just a register.  */
5481
5482       if (!REG_P (temp)
5483           && ! (GET_CODE (temp) == SUBREG
5484                 && REG_P (SUBREG_REG (temp)))
5485           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5486         {
5487           rtx temp1 = simplify_shift_const
5488             (NULL_RTX, ASHIFTRT, mode,
5489              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5490                                    GET_MODE_PRECISION (mode) - 1 - i),
5491              GET_MODE_PRECISION (mode) - 1 - i);
5492
5493           /* If all we did was surround TEMP with the two shifts, we
5494              haven't improved anything, so don't use it.  Otherwise,
5495              we are better off with TEMP1.  */
5496           if (GET_CODE (temp1) != ASHIFTRT
5497               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5498               || XEXP (XEXP (temp1, 0), 0) != temp)
5499             return temp1;
5500         }
5501       break;
5502
5503     case TRUNCATE:
5504       /* We can't handle truncation to a partial integer mode here
5505          because we don't know the real bitsize of the partial
5506          integer mode.  */
5507       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5508         break;
5509
5510       if (HWI_COMPUTABLE_MODE_P (mode))
5511         SUBST (XEXP (x, 0),
5512                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5513                               GET_MODE_MASK (mode), 0));
5514
5515       /* We can truncate a constant value and return it.  */
5516       if (CONST_INT_P (XEXP (x, 0)))
5517         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5518
5519       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5520          whose value is a comparison can be replaced with a subreg if
5521          STORE_FLAG_VALUE permits.  */
5522       if (HWI_COMPUTABLE_MODE_P (mode)
5523           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5524           && (temp = get_last_value (XEXP (x, 0)))
5525           && COMPARISON_P (temp))
5526         return gen_lowpart (mode, XEXP (x, 0));
5527       break;
5528
5529     case CONST:
5530       /* (const (const X)) can become (const X).  Do it this way rather than
5531          returning the inner CONST since CONST can be shared with a
5532          REG_EQUAL note.  */
5533       if (GET_CODE (XEXP (x, 0)) == CONST)
5534         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5535       break;
5536
5537 #ifdef HAVE_lo_sum
5538     case LO_SUM:
5539       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5540          can add in an offset.  find_split_point will split this address up
5541          again if it doesn't match.  */
5542       if (GET_CODE (XEXP (x, 0)) == HIGH
5543           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5544         return XEXP (x, 1);
5545       break;
5546 #endif
5547
5548     case PLUS:
5549       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5550          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5551          bit-field and can be replaced by either a sign_extend or a
5552          sign_extract.  The `and' may be a zero_extend and the two
5553          <c>, -<c> constants may be reversed.  */
5554       if (GET_CODE (XEXP (x, 0)) == XOR
5555           && CONST_INT_P (XEXP (x, 1))
5556           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5557           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5558           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5559               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5560           && HWI_COMPUTABLE_MODE_P (mode)
5561           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5562                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5563                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5564                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5565               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5566                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5567                       == (unsigned int) i + 1))))
5568         return simplify_shift_const
5569           (NULL_RTX, ASHIFTRT, mode,
5570            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5571                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5572                                  GET_MODE_PRECISION (mode) - (i + 1)),
5573            GET_MODE_PRECISION (mode) - (i + 1));
5574
5575       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5576          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5577          the bitsize of the mode - 1.  This allows simplification of
5578          "a = (b & 8) == 0;"  */
5579       if (XEXP (x, 1) == constm1_rtx
5580           && !REG_P (XEXP (x, 0))
5581           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5582                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5583           && nonzero_bits (XEXP (x, 0), mode) == 1)
5584         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5585            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5586                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5587                                  GET_MODE_PRECISION (mode) - 1),
5588            GET_MODE_PRECISION (mode) - 1);
5589
5590       /* If we are adding two things that have no bits in common, convert
5591          the addition into an IOR.  This will often be further simplified,
5592          for example in cases like ((a & 1) + (a & 2)), which can
5593          become a & 3.  */
5594
5595       if (HWI_COMPUTABLE_MODE_P (mode)
5596           && (nonzero_bits (XEXP (x, 0), mode)
5597               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5598         {
5599           /* Try to simplify the expression further.  */
5600           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5601           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5602
5603           /* If we could, great.  If not, do not go ahead with the IOR
5604              replacement, since PLUS appears in many special purpose
5605              address arithmetic instructions.  */
5606           if (GET_CODE (temp) != CLOBBER
5607               && (GET_CODE (temp) != IOR
5608                   || ((XEXP (temp, 0) != XEXP (x, 0)
5609                        || XEXP (temp, 1) != XEXP (x, 1))
5610                       && (XEXP (temp, 0) != XEXP (x, 1)
5611                           || XEXP (temp, 1) != XEXP (x, 0)))))
5612             return temp;
5613         }
5614       break;
5615
5616     case MINUS:
5617       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5618          (and <foo> (const_int pow2-1))  */
5619       if (GET_CODE (XEXP (x, 1)) == AND
5620           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5621           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5622           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5623         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5624                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5625       break;
5626
5627     case MULT:
5628       /* If we have (mult (plus A B) C), apply the distributive law and then
5629          the inverse distributive law to see if things simplify.  This
5630          occurs mostly in addresses, often when unrolling loops.  */
5631
5632       if (GET_CODE (XEXP (x, 0)) == PLUS)
5633         {
5634           rtx result = distribute_and_simplify_rtx (x, 0);
5635           if (result)
5636             return result;
5637         }
5638
5639       /* Try simplify a*(b/c) as (a*b)/c.  */
5640       if (FLOAT_MODE_P (mode) && flag_associative_math
5641           && GET_CODE (XEXP (x, 0)) == DIV)
5642         {
5643           rtx tem = simplify_binary_operation (MULT, mode,
5644                                                XEXP (XEXP (x, 0), 0),
5645                                                XEXP (x, 1));
5646           if (tem)
5647             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5648         }
5649       break;
5650
5651     case UDIV:
5652       /* If this is a divide by a power of two, treat it as a shift if
5653          its first operand is a shift.  */
5654       if (CONST_INT_P (XEXP (x, 1))
5655           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5656           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5657               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5658               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5659               || GET_CODE (XEXP (x, 0)) == ROTATE
5660               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5661         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5662       break;
5663
5664     case EQ:  case NE:
5665     case GT:  case GTU:  case GE:  case GEU:
5666     case LT:  case LTU:  case LE:  case LEU:
5667     case UNEQ:  case LTGT:
5668     case UNGT:  case UNGE:
5669     case UNLT:  case UNLE:
5670     case UNORDERED: case ORDERED:
5671       /* If the first operand is a condition code, we can't do anything
5672          with it.  */
5673       if (GET_CODE (XEXP (x, 0)) == COMPARE
5674           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5675               && ! CC0_P (XEXP (x, 0))))
5676         {
5677           rtx op0 = XEXP (x, 0);
5678           rtx op1 = XEXP (x, 1);
5679           enum rtx_code new_code;
5680
5681           if (GET_CODE (op0) == COMPARE)
5682             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5683
5684           /* Simplify our comparison, if possible.  */
5685           new_code = simplify_comparison (code, &op0, &op1);
5686
5687           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5688              if only the low-order bit is possibly nonzero in X (such as when
5689              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5690              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5691              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5692              (plus X 1).
5693
5694              Remove any ZERO_EXTRACT we made when thinking this was a
5695              comparison.  It may now be simpler to use, e.g., an AND.  If a
5696              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5697              the call to make_compound_operation in the SET case.
5698
5699              Don't apply these optimizations if the caller would
5700              prefer a comparison rather than a value.
5701              E.g., for the condition in an IF_THEN_ELSE most targets need
5702              an explicit comparison.  */
5703
5704           if (in_cond)
5705             ;
5706
5707           else if (STORE_FLAG_VALUE == 1
5708               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5709               && op1 == const0_rtx
5710               && mode == GET_MODE (op0)
5711               && nonzero_bits (op0, mode) == 1)
5712             return gen_lowpart (mode,
5713                                 expand_compound_operation (op0));
5714
5715           else if (STORE_FLAG_VALUE == 1
5716                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5717                    && op1 == const0_rtx
5718                    && mode == GET_MODE (op0)
5719                    && (num_sign_bit_copies (op0, mode)
5720                        == GET_MODE_PRECISION (mode)))
5721             {
5722               op0 = expand_compound_operation (op0);
5723               return simplify_gen_unary (NEG, mode,
5724                                          gen_lowpart (mode, op0),
5725                                          mode);
5726             }
5727
5728           else if (STORE_FLAG_VALUE == 1
5729                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5730                    && op1 == const0_rtx
5731                    && mode == GET_MODE (op0)
5732                    && nonzero_bits (op0, mode) == 1)
5733             {
5734               op0 = expand_compound_operation (op0);
5735               return simplify_gen_binary (XOR, mode,
5736                                           gen_lowpart (mode, op0),
5737                                           const1_rtx);
5738             }
5739
5740           else if (STORE_FLAG_VALUE == 1
5741                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5742                    && op1 == const0_rtx
5743                    && mode == GET_MODE (op0)
5744                    && (num_sign_bit_copies (op0, mode)
5745                        == GET_MODE_PRECISION (mode)))
5746             {
5747               op0 = expand_compound_operation (op0);
5748               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5749             }
5750
5751           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5752              those above.  */
5753           if (in_cond)
5754             ;
5755
5756           else if (STORE_FLAG_VALUE == -1
5757               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5758               && op1 == const0_rtx
5759               && (num_sign_bit_copies (op0, mode)
5760                   == GET_MODE_PRECISION (mode)))
5761             return gen_lowpart (mode,
5762                                 expand_compound_operation (op0));
5763
5764           else if (STORE_FLAG_VALUE == -1
5765                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5766                    && op1 == const0_rtx
5767                    && mode == GET_MODE (op0)
5768                    && nonzero_bits (op0, mode) == 1)
5769             {
5770               op0 = expand_compound_operation (op0);
5771               return simplify_gen_unary (NEG, mode,
5772                                          gen_lowpart (mode, op0),
5773                                          mode);
5774             }
5775
5776           else if (STORE_FLAG_VALUE == -1
5777                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5778                    && op1 == const0_rtx
5779                    && mode == GET_MODE (op0)
5780                    && (num_sign_bit_copies (op0, mode)
5781                        == GET_MODE_PRECISION (mode)))
5782             {
5783               op0 = expand_compound_operation (op0);
5784               return simplify_gen_unary (NOT, mode,
5785                                          gen_lowpart (mode, op0),
5786                                          mode);
5787             }
5788
5789           /* If X is 0/1, (eq X 0) is X-1.  */
5790           else if (STORE_FLAG_VALUE == -1
5791                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5792                    && op1 == const0_rtx
5793                    && mode == GET_MODE (op0)
5794                    && nonzero_bits (op0, mode) == 1)
5795             {
5796               op0 = expand_compound_operation (op0);
5797               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5798             }
5799
5800           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5801              one bit that might be nonzero, we can convert (ne x 0) to
5802              (ashift x c) where C puts the bit in the sign bit.  Remove any
5803              AND with STORE_FLAG_VALUE when we are done, since we are only
5804              going to test the sign bit.  */
5805           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5806               && HWI_COMPUTABLE_MODE_P (mode)
5807               && val_signbit_p (mode, STORE_FLAG_VALUE)
5808               && op1 == const0_rtx
5809               && mode == GET_MODE (op0)
5810               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5811             {
5812               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5813                                         expand_compound_operation (op0),
5814                                         GET_MODE_PRECISION (mode) - 1 - i);
5815               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5816                 return XEXP (x, 0);
5817               else
5818                 return x;
5819             }
5820
5821           /* If the code changed, return a whole new comparison.
5822              We also need to avoid using SUBST in cases where
5823              simplify_comparison has widened a comparison with a CONST_INT,
5824              since in that case the wider CONST_INT may fail the sanity
5825              checks in do_SUBST.  */
5826           if (new_code != code
5827               || (CONST_INT_P (op1)
5828                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5829                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5830             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5831
5832           /* Otherwise, keep this operation, but maybe change its operands.
5833              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5834           SUBST (XEXP (x, 0), op0);
5835           SUBST (XEXP (x, 1), op1);
5836         }
5837       break;
5838
5839     case IF_THEN_ELSE:
5840       return simplify_if_then_else (x);
5841
5842     case ZERO_EXTRACT:
5843     case SIGN_EXTRACT:
5844     case ZERO_EXTEND:
5845     case SIGN_EXTEND:
5846       /* If we are processing SET_DEST, we are done.  */
5847       if (in_dest)
5848         return x;
5849
5850       return expand_compound_operation (x);
5851
5852     case SET:
5853       return simplify_set (x);
5854
5855     case AND:
5856     case IOR:
5857       return simplify_logical (x);
5858
5859     case ASHIFT:
5860     case LSHIFTRT:
5861     case ASHIFTRT:
5862     case ROTATE:
5863     case ROTATERT:
5864       /* If this is a shift by a constant amount, simplify it.  */
5865       if (CONST_INT_P (XEXP (x, 1)))
5866         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5867                                      INTVAL (XEXP (x, 1)));
5868
5869       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5870         SUBST (XEXP (x, 1),
5871                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5872                               ((unsigned HOST_WIDE_INT) 1
5873                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5874                               - 1,
5875                               0));
5876       break;
5877
5878     default:
5879       break;
5880     }
5881
5882   return x;
5883 }
5884 \f
5885 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5886
5887 static rtx
5888 simplify_if_then_else (rtx x)
5889 {
5890   enum machine_mode mode = GET_MODE (x);
5891   rtx cond = XEXP (x, 0);
5892   rtx true_rtx = XEXP (x, 1);
5893   rtx false_rtx = XEXP (x, 2);
5894   enum rtx_code true_code = GET_CODE (cond);
5895   int comparison_p = COMPARISON_P (cond);
5896   rtx temp;
5897   int i;
5898   enum rtx_code false_code;
5899   rtx reversed;
5900
5901   /* Simplify storing of the truth value.  */
5902   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5903     return simplify_gen_relational (true_code, mode, VOIDmode,
5904                                     XEXP (cond, 0), XEXP (cond, 1));
5905
5906   /* Also when the truth value has to be reversed.  */
5907   if (comparison_p
5908       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5909       && (reversed = reversed_comparison (cond, mode)))
5910     return reversed;
5911
5912   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5913      in it is being compared against certain values.  Get the true and false
5914      comparisons and see if that says anything about the value of each arm.  */
5915
5916   if (comparison_p
5917       && ((false_code = reversed_comparison_code (cond, NULL))
5918           != UNKNOWN)
5919       && REG_P (XEXP (cond, 0)))
5920     {
5921       HOST_WIDE_INT nzb;
5922       rtx from = XEXP (cond, 0);
5923       rtx true_val = XEXP (cond, 1);
5924       rtx false_val = true_val;
5925       int swapped = 0;
5926
5927       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5928
5929       if (false_code == EQ)
5930         {
5931           swapped = 1, true_code = EQ, false_code = NE;
5932           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5933         }
5934
5935       /* If we are comparing against zero and the expression being tested has
5936          only a single bit that might be nonzero, that is its value when it is
5937          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5938
5939       if (true_code == EQ && true_val == const0_rtx
5940           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5941         {
5942           false_code = EQ;
5943           false_val = gen_int_mode (nzb, GET_MODE (from));
5944         }
5945       else if (true_code == EQ && true_val == const0_rtx
5946                && (num_sign_bit_copies (from, GET_MODE (from))
5947                    == GET_MODE_PRECISION (GET_MODE (from))))
5948         {
5949           false_code = EQ;
5950           false_val = constm1_rtx;
5951         }
5952
5953       /* Now simplify an arm if we know the value of the register in the
5954          branch and it is used in the arm.  Be careful due to the potential
5955          of locally-shared RTL.  */
5956
5957       if (reg_mentioned_p (from, true_rtx))
5958         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5959                                       from, true_val),
5960                           pc_rtx, pc_rtx, 0, 0, 0);
5961       if (reg_mentioned_p (from, false_rtx))
5962         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5963                                    from, false_val),
5964                            pc_rtx, pc_rtx, 0, 0, 0);
5965
5966       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5967       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5968
5969       true_rtx = XEXP (x, 1);
5970       false_rtx = XEXP (x, 2);
5971       true_code = GET_CODE (cond);
5972     }
5973
5974   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5975      reversed, do so to avoid needing two sets of patterns for
5976      subtract-and-branch insns.  Similarly if we have a constant in the true
5977      arm, the false arm is the same as the first operand of the comparison, or
5978      the false arm is more complicated than the true arm.  */
5979
5980   if (comparison_p
5981       && reversed_comparison_code (cond, NULL) != UNKNOWN
5982       && (true_rtx == pc_rtx
5983           || (CONSTANT_P (true_rtx)
5984               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5985           || true_rtx == const0_rtx
5986           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5987           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5988               && !OBJECT_P (false_rtx))
5989           || reg_mentioned_p (true_rtx, false_rtx)
5990           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5991     {
5992       true_code = reversed_comparison_code (cond, NULL);
5993       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5994       SUBST (XEXP (x, 1), false_rtx);
5995       SUBST (XEXP (x, 2), true_rtx);
5996
5997       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5998       cond = XEXP (x, 0);
5999
6000       /* It is possible that the conditional has been simplified out.  */
6001       true_code = GET_CODE (cond);
6002       comparison_p = COMPARISON_P (cond);
6003     }
6004
6005   /* If the two arms are identical, we don't need the comparison.  */
6006
6007   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6008     return true_rtx;
6009
6010   /* Convert a == b ? b : a to "a".  */
6011   if (true_code == EQ && ! side_effects_p (cond)
6012       && !HONOR_NANS (mode)
6013       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6014       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6015     return false_rtx;
6016   else if (true_code == NE && ! side_effects_p (cond)
6017            && !HONOR_NANS (mode)
6018            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6019            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6020     return true_rtx;
6021
6022   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6023
6024   if (GET_MODE_CLASS (mode) == MODE_INT
6025       && comparison_p
6026       && XEXP (cond, 1) == const0_rtx
6027       && GET_CODE (false_rtx) == NEG
6028       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6029       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6030       && ! side_effects_p (true_rtx))
6031     switch (true_code)
6032       {
6033       case GT:
6034       case GE:
6035         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6036       case LT:
6037       case LE:
6038         return
6039           simplify_gen_unary (NEG, mode,
6040                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6041                               mode);
6042       default:
6043         break;
6044       }
6045
6046   /* Look for MIN or MAX.  */
6047
6048   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6049       && comparison_p
6050       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6051       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6052       && ! side_effects_p (cond))
6053     switch (true_code)
6054       {
6055       case GE:
6056       case GT:
6057         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6058       case LE:
6059       case LT:
6060         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6061       case GEU:
6062       case GTU:
6063         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6064       case LEU:
6065       case LTU:
6066         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6067       default:
6068         break;
6069       }
6070
6071   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6072      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6073      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6074      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6075      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6076      neither 1 or -1, but it isn't worth checking for.  */
6077
6078   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6079       && comparison_p
6080       && GET_MODE_CLASS (mode) == MODE_INT
6081       && ! side_effects_p (x))
6082     {
6083       rtx t = make_compound_operation (true_rtx, SET);
6084       rtx f = make_compound_operation (false_rtx, SET);
6085       rtx cond_op0 = XEXP (cond, 0);
6086       rtx cond_op1 = XEXP (cond, 1);
6087       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6088       enum machine_mode m = mode;
6089       rtx z = 0, c1 = NULL_RTX;
6090
6091       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6092            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6093            || GET_CODE (t) == ASHIFT
6094            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6095           && rtx_equal_p (XEXP (t, 0), f))
6096         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6097
6098       /* If an identity-zero op is commutative, check whether there
6099          would be a match if we swapped the operands.  */
6100       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6101                 || GET_CODE (t) == XOR)
6102                && rtx_equal_p (XEXP (t, 1), f))
6103         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6104       else if (GET_CODE (t) == SIGN_EXTEND
6105                && (GET_CODE (XEXP (t, 0)) == PLUS
6106                    || GET_CODE (XEXP (t, 0)) == MINUS
6107                    || GET_CODE (XEXP (t, 0)) == IOR
6108                    || GET_CODE (XEXP (t, 0)) == XOR
6109                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6110                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6111                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6112                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6113                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6114                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6115                && (num_sign_bit_copies (f, GET_MODE (f))
6116                    > (unsigned int)
6117                      (GET_MODE_PRECISION (mode)
6118                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6119         {
6120           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6121           extend_op = SIGN_EXTEND;
6122           m = GET_MODE (XEXP (t, 0));
6123         }
6124       else if (GET_CODE (t) == SIGN_EXTEND
6125                && (GET_CODE (XEXP (t, 0)) == PLUS
6126                    || GET_CODE (XEXP (t, 0)) == IOR
6127                    || GET_CODE (XEXP (t, 0)) == XOR)
6128                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6129                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6130                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6131                && (num_sign_bit_copies (f, GET_MODE (f))
6132                    > (unsigned int)
6133                      (GET_MODE_PRECISION (mode)
6134                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6135         {
6136           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6137           extend_op = SIGN_EXTEND;
6138           m = GET_MODE (XEXP (t, 0));
6139         }
6140       else if (GET_CODE (t) == ZERO_EXTEND
6141                && (GET_CODE (XEXP (t, 0)) == PLUS
6142                    || GET_CODE (XEXP (t, 0)) == MINUS
6143                    || GET_CODE (XEXP (t, 0)) == IOR
6144                    || GET_CODE (XEXP (t, 0)) == XOR
6145                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6146                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6147                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6148                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6149                && HWI_COMPUTABLE_MODE_P (mode)
6150                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6151                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6152                && ((nonzero_bits (f, GET_MODE (f))
6153                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6154                    == 0))
6155         {
6156           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6157           extend_op = ZERO_EXTEND;
6158           m = GET_MODE (XEXP (t, 0));
6159         }
6160       else if (GET_CODE (t) == ZERO_EXTEND
6161                && (GET_CODE (XEXP (t, 0)) == PLUS
6162                    || GET_CODE (XEXP (t, 0)) == IOR
6163                    || GET_CODE (XEXP (t, 0)) == XOR)
6164                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6165                && HWI_COMPUTABLE_MODE_P (mode)
6166                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6167                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6168                && ((nonzero_bits (f, GET_MODE (f))
6169                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6170                    == 0))
6171         {
6172           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6173           extend_op = ZERO_EXTEND;
6174           m = GET_MODE (XEXP (t, 0));
6175         }
6176
6177       if (z)
6178         {
6179           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6180                                                  cond_op0, cond_op1),
6181                         pc_rtx, pc_rtx, 0, 0, 0);
6182           temp = simplify_gen_binary (MULT, m, temp,
6183                                       simplify_gen_binary (MULT, m, c1,
6184                                                            const_true_rtx));
6185           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6186           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6187
6188           if (extend_op != UNKNOWN)
6189             temp = simplify_gen_unary (extend_op, mode, temp, m);
6190
6191           return temp;
6192         }
6193     }
6194
6195   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6196      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6197      negation of a single bit, we can convert this operation to a shift.  We
6198      can actually do this more generally, but it doesn't seem worth it.  */
6199
6200   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6201       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6202       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6203            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6204           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6205                == GET_MODE_PRECISION (mode))
6206               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6207     return
6208       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6209                             gen_lowpart (mode, XEXP (cond, 0)), i);
6210
6211   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6212   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6213       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6214       && GET_MODE (XEXP (cond, 0)) == mode
6215       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6216           == nonzero_bits (XEXP (cond, 0), mode)
6217       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6218     return XEXP (cond, 0);
6219
6220   return x;
6221 }
6222 \f
6223 /* Simplify X, a SET expression.  Return the new expression.  */
6224
6225 static rtx
6226 simplify_set (rtx x)
6227 {
6228   rtx src = SET_SRC (x);
6229   rtx dest = SET_DEST (x);
6230   enum machine_mode mode
6231     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6232   rtx other_insn;
6233   rtx *cc_use;
6234
6235   /* (set (pc) (return)) gets written as (return).  */
6236   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6237     return src;
6238
6239   /* Now that we know for sure which bits of SRC we are using, see if we can
6240      simplify the expression for the object knowing that we only need the
6241      low-order bits.  */
6242
6243   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6244     {
6245       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6246       SUBST (SET_SRC (x), src);
6247     }
6248
6249   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6250      the comparison result and try to simplify it unless we already have used
6251      undobuf.other_insn.  */
6252   if ((GET_MODE_CLASS (mode) == MODE_CC
6253        || GET_CODE (src) == COMPARE
6254        || CC0_P (dest))
6255       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6256       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6257       && COMPARISON_P (*cc_use)
6258       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6259     {
6260       enum rtx_code old_code = GET_CODE (*cc_use);
6261       enum rtx_code new_code;
6262       rtx op0, op1, tmp;
6263       int other_changed = 0;
6264       rtx inner_compare = NULL_RTX;
6265       enum machine_mode compare_mode = GET_MODE (dest);
6266
6267       if (GET_CODE (src) == COMPARE)
6268         {
6269           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6270           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6271             {
6272               inner_compare = op0;
6273               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6274             }
6275         }
6276       else
6277         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6278
6279       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6280                                            op0, op1);
6281       if (!tmp)
6282         new_code = old_code;
6283       else if (!CONSTANT_P (tmp))
6284         {
6285           new_code = GET_CODE (tmp);
6286           op0 = XEXP (tmp, 0);
6287           op1 = XEXP (tmp, 1);
6288         }
6289       else
6290         {
6291           rtx pat = PATTERN (other_insn);
6292           undobuf.other_insn = other_insn;
6293           SUBST (*cc_use, tmp);
6294
6295           /* Attempt to simplify CC user.  */
6296           if (GET_CODE (pat) == SET)
6297             {
6298               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6299               if (new_rtx != NULL_RTX)
6300                 SUBST (SET_SRC (pat), new_rtx);
6301             }
6302
6303           /* Convert X into a no-op move.  */
6304           SUBST (SET_DEST (x), pc_rtx);
6305           SUBST (SET_SRC (x), pc_rtx);
6306           return x;
6307         }
6308
6309       /* Simplify our comparison, if possible.  */
6310       new_code = simplify_comparison (new_code, &op0, &op1);
6311
6312 #ifdef SELECT_CC_MODE
6313       /* If this machine has CC modes other than CCmode, check to see if we
6314          need to use a different CC mode here.  */
6315       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6316         compare_mode = GET_MODE (op0);
6317       else if (inner_compare
6318                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6319                && new_code == old_code
6320                && op0 == XEXP (inner_compare, 0)
6321                && op1 == XEXP (inner_compare, 1))
6322         compare_mode = GET_MODE (inner_compare);
6323       else
6324         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6325
6326 #ifndef HAVE_cc0
6327       /* If the mode changed, we have to change SET_DEST, the mode in the
6328          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6329          a hard register, just build new versions with the proper mode.  If it
6330          is a pseudo, we lose unless it is only time we set the pseudo, in
6331          which case we can safely change its mode.  */
6332       if (compare_mode != GET_MODE (dest))
6333         {
6334           if (can_change_dest_mode (dest, 0, compare_mode))
6335             {
6336               unsigned int regno = REGNO (dest);
6337               rtx new_dest;
6338
6339               if (regno < FIRST_PSEUDO_REGISTER)
6340                 new_dest = gen_rtx_REG (compare_mode, regno);
6341               else
6342                 {
6343                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6344                   new_dest = regno_reg_rtx[regno];
6345                 }
6346
6347               SUBST (SET_DEST (x), new_dest);
6348               SUBST (XEXP (*cc_use, 0), new_dest);
6349               other_changed = 1;
6350
6351               dest = new_dest;
6352             }
6353         }
6354 #endif  /* cc0 */
6355 #endif  /* SELECT_CC_MODE */
6356
6357       /* If the code changed, we have to build a new comparison in
6358          undobuf.other_insn.  */
6359       if (new_code != old_code)
6360         {
6361           int other_changed_previously = other_changed;
6362           unsigned HOST_WIDE_INT mask;
6363           rtx old_cc_use = *cc_use;
6364
6365           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6366                                           dest, const0_rtx));
6367           other_changed = 1;
6368
6369           /* If the only change we made was to change an EQ into an NE or
6370              vice versa, OP0 has only one bit that might be nonzero, and OP1
6371              is zero, check if changing the user of the condition code will
6372              produce a valid insn.  If it won't, we can keep the original code
6373              in that insn by surrounding our operation with an XOR.  */
6374
6375           if (((old_code == NE && new_code == EQ)
6376                || (old_code == EQ && new_code == NE))
6377               && ! other_changed_previously && op1 == const0_rtx
6378               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6379               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6380             {
6381               rtx pat = PATTERN (other_insn), note = 0;
6382
6383               if ((recog_for_combine (&pat, other_insn, &note) < 0
6384                    && ! check_asm_operands (pat)))
6385                 {
6386                   *cc_use = old_cc_use;
6387                   other_changed = 0;
6388
6389                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6390                                              gen_int_mode (mask,
6391                                                            GET_MODE (op0)));
6392                 }
6393             }
6394         }
6395
6396       if (other_changed)
6397         undobuf.other_insn = other_insn;
6398
6399       /* Otherwise, if we didn't previously have a COMPARE in the
6400          correct mode, we need one.  */
6401       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6402         {
6403           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6404           src = SET_SRC (x);
6405         }
6406       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6407         {
6408           SUBST (SET_SRC (x), op0);
6409           src = SET_SRC (x);
6410         }
6411       /* Otherwise, update the COMPARE if needed.  */
6412       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6413         {
6414           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6415           src = SET_SRC (x);
6416         }
6417     }
6418   else
6419     {
6420       /* Get SET_SRC in a form where we have placed back any
6421          compound expressions.  Then do the checks below.  */
6422       src = make_compound_operation (src, SET);
6423       SUBST (SET_SRC (x), src);
6424     }
6425
6426   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6427      and X being a REG or (subreg (reg)), we may be able to convert this to
6428      (set (subreg:m2 x) (op)).
6429
6430      We can always do this if M1 is narrower than M2 because that means that
6431      we only care about the low bits of the result.
6432
6433      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6434      perform a narrower operation than requested since the high-order bits will
6435      be undefined.  On machine where it is defined, this transformation is safe
6436      as long as M1 and M2 have the same number of words.  */
6437
6438   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6439       && !OBJECT_P (SUBREG_REG (src))
6440       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6441            / UNITS_PER_WORD)
6442           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6443                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6444 #ifndef WORD_REGISTER_OPERATIONS
6445       && (GET_MODE_SIZE (GET_MODE (src))
6446         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6447 #endif
6448 #ifdef CANNOT_CHANGE_MODE_CLASS
6449       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6450             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6451                                          GET_MODE (SUBREG_REG (src)),
6452                                          GET_MODE (src)))
6453 #endif
6454       && (REG_P (dest)
6455           || (GET_CODE (dest) == SUBREG
6456               && REG_P (SUBREG_REG (dest)))))
6457     {
6458       SUBST (SET_DEST (x),
6459              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6460                                       dest));
6461       SUBST (SET_SRC (x), SUBREG_REG (src));
6462
6463       src = SET_SRC (x), dest = SET_DEST (x);
6464     }
6465
6466 #ifdef HAVE_cc0
6467   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6468      in SRC.  */
6469   if (dest == cc0_rtx
6470       && GET_CODE (src) == SUBREG
6471       && subreg_lowpart_p (src)
6472       && (GET_MODE_PRECISION (GET_MODE (src))
6473           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6474     {
6475       rtx inner = SUBREG_REG (src);
6476       enum machine_mode inner_mode = GET_MODE (inner);
6477
6478       /* Here we make sure that we don't have a sign bit on.  */
6479       if (val_signbit_known_clear_p (GET_MODE (src),
6480                                      nonzero_bits (inner, inner_mode)))
6481         {
6482           SUBST (SET_SRC (x), inner);
6483           src = SET_SRC (x);
6484         }
6485     }
6486 #endif
6487
6488 #ifdef LOAD_EXTEND_OP
6489   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6490      would require a paradoxical subreg.  Replace the subreg with a
6491      zero_extend to avoid the reload that would otherwise be required.  */
6492
6493   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6494       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6495       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6496       && SUBREG_BYTE (src) == 0
6497       && paradoxical_subreg_p (src)
6498       && MEM_P (SUBREG_REG (src)))
6499     {
6500       SUBST (SET_SRC (x),
6501              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6502                             GET_MODE (src), SUBREG_REG (src)));
6503
6504       src = SET_SRC (x);
6505     }
6506 #endif
6507
6508   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6509      are comparing an item known to be 0 or -1 against 0, use a logical
6510      operation instead. Check for one of the arms being an IOR of the other
6511      arm with some value.  We compute three terms to be IOR'ed together.  In
6512      practice, at most two will be nonzero.  Then we do the IOR's.  */
6513
6514   if (GET_CODE (dest) != PC
6515       && GET_CODE (src) == IF_THEN_ELSE
6516       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6517       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6518       && XEXP (XEXP (src, 0), 1) == const0_rtx
6519       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6520 #ifdef HAVE_conditional_move
6521       && ! can_conditionally_move_p (GET_MODE (src))
6522 #endif
6523       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6524                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6525           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6526       && ! side_effects_p (src))
6527     {
6528       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6529                       ? XEXP (src, 1) : XEXP (src, 2));
6530       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6531                    ? XEXP (src, 2) : XEXP (src, 1));
6532       rtx term1 = const0_rtx, term2, term3;
6533
6534       if (GET_CODE (true_rtx) == IOR
6535           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6536         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6537       else if (GET_CODE (true_rtx) == IOR
6538                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6539         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6540       else if (GET_CODE (false_rtx) == IOR
6541                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6542         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6543       else if (GET_CODE (false_rtx) == IOR
6544                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6545         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6546
6547       term2 = simplify_gen_binary (AND, GET_MODE (src),
6548                                    XEXP (XEXP (src, 0), 0), true_rtx);
6549       term3 = simplify_gen_binary (AND, GET_MODE (src),
6550                                    simplify_gen_unary (NOT, GET_MODE (src),
6551                                                        XEXP (XEXP (src, 0), 0),
6552                                                        GET_MODE (src)),
6553                                    false_rtx);
6554
6555       SUBST (SET_SRC (x),
6556              simplify_gen_binary (IOR, GET_MODE (src),
6557                                   simplify_gen_binary (IOR, GET_MODE (src),
6558                                                        term1, term2),
6559                                   term3));
6560
6561       src = SET_SRC (x);
6562     }
6563
6564   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6565      whole thing fail.  */
6566   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6567     return src;
6568   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6569     return dest;
6570   else
6571     /* Convert this into a field assignment operation, if possible.  */
6572     return make_field_assignment (x);
6573 }
6574 \f
6575 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6576    result.  */
6577
6578 static rtx
6579 simplify_logical (rtx x)
6580 {
6581   enum machine_mode mode = GET_MODE (x);
6582   rtx op0 = XEXP (x, 0);
6583   rtx op1 = XEXP (x, 1);
6584
6585   switch (GET_CODE (x))
6586     {
6587     case AND:
6588       /* We can call simplify_and_const_int only if we don't lose
6589          any (sign) bits when converting INTVAL (op1) to
6590          "unsigned HOST_WIDE_INT".  */
6591       if (CONST_INT_P (op1)
6592           && (HWI_COMPUTABLE_MODE_P (mode)
6593               || INTVAL (op1) > 0))
6594         {
6595           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6596           if (GET_CODE (x) != AND)
6597             return x;
6598
6599           op0 = XEXP (x, 0);
6600           op1 = XEXP (x, 1);
6601         }
6602
6603       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6604          apply the distributive law and then the inverse distributive
6605          law to see if things simplify.  */
6606       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6607         {
6608           rtx result = distribute_and_simplify_rtx (x, 0);
6609           if (result)
6610             return result;
6611         }
6612       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6613         {
6614           rtx result = distribute_and_simplify_rtx (x, 1);
6615           if (result)
6616             return result;
6617         }
6618       break;
6619
6620     case IOR:
6621       /* If we have (ior (and A B) C), apply the distributive law and then
6622          the inverse distributive law to see if things simplify.  */
6623
6624       if (GET_CODE (op0) == AND)
6625         {
6626           rtx result = distribute_and_simplify_rtx (x, 0);
6627           if (result)
6628             return result;
6629         }
6630
6631       if (GET_CODE (op1) == AND)
6632         {
6633           rtx result = distribute_and_simplify_rtx (x, 1);
6634           if (result)
6635             return result;
6636         }
6637       break;
6638
6639     default:
6640       gcc_unreachable ();
6641     }
6642
6643   return x;
6644 }
6645 \f
6646 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6647    operations" because they can be replaced with two more basic operations.
6648    ZERO_EXTEND is also considered "compound" because it can be replaced with
6649    an AND operation, which is simpler, though only one operation.
6650
6651    The function expand_compound_operation is called with an rtx expression
6652    and will convert it to the appropriate shifts and AND operations,
6653    simplifying at each stage.
6654
6655    The function make_compound_operation is called to convert an expression
6656    consisting of shifts and ANDs into the equivalent compound expression.
6657    It is the inverse of this function, loosely speaking.  */
6658
6659 static rtx
6660 expand_compound_operation (rtx x)
6661 {
6662   unsigned HOST_WIDE_INT pos = 0, len;
6663   int unsignedp = 0;
6664   unsigned int modewidth;
6665   rtx tem;
6666
6667   switch (GET_CODE (x))
6668     {
6669     case ZERO_EXTEND:
6670       unsignedp = 1;
6671     case SIGN_EXTEND:
6672       /* We can't necessarily use a const_int for a multiword mode;
6673          it depends on implicitly extending the value.
6674          Since we don't know the right way to extend it,
6675          we can't tell whether the implicit way is right.
6676
6677          Even for a mode that is no wider than a const_int,
6678          we can't win, because we need to sign extend one of its bits through
6679          the rest of it, and we don't know which bit.  */
6680       if (CONST_INT_P (XEXP (x, 0)))
6681         return x;
6682
6683       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6684          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6685          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6686          reloaded. If not for that, MEM's would very rarely be safe.
6687
6688          Reject MODEs bigger than a word, because we might not be able
6689          to reference a two-register group starting with an arbitrary register
6690          (and currently gen_lowpart might crash for a SUBREG).  */
6691
6692       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6693         return x;
6694
6695       /* Reject MODEs that aren't scalar integers because turning vector
6696          or complex modes into shifts causes problems.  */
6697
6698       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6699         return x;
6700
6701       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6702       /* If the inner object has VOIDmode (the only way this can happen
6703          is if it is an ASM_OPERANDS), we can't do anything since we don't
6704          know how much masking to do.  */
6705       if (len == 0)
6706         return x;
6707
6708       break;
6709
6710     case ZERO_EXTRACT:
6711       unsignedp = 1;
6712
6713       /* ... fall through ...  */
6714
6715     case SIGN_EXTRACT:
6716       /* If the operand is a CLOBBER, just return it.  */
6717       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6718         return XEXP (x, 0);
6719
6720       if (!CONST_INT_P (XEXP (x, 1))
6721           || !CONST_INT_P (XEXP (x, 2))
6722           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6723         return x;
6724
6725       /* Reject MODEs that aren't scalar integers because turning vector
6726          or complex modes into shifts causes problems.  */
6727
6728       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6729         return x;
6730
6731       len = INTVAL (XEXP (x, 1));
6732       pos = INTVAL (XEXP (x, 2));
6733
6734       /* This should stay within the object being extracted, fail otherwise.  */
6735       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6736         return x;
6737
6738       if (BITS_BIG_ENDIAN)
6739         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6740
6741       break;
6742
6743     default:
6744       return x;
6745     }
6746   /* Convert sign extension to zero extension, if we know that the high
6747      bit is not set, as this is easier to optimize.  It will be converted
6748      back to cheaper alternative in make_extraction.  */
6749   if (GET_CODE (x) == SIGN_EXTEND
6750       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6751           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6752                 & ~(((unsigned HOST_WIDE_INT)
6753                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6754                      >> 1))
6755                == 0)))
6756     {
6757       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6758       rtx temp2 = expand_compound_operation (temp);
6759
6760       /* Make sure this is a profitable operation.  */
6761       if (set_src_cost (x, optimize_this_for_speed_p)
6762           > set_src_cost (temp2, optimize_this_for_speed_p))
6763        return temp2;
6764       else if (set_src_cost (x, optimize_this_for_speed_p)
6765                > set_src_cost (temp, optimize_this_for_speed_p))
6766        return temp;
6767       else
6768        return x;
6769     }
6770
6771   /* We can optimize some special cases of ZERO_EXTEND.  */
6772   if (GET_CODE (x) == ZERO_EXTEND)
6773     {
6774       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6775          know that the last value didn't have any inappropriate bits
6776          set.  */
6777       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6778           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6779           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6780           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6781               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6782         return XEXP (XEXP (x, 0), 0);
6783
6784       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6785       if (GET_CODE (XEXP (x, 0)) == SUBREG
6786           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6787           && subreg_lowpart_p (XEXP (x, 0))
6788           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6789           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6790               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6791         return SUBREG_REG (XEXP (x, 0));
6792
6793       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6794          is a comparison and STORE_FLAG_VALUE permits.  This is like
6795          the first case, but it works even when GET_MODE (x) is larger
6796          than HOST_WIDE_INT.  */
6797       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6798           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6799           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6800           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6801               <= HOST_BITS_PER_WIDE_INT)
6802           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6803         return XEXP (XEXP (x, 0), 0);
6804
6805       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6806       if (GET_CODE (XEXP (x, 0)) == SUBREG
6807           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6808           && subreg_lowpart_p (XEXP (x, 0))
6809           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6810           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6811               <= HOST_BITS_PER_WIDE_INT)
6812           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6813         return SUBREG_REG (XEXP (x, 0));
6814
6815     }
6816
6817   /* If we reach here, we want to return a pair of shifts.  The inner
6818      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6819      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6820      logical depending on the value of UNSIGNEDP.
6821
6822      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6823      converted into an AND of a shift.
6824
6825      We must check for the case where the left shift would have a negative
6826      count.  This can happen in a case like (x >> 31) & 255 on machines
6827      that can't shift by a constant.  On those machines, we would first
6828      combine the shift with the AND to produce a variable-position
6829      extraction.  Then the constant of 31 would be substituted in
6830      to produce such a position.  */
6831
6832   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6833   if (modewidth >= pos + len)
6834     {
6835       enum machine_mode mode = GET_MODE (x);
6836       tem = gen_lowpart (mode, XEXP (x, 0));
6837       if (!tem || GET_CODE (tem) == CLOBBER)
6838         return x;
6839       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6840                                   tem, modewidth - pos - len);
6841       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6842                                   mode, tem, modewidth - len);
6843     }
6844   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6845     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6846                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6847                                                         GET_MODE (x),
6848                                                         XEXP (x, 0), pos),
6849                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6850   else
6851     /* Any other cases we can't handle.  */
6852     return x;
6853
6854   /* If we couldn't do this for some reason, return the original
6855      expression.  */
6856   if (GET_CODE (tem) == CLOBBER)
6857     return x;
6858
6859   return tem;
6860 }
6861 \f
6862 /* X is a SET which contains an assignment of one object into
6863    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6864    or certain SUBREGS). If possible, convert it into a series of
6865    logical operations.
6866
6867    We half-heartedly support variable positions, but do not at all
6868    support variable lengths.  */
6869
6870 static const_rtx
6871 expand_field_assignment (const_rtx x)
6872 {
6873   rtx inner;
6874   rtx pos;                      /* Always counts from low bit.  */
6875   int len;
6876   rtx mask, cleared, masked;
6877   enum machine_mode compute_mode;
6878
6879   /* Loop until we find something we can't simplify.  */
6880   while (1)
6881     {
6882       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6883           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6884         {
6885           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6886           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6887           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6888         }
6889       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6890                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6891         {
6892           inner = XEXP (SET_DEST (x), 0);
6893           len = INTVAL (XEXP (SET_DEST (x), 1));
6894           pos = XEXP (SET_DEST (x), 2);
6895
6896           /* A constant position should stay within the width of INNER.  */
6897           if (CONST_INT_P (pos)
6898               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6899             break;
6900
6901           if (BITS_BIG_ENDIAN)
6902             {
6903               if (CONST_INT_P (pos))
6904                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6905                                - INTVAL (pos));
6906               else if (GET_CODE (pos) == MINUS
6907                        && CONST_INT_P (XEXP (pos, 1))
6908                        && (INTVAL (XEXP (pos, 1))
6909                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6910                 /* If position is ADJUST - X, new position is X.  */
6911                 pos = XEXP (pos, 0);
6912               else
6913                 {
6914                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6915                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6916                                              gen_int_mode (prec - len,
6917                                                            GET_MODE (pos)),
6918                                              pos);
6919                 }
6920             }
6921         }
6922
6923       /* A SUBREG between two modes that occupy the same numbers of words
6924          can be done by moving the SUBREG to the source.  */
6925       else if (GET_CODE (SET_DEST (x)) == SUBREG
6926                /* We need SUBREGs to compute nonzero_bits properly.  */
6927                && nonzero_sign_valid
6928                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6929                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6930                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6931                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6932         {
6933           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6934                            gen_lowpart
6935                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6936                             SET_SRC (x)));
6937           continue;
6938         }
6939       else
6940         break;
6941
6942       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6943         inner = SUBREG_REG (inner);
6944
6945       compute_mode = GET_MODE (inner);
6946
6947       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
6948       if (! SCALAR_INT_MODE_P (compute_mode))
6949         {
6950           enum machine_mode imode;
6951
6952           /* Don't do anything for vector or complex integral types.  */
6953           if (! FLOAT_MODE_P (compute_mode))
6954             break;
6955
6956           /* Try to find an integral mode to pun with.  */
6957           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6958           if (imode == BLKmode)
6959             break;
6960
6961           compute_mode = imode;
6962           inner = gen_lowpart (imode, inner);
6963         }
6964
6965       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
6966       if (len >= HOST_BITS_PER_WIDE_INT)
6967         break;
6968
6969       /* Now compute the equivalent expression.  Make a copy of INNER
6970          for the SET_DEST in case it is a MEM into which we will substitute;
6971          we don't want shared RTL in that case.  */
6972       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
6973                            compute_mode);
6974       cleared = simplify_gen_binary (AND, compute_mode,
6975                                      simplify_gen_unary (NOT, compute_mode,
6976                                        simplify_gen_binary (ASHIFT,
6977                                                             compute_mode,
6978                                                             mask, pos),
6979                                        compute_mode),
6980                                      inner);
6981       masked = simplify_gen_binary (ASHIFT, compute_mode,
6982                                     simplify_gen_binary (
6983                                       AND, compute_mode,
6984                                       gen_lowpart (compute_mode, SET_SRC (x)),
6985                                       mask),
6986                                     pos);
6987
6988       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6989                        simplify_gen_binary (IOR, compute_mode,
6990                                             cleared, masked));
6991     }
6992
6993   return x;
6994 }
6995 \f
6996 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
6997    it is an RTX that represents the (variable) starting position; otherwise,
6998    POS is the (constant) starting bit position.  Both are counted from the LSB.
6999
7000    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7001
7002    IN_DEST is nonzero if this is a reference in the destination of a SET.
7003    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7004    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7005    be used.
7006
7007    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7008    ZERO_EXTRACT should be built even for bits starting at bit 0.
7009
7010    MODE is the desired mode of the result (if IN_DEST == 0).
7011
7012    The result is an RTX for the extraction or NULL_RTX if the target
7013    can't handle it.  */
7014
7015 static rtx
7016 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7017                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7018                  int in_dest, int in_compare)
7019 {
7020   /* This mode describes the size of the storage area
7021      to fetch the overall value from.  Within that, we
7022      ignore the POS lowest bits, etc.  */
7023   enum machine_mode is_mode = GET_MODE (inner);
7024   enum machine_mode inner_mode;
7025   enum machine_mode wanted_inner_mode;
7026   enum machine_mode wanted_inner_reg_mode = word_mode;
7027   enum machine_mode pos_mode = word_mode;
7028   enum machine_mode extraction_mode = word_mode;
7029   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7030   rtx new_rtx = 0;
7031   rtx orig_pos_rtx = pos_rtx;
7032   HOST_WIDE_INT orig_pos;
7033
7034   if (pos_rtx && CONST_INT_P (pos_rtx))
7035     pos = INTVAL (pos_rtx), pos_rtx = 0;
7036
7037   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7038     {
7039       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7040          consider just the QI as the memory to extract from.
7041          The subreg adds or removes high bits; its mode is
7042          irrelevant to the meaning of this extraction,
7043          since POS and LEN count from the lsb.  */
7044       if (MEM_P (SUBREG_REG (inner)))
7045         is_mode = GET_MODE (SUBREG_REG (inner));
7046       inner = SUBREG_REG (inner);
7047     }
7048   else if (GET_CODE (inner) == ASHIFT
7049            && CONST_INT_P (XEXP (inner, 1))
7050            && pos_rtx == 0 && pos == 0
7051            && len > UINTVAL (XEXP (inner, 1)))
7052     {
7053       /* We're extracting the least significant bits of an rtx
7054          (ashift X (const_int C)), where LEN > C.  Extract the
7055          least significant (LEN - C) bits of X, giving an rtx
7056          whose mode is MODE, then shift it left C times.  */
7057       new_rtx = make_extraction (mode, XEXP (inner, 0),
7058                              0, 0, len - INTVAL (XEXP (inner, 1)),
7059                              unsignedp, in_dest, in_compare);
7060       if (new_rtx != 0)
7061         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7062     }
7063   else if (GET_CODE (inner) == TRUNCATE)
7064     inner = XEXP (inner, 0);
7065
7066   inner_mode = GET_MODE (inner);
7067
7068   /* See if this can be done without an extraction.  We never can if the
7069      width of the field is not the same as that of some integer mode. For
7070      registers, we can only avoid the extraction if the position is at the
7071      low-order bit and this is either not in the destination or we have the
7072      appropriate STRICT_LOW_PART operation available.
7073
7074      For MEM, we can avoid an extract if the field starts on an appropriate
7075      boundary and we can change the mode of the memory reference.  */
7076
7077   if (tmode != BLKmode
7078       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7079            && !MEM_P (inner)
7080            && (inner_mode == tmode
7081                || !REG_P (inner)
7082                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7083                || reg_truncated_to_mode (tmode, inner))
7084            && (! in_dest
7085                || (REG_P (inner)
7086                    && have_insn_for (STRICT_LOW_PART, tmode))))
7087           || (MEM_P (inner) && pos_rtx == 0
7088               && (pos
7089                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7090                      : BITS_PER_UNIT)) == 0
7091               /* We can't do this if we are widening INNER_MODE (it
7092                  may not be aligned, for one thing).  */
7093               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7094               && (inner_mode == tmode
7095                   || (! mode_dependent_address_p (XEXP (inner, 0),
7096                                                   MEM_ADDR_SPACE (inner))
7097                       && ! MEM_VOLATILE_P (inner))))))
7098     {
7099       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7100          field.  If the original and current mode are the same, we need not
7101          adjust the offset.  Otherwise, we do if bytes big endian.
7102
7103          If INNER is not a MEM, get a piece consisting of just the field
7104          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7105
7106       if (MEM_P (inner))
7107         {
7108           HOST_WIDE_INT offset;
7109
7110           /* POS counts from lsb, but make OFFSET count in memory order.  */
7111           if (BYTES_BIG_ENDIAN)
7112             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7113           else
7114             offset = pos / BITS_PER_UNIT;
7115
7116           new_rtx = adjust_address_nv (inner, tmode, offset);
7117         }
7118       else if (REG_P (inner))
7119         {
7120           if (tmode != inner_mode)
7121             {
7122               /* We can't call gen_lowpart in a DEST since we
7123                  always want a SUBREG (see below) and it would sometimes
7124                  return a new hard register.  */
7125               if (pos || in_dest)
7126                 {
7127                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7128
7129                   if (WORDS_BIG_ENDIAN
7130                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7131                     final_word = ((GET_MODE_SIZE (inner_mode)
7132                                    - GET_MODE_SIZE (tmode))
7133                                   / UNITS_PER_WORD) - final_word;
7134
7135                   final_word *= UNITS_PER_WORD;
7136                   if (BYTES_BIG_ENDIAN &&
7137                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7138                     final_word += (GET_MODE_SIZE (inner_mode)
7139                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7140
7141                   /* Avoid creating invalid subregs, for example when
7142                      simplifying (x>>32)&255.  */
7143                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7144                     return NULL_RTX;
7145
7146                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7147                 }
7148               else
7149                 new_rtx = gen_lowpart (tmode, inner);
7150             }
7151           else
7152             new_rtx = inner;
7153         }
7154       else
7155         new_rtx = force_to_mode (inner, tmode,
7156                              len >= HOST_BITS_PER_WIDE_INT
7157                              ? ~(unsigned HOST_WIDE_INT) 0
7158                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7159                              0);
7160
7161       /* If this extraction is going into the destination of a SET,
7162          make a STRICT_LOW_PART unless we made a MEM.  */
7163
7164       if (in_dest)
7165         return (MEM_P (new_rtx) ? new_rtx
7166                 : (GET_CODE (new_rtx) != SUBREG
7167                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7168                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7169
7170       if (mode == tmode)
7171         return new_rtx;
7172
7173       if (CONST_SCALAR_INT_P (new_rtx))
7174         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7175                                          mode, new_rtx, tmode);
7176
7177       /* If we know that no extraneous bits are set, and that the high
7178          bit is not set, convert the extraction to the cheaper of
7179          sign and zero extension, that are equivalent in these cases.  */
7180       if (flag_expensive_optimizations
7181           && (HWI_COMPUTABLE_MODE_P (tmode)
7182               && ((nonzero_bits (new_rtx, tmode)
7183                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7184                   == 0)))
7185         {
7186           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7187           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7188
7189           /* Prefer ZERO_EXTENSION, since it gives more information to
7190              backends.  */
7191           if (set_src_cost (temp, optimize_this_for_speed_p)
7192               <= set_src_cost (temp1, optimize_this_for_speed_p))
7193             return temp;
7194           return temp1;
7195         }
7196
7197       /* Otherwise, sign- or zero-extend unless we already are in the
7198          proper mode.  */
7199
7200       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7201                              mode, new_rtx));
7202     }
7203
7204   /* Unless this is a COMPARE or we have a funny memory reference,
7205      don't do anything with zero-extending field extracts starting at
7206      the low-order bit since they are simple AND operations.  */
7207   if (pos_rtx == 0 && pos == 0 && ! in_dest
7208       && ! in_compare && unsignedp)
7209     return 0;
7210
7211   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7212      if the position is not a constant and the length is not 1.  In all
7213      other cases, we would only be going outside our object in cases when
7214      an original shift would have been undefined.  */
7215   if (MEM_P (inner)
7216       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7217           || (pos_rtx != 0 && len != 1)))
7218     return 0;
7219
7220   enum extraction_pattern pattern = (in_dest ? EP_insv
7221                                      : unsignedp ? EP_extzv : EP_extv);
7222
7223   /* If INNER is not from memory, we want it to have the mode of a register
7224      extraction pattern's structure operand, or word_mode if there is no
7225      such pattern.  The same applies to extraction_mode and pos_mode
7226      and their respective operands.
7227
7228      For memory, assume that the desired extraction_mode and pos_mode
7229      are the same as for a register operation, since at present we don't
7230      have named patterns for aligned memory structures.  */
7231   struct extraction_insn insn;
7232   if (get_best_reg_extraction_insn (&insn, pattern,
7233                                     GET_MODE_BITSIZE (inner_mode), mode))
7234     {
7235       wanted_inner_reg_mode = insn.struct_mode;
7236       pos_mode = insn.pos_mode;
7237       extraction_mode = insn.field_mode;
7238     }
7239
7240   /* Never narrow an object, since that might not be safe.  */
7241
7242   if (mode != VOIDmode
7243       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7244     extraction_mode = mode;
7245
7246   if (!MEM_P (inner))
7247     wanted_inner_mode = wanted_inner_reg_mode;
7248   else
7249     {
7250       /* Be careful not to go beyond the extracted object and maintain the
7251          natural alignment of the memory.  */
7252       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7253       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7254              > GET_MODE_BITSIZE (wanted_inner_mode))
7255         {
7256           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7257           gcc_assert (wanted_inner_mode != VOIDmode);
7258         }
7259     }
7260
7261   orig_pos = pos;
7262
7263   if (BITS_BIG_ENDIAN)
7264     {
7265       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7266          BITS_BIG_ENDIAN style.  If position is constant, compute new
7267          position.  Otherwise, build subtraction.
7268          Note that POS is relative to the mode of the original argument.
7269          If it's a MEM we need to recompute POS relative to that.
7270          However, if we're extracting from (or inserting into) a register,
7271          we want to recompute POS relative to wanted_inner_mode.  */
7272       int width = (MEM_P (inner)
7273                    ? GET_MODE_BITSIZE (is_mode)
7274                    : GET_MODE_BITSIZE (wanted_inner_mode));
7275
7276       if (pos_rtx == 0)
7277         pos = width - len - pos;
7278       else
7279         pos_rtx
7280           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7281                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7282                            pos_rtx);
7283       /* POS may be less than 0 now, but we check for that below.
7284          Note that it can only be less than 0 if !MEM_P (inner).  */
7285     }
7286
7287   /* If INNER has a wider mode, and this is a constant extraction, try to
7288      make it smaller and adjust the byte to point to the byte containing
7289      the value.  */
7290   if (wanted_inner_mode != VOIDmode
7291       && inner_mode != wanted_inner_mode
7292       && ! pos_rtx
7293       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7294       && MEM_P (inner)
7295       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7296       && ! MEM_VOLATILE_P (inner))
7297     {
7298       int offset = 0;
7299
7300       /* The computations below will be correct if the machine is big
7301          endian in both bits and bytes or little endian in bits and bytes.
7302          If it is mixed, we must adjust.  */
7303
7304       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7305          adjust OFFSET to compensate.  */
7306       if (BYTES_BIG_ENDIAN
7307           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7308         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7309
7310       /* We can now move to the desired byte.  */
7311       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7312                 * GET_MODE_SIZE (wanted_inner_mode);
7313       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7314
7315       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7316           && is_mode != wanted_inner_mode)
7317         offset = (GET_MODE_SIZE (is_mode)
7318                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7319
7320       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7321     }
7322
7323   /* If INNER is not memory, get it into the proper mode.  If we are changing
7324      its mode, POS must be a constant and smaller than the size of the new
7325      mode.  */
7326   else if (!MEM_P (inner))
7327     {
7328       /* On the LHS, don't create paradoxical subregs implicitely truncating
7329          the register unless TRULY_NOOP_TRUNCATION.  */
7330       if (in_dest
7331           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7332                                              wanted_inner_mode))
7333         return NULL_RTX;
7334
7335       if (GET_MODE (inner) != wanted_inner_mode
7336           && (pos_rtx != 0
7337               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7338         return NULL_RTX;
7339
7340       if (orig_pos < 0)
7341         return NULL_RTX;
7342
7343       inner = force_to_mode (inner, wanted_inner_mode,
7344                              pos_rtx
7345                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7346                              ? ~(unsigned HOST_WIDE_INT) 0
7347                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7348                                 << orig_pos),
7349                              0);
7350     }
7351
7352   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7353      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7354   if (pos_rtx != 0
7355       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7356     {
7357       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7358                                      GET_MODE (pos_rtx));
7359
7360       /* If we know that no extraneous bits are set, and that the high
7361          bit is not set, convert extraction to cheaper one - either
7362          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7363          cases.  */
7364       if (flag_expensive_optimizations
7365           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7366               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7367                    & ~(((unsigned HOST_WIDE_INT)
7368                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7369                        >> 1))
7370                   == 0)))
7371         {
7372           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7373                                           GET_MODE (pos_rtx));
7374
7375           /* Prefer ZERO_EXTENSION, since it gives more information to
7376              backends.  */
7377           if (set_src_cost (temp1, optimize_this_for_speed_p)
7378               < set_src_cost (temp, optimize_this_for_speed_p))
7379             temp = temp1;
7380         }
7381       pos_rtx = temp;
7382     }
7383
7384   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7385      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7386      be a CONST_INT.  */
7387   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7388     pos_rtx = orig_pos_rtx;
7389
7390   else if (pos_rtx == 0)
7391     pos_rtx = GEN_INT (pos);
7392
7393   /* Make the required operation.  See if we can use existing rtx.  */
7394   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7395                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7396   if (! in_dest)
7397     new_rtx = gen_lowpart (mode, new_rtx);
7398
7399   return new_rtx;
7400 }
7401 \f
7402 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7403    with any other operations in X.  Return X without that shift if so.  */
7404
7405 static rtx
7406 extract_left_shift (rtx x, int count)
7407 {
7408   enum rtx_code code = GET_CODE (x);
7409   enum machine_mode mode = GET_MODE (x);
7410   rtx tem;
7411
7412   switch (code)
7413     {
7414     case ASHIFT:
7415       /* This is the shift itself.  If it is wide enough, we will return
7416          either the value being shifted if the shift count is equal to
7417          COUNT or a shift for the difference.  */
7418       if (CONST_INT_P (XEXP (x, 1))
7419           && INTVAL (XEXP (x, 1)) >= count)
7420         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7421                                      INTVAL (XEXP (x, 1)) - count);
7422       break;
7423
7424     case NEG:  case NOT:
7425       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7426         return simplify_gen_unary (code, mode, tem, mode);
7427
7428       break;
7429
7430     case PLUS:  case IOR:  case XOR:  case AND:
7431       /* If we can safely shift this constant and we find the inner shift,
7432          make a new operation.  */
7433       if (CONST_INT_P (XEXP (x, 1))
7434           && (UINTVAL (XEXP (x, 1))
7435               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7436           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7437         {
7438           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7439           return simplify_gen_binary (code, mode, tem,
7440                                       gen_int_mode (val, mode));
7441         }
7442       break;
7443
7444     default:
7445       break;
7446     }
7447
7448   return 0;
7449 }
7450 \f
7451 /* Look at the expression rooted at X.  Look for expressions
7452    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7453    Form these expressions.
7454
7455    Return the new rtx, usually just X.
7456
7457    Also, for machines like the VAX that don't have logical shift insns,
7458    try to convert logical to arithmetic shift operations in cases where
7459    they are equivalent.  This undoes the canonicalizations to logical
7460    shifts done elsewhere.
7461
7462    We try, as much as possible, to re-use rtl expressions to save memory.
7463
7464    IN_CODE says what kind of expression we are processing.  Normally, it is
7465    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7466    being kludges), it is MEM.  When processing the arguments of a comparison
7467    or a COMPARE against zero, it is COMPARE.  */
7468
7469 rtx
7470 make_compound_operation (rtx x, enum rtx_code in_code)
7471 {
7472   enum rtx_code code = GET_CODE (x);
7473   enum machine_mode mode = GET_MODE (x);
7474   int mode_width = GET_MODE_PRECISION (mode);
7475   rtx rhs, lhs;
7476   enum rtx_code next_code;
7477   int i, j;
7478   rtx new_rtx = 0;
7479   rtx tem;
7480   const char *fmt;
7481
7482   /* Select the code to be used in recursive calls.  Once we are inside an
7483      address, we stay there.  If we have a comparison, set to COMPARE,
7484      but once inside, go back to our default of SET.  */
7485
7486   next_code = (code == MEM ? MEM
7487                : ((code == PLUS || code == MINUS)
7488                   && SCALAR_INT_MODE_P (mode)) ? MEM
7489                : ((code == COMPARE || COMPARISON_P (x))
7490                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7491                : in_code == COMPARE ? SET : in_code);
7492
7493   /* Process depending on the code of this operation.  If NEW is set
7494      nonzero, it will be returned.  */
7495
7496   switch (code)
7497     {
7498     case ASHIFT:
7499       /* Convert shifts by constants into multiplications if inside
7500          an address.  */
7501       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7502           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7503           && INTVAL (XEXP (x, 1)) >= 0
7504           && SCALAR_INT_MODE_P (mode))
7505         {
7506           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7507           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7508
7509           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7510           if (GET_CODE (new_rtx) == NEG)
7511             {
7512               new_rtx = XEXP (new_rtx, 0);
7513               multval = -multval;
7514             }
7515           multval = trunc_int_for_mode (multval, mode);
7516           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7517         }
7518       break;
7519
7520     case PLUS:
7521       lhs = XEXP (x, 0);
7522       rhs = XEXP (x, 1);
7523       lhs = make_compound_operation (lhs, next_code);
7524       rhs = make_compound_operation (rhs, next_code);
7525       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7526           && SCALAR_INT_MODE_P (mode))
7527         {
7528           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7529                                      XEXP (lhs, 1));
7530           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7531         }
7532       else if (GET_CODE (lhs) == MULT
7533                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7534         {
7535           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7536                                      simplify_gen_unary (NEG, mode,
7537                                                          XEXP (lhs, 1),
7538                                                          mode));
7539           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7540         }
7541       else
7542         {
7543           SUBST (XEXP (x, 0), lhs);
7544           SUBST (XEXP (x, 1), rhs);
7545           goto maybe_swap;
7546         }
7547       x = gen_lowpart (mode, new_rtx);
7548       goto maybe_swap;
7549
7550     case MINUS:
7551       lhs = XEXP (x, 0);
7552       rhs = XEXP (x, 1);
7553       lhs = make_compound_operation (lhs, next_code);
7554       rhs = make_compound_operation (rhs, next_code);
7555       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7556           && SCALAR_INT_MODE_P (mode))
7557         {
7558           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7559                                      XEXP (rhs, 1));
7560           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7561         }
7562       else if (GET_CODE (rhs) == MULT
7563                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7564         {
7565           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7566                                      simplify_gen_unary (NEG, mode,
7567                                                          XEXP (rhs, 1),
7568                                                          mode));
7569           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7570         }
7571       else
7572         {
7573           SUBST (XEXP (x, 0), lhs);
7574           SUBST (XEXP (x, 1), rhs);
7575           return x;
7576         }
7577       return gen_lowpart (mode, new_rtx);
7578
7579     case AND:
7580       /* If the second operand is not a constant, we can't do anything
7581          with it.  */
7582       if (!CONST_INT_P (XEXP (x, 1)))
7583         break;
7584
7585       /* If the constant is a power of two minus one and the first operand
7586          is a logical right shift, make an extraction.  */
7587       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7588           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7589         {
7590           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7591           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7592                                  0, in_code == COMPARE);
7593         }
7594
7595       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7596       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7597                && subreg_lowpart_p (XEXP (x, 0))
7598                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7599                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7600         {
7601           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7602                                          next_code);
7603           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7604                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7605                                  0, in_code == COMPARE);
7606         }
7607       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7608       else if ((GET_CODE (XEXP (x, 0)) == XOR
7609                 || GET_CODE (XEXP (x, 0)) == IOR)
7610                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7611                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7612                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7613         {
7614           /* Apply the distributive law, and then try to make extractions.  */
7615           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7616                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7617                                              XEXP (x, 1)),
7618                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7619                                              XEXP (x, 1)));
7620           new_rtx = make_compound_operation (new_rtx, in_code);
7621         }
7622
7623       /* If we are have (and (rotate X C) M) and C is larger than the number
7624          of bits in M, this is an extraction.  */
7625
7626       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7627                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7628                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7629                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7630         {
7631           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7632           new_rtx = make_extraction (mode, new_rtx,
7633                                  (GET_MODE_PRECISION (mode)
7634                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7635                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7636         }
7637
7638       /* On machines without logical shifts, if the operand of the AND is
7639          a logical shift and our mask turns off all the propagated sign
7640          bits, we can replace the logical shift with an arithmetic shift.  */
7641       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7642                && !have_insn_for (LSHIFTRT, mode)
7643                && have_insn_for (ASHIFTRT, mode)
7644                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7645                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7646                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7647                && mode_width <= HOST_BITS_PER_WIDE_INT)
7648         {
7649           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7650
7651           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7652           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7653             SUBST (XEXP (x, 0),
7654                    gen_rtx_ASHIFTRT (mode,
7655                                      make_compound_operation
7656                                      (XEXP (XEXP (x, 0), 0), next_code),
7657                                      XEXP (XEXP (x, 0), 1)));
7658         }
7659
7660       /* If the constant is one less than a power of two, this might be
7661          representable by an extraction even if no shift is present.
7662          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7663          we are in a COMPARE.  */
7664       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7665         new_rtx = make_extraction (mode,
7666                                make_compound_operation (XEXP (x, 0),
7667                                                         next_code),
7668                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7669
7670       /* If we are in a comparison and this is an AND with a power of two,
7671          convert this into the appropriate bit extract.  */
7672       else if (in_code == COMPARE
7673                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7674         new_rtx = make_extraction (mode,
7675                                make_compound_operation (XEXP (x, 0),
7676                                                         next_code),
7677                                i, NULL_RTX, 1, 1, 0, 1);
7678
7679       break;
7680
7681     case LSHIFTRT:
7682       /* If the sign bit is known to be zero, replace this with an
7683          arithmetic shift.  */
7684       if (have_insn_for (ASHIFTRT, mode)
7685           && ! have_insn_for (LSHIFTRT, mode)
7686           && mode_width <= HOST_BITS_PER_WIDE_INT
7687           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7688         {
7689           new_rtx = gen_rtx_ASHIFTRT (mode,
7690                                   make_compound_operation (XEXP (x, 0),
7691                                                            next_code),
7692                                   XEXP (x, 1));
7693           break;
7694         }
7695
7696       /* ... fall through ...  */
7697
7698     case ASHIFTRT:
7699       lhs = XEXP (x, 0);
7700       rhs = XEXP (x, 1);
7701
7702       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7703          this is a SIGN_EXTRACT.  */
7704       if (CONST_INT_P (rhs)
7705           && GET_CODE (lhs) == ASHIFT
7706           && CONST_INT_P (XEXP (lhs, 1))
7707           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7708           && INTVAL (XEXP (lhs, 1)) >= 0
7709           && INTVAL (rhs) < mode_width)
7710         {
7711           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7712           new_rtx = make_extraction (mode, new_rtx,
7713                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7714                                  NULL_RTX, mode_width - INTVAL (rhs),
7715                                  code == LSHIFTRT, 0, in_code == COMPARE);
7716           break;
7717         }
7718
7719       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7720          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7721          also do this for some cases of SIGN_EXTRACT, but it doesn't
7722          seem worth the effort; the case checked for occurs on Alpha.  */
7723
7724       if (!OBJECT_P (lhs)
7725           && ! (GET_CODE (lhs) == SUBREG
7726                 && (OBJECT_P (SUBREG_REG (lhs))))
7727           && CONST_INT_P (rhs)
7728           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7729           && INTVAL (rhs) < mode_width
7730           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7731         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7732                                0, NULL_RTX, mode_width - INTVAL (rhs),
7733                                code == LSHIFTRT, 0, in_code == COMPARE);
7734
7735       break;
7736
7737     case SUBREG:
7738       /* Call ourselves recursively on the inner expression.  If we are
7739          narrowing the object and it has a different RTL code from
7740          what it originally did, do this SUBREG as a force_to_mode.  */
7741       {
7742         rtx inner = SUBREG_REG (x), simplified;
7743         enum rtx_code subreg_code = in_code;
7744
7745         /* If in_code is COMPARE, it isn't always safe to pass it through
7746            to the recursive make_compound_operation call.  */
7747         if (subreg_code == COMPARE
7748             && (!subreg_lowpart_p (x)
7749                 || GET_CODE (inner) == SUBREG
7750                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7751                    is (const_int 0), rather than
7752                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7753                 || (GET_CODE (inner) == AND
7754                     && CONST_INT_P (XEXP (inner, 1))
7755                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7756                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7757                        >= GET_MODE_BITSIZE (mode))))
7758           subreg_code = SET;
7759
7760         tem = make_compound_operation (inner, subreg_code);
7761
7762         simplified
7763           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7764         if (simplified)
7765           tem = simplified;
7766
7767         if (GET_CODE (tem) != GET_CODE (inner)
7768             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7769             && subreg_lowpart_p (x))
7770           {
7771             rtx newer
7772               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7773
7774             /* If we have something other than a SUBREG, we might have
7775                done an expansion, so rerun ourselves.  */
7776             if (GET_CODE (newer) != SUBREG)
7777               newer = make_compound_operation (newer, in_code);
7778
7779             /* force_to_mode can expand compounds.  If it just re-expanded the
7780                compound, use gen_lowpart to convert to the desired mode.  */
7781             if (rtx_equal_p (newer, x)
7782                 /* Likewise if it re-expanded the compound only partially.
7783                    This happens for SUBREG of ZERO_EXTRACT if they extract
7784                    the same number of bits.  */
7785                 || (GET_CODE (newer) == SUBREG
7786                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7787                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7788                     && GET_CODE (inner) == AND
7789                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7790               return gen_lowpart (GET_MODE (x), tem);
7791
7792             return newer;
7793           }
7794
7795         if (simplified)
7796           return tem;
7797       }
7798       break;
7799
7800     default:
7801       break;
7802     }
7803
7804   if (new_rtx)
7805     {
7806       x = gen_lowpart (mode, new_rtx);
7807       code = GET_CODE (x);
7808     }
7809
7810   /* Now recursively process each operand of this operation.  We need to
7811      handle ZERO_EXTEND specially so that we don't lose track of the
7812      inner mode.  */
7813   if (GET_CODE (x) == ZERO_EXTEND)
7814     {
7815       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7816       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7817                                             new_rtx, GET_MODE (XEXP (x, 0)));
7818       if (tem)
7819         return tem;
7820       SUBST (XEXP (x, 0), new_rtx);
7821       return x;
7822     }
7823
7824   fmt = GET_RTX_FORMAT (code);
7825   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7826     if (fmt[i] == 'e')
7827       {
7828         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7829         SUBST (XEXP (x, i), new_rtx);
7830       }
7831     else if (fmt[i] == 'E')
7832       for (j = 0; j < XVECLEN (x, i); j++)
7833         {
7834           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7835           SUBST (XVECEXP (x, i, j), new_rtx);
7836         }
7837
7838  maybe_swap:
7839   /* If this is a commutative operation, the changes to the operands
7840      may have made it noncanonical.  */
7841   if (COMMUTATIVE_ARITH_P (x)
7842       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7843     {
7844       tem = XEXP (x, 0);
7845       SUBST (XEXP (x, 0), XEXP (x, 1));
7846       SUBST (XEXP (x, 1), tem);
7847     }
7848
7849   return x;
7850 }
7851 \f
7852 /* Given M see if it is a value that would select a field of bits
7853    within an item, but not the entire word.  Return -1 if not.
7854    Otherwise, return the starting position of the field, where 0 is the
7855    low-order bit.
7856
7857    *PLEN is set to the length of the field.  */
7858
7859 static int
7860 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7861 {
7862   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7863   int pos = m ? ctz_hwi (m) : -1;
7864   int len = 0;
7865
7866   if (pos >= 0)
7867     /* Now shift off the low-order zero bits and see if we have a
7868        power of two minus 1.  */
7869     len = exact_log2 ((m >> pos) + 1);
7870
7871   if (len <= 0)
7872     pos = -1;
7873
7874   *plen = len;
7875   return pos;
7876 }
7877 \f
7878 /* If X refers to a register that equals REG in value, replace these
7879    references with REG.  */
7880 static rtx
7881 canon_reg_for_combine (rtx x, rtx reg)
7882 {
7883   rtx op0, op1, op2;
7884   const char *fmt;
7885   int i;
7886   bool copied;
7887
7888   enum rtx_code code = GET_CODE (x);
7889   switch (GET_RTX_CLASS (code))
7890     {
7891     case RTX_UNARY:
7892       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7893       if (op0 != XEXP (x, 0))
7894         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7895                                    GET_MODE (reg));
7896       break;
7897
7898     case RTX_BIN_ARITH:
7899     case RTX_COMM_ARITH:
7900       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7901       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7902       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7903         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7904       break;
7905
7906     case RTX_COMPARE:
7907     case RTX_COMM_COMPARE:
7908       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7909       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7910       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7911         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7912                                         GET_MODE (op0), op0, op1);
7913       break;
7914
7915     case RTX_TERNARY:
7916     case RTX_BITFIELD_OPS:
7917       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7918       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7919       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7920       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7921         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7922                                      GET_MODE (op0), op0, op1, op2);
7923
7924     case RTX_OBJ:
7925       if (REG_P (x))
7926         {
7927           if (rtx_equal_p (get_last_value (reg), x)
7928               || rtx_equal_p (reg, get_last_value (x)))
7929             return reg;
7930           else
7931             break;
7932         }
7933
7934       /* fall through */
7935
7936     default:
7937       fmt = GET_RTX_FORMAT (code);
7938       copied = false;
7939       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7940         if (fmt[i] == 'e')
7941           {
7942             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7943             if (op != XEXP (x, i))
7944               {
7945                 if (!copied)
7946                   {
7947                     copied = true;
7948                     x = copy_rtx (x);
7949                   }
7950                 XEXP (x, i) = op;
7951               }
7952           }
7953         else if (fmt[i] == 'E')
7954           {
7955             int j;
7956             for (j = 0; j < XVECLEN (x, i); j++)
7957               {
7958                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7959                 if (op != XVECEXP (x, i, j))
7960                   {
7961                     if (!copied)
7962                       {
7963                         copied = true;
7964                         x = copy_rtx (x);
7965                       }
7966                     XVECEXP (x, i, j) = op;
7967                   }
7968               }
7969           }
7970
7971       break;
7972     }
7973
7974   return x;
7975 }
7976
7977 /* Return X converted to MODE.  If the value is already truncated to
7978    MODE we can just return a subreg even though in the general case we
7979    would need an explicit truncation.  */
7980
7981 static rtx
7982 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7983 {
7984   if (!CONST_INT_P (x)
7985       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7986       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
7987       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7988     {
7989       /* Bit-cast X into an integer mode.  */
7990       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7991         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7992       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7993                               x, GET_MODE (x));
7994     }
7995
7996   return gen_lowpart (mode, x);
7997 }
7998
7999 /* See if X can be simplified knowing that we will only refer to it in
8000    MODE and will only refer to those bits that are nonzero in MASK.
8001    If other bits are being computed or if masking operations are done
8002    that select a superset of the bits in MASK, they can sometimes be
8003    ignored.
8004
8005    Return a possibly simplified expression, but always convert X to
8006    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8007
8008    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8009    are all off in X.  This is used when X will be complemented, by either
8010    NOT, NEG, or XOR.  */
8011
8012 static rtx
8013 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8014                int just_select)
8015 {
8016   enum rtx_code code = GET_CODE (x);
8017   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8018   enum machine_mode op_mode;
8019   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8020   rtx op0, op1, temp;
8021
8022   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8023      code below will do the wrong thing since the mode of such an
8024      expression is VOIDmode.
8025
8026      Also do nothing if X is a CLOBBER; this can happen if X was
8027      the return value from a call to gen_lowpart.  */
8028   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8029     return x;
8030
8031   /* We want to perform the operation is its present mode unless we know
8032      that the operation is valid in MODE, in which case we do the operation
8033      in MODE.  */
8034   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8035               && have_insn_for (code, mode))
8036              ? mode : GET_MODE (x));
8037
8038   /* It is not valid to do a right-shift in a narrower mode
8039      than the one it came in with.  */
8040   if ((code == LSHIFTRT || code == ASHIFTRT)
8041       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8042     op_mode = GET_MODE (x);
8043
8044   /* Truncate MASK to fit OP_MODE.  */
8045   if (op_mode)
8046     mask &= GET_MODE_MASK (op_mode);
8047
8048   /* When we have an arithmetic operation, or a shift whose count we
8049      do not know, we need to assume that all bits up to the highest-order
8050      bit in MASK will be needed.  This is how we form such a mask.  */
8051   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8052     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8053   else
8054     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8055                    - 1);
8056
8057   /* Determine what bits of X are guaranteed to be (non)zero.  */
8058   nonzero = nonzero_bits (x, mode);
8059
8060   /* If none of the bits in X are needed, return a zero.  */
8061   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8062     x = const0_rtx;
8063
8064   /* If X is a CONST_INT, return a new one.  Do this here since the
8065      test below will fail.  */
8066   if (CONST_INT_P (x))
8067     {
8068       if (SCALAR_INT_MODE_P (mode))
8069         return gen_int_mode (INTVAL (x) & mask, mode);
8070       else
8071         {
8072           x = GEN_INT (INTVAL (x) & mask);
8073           return gen_lowpart_common (mode, x);
8074         }
8075     }
8076
8077   /* If X is narrower than MODE and we want all the bits in X's mode, just
8078      get X in the proper mode.  */
8079   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8080       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8081     return gen_lowpart (mode, x);
8082
8083   /* We can ignore the effect of a SUBREG if it narrows the mode or
8084      if the constant masks to zero all the bits the mode doesn't have.  */
8085   if (GET_CODE (x) == SUBREG
8086       && subreg_lowpart_p (x)
8087       && ((GET_MODE_SIZE (GET_MODE (x))
8088            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8089           || (0 == (mask
8090                     & GET_MODE_MASK (GET_MODE (x))
8091                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8092     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8093
8094   /* The arithmetic simplifications here only work for scalar integer modes.  */
8095   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8096     return gen_lowpart_or_truncate (mode, x);
8097
8098   switch (code)
8099     {
8100     case CLOBBER:
8101       /* If X is a (clobber (const_int)), return it since we know we are
8102          generating something that won't match.  */
8103       return x;
8104
8105     case SIGN_EXTEND:
8106     case ZERO_EXTEND:
8107     case ZERO_EXTRACT:
8108     case SIGN_EXTRACT:
8109       x = expand_compound_operation (x);
8110       if (GET_CODE (x) != code)
8111         return force_to_mode (x, mode, mask, next_select);
8112       break;
8113
8114     case TRUNCATE:
8115       /* Similarly for a truncate.  */
8116       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8117
8118     case AND:
8119       /* If this is an AND with a constant, convert it into an AND
8120          whose constant is the AND of that constant with MASK.  If it
8121          remains an AND of MASK, delete it since it is redundant.  */
8122
8123       if (CONST_INT_P (XEXP (x, 1)))
8124         {
8125           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8126                                       mask & INTVAL (XEXP (x, 1)));
8127
8128           /* If X is still an AND, see if it is an AND with a mask that
8129              is just some low-order bits.  If so, and it is MASK, we don't
8130              need it.  */
8131
8132           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8133               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8134                   == mask))
8135             x = XEXP (x, 0);
8136
8137           /* If it remains an AND, try making another AND with the bits
8138              in the mode mask that aren't in MASK turned on.  If the
8139              constant in the AND is wide enough, this might make a
8140              cheaper constant.  */
8141
8142           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8143               && GET_MODE_MASK (GET_MODE (x)) != mask
8144               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8145             {
8146               unsigned HOST_WIDE_INT cval
8147                 = UINTVAL (XEXP (x, 1))
8148                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8149               rtx y;
8150
8151               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8152                                        gen_int_mode (cval, GET_MODE (x)));
8153               if (set_src_cost (y, optimize_this_for_speed_p)
8154                   < set_src_cost (x, optimize_this_for_speed_p))
8155                 x = y;
8156             }
8157
8158           break;
8159         }
8160
8161       goto binop;
8162
8163     case PLUS:
8164       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8165          low-order bits (as in an alignment operation) and FOO is already
8166          aligned to that boundary, mask C1 to that boundary as well.
8167          This may eliminate that PLUS and, later, the AND.  */
8168
8169       {
8170         unsigned int width = GET_MODE_PRECISION (mode);
8171         unsigned HOST_WIDE_INT smask = mask;
8172
8173         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8174            number, sign extend it.  */
8175
8176         if (width < HOST_BITS_PER_WIDE_INT
8177             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8178           smask |= HOST_WIDE_INT_M1U << width;
8179
8180         if (CONST_INT_P (XEXP (x, 1))
8181             && exact_log2 (- smask) >= 0
8182             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8183             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8184           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8185                                                (INTVAL (XEXP (x, 1)) & smask)),
8186                                 mode, smask, next_select);
8187       }
8188
8189       /* ... fall through ...  */
8190
8191     case MULT:
8192       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8193          most significant bit in MASK since carries from those bits will
8194          affect the bits we are interested in.  */
8195       mask = fuller_mask;
8196       goto binop;
8197
8198     case MINUS:
8199       /* If X is (minus C Y) where C's least set bit is larger than any bit
8200          in the mask, then we may replace with (neg Y).  */
8201       if (CONST_INT_P (XEXP (x, 0))
8202           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8203                                         & -INTVAL (XEXP (x, 0))))
8204               > mask))
8205         {
8206           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8207                                   GET_MODE (x));
8208           return force_to_mode (x, mode, mask, next_select);
8209         }
8210
8211       /* Similarly, if C contains every bit in the fuller_mask, then we may
8212          replace with (not Y).  */
8213       if (CONST_INT_P (XEXP (x, 0))
8214           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8215         {
8216           x = simplify_gen_unary (NOT, GET_MODE (x),
8217                                   XEXP (x, 1), GET_MODE (x));
8218           return force_to_mode (x, mode, mask, next_select);
8219         }
8220
8221       mask = fuller_mask;
8222       goto binop;
8223
8224     case IOR:
8225     case XOR:
8226       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8227          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8228          operation which may be a bitfield extraction.  Ensure that the
8229          constant we form is not wider than the mode of X.  */
8230
8231       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8232           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8233           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8234           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8235           && CONST_INT_P (XEXP (x, 1))
8236           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8237                + floor_log2 (INTVAL (XEXP (x, 1))))
8238               < GET_MODE_PRECISION (GET_MODE (x)))
8239           && (UINTVAL (XEXP (x, 1))
8240               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8241         {
8242           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8243                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8244                                GET_MODE (x));
8245           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8246                                       XEXP (XEXP (x, 0), 0), temp);
8247           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8248                                    XEXP (XEXP (x, 0), 1));
8249           return force_to_mode (x, mode, mask, next_select);
8250         }
8251
8252     binop:
8253       /* For most binary operations, just propagate into the operation and
8254          change the mode if we have an operation of that mode.  */
8255
8256       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8257       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8258
8259       /* If we ended up truncating both operands, truncate the result of the
8260          operation instead.  */
8261       if (GET_CODE (op0) == TRUNCATE
8262           && GET_CODE (op1) == TRUNCATE)
8263         {
8264           op0 = XEXP (op0, 0);
8265           op1 = XEXP (op1, 0);
8266         }
8267
8268       op0 = gen_lowpart_or_truncate (op_mode, op0);
8269       op1 = gen_lowpart_or_truncate (op_mode, op1);
8270
8271       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8272         x = simplify_gen_binary (code, op_mode, op0, op1);
8273       break;
8274
8275     case ASHIFT:
8276       /* For left shifts, do the same, but just for the first operand.
8277          However, we cannot do anything with shifts where we cannot
8278          guarantee that the counts are smaller than the size of the mode
8279          because such a count will have a different meaning in a
8280          wider mode.  */
8281
8282       if (! (CONST_INT_P (XEXP (x, 1))
8283              && INTVAL (XEXP (x, 1)) >= 0
8284              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8285           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8286                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8287                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8288         break;
8289
8290       /* If the shift count is a constant and we can do arithmetic in
8291          the mode of the shift, refine which bits we need.  Otherwise, use the
8292          conservative form of the mask.  */
8293       if (CONST_INT_P (XEXP (x, 1))
8294           && INTVAL (XEXP (x, 1)) >= 0
8295           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8296           && HWI_COMPUTABLE_MODE_P (op_mode))
8297         mask >>= INTVAL (XEXP (x, 1));
8298       else
8299         mask = fuller_mask;
8300
8301       op0 = gen_lowpart_or_truncate (op_mode,
8302                                      force_to_mode (XEXP (x, 0), op_mode,
8303                                                     mask, next_select));
8304
8305       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8306         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8307       break;
8308
8309     case LSHIFTRT:
8310       /* Here we can only do something if the shift count is a constant,
8311          this shift constant is valid for the host, and we can do arithmetic
8312          in OP_MODE.  */
8313
8314       if (CONST_INT_P (XEXP (x, 1))
8315           && INTVAL (XEXP (x, 1)) >= 0
8316           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8317           && HWI_COMPUTABLE_MODE_P (op_mode))
8318         {
8319           rtx inner = XEXP (x, 0);
8320           unsigned HOST_WIDE_INT inner_mask;
8321
8322           /* Select the mask of the bits we need for the shift operand.  */
8323           inner_mask = mask << INTVAL (XEXP (x, 1));
8324
8325           /* We can only change the mode of the shift if we can do arithmetic
8326              in the mode of the shift and INNER_MASK is no wider than the
8327              width of X's mode.  */
8328           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8329             op_mode = GET_MODE (x);
8330
8331           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8332
8333           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8334             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8335         }
8336
8337       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8338          shift and AND produces only copies of the sign bit (C2 is one less
8339          than a power of two), we can do this with just a shift.  */
8340
8341       if (GET_CODE (x) == LSHIFTRT
8342           && CONST_INT_P (XEXP (x, 1))
8343           /* The shift puts one of the sign bit copies in the least significant
8344              bit.  */
8345           && ((INTVAL (XEXP (x, 1))
8346                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8347               >= GET_MODE_PRECISION (GET_MODE (x)))
8348           && exact_log2 (mask + 1) >= 0
8349           /* Number of bits left after the shift must be more than the mask
8350              needs.  */
8351           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8352               <= GET_MODE_PRECISION (GET_MODE (x)))
8353           /* Must be more sign bit copies than the mask needs.  */
8354           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8355               >= exact_log2 (mask + 1)))
8356         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8357                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8358                                           - exact_log2 (mask + 1)));
8359
8360       goto shiftrt;
8361
8362     case ASHIFTRT:
8363       /* If we are just looking for the sign bit, we don't need this shift at
8364          all, even if it has a variable count.  */
8365       if (val_signbit_p (GET_MODE (x), mask))
8366         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8367
8368       /* If this is a shift by a constant, get a mask that contains those bits
8369          that are not copies of the sign bit.  We then have two cases:  If
8370          MASK only includes those bits, this can be a logical shift, which may
8371          allow simplifications.  If MASK is a single-bit field not within
8372          those bits, we are requesting a copy of the sign bit and hence can
8373          shift the sign bit to the appropriate location.  */
8374
8375       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8376           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8377         {
8378           int i;
8379
8380           /* If the considered data is wider than HOST_WIDE_INT, we can't
8381              represent a mask for all its bits in a single scalar.
8382              But we only care about the lower bits, so calculate these.  */
8383
8384           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8385             {
8386               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8387
8388               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8389                  is the number of bits a full-width mask would have set.
8390                  We need only shift if these are fewer than nonzero can
8391                  hold.  If not, we must keep all bits set in nonzero.  */
8392
8393               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8394                   < HOST_BITS_PER_WIDE_INT)
8395                 nonzero >>= INTVAL (XEXP (x, 1))
8396                             + HOST_BITS_PER_WIDE_INT
8397                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8398             }
8399           else
8400             {
8401               nonzero = GET_MODE_MASK (GET_MODE (x));
8402               nonzero >>= INTVAL (XEXP (x, 1));
8403             }
8404
8405           if ((mask & ~nonzero) == 0)
8406             {
8407               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8408                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8409               if (GET_CODE (x) != ASHIFTRT)
8410                 return force_to_mode (x, mode, mask, next_select);
8411             }
8412
8413           else if ((i = exact_log2 (mask)) >= 0)
8414             {
8415               x = simplify_shift_const
8416                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8417                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8418
8419               if (GET_CODE (x) != ASHIFTRT)
8420                 return force_to_mode (x, mode, mask, next_select);
8421             }
8422         }
8423
8424       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8425          even if the shift count isn't a constant.  */
8426       if (mask == 1)
8427         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8428                                  XEXP (x, 0), XEXP (x, 1));
8429
8430     shiftrt:
8431
8432       /* If this is a zero- or sign-extension operation that just affects bits
8433          we don't care about, remove it.  Be sure the call above returned
8434          something that is still a shift.  */
8435
8436       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8437           && CONST_INT_P (XEXP (x, 1))
8438           && INTVAL (XEXP (x, 1)) >= 0
8439           && (INTVAL (XEXP (x, 1))
8440               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8441           && GET_CODE (XEXP (x, 0)) == ASHIFT
8442           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8443         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8444                               next_select);
8445
8446       break;
8447
8448     case ROTATE:
8449     case ROTATERT:
8450       /* If the shift count is constant and we can do computations
8451          in the mode of X, compute where the bits we care about are.
8452          Otherwise, we can't do anything.  Don't change the mode of
8453          the shift or propagate MODE into the shift, though.  */
8454       if (CONST_INT_P (XEXP (x, 1))
8455           && INTVAL (XEXP (x, 1)) >= 0)
8456         {
8457           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8458                                             GET_MODE (x),
8459                                             gen_int_mode (mask, GET_MODE (x)),
8460                                             XEXP (x, 1));
8461           if (temp && CONST_INT_P (temp))
8462             SUBST (XEXP (x, 0),
8463                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8464                                   INTVAL (temp), next_select));
8465         }
8466       break;
8467
8468     case NEG:
8469       /* If we just want the low-order bit, the NEG isn't needed since it
8470          won't change the low-order bit.  */
8471       if (mask == 1)
8472         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8473
8474       /* We need any bits less significant than the most significant bit in
8475          MASK since carries from those bits will affect the bits we are
8476          interested in.  */
8477       mask = fuller_mask;
8478       goto unop;
8479
8480     case NOT:
8481       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8482          same as the XOR case above.  Ensure that the constant we form is not
8483          wider than the mode of X.  */
8484
8485       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8486           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8487           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8488           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8489               < GET_MODE_PRECISION (GET_MODE (x)))
8490           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8491         {
8492           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8493                                GET_MODE (x));
8494           temp = simplify_gen_binary (XOR, GET_MODE (x),
8495                                       XEXP (XEXP (x, 0), 0), temp);
8496           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8497                                    temp, XEXP (XEXP (x, 0), 1));
8498
8499           return force_to_mode (x, mode, mask, next_select);
8500         }
8501
8502       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8503          use the full mask inside the NOT.  */
8504       mask = fuller_mask;
8505
8506     unop:
8507       op0 = gen_lowpart_or_truncate (op_mode,
8508                                      force_to_mode (XEXP (x, 0), mode, mask,
8509                                                     next_select));
8510       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8511         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8512       break;
8513
8514     case NE:
8515       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8516          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8517          which is equal to STORE_FLAG_VALUE.  */
8518       if ((mask & ~STORE_FLAG_VALUE) == 0
8519           && XEXP (x, 1) == const0_rtx
8520           && GET_MODE (XEXP (x, 0)) == mode
8521           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8522           && (nonzero_bits (XEXP (x, 0), mode)
8523               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8524         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8525
8526       break;
8527
8528     case IF_THEN_ELSE:
8529       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8530          written in a narrower mode.  We play it safe and do not do so.  */
8531
8532       SUBST (XEXP (x, 1),
8533              gen_lowpart_or_truncate (GET_MODE (x),
8534                                       force_to_mode (XEXP (x, 1), mode,
8535                                                      mask, next_select)));
8536       SUBST (XEXP (x, 2),
8537              gen_lowpart_or_truncate (GET_MODE (x),
8538                                       force_to_mode (XEXP (x, 2), mode,
8539                                                      mask, next_select)));
8540       break;
8541
8542     default:
8543       break;
8544     }
8545
8546   /* Ensure we return a value of the proper mode.  */
8547   return gen_lowpart_or_truncate (mode, x);
8548 }
8549 \f
8550 /* Return nonzero if X is an expression that has one of two values depending on
8551    whether some other value is zero or nonzero.  In that case, we return the
8552    value that is being tested, *PTRUE is set to the value if the rtx being
8553    returned has a nonzero value, and *PFALSE is set to the other alternative.
8554
8555    If we return zero, we set *PTRUE and *PFALSE to X.  */
8556
8557 static rtx
8558 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8559 {
8560   enum machine_mode mode = GET_MODE (x);
8561   enum rtx_code code = GET_CODE (x);
8562   rtx cond0, cond1, true0, true1, false0, false1;
8563   unsigned HOST_WIDE_INT nz;
8564
8565   /* If we are comparing a value against zero, we are done.  */
8566   if ((code == NE || code == EQ)
8567       && XEXP (x, 1) == const0_rtx)
8568     {
8569       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8570       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8571       return XEXP (x, 0);
8572     }
8573
8574   /* If this is a unary operation whose operand has one of two values, apply
8575      our opcode to compute those values.  */
8576   else if (UNARY_P (x)
8577            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8578     {
8579       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8580       *pfalse = simplify_gen_unary (code, mode, false0,
8581                                     GET_MODE (XEXP (x, 0)));
8582       return cond0;
8583     }
8584
8585   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8586      make can't possibly match and would suppress other optimizations.  */
8587   else if (code == COMPARE)
8588     ;
8589
8590   /* If this is a binary operation, see if either side has only one of two
8591      values.  If either one does or if both do and they are conditional on
8592      the same value, compute the new true and false values.  */
8593   else if (BINARY_P (x))
8594     {
8595       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8596       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8597
8598       if ((cond0 != 0 || cond1 != 0)
8599           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8600         {
8601           /* If if_then_else_cond returned zero, then true/false are the
8602              same rtl.  We must copy one of them to prevent invalid rtl
8603              sharing.  */
8604           if (cond0 == 0)
8605             true0 = copy_rtx (true0);
8606           else if (cond1 == 0)
8607             true1 = copy_rtx (true1);
8608
8609           if (COMPARISON_P (x))
8610             {
8611               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8612                                                 true0, true1);
8613               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8614                                                  false0, false1);
8615              }
8616           else
8617             {
8618               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8619               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8620             }
8621
8622           return cond0 ? cond0 : cond1;
8623         }
8624
8625       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8626          operands is zero when the other is nonzero, and vice-versa,
8627          and STORE_FLAG_VALUE is 1 or -1.  */
8628
8629       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8630           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8631               || code == UMAX)
8632           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8633         {
8634           rtx op0 = XEXP (XEXP (x, 0), 1);
8635           rtx op1 = XEXP (XEXP (x, 1), 1);
8636
8637           cond0 = XEXP (XEXP (x, 0), 0);
8638           cond1 = XEXP (XEXP (x, 1), 0);
8639
8640           if (COMPARISON_P (cond0)
8641               && COMPARISON_P (cond1)
8642               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8643                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8644                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8645                   || ((swap_condition (GET_CODE (cond0))
8646                        == reversed_comparison_code (cond1, NULL))
8647                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8648                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8649               && ! side_effects_p (x))
8650             {
8651               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8652               *pfalse = simplify_gen_binary (MULT, mode,
8653                                              (code == MINUS
8654                                               ? simplify_gen_unary (NEG, mode,
8655                                                                     op1, mode)
8656                                               : op1),
8657                                               const_true_rtx);
8658               return cond0;
8659             }
8660         }
8661
8662       /* Similarly for MULT, AND and UMIN, except that for these the result
8663          is always zero.  */
8664       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8665           && (code == MULT || code == AND || code == UMIN)
8666           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8667         {
8668           cond0 = XEXP (XEXP (x, 0), 0);
8669           cond1 = XEXP (XEXP (x, 1), 0);
8670
8671           if (COMPARISON_P (cond0)
8672               && COMPARISON_P (cond1)
8673               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8674                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8675                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8676                   || ((swap_condition (GET_CODE (cond0))
8677                        == reversed_comparison_code (cond1, NULL))
8678                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8679                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8680               && ! side_effects_p (x))
8681             {
8682               *ptrue = *pfalse = const0_rtx;
8683               return cond0;
8684             }
8685         }
8686     }
8687
8688   else if (code == IF_THEN_ELSE)
8689     {
8690       /* If we have IF_THEN_ELSE already, extract the condition and
8691          canonicalize it if it is NE or EQ.  */
8692       cond0 = XEXP (x, 0);
8693       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8694       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8695         return XEXP (cond0, 0);
8696       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8697         {
8698           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8699           return XEXP (cond0, 0);
8700         }
8701       else
8702         return cond0;
8703     }
8704
8705   /* If X is a SUBREG, we can narrow both the true and false values
8706      if the inner expression, if there is a condition.  */
8707   else if (code == SUBREG
8708            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8709                                                &true0, &false0)))
8710     {
8711       true0 = simplify_gen_subreg (mode, true0,
8712                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8713       false0 = simplify_gen_subreg (mode, false0,
8714                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8715       if (true0 && false0)
8716         {
8717           *ptrue = true0;
8718           *pfalse = false0;
8719           return cond0;
8720         }
8721     }
8722
8723   /* If X is a constant, this isn't special and will cause confusions
8724      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8725   else if (CONSTANT_P (x)
8726            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8727     ;
8728
8729   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8730      will be least confusing to the rest of the compiler.  */
8731   else if (mode == BImode)
8732     {
8733       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8734       return x;
8735     }
8736
8737   /* If X is known to be either 0 or -1, those are the true and
8738      false values when testing X.  */
8739   else if (x == constm1_rtx || x == const0_rtx
8740            || (mode != VOIDmode
8741                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8742     {
8743       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8744       return x;
8745     }
8746
8747   /* Likewise for 0 or a single bit.  */
8748   else if (HWI_COMPUTABLE_MODE_P (mode)
8749            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8750     {
8751       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8752       return x;
8753     }
8754
8755   /* Otherwise fail; show no condition with true and false values the same.  */
8756   *ptrue = *pfalse = x;
8757   return 0;
8758 }
8759 \f
8760 /* Return the value of expression X given the fact that condition COND
8761    is known to be true when applied to REG as its first operand and VAL
8762    as its second.  X is known to not be shared and so can be modified in
8763    place.
8764
8765    We only handle the simplest cases, and specifically those cases that
8766    arise with IF_THEN_ELSE expressions.  */
8767
8768 static rtx
8769 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8770 {
8771   enum rtx_code code = GET_CODE (x);
8772   rtx temp;
8773   const char *fmt;
8774   int i, j;
8775
8776   if (side_effects_p (x))
8777     return x;
8778
8779   /* If either operand of the condition is a floating point value,
8780      then we have to avoid collapsing an EQ comparison.  */
8781   if (cond == EQ
8782       && rtx_equal_p (x, reg)
8783       && ! FLOAT_MODE_P (GET_MODE (x))
8784       && ! FLOAT_MODE_P (GET_MODE (val)))
8785     return val;
8786
8787   if (cond == UNEQ && rtx_equal_p (x, reg))
8788     return val;
8789
8790   /* If X is (abs REG) and we know something about REG's relationship
8791      with zero, we may be able to simplify this.  */
8792
8793   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8794     switch (cond)
8795       {
8796       case GE:  case GT:  case EQ:
8797         return XEXP (x, 0);
8798       case LT:  case LE:
8799         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8800                                    XEXP (x, 0),
8801                                    GET_MODE (XEXP (x, 0)));
8802       default:
8803         break;
8804       }
8805
8806   /* The only other cases we handle are MIN, MAX, and comparisons if the
8807      operands are the same as REG and VAL.  */
8808
8809   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8810     {
8811       if (rtx_equal_p (XEXP (x, 0), val))
8812         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8813
8814       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8815         {
8816           if (COMPARISON_P (x))
8817             {
8818               if (comparison_dominates_p (cond, code))
8819                 return const_true_rtx;
8820
8821               code = reversed_comparison_code (x, NULL);
8822               if (code != UNKNOWN
8823                   && comparison_dominates_p (cond, code))
8824                 return const0_rtx;
8825               else
8826                 return x;
8827             }
8828           else if (code == SMAX || code == SMIN
8829                    || code == UMIN || code == UMAX)
8830             {
8831               int unsignedp = (code == UMIN || code == UMAX);
8832
8833               /* Do not reverse the condition when it is NE or EQ.
8834                  This is because we cannot conclude anything about
8835                  the value of 'SMAX (x, y)' when x is not equal to y,
8836                  but we can when x equals y.  */
8837               if ((code == SMAX || code == UMAX)
8838                   && ! (cond == EQ || cond == NE))
8839                 cond = reverse_condition (cond);
8840
8841               switch (cond)
8842                 {
8843                 case GE:   case GT:
8844                   return unsignedp ? x : XEXP (x, 1);
8845                 case LE:   case LT:
8846                   return unsignedp ? x : XEXP (x, 0);
8847                 case GEU:  case GTU:
8848                   return unsignedp ? XEXP (x, 1) : x;
8849                 case LEU:  case LTU:
8850                   return unsignedp ? XEXP (x, 0) : x;
8851                 default:
8852                   break;
8853                 }
8854             }
8855         }
8856     }
8857   else if (code == SUBREG)
8858     {
8859       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8860       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8861
8862       if (SUBREG_REG (x) != r)
8863         {
8864           /* We must simplify subreg here, before we lose track of the
8865              original inner_mode.  */
8866           new_rtx = simplify_subreg (GET_MODE (x), r,
8867                                  inner_mode, SUBREG_BYTE (x));
8868           if (new_rtx)
8869             return new_rtx;
8870           else
8871             SUBST (SUBREG_REG (x), r);
8872         }
8873
8874       return x;
8875     }
8876   /* We don't have to handle SIGN_EXTEND here, because even in the
8877      case of replacing something with a modeless CONST_INT, a
8878      CONST_INT is already (supposed to be) a valid sign extension for
8879      its narrower mode, which implies it's already properly
8880      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8881      story is different.  */
8882   else if (code == ZERO_EXTEND)
8883     {
8884       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8885       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8886
8887       if (XEXP (x, 0) != r)
8888         {
8889           /* We must simplify the zero_extend here, before we lose
8890              track of the original inner_mode.  */
8891           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8892                                           r, inner_mode);
8893           if (new_rtx)
8894             return new_rtx;
8895           else
8896             SUBST (XEXP (x, 0), r);
8897         }
8898
8899       return x;
8900     }
8901
8902   fmt = GET_RTX_FORMAT (code);
8903   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8904     {
8905       if (fmt[i] == 'e')
8906         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8907       else if (fmt[i] == 'E')
8908         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8909           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8910                                                 cond, reg, val));
8911     }
8912
8913   return x;
8914 }
8915 \f
8916 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8917    assignment as a field assignment.  */
8918
8919 static int
8920 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8921 {
8922   if (x == y || rtx_equal_p (x, y))
8923     return 1;
8924
8925   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8926     return 0;
8927
8928   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8929      Note that all SUBREGs of MEM are paradoxical; otherwise they
8930      would have been rewritten.  */
8931   if (MEM_P (x) && GET_CODE (y) == SUBREG
8932       && MEM_P (SUBREG_REG (y))
8933       && rtx_equal_p (SUBREG_REG (y),
8934                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8935     return 1;
8936
8937   if (MEM_P (y) && GET_CODE (x) == SUBREG
8938       && MEM_P (SUBREG_REG (x))
8939       && rtx_equal_p (SUBREG_REG (x),
8940                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8941     return 1;
8942
8943   /* We used to see if get_last_value of X and Y were the same but that's
8944      not correct.  In one direction, we'll cause the assignment to have
8945      the wrong destination and in the case, we'll import a register into this
8946      insn that might have already have been dead.   So fail if none of the
8947      above cases are true.  */
8948   return 0;
8949 }
8950 \f
8951 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8952    Return that assignment if so.
8953
8954    We only handle the most common cases.  */
8955
8956 static rtx
8957 make_field_assignment (rtx x)
8958 {
8959   rtx dest = SET_DEST (x);
8960   rtx src = SET_SRC (x);
8961   rtx assign;
8962   rtx rhs, lhs;
8963   HOST_WIDE_INT c1;
8964   HOST_WIDE_INT pos;
8965   unsigned HOST_WIDE_INT len;
8966   rtx other;
8967   enum machine_mode mode;
8968
8969   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8970      a clear of a one-bit field.  We will have changed it to
8971      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
8972      for a SUBREG.  */
8973
8974   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8975       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8976       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8977       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8978     {
8979       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8980                                 1, 1, 1, 0);
8981       if (assign != 0)
8982         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8983       return x;
8984     }
8985
8986   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8987       && subreg_lowpart_p (XEXP (src, 0))
8988       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8989           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8990       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8991       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8992       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8993       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8994     {
8995       assign = make_extraction (VOIDmode, dest, 0,
8996                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8997                                 1, 1, 1, 0);
8998       if (assign != 0)
8999         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9000       return x;
9001     }
9002
9003   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9004      one-bit field.  */
9005   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9006       && XEXP (XEXP (src, 0), 0) == const1_rtx
9007       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9008     {
9009       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9010                                 1, 1, 1, 0);
9011       if (assign != 0)
9012         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9013       return x;
9014     }
9015
9016   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9017      SRC is an AND with all bits of that field set, then we can discard
9018      the AND.  */
9019   if (GET_CODE (dest) == ZERO_EXTRACT
9020       && CONST_INT_P (XEXP (dest, 1))
9021       && GET_CODE (src) == AND
9022       && CONST_INT_P (XEXP (src, 1)))
9023     {
9024       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9025       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9026       unsigned HOST_WIDE_INT ze_mask;
9027
9028       if (width >= HOST_BITS_PER_WIDE_INT)
9029         ze_mask = -1;
9030       else
9031         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9032
9033       /* Complete overlap.  We can remove the source AND.  */
9034       if ((and_mask & ze_mask) == ze_mask)
9035         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9036
9037       /* Partial overlap.  We can reduce the source AND.  */
9038       if ((and_mask & ze_mask) != and_mask)
9039         {
9040           mode = GET_MODE (src);
9041           src = gen_rtx_AND (mode, XEXP (src, 0),
9042                              gen_int_mode (and_mask & ze_mask, mode));
9043           return gen_rtx_SET (VOIDmode, dest, src);
9044         }
9045     }
9046
9047   /* The other case we handle is assignments into a constant-position
9048      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9049      a mask that has all one bits except for a group of zero bits and
9050      OTHER is known to have zeros where C1 has ones, this is such an
9051      assignment.  Compute the position and length from C1.  Shift OTHER
9052      to the appropriate position, force it to the required mode, and
9053      make the extraction.  Check for the AND in both operands.  */
9054
9055   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9056     return x;
9057
9058   rhs = expand_compound_operation (XEXP (src, 0));
9059   lhs = expand_compound_operation (XEXP (src, 1));
9060
9061   if (GET_CODE (rhs) == AND
9062       && CONST_INT_P (XEXP (rhs, 1))
9063       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9064     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9065   else if (GET_CODE (lhs) == AND
9066            && CONST_INT_P (XEXP (lhs, 1))
9067            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9068     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9069   else
9070     return x;
9071
9072   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9073   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9074       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9075       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9076     return x;
9077
9078   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9079   if (assign == 0)
9080     return x;
9081
9082   /* The mode to use for the source is the mode of the assignment, or of
9083      what is inside a possible STRICT_LOW_PART.  */
9084   mode = (GET_CODE (assign) == STRICT_LOW_PART
9085           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9086
9087   /* Shift OTHER right POS places and make it the source, restricting it
9088      to the proper length and mode.  */
9089
9090   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9091                                                      GET_MODE (src),
9092                                                      other, pos),
9093                                dest);
9094   src = force_to_mode (src, mode,
9095                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9096                        ? ~(unsigned HOST_WIDE_INT) 0
9097                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9098                        0);
9099
9100   /* If SRC is masked by an AND that does not make a difference in
9101      the value being stored, strip it.  */
9102   if (GET_CODE (assign) == ZERO_EXTRACT
9103       && CONST_INT_P (XEXP (assign, 1))
9104       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9105       && GET_CODE (src) == AND
9106       && CONST_INT_P (XEXP (src, 1))
9107       && UINTVAL (XEXP (src, 1))
9108          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9109     src = XEXP (src, 0);
9110
9111   return gen_rtx_SET (VOIDmode, assign, src);
9112 }
9113 \f
9114 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9115    if so.  */
9116
9117 static rtx
9118 apply_distributive_law (rtx x)
9119 {
9120   enum rtx_code code = GET_CODE (x);
9121   enum rtx_code inner_code;
9122   rtx lhs, rhs, other;
9123   rtx tem;
9124
9125   /* Distributivity is not true for floating point as it can change the
9126      value.  So we don't do it unless -funsafe-math-optimizations.  */
9127   if (FLOAT_MODE_P (GET_MODE (x))
9128       && ! flag_unsafe_math_optimizations)
9129     return x;
9130
9131   /* The outer operation can only be one of the following:  */
9132   if (code != IOR && code != AND && code != XOR
9133       && code != PLUS && code != MINUS)
9134     return x;
9135
9136   lhs = XEXP (x, 0);
9137   rhs = XEXP (x, 1);
9138
9139   /* If either operand is a primitive we can't do anything, so get out
9140      fast.  */
9141   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9142     return x;
9143
9144   lhs = expand_compound_operation (lhs);
9145   rhs = expand_compound_operation (rhs);
9146   inner_code = GET_CODE (lhs);
9147   if (inner_code != GET_CODE (rhs))
9148     return x;
9149
9150   /* See if the inner and outer operations distribute.  */
9151   switch (inner_code)
9152     {
9153     case LSHIFTRT:
9154     case ASHIFTRT:
9155     case AND:
9156     case IOR:
9157       /* These all distribute except over PLUS.  */
9158       if (code == PLUS || code == MINUS)
9159         return x;
9160       break;
9161
9162     case MULT:
9163       if (code != PLUS && code != MINUS)
9164         return x;
9165       break;
9166
9167     case ASHIFT:
9168       /* This is also a multiply, so it distributes over everything.  */
9169       break;
9170
9171     /* This used to handle SUBREG, but this turned out to be counter-
9172        productive, since (subreg (op ...)) usually is not handled by
9173        insn patterns, and this "optimization" therefore transformed
9174        recognizable patterns into unrecognizable ones.  Therefore the
9175        SUBREG case was removed from here.
9176
9177        It is possible that distributing SUBREG over arithmetic operations
9178        leads to an intermediate result than can then be optimized further,
9179        e.g. by moving the outer SUBREG to the other side of a SET as done
9180        in simplify_set.  This seems to have been the original intent of
9181        handling SUBREGs here.
9182
9183        However, with current GCC this does not appear to actually happen,
9184        at least on major platforms.  If some case is found where removing
9185        the SUBREG case here prevents follow-on optimizations, distributing
9186        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9187
9188     default:
9189       return x;
9190     }
9191
9192   /* Set LHS and RHS to the inner operands (A and B in the example
9193      above) and set OTHER to the common operand (C in the example).
9194      There is only one way to do this unless the inner operation is
9195      commutative.  */
9196   if (COMMUTATIVE_ARITH_P (lhs)
9197       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9198     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9199   else if (COMMUTATIVE_ARITH_P (lhs)
9200            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9201     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9202   else if (COMMUTATIVE_ARITH_P (lhs)
9203            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9204     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9205   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9206     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9207   else
9208     return x;
9209
9210   /* Form the new inner operation, seeing if it simplifies first.  */
9211   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9212
9213   /* There is one exception to the general way of distributing:
9214      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9215   if (code == XOR && inner_code == IOR)
9216     {
9217       inner_code = AND;
9218       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9219     }
9220
9221   /* We may be able to continuing distributing the result, so call
9222      ourselves recursively on the inner operation before forming the
9223      outer operation, which we return.  */
9224   return simplify_gen_binary (inner_code, GET_MODE (x),
9225                               apply_distributive_law (tem), other);
9226 }
9227
9228 /* See if X is of the form (* (+ A B) C), and if so convert to
9229    (+ (* A C) (* B C)) and try to simplify.
9230
9231    Most of the time, this results in no change.  However, if some of
9232    the operands are the same or inverses of each other, simplifications
9233    will result.
9234
9235    For example, (and (ior A B) (not B)) can occur as the result of
9236    expanding a bit field assignment.  When we apply the distributive
9237    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9238    which then simplifies to (and (A (not B))).
9239
9240    Note that no checks happen on the validity of applying the inverse
9241    distributive law.  This is pointless since we can do it in the
9242    few places where this routine is called.
9243
9244    N is the index of the term that is decomposed (the arithmetic operation,
9245    i.e. (+ A B) in the first example above).  !N is the index of the term that
9246    is distributed, i.e. of C in the first example above.  */
9247 static rtx
9248 distribute_and_simplify_rtx (rtx x, int n)
9249 {
9250   enum machine_mode mode;
9251   enum rtx_code outer_code, inner_code;
9252   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9253
9254   /* Distributivity is not true for floating point as it can change the
9255      value.  So we don't do it unless -funsafe-math-optimizations.  */
9256   if (FLOAT_MODE_P (GET_MODE (x))
9257       && ! flag_unsafe_math_optimizations)
9258     return NULL_RTX;
9259
9260   decomposed = XEXP (x, n);
9261   if (!ARITHMETIC_P (decomposed))
9262     return NULL_RTX;
9263
9264   mode = GET_MODE (x);
9265   outer_code = GET_CODE (x);
9266   distributed = XEXP (x, !n);
9267
9268   inner_code = GET_CODE (decomposed);
9269   inner_op0 = XEXP (decomposed, 0);
9270   inner_op1 = XEXP (decomposed, 1);
9271
9272   /* Special case (and (xor B C) (not A)), which is equivalent to
9273      (xor (ior A B) (ior A C))  */
9274   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9275     {
9276       distributed = XEXP (distributed, 0);
9277       outer_code = IOR;
9278     }
9279
9280   if (n == 0)
9281     {
9282       /* Distribute the second term.  */
9283       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9284       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9285     }
9286   else
9287     {
9288       /* Distribute the first term.  */
9289       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9290       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9291     }
9292
9293   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9294                                                      new_op0, new_op1));
9295   if (GET_CODE (tmp) != outer_code
9296       && (set_src_cost (tmp, optimize_this_for_speed_p)
9297           < set_src_cost (x, optimize_this_for_speed_p)))
9298     return tmp;
9299
9300   return NULL_RTX;
9301 }
9302 \f
9303 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9304    in MODE.  Return an equivalent form, if different from (and VAROP
9305    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9306
9307 static rtx
9308 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9309                           unsigned HOST_WIDE_INT constop)
9310 {
9311   unsigned HOST_WIDE_INT nonzero;
9312   unsigned HOST_WIDE_INT orig_constop;
9313   rtx orig_varop;
9314   int i;
9315
9316   orig_varop = varop;
9317   orig_constop = constop;
9318   if (GET_CODE (varop) == CLOBBER)
9319     return NULL_RTX;
9320
9321   /* Simplify VAROP knowing that we will be only looking at some of the
9322      bits in it.
9323
9324      Note by passing in CONSTOP, we guarantee that the bits not set in
9325      CONSTOP are not significant and will never be examined.  We must
9326      ensure that is the case by explicitly masking out those bits
9327      before returning.  */
9328   varop = force_to_mode (varop, mode, constop, 0);
9329
9330   /* If VAROP is a CLOBBER, we will fail so return it.  */
9331   if (GET_CODE (varop) == CLOBBER)
9332     return varop;
9333
9334   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9335      to VAROP and return the new constant.  */
9336   if (CONST_INT_P (varop))
9337     return gen_int_mode (INTVAL (varop) & constop, mode);
9338
9339   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9340      a call to nonzero_bits, here we don't care about bits outside
9341      MODE.  */
9342
9343   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9344
9345   /* Turn off all bits in the constant that are known to already be zero.
9346      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9347      which is tested below.  */
9348
9349   constop &= nonzero;
9350
9351   /* If we don't have any bits left, return zero.  */
9352   if (constop == 0)
9353     return const0_rtx;
9354
9355   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9356      a power of two, we can replace this with an ASHIFT.  */
9357   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9358       && (i = exact_log2 (constop)) >= 0)
9359     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9360
9361   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9362      or XOR, then try to apply the distributive law.  This may eliminate
9363      operations if either branch can be simplified because of the AND.
9364      It may also make some cases more complex, but those cases probably
9365      won't match a pattern either with or without this.  */
9366
9367   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9368     return
9369       gen_lowpart
9370         (mode,
9371          apply_distributive_law
9372          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9373                                simplify_and_const_int (NULL_RTX,
9374                                                        GET_MODE (varop),
9375                                                        XEXP (varop, 0),
9376                                                        constop),
9377                                simplify_and_const_int (NULL_RTX,
9378                                                        GET_MODE (varop),
9379                                                        XEXP (varop, 1),
9380                                                        constop))));
9381
9382   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9383      the AND and see if one of the operands simplifies to zero.  If so, we
9384      may eliminate it.  */
9385
9386   if (GET_CODE (varop) == PLUS
9387       && exact_log2 (constop + 1) >= 0)
9388     {
9389       rtx o0, o1;
9390
9391       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9392       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9393       if (o0 == const0_rtx)
9394         return o1;
9395       if (o1 == const0_rtx)
9396         return o0;
9397     }
9398
9399   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9400   varop = gen_lowpart (mode, varop);
9401   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9402     return NULL_RTX;
9403
9404   /* If we are only masking insignificant bits, return VAROP.  */
9405   if (constop == nonzero)
9406     return varop;
9407
9408   if (varop == orig_varop && constop == orig_constop)
9409     return NULL_RTX;
9410
9411   /* Otherwise, return an AND.  */
9412   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9413 }
9414
9415
9416 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9417    in MODE.
9418
9419    Return an equivalent form, if different from X.  Otherwise, return X.  If
9420    X is zero, we are to always construct the equivalent form.  */
9421
9422 static rtx
9423 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9424                         unsigned HOST_WIDE_INT constop)
9425 {
9426   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9427   if (tem)
9428     return tem;
9429
9430   if (!x)
9431     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9432                              gen_int_mode (constop, mode));
9433   if (GET_MODE (x) != mode)
9434     x = gen_lowpart (mode, x);
9435   return x;
9436 }
9437 \f
9438 /* Given a REG, X, compute which bits in X can be nonzero.
9439    We don't care about bits outside of those defined in MODE.
9440
9441    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9442    a shift, AND, or zero_extract, we can do better.  */
9443
9444 static rtx
9445 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9446                               const_rtx known_x ATTRIBUTE_UNUSED,
9447                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9448                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9449                               unsigned HOST_WIDE_INT *nonzero)
9450 {
9451   rtx tem;
9452   reg_stat_type *rsp;
9453
9454   /* If X is a register whose nonzero bits value is current, use it.
9455      Otherwise, if X is a register whose value we can find, use that
9456      value.  Otherwise, use the previously-computed global nonzero bits
9457      for this register.  */
9458
9459   rsp = &reg_stat[REGNO (x)];
9460   if (rsp->last_set_value != 0
9461       && (rsp->last_set_mode == mode
9462           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9463               && GET_MODE_CLASS (mode) == MODE_INT))
9464       && ((rsp->last_set_label >= label_tick_ebb_start
9465            && rsp->last_set_label < label_tick)
9466           || (rsp->last_set_label == label_tick
9467               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9468           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9469               && REG_N_SETS (REGNO (x)) == 1
9470               && !REGNO_REG_SET_P
9471                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9472     {
9473       *nonzero &= rsp->last_set_nonzero_bits;
9474       return NULL;
9475     }
9476
9477   tem = get_last_value (x);
9478
9479   if (tem)
9480     {
9481 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9482       /* If X is narrower than MODE and TEM is a non-negative
9483          constant that would appear negative in the mode of X,
9484          sign-extend it for use in reg_nonzero_bits because some
9485          machines (maybe most) will actually do the sign-extension
9486          and this is the conservative approach.
9487
9488          ??? For 2.5, try to tighten up the MD files in this regard
9489          instead of this kludge.  */
9490
9491       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9492           && CONST_INT_P (tem)
9493           && INTVAL (tem) > 0
9494           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9495         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9496 #endif
9497       return tem;
9498     }
9499   else if (nonzero_sign_valid && rsp->nonzero_bits)
9500     {
9501       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9502
9503       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9504         /* We don't know anything about the upper bits.  */
9505         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9506       *nonzero &= mask;
9507     }
9508
9509   return NULL;
9510 }
9511
9512 /* Return the number of bits at the high-order end of X that are known to
9513    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9514    VOIDmode, X will be used in its own mode.  The returned value  will always
9515    be between 1 and the number of bits in MODE.  */
9516
9517 static rtx
9518 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9519                                      const_rtx known_x ATTRIBUTE_UNUSED,
9520                                      enum machine_mode known_mode
9521                                      ATTRIBUTE_UNUSED,
9522                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9523                                      unsigned int *result)
9524 {
9525   rtx tem;
9526   reg_stat_type *rsp;
9527
9528   rsp = &reg_stat[REGNO (x)];
9529   if (rsp->last_set_value != 0
9530       && rsp->last_set_mode == mode
9531       && ((rsp->last_set_label >= label_tick_ebb_start
9532            && rsp->last_set_label < label_tick)
9533           || (rsp->last_set_label == label_tick
9534               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9535           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9536               && REG_N_SETS (REGNO (x)) == 1
9537               && !REGNO_REG_SET_P
9538                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9539     {
9540       *result = rsp->last_set_sign_bit_copies;
9541       return NULL;
9542     }
9543
9544   tem = get_last_value (x);
9545   if (tem != 0)
9546     return tem;
9547
9548   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9549       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9550     *result = rsp->sign_bit_copies;
9551
9552   return NULL;
9553 }
9554 \f
9555 /* Return the number of "extended" bits there are in X, when interpreted
9556    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9557    unsigned quantities, this is the number of high-order zero bits.
9558    For signed quantities, this is the number of copies of the sign bit
9559    minus 1.  In both case, this function returns the number of "spare"
9560    bits.  For example, if two quantities for which this function returns
9561    at least 1 are added, the addition is known not to overflow.
9562
9563    This function will always return 0 unless called during combine, which
9564    implies that it must be called from a define_split.  */
9565
9566 unsigned int
9567 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9568 {
9569   if (nonzero_sign_valid == 0)
9570     return 0;
9571
9572   return (unsignedp
9573           ? (HWI_COMPUTABLE_MODE_P (mode)
9574              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9575                                - floor_log2 (nonzero_bits (x, mode)))
9576              : 0)
9577           : num_sign_bit_copies (x, mode) - 1);
9578 }
9579
9580 /* This function is called from `simplify_shift_const' to merge two
9581    outer operations.  Specifically, we have already found that we need
9582    to perform operation *POP0 with constant *PCONST0 at the outermost
9583    position.  We would now like to also perform OP1 with constant CONST1
9584    (with *POP0 being done last).
9585
9586    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9587    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9588    complement the innermost operand, otherwise it is unchanged.
9589
9590    MODE is the mode in which the operation will be done.  No bits outside
9591    the width of this mode matter.  It is assumed that the width of this mode
9592    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9593
9594    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9595    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9596    result is simply *PCONST0.
9597
9598    If the resulting operation cannot be expressed as one operation, we
9599    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9600
9601 static int
9602 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9603 {
9604   enum rtx_code op0 = *pop0;
9605   HOST_WIDE_INT const0 = *pconst0;
9606
9607   const0 &= GET_MODE_MASK (mode);
9608   const1 &= GET_MODE_MASK (mode);
9609
9610   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9611   if (op0 == AND)
9612     const1 &= const0;
9613
9614   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9615      if OP0 is SET.  */
9616
9617   if (op1 == UNKNOWN || op0 == SET)
9618     return 1;
9619
9620   else if (op0 == UNKNOWN)
9621     op0 = op1, const0 = const1;
9622
9623   else if (op0 == op1)
9624     {
9625       switch (op0)
9626         {
9627         case AND:
9628           const0 &= const1;
9629           break;
9630         case IOR:
9631           const0 |= const1;
9632           break;
9633         case XOR:
9634           const0 ^= const1;
9635           break;
9636         case PLUS:
9637           const0 += const1;
9638           break;
9639         case NEG:
9640           op0 = UNKNOWN;
9641           break;
9642         default:
9643           break;
9644         }
9645     }
9646
9647   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9648   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9649     return 0;
9650
9651   /* If the two constants aren't the same, we can't do anything.  The
9652      remaining six cases can all be done.  */
9653   else if (const0 != const1)
9654     return 0;
9655
9656   else
9657     switch (op0)
9658       {
9659       case IOR:
9660         if (op1 == AND)
9661           /* (a & b) | b == b */
9662           op0 = SET;
9663         else /* op1 == XOR */
9664           /* (a ^ b) | b == a | b */
9665           {;}
9666         break;
9667
9668       case XOR:
9669         if (op1 == AND)
9670           /* (a & b) ^ b == (~a) & b */
9671           op0 = AND, *pcomp_p = 1;
9672         else /* op1 == IOR */
9673           /* (a | b) ^ b == a & ~b */
9674           op0 = AND, const0 = ~const0;
9675         break;
9676
9677       case AND:
9678         if (op1 == IOR)
9679           /* (a | b) & b == b */
9680         op0 = SET;
9681         else /* op1 == XOR */
9682           /* (a ^ b) & b) == (~a) & b */
9683           *pcomp_p = 1;
9684         break;
9685       default:
9686         break;
9687       }
9688
9689   /* Check for NO-OP cases.  */
9690   const0 &= GET_MODE_MASK (mode);
9691   if (const0 == 0
9692       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9693     op0 = UNKNOWN;
9694   else if (const0 == 0 && op0 == AND)
9695     op0 = SET;
9696   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9697            && op0 == AND)
9698     op0 = UNKNOWN;
9699
9700   *pop0 = op0;
9701
9702   /* ??? Slightly redundant with the above mask, but not entirely.
9703      Moving this above means we'd have to sign-extend the mode mask
9704      for the final test.  */
9705   if (op0 != UNKNOWN && op0 != NEG)
9706     *pconst0 = trunc_int_for_mode (const0, mode);
9707
9708   return 1;
9709 }
9710 \f
9711 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9712    the shift in.  The original shift operation CODE is performed on OP in
9713    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9714    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9715    result of the shift is subject to operation OUTER_CODE with operand
9716    OUTER_CONST.  */
9717
9718 static enum machine_mode
9719 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9720                       enum machine_mode orig_mode, enum machine_mode mode,
9721                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9722 {
9723   if (orig_mode == mode)
9724     return mode;
9725   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9726
9727   /* In general we can't perform in wider mode for right shift and rotate.  */
9728   switch (code)
9729     {
9730     case ASHIFTRT:
9731       /* We can still widen if the bits brought in from the left are identical
9732          to the sign bit of ORIG_MODE.  */
9733       if (num_sign_bit_copies (op, mode)
9734           > (unsigned) (GET_MODE_PRECISION (mode)
9735                         - GET_MODE_PRECISION (orig_mode)))
9736         return mode;
9737       return orig_mode;
9738
9739     case LSHIFTRT:
9740       /* Similarly here but with zero bits.  */
9741       if (HWI_COMPUTABLE_MODE_P (mode)
9742           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9743         return mode;
9744
9745       /* We can also widen if the bits brought in will be masked off.  This
9746          operation is performed in ORIG_MODE.  */
9747       if (outer_code == AND)
9748         {
9749           int care_bits = low_bitmask_len (orig_mode, outer_const);
9750
9751           if (care_bits >= 0
9752               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9753             return mode;
9754         }
9755       /* fall through */
9756
9757     case ROTATE:
9758       return orig_mode;
9759
9760     case ROTATERT:
9761       gcc_unreachable ();
9762
9763     default:
9764       return mode;
9765     }
9766 }
9767
9768 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9769    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9770    if we cannot simplify it.  Otherwise, return a simplified value.
9771
9772    The shift is normally computed in the widest mode we find in VAROP, as
9773    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9774    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9775
9776 static rtx
9777 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9778                         rtx varop, int orig_count)
9779 {
9780   enum rtx_code orig_code = code;
9781   rtx orig_varop = varop;
9782   int count;
9783   enum machine_mode mode = result_mode;
9784   enum machine_mode shift_mode, tmode;
9785   unsigned int mode_words
9786     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9787   /* We form (outer_op (code varop count) (outer_const)).  */
9788   enum rtx_code outer_op = UNKNOWN;
9789   HOST_WIDE_INT outer_const = 0;
9790   int complement_p = 0;
9791   rtx new_rtx, x;
9792
9793   /* Make sure and truncate the "natural" shift on the way in.  We don't
9794      want to do this inside the loop as it makes it more difficult to
9795      combine shifts.  */
9796   if (SHIFT_COUNT_TRUNCATED)
9797     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9798
9799   /* If we were given an invalid count, don't do anything except exactly
9800      what was requested.  */
9801
9802   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9803     return NULL_RTX;
9804
9805   count = orig_count;
9806
9807   /* Unless one of the branches of the `if' in this loop does a `continue',
9808      we will `break' the loop after the `if'.  */
9809
9810   while (count != 0)
9811     {
9812       /* If we have an operand of (clobber (const_int 0)), fail.  */
9813       if (GET_CODE (varop) == CLOBBER)
9814         return NULL_RTX;
9815
9816       /* Convert ROTATERT to ROTATE.  */
9817       if (code == ROTATERT)
9818         {
9819           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9820           code = ROTATE;
9821           if (VECTOR_MODE_P (result_mode))
9822             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9823           else
9824             count = bitsize - count;
9825         }
9826
9827       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9828                                          mode, outer_op, outer_const);
9829
9830       /* Handle cases where the count is greater than the size of the mode
9831          minus 1.  For ASHIFT, use the size minus one as the count (this can
9832          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9833          take the count modulo the size.  For other shifts, the result is
9834          zero.
9835
9836          Since these shifts are being produced by the compiler by combining
9837          multiple operations, each of which are defined, we know what the
9838          result is supposed to be.  */
9839
9840       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9841         {
9842           if (code == ASHIFTRT)
9843             count = GET_MODE_PRECISION (shift_mode) - 1;
9844           else if (code == ROTATE || code == ROTATERT)
9845             count %= GET_MODE_PRECISION (shift_mode);
9846           else
9847             {
9848               /* We can't simply return zero because there may be an
9849                  outer op.  */
9850               varop = const0_rtx;
9851               count = 0;
9852               break;
9853             }
9854         }
9855
9856       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9857          here would cause an infinite loop.  */
9858       if (complement_p)
9859         break;
9860
9861       /* An arithmetic right shift of a quantity known to be -1 or 0
9862          is a no-op.  */
9863       if (code == ASHIFTRT
9864           && (num_sign_bit_copies (varop, shift_mode)
9865               == GET_MODE_PRECISION (shift_mode)))
9866         {
9867           count = 0;
9868           break;
9869         }
9870
9871       /* If we are doing an arithmetic right shift and discarding all but
9872          the sign bit copies, this is equivalent to doing a shift by the
9873          bitsize minus one.  Convert it into that shift because it will often
9874          allow other simplifications.  */
9875
9876       if (code == ASHIFTRT
9877           && (count + num_sign_bit_copies (varop, shift_mode)
9878               >= GET_MODE_PRECISION (shift_mode)))
9879         count = GET_MODE_PRECISION (shift_mode) - 1;
9880
9881       /* We simplify the tests below and elsewhere by converting
9882          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9883          `make_compound_operation' will convert it to an ASHIFTRT for
9884          those machines (such as VAX) that don't have an LSHIFTRT.  */
9885       if (code == ASHIFTRT
9886           && val_signbit_known_clear_p (shift_mode,
9887                                         nonzero_bits (varop, shift_mode)))
9888         code = LSHIFTRT;
9889
9890       if (((code == LSHIFTRT
9891             && HWI_COMPUTABLE_MODE_P (shift_mode)
9892             && !(nonzero_bits (varop, shift_mode) >> count))
9893            || (code == ASHIFT
9894                && HWI_COMPUTABLE_MODE_P (shift_mode)
9895                && !((nonzero_bits (varop, shift_mode) << count)
9896                     & GET_MODE_MASK (shift_mode))))
9897           && !side_effects_p (varop))
9898         varop = const0_rtx;
9899
9900       switch (GET_CODE (varop))
9901         {
9902         case SIGN_EXTEND:
9903         case ZERO_EXTEND:
9904         case SIGN_EXTRACT:
9905         case ZERO_EXTRACT:
9906           new_rtx = expand_compound_operation (varop);
9907           if (new_rtx != varop)
9908             {
9909               varop = new_rtx;
9910               continue;
9911             }
9912           break;
9913
9914         case MEM:
9915           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9916              minus the width of a smaller mode, we can do this with a
9917              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9918           if ((code == ASHIFTRT || code == LSHIFTRT)
9919               && ! mode_dependent_address_p (XEXP (varop, 0),
9920                                              MEM_ADDR_SPACE (varop))
9921               && ! MEM_VOLATILE_P (varop)
9922               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9923                                          MODE_INT, 1)) != BLKmode)
9924             {
9925               new_rtx = adjust_address_nv (varop, tmode,
9926                                        BYTES_BIG_ENDIAN ? 0
9927                                        : count / BITS_PER_UNIT);
9928
9929               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9930                                      : ZERO_EXTEND, mode, new_rtx);
9931               count = 0;
9932               continue;
9933             }
9934           break;
9935
9936         case SUBREG:
9937           /* If VAROP is a SUBREG, strip it as long as the inner operand has
9938              the same number of words as what we've seen so far.  Then store
9939              the widest mode in MODE.  */
9940           if (subreg_lowpart_p (varop)
9941               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9942                   > GET_MODE_SIZE (GET_MODE (varop)))
9943               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9944                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9945                  == mode_words
9946               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9947               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9948             {
9949               varop = SUBREG_REG (varop);
9950               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9951                 mode = GET_MODE (varop);
9952               continue;
9953             }
9954           break;
9955
9956         case MULT:
9957           /* Some machines use MULT instead of ASHIFT because MULT
9958              is cheaper.  But it is still better on those machines to
9959              merge two shifts into one.  */
9960           if (CONST_INT_P (XEXP (varop, 1))
9961               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9962             {
9963               varop
9964                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9965                                        XEXP (varop, 0),
9966                                        GEN_INT (exact_log2 (
9967                                                 UINTVAL (XEXP (varop, 1)))));
9968               continue;
9969             }
9970           break;
9971
9972         case UDIV:
9973           /* Similar, for when divides are cheaper.  */
9974           if (CONST_INT_P (XEXP (varop, 1))
9975               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9976             {
9977               varop
9978                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9979                                        XEXP (varop, 0),
9980                                        GEN_INT (exact_log2 (
9981                                                 UINTVAL (XEXP (varop, 1)))));
9982               continue;
9983             }
9984           break;
9985
9986         case ASHIFTRT:
9987           /* If we are extracting just the sign bit of an arithmetic
9988              right shift, that shift is not needed.  However, the sign
9989              bit of a wider mode may be different from what would be
9990              interpreted as the sign bit in a narrower mode, so, if
9991              the result is narrower, don't discard the shift.  */
9992           if (code == LSHIFTRT
9993               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9994               && (GET_MODE_BITSIZE (result_mode)
9995                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
9996             {
9997               varop = XEXP (varop, 0);
9998               continue;
9999             }
10000
10001           /* ... fall through ...  */
10002
10003         case LSHIFTRT:
10004         case ASHIFT:
10005         case ROTATE:
10006           /* Here we have two nested shifts.  The result is usually the
10007              AND of a new shift with a mask.  We compute the result below.  */
10008           if (CONST_INT_P (XEXP (varop, 1))
10009               && INTVAL (XEXP (varop, 1)) >= 0
10010               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10011               && HWI_COMPUTABLE_MODE_P (result_mode)
10012               && HWI_COMPUTABLE_MODE_P (mode)
10013               && !VECTOR_MODE_P (result_mode))
10014             {
10015               enum rtx_code first_code = GET_CODE (varop);
10016               unsigned int first_count = INTVAL (XEXP (varop, 1));
10017               unsigned HOST_WIDE_INT mask;
10018               rtx mask_rtx;
10019
10020               /* We have one common special case.  We can't do any merging if
10021                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10022                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10023                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10024                  we can convert it to
10025                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10026                  This simplifies certain SIGN_EXTEND operations.  */
10027               if (code == ASHIFT && first_code == ASHIFTRT
10028                   && count == (GET_MODE_PRECISION (result_mode)
10029                                - GET_MODE_PRECISION (GET_MODE (varop))))
10030                 {
10031                   /* C3 has the low-order C1 bits zero.  */
10032
10033                   mask = GET_MODE_MASK (mode)
10034                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10035
10036                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10037                                                   XEXP (varop, 0), mask);
10038                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10039                                                 varop, count);
10040                   count = first_count;
10041                   code = ASHIFTRT;
10042                   continue;
10043                 }
10044
10045               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10046                  than C1 high-order bits equal to the sign bit, we can convert
10047                  this to either an ASHIFT or an ASHIFTRT depending on the
10048                  two counts.
10049
10050                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10051
10052               if (code == ASHIFTRT && first_code == ASHIFT
10053                   && GET_MODE (varop) == shift_mode
10054                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10055                       > first_count))
10056                 {
10057                   varop = XEXP (varop, 0);
10058                   count -= first_count;
10059                   if (count < 0)
10060                     {
10061                       count = -count;
10062                       code = ASHIFT;
10063                     }
10064
10065                   continue;
10066                 }
10067
10068               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10069                  we can only do this if FIRST_CODE is also ASHIFTRT.
10070
10071                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10072                  ASHIFTRT.
10073
10074                  If the mode of this shift is not the mode of the outer shift,
10075                  we can't do this if either shift is a right shift or ROTATE.
10076
10077                  Finally, we can't do any of these if the mode is too wide
10078                  unless the codes are the same.
10079
10080                  Handle the case where the shift codes are the same
10081                  first.  */
10082
10083               if (code == first_code)
10084                 {
10085                   if (GET_MODE (varop) != result_mode
10086                       && (code == ASHIFTRT || code == LSHIFTRT
10087                           || code == ROTATE))
10088                     break;
10089
10090                   count += first_count;
10091                   varop = XEXP (varop, 0);
10092                   continue;
10093                 }
10094
10095               if (code == ASHIFTRT
10096                   || (code == ROTATE && first_code == ASHIFTRT)
10097                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10098                   || (GET_MODE (varop) != result_mode
10099                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10100                           || first_code == ROTATE
10101                           || code == ROTATE)))
10102                 break;
10103
10104               /* To compute the mask to apply after the shift, shift the
10105                  nonzero bits of the inner shift the same way the
10106                  outer shift will.  */
10107
10108               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10109                                        result_mode);
10110
10111               mask_rtx
10112                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10113                                                    GEN_INT (count));
10114
10115               /* Give up if we can't compute an outer operation to use.  */
10116               if (mask_rtx == 0
10117                   || !CONST_INT_P (mask_rtx)
10118                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10119                                         INTVAL (mask_rtx),
10120                                         result_mode, &complement_p))
10121                 break;
10122
10123               /* If the shifts are in the same direction, we add the
10124                  counts.  Otherwise, we subtract them.  */
10125               if ((code == ASHIFTRT || code == LSHIFTRT)
10126                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10127                 count += first_count;
10128               else
10129                 count -= first_count;
10130
10131               /* If COUNT is positive, the new shift is usually CODE,
10132                  except for the two exceptions below, in which case it is
10133                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10134                  always be used  */
10135               if (count > 0
10136                   && ((first_code == ROTATE && code == ASHIFT)
10137                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10138                 code = first_code;
10139               else if (count < 0)
10140                 code = first_code, count = -count;
10141
10142               varop = XEXP (varop, 0);
10143               continue;
10144             }
10145
10146           /* If we have (A << B << C) for any shift, we can convert this to
10147              (A << C << B).  This wins if A is a constant.  Only try this if
10148              B is not a constant.  */
10149
10150           else if (GET_CODE (varop) == code
10151                    && CONST_INT_P (XEXP (varop, 0))
10152                    && !CONST_INT_P (XEXP (varop, 1)))
10153             {
10154               rtx new_rtx = simplify_const_binary_operation (code, mode,
10155                                                          XEXP (varop, 0),
10156                                                          GEN_INT (count));
10157               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10158               count = 0;
10159               continue;
10160             }
10161           break;
10162
10163         case NOT:
10164           if (VECTOR_MODE_P (mode))
10165             break;
10166
10167           /* Make this fit the case below.  */
10168           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10169           continue;
10170
10171         case IOR:
10172         case AND:
10173         case XOR:
10174           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10175              with C the size of VAROP - 1 and the shift is logical if
10176              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10177              we have an (le X 0) operation.   If we have an arithmetic shift
10178              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10179              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10180
10181           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10182               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10183               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10184               && (code == LSHIFTRT || code == ASHIFTRT)
10185               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10186               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10187             {
10188               count = 0;
10189               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10190                                   const0_rtx);
10191
10192               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10193                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10194
10195               continue;
10196             }
10197
10198           /* If we have (shift (logical)), move the logical to the outside
10199              to allow it to possibly combine with another logical and the
10200              shift to combine with another shift.  This also canonicalizes to
10201              what a ZERO_EXTRACT looks like.  Also, some machines have
10202              (and (shift)) insns.  */
10203
10204           if (CONST_INT_P (XEXP (varop, 1))
10205               /* We can't do this if we have (ashiftrt (xor))  and the
10206                  constant has its sign bit set in shift_mode.  */
10207               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10208                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10209                                               shift_mode))
10210               && (new_rtx = simplify_const_binary_operation
10211                   (code, result_mode,
10212                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10213                    GEN_INT (count))) != 0
10214               && CONST_INT_P (new_rtx)
10215               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10216                                   INTVAL (new_rtx), result_mode, &complement_p))
10217             {
10218               varop = XEXP (varop, 0);
10219               continue;
10220             }
10221
10222           /* If we can't do that, try to simplify the shift in each arm of the
10223              logical expression, make a new logical expression, and apply
10224              the inverse distributive law.  This also can't be done
10225              for some (ashiftrt (xor)).  */
10226           if (CONST_INT_P (XEXP (varop, 1))
10227              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10228                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10229                                              shift_mode)))
10230             {
10231               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10232                                               XEXP (varop, 0), count);
10233               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10234                                               XEXP (varop, 1), count);
10235
10236               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10237                                            lhs, rhs);
10238               varop = apply_distributive_law (varop);
10239
10240               count = 0;
10241               continue;
10242             }
10243           break;
10244
10245         case EQ:
10246           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10247              says that the sign bit can be tested, FOO has mode MODE, C is
10248              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10249              that may be nonzero.  */
10250           if (code == LSHIFTRT
10251               && XEXP (varop, 1) == const0_rtx
10252               && GET_MODE (XEXP (varop, 0)) == result_mode
10253               && count == (GET_MODE_PRECISION (result_mode) - 1)
10254               && HWI_COMPUTABLE_MODE_P (result_mode)
10255               && STORE_FLAG_VALUE == -1
10256               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10257               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10258                                   &complement_p))
10259             {
10260               varop = XEXP (varop, 0);
10261               count = 0;
10262               continue;
10263             }
10264           break;
10265
10266         case NEG:
10267           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10268              than the number of bits in the mode is equivalent to A.  */
10269           if (code == LSHIFTRT
10270               && count == (GET_MODE_PRECISION (result_mode) - 1)
10271               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10272             {
10273               varop = XEXP (varop, 0);
10274               count = 0;
10275               continue;
10276             }
10277
10278           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10279              NEG outside to allow shifts to combine.  */
10280           if (code == ASHIFT
10281               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10282                                   &complement_p))
10283             {
10284               varop = XEXP (varop, 0);
10285               continue;
10286             }
10287           break;
10288
10289         case PLUS:
10290           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10291              is one less than the number of bits in the mode is
10292              equivalent to (xor A 1).  */
10293           if (code == LSHIFTRT
10294               && count == (GET_MODE_PRECISION (result_mode) - 1)
10295               && XEXP (varop, 1) == constm1_rtx
10296               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10297               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10298                                   &complement_p))
10299             {
10300               count = 0;
10301               varop = XEXP (varop, 0);
10302               continue;
10303             }
10304
10305           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10306              that might be nonzero in BAR are those being shifted out and those
10307              bits are known zero in FOO, we can replace the PLUS with FOO.
10308              Similarly in the other operand order.  This code occurs when
10309              we are computing the size of a variable-size array.  */
10310
10311           if ((code == ASHIFTRT || code == LSHIFTRT)
10312               && count < HOST_BITS_PER_WIDE_INT
10313               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10314               && (nonzero_bits (XEXP (varop, 1), result_mode)
10315                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10316             {
10317               varop = XEXP (varop, 0);
10318               continue;
10319             }
10320           else if ((code == ASHIFTRT || code == LSHIFTRT)
10321                    && count < HOST_BITS_PER_WIDE_INT
10322                    && HWI_COMPUTABLE_MODE_P (result_mode)
10323                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10324                             >> count)
10325                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10326                             & nonzero_bits (XEXP (varop, 1),
10327                                                  result_mode)))
10328             {
10329               varop = XEXP (varop, 1);
10330               continue;
10331             }
10332
10333           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10334           if (code == ASHIFT
10335               && CONST_INT_P (XEXP (varop, 1))
10336               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10337                                                          XEXP (varop, 1),
10338                                                          GEN_INT (count))) != 0
10339               && CONST_INT_P (new_rtx)
10340               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10341                                   INTVAL (new_rtx), result_mode, &complement_p))
10342             {
10343               varop = XEXP (varop, 0);
10344               continue;
10345             }
10346
10347           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10348              signbit', and attempt to change the PLUS to an XOR and move it to
10349              the outer operation as is done above in the AND/IOR/XOR case
10350              leg for shift(logical). See details in logical handling above
10351              for reasoning in doing so.  */
10352           if (code == LSHIFTRT
10353               && CONST_INT_P (XEXP (varop, 1))
10354               && mode_signbit_p (result_mode, XEXP (varop, 1))
10355               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10356                                                          XEXP (varop, 1),
10357                                                          GEN_INT (count))) != 0
10358               && CONST_INT_P (new_rtx)
10359               && merge_outer_ops (&outer_op, &outer_const, XOR,
10360                                   INTVAL (new_rtx), result_mode, &complement_p))
10361             {
10362               varop = XEXP (varop, 0);
10363               continue;
10364             }
10365
10366           break;
10367
10368         case MINUS:
10369           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10370              with C the size of VAROP - 1 and the shift is logical if
10371              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10372              we have a (gt X 0) operation.  If the shift is arithmetic with
10373              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10374              we have a (neg (gt X 0)) operation.  */
10375
10376           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10377               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10378               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10379               && (code == LSHIFTRT || code == ASHIFTRT)
10380               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10381               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10382               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10383             {
10384               count = 0;
10385               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10386                                   const0_rtx);
10387
10388               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10389                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10390
10391               continue;
10392             }
10393           break;
10394
10395         case TRUNCATE:
10396           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10397              if the truncate does not affect the value.  */
10398           if (code == LSHIFTRT
10399               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10400               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10401               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10402                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10403                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10404             {
10405               rtx varop_inner = XEXP (varop, 0);
10406
10407               varop_inner
10408                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10409                                     XEXP (varop_inner, 0),
10410                                     GEN_INT
10411                                     (count + INTVAL (XEXP (varop_inner, 1))));
10412               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10413               count = 0;
10414               continue;
10415             }
10416           break;
10417
10418         default:
10419           break;
10420         }
10421
10422       break;
10423     }
10424
10425   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10426                                      outer_op, outer_const);
10427
10428   /* We have now finished analyzing the shift.  The result should be
10429      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10430      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10431      to the result of the shift.  OUTER_CONST is the relevant constant,
10432      but we must turn off all bits turned off in the shift.  */
10433
10434   if (outer_op == UNKNOWN
10435       && orig_code == code && orig_count == count
10436       && varop == orig_varop
10437       && shift_mode == GET_MODE (varop))
10438     return NULL_RTX;
10439
10440   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10441   varop = gen_lowpart (shift_mode, varop);
10442   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10443     return NULL_RTX;
10444
10445   /* If we have an outer operation and we just made a shift, it is
10446      possible that we could have simplified the shift were it not
10447      for the outer operation.  So try to do the simplification
10448      recursively.  */
10449
10450   if (outer_op != UNKNOWN)
10451     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10452   else
10453     x = NULL_RTX;
10454
10455   if (x == NULL_RTX)
10456     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10457
10458   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10459      turn off all the bits that the shift would have turned off.  */
10460   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10461     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10462                                 GET_MODE_MASK (result_mode) >> orig_count);
10463
10464   /* Do the remainder of the processing in RESULT_MODE.  */
10465   x = gen_lowpart_or_truncate (result_mode, x);
10466
10467   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10468      operation.  */
10469   if (complement_p)
10470     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10471
10472   if (outer_op != UNKNOWN)
10473     {
10474       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10475           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10476         outer_const = trunc_int_for_mode (outer_const, result_mode);
10477
10478       if (outer_op == AND)
10479         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10480       else if (outer_op == SET)
10481         {
10482           /* This means that we have determined that the result is
10483              equivalent to a constant.  This should be rare.  */
10484           if (!side_effects_p (x))
10485             x = GEN_INT (outer_const);
10486         }
10487       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10488         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10489       else
10490         x = simplify_gen_binary (outer_op, result_mode, x,
10491                                  GEN_INT (outer_const));
10492     }
10493
10494   return x;
10495 }
10496
10497 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10498    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10499    return X or, if it is NULL, synthesize the expression with
10500    simplify_gen_binary.  Otherwise, return a simplified value.
10501
10502    The shift is normally computed in the widest mode we find in VAROP, as
10503    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10504    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10505
10506 static rtx
10507 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10508                       rtx varop, int count)
10509 {
10510   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10511   if (tem)
10512     return tem;
10513
10514   if (!x)
10515     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10516   if (GET_MODE (x) != result_mode)
10517     x = gen_lowpart (result_mode, x);
10518   return x;
10519 }
10520
10521 \f
10522 /* Like recog, but we receive the address of a pointer to a new pattern.
10523    We try to match the rtx that the pointer points to.
10524    If that fails, we may try to modify or replace the pattern,
10525    storing the replacement into the same pointer object.
10526
10527    Modifications include deletion or addition of CLOBBERs.
10528
10529    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10530    the CLOBBERs are placed.
10531
10532    The value is the final insn code from the pattern ultimately matched,
10533    or -1.  */
10534
10535 static int
10536 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10537 {
10538   rtx pat = *pnewpat;
10539   rtx pat_without_clobbers;
10540   int insn_code_number;
10541   int num_clobbers_to_add = 0;
10542   int i;
10543   rtx notes = NULL_RTX;
10544   rtx old_notes, old_pat;
10545   int old_icode;
10546
10547   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10548      we use to indicate that something didn't match.  If we find such a
10549      thing, force rejection.  */
10550   if (GET_CODE (pat) == PARALLEL)
10551     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10552       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10553           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10554         return -1;
10555
10556   old_pat = PATTERN (insn);
10557   old_notes = REG_NOTES (insn);
10558   PATTERN (insn) = pat;
10559   REG_NOTES (insn) = NULL_RTX;
10560
10561   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10562   if (dump_file && (dump_flags & TDF_DETAILS))
10563     {
10564       if (insn_code_number < 0)
10565         fputs ("Failed to match this instruction:\n", dump_file);
10566       else
10567         fputs ("Successfully matched this instruction:\n", dump_file);
10568       print_rtl_single (dump_file, pat);
10569     }
10570
10571   /* If it isn't, there is the possibility that we previously had an insn
10572      that clobbered some register as a side effect, but the combined
10573      insn doesn't need to do that.  So try once more without the clobbers
10574      unless this represents an ASM insn.  */
10575
10576   if (insn_code_number < 0 && ! check_asm_operands (pat)
10577       && GET_CODE (pat) == PARALLEL)
10578     {
10579       int pos;
10580
10581       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10582         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10583           {
10584             if (i != pos)
10585               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10586             pos++;
10587           }
10588
10589       SUBST_INT (XVECLEN (pat, 0), pos);
10590
10591       if (pos == 1)
10592         pat = XVECEXP (pat, 0, 0);
10593
10594       PATTERN (insn) = pat;
10595       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10596       if (dump_file && (dump_flags & TDF_DETAILS))
10597         {
10598           if (insn_code_number < 0)
10599             fputs ("Failed to match this instruction:\n", dump_file);
10600           else
10601             fputs ("Successfully matched this instruction:\n", dump_file);
10602           print_rtl_single (dump_file, pat);
10603         }
10604     }
10605
10606   pat_without_clobbers = pat;
10607
10608   PATTERN (insn) = old_pat;
10609   REG_NOTES (insn) = old_notes;
10610
10611   /* Recognize all noop sets, these will be killed by followup pass.  */
10612   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10613     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10614
10615   /* If we had any clobbers to add, make a new pattern than contains
10616      them.  Then check to make sure that all of them are dead.  */
10617   if (num_clobbers_to_add)
10618     {
10619       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10620                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10621                                                   ? (XVECLEN (pat, 0)
10622                                                      + num_clobbers_to_add)
10623                                                   : num_clobbers_to_add + 1));
10624
10625       if (GET_CODE (pat) == PARALLEL)
10626         for (i = 0; i < XVECLEN (pat, 0); i++)
10627           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10628       else
10629         XVECEXP (newpat, 0, 0) = pat;
10630
10631       add_clobbers (newpat, insn_code_number);
10632
10633       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10634            i < XVECLEN (newpat, 0); i++)
10635         {
10636           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10637               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10638             return -1;
10639           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10640             {
10641               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10642               notes = alloc_reg_note (REG_UNUSED,
10643                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10644             }
10645         }
10646       pat = newpat;
10647     }
10648
10649   if (insn_code_number >= 0
10650       && insn_code_number != NOOP_MOVE_INSN_CODE)
10651     {
10652       old_pat = PATTERN (insn);
10653       old_notes = REG_NOTES (insn);
10654       old_icode = INSN_CODE (insn);
10655       PATTERN (insn) = pat;
10656       REG_NOTES (insn) = notes;
10657
10658       /* Allow targets to reject combined insn.  */
10659       if (!targetm.legitimate_combined_insn (insn))
10660         {
10661           if (dump_file && (dump_flags & TDF_DETAILS))
10662             fputs ("Instruction not appropriate for target.",
10663                    dump_file);
10664
10665           /* Callers expect recog_for_combine to strip
10666              clobbers from the pattern on failure.  */
10667           pat = pat_without_clobbers;
10668           notes = NULL_RTX;
10669
10670           insn_code_number = -1;
10671         }
10672
10673       PATTERN (insn) = old_pat;
10674       REG_NOTES (insn) = old_notes;
10675       INSN_CODE (insn) = old_icode;
10676     }
10677
10678   *pnewpat = pat;
10679   *pnotes = notes;
10680
10681   return insn_code_number;
10682 }
10683 \f
10684 /* Like gen_lowpart_general but for use by combine.  In combine it
10685    is not possible to create any new pseudoregs.  However, it is
10686    safe to create invalid memory addresses, because combine will
10687    try to recognize them and all they will do is make the combine
10688    attempt fail.
10689
10690    If for some reason this cannot do its job, an rtx
10691    (clobber (const_int 0)) is returned.
10692    An insn containing that will not be recognized.  */
10693
10694 static rtx
10695 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10696 {
10697   enum machine_mode imode = GET_MODE (x);
10698   unsigned int osize = GET_MODE_SIZE (omode);
10699   unsigned int isize = GET_MODE_SIZE (imode);
10700   rtx result;
10701
10702   if (omode == imode)
10703     return x;
10704
10705   /* We can only support MODE being wider than a word if X is a
10706      constant integer or has a mode the same size.  */
10707   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10708       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10709     goto fail;
10710
10711   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10712      won't know what to do.  So we will strip off the SUBREG here and
10713      process normally.  */
10714   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10715     {
10716       x = SUBREG_REG (x);
10717
10718       /* For use in case we fall down into the address adjustments
10719          further below, we need to adjust the known mode and size of
10720          x; imode and isize, since we just adjusted x.  */
10721       imode = GET_MODE (x);
10722
10723       if (imode == omode)
10724         return x;
10725
10726       isize = GET_MODE_SIZE (imode);
10727     }
10728
10729   result = gen_lowpart_common (omode, x);
10730
10731   if (result)
10732     return result;
10733
10734   if (MEM_P (x))
10735     {
10736       int offset = 0;
10737
10738       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10739          address.  */
10740       if (MEM_VOLATILE_P (x)
10741           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10742         goto fail;
10743
10744       /* If we want to refer to something bigger than the original memref,
10745          generate a paradoxical subreg instead.  That will force a reload
10746          of the original memref X.  */
10747       if (isize < osize)
10748         return gen_rtx_SUBREG (omode, x, 0);
10749
10750       if (WORDS_BIG_ENDIAN)
10751         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10752
10753       /* Adjust the address so that the address-after-the-data is
10754          unchanged.  */
10755       if (BYTES_BIG_ENDIAN)
10756         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10757
10758       return adjust_address_nv (x, omode, offset);
10759     }
10760
10761   /* If X is a comparison operator, rewrite it in a new mode.  This
10762      probably won't match, but may allow further simplifications.  */
10763   else if (COMPARISON_P (x))
10764     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10765
10766   /* If we couldn't simplify X any other way, just enclose it in a
10767      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10768      include an explicit SUBREG or we may simplify it further in combine.  */
10769   else
10770     {
10771       int offset = 0;
10772       rtx res;
10773
10774       offset = subreg_lowpart_offset (omode, imode);
10775       if (imode == VOIDmode)
10776         {
10777           imode = int_mode_for_mode (omode);
10778           x = gen_lowpart_common (imode, x);
10779           if (x == NULL)
10780             goto fail;
10781         }
10782       res = simplify_gen_subreg (omode, x, imode, offset);
10783       if (res)
10784         return res;
10785     }
10786
10787  fail:
10788   return gen_rtx_CLOBBER (omode, const0_rtx);
10789 }
10790 \f
10791 /* Try to simplify a comparison between OP0 and a constant OP1,
10792    where CODE is the comparison code that will be tested, into a
10793    (CODE OP0 const0_rtx) form.
10794
10795    The result is a possibly different comparison code to use.
10796    *POP1 may be updated.  */
10797
10798 static enum rtx_code
10799 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10800 {
10801   enum machine_mode mode = GET_MODE (op0);
10802   unsigned int mode_width = GET_MODE_PRECISION (mode);
10803   HOST_WIDE_INT const_op = INTVAL (*pop1);
10804
10805   /* Get the constant we are comparing against and turn off all bits
10806      not on in our mode.  */
10807   if (mode != VOIDmode)
10808     const_op = trunc_int_for_mode (const_op, mode);
10809
10810   /* If we are comparing against a constant power of two and the value
10811      being compared can only have that single bit nonzero (e.g., it was
10812      `and'ed with that bit), we can replace this with a comparison
10813      with zero.  */
10814   if (const_op
10815       && (code == EQ || code == NE || code == GE || code == GEU
10816           || code == LT || code == LTU)
10817       && mode_width <= HOST_BITS_PER_WIDE_INT
10818       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10819       && (nonzero_bits (op0, mode)
10820           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10821     {
10822       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10823       const_op = 0;
10824     }
10825
10826   /* Similarly, if we are comparing a value known to be either -1 or
10827      0 with -1, change it to the opposite comparison against zero.  */
10828   if (const_op == -1
10829       && (code == EQ || code == NE || code == GT || code == LE
10830           || code == GEU || code == LTU)
10831       && num_sign_bit_copies (op0, mode) == mode_width)
10832     {
10833       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10834       const_op = 0;
10835     }
10836
10837   /* Do some canonicalizations based on the comparison code.  We prefer
10838      comparisons against zero and then prefer equality comparisons.
10839      If we can reduce the size of a constant, we will do that too.  */
10840   switch (code)
10841     {
10842     case LT:
10843       /* < C is equivalent to <= (C - 1) */
10844       if (const_op > 0)
10845         {
10846           const_op -= 1;
10847           code = LE;
10848           /* ... fall through to LE case below.  */
10849         }
10850       else
10851         break;
10852
10853     case LE:
10854       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10855       if (const_op < 0)
10856         {
10857           const_op += 1;
10858           code = LT;
10859         }
10860
10861       /* If we are doing a <= 0 comparison on a value known to have
10862          a zero sign bit, we can replace this with == 0.  */
10863       else if (const_op == 0
10864                && mode_width <= HOST_BITS_PER_WIDE_INT
10865                && (nonzero_bits (op0, mode)
10866                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10867                == 0)
10868         code = EQ;
10869       break;
10870
10871     case GE:
10872       /* >= C is equivalent to > (C - 1).  */
10873       if (const_op > 0)
10874         {
10875           const_op -= 1;
10876           code = GT;
10877           /* ... fall through to GT below.  */
10878         }
10879       else
10880         break;
10881
10882     case GT:
10883       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10884       if (const_op < 0)
10885         {
10886           const_op += 1;
10887           code = GE;
10888         }
10889
10890       /* If we are doing a > 0 comparison on a value known to have
10891          a zero sign bit, we can replace this with != 0.  */
10892       else if (const_op == 0
10893                && mode_width <= HOST_BITS_PER_WIDE_INT
10894                && (nonzero_bits (op0, mode)
10895                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10896                == 0)
10897         code = NE;
10898       break;
10899
10900     case LTU:
10901       /* < C is equivalent to <= (C - 1).  */
10902       if (const_op > 0)
10903         {
10904           const_op -= 1;
10905           code = LEU;
10906           /* ... fall through ...  */
10907         }
10908       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10909       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10910                && (unsigned HOST_WIDE_INT) const_op
10911                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10912         {
10913           const_op = 0;
10914           code = GE;
10915           break;
10916         }
10917       else
10918         break;
10919
10920     case LEU:
10921       /* unsigned <= 0 is equivalent to == 0 */
10922       if (const_op == 0)
10923         code = EQ;
10924       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10925       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10926                && (unsigned HOST_WIDE_INT) const_op
10927                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10928         {
10929           const_op = 0;
10930           code = GE;
10931         }
10932       break;
10933
10934     case GEU:
10935       /* >= C is equivalent to > (C - 1).  */
10936       if (const_op > 1)
10937         {
10938           const_op -= 1;
10939           code = GTU;
10940           /* ... fall through ...  */
10941         }
10942
10943       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
10944       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10945                && (unsigned HOST_WIDE_INT) const_op
10946                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10947         {
10948           const_op = 0;
10949           code = LT;
10950           break;
10951         }
10952       else
10953         break;
10954
10955     case GTU:
10956       /* unsigned > 0 is equivalent to != 0 */
10957       if (const_op == 0)
10958         code = NE;
10959       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
10960       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10961                && (unsigned HOST_WIDE_INT) const_op
10962                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10963         {
10964           const_op = 0;
10965           code = LT;
10966         }
10967       break;
10968
10969     default:
10970       break;
10971     }
10972
10973   *pop1 = GEN_INT (const_op);
10974   return code;
10975 }
10976 \f
10977 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10978    comparison code that will be tested.
10979
10980    The result is a possibly different comparison code to use.  *POP0 and
10981    *POP1 may be updated.
10982
10983    It is possible that we might detect that a comparison is either always
10984    true or always false.  However, we do not perform general constant
10985    folding in combine, so this knowledge isn't useful.  Such tautologies
10986    should have been detected earlier.  Hence we ignore all such cases.  */
10987
10988 static enum rtx_code
10989 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10990 {
10991   rtx op0 = *pop0;
10992   rtx op1 = *pop1;
10993   rtx tem, tem1;
10994   int i;
10995   enum machine_mode mode, tmode;
10996
10997   /* Try a few ways of applying the same transformation to both operands.  */
10998   while (1)
10999     {
11000 #ifndef WORD_REGISTER_OPERATIONS
11001       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11002          so check specially.  */
11003       if (code != GTU && code != GEU && code != LTU && code != LEU
11004           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11005           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11006           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11007           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11008           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11009           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11010               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11011           && CONST_INT_P (XEXP (op0, 1))
11012           && XEXP (op0, 1) == XEXP (op1, 1)
11013           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11014           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11015           && (INTVAL (XEXP (op0, 1))
11016               == (GET_MODE_PRECISION (GET_MODE (op0))
11017                   - (GET_MODE_PRECISION
11018                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11019         {
11020           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11021           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11022         }
11023 #endif
11024
11025       /* If both operands are the same constant shift, see if we can ignore the
11026          shift.  We can if the shift is a rotate or if the bits shifted out of
11027          this shift are known to be zero for both inputs and if the type of
11028          comparison is compatible with the shift.  */
11029       if (GET_CODE (op0) == GET_CODE (op1)
11030           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11031           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11032               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11033                   && (code != GT && code != LT && code != GE && code != LE))
11034               || (GET_CODE (op0) == ASHIFTRT
11035                   && (code != GTU && code != LTU
11036                       && code != GEU && code != LEU)))
11037           && CONST_INT_P (XEXP (op0, 1))
11038           && INTVAL (XEXP (op0, 1)) >= 0
11039           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11040           && XEXP (op0, 1) == XEXP (op1, 1))
11041         {
11042           enum machine_mode mode = GET_MODE (op0);
11043           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11044           int shift_count = INTVAL (XEXP (op0, 1));
11045
11046           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11047             mask &= (mask >> shift_count) << shift_count;
11048           else if (GET_CODE (op0) == ASHIFT)
11049             mask = (mask & (mask << shift_count)) >> shift_count;
11050
11051           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11052               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11053             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11054           else
11055             break;
11056         }
11057
11058       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11059          SUBREGs are of the same mode, and, in both cases, the AND would
11060          be redundant if the comparison was done in the narrower mode,
11061          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11062          and the operand's possibly nonzero bits are 0xffffff01; in that case
11063          if we only care about QImode, we don't need the AND).  This case
11064          occurs if the output mode of an scc insn is not SImode and
11065          STORE_FLAG_VALUE == 1 (e.g., the 386).
11066
11067          Similarly, check for a case where the AND's are ZERO_EXTEND
11068          operations from some narrower mode even though a SUBREG is not
11069          present.  */
11070
11071       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11072                && CONST_INT_P (XEXP (op0, 1))
11073                && CONST_INT_P (XEXP (op1, 1)))
11074         {
11075           rtx inner_op0 = XEXP (op0, 0);
11076           rtx inner_op1 = XEXP (op1, 0);
11077           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11078           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11079           int changed = 0;
11080
11081           if (paradoxical_subreg_p (inner_op0)
11082               && GET_CODE (inner_op1) == SUBREG
11083               && (GET_MODE (SUBREG_REG (inner_op0))
11084                   == GET_MODE (SUBREG_REG (inner_op1)))
11085               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11086                   <= HOST_BITS_PER_WIDE_INT)
11087               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11088                                              GET_MODE (SUBREG_REG (inner_op0)))))
11089               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11090                                              GET_MODE (SUBREG_REG (inner_op1))))))
11091             {
11092               op0 = SUBREG_REG (inner_op0);
11093               op1 = SUBREG_REG (inner_op1);
11094
11095               /* The resulting comparison is always unsigned since we masked
11096                  off the original sign bit.  */
11097               code = unsigned_condition (code);
11098
11099               changed = 1;
11100             }
11101
11102           else if (c0 == c1)
11103             for (tmode = GET_CLASS_NARROWEST_MODE
11104                  (GET_MODE_CLASS (GET_MODE (op0)));
11105                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11106               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11107                 {
11108                   op0 = gen_lowpart (tmode, inner_op0);
11109                   op1 = gen_lowpart (tmode, inner_op1);
11110                   code = unsigned_condition (code);
11111                   changed = 1;
11112                   break;
11113                 }
11114
11115           if (! changed)
11116             break;
11117         }
11118
11119       /* If both operands are NOT, we can strip off the outer operation
11120          and adjust the comparison code for swapped operands; similarly for
11121          NEG, except that this must be an equality comparison.  */
11122       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11123                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11124                    && (code == EQ || code == NE)))
11125         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11126
11127       else
11128         break;
11129     }
11130
11131   /* If the first operand is a constant, swap the operands and adjust the
11132      comparison code appropriately, but don't do this if the second operand
11133      is already a constant integer.  */
11134   if (swap_commutative_operands_p (op0, op1))
11135     {
11136       tem = op0, op0 = op1, op1 = tem;
11137       code = swap_condition (code);
11138     }
11139
11140   /* We now enter a loop during which we will try to simplify the comparison.
11141      For the most part, we only are concerned with comparisons with zero,
11142      but some things may really be comparisons with zero but not start
11143      out looking that way.  */
11144
11145   while (CONST_INT_P (op1))
11146     {
11147       enum machine_mode mode = GET_MODE (op0);
11148       unsigned int mode_width = GET_MODE_PRECISION (mode);
11149       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11150       int equality_comparison_p;
11151       int sign_bit_comparison_p;
11152       int unsigned_comparison_p;
11153       HOST_WIDE_INT const_op;
11154
11155       /* We only want to handle integral modes.  This catches VOIDmode,
11156          CCmode, and the floating-point modes.  An exception is that we
11157          can handle VOIDmode if OP0 is a COMPARE or a comparison
11158          operation.  */
11159
11160       if (GET_MODE_CLASS (mode) != MODE_INT
11161           && ! (mode == VOIDmode
11162                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11163         break;
11164
11165       /* Try to simplify the compare to constant, possibly changing the
11166          comparison op, and/or changing op1 to zero.  */
11167       code = simplify_compare_const (code, op0, &op1);
11168       const_op = INTVAL (op1);
11169
11170       /* Compute some predicates to simplify code below.  */
11171
11172       equality_comparison_p = (code == EQ || code == NE);
11173       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11174       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11175                                || code == GEU);
11176
11177       /* If this is a sign bit comparison and we can do arithmetic in
11178          MODE, say that we will only be needing the sign bit of OP0.  */
11179       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11180         op0 = force_to_mode (op0, mode,
11181                              (unsigned HOST_WIDE_INT) 1
11182                              << (GET_MODE_PRECISION (mode) - 1),
11183                              0);
11184
11185       /* Now try cases based on the opcode of OP0.  If none of the cases
11186          does a "continue", we exit this loop immediately after the
11187          switch.  */
11188
11189       switch (GET_CODE (op0))
11190         {
11191         case ZERO_EXTRACT:
11192           /* If we are extracting a single bit from a variable position in
11193              a constant that has only a single bit set and are comparing it
11194              with zero, we can convert this into an equality comparison
11195              between the position and the location of the single bit.  */
11196           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11197              have already reduced the shift count modulo the word size.  */
11198           if (!SHIFT_COUNT_TRUNCATED
11199               && CONST_INT_P (XEXP (op0, 0))
11200               && XEXP (op0, 1) == const1_rtx
11201               && equality_comparison_p && const_op == 0
11202               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11203             {
11204               if (BITS_BIG_ENDIAN)
11205                 i = BITS_PER_WORD - 1 - i;
11206
11207               op0 = XEXP (op0, 2);
11208               op1 = GEN_INT (i);
11209               const_op = i;
11210
11211               /* Result is nonzero iff shift count is equal to I.  */
11212               code = reverse_condition (code);
11213               continue;
11214             }
11215
11216           /* ... fall through ...  */
11217
11218         case SIGN_EXTRACT:
11219           tem = expand_compound_operation (op0);
11220           if (tem != op0)
11221             {
11222               op0 = tem;
11223               continue;
11224             }
11225           break;
11226
11227         case NOT:
11228           /* If testing for equality, we can take the NOT of the constant.  */
11229           if (equality_comparison_p
11230               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11231             {
11232               op0 = XEXP (op0, 0);
11233               op1 = tem;
11234               continue;
11235             }
11236
11237           /* If just looking at the sign bit, reverse the sense of the
11238              comparison.  */
11239           if (sign_bit_comparison_p)
11240             {
11241               op0 = XEXP (op0, 0);
11242               code = (code == GE ? LT : GE);
11243               continue;
11244             }
11245           break;
11246
11247         case NEG:
11248           /* If testing for equality, we can take the NEG of the constant.  */
11249           if (equality_comparison_p
11250               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11251             {
11252               op0 = XEXP (op0, 0);
11253               op1 = tem;
11254               continue;
11255             }
11256
11257           /* The remaining cases only apply to comparisons with zero.  */
11258           if (const_op != 0)
11259             break;
11260
11261           /* When X is ABS or is known positive,
11262              (neg X) is < 0 if and only if X != 0.  */
11263
11264           if (sign_bit_comparison_p
11265               && (GET_CODE (XEXP (op0, 0)) == ABS
11266                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11267                       && (nonzero_bits (XEXP (op0, 0), mode)
11268                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11269                          == 0)))
11270             {
11271               op0 = XEXP (op0, 0);
11272               code = (code == LT ? NE : EQ);
11273               continue;
11274             }
11275
11276           /* If we have NEG of something whose two high-order bits are the
11277              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11278           if (num_sign_bit_copies (op0, mode) >= 2)
11279             {
11280               op0 = XEXP (op0, 0);
11281               code = swap_condition (code);
11282               continue;
11283             }
11284           break;
11285
11286         case ROTATE:
11287           /* If we are testing equality and our count is a constant, we
11288              can perform the inverse operation on our RHS.  */
11289           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11290               && (tem = simplify_binary_operation (ROTATERT, mode,
11291                                                    op1, XEXP (op0, 1))) != 0)
11292             {
11293               op0 = XEXP (op0, 0);
11294               op1 = tem;
11295               continue;
11296             }
11297
11298           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11299              a particular bit.  Convert it to an AND of a constant of that
11300              bit.  This will be converted into a ZERO_EXTRACT.  */
11301           if (const_op == 0 && sign_bit_comparison_p
11302               && CONST_INT_P (XEXP (op0, 1))
11303               && mode_width <= HOST_BITS_PER_WIDE_INT)
11304             {
11305               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11306                                             ((unsigned HOST_WIDE_INT) 1
11307                                              << (mode_width - 1
11308                                                  - INTVAL (XEXP (op0, 1)))));
11309               code = (code == LT ? NE : EQ);
11310               continue;
11311             }
11312
11313           /* Fall through.  */
11314
11315         case ABS:
11316           /* ABS is ignorable inside an equality comparison with zero.  */
11317           if (const_op == 0 && equality_comparison_p)
11318             {
11319               op0 = XEXP (op0, 0);
11320               continue;
11321             }
11322           break;
11323
11324         case SIGN_EXTEND:
11325           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11326              (compare FOO CONST) if CONST fits in FOO's mode and we
11327              are either testing inequality or have an unsigned
11328              comparison with ZERO_EXTEND or a signed comparison with
11329              SIGN_EXTEND.  But don't do it if we don't have a compare
11330              insn of the given mode, since we'd have to revert it
11331              later on, and then we wouldn't know whether to sign- or
11332              zero-extend.  */
11333           mode = GET_MODE (XEXP (op0, 0));
11334           if (GET_MODE_CLASS (mode) == MODE_INT
11335               && ! unsigned_comparison_p
11336               && HWI_COMPUTABLE_MODE_P (mode)
11337               && trunc_int_for_mode (const_op, mode) == const_op
11338               && have_insn_for (COMPARE, mode))
11339             {
11340               op0 = XEXP (op0, 0);
11341               continue;
11342             }
11343           break;
11344
11345         case SUBREG:
11346           /* Check for the case where we are comparing A - C1 with C2, that is
11347
11348                (subreg:MODE (plus (A) (-C1))) op (C2)
11349
11350              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11351              comparison in the wider mode.  One of the following two conditions
11352              must be true in order for this to be valid:
11353
11354                1. The mode extension results in the same bit pattern being added
11355                   on both sides and the comparison is equality or unsigned.  As
11356                   C2 has been truncated to fit in MODE, the pattern can only be
11357                   all 0s or all 1s.
11358
11359                2. The mode extension results in the sign bit being copied on
11360                   each side.
11361
11362              The difficulty here is that we have predicates for A but not for
11363              (A - C1) so we need to check that C1 is within proper bounds so
11364              as to perturbate A as little as possible.  */
11365
11366           if (mode_width <= HOST_BITS_PER_WIDE_INT
11367               && subreg_lowpart_p (op0)
11368               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11369               && GET_CODE (SUBREG_REG (op0)) == PLUS
11370               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11371             {
11372               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11373               rtx a = XEXP (SUBREG_REG (op0), 0);
11374               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11375
11376               if ((c1 > 0
11377                    && (unsigned HOST_WIDE_INT) c1
11378                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11379                    && (equality_comparison_p || unsigned_comparison_p)
11380                    /* (A - C1) zero-extends if it is positive and sign-extends
11381                       if it is negative, C2 both zero- and sign-extends.  */
11382                    && ((0 == (nonzero_bits (a, inner_mode)
11383                               & ~GET_MODE_MASK (mode))
11384                         && const_op >= 0)
11385                        /* (A - C1) sign-extends if it is positive and 1-extends
11386                           if it is negative, C2 both sign- and 1-extends.  */
11387                        || (num_sign_bit_copies (a, inner_mode)
11388                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11389                                              - mode_width)
11390                            && const_op < 0)))
11391                   || ((unsigned HOST_WIDE_INT) c1
11392                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11393                       /* (A - C1) always sign-extends, like C2.  */
11394                       && num_sign_bit_copies (a, inner_mode)
11395                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11396                                            - (mode_width - 1))))
11397                 {
11398                   op0 = SUBREG_REG (op0);
11399                   continue;
11400                 }
11401             }
11402
11403           /* If the inner mode is narrower and we are extracting the low part,
11404              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11405           if (subreg_lowpart_p (op0)
11406               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11407             /* Fall through */ ;
11408           else
11409             break;
11410
11411           /* ... fall through ...  */
11412
11413         case ZERO_EXTEND:
11414           mode = GET_MODE (XEXP (op0, 0));
11415           if (GET_MODE_CLASS (mode) == MODE_INT
11416               && (unsigned_comparison_p || equality_comparison_p)
11417               && HWI_COMPUTABLE_MODE_P (mode)
11418               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11419               && const_op >= 0
11420               && have_insn_for (COMPARE, mode))
11421             {
11422               op0 = XEXP (op0, 0);
11423               continue;
11424             }
11425           break;
11426
11427         case PLUS:
11428           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11429              this for equality comparisons due to pathological cases involving
11430              overflows.  */
11431           if (equality_comparison_p
11432               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11433                                                         op1, XEXP (op0, 1))))
11434             {
11435               op0 = XEXP (op0, 0);
11436               op1 = tem;
11437               continue;
11438             }
11439
11440           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11441           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11442               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11443             {
11444               op0 = XEXP (XEXP (op0, 0), 0);
11445               code = (code == LT ? EQ : NE);
11446               continue;
11447             }
11448           break;
11449
11450         case MINUS:
11451           /* We used to optimize signed comparisons against zero, but that
11452              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11453              arrive here as equality comparisons, or (GEU, LTU) are
11454              optimized away.  No need to special-case them.  */
11455
11456           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11457              (eq B (minus A C)), whichever simplifies.  We can only do
11458              this for equality comparisons due to pathological cases involving
11459              overflows.  */
11460           if (equality_comparison_p
11461               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11462                                                         XEXP (op0, 1), op1)))
11463             {
11464               op0 = XEXP (op0, 0);
11465               op1 = tem;
11466               continue;
11467             }
11468
11469           if (equality_comparison_p
11470               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11471                                                         XEXP (op0, 0), op1)))
11472             {
11473               op0 = XEXP (op0, 1);
11474               op1 = tem;
11475               continue;
11476             }
11477
11478           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11479              of bits in X minus 1, is one iff X > 0.  */
11480           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11481               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11482               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11483               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11484             {
11485               op0 = XEXP (op0, 1);
11486               code = (code == GE ? LE : GT);
11487               continue;
11488             }
11489           break;
11490
11491         case XOR:
11492           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11493              if C is zero or B is a constant.  */
11494           if (equality_comparison_p
11495               && 0 != (tem = simplify_binary_operation (XOR, mode,
11496                                                         XEXP (op0, 1), op1)))
11497             {
11498               op0 = XEXP (op0, 0);
11499               op1 = tem;
11500               continue;
11501             }
11502           break;
11503
11504         case EQ:  case NE:
11505         case UNEQ:  case LTGT:
11506         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11507         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11508         case UNORDERED: case ORDERED:
11509           /* We can't do anything if OP0 is a condition code value, rather
11510              than an actual data value.  */
11511           if (const_op != 0
11512               || CC0_P (XEXP (op0, 0))
11513               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11514             break;
11515
11516           /* Get the two operands being compared.  */
11517           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11518             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11519           else
11520             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11521
11522           /* Check for the cases where we simply want the result of the
11523              earlier test or the opposite of that result.  */
11524           if (code == NE || code == EQ
11525               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11526                   && (code == LT || code == GE)))
11527             {
11528               enum rtx_code new_code;
11529               if (code == LT || code == NE)
11530                 new_code = GET_CODE (op0);
11531               else
11532                 new_code = reversed_comparison_code (op0, NULL);
11533
11534               if (new_code != UNKNOWN)
11535                 {
11536                   code = new_code;
11537                   op0 = tem;
11538                   op1 = tem1;
11539                   continue;
11540                 }
11541             }
11542           break;
11543
11544         case IOR:
11545           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11546              iff X <= 0.  */
11547           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11548               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11549               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11550             {
11551               op0 = XEXP (op0, 1);
11552               code = (code == GE ? GT : LE);
11553               continue;
11554             }
11555           break;
11556
11557         case AND:
11558           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11559              will be converted to a ZERO_EXTRACT later.  */
11560           if (const_op == 0 && equality_comparison_p
11561               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11562               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11563             {
11564               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11565                                       XEXP (XEXP (op0, 0), 1));
11566               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11567               continue;
11568             }
11569
11570           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11571              zero and X is a comparison and C1 and C2 describe only bits set
11572              in STORE_FLAG_VALUE, we can compare with X.  */
11573           if (const_op == 0 && equality_comparison_p
11574               && mode_width <= HOST_BITS_PER_WIDE_INT
11575               && CONST_INT_P (XEXP (op0, 1))
11576               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11577               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11578               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11579               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11580             {
11581               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11582                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11583               if ((~STORE_FLAG_VALUE & mask) == 0
11584                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11585                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11586                           && COMPARISON_P (tem))))
11587                 {
11588                   op0 = XEXP (XEXP (op0, 0), 0);
11589                   continue;
11590                 }
11591             }
11592
11593           /* If we are doing an equality comparison of an AND of a bit equal
11594              to the sign bit, replace this with a LT or GE comparison of
11595              the underlying value.  */
11596           if (equality_comparison_p
11597               && const_op == 0
11598               && CONST_INT_P (XEXP (op0, 1))
11599               && mode_width <= HOST_BITS_PER_WIDE_INT
11600               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11601                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11602             {
11603               op0 = XEXP (op0, 0);
11604               code = (code == EQ ? GE : LT);
11605               continue;
11606             }
11607
11608           /* If this AND operation is really a ZERO_EXTEND from a narrower
11609              mode, the constant fits within that mode, and this is either an
11610              equality or unsigned comparison, try to do this comparison in
11611              the narrower mode.
11612
11613              Note that in:
11614
11615              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11616              -> (ne:DI (reg:SI 4) (const_int 0))
11617
11618              unless TRULY_NOOP_TRUNCATION allows it or the register is
11619              known to hold a value of the required mode the
11620              transformation is invalid.  */
11621           if ((equality_comparison_p || unsigned_comparison_p)
11622               && CONST_INT_P (XEXP (op0, 1))
11623               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11624                                    & GET_MODE_MASK (mode))
11625                                   + 1)) >= 0
11626               && const_op >> i == 0
11627               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11628               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11629                   || (REG_P (XEXP (op0, 0))
11630                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11631             {
11632               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11633               continue;
11634             }
11635
11636           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11637              fits in both M1 and M2 and the SUBREG is either paradoxical
11638              or represents the low part, permute the SUBREG and the AND
11639              and try again.  */
11640           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11641             {
11642               unsigned HOST_WIDE_INT c1;
11643               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11644               /* Require an integral mode, to avoid creating something like
11645                  (AND:SF ...).  */
11646               if (SCALAR_INT_MODE_P (tmode)
11647                   /* It is unsafe to commute the AND into the SUBREG if the
11648                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11649                      not defined.  As originally written the upper bits
11650                      have a defined value due to the AND operation.
11651                      However, if we commute the AND inside the SUBREG then
11652                      they no longer have defined values and the meaning of
11653                      the code has been changed.  */
11654                   && (0
11655 #ifdef WORD_REGISTER_OPERATIONS
11656                       || (mode_width > GET_MODE_PRECISION (tmode)
11657                           && mode_width <= BITS_PER_WORD)
11658 #endif
11659                       || (mode_width <= GET_MODE_PRECISION (tmode)
11660                           && subreg_lowpart_p (XEXP (op0, 0))))
11661                   && CONST_INT_P (XEXP (op0, 1))
11662                   && mode_width <= HOST_BITS_PER_WIDE_INT
11663                   && HWI_COMPUTABLE_MODE_P (tmode)
11664                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11665                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11666                   && c1 != mask
11667                   && c1 != GET_MODE_MASK (tmode))
11668                 {
11669                   op0 = simplify_gen_binary (AND, tmode,
11670                                              SUBREG_REG (XEXP (op0, 0)),
11671                                              gen_int_mode (c1, tmode));
11672                   op0 = gen_lowpart (mode, op0);
11673                   continue;
11674                 }
11675             }
11676
11677           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11678           if (const_op == 0 && equality_comparison_p
11679               && XEXP (op0, 1) == const1_rtx
11680               && GET_CODE (XEXP (op0, 0)) == NOT)
11681             {
11682               op0 = simplify_and_const_int (NULL_RTX, mode,
11683                                             XEXP (XEXP (op0, 0), 0), 1);
11684               code = (code == NE ? EQ : NE);
11685               continue;
11686             }
11687
11688           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11689              (eq (and (lshiftrt X) 1) 0).
11690              Also handle the case where (not X) is expressed using xor.  */
11691           if (const_op == 0 && equality_comparison_p
11692               && XEXP (op0, 1) == const1_rtx
11693               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11694             {
11695               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11696               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11697
11698               if (GET_CODE (shift_op) == NOT
11699                   || (GET_CODE (shift_op) == XOR
11700                       && CONST_INT_P (XEXP (shift_op, 1))
11701                       && CONST_INT_P (shift_count)
11702                       && HWI_COMPUTABLE_MODE_P (mode)
11703                       && (UINTVAL (XEXP (shift_op, 1))
11704                           == (unsigned HOST_WIDE_INT) 1
11705                                << INTVAL (shift_count))))
11706                 {
11707                   op0
11708                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11709                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11710                   code = (code == NE ? EQ : NE);
11711                   continue;
11712                 }
11713             }
11714           break;
11715
11716         case ASHIFT:
11717           /* If we have (compare (ashift FOO N) (const_int C)) and
11718              the high order N bits of FOO (N+1 if an inequality comparison)
11719              are known to be zero, we can do this by comparing FOO with C
11720              shifted right N bits so long as the low-order N bits of C are
11721              zero.  */
11722           if (CONST_INT_P (XEXP (op0, 1))
11723               && INTVAL (XEXP (op0, 1)) >= 0
11724               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11725                   < HOST_BITS_PER_WIDE_INT)
11726               && (((unsigned HOST_WIDE_INT) const_op
11727                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11728                       - 1)) == 0)
11729               && mode_width <= HOST_BITS_PER_WIDE_INT
11730               && (nonzero_bits (XEXP (op0, 0), mode)
11731                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11732                                + ! equality_comparison_p))) == 0)
11733             {
11734               /* We must perform a logical shift, not an arithmetic one,
11735                  as we want the top N bits of C to be zero.  */
11736               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11737
11738               temp >>= INTVAL (XEXP (op0, 1));
11739               op1 = gen_int_mode (temp, mode);
11740               op0 = XEXP (op0, 0);
11741               continue;
11742             }
11743
11744           /* If we are doing a sign bit comparison, it means we are testing
11745              a particular bit.  Convert it to the appropriate AND.  */
11746           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11747               && mode_width <= HOST_BITS_PER_WIDE_INT)
11748             {
11749               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11750                                             ((unsigned HOST_WIDE_INT) 1
11751                                              << (mode_width - 1
11752                                                  - INTVAL (XEXP (op0, 1)))));
11753               code = (code == LT ? NE : EQ);
11754               continue;
11755             }
11756
11757           /* If this an equality comparison with zero and we are shifting
11758              the low bit to the sign bit, we can convert this to an AND of the
11759              low-order bit.  */
11760           if (const_op == 0 && equality_comparison_p
11761               && CONST_INT_P (XEXP (op0, 1))
11762               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11763             {
11764               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11765               continue;
11766             }
11767           break;
11768
11769         case ASHIFTRT:
11770           /* If this is an equality comparison with zero, we can do this
11771              as a logical shift, which might be much simpler.  */
11772           if (equality_comparison_p && const_op == 0
11773               && CONST_INT_P (XEXP (op0, 1)))
11774             {
11775               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11776                                           XEXP (op0, 0),
11777                                           INTVAL (XEXP (op0, 1)));
11778               continue;
11779             }
11780
11781           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11782              do the comparison in a narrower mode.  */
11783           if (! unsigned_comparison_p
11784               && CONST_INT_P (XEXP (op0, 1))
11785               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11786               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11787               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11788                                          MODE_INT, 1)) != BLKmode
11789               && (((unsigned HOST_WIDE_INT) const_op
11790                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11791                   <= GET_MODE_MASK (tmode)))
11792             {
11793               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11794               continue;
11795             }
11796
11797           /* Likewise if OP0 is a PLUS of a sign extension with a
11798              constant, which is usually represented with the PLUS
11799              between the shifts.  */
11800           if (! unsigned_comparison_p
11801               && CONST_INT_P (XEXP (op0, 1))
11802               && GET_CODE (XEXP (op0, 0)) == PLUS
11803               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11804               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11805               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11806               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11807                                          MODE_INT, 1)) != BLKmode
11808               && (((unsigned HOST_WIDE_INT) const_op
11809                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11810                   <= GET_MODE_MASK (tmode)))
11811             {
11812               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11813               rtx add_const = XEXP (XEXP (op0, 0), 1);
11814               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11815                                                    add_const, XEXP (op0, 1));
11816
11817               op0 = simplify_gen_binary (PLUS, tmode,
11818                                          gen_lowpart (tmode, inner),
11819                                          new_const);
11820               continue;
11821             }
11822
11823           /* ... fall through ...  */
11824         case LSHIFTRT:
11825           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11826              the low order N bits of FOO are known to be zero, we can do this
11827              by comparing FOO with C shifted left N bits so long as no
11828              overflow occurs.  Even if the low order N bits of FOO aren't known
11829              to be zero, if the comparison is >= or < we can use the same
11830              optimization and for > or <= by setting all the low
11831              order N bits in the comparison constant.  */
11832           if (CONST_INT_P (XEXP (op0, 1))
11833               && INTVAL (XEXP (op0, 1)) > 0
11834               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11835               && mode_width <= HOST_BITS_PER_WIDE_INT
11836               && (((unsigned HOST_WIDE_INT) const_op
11837                    + (GET_CODE (op0) != LSHIFTRT
11838                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11839                          + 1)
11840                       : 0))
11841                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11842             {
11843               unsigned HOST_WIDE_INT low_bits
11844                 = (nonzero_bits (XEXP (op0, 0), mode)
11845                    & (((unsigned HOST_WIDE_INT) 1
11846                        << INTVAL (XEXP (op0, 1))) - 1));
11847               if (low_bits == 0 || !equality_comparison_p)
11848                 {
11849                   /* If the shift was logical, then we must make the condition
11850                      unsigned.  */
11851                   if (GET_CODE (op0) == LSHIFTRT)
11852                     code = unsigned_condition (code);
11853
11854                   const_op <<= INTVAL (XEXP (op0, 1));
11855                   if (low_bits != 0
11856                       && (code == GT || code == GTU
11857                           || code == LE || code == LEU))
11858                     const_op
11859                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11860                   op1 = GEN_INT (const_op);
11861                   op0 = XEXP (op0, 0);
11862                   continue;
11863                 }
11864             }
11865
11866           /* If we are using this shift to extract just the sign bit, we
11867              can replace this with an LT or GE comparison.  */
11868           if (const_op == 0
11869               && (equality_comparison_p || sign_bit_comparison_p)
11870               && CONST_INT_P (XEXP (op0, 1))
11871               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11872             {
11873               op0 = XEXP (op0, 0);
11874               code = (code == NE || code == GT ? LT : GE);
11875               continue;
11876             }
11877           break;
11878
11879         default:
11880           break;
11881         }
11882
11883       break;
11884     }
11885
11886   /* Now make any compound operations involved in this comparison.  Then,
11887      check for an outmost SUBREG on OP0 that is not doing anything or is
11888      paradoxical.  The latter transformation must only be performed when
11889      it is known that the "extra" bits will be the same in op0 and op1 or
11890      that they don't matter.  There are three cases to consider:
11891
11892      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11893      care bits and we can assume they have any convenient value.  So
11894      making the transformation is safe.
11895
11896      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11897      In this case the upper bits of op0 are undefined.  We should not make
11898      the simplification in that case as we do not know the contents of
11899      those bits.
11900
11901      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11902      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11903      also be sure that they are the same as the upper bits of op1.
11904
11905      We can never remove a SUBREG for a non-equality comparison because
11906      the sign bit is in a different place in the underlying object.  */
11907
11908   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11909   op1 = make_compound_operation (op1, SET);
11910
11911   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11912       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11913       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11914       && (code == NE || code == EQ))
11915     {
11916       if (paradoxical_subreg_p (op0))
11917         {
11918           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11919              implemented.  */
11920           if (REG_P (SUBREG_REG (op0)))
11921             {
11922               op0 = SUBREG_REG (op0);
11923               op1 = gen_lowpart (GET_MODE (op0), op1);
11924             }
11925         }
11926       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11927                 <= HOST_BITS_PER_WIDE_INT)
11928                && (nonzero_bits (SUBREG_REG (op0),
11929                                  GET_MODE (SUBREG_REG (op0)))
11930                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11931         {
11932           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11933
11934           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11935                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11936             op0 = SUBREG_REG (op0), op1 = tem;
11937         }
11938     }
11939
11940   /* We now do the opposite procedure: Some machines don't have compare
11941      insns in all modes.  If OP0's mode is an integer mode smaller than a
11942      word and we can't do a compare in that mode, see if there is a larger
11943      mode for which we can do the compare.  There are a number of cases in
11944      which we can use the wider mode.  */
11945
11946   mode = GET_MODE (op0);
11947   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11948       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11949       && ! have_insn_for (COMPARE, mode))
11950     for (tmode = GET_MODE_WIDER_MODE (mode);
11951          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
11952          tmode = GET_MODE_WIDER_MODE (tmode))
11953       if (have_insn_for (COMPARE, tmode))
11954         {
11955           int zero_extended;
11956
11957           /* If this is a test for negative, we can make an explicit
11958              test of the sign bit.  Test this first so we can use
11959              a paradoxical subreg to extend OP0.  */
11960
11961           if (op1 == const0_rtx && (code == LT || code == GE)
11962               && HWI_COMPUTABLE_MODE_P (mode))
11963             {
11964               unsigned HOST_WIDE_INT sign
11965                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
11966               op0 = simplify_gen_binary (AND, tmode,
11967                                          gen_lowpart (tmode, op0),
11968                                          gen_int_mode (sign, mode));
11969               code = (code == LT) ? NE : EQ;
11970               break;
11971             }
11972
11973           /* If the only nonzero bits in OP0 and OP1 are those in the
11974              narrower mode and this is an equality or unsigned comparison,
11975              we can use the wider mode.  Similarly for sign-extended
11976              values, in which case it is true for all comparisons.  */
11977           zero_extended = ((code == EQ || code == NE
11978                             || code == GEU || code == GTU
11979                             || code == LEU || code == LTU)
11980                            && (nonzero_bits (op0, tmode)
11981                                & ~GET_MODE_MASK (mode)) == 0
11982                            && ((CONST_INT_P (op1)
11983                                 || (nonzero_bits (op1, tmode)
11984                                     & ~GET_MODE_MASK (mode)) == 0)));
11985
11986           if (zero_extended
11987               || ((num_sign_bit_copies (op0, tmode)
11988                    > (unsigned int) (GET_MODE_PRECISION (tmode)
11989                                      - GET_MODE_PRECISION (mode)))
11990                   && (num_sign_bit_copies (op1, tmode)
11991                       > (unsigned int) (GET_MODE_PRECISION (tmode)
11992                                         - GET_MODE_PRECISION (mode)))))
11993             {
11994               /* If OP0 is an AND and we don't have an AND in MODE either,
11995                  make a new AND in the proper mode.  */
11996               if (GET_CODE (op0) == AND
11997                   && !have_insn_for (AND, mode))
11998                 op0 = simplify_gen_binary (AND, tmode,
11999                                            gen_lowpart (tmode,
12000                                                         XEXP (op0, 0)),
12001                                            gen_lowpart (tmode,
12002                                                         XEXP (op0, 1)));
12003               else
12004                 {
12005                   if (zero_extended)
12006                     {
12007                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12008                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12009                     }
12010                   else
12011                     {
12012                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12013                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12014                     }
12015                   break;
12016                 }
12017             }
12018         }
12019
12020   /* We may have changed the comparison operands.  Re-canonicalize.  */
12021   if (swap_commutative_operands_p (op0, op1))
12022     {
12023       tem = op0, op0 = op1, op1 = tem;
12024       code = swap_condition (code);
12025     }
12026
12027   /* If this machine only supports a subset of valid comparisons, see if we
12028      can convert an unsupported one into a supported one.  */
12029   target_canonicalize_comparison (&code, &op0, &op1, 0);
12030
12031   *pop0 = op0;
12032   *pop1 = op1;
12033
12034   return code;
12035 }
12036 \f
12037 /* Utility function for record_value_for_reg.  Count number of
12038    rtxs in X.  */
12039 static int
12040 count_rtxs (rtx x)
12041 {
12042   enum rtx_code code = GET_CODE (x);
12043   const char *fmt;
12044   int i, j, ret = 1;
12045
12046   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12047       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12048     {
12049       rtx x0 = XEXP (x, 0);
12050       rtx x1 = XEXP (x, 1);
12051
12052       if (x0 == x1)
12053         return 1 + 2 * count_rtxs (x0);
12054
12055       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12056            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12057           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12058         return 2 + 2 * count_rtxs (x0)
12059                + count_rtxs (x == XEXP (x1, 0)
12060                              ? XEXP (x1, 1) : XEXP (x1, 0));
12061
12062       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12063            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12064           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12065         return 2 + 2 * count_rtxs (x1)
12066                + count_rtxs (x == XEXP (x0, 0)
12067                              ? XEXP (x0, 1) : XEXP (x0, 0));
12068     }
12069
12070   fmt = GET_RTX_FORMAT (code);
12071   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12072     if (fmt[i] == 'e')
12073       ret += count_rtxs (XEXP (x, i));
12074     else if (fmt[i] == 'E')
12075       for (j = 0; j < XVECLEN (x, i); j++)
12076         ret += count_rtxs (XVECEXP (x, i, j));
12077
12078   return ret;
12079 }
12080 \f
12081 /* Utility function for following routine.  Called when X is part of a value
12082    being stored into last_set_value.  Sets last_set_table_tick
12083    for each register mentioned.  Similar to mention_regs in cse.c  */
12084
12085 static void
12086 update_table_tick (rtx x)
12087 {
12088   enum rtx_code code = GET_CODE (x);
12089   const char *fmt = GET_RTX_FORMAT (code);
12090   int i, j;
12091
12092   if (code == REG)
12093     {
12094       unsigned int regno = REGNO (x);
12095       unsigned int endregno = END_REGNO (x);
12096       unsigned int r;
12097
12098       for (r = regno; r < endregno; r++)
12099         {
12100           reg_stat_type *rsp = &reg_stat[r];
12101           rsp->last_set_table_tick = label_tick;
12102         }
12103
12104       return;
12105     }
12106
12107   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12108     if (fmt[i] == 'e')
12109       {
12110         /* Check for identical subexpressions.  If x contains
12111            identical subexpression we only have to traverse one of
12112            them.  */
12113         if (i == 0 && ARITHMETIC_P (x))
12114           {
12115             /* Note that at this point x1 has already been
12116                processed.  */
12117             rtx x0 = XEXP (x, 0);
12118             rtx x1 = XEXP (x, 1);
12119
12120             /* If x0 and x1 are identical then there is no need to
12121                process x0.  */
12122             if (x0 == x1)
12123               break;
12124
12125             /* If x0 is identical to a subexpression of x1 then while
12126                processing x1, x0 has already been processed.  Thus we
12127                are done with x.  */
12128             if (ARITHMETIC_P (x1)
12129                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12130               break;
12131
12132             /* If x1 is identical to a subexpression of x0 then we
12133                still have to process the rest of x0.  */
12134             if (ARITHMETIC_P (x0)
12135                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12136               {
12137                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12138                 break;
12139               }
12140           }
12141
12142         update_table_tick (XEXP (x, i));
12143       }
12144     else if (fmt[i] == 'E')
12145       for (j = 0; j < XVECLEN (x, i); j++)
12146         update_table_tick (XVECEXP (x, i, j));
12147 }
12148
12149 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12150    are saying that the register is clobbered and we no longer know its
12151    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12152    only permitted with VALUE also zero and is used to invalidate the
12153    register.  */
12154
12155 static void
12156 record_value_for_reg (rtx reg, rtx insn, rtx value)
12157 {
12158   unsigned int regno = REGNO (reg);
12159   unsigned int endregno = END_REGNO (reg);
12160   unsigned int i;
12161   reg_stat_type *rsp;
12162
12163   /* If VALUE contains REG and we have a previous value for REG, substitute
12164      the previous value.  */
12165   if (value && insn && reg_overlap_mentioned_p (reg, value))
12166     {
12167       rtx tem;
12168
12169       /* Set things up so get_last_value is allowed to see anything set up to
12170          our insn.  */
12171       subst_low_luid = DF_INSN_LUID (insn);
12172       tem = get_last_value (reg);
12173
12174       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12175          it isn't going to be useful and will take a lot of time to process,
12176          so just use the CLOBBER.  */
12177
12178       if (tem)
12179         {
12180           if (ARITHMETIC_P (tem)
12181               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12182               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12183             tem = XEXP (tem, 0);
12184           else if (count_occurrences (value, reg, 1) >= 2)
12185             {
12186               /* If there are two or more occurrences of REG in VALUE,
12187                  prevent the value from growing too much.  */
12188               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12189                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12190             }
12191
12192           value = replace_rtx (copy_rtx (value), reg, tem);
12193         }
12194     }
12195
12196   /* For each register modified, show we don't know its value, that
12197      we don't know about its bitwise content, that its value has been
12198      updated, and that we don't know the location of the death of the
12199      register.  */
12200   for (i = regno; i < endregno; i++)
12201     {
12202       rsp = &reg_stat[i];
12203
12204       if (insn)
12205         rsp->last_set = insn;
12206
12207       rsp->last_set_value = 0;
12208       rsp->last_set_mode = VOIDmode;
12209       rsp->last_set_nonzero_bits = 0;
12210       rsp->last_set_sign_bit_copies = 0;
12211       rsp->last_death = 0;
12212       rsp->truncated_to_mode = VOIDmode;
12213     }
12214
12215   /* Mark registers that are being referenced in this value.  */
12216   if (value)
12217     update_table_tick (value);
12218
12219   /* Now update the status of each register being set.
12220      If someone is using this register in this block, set this register
12221      to invalid since we will get confused between the two lives in this
12222      basic block.  This makes using this register always invalid.  In cse, we
12223      scan the table to invalidate all entries using this register, but this
12224      is too much work for us.  */
12225
12226   for (i = regno; i < endregno; i++)
12227     {
12228       rsp = &reg_stat[i];
12229       rsp->last_set_label = label_tick;
12230       if (!insn
12231           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12232         rsp->last_set_invalid = 1;
12233       else
12234         rsp->last_set_invalid = 0;
12235     }
12236
12237   /* The value being assigned might refer to X (like in "x++;").  In that
12238      case, we must replace it with (clobber (const_int 0)) to prevent
12239      infinite loops.  */
12240   rsp = &reg_stat[regno];
12241   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12242     {
12243       value = copy_rtx (value);
12244       if (!get_last_value_validate (&value, insn, label_tick, 1))
12245         value = 0;
12246     }
12247
12248   /* For the main register being modified, update the value, the mode, the
12249      nonzero bits, and the number of sign bit copies.  */
12250
12251   rsp->last_set_value = value;
12252
12253   if (value)
12254     {
12255       enum machine_mode mode = GET_MODE (reg);
12256       subst_low_luid = DF_INSN_LUID (insn);
12257       rsp->last_set_mode = mode;
12258       if (GET_MODE_CLASS (mode) == MODE_INT
12259           && HWI_COMPUTABLE_MODE_P (mode))
12260         mode = nonzero_bits_mode;
12261       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12262       rsp->last_set_sign_bit_copies
12263         = num_sign_bit_copies (value, GET_MODE (reg));
12264     }
12265 }
12266
12267 /* Called via note_stores from record_dead_and_set_regs to handle one
12268    SET or CLOBBER in an insn.  DATA is the instruction in which the
12269    set is occurring.  */
12270
12271 static void
12272 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12273 {
12274   rtx record_dead_insn = (rtx) data;
12275
12276   if (GET_CODE (dest) == SUBREG)
12277     dest = SUBREG_REG (dest);
12278
12279   if (!record_dead_insn)
12280     {
12281       if (REG_P (dest))
12282         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12283       return;
12284     }
12285
12286   if (REG_P (dest))
12287     {
12288       /* If we are setting the whole register, we know its value.  Otherwise
12289          show that we don't know the value.  We can handle SUBREG in
12290          some cases.  */
12291       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12292         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12293       else if (GET_CODE (setter) == SET
12294                && GET_CODE (SET_DEST (setter)) == SUBREG
12295                && SUBREG_REG (SET_DEST (setter)) == dest
12296                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12297                && subreg_lowpart_p (SET_DEST (setter)))
12298         record_value_for_reg (dest, record_dead_insn,
12299                               gen_lowpart (GET_MODE (dest),
12300                                                        SET_SRC (setter)));
12301       else
12302         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12303     }
12304   else if (MEM_P (dest)
12305            /* Ignore pushes, they clobber nothing.  */
12306            && ! push_operand (dest, GET_MODE (dest)))
12307     mem_last_set = DF_INSN_LUID (record_dead_insn);
12308 }
12309
12310 /* Update the records of when each REG was most recently set or killed
12311    for the things done by INSN.  This is the last thing done in processing
12312    INSN in the combiner loop.
12313
12314    We update reg_stat[], in particular fields last_set, last_set_value,
12315    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12316    last_death, and also the similar information mem_last_set (which insn
12317    most recently modified memory) and last_call_luid (which insn was the
12318    most recent subroutine call).  */
12319
12320 static void
12321 record_dead_and_set_regs (rtx insn)
12322 {
12323   rtx link;
12324   unsigned int i;
12325
12326   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12327     {
12328       if (REG_NOTE_KIND (link) == REG_DEAD
12329           && REG_P (XEXP (link, 0)))
12330         {
12331           unsigned int regno = REGNO (XEXP (link, 0));
12332           unsigned int endregno = END_REGNO (XEXP (link, 0));
12333
12334           for (i = regno; i < endregno; i++)
12335             {
12336               reg_stat_type *rsp;
12337
12338               rsp = &reg_stat[i];
12339               rsp->last_death = insn;
12340             }
12341         }
12342       else if (REG_NOTE_KIND (link) == REG_INC)
12343         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12344     }
12345
12346   if (CALL_P (insn))
12347     {
12348       hard_reg_set_iterator hrsi;
12349       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12350         {
12351           reg_stat_type *rsp;
12352
12353           rsp = &reg_stat[i];
12354           rsp->last_set_invalid = 1;
12355           rsp->last_set = insn;
12356           rsp->last_set_value = 0;
12357           rsp->last_set_mode = VOIDmode;
12358           rsp->last_set_nonzero_bits = 0;
12359           rsp->last_set_sign_bit_copies = 0;
12360           rsp->last_death = 0;
12361           rsp->truncated_to_mode = VOIDmode;
12362         }
12363
12364       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12365
12366       /* We can't combine into a call pattern.  Remember, though, that
12367          the return value register is set at this LUID.  We could
12368          still replace a register with the return value from the
12369          wrong subroutine call!  */
12370       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12371     }
12372   else
12373     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12374 }
12375
12376 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12377    register present in the SUBREG, so for each such SUBREG go back and
12378    adjust nonzero and sign bit information of the registers that are
12379    known to have some zero/sign bits set.
12380
12381    This is needed because when combine blows the SUBREGs away, the
12382    information on zero/sign bits is lost and further combines can be
12383    missed because of that.  */
12384
12385 static void
12386 record_promoted_value (rtx insn, rtx subreg)
12387 {
12388   struct insn_link *links;
12389   rtx set;
12390   unsigned int regno = REGNO (SUBREG_REG (subreg));
12391   enum machine_mode mode = GET_MODE (subreg);
12392
12393   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12394     return;
12395
12396   for (links = LOG_LINKS (insn); links;)
12397     {
12398       reg_stat_type *rsp;
12399
12400       insn = links->insn;
12401       set = single_set (insn);
12402
12403       if (! set || !REG_P (SET_DEST (set))
12404           || REGNO (SET_DEST (set)) != regno
12405           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12406         {
12407           links = links->next;
12408           continue;
12409         }
12410
12411       rsp = &reg_stat[regno];
12412       if (rsp->last_set == insn)
12413         {
12414           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12415             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12416         }
12417
12418       if (REG_P (SET_SRC (set)))
12419         {
12420           regno = REGNO (SET_SRC (set));
12421           links = LOG_LINKS (insn);
12422         }
12423       else
12424         break;
12425     }
12426 }
12427
12428 /* Check if X, a register, is known to contain a value already
12429    truncated to MODE.  In this case we can use a subreg to refer to
12430    the truncated value even though in the generic case we would need
12431    an explicit truncation.  */
12432
12433 static bool
12434 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12435 {
12436   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12437   enum machine_mode truncated = rsp->truncated_to_mode;
12438
12439   if (truncated == 0
12440       || rsp->truncation_label < label_tick_ebb_start)
12441     return false;
12442   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12443     return true;
12444   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12445     return true;
12446   return false;
12447 }
12448
12449 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12450    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12451    might be able to turn a truncate into a subreg using this information.
12452    Return -1 if traversing *P is complete or 0 otherwise.  */
12453
12454 static int
12455 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12456 {
12457   rtx x = *p;
12458   enum machine_mode truncated_mode;
12459   reg_stat_type *rsp;
12460
12461   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12462     {
12463       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12464       truncated_mode = GET_MODE (x);
12465
12466       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12467         return -1;
12468
12469       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12470         return -1;
12471
12472       x = SUBREG_REG (x);
12473     }
12474   /* ??? For hard-regs we now record everything.  We might be able to
12475      optimize this using last_set_mode.  */
12476   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12477     truncated_mode = GET_MODE (x);
12478   else
12479     return 0;
12480
12481   rsp = &reg_stat[REGNO (x)];
12482   if (rsp->truncated_to_mode == 0
12483       || rsp->truncation_label < label_tick_ebb_start
12484       || (GET_MODE_SIZE (truncated_mode)
12485           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12486     {
12487       rsp->truncated_to_mode = truncated_mode;
12488       rsp->truncation_label = label_tick;
12489     }
12490
12491   return -1;
12492 }
12493
12494 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12495    the modes they are used in.  This can help truning TRUNCATEs into
12496    SUBREGs.  */
12497
12498 static void
12499 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12500 {
12501   for_each_rtx (x, record_truncated_value, NULL);
12502 }
12503
12504 /* Scan X for promoted SUBREGs.  For each one found,
12505    note what it implies to the registers used in it.  */
12506
12507 static void
12508 check_promoted_subreg (rtx insn, rtx x)
12509 {
12510   if (GET_CODE (x) == SUBREG
12511       && SUBREG_PROMOTED_VAR_P (x)
12512       && REG_P (SUBREG_REG (x)))
12513     record_promoted_value (insn, x);
12514   else
12515     {
12516       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12517       int i, j;
12518
12519       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12520         switch (format[i])
12521           {
12522           case 'e':
12523             check_promoted_subreg (insn, XEXP (x, i));
12524             break;
12525           case 'V':
12526           case 'E':
12527             if (XVEC (x, i) != 0)
12528               for (j = 0; j < XVECLEN (x, i); j++)
12529                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12530             break;
12531           }
12532     }
12533 }
12534 \f
12535 /* Verify that all the registers and memory references mentioned in *LOC are
12536    still valid.  *LOC was part of a value set in INSN when label_tick was
12537    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12538    the invalid references with (clobber (const_int 0)) and return 1.  This
12539    replacement is useful because we often can get useful information about
12540    the form of a value (e.g., if it was produced by a shift that always
12541    produces -1 or 0) even though we don't know exactly what registers it
12542    was produced from.  */
12543
12544 static int
12545 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12546 {
12547   rtx x = *loc;
12548   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12549   int len = GET_RTX_LENGTH (GET_CODE (x));
12550   int i, j;
12551
12552   if (REG_P (x))
12553     {
12554       unsigned int regno = REGNO (x);
12555       unsigned int endregno = END_REGNO (x);
12556       unsigned int j;
12557
12558       for (j = regno; j < endregno; j++)
12559         {
12560           reg_stat_type *rsp = &reg_stat[j];
12561           if (rsp->last_set_invalid
12562               /* If this is a pseudo-register that was only set once and not
12563                  live at the beginning of the function, it is always valid.  */
12564               || (! (regno >= FIRST_PSEUDO_REGISTER
12565                      && REG_N_SETS (regno) == 1
12566                      && (!REGNO_REG_SET_P
12567                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12568                   && rsp->last_set_label > tick))
12569           {
12570             if (replace)
12571               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12572             return replace;
12573           }
12574         }
12575
12576       return 1;
12577     }
12578   /* If this is a memory reference, make sure that there were no stores after
12579      it that might have clobbered the value.  We don't have alias info, so we
12580      assume any store invalidates it.  Moreover, we only have local UIDs, so
12581      we also assume that there were stores in the intervening basic blocks.  */
12582   else if (MEM_P (x) && !MEM_READONLY_P (x)
12583            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12584     {
12585       if (replace)
12586         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12587       return replace;
12588     }
12589
12590   for (i = 0; i < len; i++)
12591     {
12592       if (fmt[i] == 'e')
12593         {
12594           /* Check for identical subexpressions.  If x contains
12595              identical subexpression we only have to traverse one of
12596              them.  */
12597           if (i == 1 && ARITHMETIC_P (x))
12598             {
12599               /* Note that at this point x0 has already been checked
12600                  and found valid.  */
12601               rtx x0 = XEXP (x, 0);
12602               rtx x1 = XEXP (x, 1);
12603
12604               /* If x0 and x1 are identical then x is also valid.  */
12605               if (x0 == x1)
12606                 return 1;
12607
12608               /* If x1 is identical to a subexpression of x0 then
12609                  while checking x0, x1 has already been checked.  Thus
12610                  it is valid and so as x.  */
12611               if (ARITHMETIC_P (x0)
12612                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12613                 return 1;
12614
12615               /* If x0 is identical to a subexpression of x1 then x is
12616                  valid iff the rest of x1 is valid.  */
12617               if (ARITHMETIC_P (x1)
12618                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12619                 return
12620                   get_last_value_validate (&XEXP (x1,
12621                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12622                                            insn, tick, replace);
12623             }
12624
12625           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12626                                        replace) == 0)
12627             return 0;
12628         }
12629       else if (fmt[i] == 'E')
12630         for (j = 0; j < XVECLEN (x, i); j++)
12631           if (get_last_value_validate (&XVECEXP (x, i, j),
12632                                        insn, tick, replace) == 0)
12633             return 0;
12634     }
12635
12636   /* If we haven't found a reason for it to be invalid, it is valid.  */
12637   return 1;
12638 }
12639
12640 /* Get the last value assigned to X, if known.  Some registers
12641    in the value may be replaced with (clobber (const_int 0)) if their value
12642    is known longer known reliably.  */
12643
12644 static rtx
12645 get_last_value (const_rtx x)
12646 {
12647   unsigned int regno;
12648   rtx value;
12649   reg_stat_type *rsp;
12650
12651   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12652      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12653      we cannot predict what values the "extra" bits might have.  */
12654   if (GET_CODE (x) == SUBREG
12655       && subreg_lowpart_p (x)
12656       && !paradoxical_subreg_p (x)
12657       && (value = get_last_value (SUBREG_REG (x))) != 0)
12658     return gen_lowpart (GET_MODE (x), value);
12659
12660   if (!REG_P (x))
12661     return 0;
12662
12663   regno = REGNO (x);
12664   rsp = &reg_stat[regno];
12665   value = rsp->last_set_value;
12666
12667   /* If we don't have a value, or if it isn't for this basic block and
12668      it's either a hard register, set more than once, or it's a live
12669      at the beginning of the function, return 0.
12670
12671      Because if it's not live at the beginning of the function then the reg
12672      is always set before being used (is never used without being set).
12673      And, if it's set only once, and it's always set before use, then all
12674      uses must have the same last value, even if it's not from this basic
12675      block.  */
12676
12677   if (value == 0
12678       || (rsp->last_set_label < label_tick_ebb_start
12679           && (regno < FIRST_PSEUDO_REGISTER
12680               || REG_N_SETS (regno) != 1
12681               || REGNO_REG_SET_P
12682                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12683     return 0;
12684
12685   /* If the value was set in a later insn than the ones we are processing,
12686      we can't use it even if the register was only set once.  */
12687   if (rsp->last_set_label == label_tick
12688       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12689     return 0;
12690
12691   /* If the value has all its registers valid, return it.  */
12692   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12693     return value;
12694
12695   /* Otherwise, make a copy and replace any invalid register with
12696      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12697
12698   value = copy_rtx (value);
12699   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12700     return value;
12701
12702   return 0;
12703 }
12704 \f
12705 /* Return nonzero if expression X refers to a REG or to memory
12706    that is set in an instruction more recent than FROM_LUID.  */
12707
12708 static int
12709 use_crosses_set_p (const_rtx x, int from_luid)
12710 {
12711   const char *fmt;
12712   int i;
12713   enum rtx_code code = GET_CODE (x);
12714
12715   if (code == REG)
12716     {
12717       unsigned int regno = REGNO (x);
12718       unsigned endreg = END_REGNO (x);
12719
12720 #ifdef PUSH_ROUNDING
12721       /* Don't allow uses of the stack pointer to be moved,
12722          because we don't know whether the move crosses a push insn.  */
12723       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12724         return 1;
12725 #endif
12726       for (; regno < endreg; regno++)
12727         {
12728           reg_stat_type *rsp = &reg_stat[regno];
12729           if (rsp->last_set
12730               && rsp->last_set_label == label_tick
12731               && DF_INSN_LUID (rsp->last_set) > from_luid)
12732             return 1;
12733         }
12734       return 0;
12735     }
12736
12737   if (code == MEM && mem_last_set > from_luid)
12738     return 1;
12739
12740   fmt = GET_RTX_FORMAT (code);
12741
12742   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12743     {
12744       if (fmt[i] == 'E')
12745         {
12746           int j;
12747           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12748             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12749               return 1;
12750         }
12751       else if (fmt[i] == 'e'
12752                && use_crosses_set_p (XEXP (x, i), from_luid))
12753         return 1;
12754     }
12755   return 0;
12756 }
12757 \f
12758 /* Define three variables used for communication between the following
12759    routines.  */
12760
12761 static unsigned int reg_dead_regno, reg_dead_endregno;
12762 static int reg_dead_flag;
12763
12764 /* Function called via note_stores from reg_dead_at_p.
12765
12766    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12767    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12768
12769 static void
12770 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12771 {
12772   unsigned int regno, endregno;
12773
12774   if (!REG_P (dest))
12775     return;
12776
12777   regno = REGNO (dest);
12778   endregno = END_REGNO (dest);
12779   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12780     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12781 }
12782
12783 /* Return nonzero if REG is known to be dead at INSN.
12784
12785    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12786    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12787    live.  Otherwise, see if it is live or dead at the start of the basic
12788    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12789    must be assumed to be always live.  */
12790
12791 static int
12792 reg_dead_at_p (rtx reg, rtx insn)
12793 {
12794   basic_block block;
12795   unsigned int i;
12796
12797   /* Set variables for reg_dead_at_p_1.  */
12798   reg_dead_regno = REGNO (reg);
12799   reg_dead_endregno = END_REGNO (reg);
12800
12801   reg_dead_flag = 0;
12802
12803   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12804      we allow the machine description to decide whether use-and-clobber
12805      patterns are OK.  */
12806   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12807     {
12808       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12809         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12810           return 0;
12811     }
12812
12813   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12814      beginning of basic block.  */
12815   block = BLOCK_FOR_INSN (insn);
12816   for (;;)
12817     {
12818       if (INSN_P (insn))
12819         {
12820           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12821           if (reg_dead_flag)
12822             return reg_dead_flag == 1 ? 1 : 0;
12823
12824           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12825             return 1;
12826         }
12827
12828       if (insn == BB_HEAD (block))
12829         break;
12830
12831       insn = PREV_INSN (insn);
12832     }
12833
12834   /* Look at live-in sets for the basic block that we were in.  */
12835   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12836     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12837       return 0;
12838
12839   return 1;
12840 }
12841 \f
12842 /* Note hard registers in X that are used.  */
12843
12844 static void
12845 mark_used_regs_combine (rtx x)
12846 {
12847   RTX_CODE code = GET_CODE (x);
12848   unsigned int regno;
12849   int i;
12850
12851   switch (code)
12852     {
12853     case LABEL_REF:
12854     case SYMBOL_REF:
12855     case CONST:
12856     CASE_CONST_ANY:
12857     case PC:
12858     case ADDR_VEC:
12859     case ADDR_DIFF_VEC:
12860     case ASM_INPUT:
12861 #ifdef HAVE_cc0
12862     /* CC0 must die in the insn after it is set, so we don't need to take
12863        special note of it here.  */
12864     case CC0:
12865 #endif
12866       return;
12867
12868     case CLOBBER:
12869       /* If we are clobbering a MEM, mark any hard registers inside the
12870          address as used.  */
12871       if (MEM_P (XEXP (x, 0)))
12872         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12873       return;
12874
12875     case REG:
12876       regno = REGNO (x);
12877       /* A hard reg in a wide mode may really be multiple registers.
12878          If so, mark all of them just like the first.  */
12879       if (regno < FIRST_PSEUDO_REGISTER)
12880         {
12881           /* None of this applies to the stack, frame or arg pointers.  */
12882           if (regno == STACK_POINTER_REGNUM
12883 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12884               || regno == HARD_FRAME_POINTER_REGNUM
12885 #endif
12886 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12887               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12888 #endif
12889               || regno == FRAME_POINTER_REGNUM)
12890             return;
12891
12892           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12893         }
12894       return;
12895
12896     case SET:
12897       {
12898         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12899            the address.  */
12900         rtx testreg = SET_DEST (x);
12901
12902         while (GET_CODE (testreg) == SUBREG
12903                || GET_CODE (testreg) == ZERO_EXTRACT
12904                || GET_CODE (testreg) == STRICT_LOW_PART)
12905           testreg = XEXP (testreg, 0);
12906
12907         if (MEM_P (testreg))
12908           mark_used_regs_combine (XEXP (testreg, 0));
12909
12910         mark_used_regs_combine (SET_SRC (x));
12911       }
12912       return;
12913
12914     default:
12915       break;
12916     }
12917
12918   /* Recursively scan the operands of this expression.  */
12919
12920   {
12921     const char *fmt = GET_RTX_FORMAT (code);
12922
12923     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12924       {
12925         if (fmt[i] == 'e')
12926           mark_used_regs_combine (XEXP (x, i));
12927         else if (fmt[i] == 'E')
12928           {
12929             int j;
12930
12931             for (j = 0; j < XVECLEN (x, i); j++)
12932               mark_used_regs_combine (XVECEXP (x, i, j));
12933           }
12934       }
12935   }
12936 }
12937 \f
12938 /* Remove register number REGNO from the dead registers list of INSN.
12939
12940    Return the note used to record the death, if there was one.  */
12941
12942 rtx
12943 remove_death (unsigned int regno, rtx insn)
12944 {
12945   rtx note = find_regno_note (insn, REG_DEAD, regno);
12946
12947   if (note)
12948     remove_note (insn, note);
12949
12950   return note;
12951 }
12952
12953 /* For each register (hardware or pseudo) used within expression X, if its
12954    death is in an instruction with luid between FROM_LUID (inclusive) and
12955    TO_INSN (exclusive), put a REG_DEAD note for that register in the
12956    list headed by PNOTES.
12957
12958    That said, don't move registers killed by maybe_kill_insn.
12959
12960    This is done when X is being merged by combination into TO_INSN.  These
12961    notes will then be distributed as needed.  */
12962
12963 static void
12964 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12965              rtx *pnotes)
12966 {
12967   const char *fmt;
12968   int len, i;
12969   enum rtx_code code = GET_CODE (x);
12970
12971   if (code == REG)
12972     {
12973       unsigned int regno = REGNO (x);
12974       rtx where_dead = reg_stat[regno].last_death;
12975
12976       /* Don't move the register if it gets killed in between from and to.  */
12977       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12978           && ! reg_referenced_p (x, maybe_kill_insn))
12979         return;
12980
12981       if (where_dead
12982           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12983           && DF_INSN_LUID (where_dead) >= from_luid
12984           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12985         {
12986           rtx note = remove_death (regno, where_dead);
12987
12988           /* It is possible for the call above to return 0.  This can occur
12989              when last_death points to I2 or I1 that we combined with.
12990              In that case make a new note.
12991
12992              We must also check for the case where X is a hard register
12993              and NOTE is a death note for a range of hard registers
12994              including X.  In that case, we must put REG_DEAD notes for
12995              the remaining registers in place of NOTE.  */
12996
12997           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12998               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12999                   > GET_MODE_SIZE (GET_MODE (x))))
13000             {
13001               unsigned int deadregno = REGNO (XEXP (note, 0));
13002               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13003               unsigned int ourend = END_HARD_REGNO (x);
13004               unsigned int i;
13005
13006               for (i = deadregno; i < deadend; i++)
13007                 if (i < regno || i >= ourend)
13008                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13009             }
13010
13011           /* If we didn't find any note, or if we found a REG_DEAD note that
13012              covers only part of the given reg, and we have a multi-reg hard
13013              register, then to be safe we must check for REG_DEAD notes
13014              for each register other than the first.  They could have
13015              their own REG_DEAD notes lying around.  */
13016           else if ((note == 0
13017                     || (note != 0
13018                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13019                             < GET_MODE_SIZE (GET_MODE (x)))))
13020                    && regno < FIRST_PSEUDO_REGISTER
13021                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13022             {
13023               unsigned int ourend = END_HARD_REGNO (x);
13024               unsigned int i, offset;
13025               rtx oldnotes = 0;
13026
13027               if (note)
13028                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13029               else
13030                 offset = 1;
13031
13032               for (i = regno + offset; i < ourend; i++)
13033                 move_deaths (regno_reg_rtx[i],
13034                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13035             }
13036
13037           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13038             {
13039               XEXP (note, 1) = *pnotes;
13040               *pnotes = note;
13041             }
13042           else
13043             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13044         }
13045
13046       return;
13047     }
13048
13049   else if (GET_CODE (x) == SET)
13050     {
13051       rtx dest = SET_DEST (x);
13052
13053       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13054
13055       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13056          that accesses one word of a multi-word item, some
13057          piece of everything register in the expression is used by
13058          this insn, so remove any old death.  */
13059       /* ??? So why do we test for equality of the sizes?  */
13060
13061       if (GET_CODE (dest) == ZERO_EXTRACT
13062           || GET_CODE (dest) == STRICT_LOW_PART
13063           || (GET_CODE (dest) == SUBREG
13064               && (((GET_MODE_SIZE (GET_MODE (dest))
13065                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13066                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13067                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13068         {
13069           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13070           return;
13071         }
13072
13073       /* If this is some other SUBREG, we know it replaces the entire
13074          value, so use that as the destination.  */
13075       if (GET_CODE (dest) == SUBREG)
13076         dest = SUBREG_REG (dest);
13077
13078       /* If this is a MEM, adjust deaths of anything used in the address.
13079          For a REG (the only other possibility), the entire value is
13080          being replaced so the old value is not used in this insn.  */
13081
13082       if (MEM_P (dest))
13083         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13084                      to_insn, pnotes);
13085       return;
13086     }
13087
13088   else if (GET_CODE (x) == CLOBBER)
13089     return;
13090
13091   len = GET_RTX_LENGTH (code);
13092   fmt = GET_RTX_FORMAT (code);
13093
13094   for (i = 0; i < len; i++)
13095     {
13096       if (fmt[i] == 'E')
13097         {
13098           int j;
13099           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13100             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13101                          to_insn, pnotes);
13102         }
13103       else if (fmt[i] == 'e')
13104         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13105     }
13106 }
13107 \f
13108 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13109    pattern of an insn.  X must be a REG.  */
13110
13111 static int
13112 reg_bitfield_target_p (rtx x, rtx body)
13113 {
13114   int i;
13115
13116   if (GET_CODE (body) == SET)
13117     {
13118       rtx dest = SET_DEST (body);
13119       rtx target;
13120       unsigned int regno, tregno, endregno, endtregno;
13121
13122       if (GET_CODE (dest) == ZERO_EXTRACT)
13123         target = XEXP (dest, 0);
13124       else if (GET_CODE (dest) == STRICT_LOW_PART)
13125         target = SUBREG_REG (XEXP (dest, 0));
13126       else
13127         return 0;
13128
13129       if (GET_CODE (target) == SUBREG)
13130         target = SUBREG_REG (target);
13131
13132       if (!REG_P (target))
13133         return 0;
13134
13135       tregno = REGNO (target), regno = REGNO (x);
13136       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13137         return target == x;
13138
13139       endtregno = end_hard_regno (GET_MODE (target), tregno);
13140       endregno = end_hard_regno (GET_MODE (x), regno);
13141
13142       return endregno > tregno && regno < endtregno;
13143     }
13144
13145   else if (GET_CODE (body) == PARALLEL)
13146     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13147       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13148         return 1;
13149
13150   return 0;
13151 }
13152 \f
13153 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13154    as appropriate.  I3 and I2 are the insns resulting from the combination
13155    insns including FROM (I2 may be zero).
13156
13157    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13158    not need REG_DEAD notes because they are being substituted for.  This
13159    saves searching in the most common cases.
13160
13161    Each note in the list is either ignored or placed on some insns, depending
13162    on the type of note.  */
13163
13164 static void
13165 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13166                   rtx elim_i1, rtx elim_i0)
13167 {
13168   rtx note, next_note;
13169   rtx tem;
13170
13171   for (note = notes; note; note = next_note)
13172     {
13173       rtx place = 0, place2 = 0;
13174
13175       next_note = XEXP (note, 1);
13176       switch (REG_NOTE_KIND (note))
13177         {
13178         case REG_BR_PROB:
13179         case REG_BR_PRED:
13180           /* Doesn't matter much where we put this, as long as it's somewhere.
13181              It is preferable to keep these notes on branches, which is most
13182              likely to be i3.  */
13183           place = i3;
13184           break;
13185
13186         case REG_NON_LOCAL_GOTO:
13187           if (JUMP_P (i3))
13188             place = i3;
13189           else
13190             {
13191               gcc_assert (i2 && JUMP_P (i2));
13192               place = i2;
13193             }
13194           break;
13195
13196         case REG_EH_REGION:
13197           /* These notes must remain with the call or trapping instruction.  */
13198           if (CALL_P (i3))
13199             place = i3;
13200           else if (i2 && CALL_P (i2))
13201             place = i2;
13202           else
13203             {
13204               gcc_assert (cfun->can_throw_non_call_exceptions);
13205               if (may_trap_p (i3))
13206                 place = i3;
13207               else if (i2 && may_trap_p (i2))
13208                 place = i2;
13209               /* ??? Otherwise assume we've combined things such that we
13210                  can now prove that the instructions can't trap.  Drop the
13211                  note in this case.  */
13212             }
13213           break;
13214
13215         case REG_ARGS_SIZE:
13216           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13217              entire adjustment.  Assert i3 contains at least some adjust.  */
13218           if (!noop_move_p (i3))
13219             {
13220               int old_size, args_size = INTVAL (XEXP (note, 0));
13221               /* fixup_args_size_notes looks at REG_NORETURN note,
13222                  so ensure the note is placed there first.  */
13223               if (CALL_P (i3))
13224                 {
13225                   rtx *np;
13226                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13227                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13228                       {
13229                         rtx n = *np;
13230                         *np = XEXP (n, 1);
13231                         XEXP (n, 1) = REG_NOTES (i3);
13232                         REG_NOTES (i3) = n;
13233                         break;
13234                       }
13235                 }
13236               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13237               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13238                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13239               gcc_assert (old_size != args_size
13240                           || (CALL_P (i3)
13241                               && !ACCUMULATE_OUTGOING_ARGS
13242                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13243             }
13244           break;
13245
13246         case REG_NORETURN:
13247         case REG_SETJMP:
13248         case REG_TM:
13249           /* These notes must remain with the call.  It should not be
13250              possible for both I2 and I3 to be a call.  */
13251           if (CALL_P (i3))
13252             place = i3;
13253           else
13254             {
13255               gcc_assert (i2 && CALL_P (i2));
13256               place = i2;
13257             }
13258           break;
13259
13260         case REG_UNUSED:
13261           /* Any clobbers for i3 may still exist, and so we must process
13262              REG_UNUSED notes from that insn.
13263
13264              Any clobbers from i2 or i1 can only exist if they were added by
13265              recog_for_combine.  In that case, recog_for_combine created the
13266              necessary REG_UNUSED notes.  Trying to keep any original
13267              REG_UNUSED notes from these insns can cause incorrect output
13268              if it is for the same register as the original i3 dest.
13269              In that case, we will notice that the register is set in i3,
13270              and then add a REG_UNUSED note for the destination of i3, which
13271              is wrong.  However, it is possible to have REG_UNUSED notes from
13272              i2 or i1 for register which were both used and clobbered, so
13273              we keep notes from i2 or i1 if they will turn into REG_DEAD
13274              notes.  */
13275
13276           /* If this register is set or clobbered in I3, put the note there
13277              unless there is one already.  */
13278           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13279             {
13280               if (from_insn != i3)
13281                 break;
13282
13283               if (! (REG_P (XEXP (note, 0))
13284                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13285                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13286                 place = i3;
13287             }
13288           /* Otherwise, if this register is used by I3, then this register
13289              now dies here, so we must put a REG_DEAD note here unless there
13290              is one already.  */
13291           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13292                    && ! (REG_P (XEXP (note, 0))
13293                          ? find_regno_note (i3, REG_DEAD,
13294                                             REGNO (XEXP (note, 0)))
13295                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13296             {
13297               PUT_REG_NOTE_KIND (note, REG_DEAD);
13298               place = i3;
13299             }
13300           break;
13301
13302         case REG_EQUAL:
13303         case REG_EQUIV:
13304         case REG_NOALIAS:
13305           /* These notes say something about results of an insn.  We can
13306              only support them if they used to be on I3 in which case they
13307              remain on I3.  Otherwise they are ignored.
13308
13309              If the note refers to an expression that is not a constant, we
13310              must also ignore the note since we cannot tell whether the
13311              equivalence is still true.  It might be possible to do
13312              slightly better than this (we only have a problem if I2DEST
13313              or I1DEST is present in the expression), but it doesn't
13314              seem worth the trouble.  */
13315
13316           if (from_insn == i3
13317               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13318             place = i3;
13319           break;
13320
13321         case REG_INC:
13322           /* These notes say something about how a register is used.  They must
13323              be present on any use of the register in I2 or I3.  */
13324           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13325             place = i3;
13326
13327           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13328             {
13329               if (place)
13330                 place2 = i2;
13331               else
13332                 place = i2;
13333             }
13334           break;
13335
13336         case REG_LABEL_TARGET:
13337         case REG_LABEL_OPERAND:
13338           /* This can show up in several ways -- either directly in the
13339              pattern, or hidden off in the constant pool with (or without?)
13340              a REG_EQUAL note.  */
13341           /* ??? Ignore the without-reg_equal-note problem for now.  */
13342           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13343               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13344                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13345                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13346             place = i3;
13347
13348           if (i2
13349               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13350                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13351                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13352                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13353             {
13354               if (place)
13355                 place2 = i2;
13356               else
13357                 place = i2;
13358             }
13359
13360           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13361              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13362              there.  */
13363           if (place && JUMP_P (place)
13364               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13365               && (JUMP_LABEL (place) == NULL
13366                   || JUMP_LABEL (place) == XEXP (note, 0)))
13367             {
13368               rtx label = JUMP_LABEL (place);
13369
13370               if (!label)
13371                 JUMP_LABEL (place) = XEXP (note, 0);
13372               else if (LABEL_P (label))
13373                 LABEL_NUSES (label)--;
13374             }
13375
13376           if (place2 && JUMP_P (place2)
13377               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13378               && (JUMP_LABEL (place2) == NULL
13379                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13380             {
13381               rtx label = JUMP_LABEL (place2);
13382
13383               if (!label)
13384                 JUMP_LABEL (place2) = XEXP (note, 0);
13385               else if (LABEL_P (label))
13386                 LABEL_NUSES (label)--;
13387               place2 = 0;
13388             }
13389           break;
13390
13391         case REG_NONNEG:
13392           /* This note says something about the value of a register prior
13393              to the execution of an insn.  It is too much trouble to see
13394              if the note is still correct in all situations.  It is better
13395              to simply delete it.  */
13396           break;
13397
13398         case REG_DEAD:
13399           /* If we replaced the right hand side of FROM_INSN with a
13400              REG_EQUAL note, the original use of the dying register
13401              will not have been combined into I3 and I2.  In such cases,
13402              FROM_INSN is guaranteed to be the first of the combined
13403              instructions, so we simply need to search back before
13404              FROM_INSN for the previous use or set of this register,
13405              then alter the notes there appropriately.
13406
13407              If the register is used as an input in I3, it dies there.
13408              Similarly for I2, if it is nonzero and adjacent to I3.
13409
13410              If the register is not used as an input in either I3 or I2
13411              and it is not one of the registers we were supposed to eliminate,
13412              there are two possibilities.  We might have a non-adjacent I2
13413              or we might have somehow eliminated an additional register
13414              from a computation.  For example, we might have had A & B where
13415              we discover that B will always be zero.  In this case we will
13416              eliminate the reference to A.
13417
13418              In both cases, we must search to see if we can find a previous
13419              use of A and put the death note there.  */
13420
13421           if (from_insn
13422               && from_insn == i2mod
13423               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13424             tem = from_insn;
13425           else
13426             {
13427               if (from_insn
13428                   && CALL_P (from_insn)
13429                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13430                 place = from_insn;
13431               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13432                 place = i3;
13433               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13434                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13435                 place = i2;
13436               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13437                         && !(i2mod
13438                              && reg_overlap_mentioned_p (XEXP (note, 0),
13439                                                          i2mod_old_rhs)))
13440                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13441                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13442                 break;
13443               tem = i3;
13444             }
13445
13446           if (place == 0)
13447             {
13448               basic_block bb = this_basic_block;
13449
13450               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13451                 {
13452                   if (!NONDEBUG_INSN_P (tem))
13453                     {
13454                       if (tem == BB_HEAD (bb))
13455                         break;
13456                       continue;
13457                     }
13458
13459                   /* If the register is being set at TEM, see if that is all
13460                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13461                      into a REG_UNUSED note instead. Don't delete sets to
13462                      global register vars.  */
13463                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13464                        || !global_regs[REGNO (XEXP (note, 0))])
13465                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13466                     {
13467                       rtx set = single_set (tem);
13468                       rtx inner_dest = 0;
13469 #ifdef HAVE_cc0
13470                       rtx cc0_setter = NULL_RTX;
13471 #endif
13472
13473                       if (set != 0)
13474                         for (inner_dest = SET_DEST (set);
13475                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13476                               || GET_CODE (inner_dest) == SUBREG
13477                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13478                              inner_dest = XEXP (inner_dest, 0))
13479                           ;
13480
13481                       /* Verify that it was the set, and not a clobber that
13482                          modified the register.
13483
13484                          CC0 targets must be careful to maintain setter/user
13485                          pairs.  If we cannot delete the setter due to side
13486                          effects, mark the user with an UNUSED note instead
13487                          of deleting it.  */
13488
13489                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13490                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13491 #ifdef HAVE_cc0
13492                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13493                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13494                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13495 #endif
13496                           )
13497                         {
13498                           /* Move the notes and links of TEM elsewhere.
13499                              This might delete other dead insns recursively.
13500                              First set the pattern to something that won't use
13501                              any register.  */
13502                           rtx old_notes = REG_NOTES (tem);
13503
13504                           PATTERN (tem) = pc_rtx;
13505                           REG_NOTES (tem) = NULL;
13506
13507                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13508                                             NULL_RTX, NULL_RTX, NULL_RTX);
13509                           distribute_links (LOG_LINKS (tem));
13510
13511                           SET_INSN_DELETED (tem);
13512                           if (tem == i2)
13513                             i2 = NULL_RTX;
13514
13515 #ifdef HAVE_cc0
13516                           /* Delete the setter too.  */
13517                           if (cc0_setter)
13518                             {
13519                               PATTERN (cc0_setter) = pc_rtx;
13520                               old_notes = REG_NOTES (cc0_setter);
13521                               REG_NOTES (cc0_setter) = NULL;
13522
13523                               distribute_notes (old_notes, cc0_setter,
13524                                                 cc0_setter, NULL_RTX,
13525                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13526                               distribute_links (LOG_LINKS (cc0_setter));
13527
13528                               SET_INSN_DELETED (cc0_setter);
13529                               if (cc0_setter == i2)
13530                                 i2 = NULL_RTX;
13531                             }
13532 #endif
13533                         }
13534                       else
13535                         {
13536                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13537
13538                           /*  If there isn't already a REG_UNUSED note, put one
13539                               here.  Do not place a REG_DEAD note, even if
13540                               the register is also used here; that would not
13541                               match the algorithm used in lifetime analysis
13542                               and can cause the consistency check in the
13543                               scheduler to fail.  */
13544                           if (! find_regno_note (tem, REG_UNUSED,
13545                                                  REGNO (XEXP (note, 0))))
13546                             place = tem;
13547                           break;
13548                         }
13549                     }
13550                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13551                            || (CALL_P (tem)
13552                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13553                     {
13554                       place = tem;
13555
13556                       /* If we are doing a 3->2 combination, and we have a
13557                          register which formerly died in i3 and was not used
13558                          by i2, which now no longer dies in i3 and is used in
13559                          i2 but does not die in i2, and place is between i2
13560                          and i3, then we may need to move a link from place to
13561                          i2.  */
13562                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13563                           && from_insn
13564                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13565                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13566                         {
13567                           struct insn_link *links = LOG_LINKS (place);
13568                           LOG_LINKS (place) = NULL;
13569                           distribute_links (links);
13570                         }
13571                       break;
13572                     }
13573
13574                   if (tem == BB_HEAD (bb))
13575                     break;
13576                 }
13577
13578             }
13579
13580           /* If the register is set or already dead at PLACE, we needn't do
13581              anything with this note if it is still a REG_DEAD note.
13582              We check here if it is set at all, not if is it totally replaced,
13583              which is what `dead_or_set_p' checks, so also check for it being
13584              set partially.  */
13585
13586           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13587             {
13588               unsigned int regno = REGNO (XEXP (note, 0));
13589               reg_stat_type *rsp = &reg_stat[regno];
13590
13591               if (dead_or_set_p (place, XEXP (note, 0))
13592                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13593                 {
13594                   /* Unless the register previously died in PLACE, clear
13595                      last_death.  [I no longer understand why this is
13596                      being done.] */
13597                   if (rsp->last_death != place)
13598                     rsp->last_death = 0;
13599                   place = 0;
13600                 }
13601               else
13602                 rsp->last_death = place;
13603
13604               /* If this is a death note for a hard reg that is occupying
13605                  multiple registers, ensure that we are still using all
13606                  parts of the object.  If we find a piece of the object
13607                  that is unused, we must arrange for an appropriate REG_DEAD
13608                  note to be added for it.  However, we can't just emit a USE
13609                  and tag the note to it, since the register might actually
13610                  be dead; so we recourse, and the recursive call then finds
13611                  the previous insn that used this register.  */
13612
13613               if (place && regno < FIRST_PSEUDO_REGISTER
13614                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13615                 {
13616                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13617                   bool all_used = true;
13618                   unsigned int i;
13619
13620                   for (i = regno; i < endregno; i++)
13621                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13622                          && ! find_regno_fusage (place, USE, i))
13623                         || dead_or_set_regno_p (place, i))
13624                       {
13625                         all_used = false;
13626                         break;
13627                       }
13628
13629                   if (! all_used)
13630                     {
13631                       /* Put only REG_DEAD notes for pieces that are
13632                          not already dead or set.  */
13633
13634                       for (i = regno; i < endregno;
13635                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13636                         {
13637                           rtx piece = regno_reg_rtx[i];
13638                           basic_block bb = this_basic_block;
13639
13640                           if (! dead_or_set_p (place, piece)
13641                               && ! reg_bitfield_target_p (piece,
13642                                                           PATTERN (place)))
13643                             {
13644                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13645                                                              NULL_RTX);
13646
13647                               distribute_notes (new_note, place, place,
13648                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13649                                                 NULL_RTX);
13650                             }
13651                           else if (! refers_to_regno_p (i, i + 1,
13652                                                         PATTERN (place), 0)
13653                                    && ! find_regno_fusage (place, USE, i))
13654                             for (tem = PREV_INSN (place); ;
13655                                  tem = PREV_INSN (tem))
13656                               {
13657                                 if (!NONDEBUG_INSN_P (tem))
13658                                   {
13659                                     if (tem == BB_HEAD (bb))
13660                                       break;
13661                                     continue;
13662                                   }
13663                                 if (dead_or_set_p (tem, piece)
13664                                     || reg_bitfield_target_p (piece,
13665                                                               PATTERN (tem)))
13666                                   {
13667                                     add_reg_note (tem, REG_UNUSED, piece);
13668                                     break;
13669                                   }
13670                               }
13671                         }
13672
13673                       place = 0;
13674                     }
13675                 }
13676             }
13677           break;
13678
13679         default:
13680           /* Any other notes should not be present at this point in the
13681              compilation.  */
13682           gcc_unreachable ();
13683         }
13684
13685       if (place)
13686         {
13687           XEXP (note, 1) = REG_NOTES (place);
13688           REG_NOTES (place) = note;
13689         }
13690
13691       if (place2)
13692         add_shallow_copy_of_reg_note (place2, note);
13693     }
13694 }
13695 \f
13696 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13697    I3, I2, and I1 to new locations.  This is also called to add a link
13698    pointing at I3 when I3's destination is changed.  */
13699
13700 static void
13701 distribute_links (struct insn_link *links)
13702 {
13703   struct insn_link *link, *next_link;
13704
13705   for (link = links; link; link = next_link)
13706     {
13707       rtx place = 0;
13708       rtx insn;
13709       rtx set, reg;
13710
13711       next_link = link->next;
13712
13713       /* If the insn that this link points to is a NOTE or isn't a single
13714          set, ignore it.  In the latter case, it isn't clear what we
13715          can do other than ignore the link, since we can't tell which
13716          register it was for.  Such links wouldn't be used by combine
13717          anyway.
13718
13719          It is not possible for the destination of the target of the link to
13720          have been changed by combine.  The only potential of this is if we
13721          replace I3, I2, and I1 by I3 and I2.  But in that case the
13722          destination of I2 also remains unchanged.  */
13723
13724       if (NOTE_P (link->insn)
13725           || (set = single_set (link->insn)) == 0)
13726         continue;
13727
13728       reg = SET_DEST (set);
13729       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13730              || GET_CODE (reg) == STRICT_LOW_PART)
13731         reg = XEXP (reg, 0);
13732
13733       /* A LOG_LINK is defined as being placed on the first insn that uses
13734          a register and points to the insn that sets the register.  Start
13735          searching at the next insn after the target of the link and stop
13736          when we reach a set of the register or the end of the basic block.
13737
13738          Note that this correctly handles the link that used to point from
13739          I3 to I2.  Also note that not much searching is typically done here
13740          since most links don't point very far away.  */
13741
13742       for (insn = NEXT_INSN (link->insn);
13743            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13744                      || BB_HEAD (this_basic_block->next_bb) != insn));
13745            insn = NEXT_INSN (insn))
13746         if (DEBUG_INSN_P (insn))
13747           continue;
13748         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13749           {
13750             if (reg_referenced_p (reg, PATTERN (insn)))
13751               place = insn;
13752             break;
13753           }
13754         else if (CALL_P (insn)
13755                  && find_reg_fusage (insn, USE, reg))
13756           {
13757             place = insn;
13758             break;
13759           }
13760         else if (INSN_P (insn) && reg_set_p (reg, insn))
13761           break;
13762
13763       /* If we found a place to put the link, place it there unless there
13764          is already a link to the same insn as LINK at that point.  */
13765
13766       if (place)
13767         {
13768           struct insn_link *link2;
13769
13770           FOR_EACH_LOG_LINK (link2, place)
13771             if (link2->insn == link->insn)
13772               break;
13773
13774           if (link2 == NULL)
13775             {
13776               link->next = LOG_LINKS (place);
13777               LOG_LINKS (place) = link;
13778
13779               /* Set added_links_insn to the earliest insn we added a
13780                  link to.  */
13781               if (added_links_insn == 0
13782                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13783                 added_links_insn = place;
13784             }
13785         }
13786     }
13787 }
13788 \f
13789 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13790    Check whether the expression pointer to by LOC is a register or
13791    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13792    Otherwise return zero.  */
13793
13794 static int
13795 unmentioned_reg_p_1 (rtx *loc, void *expr)
13796 {
13797   rtx x = *loc;
13798
13799   if (x != NULL_RTX
13800       && (REG_P (x) || MEM_P (x))
13801       && ! reg_mentioned_p (x, (rtx) expr))
13802     return 1;
13803   return 0;
13804 }
13805
13806 /* Check for any register or memory mentioned in EQUIV that is not
13807    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13808    of EXPR where some registers may have been replaced by constants.  */
13809
13810 static bool
13811 unmentioned_reg_p (rtx equiv, rtx expr)
13812 {
13813   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13814 }
13815 \f
13816 DEBUG_FUNCTION void
13817 dump_combine_stats (FILE *file)
13818 {
13819   fprintf
13820     (file,
13821      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13822      combine_attempts, combine_merges, combine_extras, combine_successes);
13823 }
13824
13825 void
13826 dump_combine_total_stats (FILE *file)
13827 {
13828   fprintf
13829     (file,
13830      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13831      total_attempts, total_merges, total_extras, total_successes);
13832 }
13833 \f
13834 static bool
13835 gate_handle_combine (void)
13836 {
13837   return (optimize > 0);
13838 }
13839
13840 /* Try combining insns through substitution.  */
13841 static unsigned int
13842 rest_of_handle_combine (void)
13843 {
13844   int rebuild_jump_labels_after_combine;
13845
13846   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13847   df_note_add_problem ();
13848   df_analyze ();
13849
13850   regstat_init_n_sets_and_refs ();
13851
13852   rebuild_jump_labels_after_combine
13853     = combine_instructions (get_insns (), max_reg_num ());
13854
13855   /* Combining insns may have turned an indirect jump into a
13856      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13857      instructions.  */
13858   if (rebuild_jump_labels_after_combine)
13859     {
13860       timevar_push (TV_JUMP);
13861       rebuild_jump_labels (get_insns ());
13862       cleanup_cfg (0);
13863       timevar_pop (TV_JUMP);
13864     }
13865
13866   regstat_free_n_sets_and_refs ();
13867   return 0;
13868 }
13869
13870 namespace {
13871
13872 const pass_data pass_data_combine =
13873 {
13874   RTL_PASS, /* type */
13875   "combine", /* name */
13876   OPTGROUP_NONE, /* optinfo_flags */
13877   true, /* has_gate */
13878   true, /* has_execute */
13879   TV_COMBINE, /* tv_id */
13880   PROP_cfglayout, /* properties_required */
13881   0, /* properties_provided */
13882   0, /* properties_destroyed */
13883   0, /* todo_flags_start */
13884   ( TODO_df_finish | TODO_verify_rtl_sharing ), /* todo_flags_finish */
13885 };
13886
13887 class pass_combine : public rtl_opt_pass
13888 {
13889 public:
13890   pass_combine (gcc::context *ctxt)
13891     : rtl_opt_pass (pass_data_combine, ctxt)
13892   {}
13893
13894   /* opt_pass methods: */
13895   bool gate () { return gate_handle_combine (); }
13896   unsigned int execute () { return rest_of_handle_combine (); }
13897
13898 }; // class pass_combine
13899
13900 } // anon namespace
13901
13902 rtl_opt_pass *
13903 make_pass_combine (gcc::context *ctxt)
13904 {
13905   return new pass_combine (ctxt);
13906 }