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Delete target options -m2 -m3 & -m6.
[official-gcc.git] / gcc / config / arm / arm.h
blobf8800bc65382bea9becc260a626d031e261e9c54
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 /* Configuration triples for ARM ports work as follows:
25 (This is a bit of a mess and needs some thought)
26 arm-*-*: little endian
27 armel-*-*: little endian
28 armeb-*-*: big endian
29 If a non-embedded environment (ie: "real" OS) is specified, `arm'
30 should default to that used by the OS.
31 */
32
33 #ifndef __ARM_H__
34 #define __ARM_H__
35
36 #define TARGET_CPU_arm2 0x0000
37 #define TARGET_CPU_arm250 0x0000
38 #define TARGET_CPU_arm3 0x0000
39 #define TARGET_CPU_arm6 0x0001
40 #define TARGET_CPU_arm600 0x0001
41 #define TARGET_CPU_arm610 0x0002
42 #define TARGET_CPU_arm7 0x0001
43 #define TARGET_CPU_arm7m 0x0004
44 #define TARGET_CPU_arm7dm 0x0004
45 #define TARGET_CPU_arm7dmi 0x0004
46 #define TARGET_CPU_arm700 0x0001
47 #define TARGET_CPU_arm710 0x0002
48 #define TARGET_CPU_arm7100 0x0002
49 #define TARGET_CPU_arm7500 0x0002
50 #define TARGET_CPU_arm7500fe 0x1001
51 #define TARGET_CPU_arm7tdmi 0x0008
52 #define TARGET_CPU_arm8 0x0010
53 #define TARGET_CPU_arm810 0x0020
54 #define TARGET_CPU_strongarm 0x0040
55 #define TARGET_CPU_strongarm110 0x0040
56 #define TARGET_CPU_strongarm1100 0x0040
57 #define TARGET_CPU_arm9 0x0080
58 #define TARGET_CPU_arm9tdmi 0x0080
59 /* Configure didn't specify */
60 #define TARGET_CPU_generic 0x8000
61
62 enum arm_cond_code
63 {
64 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
65 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
66 };
67 extern enum arm_cond_code arm_current_cc;
68 extern char *arm_condition_codes[];
69
70 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
71
72 /* This is needed by the tail-calling peepholes */
73 extern int frame_pointer_needed;
74
75 \f
76 /* Just in case configure has failed to define anything. */
77 #ifndef TARGET_CPU_DEFAULT
78 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
79 #endif
80
81 /* If the configuration file doesn't specify the cpu, the subtarget may
82 override it. If it doesn't, then default to an ARM6. */
83 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
84 #undef TARGET_CPU_DEFAULT
85 #ifdef SUBTARGET_CPU_DEFAULT
86 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
87 #else
88 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
89 #endif
90 #endif
91
92 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
93 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
94 #else
95 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
96 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
97 #else
98 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
99 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
100 #else
101 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
102 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
103 #else
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
106 #else
107 Unrecognized value in TARGET_CPU_DEFAULT.
108 #endif
109 #endif
110 #endif
111 #endif
112 #endif
113
114 #ifndef CPP_PREDEFINES
115 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
116 #endif
117
118 #define CPP_SPEC "\
119 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
120 %(cpp_endian) %(subtarget_cpp_spec)"
121
122 /* Set the architecture define -- if -march= is set, then it overrides
123 the -mcpu= setting. */
124 #define CPP_CPU_ARCH_SPEC "\
125 %{march=arm2:-D__ARM_ARCH_2__} \
126 %{march=arm250:-D__ARM_ARCH_2__} \
127 %{march=arm3:-D__ARM_ARCH_2__} \
128 %{march=arm6:-D__ARM_ARCH_3__} \
129 %{march=arm600:-D__ARM_ARCH_3__} \
130 %{march=arm610:-D__ARM_ARCH_3__} \
131 %{march=arm7:-D__ARM_ARCH_3__} \
132 %{march=arm700:-D__ARM_ARCH_3__} \
133 %{march=arm710:-D__ARM_ARCH_3__} \
134 %{march=arm7100:-D__ARM_ARCH_3__} \
135 %{march=arm7500:-D__ARM_ARCH_3__} \
136 %{march=arm7500fe:-D__ARM_ARCH_3__} \
137 %{march=arm7m:-D__ARM_ARCH_3M__} \
138 %{march=arm7dm:-D__ARM_ARCH_3M__} \
139 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
140 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
141 %{march=arm8:-D__ARM_ARCH_4__} \
142 %{march=arm810:-D__ARM_ARCH_4__} \
143 %{march=arm9:-D__ARM_ARCH_4T__} \
144 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
145 %{march=strongarm:-D__ARM_ARCH_4__} \
146 %{march=strongarm110:-D__ARM_ARCH_4__} \
147 %{march=strongarm1100:-D__ARM_ARCH_4__} \
148 %{march=armv2:-D__ARM_ARCH_2__} \
149 %{march=armv2a:-D__ARM_ARCH_2__} \
150 %{march=armv3:-D__ARM_ARCH_3__} \
151 %{march=armv3m:-D__ARM_ARCH_3M__} \
152 %{march=armv4:-D__ARM_ARCH_4__} \
153 %{march=armv4t:-D__ARM_ARCH_4T__} \
154 %{!march=*: \
155 %{mcpu=arm2:-D__ARM_ARCH_2__} \
156 %{mcpu=arm250:-D__ARM_ARCH_2__} \
157 %{mcpu=arm3:-D__ARM_ARCH_2__} \
158 %{mcpu=arm6:-D__ARM_ARCH_3__} \
159 %{mcpu=arm600:-D__ARM_ARCH_3__} \
160 %{mcpu=arm610:-D__ARM_ARCH_3__} \
161 %{mcpu=arm7:-D__ARM_ARCH_3__} \
162 %{mcpu=arm700:-D__ARM_ARCH_3__} \
163 %{mcpu=arm710:-D__ARM_ARCH_3__} \
164 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
165 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
166 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
167 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
168 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
169 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
170 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
171 %{mcpu=arm8:-D__ARM_ARCH_4__} \
172 %{mcpu=arm810:-D__ARM_ARCH_4__} \
173 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
174 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
175 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
176 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
177 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
178 %{!mcpu*:%(cpp_cpu_arch_default)}} \
179 "
180
181 /* Define __APCS_26__ if the PC also contains the PSR */
182 #define CPP_APCS_PC_SPEC "\
183 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
184 -D__APCS_32__} \
185 %{mapcs-26:-D__APCS_26__} \
186 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
187 "
188
189 #ifndef CPP_APCS_PC_DEFAULT_SPEC
190 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
191 #endif
192
193 #define CPP_FLOAT_SPEC "\
194 %{msoft-float:\
195 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
196 -D__SOFTFP__} \
197 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
198 "
199
200 /* Default is hard float, which doesn't define anything */
201 #define CPP_FLOAT_DEFAULT_SPEC ""
202
203 #define CPP_ENDIAN_SPEC "\
204 %{mbig-endian: \
205 %{mlittle-endian: \
206 %e-mbig-endian and -mlittle-endian may not be used together} \
207 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
208 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
209 "
210
211 /* Default is little endian, which doesn't define anything. */
212 #define CPP_ENDIAN_DEFAULT_SPEC ""
213
214 #define CC1_SPEC ""
215
216 /* This macro defines names of additional specifications to put in the specs
217 that can be used in various specifications like CC1_SPEC. Its definition
218 is an initializer with a subgrouping for each command option.
219
220 Each subgrouping contains a string constant, that defines the
221 specification name, and a string constant that used by the GNU CC driver
222 program.
223
224 Do not define this macro if it does not need to do anything. */
225 #define EXTRA_SPECS \
226 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
227 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
228 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
229 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
230 { "cpp_float", CPP_FLOAT_SPEC }, \
231 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
232 { "cpp_endian", CPP_ENDIAN_SPEC }, \
233 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
235 SUBTARGET_EXTRA_SPECS
236
237 #define SUBTARGET_EXTRA_SPECS
238 #define SUBTARGET_CPP_SPEC ""
239
240 \f
241 /* Run-time Target Specification. */
242 #ifndef TARGET_VERSION
243 #define TARGET_VERSION \
244 fputs (" (ARM/generic)", stderr);
245 #endif
246
247 /* Run-time compilation parameters selecting different hardware subsets. */
248 extern int target_flags;
249
250 /* The floating point instruction architecture, can be 2 or 3 */
251 extern char * target_fp_name;
252
253 /* Nonzero if the function prologue (and epilogue) should obey
254 the ARM Procedure Call Standard. */
255 #define ARM_FLAG_APCS_FRAME (0x0001)
256
257 /* Nonzero if the function prologue should output the function name to enable
258 the post mortem debugger to print a backtrace (very useful on RISCOS,
259 unused on RISCiX). Specifying this flag also enables
260 -fno-omit-frame-pointer.
261 XXX Must still be implemented in the prologue. */
262 #define ARM_FLAG_POKE (0x0002)
263
264 /* Nonzero if floating point instructions are emulated by the FPE, in which
265 case instruction scheduling becomes very uninteresting. */
266 #define ARM_FLAG_FPE (0x0004)
267
268 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
269 that assume restoration of the condition flags when returning from a
270 branch and link (ie a function). */
271 #define ARM_FLAG_APCS_32 (0x0020)
272
273 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
274
275 /* Nonzero if stack checking should be performed on entry to each function
276 which allocates temporary variables on the stack. */
277 #define ARM_FLAG_APCS_STACK (0x0040)
278
279 /* Nonzero if floating point parameters should be passed to functions in
280 floating point registers. */
281 #define ARM_FLAG_APCS_FLOAT (0x0080)
282
283 /* Nonzero if re-entrant, position independent code should be generated.
284 This is equivalent to -fpic. */
285 #define ARM_FLAG_APCS_REENT (0x0100)
286
287 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
288 loaded byte-at-a-time. */
289 #define ARM_FLAG_SHORT_BYTE (0x0200)
290
291 /* Nonzero if all floating point instructions are missing (and there is no
292 emulator either). Generate function calls for all ops in this case. */
293 #define ARM_FLAG_SOFT_FLOAT (0x0400)
294
295 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
296 #define ARM_FLAG_BIG_END (0x0800)
297
298 /* Nonzero if we should compile for Thumb interworking. */
299 #define ARM_FLAG_THUMB (0x1000)
300
301 /* Nonzero if we should have little-endian words even when compiling for
302 big-endian (for backwards compatibility with older versions of GCC). */
303 #define ARM_FLAG_LITTLE_WORDS (0x2000)
304
305 /* Nonzero if we need to protect the prolog from scheduling */
306 #define ARM_FLAG_NO_SCHED_PRO (0x4000)
307
308 /* Nonzero if a call to abort should be generated if a noreturn
309 function tries to return. */
310 #define ARM_FLAG_ABORT_NORETURN (0x8000)
311
312 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
313 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
314 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
315 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
316 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
317 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
318 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
319 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
320 that short values sould not be accessed using word load instructions
321 as there is a possibility that they may not be word aligned and this
322 would generate an MMU fault. On processors which do not have a 16 bit
323 load instruction therefore, short values must be loaded by individual
324 byte accesses rather than loading a word and then shifting the desired
325 value into place. */
326 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
327 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
328 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
329 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
330 #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB)
331 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
332 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
333 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
334
335 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
336 Bit 31 is reserved. See riscix.h. */
337 #ifndef SUBTARGET_SWITCHES
338 #define SUBTARGET_SWITCHES
339 #endif
340
341 #define TARGET_SWITCHES \
342 { \
343 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
344 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
345 "Generate APCS conformant stack frames" }, \
346 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
347 {"poke-function-name", ARM_FLAG_POKE, \
348 "Store function names in object code" }, \
349 {"fpe", ARM_FLAG_FPE, "" }, \
350 {"apcs-32", ARM_FLAG_APCS_32, \
351 "Use the 32bit version of the APCS" }, \
352 {"apcs-26", -ARM_FLAG_APCS_32, \
353 "Use the 26bit version of the APCS" }, \
354 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
355 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
356 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
357 "Pass FP arguments in FP registers" }, \
358 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
359 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
360 "Generate re-entrant, PIC code" }, \
361 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
362 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
363 "Load shorts a byte at a time" }, \
364 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
365 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
366 "Load words a byte at a time" }, \
367 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
368 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
369 "Use library calls to perform FP operations" }, \
370 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
371 "Use hardware floating point instructions" }, \
372 {"big-endian", ARM_FLAG_BIG_END, \
373 "Assume target CPU is configured as big endian" }, \
374 {"little-endian", -ARM_FLAG_BIG_END, \
375 "Assume target CPU is configured as little endian" }, \
376 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
377 "Assume big endian bytes, little endian words" }, \
378 {"thumb-interwork", ARM_FLAG_THUMB, \
379 "Support calls between THUMB and ARM instructions sets" }, \
380 {"no-thumb-interwork", -ARM_FLAG_THUMB, "" }, \
381 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
382 "Generate a call to abort if a noreturn function returns"}, \
383 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
384 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
385 "Do not move instructions into a function's prologue" }, \
386 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
387 SUBTARGET_SWITCHES \
388 {"", TARGET_DEFAULT } \
389 }
390
391 #define TARGET_OPTIONS \
392 { \
393 {"cpu=", & arm_select[0].string, \
394 "Specify the name of the target CPU" }, \
395 {"arch=", & arm_select[1].string, \
396 "Specify the name of the target architecture" }, \
397 {"tune=", & arm_select[2].string, "" }, \
398 {"fpe=", & target_fp_name, "" }, \
399 {"fp=", & target_fp_name, \
400 "Specify the version of the floating point emulator" }, \
401 { "structure-size-boundary=", & structure_size_string, \
402 "Specify the minumum bit alignment of structures" } \
403 }
404
405 struct arm_cpu_select
406 {
407 char * string;
408 char * name;
409 struct processors * processors;
410 };
411
412 /* This is a magic array. If the user specifies a command line switch
413 which matches one of the entries in TARGET_OPTIONS then the corresponding
414 string pointer will be set to the value specified by the user. */
415 extern struct arm_cpu_select arm_select[];
416
417 enum prog_mode_type
418 {
419 prog_mode26,
420 prog_mode32
421 };
422
423 /* Recast the program mode class to be the prog_mode attribute */
424 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
425
426 extern enum prog_mode_type arm_prgmode;
427
428 /* What sort of floating point unit do we have? Hardware or software.
429 If software, is it issue 2 or issue 3? */
430 enum floating_point_type
431 {
432 FP_HARD,
433 FP_SOFT2,
434 FP_SOFT3
435 };
436
437 /* Recast the floating point class to be the floating point attribute. */
438 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
439
440 /* What type of floating point to tune for */
441 extern enum floating_point_type arm_fpu;
442
443 /* What type of floating point instructions are available */
444 extern enum floating_point_type arm_fpu_arch;
445
446 /* Default floating point architecture. Override in sub-target if
447 necessary. */
448 #define FP_DEFAULT FP_SOFT2
449
450 /* Nonzero if the processor has a fast multiply insn, and one that does
451 a 64-bit multiply of two 32-bit values. */
452 extern int arm_fast_multiply;
453
454 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
455 extern int arm_arch4;
456
457 /* Nonzero if this chip can benefit from load scheduling. */
458 extern int arm_ld_sched;
459
460 /* Nonzero if this chip is a StrongARM. */
461 extern int arm_is_strong;
462
463 /* Nonzero if this chip is a an ARM6 or an ARM7. */
464 extern int arm_is_6_or_7;
465
466 #ifndef TARGET_DEFAULT
467 #define TARGET_DEFAULT 0
468 #endif
469
470 /* The frame pointer register used in gcc has nothing to do with debugging;
471 that is controlled by the APCS-FRAME option. */
472 /* Not fully implemented yet */
473 /* #define CAN_DEBUG_WITHOUT_FP 1 */
474
475 #define TARGET_MEM_FUNCTIONS 1
476
477 #define OVERRIDE_OPTIONS arm_override_options ()
478 \f
479 /* Target machine storage Layout. */
480
481
482 /* Define this macro if it is advisable to hold scalars in registers
483 in a wider mode than that declared by the program. In such cases,
484 the value is constrained to be within the bounds of the declared
485 type, but kept valid in the wider mode. The signedness of the
486 extension may differ from that of the type. */
487
488 /* It is far faster to zero extend chars than to sign extend them */
489
490 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
491 if (GET_MODE_CLASS (MODE) == MODE_INT \
492 && GET_MODE_SIZE (MODE) < 4) \
493 { \
494 if (MODE == QImode) \
495 UNSIGNEDP = 1; \
496 else if (MODE == HImode) \
497 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
498 (MODE) = SImode; \
499 }
500
501 /* Define this macro if the promotion described by `PROMOTE_MODE'
502 should also be done for outgoing function arguments. */
503 /* This is required to ensure that push insns always push a word. */
504 #define PROMOTE_FUNCTION_ARGS
505
506 /* Define for XFmode extended real floating point support.
507 This will automatically cause REAL_ARITHMETIC to be defined. */
508 /* For the ARM:
509 I think I have added all the code to make this work. Unfortunately,
510 early releases of the floating point emulation code on RISCiX used a
511 different format for extended precision numbers. On my RISCiX box there
512 is a bug somewhere which causes the machine to lock up when running enquire
513 with long doubles. There is the additional aspect that Norcroft C
514 treats long doubles as doubles and we ought to remain compatible.
515 Perhaps someone with an FPA coprocessor and not running RISCiX would like
516 to try this someday. */
517 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
518
519 /* Disable XFmode patterns in md file */
520 #define ENABLE_XF_PATTERNS 0
521
522 /* Define if you don't want extended real, but do want to use the
523 software floating point emulator for REAL_ARITHMETIC and
524 decimal <-> binary conversion. */
525 /* See comment above */
526 #define REAL_ARITHMETIC
527
528 /* Define this if most significant bit is lowest numbered
529 in instructions that operate on numbered bit-fields. */
530 #define BITS_BIG_ENDIAN 0
531
532 /* Define this if most significant byte of a word is the lowest numbered.
533 Most ARM processors are run in little endian mode, so that is the default.
534 If you want to have it run-time selectable, change the definition in a
535 cover file to be TARGET_BIG_ENDIAN. */
536 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
537
538 /* Define this if most significant word of a multiword number is the lowest
539 numbered.
540 This is always false, even when in big-endian mode. */
541 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
542
543 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
544 on processor pre-defineds when compiling libgcc2.c. */
545 #if defined(__ARMEB__) && !defined(__ARMWEL__)
546 #define LIBGCC2_WORDS_BIG_ENDIAN 1
547 #else
548 #define LIBGCC2_WORDS_BIG_ENDIAN 0
549 #endif
550
551 /* Define this if most significant word of doubles is the lowest numbered.
552 This is always true, even when in little-endian mode. */
553 #define FLOAT_WORDS_BIG_ENDIAN 1
554
555 /* Number of bits in an addressable storage unit */
556 #define BITS_PER_UNIT 8
557
558 #define BITS_PER_WORD 32
559
560 #define UNITS_PER_WORD 4
561
562 #define POINTER_SIZE 32
563
564 #define PARM_BOUNDARY 32
565
566 #define STACK_BOUNDARY 32
567
568 #define FUNCTION_BOUNDARY 32
569
570 #define EMPTY_FIELD_BOUNDARY 32
571
572 #define BIGGEST_ALIGNMENT 32
573
574 /* Make strings word-aligned so strcpy from constants will be faster. */
575 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
576 (TREE_CODE (EXP) == STRING_CST \
577 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
578
579 /* Every structures size must be a multiple of 32 bits. */
580 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
581 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
582 boundaries". */
583 #ifndef STRUCTURE_SIZE_BOUNDARY
584 #define STRUCTURE_SIZE_BOUNDARY 32
585 #endif
586
587 /* Used when parsing command line option -mstructure_size_boundary. */
588 extern char * structure_size_string;
589
590 /* Non-zero if move instructions will actually fail to work
591 when given unaligned data. */
592 #define STRICT_ALIGNMENT 1
593
594 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
595
596 \f
597 /* Standard register usage. */
598
599 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
600 (S - saved over call).
601
602 r0 * argument word/integer result
603 r1-r3 argument word
604
605 r4-r8 S register variable
606 r9 S (rfp) register variable (real frame pointer)
607
608 r10 F S (sl) stack limit (used by -mapcs-stack-check)
609 r11 F S (fp) argument pointer
610 r12 (ip) temp workspace
611 r13 F S (sp) lower end of current stack frame
612 r14 (lr) link address/workspace
613 r15 F (pc) program counter
614
615 f0 floating point result
616 f1-f3 floating point scratch
617
618 f4-f7 S floating point variable
619
620 cc This is NOT a real register, but is used internally
621 to represent things that use or set the condition
622 codes.
623 sfp This isn't either. It is used during rtl generation
624 since the offset between the frame pointer and the
625 auto's isn't known until after register allocation.
626 afp Nor this, we only need this because of non-local
627 goto. Without it fp appears to be used and the
628 elimination code won't get rid of sfp. It tracks
629 fp exactly at all times.
630
631 *: See CONDITIONAL_REGISTER_USAGE */
632
633 /* The stack backtrace structure is as follows:
634 fp points to here: | save code pointer | [fp]
635 | return link value | [fp, #-4]
636 | return sp value | [fp, #-8]
637 | return fp value | [fp, #-12]
638 [| saved r10 value |]
639 [| saved r9 value |]
640 [| saved r8 value |]
641 [| saved r7 value |]
642 [| saved r6 value |]
643 [| saved r5 value |]
644 [| saved r4 value |]
645 [| saved r3 value |]
646 [| saved r2 value |]
647 [| saved r1 value |]
648 [| saved r0 value |]
649 [| saved f7 value |] three words
650 [| saved f6 value |] three words
651 [| saved f5 value |] three words
652 [| saved f4 value |] three words
653 r0-r3 are not normally saved in a C function. */
654
655 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
656 #define FIRST_PSEUDO_REGISTER 27
657
658 /* 1 for registers that have pervasive standard uses
659 and are not available for the register allocator. */
660 #define FIXED_REGISTERS \
661 { \
662 0,0,0,0,0,0,0,0, \
663 0,0,0,1,0,1,0,1, \
664 0,0,0,0,0,0,0,0, \
665 1,1,1 \
666 }
667
668 /* 1 for registers not available across function calls.
669 These must include the FIXED_REGISTERS and also any
670 registers that can be used without being saved.
671 The latter must include the registers where values are returned
672 and the register where structure-value addresses are passed.
673 Aside from that, you can include as many other registers as you like.
674 The CC is not preserved over function calls on the ARM 6, so it is
675 easier to assume this for all. SFP is preserved, since FP is. */
676 #define CALL_USED_REGISTERS \
677 { \
678 1,1,1,1,0,0,0,0, \
679 0,0,0,1,1,1,1,1, \
680 1,1,1,1,0,0,0,0, \
681 1,1,1 \
682 }
683
684 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
685 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
686 #endif
687
688 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
689 trampled. This effectively reduces the number of available registers by 1.
690 XXX It is a hack, I know.
691 XXX Is this still needed? */
692 #define CONDITIONAL_REGISTER_USAGE \
693 { \
694 if (obey_regdecls) \
695 fixed_regs[0] = 1; \
696 if (TARGET_SOFT_FLOAT) \
697 { \
698 int regno; \
699 for (regno = 16; regno < 24; ++regno) \
700 fixed_regs[regno] = call_used_regs[regno] = 1; \
701 } \
702 if (flag_pic) \
703 { \
704 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
705 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
706 } \
707 else if (TARGET_APCS_STACK) \
708 { \
709 fixed_regs[10] = 1; \
710 call_used_regs[10] = 1; \
711 } \
712 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
713 }
714
715 /* Return number of consecutive hard regs needed starting at reg REGNO
716 to hold something of mode MODE.
717 This is ordinarily the length in words of a value of mode MODE
718 but can be less for certain modes in special long registers.
719
720 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
721 mode. */
722 #define HARD_REGNO_NREGS(REGNO, MODE) \
723 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
724 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
725 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
726
727 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
728 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
729 regs holding FP. */
730 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
731 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
732 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
733 || REGNO == ARG_POINTER_REGNUM \
734 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
735
736 /* Value is 1 if it is a good idea to tie two pseudo registers
737 when one has mode MODE1 and one has mode MODE2.
738 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
739 for any hard reg, then this must be 0 for correct output. */
740 #define MODES_TIEABLE_P(MODE1, MODE2) \
741 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
742
743 /* Specify the registers used for certain standard purposes.
744 The values of these macros are register numbers. */
745
746 /* Define this if the program counter is overloaded on a register. */
747 #define PC_REGNUM 15
748
749 /* Register to use for pushing function arguments. */
750 #define STACK_POINTER_REGNUM 13
751
752 /* Base register for access to local variables of the function. */
753 #define FRAME_POINTER_REGNUM 25
754
755 /* Define this to be where the real frame pointer is if it is not possible to
756 work out the offset between the frame pointer and the automatic variables
757 until after register allocation has taken place. FRAME_POINTER_REGNUM
758 should point to a special register that we will make sure is eliminated. */
759 #define HARD_FRAME_POINTER_REGNUM 11
760
761 /* Value should be nonzero if functions must have frame pointers.
762 Zero means the frame pointer need not be set up (and parms may be accessed
763 via the stack pointer) in functions that seem suitable.
764 If we have to have a frame pointer we might as well make use of it.
765 APCS says that the frame pointer does not need to be pushed in leaf
766 functions, or simple tail call functions. */
767 #define FRAME_POINTER_REQUIRED \
768 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
769
770 /* Base register for access to arguments of the function. */
771 #define ARG_POINTER_REGNUM 26
772
773 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
774 as an invisible last argument (possible since varargs don't exist in
775 Pascal), so the following is not true. */
776 #define STATIC_CHAIN_REGNUM 8
777
778 /* Register in which address to store a structure value
779 is passed to a function. */
780 #define STRUCT_VALUE_REGNUM 0
781
782 /* Internal, so that we don't need to refer to a raw number */
783 #define CC_REGNUM 24
784
785 /* The order in which register should be allocated. It is good to use ip
786 since no saving is required (though calls clobber it) and it never contains
787 function parameters. It is quite good to use lr since other calls may
788 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
789 least likely to contain a function parameter; in addition results are
790 returned in r0.
791 */
792 #define REG_ALLOC_ORDER \
793 { \
794 3, 2, 1, 0, 12, 14, 4, 5, \
795 6, 7, 8, 10, 9, 11, 13, 15, \
796 16, 17, 18, 19, 20, 21, 22, 23, \
797 24, 25, 26 \
798 }
799 \f
800 /* Register and constant classes. */
801
802 /* Register classes: all ARM regs or all FPU regs---simple! */
803 enum reg_class
804 {
805 NO_REGS,
806 FPU_REGS,
807 GENERAL_REGS,
808 ALL_REGS,
809 LIM_REG_CLASSES
810 };
811
812 #define N_REG_CLASSES (int) LIM_REG_CLASSES
813
814 /* Give names of register classes as strings for dump file. */
815 #define REG_CLASS_NAMES \
816 { \
817 "NO_REGS", \
818 "FPU_REGS", \
819 "GENERAL_REGS", \
820 "ALL_REGS", \
821 }
822
823 /* Define which registers fit in which classes.
824 This is an initializer for a vector of HARD_REG_SET
825 of length N_REG_CLASSES. */
826 #define REG_CLASS_CONTENTS \
827 { \
828 0x0000000, /* NO_REGS */ \
829 0x0FF0000, /* FPU_REGS */ \
830 0x200FFFF, /* GENERAL_REGS */ \
831 0x2FFFFFF /* ALL_REGS */ \
832 }
833
834 /* The same information, inverted:
835 Return the class number of the smallest class containing
836 reg number REGNO. This could be a conditional expression
837 or could index an array. */
838 #define REGNO_REG_CLASS(REGNO) \
839 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
840 || REGNO == ARG_POINTER_REGNUM) \
841 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
842 ? NO_REGS : FPU_REGS)
843
844 /* The class value for index registers, and the one for base regs. */
845 #define INDEX_REG_CLASS GENERAL_REGS
846 #define BASE_REG_CLASS GENERAL_REGS
847
848 /* Get reg_class from a letter such as appears in the machine description.
849 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
850 #define REG_CLASS_FROM_LETTER(C) \
851 ((C)=='f' ? FPU_REGS : NO_REGS)
852
853 /* The letters I, J, K, L and M in a register constraint string
854 can be used to stand for particular ranges of immediate operands.
855 This macro defines what the ranges are.
856 C is the letter, and VALUE is a constant value.
857 Return 1 if VALUE is in the range specified by C.
858 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
859 J: valid indexing constants.
860 K: ~value ok in rhs argument of data operand.
861 L: -value ok in rhs argument of data operand.
862 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
863 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
864 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
865 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
866 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
867 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
868 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
869 || (((VALUE) & ((VALUE) - 1)) == 0)) \
870 : 0)
871
872 /* For the ARM, `Q' means that this is a memory operand that is just
873 an offset from a register.
874 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
875 address. This means that the symbol is in the text segment and can be
876 accessed without using a load. */
877
878 #define EXTRA_CONSTRAINT(OP, C) \
879 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
880 : (C) == 'R' ? (GET_CODE (OP) == MEM \
881 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
882 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
883 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
884 : 0)
885
886 /* Constant letter 'G' for the FPU immediate constants.
887 'H' means the same constant negated. */
888 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
889 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
890 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
891
892 /* Given an rtx X being reloaded into a reg required to be
893 in class CLASS, return the class of reg to actually use.
894 In general this is just CLASS; but on some machines
895 in some cases it is preferable to use a more restrictive class. */
896 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
897
898 /* Return the register class of a scratch register needed to copy IN into
899 or out of a register in CLASS in MODE. If it can be done directly,
900 NO_REGS is returned. */
901 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
902 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
903 ? GENERAL_REGS : NO_REGS)
904
905 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
906 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
907 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
908 && (GET_CODE (X) == MEM \
909 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
910 && true_regnum (X) == -1))) \
911 ? GENERAL_REGS : NO_REGS)
912
913 /* Try a machine-dependent way of reloading an illegitimate address
914 operand. If we find one, push the reload and jump to WIN. This
915 macro is used in only one place: `find_reloads_address' in reload.c.
916
917 For the ARM, we wish to handle large displacements off a base
918 register by splitting the addend across a MOV and the mem insn.
919 This can cut the number of reloads needed. */
920 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
921 do { \
922 if (GET_CODE (X) == PLUS \
923 && GET_CODE (XEXP (X, 0)) == REG \
924 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
925 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
926 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
927 { \
928 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
929 HOST_WIDE_INT low, high; \
930 \
931 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
932 low = ((val & 0xf) ^ 0x8) - 0x8; \
933 else if (MODE == SImode || MODE == QImode \
934 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
935 || (MODE == HImode && ! arm_arch4)) \
936 /* Need to be careful, -4096 is not a valid offset */ \
937 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
938 else if (MODE == HImode && arm_arch4) \
939 /* Need to be careful, -256 is not a valid offset */ \
940 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
941 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
942 && TARGET_HARD_FLOAT) \
943 /* Need to be careful, -1024 is not a valid offset */ \
944 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
945 else \
946 break; \
947 \
948 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
949 /* Check for overflow or zero */ \
950 if (low == 0 || high == 0 || (high + low != val)) \
951 break; \
952 \
953 /* Reload the high part into a base reg; leave the low part \
954 in the mem. */ \
955 X = gen_rtx_PLUS (GET_MODE (X), \
956 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
957 GEN_INT (high)), \
958 GEN_INT (low)); \
959 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
960 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
961 OPNUM, TYPE); \
962 goto WIN; \
963 } \
964 } while (0)
965
966 /* Return the maximum number of consecutive registers
967 needed to represent mode MODE in a register of class CLASS.
968 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
969 #define CLASS_MAX_NREGS(CLASS, MODE) \
970 ((CLASS) == FPU_REGS ? 1 \
971 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
972
973 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
974 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
975 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
976 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
977 ? 20 : 2)
978 \f
979 /* Stack layout; function entry, exit and calling. */
980
981 /* Define this if pushing a word on the stack
982 makes the stack pointer a smaller address. */
983 #define STACK_GROWS_DOWNWARD 1
984
985 /* Define this if the nominal address of the stack frame
986 is at the high-address end of the local variables;
987 that is, each additional local variable allocated
988 goes at a more negative offset in the frame. */
989 #define FRAME_GROWS_DOWNWARD 1
990
991 /* Offset within stack frame to start allocating local variables at.
992 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
993 first local allocated. Otherwise, it is the offset to the BEGINNING
994 of the first local allocated. */
995 #define STARTING_FRAME_OFFSET 0
996
997 /* If we generate an insn to push BYTES bytes,
998 this says how many the stack pointer really advances by. */
999 /* The push insns do not do this rounding implicitly. So don't define this. */
1000 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1001
1002 /* Define this if the maximum size of all the outgoing args is to be
1003 accumulated and pushed during the prologue. The amount can be
1004 found in the variable current_function_outgoing_args_size. */
1005 #define ACCUMULATE_OUTGOING_ARGS
1006
1007 /* Offset of first parameter from the argument pointer register value. */
1008 #define FIRST_PARM_OFFSET(FNDECL) 4
1009
1010 /* Value is the number of byte of arguments automatically
1011 popped when returning from a subroutine call.
1012 FUNDECL is the declaration node of the function (as a tree),
1013 FUNTYPE is the data type of the function (as a tree),
1014 or for a library call it is an identifier node for the subroutine name.
1015 SIZE is the number of bytes of arguments passed on the stack.
1016
1017 On the ARM, the caller does not pop any of its arguments that were passed
1018 on the stack. */
1019 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1020
1021 /* Define how to find the value returned by a function.
1022 VALTYPE is the data type of the value (as a tree).
1023 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1024 otherwise, FUNC is 0. */
1025 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1026 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \
1027 ? gen_rtx_REG (TYPE_MODE (VALTYPE), 16) \
1028 : gen_rtx_REG (TYPE_MODE (VALTYPE), 0))
1029
1030 /* Define how to find the value returned by a library function
1031 assuming the value has mode MODE. */
1032 #define LIBCALL_VALUE(MODE) \
1033 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1034 ? gen_rtx_REG (MODE, 16) \
1035 : gen_rtx_REG (MODE, 0))
1036
1037 /* 1 if N is a possible register number for a function value.
1038 On the ARM, only r0 and f0 can return results. */
1039 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1040 ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT)
1041
1042 /* How large values are returned */
1043 /* A C expression which can inhibit the returning of certain function values
1044 in registers, based on the type of value. */
1045 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1046
1047 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1048 values must be in memory. On the ARM, they need only do so if larger
1049 than a word, or if they contain elements offset from zero in the struct. */
1050 #define DEFAULT_PCC_STRUCT_RETURN 0
1051
1052 /* Define where to put the arguments to a function.
1053 Value is zero to push the argument on the stack,
1054 or a hard register in which to store the argument.
1055
1056 MODE is the argument's machine mode.
1057 TYPE is the data type of the argument (as a tree).
1058 This is null for libcalls where that information may
1059 not be available.
1060 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1061 the preceding args and about the function being called.
1062 NAMED is nonzero if this argument is a named parameter
1063 (otherwise it is an extra parameter matching an ellipsis).
1064
1065 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1066 other arguments are passed on the stack. If (NAMED == 0) (which happens
1067 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1068 passed in the stack (function_prologue will indeed make it pass in the
1069 stack if necessary). */
1070 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1071 ((NAMED) \
1072 ? ((CUM) >= 16 ? 0 : gen_rtx_REG (MODE, (CUM) / 4)) \
1073 : 0)
1074
1075 /* For an arg passed partly in registers and partly in memory,
1076 this is the number of registers used.
1077 For args passed entirely in registers or entirely in memory, zero. */
1078 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1079 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
1080 ? GET_MODE_SIZE (MODE) \
1081 : int_size_in_bytes (TYPE)) \
1082 ? 4 - (CUM) / 4 : 0)
1083
1084 /* A C type for declaring a variable that is used as the first argument of
1085 `FUNCTION_ARG' and other related values. For some target machines, the
1086 type `int' suffices and can hold the number of bytes of argument so far.
1087
1088 On the ARM, this is the number of bytes of arguments scanned so far. */
1089 #define CUMULATIVE_ARGS int
1090
1091 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1092 for a call to a function whose data type is FNTYPE.
1093 For a library call, FNTYPE is 0.
1094 On the ARM, the offset starts at 0. */
1095 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1096 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
1097
1098 /* Update the data in CUM to advance over an argument
1099 of mode MODE and data type TYPE.
1100 (TYPE is null for libcalls where that information may not be available.) */
1101 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1102 (CUM) += ((MODE) != BLKmode \
1103 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
1104 : (int_size_in_bytes (TYPE) + 3) & ~3) \
1105
1106 /* 1 if N is a possible register number for function argument passing.
1107 On the ARM, r0-r3 are used to pass args. */
1108 #define FUNCTION_ARG_REGNO_P(REGNO) \
1109 ((REGNO) >= 0 && (REGNO) <= 3)
1110
1111 /* Perform any actions needed for a function that is receiving a variable
1112 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1113 of the current parameter. PRETEND_SIZE is a variable that should be set to
1114 the amount of stack that must be pushed by the prolog to pretend that our
1115 caller pushed it.
1116
1117 Normally, this macro will push all remaining incoming registers on the
1118 stack and set PRETEND_SIZE to the length of the registers pushed.
1119
1120 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1121 named arg and all anonymous args onto the stack.
1122 XXX I know the prologue shouldn't be pushing registers, but it is faster
1123 that way. */
1124 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1125 { \
1126 extern int current_function_anonymous_args; \
1127 current_function_anonymous_args = 1; \
1128 if ((CUM) < 16) \
1129 (PRETEND_SIZE) = 16 - (CUM); \
1130 }
1131
1132 /* Generate assembly output for the start of a function. */
1133 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1134 output_func_prologue ((STREAM), (SIZE))
1135
1136 /* Call the function profiler with a given profile label. The Acorn compiler
1137 puts this BEFORE the prolog but gcc puts it afterwards. The ``mov ip,lr''
1138 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
1139 to mind about this! */
1140 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1141 { \
1142 fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \
1143 fprintf(STREAM, "\tbl\tmcount\n"); \
1144 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
1145 }
1146
1147 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1148 the stack pointer does not matter. The value is tested only in
1149 functions that have frame pointers.
1150 No definition is equivalent to always zero.
1151
1152 On the ARM, the function epilogue recovers the stack pointer from the
1153 frame. */
1154 #define EXIT_IGNORE_STACK 1
1155
1156 /* Generate the assembly code for function exit. */
1157 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1158 output_func_epilogue ((STREAM), (SIZE))
1159
1160 /* Determine if the epilogue should be output as RTL.
1161 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1162 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1163
1164 /* Definitions for register eliminations.
1165
1166 This is an array of structures. Each structure initializes one pair
1167 of eliminable registers. The "from" register number is given first,
1168 followed by "to". Eliminations of the same "from" register are listed
1169 in order of preference.
1170
1171 We have two registers that can be eliminated on the ARM. First, the
1172 arg pointer register can often be eliminated in favor of the stack
1173 pointer register. Secondly, the pseudo frame pointer register can always
1174 be eliminated; it is replaced with either the stack or the real frame
1175 pointer. */
1176
1177 #define ELIMINABLE_REGS \
1178 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1179 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1180 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1181 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
1182
1183 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1184 Frame pointer elimination is automatically handled.
1185
1186 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1187 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1188 pointer, we must eliminate FRAME_POINTER_REGNUM into
1189 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1190 #define CAN_ELIMINATE(FROM, TO) \
1191 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1192
1193 /* Define the offset between two registers, one to be eliminated, and the other
1194 its replacement, at the start of a routine. */
1195 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1196 { \
1197 int volatile_func = arm_volatile_func (); \
1198 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1199 (OFFSET) = 0; \
1200 else if ((FROM) == FRAME_POINTER_REGNUM \
1201 && (TO) == STACK_POINTER_REGNUM) \
1202 (OFFSET) = (current_function_outgoing_args_size \
1203 + (get_frame_size () + 3 & ~3)); \
1204 else \
1205 { \
1206 int regno; \
1207 int offset = 12; \
1208 int saved_hard_reg = 0; \
1209 \
1210 if (! volatile_func) \
1211 { \
1212 for (regno = 0; regno <= 10; regno++) \
1213 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1214 saved_hard_reg = 1, offset += 4; \
1215 for (regno = 16; regno <=23; regno++) \
1216 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1217 offset += 12; \
1218 } \
1219 if ((FROM) == FRAME_POINTER_REGNUM) \
1220 (OFFSET) = -offset; \
1221 else \
1222 { \
1223 if (! frame_pointer_needed) \
1224 offset -= 16; \
1225 if (! volatile_func \
1226 && (regs_ever_live[14] || saved_hard_reg)) \
1227 offset += 4; \
1228 offset += current_function_outgoing_args_size; \
1229 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
1230 } \
1231 } \
1232 }
1233
1234 /* Output assembler code for a block containing the constant parts
1235 of a trampoline, leaving space for the variable parts.
1236
1237 On the ARM, (if r8 is the static chain regnum, and remembering that
1238 referencing pc adds an offset of 8) the trampoline looks like:
1239 ldr r8, [pc, #0]
1240 ldr pc, [pc]
1241 .word static chain value
1242 .word function's address
1243 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1244 #define TRAMPOLINE_TEMPLATE(FILE) \
1245 { \
1246 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \
1247 REGISTER_PREFIX, REGISTER_PREFIX); \
1248 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \
1249 REGISTER_PREFIX, REGISTER_PREFIX); \
1250 fprintf ((FILE), "\t.word\t0\n"); \
1251 fprintf ((FILE), "\t.word\t0\n"); \
1252 }
1253
1254 /* Length in units of the trampoline for entering a nested function. */
1255 #define TRAMPOLINE_SIZE 16
1256
1257 /* Alignment required for a trampoline in units. */
1258 #define TRAMPOLINE_ALIGN 4
1259
1260 /* Emit RTL insns to initialize the variable parts of a trampoline.
1261 FNADDR is an RTX for the address of the function's pure code.
1262 CXT is an RTX for the static chain value for the function. */
1263 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1264 { \
1265 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1266 (CXT)); \
1267 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1268 (FNADDR)); \
1269 }
1270
1271 \f
1272 /* Addressing modes, and classification of registers for them. */
1273
1274 #define HAVE_POST_INCREMENT 1
1275 #define HAVE_PRE_INCREMENT 1
1276 #define HAVE_POST_DECREMENT 1
1277 #define HAVE_PRE_DECREMENT 1
1278
1279 /* Macros to check register numbers against specific register classes. */
1280
1281 /* These assume that REGNO is a hard or pseudo reg number.
1282 They give nonzero only if REGNO is a hard reg of the suitable class
1283 or a pseudo reg currently allocated to a suitable hard reg.
1284 Since they use reg_renumber, they are safe only once reg_renumber
1285 has been allocated, which happens in local-alloc.c.
1286
1287 On the ARM, don't allow the pc to be used. */
1288 #define REGNO_OK_FOR_BASE_P(REGNO) \
1289 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1290 || (REGNO) == ARG_POINTER_REGNUM \
1291 || (unsigned) reg_renumber[(REGNO)] < 15 \
1292 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1293 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1294 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1295 REGNO_OK_FOR_BASE_P(REGNO)
1296
1297 /* Maximum number of registers that can appear in a valid memory address.
1298 Shifts in addresses can't be by a register. */
1299
1300 #define MAX_REGS_PER_ADDRESS 2
1301
1302 /* Recognize any constant value that is a valid address. */
1303 /* XXX We can address any constant, eventually... */
1304
1305 #ifdef AOF_ASSEMBLER
1306
1307 #define CONSTANT_ADDRESS_P(X) \
1308 (GET_CODE (X) == SYMBOL_REF \
1309 && CONSTANT_POOL_ADDRESS_P (X))
1310
1311 #else
1312
1313 #define CONSTANT_ADDRESS_P(X) \
1314 (GET_CODE (X) == SYMBOL_REF \
1315 && (CONSTANT_POOL_ADDRESS_P (X) \
1316 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1317
1318 #endif /* AOF_ASSEMBLER */
1319
1320 /* Nonzero if the constant value X is a legitimate general operand.
1321 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1322
1323 On the ARM, allow any integer (invalid ones are removed later by insn
1324 patterns), nice doubles and symbol_refs which refer to the function's
1325 constant pool XXX. */
1326 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1327
1328 /* Symbols in the text segment can be accessed without indirecting via the
1329 constant pool; it may take an extra binary operation, but this is still
1330 faster than indirecting via memory. Don't do this when not optimizing,
1331 since we won't be calculating al of the offsets necessary to do this
1332 simplification. */
1333 /* This doesn't work with AOF syntax, since the string table may be in
1334 a different AREA. */
1335 #ifndef AOF_ASSEMBLER
1336 #define ENCODE_SECTION_INFO(decl) \
1337 { \
1338 if (optimize > 0 && TREE_CONSTANT (decl) \
1339 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1340 { \
1341 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1342 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1343 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1344 } \
1345 }
1346 #endif
1347
1348 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1349 and check its validity for a certain class.
1350 We have two alternate definitions for each of them.
1351 The usual definition accepts all pseudo regs; the other rejects
1352 them unless they have been allocated suitable hard regs.
1353 The symbol REG_OK_STRICT causes the latter definition to be used. */
1354 #ifndef REG_OK_STRICT
1355
1356 /* Nonzero if X is a hard reg that can be used as a base reg
1357 or if it is a pseudo reg. */
1358 #define REG_OK_FOR_BASE_P(X) \
1359 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1360 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1361
1362 /* Nonzero if X is a hard reg that can be used as an index
1363 or if it is a pseudo reg. */
1364 #define REG_OK_FOR_INDEX_P(X) \
1365 REG_OK_FOR_BASE_P(X)
1366
1367 #define REG_OK_FOR_PRE_POST_P(X) \
1368 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1369 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1370
1371 #else
1372
1373 /* Nonzero if X is a hard reg that can be used as a base reg. */
1374 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1375
1376 /* Nonzero if X is a hard reg that can be used as an index. */
1377 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1378
1379 #define REG_OK_FOR_PRE_POST_P(X) \
1380 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1381 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1382 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1383 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1384
1385 #endif
1386 \f
1387 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1388 that is a valid memory address for an instruction.
1389 The MODE argument is the machine mode for the MEM expression
1390 that wants to use this address.
1391
1392 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1393 #define BASE_REGISTER_RTX_P(X) \
1394 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1395
1396 #define INDEX_REGISTER_RTX_P(X) \
1397 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1398
1399 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1400 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1401 only be small constants. */
1402 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1403 do \
1404 { \
1405 HOST_WIDE_INT range; \
1406 enum rtx_code code = GET_CODE (INDEX); \
1407 \
1408 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1409 { \
1410 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1411 && INTVAL (INDEX) > -1024 \
1412 && (INTVAL (INDEX) & 3) == 0) \
1413 goto LABEL; \
1414 } \
1415 else \
1416 { \
1417 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1418 goto LABEL; \
1419 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1420 && (! arm_arch4 || (MODE) != HImode)) \
1421 { \
1422 rtx xiop0 = XEXP (INDEX, 0); \
1423 rtx xiop1 = XEXP (INDEX, 1); \
1424 if (INDEX_REGISTER_RTX_P (xiop0) \
1425 && power_of_two_operand (xiop1, SImode)) \
1426 goto LABEL; \
1427 if (INDEX_REGISTER_RTX_P (xiop1) \
1428 && power_of_two_operand (xiop0, SImode)) \
1429 goto LABEL; \
1430 } \
1431 if (GET_MODE_SIZE (MODE) <= 4 \
1432 && (code == LSHIFTRT || code == ASHIFTRT \
1433 || code == ASHIFT || code == ROTATERT) \
1434 && (! arm_arch4 || (MODE) != HImode)) \
1435 { \
1436 rtx op = XEXP (INDEX, 1); \
1437 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1438 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1439 && INTVAL (op) <= 31) \
1440 goto LABEL; \
1441 } \
1442 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1443 range = ((MODE) == HImode || (MODE) == QImode) \
1444 ? (arm_arch4 ? 256 : 4095) : 4096; \
1445 if (code == CONST_INT && INTVAL (INDEX) < range \
1446 && INTVAL (INDEX) > -range) \
1447 goto LABEL; \
1448 } \
1449 } while (0)
1450
1451 /* Jump to LABEL if X is a valid address RTX. This must also take
1452 REG_OK_STRICT into account when deciding about valid registers, but it uses
1453 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1454 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1455 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1456 refs must be forced though a static cell to ensure addressability. */
1457 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1458 { \
1459 if (BASE_REGISTER_RTX_P (X)) \
1460 goto LABEL; \
1461 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1462 && GET_CODE (XEXP (X, 0)) == REG \
1463 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1464 goto LABEL; \
1465 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1466 && (GET_CODE (X) == LABEL_REF \
1467 || (GET_CODE (X) == CONST \
1468 && GET_CODE (XEXP ((X), 0)) == PLUS \
1469 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1470 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1471 goto LABEL; \
1472 else if ((MODE) == TImode) \
1473 ; \
1474 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1475 { \
1476 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1477 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1478 { \
1479 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1480 if (val == 4 || val == -4 || val == -8) \
1481 goto LABEL; \
1482 } \
1483 } \
1484 else if (GET_CODE (X) == PLUS) \
1485 { \
1486 rtx xop0 = XEXP(X,0); \
1487 rtx xop1 = XEXP(X,1); \
1488 \
1489 if (BASE_REGISTER_RTX_P (xop0)) \
1490 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1491 else if (BASE_REGISTER_RTX_P (xop1)) \
1492 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1493 } \
1494 /* Reload currently can't handle MINUS, so disable this for now */ \
1495 /* else if (GET_CODE (X) == MINUS) \
1496 { \
1497 rtx xop0 = XEXP (X,0); \
1498 rtx xop1 = XEXP (X,1); \
1499 \
1500 if (BASE_REGISTER_RTX_P (xop0)) \
1501 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1502 } */ \
1503 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1504 && GET_CODE (X) == SYMBOL_REF \
1505 && CONSTANT_POOL_ADDRESS_P (X) \
1506 && ! (flag_pic \
1507 && symbol_mentioned_p (get_pool_constant (X)))) \
1508 goto LABEL; \
1509 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1510 && (GET_MODE_SIZE (MODE) <= 4) \
1511 && GET_CODE (XEXP (X, 0)) == REG \
1512 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1513 goto LABEL; \
1514 }
1515 \f
1516 /* Try machine-dependent ways of modifying an illegitimate address
1517 to be legitimate. If we find one, return the new, valid address.
1518 This macro is used in only one place: `memory_address' in explow.c.
1519
1520 OLDX is the address as it was before break_out_memory_refs was called.
1521 In some cases it is useful to look at this to decide what needs to be done.
1522
1523 MODE and WIN are passed so that this macro can use
1524 GO_IF_LEGITIMATE_ADDRESS.
1525
1526 It is always safe for this macro to do nothing. It exists to recognize
1527 opportunities to optimize the output.
1528
1529 On the ARM, try to convert [REG, #BIGCONST]
1530 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1531 where VALIDCONST == 0 in case of TImode. */
1532 extern struct rtx_def *legitimize_pic_address ();
1533 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1534 { \
1535 if (GET_CODE (X) == PLUS) \
1536 { \
1537 rtx xop0 = XEXP (X, 0); \
1538 rtx xop1 = XEXP (X, 1); \
1539 \
1540 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1541 xop0 = force_reg (SImode, xop0); \
1542 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1543 xop1 = force_reg (SImode, xop1); \
1544 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1545 { \
1546 HOST_WIDE_INT n, low_n; \
1547 rtx base_reg, val; \
1548 n = INTVAL (xop1); \
1549 \
1550 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1551 { \
1552 low_n = n & 0x0f; \
1553 n &= ~0x0f; \
1554 if (low_n > 4) \
1555 { \
1556 n += 16; \
1557 low_n -= 16; \
1558 } \
1559 } \
1560 else \
1561 { \
1562 low_n = ((MODE) == TImode ? 0 \
1563 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1564 n -= low_n; \
1565 } \
1566 base_reg = gen_reg_rtx (SImode); \
1567 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1568 GEN_INT (n)), NULL_RTX); \
1569 emit_move_insn (base_reg, val); \
1570 (X) = (low_n == 0 ? base_reg \
1571 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1572 } \
1573 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1574 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1575 } \
1576 else if (GET_CODE (X) == MINUS) \
1577 { \
1578 rtx xop0 = XEXP (X, 0); \
1579 rtx xop1 = XEXP (X, 1); \
1580 \
1581 if (CONSTANT_P (xop0)) \
1582 xop0 = force_reg (SImode, xop0); \
1583 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1584 xop1 = force_reg (SImode, xop1); \
1585 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1586 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1587 } \
1588 if (flag_pic) \
1589 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1590 if (memory_address_p (MODE, X)) \
1591 goto WIN; \
1592 }
1593
1594 /* Go to LABEL if ADDR (a legitimate address expression)
1595 has an effect that depends on the machine mode it is used for. */
1596 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1597 { \
1598 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1599 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1600 goto LABEL; \
1601 }
1602 \f
1603 /* Specify the machine mode that this machine uses
1604 for the index in the tablejump instruction. */
1605 #define CASE_VECTOR_MODE SImode
1606
1607 /* Define as C expression which evaluates to nonzero if the tablejump
1608 instruction expects the table to contain offsets from the address of the
1609 table.
1610 Do not define this if the table should contain absolute addresses. */
1611 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1612
1613 /* Specify the tree operation to be used to convert reals to integers. */
1614 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1615
1616 /* This is the kind of divide that is easiest to do in the general case. */
1617 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1618
1619 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1620 unsigned is probably best, but may break some code. */
1621 #ifndef DEFAULT_SIGNED_CHAR
1622 #define DEFAULT_SIGNED_CHAR 0
1623 #endif
1624
1625 /* Don't cse the address of the function being compiled. */
1626 #define NO_RECURSIVE_FUNCTION_CSE 1
1627
1628 /* Max number of bytes we can move from memory to memory
1629 in one reasonably fast instruction. */
1630 #define MOVE_MAX 4
1631
1632 /* Define if operations between registers always perform the operation
1633 on the full register even if a narrower mode is specified. */
1634 #define WORD_REGISTER_OPERATIONS
1635
1636 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1637 will either zero-extend or sign-extend. The value of this macro should
1638 be the code that says which one of the two operations is implicitly
1639 done, NIL if none. */
1640 #define LOAD_EXTEND_OP(MODE) \
1641 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1642 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1643
1644 /* Define this if zero-extension is slow (more than one real instruction).
1645 On the ARM, it is more than one instruction only if not fetching from
1646 memory. */
1647 /* #define SLOW_ZERO_EXTEND */
1648
1649 /* Nonzero if access to memory by bytes is slow and undesirable. */
1650 #define SLOW_BYTE_ACCESS 0
1651
1652 /* Immediate shift counts are truncated by the output routines (or was it
1653 the assembler?). Shift counts in a register are truncated by ARM. Note
1654 that the native compiler puts too large (> 32) immediate shift counts
1655 into a register and shifts by the register, letting the ARM decide what
1656 to do instead of doing that itself. */
1657 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1658 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1659 On the arm, Y in a register is used modulo 256 for the shift. Only for
1660 rotates is modulo 32 used. */
1661 /* #define SHIFT_COUNT_TRUNCATED 1 */
1662
1663 /* All integers have the same format so truncation is easy. */
1664 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1665
1666 /* Calling from registers is a massive pain. */
1667 #define NO_FUNCTION_CSE 1
1668
1669 /* Chars and shorts should be passed as ints. */
1670 #define PROMOTE_PROTOTYPES 1
1671
1672 /* The machine modes of pointers and functions */
1673 #define Pmode SImode
1674 #define FUNCTION_MODE Pmode
1675
1676 /* The structure type of the machine dependent info field of insns
1677 No uses for this yet. */
1678 /* #define INSN_MACHINE_INFO struct machine_info */
1679
1680 /* The relative costs of various types of constants. Note that cse.c defines
1681 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1682 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1683 case CONST_INT: \
1684 if (const_ok_for_arm (INTVAL (RTX))) \
1685 return (OUTER_CODE) == SET ? 2 : -1; \
1686 else if (OUTER_CODE == AND \
1687 && const_ok_for_arm (~INTVAL (RTX))) \
1688 return -1; \
1689 else if ((OUTER_CODE == COMPARE \
1690 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1691 && const_ok_for_arm (-INTVAL (RTX))) \
1692 return -1; \
1693 else \
1694 return 5; \
1695 case CONST: \
1696 case LABEL_REF: \
1697 case SYMBOL_REF: \
1698 return 6; \
1699 case CONST_DOUBLE: \
1700 if (const_double_rtx_ok_for_fpu (RTX)) \
1701 return (OUTER_CODE) == SET ? 2 : -1; \
1702 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1703 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1704 return -1; \
1705 return(7);
1706
1707 #define ARM_FRAME_RTX(X) \
1708 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1709 || (X) == arg_pointer_rtx)
1710
1711 #define DEFAULT_RTX_COSTS(X,CODE,OUTER_CODE) \
1712 return arm_rtx_costs (X, CODE, OUTER_CODE);
1713
1714 /* Moves to and from memory are quite expensive */
1715 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1716
1717 /* All address computations that can be done are free, but rtx cost returns
1718 the same for practically all of them. So we weight the different types
1719 of address here in the order (most pref first):
1720 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1721 #define ADDRESS_COST(X) \
1722 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1723 || GET_CODE (X) == SYMBOL_REF) \
1724 ? 0 \
1725 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1726 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1727 ? 10 \
1728 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1729 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1730 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1731 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1732 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1733 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1734 ? 1 : 0)) \
1735 : 4)))))
1736
1737
1738
1739 /* Try to generate sequences that don't involve branches, we can then use
1740 conditional instructions */
1741 #define BRANCH_COST 4
1742
1743 /* A C statement to update the variable COST based on the relationship
1744 between INSN that is dependent on DEP through dependence LINK. */
1745 #define ADJUST_COST(INSN,LINK,DEP,COST) \
1746 (COST) = arm_adjust_cost ((INSN), (LINK), (DEP), (COST))
1747 \f
1748 /* Position Independent Code. */
1749 /* We decide which register to use based on the compilation options and
1750 the assembler in use; this is more general than the APCS restriction of
1751 using sb (r9) all the time. */
1752 extern int arm_pic_register;
1753
1754 /* The register number of the register used to address a table of static
1755 data addresses in memory. */
1756 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1757
1758 #define FINALIZE_PIC arm_finalize_pic ()
1759
1760 /* We can't directly access anything that contains a symbol,
1761 nor can we indirect via the constant pool. */
1762 #define LEGITIMATE_PIC_OPERAND_P(X) \
1763 (! symbol_mentioned_p (X) \
1764 && (! CONSTANT_POOL_ADDRESS_P (X) \
1765 || ! symbol_mentioned_p (get_pool_constant (X))))
1766
1767
1768 \f
1769 /* Condition code information. */
1770 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1771 return the mode to be used for the comparison.
1772 CCFPEmode should be used with floating inequalities,
1773 CCFPmode should be used with floating equalities.
1774 CC_NOOVmode should be used with SImode integer equalities.
1775 CC_Zmode should be used if only the Z flag is set correctly
1776 CCmode should be used otherwise. */
1777
1778 #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \
1779 CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \
1780 CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \
1781 CC_DGEUmode, CC_DGTUmode, CC_Cmode
1782
1783 #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \
1784 "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \
1785 "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C"
1786
1787 enum machine_mode arm_select_cc_mode ();
1788 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1789
1790 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1791
1792 enum rtx_code arm_canonicalize_comparison ();
1793 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1794 do \
1795 { \
1796 if (GET_CODE (OP1) == CONST_INT \
1797 && ! (const_ok_for_arm (INTVAL (OP1)) \
1798 || (const_ok_for_arm (- INTVAL (OP1))))) \
1799 { \
1800 rtx const_op = OP1; \
1801 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1802 OP1 = const_op; \
1803 } \
1804 } while (0)
1805
1806 #define STORE_FLAG_VALUE 1
1807
1808 /* Define the information needed to generate branch insns. This is
1809 stored from the compare operation. Note that we can't use "rtx" here
1810 since it hasn't been defined! */
1811
1812 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1813 extern int arm_compare_fp;
1814
1815 /* Define the codes that are matched by predicates in arm.c */
1816 #define PREDICATE_CODES \
1817 {"s_register_operand", {SUBREG, REG}}, \
1818 {"f_register_operand", {SUBREG, REG}}, \
1819 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1820 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1821 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1822 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1823 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1824 {"offsettable_memory_operand", {MEM}}, \
1825 {"bad_signed_byte_operand", {MEM}}, \
1826 {"alignable_memory_operand", {MEM}}, \
1827 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1828 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1829 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1830 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1831 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1832 {"load_multiple_operation", {PARALLEL}}, \
1833 {"store_multiple_operation", {PARALLEL}}, \
1834 {"equality_operator", {EQ, NE}}, \
1835 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1836 {"const_shift_operand", {CONST_INT}}, \
1837 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1838 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1839 {"multi_register_push", {PARALLEL}}, \
1840 {"cc_register", {REG}}, \
1841 {"dominant_cc_register", {REG}},
1842
1843 \f
1844
1845 /* Gcc puts the pool in the wrong place for ARM, since we can only
1846 load addresses a limited distance around the pc. We do some
1847 special munging to move the constant pool values to the correct
1848 point in the code. */
1849 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1850
1851 /* The pool is empty, since we have moved everything into the code. */
1852 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \
1853 goto JUMPTO
1854
1855 /* Output an internal label definition. */
1856 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1857 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1858 do \
1859 { \
1860 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1861 extern int arm_target_label, arm_ccfsm_state; \
1862 extern rtx arm_target_insn; \
1863 \
1864 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1865 && !strcmp (PREFIX, "L")) \
1866 { \
1867 arm_ccfsm_state = 0; \
1868 arm_target_insn = NULL; \
1869 } \
1870 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1871 ASM_OUTPUT_LABEL (STREAM, s); \
1872 } while (0)
1873 #endif
1874
1875 /* Output a push or a pop instruction (only used when profiling). */
1876 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1877 fprintf (STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \
1878 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1879
1880 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1881 fprintf (STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \
1882 REGISTER_PREFIX, REGISTER_PREFIX, reg_names [REGNO])
1883
1884 /* Target characters. */
1885 #define TARGET_BELL 007
1886 #define TARGET_BS 010
1887 #define TARGET_TAB 011
1888 #define TARGET_NEWLINE 012
1889 #define TARGET_VT 013
1890 #define TARGET_FF 014
1891 #define TARGET_CR 015
1892 \f
1893 /* Only perform branch elimination (by making instructions conditional) if
1894 we're optimising. Otherwise it's of no use anyway. */
1895 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1896 if (optimize) \
1897 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1898
1899 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1900 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1901 /* Output an operand of an instruction. */
1902 #define PRINT_OPERAND(STREAM, X, CODE) \
1903 arm_print_operand (STREAM, X, CODE)
1904
1905 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1906 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1907 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1908 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1909 ? ((~ (HOST_WIDE_INT) 0) \
1910 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1911 : 0))))
1912
1913 /* Output the address of an operand. */
1914 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1915 { \
1916 int is_minus = GET_CODE (X) == MINUS; \
1917 \
1918 if (GET_CODE (X) == REG) \
1919 fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \
1920 reg_names[REGNO (X)]); \
1921 else if (GET_CODE (X) == PLUS || is_minus) \
1922 { \
1923 rtx base = XEXP (X, 0); \
1924 rtx index = XEXP (X, 1); \
1925 char * base_reg_name; \
1926 HOST_WIDE_INT offset = 0; \
1927 if (GET_CODE (base) != REG) \
1928 { \
1929 /* Ensure that BASE is a register (one of them must be). */ \
1930 rtx temp = base; \
1931 base = index; \
1932 index = temp; \
1933 } \
1934 base_reg_name = reg_names[REGNO (base)]; \
1935 switch (GET_CODE (index)) \
1936 { \
1937 case CONST_INT: \
1938 offset = INTVAL (index); \
1939 if (is_minus) \
1940 offset = -offset; \
1941 fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \
1942 base_reg_name, offset); \
1943 break; \
1944 \
1945 case REG: \
1946 fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \
1947 base_reg_name, is_minus ? "-" : "", \
1948 REGISTER_PREFIX, reg_names[REGNO (index)] ); \
1949 break; \
1950 \
1951 case MULT: \
1952 case ASHIFTRT: \
1953 case LSHIFTRT: \
1954 case ASHIFT: \
1955 case ROTATERT: \
1956 { \
1957 fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \
1958 base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\
1959 reg_names[REGNO (XEXP (index, 0))]); \
1960 arm_print_operand (STREAM, index, 'S'); \
1961 fputs ("]", STREAM); \
1962 break; \
1963 } \
1964 \
1965 default: \
1966 abort(); \
1967 } \
1968 } \
1969 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1970 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1971 { \
1972 extern int output_memory_reference_mode; \
1973 \
1974 if (GET_CODE (XEXP (X, 0)) != REG) \
1975 abort (); \
1976 \
1977 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1978 fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \
1979 reg_names[REGNO (XEXP (X, 0))], \
1980 GET_CODE (X) == PRE_DEC ? "-" : "", \
1981 GET_MODE_SIZE (output_memory_reference_mode)); \
1982 else \
1983 fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \
1984 reg_names[REGNO (XEXP (X, 0))], \
1985 GET_CODE (X) == POST_DEC ? "-" : "", \
1986 GET_MODE_SIZE (output_memory_reference_mode)); \
1987 } \
1988 else output_addr_const(STREAM, X); \
1989 }
1990
1991 /* Handles PIC addr specially */
1992 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
1993 { \
1994 if (flag_pic && GET_CODE(X) == CONST && is_pic(X)) \
1995 { \
1996 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
1997 fputs(" - (", STREAM); \
1998 output_addr_const(STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
1999 fputs(")", STREAM); \
2000 } \
2001 else output_addr_const(STREAM, X); \
2002 }
2003
2004 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2005 Used for C++ multiple inheritance. */
2006 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2007 do { \
2008 int mi_delta = (DELTA); \
2009 char *mi_op = mi_delta < 0 ? "sub" : "add"; \
2010 int shift = 0; \
2011 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2012 ? 1 : 0); \
2013 if (mi_delta < 0) mi_delta = -mi_delta; \
2014 while (mi_delta != 0) \
2015 { \
2016 if (mi_delta & (3 << shift) == 0) \
2017 shift += 2; \
2018 else \
2019 { \
2020 fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \
2021 mi_op, REGISTER_PREFIX, reg_names[this_regno], \
2022 REGISTER_PREFIX, reg_names[this_regno], \
2023 mi_delta & (0xff << shift)); \
2024 mi_delta &= ~(0xff << shift); \
2025 shift += 8; \
2026 } \
2027 } \
2028 fputs ("\tb\t", FILE); \
2029 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2030 fputc ('\n', FILE); \
2031 } while (0)
2032
2033 /* A C expression whose value is RTL representing the value of the return
2034 address for the frame COUNT steps up from the current frame. */
2035
2036 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2037 ((COUNT == 0) \
2038 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2039 : NULL_RTX)
2040
2041 /* Used to mask out junk bits from the return address, such as
2042 processor state, interrupt status, condition codes and the like. */
2043 #define MASK_RETURN_ADDR \
2044 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2045 in 26 bit mode, the condition codes must be masked out of the \
2046 return address. This does not apply to ARM6 and later processors \
2047 when running in 32 bit mode. */ \
2048 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2049
2050 /* Prototypes for arm.c -- actually, they aren't since the types aren't
2051 fully defined yet. */
2052
2053 void arm_override_options PROTO ((void));
2054 int use_return_insn PROTO ((int));
2055 int const_ok_for_arm (/* HOST_WIDE_INT */);
2056 int const_ok_for_op (/* HOST_WIDE_INT, enum rtx_code,
2057 enum machine_mode */);
2058 int arm_split_constant (/* enum rtx_code, enum machine_mode,
2059 HOST_WIDE_INT, struct rtx_def *,
2060 struct rtx_def *, int */);
2061 enum rtx_code arm_canonicalize_comparison (/* enum rtx_code,
2062 struct rtx_def ** */);
2063 int arm_return_in_memory (/* union tree_node * */);
2064 int legitimate_pic_operand_p (/* struct rtx_def * */);
2065 struct rtx_def *legitimize_pic_address (/* struct rtx_def *,
2066 enum machine_mode,
2067 struct rtx_def * */);
2068 int is_pic (/* struct rtx_def * */);
2069 void arm_finalize_pic (/* void */);
2070 int arm_rtx_costs (/* struct rtx_def *, enum rtx_code, enum rtx_code */);
2071 int arm_adjust_cost (/* struct rtx_def *, struct rtx_def *,
2072 struct rtx_def *, int */);
2073 int const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2074 int neg_const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
2075 int s_register_operand (/* struct rtx_def *, enum machine_mode */);
2076 int f_register_operand (/* struct rtx_def *, enum machine_mode */);
2077 int reg_or_int_operand (/* struct rtx_def *, enum machine_mode */);
2078 int reload_memory_operand (/* struct rtx_def *, enum machine_mode */);
2079 int arm_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2080 int arm_rhsm_operand (/* struct rtx_def *, enum machine_mode */);
2081 int arm_add_operand (/* struct rtx_def *, enum machine_mode */);
2082 int arm_not_operand (/* struct rtx_def *, enum machine_mode */);
2083 int offsettable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2084 int alignable_memory_operand (/* struct rtx_def *, enum machine_mode */);
2085 int bad_signed_byte_operand (/* struct rtx_def *, enum machine_mode */);
2086 int fpu_rhs_operand (/* struct rtx_def *, enum machine_mode */);
2087 int fpu_add_operand (/* struct rtx_def *, enum machine_mode */);
2088 int power_of_two_operand (/* struct rtx_def *, enum machine_mode */);
2089 int di_operand (/* struct rtx_def *, enum machine_mode */);
2090 int soft_df_operand (/* struct rtx_def *, enum machine_mode */);
2091 int index_operand (/* struct rtx_def *, enum machine_mode */);
2092 int const_shift_operand (/* struct rtx_def *, enum machine_mode */);
2093 int shiftable_operator (/* struct rtx_def *, enum machine_mode */);
2094 int shift_operator (/* struct rtx_def *, enum machine_mode */);
2095 int equality_operator (/* struct rtx_def *, enum machine_mode */);
2096 int minmax_operator (/* struct rtx_def *, enum machine_mode */);
2097 int cc_register (/* struct rtx_def *, enum machine_mode */);
2098 int dominant_cc_register (/* struct rtx_def *, enum machine_mode */);
2099 int symbol_mentioned_p (/* struct rtx_def * */);
2100 int label_mentioned_p (/* struct rtx_def * */);
2101 enum rtx_code minmax_code (/* struct rtx_def * */);
2102 int adjacent_mem_locations (/* struct rtx_def *, struct rtx_def * */);
2103 int load_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2104 int store_multiple_operation (/* struct rtx_def *, enum machine_mode */);
2105 int load_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2106 HOST_WIDE_INT * */);
2107 char *emit_ldm_seq (/* struct rtx_def **, int */);
2108 int store_multiple_sequence (/* struct rtx_def **, int, int *, int *,
2109 HOST_WIDE_INT * */);
2110 char *emit_stm_seq (/* struct rtx_def **, int */);
2111 int multi_register_push (/* struct rtx_def *, enum machine_mode */);
2112 int arm_valid_machine_decl_attribute (/* union tree_node *, union tree_node *,
2113 union tree_node *,
2114 union tree_node * */);
2115 struct rtx_def *arm_gen_load_multiple (/* int, int, struct rtx_def *,
2116 int, int, int, int, int */);
2117 struct rtx_def *arm_gen_store_multiple (/* int, int, struct rtx_def *,
2118 int, int, int, int, int */);
2119 int arm_gen_movstrqi (/* struct rtx_def ** */);
2120 struct rtx_def *gen_rotated_half_load (/* struct rtx_def * */);
2121 enum machine_mode arm_select_cc_mode (/* enum rtx_code, struct rtx_def *,
2122 struct rtx_def * */);
2123 struct rtx_def *gen_compare_reg (/* enum rtx_code, struct rtx_def *,
2124 struct rtx_def * */);
2125 void arm_reload_in_hi (/* struct rtx_def ** */);
2126 void arm_reload_out_hi (/* struct rtx_def ** */);
2127 void arm_reorg (/* struct rtx_def * */);
2128 char *fp_immediate_constant (/* struct rtx_def * */);
2129 void print_multi_reg (/* FILE *, char *, int, int */);
2130 char *output_call (/* struct rtx_def ** */);
2131 char *output_call_mem (/* struct rtx_def ** */);
2132 char *output_mov_long_double_fpu_from_arm (/* struct rtx_def ** */);
2133 char *output_mov_long_double_arm_from_fpu (/* struct rtx_def ** */);
2134 char *output_mov_long_double_arm_from_arm (/* struct rtx_def ** */);
2135 char *output_mov_double_fpu_from_arm (/* struct rtx_def ** */);
2136 char *output_mov_double_arm_from_fpu (/* struct rtx_def ** */);
2137 char *output_move_double (/* struct rtx_def ** */);
2138 char *output_mov_immediate (/* struct rtx_def ** */);
2139 char *output_add_immediate (/* struct rtx_def ** */);
2140 char *arithmetic_instr (/* struct rtx_def *, int */);
2141 void output_ascii_pseudo_op (/* FILE *, unsigned char *, int */);
2142 char *output_return_instruction (/* struct rtx_def *, int, int */);
2143 int arm_volatile_func (/* void */);
2144 void output_func_prologue (/* FILE *, int */);
2145 void output_func_epilogue (/* FILE *, int */);
2146 void arm_expand_prologue (/* void */);
2147 void arm_print_operand (/* FILE *, struct rtx_def *, int */);
2148 void final_prescan_insn (/* struct rtx_def *, struct rtx_def **, int */);
2149 #ifdef AOF_ASSEMBLER
2150 struct rtx_def *aof_pic_entry (/* struct rtx_def * */);
2151 void aof_dump_pic_table (/* FILE * */);
2152 char *aof_text_section (/* void */);
2153 char *aof_data_section (/* void */);
2154 void aof_add_import (/* char * */);
2155 void aof_delete_import (/* char * */);
2156 void aof_dump_imports (/* FILE * */);
2157 #endif
2158
2159 #endif /* __ARM_H__ */
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