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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2023 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch. */
111 \f
112 /* First, some functions that were used before GCC got a control flow graph.
113 These functions are now only used here in reorg.cc, and have therefore
114 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
116 /* Return the last label to mark the same position as LABEL. Return LABEL
117 itself if it is null or any return rtx. */
119 static rtx
121 {
129 /* __builtin_unreachable can create a CODE_LABEL followed by a BARRIER.
131 Since reaching the CODE_LABEL is undefined behavior, we can return
132 any code label and we're OK at run time.
134 However, if we return a CODE_LABEL which leads to a shrink-wrapped
135 epilogue, but the path does not have a prologue, then we will trip
136 a sanity check in the dwarf2 cfi code which wants to verify that
137 the CFIs are all the same on the traces leading to the epilogue.
139 So we explicitly disallow looking through BARRIERS here. */
147 }
148 \f
149 /* Insns which have delay slots that have not yet been filled. */
154 /* Define macros to refer to the first and last slot containing unfilled
155 insns. These are used because the list may move and its address
156 should be recomputed at each use. */
158 #define unfilled_slots_base \
159 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
161 #define unfilled_slots_next \
162 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
164 /* Points to the label before the end of the function, or before a
165 return insn. */
167 /* Likewise for a simple_return. */
170 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
171 not always monotonically increase. */
174 /* Highest valid index in `uid_to_ruid'. */
202 rtx *);
224 \f
225 /* A wrapper around next_active_insn which takes care to return ret_rtx
226 unchanged. */
228 static rtx
230 {
234 }
235 \f
236 /* Return true iff INSN is a simplejump, or any kind of return insn. */
238 static bool
240 {
244 }
245 \f
246 /* Return TRUE if this insn should stop the search for insn to fill delay
247 slots. LABELS_P indicates that labels should terminate the search.
248 In all cases, jumps terminate the search. */
250 static bool
252 {
256 /* If the insn can throw an exception that is caught within the function,
257 it may effectively perform a jump from the viewpoint of the function.
258 Therefore act like for a jump. */
263 {
277 /* OK unless it contains a delay slot or is an `asm' insn of some type.
278 We don't know anything about these. */
285 }
286 }
287 \f
288 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
289 resource set contains a volatile memory reference. Otherwise, return FALSE. */
291 static bool
293 {
299 }
301 /* Return TRUE if any resource marked in RES, a `struct resources', is
302 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
303 routine is using those resources.
305 We compute this by computing all the resources referenced by INSN and
306 seeing if this conflicts with RES. It might be faster to directly check
307 ourselves, and this is the way it used to work, but it means duplicating
308 a large block of complex code. */
310 static bool
313 {
319 }
321 /* Return TRUE if INSN modifies resources that are marked in RES.
322 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
323 included. */
325 static bool
328 {
333 (include_delayed_effects
334 ? MARK_SRC_DEST_CALL
337 }
338 \f
339 /* Find a label at the end of the function or before a RETURN. If there
340 is none, try to make one. If that fails, returns 0.
342 The property of such a label is that it is placed just before the
343 epilogue or a bare RETURN insn, so that another bare RETURN can be
344 turned into a jump to the label unconditionally. In particular, the
345 label cannot be placed before a RETURN insn with a filled delay slot.
347 ??? There may be a problem with the current implementation. Suppose
348 we start with a bare RETURN insn and call find_end_label. It may set
349 function_return_label just before the RETURN. Suppose the machinery
350 is able to fill the delay slot of the RETURN insn afterwards. Then
351 function_return_label is no longer valid according to the property
352 described above and find_end_label will still return it unmodified.
353 Note that this is probably mitigated by the following observation:
354 once function_return_label is made, it is very likely the target of
355 a jump, so filling the delay slot of the RETURN will be much more
356 difficult.
357 KIND is either simple_return_rtx or ret_rtx, indicating which type of
358 return we're looking for. */
362 {
368 else
369 {
372 }
374 /* If we found one previously, return it. */
378 /* Otherwise, see if there is a label at the end of the function. If there
379 is, it must be that RETURN insns aren't needed, so that is our return
380 label and we don't have to do anything else. */
389 /* When a target threads its epilogue we might already have a
390 suitable return insn. If so put a label before it for the
391 function_return_label. */
395 {
400 /* Put the label before any USE insns that may precede the RETURN
401 insn. */
407 }
411 else
412 {
415 /* If the basic block reorder pass moves the return insn to
416 some other place try to locate it again and put our
417 function_return_label there. */
421 {
424 /* Put the label before any USE insns that may precede the
425 RETURN insn. */
430 }
431 else
432 {
434 /* The RETURN insn has its delay slot filled so we cannot
435 emit the label just before it. Since we already have
436 an epilogue and cannot emit a new RETURN, we cannot
437 emit the label at all. */
440 /* Otherwise, make a new label and emit a RETURN and BARRIER,
441 if needed. */
444 {
445 /* The return we make may have delay slots too. */
452 }
453 }
455 }
457 /* Show one additional use for this label so it won't go away until
458 we are done. */
462 }
463 \f
464 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
465 the pattern of INSN with the SEQUENCE.
467 Returns the insn containing the SEQUENCE that replaces INSN. */
471 {
472 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
477 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
478 not have a location, but one of the delayed insns does, we pick up a
479 location from there later. */
482 /* Unlink INSN from the insn chain, so that we can put it into
483 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
488 /* Build our SEQUENCE and rebuild the insn chain. */
495 {
499 /* Show that this copy of the insn isn't deleted. */
502 /* Unlink insn from its original place, and re-emit it into
503 the sequence. */
507 /* SPARC assembler, for instance, emit warning when debug info is output
508 into the delay slot. */
514 {
517 {
519 /* Remove any REG_DEAD notes because we can't rely on them now
520 that the insn has been moved. */
526 /* Keep the label reference count up to date. */
533 }
534 }
535 }
538 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
542 }
544 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
545 be in the order in which the insns are to be executed. */
547 static void
549 {
550 /* If INSN has its block number recorded, clear it since we may
551 be moving the insn to a new block. */
555 }
556 \f
557 /* Delete INSN from the delay slot of the insn that it is in, which may
558 produce an insn with no delay slots. Return the new insn. */
562 {
568 /* We first must find the insn containing the SEQUENCE with INSN in its
569 delay slot. Do this by finding an insn, TRIAL, where
570 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
575 ;
583 /* Create a delay list consisting of all the insns other than the one
584 we are deleting (unless we were the only one). */
591 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
592 list, and rebuild the delay list if non-empty. */
598 /* If there was a barrier after the old SEQUENCE, remit it. */
602 /* If there are any delay insns, remit them. Otherwise clear the
603 annul flag. */
611 /* Show we need to fill this insn again. */
615 }
616 \f
617 /* Delete INSN, a JUMP_INSN. */
619 static void
621 {
623 }
624 \f
625 /* Counters for delay-slot filling. */
627 #define NUM_REORG_FUNCTIONS 2
628 #define MAX_DELAY_HISTOGRAM 3
629 #define MAX_REORG_PASSES 2
637 static void
639 {
644 }
645 \f
646 /* Optimize the following cases:
648 1. When a conditional branch skips over only one instruction,
649 use an annulling branch and put that insn in the delay slot.
650 Use either a branch that annuls when the condition if true or
651 invert the test with a branch that annuls when the condition is
652 false. This saves insns, since otherwise we must copy an insn
653 from the L1 target.
655 (orig) (skip) (otherwise)
656 Bcc.n L1 Bcc',a L1 Bcc,a L1'
657 insn insn insn2
658 L1: L1: L1:
659 insn2 insn2 insn2
660 insn3 insn3 L1':
661 insn3
663 2. When a conditional branch skips over only one instruction,
664 and after that, it unconditionally branches somewhere else,
665 perform the similar optimization. This saves executing the
666 second branch in the case where the inverted condition is true.
668 Bcc.n L1 Bcc',a L2
669 insn insn
670 L1: L1:
671 Bra L2 Bra L2
673 INSN is a JUMP_INSN.
675 This should be expanded to skip over N insns, where N is the number
676 of delay slots required. */
678 static void
680 {
697 /* There are two cases where we are just executing one insn (we assume
698 here that a branch requires only one insn; this should be generalized
699 at some point): Where the branch goes around a single insn or where
700 we have one insn followed by a branch to the same label we branch to.
701 In both of these cases, inverting the jump and annulling the delay
702 slot give the same effect in fewer insns. */
707 {
709 {
714 }
721 /* Also, if we are targeting an unconditional
722 branch, thread our jump to the target of that branch. Don't
723 change this into a RETURN here, because it may not accept what
724 we have in the delay slot. We'll fix this up later. */
726 {
732 {
733 /* Recompute the flags based on TARGET_LABEL since threading
734 the jump to TARGET_LABEL may change the direction of the
735 jump (which may change the circumstances in which the
736 delay slot is nullified). */
740 }
741 }
744 }
745 }
746 \f
747 /* Encode and return branch direction and prediction information for
748 INSN assuming it will jump to LABEL.
750 Non conditional branches return no direction information and
751 are predicted as very likely taken. */
753 static int
755 {
758 /* get_jump_flags can be passed any insn with delay slots, these may
759 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
760 direction information, and only if they are conditional jumps.
762 If LABEL is a return, then there is no way to determine the branch
763 direction. */
769 flags
772 /* No valid direction information. */
773 else
777 }
779 /* Return truth value of the statement that this branch
780 is mostly taken. If we think that the branch is extremely likely
781 to be taken, we return 2. If the branch is slightly more likely to be
782 taken, return 1. If the branch is slightly less likely to be taken,
783 return 0 and if the branch is highly unlikely to be taken, return -1. */
785 static int
787 {
788 /* If branch probabilities are available, then use that number since it
789 always gives a correct answer. */
792 {
802 else
804 }
806 /* If there is no note, assume branches are not taken.
807 This should be rare. */
809 }
811 /* Return the condition under which INSN will branch to TARGET. If TARGET
812 is zero, return the condition under which INSN will return. If INSN is
813 an unconditional branch, return const_true_rtx. If INSN isn't a simple
814 type of jump, or it doesn't go to TARGET, return 0. */
816 static rtx
818 {
820 rtx src;
847 {
854 }
857 }
859 /* Return true if CONDITION is more strict than the condition of
860 INSN, i.e., if INSN will always branch if CONDITION is true. */
862 static bool
864 {
883 }
885 /* Return true if redirecting JUMP to NEWLABEL does not invalidate
886 any insns already in the delay slot of JUMP. */
888 static bool
890 {
894 /* Make sure all the delay slots of this jump would still
895 be valid after threading the jump. If they are still
896 valid, then return nonzero. */
901 #if ANNUL_IFFALSE_SLOTS
905 #endif
906 #if ANNUL_IFTRUE_SLOTS
910 #endif
915 }
917 /* Return true if redirecting JUMP to NEWLABEL does not invalidate
918 any insns we wish to place in the delay slot of JUMP. */
920 static bool
923 {
924 /* Make sure all the insns in DELAY_LIST would still be
925 valid after threading the jump. If they are still
926 valid, then return true. */
933 #if ANNUL_IFFALSE_SLOTS
937 #endif
938 #if ANNUL_IFTRUE_SLOTS
942 #endif
947 }
949 /* DELAY_LIST is a list of insns that have already been placed into delay
950 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
951 If not, return false; otherwise return true. */
953 static bool
956 {
965 }
966 \f
967 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
968 the condition tested by INSN is CONDITION and the resources shown in
969 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
970 from SEQ's delay list, in addition to whatever insns it may execute
971 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
972 needed while searching for delay slot insns. Return the concatenated
973 delay list if possible, otherwise, return 0.
975 SLOTS_TO_FILL is the total number of slots required by INSN, and
976 PSLOTS_FILLED points to the number filled so far (also the number of
977 insns in DELAY_LIST). It is updated with the number that have been
978 filled from the SEQUENCE, if any.
980 PANNUL_P points to a nonzero value if we already know that we need
981 to annul INSN. If this routine determines that annulling is needed,
982 it may set that value to true.
984 PNEW_THREAD points to a location that is to receive the place at which
985 execution should continue. */
987 static void
995 {
1005 /* We can't do anything if there are more delay slots in SEQ than we
1006 can handle, or if we don't know that it will be a taken branch.
1007 We know that it will be a taken branch if it is either an unconditional
1008 branch or a conditional branch with a stricter branch condition.
1010 Also, exit if the branch has more than one set, since then it is computing
1011 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1012 ??? It may be possible to move other sets into INSN in addition to
1013 moving the instructions in the delay slots.
1015 We cannot steal the delay list if one of the instructions in the
1016 current delay_list modifies the condition codes and the jump in the
1017 sequence is a conditional jump. We cannot do this because we cannot
1018 change the direction of the jump because the condition codes
1019 will effect the direction of the jump in the sequence. */
1025 {
1029 }
1036 /* On some targets, branches with delay slots can have a limited
1037 displacement. Give the back end a chance to tell us we can't do
1038 this. */
1044 {
1051 /* If TRIAL is from the fallthrough code of an annulled branch insn
1052 in SEQ, we cannot use it. */
1057 /* If this insn was already done (usually in a previous delay slot),
1058 pretend we put it in our delay slot. */
1063 /* We will end up re-vectoring this branch, so compute flags
1064 based on jumping to the new label. */
1078 {
1080 {
1081 /* Frame related instructions cannot go into annulled delay
1082 slots, it messes up the dwarf info. */
1086 }
1090 total_slots_filled++;
1094 }
1095 else
1097 }
1099 /* Record the effect of the instructions that were redundant and which
1100 we therefore decided not to copy. */
1103 {
1106 }
1108 /* Show the place to which we will be branching. */
1111 /* Add any new insns to the delay list and update the count of the
1112 number of slots filled. */
1120 }
1121 \f
1122 /* Similar to steal_delay_list_from_target except that SEQ is on the
1123 fallthrough path of INSN. Here we only do something if the delay insn
1124 of SEQ is an unconditional branch. In that case we steal its delay slot
1125 for INSN since unconditional branches are much easier to fill. */
1127 static void
1136 {
1144 /* We can't do anything if SEQ's delay insn isn't an
1145 unconditional branch. */
1151 {
1160 /* If this insn was already done, we don't need it. */
1162 {
1167 }
1177 {
1185 }
1186 else
1188 }
1192 }
1193 \f
1194 /* Try merging insns starting at THREAD which match exactly the insns in
1195 INSN's delay list.
1197 If all insns were matched and the insn was previously annulling, the
1198 annul bit will be cleared.
1200 For each insn that is merged, if the branch is or will be non-annulling,
1201 we delete the merged insn. */
1203 static void
1205 {
1221 /* If this is not an annulling branch, take into account anything needed in
1222 INSN's delay slot. This prevents two increments from being incorrectly
1223 folded into one. If we are annulling, this would be the correct
1224 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1225 will essentially disable this optimization. This method is somewhat of
1226 a kludge, but I don't see a better way.) */
1234 {
1240 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1250 /* Update next_trial, in case try_split succeeded. */
1252 /* Likewise THREAD. */
1255 /* Have to test this condition if annul condition is different
1256 from (and less restrictive than) non-annulling one. */
1258 {
1261 {
1268 }
1269 else
1276 }
1280 }
1282 /* See if we stopped on a filled insn. If we did, try to see if its
1283 delay slots match. */
1289 {
1293 /* Account for resources set/needed by the filled insn. */
1298 {
1302 /* Account for resources set by the insn following NEXT_TO_MATCH
1303 inside INSN's delay list. */
1307 /* Account for resources set by the insn before DTRIAL and inside
1308 TRIAL's delay list. */
1316 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1317 resource modified between them (only dtrial is checked because
1318 next_to_match and dtrial shall to be equal in order to hit
1319 this line) */
1322 {
1324 {
1332 }
1333 else
1341 }
1342 else
1343 {
1344 /* Keep track of the set/referenced resources for the delay
1345 slots of any trial insns we encounter. */
1348 }
1349 }
1350 }
1352 /* If all insns in the delay slot have been matched and we were previously
1353 annulling the branch, we need not any more. In that case delete all the
1354 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1355 the delay list so that we know that it isn't only being used at the
1356 target. */
1358 {
1362 {
1367 }
1368 else
1369 {
1372 }
1378 }
1379 }
1380 \f
1381 /* See if INSN is redundant with an insn in front of TARGET. Often this
1382 is called when INSN is a candidate for a delay slot of TARGET.
1383 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1384 of INSN. Often INSN will be redundant with an insn in a delay slot of
1385 some previous insn. This happens when we have a series of branches to the
1386 same label; in that case the first insn at the target might want to go
1387 into each of the delay slots.
1389 If we are not careful, this routine can take up a significant fraction
1390 of the total compilation time (4%), but only wins rarely. Hence we
1391 speed this routine up by making two passes. The first pass goes back
1392 until it hits a label and sees if it finds an insn with an identical
1393 pattern. Only in this (relatively rare) event does it check for
1394 data conflicts.
1396 We do not split insns we encounter. This could cause us not to find a
1397 redundant insn, but the cost of splitting seems greater than the possible
1398 gain in rare cases. */
1402 {
1406 rtx pat;
1411 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1412 are allowed to not actually assign to such a register. */
1416 /* Scan backwards looking for a match. */
1421 {
1422 /* (use (insn))s can come immediately after a barrier if the
1423 label that used to precede them has been deleted as dead.
1424 See delete_related_insns. */
1440 {
1441 /* Stop for a CALL and its delay slots because it is difficult to
1442 track its resource needs correctly. */
1446 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1447 slots because it is difficult to track its resource needs
1448 correctly. */
1456 /* See if any of the insns in the delay slot match, updating
1457 resource requirements as we go. */
1464 /* If found a match, exit this loop early. */
1467 }
1472 }
1474 /* If we didn't find an insn that matches, return 0. */
1478 /* See what resources this insn sets and needs. If they overlap, it
1479 can't be redundant. */
1486 /* If TARGET is a SEQUENCE, get the main insn. */
1491 /* The insn requiring the delay may not set anything needed or set by
1492 INSN. */
1497 /* Insns we pass may not set either NEEDED or SET, so merge them for
1498 simpler tests. */
1502 /* This insn isn't redundant if it conflicts with an insn that either is
1503 or will be in a delay slot of TARGET. */
1517 /* Scan backwards until we reach a label or an insn that uses something
1518 INSN sets or sets something insn uses or sets. */
1524 {
1537 {
1541 /* If this is a CALL_INSN and its delay slots, it is hard to track
1542 the resource needs properly, so give up. */
1546 /* If this is an INSN or JUMP_INSN with delayed effects, it
1547 is hard to track the resource needs properly, so give up. */
1558 /* See if any of the insns in the delay slot match, updating
1559 resource requirements as we go. */
1561 {
1564 /* If an insn will be annulled if the branch is false, it isn't
1565 considered as a possible duplicate insn. */
1568 {
1569 /* Show that this insn will be used in the sequel. */
1572 }
1574 /* Unless this is an annulled insn from the target of a branch,
1575 we must stop if it sets anything needed or set by INSN. */
1579 }
1581 /* If the insn requiring the delay slot conflicts with INSN, we
1582 must stop. */
1585 }
1586 else
1587 {
1588 /* See if TRIAL is the same as INSN. */
1593 /* Can't go any further if TRIAL conflicts with INSN. */
1596 }
1597 }
1600 }
1601 \f
1602 /* Return true if THREAD can only be executed in one way. If LABEL is nonzero,
1603 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1604 is true, we are allowed to fall into this thread; otherwise, we are not.
1606 If LABEL is used more than one or we pass a label other than LABEL before
1607 finding an active insn, we do not own this thread. */
1609 static bool
1611 {
1615 /* We don't own the function end. */
1619 /* We have a non-NULL insn. */
1622 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1633 /* Ensure that we reach a BARRIER before any insn or label. */
1645 }
1646 \f
1647 /* Called when INSN is being moved from a location near the target of a jump.
1648 We leave a marker of the form (use (INSN)) immediately in front of WHERE
1649 for mark_target_live_regs. These markers will be deleted at the end.
1651 We used to try to update the live status of registers if WHERE is at
1652 the start of a basic block, but that can't work since we may remove a
1653 BARRIER in relax_delay_slots. */
1655 static void
1657 {
1660 /* INSN might be making a value live in a block where it didn't use to
1661 be. So recompute liveness information for this block. */
1663 }
1665 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1666 the basic block containing the jump. */
1668 static bool
1670 {
1673 }
1675 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1676 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1677 that reference values used in INSN. If we find one, then we move the
1678 REG_DEAD note to INSN.
1680 This is needed to handle the case where a later insn (after INSN) has a
1681 REG_DEAD note for a register used by INSN, and this later insn subsequently
1682 gets moved before a CODE_LABEL because it is a redundant insn. In this
1683 case, mark_target_live_regs may be confused into thinking the register
1684 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1686 static void
1688 {
1695 {
1703 {
1704 /* Move the REG_DEAD note from P to INSN. */
1708 }
1709 }
1710 }
1712 /* Called when an insn redundant with start_insn is deleted. If there
1713 is a REG_DEAD note for the target of start_insn between start_insn
1714 and stop_insn, then the REG_DEAD note needs to be deleted since the
1715 value no longer dies there.
1717 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1718 confused into thinking the register is dead. */
1720 static void
1722 {
1729 {
1737 {
1740 }
1741 }
1742 }
1744 /* Delete any REG_UNUSED notes that exist on INSN but not on OTHER_INSN.
1746 This handles the case of udivmodXi4 instructions which optimize their
1747 output depending on whether any REG_UNUSED notes are present. We must
1748 make sure that INSN calculates as many results as OTHER_INSN does. */
1750 static void
1752 {
1756 {
1765 }
1766 }
1767 \f
1770 /* Return the label before INSN, or put a new label there. If SIBLING is
1771 non-zero, it is another label associated with the new label (if any),
1772 typically the former target of the jump that will be redirected to
1773 the new label. */
1777 {
1780 /* Find an existing label at this point
1781 or make a new one if there is none. */
1785 {
1792 {
1795 }
1796 }
1798 }
1800 /* Scan a function looking for insns that need a delay slot and find insns to
1801 put into the delay slot.
1803 NON_JUMPS_P is true if we are to only try to fill non-jump insns (such
1804 as calls). We do these first since we don't want jump insns (that are
1805 easier to fill) to get the only insns that could be used for non-jump insns.
1806 When it is zero, only try to fill JUMP_INSNs.
1808 When slots are filled in this manner, the insns (including the
1809 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1810 it is possible to tell whether a delay slot has really been filled
1811 or not. `final' knows how to deal with this, by communicating
1812 through FINAL_SEQUENCE. */
1814 static void
1816 {
1818 rtx pat;
1826 {
1828 /* Get the next insn to fill. If it has already had any slots assigned,
1829 we can't do anything with it. Maybe we'll improve this later. */
1840 /* It may have been that this insn used to need delay slots, but
1841 now doesn't; ignore in that case. This can happen, for example,
1842 on the HP PA RISC, where the number of delay slots depends on
1843 what insns are nearby. */
1846 /* Some machine description have defined instructions to have
1847 delay slots only in certain circumstances which may depend on
1848 nearby insns (which change due to reorg's actions).
1850 For example, the PA port normally has delay slots for unconditional
1851 jumps.
1853 However, the PA port claims such jumps do not have a delay slot
1854 if they are immediate successors of certain CALL_INSNs. This
1855 allows the port to favor filling the delay slot of the call with
1856 the unconditional jump. */
1860 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1861 says how many. After initialization, first try optimizing
1863 call _foo call _foo
1864 nop add %o7,.-L1,%o7
1865 b,a L1
1866 nop
1868 If this case applies, the delay slot of the call is filled with
1869 the unconditional jump. This is done first to avoid having the
1870 delay slot of the call filled in the backward scan. Also, since
1871 the unconditional jump is likely to also have a delay slot, that
1872 insn must exist when it is subsequently scanned.
1874 This is tried on each insn with delay slots as some machines
1875 have insns which perform calls, but are not represented as
1876 CALL_INSNs. */
1883 else
1892 {
1894 slots_filled++;
1897 /* TRIAL may have had its delay slot filled, then unfilled. When
1898 the delay slot is unfilled, TRIAL is placed back on the unfilled
1899 slots obstack. Unfortunately, it is placed on the end of the
1900 obstack, not in its original location. Therefore, we must search
1901 from entry i + 1 to the end of the unfilled slots obstack to
1902 try and find TRIAL. */
1905 tmp++;
1907 /* Remove the unconditional jump from consideration for delay slot
1908 filling and unthread it. */
1911 {
1918 }
1919 }
1921 /* Now, scan backwards from the insn to search for a potential
1922 delay-slot candidate. Stop searching when a label or jump is hit.
1924 For each candidate, if it is to go into the delay slot (moved
1925 forward in execution sequence), it must not need or set any resources
1926 that were set by later insns and must not set any resources that
1927 are needed for those insns.
1929 The delay slot insn itself sets resources unless it is a call
1930 (in which case the called routine, not the insn itself, is doing
1931 the setting). */
1934 {
1935 /* If the flags register is dead after the insn, then we want to be
1936 able to accept a candidate that clobbers it. For this purpose,
1937 we need to filter the flags register during life analysis, so
1938 that it doesn't create RAW and WAW dependencies, while still
1939 creating the necessary WAR dependencies. */
1940 bool filter_flags
1949 {
1952 }
1957 {
1960 /* This must be an INSN or CALL_INSN. */
1963 /* Stand-alone USE and CLOBBER are just for flow. */
1967 /* And DEBUG_INSNs never go into delay slots. */
1971 /* Check for resource conflict first, to avoid unnecessary
1972 splitting. */
1979 {
1983 {
1984 /* In this case, we are searching backward, so if we
1985 find insns to put on the delay list, we want
1986 to put them at the head, rather than the
1987 tail, of the list. */
1996 }
1997 }
2001 {
2003 /* If the flags register is set, then it doesn't create RAW
2004 dependencies any longer and it also doesn't create WAW
2005 dependencies since it's dead after the original insn. */
2007 {
2010 }
2011 }
2013 }
2014 }
2016 /* If all needed slots haven't been filled, we come here. */
2018 /* Try to optimize case of jumping around a single insn. */
2025 {
2029 }
2031 /* Try to get insns from beyond the insn needing the delay slot.
2032 These insns can neither set or reference resources set in insns being
2033 skipped, cannot set resources in the insn being skipped, and, if this
2034 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2035 call might not return).
2037 There used to be code which continued past the target label if
2038 we saw all uses of the target label. This code did not work,
2039 because it failed to account for some instructions which were
2040 both annulled and marked as from the target. This can happen as a
2041 result of optimize_skip. Since this code was redundant with
2042 fill_eager_delay_slots anyways, it was just deleted. */
2045 /* If this instruction could throw an exception which is
2046 caught in the same function, then it's not safe to fill
2047 the delay slot with an instruction from beyond this
2048 point. For example, consider:
2050 int i = 2;
2052 try {
2053 f();
2054 i = 3;
2055 } catch (...) {}
2057 return i;
2059 Even though `i' is a local variable, we must be sure not
2060 to put `i = 3' in the delay slot if `f' might throw an
2061 exception.
2063 Presumably, we should also check to see if we could get
2064 back to this function via `setjmp'. */
2067 {
2081 {
2084 /* This must be an INSN or CALL_INSN. */
2087 /* Stand-alone USE and CLOBBER are just for flow. */
2091 /* And DEBUG_INSNs do not go in delay slots. */
2095 /* If this already has filled delay slots, get the insn needing
2096 the delay slots. */
2099 else
2102 /* Stop our search when seeing a jump. */
2106 /* See if we have a resource problem before we try to split. */
2115 {
2123 }
2128 /* Ensure we don't put insns between the setting of cc and the
2129 comparison by moving a setting of cc into an earlier delay
2130 slot since these insns could clobber the condition code. */
2133 /* If this is a call, we might not get here. */
2136 }
2138 /* If there are slots left to fill and our search was stopped by an
2139 unconditional branch, try the insn at the branch target. We can
2140 redirect the branch if it works.
2142 Don't do this if the insn at the branch target is a branch. */
2144 && trial
2158 {
2159 /* See comment in relax_delay_slots about necessity of using
2160 next_real_nondebug_insn here. */
2165 else
2169 {
2172 slots_filled++;
2174 new_label);
2175 }
2176 }
2177 }
2179 /* If this is an unconditional jump, then try to get insns from the
2180 target of the jump. */
2199 }
2200 }
2201 \f
2202 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2203 return the ultimate label reached by any such chain of jumps.
2204 Return a suitable return rtx if the chain ultimately leads to a
2205 return instruction.
2206 If LABEL is not followed by a jump, return LABEL.
2207 If the chain loops or we can't find end, return LABEL,
2208 since that tells caller to avoid changing the insn.
2209 If the returned label is obtained by following a crossing jump,
2210 set *CROSSING to true, otherwise set it to false. */
2212 static rtx
2214 {
2234 depth++)
2235 {
2238 /* If we have found a cycle, make the insn jump to itself. */
2242 /* Cannot follow returns and cannot look through tablejumps. */
2256 }
2260 }
2262 /* Try to find insns to place in delay slots.
2264 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2265 or is an unconditional branch if CONDITION is const_true_rtx.
2266 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2268 THREAD is a flow-of-control, either the insns to be executed if the
2269 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2271 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2272 to see if any potential delay slot insns set things needed there.
2274 LIKELY is true if it is extremely likely that the branch will be
2275 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2276 end of a loop back up to the top.
2278 OWN_THREAD is true if we are the only user of the thread, i.e. it is
2279 the target of the jump when we are the only jump going there.
2281 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2282 case, we can only take insns from the head of the thread for our delay
2283 slot. We then adjust the jump to point after the insns we have taken. */
2285 static void
2290 {
2291 rtx new_thread;
2298 /* Validate our arguments. */
2304 /* If our thread is the end of subroutine, we can't get any delay
2305 insns from that. */
2311 /* If this is an unconditional branch, nothing is needed at the
2312 opposite thread. Otherwise, compute what is needed there. */
2315 else
2318 /* If the insn at THREAD can be split, do it here to avoid having to
2319 update THREAD and NEW_THREAD if it is done in the loop below. Also
2320 initialize NEW_THREAD. */
2324 /* Scan insns at THREAD. We are looking for an insn that can be removed
2325 from THREAD (it neither sets nor references resources that were set
2326 ahead of it and it doesn't set anything needs by the insns ahead of
2327 it) and that either can be placed in an annulling insn or aren't
2328 needed at OPPOSITE_THREAD. */
2333 /* Handle the flags register specially, to be able to accept a
2334 candidate that clobbers it. See also fill_simple_delay_slots. */
2335 bool filter_flags
2342 {
2346 }
2348 /* If we do not own this thread, we must stop as soon as we find
2349 something that we can't put in a delay slot, since all we can do
2350 is branch into THREAD at a later point. Therefore, labels stop
2351 the search if this is not the `true' thread. */
2356 {
2359 /* If we have passed a label, we no longer own this thread. */
2361 {
2364 }
2373 /* If TRIAL conflicts with the insns ahead of it, we lose. */
2377 /* If we're handling sets to the flags register specially, we
2378 only allow an insn into a delay-slot, if it either:
2379 - doesn't set the flags register,
2380 - the "set" of the flags register isn't used (clobbered),
2381 - insns between the delay-slot insn and the trial-insn
2382 as accounted in "set", have not affected the flags register. */
2383 && (! filter_flags
2388 {
2391 /* If TRIAL is redundant with some insn before INSN, we don't
2392 actually need to add it to the delay list; we can merely pretend
2393 we did. */
2395 {
2398 {
2401 {
2405 }
2408 }
2409 else
2410 {
2413 }
2416 }
2418 /* There are two ways we can win: If TRIAL doesn't set anything
2419 needed at the opposite thread and can't trap, or if it can
2420 go into an annulled delay slot. But we want neither to copy
2421 nor to speculate frame-related insns. */
2428 {
2438 }
2442 {
2455 {
2459 winner:
2461 /* If we own this thread, delete the insn. If this is the
2462 destination of a branch, show that a basic block status
2463 may have been updated. In any case, mark the new
2464 starting point of this thread. */
2466 {
2467 rtx note;
2471 {
2475 }
2477 /* We are moving this insn, not deleting it. We must
2478 temporarily increment the use count on any referenced
2479 label lest it be deleted by delete_related_insns. */
2485 {
2486 /* REG_LABEL_OPERAND could be
2487 NOTE_INSN_DELETED_LABEL too. */
2490 else
2493 }
2504 {
2505 /* REG_LABEL_OPERAND could be
2506 NOTE_INSN_DELETED_LABEL too. */
2509 else
2512 }
2515 }
2516 else
2526 {
2527 /* Even though we have filled all the slots, we
2528 may be branching to a location that has a
2529 redundant insn. Skip any if so. */
2536 && (prior_insn
2539 {
2540 /* We know we do not own the thread, so no need
2541 to call update_block and delete_insn. */
2544 new_thread
2546 }
2548 }
2551 }
2552 }
2553 }
2555 /* This insn can't go into a delay slot. */
2560 {
2563 /* Groups of flags-register setters with users should not
2564 affect opportunities to move flags-register-setting insns
2565 (clobbers) into the delay-slot. */
2568 }
2570 /* Ensure we don't put insns between the setting of cc and the comparison
2571 by moving a setting of cc into an earlier delay slot since these insns
2572 could clobber the condition code. */
2575 /* If this insn is a register-register copy and the next insn has
2576 a use of our destination, change it to use our source. That way,
2577 it will become a candidate for our delay slot the next time
2578 through this loop. This case occurs commonly in loops that
2579 scan a list.
2581 We could check for more complex cases than those tested below,
2582 but it doesn't seem worth it. It might also be a good idea to try
2583 to swap the two insns. That might do better.
2585 We can't do this if the next insn modifies our destination, because
2586 that would make the replacement into the insn invalid. We also can't
2587 do this if it modifies our source, because it might be an earlyclobber
2588 operand. This latter test also prevents updating the contents of
2589 a PRE_INC. We also can't do this if there's overlap of source and
2590 destination. Overlap may happen for larger-than-register-size modes. */
2596 {
2606 }
2607 }
2609 /* If we stopped on a branch insn that has delay slots, see if we can
2610 steal some of the insns in those slots. */
2614 {
2616 /* If this is the `true' thread, we will want to follow the jump,
2617 so we can only do this if we have taken everything up to here. */
2619 {
2625 /* If we owned the thread and are told that it branched
2626 elsewhere, make sure we own the thread at the new location. */
2629 }
2635 }
2637 /* If we haven't found anything for this delay slot and it is very
2638 likely that the branch will be taken, see if the insn at our target
2639 increments or decrements a register with an increment that does not
2640 depend on the destination register. If so, try to place the opposite
2641 arithmetic insn after the jump insn and put the arithmetic insn in the
2642 delay slot. If we can't do this, return. */
2649 {
2650 rtx dest;
2651 rtx src;
2653 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2654 above. */
2671 {
2673 rtx new_arith;
2676 /* If this is a constant adjustment, use the same code with
2677 the negated constant. Otherwise, reverse the sense of the
2678 arithmetic. */
2682 else
2691 {
2694 }
2697 {
2700 {
2704 }
2706 }
2707 else
2716 }
2717 }
2722 /* If we are to branch into the middle of this thread, find an appropriate
2723 label or make a new one if none, and redirect INSN to it. If we hit the
2724 end of the function, use the end-of-function label. */
2726 {
2727 rtx label;
2743 else
2748 {
2752 }
2753 }
2754 }
2755 \f
2756 /* Make another attempt to find insns to place in delay slots.
2758 We previously looked for insns located in front of the delay insn
2759 and, for non-jump delay insns, located behind the delay insn.
2761 Here only try to schedule jump insns and try to move insns from either
2762 the target or the following insns into the delay slot. If annulling is
2763 supported, we will be likely to do this. Otherwise, we can do this only
2764 if safe. */
2766 static void
2768 {
2774 {
2775 rtx condition;
2792 /* Some machine description have defined instructions to have
2793 delay slots only in certain circumstances which may depend on
2794 nearby insns (which change due to reorg's actions).
2796 For example, the PA port normally has delay slots for unconditional
2797 jumps.
2799 However, the PA port claims such jumps do not have a delay slot
2800 if they are immediate successors of certain CALL_INSNs. This
2801 allows the port to favor filling the delay slot of the call with
2802 the unconditional jump. */
2813 /* Get the next active fallthrough and target insns and see if we own
2814 them. Then see whether the branch is likely true. We don't need
2815 to do a lot of this for unconditional branches. */
2821 {
2825 }
2826 else
2827 {
2832 }
2834 /* If this insn is expected to branch, first try to get insns from our
2835 target, then our fallthrough insns. If it is not expected to branch,
2836 try the other order. */
2839 {
2846 {
2847 /* Even though we didn't find anything for delay slots,
2848 we might have found a redundant insn which we deleted
2849 from the thread that was filled. So we have to recompute
2850 the next insn at the target. */
2858 }
2859 }
2860 else
2861 {
2873 }
2883 }
2884 }
2885 \f
2888 /* Recursively delete prior insns that compute the value (used only by INSN
2889 which the caller is deleting) stored in the register mentioned by NOTE
2890 which is a REG_DEAD note associated with INSN. */
2892 static void
2894 {
2902 {
2905 /* If we reach a CALL which is not calling a const function
2906 or the callee pops the arguments, then give up. */
2912 /* If we reach a SEQUENCE, it is too complex to try to
2913 do anything with it, so give up. We can be run during
2914 and after reorg, so SEQUENCE rtl can legitimately show
2915 up here. */
2921 /* reorg creates USEs that look like this. We leave them
2922 alone because reorg needs them for its own purposes. */
2926 {
2931 {
2932 /* If we find a SET of something else, we can't
2933 delete the insn. */
2938 {
2944 }
2948 }
2951 {
2961 /* We may have a multi-word hard register and some, but not
2962 all, of the words of the register are needed in subsequent
2963 insns. Write REG_UNUSED notes for those parts that were not
2964 needed. */
2967 {
2978 }
2979 }
2982 }
2984 /* If PAT references the register that dies here, it is an
2985 additional use. Hence any prior SET isn't dead. However, this
2986 insn becomes the new place for the REG_DEAD note. */
2988 {
2992 }
2993 }
2994 }
2996 /* Delete INSN and recursively delete insns that compute values used only
2997 by INSN. This uses the REG_DEAD notes computed during flow analysis.
2999 Look at all our REG_DEAD notes. If a previous insn does nothing other
3000 than set a register that dies in this insn, we can delete that insn
3001 as well. */
3003 static void
3005 {
3009 {
3013 /* Verify that the REG_NOTE is legitimate. */
3018 }
3021 }
3023 /* If all INSN does is set the pc, delete it,
3024 and delete the insn that set the condition codes for it
3025 if that's what the previous thing was. */
3027 static void
3029 {
3034 }
3038 {
3041 {
3047 }
3049 }
3051 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3052 BEG and END. */
3054 static bool
3056 {
3062 }
3064 \f
3065 /* Once we have tried two ways to fill a delay slot, make a pass over the
3066 code to try to improve the results and to do such things as more jump
3067 threading. */
3069 static void
3071 {
3075 rtx target_label;
3077 /* Look at every JUMP_INSN and see if we can improve it. */
3079 {
3085 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3086 the next insn, or jumps to a label that is not the last of a
3087 group of consecutive labels. */
3091 {
3093 target_label
3103 {
3107 /* If the insn jumps over a BARRIER and is the only way to reach
3108 its target, then we need to delete the BARRIER before the jump
3109 because, otherwise, the target may end up being considered as
3110 unreachable and thus also deleted. */
3112 {
3115 /* We have just removed a BARRIER, which means that the block
3116 number of the next insns has effectively been changed (see
3117 find_basic_block in resource.cc), so clear it. */
3119 }
3123 }
3126 {
3130 }
3132 /* See if this jump conditionally branches around an unconditional
3133 jump. If so, invert this jump and point it to the target of the
3134 second jump. Check if it's possible on the target. */
3137 && target_label
3142 {
3145 /* Be careful how we do this to avoid deleting code or
3146 labels that are momentarily dead. See similar optimization
3147 in jump.cc.
3149 We also need to ensure we properly handle the case when
3150 invert_jump fails. */
3157 {
3160 /* We have just removed a BARRIER, which means that the block
3161 number of the next insns has effectively been changed (see
3162 find_basic_block in resource.cc), so clear it. */
3167 }
3176 }
3177 }
3179 /* If this is an unconditional jump and the previous insn is a
3180 conditional jump, try reversing the condition of the previous
3181 insn and swapping our targets. The next pass might be able to
3182 fill the slots.
3184 Don't do this if we expect the conditional branch to be true, because
3185 we would then be making the more common case longer. */
3192 {
3198 }
3200 /* Now look only at cases where we have a filled delay slot. */
3207 /* See if the first insn in the delay slot is redundant with some
3208 previous insn. Remove it from the delay slot if so; then set up
3209 to reprocess this insn. */
3211 {
3217 }
3219 /* See if we have a RETURN insn with a filled delay slot followed
3220 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3221 the first RETURN (but not its delay insn). This gives the same
3222 effect in fewer instructions.
3224 Only do so if optimizing for size since this results in slower, but
3225 smaller code. */
3228 && next
3231 {
3235 /* Delete the RETURN and just execute the delay list insns.
3237 We do this by deleting the INSN containing the SEQUENCE, then
3238 re-emitting the insns separately, and then deleting the RETURN.
3239 This allows the count of the jump target to be properly
3240 decremented.
3242 Note that we need to change the INSN_UID of the re-emitted insns
3243 since it is used to hash the insns for mark_target_live_regs and
3244 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3246 Clear the from target bit, since these insns are no longer
3247 in delay slots. */
3260 }
3262 /* Now look only at the cases where we have a filled JUMP_INSN. */
3273 /* If this jump goes to another unconditional jump, thread it, but
3274 don't convert a jump into a RETURN here. */
3276 delay_jump_insn,
3283 {
3288 }
3290 /* If the first insn at TARGET_LABEL is redundant with a previous
3291 insn, redirect the jump to the following insn and process again.
3292 We use next_real_nondebug_insn instead of next_active_insn so we
3293 don't skip USE-markers, or we'll end up with incorrect
3294 liveness info. */
3299 {
3300 /* Figure out where to emit the special USE insn so we don't
3301 later incorrectly compute register live/death info. */
3307 {
3308 /* Insert the special USE insn and update dataflow info.
3309 We know "trial" is an insn here as it is the output of
3310 next_real_nondebug_insn () above. */
3313 /* Now emit a label before the special USE insn, and
3314 redirect our jump to the new label. */
3319 }
3320 }
3322 /* Similarly, if it is an unconditional jump with one insn in its
3323 delay list and that insn is redundant, thread the jump. */
3331 {
3339 {
3344 }
3345 }
3347 /* See if we have a simple (conditional) jump that is useless. */
3353 {
3357 /* All this insn does is execute its delay list and jump to the
3358 following insn. So delete the jump and just execute the delay
3359 list insns.
3361 We do this by deleting the INSN containing the SEQUENCE, then
3362 re-emitting the insns separately, and then deleting the jump.
3363 This allows the count of the jump target to be properly
3364 decremented.
3366 Note that we need to change the INSN_UID of the re-emitted insns
3367 since it is used to hash the insns for mark_target_live_regs and
3368 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3370 Clear the from target bit, since these insns are no longer
3371 in delay slots. */
3384 }
3386 /* See if this is an unconditional jump around a single insn which is
3387 identical to the one in its delay slot. In this case, we can just
3388 delete the branch and the insn in its delay slot. */
3394 {
3397 }
3399 /* See if this jump (with its delay slots) conditionally branches
3400 around an unconditional jump (without delay slots). If so, invert
3401 this jump and point it to the target of the second jump. We cannot
3402 do this for annulled jumps, though. Again, don't convert a jump to
3403 a RETURN here. */
3410 {
3417 /* find_end_label can generate a new label. Check this first. */
3422 {
3423 /* Be careful how we do this to avoid deleting code or labels
3424 that are momentarily dead. See similar optimization in
3425 jump.cc */
3430 {
3431 /* Must update the INSN_FROM_TARGET_P bits now that
3432 the branch is reversed, so that mark_target_live_regs
3433 will handle the delay slot insn correctly. */
3435 {
3438 }
3440 /* We have just removed a BARRIER, which means that the block
3441 number of the next insns has effectively been changed (see
3442 find_basic_block in resource.cc), so clear it. */
3448 }
3453 }
3454 }
3456 /* If we own the thread opposite the way this insn branches, see if we
3457 can merge its delay slots with following insns. */
3466 /* If we get here, we haven't deleted INSN. But we may have deleted
3467 NEXT, so recompute it. */
3469 }
3470 }
3471 \f
3473 /* Look for filled jumps to the end of function label. We can try to convert
3474 them into RETURN insns if the insns in the delay slot are valid for the
3475 RETURN as well. */
3477 static void
3479 {
3486 /* See if there is a RETURN insn in the function other than the one we
3487 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3488 into a RETURN to jump to it. */
3491 {
3495 else
3498 }
3500 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3501 was equal to END_OF_FUNCTION_LABEL. */
3507 /* Clear the list of insns to fill so we can use it. */
3511 {
3515 /* Only look at filled JUMP_INSNs that go to the end of function
3516 label. */
3529 {
3532 }
3534 {
3537 }
3538 else
3543 /* If we can't make the jump into a RETURN, try to redirect it to the best
3544 RETURN and go on to the next insn. */
3546 {
3547 /* Make sure redirecting the jump will not invalidate the delay
3548 slot insns. */
3552 }
3554 /* See if this RETURN can accept the insns current in its delay slot.
3555 It can if it has more or an equal number of slots and the contents
3556 of each is valid. */
3561 {
3564 #if ANNUL_IFFALSE_SLOTS
3569 #endif
3570 #if ANNUL_IFTRUE_SLOTS
3575 #endif
3579 }
3580 else
3586 /* We have to do something with this insn. If it is an unconditional
3587 RETURN, delete the SEQUENCE and output the individual insns,
3588 followed by the RETURN. Then set things up so we try to find
3589 insns for its delay slots, if it needs some. */
3591 {
3603 }
3604 else
3605 /* It is probably more efficient to keep this with its current
3606 delay slot as a branch to a RETURN. */
3608 }
3610 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3611 new delay slots we have created. */
3620 }
3621 \f
3622 /* Try to find insns to place in delay slots. */
3624 static void
3626 {
3631 /* If the current function has no insns other than the prologue and
3632 epilogue, then do not try to fill any delay slots. */
3636 /* Find the highest INSN_UID and allocate and initialize our map from
3637 INSN_UID's to position in code. */
3639 {
3645 }
3651 /* Initialize the list of insns that need filling. */
3653 {
3656 }
3659 {
3660 rtx target;
3662 /* Skip vector tables. We can't get attributes for them. */
3673 /* Ensure all jumps go to the last of a set of consecutive labels. */
3680 }
3684 /* Show we haven't computed an end-of-function label yet. */
3687 /* Initialize the statistics for this function. */
3691 /* Now do the delay slot filling. Try everything twice in case earlier
3692 changes make more slots fillable. */
3696 reorg_pass_number++)
3697 {
3703 }
3705 /* If we made an end of function label, indicate that it is now
3706 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3707 If it is now unused, delete it. */
3721 /* Delete any USE insns made by update_block; subsequent passes don't need
3722 them or know how to deal with them. */
3724 {
3730 }
3734 /* It is not clear why the line below is needed, but it does seem to be. */
3738 {
3745 reorg_pass_number++)
3746 {
3749 {
3758 {
3764 }
3766 }
3767 }
3771 {
3776 {
3778 {
3779 rtx control;
3786 else
3788 }
3791 }
3792 }
3796 {
3798 {
3803 }
3804 }
3808 {
3812 {
3814 {
3819 }
3820 }
3822 }
3825 }
3828 {
3831 }
3836 }
3837 \f
3838 /* Run delay slot optimization. */
3839 static void
3841 {
3844 }
3849 {
3859 };
3862 {
3866 {}
3868 /* opt_pass methods: */
3871 {
3874 }
3878 bool
3880 {
3881 /* At -O0 dataflow info isn't updated after RA. */
3886 }
3890 rtl_opt_pass *
3892 {
3894 }
3896 /* Machine dependent reorg pass. */
3901 {
3911 };
3914 {
3918 {}
3920 /* opt_pass methods: */
3922 {
3924 }
3927 {
3930 }
3936 rtl_opt_pass *
3938 {
3940 }